rt_sysc_m32       234 arch/mips/pci/pci-mt7620.c 	rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
rt_sysc_m32       235 arch/mips/pci/pci-mt7620.c 	rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
rt_sysc_m32       239 arch/mips/pci/pci-mt7620.c 	rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
rt_sysc_m32       245 arch/mips/pci/pci-mt7620.c 		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
rt_sysc_m32       250 arch/mips/pci/pci-mt7620.c 	rt_sysc_m32(LC_CKDRVHZ | LC_CKDRVOHZ, LC_CKDRVPD | PDRV_SW_SET,
rt_sysc_m32       261 arch/mips/pci/pci-mt7620.c 	rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
rt_sysc_m32       265 arch/mips/pci/pci-mt7620.c 	rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
rt_sysc_m32       333 arch/mips/pci/pci-mt7620.c 		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
rt_sysc_m32       335 arch/mips/pci/pci-mt7620.c 			rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
rt_sysc_m32        88 arch/mips/ralink/reset.c 		rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL);
rt_sysc_m32       229 drivers/staging/mt7621-pci/pci-mt7621.c 	rt_sysc_m32(PCIE_PORT_CLK_EN(port->slot), 0, RALINK_CLKCFG1);
rt_sysc_m32       460 drivers/staging/mt7621-pci/pci-mt7621.c 	rt_sysc_m32(PERST_MODE_MASK, PERST_MODE_GPIO, MT7621_GPIO_MODE);
rt_sysc_m32       495 drivers/staging/mt7621-pci/pci-mt7621.c 	rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
rt_sysc_m32       496 drivers/staging/mt7621-pci/pci-mt7621.c 	rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN);
rt_sysc_m32       497 drivers/staging/mt7621-pci/pci-mt7621.c 	rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1);
rt_sysc_m32       498 drivers/staging/mt7621-pci/pci-mt7621.c 	rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN);