rst_boot           43 arch/mips/cavium-octeon/csrc-octeon.c 		union cvmx_mio_rst_boot rst_boot;
rst_boot           45 arch/mips/cavium-octeon/csrc-octeon.c 		rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
rst_boot           46 arch/mips/cavium-octeon/csrc-octeon.c 		rdiv = rst_boot.s.c_mul;	/* CPU clock */
rst_boot           47 arch/mips/cavium-octeon/csrc-octeon.c 		sdiv = rst_boot.s.pnr_mul;	/* I/O clock */
rst_boot           50 arch/mips/cavium-octeon/csrc-octeon.c 		union cvmx_rst_boot rst_boot;
rst_boot           52 arch/mips/cavium-octeon/csrc-octeon.c 		rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);
rst_boot           53 arch/mips/cavium-octeon/csrc-octeon.c 		rdiv = rst_boot.s.c_mul;	/* CPU clock */
rst_boot           54 arch/mips/cavium-octeon/csrc-octeon.c 		sdiv = rst_boot.s.pnr_mul;	/* I/O clock */
rst_boot          720 arch/mips/cavium-octeon/setup.c 		union cvmx_mio_rst_boot rst_boot;
rst_boot          721 arch/mips/cavium-octeon/setup.c 		rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
rst_boot          722 arch/mips/cavium-octeon/setup.c 		octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
rst_boot          725 arch/mips/cavium-octeon/setup.c 		union cvmx_rst_boot rst_boot;
rst_boot          726 arch/mips/cavium-octeon/setup.c 		rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);
rst_boot          727 arch/mips/cavium-octeon/setup.c 		octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
rst_boot          610 drivers/crypto/cavium/nitrox/nitrox_hal.c 	union rst_boot rst_boot;
rst_boot          618 drivers/crypto/cavium/nitrox/nitrox_hal.c 	rst_boot.value = nitrox_read_csr(ndev, offset);
rst_boot          619 drivers/crypto/cavium/nitrox/nitrox_hal.c 	ndev->hw.freq = (rst_boot.pnr_mul + 3) * PLL_REF_CLK;