rreg_t 718 drivers/atm/iphase.h rreg_t mode_reg_0; /* Mode register 0 */ rreg_t 719 drivers/atm/iphase.h rreg_t protocol_id; /* Protocol ID */ rreg_t 720 drivers/atm/iphase.h rreg_t mask_reg; /* Mask Register */ rreg_t 721 drivers/atm/iphase.h rreg_t intr_status_reg;/* Interrupt status register */ rreg_t 722 drivers/atm/iphase.h rreg_t drp_pkt_cntr; /* Dropped packet cntr (clear on read) */ rreg_t 723 drivers/atm/iphase.h rreg_t err_cntr; /* Error Counter (cleared on read) */ rreg_t 725 drivers/atm/iphase.h rreg_t raw_base_adr; /* Base addr for raw cell Q */ rreg_t 727 drivers/atm/iphase.h rreg_t cell_ctr0; /* Cell Counter 0 (cleared when read) */ rreg_t 728 drivers/atm/iphase.h rreg_t cell_ctr1; /* Cell Counter 1 (cleared when read) */ rreg_t 730 drivers/atm/iphase.h rreg_t cmd_reg; /* Command register */ rreg_t 731 drivers/atm/iphase.h rreg_t desc_base; /* Base address for description table */ rreg_t 732 drivers/atm/iphase.h rreg_t vc_lkup_base; /* Base address for VC lookup table */ rreg_t 733 drivers/atm/iphase.h rreg_t reass_base; /* Base address for reassembler table */ rreg_t 734 drivers/atm/iphase.h rreg_t queue_base; /* Base address for Communication queue */ rreg_t 736 drivers/atm/iphase.h rreg_t pkt_tm_cnt; /* Packet Timeout and count register */ rreg_t 737 drivers/atm/iphase.h rreg_t tmout_range; /* Range of reassembley IDs for timeout */ rreg_t 738 drivers/atm/iphase.h rreg_t intrvl_cntr; /* Packet aging interval counter */ rreg_t 739 drivers/atm/iphase.h rreg_t tmout_indx; /* index of pkt being tested for aging */ rreg_t 741 drivers/atm/iphase.h rreg_t vp_lkup_base; /* Base address for VP lookup table */ rreg_t 742 drivers/atm/iphase.h rreg_t vp_filter; /* VP filter register */ rreg_t 743 drivers/atm/iphase.h rreg_t abr_lkup_base; /* Base address of ABR VC Table */ rreg_t 745 drivers/atm/iphase.h rreg_t fdq_st_adr; /* Free desc queue start address */ rreg_t 746 drivers/atm/iphase.h rreg_t fdq_ed_adr; /* Free desc queue end address */ rreg_t 747 drivers/atm/iphase.h rreg_t fdq_rd_ptr; /* Free desc queue read pointer */ rreg_t 748 drivers/atm/iphase.h rreg_t fdq_wr_ptr; /* Free desc queue write pointer */ rreg_t 749 drivers/atm/iphase.h rreg_t pcq_st_adr; /* Packet Complete queue start address */ rreg_t 750 drivers/atm/iphase.h rreg_t pcq_ed_adr; /* Packet Complete queue end address */ rreg_t 751 drivers/atm/iphase.h rreg_t pcq_rd_ptr; /* Packet Complete queue read pointer */ rreg_t 752 drivers/atm/iphase.h rreg_t pcq_wr_ptr; /* Packet Complete queue write pointer */ rreg_t 753 drivers/atm/iphase.h rreg_t excp_st_adr; /* Exception queue start address */ rreg_t 754 drivers/atm/iphase.h rreg_t excp_ed_adr; /* Exception queue end address */ rreg_t 755 drivers/atm/iphase.h rreg_t excp_rd_ptr; /* Exception queue read pointer */ rreg_t 756 drivers/atm/iphase.h rreg_t excp_wr_ptr; /* Exception queue write pointer */ rreg_t 758 drivers/atm/iphase.h rreg_t raw_st_adr; /* Raw Cell start address */ rreg_t 759 drivers/atm/iphase.h rreg_t raw_ed_adr; /* Raw Cell end address */ rreg_t 760 drivers/atm/iphase.h rreg_t raw_rd_ptr; /* Raw Cell read pointer */ rreg_t 761 drivers/atm/iphase.h rreg_t raw_wr_ptr; /* Raw Cell write pointer */ rreg_t 762 drivers/atm/iphase.h rreg_t state_reg; /* State Register */ rreg_t 764 drivers/atm/iphase.h rreg_t buf_size; /* Buffer size */ rreg_t 766 drivers/atm/iphase.h rreg_t xtra_rm_offset; /* Offset of the additional turnaround RM */ rreg_t 768 drivers/atm/iphase.h rreg_t drp_pkt_cntr_nc;/* Dropped Packet cntr, Not clear on rd */ rreg_t 769 drivers/atm/iphase.h rreg_t err_cntr_nc; /* Error Counter, Not clear on read */ rreg_t 771 drivers/atm/iphase.h rreg_t cell_ctr0_nc; /* Cell Counter 0, Not clear on read */ rreg_t 772 drivers/atm/iphase.h rreg_t cell_ctr1_nc; /* Cell Counter 1, Not clear on read */