riscv_pmu          35 arch/riscv/kernel/perf_event.c static const struct riscv_pmu *riscv_pmu __read_mostly;
riscv_pmu         144 arch/riscv/kernel/perf_event.c 	if (config >= riscv_pmu->max_events)
riscv_pmu         147 arch/riscv/kernel/perf_event.c 	return riscv_pmu->hw_events[config];
riscv_pmu         163 arch/riscv/kernel/perf_event.c 	if (!riscv_pmu->cache_events || err)
riscv_pmu         171 arch/riscv/kernel/perf_event.c 	code = (*riscv_pmu->cache_events)[type][op][result];
riscv_pmu         234 arch/riscv/kernel/perf_event.c 		((1ULL << riscv_pmu->counter_width) - 1);
riscv_pmu         259 arch/riscv/kernel/perf_event.c 		riscv_pmu->pmu->read(event);
riscv_pmu         302 arch/riscv/kernel/perf_event.c 	if (cpuc->n_events == riscv_pmu->num_counters)
riscv_pmu         320 arch/riscv/kernel/perf_event.c 		riscv_pmu->pmu->start(event, PERF_EF_RELOAD);
riscv_pmu         335 arch/riscv/kernel/perf_event.c 	riscv_pmu->pmu->stop(event, PERF_EF_UPDATE);
riscv_pmu         355 arch/riscv/kernel/perf_event.c 	if (riscv_pmu->irq >= 0 && riscv_pmu->handle_irq) {
riscv_pmu         356 arch/riscv/kernel/perf_event.c 		err = request_irq(riscv_pmu->irq, riscv_pmu->handle_irq,
riscv_pmu         367 arch/riscv/kernel/perf_event.c 	if (riscv_pmu->irq >= 0)
riscv_pmu         368 arch/riscv/kernel/perf_event.c 		free_irq(riscv_pmu->irq, NULL);
riscv_pmu         403 arch/riscv/kernel/perf_event.c 		code = riscv_pmu->map_hw_event(attr->config);
riscv_pmu         406 arch/riscv/kernel/perf_event.c 		code = riscv_pmu->map_cache_event(attr->config);
riscv_pmu         447 arch/riscv/kernel/perf_event.c static const struct riscv_pmu riscv_base_pmu = {
riscv_pmu         472 arch/riscv/kernel/perf_event.c 	riscv_pmu = &riscv_base_pmu;
riscv_pmu         478 arch/riscv/kernel/perf_event.c 			riscv_pmu = of_id->data;
riscv_pmu         482 arch/riscv/kernel/perf_event.c 	perf_pmu_register(riscv_pmu->pmu, "cpu", PERF_TYPE_RAW);