reset_val         394 arch/arm/kvm/coproc.c 			NULL, reset_val, c1_CPACR, 0x00000000 },
reset_val         403 arch/arm/kvm/coproc.c 			access_vm_reg, reset_val, c2_TTBCR, 0x00000000 },
reset_val         477 arch/arm/kvm/coproc.c 			NULL, reset_val, c12_VBAR, 0x00000000 },
reset_val         488 arch/arm/kvm/coproc.c 			access_vm_reg, reset_val, c13_CID, 0x00000000 },
reset_val         501 arch/arm/kvm/coproc.c 			NULL, reset_val, c14_CNTKCTL, 0x00000000 },
reset_val          25 arch/arm/kvm/coproc_a15.c 			access_vm_reg, reset_val, c1_SCTLR, 0x00C50078 },
reset_val          28 arch/arm/kvm/coproc_a7.c 			access_vm_reg, reset_val, c1_SCTLR, 0x00C50878 },
reset_val        1374 arch/arm64/kvm/sys_regs.c 	{ SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
reset_val        1375 arch/arm64/kvm/sys_regs.c 	{ SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
reset_val        1405 arch/arm64/kvm/sys_regs.c 	{ SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
reset_val        1486 arch/arm64/kvm/sys_regs.c 	{ SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
reset_val        1487 arch/arm64/kvm/sys_regs.c 	{ SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
reset_val        1488 arch/arm64/kvm/sys_regs.c 	{ SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
reset_val        1491 arch/arm64/kvm/sys_regs.c 	{ SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
reset_val        1527 arch/arm64/kvm/sys_regs.c 	{ SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
reset_val        1528 arch/arm64/kvm/sys_regs.c 	{ SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
reset_val        1543 arch/arm64/kvm/sys_regs.c 	{ SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
reset_val        1546 arch/arm64/kvm/sys_regs.c 	{ SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
reset_val        1568 arch/arm64/kvm/sys_regs.c 	{ SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
reset_val        1646 arch/arm64/kvm/sys_regs.c 	{ SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
reset_val        1650 arch/arm64/kvm/sys_regs.c 	{ SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
reset_val         530 drivers/gpu/drm/exynos/exynos_drm_dsi.c 	u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
reset_val         533 drivers/gpu/drm/exynos/exynos_drm_dsi.c 	exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val);
reset_val        1049 drivers/infiniband/hw/efa/efa_com.c 	u32 stat, timeout, cap, reset_val;
reset_val        1069 drivers/infiniband/hw/efa/efa_com.c 	reset_val = EFA_REGS_DEV_CTL_DEV_RESET_MASK;
reset_val        1070 drivers/infiniband/hw/efa/efa_com.c 	reset_val |= (reset_reason << EFA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
reset_val        1072 drivers/infiniband/hw/efa/efa_com.c 	writel(reset_val, edev->reg_bar + EFA_REGS_DEV_CTL_OFF);
reset_val        2073 drivers/net/ethernet/amazon/ena/ena_com.c 	u32 stat, timeout, cap, reset_val;
reset_val        2098 drivers/net/ethernet/amazon/ena/ena_com.c 	reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
reset_val        2099 drivers/net/ethernet/amazon/ena/ena_com.c 	reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
reset_val        2101 drivers/net/ethernet/amazon/ena/ena_com.c 	writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
reset_val         472 drivers/net/ethernet/amd/lance.c 	int i, reset_val, lance_version;
reset_val         504 drivers/net/ethernet/amd/lance.c 	reset_val = inw(ioaddr+LANCE_RESET); /* Reset the LANCE */
reset_val         509 drivers/net/ethernet/amd/lance.c 		outw(reset_val, ioaddr+LANCE_RESET);
reset_val         599 drivers/net/ethernet/amd/lance.c 		short reset_val = inw(ioaddr+LANCE_RESET);
reset_val         600 drivers/net/ethernet/amd/lance.c 		dev->dma = dma_tbl[(reset_val >> 2) & 3];
reset_val         601 drivers/net/ethernet/amd/lance.c 		dev->irq = irq_tbl[(reset_val >> 4) & 7];
reset_val         913 drivers/net/ethernet/sun/niu.c 	u64 reset_val, val_rd;
reset_val         920 drivers/net/ethernet/sun/niu.c 		reset_val =  ENET_SERDES_RESET_0;
reset_val         926 drivers/net/ethernet/sun/niu.c 		reset_val =  ENET_SERDES_RESET_1;
reset_val         960 drivers/net/ethernet/sun/niu.c 	nw64(ENET_SERDES_RESET, reset_val);
reset_val         963 drivers/net/ethernet/sun/niu.c 	val_rd &= ~reset_val;
reset_val        1013 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c 	int i, reset_val;
reset_val        1020 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c 		reset_val = 0x1fffff;
reset_val        1022 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c 		reset_val = 0x7ffff;
reset_val        1082 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c 				reset_val);
reset_val        1084 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c 				reset_val);
reset_val        1087 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c 		if (reset_val != (val & reset_val)) {
reset_val        1094 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c 				reset_val);
reset_val        1096 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c 				reset_val);
reset_val        1100 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c 		if (val & reset_val) {
reset_val         481 include/linux/qed/qed_chain.h 		u32 reset_val = p_chain->page_cnt - 1;
reset_val         484 include/linux/qed/qed_chain.h 			p_chain->pbl.c.u16.prod_page_idx = (u16)reset_val;
reset_val         485 include/linux/qed/qed_chain.h 			p_chain->pbl.c.u16.cons_page_idx = (u16)reset_val;
reset_val         487 include/linux/qed/qed_chain.h 			p_chain->pbl.c.u32.prod_page_idx = reset_val;
reset_val         488 include/linux/qed/qed_chain.h 			p_chain->pbl.c.u32.cons_page_idx = reset_val;