regval 229 arch/arm/mach-omap1/clock.c u16 regval; regval 237 arch/arm/mach-omap1/clock.c regval = __raw_readw(DSP_CKCTL); regval 238 arch/arm/mach-omap1/clock.c regval &= ~(3 << clk->rate_offset); regval 239 arch/arm/mach-omap1/clock.c regval |= dsor_exp << clk->rate_offset; regval 240 arch/arm/mach-omap1/clock.c __raw_writew(regval, DSP_CKCTL); regval 259 arch/arm/mach-omap1/clock.c u16 regval; regval 267 arch/arm/mach-omap1/clock.c regval = omap_readw(ARM_CKCTL); regval 268 arch/arm/mach-omap1/clock.c regval &= ~(3 << clk->rate_offset); regval 269 arch/arm/mach-omap1/clock.c regval |= dsor_exp << clk->rate_offset; regval 270 arch/arm/mach-omap1/clock.c regval = verify_ckctl_value(regval); regval 271 arch/arm/mach-omap1/clock.c omap_writew(regval, ARM_CKCTL); regval 58 arch/arm/mach-omap2/omap_phy_internal.c u32 regval; regval 61 arch/arm/mach-omap2/omap_phy_internal.c regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); regval 63 arch/arm/mach-omap2/omap_phy_internal.c regval |= AM35XX_USBOTGSS_SW_RST; regval 64 arch/arm/mach-omap2/omap_phy_internal.c omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); regval 66 arch/arm/mach-omap2/omap_phy_internal.c regval &= ~AM35XX_USBOTGSS_SW_RST; regval 67 arch/arm/mach-omap2/omap_phy_internal.c omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); regval 69 arch/arm/mach-omap2/omap_phy_internal.c regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); regval 112 arch/arm/mach-omap2/omap_phy_internal.c u32 regval; regval 114 arch/arm/mach-omap2/omap_phy_internal.c regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); regval 115 arch/arm/mach-omap2/omap_phy_internal.c regval |= AM35XX_USBOTGSS_INT_CLR; regval 116 arch/arm/mach-omap2/omap_phy_internal.c omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); regval 117 arch/arm/mach-omap2/omap_phy_internal.c regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); regval 219 arch/arm64/kvm/sys_regs.c val = p->regval; regval 223 arch/arm64/kvm/sys_regs.c val = (p->regval << 32) | (u64)lower_32_bits(val); regval 226 arch/arm64/kvm/sys_regs.c lower_32_bits(p->regval); regval 280 arch/arm64/kvm/sys_regs.c vgic_v3_dispatch_sgi(vcpu, p->regval, g1); regval 292 arch/arm64/kvm/sys_regs.c p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; regval 338 arch/arm64/kvm/sys_regs.c p->regval = (1 << 3); regval 350 arch/arm64/kvm/sys_regs.c p->regval = read_sysreg(dbgauthstatus_el1); regval 387 arch/arm64/kvm/sys_regs.c vcpu_write_sys_reg(vcpu, p->regval, r->reg); regval 390 arch/arm64/kvm/sys_regs.c p->regval = vcpu_read_sys_reg(vcpu, r->reg); regval 393 arch/arm64/kvm/sys_regs.c trace_trap_reg(__func__, r->reg, p->is_write, p->regval); regval 411 arch/arm64/kvm/sys_regs.c u64 val = p->regval; regval 426 arch/arm64/kvm/sys_regs.c p->regval = *dbg_reg; regval 428 arch/arm64/kvm/sys_regs.c p->regval &= 0xffffffffUL; regval 686 arch/arm64/kvm/sys_regs.c val |= p->regval & ARMV8_PMU_PMCR_MASK; regval 696 arch/arm64/kvm/sys_regs.c p->regval = val; regval 712 arch/arm64/kvm/sys_regs.c __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; regval 715 arch/arm64/kvm/sys_regs.c p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) regval 739 arch/arm64/kvm/sys_regs.c p->regval = pmceid; regval 807 arch/arm64/kvm/sys_regs.c kvm_pmu_set_counter_value(vcpu, idx, p->regval); regval 809 arch/arm64/kvm/sys_regs.c p->regval = kvm_pmu_get_counter_value(vcpu, idx); regval 845 arch/arm64/kvm/sys_regs.c kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); regval 846 arch/arm64/kvm/sys_regs.c __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK; regval 849 arch/arm64/kvm/sys_regs.c p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; regval 868 arch/arm64/kvm/sys_regs.c val = p->regval & mask; regval 880 arch/arm64/kvm/sys_regs.c p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask; regval 900 arch/arm64/kvm/sys_regs.c u64 val = p->regval & mask; regval 909 arch/arm64/kvm/sys_regs.c p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask; regval 929 arch/arm64/kvm/sys_regs.c __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); regval 932 arch/arm64/kvm/sys_regs.c __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); regval 934 arch/arm64/kvm/sys_regs.c p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask; regval 955 arch/arm64/kvm/sys_regs.c kvm_pmu_software_increment(vcpu, p->regval & mask); regval 972 arch/arm64/kvm/sys_regs.c p->regval & ARMV8_PMU_USERENR_MASK; regval 974 arch/arm64/kvm/sys_regs.c p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) regval 1066 arch/arm64/kvm/sys_regs.c kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); regval 1068 arch/arm64/kvm/sys_regs.c p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); regval 1103 arch/arm64/kvm/sys_regs.c p->regval = read_id_reg(vcpu, r, raz); regval 1161 arch/arm64/kvm/sys_regs.c p->regval = guest_id_aa64zfr0_el1(vcpu); regval 1266 arch/arm64/kvm/sys_regs.c p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0); regval 1276 arch/arm64/kvm/sys_regs.c p->regval = read_sysreg(clidr_el1); regval 1290 arch/arm64/kvm/sys_regs.c vcpu_write_sys_reg(vcpu, p->regval, reg); regval 1292 arch/arm64/kvm/sys_regs.c p->regval = vcpu_read_sys_reg(vcpu, reg); regval 1305 arch/arm64/kvm/sys_regs.c p->regval = get_ccsidr(csselr); regval 1320 arch/arm64/kvm/sys_regs.c p->regval &= ~GENMASK(27, 3); regval 1664 arch/arm64/kvm/sys_regs.c p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | regval 1677 arch/arm64/kvm/sys_regs.c vcpu_cp14(vcpu, r->reg) = p->regval; regval 1680 arch/arm64/kvm/sys_regs.c p->regval = vcpu_cp14(vcpu, r->reg); regval 1707 arch/arm64/kvm/sys_regs.c val |= p->regval << 32; regval 1712 arch/arm64/kvm/sys_regs.c p->regval = *dbg_reg >> 32; regval 2144 arch/arm64/kvm/sys_regs.c params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; regval 2145 arch/arm64/kvm/sys_regs.c params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; regval 2159 arch/arm64/kvm/sys_regs.c vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); regval 2160 arch/arm64/kvm/sys_regs.c vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); regval 2188 arch/arm64/kvm/sys_regs.c params.regval = vcpu_get_reg(vcpu, Rt); regval 2198 arch/arm64/kvm/sys_regs.c vcpu_set_reg(vcpu, Rt, params.regval); regval 2303 arch/arm64/kvm/sys_regs.c params.regval = vcpu_get_reg(vcpu, Rt); regval 2309 arch/arm64/kvm/sys_regs.c vcpu_set_reg(vcpu, Rt, params.regval); regval 20 arch/arm64/kvm/sys_regs.h u64 regval; regval 81 arch/arm64/kvm/sys_regs.h p->regval = 0; regval 30 arch/arm64/kvm/sys_regs_generic_v8.c p->regval = vcpu_read_sys_reg(vcpu, ACTLR_EL1); regval 23 arch/arm64/kvm/vgic-sys-reg-v3.c val = p->regval; regval 81 arch/arm64/kvm/vgic-sys-reg-v3.c p->regval = val; regval 94 arch/arm64/kvm/vgic-sys-reg-v3.c vmcr.pmr = (p->regval & ICC_PMR_EL1_MASK) >> ICC_PMR_EL1_SHIFT; regval 97 arch/arm64/kvm/vgic-sys-reg-v3.c p->regval = (vmcr.pmr << ICC_PMR_EL1_SHIFT) & ICC_PMR_EL1_MASK; regval 110 arch/arm64/kvm/vgic-sys-reg-v3.c vmcr.bpr = (p->regval & ICC_BPR0_EL1_MASK) >> regval 114 arch/arm64/kvm/vgic-sys-reg-v3.c p->regval = (vmcr.bpr << ICC_BPR0_EL1_SHIFT) & regval 127 arch/arm64/kvm/vgic-sys-reg-v3.c p->regval = 0; regval 132 arch/arm64/kvm/vgic-sys-reg-v3.c vmcr.abpr = (p->regval & ICC_BPR1_EL1_MASK) >> regval 136 arch/arm64/kvm/vgic-sys-reg-v3.c p->regval = (vmcr.abpr << ICC_BPR1_EL1_SHIFT) & regval 141 arch/arm64/kvm/vgic-sys-reg-v3.c p->regval = min((vmcr.bpr + 1), 7U); regval 154 arch/arm64/kvm/vgic-sys-reg-v3.c vmcr.grpen0 = (p->regval & ICC_IGRPEN0_EL1_MASK) >> regval 158 arch/arm64/kvm/vgic-sys-reg-v3.c p->regval = (vmcr.grpen0 << ICC_IGRPEN0_EL1_SHIFT) & regval 172 arch/arm64/kvm/vgic-sys-reg-v3.c vmcr.grpen1 = (p->regval & ICC_IGRPEN1_EL1_MASK) >> regval 176 arch/arm64/kvm/vgic-sys-reg-v3.c p->regval = (vmcr.grpen1 << ICC_IGRPEN1_EL1_SHIFT) & regval 195 arch/arm64/kvm/vgic-sys-reg-v3.c *ap_reg = p->regval; regval 197 arch/arm64/kvm/vgic-sys-reg-v3.c p->regval = *ap_reg; regval 212 arch/arm64/kvm/vgic-sys-reg-v3.c p->regval = 0; regval 237 arch/arm64/kvm/vgic-sys-reg-v3.c if (!(p->regval & ICC_SRE_EL1_SRE)) regval 240 arch/arm64/kvm/vgic-sys-reg-v3.c p->regval = vgicv3->vgic_sre; regval 269 arch/arm64/kvm/vgic-sys-reg-v3.c params.regval = *reg; regval 289 arch/arm64/kvm/vgic-sys-reg-v3.c params.regval = *reg; regval 303 arch/arm64/kvm/vgic-sys-reg-v3.c *reg = params.regval; regval 100 arch/mips/loongson64/lemote-2f/clock.c int regval; regval 121 arch/mips/loongson64/lemote-2f/clock.c regval = LOONGSON_CHIPCFG(0); regval 122 arch/mips/loongson64/lemote-2f/clock.c regval = (regval & ~0x7) | (pos->driver_data - 1); regval 123 arch/mips/loongson64/lemote-2f/clock.c LOONGSON_CHIPCFG(0) = regval; regval 75 arch/riscv/mm/sifive_l2_cache.c u32 regval, val; regval 77 arch/riscv/mm/sifive_l2_cache.c regval = readl(l2_base + SIFIVE_L2_CONFIG); regval 78 arch/riscv/mm/sifive_l2_cache.c val = regval & 0xFF; regval 80 arch/riscv/mm/sifive_l2_cache.c val = (regval & 0xFF00) >> 8; regval 82 arch/riscv/mm/sifive_l2_cache.c val = (regval & 0xFF0000) >> 16; regval 84 arch/riscv/mm/sifive_l2_cache.c val = (regval & 0xFF000000) >> 24; regval 87 arch/riscv/mm/sifive_l2_cache.c regval = readl(l2_base + SIFIVE_L2_WAYENABLE); regval 88 arch/riscv/mm/sifive_l2_cache.c pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval); regval 150 arch/sparc/include/asm/pgtsrmmu.h void srmmu_set_mmureg(unsigned long regval); regval 106 arch/sparc/include/asm/turbosparc.h static inline void turbosparc_set_ccreg(unsigned long regval) regval 110 arch/sparc/include/asm/turbosparc.h : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS) regval 116 arch/sparc/include/asm/turbosparc.h unsigned long regval; regval 119 arch/sparc/include/asm/turbosparc.h : "=r" (regval) regval 121 arch/sparc/include/asm/turbosparc.h return regval; regval 146 arch/sparc/include/asm/viking.h static inline void viking_set_bpreg(unsigned long regval) regval 150 arch/sparc/include/asm/viking.h : "r" (regval), "i" (ASI_M_ACTION) regval 156 arch/sparc/include/asm/viking.h unsigned long regval; regval 159 arch/sparc/include/asm/viking.h : "=r" (regval) regval 161 arch/sparc/include/asm/viking.h return regval; regval 88 arch/sparc/kernel/auxio_32.c unsigned char regval; regval 95 arch/sparc/kernel/auxio_32.c regval = sbus_readb(auxio_register); regval 96 arch/sparc/kernel/auxio_32.c sbus_writeb(((regval | bits_on) & ~bits_off) | AUXIO_ORMEIN4M, regval 35 arch/sparc/kernel/auxio_64.c u8 regval, newval; regval 39 arch/sparc/kernel/auxio_64.c regval = (ebus ? regval 42 arch/sparc/kernel/auxio_64.c newval = regval | bits_on; regval 1857 drivers/ata/sata_nv.c u8 regval; regval 1860 drivers/ata/sata_nv.c pci_read_config_byte(pdev, 0x7f, ®val); regval 1861 drivers/ata/sata_nv.c regval &= ~(1 << 7); regval 1862 drivers/ata/sata_nv.c pci_write_config_byte(pdev, 0x7f, regval); regval 2371 drivers/ata/sata_nv.c u8 regval; regval 2373 drivers/ata/sata_nv.c pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); regval 2374 drivers/ata/sata_nv.c regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN; regval 2375 drivers/ata/sata_nv.c pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); regval 2408 drivers/ata/sata_nv.c u8 regval; regval 2410 drivers/ata/sata_nv.c pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); regval 2411 drivers/ata/sata_nv.c regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN; regval 2412 drivers/ata/sata_nv.c pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); regval 2448 drivers/ata/sata_nv.c u8 regval; regval 2451 drivers/ata/sata_nv.c pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); regval 2452 drivers/ata/sata_nv.c regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN; regval 2453 drivers/ata/sata_nv.c pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); regval 31 drivers/clk/hisilicon/clk-hisi-phase.c u32 regval) regval 36 drivers/clk/hisilicon/clk-hisi-phase.c if (phase->phase_regvals[i] == regval) regval 45 drivers/clk/hisilicon/clk-hisi-phase.c u32 regval; regval 47 drivers/clk/hisilicon/clk-hisi-phase.c regval = readl(phase->reg); regval 48 drivers/clk/hisilicon/clk-hisi-phase.c regval = (regval & phase->mask) >> phase->shift; regval 50 drivers/clk/hisilicon/clk-hisi-phase.c return hisi_phase_regval_to_degrees(phase, regval); regval 69 drivers/clk/hisilicon/clk-hisi-phase.c int regval; regval 72 drivers/clk/hisilicon/clk-hisi-phase.c regval = hisi_phase_degrees_to_regval(phase, degrees); regval 73 drivers/clk/hisilicon/clk-hisi-phase.c if (regval < 0) regval 74 drivers/clk/hisilicon/clk-hisi-phase.c return regval; regval 80 drivers/clk/hisilicon/clk-hisi-phase.c val |= regval << phase->shift; regval 36 drivers/clk/qcom/clk-hfpll.c u32 regval = hd->user_val; regval 43 drivers/clk/qcom/clk-hfpll.c regval |= hd->user_vco_mask; regval 44 drivers/clk/qcom/clk-hfpll.c regmap_write(regmap, hd->user_reg, regval); regval 24 drivers/clk/qcom/clk-krait.c u32 regval; regval 27 drivers/clk/qcom/clk-krait.c regval = krait_get_l2_indirect_reg(mux->offset); regval 28 drivers/clk/qcom/clk-krait.c regval &= ~(mux->mask << mux->shift); regval 29 drivers/clk/qcom/clk-krait.c regval |= (sel & mux->mask) << mux->shift; regval 31 drivers/clk/qcom/clk-krait.c regval &= ~(mux->mask << (mux->shift + LPL_SHIFT)); regval 32 drivers/clk/qcom/clk-krait.c regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT); regval 34 drivers/clk/qcom/clk-krait.c krait_set_l2_indirect_reg(mux->offset, regval); regval 47 drivers/crypto/ccp/ccp-debugfs.c unsigned int regval; regval 63 drivers/crypto/ccp/ccp-debugfs.c regval = ioread32(ccp->io_regs + CMD5_PSP_CCP_VERSION); regval 64 drivers/crypto/ccp/ccp-debugfs.c oboff += OSCNPRINTF(" Version: %d\n", regval & RI_VERSION_NUM); regval 66 drivers/crypto/ccp/ccp-debugfs.c if (regval & RI_AES_PRESENT) regval 68 drivers/crypto/ccp/ccp-debugfs.c if (regval & RI_3DES_PRESENT) regval 70 drivers/crypto/ccp/ccp-debugfs.c if (regval & RI_SHA_PRESENT) regval 72 drivers/crypto/ccp/ccp-debugfs.c if (regval & RI_RSA_PRESENT) regval 74 drivers/crypto/ccp/ccp-debugfs.c if (regval & RI_ECC_PRESENT) regval 76 drivers/crypto/ccp/ccp-debugfs.c if (regval & RI_ZDE_PRESENT) regval 78 drivers/crypto/ccp/ccp-debugfs.c if (regval & RI_ZCE_PRESENT) regval 80 drivers/crypto/ccp/ccp-debugfs.c if (regval & RI_TRNG_PRESENT) regval 84 drivers/crypto/ccp/ccp-debugfs.c (regval & RI_NUM_VQM) >> RI_NVQM_SHIFT); regval 86 drivers/crypto/ccp/ccp-debugfs.c (regval & RI_LSB_ENTRIES) >> RI_NLSB_SHIFT); regval 196 drivers/crypto/ccp/ccp-debugfs.c unsigned int regval; regval 224 drivers/crypto/ccp/ccp-debugfs.c regval = ioread32(cmd_q->reg_int_enable); regval 226 drivers/crypto/ccp/ccp-debugfs.c if (regval & INT_EMPTY_QUEUE) regval 228 drivers/crypto/ccp/ccp-debugfs.c if (regval & INT_QUEUE_STOPPED) regval 230 drivers/crypto/ccp/ccp-debugfs.c if (regval & INT_ERROR) regval 232 drivers/crypto/ccp/ccp-debugfs.c if (regval & INT_COMPLETION) regval 255 drivers/crypto/hisilicon/sec/sec_drv.c u32 regval; regval 257 drivers/crypto/hisilicon/sec/sec_drv.c regval = readl_relaxed(addr); regval 259 drivers/crypto/hisilicon/sec/sec_drv.c regval |= SEC_Q_ARUSER_CFG_PKG; regval 261 drivers/crypto/hisilicon/sec/sec_drv.c regval &= ~SEC_Q_ARUSER_CFG_PKG; regval 262 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(regval, addr); regval 270 drivers/crypto/hisilicon/sec/sec_drv.c u32 regval; regval 272 drivers/crypto/hisilicon/sec/sec_drv.c regval = readl_relaxed(addr); regval 273 drivers/crypto/hisilicon/sec/sec_drv.c regval |= SEC_Q_AWUSER_CFG_PKG; regval 274 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(regval, addr); regval 361 drivers/crypto/hisilicon/sec/sec_drv.c u32 regval; regval 363 drivers/crypto/hisilicon/sec/sec_drv.c regval = readl_relaxed(addr); regval 364 drivers/crypto/hisilicon/sec/sec_drv.c regval &= ~(SEC_CTRL2_ENDIAN_BD | SEC_CTRL2_ENDIAN_BD_TYPE); regval 365 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(regval, addr); regval 388 drivers/crypto/hisilicon/sec/sec_drv.c u32 regval; regval 390 drivers/crypto/hisilicon/sec/sec_drv.c regval = readl_relaxed(addr); regval 391 drivers/crypto/hisilicon/sec/sec_drv.c regval &= ~SEC_CTRL2_DATA_AXI_WR_OTSD_CFG_M; regval 392 drivers/crypto/hisilicon/sec/sec_drv.c regval |= (cfg << SEC_CTRL2_DATA_AXI_WR_OTSD_CFG_S) & regval 394 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(regval, addr); regval 400 drivers/crypto/hisilicon/sec/sec_drv.c u32 regval; regval 402 drivers/crypto/hisilicon/sec/sec_drv.c regval = readl_relaxed(addr); regval 403 drivers/crypto/hisilicon/sec/sec_drv.c regval &= ~SEC_CTRL2_DATA_AXI_RD_OTSD_CFG_M; regval 404 drivers/crypto/hisilicon/sec/sec_drv.c regval |= (cfg << SEC_CTRL2_DATA_AXI_RD_OTSD_CFG_S) & regval 406 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(regval, addr); regval 412 drivers/crypto/hisilicon/sec/sec_drv.c u32 regval; regval 414 drivers/crypto/hisilicon/sec/sec_drv.c regval = readl_relaxed(addr); regval 416 drivers/crypto/hisilicon/sec/sec_drv.c regval |= SEC_CTRL2_CLK_GATE_EN; regval 418 drivers/crypto/hisilicon/sec/sec_drv.c regval &= ~SEC_CTRL2_CLK_GATE_EN; regval 419 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(regval, addr); regval 425 drivers/crypto/hisilicon/sec/sec_drv.c u32 regval; regval 427 drivers/crypto/hisilicon/sec/sec_drv.c regval = readl_relaxed(addr); regval 429 drivers/crypto/hisilicon/sec/sec_drv.c regval |= SEC_COMMON_CNT_CLR_CE_CLEAR; regval 431 drivers/crypto/hisilicon/sec/sec_drv.c regval &= ~SEC_COMMON_CNT_CLR_CE_CLEAR; regval 432 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(regval, addr); regval 438 drivers/crypto/hisilicon/sec/sec_drv.c u32 regval; regval 440 drivers/crypto/hisilicon/sec/sec_drv.c regval = readl_relaxed(addr); regval 442 drivers/crypto/hisilicon/sec/sec_drv.c regval |= SEC_COMMON_CNT_CLR_CE_SNAP_EN; regval 444 drivers/crypto/hisilicon/sec/sec_drv.c regval &= ~SEC_COMMON_CNT_CLR_CE_SNAP_EN; regval 445 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(regval, addr); regval 474 drivers/crypto/hisilicon/sec/sec_drv.c u32 regval; regval 476 drivers/crypto/hisilicon/sec/sec_drv.c regval = readl_relaxed(addr); regval 478 drivers/crypto/hisilicon/sec/sec_drv.c regval &= ~SEC_DEBUG_BD_CFG_WB_NORMAL; regval 481 drivers/crypto/hisilicon/sec/sec_drv.c regval &= ~SEC_DEBUG_BD_CFG_WB_EN; regval 483 drivers/crypto/hisilicon/sec/sec_drv.c regval |= SEC_DEBUG_BD_CFG_WB_EN; regval 485 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(regval, addr); regval 492 drivers/crypto/hisilicon/sec/sec_drv.c u32 regval; regval 494 drivers/crypto/hisilicon/sec/sec_drv.c regval = readl_relaxed(addr); regval 496 drivers/crypto/hisilicon/sec/sec_drv.c regval |= SEC_SAA_CTRL_GET_QM_EN; regval 498 drivers/crypto/hisilicon/sec/sec_drv.c regval &= ~SEC_SAA_CTRL_GET_QM_EN; regval 499 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(regval, addr); regval 522 drivers/crypto/hisilicon/sec/sec_drv.c u32 regval; regval 524 drivers/crypto/hisilicon/sec/sec_drv.c regval = readl_relaxed(addr); regval 526 drivers/crypto/hisilicon/sec/sec_drv.c regval |= SEC_Q_ARUSER_CFG_FA; regval 527 drivers/crypto/hisilicon/sec/sec_drv.c regval &= ~SEC_Q_ARUSER_CFG_FNA; regval 529 drivers/crypto/hisilicon/sec/sec_drv.c regval &= ~SEC_Q_ARUSER_CFG_FA; regval 530 drivers/crypto/hisilicon/sec/sec_drv.c regval |= SEC_Q_ARUSER_CFG_FNA; regval 533 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(regval, addr); regval 539 drivers/crypto/hisilicon/sec/sec_drv.c u32 regval; regval 541 drivers/crypto/hisilicon/sec/sec_drv.c regval = readl_relaxed(addr); regval 543 drivers/crypto/hisilicon/sec/sec_drv.c regval |= SEC_Q_AWUSER_CFG_FA; regval 544 drivers/crypto/hisilicon/sec/sec_drv.c regval &= ~SEC_Q_AWUSER_CFG_FNA; regval 546 drivers/crypto/hisilicon/sec/sec_drv.c regval &= ~SEC_Q_AWUSER_CFG_FA; regval 547 drivers/crypto/hisilicon/sec/sec_drv.c regval |= SEC_Q_AWUSER_CFG_FNA; regval 550 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(regval, addr); regval 556 drivers/crypto/hisilicon/sec/sec_drv.c u32 regval; regval 558 drivers/crypto/hisilicon/sec/sec_drv.c regval = readl_relaxed(base + SEC_Q_CFG_REG); regval 560 drivers/crypto/hisilicon/sec/sec_drv.c regval |= SEC_Q_CFG_REORDER; regval 562 drivers/crypto/hisilicon/sec/sec_drv.c regval &= ~SEC_Q_CFG_REORDER; regval 563 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(regval, base + SEC_Q_CFG_REG); regval 569 drivers/crypto/hisilicon/sec/sec_drv.c u32 regval; regval 571 drivers/crypto/hisilicon/sec/sec_drv.c regval = readl_relaxed(addr); regval 572 drivers/crypto/hisilicon/sec/sec_drv.c regval &= ~SEC_Q_DEPTH_CFG_DEPTH_M; regval 573 drivers/crypto/hisilicon/sec/sec_drv.c regval |= (depth << SEC_Q_DEPTH_CFG_DEPTH_S) & SEC_Q_DEPTH_CFG_DEPTH_M; regval 575 drivers/crypto/hisilicon/sec/sec_drv.c writel_relaxed(regval, addr); regval 232 drivers/dma/owl-dma.c u32 regval; regval 234 drivers/dma/owl-dma.c regval = readl(pchan->base + reg); regval 237 drivers/dma/owl-dma.c regval |= val; regval 239 drivers/dma/owl-dma.c regval &= ~val; regval 256 drivers/dma/owl-dma.c u32 regval; regval 258 drivers/dma/owl-dma.c regval = readl(od->base + reg); regval 261 drivers/dma/owl-dma.c regval |= val; regval 263 drivers/dma/owl-dma.c regval &= ~val; regval 360 drivers/edac/synopsys_edac.c u32 regval, clearval = 0; regval 366 drivers/edac/synopsys_edac.c regval = readl(base + STAT_OFST); regval 367 drivers/edac/synopsys_edac.c if (!regval) regval 370 drivers/edac/synopsys_edac.c p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT; regval 371 drivers/edac/synopsys_edac.c p->ue_cnt = regval & STAT_UECNT_MASK; regval 373 drivers/edac/synopsys_edac.c regval = readl(base + CE_LOG_OFST); regval 374 drivers/edac/synopsys_edac.c if (!(p->ce_cnt && (regval & LOG_VALID))) regval 377 drivers/edac/synopsys_edac.c p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT; regval 378 drivers/edac/synopsys_edac.c regval = readl(base + CE_ADDR_OFST); regval 379 drivers/edac/synopsys_edac.c p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; regval 380 drivers/edac/synopsys_edac.c p->ceinfo.col = regval & ADDR_COL_MASK; regval 381 drivers/edac/synopsys_edac.c p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; regval 388 drivers/edac/synopsys_edac.c regval = readl(base + UE_LOG_OFST); regval 389 drivers/edac/synopsys_edac.c if (!(p->ue_cnt && (regval & LOG_VALID))) regval 392 drivers/edac/synopsys_edac.c regval = readl(base + UE_ADDR_OFST); regval 393 drivers/edac/synopsys_edac.c p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; regval 394 drivers/edac/synopsys_edac.c p->ueinfo.col = regval & ADDR_COL_MASK; regval 395 drivers/edac/synopsys_edac.c p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; regval 415 drivers/edac/synopsys_edac.c u32 regval, clearval = 0; regval 421 drivers/edac/synopsys_edac.c regval = readl(base + ECC_STAT_OFST); regval 422 drivers/edac/synopsys_edac.c if (!regval) regval 425 drivers/edac/synopsys_edac.c p->ce_cnt = (regval & ECC_STAT_CECNT_MASK) >> ECC_STAT_CECNT_SHIFT; regval 426 drivers/edac/synopsys_edac.c p->ue_cnt = (regval & ECC_STAT_UECNT_MASK) >> ECC_STAT_UECNT_SHIFT; regval 430 drivers/edac/synopsys_edac.c p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK); regval 432 drivers/edac/synopsys_edac.c regval = readl(base + ECC_CEADDR0_OFST); regval 433 drivers/edac/synopsys_edac.c p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK); regval 434 drivers/edac/synopsys_edac.c regval = readl(base + ECC_CEADDR1_OFST); regval 435 drivers/edac/synopsys_edac.c p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> regval 437 drivers/edac/synopsys_edac.c p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> regval 439 drivers/edac/synopsys_edac.c p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); regval 448 drivers/edac/synopsys_edac.c regval = readl(base + ECC_UEADDR0_OFST); regval 449 drivers/edac/synopsys_edac.c p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK); regval 450 drivers/edac/synopsys_edac.c regval = readl(base + ECC_UEADDR1_OFST); regval 451 drivers/edac/synopsys_edac.c p->ueinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> regval 453 drivers/edac/synopsys_edac.c p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> regval 455 drivers/edac/synopsys_edac.c p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); regval 531 drivers/edac/synopsys_edac.c int status, regval; regval 536 drivers/edac/synopsys_edac.c regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); regval 537 drivers/edac/synopsys_edac.c regval &= (DDR_QOSCE_MASK | DDR_QOSUE_MASK); regval 538 drivers/edac/synopsys_edac.c if (!(regval & ECC_CE_UE_INTR_MASK)) regval 551 drivers/edac/synopsys_edac.c writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); regval 921 drivers/edac/synopsys_edac.c int col = 0, row = 0, bank = 0, bankgrp = 0, rank = 0, regval; regval 962 drivers/edac/synopsys_edac.c regval = (rank << ECC_POISON0_RANK_SHIFT) & ECC_POISON0_RANK_MASK; regval 963 drivers/edac/synopsys_edac.c regval |= (col << ECC_POISON0_COLUMN_SHIFT) & ECC_POISON0_COLUMN_MASK; regval 964 drivers/edac/synopsys_edac.c writel(regval, priv->baseaddr + ECC_POISON0_OFST); regval 966 drivers/edac/synopsys_edac.c regval = (bankgrp << ECC_POISON1_BG_SHIFT) & ECC_POISON1_BG_MASK; regval 967 drivers/edac/synopsys_edac.c regval |= (bank << ECC_POISON1_BANKNR_SHIFT) & ECC_POISON1_BANKNR_MASK; regval 968 drivers/edac/synopsys_edac.c regval |= (row << ECC_POISON1_ROW_SHIFT) & ECC_POISON1_ROW_MASK; regval 969 drivers/edac/synopsys_edac.c writel(regval, priv->baseaddr + ECC_POISON1_OFST); regval 583 drivers/fpga/altera-cvp.c u32 regval; regval 603 drivers/fpga/altera-cvp.c pci_read_config_dword(pdev, offset + VSE_CVP_STATUS, ®val); regval 604 drivers/fpga/altera-cvp.c if (!(regval & VSE_CVP_STATUS_CVP_EN)) { regval 607 drivers/fpga/altera-cvp.c regval); regval 55 drivers/gpio/gpio-max77650.c int mask, regval; regval 58 drivers/gpio/gpio-max77650.c regval = value ? MAX77650_GPIO_OUT_HIGH : MAX77650_GPIO_OUT_LOW; regval 59 drivers/gpio/gpio-max77650.c regval |= MAX77650_GPIO_DIR_OUT; regval 62 drivers/gpio/gpio-max77650.c MAX77650_REG_CNFG_GPIO, mask, regval); regval 69 drivers/gpio/gpio-max77650.c int rv, regval; regval 71 drivers/gpio/gpio-max77650.c regval = value ? MAX77650_GPIO_OUT_HIGH : MAX77650_GPIO_OUT_LOW; regval 74 drivers/gpio/gpio-max77650.c MAX77650_GPIO_OUTVAL_MASK, regval); regval 73 drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c uint16_t regval[12]; regval 216 drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c val = output_csc_matrix[i].regval; regval 70 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t regval; regval 102 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c regval = REG_READ(AFMT_VBI_PACKET_CONTROL); regval 968 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c OUTPUT_CSC_C11, tbl_entry->regval[0], regval 969 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c OUTPUT_CSC_C12, tbl_entry->regval[1]); regval 973 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c OUTPUT_CSC_C11, tbl_entry->regval[2], regval 974 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c OUTPUT_CSC_C12, tbl_entry->regval[3]); regval 978 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c OUTPUT_CSC_C11, tbl_entry->regval[4], regval 979 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c OUTPUT_CSC_C12, tbl_entry->regval[5]); regval 983 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c OUTPUT_CSC_C11, tbl_entry->regval[6], regval 984 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c OUTPUT_CSC_C12, tbl_entry->regval[7]); regval 988 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c OUTPUT_CSC_C11, tbl_entry->regval[8], regval 989 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c OUTPUT_CSC_C12, tbl_entry->regval[9]); regval 993 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c OUTPUT_CSC_C11, tbl_entry->regval[10], regval 994 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c OUTPUT_CSC_C12, tbl_entry->regval[11]); regval 2490 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c tbl_entry.regval[i] = regval 2674 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; regval 132 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[0], regval 138 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[1], regval 150 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[2], regval 156 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[3], regval 168 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[4], regval 174 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[5], regval 186 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[6], regval 192 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[7], regval 204 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[8], regval 210 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[9], regval 222 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[10], regval 228 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[11], regval 246 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[0], regval 252 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[1], regval 264 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[2], regval 270 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[3], regval 282 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[4], regval 288 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[5], regval 300 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[6], regval 306 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[7], regval 318 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[8], regval 324 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[9], regval 336 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[10], regval 342 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c tbl_entry->regval[11], regval 508 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c uint32_t regval[12]; regval 536 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c const uint32_t *regval = NULL; regval 543 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c regval = input_csc_matrix[i].regval; regval 546 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c if (regval == NULL) { regval 563 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[0], INPUT_CSC_C11_C12_A, INPUT_CSC_C11_A); regval 565 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[1], INPUT_CSC_C11_C12_A, INPUT_CSC_C12_A); regval 570 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[2], INPUT_CSC_C13_C14_A, INPUT_CSC_C13_A); regval 572 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[3], INPUT_CSC_C13_C14_A, INPUT_CSC_C14_A); regval 577 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[4], INPUT_CSC_C21_C22_A, INPUT_CSC_C21_A); regval 579 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[5], INPUT_CSC_C21_C22_A, INPUT_CSC_C22_A); regval 584 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[6], INPUT_CSC_C23_C24_A, INPUT_CSC_C23_A); regval 586 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[7], INPUT_CSC_C23_C24_A, INPUT_CSC_C24_A); regval 591 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[8], INPUT_CSC_C31_C32_A, INPUT_CSC_C31_A); regval 593 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[9], INPUT_CSC_C31_C32_A, INPUT_CSC_C32_A); regval 598 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[10], INPUT_CSC_C33_C34_A, INPUT_CSC_C33_A); regval 600 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[11], INPUT_CSC_C33_C34_A, INPUT_CSC_C34_A); regval 606 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[0], INPUT_CSC_C11_C12_B, INPUT_CSC_C11_B); regval 608 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[1], INPUT_CSC_C11_C12_B, INPUT_CSC_C12_B); regval 613 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[2], INPUT_CSC_C13_C14_B, INPUT_CSC_C13_B); regval 615 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[3], INPUT_CSC_C13_C14_B, INPUT_CSC_C14_B); regval 620 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[4], INPUT_CSC_C21_C22_B, INPUT_CSC_C21_B); regval 622 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[5], INPUT_CSC_C21_C22_B, INPUT_CSC_C22_B); regval 627 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[6], INPUT_CSC_C23_C24_B, INPUT_CSC_C23_B); regval 629 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[7], INPUT_CSC_C23_C24_B, INPUT_CSC_C24_B); regval 634 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[8], INPUT_CSC_C31_C32_B, INPUT_CSC_C31_B); regval 636 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[9], INPUT_CSC_C31_C32_B, INPUT_CSC_C32_B); regval 641 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[10], INPUT_CSC_C33_C34_B, INPUT_CSC_C33_B); regval 643 drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_csc_v.c value, regval[11], INPUT_CSC_C33_C34_B, INPUT_CSC_C34_B); regval 109 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t regval; regval 113 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c regval = dm_read_reg(tg->ctx, address); regval 114 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c set_reg_field_value(regval, early_cntl, regval 116 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c dm_write_reg(tg->ctx, address, regval); regval 259 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t regval; regval 262 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c regval = dm_read_reg(tg->ctx, regval 265 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c set_reg_field_value(regval, 0, CRTC_COUNT_CONTROL, regval 269 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c set_reg_field_value(regval, 1, CRTC_COUNT_CONTROL, regval 273 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c CRTC_REG(mmCRTC_COUNT_CONTROL), regval); regval 594 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t regval; regval 597 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c regval = dm_read_reg(tg->ctx, address); regval 598 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c set_reg_field_value(regval, early_cntl, regval 600 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c dm_write_reg(tg->ctx, address, regval); regval 43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c const uint16_t *regval, regval 53 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c const uint16_t *regval0 = &(regval[2 * i]); regval 54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c const uint16_t *regval1 = &(regval[(2 * i) + 1]); regval 94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h const uint16_t *regval, regval 406 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c tbl_entry.regval[i] = input_csc_color_matrix.matrix[i]; regval 1470 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h const uint16_t *regval); regval 113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c const uint16_t *regval, regval 119 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c if (regval == NULL || select == GAMUT_REMAP_BYPASS) { regval 150 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c regval, regval 160 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c regval, regval 170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c regval, regval 206 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c const uint16_t *regval) regval 212 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c if (regval == NULL) { regval 252 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c regval, regval 264 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c const uint16_t *regval = NULL; regval 267 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c regval = find_color_matrix(colorspace, &arr_size); regval 268 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c if (regval == NULL) { regval 273 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_cm_program_color_matrix(dpp, regval); regval 331 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c const uint16_t *regval) regval 335 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_cm_program_color_matrix(dpp, regval); regval 447 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c const uint16_t *regval = NULL; regval 460 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c regval = dpp_input_csc_matrix[i].regval; regval 464 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c if (regval == NULL) { regval 469 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c regval = tbl_entry->regval; regval 506 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c regval, regval 380 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c uint32_t regval = enable ? 1 : 0; regval 382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c REG_UPDATE(OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, regval); regval 588 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c uint32_t regval = 0; regval 590 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c regval = REG_READ(OTG_CONTROL); regval 593 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if ((regval & 0x1) == 0x0) regval 61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t regval; regval 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c regval = REG_READ(AFMT_VBI_PACKET_CONTROL); regval 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c tbl_entry.regval[i] = input_csc_color_matrix.matrix[i]; regval 132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c const uint16_t *regval, regval 143 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c if (regval == NULL) { regval 162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c regval, regval 175 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c const uint16_t *regval = NULL; regval 181 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c regval = find_color_matrix(color_space, &arr_size); regval 183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c if (regval == NULL) { regval 204 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c regval, regval 272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h const uint16_t *regval, regval 75 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c uint32_t regval; regval 87 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c regval = REG_GET_3(gpio.MASK_reg, regval 101 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c REG_SET_2(gpio.MASK_reg, regval, regval 119 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c REG_SET(gpio.MASK_reg, regval, regval 128 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c REG_SET(gpio.MASK_reg, regval, regval 166 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c REG_SET(gpio.MASK_reg, regval, regval 51 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h uint16_t regval[12]; regval 145 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h const uint16_t *regval); regval 181 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h uint16_t regval[12]; regval 245 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h const uint16_t *regval, regval 386 drivers/gpu/ipu-v3/ipu-common.c u32 bursts, regval; regval 424 drivers/gpu/ipu-v3/ipu-common.c regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg); regval 425 drivers/gpu/ipu-v3/ipu-common.c regval &= ~(0x03 << idmac_lock_en_info[i].shift); regval 426 drivers/gpu/ipu-v3/ipu-common.c regval |= (bursts << idmac_lock_en_info[i].shift); regval 427 drivers/gpu/ipu-v3/ipu-common.c ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg); regval 169 drivers/hwmon/adc128d818.c u8 reg, regval; regval 179 drivers/hwmon/adc128d818.c regval = clamp_val(DIV_ROUND_CLOSEST(val, 10), 0, 255); regval 180 drivers/hwmon/adc128d818.c data->in[index][nr] = regval << 4; regval 182 drivers/hwmon/adc128d818.c i2c_smbus_write_byte_data(data->client, reg, regval); regval 210 drivers/hwmon/adc128d818.c s8 regval; regval 217 drivers/hwmon/adc128d818.c regval = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127); regval 218 drivers/hwmon/adc128d818.c data->temp[index] = regval << 1; regval 222 drivers/hwmon/adc128d818.c regval); regval 58 drivers/hwmon/ads7828.c unsigned int regval; regval 61 drivers/hwmon/ads7828.c err = regmap_read(data->regmap, cmd, ®val); regval 66 drivers/hwmon/ads7828.c DIV_ROUND_CLOSEST(regval * data->lsb_resol, 1000)); regval 113 drivers/hwmon/ads7828.c unsigned int regval; regval 175 drivers/hwmon/ads7828.c regmap_read(data->regmap, data->cmd_byte, ®val); regval 237 drivers/hwmon/asc7621.c u16 regval; regval 240 drivers/hwmon/asc7621.c regval = (data->reg[param->msb[0]] << 8) | data->reg[param->lsb[0]]; regval 244 drivers/hwmon/asc7621.c (regval == 0 ? -1 : (regval) == regval 245 drivers/hwmon/asc7621.c 0xffff ? 0 : 5400000 / regval)); regval 298 drivers/hwmon/asc7621.c u16 regval; regval 302 drivers/hwmon/asc7621.c regval = (data->reg[param->msb[0]] << 8) | (data->reg[param->lsb[0]]); regval 306 drivers/hwmon/asc7621.c regval = (regval >> 6) * asc7621_in_scaling[nr] / (0xc0 << 2); regval 308 drivers/hwmon/asc7621.c return sprintf(buf, "%u\n", regval); regval 405 drivers/hwmon/asc7621.c u8 regval = data->reg[param->msb[0]]; regval 406 drivers/hwmon/asc7621.c int temp = ((s8) (regval & 0xfc) * 1000) + ((regval & 0x03) * 250); regval 451 drivers/hwmon/asc7621.c u8 regval; regval 456 drivers/hwmon/asc7621.c regval = regval 458 drivers/hwmon/asc7621.c temp = auto_point1 + asc7621_range_map[clamp_val(regval, 0, 15)]; regval 501 drivers/hwmon/asc7621.c u8 config, altbit, regval; regval 510 drivers/hwmon/asc7621.c regval = config | (altbit << 3); regval 513 drivers/hwmon/asc7621.c return sprintf(buf, "%u\n", map[clamp_val(regval, 0, 15)]); regval 649 drivers/hwmon/asc7621.c u8 regval = regval 652 drivers/hwmon/asc7621.c regval = clamp_val(regval, 0, 15); regval 654 drivers/hwmon/asc7621.c return sprintf(buf, "%u\n", asc7621_pwm_freq_map[regval]); regval 697 drivers/hwmon/asc7621.c u8 regval = regval 700 drivers/hwmon/asc7621.c regval = clamp_val(regval, 0, 7); regval 702 drivers/hwmon/asc7621.c return sprintf(buf, "%u\n", asc7621_pwm_auto_spinup_map[regval]); regval 746 drivers/hwmon/asc7621.c u8 regval = regval 748 drivers/hwmon/asc7621.c regval = clamp_val(regval, 0, 7); regval 750 drivers/hwmon/asc7621.c return sprintf(buf, "%u\n", asc7621_temp_smoothing_time_map[regval]); regval 236 drivers/hwmon/ina209.c u16 regval; regval 247 drivers/hwmon/ina209.c regval = ina209_reg_from_interval(data->regs[INA209_CONFIGURATION], regval 250 drivers/hwmon/ina209.c regval); regval 251 drivers/hwmon/ina209.c data->regs[INA209_CONFIGURATION] = regval; regval 252 drivers/hwmon/ina209.c data->update_interval = ina209_interval_from_reg(regval); regval 196 drivers/hwmon/ina2xx.c static int ina2xx_read_reg(struct device *dev, int reg, unsigned int *regval) regval 205 drivers/hwmon/ina2xx.c ret = regmap_read(data->regmap, reg, regval); regval 209 drivers/hwmon/ina2xx.c dev_dbg(dev, "read %d, val = 0x%04x\n", reg, *regval); regval 219 drivers/hwmon/ina2xx.c if (*regval == 0) { regval 255 drivers/hwmon/ina2xx.c unsigned int regval) regval 262 drivers/hwmon/ina2xx.c val = DIV_ROUND_CLOSEST((s16)regval, data->config->shunt_div); regval 265 drivers/hwmon/ina2xx.c val = (regval >> data->config->bus_voltage_shift) regval 270 drivers/hwmon/ina2xx.c val = regval * data->power_lsb_uW; regval 274 drivers/hwmon/ina2xx.c val = (s16)regval * data->current_lsb_uA; regval 278 drivers/hwmon/ina2xx.c val = regval; regval 295 drivers/hwmon/ina2xx.c unsigned int regval; regval 297 drivers/hwmon/ina2xx.c int err = ina2xx_read_reg(dev, attr->index, ®val); regval 303 drivers/hwmon/ina2xx.c ina2xx_get_value(data, attr->index, regval)); regval 384 drivers/hwmon/ina2xx.c unsigned int regval; regval 386 drivers/hwmon/ina2xx.c status = regmap_read(data->regmap, INA2XX_CONFIG, ®val); regval 390 drivers/hwmon/ina2xx.c return snprintf(buf, PAGE_SIZE, "%d\n", ina226_reg_to_interval(regval)); regval 179 drivers/hwmon/ina3221.c unsigned int regval; regval 182 drivers/hwmon/ina3221.c ret = regmap_read(ina->regmap, reg, ®val); regval 186 drivers/hwmon/ina3221.c *val = sign_extend32(regval >> 3, 12); regval 203 drivers/hwmon/ina3221.c int regval; regval 207 drivers/hwmon/ina3221.c regval = INA3221_CONFIG_AVG(ina->reg_config); regval 208 drivers/hwmon/ina3221.c *val = ina3221_avg_samples[regval]; regval 225 drivers/hwmon/ina3221.c int regval, ret; regval 244 drivers/hwmon/ina3221.c ret = ina3221_read_value(ina, reg, ®val); regval 252 drivers/hwmon/ina3221.c *val = regval * (is_shunt ? 40 : 8); regval 277 drivers/hwmon/ina3221.c int regval, voltage_nv, ret; regval 296 drivers/hwmon/ina3221.c ret = ina3221_read_value(ina, reg, ®val); regval 301 drivers/hwmon/ina3221.c voltage_nv = regval * 40000; regval 313 drivers/hwmon/ina3221.c ret = regmap_field_read(ina->fields[reg], ®val); regval 316 drivers/hwmon/ina3221.c *val = regval; regval 372 drivers/hwmon/ina3221.c int regval, current_ma, voltage_uv; regval 385 drivers/hwmon/ina3221.c regval = DIV_ROUND_CLOSEST(voltage_uv, 5) & 0xfff8; regval 387 drivers/hwmon/ina3221.c return regmap_write(ina->regmap, reg, regval); regval 962 drivers/hwmon/it87.c u8 reg, regval; regval 978 drivers/hwmon/it87.c regval = it87_read_value(data, IT87_REG_BEEP_ENABLE); regval 979 drivers/hwmon/it87.c if (!(regval & 0x80)) { regval 980 drivers/hwmon/it87.c regval |= 0x80; regval 981 drivers/hwmon/it87.c it87_write_value(data, IT87_REG_BEEP_ENABLE, regval); regval 65 drivers/hwmon/k10temp.c void (*read_htcreg)(struct pci_dev *pdev, u32 *regval); regval 66 drivers/hwmon/k10temp.c void (*read_tempreg)(struct pci_dev *pdev, u32 *regval); regval 87 drivers/hwmon/k10temp.c static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval) regval 89 drivers/hwmon/k10temp.c pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval); regval 92 drivers/hwmon/k10temp.c static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval) regval 94 drivers/hwmon/k10temp.c pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval); regval 108 drivers/hwmon/k10temp.c static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval) regval 111 drivers/hwmon/k10temp.c F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval); regval 114 drivers/hwmon/k10temp.c static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval) regval 117 drivers/hwmon/k10temp.c F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval); regval 120 drivers/hwmon/k10temp.c static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval) regval 123 drivers/hwmon/k10temp.c F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval); regval 129 drivers/hwmon/k10temp.c u32 regval; regval 131 drivers/hwmon/k10temp.c data->read_tempreg(data->pdev, ®val); regval 132 drivers/hwmon/k10temp.c temp = (regval >> 21) * 125; regval 133 drivers/hwmon/k10temp.c if (regval & data->temp_adjust_mask) regval 181 drivers/hwmon/k10temp.c u32 regval; regval 184 drivers/hwmon/k10temp.c data->read_htcreg(data->pdev, ®val); regval 185 drivers/hwmon/k10temp.c value = ((regval >> 16) & 0x7f) * 500 + 52000; regval 187 drivers/hwmon/k10temp.c value -= ((regval >> 24) & 0xf) * 500; regval 327 drivers/hwmon/lm75.c unsigned int regval; regval 354 drivers/hwmon/lm75.c err = regmap_read(data->regmap, reg, ®val); regval 358 drivers/hwmon/lm75.c *val = lm75_reg_to_mc(regval, data->resolution); regval 464 drivers/hwmon/lm95234.c u8 regval; regval 473 drivers/hwmon/lm95234.c for (regval = 0; regval < 3; regval++) { regval 474 drivers/hwmon/lm95234.c if (val <= update_intervals[regval]) regval 479 drivers/hwmon/lm95234.c data->interval = msecs_to_jiffies(update_intervals[regval]); regval 480 drivers/hwmon/lm95234.c i2c_smbus_write_byte_data(data->client, LM95234_REG_CONVRATE, regval); regval 281 drivers/hwmon/lm95245.c unsigned int regval; regval 298 drivers/hwmon/lm95245.c ®val); regval 305 drivers/hwmon/lm95245.c val = regval - val / 1000; regval 242 drivers/hwmon/ltc2945.c int regval; regval 250 drivers/hwmon/ltc2945.c regval = ltc2945_val_to_reg(dev, reg, val); regval 252 drivers/hwmon/ltc2945.c regval = clamp_val(regval, 0, 0xffffff); regval 253 drivers/hwmon/ltc2945.c regbuf[0] = regval >> 16; regval 254 drivers/hwmon/ltc2945.c regbuf[1] = (regval >> 8) & 0xff; regval 255 drivers/hwmon/ltc2945.c regbuf[2] = regval; regval 258 drivers/hwmon/ltc2945.c regval = clamp_val(regval, 0, 0xfff) << 4; regval 259 drivers/hwmon/ltc2945.c regbuf[0] = regval >> 8; regval 260 drivers/hwmon/ltc2945.c regbuf[1] = regval & 0xff; regval 79 drivers/hwmon/ltc4215.c const u8 regval = data->regs[reg]; regval 85 drivers/hwmon/ltc4215.c voltage = regval * 151 / 1000; regval 89 drivers/hwmon/ltc4215.c voltage = regval * 605 / 10; regval 96 drivers/hwmon/ltc4215.c voltage = regval * 482 * 125 / 1000; regval 173 drivers/hwmon/ltc4245.c const u8 regval = data->vregs[reg - 0x10]; regval 179 drivers/hwmon/ltc4245.c voltage = regval * 55; regval 183 drivers/hwmon/ltc4245.c voltage = regval * 22; regval 187 drivers/hwmon/ltc4245.c voltage = regval * 15; regval 191 drivers/hwmon/ltc4245.c voltage = regval * -55; regval 194 drivers/hwmon/ltc4245.c voltage = regval * 10; regval 209 drivers/hwmon/ltc4245.c const u8 regval = data->vregs[reg - 0x10]; regval 230 drivers/hwmon/ltc4245.c voltage = regval * 250; /* voltage in uV */ regval 234 drivers/hwmon/ltc4245.c voltage = regval * 125; /* voltage in uV */ regval 238 drivers/hwmon/ltc4245.c voltage = regval * 125; /* voltage in uV */ regval 242 drivers/hwmon/ltc4245.c voltage = regval * 250; /* voltage in uV */ regval 295 drivers/hwmon/ltc4245.c int regval = data->gpios[channel - 8]; regval 297 drivers/hwmon/ltc4245.c if (regval < 0) regval 298 drivers/hwmon/ltc4245.c return regval; regval 299 drivers/hwmon/ltc4245.c *val = regval * 10; regval 167 drivers/hwmon/max6621.c static int max6621_verify_reg_data(struct device *dev, int regval) regval 169 drivers/hwmon/max6621.c if (regval >= MAX6621_PECI_ERR_MIN && regval 170 drivers/hwmon/max6621.c regval <= MAX6621_PECI_ERR_MAX) { regval 172 drivers/hwmon/max6621.c regval); regval 177 drivers/hwmon/max6621.c switch (regval) { regval 180 drivers/hwmon/max6621.c regval); regval 183 drivers/hwmon/max6621.c dev_dbg(dev, "Polling disabled - err 0x%04x.\n", regval); regval 187 drivers/hwmon/max6621.c regval); regval 190 drivers/hwmon/max6621.c dev_dbg(dev, "Resource is disabled - err 0x%04x.\n", regval); regval 193 drivers/hwmon/max6621.c dev_dbg(dev, "No alert active - err 0x%04x.\n", regval); regval 205 drivers/hwmon/max6621.c u32 regval; regval 215 drivers/hwmon/max6621.c ret = regmap_read(data->regmap, reg, ®val); regval 219 drivers/hwmon/max6621.c ret = max6621_verify_reg_data(dev, regval); regval 228 drivers/hwmon/max6621.c temp = (regval >> MAX6621_REG_TEMP_SHIFT); regval 234 drivers/hwmon/max6621.c ®val); regval 238 drivers/hwmon/max6621.c ret = max6621_verify_reg_data(dev, regval); regval 242 drivers/hwmon/max6621.c *val = (regval >> MAX6621_REG_TEMP_SHIFT) * regval 249 drivers/hwmon/max6621.c ret = regmap_read(data->regmap, reg, ®val); regval 253 drivers/hwmon/max6621.c ret = max6621_verify_reg_data(dev, regval); regval 257 drivers/hwmon/max6621.c *val = regval * 1000L; regval 270 drivers/hwmon/max6621.c ®val); regval 274 drivers/hwmon/max6621.c ret = max6621_verify_reg_data(dev, regval); regval 277 drivers/hwmon/max6621.c if (regval == MAX6621_ALERT_DIS) regval 287 drivers/hwmon/max6621.c if (regval) { regval 294 drivers/hwmon/max6621.c *val = !!regval; regval 118 drivers/hwmon/mlxreg-fan.c u32 regval; regval 126 drivers/hwmon/mlxreg-fan.c err = regmap_read(fan->regmap, tacho->reg, ®val); regval 130 drivers/hwmon/mlxreg-fan.c *val = MLXREG_FAN_GET_RPM(regval, fan->divider, regval 135 drivers/hwmon/mlxreg-fan.c err = regmap_read(fan->regmap, tacho->reg, ®val); regval 139 drivers/hwmon/mlxreg-fan.c *val = MLXREG_FAN_GET_FAULT(regval, tacho->mask); regval 150 drivers/hwmon/mlxreg-fan.c err = regmap_read(fan->regmap, fan->pwm.reg, ®val); regval 154 drivers/hwmon/mlxreg-fan.c *val = regval; regval 274 drivers/hwmon/mlxreg-fan.c u32 regval; regval 277 drivers/hwmon/mlxreg-fan.c err = regmap_read(fan->regmap, fan->pwm.reg, ®val); regval 283 drivers/hwmon/mlxreg-fan.c *state = MLXREG_FAN_PWM_DUTY2STATE(regval); regval 294 drivers/hwmon/mlxreg-fan.c u32 regval; regval 314 drivers/hwmon/mlxreg-fan.c err = regmap_read(fan->regmap, fan->pwm.reg, ®val); regval 320 drivers/hwmon/mlxreg-fan.c cur_state = MLXREG_FAN_PWM_DUTY2STATE(regval); regval 350 drivers/hwmon/mlxreg-fan.c u32 regval; regval 353 drivers/hwmon/mlxreg-fan.c err = regmap_read(fan->regmap, data->capability, ®val); regval 360 drivers/hwmon/mlxreg-fan.c return !!(regval & data->bit); regval 366 drivers/hwmon/mlxreg-fan.c u32 regval; regval 369 drivers/hwmon/mlxreg-fan.c err = regmap_read(fan->regmap, data->capability, ®val); regval 382 drivers/hwmon/mlxreg-fan.c if (regval > 0 && regval <= MLXREG_FAN_TACHO_DIV_SCALE_MAX) regval 383 drivers/hwmon/mlxreg-fan.c fan->divider = regval * MLXREG_FAN_TACHO_DIV_MIN; regval 106 drivers/hwmon/nct7802.c unsigned int regval; regval 112 drivers/hwmon/nct7802.c ret = regmap_read(data->regmap, 0x5E, ®val); regval 116 drivers/hwmon/nct7802.c return sprintf(buf, "%u\n", !(regval & (1 << sattr->index))); regval 532 drivers/hwmon/nct7802.c unsigned int regval; regval 535 drivers/hwmon/nct7802.c err = regmap_read(data->regmap, sattr->nr, ®val); regval 539 drivers/hwmon/nct7802.c return sprintf(buf, "%u\n", !!(regval & (1 << sattr->index))); regval 856 drivers/hwmon/pmbus/pmbus_core.c u16 regval; regval 863 drivers/hwmon/pmbus/pmbus_core.c regval = pmbus_data2reg_direct(data, sensor, val); regval 866 drivers/hwmon/pmbus/pmbus_core.c regval = pmbus_data2reg_vid(data, sensor, val); regval 870 drivers/hwmon/pmbus/pmbus_core.c regval = pmbus_data2reg_linear(data, sensor, val); regval 873 drivers/hwmon/pmbus/pmbus_core.c return regval; regval 907 drivers/hwmon/pmbus/pmbus_core.c u16 regval; regval 913 drivers/hwmon/pmbus/pmbus_core.c regval = status & mask; regval 915 drivers/hwmon/pmbus/pmbus_core.c ret = !!regval; regval 929 drivers/hwmon/pmbus/pmbus_core.c ret = !!(regval && v1 >= v2); regval 970 drivers/hwmon/pmbus/pmbus_core.c u16 regval; regval 976 drivers/hwmon/pmbus/pmbus_core.c regval = pmbus_data2reg(data, sensor, val); regval 977 drivers/hwmon/pmbus/pmbus_core.c ret = _pmbus_write_word_data(client, sensor->page, sensor->reg, regval); regval 981 drivers/hwmon/pmbus/pmbus_core.c sensor->data = regval; regval 1853 drivers/hwmon/pmbus/pmbus_core.c int regval; regval 1867 drivers/hwmon/pmbus/pmbus_core.c regval = _pmbus_read_byte_data(client, page, regval 1869 drivers/hwmon/pmbus/pmbus_core.c if (regval < 0 || regval 1870 drivers/hwmon/pmbus/pmbus_core.c (!(regval & (PB_FAN_1_INSTALLED >> ((f & 1) * 4))))) regval 1882 drivers/hwmon/pmbus/pmbus_core.c page, f, regval); regval 76 drivers/hwmon/tmp102.c unsigned int regval; regval 98 drivers/hwmon/tmp102.c err = regmap_read(tmp102->regmap, reg, ®val); regval 101 drivers/hwmon/tmp102.c *temp = tmp102_reg_to_mC(regval); regval 198 drivers/hwmon/tmp102.c unsigned int regval; regval 218 drivers/hwmon/tmp102.c err = regmap_read(tmp102->regmap, TMP102_CONF_REG, ®val); regval 224 drivers/hwmon/tmp102.c if ((regval & ~TMP102_CONFREG_MASK) != regval 230 drivers/hwmon/tmp102.c tmp102->config_orig = regval; regval 236 drivers/hwmon/tmp102.c regval &= ~TMP102_CONFIG_CLEAR; regval 237 drivers/hwmon/tmp102.c regval |= TMP102_CONFIG_SET; regval 239 drivers/hwmon/tmp102.c err = regmap_write(tmp102->regmap, TMP102_CONF_REG, regval); regval 59 drivers/hwmon/tmp103.c unsigned int regval; regval 62 drivers/hwmon/tmp103.c ret = regmap_read(regmap, sda->index, ®val); regval 66 drivers/hwmon/tmp103.c return sprintf(buf, "%d\n", tmp103_reg_to_mc(regval)); regval 95 drivers/hwmon/tmp108.c unsigned int regval; regval 101 drivers/hwmon/tmp108.c ®val); regval 104 drivers/hwmon/tmp108.c switch (regval & TMP108_CONF_CONVRATE_MASK) { regval 132 drivers/hwmon/tmp108.c err = regmap_read(tmp108->regmap, TMP108_REG_TEMP, ®val); regval 135 drivers/hwmon/tmp108.c *temp = tmp108_temp_reg_to_mC(regval); regval 140 drivers/hwmon/tmp108.c TMP108_REG_TLOW : TMP108_REG_THIGH, ®val); regval 143 drivers/hwmon/tmp108.c *temp = tmp108_temp_reg_to_mC(regval); regval 147 drivers/hwmon/tmp108.c err = regmap_read(tmp108->regmap, TMP108_REG_CONF, ®val); regval 150 drivers/hwmon/tmp108.c *temp = !!(regval & (attr == hwmon_temp_min_alarm ? regval 155 drivers/hwmon/tmp108.c err = regmap_read(tmp108->regmap, TMP108_REG_CONF, ®val); regval 158 drivers/hwmon/tmp108.c switch (regval & TMP108_CONF_HYSTERESIS_MASK) { regval 174 drivers/hwmon/tmp108.c TMP108_REG_TLOW : TMP108_REG_THIGH, ®val); regval 177 drivers/hwmon/tmp108.c *temp = tmp108_temp_reg_to_mC(regval); regval 194 drivers/hwmon/tmp108.c u32 regval, mask; regval 229 drivers/hwmon/tmp108.c ®val); regval 233 drivers/hwmon/tmp108.c temp -= tmp108_temp_reg_to_mC(regval); regval 235 drivers/hwmon/tmp108.c temp = tmp108_temp_reg_to_mC(regval) - temp; regval 1957 drivers/hwmon/w83627ehf.c int fan3pin, fan4pin, fan4min, fan5pin, regval; regval 1977 drivers/hwmon/w83627ehf.c regval = superio_inb(sio_data->sioreg, SIO_REG_ENABLE); regval 1979 drivers/hwmon/w83627ehf.c if (regval & 0x80) regval 1984 drivers/hwmon/w83627ehf.c if (regval & 0x40) regval 1989 drivers/hwmon/w83627ehf.c if (regval & 0x20) regval 2026 drivers/hwmon/w83627ehf.c regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1); regval 2027 drivers/hwmon/w83627ehf.c if ((regval & (1 << 2)) && fan4pin) { regval 2031 drivers/hwmon/w83627ehf.c if (!(regval & (1 << 1)) && fan5pin) { regval 63 drivers/hwmon/w83773g.c unsigned int regval; regval 66 drivers/hwmon/w83773g.c ret = regmap_read(regmap, W83773_LOCAL_TEMP, ®val); regval 70 drivers/hwmon/w83773g.c *val = temp_of_local(regval); regval 94 drivers/hwmon/w83773g.c unsigned int regval; regval 97 drivers/hwmon/w83773g.c ret = regmap_read(regmap, W83773_STATUS[index], ®val); regval 101 drivers/hwmon/w83773g.c *val = (regval & 0x04) >> 2; regval 144 drivers/hwmon/w83773g.c unsigned int regval; regval 147 drivers/hwmon/w83773g.c ret = regmap_read(regmap, W83773_CONVERSION_RATE_REG_READ, ®val); regval 151 drivers/hwmon/w83773g.c *val = 16000 >> regval; regval 283 drivers/i2c/busses/i2c-brcmstb.c u32 regval = dev->bsc_regmap->iic_enable; regval 285 drivers/i2c/busses/i2c-brcmstb.c dev->bsc_regmap->iic_enable = (regval & ~COND_START_STOP) | cond_flag; regval 492 drivers/i2c/busses/i2c-cadence.c u32 regval; regval 497 drivers/i2c/busses/i2c-cadence.c regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); regval 498 drivers/i2c/busses/i2c-cadence.c regval &= ~CDNS_I2C_CR_HOLD; regval 499 drivers/i2c/busses/i2c-cadence.c regval |= CDNS_I2C_CR_CLR_FIFO; regval 500 drivers/i2c/busses/i2c-cadence.c cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET); regval 504 drivers/i2c/busses/i2c-cadence.c regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); regval 505 drivers/i2c/busses/i2c-cadence.c cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET); regval 507 drivers/i2c/busses/i2c-cadence.c regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET); regval 508 drivers/i2c/busses/i2c-cadence.c cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET); regval 165 drivers/i2c/busses/i2c-jz4780.c unsigned short regval; regval 171 drivers/i2c/busses/i2c-jz4780.c regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA); regval 172 drivers/i2c/busses/i2c-jz4780.c if (!(regval & JZ4780_I2C_ENB_I2C)) regval 178 drivers/i2c/busses/i2c-jz4780.c dev_err(&i2c->adap.dev, "disable failed: ENSTA=0x%04x\n", regval); regval 184 drivers/i2c/busses/i2c-jz4780.c unsigned short regval; regval 190 drivers/i2c/busses/i2c-jz4780.c regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA); regval 191 drivers/i2c/busses/i2c-jz4780.c if (regval & JZ4780_I2C_ENB_I2C) regval 197 drivers/i2c/busses/i2c-jz4780.c dev_err(&i2c->adap.dev, "enable failed: ENSTA=0x%04x\n", regval); regval 203 drivers/i2c/busses/i2c-jz4780.c unsigned short regval; regval 207 drivers/i2c/busses/i2c-jz4780.c regval = jz4780_i2c_readw(i2c, JZ4780_I2C_STA); regval 208 drivers/i2c/busses/i2c-jz4780.c if ((regval & JZ4780_I2C_STA_TFE) && regval 209 drivers/i2c/busses/i2c-jz4780.c !(regval & JZ4780_I2C_STA_MSTACT)) regval 222 drivers/i2c/busses/i2c-jz4780.c address, regval); regval 108 drivers/i2c/busses/i2c-owl.c unsigned int regval; regval 110 drivers/i2c/busses/i2c-owl.c regval = readl(reg); regval 113 drivers/i2c/busses/i2c-owl.c regval |= val; regval 115 drivers/i2c/busses/i2c-owl.c regval &= ~val; regval 117 drivers/i2c/busses/i2c-owl.c writel(regval, reg); regval 104 drivers/i2c/busses/i2c-sirf.c u32 regval; regval 110 drivers/i2c/busses/i2c-sirf.c regval = SIRFSOC_I2C_READ | SIRFSOC_I2C_CMD_RP(0); regval 113 drivers/i2c/busses/i2c-sirf.c regval |= SIRFSOC_I2C_STOP | SIRFSOC_I2C_NACK; regval 114 drivers/i2c/busses/i2c-sirf.c writel(regval, regval 123 drivers/i2c/busses/i2c-sirf.c regval = SIRFSOC_I2C_WRITE | SIRFSOC_I2C_CMD_RP(0); regval 126 drivers/i2c/busses/i2c-sirf.c regval |= SIRFSOC_I2C_STOP; regval 127 drivers/i2c/busses/i2c-sirf.c writel(regval, regval 184 drivers/i2c/busses/i2c-sirf.c u32 regval = SIRFSOC_I2C_START | SIRFSOC_I2C_CMD_RP(0) | SIRFSOC_I2C_WRITE; regval 188 drivers/i2c/busses/i2c-sirf.c regval |= SIRFSOC_I2C_STOP; regval 190 drivers/i2c/busses/i2c-sirf.c writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); regval 203 drivers/i2c/busses/i2c-sirf.c u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL); regval 209 drivers/i2c/busses/i2c-sirf.c writel(regval | SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN, regval 218 drivers/i2c/busses/i2c-sirf.c writel(regval & ~(SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN), regval 282 drivers/i2c/busses/i2c-sirf.c u32 regval; regval 376 drivers/i2c/busses/i2c-sirf.c regval = ctrl_speed / (bitrate * 5); regval 378 drivers/i2c/busses/i2c-sirf.c regval = (2 * ctrl_speed) / (bitrate * 11); regval 380 drivers/i2c/busses/i2c-sirf.c regval = ctrl_speed / (bitrate * 6); regval 382 drivers/i2c/busses/i2c-sirf.c writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL); regval 383 drivers/i2c/busses/i2c-sirf.c if (regval > 0xFF) regval 386 drivers/i2c/busses/i2c-sirf.c writel(regval, siic->base + SIRFSOC_I2C_SDA_DELAY); regval 108 drivers/i2c/muxes/i2c-mux-mlxcpld.c u8 regval = chan + 1; regval 112 drivers/i2c/muxes/i2c-mux-mlxcpld.c if (data->last_chan != regval) { regval 113 drivers/i2c/muxes/i2c-mux-mlxcpld.c err = mlxcpld_mux_reg_write(muxc->parent, client, regval); regval 114 drivers/i2c/muxes/i2c-mux-mlxcpld.c data->last_chan = err < 0 ? 0 : regval; regval 237 drivers/i2c/muxes/i2c-mux-pca954x.c u8 regval; regval 242 drivers/i2c/muxes/i2c-mux-pca954x.c regval = chan | chip->enable; regval 244 drivers/i2c/muxes/i2c-mux-pca954x.c regval = 1 << chan; regval 247 drivers/i2c/muxes/i2c-mux-pca954x.c if (data->last_chan != regval) { regval 248 drivers/i2c/muxes/i2c-mux-pca954x.c ret = pca954x_reg_write(muxc->parent, client, regval); regval 249 drivers/i2c/muxes/i2c-mux-pca954x.c data->last_chan = ret < 0 ? 0 : regval; regval 92 drivers/iio/accel/adxl345_core.c unsigned int regval; regval 124 drivers/iio/accel/adxl345_core.c ADXL345_REG_OFS_AXIS(chan->address), ®val); regval 131 drivers/iio/accel/adxl345_core.c *val = sign_extend32(regval, 7) * 4; regval 135 drivers/iio/accel/adxl345_core.c ret = regmap_read(data->regmap, ADXL345_REG_BW_RATE, ®val); regval 140 drivers/iio/accel/adxl345_core.c (regval & ADXL345_BW_RATE); regval 216 drivers/iio/accel/adxl345_core.c u32 regval; regval 219 drivers/iio/accel/adxl345_core.c ret = regmap_read(regmap, ADXL345_REG_DEVID, ®val); regval 225 drivers/iio/accel/adxl345_core.c if (regval != ADXL345_DEVID) { regval 227 drivers/iio/accel/adxl345_core.c regval, ADXL345_DEVID); regval 281 drivers/iio/accel/adxl372.c __be16 regval; regval 284 drivers/iio/accel/adxl372.c ret = regmap_bulk_read(st->regmap, addr, ®val, sizeof(regval)); regval 288 drivers/iio/accel/adxl372.c return be16_to_cpu(regval); regval 567 drivers/iio/accel/adxl372.c unsigned int regval; regval 570 drivers/iio/accel/adxl372.c ret = regmap_read(st->regmap, ADXL372_DEVID, ®val); regval 574 drivers/iio/accel/adxl372.c if (regval != ADXL372_DEVID_VAL) { regval 575 drivers/iio/accel/adxl372.c dev_err(st->dev, "Invalid chip id %x\n", regval); regval 24 drivers/iio/accel/adxl372_i2c.c unsigned int regval; regval 31 drivers/iio/accel/adxl372_i2c.c ret = regmap_read(regmap, ADXL372_REVID, ®val); regval 36 drivers/iio/accel/adxl372_i2c.c if (regval < 3) regval 165 drivers/iio/accel/kxsd9.c unsigned int regval; regval 191 drivers/iio/accel/kxsd9.c ®val); regval 195 drivers/iio/accel/kxsd9.c *val2 = kxsd9_micro_scales[regval & KXSD9_CTRL_C_FS_MASK]; regval 279 drivers/iio/adc/ad7291.c u16 regval; regval 282 drivers/iio/adc/ad7291.c regval = chip->command; regval 300 drivers/iio/adc/ad7291.c regval &= ~AD7291_AUTOCYCLE; regval 301 drivers/iio/adc/ad7291.c regval |= chip->c_mask; regval 303 drivers/iio/adc/ad7291.c regval |= AD7291_AUTOCYCLE; regval 305 drivers/iio/adc/ad7291.c ret = ad7291_i2c_write(chip, AD7291_COMMAND, regval); regval 309 drivers/iio/adc/ad7291.c chip->command = regval; regval 328 drivers/iio/adc/ad7291.c u16 regval; regval 341 drivers/iio/adc/ad7291.c regval = chip->command & (~AD7291_VOLTAGE_MASK); regval 342 drivers/iio/adc/ad7291.c regval |= BIT(15 - chan->channel); regval 343 drivers/iio/adc/ad7291.c ret = ad7291_i2c_write(chip, AD7291_COMMAND, regval); regval 204 drivers/iio/adc/ad7768-1.c int regval; regval 206 drivers/iio/adc/ad7768-1.c regval = ad7768_spi_reg_read(st, AD7768_REG_CONVERSION, 1); regval 207 drivers/iio/adc/ad7768-1.c if (regval < 0) regval 208 drivers/iio/adc/ad7768-1.c return regval; regval 210 drivers/iio/adc/ad7768-1.c regval &= ~AD7768_CONV_MODE_MSK; regval 211 drivers/iio/adc/ad7768-1.c regval |= AD7768_CONV_MODE(mode); regval 213 drivers/iio/adc/ad7768-1.c return ad7768_spi_reg_write(st, AD7768_REG_CONVERSION, regval); regval 530 drivers/iio/adc/axp20x_adc.c unsigned int reg, regval; regval 547 drivers/iio/adc/axp20x_adc.c regval = AXP20X_GPIO10_IN_RANGE_GPIO0_VAL(val); regval 552 drivers/iio/adc/axp20x_adc.c regval = AXP20X_GPIO10_IN_RANGE_GPIO1_VAL(val); regval 560 drivers/iio/adc/axp20x_adc.c regval); regval 178 drivers/iio/adc/ina2xx-adc.c unsigned int regval; regval 182 drivers/iio/adc/ina2xx-adc.c ret = regmap_read(chip->regmap, chan->address, ®val); regval 187 drivers/iio/adc/ina2xx-adc.c *val = (s16) regval; regval 189 drivers/iio/adc/ina2xx-adc.c *val = regval; regval 471 drivers/iio/adc/max9611.c u16 regval; regval 483 drivers/iio/adc/max9611.c ret = max9611_read_single(max9611, CONF_TEMP, ®val); regval 487 drivers/iio/adc/max9611.c regval &= MAX9611_TEMP_MASK; regval 489 drivers/iio/adc/max9611.c if ((regval > MAX9611_TEMP_MAX_POS && regval 490 drivers/iio/adc/max9611.c regval < MAX9611_TEMP_MIN_NEG) || regval 491 drivers/iio/adc/max9611.c regval > MAX9611_TEMP_MAX_NEG) { regval 494 drivers/iio/adc/max9611.c regval); regval 304 drivers/iio/adc/meson_saradc.c u32 regval; regval 306 drivers/iio/adc/meson_saradc.c regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); regval 308 drivers/iio/adc/meson_saradc.c return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval); regval 325 drivers/iio/adc/meson_saradc.c int regval, timeout = 10000; regval 334 drivers/iio/adc/meson_saradc.c regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); regval 335 drivers/iio/adc/meson_saradc.c } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--); regval 348 drivers/iio/adc/meson_saradc.c int regval, fifo_chan, fifo_val, count; regval 361 drivers/iio/adc/meson_saradc.c regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val); regval 362 drivers/iio/adc/meson_saradc.c fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval); regval 370 drivers/iio/adc/meson_saradc.c fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval); regval 399 drivers/iio/adc/meson_saradc.c u32 regval; regval 406 drivers/iio/adc/meson_saradc.c regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0); regval 408 drivers/iio/adc/meson_saradc.c MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval); regval 411 drivers/iio/adc/meson_saradc.c regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval 414 drivers/iio/adc/meson_saradc.c MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval); regval 416 drivers/iio/adc/meson_saradc.c regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK, regval 420 drivers/iio/adc/meson_saradc.c regval); regval 422 drivers/iio/adc/meson_saradc.c regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK, regval 426 drivers/iio/adc/meson_saradc.c regval); regval 430 drivers/iio/adc/meson_saradc.c regval = MESON_SAR_ADC_DELTA_10_TEMP_SEL; regval 432 drivers/iio/adc/meson_saradc.c regval = 0; regval 436 drivers/iio/adc/meson_saradc.c MESON_SAR_ADC_DELTA_10_TEMP_SEL, regval); regval 444 drivers/iio/adc/meson_saradc.c u32 regval; regval 446 drivers/iio/adc/meson_saradc.c regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel); regval 448 drivers/iio/adc/meson_saradc.c MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval); regval 773 drivers/iio/adc/meson_saradc.c int regval, i, ret; regval 787 drivers/iio/adc/meson_saradc.c regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val); regval 788 drivers/iio/adc/meson_saradc.c if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED) regval 834 drivers/iio/adc/meson_saradc.c regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0); regval 837 drivers/iio/adc/meson_saradc.c regval); regval 838 drivers/iio/adc/meson_saradc.c regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1); regval 841 drivers/iio/adc/meson_saradc.c regval); regval 849 drivers/iio/adc/meson_saradc.c regval = 0; regval 851 drivers/iio/adc/meson_saradc.c regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i); regval 852 drivers/iio/adc/meson_saradc.c regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW; regval 853 drivers/iio/adc/meson_saradc.c regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW; regval 854 drivers/iio/adc/meson_saradc.c regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval); regval 868 drivers/iio/adc/meson_saradc.c regval = FIELD_PREP(MESON_SAR_ADC_DELTA_10_TS_C_MASK, regval 871 drivers/iio/adc/meson_saradc.c MESON_SAR_ADC_DELTA_10_TS_C_MASK, regval); regval 875 drivers/iio/adc/meson_saradc.c regval = MESON_HHI_DPLL_TOP_0_TSC_BIT4; regval 877 drivers/iio/adc/meson_saradc.c regval = 0; regval 886 drivers/iio/adc/meson_saradc.c regval); regval 931 drivers/iio/adc/meson_saradc.c u32 regval; regval 950 drivers/iio/adc/meson_saradc.c regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1); regval 952 drivers/iio/adc/meson_saradc.c MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval); regval 1015 drivers/iio/adc/meson_saradc.c u32 regval; regval 1017 drivers/iio/adc/meson_saradc.c regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); regval 1018 drivers/iio/adc/meson_saradc.c cnt = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval); regval 1019 drivers/iio/adc/meson_saradc.c threshold = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval); regval 689 drivers/iio/adc/twl4030-madc.c u8 regval; regval 692 drivers/iio/adc/twl4030-madc.c ®val, TWL4030_BCI_BCICTL1); regval 701 drivers/iio/adc/twl4030-madc.c regval |= regmask; regval 703 drivers/iio/adc/twl4030-madc.c regval &= ~regmask; regval 706 drivers/iio/adc/twl4030-madc.c regval, TWL4030_BCI_BCICTL1); regval 724 drivers/iio/adc/twl4030-madc.c u8 regval; regval 728 drivers/iio/adc/twl4030-madc.c ®val, TWL4030_MADC_CTRL1); regval 735 drivers/iio/adc/twl4030-madc.c regval |= TWL4030_MADC_MADCON; regval 737 drivers/iio/adc/twl4030-madc.c regval &= ~TWL4030_MADC_MADCON; regval 738 drivers/iio/adc/twl4030-madc.c ret = twl_i2c_write_u8(TWL4030_MODULE_MADC, regval, TWL4030_MADC_CTRL1); regval 757 drivers/iio/adc/twl4030-madc.c u8 regval; regval 806 drivers/iio/adc/twl4030-madc.c ®val, TWL4030_BCI_BCICTL1); regval 812 drivers/iio/adc/twl4030-madc.c regval |= TWL4030_BCI_MESBAT; regval 814 drivers/iio/adc/twl4030-madc.c regval, TWL4030_BCI_BCICTL1); regval 822 drivers/iio/adc/twl4030-madc.c ret = twl_i2c_read_u8(TWL4030_MODULE_INTBR, ®val, TWL4030_REG_GPBR1); regval 830 drivers/iio/adc/twl4030-madc.c if (!(regval & TWL4030_GPBR1_MADC_HFCLK_EN)) { regval 832 drivers/iio/adc/twl4030-madc.c regval |= TWL4030_GPBR1_MADC_HFCLK_EN; regval 833 drivers/iio/adc/twl4030-madc.c ret = twl_i2c_write_u8(TWL4030_MODULE_INTBR, regval, regval 857 drivers/iio/adc/twl4030-madc.c ret = twl_i2c_read_u8(TWL_MODULE_USB, ®val, regval 864 drivers/iio/adc/twl4030-madc.c regval |= TWL4030_USB_SEL_MADC_MCPC; regval 865 drivers/iio/adc/twl4030-madc.c ret = twl_i2c_write_u8(TWL_MODULE_USB, regval, regval 229 drivers/iio/dac/ad5758.c int regval; regval 231 drivers/iio/dac/ad5758.c regval = ad5758_spi_reg_read(st, addr); regval 232 drivers/iio/dac/ad5758.c if (regval < 0) regval 233 drivers/iio/dac/ad5758.c return regval; regval 235 drivers/iio/dac/ad5758.c regval &= ~mask; regval 236 drivers/iio/dac/ad5758.c regval |= val; regval 238 drivers/iio/dac/ad5758.c return ad5758_spi_reg_write(st, addr, regval); regval 771 drivers/iio/dac/ad5758.c int regval, ret; regval 798 drivers/iio/dac/ad5758.c regval = ad5758_spi_reg_read(st, AD5758_DIGITAL_DIAG_RESULTS); regval 799 drivers/iio/dac/ad5758.c if (regval < 0) regval 800 drivers/iio/dac/ad5758.c return regval; regval 803 drivers/iio/dac/ad5758.c ret = ad5758_spi_reg_write(st, AD5758_DIGITAL_DIAG_RESULTS, regval); regval 39 drivers/iio/dummy/iio_simple_dummy.c int regval; /* what would be written to hardware */ regval 90 drivers/iio/gyro/itg3200_core.c u8 regval; regval 109 drivers/iio/gyro/itg3200_core.c ret = itg3200_read_reg_8(indio_dev, ITG3200_REG_DLPF, ®val); regval 113 drivers/iio/gyro/itg3200_core.c *val = (regval & ITG3200_DLPF_CFG_MASK) ? 1000 : 8000; regval 117 drivers/iio/gyro/itg3200_core.c ®val); regval 121 drivers/iio/gyro/itg3200_core.c *val /= regval + 1; regval 975 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c unsigned int regval; regval 982 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_read(st->map, INV_MPU6050_REG_WHOAMI, ®val); regval 985 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c if (regval != st->hw->whoami) { regval 988 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c if (regval == hw_info[i].whoami) { regval 992 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c regval, hw_info[i].name, regval 1000 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c regval, st->hw->whoami, st->hw->name); regval 74 drivers/iio/light/bh1750.c u8 regval; regval 88 drivers/iio/light/bh1750.c regval = (val & chip_info->int_time_high_mask) >> 5; regval 90 drivers/iio/light/bh1750.c BH1750_CHANGE_INT_TIME_H_BIT | regval); regval 94 drivers/iio/light/bh1750.c regval = val & chip_info->int_time_low_mask; regval 96 drivers/iio/light/bh1750.c BH1750_CHANGE_INT_TIME_L_BIT | regval); regval 49 drivers/iio/light/lv0104cs.c u8 regval; regval 131 drivers/iio/light/lv0104cs.c static int lv0104cs_write_reg(struct i2c_client *client, u8 regval) regval 135 drivers/iio/light/lv0104cs.c ret = i2c_master_send(client, (char *)®val, sizeof(regval)); regval 138 drivers/iio/light/lv0104cs.c if (ret != sizeof(regval)) regval 146 drivers/iio/light/lv0104cs.c __be16 regval; regval 149 drivers/iio/light/lv0104cs.c ret = i2c_master_recv(client, (char *)®val, sizeof(regval)); regval 152 drivers/iio/light/lv0104cs.c if (ret != sizeof(regval)) regval 155 drivers/iio/light/lv0104cs.c *adc_output = be16_to_cpu(regval); regval 163 drivers/iio/light/lv0104cs.c u8 regval = LV0104CS_REGVAL_MEASURE; regval 167 drivers/iio/light/lv0104cs.c regval |= lv0104cs_scales[lv0104cs->scale].regval; regval 168 drivers/iio/light/lv0104cs.c regval |= lv0104cs_int_times[lv0104cs->int_time].regval; regval 169 drivers/iio/light/lv0104cs.c ret = lv0104cs_write_reg(lv0104cs->client, regval); regval 309 drivers/iio/light/lv0104cs.c lv0104cs_calibscales[index].regval); regval 500 drivers/iio/light/lv0104cs.c lv0104cs_calibscales[LV0104CS_CALIBSCALE_UNITY].regval); regval 202 drivers/iio/light/max44000.c u16 regval; regval 214 drivers/iio/light/max44000.c regval = be16_to_cpu(val); regval 225 drivers/iio/light/max44000.c if (regval & MAX44000_ALSDATA_OVERFLOW) regval 228 drivers/iio/light/max44000.c return regval << MAX44000_ALSTIM_SHIFT(alstim); regval 244 drivers/iio/light/max44000.c unsigned int regval; regval 247 drivers/iio/light/max44000.c ret = regmap_read(data->regmap, MAX44000_REG_CFG_TX, ®val); regval 250 drivers/iio/light/max44000.c regval &= MAX44000_LED_CURRENT_MASK; regval 251 drivers/iio/light/max44000.c if (regval >= 8) regval 252 drivers/iio/light/max44000.c regval -= 4; regval 253 drivers/iio/light/max44000.c return regval; regval 262 drivers/iio/light/max44000.c unsigned int regval; regval 279 drivers/iio/light/max44000.c ret = regmap_read(data->regmap, MAX44000_REG_PRX_DATA, ®val); regval 283 drivers/iio/light/max44000.c *val = regval; regval 493 drivers/iio/light/max44000.c unsigned int regval; regval 504 drivers/iio/light/max44000.c ret = regmap_read(data->regmap, MAX44000_REG_PRX_DATA, ®val); regval 507 drivers/iio/light/max44000.c buf[index] = regval; regval 595 drivers/iio/light/si1145.c static int si1145_scale_from_adcgain(int regval) regval 597 drivers/iio/light/si1145.c return 128 >> regval; regval 457 drivers/iio/magnetometer/ak8975.c u8 regval; regval 460 drivers/iio/magnetometer/ak8975.c regval = (data->cntl_cache & ~data->def->ctrl_masks[CNTL_MODE]) | regval 463 drivers/iio/magnetometer/ak8975.c data->def->ctrl_regs[CNTL], regval); regval 467 drivers/iio/magnetometer/ak8975.c data->cntl_cache = regval; regval 93 drivers/iio/magnetometer/bmc150_magn.c #define BMC150_MAGN_REGVAL_TO_REPXY(regval) (((regval) * 2) + 1) regval 94 drivers/iio/magnetometer/bmc150_magn.c #define BMC150_MAGN_REGVAL_TO_REPZ(regval) ((regval) + 1) regval 265 drivers/iio/proximity/srf08.c u8 regval; regval 273 drivers/iio/proximity/srf08.c regval = ret; regval 277 drivers/iio/proximity/srf08.c ret = i2c_smbus_write_byte_data(client, SRF08_WRITE_RANGE, regval); regval 351 drivers/iio/proximity/srf08.c u8 regval; regval 358 drivers/iio/proximity/srf08.c regval = i; regval 367 drivers/iio/proximity/srf08.c ret = i2c_smbus_write_byte_data(client, SRF08_WRITE_MAX_GAIN, regval); regval 269 drivers/iio/proximity/sx9500.c __be16 regval; regval 275 drivers/iio/proximity/sx9500.c ret = regmap_bulk_read(data->regmap, SX9500_REG_USE_MSB, ®val, 2); regval 279 drivers/iio/proximity/sx9500.c *val = be16_to_cpu(regval); regval 363 drivers/iio/proximity/sx9500.c unsigned int regval; regval 366 drivers/iio/proximity/sx9500.c ret = regmap_read(data->regmap, SX9500_REG_PROX_CTRL0, ®val); regval 372 drivers/iio/proximity/sx9500.c regval = (regval & SX9500_SCAN_PERIOD_MASK) >> SX9500_SCAN_PERIOD_SHIFT; regval 373 drivers/iio/proximity/sx9500.c *val = sx9500_samp_freq_table[regval].val; regval 374 drivers/iio/proximity/sx9500.c *val2 = sx9500_samp_freq_table[regval].val2; regval 266 drivers/iommu/mtk_iommu.c u32 int_state, regval, fault_iova, fault_pa; regval 273 drivers/iommu/mtk_iommu.c regval = readl_relaxed(data->base + REG_MMU0_INT_ID); regval 277 drivers/iommu/mtk_iommu.c regval = readl_relaxed(data->base + REG_MMU1_INT_ID); regval 283 drivers/iommu/mtk_iommu.c fault_larb = F_MMU_INT_ID_LARB_ID(regval); regval 284 drivers/iommu/mtk_iommu.c fault_port = F_MMU_INT_ID_PORT_ID(regval); regval 298 drivers/iommu/mtk_iommu.c regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0); regval 299 drivers/iommu/mtk_iommu.c regval |= F_INT_CLR_BIT; regval 300 drivers/iommu/mtk_iommu.c writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); regval 592 drivers/iommu/mtk_iommu.c u32 regval; regval 602 drivers/iommu/mtk_iommu.c regval = F_MMU_PREFETCH_RT_REPLACE_MOD | regval 605 drivers/iommu/mtk_iommu.c regval = F_MMU_TF_PROT_TO_PROGRAM_ADDR; regval 606 drivers/iommu/mtk_iommu.c writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); regval 608 drivers/iommu/mtk_iommu.c regval = F_L2_MULIT_HIT_EN | regval 614 drivers/iommu/mtk_iommu.c writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); regval 616 drivers/iommu/mtk_iommu.c regval = F_INT_TRANSLATION_FAULT | regval 623 drivers/iommu/mtk_iommu.c writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); regval 626 drivers/iommu/mtk_iommu.c regval = (data->protect_base >> 1) | (data->enable_4GB << 31); regval 628 drivers/iommu/mtk_iommu.c regval = lower_32_bits(data->protect_base) | regval 630 drivers/iommu/mtk_iommu.c writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR); regval 637 drivers/iommu/mtk_iommu.c regval = F_MMU_VLD_PA_RNG(7, 4); regval 638 drivers/iommu/mtk_iommu.c writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); regval 164 drivers/iommu/mtk_iommu_v1.c u32 int_state, regval, fault_iova, fault_pa; regval 173 drivers/iommu/mtk_iommu_v1.c regval = readl_relaxed(data->base + REG_MMU_INT_ID); regval 174 drivers/iommu/mtk_iommu_v1.c fault_larb = MT2701_M4U_TF_LARB(regval); regval 175 drivers/iommu/mtk_iommu_v1.c fault_port = MT2701_M4U_TF_PORT(regval); regval 189 drivers/iommu/mtk_iommu_v1.c regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL); regval 190 drivers/iommu/mtk_iommu_v1.c regval |= F_INT_CLR_BIT; regval 191 drivers/iommu/mtk_iommu_v1.c writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); regval 490 drivers/iommu/mtk_iommu_v1.c u32 regval; regval 499 drivers/iommu/mtk_iommu_v1.c regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2); regval 500 drivers/iommu/mtk_iommu_v1.c writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); regval 502 drivers/iommu/mtk_iommu_v1.c regval = F_INT_TRANSLATION_FAULT | regval 510 drivers/iommu/mtk_iommu_v1.c writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); regval 65 drivers/leds/leds-mlxreg.c u32 regval; regval 81 drivers/leds/leds-mlxreg.c ret = regmap_read(led_pdata->regmap, data->reg, ®val); regval 87 drivers/leds/leds-mlxreg.c regval = (regval & data->mask) | nib; regval 89 drivers/leds/leds-mlxreg.c ret = regmap_write(led_pdata->regmap, data->reg, regval); regval 103 drivers/leds/leds-mlxreg.c u32 regval; regval 116 drivers/leds/leds-mlxreg.c err = regmap_read(led_pdata->regmap, data->reg, ®val); regval 124 drivers/leds/leds-mlxreg.c regval = regval & ~data->mask; regval 125 drivers/leds/leds-mlxreg.c regval = (ror32(data->mask, data->bit) == 0xf0) ? ror32(regval, regval 126 drivers/leds/leds-mlxreg.c data->bit) : ror32(regval, data->bit + 4); regval 127 drivers/leds/leds-mlxreg.c if (regval >= led_data->base_color && regval 128 drivers/leds/leds-mlxreg.c regval <= (led_data->base_color + MLXREG_LED_OFFSET_BLINK_6HZ)) regval 191 drivers/leds/leds-mlxreg.c u32 regval; regval 203 drivers/leds/leds-mlxreg.c ®val); regval 208 drivers/leds/leds-mlxreg.c if (!(regval & data->bit)) regval 142 drivers/media/dvb-frontends/cxd2099.c unsigned int regval; regval 147 drivers/media/dvb-frontends/cxd2099.c status = regmap_read(ci->regmap, 1, ®val); regval 148 drivers/media/dvb-frontends/cxd2099.c ci->regs[reg] = regval; regval 2768 drivers/media/dvb-frontends/stv0367.c u32 regval = 0; regval 2772 drivers/media/dvb-frontends/stv0367.c regval += (stv0367_readbits(state, F367CAB_SNR_LO) regval 2777 drivers/media/dvb-frontends/stv0367.c regval /= 10; regval 2779 drivers/media/dvb-frontends/stv0367.c return regval; regval 2786 drivers/media/dvb-frontends/stv0367.c u32 regval = 0, temp = 0; regval 2790 drivers/media/dvb-frontends/stv0367.c regval = stv0367cab_snr_readreg(fe, 1); regval 2792 drivers/media/dvb-frontends/stv0367.c if (regval != 0) { regval 2795 drivers/media/dvb-frontends/stv0367.c temp /= regval; regval 3049 drivers/media/dvb-frontends/stv0367.c u32 regval, tmpval, snrval = 0; regval 3057 drivers/media/dvb-frontends/stv0367.c regval = stv0367cab_snr_readreg(fe, 0); regval 3060 drivers/media/dvb-frontends/stv0367.c if (!regval) { regval 3065 drivers/media/dvb-frontends/stv0367.c tmpval = (cab_pwr * 320) / regval; regval 610 drivers/media/dvb-frontends/stv0900_core.c if (INRANGE(lookup->table[imin].regval, agc_gain, regval 611 drivers/media/dvb-frontends/stv0900_core.c lookup->table[imax].regval)) { regval 615 drivers/media/dvb-frontends/stv0900_core.c if (INRANGE(lookup->table[imin].regval, regval 617 drivers/media/dvb-frontends/stv0900_core.c lookup->table[i].regval)) regval 623 drivers/media/dvb-frontends/stv0900_core.c rf_lvl = (s32)agc_gain - lookup->table[imin].regval; regval 626 drivers/media/dvb-frontends/stv0900_core.c rf_lvl /= (lookup->table[imax].regval - regval 627 drivers/media/dvb-frontends/stv0900_core.c lookup->table[imin].regval); regval 629 drivers/media/dvb-frontends/stv0900_core.c } else if (agc_gain > lookup->table[0].regval) regval 631 drivers/media/dvb-frontends/stv0900_core.c else if (agc_gain < lookup->table[lookup->size-1].regval) regval 666 drivers/media/dvb-frontends/stv0900_core.c regval, regval 685 drivers/media/dvb-frontends/stv0900_core.c regval = 0; regval 688 drivers/media/dvb-frontends/stv0900_core.c regval += MAKEWORD(stv0900_get_bits(intp, regval 695 drivers/media/dvb-frontends/stv0900_core.c regval /= 16; regval 698 drivers/media/dvb-frontends/stv0900_core.c if (INRANGE(lookup->table[imin].regval, regval 699 drivers/media/dvb-frontends/stv0900_core.c regval, regval 700 drivers/media/dvb-frontends/stv0900_core.c lookup->table[imax].regval)) { regval 703 drivers/media/dvb-frontends/stv0900_core.c if (INRANGE(lookup->table[imin].regval, regval 704 drivers/media/dvb-frontends/stv0900_core.c regval, regval 705 drivers/media/dvb-frontends/stv0900_core.c lookup->table[i].regval)) regval 711 drivers/media/dvb-frontends/stv0900_core.c c_n = ((regval - lookup->table[imin].regval) regval 714 drivers/media/dvb-frontends/stv0900_core.c / (lookup->table[imax].regval regval 715 drivers/media/dvb-frontends/stv0900_core.c - lookup->table[imin].regval)) regval 717 drivers/media/dvb-frontends/stv0900_core.c } else if (regval < lookup->table[imin].regval) regval 48 drivers/media/dvb-frontends/stv0900_priv.h s32 regval;/* binary value */ regval 357 drivers/media/dvb-frontends/stv6111.c u8 regval; regval 359 drivers/media/dvb-frontends/stv6111.c status = read_reg(state, 9, ®val); regval 363 drivers/media/dvb-frontends/stv6111.c if ((regval & mask) == 0) regval 485 drivers/media/i2c/adv748x/adv748x-core.c u8 regval = 0; regval 515 drivers/media/i2c/adv748x/adv748x-core.c regval |= ADV748X_IO_10_CSI4_EN; regval 517 drivers/media/i2c/adv748x/adv748x-core.c regval |= ADV748X_IO_10_CSI1_EN; regval 518 drivers/media/i2c/adv748x/adv748x-core.c io_write(state, ADV748X_IO_10, regval); regval 318 drivers/media/i2c/max2175.c u32 regval; regval 321 drivers/media/i2c/max2175.c ret = regmap_read(ctx->regmap, idx, ®val); regval 325 drivers/media/i2c/max2175.c *val = regval; regval 80 drivers/media/i2c/ov2685.c const struct regval *reg_list; regval 106 drivers/media/i2c/ov2685.c static struct regval ov2685_1600x1200_regs[] = { regval 274 drivers/media/i2c/ov2685.c const struct regval *regs) regval 92 drivers/media/i2c/ov5695.c const struct regval *reg_list; regval 127 drivers/media/i2c/ov5695.c static const struct regval ov5695_global_regs[] = { regval 302 drivers/media/i2c/ov5695.c static const struct regval ov5695_2592x1944_regs[] = { regval 344 drivers/media/i2c/ov5695.c static const struct regval ov5695_1920x1080_regs[] = { regval 386 drivers/media/i2c/ov5695.c static const struct regval ov5695_1296x972_regs[] = { regval 569 drivers/media/i2c/ov5695.c static const struct regval ov5695_1280x720_regs[] = { regval 611 drivers/media/i2c/ov5695.c static const struct regval ov5695_640x480_regs[] = { regval 734 drivers/media/i2c/ov5695.c const struct regval *regs) regval 275 drivers/media/pci/cx23885/cx23885-417.c u32 regval; regval 280 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_SPD_CTL(MC417_SPD_CTL_FAST) | regval 283 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_CTL, regval); regval 286 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRDY; regval 287 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_OEN, regval); regval 290 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIWR | MC417_MIRD | MC417_MICS; regval 291 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 311 drivers/media/pci/cx23885/cx23885-417.c u32 regval; regval 319 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0 | regval 321 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 324 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 325 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 328 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1 | regval 330 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 331 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 332 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 335 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2 | regval 337 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 338 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 339 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 342 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3 | regval 344 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 345 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 346 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 349 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 | regval 351 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 352 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 353 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 356 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 | regval 358 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 359 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 360 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 363 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE | regval 365 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 366 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 367 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 376 drivers/media/pci/cx23885/cx23885-417.c u32 regval; regval 386 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 | regval 388 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 389 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 390 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 393 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 | regval 395 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 396 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 397 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 400 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE | regval 402 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 403 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 404 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 413 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0; regval 414 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 421 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0; regval 422 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 429 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; regval 430 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 433 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1; regval 434 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 435 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1; regval 436 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 439 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; regval 440 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 443 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2; regval 444 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 445 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2; regval 446 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 449 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; regval 450 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 453 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3; regval 454 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 455 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3; regval 456 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 459 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; regval 460 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 469 drivers/media/pci/cx23885/cx23885-417.c u32 regval; regval 477 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0 | regval 479 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 482 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 483 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 486 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1 | regval 488 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 489 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 490 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 493 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2 | regval 495 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 496 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 497 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 500 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3 | regval 502 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 503 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 504 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 507 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 | regval 509 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 510 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 511 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 514 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 | regval 516 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 517 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 518 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 521 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 | regval 523 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 524 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 525 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 534 drivers/media/pci/cx23885/cx23885-417.c u32 regval; regval 544 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 | regval 546 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 547 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 548 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 551 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 | regval 553 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 554 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 555 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 558 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 | regval 560 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 561 drivers/media/pci/cx23885/cx23885-417.c regval |= MC417_MICS | MC417_MIWR; regval 562 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 571 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3; regval 572 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 575 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3; regval 576 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 583 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; regval 584 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 587 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2; regval 588 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 589 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2; regval 590 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 593 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; regval 594 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 597 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1; regval 598 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 599 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1; regval 600 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 603 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; regval 604 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 607 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0; regval 608 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 609 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0; regval 610 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 613 drivers/media/pci/cx23885/cx23885-417.c regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY; regval 614 drivers/media/pci/cx23885/cx23885-417.c cx_write(MC417_RWD, regval); regval 1644 drivers/media/platform/ti-vpe/cal.c u32 regval = 0; regval 1666 drivers/media/platform/ti-vpe/cal.c of_property_read_u32(port, "reg", ®val); regval 1668 drivers/media/platform/ti-vpe/cal.c index, inst, regval); regval 1669 drivers/media/platform/ti-vpe/cal.c if ((regval == inst) && (index == inst)) { regval 636 drivers/media/tuners/xc5000.c u16 regval; regval 678 drivers/media/tuners/xc5000.c if (!xc5000_readreg(priv, priv->pll_register_no, ®val)) regval 679 drivers/media/tuners/xc5000.c dprintk(1, "*** PLL lock status = 0x%04x\n", regval); regval 512 drivers/media/usb/em28xx/em28xx-input.c int regval; regval 519 drivers/media/usb/em28xx/em28xx-input.c regval = em28xx_read_reg(dev, dev->button_polling_addresses[i]); regval 520 drivers/media/usb/em28xx/em28xx-input.c if (regval < 0) regval 536 drivers/media/usb/em28xx/em28xx-input.c is_pressed = regval & button->mask; regval 546 drivers/media/usb/em28xx/em28xx-input.c (~regval & button->mask) regval 547 drivers/media/usb/em28xx/em28xx-input.c | (regval & ~button->mask)); regval 578 drivers/media/usb/em28xx/em28xx-input.c dev->button_polling_last_values[i] = regval; regval 122 drivers/media/usb/stk1160/stk1160-core.c static const struct regval ctl[] = { regval 71 drivers/media/usb/stk1160/stk1160-v4l.c static struct regval std525[] = { regval 90 drivers/media/usb/stk1160/stk1160-v4l.c static struct regval std625[] = { regval 272 drivers/media/usb/stkwebcam/stk-sensor.c struct regval *rv) regval 300 drivers/media/usb/stkwebcam/stk-sensor.c static struct regval ov_initvals[] = { regval 390 drivers/media/usb/stkwebcam/stk-sensor.c static struct regval ov_fmt_uyvy[] = { regval 403 drivers/media/usb/stkwebcam/stk-sensor.c static struct regval ov_fmt_yuyv[] = { regval 417 drivers/media/usb/stkwebcam/stk-sensor.c static struct regval ov_fmt_rgbr[] = { regval 434 drivers/media/usb/stkwebcam/stk-sensor.c static struct regval ov_fmt_rgbp[] = { regval 451 drivers/media/usb/stkwebcam/stk-sensor.c static struct regval ov_fmt_bayer[] = { regval 499 drivers/media/usb/stkwebcam/stk-sensor.c struct regval *rv; regval 246 drivers/media/usb/stkwebcam/stk-webcam.c static struct regval stk1125_initvals[] = { regval 278 drivers/media/usb/stkwebcam/stk-webcam.c struct regval *rv; regval 1055 drivers/memory/omap-gpmc.c u32 regval; regval 1059 drivers/memory/omap-gpmc.c regval = gpmc_read_reg(GPMC_CONFIG); regval 1061 drivers/memory/omap-gpmc.c regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ regval 1063 drivers/memory/omap-gpmc.c regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ regval 1064 drivers/memory/omap-gpmc.c gpmc_write_reg(GPMC_CONFIG, regval); regval 1262 drivers/memory/omap-gpmc.c u32 regval; regval 1268 drivers/memory/omap-gpmc.c regval = gpmc_read_reg(GPMC_IRQENABLE); regval 1270 drivers/memory/omap-gpmc.c regval |= BIT(hwirq); regval 1272 drivers/memory/omap-gpmc.c regval &= ~BIT(hwirq); regval 1273 drivers/memory/omap-gpmc.c gpmc_write_reg(GPMC_IRQENABLE, regval); regval 1300 drivers/memory/omap-gpmc.c u32 regval; regval 1309 drivers/memory/omap-gpmc.c regval = gpmc_read_reg(GPMC_CONFIG); regval 1311 drivers/memory/omap-gpmc.c regval &= ~BIT(hwirq); regval 1313 drivers/memory/omap-gpmc.c regval |= BIT(hwirq); regval 1315 drivers/memory/omap-gpmc.c gpmc_write_reg(GPMC_CONFIG, regval); regval 1373 drivers/memory/omap-gpmc.c u32 regval, regvalx; regval 1376 drivers/memory/omap-gpmc.c regval = gpmc_read_reg(GPMC_IRQSTATUS); regval 1377 drivers/memory/omap-gpmc.c regvalx = regval; regval 1379 drivers/memory/omap-gpmc.c if (!regval) regval 1399 drivers/memory/omap-gpmc.c gpmc_write_reg(GPMC_IRQSTATUS, regval); regval 1406 drivers/memory/omap-gpmc.c u32 regval; regval 1413 drivers/memory/omap-gpmc.c regval = gpmc_read_reg(GPMC_IRQSTATUS); regval 1414 drivers/memory/omap-gpmc.c gpmc_write_reg(GPMC_IRQSTATUS, regval); regval 73 drivers/mfd/ab3100-core.c u8 reg, u8 regval) regval 75 drivers/mfd/ab3100-core.c u8 regandval[2] = {reg, regval}; regval 122 drivers/mfd/ab3100-core.c u8 reg, u8 regval) regval 124 drivers/mfd/ab3100-core.c u8 regandval[2] = {reg, regval}; regval 152 drivers/mfd/ab3100-core.c u8 reg, u8 *regval) regval 184 drivers/mfd/ab3100-core.c err = i2c_master_recv(ab3100->i2c_client, regval, 1); regval 241 drivers/mfd/asic3.c int regval; regval 245 drivers/mfd/asic3.c regval = asic3_read_register(asic, regval 249 drivers/mfd/asic3.c regval &= ~(ASIC3_INTMASK_MASK0 << regval 255 drivers/mfd/asic3.c regval); regval 278 drivers/mfd/asic3.c int regval; regval 282 drivers/mfd/asic3.c regval = asic3_read_register(asic, regval 286 drivers/mfd/asic3.c regval |= (ASIC3_INTMASK_MASK0 << regval 292 drivers/mfd/asic3.c regval); regval 35 drivers/mfd/tps6105x.c unsigned int regval; regval 37 drivers/mfd/tps6105x.c ret = regmap_read(tps6105x->regmap, TPS6105X_REG_0, ®val); regval 40 drivers/mfd/tps6105x.c switch (regval >> TPS6105X_REG0_MODE_SHIFT) { regval 998 drivers/mmc/host/meson-gx-mmc.c u32 regval; regval 1000 drivers/mmc/host/meson-gx-mmc.c regval = readl(host->regs + SD_EMMC_STATUS); regval 1003 drivers/mmc/host/meson-gx-mmc.c return !(FIELD_GET(STATUS_DATI, regval) & 0xf); regval 129 drivers/mmc/host/meson-mx-sdio.c u32 regval; regval 131 drivers/mmc/host/meson-mx-sdio.c regval = readl(host->base + reg); regval 132 drivers/mmc/host/meson-mx-sdio.c regval &= ~mask; regval 133 drivers/mmc/host/meson-mx-sdio.c regval |= (val & mask); regval 135 drivers/mmc/host/meson-mx-sdio.c writel(regval, host->base + reg); regval 536 drivers/mmc/host/omap_hsmmc.c unsigned long regval; regval 544 drivers/mmc/host/omap_hsmmc.c regval = OMAP_HSMMC_READ(host->base, SYSCTL); regval 545 drivers/mmc/host/omap_hsmmc.c regval = regval & ~(CLKD_MASK | DTO_MASK); regval 547 drivers/mmc/host/omap_hsmmc.c regval = regval | (clkdiv << 6) | (DTO << 16); regval 548 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); regval 571 drivers/mmc/host/omap_hsmmc.c regval = OMAP_HSMMC_READ(host->base, HCTL); regval 573 drivers/mmc/host/omap_hsmmc.c regval |= HSPE; regval 575 drivers/mmc/host/omap_hsmmc.c regval &= ~HSPE; regval 577 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, HCTL, regval); regval 469 drivers/net/ethernet/amd/sunlance.c u16 regval = 0; regval 480 drivers/net/ethernet/amd/sunlance.c regval = sbus_readw(lp->lregs + RDP); regval 482 drivers/net/ethernet/amd/sunlance.c if (regval & (LE_C0_ERR | LE_C0_IDON)) regval 486 drivers/net/ethernet/amd/sunlance.c if (i == 100 || (regval & LE_C0_ERR)) { regval 488 drivers/net/ethernet/amd/sunlance.c i, regval); regval 929 drivers/net/ethernet/amd/sunlance.c u32 regval = lp->init_block_dvma & 0xff000000; regval 931 drivers/net/ethernet/amd/sunlance.c sbus_writel(regval, lp->dregs + DMA_TEST); regval 427 drivers/net/ethernet/broadcom/sb1250-mac.c int regval; regval 475 drivers/net/ethernet/broadcom/sb1250-mac.c regval = 0; regval 478 drivers/net/ethernet/broadcom/sb1250-mac.c regval <<= 1; regval 482 drivers/net/ethernet/broadcom/sb1250-mac.c regval |= 1; regval 494 drivers/net/ethernet/broadcom/sb1250-mac.c return regval; regval 515 drivers/net/ethernet/broadcom/sb1250-mac.c u16 regval) regval 528 drivers/net/ethernet/broadcom/sb1250-mac.c sbmac_mii_senddata(sbm_mdio, regval, 16); regval 443 drivers/net/ethernet/cadence/macb_ptp.c u32 regval; regval 489 drivers/net/ethernet/cadence/macb_ptp.c regval = macb_readl(bp, NCR); regval 490 drivers/net/ethernet/cadence/macb_ptp.c macb_writel(bp, NCR, (regval | MACB_BIT(SRTSM))); regval 42 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c u32 regval = 0; regval 76 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, ®val); regval 79 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c CVM_CAST64(CN23XX_CONFIG_PCIE_DEVCTL), CVM_CAST64(regval)); regval 241 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c u32 regval; regval 244 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, ®val); regval 245 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c if (regval & CN23XX_CONFIG_PCIE_DEVCTL_MASK) { regval 258 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c regval, uncorrectable_err_mask, regval 262 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c regval |= 0xf; /* Enable Link error reporting */ regval 266 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c pci_write_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, regval); regval 3564 drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h __be32 regval; regval 1998 drivers/net/ethernet/dec/tulip/de4x5.c u_char irq, regval; regval 2029 drivers/net/ethernet/dec/tulip/de4x5.c regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT); regval 2048 drivers/net/ethernet/dec/tulip/de4x5.c outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0); regval 2050 drivers/net/ethernet/dec/tulip/de4x5.c irq = de4x5_irq[(regval >> 1) & 0x03]; regval 57 drivers/net/ethernet/intel/e1000e/ich8lan.c u16 regval; regval 70 drivers/net/ethernet/intel/e1000e/ich8lan.c u16 regval; regval 81 drivers/net/ethernet/intel/e1000e/ich8lan.c u16 regval; regval 94 drivers/net/ethernet/intel/e1000e/ich8lan.c u32 regval; regval 3374 drivers/net/ethernet/intel/e1000e/ich8lan.c hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); regval 3386 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); regval 3388 drivers/net/ethernet/intel/e1000e/ich8lan.c ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); regval 3405 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); regval 3407 drivers/net/ethernet/intel/e1000e/ich8lan.c ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); regval 3416 drivers/net/ethernet/intel/e1000e/ich8lan.c hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); regval 3430 drivers/net/ethernet/intel/e1000e/ich8lan.c hsfsts.regval & 0xFFFF); regval 3432 drivers/net/ethernet/intel/e1000e/ich8lan.c ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); regval 3456 drivers/net/ethernet/intel/e1000e/ich8lan.c hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; regval 3458 drivers/net/ethernet/intel/e1000e/ich8lan.c hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); regval 3462 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); regval 3464 drivers/net/ethernet/intel/e1000e/ich8lan.c ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); regval 3468 drivers/net/ethernet/intel/e1000e/ich8lan.c hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); regval 3577 drivers/net/ethernet/intel/e1000e/ich8lan.c hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); regval 3581 drivers/net/ethernet/intel/e1000e/ich8lan.c ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); regval 3607 drivers/net/ethernet/intel/e1000e/ich8lan.c hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); regval 3653 drivers/net/ethernet/intel/e1000e/ich8lan.c hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; regval 3661 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16); regval 3682 drivers/net/ethernet/intel/e1000e/ich8lan.c hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); regval 4121 drivers/net/ethernet/intel/e1000e/ich8lan.c pr0.regval = er32flash(ICH_FLASH_PR0); regval 4125 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32flash(ICH_FLASH_PR0, pr0.regval); regval 4132 drivers/net/ethernet/intel/e1000e/ich8lan.c hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); regval 4134 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); regval 4179 drivers/net/ethernet/intel/e1000e/ich8lan.c hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; regval 4181 drivers/net/ethernet/intel/e1000e/ich8lan.c hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); regval 4191 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); regval 4193 drivers/net/ethernet/intel/e1000e/ich8lan.c ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); regval 4218 drivers/net/ethernet/intel/e1000e/ich8lan.c hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); regval 4265 drivers/net/ethernet/intel/e1000e/ich8lan.c hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) regval 4268 drivers/net/ethernet/intel/e1000e/ich8lan.c hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); regval 4278 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); regval 4280 drivers/net/ethernet/intel/e1000e/ich8lan.c ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); regval 4301 drivers/net/ethernet/intel/e1000e/ich8lan.c hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); regval 4417 drivers/net/ethernet/intel/e1000e/ich8lan.c hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); regval 4470 drivers/net/ethernet/intel/e1000e/ich8lan.c hsflctl.regval = regval 4473 drivers/net/ethernet/intel/e1000e/ich8lan.c hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); regval 4478 drivers/net/ethernet/intel/e1000e/ich8lan.c hsflctl.regval << 16); regval 4480 drivers/net/ethernet/intel/e1000e/ich8lan.c ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); regval 4497 drivers/net/ethernet/intel/e1000e/ich8lan.c hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); regval 3595 drivers/net/ethernet/intel/e1000e/netdev.c u32 regval; regval 3692 drivers/net/ethernet/intel/e1000e/netdev.c regval = er32(TSYNCTXCTL); regval 3693 drivers/net/ethernet/intel/e1000e/netdev.c regval &= ~E1000_TSYNCTXCTL_ENABLED; regval 3694 drivers/net/ethernet/intel/e1000e/netdev.c regval |= tsync_tx_ctl; regval 3695 drivers/net/ethernet/intel/e1000e/netdev.c ew32(TSYNCTXCTL, regval); regval 3697 drivers/net/ethernet/intel/e1000e/netdev.c (regval & E1000_TSYNCTXCTL_ENABLED)) { regval 3703 drivers/net/ethernet/intel/e1000e/netdev.c regval = er32(TSYNCRXCTL); regval 3704 drivers/net/ethernet/intel/e1000e/netdev.c regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); regval 3705 drivers/net/ethernet/intel/e1000e/netdev.c regval |= tsync_rx_ctl; regval 3706 drivers/net/ethernet/intel/e1000e/netdev.c ew32(TSYNCRXCTL, regval); regval 3709 drivers/net/ethernet/intel/e1000e/netdev.c (regval & (E1000_TSYNCRXCTL_ENABLED | regval 543 drivers/net/ethernet/intel/i40e/i40e_ptp.c u32 tsyntype, regval; regval 621 drivers/net/ethernet/intel/i40e/i40e_ptp.c regval = rd32(hw, I40E_PRTTSYN_CTL0); regval 623 drivers/net/ethernet/intel/i40e/i40e_ptp.c regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; regval 625 drivers/net/ethernet/intel/i40e/i40e_ptp.c regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; regval 626 drivers/net/ethernet/intel/i40e/i40e_ptp.c wr32(hw, I40E_PRTTSYN_CTL0, regval); regval 628 drivers/net/ethernet/intel/i40e/i40e_ptp.c regval = rd32(hw, I40E_PFINT_ICR0_ENA); regval 630 drivers/net/ethernet/intel/i40e/i40e_ptp.c regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; regval 632 drivers/net/ethernet/intel/i40e/i40e_ptp.c regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; regval 633 drivers/net/ethernet/intel/i40e/i40e_ptp.c wr32(hw, I40E_PFINT_ICR0_ENA, regval); regval 641 drivers/net/ethernet/intel/i40e/i40e_ptp.c regval = rd32(hw, I40E_PRTTSYN_CTL1); regval 643 drivers/net/ethernet/intel/i40e/i40e_ptp.c regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK; regval 645 drivers/net/ethernet/intel/i40e/i40e_ptp.c regval |= tsyntype; regval 646 drivers/net/ethernet/intel/i40e/i40e_ptp.c wr32(hw, I40E_PRTTSYN_CTL1, regval); regval 820 drivers/net/ethernet/intel/i40e/i40e_ptp.c u32 regval; regval 827 drivers/net/ethernet/intel/i40e/i40e_ptp.c regval = rd32(hw, I40E_PRTTSYN_CTL0); regval 828 drivers/net/ethernet/intel/i40e/i40e_ptp.c regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK; regval 829 drivers/net/ethernet/intel/i40e/i40e_ptp.c wr32(hw, I40E_PRTTSYN_CTL0, regval); regval 830 drivers/net/ethernet/intel/i40e/i40e_ptp.c regval = rd32(hw, I40E_PRTTSYN_CTL1); regval 831 drivers/net/ethernet/intel/i40e/i40e_ptp.c regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK; regval 832 drivers/net/ethernet/intel/i40e/i40e_ptp.c wr32(hw, I40E_PRTTSYN_CTL1, regval); regval 20 drivers/net/ethernet/intel/ice/ice_lib.c u32 regval; regval 73 drivers/net/ethernet/intel/ice/ice_lib.c regval = rd32(hw, QRXFLXP_CNTXT(pf_q)); regval 74 drivers/net/ethernet/intel/ice/ice_lib.c regval |= (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) & regval 81 drivers/net/ethernet/intel/ice/ice_lib.c regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) & regval 84 drivers/net/ethernet/intel/ice/ice_lib.c wr32(hw, QRXFLXP_CNTXT(pf_q), regval); regval 1848 drivers/net/ethernet/intel/ice/ice_lib.c u32 regval = rd32(hw, GLINT_CTL); regval 1851 drivers/net/ethernet/intel/ice/ice_lib.c if (!(regval & GLINT_CTL_DIS_AUTOMASK_M) && regval 1852 drivers/net/ethernet/intel/ice/ice_lib.c (((regval & GLINT_CTL_ITR_GRAN_200_M) >> regval 1854 drivers/net/ethernet/intel/ice/ice_lib.c (((regval & GLINT_CTL_ITR_GRAN_100_M) >> regval 1856 drivers/net/ethernet/intel/ice/ice_lib.c (((regval & GLINT_CTL_ITR_GRAN_50_M) >> regval 1858 drivers/net/ethernet/intel/ice/ice_lib.c (((regval & GLINT_CTL_ITR_GRAN_25_M) >> regval 1862 drivers/net/ethernet/intel/ice/ice_lib.c regval = ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_200_S) & regval 1870 drivers/net/ethernet/intel/ice/ice_lib.c wr32(hw, GLINT_CTL, regval); regval 1487 drivers/net/ethernet/intel/igb/igb_main.c u32 regval = rd32(E1000_EIAM); regval 1489 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); regval 1491 drivers/net/ethernet/intel/igb/igb_main.c regval = rd32(E1000_EIAC); regval 1492 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); regval 1518 drivers/net/ethernet/intel/igb/igb_main.c u32 regval = rd32(E1000_EIAC); regval 1520 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_EIAC, regval | adapter->eims_enable_mask); regval 1521 drivers/net/ethernet/intel/igb/igb_main.c regval = rd32(E1000_EIAM); regval 1522 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_EIAM, regval | adapter->eims_enable_mask); regval 821 drivers/net/ethernet/intel/igb/igb_ptp.c u64 regval; regval 824 drivers/net/ethernet/intel/igb/igb_ptp.c regval = rd32(E1000_TXSTMPL); regval 825 drivers/net/ethernet/intel/igb/igb_ptp.c regval |= (u64)rd32(E1000_TXSTMPH) << 32; regval 827 drivers/net/ethernet/intel/igb/igb_ptp.c igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); regval 872 drivers/net/ethernet/intel/igb/igb_ptp.c __le64 *regval = (__le64 *)va; regval 881 drivers/net/ethernet/intel/igb/igb_ptp.c le64_to_cpu(regval[1])); regval 914 drivers/net/ethernet/intel/igb/igb_ptp.c u64 regval; regval 930 drivers/net/ethernet/intel/igb/igb_ptp.c regval = rd32(E1000_RXSTMPL); regval 931 drivers/net/ethernet/intel/igb/igb_ptp.c regval |= (u64)rd32(E1000_RXSTMPH) << 32; regval 933 drivers/net/ethernet/intel/igb/igb_ptp.c igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); regval 1002 drivers/net/ethernet/intel/igb/igb_ptp.c u32 regval; regval 1081 drivers/net/ethernet/intel/igb/igb_ptp.c regval = rd32(E1000_RXPBS); regval 1082 drivers/net/ethernet/intel/igb/igb_ptp.c regval |= E1000_RXPBS_CFG_TS_EN; regval 1083 drivers/net/ethernet/intel/igb/igb_ptp.c wr32(E1000_RXPBS, regval); regval 1088 drivers/net/ethernet/intel/igb/igb_ptp.c regval = rd32(E1000_TSYNCTXCTL); regval 1089 drivers/net/ethernet/intel/igb/igb_ptp.c regval &= ~E1000_TSYNCTXCTL_ENABLED; regval 1090 drivers/net/ethernet/intel/igb/igb_ptp.c regval |= tsync_tx_ctl; regval 1091 drivers/net/ethernet/intel/igb/igb_ptp.c wr32(E1000_TSYNCTXCTL, regval); regval 1094 drivers/net/ethernet/intel/igb/igb_ptp.c regval = rd32(E1000_TSYNCRXCTL); regval 1095 drivers/net/ethernet/intel/igb/igb_ptp.c regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); regval 1096 drivers/net/ethernet/intel/igb/igb_ptp.c regval |= tsync_rx_ctl; regval 1097 drivers/net/ethernet/intel/igb/igb_ptp.c wr32(E1000_TSYNCRXCTL, regval); regval 1134 drivers/net/ethernet/intel/igb/igb_ptp.c regval = rd32(E1000_TXSTMPL); regval 1135 drivers/net/ethernet/intel/igb/igb_ptp.c regval = rd32(E1000_TXSTMPH); regval 1136 drivers/net/ethernet/intel/igb/igb_ptp.c regval = rd32(E1000_RXSTMPL); regval 1137 drivers/net/ethernet/intel/igb/igb_ptp.c regval = rd32(E1000_RXSTMPH); regval 3737 drivers/net/ethernet/intel/igc/igc_main.c u32 regval = rd32(IGC_EIAM); regval 3739 drivers/net/ethernet/intel/igc/igc_main.c wr32(IGC_EIAM, regval & ~adapter->eims_enable_mask); regval 3741 drivers/net/ethernet/intel/igc/igc_main.c regval = rd32(IGC_EIAC); regval 3742 drivers/net/ethernet/intel/igc/igc_main.c wr32(IGC_EIAC, regval & ~adapter->eims_enable_mask); regval 3771 drivers/net/ethernet/intel/igc/igc_main.c u32 regval = rd32(IGC_EIAC); regval 3773 drivers/net/ethernet/intel/igc/igc_main.c wr32(IGC_EIAC, regval | adapter->eims_enable_mask); regval 3774 drivers/net/ethernet/intel/igc/igc_main.c regval = rd32(IGC_EIAM); regval 3775 drivers/net/ethernet/intel/igc/igc_main.c wr32(IGC_EIAM, regval | adapter->eims_enable_mask); regval 1838 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) regval 1848 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c if (regval & IXGBE_RXCTRL_RXEN) regval 2735 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) regval 2737 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c if (regval & IXGBE_RXCTRL_RXEN) regval 58 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval); regval 817 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c u64 regval = 0; regval 819 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); regval 820 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32; regval 821 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c ixgbe_ptp_convert_to_hwtstamp(adapter, &shhwtstamps, regval); regval 888 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c __le64 regval; regval 891 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c skb_copy_bits(skb, skb->len - IXGBE_TS_HDR_LEN, ®val, regval 902 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c le64_to_cpu(regval)); regval 919 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c u64 regval = 0; regval 937 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); regval 938 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32; regval 940 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c ixgbe_ptp_convert_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); regval 993 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c u32 regval; regval 1113 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); regval 1114 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c regval &= ~IXGBE_TSYNCTXCTL_ENABLED; regval 1115 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c regval |= tsync_tx_ctl; regval 1116 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval); regval 1119 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); regval 1120 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK); regval 1121 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c regval |= tsync_rx_ctl; regval 1122 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval); regval 536 drivers/net/ethernet/marvell/octeontx2/af/mbox.h u64 regval[MAX_REGS_PER_MBOX_MSG]; regval 1397 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int lvl, u64 reg, u64 regval) regval 1410 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c parent = (regval >> 16) & 0x1FF; regval 1441 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c u64 reg, regval; regval 1472 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c regval = (TXSCH_TL1_DFLT_RR_PRIO << 1); regval 1473 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, reg, regval); regval 1475 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c regval = TXSCH_TL1_DFLT_RR_QTM; regval 1476 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, reg, regval); regval 1478 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c regval = 0; regval 1479 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, reg, regval); regval 1495 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c u64 reg, regval, schq_regbase; regval 1532 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c regval = req->regval[idx]; regval 1536 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c txsch->lvl, reg, regval)) regval 1543 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c regval &= ~(0x7FULL << 24); regval 1544 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c regval |= ((u64)nixlf << 24); regval 1562 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, reg, regval); regval 1566 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c (regval & BIT_ULL(49))) { regval 1579 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c u64 regval = req->vtag_size; regval 1585 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c regval |= BIT_ULL(5); regval 1587 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c regval |= BIT_ULL(4); regval 1590 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c NIX_AF_LFX_RX_VTAG_TYPEX(nixlf, req->rx.vtag_type), regval); regval 752 drivers/net/ethernet/microchip/lan743x_main.c int phy_id, int index, u16 regval) regval 762 drivers/net/ethernet/microchip/lan743x_main.c val = (u32)regval; regval 2740 drivers/net/ethernet/natsemi/natsemi.c u32 regval = readl(ioaddr + WOLCmd); regval 2752 drivers/net/ethernet/natsemi/natsemi.c if (regval & WakePhy) regval 2754 drivers/net/ethernet/natsemi/natsemi.c if (regval & WakeUnicast) regval 2756 drivers/net/ethernet/natsemi/natsemi.c if (regval & WakeMulticast) regval 2758 drivers/net/ethernet/natsemi/natsemi.c if (regval & WakeBroadcast) regval 2760 drivers/net/ethernet/natsemi/natsemi.c if (regval & WakeArp) regval 2762 drivers/net/ethernet/natsemi/natsemi.c if (regval & WakeMagic) regval 2764 drivers/net/ethernet/natsemi/natsemi.c if (regval & WakeMagicSecure) { regval 1000 drivers/net/ethernet/ni/nixge.c u32 regval = 0; regval 1002 drivers/net/ethernet/ni/nixge.c regval = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); regval 1003 drivers/net/ethernet/ni/nixge.c ecoalesce->rx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK) regval 1005 drivers/net/ethernet/ni/nixge.c regval = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); regval 1006 drivers/net/ethernet/ni/nixge.c ecoalesce->tx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK) regval 23 drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c u32 regval; regval 26 drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c regval = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); regval 30 drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c regval |= SXGBE_TX_JABBER_DISABLE; regval 31 drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c writel(regval, ioaddr + SXGBE_CORE_TX_CONFIG_REG); regval 34 drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c regval = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); regval 39 drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c regval |= SXGBE_RX_JUMBPKT_ENABLE | SXGBE_RX_ACS_ENABLE; regval 40 drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c writel(regval, ioaddr + SXGBE_CORE_RX_CONFIG_REG); regval 103 drivers/net/ethernet/sun/sunbmac.c u32 regval; regval 109 drivers/net/ethernet/sun/sunbmac.c regval = GLOB_CTRL_B32; regval 111 drivers/net/ethernet/sun/sunbmac.c regval = GLOB_CTRL_B16; regval 112 drivers/net/ethernet/sun/sunbmac.c sbus_writel(regval | GLOB_CTRL_BMODE, gregs + GLOB_CTRL); regval 38 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 40 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_RCR); regval 41 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_IPC_POS, regval 43 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_RCR); regval 50 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 52 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_RCR); regval 53 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_IPC_POS, regval 55 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_RCR); regval 112 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 114 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_VLANTR); regval 116 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_EVLRXS_POS, regval 119 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_DOVLTC_POS, regval 122 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_ERSVLM_POS, regval 125 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_ESVL_POS, regval 128 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_EVLS_POS, regval 130 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_VLANTR); regval 137 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 139 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_VLANTR); regval 140 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_EVLS_POS, regval 142 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_VLANTR); regval 149 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 151 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_PFR); regval 153 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_VTFE_POS, regval 155 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_PFR); regval 157 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_VLANTR); regval 159 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_VTHM_POS, regval 162 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_VTIM_POS, regval 165 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_ETV_POS, regval 173 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_VL_POS, regval 175 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_VLANTR); regval 182 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 184 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_PFR); regval 186 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_VTFE_POS, regval 188 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_PFR); regval 221 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 234 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_VLANHTR); regval 236 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANHTR_VLHT_POS, regval 238 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_VLANHTR); regval 247 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 249 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_PFR), regval 251 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c if (regval == val) regval 257 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_PFR); regval 258 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_PR_POS, regval 260 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_PFR); regval 277 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 279 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_PFR), regval 281 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c if (regval == val) regval 287 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_PFR); regval 288 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_PM_POS, regval 290 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_PFR); regval 375 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 381 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_PFR); regval 382 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_HPF_POS, regval 384 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_HUC_POS, regval 386 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_HMC_POS, regval 388 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_PFR); regval 395 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 399 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_RCR); regval 400 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_JE_POS, regval 402 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_RCR); regval 415 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 417 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_VLANIR); regval 419 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANIR_CSVL_POS, regval 421 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANIR_VLTI_POS, regval 423 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_VLANIR); regval 501 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 509 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR)); regval 510 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_ST_POS, regval 512 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR)); regval 517 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); regval 518 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TXQEN_POS, regval 521 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); regval 525 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_TCR); regval 526 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_TE_POS, regval 528 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_TCR); regval 535 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 547 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_TCR); regval 548 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_TE_POS, regval 550 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_TCR); regval 554 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); regval 555 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TXQEN_POS, regval 557 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); regval 566 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR)); regval 567 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_ST_POS, regval 569 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR)); regval 605 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c unsigned int regval, i; regval 613 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR)); regval 614 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_SR_POS, regval 616 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR)); regval 620 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = 0; regval 622 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval |= (0x02 << (i << 1)); regval 623 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_RQC0R); regval 626 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_RCR); regval 627 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_DCRCC_POS, regval 629 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_CST_POS, regval 631 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_ACS_POS, regval 633 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_RE_POS, regval 635 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_RCR); regval 642 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 645 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_RCR); regval 646 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_DCRCC_POS, regval 648 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_CST_POS, regval 650 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_ACS_POS, regval 652 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_RE_POS, regval 654 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_RCR); regval 669 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR)); regval 670 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_SR_POS, regval 672 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR)); regval 1191 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c unsigned int reg, regval; regval 1196 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); regval 1197 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_EHFC_POS, regval 1199 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); regval 1207 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + reg); regval 1208 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, regval 1212 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + reg); regval 1223 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c unsigned int reg, regval; regval 1228 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); regval 1229 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_EHFC_POS, regval 1231 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); regval 1239 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + reg); regval 1242 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_Q0TFCR_TFE_POS, regval 1245 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_Q0TFCR_PT_POS, regval 1248 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + reg); regval 1258 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1260 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_RFCR); regval 1261 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RFCR_RFE_POS, regval 1263 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_RFCR); regval 1270 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1272 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_RFCR); regval 1273 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RFCR_RFE_POS, regval 1275 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_RFCR); regval 1304 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1311 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RIWT)); regval 1312 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RIWT_RWT_POS, regval 1315 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RIWT)); regval 1330 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1333 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); regval 1334 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_FEP_POS, regval 1336 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); regval 1343 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1346 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); regval 1347 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_FUP_POS, regval 1349 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); regval 1362 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1369 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR)); regval 1370 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_RBSZ_POS, regval 1373 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR)); regval 1381 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1389 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR)); regval 1390 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_TSE_POS, regval 1392 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR)); regval 1401 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1408 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_CR)); regval 1409 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_CR_SPH_POS, regval 1411 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_CR)); regval 1414 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_RCR); regval 1415 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_HDSMS_POS, regval 1418 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_RCR); regval 1461 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1464 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); regval 1465 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_RTC_POS, regval 1467 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); regval 1476 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1479 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MTL_OMR); regval 1480 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_OMR_ETSALG_POS, regval 1482 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MTL_OMR); regval 1486 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_TC_ETSCR)); regval 1487 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_TC_ETSCR_TSA_POS, regval 1489 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_TC_ETSCR)); regval 1491 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_TC_QWR)); regval 1492 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_TC_QWR_QW_POS, regval 1494 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_TC_QWR)); regval 1498 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MTL_OMR); regval 1499 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_OMR_RAA_POS, regval 1501 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MTL_OMR); regval 1508 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c unsigned int reg, regval; regval 1522 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, queue, regval 1524 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, regval 1528 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_MTL_REG(pdata, queue, regval 1536 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, queue, regval 1538 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, regval 1542 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_MTL_REG(pdata, queue, regval 1555 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = 0; regval 1572 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); regval 1577 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + reg); regval 1579 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = 0; regval 1586 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + reg); regval 1587 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval |= (MTL_RQDCM0R_Q0MDMACH | MTL_RQDCM0R_Q1MDMACH | regval 1589 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + reg); regval 1592 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + reg); regval 1593 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval |= (MTL_RQDCM1R_Q4MDMACH | MTL_RQDCM1R_Q5MDMACH | regval 1595 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + reg); regval 1598 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + reg); regval 1599 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval |= (MTL_RQDCM2R_Q8MDMACH | MTL_RQDCM2R_Q9MDMACH | regval 1601 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + reg); regval 1634 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1641 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); regval 1642 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TQS_POS, regval 1644 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); regval 1656 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1663 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); regval 1664 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_RQS_POS, regval 1666 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); regval 1677 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1680 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQFCR)); regval 1682 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQFCR_RFA_POS, regval 1685 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQFCR_RFD_POS, regval 1687 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQFCR)); regval 1695 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1698 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); regval 1699 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TTC_POS, regval 1701 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); regval 1711 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1714 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); regval 1715 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_RSF_POS, regval 1717 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); regval 1727 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1730 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); regval 1731 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TSF_POS, regval 1733 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); regval 1743 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1750 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR)); regval 1751 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_OSP_POS, regval 1754 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR)); regval 1764 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1768 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_CR)); regval 1769 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_CR_PBLX8_POS, regval 1772 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_CR)); regval 1780 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1782 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_DMA_REG(pdata->channel_head, DMA_CH_TCR)); regval 1783 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_GET_REG_BITS(regval, DMA_CH_TCR_PBL_POS, regval 1785 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c return regval; regval 1792 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1799 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR)); regval 1800 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_PBL_POS, regval 1803 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR)); regval 1811 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1813 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_DMA_REG(pdata->channel_head, DMA_CH_RCR)); regval 1814 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_GET_REG_BITS(regval, DMA_CH_RCR_PBL_POS, regval 1816 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c return regval; regval 1823 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 1830 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR)); regval 1831 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_PBL_POS, regval 1834 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR)); regval 2127 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 2130 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MMC_CR); regval 2131 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_MCF_POS, regval 2133 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MMC_CR); regval 2259 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MMC_CR); regval 2260 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_MCF_POS, regval 2262 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MMC_CR); regval 2267 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 2269 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MMC_CR); regval 2271 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_ROR_POS, regval 2274 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_CR_POS, regval 2276 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MMC_CR); regval 2284 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 2288 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_RSSAR), regval 2290 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c if (regval) { regval 2297 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_RSSAR); regval 2298 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_RSSIA_POS, regval 2300 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_ADDRT_POS, regval 2302 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_CT_POS, regval 2304 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_OB_POS, regval 2306 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_RSSAR); regval 2310 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_RSSAR), regval 2313 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c if (!regval) regval 2386 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 2406 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_RSSCR); regval 2407 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSCR_RSSE_POS, regval 2409 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_RSSCR); regval 2416 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 2421 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_RSSCR); regval 2422 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSCR_RSSE_POS, regval 2424 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_RSSCR); regval 2530 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 2539 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MMC_RIER); regval 2540 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MMC_RIER_ALL_INTERRUPTS_POS, regval 2542 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MMC_RIER); regval 2543 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MMC_TIER); regval 2544 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MMC_TIER_ALL_INTERRUPTS_POS, regval 2546 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MMC_TIER); regval 2551 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 2553 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR), regval 2555 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c if (regval == 0x1) regval 2558 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_TCR); regval 2559 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS, regval 2561 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_TCR); regval 2568 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 2570 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR), regval 2572 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c if (regval == 0) regval 2575 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_TCR); regval 2576 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS, regval 2578 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_TCR); regval 2585 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 2587 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR), regval 2589 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c if (regval == 0x2) regval 2592 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_TCR); regval 2593 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS, regval 2595 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_TCR); regval 2602 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 2604 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR), regval 2606 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c if (regval == 0x3) regval 2609 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + MAC_TCR); regval 2610 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS, regval 2612 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + MAC_TCR); regval 2946 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 2949 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); regval 2950 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_FTQ_POS, regval 2952 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); regval 2958 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); regval 2959 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_GET_REG_BITS(regval, MTL_Q_TQOMR_FTQ_POS, regval 2961 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c while (--count && regval) regval 2973 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 2975 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + DMA_SBMR); regval 2977 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, DMA_SBMR_EAME_POS, regval 2980 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, DMA_SBMR_UNDEF_POS, regval 2982 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, DMA_SBMR_BLEN_256_POS, regval 2984 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + DMA_SBMR); regval 3044 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c u32 regval; regval 3047 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + DMA_MR); regval 3048 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = XLGMAC_SET_REG_BITS(regval, DMA_MR_SWR_POS, regval 3050 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + DMA_MR); regval 1279 drivers/net/ethernet/xilinx/xilinx_axienet_main.c u32 regval = 0; regval 1281 drivers/net/ethernet/xilinx/xilinx_axienet_main.c regval = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); regval 1282 drivers/net/ethernet/xilinx/xilinx_axienet_main.c ecoalesce->rx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK) regval 1284 drivers/net/ethernet/xilinx/xilinx_axienet_main.c regval = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); regval 1285 drivers/net/ethernet/xilinx/xilinx_axienet_main.c ecoalesce->tx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK) regval 766 drivers/net/phy/micrel.c int regval; regval 769 drivers/net/phy/micrel.c regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); regval 771 drivers/net/phy/micrel.c regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); regval 773 drivers/net/phy/micrel.c if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) regval 778 drivers/net/phy/micrel.c if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) regval 819 drivers/net/phy/micrel.c int regval; regval 828 drivers/net/phy/micrel.c regval = phy_read(phydev, MII_STAT1000); regval 829 drivers/net/phy/micrel.c if ((regval & 0xFF) == 0xFF) { regval 1763 drivers/net/usb/lan78xx.c u16 regval) regval 1780 drivers/net/usb/lan78xx.c val = (u32)regval; regval 227 drivers/net/usb/smsc75xx.c int idx, int regval, int in_pm) regval 242 drivers/net/usb/smsc75xx.c val = regval; regval 278 drivers/net/usb/smsc75xx.c int idx, int regval) regval 280 drivers/net/usb/smsc75xx.c __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1); regval 289 drivers/net/usb/smsc75xx.c int regval) regval 291 drivers/net/usb/smsc75xx.c __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0); regval 222 drivers/net/usb/smsc95xx.c int idx, int regval, int in_pm) regval 237 drivers/net/usb/smsc95xx.c val = regval; regval 271 drivers/net/usb/smsc95xx.c int idx, int regval) regval 273 drivers/net/usb/smsc95xx.c __smsc95xx_mdio_write(netdev, phy_id, idx, regval, 1); regval 282 drivers/net/usb/smsc95xx.c int regval) regval 284 drivers/net/usb/smsc95xx.c __smsc95xx_mdio_write(netdev, phy_id, idx, regval, 0); regval 678 drivers/net/wan/farsync.c unsigned int regval; regval 710 drivers/net/wan/farsync.c regval = inl(card->pci_conf + CNTRL_9052); regval 712 drivers/net/wan/farsync.c outl(regval | 0x40000000, card->pci_conf + CNTRL_9052); regval 713 drivers/net/wan/farsync.c outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052); regval 450 drivers/net/wireless/ath/ath5k/reset.c u32 regval; regval 478 drivers/net/wireless/ath/ath5k/reset.c regval = ioread32(reg); regval 479 drivers/net/wireless/ath/ath5k/reset.c iowrite32(regval | val, reg); regval 480 drivers/net/wireless/ath/ath5k/reset.c regval = ioread32(reg); regval 484 drivers/net/wireless/ath/ath5k/reset.c iowrite32(regval & ~val, reg); regval 485 drivers/net/wireless/ath/ath5k/reset.c regval = ioread32(reg); regval 401 drivers/net/wireless/ath/ath9k/ar9002_calib.c int delta, currPDADC, regval; regval 417 drivers/net/wireless/ath/ath9k/ar9002_calib.c regval = ah->originalGain[i] - delta; regval 418 drivers/net/wireless/ath/ath9k/ar9002_calib.c if (regval < 0) regval 419 drivers/net/wireless/ath/ath9k/ar9002_calib.c regval = 0; regval 423 drivers/net/wireless/ath/ath9k/ar9002_calib.c AR_PHY_TX_GAIN, regval); regval 381 drivers/net/wireless/ath/ath9k/ar9002_phy.c u32 regval; regval 383 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); regval 384 drivers/net/wireless/ath/ath9k/ar9002_phy.c antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >> regval 386 drivers/net/wireless/ath/ath9k/ar9002_phy.c antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >> regval 388 drivers/net/wireless/ath/ath9k/ar9002_phy.c antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >> regval 398 drivers/net/wireless/ath/ath9k/ar9002_phy.c u32 regval; regval 400 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); regval 401 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF | regval 404 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S) regval 406 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S) regval 408 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S) regval 411 drivers/net/wireless/ath/ath9k/ar9002_phy.c REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval); regval 420 drivers/net/wireless/ath/ath9k/ar9002_phy.c u32 regval; regval 455 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); regval 456 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); regval 461 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval &= (~(AR_PHY_9285_FAST_DIV_BIAS)); regval 462 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval |= SM(antdiv_ctrl1, AR_PHY_9285_ANT_DIV_CTL); regval 463 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval |= SM(antdiv_ctrl2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); regval 464 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval |= SM((antdiv_ctrl2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF); regval 465 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval |= SM((antdiv_ctrl1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB); regval 466 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval |= SM((antdiv_ctrl1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB); regval 467 drivers/net/wireless/ath/ath9k/ar9002_phy.c REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval); regval 469 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval = REG_READ(ah, AR_PHY_CCK_DETECT); regval 470 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); regval 471 drivers/net/wireless/ath/ath9k/ar9002_phy.c regval |= SM((antdiv_ctrl1 >> 3), AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); regval 472 drivers/net/wireless/ath/ath9k/ar9002_phy.c REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); regval 3649 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c u32 regval, value, gpio; regval 3729 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); regval 3730 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval &= (~AR_ANT_DIV_CTRL_ALL); regval 3731 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S; regval 3733 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval &= (~AR_PHY_ANT_DIV_LNADIV); regval 3734 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval |= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S; regval 3737 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval |= AR_ANT_DIV_ENABLE; regval 3741 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval |= (1 << AR_PHY_ANT_SW_RX_PROT_S); regval 3750 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval &= ~(1 << AR_PHY_ANT_DIV_LNADIV_S); regval 3751 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval &= ~(1 << AR_PHY_ANT_SW_RX_PROT_S); regval 3762 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); regval 3765 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval = REG_READ(ah, AR_PHY_CCK_DETECT); regval 3766 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval &= (~AR_FAST_DIV_ENABLE); regval 3767 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval |= ((value >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S; regval 3771 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval |= AR_FAST_DIV_ENABLE; regval 3773 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); regval 3776 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); regval 3781 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF | regval 3786 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval |= (ATH_ANT_DIV_COMB_LNA1 << regval 3788 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c regval |= (ATH_ANT_DIV_COMB_LNA2 << regval 3790 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); regval 866 drivers/net/wireless/ath/ath9k/ar9003_mci.c u32 regval; regval 868 drivers/net/wireless/ath/ath9k/ar9003_mci.c regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) | regval 880 drivers/net/wireless/ath/ath9k/ar9003_mci.c REG_WRITE(ah, AR_BTCOEX_CTRL, regval); regval 885 drivers/net/wireless/ath/ath9k/ar9003_mci.c u32 regval; regval 887 drivers/net/wireless/ath/ath9k/ar9003_mci.c regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) | regval 899 drivers/net/wireless/ath/ath9k/ar9003_mci.c REG_WRITE(ah, AR_BTCOEX_CTRL, regval); regval 904 drivers/net/wireless/ath/ath9k/ar9003_mci.c u32 regval; regval 906 drivers/net/wireless/ath/ath9k/ar9003_mci.c regval = SM(1, AR_BTCOEX_CTRL_AR9462_MODE) | regval 916 drivers/net/wireless/ath/ath9k/ar9003_mci.c REG_WRITE(ah, AR_BTCOEX_CTRL, regval); regval 924 drivers/net/wireless/ath/ath9k/ar9003_mci.c u32 regval, i; regval 982 drivers/net/wireless/ath/ath9k/ar9003_mci.c regval = MS(mci->config, ATH_MCI_CONFIG_CLK_DIV); regval 983 drivers/net/wireless/ath/ath9k/ar9003_mci.c REG_RMW_FIELD(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_CLK_DIV, regval); regval 987 drivers/net/wireless/ath/ath9k/ar9003_mci.c regval = REG_READ(ah, AR_MCI_COMMAND2); regval 988 drivers/net/wireless/ath/ath9k/ar9003_mci.c regval |= SM(1, AR_MCI_COMMAND2_RESET_TX); regval 989 drivers/net/wireless/ath/ath9k/ar9003_mci.c REG_WRITE(ah, AR_MCI_COMMAND2, regval); regval 993 drivers/net/wireless/ath/ath9k/ar9003_mci.c regval &= ~SM(1, AR_MCI_COMMAND2_RESET_TX); regval 994 drivers/net/wireless/ath/ath9k/ar9003_mci.c REG_WRITE(ah, AR_MCI_COMMAND2, regval); regval 1004 drivers/net/wireless/ath/ath9k/ar9003_mci.c regval |= SM(1, AR_MCI_COMMAND2_RESET_RX); regval 1005 drivers/net/wireless/ath/ath9k/ar9003_mci.c REG_WRITE(ah, AR_MCI_COMMAND2, regval); regval 1007 drivers/net/wireless/ath/ath9k/ar9003_mci.c regval &= ~SM(1, AR_MCI_COMMAND2_RESET_RX); regval 1008 drivers/net/wireless/ath/ath9k/ar9003_mci.c REG_WRITE(ah, AR_MCI_COMMAND2, regval); regval 1173 drivers/net/wireless/ath/ath9k/ar9003_mci.c u32 regval; regval 1178 drivers/net/wireless/ath/ath9k/ar9003_mci.c regval = REG_READ(ah, AR_BTCOEX_CTRL); regval 1180 drivers/net/wireless/ath/ath9k/ar9003_mci.c if ((regval == 0xdeadbeef) || !(regval & AR_BTCOEX_CTRL_MCI_MODE_EN)) { regval 1510 drivers/net/wireless/ath/ath9k/ar9003_phy.c u32 regval; regval 1512 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); regval 1513 drivers/net/wireless/ath/ath9k/ar9003_phy.c antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >> regval 1515 drivers/net/wireless/ath/ath9k/ar9003_phy.c antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >> regval 1517 drivers/net/wireless/ath/ath9k/ar9003_phy.c antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >> regval 1542 drivers/net/wireless/ath/ath9k/ar9003_phy.c u32 regval; regval 1544 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); regval 1545 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF | regval 1550 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S) regval 1552 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S) regval 1554 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S) regval 1556 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S) regval 1558 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S) regval 1561 drivers/net/wireless/ath/ath9k/ar9003_phy.c REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); regval 1570 drivers/net/wireless/ath/ath9k/ar9003_phy.c u32 regval; regval 1576 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval = ar9003_hw_ant_ctrl_common_2_get(ah, regval 1579 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval &= ~AR_SWITCH_TABLE_COM2_ALL; regval 1580 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval |= ah->config.ant_ctrl_comm2g_switch_enable; regval 1583 drivers/net/wireless/ath/ath9k/ar9003_phy.c AR_SWITCH_TABLE_COM2_ALL, regval); regval 1592 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); regval 1593 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval &= (~AR_ANT_DIV_CTRL_ALL); regval 1594 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S; regval 1595 drivers/net/wireless/ath/ath9k/ar9003_phy.c REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); regval 1601 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); regval 1602 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval &= ~AR_PHY_ANT_DIV_LNADIV; regval 1603 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S; regval 1605 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval |= AR_ANT_DIV_ENABLE; regval 1607 drivers/net/wireless/ath/ath9k/ar9003_phy.c REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); regval 1612 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval = REG_READ(ah, AR_PHY_CCK_DETECT); regval 1613 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval &= ~AR_FAST_DIV_ENABLE; regval 1614 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S; regval 1616 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval |= AR_FAST_DIV_ENABLE; regval 1618 drivers/net/wireless/ath/ath9k/ar9003_phy.c REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); regval 1621 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); regval 1622 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF | regval 1630 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval |= (ATH_ANT_DIV_COMB_LNA1 << regval 1632 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval |= (ATH_ANT_DIV_COMB_LNA2 << regval 1634 drivers/net/wireless/ath/ath9k/ar9003_phy.c REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); regval 1660 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); regval 1661 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF | regval 1665 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval |= (ATH_ANT_DIV_COMB_LNA1 << regval 1667 drivers/net/wireless/ath/ath9k/ar9003_phy.c regval |= (ATH_ANT_DIV_COMB_LNA2 << regval 1669 drivers/net/wireless/ath/ath9k/ar9003_phy.c REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); regval 870 drivers/net/wireless/ath/ath9k/debug.c u32 regval; regval 873 drivers/net/wireless/ath/ath9k/debug.c regval = REG_READ_D(ah, sc->debug.regidx); regval 875 drivers/net/wireless/ath/ath9k/debug.c len = sprintf(buf, "0x%08x\n", regval); regval 884 drivers/net/wireless/ath/ath9k/debug.c unsigned long regval; regval 893 drivers/net/wireless/ath/ath9k/debug.c if (kstrtoul(buf, 0, ®val)) regval 897 drivers/net/wireless/ath/ath9k/debug.c REG_WRITE_D(ah, sc->debug.regidx, regval); regval 365 drivers/net/wireless/ath/ath9k/eeprom_9287.c u32 reg32, regOffset, regChainOffset, regval; regval 443 drivers/net/wireless/ath/ath9k/eeprom_9287.c regval = SM(pdGainOverlap_t2, regval 456 drivers/net/wireless/ath/ath9k/eeprom_9287.c regval); regval 855 drivers/net/wireless/ath/ath9k/eeprom_9287.c u32 regChainOffset, regval; regval 919 drivers/net/wireless/ath/ath9k/eeprom_9287.c regval = REG_READ(ah, AR9287_AN_RF2G3_CH0); regval 920 drivers/net/wireless/ath/ath9k/eeprom_9287.c regval &= ~(AR9287_AN_RF2G3_DB1 | regval 926 drivers/net/wireless/ath/ath9k/eeprom_9287.c regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) | regval 933 drivers/net/wireless/ath/ath9k/eeprom_9287.c ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH0, regval); regval 935 drivers/net/wireless/ath/ath9k/eeprom_9287.c regval = REG_READ(ah, AR9287_AN_RF2G3_CH1); regval 936 drivers/net/wireless/ath/ath9k/eeprom_9287.c regval &= ~(AR9287_AN_RF2G3_DB1 | regval 942 drivers/net/wireless/ath/ath9k/eeprom_9287.c regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) | regval 949 drivers/net/wireless/ath/ath9k/eeprom_9287.c ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH1, regval); regval 834 drivers/net/wireless/ath/ath9k/hw.c u32 regval, pll2_divint, pll2_divfrac, refdiv; regval 867 drivers/net/wireless/ath/ath9k/hw.c regval = REG_READ(ah, AR_PHY_PLL_MODE); regval 869 drivers/net/wireless/ath/ath9k/hw.c regval |= (0x1 << 22); regval 871 drivers/net/wireless/ath/ath9k/hw.c regval |= (0x1 << 16); regval 872 drivers/net/wireless/ath/ath9k/hw.c REG_WRITE(ah, AR_PHY_PLL_MODE, regval); regval 879 drivers/net/wireless/ath/ath9k/hw.c regval = REG_READ(ah, AR_PHY_PLL_MODE); regval 881 drivers/net/wireless/ath/ath9k/hw.c regval = (regval & 0x80071fff) | regval 887 drivers/net/wireless/ath/ath9k/hw.c regval = (regval & 0x01c00fff) | regval 894 drivers/net/wireless/ath/ath9k/hw.c regval |= (0x6 << 12); regval 896 drivers/net/wireless/ath/ath9k/hw.c regval = (regval & 0x80071fff) | regval 901 drivers/net/wireless/ath/ath9k/hw.c REG_WRITE(ah, AR_PHY_PLL_MODE, regval); regval 717 drivers/net/wireless/broadcom/b43/phy_ht.c u32 regval[64]; regval 723 drivers/net/wireless/broadcom/b43/phy_ht.c regval[i] = pwr; regval 725 drivers/net/wireless/broadcom/b43/phy_ht.c b43_httab_write_bulk(dev, B43_HTTAB16(26 + c, 0), 64, regval); regval 4054 drivers/net/wireless/broadcom/b43/phy_n.c u32 regval[64]; regval 4204 drivers/net/wireless/broadcom/b43/phy_n.c regval[i] = pwr; regval 4206 drivers/net/wireless/broadcom/b43/phy_n.c b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval); regval 180 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) regval 181 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) regval 182 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) regval 183 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c #define SBSDIO_CLKAV(regval, alponly) \ regval 184 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval))) regval 15087 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 regval[4]; regval 15120 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[0] = nphy_def_lnagains[2] + gain_delta[core]; regval 15121 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[1] = nphy_def_lnagains[3] + gain_delta[core]; regval 15122 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[2] = nphy_def_lnagains[3] + gain_delta[core]; regval 15123 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[3] = nphy_def_lnagains[3] + gain_delta[core]; regval 15126 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[ctr] = regval 15130 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, core, 4, 8, 16, regval); regval 15582 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 regval[21]; regval 16008 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[ctr] = (hpf_code << 8) | 0x7c; regval 16009 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, 7, 4, 0x106, 16, regval); regval 16014 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[0] = 0; regval 16015 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[1] = 1; regval 16016 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[2] = 1; regval 16017 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[3] = 1; regval 16018 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, 2, 4, 8, 16, regval); regval 16019 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, 3, 4, 8, 16, regval); regval 16022 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[ctr] = (hpf_code << 8) | 0x74; regval 16023 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, 7, 4, 0x106, 16, regval); regval 16028 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[ctr] = 3 * ctr; regval 16029 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, 0, 21, 32, 16, regval); regval 16030 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, 1, 21, 32, 16, regval); regval 16033 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[ctr] = (u16) ctr; regval 16034 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, 2, 21, 32, 16, regval); regval 16035 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, 3, 21, 32, 16, regval); regval 16920 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 regval; regval 16938 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval = 0x000a; regval 16939 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, 8, 1, 0, 16, ®val); regval 16940 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, 8, 1, 0x10, 16, ®val); regval 16943 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval = 0xcdaa; regval 16944 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, 8, 1, 0x02, 16, ®val); regval 16945 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, 8, 1, 0x12, 16, ®val); regval 16949 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval = 0x0000; regval 16950 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, 8, 1, 0x08, 16, ®val); regval 16951 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, 8, 1, 0x18, 16, ®val); regval 16953 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval = 0x7aab; regval 16954 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, 8, 1, 0x07, 16, ®val); regval 16955 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, 8, 1, 0x17, 16, ®val); regval 16957 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval = 0x0800; regval 16958 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, 8, 1, 0x06, 16, ®val); regval 16959 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c wlc_phy_table_write_nphy(pi, 8, 1, 0x16, 16, ®val); regval 17575 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u32 regval[64]; regval 17760 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[idx] = (u32) pwr_est; regval 17763 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval); regval 18801 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u32 regval[128]; regval 18820 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[idx] = iqcomp; regval 18822 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval); regval 18848 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[idx] = curr_locomp; regval 18851 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval); regval 18980 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 regval; regval 18986 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval = read_phy_reg(pi, 0x27d); regval 18987 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c pi->nphy_crsminpwr[0] = regval & 0xff; regval 18988 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval &= 0xff00; regval 18989 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval |= (u16) minpwr; regval 18990 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, 0x27d, regval); regval 18992 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval = read_phy_reg(pi, 0x280); regval 18993 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c pi->nphy_crsminpwr[1] = regval & 0xff; regval 18994 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval &= 0xff00; regval 18995 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval |= (u16) minpwr; regval 18996 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, 0x280, regval); regval 18998 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval = read_phy_reg(pi, 0x283); regval 18999 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c pi->nphy_crsminpwr[2] = regval & 0xff; regval 19000 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval &= 0xff00; regval 19001 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval |= (u16) minpwr; regval 19002 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, 0x283, regval); regval 19008 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval = read_phy_reg(pi, 0x27d); regval 19009 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval &= 0xff00; regval 19010 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval |= pi->nphy_crsminpwr[0]; regval 19011 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, 0x27d, regval); regval 19013 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval = read_phy_reg(pi, 0x280); regval 19014 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval &= 0xff00; regval 19015 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval |= pi->nphy_crsminpwr[1]; regval 19016 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, 0x280, regval); regval 19018 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval = read_phy_reg(pi, 0x283); regval 19019 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval &= 0xff00; regval 19020 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval |= pi->nphy_crsminpwr[2]; regval 19021 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, 0x283, regval); regval 19636 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 regval; regval 19656 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval = read_phy_reg(pi, 0xa2); regval 19657 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval &= ~(0xf << 4); regval 19658 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval |= ((u16) (rxcore_bitmask & 0x3)) << 4; regval 19659 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_phy_reg(pi, 0xa2, regval); regval 19716 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 regval, rxen_bits; regval 19719 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval = read_phy_reg(pi, 0xa2); regval 19720 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c rxen_bits = (regval >> 4) & 0xf; regval 28197 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 regval[84]; regval 28228 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[ctr] = 0; regval 28230 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval); regval 28232 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval); regval 28349 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 regval[2]; regval 28512 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[0] = (u16) iqcomp_a; regval 28513 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval[1] = (u16) iqcomp_b; regval 28516 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c regval); regval 237 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c u16 regval; regval 241 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); regval 243 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c regval | BIT(13) | BIT(0) | BIT(1)); regval 72 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c u16 regval; regval 77 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); regval 79 drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c regval | BIT(13) | BIT(0) | BIT(1)); regval 94 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c u16 regval; regval 99 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); regval 100 drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, regval | BIT(13) | regval 730 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c u16 regval; regval 735 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); regval 737 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c regval | BIT(13) | BIT(0) | BIT(1)); regval 227 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c u16 regval; regval 232 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); regval 234 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c regval | BIT(13) | BIT(0) | BIT(1)); regval 101 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c u16 regval; regval 106 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); regval 108 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c regval | BIT(13) | BIT(0) | BIT(1)); regval 304 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c u8 regval; regval 309 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c regval = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); regval 310 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c regval |= FEN_PCIEA; regval 311 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, regval); regval 313 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c regval | FEN_BB_GLB_RSTN | FEN_BBRSTB); regval 1041 drivers/net/wireless/realtek/rtw88/rtw8822b.c u8 regval = 0; regval 1067 drivers/net/wireless/realtek/rtw88/rtw8822b.c regval = 0x3; regval 1069 drivers/net/wireless/realtek/rtw88/rtw8822b.c regval = (!polarity_inverse ? 0x2 : 0x1); regval 1071 drivers/net/wireless/realtek/rtw88/rtw8822b.c regval = (!polarity_inverse ? 0x2 : 0x1); regval 1073 drivers/net/wireless/realtek/rtw88/rtw8822b.c regval = (!polarity_inverse ? 0x1 : 0x2); regval 1076 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval); regval 1086 drivers/net/wireless/realtek/rtw88/rtw8822b.c regval = (!polarity_inverse ? 0x2 : 0x1); regval 1087 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval); regval 1100 drivers/net/wireless/realtek/rtw88/rtw8822b.c regval = (!polarity_inverse ? 0x0 : 0x1); regval 1101 drivers/net/wireless/realtek/rtw88/rtw8822b.c rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, regval); regval 94 drivers/nvmem/meson-mx-efuse.c u32 regval; regval 97 drivers/nvmem/meson-mx-efuse.c regval = FIELD_PREP(MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, addr); regval 99 drivers/nvmem/meson-mx-efuse.c MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, regval); regval 122 drivers/nvmem/meson-mx-efuse.c regval, regval 123 drivers/nvmem/meson-mx-efuse.c (!(regval & MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY)), regval 154 drivers/pci/controller/dwc/pcie-histb.c u32 regval; regval 157 drivers/pci/controller/dwc/pcie-histb.c regval = histb_pcie_readl(hipcie, PCIE_SYS_STAT0); regval 160 drivers/pci/controller/dwc/pcie-histb.c if ((regval & PCIE_XMLH_LINK_UP) && (regval & PCIE_RDLH_LINK_UP) && regval 171 drivers/pci/controller/dwc/pcie-histb.c u32 regval; regval 179 drivers/pci/controller/dwc/pcie-histb.c regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL0); regval 180 drivers/pci/controller/dwc/pcie-histb.c regval &= ~PCIE_DEVICE_TYPE_MASK; regval 181 drivers/pci/controller/dwc/pcie-histb.c regval |= PCIE_WM_RC; regval 182 drivers/pci/controller/dwc/pcie-histb.c histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, regval); regval 188 drivers/pci/controller/dwc/pcie-histb.c regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL7); regval 189 drivers/pci/controller/dwc/pcie-histb.c regval |= PCIE_APP_LTSSM_ENABLE; regval 190 drivers/pci/controller/dwc/pcie-histb.c histb_pcie_writel(hipcie, PCIE_SYS_CTRL7, regval); regval 530 drivers/phy/allwinner/phy-sun4i-usb.c u32 regval; regval 532 drivers/phy/allwinner/phy-sun4i-usb.c regval = readl(data->base + REG_PHY_OTGCTL); regval 535 drivers/phy/allwinner/phy-sun4i-usb.c regval &= ~OTGCTL_ROUTE_MUSB; regval 538 drivers/phy/allwinner/phy-sun4i-usb.c regval |= OTGCTL_ROUTE_MUSB; regval 540 drivers/phy/allwinner/phy-sun4i-usb.c writel(regval, data->base + REG_PHY_OTGCTL); regval 68 drivers/phy/marvell/phy-berlin-sata.c u32 regval; regval 74 drivers/phy/marvell/phy-berlin-sata.c regval = readl(ctrl_reg + PORT_VSR_DATA); regval 75 drivers/phy/marvell/phy-berlin-sata.c regval &= ~mask; regval 76 drivers/phy/marvell/phy-berlin-sata.c regval |= val; regval 77 drivers/phy/marvell/phy-berlin-sata.c writel(regval, ctrl_reg + PORT_VSR_DATA); regval 85 drivers/phy/marvell/phy-berlin-sata.c u32 regval; regval 93 drivers/phy/marvell/phy-berlin-sata.c regval = readl(priv->base + HOST_VSA_DATA); regval 94 drivers/phy/marvell/phy-berlin-sata.c regval &= ~desc->power_bit; regval 95 drivers/phy/marvell/phy-berlin-sata.c writel(regval, priv->base + HOST_VSA_DATA); regval 99 drivers/phy/marvell/phy-berlin-sata.c regval = readl(priv->base + HOST_VSA_DATA); regval 100 drivers/phy/marvell/phy-berlin-sata.c regval |= MBUS_WRITE_REQUEST_SIZE_128 | MBUS_READ_REQUEST_SIZE_128; regval 101 drivers/phy/marvell/phy-berlin-sata.c writel(regval, priv->base + HOST_VSA_DATA); regval 121 drivers/phy/marvell/phy-berlin-sata.c regval = readl(ctrl_reg + PORT_SCR_CTL); regval 122 drivers/phy/marvell/phy-berlin-sata.c regval &= ~GENMASK(7, 4); regval 123 drivers/phy/marvell/phy-berlin-sata.c regval |= 0x30; regval 124 drivers/phy/marvell/phy-berlin-sata.c writel(regval, ctrl_reg + PORT_SCR_CTL); regval 137 drivers/phy/marvell/phy-berlin-sata.c u32 regval; regval 145 drivers/phy/marvell/phy-berlin-sata.c regval = readl(priv->base + HOST_VSA_DATA); regval 146 drivers/phy/marvell/phy-berlin-sata.c regval |= desc->power_bit; regval 147 drivers/phy/marvell/phy-berlin-sata.c writel(regval, priv->base + HOST_VSA_DATA); regval 38 drivers/phy/mscc/phy-ocelot-serdes.c unsigned int regval = 0; regval 43 drivers/phy/mscc/phy-ocelot-serdes.c return regmap_read_poll_timeout(regmap, HSIO_MCB_S6G_ADDR_CFG, regval, regval 44 drivers/phy/mscc/phy-ocelot-serdes.c (regval & op) != op, 100, regval 270 drivers/phy/mscc/phy-ocelot-serdes.c unsigned int regval; regval 275 drivers/phy/mscc/phy-ocelot-serdes.c return regmap_read_poll_timeout(regmap, HSIO_MCB_S1G_ADDR_CFG, regval, regval 276 drivers/phy/mscc/phy-ocelot-serdes.c (regval & op) != op, 100, regval 429 drivers/pinctrl/cirrus/pinctrl-madera-core.c u16 regval) regval 431 drivers/pinctrl/cirrus/pinctrl-madera-core.c regval = (regval & MADERA_GP1_DRV_STR_MASK) >> MADERA_GP1_DRV_STR_SHIFT; regval 433 drivers/pinctrl/cirrus/pinctrl-madera-core.c switch (regval) { regval 544 drivers/pinctrl/pinctrl-amd.c u32 regval; regval 564 drivers/pinctrl/pinctrl-amd.c regval = readl(regs + i); regval 565 drivers/pinctrl/pinctrl-amd.c if (!(regval & PIN_IRQ_PENDING) || regval 566 drivers/pinctrl/pinctrl-amd.c !(regval & BIT(INTERRUPT_MASK_OFF))) regval 581 drivers/pinctrl/pinctrl-amd.c regval = readl(regs + i); regval 583 drivers/pinctrl/pinctrl-amd.c regval &= ~BIT(INTERRUPT_ENABLE_OFF); regval 588 drivers/pinctrl/pinctrl-amd.c writel(regval, regs + i); regval 596 drivers/pinctrl/pinctrl-amd.c regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); regval 597 drivers/pinctrl/pinctrl-amd.c regval |= EOI_MASK; regval 598 drivers/pinctrl/pinctrl-amd.c writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); regval 657 drivers/pinctrl/pinctrl-artpec6.c unsigned int regval, val; regval 684 drivers/pinctrl/pinctrl-artpec6.c regval = readl(pmx->base + reg); regval 685 drivers/pinctrl/pinctrl-artpec6.c regval &= ~ARTPEC6_PINMUX_SEL_MASK; regval 686 drivers/pinctrl/pinctrl-artpec6.c regval |= val; regval 687 drivers/pinctrl/pinctrl-artpec6.c writel(regval, pmx->base + reg); regval 738 drivers/pinctrl/pinctrl-artpec6.c unsigned int regval; regval 751 drivers/pinctrl/pinctrl-artpec6.c regval = readl(pmx->base + artpec6_pmx_reg_offset(pin)); regval 756 drivers/pinctrl/pinctrl-artpec6.c if (!(regval & ARTPEC6_PINMUX_UDC1_MASK)) regval 762 drivers/pinctrl/pinctrl-artpec6.c if (regval & ARTPEC6_PINMUX_UDC1_MASK) regval 765 drivers/pinctrl/pinctrl-artpec6.c regval = regval & ARTPEC6_PINMUX_UDC0_MASK; regval 766 drivers/pinctrl/pinctrl-artpec6.c if ((param == PIN_CONFIG_BIAS_PULL_UP && !regval) || regval 767 drivers/pinctrl/pinctrl-artpec6.c (param == PIN_CONFIG_BIAS_PULL_DOWN && regval)) regval 771 drivers/pinctrl/pinctrl-artpec6.c regval = (regval & ARTPEC6_PINMUX_DRV_MASK) regval 773 drivers/pinctrl/pinctrl-artpec6.c regval = artpec6_pconf_drive_field_to_mA(regval); regval 774 drivers/pinctrl/pinctrl-artpec6.c *config = pinconf_to_config_packed(param, regval); regval 800 drivers/pinctrl/pinctrl-artpec6.c unsigned int regval; regval 825 drivers/pinctrl/pinctrl-artpec6.c regval = readl(reg); regval 826 drivers/pinctrl/pinctrl-artpec6.c regval |= (1 << ARTPEC6_PINMUX_UDC1_SHIFT); regval 827 drivers/pinctrl/pinctrl-artpec6.c writel(regval, reg); regval 837 drivers/pinctrl/pinctrl-artpec6.c regval = readl(reg); regval 838 drivers/pinctrl/pinctrl-artpec6.c regval |= (arg << ARTPEC6_PINMUX_UDC0_SHIFT); regval 839 drivers/pinctrl/pinctrl-artpec6.c regval &= ~ARTPEC6_PINMUX_UDC1_MASK; /* Enable */ regval 840 drivers/pinctrl/pinctrl-artpec6.c writel(regval, reg); regval 850 drivers/pinctrl/pinctrl-artpec6.c regval = readl(reg); regval 851 drivers/pinctrl/pinctrl-artpec6.c regval &= ~(arg << ARTPEC6_PINMUX_UDC0_SHIFT); regval 852 drivers/pinctrl/pinctrl-artpec6.c regval &= ~ARTPEC6_PINMUX_UDC1_MASK; /* Enable */ regval 853 drivers/pinctrl/pinctrl-artpec6.c writel(regval, reg); regval 864 drivers/pinctrl/pinctrl-artpec6.c regval = readl(reg); regval 865 drivers/pinctrl/pinctrl-artpec6.c regval &= ~ARTPEC6_PINMUX_DRV_MASK; regval 866 drivers/pinctrl/pinctrl-artpec6.c regval |= (drive << ARTPEC6_PINMUX_DRV_SHIFT); regval 867 drivers/pinctrl/pinctrl-artpec6.c writel(regval, reg); regval 993 drivers/pinctrl/pinctrl-bm1880.c u32 regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + regval 996 drivers/pinctrl/pinctrl-bm1880.c regval &= ~(0x03 << mux_offset); regval 997 drivers/pinctrl/pinctrl-bm1880.c regval |= func->mux_val << mux_offset; regval 999 drivers/pinctrl/pinctrl-bm1880.c writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset); regval 1014 drivers/pinctrl/pinctrl-bm1880.c u32 *regval, u32 bit_offset) regval 1018 drivers/pinctrl/pinctrl-bm1880.c _regval = *regval; regval 1084 drivers/pinctrl/pinctrl-bm1880.c *regval = _regval; regval 1155 drivers/pinctrl/pinctrl-bm1880.c u32 regval, offset, bit_offset; regval 1159 drivers/pinctrl/pinctrl-bm1880.c regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset); regval 1164 drivers/pinctrl/pinctrl-bm1880.c arg = !!(regval & BIT(bit_offset)); regval 1168 drivers/pinctrl/pinctrl-bm1880.c arg = !!(regval & BIT(bit_offset)); regval 1172 drivers/pinctrl/pinctrl-bm1880.c arg = !!(regval & BIT(bit_offset)); regval 1176 drivers/pinctrl/pinctrl-bm1880.c arg = !!(regval & BIT(bit_offset)); regval 1180 drivers/pinctrl/pinctrl-bm1880.c arg = !!(regval & BIT(bit_offset)); regval 1185 drivers/pinctrl/pinctrl-bm1880.c !!(regval & BIT(bit_offset))); regval 1206 drivers/pinctrl/pinctrl-bm1880.c u32 regval, offset, bit_offset; regval 1210 drivers/pinctrl/pinctrl-bm1880.c regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset); regval 1219 drivers/pinctrl/pinctrl-bm1880.c regval |= BIT(bit_offset); regval 1223 drivers/pinctrl/pinctrl-bm1880.c regval |= BIT(bit_offset); regval 1227 drivers/pinctrl/pinctrl-bm1880.c regval |= BIT(bit_offset); regval 1232 drivers/pinctrl/pinctrl-bm1880.c regval |= BIT(bit_offset); regval 1234 drivers/pinctrl/pinctrl-bm1880.c regval &= ~BIT(bit_offset); regval 1239 drivers/pinctrl/pinctrl-bm1880.c regval |= BIT(bit_offset); regval 1241 drivers/pinctrl/pinctrl-bm1880.c regval &= ~BIT(bit_offset); regval 1247 drivers/pinctrl/pinctrl-bm1880.c ®val, bit_offset); regval 1259 drivers/pinctrl/pinctrl-bm1880.c writel_relaxed(regval, pctrl->base + BM1880_REG_MUX + offset); regval 938 drivers/pinctrl/pinctrl-u300.c u16 regval, val, mask; regval 951 drivers/pinctrl/pinctrl-u300.c regval = readw(upmx->virtbase + u300_pmx_registers[i]); regval 952 drivers/pinctrl/pinctrl-u300.c regval &= ~mask; regval 953 drivers/pinctrl/pinctrl-u300.c regval |= val; regval 954 drivers/pinctrl/pinctrl-u300.c writew(regval, upmx->virtbase + u300_pmx_registers[i]); regval 868 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 regval; regval 872 drivers/pinctrl/sunxi/pinctrl-sunxi.c regval = readl(pctl->membase + reg); regval 875 drivers/pinctrl/sunxi/pinctrl-sunxi.c regval |= BIT(index); regval 877 drivers/pinctrl/sunxi/pinctrl-sunxi.c regval &= ~(BIT(index)); regval 879 drivers/pinctrl/sunxi/pinctrl-sunxi.c writel(regval, pctl->membase + reg); regval 970 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 regval; regval 1002 drivers/pinctrl/sunxi/pinctrl-sunxi.c regval = readl(pctl->membase + reg); regval 1003 drivers/pinctrl/sunxi/pinctrl-sunxi.c regval &= ~(IRQ_CFG_IRQ_MASK << index); regval 1004 drivers/pinctrl/sunxi/pinctrl-sunxi.c writel(regval | (mode << index), pctl->membase + reg); regval 374 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c u32 regval; regval 388 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c regval = padctl_readl(padctl, lane->offset); regval 391 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c regval &= ~BIT(lane->iddq); regval 393 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c regval |= BIT(lane->iddq); regval 395 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c padctl_writel(padctl, regval, lane->offset); regval 167 drivers/platform/mellanox/mlxreg-hotplug.c u32 regval; regval 174 drivers/platform/mellanox/mlxreg-hotplug.c ret = regmap_read(priv->regmap, data->reg, ®val); regval 179 drivers/platform/mellanox/mlxreg-hotplug.c regval &= data->mask; regval 183 drivers/platform/mellanox/mlxreg-hotplug.c regval = !(regval & data->mask); regval 185 drivers/platform/mellanox/mlxreg-hotplug.c regval = !!(regval & data->mask); regval 188 drivers/platform/mellanox/mlxreg-hotplug.c return sprintf(buf, "%u\n", regval); regval 252 drivers/platform/mellanox/mlxreg-hotplug.c u32 regval, bit; regval 276 drivers/platform/mellanox/mlxreg-hotplug.c ret = regmap_read(priv->regmap, item->reg, ®val); regval 281 drivers/platform/mellanox/mlxreg-hotplug.c regval &= item->mask; regval 282 drivers/platform/mellanox/mlxreg-hotplug.c asserted = item->cache ^ regval; regval 283 drivers/platform/mellanox/mlxreg-hotplug.c item->cache = regval; regval 287 drivers/platform/mellanox/mlxreg-hotplug.c if (regval & BIT(bit)) { regval 320 drivers/platform/mellanox/mlxreg-hotplug.c u32 regval; regval 331 drivers/platform/mellanox/mlxreg-hotplug.c ret = regmap_read(priv->regmap, data->reg, ®val); regval 335 drivers/platform/mellanox/mlxreg-hotplug.c regval &= data->mask; regval 337 drivers/platform/mellanox/mlxreg-hotplug.c if (item->cache == regval) regval 347 drivers/platform/mellanox/mlxreg-hotplug.c if (regval == MLXREG_HOTPLUG_GOOD_HEALTH_MASK) { regval 368 drivers/platform/mellanox/mlxreg-hotplug.c item->cache = regval; regval 420 drivers/platform/mellanox/mlxreg-hotplug.c u32 regval, aggr_asserted; regval 436 drivers/platform/mellanox/mlxreg-hotplug.c ret = regmap_read(priv->regmap, pdata->cell, ®val); regval 440 drivers/platform/mellanox/mlxreg-hotplug.c regval &= pdata->mask; regval 441 drivers/platform/mellanox/mlxreg-hotplug.c aggr_asserted = priv->aggr_cache ^ regval; regval 442 drivers/platform/mellanox/mlxreg-hotplug.c priv->aggr_cache = regval; regval 500 drivers/platform/mellanox/mlxreg-hotplug.c u32 regval; regval 523 drivers/platform/mellanox/mlxreg-hotplug.c data->capability, ®val); regval 527 drivers/platform/mellanox/mlxreg-hotplug.c if (!(regval & data->bit)) regval 46 drivers/platform/mellanox/mlxreg-io.c bool rw_flag, u32 *regval) regval 50 drivers/platform/mellanox/mlxreg-io.c ret = regmap_read(regmap, data->reg, regval); regval 68 drivers/platform/mellanox/mlxreg-io.c *regval = !!(*regval & ~data->mask); regval 71 drivers/platform/mellanox/mlxreg-io.c *regval &= data->mask; regval 73 drivers/platform/mellanox/mlxreg-io.c *regval |= ~data->mask; regval 79 drivers/platform/mellanox/mlxreg-io.c *regval = ror32(*regval & data->mask, (data->bit - 1)); regval 84 drivers/platform/mellanox/mlxreg-io.c *regval = (*regval & ~data->mask) | in_val; regval 99 drivers/platform/mellanox/mlxreg-io.c u32 regval = 0; regval 102 drivers/platform/mellanox/mlxreg-io.c ret = mlxreg_io_get_reg(priv->pdata->regmap, data, 0, true, ®val); regval 106 drivers/platform/mellanox/mlxreg-io.c return sprintf(buf, "%u\n", regval); regval 119 drivers/platform/mellanox/mlxreg-io.c u32 input_val, regval; regval 131 drivers/platform/mellanox/mlxreg-io.c ®val); regval 135 drivers/platform/mellanox/mlxreg-io.c ret = regmap_write(priv->pdata->regmap, data->reg, regval); regval 178 drivers/power/supply/adp5061.c unsigned int regval; regval 181 drivers/power/supply/adp5061.c ret = regmap_read(st->regmap, ADP5061_VINX_SET, ®val); regval 185 drivers/power/supply/adp5061.c mode = ADP5061_VINX_SET_ILIM_MODE(regval); regval 228 drivers/power/supply/adp5061.c unsigned int regval; regval 231 drivers/power/supply/adp5061.c ret = regmap_read(st->regmap, ADP5061_VOLTAGE_TH, ®val); regval 235 drivers/power/supply/adp5061.c regval = ((regval & ADP5061_VOLTAGE_TH_VTRK_DEAD_MSK) >> 3); regval 236 drivers/power/supply/adp5061.c val->intval = adp5061_vmin[regval] * 1000; regval 244 drivers/power/supply/adp5061.c unsigned int regval; regval 247 drivers/power/supply/adp5061.c ret = regmap_read(st->regmap, ADP5061_TERM_SET, ®val); regval 251 drivers/power/supply/adp5061.c mode = ADP5061_TERM_SET_CHG_VLIM_MODE(regval); regval 260 drivers/power/supply/adp5061.c unsigned int regval; regval 263 drivers/power/supply/adp5061.c ret = regmap_read(st->regmap, ADP5061_TERM_SET, ®val); regval 267 drivers/power/supply/adp5061.c regval = ((regval & ADP5061_TERM_SET_VTRM_MSK) >> 2) - 0x0F; regval 268 drivers/power/supply/adp5061.c if (regval >= ARRAY_SIZE(adp5061_vmax)) regval 269 drivers/power/supply/adp5061.c regval = ARRAY_SIZE(adp5061_vmax) - 1; regval 271 drivers/power/supply/adp5061.c val->intval = adp5061_vmax[regval] * 1000; regval 338 drivers/power/supply/adp5061.c unsigned int regval; regval 341 drivers/power/supply/adp5061.c ret = regmap_read(st->regmap, ADP5061_CHG_CURR, ®val); regval 345 drivers/power/supply/adp5061.c regval = ((regval & ADP5061_CHG_CURR_ICHG_MSK) >> 2); regval 346 drivers/power/supply/adp5061.c if (regval >= ARRAY_SIZE(adp5061_const_ichg)) regval 347 drivers/power/supply/adp5061.c regval = ARRAY_SIZE(adp5061_const_ichg) - 1; regval 349 drivers/power/supply/adp5061.c val->intval = adp5061_const_ichg[regval] * 1000; regval 357 drivers/power/supply/adp5061.c unsigned int regval; regval 360 drivers/power/supply/adp5061.c ret = regmap_read(st->regmap, ADP5061_CHG_CURR, ®val); regval 364 drivers/power/supply/adp5061.c regval &= ADP5061_CHG_CURR_ITRK_DEAD_MSK; regval 365 drivers/power/supply/adp5061.c val->intval = adp5061_prechg_current[regval] * 1000; regval 390 drivers/power/supply/adp5061.c unsigned int regval; regval 393 drivers/power/supply/adp5061.c ret = regmap_read(st->regmap, ADP5061_VOLTAGE_TH, ®val); regval 397 drivers/power/supply/adp5061.c regval &= ADP5061_VOLTAGE_TH_VWEAK_MSK; regval 398 drivers/power/supply/adp5061.c val->intval = adp5061_vweak_th[regval] * 1000; regval 504 drivers/power/supply/adp5061.c unsigned int regval; regval 507 drivers/power/supply/adp5061.c ret = regmap_read(st->regmap, ADP5061_IEND, ®val); regval 511 drivers/power/supply/adp5061.c regval = (regval & ADP5061_IEND_IEND_MSK) >> 5; regval 512 drivers/power/supply/adp5061.c val->intval = adp5061_iend[regval]; regval 97 drivers/power/supply/sbs-manager.c int regval = 0; regval 101 drivers/power/supply/sbs-manager.c regval = sbsm_read_word(data->client, SBSM_CMD_BATSYSSTATECONT); regval 102 drivers/power/supply/sbs-manager.c if (regval < 0) regval 103 drivers/power/supply/sbs-manager.c return regval; regval 104 drivers/power/supply/sbs-manager.c val->intval = !!(regval & SBSM_BIT_AC_PRESENT); regval 108 drivers/power/supply/sbs-manager.c regval = sbsm_read_word(data->client, SBSM_CMD_BATSYSSTATE); regval 109 drivers/power/supply/sbs-manager.c if (regval < 0) regval 110 drivers/power/supply/sbs-manager.c return regval; regval 112 drivers/power/supply/sbs-manager.c if ((regval & SBSM_MASK_CHARGE_BAT) == 0) { regval 120 drivers/power/supply/sbs-manager.c regval = sbsm_read_word(data->client, SBSM_CMD_LTC); regval 121 drivers/power/supply/sbs-manager.c if (regval < 0) regval 122 drivers/power/supply/sbs-manager.c return regval; regval 123 drivers/power/supply/sbs-manager.c else if (regval & SBSM_BIT_TURBO) regval 149 drivers/power/supply/sbs-manager.c u16 regval; regval 156 drivers/power/supply/sbs-manager.c regval = val->intval == regval 158 drivers/power/supply/sbs-manager.c ret = sbsm_write_word(data->client, SBSM_CMD_LTC, regval); regval 215 drivers/power/supply/twl4030_charger.c static int regval2ua(int regval, bool cgain) regval 218 drivers/power/supply/twl4030_charger.c return (regval * 16618 - 8500 * 1000) / 5; regval 220 drivers/power/supply/twl4030_charger.c return (regval * 16618 - 8500 * 1000) / 10; regval 444 drivers/power/supply/ucs1002_power.c int ret, regval; regval 450 drivers/power/supply/ucs1002_power.c ret = regmap_read(info->regmap, UCS1002_REG_OTHER_STATUS, ®val); regval 455 drivers/power/supply/ucs1002_power.c info->present = regval & F_ADET_PIN; regval 504 drivers/power/supply/ucs1002_power.c unsigned int regval; regval 525 drivers/power/supply/ucs1002_power.c ret = regmap_read(info->regmap, UCS1002_REG_PRODUCT_ID, ®val); regval 531 drivers/power/supply/ucs1002_power.c if (regval != UCS1002_PRODUCT_ID) { regval 534 drivers/power/supply/ucs1002_power.c regval, UCS1002_PRODUCT_ID); regval 574 drivers/power/supply/ucs1002_power.c ret = regmap_read(info->regmap, UCS1002_REG_PIN_STATUS, ®val); regval 587 drivers/power/supply/ucs1002_power.c info->regulator_descriptor->enable_is_inverted = !(regval & F_SEL_PIN); regval 368 drivers/rapidio/devices/tsi721.c u32 regval; regval 371 drivers/rapidio/devices/tsi721.c regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); regval 372 drivers/rapidio/devices/tsi721.c regval &= ~TSI721_SR_CHINT_IDBQRCV; regval 373 drivers/rapidio/devices/tsi721.c iowrite32(regval, regval 390 drivers/rapidio/devices/tsi721.c u32 regval; regval 439 drivers/rapidio/devices/tsi721.c regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); regval 440 drivers/rapidio/devices/tsi721.c regval |= TSI721_SR_CHINT_IDBQRCV; regval 441 drivers/rapidio/devices/tsi721.c iowrite32(regval, regval 1091 drivers/rapidio/devices/tsi721.c u32 regval; regval 1187 drivers/rapidio/devices/tsi721.c regval = ioread32(priv->regs + TSI721_IBWIN_LB(i)); regval 1188 drivers/rapidio/devices/tsi721.c if (WARN_ON(regval & TSI721_IBWIN_LB_WEN)) { regval 528 drivers/rapidio/rio-scan.c u32 regval; regval 544 drivers/rapidio/rio-scan.c hopcount, RIO_COMPONENT_TAG_CSR, ®val); regval 546 drivers/rapidio/rio-scan.c if (regval) { regval 547 drivers/rapidio/rio-scan.c rdev = rio_get_comptag((regval & 0xffff), NULL); regval 708 drivers/rapidio/rio-scan.c u32 regval; regval 711 drivers/rapidio/rio-scan.c ®val); regval 712 drivers/rapidio/rio-scan.c return (regval & RIO_PORT_GEN_DISCOVERED) ? 1 : 0; regval 869 drivers/rapidio/rio.c u32 regval; regval 873 drivers/rapidio/rio.c ®val); regval 875 drivers/rapidio/rio.c regval |= RIO_PORT_N_CTL_LOCKOUT; regval 877 drivers/rapidio/rio.c regval &= ~RIO_PORT_N_CTL_LOCKOUT; regval 881 drivers/rapidio/rio.c regval); regval 903 drivers/rapidio/rio.c u32 regval; regval 919 drivers/rapidio/rio.c ®val); regval 923 drivers/rapidio/rio.c ®val) < 0) regval 927 drivers/rapidio/rio.c regval = regval | RIO_PORT_N_CTL_EN_RX | RIO_PORT_N_CTL_EN_TX; regval 931 drivers/rapidio/rio.c ext_ftr_ptr + RIO_PORT_N_CTL_CSR(0, rmap), regval); regval 935 drivers/rapidio/rio.c regval) < 0) regval 1030 drivers/rapidio/rio.c u32 regval; regval 1038 drivers/rapidio/rio.c ®val); regval 1056 drivers/rapidio/rio.c ®val); regval 1057 drivers/rapidio/rio.c if (regval & RIO_PORT_N_MNT_RSP_RVAL) { regval 1058 drivers/rapidio/rio.c *lnkresp = regval; regval 1082 drivers/rapidio/rio.c u32 regval; regval 1095 drivers/rapidio/rio.c if (rio_get_input_status(rdev, pnum, ®val)) { regval 1101 drivers/rapidio/rio.c pnum, regval); regval 1102 drivers/rapidio/rio.c far_ackid = (regval & RIO_PORT_N_MNT_RSP_ASTAT) >> 5; regval 1103 drivers/rapidio/rio.c far_linkstat = regval & RIO_PORT_N_MNT_RSP_LSTAT; regval 1106 drivers/rapidio/rio.c ®val); regval 1107 drivers/rapidio/rio.c pr_debug("RIO_EM: SP%d_ACK_STS_CSR=0x%08x\n", pnum, regval); regval 1108 drivers/rapidio/rio.c near_ackid = (regval & RIO_PORT_N_ACK_INBOUND) >> 24; regval 1117 drivers/rapidio/rio.c if ((far_ackid != ((regval & RIO_PORT_N_ACK_OUTSTAND) >> 8)) || regval 1118 drivers/rapidio/rio.c (far_ackid != (regval & RIO_PORT_N_ACK_OUTBOUND))) { regval 199 drivers/rapidio/switches/idt_gen2.c u32 regval; regval 205 drivers/rapidio/switches/idt_gen2.c IDT_RIO_DOMAIN, ®val); regval 207 drivers/rapidio/switches/idt_gen2.c *sw_domain = (u8)(regval & 0xff); regval 215 drivers/rapidio/switches/idt_gen2.c u32 regval; regval 240 drivers/rapidio/switches/idt_gen2.c rio_read_config_32(rdev, IDT_DEV_CTRL_1, ®val); regval 242 drivers/rapidio/switches/idt_gen2.c regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH); regval 258 drivers/rapidio/switches/idt_gen2.c rio_read_config_32(rdev, IDT_PORT_OPS(i), ®val); regval 260 drivers/rapidio/switches/idt_gen2.c IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW | regval 280 drivers/rapidio/switches/idt_gen2.c rio_read_config_32(rdev, IDT_LANE_CTRL(i), ®val); regval 282 drivers/rapidio/switches/idt_gen2.c regval | IDT_LANE_CTRL_GENPW); regval 299 drivers/rapidio/switches/idt_gen2.c rio_read_config_32(rdev, IDT_I2C_MCTRL, ®val); regval 300 drivers/rapidio/switches/idt_gen2.c rio_write_config_32(rdev, IDT_I2C_MCTRL, regval & ~IDT_I2C_MCTRL_GENPW); regval 310 drivers/rapidio/switches/idt_gen2.c rio_read_config_32(rdev, IDT_CFGBLK_ERR_REPORT, ®val); regval 312 drivers/rapidio/switches/idt_gen2.c regval & ~IDT_CFGBLK_ERR_REPORT_GENPW); regval 324 drivers/rapidio/switches/idt_gen2.c u32 regval, em_perrdet, em_ltlerrdet; regval 333 drivers/rapidio/switches/idt_gen2.c IDT_ISLTL_ADDRESS_CAP, ®val); regval 337 drivers/rapidio/switches/idt_gen2.c rio_name(rdev), em_ltlerrdet, regval); regval 354 drivers/rapidio/switches/idt_gen2.c IDT_PORT_ISERR_DET(portnum), ®val); regval 357 drivers/rapidio/switches/idt_gen2.c " errors 0x%x\n", rio_name(rdev), regval); regval 373 drivers/rapidio/switches/idt_gen2.c u32 regval; regval 375 drivers/rapidio/switches/idt_gen2.c while (!rio_read_config_32(rdev, IDT_ERR_RD, ®val)) { regval 376 drivers/rapidio/switches/idt_gen2.c if (!regval) /* 0 = end of log */ regval 379 drivers/rapidio/switches/idt_gen2.c "%08x\n", regval); regval 105 drivers/rapidio/switches/idtcps.c u32 regval; regval 111 drivers/rapidio/switches/idtcps.c IDTCPS_RIO_DOMAIN, ®val); regval 113 drivers/rapidio/switches/idtcps.c *sw_domain = (u8)(regval & 0xff); regval 113 drivers/rapidio/switches/tsi568.c u32 regval; regval 121 drivers/rapidio/switches/tsi568.c rio_read_config_32(rdev, TSI568_SP_MODE(portnum), ®val); regval 123 drivers/rapidio/switches/tsi568.c regval | TSI568_SP_MODE_PW_DIS); regval 120 drivers/rapidio/switches/tsi57x.c u32 regval; regval 128 drivers/rapidio/switches/tsi57x.c TSI578_SP_MODE_GLBL, ®val); regval 130 drivers/rapidio/switches/tsi57x.c regval & ~TSI578_SP_MODE_LUT_512); regval 142 drivers/rapidio/switches/tsi57x.c u32 regval; regval 148 drivers/rapidio/switches/tsi57x.c TSI578_GLBL_ROUTE_BASE, ®val); regval 150 drivers/rapidio/switches/tsi57x.c *sw_domain = (u8)(regval >> 24); regval 158 drivers/rapidio/switches/tsi57x.c u32 regval; regval 167 drivers/rapidio/switches/tsi57x.c TSI578_SP_MODE(portnum), ®val); regval 170 drivers/rapidio/switches/tsi57x.c regval & ~TSI578_SP_MODE_PW_DIS); regval 175 drivers/rapidio/switches/tsi57x.c ®val); regval 178 drivers/rapidio/switches/tsi57x.c regval & 0x07120214); regval 181 drivers/rapidio/switches/tsi57x.c TSI578_SP_INT_STATUS(portnum), ®val); regval 184 drivers/rapidio/switches/tsi57x.c regval & 0x000700bd); regval 188 drivers/rapidio/switches/tsi57x.c TSI578_SP_CTL_INDEP(portnum), ®val); regval 191 drivers/rapidio/switches/tsi57x.c regval | 0x000b0000); regval 196 drivers/rapidio/switches/tsi57x.c ®val); regval 197 drivers/rapidio/switches/tsi57x.c if ((regval & RIO_PORT_N_CTL_PWIDTH) == RIO_PORT_N_CTL_PWIDTH_4) regval 215 drivers/rapidio/switches/tsi57x.c u32 regval; regval 227 drivers/rapidio/switches/tsi57x.c ®val); regval 228 drivers/rapidio/switches/tsi57x.c if (!(regval & RIO_PORT_N_CTL_LOCKOUT)) { regval 231 drivers/rapidio/switches/tsi57x.c regval | RIO_PORT_N_CTL_LOCKOUT); regval 235 drivers/rapidio/switches/tsi57x.c regval); regval 243 drivers/rapidio/switches/tsi57x.c ®val); regval 258 drivers/rapidio/switches/tsi57x.c ®val); regval 259 drivers/rapidio/switches/tsi57x.c if (regval & RIO_PORT_N_MNT_RSP_RVAL) regval 275 drivers/rapidio/switches/tsi57x.c TSI578_SP_LUT_PEINF(portnum), ®val); regval 276 drivers/rapidio/switches/tsi57x.c regval = (mport->sys_size) ? (regval >> 16) : (regval >> 24); regval 277 drivers/rapidio/switches/tsi57x.c route_port = rdev->rswitch->route_table[regval]; regval 279 drivers/rapidio/switches/tsi57x.c rio_name(rdev), portnum, regval); regval 281 drivers/rapidio/switches/tsi57x.c RIO_GLOBAL_TABLE, regval, route_port); regval 162 drivers/regulator/ab3100.c u8 regval; regval 165 drivers/regulator/ab3100.c ®val); regval 173 drivers/regulator/ab3100.c if (regval & AB3100_REG_ON_MASK) regval 176 drivers/regulator/ab3100.c regval |= AB3100_REG_ON_MASK; regval 179 drivers/regulator/ab3100.c regval); regval 193 drivers/regulator/ab3100.c u8 regval; regval 211 drivers/regulator/ab3100.c ®val); regval 217 drivers/regulator/ab3100.c regval &= ~AB3100_REG_ON_MASK; regval 219 drivers/regulator/ab3100.c regval); regval 225 drivers/regulator/ab3100.c u8 regval; regval 229 drivers/regulator/ab3100.c ®val); regval 236 drivers/regulator/ab3100.c return regval & AB3100_REG_ON_MASK; regval 242 drivers/regulator/ab3100.c u8 regval; regval 250 drivers/regulator/ab3100.c abreg->regreg, ®val); regval 259 drivers/regulator/ab3100.c regval &= 0xE0; regval 260 drivers/regulator/ab3100.c regval >>= 5; regval 262 drivers/regulator/ab3100.c if (regval >= reg->desc->n_voltages) { regval 269 drivers/regulator/ab3100.c return reg->desc->volt_table[regval]; regval 276 drivers/regulator/ab3100.c u8 regval; regval 280 drivers/regulator/ab3100.c abreg->regreg, ®val); regval 289 drivers/regulator/ab3100.c regval &= ~0xE0; regval 290 drivers/regulator/ab3100.c regval |= (selector << 5); regval 293 drivers/regulator/ab3100.c abreg->regreg, regval); regval 305 drivers/regulator/ab3100.c u8 regval; regval 321 drivers/regulator/ab3100.c targetreg, ®val); regval 330 drivers/regulator/ab3100.c regval &= ~0xE0; regval 331 drivers/regulator/ab3100.c regval |= (bestindex << 5); regval 334 drivers/regulator/ab3100.c targetreg, regval); regval 510 drivers/regulator/ab8500-ext.c u8 regval; regval 522 drivers/regulator/ab8500-ext.c regval = info->update_val_hp; regval 524 drivers/regulator/ab8500-ext.c regval = info->update_val; regval 528 drivers/regulator/ab8500-ext.c info->update_mask, regval); regval 538 drivers/regulator/ab8500-ext.c info->update_mask, regval); regval 547 drivers/regulator/ab8500-ext.c u8 regval; regval 558 drivers/regulator/ab8500-ext.c regval = info->update_val_hw; regval 560 drivers/regulator/ab8500-ext.c regval = 0; regval 564 drivers/regulator/ab8500-ext.c info->update_mask, regval); regval 574 drivers/regulator/ab8500-ext.c info->update_mask, regval); regval 583 drivers/regulator/ab8500-ext.c u8 regval; regval 591 drivers/regulator/ab8500-ext.c info->update_bank, info->update_reg, ®val); regval 601 drivers/regulator/ab8500-ext.c info->update_mask, regval); regval 603 drivers/regulator/ab8500-ext.c if (((regval & info->update_mask) == info->update_val_lp) || regval 604 drivers/regulator/ab8500-ext.c ((regval & info->update_mask) == info->update_val_hp)) regval 615 drivers/regulator/ab8500-ext.c u8 regval; regval 624 drivers/regulator/ab8500-ext.c regval = info->update_val_hp; regval 627 drivers/regulator/ab8500-ext.c regval = info->update_val_lp; regval 642 drivers/regulator/ab8500-ext.c info->update_mask, regval); regval 653 drivers/regulator/ab8500-ext.c info->update_mask, regval); regval 656 drivers/regulator/ab8500-ext.c info->update_val = regval; regval 264 drivers/regulator/ab8500.c u8 regval; regval 272 drivers/regulator/ab8500.c info->update_bank, info->update_reg, ®val); regval 283 drivers/regulator/ab8500.c info->update_mask, regval); regval 285 drivers/regulator/ab8500.c if (regval & info->update_mask) regval 451 drivers/regulator/ab8500.c u8 regval; regval 461 drivers/regulator/ab8500.c info->voltage_bank, info->voltage_reg, ®val); regval 473 drivers/regulator/ab8500.c voltage_shift, regval); regval 475 drivers/regulator/ab8500.c return (regval & info->voltage_mask) >> voltage_shift; regval 483 drivers/regulator/ab8500.c u8 regval; regval 493 drivers/regulator/ab8500.c regval = (u8)selector << voltage_shift; regval 496 drivers/regulator/ab8500.c info->voltage_mask, regval); regval 505 drivers/regulator/ab8500.c info->voltage_mask, regval); regval 194 drivers/regulator/fan53555.c int regval = -1, i; regval 198 drivers/regulator/fan53555.c regval = i; regval 203 drivers/regulator/fan53555.c if (regval < 0) { regval 209 drivers/regulator/fan53555.c CTL_SLEW_MASK, regval << CTL_SLEW_SHIFT); regval 92 drivers/regulator/lp8755.c unsigned int regval; regval 96 drivers/regulator/lp8755.c ret = lp8755_read(pchip, 0x12 + id, ®val); regval 101 drivers/regulator/lp8755.c return (regval & 0xff) * 100; regval 150 drivers/regulator/lp8755.c unsigned int regval; regval 154 drivers/regulator/lp8755.c ret = lp8755_read(pchip, 0x06, ®val); regval 159 drivers/regulator/lp8755.c if (regval & (0x01 << id)) regval 162 drivers/regulator/lp8755.c ret = lp8755_read(pchip, 0x08 + id, ®val); regval 167 drivers/regulator/lp8755.c if (regval & 0x20) regval 181 drivers/regulator/lp8755.c unsigned int regval = 0x00; regval 188 drivers/regulator/lp8755.c regval = 0x07; regval 191 drivers/regulator/lp8755.c regval = 0x06; regval 194 drivers/regulator/lp8755.c regval = 0x05; regval 197 drivers/regulator/lp8755.c regval = 0x04; regval 200 drivers/regulator/lp8755.c regval = 0x03; regval 203 drivers/regulator/lp8755.c regval = 0x02; regval 206 drivers/regulator/lp8755.c regval = 0x01; regval 209 drivers/regulator/lp8755.c regval = 0x00; regval 217 drivers/regulator/lp8755.c ret = lp8755_update_bits(pchip, 0x07 + id, 0x07, regval); regval 276 drivers/regulator/lp8755.c unsigned int regval; regval 281 drivers/regulator/lp8755.c ret = lp8755_read(pchip, 0x3D, ®val); regval 284 drivers/regulator/lp8755.c pchip->mphase = regval & 0x0F; regval 419 drivers/regulator/lp8755.c unsigned int regval; regval 426 drivers/regulator/lp8755.c ret = lp8755_read(pchip, 0x0F, ®val); regval 432 drivers/regulator/lp8755.c pchip->irqmask = regval; regval 160 drivers/regulator/mt6323-regulator.c u32 regval; regval 163 drivers/regulator/mt6323-regulator.c ret = regmap_read(rdev->regmap, info->desc.enable_reg, ®val); regval 169 drivers/regulator/mt6323-regulator.c return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF; regval 347 drivers/regulator/mt6323-regulator.c u32 regval; regval 353 drivers/regulator/mt6323-regulator.c ®val) < 0) { regval 359 drivers/regulator/mt6323-regulator.c if (regval & mt6323_regulators[i].vselctrl_mask) { regval 297 drivers/regulator/mt6358-regulator.c int ret, regval; regval 300 drivers/regulator/mt6358-regulator.c ret = regmap_read(rdev->regmap, info->da_vsel_reg, ®val); regval 308 drivers/regulator/mt6358-regulator.c ret = (regval >> info->da_vsel_shift) & info->da_vsel_mask; regval 316 drivers/regulator/mt6358-regulator.c u32 regval; regval 319 drivers/regulator/mt6358-regulator.c ret = regmap_read(rdev->regmap, info->status_reg, ®val); regval 325 drivers/regulator/mt6358-regulator.c return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF; regval 358 drivers/regulator/mt6358-regulator.c int ret, regval; regval 360 drivers/regulator/mt6358-regulator.c ret = regmap_read(rdev->regmap, info->modeset_reg, ®val); regval 367 drivers/regulator/mt6358-regulator.c switch ((regval & info->modeset_mask) >> info->modeset_shift) { regval 187 drivers/regulator/mt6397-regulator.c int ret, regval; regval 189 drivers/regulator/mt6397-regulator.c ret = regmap_read(rdev->regmap, info->modeset_reg, ®val); regval 196 drivers/regulator/mt6397-regulator.c switch ((regval & info->modeset_mask) >> info->modeset_shift) { regval 209 drivers/regulator/mt6397-regulator.c u32 regval; regval 212 drivers/regulator/mt6397-regulator.c ret = regmap_read(rdev->regmap, info->desc.enable_reg, ®val); regval 218 drivers/regulator/mt6397-regulator.c return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF; regval 315 drivers/regulator/mt6397-regulator.c u32 regval; regval 321 drivers/regulator/mt6397-regulator.c ®val) < 0) { regval 327 drivers/regulator/mt6397-regulator.c if (regval & mt6397_regulators[i].vselctrl_mask) { regval 204 drivers/rtc/rtc-ab3100.c u8 regval; regval 209 drivers/rtc/rtc-ab3100.c AB3100_RTC, ®val); regval 215 drivers/rtc/rtc-ab3100.c if ((regval & 0xFE) != RTC_SETTING) { regval 217 drivers/rtc/rtc-ab3100.c regval); regval 220 drivers/rtc/rtc-ab3100.c if ((regval & 1) == 0) { regval 225 drivers/rtc/rtc-ab3100.c regval = 1 | RTC_SETTING; regval 227 drivers/rtc/rtc-ab3100.c AB3100_RTC, regval); regval 90 drivers/sbus/char/display7seg.c u8 regval = 0; regval 92 drivers/sbus/char/display7seg.c regval = readb(p->regs); regval 94 drivers/sbus/char/display7seg.c regval |= D7S_FLIP; regval 96 drivers/sbus/char/display7seg.c regval &= ~D7S_FLIP; regval 97 drivers/sbus/char/display7seg.c writeb(regval, p->regs); regval 1223 drivers/scsi/pm8001/pm80xx_hwi.c u32 regval; regval 1231 drivers/scsi/pm8001/pm80xx_hwi.c regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); regval 1234 drivers/scsi/pm8001/pm80xx_hwi.c regval)); regval 1239 drivers/scsi/pm8001/pm80xx_hwi.c regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); regval 1241 drivers/scsi/pm8001/pm80xx_hwi.c pm8001_printk("reset register before write : 0x%x\n", regval)); regval 1246 drivers/scsi/pm8001/pm80xx_hwi.c regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); regval 1248 drivers/scsi/pm8001/pm80xx_hwi.c pm8001_printk("reset register after write 0x%x\n", regval)); regval 1250 drivers/scsi/pm8001/pm80xx_hwi.c if ((regval & SPCv_SOFT_RESET_READ_MASK) == regval 1254 drivers/scsi/pm8001/pm80xx_hwi.c regval)); regval 1258 drivers/scsi/pm8001/pm80xx_hwi.c regval)); regval 3816 drivers/scsi/pm8001/pm80xx_hwi.c u32 regval; regval 3819 drivers/scsi/pm8001/pm80xx_hwi.c regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); regval 3820 drivers/scsi/pm8001/pm80xx_hwi.c if ((regval & SCRATCH_PAD_MIPSALL_READY) != regval 3824 drivers/scsi/pm8001/pm80xx_hwi.c "Firmware Fatal error! Regval:0x%x\n", regval)); regval 586 drivers/spi/spi-fsl-espi.c u32 regval; regval 588 drivers/spi/spi-fsl-espi.c regval = fsl_espi_read_reg(espi, ESPI_SPMODE); regval 589 drivers/spi/spi-fsl-espi.c regval &= ~SPMODE_ENABLE; regval 590 drivers/spi/spi-fsl-espi.c fsl_espi_write_reg(espi, ESPI_SPMODE, regval); regval 599 drivers/spi/spi-fsl-espi.c u32 regval; regval 601 drivers/spi/spi-fsl-espi.c regval = fsl_espi_read_reg(espi, ESPI_SPMODE); regval 602 drivers/spi/spi-fsl-espi.c regval |= SPMODE_ENABLE; regval 603 drivers/spi/spi-fsl-espi.c fsl_espi_write_reg(espi, ESPI_SPMODE, regval); regval 599 drivers/spi/spi-fsl-spi.c u32 regval; regval 662 drivers/spi/spi-fsl-spi.c regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; regval 664 drivers/spi/spi-fsl-spi.c regval &= ~SPMODE_LEN(0xF); regval 665 drivers/spi/spi-fsl-spi.c regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1); regval 668 drivers/spi/spi-fsl-spi.c regval |= SPMODE_OP; regval 670 drivers/spi/spi-fsl-spi.c mpc8xxx_spi_write_reg(®_base->mode, regval); regval 37 drivers/spi/spi-rb4xx.c u32 regval; regval 39 drivers/spi/spi-rb4xx.c regval = spi_ioc; regval 41 drivers/spi/spi-rb4xx.c regval |= AR71XX_SPI_IOC_DO; regval 43 drivers/spi/spi-rb4xx.c rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval); regval 44 drivers/spi/spi-rb4xx.c rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK); regval 59 drivers/spi/spi-rb4xx.c u32 regval; regval 61 drivers/spi/spi-rb4xx.c regval = spi_ioc; regval 63 drivers/spi/spi-rb4xx.c regval |= AR71XX_SPI_IOC_DO; regval 65 drivers/spi/spi-rb4xx.c regval |= AR71XX_SPI_IOC_CS2; regval 67 drivers/spi/spi-rb4xx.c rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval); regval 68 drivers/spi/spi-rb4xx.c rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK); regval 734 drivers/spi/spi-sirf.c u32 regval; regval 738 drivers/spi/spi-sirf.c regval = readl(sspi->base + sspi->regs->spi_ctrl); regval 742 drivers/spi/spi-sirf.c regval |= SIRFSOC_SPI_CS_IO_OUT; regval 744 drivers/spi/spi-sirf.c regval &= ~SIRFSOC_SPI_CS_IO_OUT; regval 748 drivers/spi/spi-sirf.c regval &= ~SIRFSOC_SPI_CS_IO_OUT; regval 750 drivers/spi/spi-sirf.c regval |= SIRFSOC_SPI_CS_IO_OUT; regval 753 drivers/spi/spi-sirf.c writel(regval, sspi->base + sspi->regs->spi_ctrl); regval 757 drivers/spi/spi-sirf.c regval = readl(sspi->base + regval 762 drivers/spi/spi-sirf.c regval |= SIRFSOC_USP_CS_HIGH_VALUE; regval 764 drivers/spi/spi-sirf.c regval &= ~(SIRFSOC_USP_CS_HIGH_VALUE); regval 768 drivers/spi/spi-sirf.c regval &= ~(SIRFSOC_USP_CS_HIGH_VALUE); regval 770 drivers/spi/spi-sirf.c regval |= SIRFSOC_USP_CS_HIGH_VALUE; regval 773 drivers/spi/spi-sirf.c writel(regval, regval 794 drivers/spi/spi-sirf.c u32 regval, usp_mode1; regval 797 drivers/spi/spi-sirf.c regval = readl(sspi->base + sspi->regs->spi_ctrl); regval 800 drivers/spi/spi-sirf.c regval |= SIRFSOC_SPI_CS_IDLE_STAT; regval 803 drivers/spi/spi-sirf.c regval &= ~SIRFSOC_SPI_CS_IDLE_STAT; regval 807 drivers/spi/spi-sirf.c regval |= SIRFSOC_SPI_TRAN_MSB; regval 810 drivers/spi/spi-sirf.c regval &= ~SIRFSOC_SPI_TRAN_MSB; regval 814 drivers/spi/spi-sirf.c regval |= SIRFSOC_SPI_CLK_IDLE_STAT; regval 817 drivers/spi/spi-sirf.c regval &= ~SIRFSOC_SPI_CLK_IDLE_STAT; regval 826 drivers/spi/spi-sirf.c regval &= ~SIRFSOC_SPI_DRV_POS_EDGE; regval 830 drivers/spi/spi-sirf.c regval |= SIRFSOC_SPI_DRV_POS_EDGE; regval 854 drivers/spi/spi-sirf.c regval |= SIRFSOC_SPI_CS_IO_MODE; regval 855 drivers/spi/spi-sirf.c writel(regval, sspi->base + sspi->regs->spi_ctrl); regval 875 drivers/spi/spi-sirf.c u32 regval, txfifo_ctrl, rxfifo_ctrl, tx_frm_ctl, rx_frm_ctl, usp_mode2; regval 882 drivers/spi/spi-sirf.c usp_mode2 = regval = (sspi->ctrl_freq / (2 * hz)) - 1; regval 883 drivers/spi/spi-sirf.c if (regval > 0xFFFF || regval < 0) { regval 889 drivers/spi/spi-sirf.c regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8; regval 895 drivers/spi/spi-sirf.c regval |= (bits_per_word == 12) ? regval 902 drivers/spi/spi-sirf.c regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32; regval 962 drivers/spi/spi-sirf.c writel(regval, sspi->base + sspi->regs->spi_ctrl); regval 835 drivers/spmi/spmi-pmic-arb.c u32 regval, offset; regval 843 drivers/spmi/spmi-pmic-arb.c regval = readl_relaxed(pmic_arb->cnfg + regval 845 drivers/spmi/spmi-pmic-arb.c apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval); regval 848 drivers/spmi/spmi-pmic-arb.c regval = readl_relaxed(pmic_arb->core + offset); regval 849 drivers/spmi/spmi-pmic-arb.c if (!regval) regval 852 drivers/spmi/spmi-pmic-arb.c id = (regval >> 8) & PMIC_ARB_PPID_MASK; regval 884 drivers/spmi/spmi-pmic-arb.c u32 regval, offset; regval 898 drivers/spmi/spmi-pmic-arb.c regval = readl_relaxed(pmic_arb->core + offset); regval 899 drivers/spmi/spmi-pmic-arb.c if (!regval) regval 901 drivers/spmi/spmi-pmic-arb.c ppid = (regval >> 8) & PMIC_ARB_PPID_MASK; regval 902 drivers/spmi/spmi-pmic-arb.c is_irq_ee = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval); regval 904 drivers/spmi/spmi-pmic-arb.c regval = readl_relaxed(pmic_arb->cnfg + regval 906 drivers/spmi/spmi-pmic-arb.c apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval); regval 381 drivers/staging/comedi/drivers/ni_routes.c s8 regval; regval 391 drivers/staging/comedi/drivers/ni_routes.c regval = RVi(tables->route_values, src, dest); regval 392 drivers/staging/comedi/drivers/ni_routes.c if (!regval) regval 395 drivers/staging/comedi/drivers/ni_routes.c return UNMARK(regval); regval 435 drivers/staging/comedi/drivers/ni_routes.c s8 regval; regval 449 drivers/staging/comedi/drivers/ni_routes.c regval = RVi(rv, B(src), B(dest)); regval 455 drivers/staging/comedi/drivers/ni_routes.c if (!regval && channel_is_rtsi(dest)) { regval 456 drivers/staging/comedi/drivers/ni_routes.c regval = RVi(rv, B(src), B(NI_RGOUT0)); regval 457 drivers/staging/comedi/drivers/ni_routes.c if (!regval && (RVi(rv, B(src), B(NI_RTSI_BRD(0))) || regval 461 drivers/staging/comedi/drivers/ni_routes.c regval = BIT(6); regval 464 drivers/staging/comedi/drivers/ni_routes.c if (!regval) regval 467 drivers/staging/comedi/drivers/ni_routes.c return UNMARK(regval); regval 287 drivers/staging/iio/cdc/ad7746.c u8 regval) regval 302 drivers/staging/iio/cdc/ad7746.c regval |= chip->config; regval 303 drivers/staging/iio/cdc/ad7746.c ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_CFG, regval); regval 313 drivers/staging/iio/cdc/ad7746.c } while ((ret == regval) && timeout--); regval 535 drivers/staging/iio/cdc/ad7746.c u8 regval, reg; regval 547 drivers/staging/iio/cdc/ad7746.c regval = chip->config | AD7746_CONF_MODE_SINGLE_CONV; regval 549 drivers/staging/iio/cdc/ad7746.c regval); regval 682 drivers/staging/iio/cdc/ad7746.c unsigned char regval = 0; regval 711 drivers/staging/iio/cdc/ad7746.c regval |= AD7746_EXCSETUP_NEXCA; regval 713 drivers/staging/iio/cdc/ad7746.c regval |= AD7746_EXCSETUP_EXCA; regval 718 drivers/staging/iio/cdc/ad7746.c regval |= AD7746_EXCSETUP_NEXCB; regval 720 drivers/staging/iio/cdc/ad7746.c regval |= AD7746_EXCSETUP_EXCB; regval 723 drivers/staging/iio/cdc/ad7746.c regval |= AD7746_EXCSETUP_EXCLVL(pdata->exclvl); regval 726 drivers/staging/iio/cdc/ad7746.c regval = AD7746_EXCSETUP_EXCA | AD7746_EXCSETUP_EXCB | regval 731 drivers/staging/iio/cdc/ad7746.c AD7746_REG_EXC_SETUP, regval); regval 132 drivers/staging/iio/frequency/ad9832.c unsigned long regval; regval 137 drivers/staging/iio/frequency/ad9832.c regval = ad9832_calc_freqreg(clk_get_rate(st->mclk), fout); regval 141 drivers/staging/iio/frequency/ad9832.c ((regval >> 24) & 0xFF)); regval 144 drivers/staging/iio/frequency/ad9832.c ((regval >> 16) & 0xFF)); regval 147 drivers/staging/iio/frequency/ad9832.c ((regval >> 8) & 0xFF)); regval 150 drivers/staging/iio/frequency/ad9832.c ((regval >> 0) & 0xFF)); regval 114 drivers/staging/iio/frequency/ad9834.c unsigned long regval; regval 121 drivers/staging/iio/frequency/ad9834.c regval = ad9834_calc_freqreg(clk_freq, fout); regval 123 drivers/staging/iio/frequency/ad9834.c st->freq_data[0] = cpu_to_be16(addr | (regval & regval 125 drivers/staging/iio/frequency/ad9834.c st->freq_data[1] = cpu_to_be16(addr | ((regval >> regval 305 drivers/staging/kpc2000/kpc2000/core.c u16 regval; regval 410 drivers/staging/kpc2000/kpc2000/core.c pci_read_config_word(pcard->pdev, PCI_COMMAND, ®val); regval 411 drivers/staging/kpc2000/kpc2000/core.c regval |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); regval 412 drivers/staging/kpc2000/kpc2000/core.c pci_write_config_word(pcard->pdev, PCI_COMMAND, regval); regval 419 drivers/staging/kpc2000/kpc2000/core.c regval = (0x0) << 5; // Max_Payload_Size = 128 B regval 421 drivers/staging/kpc2000/kpc2000/core.c PCI_EXP_DEVCTL_PAYLOAD, regval); regval 422 drivers/staging/kpc2000/kpc2000/core.c regval = (0x0) << 12; // Max_Read_Request_Size = 128 B regval 424 drivers/staging/kpc2000/kpc2000/core.c PCI_EXP_DEVCTL_READRQ, regval); regval 303 drivers/staging/netlogic/xlr_net.c u32 regval; regval 305 drivers/staging/netlogic/xlr_net.c regval = xlr_nae_rdreg(priv->base_addr, R_MAC_FILTER_CONFIG); regval 308 drivers/staging/netlogic/xlr_net.c regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) | regval 313 drivers/staging/netlogic/xlr_net.c regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) | regval 317 drivers/staging/netlogic/xlr_net.c xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, regval); regval 657 drivers/staging/rtl8188eu/hal/bb_cfg.c u32 regval; regval 663 drivers/staging/rtl8188eu/hal/bb_cfg.c regval = usb_read16(adapt, REG_SYS_FUNC_EN); regval 665 drivers/staging/rtl8188eu/hal/bb_cfg.c (u16)(regval | BIT(13) | BIT(0) | BIT(1))); regval 558 drivers/thermal/ti-soc-thermal/ti-bandgap.c bgp->regval[id].data = data; regval 577 drivers/thermal/ti-soc-thermal/ti-bandgap.c return bgp->regval[id].data; regval 841 drivers/thermal/ti-soc-thermal/ti-bandgap.c bgp->regval = devm_kcalloc(&pdev->dev, bgp->conf->sensor_count, regval 842 drivers/thermal/ti-soc-thermal/ti-bandgap.c sizeof(*bgp->regval), GFP_KERNEL); regval 843 drivers/thermal/ti-soc-thermal/ti-bandgap.c if (!bgp->regval) regval 1099 drivers/thermal/ti-soc-thermal/ti-bandgap.c rval = &bgp->regval[i]; regval 1132 drivers/thermal/ti-soc-thermal/ti-bandgap.c rval = &bgp->regval[i]; regval 197 drivers/thermal/ti-soc-thermal/ti-bandgap.h struct temp_sensor_regval *regval; regval 140 drivers/tty/serial/ip22zilog.c unsigned char regval; regval 142 drivers/tty/serial/ip22zilog.c regval = readb(&channel->control); regval 144 drivers/tty/serial/ip22zilog.c if (regval & Rx_CH_AV) regval 147 drivers/tty/serial/ip22zilog.c regval = read_zsreg(channel, R1); regval 151 drivers/tty/serial/ip22zilog.c if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) { regval 157 drivers/tty/serial/sunzilog.c unsigned char regval; regval 159 drivers/tty/serial/sunzilog.c regval = readb(&channel->control); regval 161 drivers/tty/serial/sunzilog.c if (regval & Rx_CH_AV) regval 164 drivers/tty/serial/sunzilog.c regval = read_zsreg(channel, R1); regval 168 drivers/tty/serial/sunzilog.c if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) { regval 611 drivers/tty/serial/xilinx_uartps.c unsigned int regval; regval 613 drivers/tty/serial/xilinx_uartps.c regval = readl(port->membase + CDNS_UART_CR); regval 614 drivers/tty/serial/xilinx_uartps.c regval |= CDNS_UART_CR_TX_DIS; regval 616 drivers/tty/serial/xilinx_uartps.c writel(regval, port->membase + CDNS_UART_CR); regval 625 drivers/tty/serial/xilinx_uartps.c unsigned int regval; regval 631 drivers/tty/serial/xilinx_uartps.c regval = readl(port->membase + CDNS_UART_CR); regval 632 drivers/tty/serial/xilinx_uartps.c regval |= CDNS_UART_CR_RX_DIS; regval 633 drivers/tty/serial/xilinx_uartps.c writel(regval, port->membase + CDNS_UART_CR); regval 1186 drivers/usb/gadget/udc/atmel_usba_udc.c u32 regval; regval 1189 drivers/usb/gadget/udc/atmel_usba_udc.c regval = usba_readl(udc, CTRL); regval 1190 drivers/usb/gadget/udc/atmel_usba_udc.c regval = USBA_BFINS(DEV_ADDR, addr, regval); regval 1191 drivers/usb/gadget/udc/atmel_usba_udc.c usba_writel(udc, CTRL, regval); regval 305 drivers/usb/host/ohci-at91.c u32 regval; regval 311 drivers/usb/host/ohci-at91.c ret = regmap_read(regmap, AT91_SFR_OHCIICR, ®val); regval 316 drivers/usb/host/ohci-at91.c regval |= AT91_OHCIICR_USB_SUSPEND; regval 318 drivers/usb/host/ohci-at91.c regval &= ~AT91_OHCIICR_USB_SUSPEND; regval 320 drivers/usb/host/ohci-at91.c regmap_write(regmap, AT91_SFR_OHCIICR, regval); regval 52 drivers/usb/host/xhci-histb.c u32 regval; regval 56 drivers/usb/host/xhci-histb.c regval = readl(histb->ctrl + REG_GUSB2PHYCFG0); regval 57 drivers/usb/host/xhci-histb.c regval &= ~BIT_UTMI_ULPI; regval 58 drivers/usb/host/xhci-histb.c regval &= ~(BIT_UTMI_8_16); regval 59 drivers/usb/host/xhci-histb.c regval &= ~BIT_FREECLK_EXIST; regval 60 drivers/usb/host/xhci-histb.c writel(regval, histb->ctrl + REG_GUSB2PHYCFG0); regval 71 drivers/usb/host/xhci-histb.c regval = readl(histb->ctrl + REG_GUSB3PIPECTL0); regval 72 drivers/usb/host/xhci-histb.c regval &= ~USB3_DEEMPHASIS_MASK; regval 73 drivers/usb/host/xhci-histb.c regval |= USB3_DEEMPHASIS0; regval 74 drivers/usb/host/xhci-histb.c regval |= USB3_TX_MARGIN1; regval 75 drivers/usb/host/xhci-histb.c writel(regval, histb->ctrl + REG_GUSB3PIPECTL0); regval 447 drivers/usb/serial/mos7840.c __u8 regval = 0x0; regval 474 drivers/usb/serial/mos7840.c regval = (__u8) data[0]; regval 475 drivers/usb/serial/mos7840.c dev_dbg(dev, "%s data is %x\n", __func__, regval); regval 477 drivers/usb/serial/mos7840.c mos7840_handle_new_msr(mos7840_port, regval); regval 479 drivers/usb/serial/mos7840.c mos7840_handle_new_lsr(mos7840_port, regval); regval 464 drivers/video/fbdev/arkfb.c u8 regval; regval 467 drivers/video/fbdev/arkfb.c regval = vga_rseq(par->state.vgabase, 0x1C); regval 470 drivers/video/fbdev/arkfb.c vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0)); regval 476 drivers/video/fbdev/arkfb.c vga_wseq(par->state.vgabase, 0x1C, regval); regval 483 drivers/video/fbdev/arkfb.c u8 regval; regval 486 drivers/video/fbdev/arkfb.c regval = vga_rseq(par->state.vgabase, 0x1C); regval 489 drivers/video/fbdev/arkfb.c vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0)); regval 495 drivers/video/fbdev/arkfb.c vga_wseq(par->state.vgabase, 0x1C, regval); regval 502 drivers/video/fbdev/arkfb.c u8 regval; regval 511 drivers/video/fbdev/arkfb.c regval = vga_r(par->state.vgabase, VGA_MIS_R); regval 512 drivers/video/fbdev/arkfb.c vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); regval 619 drivers/video/fbdev/arkfb.c u8 regval; regval 679 drivers/video/fbdev/arkfb.c regval = 0x10 | ((threshold & 0x0E) >> 1) | (threshold & 0x01) << 7 | (threshold & 0x10) << 1; regval 680 drivers/video/fbdev/arkfb.c vga_wseq(par->state.vgabase, 0x18, regval); regval 947 drivers/video/fbdev/arkfb.c u8 regval; regval 1007 drivers/video/fbdev/arkfb.c regval = vga_rseq(par->state.vgabase, 0x10); regval 1008 drivers/video/fbdev/arkfb.c info->screen_size = (1 << (regval >> 6)) << 20; regval 25 drivers/video/fbdev/core/svgalib.c u8 regval, bitval, bitnum; regval 28 drivers/video/fbdev/core/svgalib.c regval = vga_rcrt(regbase, regset->regnum); regval 32 drivers/video/fbdev/core/svgalib.c regval = regval & ~bitval; regval 33 drivers/video/fbdev/core/svgalib.c if (value & 1) regval = regval | bitval; regval 37 drivers/video/fbdev/core/svgalib.c vga_wcrt(regbase, regset->regnum, regval); regval 45 drivers/video/fbdev/core/svgalib.c u8 regval, bitval, bitnum; regval 48 drivers/video/fbdev/core/svgalib.c regval = vga_rseq(regbase, regset->regnum); regval 52 drivers/video/fbdev/core/svgalib.c regval = regval & ~bitval; regval 53 drivers/video/fbdev/core/svgalib.c if (value & 1) regval = regval | bitval; regval 57 drivers/video/fbdev/core/svgalib.c vga_wseq(regbase, regset->regnum, regval); regval 514 drivers/video/fbdev/core/svgalib.c u8 regval; regval 579 drivers/video/fbdev/core/svgalib.c regval = vga_r(regbase, VGA_MIS_R); regval 582 drivers/video/fbdev/core/svgalib.c regval = regval & ~0x80; regval 585 drivers/video/fbdev/core/svgalib.c regval = regval | 0x80; regval 589 drivers/video/fbdev/core/svgalib.c regval = regval & ~0x40; regval 592 drivers/video/fbdev/core/svgalib.c regval = regval | 0x40; regval 594 drivers/video/fbdev/core/svgalib.c vga_w(regbase, VGA_MIS_W, regval); regval 462 drivers/video/fbdev/s3fb.c u8 regval; regval 473 drivers/video/fbdev/s3fb.c regval = vga_r(par->state.vgabase, VGA_MIS_R); regval 474 drivers/video/fbdev/s3fb.c vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); regval 492 drivers/video/fbdev/s3fb.c regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ regval 493 drivers/video/fbdev/s3fb.c vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); regval 494 drivers/video/fbdev/s3fb.c vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); regval 495 drivers/video/fbdev/s3fb.c vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); regval 1120 drivers/video/fbdev/s3fb.c u8 regval, cr38, cr39; regval 1189 drivers/video/fbdev/s3fb.c regval = vga_rcrt(par->state.vgabase, 0x36); regval 1194 drivers/video/fbdev/s3fb.c switch ((regval & 0xE0) >> 5) { regval 1208 drivers/video/fbdev/s3fb.c switch ((regval & 0xC0) >> 6) { regval 1217 drivers/video/fbdev/s3fb.c switch ((regval & 0x60) >> 5) { regval 1232 drivers/video/fbdev/s3fb.c regval = vga_rcrt(par->state.vgabase, 0x37); regval 1233 drivers/video/fbdev/s3fb.c switch ((regval & 0x60) >> 5) { regval 1242 drivers/video/fbdev/s3fb.c info->screen_size = s3_memsizes[regval >> 5] << 10; regval 1246 drivers/video/fbdev/s3fb.c regval = vga_rseq(par->state.vgabase, 0x10); regval 1247 drivers/video/fbdev/s3fb.c par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); regval 1248 drivers/video/fbdev/s3fb.c par->mclk_freq = par->mclk_freq >> (regval >> 5); regval 254 drivers/video/fbdev/vt8623fb.c u8 regval; regval 264 drivers/video/fbdev/vt8623fb.c regval = vga_r(par->state.vgabase, VGA_MIS_R); regval 265 drivers/video/fbdev/vt8623fb.c vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); regval 55 drivers/watchdog/da9062_wdt.c unsigned int regval) regval 74 drivers/watchdog/da9062_wdt.c regval); regval 70 drivers/watchdog/da9063_wdt.c unsigned int regval; regval 86 drivers/watchdog/da9063_wdt.c regval = da9063_wdt_timeout_to_sel(timeout); regval 89 drivers/watchdog/da9063_wdt.c DA9063_TWDSCALE_MASK, regval); regval 58 drivers/watchdog/max77620_wdt.c u8 regval; regval 63 drivers/watchdog/max77620_wdt.c regval = MAX77620_TWD_2s; regval 68 drivers/watchdog/max77620_wdt.c regval = MAX77620_TWD_16s; regval 73 drivers/watchdog/max77620_wdt.c regval = MAX77620_TWD_64s; regval 78 drivers/watchdog/max77620_wdt.c regval = MAX77620_TWD_128s; regval 89 drivers/watchdog/max77620_wdt.c MAX77620_TWD_MASK, regval); regval 115 drivers/watchdog/max77620_wdt.c unsigned int regval; regval 157 drivers/watchdog/max77620_wdt.c ret = regmap_read(wdt->rmap, MAX77620_REG_CNFGGLBL2, ®val); regval 163 drivers/watchdog/max77620_wdt.c switch (regval & MAX77620_TWD_MASK) { regval 178 drivers/watchdog/max77620_wdt.c if (regval & MAX77620_WDTEN) regval 58 drivers/watchdog/mlx_wdt.c u32 regval; regval 68 drivers/watchdog/mlx_wdt.c rc = regmap_read(wdt->regmap, reg_data->reg, ®val); regval 70 drivers/watchdog/mlx_wdt.c if (regval & ~reg_data->mask) { regval 111 drivers/watchdog/mlx_wdt.c u32 regval, set_time, hw_timeout; regval 115 drivers/watchdog/mlx_wdt.c rc = regmap_read(wdt->regmap, reg_data->reg, ®val); regval 120 drivers/watchdog/mlx_wdt.c regval = (regval & reg_data->mask) | hw_timeout; regval 125 drivers/watchdog/mlx_wdt.c regval = timeout; regval 129 drivers/watchdog/mlx_wdt.c rc = regmap_write(wdt->regmap, reg_data->reg, regval); regval 150 drivers/watchdog/mlx_wdt.c u32 regval; regval 153 drivers/watchdog/mlx_wdt.c rc = regmap_read(wdt->regmap, reg_data->reg, ®val); regval 155 drivers/watchdog/mlx_wdt.c return rc == 0 ? regval : 0; regval 51 drivers/watchdog/ts4800_wdt.c const int regval; regval 92 drivers/watchdog/ts4800_wdt.c wdt->feed_val = ts4800_wdt_map[i].regval; regval 48 drivers/watchdog/ts72xx_wdt.c unsigned char regval; regval 56 drivers/watchdog/ts72xx_wdt.c writeb(priv->regval, priv->control_reg); regval 85 drivers/watchdog/ts72xx_wdt.c priv->regval = TS72XX_WDT_CTRL_1SEC; regval 87 drivers/watchdog/ts72xx_wdt.c priv->regval = TS72XX_WDT_CTRL_2SEC; regval 89 drivers/watchdog/ts72xx_wdt.c priv->regval = TS72XX_WDT_CTRL_4SEC; regval 92 drivers/watchdog/ts72xx_wdt.c priv->regval = TS72XX_WDT_CTRL_8SEC; regval 254 include/linux/fsl/bestcomm/bestcomm_priv.h u16 regval; regval 256 include/linux/fsl/bestcomm/bestcomm_priv.h regval = in_be16(&bcom_eng->regs->PtdCntrl); regval 257 include/linux/fsl/bestcomm/bestcomm_priv.h out_be16(&bcom_eng->regs->PtdCntrl, regval | 1); regval 1198 sound/isa/opti9xx/miro.c unsigned char regval; regval 1208 sound/isa/opti9xx/miro.c regval=inb(miro->mc_base + 4); regval 1209 sound/isa/opti9xx/miro.c aci->aci_port = (regval & 0x10) ? 0x344 : 0x354; regval 130 sound/sh/aica.c u32 regval; regval 132 sound/sh/aica.c regval = readl(ARM_RESET_REGISTER); regval 133 sound/sh/aica.c regval |= 1; regval 136 sound/sh/aica.c writel(regval, ARM_RESET_REGISTER); regval 140 sound/sh/aica.c regval = readl(SPU_REGISTER_BASE + (i * 0x80)); regval 141 sound/sh/aica.c regval = (regval & ~0x4000) | 0x8000; regval 144 sound/sh/aica.c writel(regval, SPU_REGISTER_BASE + (i * 0x80)); regval 153 sound/sh/aica.c u32 regval = readl(ARM_RESET_REGISTER); regval 154 sound/sh/aica.c regval &= ~1; regval 157 sound/sh/aica.c writel(regval, ARM_RESET_REGISTER); regval 404 sound/soc/bcm/cygnus-pcm.c u32 regval; regval 418 sound/soc/bcm/cygnus-pcm.c regval = readl(aio->cygaud->audio + p_rbuf->rdaddr); regval 419 sound/soc/bcm/cygnus-pcm.c regval = regval ^ BIT(31); regval 420 sound/soc/bcm/cygnus-pcm.c writel(regval, aio->cygaud->audio + p_rbuf->wraddr); regval 423 sound/soc/bcm/cygnus-pcm.c regval = readl(aio->cygaud->audio + p_rbuf->wraddr); regval 424 sound/soc/bcm/cygnus-pcm.c writel(regval, aio->cygaud->audio + p_rbuf->rdaddr); regval 450 sound/soc/codecs/cpcap.c int regval, mask; regval 453 sound/soc/codecs/cpcap.c err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, ®val); regval 463 sound/soc/codecs/cpcap.c switch (regval & mask) { regval 493 sound/soc/codecs/cpcap.c int regval = 0, mask; regval 504 sound/soc/codecs/cpcap.c regval = BIT(CPCAP_BIT_MIC1_MUX); regval 507 sound/soc/codecs/cpcap.c regval = BIT(CPCAP_BIT_HS_MIC_MUX); regval 510 sound/soc/codecs/cpcap.c regval = BIT(CPCAP_BIT_EMU_MIC_MUX); regval 513 sound/soc/codecs/cpcap.c regval = BIT(CPCAP_BIT_RX_R_ENCODE); regval 520 sound/soc/codecs/cpcap.c mask, regval); regval 534 sound/soc/codecs/cpcap.c int regval, mask; regval 537 sound/soc/codecs/cpcap.c err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, ®val); regval 545 sound/soc/codecs/cpcap.c switch (regval & mask) { regval 569 sound/soc/codecs/cpcap.c int regval = 0, mask; regval 578 sound/soc/codecs/cpcap.c regval = BIT(CPCAP_BIT_MIC2_MUX); regval 581 sound/soc/codecs/cpcap.c regval = BIT(CPCAP_BIT_RX_L_ENCODE); regval 588 sound/soc/codecs/cpcap.c mask, regval); regval 855 sound/soc/codecs/cs42l42.c unsigned int regval; regval 880 sound/soc/codecs/cs42l42.c regval = snd_soc_component_read32(component, CS42L42_LOAD_DET_RCSTAT); regval 881 sound/soc/codecs/cs42l42.c if (((regval & CS42L42_RLA_STAT_MASK) >> regval 51 sound/soc/codecs/inno_rk3036.c int val, ret, regval; regval 53 sound/soc/codecs/inno_rk3036.c ret = snd_soc_component_read(component, INNO_R09, ®val); regval 56 sound/soc/codecs/inno_rk3036.c val = ((regval >> INNO_R09_HPL_ANITPOP_SHIFT) & regval 60 sound/soc/codecs/inno_rk3036.c val = ((regval >> INNO_R09_HPR_ANITPOP_SHIFT) & regval 970 sound/soc/codecs/max98088.c u8 regval; regval 991 sound/soc/codecs/max98088.c if (rate_value(rate, ®val)) regval 995 sound/soc/codecs/max98088.c M98088_CLKMODE_MASK, regval); regval 1037 sound/soc/codecs/max98088.c u8 regval; regval 1058 sound/soc/codecs/max98088.c if (rate_value(rate, ®val)) regval 1062 sound/soc/codecs/max98088.c M98088_CLKMODE_MASK, regval); regval 1618 sound/soc/codecs/max98088.c u8 regval = 0; regval 1627 sound/soc/codecs/max98088.c regval |= M98088_DIGMIC_L; regval 1630 sound/soc/codecs/max98088.c regval |= M98088_DIGMIC_R; regval 1632 sound/soc/codecs/max98088.c max98088->digmic = (regval ? 1 : 0); regval 1634 sound/soc/codecs/max98088.c snd_soc_component_write(component, M98088_REG_48_CFG_MIC, regval); regval 1637 sound/soc/codecs/max98088.c regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0); regval 1639 sound/soc/codecs/max98088.c M98088_REC_LINEMODE_MASK, regval); regval 1578 sound/soc/codecs/max98090.c u8 regval; regval 1586 sound/soc/codecs/max98090.c regval = 0; regval 1602 sound/soc/codecs/max98090.c regval |= M98090_MAS_MASK | regval 1606 sound/soc/codecs/max98090.c regval |= M98090_MAS_MASK | regval 1610 sound/soc/codecs/max98090.c regval |= M98090_MAS_MASK | regval 1621 sound/soc/codecs/max98090.c snd_soc_component_write(component, M98090_REG_MASTER_MODE, regval); regval 1623 sound/soc/codecs/max98090.c regval = 0; regval 1626 sound/soc/codecs/max98090.c regval |= M98090_DLY_MASK; regval 1631 sound/soc/codecs/max98090.c regval |= M98090_RJ_MASK; regval 1644 sound/soc/codecs/max98090.c regval |= M98090_WCI_MASK; regval 1647 sound/soc/codecs/max98090.c regval |= M98090_BCI_MASK; regval 1650 sound/soc/codecs/max98090.c regval |= M98090_BCI_MASK|M98090_WCI_MASK; regval 1664 sound/soc/codecs/max98090.c regval ^= M98090_BCI_MASK; regval 1667 sound/soc/codecs/max98090.c M98090_REG_INTERFACE_FORMAT, regval); regval 2023 sound/soc/codecs/max98090.c int regval; regval 2025 sound/soc/codecs/max98090.c regval = mute ? M98090_DVM_MASK : 0; regval 2027 sound/soc/codecs/max98090.c M98090_DVM_MASK, regval); regval 947 sound/soc/codecs/max98095.c u8 regval; regval 966 sound/soc/codecs/max98095.c if (rate_value(rate, ®val)) regval 970 sound/soc/codecs/max98095.c M98095_CLKMODE_MASK, regval); regval 1008 sound/soc/codecs/max98095.c u8 regval; regval 1027 sound/soc/codecs/max98095.c if (rate_value(rate, ®val)) regval 1031 sound/soc/codecs/max98095.c M98095_CLKMODE_MASK, regval); regval 1069 sound/soc/codecs/max98095.c u8 regval; regval 1088 sound/soc/codecs/max98095.c if (rate_value(rate, ®val)) regval 1092 sound/soc/codecs/max98095.c M98095_CLKMODE_MASK, regval); regval 1164 sound/soc/codecs/max98095.c u8 regval = 0; regval 1181 sound/soc/codecs/max98095.c regval |= M98095_DAI_MAS; regval 1192 sound/soc/codecs/max98095.c regval |= M98095_DAI_DLY; regval 1204 sound/soc/codecs/max98095.c regval |= M98095_DAI_WCI; regval 1207 sound/soc/codecs/max98095.c regval |= M98095_DAI_BCI; regval 1210 sound/soc/codecs/max98095.c regval |= M98095_DAI_BCI|M98095_DAI_WCI; regval 1218 sound/soc/codecs/max98095.c M98095_DAI_WCI, regval); regval 1232 sound/soc/codecs/max98095.c u8 regval = 0; regval 1249 sound/soc/codecs/max98095.c regval |= M98095_DAI_MAS; regval 1260 sound/soc/codecs/max98095.c regval |= M98095_DAI_DLY; regval 1272 sound/soc/codecs/max98095.c regval |= M98095_DAI_WCI; regval 1275 sound/soc/codecs/max98095.c regval |= M98095_DAI_BCI; regval 1278 sound/soc/codecs/max98095.c regval |= M98095_DAI_BCI|M98095_DAI_WCI; regval 1286 sound/soc/codecs/max98095.c M98095_DAI_WCI, regval); regval 1301 sound/soc/codecs/max98095.c u8 regval = 0; regval 1318 sound/soc/codecs/max98095.c regval |= M98095_DAI_MAS; regval 1329 sound/soc/codecs/max98095.c regval |= M98095_DAI_DLY; regval 1341 sound/soc/codecs/max98095.c regval |= M98095_DAI_WCI; regval 1344 sound/soc/codecs/max98095.c regval |= M98095_DAI_BCI; regval 1347 sound/soc/codecs/max98095.c regval |= M98095_DAI_BCI|M98095_DAI_WCI; regval 1355 sound/soc/codecs/max98095.c M98095_DAI_WCI, regval); regval 1785 sound/soc/codecs/max98095.c u8 regval = 0; regval 1794 sound/soc/codecs/max98095.c regval |= M98095_DIGMIC_L; regval 1797 sound/soc/codecs/max98095.c regval |= M98095_DIGMIC_R; regval 1799 sound/soc/codecs/max98095.c snd_soc_component_write(component, M98095_087_CFG_MIC, regval); regval 75 sound/soc/qcom/lpass-cpu.c unsigned int regval; regval 84 sound/soc/qcom/lpass-cpu.c regval = LPAIF_I2SCTL_LOOPBACK_DISABLE | regval 89 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_BITWIDTH_16; regval 92 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_BITWIDTH_24; regval 95 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_BITWIDTH_32; regval 105 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_SPKMODE_SD0; regval 106 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_SPKMONO_MONO; regval 109 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_SPKMODE_SD0; regval 110 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_SPKMONO_STEREO; regval 113 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_SPKMODE_QUAD01; regval 114 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_SPKMONO_STEREO; regval 117 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_SPKMODE_6CH; regval 118 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_SPKMONO_STEREO; regval 121 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_SPKMODE_8CH; regval 122 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_SPKMONO_STEREO; regval 132 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_MICMODE_SD0; regval 133 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_MICMONO_MONO; regval 136 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_MICMODE_SD0; regval 137 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_MICMONO_STEREO; regval 140 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_MICMODE_QUAD01; regval 141 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_MICMONO_STEREO; regval 144 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_MICMODE_6CH; regval 145 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_MICMONO_STEREO; regval 148 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_MICMODE_8CH; regval 149 sound/soc/qcom/lpass-cpu.c regval |= LPAIF_I2SCTL_MICMONO_STEREO; regval 160 sound/soc/qcom/lpass-cpu.c regval); regval 136 sound/soc/qcom/lpass-platform.c unsigned int regval; regval 150 sound/soc/qcom/lpass-platform.c regval = LPAIF_DMACTL_BURSTEN_INCR4 | regval 159 sound/soc/qcom/lpass-platform.c regval |= LPAIF_DMACTL_WPSCNT_ONE; regval 162 sound/soc/qcom/lpass-platform.c regval |= LPAIF_DMACTL_WPSCNT_TWO; regval 165 sound/soc/qcom/lpass-platform.c regval |= LPAIF_DMACTL_WPSCNT_THREE; regval 168 sound/soc/qcom/lpass-platform.c regval |= LPAIF_DMACTL_WPSCNT_FOUR; regval 181 sound/soc/qcom/lpass-platform.c regval |= LPAIF_DMACTL_WPSCNT_ONE; regval 184 sound/soc/qcom/lpass-platform.c regval |= LPAIF_DMACTL_WPSCNT_TWO; regval 187 sound/soc/qcom/lpass-platform.c regval |= LPAIF_DMACTL_WPSCNT_FOUR; regval 190 sound/soc/qcom/lpass-platform.c regval |= LPAIF_DMACTL_WPSCNT_SIX; regval 193 sound/soc/qcom/lpass-platform.c regval |= LPAIF_DMACTL_WPSCNT_EIGHT; regval 209 sound/soc/qcom/lpass-platform.c LPAIF_DMACTL_REG(v, ch, dir), regval); regval 841 sound/soc/soc-ops.c unsigned int regval; regval 846 sound/soc/soc-ops.c ret = snd_soc_component_read(component, regbase+i, ®val); regval 849 sound/soc/soc-ops.c val |= (regval & regwmask) << (regwshift*(regcount-i-1)); regval 889 sound/soc/soc-ops.c unsigned int i, regval, regmask; regval 896 sound/soc/soc-ops.c regval = (val >> (regwshift*(regcount-i-1))) & regwmask; regval 899 sound/soc/soc-ops.c regmask, regval); regval 253 sound/x86/intel_hdmi_audio.c intelhaddata->aud_config.regval); regval 284 sound/x86/intel_hdmi_audio.c union aud_ch_status_0 ch_stat0 = {.regval = 0}; regval 285 sound/x86/intel_hdmi_audio.c union aud_ch_status_1 ch_stat1 = {.regval = 0}; regval 322 sound/x86/intel_hdmi_audio.c AUD_CH_STATUS_0, ch_stat0.regval); regval 339 sound/x86/intel_hdmi_audio.c AUD_CH_STATUS_1, ch_stat1.regval); regval 351 sound/x86/intel_hdmi_audio.c union aud_cfg cfg_val = {.regval = 0}; regval 352 sound/x86/intel_hdmi_audio.c union aud_buf_config buf_cfg = {.regval = 0}; regval 360 sound/x86/intel_hdmi_audio.c had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval); regval 383 sound/x86/intel_hdmi_audio.c had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval); regval 593 sound/x86/intel_hdmi_audio.c union aud_ctrl_st ctrl_state = {.regval = 0}; regval 594 sound/x86/intel_hdmi_audio.c union aud_info_frame2 frame2 = {.regval = 0}; regval 595 sound/x86/intel_hdmi_audio.c union aud_info_frame3 frame3 = {.regval = 0}; regval 603 sound/x86/intel_hdmi_audio.c had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); regval 608 sound/x86/intel_hdmi_audio.c frame2.regval = (substream->runtime->channels - 1) | (ca << 24); regval 618 sound/x86/intel_hdmi_audio.c checksum += (frame2.regval >> (i * 8)) & 0xff; regval 620 sound/x86/intel_hdmi_audio.c checksum += (frame3.regval >> (i * 8)) & 0xff; regval 626 sound/x86/intel_hdmi_audio.c had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval); regval 627 sound/x86/intel_hdmi_audio.c had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval); regval 635 sound/x86/intel_hdmi_audio.c had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval); regval 124 sound/x86/intel_hdmi_lpe_audio.h u32 regval; regval 148 sound/x86/intel_hdmi_lpe_audio.h u32 regval; regval 167 sound/x86/intel_hdmi_lpe_audio.h u32 regval; regval 182 sound/x86/intel_hdmi_lpe_audio.h u32 regval; regval 192 sound/x86/intel_hdmi_lpe_audio.h u32 regval; regval 204 sound/x86/intel_hdmi_lpe_audio.h u32 regval; regval 223 sound/x86/intel_hdmi_lpe_audio.h u32 regval; regval 236 sound/x86/intel_hdmi_lpe_audio.h u32 regval; regval 248 sound/x86/intel_hdmi_lpe_audio.h u32 regval; regval 265 sound/x86/intel_hdmi_lpe_audio.h u32 regval; regval 276 sound/x86/intel_hdmi_lpe_audio.h u32 regval; regval 294 sound/x86/intel_hdmi_lpe_audio.h u32 regval; regval 306 sound/x86/intel_hdmi_lpe_audio.h u32 regval;