regr 38 drivers/block/paride/aten.c static void aten_write_regr( PIA *pi, int cont, int regr, int val) regr 42 drivers/block/paride/aten.c r = regr + cont_map[cont] + 0x80; regr 47 drivers/block/paride/aten.c static int aten_read_regr( PIA *pi, int cont, int regr ) regr 51 drivers/block/paride/aten.c r = regr + cont_map[cont] + 0x40; regr 48 drivers/block/paride/bpck.c static int bpck_read_regr( PIA *pi, int cont, int regr ) regr 52 drivers/block/paride/bpck.c r = regr + cont_map[cont]; regr 79 drivers/block/paride/bpck.c static void bpck_write_regr( PIA *pi, int cont, int regr, int val ) regr 83 drivers/block/paride/bpck.c r = regr + cont_map[cont]; regr 45 drivers/block/paride/comm.c static int comm_read_regr( PIA *pi, int cont, int regr ) regr 49 drivers/block/paride/comm.c r = regr + cont_map[cont]; regr 71 drivers/block/paride/comm.c static void comm_write_regr( PIA *pi, int cont, int regr, int val ) regr 75 drivers/block/paride/comm.c r = regr + cont_map[cont]; regr 47 drivers/block/paride/dstr.c static int dstr_read_regr( PIA *pi, int cont, int regr ) regr 51 drivers/block/paride/dstr.c r = regr + cont_map[cont]; regr 74 drivers/block/paride/dstr.c static void dstr_write_regr( PIA *pi, int cont, int regr, int val ) regr 78 drivers/block/paride/dstr.c r = regr + cont_map[cont]; regr 47 drivers/block/paride/epat.c static void epat_write_regr( PIA *pi, int cont, int regr, int val) regr 51 drivers/block/paride/epat.c r = regr + cont_map[cont]; regr 68 drivers/block/paride/epat.c static int epat_read_regr( PIA *pi, int cont, int regr ) regr 72 drivers/block/paride/epat.c r = regr + cont_map[cont]; regr 49 drivers/block/paride/epia.c static int epia_read_regr( PIA *pi, int cont, int regr ) regr 53 drivers/block/paride/epia.c regr += cont_map[cont]; regr 57 drivers/block/paride/epia.c case 0: r = regr^0x39; regr 62 drivers/block/paride/epia.c case 1: r = regr^0x31; regr 68 drivers/block/paride/epia.c case 2: r = regr^0x29; regr 75 drivers/block/paride/epia.c case 5: w3(regr); w2(0x24); a = r4(); w2(4); regr 82 drivers/block/paride/epia.c static void epia_write_regr( PIA *pi, int cont, int regr, int val) regr 86 drivers/block/paride/epia.c regr += cont_map[cont]; regr 92 drivers/block/paride/epia.c case 2: r = regr^0x19; regr 98 drivers/block/paride/epia.c case 5: r = regr^0x40; regr 40 drivers/block/paride/fit2.c static void fit2_write_regr( PIA *pi, int cont, int regr, int val) regr 43 drivers/block/paride/fit2.c w2(0xc); w0(regr); w2(4); w0(val); w2(5); w0(0); w2(4); regr 46 drivers/block/paride/fit2.c static int fit2_read_regr( PIA *pi, int cont, int regr ) regr 51 drivers/block/paride/fit2.c if (regr != 6) return 0xff; regr 53 drivers/block/paride/fit2.c } else r = regr + 0x10; regr 42 drivers/block/paride/fit3.c static void fit3_write_regr( PIA *pi, int cont, int regr, int val) regr 49 drivers/block/paride/fit3.c case 1: w2(0xc); w0(regr); w2(0x8); w2(0xc); regr 54 drivers/block/paride/fit3.c case 2: w2(0xc); w0(regr); w2(0x8); w2(0xc); regr 62 drivers/block/paride/fit3.c static int fit3_read_regr( PIA *pi, int cont, int regr ) regr 67 drivers/block/paride/fit3.c if (regr != 6) return 0xff; regr 68 drivers/block/paride/fit3.c regr = 7; regr 73 drivers/block/paride/fit3.c case 0: w2(0xc); w0(regr + 0x10); w2(0x8); w2(0xc); regr 79 drivers/block/paride/fit3.c case 1: w2(0xc); w0(regr + 0x90); w2(0x8); w2(0xc); regr 84 drivers/block/paride/fit3.c case 2: w2(0xc); w0(regr + 0x90); w2(0x8); w2(0xc); regr 51 drivers/block/paride/friq.c static int friq_read_regr( PIA *pi, int cont, int regr ) regr 55 drivers/block/paride/friq.c r = regr + cont_map[cont]; regr 66 drivers/block/paride/friq.c static void friq_write_regr( PIA *pi, int cont, int regr, int val) regr 70 drivers/block/paride/friq.c r = regr + cont_map[cont]; regr 77 drivers/block/paride/friq.c static void friq_read_block_int( PIA *pi, char * buf, int count, int regr ) regr 83 drivers/block/paride/friq.c case 0: CMD(regr); regr 93 drivers/block/paride/friq.c CMD(regr+0xc0); regr 103 drivers/block/paride/friq.c case 2: CMD(regr+0x80); regr 111 drivers/block/paride/friq.c case 3: CMD(regr+0x80); regr 119 drivers/block/paride/friq.c case 4: CMD(regr+0x80); regr 47 drivers/block/paride/frpw.c static int frpw_read_regr( PIA *pi, int cont, int regr ) regr 51 drivers/block/paride/frpw.c r = regr + cont_map[cont]; regr 63 drivers/block/paride/frpw.c static void frpw_write_regr( PIA *pi, int cont, int regr, int val) regr 67 drivers/block/paride/frpw.c r = regr + cont_map[cont]; regr 74 drivers/block/paride/frpw.c static void frpw_read_block_int( PIA *pi, char * buf, int count, int regr ) regr 80 drivers/block/paride/frpw.c case 0: w2(4); w0(regr); cec4; regr 90 drivers/block/paride/frpw.c w2(4); w0(regr + 0xc0); cec4; regr 100 drivers/block/paride/frpw.c case 2: w2(4); w0(regr + 0x80); cec4; regr 106 drivers/block/paride/frpw.c case 3: w2(4); w0(regr + 0x80); cec4; regr 114 drivers/block/paride/frpw.c case 4: w2(4); w0(regr + 0x80); cec4; regr 122 drivers/block/paride/frpw.c case 5: w2(4); w0(regr + 0x80); cec4; regr 45 drivers/block/paride/kbic.c static int kbic_read_regr( PIA *pi, int cont, int regr ) regr 53 drivers/block/paride/kbic.c case 0: w0(regr|0x18|s); w2(4); w2(6); w2(4); w2(1); w0(8); regr 57 drivers/block/paride/kbic.c case 1: w0(regr|0x38|s); w2(4); w2(6); w2(4); w2(5); w0(8); regr 61 drivers/block/paride/kbic.c case 2: w0(regr|0x08|s); w2(4); w2(6); w2(4); w2(0xa5); w2(0xa1); regr 67 drivers/block/paride/kbic.c case 5: w0(0x20|s); w2(4); w2(6); w2(4); w3(regr); regr 75 drivers/block/paride/kbic.c static void kbic_write_regr( PIA *pi, int cont, int regr, int val) regr 85 drivers/block/paride/kbic.c case 2: w0(regr|0x10|s); w2(4); w2(6); w2(4); regr 91 drivers/block/paride/kbic.c case 5: w0(0x20|s); w2(4); w2(6); w2(4); w3(regr); regr 32 drivers/block/paride/ktti.c static void ktti_write_regr( PIA *pi, int cont, int regr, int val) regr 36 drivers/block/paride/ktti.c r = regr + cont_map[cont]; regr 42 drivers/block/paride/ktti.c static int ktti_read_regr( PIA *pi, int cont, int regr ) regr 46 drivers/block/paride/ktti.c r = regr + cont_map[cont]; regr 36 drivers/block/paride/on20.c static int on20_read_regr( PIA *pi, int cont, int regr ) regr 40 drivers/block/paride/on20.c r = (regr<<2) + 1 + cont; regr 59 drivers/block/paride/on20.c static void on20_write_regr( PIA *pi, int cont, int regr, int val ) regr 63 drivers/block/paride/on20.c r = (regr<<2) + 1 + cont; regr 47 drivers/block/paride/on26.c static int on26_read_regr( PIA *pi, int cont, int regr ) regr 51 drivers/block/paride/on26.c r = (regr<<2) + 1 + cont; regr 76 drivers/block/paride/on26.c static void on26_write_regr( PIA *pi, int cont, int regr, int val ) regr 80 drivers/block/paride/on26.c r = (regr<<2) + 1 + cont; regr 45 drivers/block/paride/paride.c void pi_write_regr(PIA * pi, int cont, int regr, int val) regr 47 drivers/block/paride/paride.c pi->proto->write_regr(pi, cont, regr, val); regr 52 drivers/block/paride/paride.c int pi_read_regr(PIA * pi, int cont, int regr) regr 54 drivers/block/paride/paride.c return pi->proto->read_regr(pi, cont, regr); regr 83 drivers/block/paride/paride.h extern void pi_write_regr(PIA *pi, int cont, int regr, int val); regr 85 drivers/block/paride/paride.h extern int pi_read_regr(PIA *pi, int cont, int regr); regr 122 drivers/media/platform/davinci/dm355_ccdc.c temp = regr(SYNCEN); regr 131 drivers/media/platform/davinci/dm355_ccdc.c temp = regr(SYNCEN); regr 373 drivers/media/platform/davinci/dm355_ccdc.c val = regr(DFCMEMCTL) | CCDC_DFCMEMCTL_DFCMWR_MASK; regr 380 drivers/media/platform/davinci/dm355_ccdc.c while (regr(DFCMEMCTL) & CCDC_DFCMEMCTL_DFCMWR_MASK) regr 440 drivers/media/platform/davinci/dm355_ccdc.c val = regr(DFCCTL) | (CCDC_DFCCTL_VDFCEN_MASK << regr 807 drivers/media/platform/davinci/dm355_ccdc.c return (regr(MODESET) >> 15) & 1; regr 170 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_ALAW); regr 172 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_CLAMP); regr 174 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_DCSUB); regr 176 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_BLKCMP); regr 178 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_FPC_ADDR); regr 180 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_FPC); regr 182 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_FMTCFG); regr 184 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_COLPTN); regr 186 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_FMT_HORZ); regr 188 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_FMT_VERT); regr 190 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_HSIZE_OFF); regr 192 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_SDOFST); regr 194 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_VP_OUT); regr 196 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_SYN_MODE); regr 198 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_HORZ_INFO); regr 200 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_VERT_START); regr 202 drivers/media/platform/davinci/dm644x_ccdc.c val = regr(CCDC_VERT_LINES); regr 661 drivers/media/platform/davinci/dm644x_ccdc.c return (regr(CCDC_SYN_MODE) >> 15) & 1; regr 691 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_PCR >> 2] = regr(CCDC_PCR); regr 692 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_SYN_MODE >> 2] = regr(CCDC_SYN_MODE); regr 693 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_HD_VD_WID >> 2] = regr(CCDC_HD_VD_WID); regr 694 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_PIX_LINES >> 2] = regr(CCDC_PIX_LINES); regr 695 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_HORZ_INFO >> 2] = regr(CCDC_HORZ_INFO); regr 696 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_VERT_START >> 2] = regr(CCDC_VERT_START); regr 697 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_VERT_LINES >> 2] = regr(CCDC_VERT_LINES); regr 698 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_CULLING >> 2] = regr(CCDC_CULLING); regr 699 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_HSIZE_OFF >> 2] = regr(CCDC_HSIZE_OFF); regr 700 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_SDOFST >> 2] = regr(CCDC_SDOFST); regr 701 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_SDR_ADDR >> 2] = regr(CCDC_SDR_ADDR); regr 702 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_CLAMP >> 2] = regr(CCDC_CLAMP); regr 703 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_DCSUB >> 2] = regr(CCDC_DCSUB); regr 704 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_COLPTN >> 2] = regr(CCDC_COLPTN); regr 705 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_BLKCMP >> 2] = regr(CCDC_BLKCMP); regr 706 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_FPC >> 2] = regr(CCDC_FPC); regr 707 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_FPC_ADDR >> 2] = regr(CCDC_FPC_ADDR); regr 708 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_VDINT >> 2] = regr(CCDC_VDINT); regr 709 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_ALAW >> 2] = regr(CCDC_ALAW); regr 710 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_REC656IF >> 2] = regr(CCDC_REC656IF); regr 711 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_CCDCFG >> 2] = regr(CCDC_CCDCFG); regr 712 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_FMTCFG >> 2] = regr(CCDC_FMTCFG); regr 713 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_FMT_HORZ >> 2] = regr(CCDC_FMT_HORZ); regr 714 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_FMT_VERT >> 2] = regr(CCDC_FMT_VERT); regr 715 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_FMT_ADDR0 >> 2] = regr(CCDC_FMT_ADDR0); regr 716 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_FMT_ADDR1 >> 2] = regr(CCDC_FMT_ADDR1); regr 717 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_FMT_ADDR2 >> 2] = regr(CCDC_FMT_ADDR2); regr 718 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_FMT_ADDR3 >> 2] = regr(CCDC_FMT_ADDR3); regr 719 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_FMT_ADDR4 >> 2] = regr(CCDC_FMT_ADDR4); regr 720 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_FMT_ADDR5 >> 2] = regr(CCDC_FMT_ADDR5); regr 721 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_FMT_ADDR6 >> 2] = regr(CCDC_FMT_ADDR6); regr 722 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_FMT_ADDR7 >> 2] = regr(CCDC_FMT_ADDR7); regr 723 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_PRGEVEN_0 >> 2] = regr(CCDC_PRGEVEN_0); regr 724 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_PRGEVEN_1 >> 2] = regr(CCDC_PRGEVEN_1); regr 725 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_PRGODD_0 >> 2] = regr(CCDC_PRGODD_0); regr 726 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_PRGODD_1 >> 2] = regr(CCDC_PRGODD_1); regr 727 drivers/media/platform/davinci/dm644x_ccdc.c ccdc_ctx[CCDC_VP_OUT >> 2] = regr(CCDC_VP_OUT); regr 149 drivers/media/platform/davinci/isif.c u32 new_val = (regr(offset) & ~mask) | (val & mask); regr 432 drivers/media/platform/davinci/isif.c val = regr(DFCMEMCTL) | (1 << ISIF_DFCMEMCTL_DFCMARST_SHIFT) | 1; regr 436 drivers/media/platform/davinci/isif.c while (count && (regr(DFCMEMCTL) & 0x1)) regr 453 drivers/media/platform/davinci/isif.c val = regr(DFCMEMCTL); regr 460 drivers/media/platform/davinci/isif.c while (count && (regr(DFCMEMCTL) & 0x1)) regr 837 drivers/media/platform/davinci/isif.c return (regr(MODESET) >> 15) & 0x1; regr 356 drivers/media/platform/davinci/vpif.c value = regr(reg); regr 421 drivers/media/platform/davinci/vpif.c return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK) regr 139 drivers/media/platform/davinci/vpif.h regw((regr(reg)) | (0x01 << bit), reg); regr 144 drivers/media/platform/davinci/vpif.h regw(((regr(reg)) & ~(0x01 << bit)), reg); regr 221 drivers/media/platform/davinci/vpif.h #define channel0_intr_assert() (regw((regr(VPIF_CH0_CTRL)|\ regr 225 drivers/media/platform/davinci/vpif.h #define channel1_intr_assert() (regw((regr(VPIF_CH1_CTRL)|\ regr 229 drivers/media/platform/davinci/vpif.h #define channel2_intr_assert() (regw((regr(VPIF_CH2_CTRL)|\ regr 233 drivers/media/platform/davinci/vpif.h #define channel3_intr_assert() (regw((regr(VPIF_CH3_CTRL)|\ regr 274 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_CH0_CTRL) | (VPIF_CH0_EN)), VPIF_CH0_CTRL); regr 276 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_CH0_CTRL) & (~VPIF_CH0_EN)), VPIF_CH0_CTRL); regr 283 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_CH1_CTRL) | (VPIF_CH1_EN)), VPIF_CH1_CTRL); regr 285 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_CH1_CTRL) & (~VPIF_CH1_EN)), VPIF_CH1_CTRL); regr 296 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); regr 297 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); regr 299 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH0), VPIF_INTEN); regr 300 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0), regr 303 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH0)), VPIF_INTEN); regr 304 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0), regr 318 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); regr 319 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); regr 321 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH1), VPIF_INTEN); regr 322 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1), regr 325 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH1)), VPIF_INTEN); regr 326 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1), regr 429 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL); regr 430 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_EN)), VPIF_CH2_CTRL); regr 432 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL); regr 433 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_EN)), VPIF_CH2_CTRL); regr 441 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL); regr 442 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_EN)), VPIF_CH3_CTRL); regr 444 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL); regr 445 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_EN)), VPIF_CH3_CTRL); regr 457 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); regr 458 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); regr 459 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH2), VPIF_INTEN); regr 460 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2), regr 463 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH2)), VPIF_INTEN); regr 464 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2), regr 478 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN); regr 479 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET); regr 481 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH3), VPIF_INTEN); regr 482 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3), regr 485 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH3)), VPIF_INTEN); regr 486 drivers/media/platform/davinci/vpif.h regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3), regr 611 drivers/media/platform/davinci/vpif.h status = regr(VPIF_STATUS) & mask;