register_base     146 arch/x86/math-emu/fpu_emu.h #define fpu_register(x)  ( * ((FPU_REG *)( register_base + 10 * (x & 7) )) )
register_base     147 arch/x86/math-emu/fpu_emu.h #define	st(x)      ( * ((FPU_REG *)( register_base + 10 * ((top+x) & 7) )) )
register_base    1129 arch/x86/math-emu/reg_ld_str.c 	FPU_copy_from_user(register_base + offset, s, other);
register_base    1131 arch/x86/math-emu/reg_ld_str.c 		FPU_copy_from_user(register_base, s + other, offset);
register_base    1210 arch/x86/math-emu/reg_ld_str.c 	if (__copy_to_user(d, register_base + offset, other))
register_base    1213 arch/x86/math-emu/reg_ld_str.c 		if (__copy_to_user(d + other, register_base, offset))
register_base      39 drivers/gpio/gpio-octeon.c 	u64 register_base;
register_base      46 drivers/gpio/gpio-octeon.c 	cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0);
register_base      54 drivers/gpio/gpio-octeon.c 	u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR);
register_base      69 drivers/gpio/gpio-octeon.c 	cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64);
register_base      76 drivers/gpio/gpio-octeon.c 	u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);
register_base      97 drivers/gpio/gpio-octeon.c 	gpio->register_base = (u64)reg_base;
register_base      55 drivers/gpio/gpio-thunderx.c 	u8 __iomem		*register_base;
register_base      78 drivers/gpio/gpio-thunderx.c 	u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
register_base     115 drivers/gpio/gpio-thunderx.c 	       txgpio->register_base + bit_cfg_reg(line));
register_base     127 drivers/gpio/gpio-thunderx.c 	void __iomem *reg = txgpio->register_base +
register_base     152 drivers/gpio/gpio-thunderx.c 	writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
register_base     171 drivers/gpio/gpio-thunderx.c 	bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
register_base     187 drivers/gpio/gpio-thunderx.c 	void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET;
register_base     198 drivers/gpio/gpio-thunderx.c 	bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
register_base     237 drivers/gpio/gpio-thunderx.c 		writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
register_base     261 drivers/gpio/gpio-thunderx.c 	u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT);
register_base     281 drivers/gpio/gpio-thunderx.c 		writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET);
register_base     282 drivers/gpio/gpio-thunderx.c 		writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR);
register_base     291 drivers/gpio/gpio-thunderx.c 	       txline->txgpio->register_base + intr_reg(txline->line));
register_base     299 drivers/gpio/gpio-thunderx.c 	       txline->txgpio->register_base + intr_reg(txline->line));
register_base     307 drivers/gpio/gpio-thunderx.c 	       txline->txgpio->register_base + intr_reg(txline->line));
register_base     315 drivers/gpio/gpio-thunderx.c 	       txline->txgpio->register_base + intr_reg(txline->line));
register_base     344 drivers/gpio/gpio-thunderx.c 	writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line));
register_base     481 drivers/gpio/gpio-thunderx.c 	txgpio->register_base = tbl[0];
register_base     482 drivers/gpio/gpio-thunderx.c 	if (!txgpio->register_base) {
register_base     493 drivers/gpio/gpio-thunderx.c 		u64 c = readq(txgpio->register_base + GPIO_CONST);
register_base     517 drivers/gpio/gpio-thunderx.c 		u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i));
register_base      21 drivers/net/phy/mdio-cavium.c 	smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK);
register_base      24 drivers/net/phy/mdio-cavium.c 	oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK);
register_base      39 drivers/net/phy/mdio-cavium.c 	oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
register_base      47 drivers/net/phy/mdio-cavium.c 	oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
register_base      54 drivers/net/phy/mdio-cavium.c 		smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
register_base      86 drivers/net/phy/mdio-cavium.c 	oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
register_base      93 drivers/net/phy/mdio-cavium.c 		smi_rd.u64 = oct_mdio_readq(p->register_base + SMI_RD_DAT);
register_base     125 drivers/net/phy/mdio-cavium.c 	oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
register_base     131 drivers/net/phy/mdio-cavium.c 	oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
register_base     138 drivers/net/phy/mdio-cavium.c 		smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
register_base      93 drivers/net/phy/mdio-cavium.h 	u64 register_base;
register_base      47 drivers/net/phy/mdio-octeon.c 	bus->register_base =
register_base      49 drivers/net/phy/mdio-octeon.c 	if (!bus->register_base) {
register_base      56 drivers/net/phy/mdio-octeon.c 	oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
register_base      59 drivers/net/phy/mdio-octeon.c 	snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%llx", bus->register_base);
register_base      77 drivers/net/phy/mdio-octeon.c 	oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
register_base      91 drivers/net/phy/mdio-octeon.c 	oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
register_base      87 drivers/net/phy/mdio-thunder.c 		bus->register_base = (u64)nexus->bar0 +
register_base      92 drivers/net/phy/mdio-thunder.c 		oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);
register_base     130 drivers/net/phy/mdio-thunder.c 		oct_mdio_writeq(0, bus->register_base + SMI_EN);
register_base      38 drivers/spi/spi-cavium-octeon.c 	p->register_base = reg_base;
register_base      78 drivers/spi/spi-cavium-octeon.c 	writeq(0, p->register_base + OCTEON_SPI_CFG(p));
register_base      41 drivers/spi/spi-cavium-thunderx.c 	p->register_base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0));
register_base      42 drivers/spi/spi-cavium-thunderx.c 	if (!p->register_base) {
register_base     102 drivers/spi/spi-cavium-thunderx.c 	writeq(0, p->register_base + OCTEON_SPI_CFG(p));
register_base      24 drivers/spi/spi-cavium.c 		mpi_sts.u64 = readq(p->register_base + OCTEON_SPI_STS(p));
register_base      66 drivers/spi/spi-cavium.c 		writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG(p));
register_base      78 drivers/spi/spi-cavium.c 			writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
register_base      85 drivers/spi/spi-cavium.c 		writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p));
register_base      90 drivers/spi/spi-cavium.c 				u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
register_base     102 drivers/spi/spi-cavium.c 		writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
register_base     113 drivers/spi/spi-cavium.c 	writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p));
register_base     118 drivers/spi/spi-cavium.c 			u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
register_base      18 drivers/spi/spi-cavium.h 	void __iomem *register_base;