reg_value          29 arch/arc/plat-eznps/platform.c 	u32 reg_value;
reg_value          44 arch/arc/plat-eznps/platform.c 	reg_value = ioread32be(REG_GIM_P_INT_POL_0);
reg_value          45 arch/arc/plat-eznps/platform.c 	reg_value &= ~gim_int_lines;
reg_value          46 arch/arc/plat-eznps/platform.c 	iowrite32be(reg_value, REG_GIM_P_INT_POL_0);
reg_value          49 arch/arc/plat-eznps/platform.c 	reg_value = ioread32be(REG_GIM_P_INT_SENS_0);
reg_value          50 arch/arc/plat-eznps/platform.c 	reg_value |= NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE;
reg_value          51 arch/arc/plat-eznps/platform.c 	reg_value |= NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE;
reg_value          52 arch/arc/plat-eznps/platform.c 	iowrite32be(reg_value, REG_GIM_P_INT_SENS_0);
reg_value          90 arch/ia64/include/uapi/asm/perfmon.h 	unsigned long	reg_value;	   /* initial pmc/pmd value */
reg_value        2805 arch/ia64/kernel/perfmon.c 		value      = req->reg_value;
reg_value        3047 arch/ia64/kernel/perfmon.c 		value = req->reg_value;
reg_value        3320 arch/ia64/kernel/perfmon.c 		req->reg_value            = val;
reg_value        4069 arch/ia64/kernel/perfmon.c 		req->reg_value = PMC_DFL_VAL(cnum);
reg_value        4073 arch/ia64/kernel/perfmon.c 		DPRINT(("pmc_reset_val pmc[%u]=0x%lx\n", cnum, req->reg_value));
reg_value          26 arch/mips/emma/markeins/irq.c 	u32 reg_value, reg_bitmask, reg_index;
reg_value          30 arch/mips/emma/markeins/irq.c 	reg_value = emma2rh_in32(reg_index);
reg_value          32 arch/mips/emma/markeins/irq.c 	emma2rh_out32(reg_index, reg_value | reg_bitmask);
reg_value          38 arch/mips/emma/markeins/irq.c 	u32 reg_value, reg_bitmask, reg_index;
reg_value          42 arch/mips/emma/markeins/irq.c 	reg_value = emma2rh_in32(reg_index);
reg_value          44 arch/mips/emma/markeins/irq.c 	emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
reg_value         203 arch/mips/include/asm/sn/sn0/hubio.h 	u64	 reg_value;
reg_value         445 arch/mips/include/asm/sn/sn0/hubio.h 	u64	reg_value;
reg_value         467 arch/mips/include/asm/sn/sn0/hubio.h 	u64	reg_value;
reg_value         514 arch/mips/include/asm/sn/sn0/hubio.h 	u64	reg_value;
reg_value         556 arch/mips/include/asm/sn/sn0/hubio.h 	u64	reg_value;
reg_value         672 arch/mips/include/asm/sn/sn0/hubio.h 	u64	reg_value;
reg_value         709 arch/mips/include/asm/sn/sn0/hubio.h 	u64	reg_value;
reg_value         824 arch/mips/include/asm/sn/sn0/hubio.h 	u64	reg_value;
reg_value         839 arch/mips/include/asm/sn/sn0/hubio.h #define iprb_regval	reg_value
reg_value         110 arch/mips/pci/pci-mt7620.c 	unsigned long reg_value = 0x0, retry = 0;
reg_value         113 arch/mips/pci/pci-mt7620.c 		reg_value = pcie_r32(PCIEPHY0_CFG);
reg_value         115 arch/mips/pci/pci-mt7620.c 		if (reg_value & BUSY)
reg_value          57 arch/powerpc/platforms/cell/cbe_thermal.c static inline u8 reg_to_temp(u8 reg_value)
reg_value          59 arch/powerpc/platforms/cell/cbe_thermal.c 	return ((reg_value & 0x3f) << 1) + TEMP_MIN;
reg_value         115 arch/powerpc/platforms/cell/cbe_thermal.c 	u64 reg_value;
reg_value         127 arch/powerpc/platforms/cell/cbe_thermal.c 	reg_value = in_be64(&pmd_regs->tm_tpr.val);
reg_value         130 arch/powerpc/platforms/cell/cbe_thermal.c 	reg_value &= ~(0xffull << pos);
reg_value         132 arch/powerpc/platforms/cell/cbe_thermal.c 	reg_value |= new_value << pos;
reg_value         134 arch/powerpc/platforms/cell/cbe_thermal.c 	out_be64(&pmd_regs->tm_tpr.val, reg_value);
reg_value         283 arch/powerpc/platforms/pseries/rtas-fadump.c 				       be64_to_cpu(reg_entry->reg_value));
reg_value         352 arch/powerpc/platforms/pseries/rtas-fadump.c 		cpu = (be64_to_cpu(reg_entry->reg_value) &
reg_value         100 arch/powerpc/platforms/pseries/rtas-fadump.h 	__be64		reg_value;
reg_value         820 drivers/ata/ahci_imx.c 	u32 reg_value;
reg_value         825 drivers/ata/ahci_imx.c 	const struct reg_value *values;
reg_value         831 drivers/ata/ahci_imx.c static const struct reg_value gpr13_tx_level[] = {
reg_value         866 drivers/ata/ahci_imx.c static const struct reg_value gpr13_tx_boost[] = {
reg_value         885 drivers/ata/ahci_imx.c static const struct reg_value gpr13_tx_atten[] = {
reg_value         894 drivers/ata/ahci_imx.c static const struct reg_value gpr13_rx_eq[] = {
reg_value         937 drivers/ata/ahci_imx.c 	u32 reg_value = 0;
reg_value         945 drivers/ata/ahci_imx.c 				reg_value |= prop->set_value;
reg_value         947 drivers/ata/ahci_imx.c 				reg_value |= prop->def_value;
reg_value         954 drivers/ata/ahci_imx.c 			reg_value |= prop->def_value;
reg_value         961 drivers/ata/ahci_imx.c 					prop->name, of_val, prop->values[j].reg_value);
reg_value         962 drivers/ata/ahci_imx.c 				reg_value |= prop->values[j].reg_value;
reg_value         970 drivers/ata/ahci_imx.c 			reg_value |= prop->def_value;
reg_value         974 drivers/ata/ahci_imx.c 	return reg_value;
reg_value        1095 drivers/ata/ahci_imx.c 		u32 reg_value;
reg_value        1105 drivers/ata/ahci_imx.c 		reg_value = imx_ahci_parse_props(dev, gpr13_props,
reg_value        1112 drivers/ata/ahci_imx.c 				   reg_value;
reg_value          36 drivers/clk/clk-max9485.c 	u8 reg_value;
reg_value          80 drivers/clk/clk-max9485.c 	u8 reg_value;
reg_value          96 drivers/clk/clk-max9485.c 	drvdata->reg_value &= ~mask;
reg_value          97 drivers/clk/clk-max9485.c 	drvdata->reg_value |= value;
reg_value         101 drivers/clk/clk-max9485.c 		mask, value, drvdata->reg_value);
reg_value         104 drivers/clk/clk-max9485.c 			      &drvdata->reg_value,
reg_value         105 drivers/clk/clk-max9485.c 			      sizeof(drvdata->reg_value));
reg_value         144 drivers/clk/clk-max9485.c 				   entry->reg_value);
reg_value         152 drivers/clk/clk-max9485.c 	u8 val = drvdata->reg_value & MAX9485_FREQ_MASK;
reg_value         156 drivers/clk/clk-max9485.c 		if (val == entry->reg_value)
reg_value         291 drivers/clk/clk-max9485.c 	ret = i2c_master_recv(drvdata->client, &drvdata->reg_value,
reg_value         292 drivers/clk/clk-max9485.c 			      sizeof(drvdata->reg_value));
reg_value         352 drivers/clk/clk-max9485.c 	ret = i2c_master_send(client, &drvdata->reg_value,
reg_value         353 drivers/clk/clk-max9485.c 			      sizeof(drvdata->reg_value));
reg_value         367 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 	cmd->cmd.cmd_setup_reg_prog.reg_value = value;
reg_value        4314 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		ib.ptr[ib.length_dw++] = vgpr_init_regs[i].reg_value;
reg_value        4342 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		ib.ptr[ib.length_dw++] = sgpr_init_regs[i].reg_value;
reg_value        6100 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	uint32_t reg_value;
reg_value        6124 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 				reg_value = RREG32(
reg_value        6129 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 				sec_count = reg_value &
reg_value        6131 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 				ded_count = reg_value &
reg_value          63 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h 	uint32_t reg_value;
reg_value          84 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h 	uint32_t reg_value;
reg_value          93 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h 	direct_wt->reg_value = value;
reg_value          92 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h 	uint32_t		reg_value;	/* Value to be set to the IH_RB_CNTL... register*/
reg_value         270 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h 	uint32_t	reg_value;
reg_value          50 drivers/gpu/drm/amd/amdgpu/soc15.h 	uint32_t reg_value;
reg_value          93 drivers/gpu/drm/amd/display/dc/basics/conversion.c 		uint32_t reg_value =
reg_value         102 drivers/gpu/drm/amd/display/dc/basics/conversion.c 		matrix[i] = (uint16_t)reg_value;
reg_value         104 drivers/gpu/drm/amd/display/dc/dm_services.h 	uint32_t reg_value,
reg_value         108 drivers/gpu/drm/amd/display/dc/dm_services.h 	return (mask & reg_value) >> shift;
reg_value         111 drivers/gpu/drm/amd/display/dc/dm_services.h #define get_reg_field_value(reg_value, reg_name, reg_field)\
reg_value         113 drivers/gpu/drm/amd/display/dc/dm_services.h 		(reg_value),\
reg_value         118 drivers/gpu/drm/amd/display/dc/dm_services.h 	uint32_t reg_value,
reg_value         124 drivers/gpu/drm/amd/display/dc/dm_services.h 	return (reg_value & ~mask) | (mask & (value << shift));
reg_value         127 drivers/gpu/drm/amd/display/dc/dm_services.h #define set_reg_field_value(reg_value, value, reg_name, reg_field)\
reg_value         128 drivers/gpu/drm/amd/display/dc/dm_services.h 	(reg_value) = set_reg_field_value_ex(\
reg_value         129 drivers/gpu/drm/amd/display/dc/dm_services.h 		(reg_value),\
reg_value         173 drivers/gpu/drm/amd/display/dc/dm_services.h #define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\
reg_value         175 drivers/gpu/drm/amd/display/dc/dm_services.h 		(reg_value),\
reg_value         179 drivers/gpu/drm/amd/display/dc/dm_services.h #define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\
reg_value         180 drivers/gpu/drm/amd/display/dc/dm_services.h 	(reg_value) = set_reg_field_value_ex(\
reg_value         181 drivers/gpu/drm/amd/display/dc/dm_services.h 		(reg_value),\
reg_value        1104 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP);
reg_value        1106 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		(reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT;
reg_value        1979 drivers/gpu/drm/gma500/cdv_intel_dp.c 	u32 reg_value;
reg_value        1980 drivers/gpu/drm/gma500/cdv_intel_dp.c 	reg_value = REG_READ(DSPCLK_GATE_D);
reg_value        1982 drivers/gpu/drm/gma500/cdv_intel_dp.c 	reg_value |= (DPUNIT_PIPEB_GATE_DISABLE |
reg_value        1989 drivers/gpu/drm/gma500/cdv_intel_dp.c 	REG_WRITE(DSPCLK_GATE_D, reg_value);
reg_value        2420 drivers/gpu/drm/i915/i915_drv.c 	u32 reg_value;
reg_value        2430 drivers/gpu/drm/i915/i915_drv.c 	ret = wait_for(((reg_value =
reg_value        2435 drivers/gpu/drm/i915/i915_drv.c 	trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
reg_value        1904 drivers/gpu/drm/i915/intel_uncore.c 	u32 uninitialized_var(reg_value);
reg_value        1905 drivers/gpu/drm/i915/intel_uncore.c #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)
reg_value        1919 drivers/gpu/drm/i915/intel_uncore.c 		*out_value = reg_value;
reg_value        1954 drivers/gpu/drm/i915/intel_uncore.c 	u32 reg_value;
reg_value        1964 drivers/gpu/drm/i915/intel_uncore.c 					   fast_timeout_us, 0, &reg_value);
reg_value        1970 drivers/gpu/drm/i915/intel_uncore.c 		ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore,
reg_value        1972 drivers/gpu/drm/i915/intel_uncore.c 				 (reg_value & mask) == value,
reg_value        1976 drivers/gpu/drm/i915/intel_uncore.c 	trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
reg_value        1979 drivers/gpu/drm/i915/intel_uncore.c 		*out_value = reg_value;
reg_value         130 drivers/hv/hv_kvp.c kvp_register(int reg_value)
reg_value         140 drivers/hv/hv_kvp.c 		kvp_msg->kvp_hdr.operation = reg_value;
reg_value         391 drivers/hwmon/aspeed-pwm-tacho.c 	u32 reg_value = ((div_high << type_params[type].h_value) |
reg_value         396 drivers/hwmon/aspeed-pwm-tacho.c 			   type_params[type].clk_ctrl_mask, reg_value);
reg_value         410 drivers/hwmon/aspeed-pwm-tacho.c 	u32 reg_value = (type & 0x1) << pwm_port_params[pwm_port].type_part1;
reg_value         412 drivers/hwmon/aspeed-pwm-tacho.c 	reg_value |= (type & 0x2) << pwm_port_params[pwm_port].type_part2;
reg_value         415 drivers/hwmon/aspeed-pwm-tacho.c 			   pwm_port_params[pwm_port].type_mask, reg_value);
reg_value         422 drivers/hwmon/aspeed-pwm-tacho.c 	u32 reg_value = (rising <<
reg_value         424 drivers/hwmon/aspeed-pwm-tacho.c 	reg_value |= (falling <<
reg_value         429 drivers/hwmon/aspeed-pwm-tacho.c 			   reg_value);
reg_value         443 drivers/hwmon/aspeed-pwm-tacho.c 	u32 reg_value = ((mode << TYPE_CTRL_FAN_MODE) |
reg_value         448 drivers/hwmon/aspeed-pwm-tacho.c 			   TYPE_CTRL_FAN_MASK, reg_value);
reg_value         211 drivers/i2c/busses/i2c-eg20t.c 	u32 reg_value;
reg_value         226 drivers/i2c/busses/i2c-eg20t.c 	reg_value = PCH_I2CCTL_I2CMEN;
reg_value         228 drivers/i2c/busses/i2c-eg20t.c 		reg_value |= FAST_MODE_EN;
reg_value         242 drivers/i2c/busses/i2c-eg20t.c 	reg_value |= NORMAL_INTR_ENBL;	/* Enable interrupts in normal mode */
reg_value         243 drivers/i2c/busses/i2c-eg20t.c 	iowrite32(reg_value, p + PCH_I2CCTL);
reg_value         229 drivers/iio/accel/bmc150-accel-core.c 	u8 reg_value;
reg_value         266 drivers/iio/accel/bmc150-accel-core.c 				bmc150_accel_sleep_value_table[i].reg_value;
reg_value         304 drivers/iio/temperature/mlx90632.c 				     s32 *reg_value)
reg_value         320 drivers/iio/temperature/mlx90632.c 	*reg_value = (read << 16) | (value & 0xffff);
reg_value         357 drivers/media/dvb-frontends/cxd2841er.c 	u32 reg_value = 0;
reg_value         366 drivers/media/dvb-frontends/cxd2841er.c 	reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
reg_value         367 drivers/media/dvb-frontends/cxd2841er.c 	if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
reg_value         372 drivers/media/dvb-frontends/cxd2841er.c 	data[0] = (u8)((reg_value >> 16) & 0x0F);
reg_value         373 drivers/media/dvb-frontends/cxd2841er.c 	data[1] = (u8)((reg_value >>  8) & 0xFF);
reg_value         374 drivers/media/dvb-frontends/cxd2841er.c 	data[2] = (u8)(reg_value & 0xFF);
reg_value          49 drivers/media/dvb-frontends/cxd2880/cxd2880_io.c 			     const struct cxd2880_reg_value reg_value[],
reg_value          59 drivers/media/dvb-frontends/cxd2880/cxd2880_io.c 		ret = io->write_reg(io, tgt, reg_value[i].addr,
reg_value          60 drivers/media/dvb-frontends/cxd2880/cxd2880_io.c 				    reg_value[i].value);
reg_value          52 drivers/media/dvb-frontends/cxd2880/cxd2880_io.h 				const struct cxd2880_reg_value reg_value[],
reg_value        1228 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 			      u16 *reg_value)
reg_value        1236 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 	if (!tnr_dmd || !reg_value)
reg_value        1275 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 	*reg_value = (data[0] << 8) | data[1];
reg_value        1281 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 			  u32 reg_value, int *snr)
reg_value        1286 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 	if (reg_value == 0)
reg_value        1289 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 	if (reg_value > 10876)
reg_value        1290 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 		reg_value = 10876;
reg_value        1292 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 	*snr = intlog10(reg_value) - intlog10(12600 - reg_value);
reg_value        1301 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 	u16 reg_value = 0;
reg_value        1319 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 		ret = dvbt2_read_snr_reg(tnr_dmd, &reg_value);
reg_value        1323 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 		ret = dvbt2_calc_snr(tnr_dmd, reg_value, snr);
reg_value        1340 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 	u16 reg_value = 0;
reg_value        1360 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 	ret = dvbt2_read_snr_reg(tnr_dmd, &reg_value);
reg_value        1362 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 		ret = dvbt2_calc_snr(tnr_dmd, reg_value, snr_main);
reg_value        1364 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 			reg_value = 0;
reg_value        1366 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 		reg_value = 0;
reg_value        1371 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 	reg_value_sum += reg_value;
reg_value        1373 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 	ret = dvbt2_read_snr_reg(tnr_dmd->diver_sub, &reg_value);
reg_value        1375 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 		ret = dvbt2_calc_snr(tnr_dmd->diver_sub, reg_value, snr_sub);
reg_value        1377 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 			reg_value = 0;
reg_value        1379 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 		reg_value = 0;
reg_value        1384 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt2_mon.c 	reg_value_sum += reg_value;
reg_value         392 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 			     u16 *reg_value)
reg_value         397 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 	if (!tnr_dmd || !reg_value)
reg_value         428 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 	*reg_value = (rdata[0] << 8) | rdata[1];
reg_value         434 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 			 u32 reg_value, int *snr)
reg_value         439 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 	if (reg_value == 0)
reg_value         442 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 	if (reg_value > 4996)
reg_value         443 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 		reg_value = 4996;
reg_value         445 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 	*snr = intlog10(reg_value) - intlog10(5350 - reg_value);
reg_value         454 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 	u16 reg_value = 0;
reg_value         472 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 		ret = dvbt_read_snr_reg(tnr_dmd, &reg_value);
reg_value         476 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 		ret = dvbt_calc_snr(tnr_dmd, reg_value, snr);
reg_value         493 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 	u16 reg_value = 0;
reg_value         513 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 	ret = dvbt_read_snr_reg(tnr_dmd, &reg_value);
reg_value         515 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 		ret = dvbt_calc_snr(tnr_dmd, reg_value, snr_main);
reg_value         517 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 			reg_value = 0;
reg_value         519 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 		reg_value = 0;
reg_value         524 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 	reg_value_sum += reg_value;
reg_value         526 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 	ret = dvbt_read_snr_reg(tnr_dmd->diver_sub, &reg_value);
reg_value         528 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 		ret = dvbt_calc_snr(tnr_dmd->diver_sub, reg_value, snr_sub);
reg_value         530 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 			reg_value = 0;
reg_value         532 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 		reg_value = 0;
reg_value         537 drivers/media/dvb-frontends/cxd2880/cxd2880_tnrdmd_dvbt_mon.c 	reg_value_sum += reg_value;
reg_value         829 drivers/media/dvb-frontends/si2165.c 	u32 reg_value;
reg_value         837 drivers/media/dvb-frontends/si2165.c 	reg_value = oversamp & 0x3fffffff;
reg_value         839 drivers/media/dvb-frontends/si2165.c 	dev_dbg(&state->client->dev, "Write oversamp=%#x\n", reg_value);
reg_value         840 drivers/media/dvb-frontends/si2165.c 	return si2165_writereg32(state, REG_OVERSAMP, reg_value);
reg_value         847 drivers/media/dvb-frontends/si2165.c 	s32 reg_value = 0;
reg_value         865 drivers/media/dvb-frontends/si2165.c 	reg_value = (s32)if_freq_shift;
reg_value         868 drivers/media/dvb-frontends/si2165.c 		reg_value = -reg_value;
reg_value         870 drivers/media/dvb-frontends/si2165.c 	reg_value = reg_value & 0x1fffffff;
reg_value         873 drivers/media/dvb-frontends/si2165.c 	return si2165_writereg32(state, REG_IF_FREQ_SHIFT, reg_value);
reg_value         138 drivers/media/dvb-frontends/stv0910.c 	u32  reg_value;
reg_value         605 drivers/media/dvb-frontends/stv0910.c 			int table_size, u32 reg_value)
reg_value         614 drivers/media/dvb-frontends/stv0910.c 	if (reg_value >= table[0].reg_value) {
reg_value         616 drivers/media/dvb-frontends/stv0910.c 	} else if (reg_value <= table[imax].reg_value) {
reg_value         621 drivers/media/dvb-frontends/stv0910.c 			if ((table[imin].reg_value >= reg_value) &&
reg_value         622 drivers/media/dvb-frontends/stv0910.c 			    (reg_value >= table[i].reg_value))
reg_value         628 drivers/media/dvb-frontends/stv0910.c 		reg_diff = table[imax].reg_value - table[imin].reg_value;
reg_value         631 drivers/media/dvb-frontends/stv0910.c 			value += ((s32)(reg_value - table[imin].reg_value) *
reg_value        1002 drivers/media/dvb-frontends/stv0910.c 	u16 reg_value = (tmp[0] << 8) | tmp[1];
reg_value        1004 drivers/media/dvb-frontends/stv0910.c 			      reg_value);
reg_value          41 drivers/media/dvb-frontends/stv6111.c 	u16 reg_value;
reg_value         542 drivers/media/dvb-frontends/stv6111.c 			int table_size, u16 reg_value)
reg_value         551 drivers/media/dvb-frontends/stv6111.c 	if (reg_value <= table[0].reg_value) {
reg_value         553 drivers/media/dvb-frontends/stv6111.c 	} else if (reg_value >= table[imax].reg_value) {
reg_value         558 drivers/media/dvb-frontends/stv6111.c 			if ((table[imin].reg_value <= reg_value) &&
reg_value         559 drivers/media/dvb-frontends/stv6111.c 			    (reg_value <= table[i].reg_value))
reg_value         564 drivers/media/dvb-frontends/stv6111.c 		reg_diff = table[imax].reg_value - table[imin].reg_value;
reg_value         567 drivers/media/dvb-frontends/stv6111.c 			gain += ((s32)(reg_value - table[imin].reg_value) *
reg_value          82 drivers/media/i2c/ov2680.c 	const struct reg_value *reg_data;
reg_value         140 drivers/media/i2c/ov2680.c static const struct reg_value ov2680_setting_30fps_QUXGA_800_600[] = {
reg_value         148 drivers/media/i2c/ov2680.c static const struct reg_value ov2680_setting_30fps_720P_1280_720[] = {
reg_value         155 drivers/media/i2c/ov2680.c static const struct reg_value ov2680_setting_30fps_UXGA_1600_1200[] = {
reg_value         288 drivers/media/i2c/ov2680.c 	const struct reg_value *regs = mode->reg_data;
reg_value         190 drivers/media/i2c/ov5640.c 	const struct reg_value *reg_data;
reg_value         273 drivers/media/i2c/ov5640.c static const struct reg_value ov5640_init_setting_30fps_VGA[] = {
reg_value         358 drivers/media/i2c/ov5640.c static const struct reg_value ov5640_setting_VGA_640_480[] = {
reg_value         377 drivers/media/i2c/ov5640.c static const struct reg_value ov5640_setting_XGA_1024_768[] = {
reg_value         396 drivers/media/i2c/ov5640.c static const struct reg_value ov5640_setting_QVGA_320_240[] = {
reg_value         415 drivers/media/i2c/ov5640.c static const struct reg_value ov5640_setting_QCIF_176_144[] = {
reg_value         434 drivers/media/i2c/ov5640.c static const struct reg_value ov5640_setting_NTSC_720_480[] = {
reg_value         453 drivers/media/i2c/ov5640.c static const struct reg_value ov5640_setting_PAL_720_576[] = {
reg_value         472 drivers/media/i2c/ov5640.c static const struct reg_value ov5640_setting_720P_1280_720[] = {
reg_value         491 drivers/media/i2c/ov5640.c static const struct reg_value ov5640_setting_1080P_1920_1080[] = {
reg_value         523 drivers/media/i2c/ov5640.c static const struct reg_value ov5640_setting_QSXGA_2592_1944[] = {
reg_value        1099 drivers/media/i2c/ov5640.c 	const struct reg_value *regs = mode->reg_data;
reg_value          81 drivers/media/i2c/ov5645.c 	const struct reg_value *data;
reg_value         122 drivers/media/i2c/ov5645.c static const struct reg_value ov5645_global_init_setting[] = {
reg_value         364 drivers/media/i2c/ov5645.c static const struct reg_value ov5645_setting_sxga[] = {
reg_value         412 drivers/media/i2c/ov5645.c static const struct reg_value ov5645_setting_1080p[] = {
reg_value         462 drivers/media/i2c/ov5645.c static const struct reg_value ov5645_setting_full[] = {
reg_value         623 drivers/media/i2c/ov5645.c 				     const struct reg_value *settings,
reg_value         717 drivers/media/i2c/ov5645.c 	u32 reg_value = (value * 0x10) + 0x40;
reg_value         720 drivers/media/i2c/ov5645.c 	ret = ov5645_write_reg(ov5645, OV5645_SDE_SAT_U, reg_value);
reg_value         724 drivers/media/i2c/ov5645.c 	return ov5645_write_reg(ov5645, OV5645_SDE_SAT_V, reg_value);
reg_value          53 drivers/media/i2c/ov7251.c 	const struct reg_value *data;
reg_value         102 drivers/media/i2c/ov7251.c static const struct reg_value ov7251_global_init_setting[] = {
reg_value         107 drivers/media/i2c/ov7251.c static const struct reg_value ov7251_setting_vga_30fps[] = {
reg_value         245 drivers/media/i2c/ov7251.c static const struct reg_value ov7251_setting_vga_60fps[] = {
reg_value         383 drivers/media/i2c/ov7251.c static const struct reg_value ov7251_setting_vga_90fps[] = {
reg_value         720 drivers/media/i2c/ov7251.c 				     const struct reg_value *settings,
reg_value         291 drivers/media/platform/omap3isp/isp.h void isp_reg_writel(struct isp_device *isp, u32 reg_value,
reg_value         294 drivers/media/platform/omap3isp/isp.h 	__raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
reg_value         466 drivers/media/rc/ene_ir.c 	u8 reg_value;
reg_value         473 drivers/media/rc/ene_ir.c 		reg_value = ene_read_reg(dev, ENE_IRQ) & 0xF0;
reg_value         474 drivers/media/rc/ene_ir.c 		reg_value |= ENE_IRQ_UNK_EN;
reg_value         475 drivers/media/rc/ene_ir.c 		reg_value &= ~ENE_IRQ_STATUS;
reg_value         476 drivers/media/rc/ene_ir.c 		reg_value |= (dev->irq & ENE_IRQ_MASK);
reg_value         477 drivers/media/rc/ene_ir.c 		ene_write_reg(dev, ENE_IRQ, reg_value);
reg_value          54 drivers/media/spi/gs1662.c 	u16 reg_value;
reg_value          59 drivers/media/spi/gs1662.c 	u16 reg_value;
reg_value         223 drivers/media/spi/gs1662.c 		if (reg_fmt[i].reg_value == std) {
reg_value         239 drivers/media/spi/gs1662.c 			return reg_fmt[i].reg_value | MASK_FORCE_STD;
reg_value         254 drivers/media/spi/gs1662.c 	int reg_value;
reg_value         256 drivers/media/spi/gs1662.c 	reg_value = get_register_timings(timings);
reg_value         257 drivers/media/spi/gs1662.c 	if (reg_value == 0x0)
reg_value         278 drivers/media/spi/gs1662.c 	u16 reg_value, i;
reg_value         289 drivers/media/spi/gs1662.c 		gs_read_register(gs->pdev, REG_LINES_PER_FRAME + i, &reg_value);
reg_value         290 drivers/media/spi/gs1662.c 		if (reg_value)
reg_value         298 drivers/media/spi/gs1662.c 	gs_read_register(gs->pdev, REG_STATUS, &reg_value);
reg_value         299 drivers/media/spi/gs1662.c 	if (!(reg_value & MASK_H_LOCK) || !(reg_value & MASK_V_LOCK))
reg_value         301 drivers/media/spi/gs1662.c 	if (!(reg_value & MASK_STD_LOCK))
reg_value         304 drivers/media/spi/gs1662.c 	ret = gs_status_format(reg_value, &fmt);
reg_value         329 drivers/media/spi/gs1662.c 	int reg_value;
reg_value         338 drivers/media/spi/gs1662.c 		reg_value = get_register_timings(&gs->current_timings);
reg_value         339 drivers/media/spi/gs1662.c 		return gs_write_register(gs->pdev, REG_FORCE_FMT, reg_value);
reg_value         349 drivers/media/spi/gs1662.c 	u16 reg_value, i;
reg_value         358 drivers/media/spi/gs1662.c 				       REG_LINES_PER_FRAME + i, &reg_value);
reg_value         359 drivers/media/spi/gs1662.c 		if (reg_value)
reg_value         371 drivers/media/spi/gs1662.c 	ret = gs_read_register(gs->pdev, REG_STATUS, &reg_value);
reg_value         372 drivers/media/spi/gs1662.c 	if (!(reg_value & MASK_H_LOCK))
reg_value         374 drivers/media/spi/gs1662.c 	if (!(reg_value & MASK_V_LOCK))
reg_value         376 drivers/media/spi/gs1662.c 	if (!(reg_value & MASK_STD_LOCK))
reg_value        2254 drivers/media/usb/usbvision/usbvision-core.c 	int buf_idx, err_code, reg_value;
reg_value        2271 drivers/media/usb/usbvision/usbvision-core.c 	reg_value = (16 - usbvision_read_reg(usbvision,
reg_value        2274 drivers/media/usb/usbvision/usbvision-core.c 	usbvision->usb_bandwidth = reg_value >> 1;
reg_value        2343 drivers/media/usb/usbvision/usbvision-core.c 	int buf_idx, err_code, reg_value;
reg_value        2376 drivers/media/usb/usbvision/usbvision-core.c 		reg_value = (16-usbvision_read_reg(usbvision, USBVISION_ALTER_REG)) & 0x0F;
reg_value        2378 drivers/media/usb/usbvision/usbvision-core.c 			(reg_value == 0) ? 0 : (reg_value * 64) - 1;
reg_value        2382 drivers/media/usb/usbvision/usbvision-core.c 		usbvision->usb_bandwidth = reg_value >> 1;
reg_value         308 drivers/misc/apds990x.c 	u8 reg_value;
reg_value         312 drivers/misc/apds990x.c 	reg_value = 256 - ((time_ms * TIME_STEP_SCALER) / TIMESTEP);
reg_value         314 drivers/misc/apds990x.c 	chip->a_max_result = (u16)(256 - reg_value) * APDS990X_TIME_TO_ADC;
reg_value         315 drivers/misc/apds990x.c 	return apds990x_write_byte(chip, APDS990X_ATIME, reg_value);
reg_value         263 drivers/misc/xilinx_sdfec.c 	u32 reg_value;
reg_value         267 drivers/misc/xilinx_sdfec.c 	reg_value = xsdfec_regread(xsdfec, XSDFEC_ORDER_ADDR);
reg_value         268 drivers/misc/xilinx_sdfec.c 	xsdfec->config.order = reg_value;
reg_value         278 drivers/misc/xilinx_sdfec.c 	reg_value = xsdfec_regread(xsdfec, XSDFEC_IMR_ADDR);
reg_value         279 drivers/misc/xilinx_sdfec.c 	xsdfec->config.irq.enable_isr = (reg_value & XSDFEC_ISR_MASK) > 0;
reg_value         281 drivers/misc/xilinx_sdfec.c 	reg_value = xsdfec_regread(xsdfec, XSDFEC_ECC_IMR_ADDR);
reg_value         283 drivers/misc/xilinx_sdfec.c 		(reg_value & XSDFEC_ECC_ISR_MASK) > 0;
reg_value         285 drivers/misc/xilinx_sdfec.c 	reg_value = xsdfec_regread(xsdfec, XSDFEC_AXIS_ENABLE_ADDR);
reg_value         286 drivers/misc/xilinx_sdfec.c 	sdfec_started = (reg_value & XSDFEC_AXIS_IN_ENABLE_MASK) > 0;
reg_value         437 drivers/misc/xilinx_sdfec.c 	u32 reg_value;
reg_value         445 drivers/misc/xilinx_sdfec.c 	reg_value = xsdfec_regread(xsdfec, XSDFEC_TURBO_ADDR);
reg_value         447 drivers/misc/xilinx_sdfec.c 	turbo_params.scale = (reg_value & XSDFEC_TURBO_SCALE_MASK) >>
reg_value         449 drivers/misc/xilinx_sdfec.c 	turbo_params.alg = reg_value & 0x1;
reg_value         781 drivers/misc/xilinx_sdfec.c 	u32 reg_value;
reg_value         785 drivers/misc/xilinx_sdfec.c 	reg_value = xsdfec_regread(xsdfec, XSDFEC_ACTIVE_ADDR);
reg_value         787 drivers/misc/xilinx_sdfec.c 	is_active = !!(reg_value & XSDFEC_IS_ACTIVITY_SET);
reg_value         831 drivers/misc/xilinx_sdfec.c 	u32 reg_value;
reg_value         848 drivers/misc/xilinx_sdfec.c 	reg_value = dout_words_field << XSDFEC_AXIS_DOUT_WORDS_LSB;
reg_value         849 drivers/misc/xilinx_sdfec.c 	reg_value |= dout_width_field << XSDFEC_AXIS_DOUT_WIDTH_LSB;
reg_value         850 drivers/misc/xilinx_sdfec.c 	reg_value |= din_words_field << XSDFEC_AXIS_DIN_WORDS_LSB;
reg_value         851 drivers/misc/xilinx_sdfec.c 	reg_value |= din_width_field << XSDFEC_AXIS_DIN_WIDTH_LSB;
reg_value         853 drivers/misc/xilinx_sdfec.c 	xsdfec_regwrite(xsdfec, XSDFEC_AXIS_WIDTH_ADDR, reg_value);
reg_value         223 drivers/mmc/host/dw_mmc-k3.c 	u32 reg_value;
reg_value         252 drivers/mmc/host/dw_mmc-k3.c 	reg_value = FIELD_PREP(UHS_REG_EXT_SAMPLE_PHASE_MASK, smpl_phase) |
reg_value         255 drivers/mmc/host/dw_mmc-k3.c 	mci_writel(host, UHS_REG_EXT, reg_value);
reg_value         259 drivers/mmc/host/dw_mmc-k3.c 	reg_value = FIELD_PREP(GPIO_CLK_DIV_MASK, GENCLK_DIV) |
reg_value         261 drivers/mmc/host/dw_mmc-k3.c 	mci_writel(host, GPIO, (unsigned int)reg_value | GPIO_CLK_ENABLE);
reg_value          37 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c 	int reg_value;
reg_value          40 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c 		reg_value = dsaf_read_dev(ppe_cb,
reg_value          43 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c 		dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N0_M,
reg_value          46 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c 		dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N1_M,
reg_value          49 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c 		dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N2_M,
reg_value          52 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c 		dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N3_M,
reg_value          56 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c 			ppe_cb, PPEV2_INDRECTION_TBL_REG + i * 0x4, reg_value);
reg_value         150 drivers/net/ethernet/hisilicon/hns_mdio.c 	u32 reg_value;
reg_value         156 drivers/net/ethernet/hisilicon/hns_mdio.c 		ret = regmap_read(mdio_dev->subctrl_vbase, st_reg, &reg_value);
reg_value         160 drivers/net/ethernet/hisilicon/hns_mdio.c 		reg_value &= st_msk;
reg_value         161 drivers/net/ethernet/hisilicon/hns_mdio.c 		if ((!!check_st) == (!!reg_value))
reg_value         165 drivers/net/ethernet/hisilicon/hns_mdio.c 	if ((!!check_st) != (!!reg_value))
reg_value        2256 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h 	__le32	reg_value;
reg_value        5357 drivers/net/ethernet/intel/i40e/i40e_common.c 	cmd->reg_value = cpu_to_le32(reg_val);
reg_value        5394 drivers/net/ethernet/intel/i40e/i40e_common.c 		*reg_val = le32_to_cpu(cmd->reg_value);
reg_value          24 drivers/net/ethernet/microchip/lan743x_ethtool.c 	u32 reg_value;
reg_value          26 drivers/net/ethernet/microchip/lan743x_ethtool.c 	reg_value = lan743x_csr_read(adapter, OTP_PWR_DN);
reg_value          28 drivers/net/ethernet/microchip/lan743x_ethtool.c 	if (reg_value & OTP_PWR_DN_PWRDN_N_) {
reg_value          30 drivers/net/ethernet/microchip/lan743x_ethtool.c 		reg_value &= ~OTP_PWR_DN_PWRDN_N_;
reg_value          31 drivers/net/ethernet/microchip/lan743x_ethtool.c 		lan743x_csr_write(adapter, OTP_PWR_DN, reg_value);
reg_value          41 drivers/net/ethernet/microchip/lan743x_ethtool.c 	u32 reg_value;
reg_value          43 drivers/net/ethernet/microchip/lan743x_ethtool.c 	reg_value = lan743x_csr_read(adapter, OTP_PWR_DN);
reg_value          44 drivers/net/ethernet/microchip/lan743x_ethtool.c 	if (!(reg_value & OTP_PWR_DN_PWRDN_N_)) {
reg_value          46 drivers/net/ethernet/microchip/lan743x_ethtool.c 		reg_value |= OTP_PWR_DN_PWRDN_N_;
reg_value          47 drivers/net/ethernet/microchip/lan743x_ethtool.c 		lan743x_csr_write(adapter, OTP_PWR_DN, reg_value);
reg_value          27 drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c 	u32 reg_value;
reg_value          48 drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c 	reg_value = data;
reg_value          50 drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c 		reg_value <<= GMAC4_PTP_SSIR_SSINC_SHIFT;
reg_value          52 drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c 	writel(reg_value, ioaddr + PTP_SSIR);
reg_value         347 drivers/net/wireless/ath/ath10k/ce.c 	u32 reg_value;
reg_value         349 drivers/net/wireless/ath/ath10k/ce.c 	reg_value = ath10k_ce_read32(ar, ce_ctrl_addr +
reg_value         351 drivers/net/wireless/ath/ath10k/ce.c 	reg_value &= ~CE_DESC_ADDR_HI_MASK;
reg_value         352 drivers/net/wireless/ath/ath10k/ce.c 	reg_value |= addr_hi;
reg_value         354 drivers/net/wireless/ath/ath10k/ce.c 			  ar->hw_ce_regs->dr_base_addr_hi, reg_value);
reg_value         429 drivers/net/wireless/marvell/mwifiex/debugfs.c 	u32 reg_type = 0, reg_offset = 0, reg_value = UINT_MAX;
reg_value         435 drivers/net/wireless/marvell/mwifiex/debugfs.c 	sscanf(buf, "%u %x %x", &reg_type, &reg_offset, &reg_value);
reg_value         443 drivers/net/wireless/marvell/mwifiex/debugfs.c 		saved_reg_value = reg_value;
reg_value         467 drivers/net/wireless/marvell/mwifiex/debugfs.c 	u32 reg_value;
reg_value         492 drivers/net/wireless/marvell/mwifiex/debugfs.c 			       saved_reg_offset, &reg_value);
reg_value         499 drivers/net/wireless/marvell/mwifiex/debugfs.c 			saved_reg_offset, reg_value);
reg_value        1523 drivers/net/wireless/marvell/mwifiex/main.h 		      u32 reg_offset, u32 reg_value);
reg_value        1256 drivers/net/wireless/marvell/mwifiex/sta_ioctl.c 		  u32 reg_offset, u32 reg_value)
reg_value        1262 drivers/net/wireless/marvell/mwifiex/sta_ioctl.c 	reg_rw.value = reg_value;
reg_value         243 drivers/phy/allwinner/phy-sun4i-usb.c 	u32 bits, reg_value;
reg_value         256 drivers/phy/allwinner/phy-sun4i-usb.c 	reg_value = readl(phy->pmu);
reg_value         259 drivers/phy/allwinner/phy-sun4i-usb.c 		reg_value |= bits;
reg_value         261 drivers/phy/allwinner/phy-sun4i-usb.c 		reg_value &= ~bits;
reg_value         263 drivers/phy/allwinner/phy-sun4i-usb.c 	writel(reg_value, phy->pmu);
reg_value          46 drivers/phy/allwinner/phy-sun9i-usb.c 	u32 bits, reg_value;
reg_value          56 drivers/phy/allwinner/phy-sun9i-usb.c 	reg_value = readl(phy->pmu);
reg_value          59 drivers/phy/allwinner/phy-sun9i-usb.c 		reg_value |= bits;
reg_value          61 drivers/phy/allwinner/phy-sun9i-usb.c 		reg_value &= ~bits;
reg_value          63 drivers/phy/allwinner/phy-sun9i-usb.c 	writel(reg_value, phy->pmu);
reg_value        1117 drivers/power/supply/ab8500_charger.c 	u8 reg_value;
reg_value        1124 drivers/power/supply/ab8500_charger.c 		reg, &reg_value);
reg_value        1133 drivers/power/supply/ab8500_charger.c 		prev_curr_index = (reg_value >> shift_value);
reg_value        1141 drivers/power/supply/ab8500_charger.c 		prev_curr_index = (reg_value >> shift_value);
reg_value        1150 drivers/power/supply/ab8500_charger.c 		prev_curr_index = (reg_value >> shift_value);
reg_value        1966 drivers/power/supply/ab8500_charger.c 	u8 reg_value;
reg_value        1974 drivers/power/supply/ab8500_charger.c 			AB8500_CHARGER, AB8500_CH_STATUS2_REG, &reg_value);
reg_value        1979 drivers/power/supply/ab8500_charger.c 		if (!(reg_value & MAIN_CH_NOK)) {
reg_value        1987 drivers/power/supply/ab8500_charger.c 			&reg_value);
reg_value        1992 drivers/power/supply/ab8500_charger.c 		if (!(reg_value & VBUS_OVV_TH)) {
reg_value        2436 drivers/power/supply/ab8500_charger.c 	u8 reg_value;
reg_value        2444 drivers/power/supply/ab8500_charger.c 		AB8500_CHARGER, AB8500_CH_USBCH_STAT2_REG, &reg_value);
reg_value        2451 drivers/power/supply/ab8500_charger.c 	if (reg_value & VBUS_CH_NOK) {
reg_value        2475 drivers/power/supply/ab8500_charger.c 	u8 reg_value;
reg_value        2482 drivers/power/supply/ab8500_charger.c 		AB8500_CHARGER, AB8500_CH_STATUS2_REG, &reg_value);
reg_value        2487 drivers/power/supply/ab8500_charger.c 	if (reg_value & MAIN_CH_TH_PROT)
reg_value        2505 drivers/power/supply/ab8500_charger.c 	u8 reg_value;
reg_value        2512 drivers/power/supply/ab8500_charger.c 		AB8500_CHARGER, AB8500_CH_USBCH_STAT2_REG, &reg_value);
reg_value        2517 drivers/power/supply/ab8500_charger.c 	if (reg_value & USB_CH_TH_PROT)
reg_value        2634 drivers/power/supply/ab8500_charger.c 	u8 reg_value;
reg_value        2643 drivers/power/supply/ab8500_charger.c 			AB8500_CH_USBCH_STAT2_REG, &reg_value);
reg_value        2650 drivers/power/supply/ab8500_charger.c 		reg_value >> AUTO_VBUS_IN_CURR_LIM_SHIFT];
reg_value        1823 drivers/power/supply/ab8500_fg.c 	u8 reg_value;
reg_value        1834 drivers/power/supply/ab8500_fg.c 		&reg_value);
reg_value        1839 drivers/power/supply/ab8500_fg.c 	if ((reg_value & BATT_OVV) == BATT_OVV) {
reg_value        2555 drivers/power/supply/ab8500_fg.c 	u8 reg_value;
reg_value        2560 drivers/power/supply/ab8500_fg.c 		AB8505_RTC_PCUT_FLAG_TIME_REG, &reg_value);
reg_value        2567 drivers/power/supply/ab8500_fg.c 	return scnprintf(buf, PAGE_SIZE, "%d\n", (reg_value & 0x7F));
reg_value        2578 drivers/power/supply/ab8500_fg.c 	int reg_value;
reg_value        2582 drivers/power/supply/ab8500_fg.c 	if (kstrtoint(buf, 10, &reg_value))
reg_value        2585 drivers/power/supply/ab8500_fg.c 	if (reg_value > 0x7F) {
reg_value        2591 drivers/power/supply/ab8500_fg.c 		AB8505_RTC_PCUT_FLAG_TIME_REG, (u8)reg_value);
reg_value        2605 drivers/power/supply/ab8500_fg.c 	u8 reg_value;
reg_value        2610 drivers/power/supply/ab8500_fg.c 		AB8505_RTC_PCUT_MAX_TIME_REG, &reg_value);
reg_value        2617 drivers/power/supply/ab8500_fg.c 	return scnprintf(buf, PAGE_SIZE, "%d\n", (reg_value & 0x7F));
reg_value        2629 drivers/power/supply/ab8500_fg.c 	int reg_value;
reg_value        2633 drivers/power/supply/ab8500_fg.c 	if (kstrtoint(buf, 10, &reg_value))
reg_value        2636 drivers/power/supply/ab8500_fg.c 	if (reg_value > 0x7F) {
reg_value        2642 drivers/power/supply/ab8500_fg.c 		AB8505_RTC_PCUT_MAX_TIME_REG, (u8)reg_value);
reg_value        2656 drivers/power/supply/ab8500_fg.c 	u8 reg_value;
reg_value        2661 drivers/power/supply/ab8500_fg.c 		AB8505_RTC_PCUT_RESTART_REG, &reg_value);
reg_value        2668 drivers/power/supply/ab8500_fg.c 	return scnprintf(buf, PAGE_SIZE, "%d\n", (reg_value & 0xF));
reg_value        2679 drivers/power/supply/ab8500_fg.c 	int reg_value;
reg_value        2683 drivers/power/supply/ab8500_fg.c 	if (kstrtoint(buf, 10, &reg_value))
reg_value        2686 drivers/power/supply/ab8500_fg.c 	if (reg_value > 0xF) {
reg_value        2692 drivers/power/supply/ab8500_fg.c 						AB8505_RTC_PCUT_RESTART_REG, (u8)reg_value);
reg_value        2707 drivers/power/supply/ab8500_fg.c 	u8 reg_value;
reg_value        2712 drivers/power/supply/ab8500_fg.c 						AB8505_RTC_PCUT_TIME_REG, &reg_value);
reg_value        2719 drivers/power/supply/ab8500_fg.c 	return scnprintf(buf, PAGE_SIZE, "%d\n", (reg_value & 0x7F));
reg_value        2730 drivers/power/supply/ab8500_fg.c 	u8 reg_value;
reg_value        2735 drivers/power/supply/ab8500_fg.c 						AB8505_RTC_PCUT_RESTART_REG, &reg_value);
reg_value        2742 drivers/power/supply/ab8500_fg.c 	return scnprintf(buf, PAGE_SIZE, "%d\n", (reg_value & 0xF0) >> 4);
reg_value        2753 drivers/power/supply/ab8500_fg.c 	u8 reg_value;
reg_value        2758 drivers/power/supply/ab8500_fg.c 						AB8505_RTC_PCUT_CTL_STATUS_REG, &reg_value);
reg_value        2763 drivers/power/supply/ab8500_fg.c 	return scnprintf(buf, PAGE_SIZE, "%d\n", (reg_value & 0x1));
reg_value        2774 drivers/power/supply/ab8500_fg.c 	int reg_value;
reg_value        2778 drivers/power/supply/ab8500_fg.c 	if (kstrtoint(buf, 10, &reg_value))
reg_value        2781 drivers/power/supply/ab8500_fg.c 	if (reg_value > 0x1) {
reg_value        2787 drivers/power/supply/ab8500_fg.c 						AB8505_RTC_PCUT_CTL_STATUS_REG, (u8)reg_value);
reg_value        2802 drivers/power/supply/ab8500_fg.c 	u8 reg_value;
reg_value        2807 drivers/power/supply/ab8500_fg.c 						AB8505_RTC_PCUT_CTL_STATUS_REG,  &reg_value);
reg_value        2814 drivers/power/supply/ab8500_fg.c 	return scnprintf(buf, PAGE_SIZE, "%d\n", ((reg_value & 0x10) >> 4));
reg_value        2825 drivers/power/supply/ab8500_fg.c 	u8 reg_value;
reg_value        2830 drivers/power/supply/ab8500_fg.c 						AB8505_RTC_PCUT_DEBOUNCE_REG,  &reg_value);
reg_value        2837 drivers/power/supply/ab8500_fg.c 	return scnprintf(buf, PAGE_SIZE, "%d\n", (reg_value & 0x7));
reg_value        2848 drivers/power/supply/ab8500_fg.c 	int reg_value;
reg_value        2852 drivers/power/supply/ab8500_fg.c 	if (kstrtoint(buf, 10, &reg_value))
reg_value        2855 drivers/power/supply/ab8500_fg.c 	if (reg_value > 0x7) {
reg_value        2861 drivers/power/supply/ab8500_fg.c 						AB8505_RTC_PCUT_DEBOUNCE_REG, (u8)reg_value);
reg_value        2875 drivers/power/supply/ab8500_fg.c 	u8 reg_value;
reg_value        2880 drivers/power/supply/ab8500_fg.c 						AB8505_RTC_PCUT_CTL_STATUS_REG, &reg_value);
reg_value        2887 drivers/power/supply/ab8500_fg.c 	return scnprintf(buf, PAGE_SIZE, "%d\n", ((reg_value & 0x20) >> 5));
reg_value         851 drivers/power/supply/pm2301_charger.c 	u8 reg_value;
reg_value         857 drivers/power/supply/pm2301_charger.c 		pm2xxx_reg_read(pm2, PM2XXX_SRCE_REG_INT4, &reg_value);
reg_value         859 drivers/power/supply/pm2301_charger.c 		if (!(reg_value & (PM2XXX_INT4_S_ITVPWR1OVV |
reg_value         442 drivers/regulator/mc13892-regulator.c 	u32 reg_value;
reg_value         447 drivers/regulator/mc13892-regulator.c 	reg_value = selector;
reg_value         467 drivers/regulator/mc13892-regulator.c 			reg_value -= MC13892_SWxHI_SEL_OFFSET;
reg_value         468 drivers/regulator/mc13892-regulator.c 			reg_value |= MC13892_SWITCHERS0_SWxHI;
reg_value         470 drivers/regulator/mc13892-regulator.c 			reg_value &= ~MC13892_SWITCHERS0_SWxHI;
reg_value         476 drivers/regulator/mc13892-regulator.c 			      mask, reg_value);
reg_value         375 drivers/regulator/mt6323-regulator.c 	u32 reg_value;
reg_value         382 drivers/regulator/mt6323-regulator.c 	if (regmap_read(mt6323->regmap, MT6323_CID, &reg_value) < 0) {
reg_value         386 drivers/regulator/mt6323-regulator.c 	dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value);
reg_value         343 drivers/regulator/mt6397-regulator.c 	u32 reg_value, version;
reg_value         350 drivers/regulator/mt6397-regulator.c 	if (regmap_read(mt6397->regmap, MT6397_CID, &reg_value) < 0) {
reg_value         354 drivers/regulator/mt6397-regulator.c 	dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value);
reg_value         356 drivers/regulator/mt6397-regulator.c 	version = (reg_value & 0xFF);
reg_value        1243 drivers/scsi/3w-sas.c 	u32 reg_value;
reg_value        1245 drivers/scsi/3w-sas.c 	reg_value = readl(reg);
reg_value        1248 drivers/scsi/3w-sas.c         while ((reg_value & value) != result) {
reg_value        1249 drivers/scsi/3w-sas.c 		reg_value = readl(reg);
reg_value         620 drivers/scsi/arm/acornscsi.c     unsigned char reg_value;
reg_value         643 drivers/scsi/arm/acornscsi.c 	if (syncxfer == sync_xfer_table[i].reg_value)
reg_value         680 drivers/scsi/arm/acornscsi.c     return sync_xfer_table[round_period(period)].reg_value |
reg_value        2765 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c 			u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
reg_value        2768 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c 			switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
reg_value        2787 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c 				reg_value = hisi_sas_read32(hisi_hba,
reg_value        2789 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c 				if (reg_value & BIT(phy_no)) {
reg_value        1701 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c 	u32 reg_value;
reg_value        1706 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c 	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
reg_value        1707 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c 	sphy->loss_of_dword_sync_count += reg_value;
reg_value        1710 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c 	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
reg_value        1711 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c 	sphy->phy_reset_problem_count += reg_value;
reg_value        1714 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c 	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
reg_value        1715 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c 	sphy->invalid_dword_count += reg_value;
reg_value        1718 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c 	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
reg_value        1719 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c 	sphy->running_disparity_error_count += reg_value;
reg_value        1722 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c 	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
reg_value        1723 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c 	phy->code_violation_err_count += reg_value;
reg_value        1749 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c 		u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
reg_value        1753 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c 			 phy_no, reg_value);
reg_value        1754 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c 		if (reg_value & BIT(4))
reg_value        1779 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c 		u32 reg_value;
reg_value        1783 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c 				HILINK_ERR_DFX, reg_value,
reg_value        1784 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c 				!((reg_value >> 8) & BIT(phy_no)),
reg_value         187 drivers/scsi/isci/registers.h #define SCU_SET_BIT(name, reg_value) \
reg_value         188 drivers/scsi/isci/registers.h 	((reg_value) | SCU_GEN_BIT(name))
reg_value         190 drivers/scsi/isci/registers.h #define SCU_CLEAR_BIT(name, reg_value) \
reg_value         191 drivers/scsi/isci/registers.h 	((reg_value)$ ~(SCU_GEN_BIT(name)))
reg_value         341 drivers/scsi/wd33c93.c 	result = sx_table[round_period(period,sx_table)].reg_value;
reg_value        1877 drivers/scsi/wd33c93.c 	sx_table[0].reg_value = 0x20;
reg_value        1880 drivers/scsi/wd33c93.c 		sx_table[i].reg_value = (i+1)*0x10;
reg_value        1882 drivers/scsi/wd33c93.c 	sx_table[7].reg_value = 0;
reg_value        1884 drivers/scsi/wd33c93.c 	sx_table[8].reg_value = 0;
reg_value         208 drivers/scsi/wd33c93.h    uchar          reg_value;
reg_value         166 drivers/soc/sunxi/sunxi_sram.c 							 unsigned int *reg_value)
reg_value         201 drivers/soc/sunxi/sunxi_sram.c 			if (reg_value)
reg_value         202 drivers/soc/sunxi/sunxi_sram.c 				*reg_value = func->reg_val;
reg_value        4814 drivers/tty/synclink_gt.c 	unsigned int reg_value;
reg_value        4840 drivers/tty/synclink_gt.c 	reg_value = rd_reg32(info, TDCSR);
reg_value        4843 drivers/tty/synclink_gt.c 	if (reg_value & BIT0)
reg_value        4847 drivers/tty/synclink_gt.c 	total_count += (reg_value >> 8) & 0xff;
reg_value        1014 drivers/video/fbdev/via/hw.c 	int reg_value;
reg_value        1020 drivers/video/fbdev/via/hw.c 		reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
reg_value        1024 drivers/video/fbdev/via/hw.c 		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
reg_value        1027 drivers/video/fbdev/via/hw.c 		reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
reg_value        1031 drivers/video/fbdev/via/hw.c 		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
reg_value        1039 drivers/video/fbdev/via/hw.c 	int reg_value;
reg_value        1159 drivers/video/fbdev/via/hw.c 		reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
reg_value        1163 drivers/video/fbdev/via/hw.c 		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
reg_value        1166 drivers/video/fbdev/via/hw.c 		reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
reg_value        1173 drivers/video/fbdev/via/hw.c 		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
reg_value        1176 drivers/video/fbdev/via/hw.c 		reg_value =
reg_value        1184 drivers/video/fbdev/via/hw.c 		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
reg_value        1187 drivers/video/fbdev/via/hw.c 		reg_value =
reg_value        1196 drivers/video/fbdev/via/hw.c 		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
reg_value        1309 drivers/video/fbdev/via/hw.c 			reg_value =
reg_value        1319 drivers/video/fbdev/via/hw.c 			viafb_load_reg(reg_value,
reg_value        1324 drivers/video/fbdev/via/hw.c 			reg_value =
reg_value        1332 drivers/video/fbdev/via/hw.c 			viafb_load_reg(reg_value,
reg_value        1337 drivers/video/fbdev/via/hw.c 		reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
reg_value        1344 drivers/video/fbdev/via/hw.c 		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
reg_value        1347 drivers/video/fbdev/via/hw.c 		reg_value =
reg_value        1355 drivers/video/fbdev/via/hw.c 		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
reg_value        1358 drivers/video/fbdev/via/hw.c 		reg_value =
reg_value        1367 drivers/video/fbdev/via/hw.c 		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
reg_value         338 drivers/video/fbdev/via/lcd.c 	int reg_value = 0;
reg_value         353 drivers/video/fbdev/via/lcd.c 			reg_value =
reg_value         359 drivers/video/fbdev/via/lcd.c 			viafb_load_reg(reg_value,
reg_value         373 drivers/video/fbdev/via/lcd.c 			reg_value =
reg_value         380 drivers/video/fbdev/via/lcd.c 			viafb_load_reg(reg_value,
reg_value         385 drivers/video/fbdev/via/lcd.c 		DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d", reg_value);
reg_value         397 drivers/video/fbdev/via/lcd.c 			reg_value =
reg_value         403 drivers/video/fbdev/via/lcd.c 			viafb_load_reg(reg_value,
reg_value         417 drivers/video/fbdev/via/lcd.c 			reg_value =
reg_value         424 drivers/video/fbdev/via/lcd.c 			viafb_load_reg(reg_value,
reg_value         429 drivers/video/fbdev/via/lcd.c 		DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d", reg_value);
reg_value          66 sound/pci/echoaudio/echoaudio_gml.c 	__le32 reg_value;
reg_value          77 sound/pci/echoaudio/echoaudio_gml.c 	reg_value = cpu_to_le32(value);
reg_value          78 sound/pci/echoaudio/echoaudio_gml.c 	if (reg_value != chip->comm_page->control_register || force) {
reg_value          81 sound/pci/echoaudio/echoaudio_gml.c 		chip->comm_page->control_register = reg_value;
reg_value         154 sound/pci/oxygen/oxygen_mixer.c 	unsigned int reg_value;
reg_value         159 sound/pci/oxygen/oxygen_mixer.c 		reg_value = reg_values[chip->dac_routing];
reg_value         162 sound/pci/oxygen/oxygen_mixer.c 		reg_value = (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
reg_value         167 sound/pci/oxygen/oxygen_mixer.c 		reg_value = (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
reg_value         172 sound/pci/oxygen/oxygen_mixer.c 		reg_value = chip->model.adjust_dac_routing(chip, reg_value);
reg_value         173 sound/pci/oxygen/oxygen_mixer.c 	oxygen_write16_masked(chip, OXYGEN_PLAY_ROUTING, reg_value,
reg_value         517 sound/pci/oxygen/xonar_wm87x6.c 	u16 reg_value;
reg_value         523 sound/pci/oxygen/xonar_wm87x6.c 	reg_value = data->wm8776_regs[reg_index] & ~bit;
reg_value         525 sound/pci/oxygen/xonar_wm87x6.c 		reg_value |= bit;
reg_value         526 sound/pci/oxygen/xonar_wm87x6.c 	changed = reg_value != data->wm8776_regs[reg_index];
reg_value         528 sound/pci/oxygen/xonar_wm87x6.c 		wm8776_write(chip, reg_index, reg_value);
reg_value         612 sound/pci/oxygen/xonar_wm87x6.c 	u16 mask, reg_value;
reg_value         633 sound/pci/oxygen/xonar_wm87x6.c 	reg_value = data->wm8776_regs[reg_index];
reg_value         634 sound/pci/oxygen/xonar_wm87x6.c 	reg_value &= ~(mask << shift);
reg_value         635 sound/pci/oxygen/xonar_wm87x6.c 	reg_value |= value << shift;
reg_value         636 sound/pci/oxygen/xonar_wm87x6.c 	wm8776_write_cached(chip, reg_index, reg_value);
reg_value         919 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c 	unsigned int reg_value;
reg_value         922 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c 	ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &reg_value);
reg_value         925 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c 		reg_value = AFE_IRQ_STATUS_BITS;
reg_value         938 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c 		if (!(reg_value & (1 << irq->irq_data->irq_clr_shift)))
reg_value         947 sound/soc/mediatek/mt8173/mt8173-afe-pcm.c 		     reg_value & AFE_IRQ_STATUS_BITS);