reg_val 162 arch/arm/mach-qcom/platsmp.c unsigned reg_val; reg_val 200 arch/arm/mach-qcom/platsmp.c reg_val = (64 << BHS_CNT_SHIFT) | (0x3f << LDO_PWR_DWN_SHIFT) | BHS_EN; reg_val 201 arch/arm/mach-qcom/platsmp.c writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL); reg_val 207 arch/arm/mach-qcom/platsmp.c reg_val |= 0x3f << BHS_SEG_SHIFT; reg_val 208 arch/arm/mach-qcom/platsmp.c writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL); reg_val 214 arch/arm/mach-qcom/platsmp.c reg_val |= 0x3f << LDO_BYP_SHIFT; reg_val 215 arch/arm/mach-qcom/platsmp.c writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL); reg_val 222 arch/arm/mach-qcom/platsmp.c reg_val = COREPOR_RST | CLAMP; reg_val 223 arch/arm/mach-qcom/platsmp.c writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); reg_val 227 arch/arm/mach-qcom/platsmp.c reg_val &= ~CLAMP; reg_val 228 arch/arm/mach-qcom/platsmp.c writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); reg_val 232 arch/arm/mach-qcom/platsmp.c reg_val &= ~COREPOR_RST; reg_val 233 arch/arm/mach-qcom/platsmp.c writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); reg_val 236 arch/arm/mach-qcom/platsmp.c reg_val |= CORE_PWRD_UP; reg_val 237 arch/arm/mach-qcom/platsmp.c writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); reg_val 499 arch/arm/plat-orion/gpio.c u32 reg_val; reg_val 503 arch/arm/plat-orion/gpio.c reg_val = irq_reg_readl(gc, ct->regs.mask); reg_val 504 arch/arm/plat-orion/gpio.c reg_val |= mask; reg_val 505 arch/arm/plat-orion/gpio.c irq_reg_writel(gc, reg_val, ct->regs.mask); reg_val 514 arch/arm/plat-orion/gpio.c u32 reg_val; reg_val 517 arch/arm/plat-orion/gpio.c reg_val = irq_reg_readl(gc, ct->regs.mask); reg_val 518 arch/arm/plat-orion/gpio.c reg_val &= ~mask; reg_val 519 arch/arm/plat-orion/gpio.c irq_reg_writel(gc, reg_val, ct->regs.mask); reg_val 74 arch/mips/include/asm/mips-cps.h uint##sz##_t reg_val = read_##unit##_##name(); \ reg_val 75 arch/mips/include/asm/mips-cps.h reg_val &= ~mask; \ reg_val 76 arch/mips/include/asm/mips-cps.h reg_val |= val; \ reg_val 77 arch/mips/include/asm/mips-cps.h write_##unit##_##name(reg_val); \ reg_val 1786 arch/mips/kernel/traps.c unsigned int reg_val; reg_val 1791 arch/mips/kernel/traps.c reg_val = read_c0_cacheerr(); reg_val 1792 arch/mips/kernel/traps.c printk("c0_cacheerr == %08x\n", reg_val); reg_val 1795 arch/mips/kernel/traps.c reg_val & (1<<30) ? "secondary" : "primary", reg_val 1796 arch/mips/kernel/traps.c reg_val & (1<<31) ? "data" : "insn"); reg_val 1800 arch/mips/kernel/traps.c reg_val & (1<<29) ? "ED " : "", reg_val 1801 arch/mips/kernel/traps.c reg_val & (1<<28) ? "ET " : "", reg_val 1802 arch/mips/kernel/traps.c reg_val & (1<<27) ? "ES " : "", reg_val 1803 arch/mips/kernel/traps.c reg_val & (1<<26) ? "EE " : "", reg_val 1804 arch/mips/kernel/traps.c reg_val & (1<<25) ? "EB " : "", reg_val 1805 arch/mips/kernel/traps.c reg_val & (1<<24) ? "EI " : "", reg_val 1806 arch/mips/kernel/traps.c reg_val & (1<<23) ? "E1 " : "", reg_val 1807 arch/mips/kernel/traps.c reg_val & (1<<22) ? "E0 " : ""); reg_val 1810 arch/mips/kernel/traps.c reg_val & (1<<29) ? "ED " : "", reg_val 1811 arch/mips/kernel/traps.c reg_val & (1<<28) ? "ET " : "", reg_val 1812 arch/mips/kernel/traps.c reg_val & (1<<26) ? "EE " : "", reg_val 1813 arch/mips/kernel/traps.c reg_val & (1<<25) ? "EB " : "", reg_val 1814 arch/mips/kernel/traps.c reg_val & (1<<24) ? "EI " : "", reg_val 1815 arch/mips/kernel/traps.c reg_val & (1<<23) ? "E1 " : "", reg_val 1816 arch/mips/kernel/traps.c reg_val & (1<<22) ? "E0 " : ""); reg_val 1818 arch/mips/kernel/traps.c printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); reg_val 1821 arch/mips/kernel/traps.c if (reg_val & (1<<22)) reg_val 1824 arch/mips/kernel/traps.c if (reg_val & (1<<23)) reg_val 1834 arch/mips/kernel/traps.c unsigned int reg_val; reg_val 1843 arch/mips/kernel/traps.c reg_val = read_c0_cacheerr(); reg_val 1844 arch/mips/kernel/traps.c pr_err("c0_cacheerr == %08x\n", reg_val); reg_val 1846 arch/mips/kernel/traps.c if ((reg_val & 0xc0000000) == 0xc0000000) { reg_val 1850 arch/mips/kernel/traps.c reg_val & (1<<30) ? "secondary" : "primary", reg_val 1851 arch/mips/kernel/traps.c reg_val & (1<<31) ? "data" : "insn"); reg_val 171 arch/mips/netlogic/xlp/ahci-init-xlp2.c u32 reg_val; reg_val 173 arch/mips/netlogic/xlp/ahci-init-xlp2.c reg_val = nlm_read_sata_reg(regbase, off); reg_val 174 arch/mips/netlogic/xlp/ahci-init-xlp2.c nlm_write_sata_reg(regbase, off, (reg_val & ~bit)); reg_val 179 arch/mips/netlogic/xlp/ahci-init-xlp2.c u32 reg_val; reg_val 181 arch/mips/netlogic/xlp/ahci-init-xlp2.c reg_val = nlm_read_sata_reg(regbase, off); reg_val 182 arch/mips/netlogic/xlp/ahci-init-xlp2.c nlm_write_sata_reg(regbase, off, (reg_val | bit)); reg_val 255 arch/mips/netlogic/xlp/ahci-init-xlp2.c u32 reg_val; reg_val 315 arch/mips/netlogic/xlp/ahci-init-xlp2.c reg_val = nlm_read_sata_reg(regbase, SATA_STATUS); reg_val 316 arch/mips/netlogic/xlp/ahci-init-xlp2.c if ((reg_val & P1_PHY_READY) && (reg_val & P0_PHY_READY)) reg_val 321 arch/mips/netlogic/xlp/ahci-init-xlp2.c if (reg_val & P0_PHY_READY) reg_val 325 arch/mips/netlogic/xlp/ahci-init-xlp2.c if (reg_val & P1_PHY_READY) reg_val 97 arch/mips/netlogic/xlp/ahci-init.c uint32_t reg_val; reg_val 99 arch/mips/netlogic/xlp/ahci-init.c reg_val = nlm_read_sata_reg(regbase, off); reg_val 100 arch/mips/netlogic/xlp/ahci-init.c nlm_write_sata_reg(regbase, off, (reg_val & ~bit)); reg_val 105 arch/mips/netlogic/xlp/ahci-init.c uint32_t reg_val; reg_val 107 arch/mips/netlogic/xlp/ahci-init.c reg_val = nlm_read_sata_reg(regbase, off); reg_val 108 arch/mips/netlogic/xlp/ahci-init.c nlm_write_sata_reg(regbase, off, (reg_val | bit)); reg_val 113 arch/mips/netlogic/xlp/ahci-init.c uint32_t reg_val; reg_val 137 arch/mips/netlogic/xlp/ahci-init.c reg_val = nlm_read_sata_reg(regbase, SATA_STATUS); reg_val 139 arch/mips/netlogic/xlp/ahci-init.c } while (((reg_val & 0xF0) != 0xF0) && (i < 10000)); reg_val 142 arch/mips/netlogic/xlp/ahci-init.c if (reg_val & (P0_PHY_READY << i)) reg_val 70 arch/mips/pci/fixup-malta.c unsigned char reg_val; reg_val 84 arch/mips/pci/fixup-malta.c pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, ®_val); reg_val 85 arch/mips/pci/fixup-malta.c if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE) reg_val 88 arch/mips/pci/fixup-malta.c pci_irq[PCIA+i] = piixirqmap[reg_val & reg_val 98 arch/mips/pci/fixup-malta.c pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, ®_val); reg_val 99 arch/mips/pci/fixup-malta.c pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val | reg_val 109 arch/mips/pci/fixup-malta.c pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, ®_val); reg_val 110 arch/mips/pci/fixup-malta.c reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT; reg_val 111 arch/mips/pci/fixup-malta.c pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val); reg_val 124 arch/mips/pci/fixup-malta.c unsigned char reg_val; reg_val 132 arch/mips/pci/fixup-malta.c ®_val); reg_val 134 arch/mips/pci/fixup-malta.c reg_val|PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN); reg_val 136 arch/mips/pci/fixup-malta.c ®_val); reg_val 138 arch/mips/pci/fixup-malta.c reg_val|PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN); reg_val 83 arch/powerpc/platforms/powernv/opal-fadump.h __be64 reg_val; reg_val 88 arch/powerpc/platforms/powernv/opal-fadump.h u64 reg_val) reg_val 92 arch/powerpc/platforms/powernv/opal-fadump.h regs->gpr[reg_num] = reg_val; reg_val 98 arch/powerpc/platforms/powernv/opal-fadump.h regs->ctr = reg_val; reg_val 101 arch/powerpc/platforms/powernv/opal-fadump.h regs->link = reg_val; reg_val 104 arch/powerpc/platforms/powernv/opal-fadump.h regs->xer = reg_val; reg_val 107 arch/powerpc/platforms/powernv/opal-fadump.h regs->dar = reg_val; reg_val 110 arch/powerpc/platforms/powernv/opal-fadump.h regs->dsisr = reg_val; reg_val 113 arch/powerpc/platforms/powernv/opal-fadump.h regs->nip = reg_val; reg_val 116 arch/powerpc/platforms/powernv/opal-fadump.h regs->msr = reg_val; reg_val 119 arch/powerpc/platforms/powernv/opal-fadump.h regs->ccr = reg_val; reg_val 137 arch/powerpc/platforms/powernv/opal-fadump.h val = (cpu_endian ? be64_to_cpu(reg_entry->reg_val) : reg_val 138 arch/powerpc/platforms/powernv/opal-fadump.h reg_entry->reg_val); reg_val 250 arch/powerpc/platforms/pseries/rtas-fadump.c void rtas_fadump_set_regval(struct pt_regs *regs, u64 reg_id, u64 reg_val) reg_val 256 arch/powerpc/platforms/pseries/rtas-fadump.c regs->gpr[i] = (unsigned long)reg_val; reg_val 258 arch/powerpc/platforms/pseries/rtas-fadump.c regs->nip = (unsigned long)reg_val; reg_val 260 arch/powerpc/platforms/pseries/rtas-fadump.c regs->msr = (unsigned long)reg_val; reg_val 262 arch/powerpc/platforms/pseries/rtas-fadump.c regs->ctr = (unsigned long)reg_val; reg_val 264 arch/powerpc/platforms/pseries/rtas-fadump.c regs->link = (unsigned long)reg_val; reg_val 266 arch/powerpc/platforms/pseries/rtas-fadump.c regs->xer = (unsigned long)reg_val; reg_val 268 arch/powerpc/platforms/pseries/rtas-fadump.c regs->ccr = (unsigned long)reg_val; reg_val 270 arch/powerpc/platforms/pseries/rtas-fadump.c regs->dar = (unsigned long)reg_val; reg_val 272 arch/powerpc/platforms/pseries/rtas-fadump.c regs->dsisr = (unsigned long)reg_val; reg_val 3446 arch/sparc/include/asm/hypervisor.h unsigned long *reg_val); reg_val 3448 arch/sparc/include/asm/hypervisor.h unsigned long reg_val); reg_val 3456 arch/sparc/include/asm/hypervisor.h unsigned long *reg_val); reg_val 3458 arch/sparc/include/asm/hypervisor.h unsigned long reg_val); reg_val 3467 arch/sparc/include/asm/hypervisor.h unsigned long *reg_val); reg_val 3469 arch/sparc/include/asm/hypervisor.h unsigned long reg_val); reg_val 39 arch/x86/hyperv/hv_apic.c u64 reg_val; reg_val 41 arch/x86/hyperv/hv_apic.c rdmsrl(HV_X64_MSR_ICR, reg_val); reg_val 42 arch/x86/hyperv/hv_apic.c return reg_val; reg_val 47 arch/x86/hyperv/hv_apic.c u64 reg_val; reg_val 49 arch/x86/hyperv/hv_apic.c reg_val = SET_APIC_DEST_FIELD(id); reg_val 50 arch/x86/hyperv/hv_apic.c reg_val = reg_val << 32; reg_val 51 arch/x86/hyperv/hv_apic.c reg_val |= low; reg_val 53 arch/x86/hyperv/hv_apic.c wrmsrl(HV_X64_MSR_ICR, reg_val); reg_val 58 arch/x86/hyperv/hv_apic.c u32 reg_val, hi; reg_val 62 arch/x86/hyperv/hv_apic.c rdmsr(HV_X64_MSR_EOI, reg_val, hi); reg_val 63 arch/x86/hyperv/hv_apic.c return reg_val; reg_val 65 arch/x86/hyperv/hv_apic.c rdmsr(HV_X64_MSR_TPR, reg_val, hi); reg_val 66 arch/x86/hyperv/hv_apic.c return reg_val; reg_val 300 drivers/acpi/pmic/intel_pmic_bxtwc.c unsigned int val, adc_val, reg_val; reg_val 315 drivers/acpi/pmic/intel_pmic_bxtwc.c reg_val = temp_l | WHISKEY_COVE_ADC_HIGH_BIT(temp_h); reg_val 318 drivers/acpi/pmic/intel_pmic_bxtwc.c adc_val = reg_val * rlsb / 1000; reg_val 748 drivers/ata/ahci_imx.c u32 reg_val; reg_val 769 drivers/ata/ahci_imx.c reg_val = readl(mmio + IMX_P0PHYCR); reg_val 770 drivers/ata/ahci_imx.c writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR); reg_val 1060 drivers/ata/ahci_imx.c unsigned int reg_val; reg_val 1159 drivers/ata/ahci_imx.c reg_val = readl(hpriv->mmio + HOST_CAP); reg_val 1160 drivers/ata/ahci_imx.c if (!(reg_val & HOST_CAP_SSS)) { reg_val 1161 drivers/ata/ahci_imx.c reg_val |= HOST_CAP_SSS; reg_val 1162 drivers/ata/ahci_imx.c writel(reg_val, hpriv->mmio + HOST_CAP); reg_val 1164 drivers/ata/ahci_imx.c reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL); reg_val 1165 drivers/ata/ahci_imx.c if (!(reg_val & 0x1)) { reg_val 1166 drivers/ata/ahci_imx.c reg_val |= 0x1; reg_val 1167 drivers/ata/ahci_imx.c writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL); reg_val 1170 drivers/ata/ahci_imx.c reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000; reg_val 1171 drivers/ata/ahci_imx.c writel(reg_val, hpriv->mmio + IMX_TIMER1MS); reg_val 55 drivers/ata/ahci_sunxi.c u32 reg_val; reg_val 57 drivers/ata/ahci_sunxi.c reg_val = readl(reg); reg_val 58 drivers/ata/ahci_sunxi.c reg_val &= ~(clr_val); reg_val 59 drivers/ata/ahci_sunxi.c writel(reg_val, reg); reg_val 64 drivers/ata/ahci_sunxi.c u32 reg_val; reg_val 66 drivers/ata/ahci_sunxi.c reg_val = readl(reg); reg_val 67 drivers/ata/ahci_sunxi.c reg_val |= set_val; reg_val 68 drivers/ata/ahci_sunxi.c writel(reg_val, reg); reg_val 73 drivers/ata/ahci_sunxi.c u32 reg_val; reg_val 75 drivers/ata/ahci_sunxi.c reg_val = readl(reg); reg_val 76 drivers/ata/ahci_sunxi.c reg_val &= ~(clr_val); reg_val 77 drivers/ata/ahci_sunxi.c reg_val |= set_val; reg_val 78 drivers/ata/ahci_sunxi.c writel(reg_val, reg); reg_val 88 drivers/ata/ahci_sunxi.c u32 reg_val; reg_val 114 drivers/ata/ahci_sunxi.c reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28); reg_val 115 drivers/ata/ahci_sunxi.c if (reg_val == 0x02) reg_val 129 drivers/ata/ahci_sunxi.c reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24); reg_val 130 drivers/ata/ahci_sunxi.c if (reg_val == 0x00) reg_val 2742 drivers/base/regmap/regmap.c unsigned int reg_val; reg_val 2743 drivers/base/regmap/regmap.c ret = regmap_read(field->regmap, field->reg, ®_val); reg_val 2747 drivers/base/regmap/regmap.c reg_val &= field->mask; reg_val 2748 drivers/base/regmap/regmap.c reg_val >>= field->shift; reg_val 2749 drivers/base/regmap/regmap.c *val = reg_val; reg_val 2769 drivers/base/regmap/regmap.c unsigned int reg_val; reg_val 2776 drivers/base/regmap/regmap.c ®_val); reg_val 2780 drivers/base/regmap/regmap.c reg_val &= field->mask; reg_val 2781 drivers/base/regmap/regmap.c reg_val >>= field->shift; reg_val 2782 drivers/base/regmap/regmap.c *val = reg_val; reg_val 42 drivers/clk/bcm/clk-kona.c static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width) reg_val 44 drivers/clk/bcm/clk-kona.c return (reg_val & bitfield_mask(shift, width)) >> shift; reg_val 48 drivers/clk/bcm/clk-kona.c static inline u32 bitfield_replace(u32 reg_val, u32 shift, u32 width, u32 val) reg_val 52 drivers/clk/bcm/clk-kona.c return (reg_val & ~mask) | (val << shift); reg_val 137 drivers/clk/bcm/clk-kona.c __ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val) reg_val 139 drivers/clk/bcm/clk-kona.c writel(reg_val, ccu->base + reg_offset); reg_val 337 drivers/clk/bcm/clk-kona.c u32 reg_val; reg_val 339 drivers/clk/bcm/clk-kona.c reg_val = __ccu_read(ccu, offset); reg_val 340 drivers/clk/bcm/clk-kona.c reg_val |= mask; reg_val 341 drivers/clk/bcm/clk-kona.c __ccu_write(ccu, offset, reg_val); reg_val 361 drivers/clk/bcm/clk-kona.c u32 reg_val; reg_val 368 drivers/clk/bcm/clk-kona.c reg_val = __ccu_read(ccu, gate->offset); reg_val 370 drivers/clk/bcm/clk-kona.c return (reg_val & bit_mask) != 0; reg_val 398 drivers/clk/bcm/clk-kona.c u32 reg_val; reg_val 406 drivers/clk/bcm/clk-kona.c reg_val = __ccu_read(ccu, gate->offset); reg_val 412 drivers/clk/bcm/clk-kona.c reg_val |= mask; reg_val 414 drivers/clk/bcm/clk-kona.c reg_val &= ~mask; reg_val 427 drivers/clk/bcm/clk-kona.c reg_val |= mask; reg_val 429 drivers/clk/bcm/clk-kona.c reg_val &= ~mask; reg_val 431 drivers/clk/bcm/clk-kona.c __ccu_write(ccu, gate->offset, reg_val); reg_val 530 drivers/clk/bcm/clk-kona.c u32 reg_val; reg_val 540 drivers/clk/bcm/clk-kona.c reg_val = __ccu_read(ccu, offset); reg_val 541 drivers/clk/bcm/clk-kona.c reg_val |= mask; reg_val 542 drivers/clk/bcm/clk-kona.c __ccu_write(ccu, offset, reg_val); reg_val 567 drivers/clk/bcm/clk-kona.c u32 reg_val; reg_val 574 drivers/clk/bcm/clk-kona.c reg_val = __ccu_read(ccu, div->u.s.offset); reg_val 578 drivers/clk/bcm/clk-kona.c reg_div = bitfield_extract(reg_val, div->u.s.shift, div->u.s.width); reg_val 596 drivers/clk/bcm/clk-kona.c u32 reg_val; reg_val 607 drivers/clk/bcm/clk-kona.c reg_val = __ccu_read(ccu, div->u.s.offset); reg_val 608 drivers/clk/bcm/clk-kona.c reg_div = bitfield_extract(reg_val, div->u.s.shift, reg_val 626 drivers/clk/bcm/clk-kona.c reg_val = __ccu_read(ccu, div->u.s.offset); reg_val 627 drivers/clk/bcm/clk-kona.c reg_val = bitfield_replace(reg_val, div->u.s.shift, div->u.s.width, reg_val 629 drivers/clk/bcm/clk-kona.c __ccu_write(ccu, div->u.s.offset, reg_val); reg_val 843 drivers/clk/bcm/clk-kona.c u32 reg_val; reg_val 853 drivers/clk/bcm/clk-kona.c reg_val = __ccu_read(ccu, sel->offset); reg_val 856 drivers/clk/bcm/clk-kona.c parent_sel = bitfield_extract(reg_val, sel->shift, sel->width); reg_val 878 drivers/clk/bcm/clk-kona.c u32 reg_val; reg_val 892 drivers/clk/bcm/clk-kona.c reg_val = __ccu_read(ccu, sel->offset); reg_val 893 drivers/clk/bcm/clk-kona.c parent_sel = bitfield_extract(reg_val, sel->shift, sel->width); reg_val 911 drivers/clk/bcm/clk-kona.c reg_val = __ccu_read(ccu, sel->offset); reg_val 912 drivers/clk/bcm/clk-kona.c reg_val = bitfield_replace(reg_val, sel->shift, sel->width, parent_sel); reg_val 913 drivers/clk/bcm/clk-kona.c __ccu_write(ccu, sel->offset, reg_val); reg_val 190 drivers/clk/clk-axi-clkgen.c unsigned int reg_val; reg_val 197 drivers/clk/clk-axi-clkgen.c reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL | AXI_CLKGEN_V2_DRP_CNTRL_READ; reg_val 198 drivers/clk/clk-axi-clkgen.c reg_val |= (reg << 16); reg_val 200 drivers/clk/clk-axi-clkgen.c axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val); reg_val 214 drivers/clk/clk-axi-clkgen.c unsigned int reg_val = 0; reg_val 222 drivers/clk/clk-axi-clkgen.c axi_clkgen_mmcm_read(axi_clkgen, reg, ®_val); reg_val 223 drivers/clk/clk-axi-clkgen.c reg_val &= ~mask; reg_val 226 drivers/clk/clk-axi-clkgen.c reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask); reg_val 228 drivers/clk/clk-axi-clkgen.c axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val); reg_val 1016 drivers/crypto/hisilicon/qm.c u32 reg_val, type, vf_num; reg_val 1024 drivers/crypto/hisilicon/qm.c reg_val = readl(qm->io_base + reg_val 1026 drivers/crypto/hisilicon/qm.c type = (reg_val & QM_DB_TIMEOUT_TYPE) >> reg_val 1028 drivers/crypto/hisilicon/qm.c vf_num = reg_val & QM_DB_TIMEOUT_VF; reg_val 1034 drivers/crypto/hisilicon/qm.c reg_val = readl(qm->io_base + reg_val 1036 drivers/crypto/hisilicon/qm.c type = (reg_val & QM_FIFO_OVERFLOW_TYPE) >> reg_val 1038 drivers/crypto/hisilicon/qm.c vf_num = reg_val & QM_FIFO_OVERFLOW_VF; reg_val 241 drivers/crypto/qat/qat_common/adf_admin.c u64 reg_val; reg_val 268 drivers/crypto/qat/qat_common/adf_admin.c reg_val = (u64)admin->phy_addr; reg_val 269 drivers/crypto/qat/qat_common/adf_admin.c ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGUR_OFFSET, reg_val >> 32); reg_val 270 drivers/crypto/qat/qat_common/adf_admin.c ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGLR_OFFSET, reg_val); reg_val 26 drivers/gpio/gpio-adp5520.c uint8_t reg_val; reg_val 36 drivers/gpio/gpio-adp5520.c adp5520_read(dev->master, ADP5520_GPIO_OUT, ®_val); reg_val 38 drivers/gpio/gpio-adp5520.c adp5520_read(dev->master, ADP5520_GPIO_IN, ®_val); reg_val 40 drivers/gpio/gpio-adp5520.c return !!(reg_val & dev->lut[off]); reg_val 213 drivers/gpio/gpio-aspeed.c case reg_val: reg_val 386 drivers/gpio/gpio-aspeed.c return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset)); reg_val 397 drivers/gpio/gpio-aspeed.c addr = bank_reg(gpio, bank, reg_val); reg_val 73 drivers/gpio/gpio-madera.c unsigned int reg_val = value ? MADERA_GP1_LVL : 0; reg_val 84 drivers/gpio/gpio-madera.c MADERA_GP1_LVL_MASK, reg_val); reg_val 93 drivers/gpio/gpio-madera.c unsigned int reg_val = value ? MADERA_GP1_LVL : 0; reg_val 98 drivers/gpio/gpio-madera.c MADERA_GP1_LVL_MASK, reg_val); reg_val 197 drivers/gpio/gpio-max732x.c uint8_t reg_val; reg_val 200 drivers/gpio/gpio-max732x.c ret = max732x_readb(chip, is_group_a(chip, off), ®_val); reg_val 204 drivers/gpio/gpio-max732x.c return !!(reg_val & (1u << (off & 0x7))); reg_val 94 drivers/gpio/gpio-ml-ioh.c u32 reg_val; reg_val 99 drivers/gpio/gpio-ml-ioh.c reg_val = ioread32(&chip->reg->regs[chip->ch].po); reg_val 101 drivers/gpio/gpio-ml-ioh.c reg_val |= (1 << nr); reg_val 103 drivers/gpio/gpio-ml-ioh.c reg_val &= ~(1 << nr); reg_val 105 drivers/gpio/gpio-ml-ioh.c iowrite32(reg_val, &chip->reg->regs[chip->ch].po); reg_val 121 drivers/gpio/gpio-ml-ioh.c u32 reg_val; reg_val 130 drivers/gpio/gpio-ml-ioh.c reg_val = ioread32(&chip->reg->regs[chip->ch].po); reg_val 132 drivers/gpio/gpio-ml-ioh.c reg_val |= (1 << nr); reg_val 134 drivers/gpio/gpio-ml-ioh.c reg_val &= ~(1 << nr); reg_val 135 drivers/gpio/gpio-ml-ioh.c iowrite32(reg_val, &chip->reg->regs[chip->ch].po); reg_val 353 drivers/gpio/gpio-ml-ioh.c u32 reg_val; reg_val 358 drivers/gpio/gpio-ml-ioh.c reg_val = ioread32(&chip->reg->regs[i].istatus); reg_val 360 drivers/gpio/gpio-ml-ioh.c if (reg_val & BIT(j)) { reg_val 363 drivers/gpio/gpio-ml-ioh.c __func__, j, irq, reg_val); reg_val 408 drivers/gpio/gpio-pca953x.c u32 reg_val; reg_val 412 drivers/gpio/gpio-pca953x.c ret = regmap_read(chip->regmap, inreg, ®_val); reg_val 422 drivers/gpio/gpio-pca953x.c return !!(reg_val & bit); reg_val 443 drivers/gpio/gpio-pca953x.c u32 reg_val; reg_val 447 drivers/gpio/gpio-pca953x.c ret = regmap_read(chip->regmap, dirreg, ®_val); reg_val 452 drivers/gpio/gpio-pca953x.c return !!(reg_val & bit); reg_val 461 drivers/gpio/gpio-pca953x.c u8 reg_val[MAX_BANK]; reg_val 465 drivers/gpio/gpio-pca953x.c ret = pca953x_read_regs(chip, chip->regs->output, reg_val); reg_val 476 drivers/gpio/gpio-pca953x.c reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val; reg_val 480 drivers/gpio/gpio-pca953x.c pca953x_write_regs(chip, chip->regs->output, reg_val); reg_val 99 drivers/gpio/gpio-pch.c u32 reg_val; reg_val 104 drivers/gpio/gpio-pch.c reg_val = ioread32(&chip->reg->po); reg_val 106 drivers/gpio/gpio-pch.c reg_val |= (1 << nr); reg_val 108 drivers/gpio/gpio-pch.c reg_val &= ~(1 << nr); reg_val 110 drivers/gpio/gpio-pch.c iowrite32(reg_val, &chip->reg->po); reg_val 126 drivers/gpio/gpio-pch.c u32 reg_val; reg_val 131 drivers/gpio/gpio-pch.c reg_val = ioread32(&chip->reg->po); reg_val 133 drivers/gpio/gpio-pch.c reg_val |= (1 << nr); reg_val 135 drivers/gpio/gpio-pch.c reg_val &= ~(1 << nr); reg_val 136 drivers/gpio/gpio-pch.c iowrite32(reg_val, &chip->reg->po); reg_val 302 drivers/gpio/gpio-pch.c unsigned long reg_val = ioread32(&chip->reg->istatus); reg_val 305 drivers/gpio/gpio-pch.c for_each_set_bit(i, ®_val, gpio_pins[chip->ioh]) { reg_val 306 drivers/gpio/gpio-pch.c dev_dbg(chip->dev, "[%d]:irq=%d status=0x%lx\n", i, irq, reg_val); reg_val 52 drivers/gpio/gpio-sch.c u8 reg_val; reg_val 57 drivers/gpio/gpio-sch.c reg_val = !!(inb(sch->iobase + offset) & BIT(bit)); reg_val 59 drivers/gpio/gpio-sch.c return reg_val; reg_val 66 drivers/gpio/gpio-sch.c u8 reg_val; reg_val 71 drivers/gpio/gpio-sch.c reg_val = inb(sch->iobase + offset); reg_val 74 drivers/gpio/gpio-sch.c outb(reg_val | BIT(bit), sch->iobase + offset); reg_val 76 drivers/gpio/gpio-sch.c outb((reg_val & ~BIT(bit)), sch->iobase + offset); reg_val 94 drivers/gpio/sgpio-aspeed.c case reg_val: reg_val 138 drivers/gpio/sgpio-aspeed.c reg = is_input ? reg_val : reg_rdata; reg_val 153 drivers/gpio/sgpio-aspeed.c addr = bank_reg(gpio, bank, reg_val); reg_val 110 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint32_t reg_val, uint32_t mask, bool check_changed) reg_val 119 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c if (val != reg_val) reg_val 122 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c if ((val & mask) == reg_val) reg_val 86 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val; reg_val 97 drivers/gpu/drm/amd/display/dc/dc_helper.c reg_val = dm_read_reg(ctx, addr); reg_val 98 drivers/gpu/drm/amd/display/dc/dc_helper.c reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; reg_val 99 drivers/gpu/drm/amd/display/dc/dc_helper.c dm_write_reg(ctx, addr, reg_val); reg_val 100 drivers/gpu/drm/amd/display/dc/dc_helper.c return reg_val; reg_val 104 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t addr, uint32_t reg_val, int n, reg_val 120 drivers/gpu/drm/amd/display/dc/dc_helper.c reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; reg_val 121 drivers/gpu/drm/amd/display/dc/dc_helper.c dm_write_reg(ctx, addr, reg_val); reg_val 122 drivers/gpu/drm/amd/display/dc/dc_helper.c return reg_val; reg_val 146 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val = dm_read_reg(ctx, addr); reg_val 147 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value = get_reg_field_value_ex(reg_val, mask, shift); reg_val 148 drivers/gpu/drm/amd/display/dc/dc_helper.c return reg_val; reg_val 155 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val = dm_read_reg(ctx, addr); reg_val 156 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); reg_val 157 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); reg_val 158 drivers/gpu/drm/amd/display/dc/dc_helper.c return reg_val; reg_val 166 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val = dm_read_reg(ctx, addr); reg_val 167 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); reg_val 168 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); reg_val 169 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); reg_val 170 drivers/gpu/drm/amd/display/dc/dc_helper.c return reg_val; reg_val 179 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val = dm_read_reg(ctx, addr); reg_val 180 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); reg_val 181 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); reg_val 182 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); reg_val 183 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); reg_val 184 drivers/gpu/drm/amd/display/dc/dc_helper.c return reg_val; reg_val 194 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val = dm_read_reg(ctx, addr); reg_val 195 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); reg_val 196 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); reg_val 197 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); reg_val 198 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); reg_val 199 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); reg_val 200 drivers/gpu/drm/amd/display/dc/dc_helper.c return reg_val; reg_val 211 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val = dm_read_reg(ctx, addr); reg_val 212 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); reg_val 213 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); reg_val 214 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); reg_val 215 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); reg_val 216 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); reg_val 217 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6); reg_val 218 drivers/gpu/drm/amd/display/dc/dc_helper.c return reg_val; reg_val 230 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val = dm_read_reg(ctx, addr); reg_val 231 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); reg_val 232 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); reg_val 233 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); reg_val 234 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); reg_val 235 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); reg_val 236 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6); reg_val 237 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7); reg_val 238 drivers/gpu/drm/amd/display/dc/dc_helper.c return reg_val; reg_val 251 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val = dm_read_reg(ctx, addr); reg_val 252 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); reg_val 253 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); reg_val 254 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3); reg_val 255 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4); reg_val 256 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); reg_val 257 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6); reg_val 258 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7); reg_val 259 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value8 = get_reg_field_value_ex(reg_val, mask8, shift8); reg_val 260 drivers/gpu/drm/amd/display/dc/dc_helper.c return reg_val; reg_val 299 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t reg_val; reg_val 313 drivers/gpu/drm/amd/display/dc/dc_helper.c reg_val = dm_read_reg(ctx, addr); reg_val 315 drivers/gpu/drm/amd/display/dc/dc_helper.c field_value = get_reg_field_value_ex(reg_val, mask, shift); reg_val 358 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t index, uint32_t reg_val, int n, reg_val 369 drivers/gpu/drm/amd/display/dc/dc_helper.c reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1); reg_val 376 drivers/gpu/drm/amd/display/dc/dc_helper.c reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift); reg_val 380 drivers/gpu/drm/amd/display/dc/dc_helper.c generic_write_indirect_reg(ctx, addr_index, addr_data, index, reg_val); reg_val 383 drivers/gpu/drm/amd/display/dc/dc_helper.c return reg_val; reg_val 802 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c const uint16_t *reg_val) reg_val 804 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c if (reg_val) { reg_val 806 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c GAMUT_REMAP_C11, reg_val[0], reg_val 807 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c GAMUT_REMAP_C12, reg_val[1]); reg_val 809 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c GAMUT_REMAP_C13, reg_val[2], reg_val 810 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c GAMUT_REMAP_C14, reg_val[3]); reg_val 812 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c GAMUT_REMAP_C21, reg_val[4], reg_val 813 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c GAMUT_REMAP_C22, reg_val[5]); reg_val 815 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c GAMUT_REMAP_C23, reg_val[6], reg_val 816 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c GAMUT_REMAP_C24, reg_val[7]); reg_val 818 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c GAMUT_REMAP_C31, reg_val[8], reg_val 819 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c GAMUT_REMAP_C32, reg_val[9]); reg_val 821 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c GAMUT_REMAP_C33, reg_val[10], reg_val 822 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c GAMUT_REMAP_C34, reg_val[11]); reg_val 620 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0); reg_val 622 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c straps->audio_stream_number = get_reg_field_value(reg_val, reg_val 625 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c straps->hdmi_disable = get_reg_field_value(reg_val, reg_val 629 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0); reg_val 630 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c straps->dc_pinstraps_audio = get_reg_field_value(reg_val, reg_val 51 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c uint32_t reg_val = REG_READ(DCHUBP_CNTL); reg_val 53 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c if (reg_val) { reg_val 919 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c uint32_t reg_val = REG_READ(DCHUBP_CNTL); reg_val 921 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c if (reg_val) { reg_val 135 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t addr, uint32_t reg_val, int n, reg_val 484 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint32_t index, uint32_t reg_val, int n, reg_val 504 drivers/gpu/drm/gma500/psb_irq.c uint32_t reg_val = 0; reg_val 513 drivers/gpu/drm/gma500/psb_irq.c reg_val = REG_READ(pipeconf_reg); reg_val 517 drivers/gpu/drm/gma500/psb_irq.c if (!(reg_val & PIPEACONF_ENABLE)) reg_val 568 drivers/gpu/drm/gma500/psb_irq.c uint32_t reg_val = 0; reg_val 572 drivers/gpu/drm/gma500/psb_irq.c reg_val = REG_READ(pipeconf_reg); reg_val 576 drivers/gpu/drm/gma500/psb_irq.c if (!(reg_val & PIPEACONF_ENABLE)) reg_val 617 drivers/gpu/drm/gma500/psb_irq.c uint32_t reg_val = 0; reg_val 641 drivers/gpu/drm/gma500/psb_irq.c reg_val = REG_READ(pipeconf_reg); reg_val 643 drivers/gpu/drm/gma500/psb_irq.c if (!(reg_val & PIPEACONF_ENABLE)) { reg_val 7593 drivers/gpu/drm/i915/display/intel_display.c u32 reg_val; reg_val 7599 drivers/gpu/drm/i915/display/intel_display.c reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); reg_val 7600 drivers/gpu/drm/i915/display/intel_display.c reg_val &= 0xffffff00; reg_val 7601 drivers/gpu/drm/i915/display/intel_display.c reg_val |= 0x00000030; reg_val 7602 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); reg_val 7604 drivers/gpu/drm/i915/display/intel_display.c reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); reg_val 7605 drivers/gpu/drm/i915/display/intel_display.c reg_val &= 0x00ffffff; reg_val 7606 drivers/gpu/drm/i915/display/intel_display.c reg_val |= 0x8c000000; reg_val 7607 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); reg_val 7609 drivers/gpu/drm/i915/display/intel_display.c reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); reg_val 7610 drivers/gpu/drm/i915/display/intel_display.c reg_val &= 0xffffff00; reg_val 7611 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); reg_val 7613 drivers/gpu/drm/i915/display/intel_display.c reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); reg_val 7614 drivers/gpu/drm/i915/display/intel_display.c reg_val &= 0x00ffffff; reg_val 7615 drivers/gpu/drm/i915/display/intel_display.c reg_val |= 0xb0000000; reg_val 7616 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); reg_val 7745 drivers/gpu/drm/i915/display/intel_display.c u32 coreclk, reg_val; reg_val 7774 drivers/gpu/drm/i915/display/intel_display.c reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); reg_val 7775 drivers/gpu/drm/i915/display/intel_display.c reg_val &= 0x00ffffff; reg_val 7776 drivers/gpu/drm/i915/display/intel_display.c vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); reg_val 30 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c u8 reg_val = 0; reg_val 37 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c ®_val) < 0) { reg_val 43 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c reg_val |= DP_EDP_BACKLIGHT_ENABLE; reg_val 45 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE); reg_val 48 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c reg_val) != 1) { reg_val 165 drivers/gpu/drm/i915/gem/i915_gem_stolen.c u32 reg_val = I915_READ(IS_GM45(dev_priv) ? reg_val 171 drivers/gpu/drm/i915/gem/i915_gem_stolen.c IS_GM45(dev_priv) ? "CTG" : "ELK", reg_val); reg_val 173 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if ((reg_val & G4X_STOLEN_RESERVED_ENABLE) == 0) reg_val 181 drivers/gpu/drm/i915/gem/i915_gem_stolen.c reg_val); reg_val 183 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (!(reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK)) reg_val 186 drivers/gpu/drm/i915/gem/i915_gem_stolen.c *base = (reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK) << 16; reg_val 187 drivers/gpu/drm/i915/gem/i915_gem_stolen.c WARN_ON((reg_val & G4X_STOLEN_RESERVED_ADDR1_MASK) < *base); reg_val 196 drivers/gpu/drm/i915/gem/i915_gem_stolen.c u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED); reg_val 198 drivers/gpu/drm/i915/gem/i915_gem_stolen.c DRM_DEBUG_DRIVER("GEN6_STOLEN_RESERVED = %08x\n", reg_val); reg_val 200 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE)) reg_val 203 drivers/gpu/drm/i915/gem/i915_gem_stolen.c *base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK; reg_val 205 drivers/gpu/drm/i915/gem/i915_gem_stolen.c switch (reg_val & GEN6_STOLEN_RESERVED_SIZE_MASK) { reg_val 220 drivers/gpu/drm/i915/gem/i915_gem_stolen.c MISSING_CASE(reg_val & GEN6_STOLEN_RESERVED_SIZE_MASK); reg_val 228 drivers/gpu/drm/i915/gem/i915_gem_stolen.c u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED); reg_val 231 drivers/gpu/drm/i915/gem/i915_gem_stolen.c DRM_DEBUG_DRIVER("GEN6_STOLEN_RESERVED = %08x\n", reg_val); reg_val 233 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE)) reg_val 236 drivers/gpu/drm/i915/gem/i915_gem_stolen.c switch (reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK) { reg_val 238 drivers/gpu/drm/i915/gem/i915_gem_stolen.c MISSING_CASE(reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK); reg_val 256 drivers/gpu/drm/i915/gem/i915_gem_stolen.c u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED); reg_val 258 drivers/gpu/drm/i915/gem/i915_gem_stolen.c DRM_DEBUG_DRIVER("GEN6_STOLEN_RESERVED = %08x\n", reg_val); reg_val 260 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE)) reg_val 263 drivers/gpu/drm/i915/gem/i915_gem_stolen.c *base = reg_val & GEN7_STOLEN_RESERVED_ADDR_MASK; reg_val 265 drivers/gpu/drm/i915/gem/i915_gem_stolen.c switch (reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK) { reg_val 274 drivers/gpu/drm/i915/gem/i915_gem_stolen.c MISSING_CASE(reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK); reg_val 282 drivers/gpu/drm/i915/gem/i915_gem_stolen.c u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED); reg_val 284 drivers/gpu/drm/i915/gem/i915_gem_stolen.c DRM_DEBUG_DRIVER("GEN6_STOLEN_RESERVED = %08x\n", reg_val); reg_val 286 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE)) reg_val 289 drivers/gpu/drm/i915/gem/i915_gem_stolen.c *base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK; reg_val 291 drivers/gpu/drm/i915/gem/i915_gem_stolen.c switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) { reg_val 306 drivers/gpu/drm/i915/gem/i915_gem_stolen.c MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK); reg_val 314 drivers/gpu/drm/i915/gem/i915_gem_stolen.c u32 reg_val = I915_READ(GEN6_STOLEN_RESERVED); reg_val 317 drivers/gpu/drm/i915/gem/i915_gem_stolen.c DRM_DEBUG_DRIVER("GEN6_STOLEN_RESERVED = %08x\n", reg_val); reg_val 319 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE)) reg_val 322 drivers/gpu/drm/i915/gem/i915_gem_stolen.c if (!(reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK)) reg_val 325 drivers/gpu/drm/i915/gem/i915_gem_stolen.c *base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK; reg_val 333 drivers/gpu/drm/i915/gem/i915_gem_stolen.c u64 reg_val = intel_uncore_read64(&i915->uncore, GEN6_STOLEN_RESERVED); reg_val 335 drivers/gpu/drm/i915/gem/i915_gem_stolen.c DRM_DEBUG_DRIVER("GEN6_STOLEN_RESERVED = 0x%016llx\n", reg_val); reg_val 337 drivers/gpu/drm/i915/gem/i915_gem_stolen.c *base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK; reg_val 339 drivers/gpu/drm/i915/gem/i915_gem_stolen.c switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) { reg_val 354 drivers/gpu/drm/i915/gem/i915_gem_stolen.c MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK); reg_val 708 drivers/gpu/drm/i915/gvt/handlers.c u32 reg_val; reg_val 711 drivers/gpu/drm/i915/gvt/handlers.c reg_val = *((u32 *)p_data); reg_val 714 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | reg_val 716 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); reg_val 404 drivers/gpu/drm/i915/intel_uncore.h u32 reg_val; reg_val 407 drivers/gpu/drm/i915/intel_uncore.h reg_val = intel_uncore_read(uncore, reg); reg_val 409 drivers/gpu/drm/i915/intel_uncore.h return (reg_val & mask) != expected_val ? -EINVAL : 0; reg_val 940 drivers/gpu/drm/mediatek/mtk_dsi.c u32 reg_val, cmdq_mask, i; reg_val 951 drivers/gpu/drm/mediatek/mtk_dsi.c reg_val = (msg->tx_len << 16) | (type << 8) | config; reg_val 956 drivers/gpu/drm/mediatek/mtk_dsi.c reg_val = (type << 8) | config; reg_val 962 drivers/gpu/drm/mediatek/mtk_dsi.c mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val); reg_val 97 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c u32 reg_val, new_val; reg_val 111 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c reg_val = DPU_REG_READ(c, reg_off); reg_val 114 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c new_val = reg_val | BIT(bit_off); reg_val 116 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c new_val = reg_val & ~BIT(bit_off); reg_val 120 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c clk_forced_on = !(reg_val & BIT(bit_off)); reg_val 61 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c u32 reg_val; reg_val 79 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val = DPU_REG_READ(c, reg_off); reg_val 80 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val &= ~(0x7 << bit_off); reg_val 81 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val |= (value & 0x7) << bit_off; reg_val 82 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c DPU_REG_WRITE(c, reg_off, reg_val); reg_val 89 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c u32 reg_val; reg_val 100 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val = DPU_REG_READ(c, reg_off); reg_val 101 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val &= ~(0xFF << bit_off); reg_val 102 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val |= (limit) << bit_off; reg_val 103 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c DPU_REG_WRITE(c, reg_off, reg_val); reg_val 110 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c u32 reg_val; reg_val 122 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val = DPU_REG_READ(c, reg_off); reg_val 123 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c limit = (reg_val >> bit_off) & 0xFF; reg_val 132 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c u32 reg_val; reg_val 134 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL0); reg_val 137 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val |= BIT(xin_id); reg_val 139 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val &= ~BIT(xin_id); reg_val 141 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c DPU_REG_WRITE(c, VBIF_XIN_HALT_CTRL0, reg_val); reg_val 148 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c u32 reg_val; reg_val 150 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL1); reg_val 152 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c return (reg_val & BIT(xin_id)) ? true : false; reg_val 159 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c u32 reg_val, reg_val_lvl, mask, reg_high, reg_shift; reg_val 169 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val = DPU_REG_READ(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high); reg_val 174 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val &= ~mask; reg_val 175 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val |= (remap_level << reg_shift) & mask; reg_val 180 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c DPU_REG_WRITE(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high, reg_val); reg_val 187 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c u32 reg_val; reg_val 194 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val = DPU_REG_READ(c, VBIF_WRITE_GATHER_EN); reg_val 195 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val |= BIT(xin_id); reg_val 196 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c DPU_REG_WRITE(c, VBIF_WRITE_GATHER_EN, reg_val); reg_val 45 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c u32 reg_val; reg_val 199 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c u32 reg_val, hdcp_int_status; reg_val 203 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_INT_CTRL); reg_val 204 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdcp_int_status = reg_val & HDCP_INT_STATUS_MASK; reg_val 210 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val |= hdcp_int_status << 1; reg_val 213 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val |= HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK; reg_val 214 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, reg_val); reg_val 228 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); reg_val 230 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c __func__, reg_val); reg_val 284 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c u32 reg_val, failure, nack0; reg_val 288 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS); reg_val 289 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c failure = reg_val & HDMI_HDCP_DDC_STATUS_FAILED; reg_val 290 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c nack0 = reg_val & HDMI_HDCP_DDC_STATUS_NACK0; reg_val 292 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val, failure, nack0); reg_val 309 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_CTRL_1); reg_val 310 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val |= HDMI_HDCP_DDC_CTRL_1_FAILED_ACK; reg_val 311 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdmi_write(hdmi, REG_HDMI_HDCP_DDC_CTRL_1, reg_val); reg_val 314 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS); reg_val 315 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c if (reg_val & HDMI_HDCP_DDC_STATUS_FAILED) reg_val 327 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); reg_val 328 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val |= HDMI_DDC_CTRL_SW_STATUS_RESET; reg_val 329 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val); reg_val 333 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); reg_val 334 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val &= ~HDMI_DDC_CTRL_SW_STATUS_RESET; reg_val 335 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val); reg_val 338 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); reg_val 339 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val |= HDMI_DDC_CTRL_SOFT_RESET; reg_val 340 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val); reg_val 346 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); reg_val 347 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val &= ~HDMI_DDC_CTRL_SOFT_RESET; reg_val 348 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val); reg_val 402 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c u32 reg_val; reg_val 412 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); reg_val 413 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val &= ~HDMI_HPD_CTRL_ENABLE; reg_val 414 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val); reg_val 434 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); reg_val 435 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val |= HDMI_HPD_CTRL_ENABLE; reg_val 436 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val); reg_val 459 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c u32 reg_val; reg_val 475 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); reg_val 476 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val &= ~HDMI_CTRL_ENCRYPTED; reg_val 477 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); reg_val 480 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_DDC_ARBITRATION); reg_val 481 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val &= ~HDMI_DDC_ARBITRATION_HW_ARBITRATION; reg_val 482 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdmi_write(hdmi, REG_HDMI_DDC_ARBITRATION, reg_val); reg_val 501 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DEBUG_CTRL); reg_val 502 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val &= ~HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER; reg_val 503 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdmi_write(hdmi, REG_HDMI_HDCP_DEBUG_CTRL, reg_val); reg_val 540 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c u32 reg_val; reg_val 546 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); reg_val 547 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val &= ~HDMI_CTRL_ENCRYPTED; reg_val 548 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); reg_val 558 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c u32 reg_val; reg_val 566 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_DDC_ARBITRATION); reg_val 567 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val |= HDMI_DDC_ARBITRATION_HW_ARBITRATION; reg_val 568 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdmi_write(hdmi, REG_HDMI_DDC_ARBITRATION, reg_val); reg_val 573 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); reg_val 574 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val |= HDMI_CTRL_ENCRYPTED; reg_val 575 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); reg_val 1120 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c u32 reg_val, data, reg; reg_val 1127 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_SHA_STATUS); reg_val 1128 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c DBG("HDCP_SHA_STATUS=%08x", reg_val); reg_val 1131 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c if (reg_val & HDMI_HDCP_SHA_STATUS_COMP_DONE) { reg_val 1139 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c if (!(reg_val & HDMI_HDCP_SHA_STATUS_BLOCK_DONE)) reg_val 1157 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = ksv_fifo[i] << 16; reg_val 1159 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val |= HDMI_HDCP_SHA_DATA_DONE; reg_val 1162 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c data = reg_val; reg_val 1307 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c u32 reg_val; reg_val 1318 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); reg_val 1319 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val &= ~HDMI_CTRL_ENCRYPTED; reg_val 1320 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); reg_val 1333 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c u32 reg_val; reg_val 1348 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); reg_val 1349 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val &= ~HDMI_HPD_CTRL_ENABLE; reg_val 1350 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val); reg_val 1378 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); reg_val 1379 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val &= ~HDMI_CTRL_ENCRYPTED; reg_val 1380 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); reg_val 1383 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); reg_val 1384 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg_val |= HDMI_HPD_CTRL_ENABLE; reg_val 1385 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val); reg_val 197 drivers/hwmon/adm1021.c int reg_val, err; reg_val 205 drivers/hwmon/adm1021.c reg_val = clamp_val(temp, -128, 127); reg_val 206 drivers/hwmon/adm1021.c data->temp_max[index] = reg_val * 1000; reg_val 209 drivers/hwmon/adm1021.c reg_val); reg_val 223 drivers/hwmon/adm1021.c int reg_val, err; reg_val 231 drivers/hwmon/adm1021.c reg_val = clamp_val(temp, -128, 127); reg_val 232 drivers/hwmon/adm1021.c data->temp_min[index] = reg_val * 1000; reg_val 235 drivers/hwmon/adm1021.c reg_val); reg_val 620 drivers/i2c/busses/i2c-eg20t.c u32 reg_val; reg_val 636 drivers/i2c/busses/i2c-eg20t.c reg_val = ioread32(p + PCH_I2CSR); reg_val 637 drivers/i2c/busses/i2c-eg20t.c if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) { reg_val 396 drivers/iio/accel/adxl372.c unsigned int reg_val, scale_factor; reg_val 408 drivers/iio/accel/adxl372.c reg_val = DIV_ROUND_CLOSEST(act_time_ms * 1000, scale_factor); reg_val 411 drivers/iio/accel/adxl372.c if (reg_val > 0xFF) reg_val 412 drivers/iio/accel/adxl372.c reg_val = 0xFF; reg_val 414 drivers/iio/accel/adxl372.c ret = regmap_write(st->regmap, ADXL372_TIME_ACT, reg_val); reg_val 167 drivers/iio/accel/bma180.c u8 reg_val = (ret & ~mask) | (val << (ffs(mask) - 1)); reg_val 172 drivers/iio/accel/bma180.c return i2c_smbus_write_byte_data(data->client, reg, reg_val); reg_val 279 drivers/iio/accel/bma180.c u8 reg_val = mode ? data->part_info->lowpower_val : 0; reg_val 281 drivers/iio/accel/bma180.c data->part_info->power_mask, reg_val); reg_val 267 drivers/iio/accel/mma9553.c u16 reg_val, config; reg_val 269 drivers/iio/accel/mma9553.c reg_val = *p_reg_val; reg_val 270 drivers/iio/accel/mma9553.c if (val == mma9553_get_bits(reg_val, mask)) reg_val 273 drivers/iio/accel/mma9553.c reg_val = mma9553_set_bits(reg_val, val, mask); reg_val 275 drivers/iio/accel/mma9553.c reg, reg_val); reg_val 282 drivers/iio/accel/mma9553.c *p_reg_val = reg_val; reg_val 65 drivers/iio/accel/stk8ba50.c u8 reg_val; reg_val 73 drivers/iio/accel/stk8ba50.c u8 reg_val; reg_val 273 drivers/iio/accel/stk8ba50.c stk8ba50_scale_table[index].reg_val); reg_val 292 drivers/iio/accel/stk8ba50.c stk8ba50_samp_freq_table[index].reg_val); reg_val 138 drivers/iio/health/afe4403.c unsigned int reg_val; reg_val 142 drivers/iio/health/afe4403.c ret = regmap_field_read(afe->fields[afe440x_attr->field], ®_val); reg_val 146 drivers/iio/health/afe4403.c if (reg_val >= afe440x_attr->table_size) reg_val 149 drivers/iio/health/afe4403.c vals[0] = afe440x_attr->val_table[reg_val].integer; reg_val 150 drivers/iio/health/afe4403.c vals[1] = afe440x_attr->val_table[reg_val].fract; reg_val 172 drivers/iio/health/afe4404.c unsigned int reg_val; reg_val 176 drivers/iio/health/afe4404.c ret = regmap_field_read(afe->fields[afe440x_attr->field], ®_val); reg_val 180 drivers/iio/health/afe4404.c if (reg_val >= afe440x_attr->table_size) reg_val 183 drivers/iio/health/afe4404.c vals[0] = afe440x_attr->val_table[reg_val].integer; reg_val 184 drivers/iio/health/afe4404.c vals[1] = afe440x_attr->val_table[reg_val].fract; reg_val 712 drivers/iio/light/tsl2772.c u8 *dev_reg, reg_val; reg_val 794 drivers/iio/light/tsl2772.c reg_val = TSL2772_CNTL_PWR_ON | TSL2772_CNTL_ADC_ENBL | reg_val 797 drivers/iio/light/tsl2772.c reg_val |= TSL2772_CNTL_ALS_INT_ENBL; reg_val 799 drivers/iio/light/tsl2772.c reg_val |= TSL2772_CNTL_PROX_INT_ENBL; reg_val 801 drivers/iio/light/tsl2772.c ret = tsl2772_write_control_reg(chip, reg_val); reg_val 149 drivers/iio/magnetometer/bmc150_magn.c u8 reg_val; reg_val 284 drivers/iio/magnetometer/bmc150_magn.c int ret, reg_val; reg_val 287 drivers/iio/magnetometer/bmc150_magn.c ret = regmap_read(data->regmap, BMC150_MAGN_REG_OPMODE_ODR, ®_val); reg_val 290 drivers/iio/magnetometer/bmc150_magn.c odr_val = (reg_val & BMC150_MAGN_MASK_ODR) >> BMC150_MAGN_SHIFT_ODR; reg_val 293 drivers/iio/magnetometer/bmc150_magn.c if (bmc150_magn_samp_freq_table[i].reg_val == odr_val) { reg_val 312 drivers/iio/magnetometer/bmc150_magn.c reg_val << reg_val 326 drivers/iio/magnetometer/bmc150_magn.c int ret, reg_val, max_odr; reg_val 330 drivers/iio/magnetometer/bmc150_magn.c ®_val); reg_val 333 drivers/iio/magnetometer/bmc150_magn.c rep_xy = BMC150_MAGN_REGVAL_TO_REPXY(reg_val); reg_val 337 drivers/iio/magnetometer/bmc150_magn.c ®_val); reg_val 340 drivers/iio/magnetometer/bmc150_magn.c rep_z = BMC150_MAGN_REGVAL_TO_REPZ(reg_val); reg_val 134 drivers/iio/temperature/max31856.c u8 reg_val[3]; reg_val 142 drivers/iio/temperature/max31856.c ret = max31856_read(data, MAX31856_LTCBH_REG, reg_val, 3); reg_val 146 drivers/iio/temperature/max31856.c *val = (reg_val[0] << 16 | reg_val[1] << 8 | reg_val[2]) >> 5; reg_val 148 drivers/iio/temperature/max31856.c if (reg_val[0] & 0x80) reg_val 157 drivers/iio/temperature/max31856.c ret = max31856_read(data, MAX31856_CJTO_REG, reg_val, 3); reg_val 161 drivers/iio/temperature/max31856.c offset_cjto = reg_val[0]; reg_val 163 drivers/iio/temperature/max31856.c *val = (reg_val[1] << 8 | reg_val[2]) >> 2; reg_val 167 drivers/iio/temperature/max31856.c if (reg_val[1] & 0x80) reg_val 175 drivers/iio/temperature/max31856.c ret = max31856_read(data, MAX31856_SR_REG, reg_val, 1); reg_val 179 drivers/iio/temperature/max31856.c if (reg_val[0] & (MAX31856_FAULT_OVUV | MAX31856_FAULT_OPEN)) reg_val 225 drivers/iio/temperature/max31856.c u8 reg_val; reg_val 229 drivers/iio/temperature/max31856.c ret = max31856_read(data, MAX31856_SR_REG, ®_val, 1); reg_val 233 drivers/iio/temperature/max31856.c fault = reg_val & faultbit; reg_val 770 drivers/infiniband/hw/efa/efa_admin_cmds_defs.h u32 reg_val; reg_val 129 drivers/infiniband/hw/efa/efa_com.c err = read_resp->reg_val; reg_val 361 drivers/infiniband/hw/hns/hns_roce_hw_v1.c u32 reg_val; reg_val 408 drivers/infiniband/hw/hns/hns_roce_hw_v1.c reg_val = roce_read(to_hr_dev(ibqp->device), reg_val 411 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(reg_val); reg_val 416 drivers/infiniband/hw/hns/hns_roce_hw_v1.c reg_val = le32_to_cpu(tmp); reg_val 419 drivers/infiniband/hw/hns/hns_roce_hw_v1.c QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val); reg_val 2580 drivers/infiniband/hw/hns/hns_roce_hw_v1.c u32 reg_val; reg_val 2681 drivers/infiniband/hw/hns/hns_roce_hw_v1.c reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG + reg_val 2683 drivers/infiniband/hw/hns/hns_roce_hw_v1.c tmp = cpu_to_le32(reg_val); reg_val 2686 drivers/infiniband/hw/hns/hns_roce_hw_v1.c reg_val = le32_to_cpu(tmp); reg_val 2688 drivers/infiniband/hw/hns/hns_roce_hw_v1.c hr_qp->phy_port * sizeof(*context), reg_val); reg_val 82 drivers/input/keyboard/imx_keypad.c unsigned short reg_val; reg_val 93 drivers/input/keyboard/imx_keypad.c reg_val = readw(keypad->mmio_base + KPDR); reg_val 94 drivers/input/keyboard/imx_keypad.c reg_val |= 0xff00; reg_val 95 drivers/input/keyboard/imx_keypad.c writew(reg_val, keypad->mmio_base + KPDR); reg_val 97 drivers/input/keyboard/imx_keypad.c reg_val = readw(keypad->mmio_base + KPCR); reg_val 98 drivers/input/keyboard/imx_keypad.c reg_val &= ~((keypad->cols_en_mask & 0xff) << 8); reg_val 99 drivers/input/keyboard/imx_keypad.c writew(reg_val, keypad->mmio_base + KPCR); reg_val 103 drivers/input/keyboard/imx_keypad.c reg_val = readw(keypad->mmio_base + KPCR); reg_val 104 drivers/input/keyboard/imx_keypad.c reg_val |= (keypad->cols_en_mask & 0xff) << 8; reg_val 105 drivers/input/keyboard/imx_keypad.c writew(reg_val, keypad->mmio_base + KPCR); reg_val 112 drivers/input/keyboard/imx_keypad.c reg_val = readw(keypad->mmio_base + KPDR); reg_val 113 drivers/input/keyboard/imx_keypad.c reg_val &= ~(1 << (8 + col)); reg_val 114 drivers/input/keyboard/imx_keypad.c writew(reg_val, keypad->mmio_base + KPDR); reg_val 126 drivers/input/keyboard/imx_keypad.c reg_val = readw(keypad->mmio_base + KPDR); reg_val 127 drivers/input/keyboard/imx_keypad.c matrix_volatile_state[col] = (~reg_val) & keypad->rows_en_mask; reg_val 134 drivers/input/keyboard/imx_keypad.c reg_val = readw(keypad->mmio_base + KPDR); reg_val 135 drivers/input/keyboard/imx_keypad.c reg_val &= 0x00ff; reg_val 136 drivers/input/keyboard/imx_keypad.c writew(reg_val, keypad->mmio_base + KPDR); reg_val 187 drivers/input/keyboard/imx_keypad.c unsigned short reg_val; reg_val 258 drivers/input/keyboard/imx_keypad.c reg_val = readw(keypad->mmio_base + KPSR); reg_val 259 drivers/input/keyboard/imx_keypad.c reg_val |= KBD_STAT_KPKD | KBD_STAT_KDSC; reg_val 260 drivers/input/keyboard/imx_keypad.c writew(reg_val, keypad->mmio_base + KPSR); reg_val 262 drivers/input/keyboard/imx_keypad.c reg_val = readw(keypad->mmio_base + KPSR); reg_val 263 drivers/input/keyboard/imx_keypad.c reg_val |= KBD_STAT_KDIE; reg_val 264 drivers/input/keyboard/imx_keypad.c reg_val &= ~KBD_STAT_KRIE; reg_val 265 drivers/input/keyboard/imx_keypad.c writew(reg_val, keypad->mmio_base + KPSR); reg_val 276 drivers/input/keyboard/imx_keypad.c reg_val = readw(keypad->mmio_base + KPSR); reg_val 277 drivers/input/keyboard/imx_keypad.c reg_val |= KBD_STAT_KPKR | KBD_STAT_KRSS; reg_val 278 drivers/input/keyboard/imx_keypad.c writew(reg_val, keypad->mmio_base + KPSR); reg_val 280 drivers/input/keyboard/imx_keypad.c reg_val = readw(keypad->mmio_base + KPSR); reg_val 281 drivers/input/keyboard/imx_keypad.c reg_val |= KBD_STAT_KRIE; reg_val 282 drivers/input/keyboard/imx_keypad.c reg_val &= ~KBD_STAT_KDIE; reg_val 283 drivers/input/keyboard/imx_keypad.c writew(reg_val, keypad->mmio_base + KPSR); reg_val 290 drivers/input/keyboard/imx_keypad.c unsigned short reg_val; reg_val 292 drivers/input/keyboard/imx_keypad.c reg_val = readw(keypad->mmio_base + KPSR); reg_val 295 drivers/input/keyboard/imx_keypad.c reg_val &= ~(KBD_STAT_KRIE | KBD_STAT_KDIE); reg_val 297 drivers/input/keyboard/imx_keypad.c reg_val |= KBD_STAT_KPKR | KBD_STAT_KPKD; reg_val 298 drivers/input/keyboard/imx_keypad.c writew(reg_val, keypad->mmio_base + KPSR); reg_val 314 drivers/input/keyboard/imx_keypad.c unsigned short reg_val; reg_val 320 drivers/input/keyboard/imx_keypad.c reg_val = readw(keypad->mmio_base + KPCR); reg_val 321 drivers/input/keyboard/imx_keypad.c reg_val |= keypad->rows_en_mask & 0xff; /* rows */ reg_val 322 drivers/input/keyboard/imx_keypad.c reg_val |= (keypad->cols_en_mask & 0xff) << 8; /* cols */ reg_val 323 drivers/input/keyboard/imx_keypad.c writew(reg_val, keypad->mmio_base + KPCR); reg_val 326 drivers/input/keyboard/imx_keypad.c reg_val = readw(keypad->mmio_base + KPDR); reg_val 327 drivers/input/keyboard/imx_keypad.c reg_val &= 0x00ff; reg_val 328 drivers/input/keyboard/imx_keypad.c writew(reg_val, keypad->mmio_base + KPDR); reg_val 337 drivers/input/keyboard/imx_keypad.c reg_val = readw(keypad->mmio_base + KPSR); reg_val 338 drivers/input/keyboard/imx_keypad.c reg_val |= KBD_STAT_KPKR | KBD_STAT_KPKD | reg_val 340 drivers/input/keyboard/imx_keypad.c writew(reg_val, keypad->mmio_base + KPSR); reg_val 343 drivers/input/keyboard/imx_keypad.c reg_val |= KBD_STAT_KDIE; reg_val 344 drivers/input/keyboard/imx_keypad.c reg_val &= ~KBD_STAT_KRIE; reg_val 345 drivers/input/keyboard/imx_keypad.c writew(reg_val, keypad->mmio_base + KPSR); reg_val 350 drivers/input/keyboard/imx_keypad.c unsigned short reg_val; reg_val 353 drivers/input/keyboard/imx_keypad.c reg_val = readw(keypad->mmio_base + KPSR); reg_val 354 drivers/input/keyboard/imx_keypad.c reg_val &= ~(KBD_STAT_KRIE | KBD_STAT_KDIE); reg_val 355 drivers/input/keyboard/imx_keypad.c reg_val |= KBD_STAT_KPKR | KBD_STAT_KPKD; reg_val 356 drivers/input/keyboard/imx_keypad.c writew(reg_val, keypad->mmio_base + KPSR); reg_val 359 drivers/input/keyboard/imx_keypad.c reg_val = (keypad->cols_en_mask & 0xff) << 8; reg_val 360 drivers/input/keyboard/imx_keypad.c writew(reg_val, keypad->mmio_base + KPCR); reg_val 530 drivers/input/keyboard/imx_keypad.c unsigned short reg_val = readw(kbd->mmio_base + KPSR); reg_val 541 drivers/input/keyboard/imx_keypad.c if (reg_val & KBD_STAT_KPKD) reg_val 542 drivers/input/keyboard/imx_keypad.c reg_val |= KBD_STAT_KRIE; reg_val 543 drivers/input/keyboard/imx_keypad.c if (reg_val & KBD_STAT_KPKR) reg_val 544 drivers/input/keyboard/imx_keypad.c reg_val |= KBD_STAT_KDIE; reg_val 545 drivers/input/keyboard/imx_keypad.c writew(reg_val, kbd->mmio_base + KPSR); reg_val 91 drivers/input/keyboard/tca6416-keypad.c u16 reg_val, val; reg_val 94 drivers/input/keyboard/tca6416-keypad.c error = tca6416_read_reg(chip, TCA6416_INPUT, ®_val); reg_val 98 drivers/input/keyboard/tca6416-keypad.c reg_val &= chip->pinmask; reg_val 101 drivers/input/keyboard/tca6416-keypad.c val = reg_val ^ chip->reg_input; reg_val 102 drivers/input/keyboard/tca6416-keypad.c chip->reg_input = reg_val; reg_val 108 drivers/input/keyboard/tca6416-keypad.c int state = ((reg_val & (1 << i)) ? 1 : 0) reg_val 1931 drivers/input/mouse/alps.c u16 reg_val = 0x181; reg_val 1938 drivers/input/mouse/alps.c ret = alps_monitor_mode_write_reg(psmouse, 0x000, reg_val); reg_val 2095 drivers/input/mouse/alps.c int reg_val, ret = -1; reg_val 2100 drivers/input/mouse/alps.c reg_val = alps_command_mode_read_reg(psmouse, reg_base + 0x0008); reg_val 2101 drivers/input/mouse/alps.c if (reg_val == -1) reg_val 2105 drivers/input/mouse/alps.c reg_val |= 0x01; reg_val 2107 drivers/input/mouse/alps.c reg_val &= ~0x01; reg_val 2109 drivers/input/mouse/alps.c ret = __alps_command_mode_write_reg(psmouse, reg_val); reg_val 2120 drivers/input/mouse/alps.c int reg_val; reg_val 2122 drivers/input/mouse/alps.c reg_val = alps_command_mode_read_reg(psmouse, 0x0004); reg_val 2123 drivers/input/mouse/alps.c if (reg_val == -1) reg_val 2126 drivers/input/mouse/alps.c reg_val |= 0x06; reg_val 2127 drivers/input/mouse/alps.c if (__alps_command_mode_write_reg(psmouse, reg_val)) reg_val 2135 drivers/input/mouse/alps.c int ret = -EIO, reg_val; reg_val 2140 drivers/input/mouse/alps.c reg_val = alps_command_mode_read_reg(psmouse, reg_base + 0x08); reg_val 2141 drivers/input/mouse/alps.c if (reg_val == -1) reg_val 2145 drivers/input/mouse/alps.c ret = reg_val & 0x80 ? 0 : -ENODEV; reg_val 2155 drivers/input/mouse/alps.c int reg_val; reg_val 2198 drivers/input/mouse/alps.c reg_val = alps_command_mode_read_reg(psmouse, reg_base + 0x08); reg_val 2199 drivers/input/mouse/alps.c if (reg_val == -1) { reg_val 2206 drivers/input/mouse/alps.c reg_val |= BIT(1); reg_val 2207 drivers/input/mouse/alps.c if (__alps_command_mode_write_reg(psmouse, reg_val)) reg_val 2221 drivers/input/mouse/alps.c int reg_val; reg_val 2234 drivers/input/mouse/alps.c reg_val = alps_command_mode_read_reg(psmouse, 0x0006); reg_val 2235 drivers/input/mouse/alps.c if (reg_val == -1) reg_val 2237 drivers/input/mouse/alps.c if (__alps_command_mode_write_reg(psmouse, reg_val | 0x01)) reg_val 2240 drivers/input/mouse/alps.c reg_val = alps_command_mode_read_reg(psmouse, 0x0007); reg_val 2241 drivers/input/mouse/alps.c if (reg_val == -1) reg_val 2243 drivers/input/mouse/alps.c if (__alps_command_mode_write_reg(psmouse, reg_val | 0x01)) reg_val 2331 drivers/input/mouse/alps.c int reg_val, ret = -1; reg_val 2334 drivers/input/mouse/alps.c reg_val = alps_setup_trackstick_v3(psmouse, reg_val 2336 drivers/input/mouse/alps.c if (reg_val == -EIO) reg_val 2348 drivers/input/mouse/alps.c reg_val = alps_command_mode_read_reg(psmouse, 0xc2c6); reg_val 2349 drivers/input/mouse/alps.c if (reg_val == -1) reg_val 2351 drivers/input/mouse/alps.c if (__alps_command_mode_write_reg(psmouse, reg_val & 0xfd)) reg_val 2358 drivers/input/mouse/alps.c reg_val = alps_command_mode_read_reg(psmouse, 0xc2c4); reg_val 2359 drivers/input/mouse/alps.c if (reg_val == -1) reg_val 2361 drivers/input/mouse/alps.c if (__alps_command_mode_write_reg(psmouse, reg_val | 0x02)) reg_val 2375 drivers/input/mouse/alps.c int reg_val; reg_val 2377 drivers/input/mouse/alps.c reg_val = alps_command_mode_read_reg(psmouse, 0x0004); reg_val 2378 drivers/input/mouse/alps.c if (reg_val == -1) reg_val 2381 drivers/input/mouse/alps.c reg_val |= 0x02; reg_val 2382 drivers/input/mouse/alps.c if (__alps_command_mode_write_reg(psmouse, reg_val)) reg_val 2553 drivers/input/mouse/alps.c int reg_val = 0; reg_val 2563 drivers/input/mouse/alps.c reg_val = alps_command_mode_read_reg(psmouse, reg_val 2569 drivers/input/mouse/alps.c if (reg_val == 0x0C || reg_val == 0x1D) reg_val 2667 drivers/input/mouse/alps.c int reg_val, ret = -1; reg_val 2679 drivers/input/mouse/alps.c reg_val = alps_command_mode_read_reg(psmouse, 0xc2c4); reg_val 2680 drivers/input/mouse/alps.c if (reg_val == -1) reg_val 2682 drivers/input/mouse/alps.c if (__alps_command_mode_write_reg(psmouse, reg_val | 0x02)) reg_val 37 drivers/input/mouse/sentelic.c static unsigned char fsp_test_swap_cmd(unsigned char reg_val) reg_val 39 drivers/input/mouse/sentelic.c switch (reg_val) { reg_val 46 drivers/input/mouse/sentelic.c return (reg_val >> 4) | (reg_val << 4); reg_val 48 drivers/input/mouse/sentelic.c return reg_val; /* swap isn't necessary */ reg_val 56 drivers/input/mouse/sentelic.c static unsigned char fsp_test_invert_cmd(unsigned char reg_val) reg_val 58 drivers/input/mouse/sentelic.c switch (reg_val) { reg_val 65 drivers/input/mouse/sentelic.c return ~reg_val; reg_val 67 drivers/input/mouse/sentelic.c return reg_val; /* inversion isn't necessary */ reg_val 71 drivers/input/mouse/sentelic.c static int fsp_reg_read(struct psmouse *psmouse, int reg_addr, int *reg_val) reg_val 116 drivers/input/mouse/sentelic.c *reg_val = param[2]; reg_val 124 drivers/input/mouse/sentelic.c reg_addr, *reg_val, rc); reg_val 128 drivers/input/mouse/sentelic.c static int fsp_reg_write(struct psmouse *psmouse, int reg_addr, int reg_val) reg_val 157 drivers/input/mouse/sentelic.c if ((v = fsp_test_invert_cmd(reg_val)) != reg_val) { reg_val 160 drivers/input/mouse/sentelic.c } else if ((v = fsp_test_swap_cmd(reg_val)) != reg_val) { reg_val 176 drivers/input/mouse/sentelic.c reg_addr, reg_val, rc); reg_val 201 drivers/input/mouse/sentelic.c static int fsp_page_reg_read(struct psmouse *psmouse, int *reg_val) reg_val 227 drivers/input/mouse/sentelic.c *reg_val = param[2]; reg_val 235 drivers/input/mouse/sentelic.c *reg_val, rc); reg_val 239 drivers/input/mouse/sentelic.c static int fsp_page_reg_write(struct psmouse *psmouse, int reg_val) reg_val 256 drivers/input/mouse/sentelic.c if ((v = fsp_test_invert_cmd(reg_val)) != reg_val) { reg_val 258 drivers/input/mouse/sentelic.c } else if ((v = fsp_test_swap_cmd(reg_val)) != reg_val) { reg_val 273 drivers/input/mouse/sentelic.c reg_val, rc); reg_val 117 drivers/input/touchscreen/sun4i-ts.c static void sun4i_ts_irq_handle_input(struct sun4i_ts_data *ts, u32 reg_val) reg_val 121 drivers/input/touchscreen/sun4i-ts.c if (reg_val & FIFO_DATA_PENDING) { reg_val 140 drivers/input/touchscreen/sun4i-ts.c if (reg_val & TP_UP_PENDING) { reg_val 150 drivers/input/touchscreen/sun4i-ts.c u32 reg_val; reg_val 152 drivers/input/touchscreen/sun4i-ts.c reg_val = readl(ts->base + TP_INT_FIFOS); reg_val 154 drivers/input/touchscreen/sun4i-ts.c if (reg_val & TEMP_DATA_PENDING) reg_val 158 drivers/input/touchscreen/sun4i-ts.c sun4i_ts_irq_handle_input(ts, reg_val); reg_val 160 drivers/input/touchscreen/sun4i-ts.c writel(reg_val, ts->base + TP_INT_FIFOS); reg_val 66 drivers/isdn/hardware/mISDN/hfcsusb.c cpu_to_le16(hw->ctrl_buff[hw->ctrl_out_idx].reg_val); reg_val 91 drivers/isdn/hardware/mISDN/hfcsusb.c buf->reg_val = val; reg_val 117 drivers/isdn/hardware/mISDN/hfcsusb.h __u8 reg_val; /* value to be written (or read) */ reg_val 230 drivers/leds/leds-lm3530.c u8 reg_val[LM3530_REG_MAX]; reg_val 266 drivers/leds/leds-lm3530.c reg_val[0] = gen_config; /* LM3530_GEN_CONFIG */ reg_val 267 drivers/leds/leds-lm3530.c reg_val[1] = als.config; /* LM3530_ALS_CONFIG */ reg_val 268 drivers/leds/leds-lm3530.c reg_val[2] = brt_ramp; /* LM3530_BRT_RAMP_RATE */ reg_val 269 drivers/leds/leds-lm3530.c reg_val[3] = als.imp_sel; /* LM3530_ALS_IMP_SELECT */ reg_val 270 drivers/leds/leds-lm3530.c reg_val[4] = brightness; /* LM3530_BRT_CTRL_REG */ reg_val 271 drivers/leds/leds-lm3530.c reg_val[5] = als.zones[0]; /* LM3530_ALS_ZB0_REG */ reg_val 272 drivers/leds/leds-lm3530.c reg_val[6] = als.zones[1]; /* LM3530_ALS_ZB1_REG */ reg_val 273 drivers/leds/leds-lm3530.c reg_val[7] = als.zones[2]; /* LM3530_ALS_ZB2_REG */ reg_val 274 drivers/leds/leds-lm3530.c reg_val[8] = als.zones[3]; /* LM3530_ALS_ZB3_REG */ reg_val 275 drivers/leds/leds-lm3530.c reg_val[9] = LM3530_DEF_ZT_0; /* LM3530_ALS_Z0T_REG */ reg_val 276 drivers/leds/leds-lm3530.c reg_val[10] = LM3530_DEF_ZT_1; /* LM3530_ALS_Z1T_REG */ reg_val 277 drivers/leds/leds-lm3530.c reg_val[11] = LM3530_DEF_ZT_2; /* LM3530_ALS_Z2T_REG */ reg_val 278 drivers/leds/leds-lm3530.c reg_val[12] = LM3530_DEF_ZT_3; /* LM3530_ALS_Z3T_REG */ reg_val 279 drivers/leds/leds-lm3530.c reg_val[13] = LM3530_DEF_ZT_4; /* LM3530_ALS_Z4T_REG */ reg_val 290 drivers/leds/leds-lm3530.c pwm->pwm_set_intensity(reg_val[i], reg_val 296 drivers/leds/leds-lm3530.c lm3530_reg[i], reg_val[i]); reg_val 162 drivers/leds/leds-lm355x.c unsigned int reg_val; reg_val 168 drivers/leds/leds-lm355x.c reg_val = pdata->pin_tx2 | pdata->ntc_pin; reg_val 169 drivers/leds/leds-lm355x.c ret = regmap_update_bits(chip->regmap, 0xE0, 0x28, reg_val); reg_val 172 drivers/leds/leds-lm355x.c reg_val = pdata->pass_mode; reg_val 173 drivers/leds/leds-lm355x.c ret = regmap_update_bits(chip->regmap, 0xA0, 0x04, reg_val); reg_val 179 drivers/leds/leds-lm355x.c reg_val = pdata->pin_tx2 | pdata->ntc_pin | pdata->pass_mode; reg_val 180 drivers/leds/leds-lm355x.c ret = regmap_update_bits(chip->regmap, 0x0A, 0xC4, reg_val); reg_val 199 drivers/leds/leds-lm355x.c unsigned int reg_val; reg_val 251 drivers/leds/leds-lm355x.c reg_val = 0x00; reg_val 253 drivers/leds/leds-lm355x.c reg_val = 0x01; reg_val 258 drivers/leds/leds-lm355x.c reg_val << reg_val 26 drivers/leds/leds-wm831x-status.c int reg_val; /* Control register value */ reg_val 44 drivers/leds/leds-wm831x-status.c led->reg_val &= ~(WM831X_LED_SRC_MASK | WM831X_LED_MODE_MASK | reg_val 49 drivers/leds/leds-wm831x-status.c led->reg_val |= led->src << WM831X_LED_SRC_SHIFT; reg_val 51 drivers/leds/leds-wm831x-status.c led->reg_val |= 2 << WM831X_LED_MODE_SHIFT; reg_val 52 drivers/leds/leds-wm831x-status.c led->reg_val |= led->blink_time << WM831X_LED_DUR_SHIFT; reg_val 53 drivers/leds/leds-wm831x-status.c led->reg_val |= led->blink_cyc; reg_val 56 drivers/leds/leds-wm831x-status.c led->reg_val |= 1 << WM831X_LED_MODE_SHIFT; reg_val 61 drivers/leds/leds-wm831x-status.c wm831x_reg_write(led->wm831x, led->reg, led->reg_val); reg_val 248 drivers/leds/leds-wm831x-status.c drvdata->reg_val = wm831x_reg_read(wm831x, drvdata->reg); reg_val 250 drivers/leds/leds-wm831x-status.c if (drvdata->reg_val & WM831X_LED_MODE_MASK) reg_val 259 drivers/leds/leds-wm831x-status.c drvdata->src = drvdata->reg_val; reg_val 33 drivers/media/dvb-frontends/af9033.c const struct reg_val *tab, int tab_len) reg_val 75 drivers/media/dvb-frontends/af9033.c const struct reg_val *init; reg_val 87 drivers/media/dvb-frontends/af9033_priv.h static const struct reg_val ofsm_init[] = { reg_val 202 drivers/media/dvb-frontends/af9033_priv.h static const struct reg_val tuner_init_tua9001[] = { reg_val 246 drivers/media/dvb-frontends/af9033_priv.h static const struct reg_val tuner_init_fc0011[] = { reg_val 309 drivers/media/dvb-frontends/af9033_priv.h static const struct reg_val tuner_init_fc0012[] = { reg_val 354 drivers/media/dvb-frontends/af9033_priv.h static const struct reg_val tuner_init_mxl5007t[] = { reg_val 391 drivers/media/dvb-frontends/af9033_priv.h static const struct reg_val tuner_init_tda18218[] = { reg_val 427 drivers/media/dvb-frontends/af9033_priv.h static const struct reg_val tuner_init_fc2580[] = { reg_val 467 drivers/media/dvb-frontends/af9033_priv.h static const struct reg_val ofsm_init_it9135_v1[] = { reg_val 582 drivers/media/dvb-frontends/af9033_priv.h static const struct reg_val tuner_init_it9135_38[] = { reg_val 801 drivers/media/dvb-frontends/af9033_priv.h static const struct reg_val tuner_init_it9135_51[] = { reg_val 1020 drivers/media/dvb-frontends/af9033_priv.h static const struct reg_val tuner_init_it9135_52[] = { reg_val 1238 drivers/media/dvb-frontends/af9033_priv.h static const struct reg_val ofsm_init_it9135_v2[] = { reg_val 1340 drivers/media/dvb-frontends/af9033_priv.h static const struct reg_val tuner_init_it9135_60[] = { reg_val 1556 drivers/media/dvb-frontends/af9033_priv.h static const struct reg_val tuner_init_it9135_61[] = { reg_val 1772 drivers/media/dvb-frontends/af9033_priv.h static const struct reg_val tuner_init_it9135_62[] = { reg_val 40 drivers/media/dvb-frontends/au8522_decoder.c u8 reg_val[8]; reg_val 284 drivers/media/dvb-frontends/au8522_decoder.c filter_coef[i].reg_val[filter_coef_type]); reg_val 406 drivers/media/dvb-frontends/au8522_decoder.c lpfilter_coef[i].reg_val[0]); reg_val 46 drivers/media/dvb-frontends/tc90522.c reg_write(struct tc90522_state *state, const struct reg_val *regs, int num) reg_val 100 drivers/media/dvb-frontends/tc90522.c struct reg_val set_tsid[] = { reg_val 112 drivers/media/dvb-frontends/tc90522.c struct reg_val rv; reg_val 474 drivers/media/dvb-frontends/tc90522.c static const struct reg_val reset_sat = { 0x03, 0x01 }; reg_val 475 drivers/media/dvb-frontends/tc90522.c static const struct reg_val reset_ter = { 0x01, 0x40 }; reg_val 530 drivers/media/dvb-frontends/tc90522.c struct reg_val agc_sat[] = { reg_val 536 drivers/media/dvb-frontends/tc90522.c struct reg_val agc_ter[] = { reg_val 542 drivers/media/dvb-frontends/tc90522.c struct reg_val *rv; reg_val 562 drivers/media/dvb-frontends/tc90522.c static const struct reg_val sleep_sat = { 0x17, 0x01 }; reg_val 563 drivers/media/dvb-frontends/tc90522.c static const struct reg_val sleep_ter = { 0x03, 0x90 }; reg_val 589 drivers/media/dvb-frontends/tc90522.c static const struct reg_val wakeup_sat = { 0x17, 0x00 }; reg_val 590 drivers/media/dvb-frontends/tc90522.c static const struct reg_val wakeup_ter = { 0x03, 0x80 }; reg_val 1441 drivers/media/i2c/imx274.c u8 reg_val; reg_val 1443 drivers/media/i2c/imx274.c reg_val = ffs(dgain); reg_val 1445 drivers/media/i2c/imx274.c if (reg_val) reg_val 1446 drivers/media/i2c/imx274.c reg_val--; reg_val 1448 drivers/media/i2c/imx274.c reg_val = clamp(reg_val, (u8)0, (u8)3); reg_val 1451 drivers/media/i2c/imx274.c reg_val & IMX274_MASK_LSB_4_BITS); reg_val 169 drivers/media/i2c/lm3560.c unsigned int reg_val; reg_val 170 drivers/media/i2c/lm3560.c rval = regmap_read(flash->regmap, REG_FLAG, ®_val); reg_val 173 drivers/media/i2c/lm3560.c if (reg_val & FAULT_SHORT_CIRCUIT) reg_val 175 drivers/media/i2c/lm3560.c if (reg_val & FAULT_OVERTEMP) reg_val 177 drivers/media/i2c/lm3560.c if (reg_val & FAULT_TIMEOUT) reg_val 377 drivers/media/i2c/lm3560.c unsigned int reg_val; reg_val 390 drivers/media/i2c/lm3560.c rval = regmap_read(flash->regmap, REG_FLAG, ®_val); reg_val 102 drivers/media/i2c/lm3646.c unsigned int reg_val; reg_val 108 drivers/media/i2c/lm3646.c rval = regmap_read(flash->regmap, REG_FLAG, ®_val); reg_val 113 drivers/media/i2c/lm3646.c if (reg_val & FAULT_TIMEOUT) reg_val 115 drivers/media/i2c/lm3646.c if (reg_val & FAULT_SHORT_CIRCUIT) reg_val 117 drivers/media/i2c/lm3646.c if (reg_val & FAULT_UVLO) reg_val 119 drivers/media/i2c/lm3646.c if (reg_val & FAULT_IVFM) reg_val 121 drivers/media/i2c/lm3646.c if (reg_val & FAULT_OCP) reg_val 123 drivers/media/i2c/lm3646.c if (reg_val & FAULT_OVERTEMP) reg_val 125 drivers/media/i2c/lm3646.c if (reg_val & FAULT_NTC_TRIP) reg_val 127 drivers/media/i2c/lm3646.c if (reg_val & FAULT_OVP) reg_val 136 drivers/media/i2c/lm3646.c unsigned int reg_val; reg_val 155 drivers/media/i2c/lm3646.c rval = regmap_read(flash->regmap, REG_ENABLE, ®_val); reg_val 156 drivers/media/i2c/lm3646.c if (rval < 0 || ((reg_val & MASK_ENABLE) != MODE_SHDN)) reg_val 168 drivers/media/i2c/lm3646.c rval = regmap_read(flash->regmap, REG_ENABLE, ®_val); reg_val 171 drivers/media/i2c/lm3646.c if ((reg_val & MASK_ENABLE) == MODE_FLASH) reg_val 296 drivers/media/i2c/lm3646.c unsigned int reg_val; reg_val 300 drivers/media/i2c/lm3646.c rval = regmap_read(flash->regmap, REG_ENABLE, ®_val); reg_val 303 drivers/media/i2c/lm3646.c flash->mode_reg = reg_val & 0xfc; reg_val 334 drivers/media/i2c/lm3646.c return regmap_read(flash->regmap, REG_FLAG, ®_val); reg_val 239 drivers/media/i2c/mt9m032.c u16 reg_val = MT9M032_FORMATTER2_DOUT_EN reg_val 244 drivers/media/i2c/mt9m032.c reg_val |= MT9M032_FORMATTER2_PIXCLK_EN; /* pixclock enable */ reg_val 246 drivers/media/i2c/mt9m032.c return mt9m032_write(client, MT9M032_FORMATTER2, reg_val); reg_val 270 drivers/media/i2c/mt9m032.c u16 reg_val; reg_val 294 drivers/media/i2c/mt9m032.c reg_val = (pll.p1 == 6 ? MT9M032_FORMATTER1_PLL_P1_6 : 0) reg_val 296 drivers/media/i2c/mt9m032.c ret = mt9m032_write(client, MT9M032_FORMATTER1, reg_val); reg_val 585 drivers/media/i2c/mt9m032.c int reg_val = (vflip << MT9M032_READ_MODE2_VFLIP_SHIFT) reg_val 590 drivers/media/i2c/mt9m032.c return mt9m032_write(client, MT9M032_READ_MODE2, reg_val); reg_val 599 drivers/media/i2c/mt9m032.c u16 reg_val; reg_val 614 drivers/media/i2c/mt9m032.c reg_val = ((digital_gain_val & MT9M032_GAIN_DIGITAL_MASK) reg_val 619 drivers/media/i2c/mt9m032.c return mt9m032_write(client, MT9M032_GAIN_ALL, reg_val); reg_val 225 drivers/media/i2c/mt9m111.c unsigned int reg_val; reg_val 260 drivers/media/i2c/mt9m111.c .reg_val = MT9M111_RM_LOW_POWER_RD, reg_val 269 drivers/media/i2c/mt9m111.c .reg_val = MT9M111_RM_FULL_POWER_RD, reg_val 278 drivers/media/i2c/mt9m111.c .reg_val = MT9M111_RM_LOW_POWER_RD | MT9M111_RM_COL_SKIP_2X | reg_val 945 drivers/media/i2c/mt9m111.c mt9m111->current_mode->reg_val, reg_val 382 drivers/media/i2c/s5c73m3/s5c73m3-core.c prev_size->width, prev_size->height, prev_size->reg_val); reg_val 384 drivers/media/i2c/s5c73m3/s5c73m3-core.c chg_mode = prev_size->reg_val | COMM_CHG_MODE_NEW; reg_val 389 drivers/media/i2c/s5c73m3/s5c73m3-core.c cap_size->width, cap_size->height, cap_size->reg_val); reg_val 390 drivers/media/i2c/s5c73m3/s5c73m3-core.c chg_mode |= cap_size->reg_val; reg_val 423 drivers/media/i2c/s5c73m3/s5c73m3.h u8 reg_val; reg_val 92 drivers/media/pci/pt3/pt3.c pt3_demod_write(struct pt3_adapter *adap, const struct reg_val *data, int num) reg_val 139 drivers/media/pci/pt3/pt3.c struct reg_val rv = { 0x1e, 0x99 }; reg_val 217 drivers/media/pci/pt3/pt3.c static const struct reg_val init0_sat[] = { reg_val 221 drivers/media/pci/pt3/pt3.c static const struct reg_val init0_ter[] = { reg_val 225 drivers/media/pci/pt3/pt3.c static const struct reg_val cfg_sat[] = { reg_val 229 drivers/media/pci/pt3/pt3.c static const struct reg_val cfg_ter[] = { reg_val 175 drivers/media/platform/fsl-viu.c static struct viu_reg reg_val; reg_val 403 drivers/media/platform/fsl-viu.c reg_val.field_base_addr = videobuf_to_dma_contig(&buf->vb); reg_val 406 drivers/media/platform/fsl-viu.c buf, buf->vb.i, (unsigned long)reg_val.field_base_addr); reg_val 409 drivers/media/platform/fsl-viu.c reg_val.status_cfg = 0; reg_val 413 drivers/media/platform/fsl-viu.c reg_val.status_cfg &= ~MODE_32BIT; reg_val 414 drivers/media/platform/fsl-viu.c reg_val.dma_inc = buf->vb.width * 2; reg_val 417 drivers/media/platform/fsl-viu.c reg_val.status_cfg |= MODE_32BIT; reg_val 418 drivers/media/platform/fsl-viu.c reg_val.dma_inc = buf->vb.width * 4; reg_val 427 drivers/media/platform/fsl-viu.c reg_val.picture_count = (buf->vb.height / 2) << 16 | reg_val 430 drivers/media/platform/fsl-viu.c reg_val.status_cfg |= DMA_ACT | INT_DMA_END_EN | INT_FIELD_EN; reg_val 437 drivers/media/platform/fsl-viu.c reg_val.dma_inc = 0; reg_val 439 drivers/media/platform/fsl-viu.c out_be32(&vr->dma_inc, reg_val.dma_inc); reg_val 440 drivers/media/platform/fsl-viu.c out_be32(&vr->picture_count, reg_val.picture_count); reg_val 441 drivers/media/platform/fsl-viu.c out_be32(&vr->field_base_addr, reg_val.field_base_addr); reg_val 701 drivers/media/platform/fsl-viu.c out_be32(&vr->field_base_addr, reg_val.field_base_addr); reg_val 702 drivers/media/platform/fsl-viu.c out_be32(&vr->dma_inc, reg_val.dma_inc); reg_val 703 drivers/media/platform/fsl-viu.c out_be32(&vr->picture_count, reg_val.picture_count); reg_val 713 drivers/media/platform/fsl-viu.c reg_val.status_cfg = 0; reg_val 716 drivers/media/platform/fsl-viu.c reg_val.picture_count = (fh->win.w.height / 2) << 16 | reg_val 723 drivers/media/platform/fsl-viu.c reg_val.status_cfg &= ~MODE_32BIT; reg_val 724 drivers/media/platform/fsl-viu.c reg_val.dma_inc = fh->win.w.width * 2; reg_val 727 drivers/media/platform/fsl-viu.c reg_val.status_cfg |= MODE_32BIT; reg_val 728 drivers/media/platform/fsl-viu.c reg_val.dma_inc = fh->win.w.width * 4; reg_val 738 drivers/media/platform/fsl-viu.c reg_val.dma_inc = 0; reg_val 740 drivers/media/platform/fsl-viu.c reg_val.status_cfg |= DMA_ACT | INT_DMA_END_EN | INT_FIELD_EN; reg_val 743 drivers/media/platform/fsl-viu.c reg_val.field_base_addr = (u32)(long)dev->ovbuf.base; reg_val 1000 drivers/media/platform/fsl-viu.c u32 addr = reg_val.field_base_addr; reg_val 1004 drivers/media/platform/fsl-viu.c addr += reg_val.dma_inc; reg_val 1007 drivers/media/platform/fsl-viu.c out_be32(&vr->dma_inc, reg_val.dma_inc); reg_val 1011 drivers/media/platform/fsl-viu.c reg_val.status_cfg); reg_val 1016 drivers/media/platform/fsl-viu.c reg_val.status_cfg); reg_val 1055 drivers/media/platform/fsl-viu.c u32 addr = reg_val.field_base_addr; reg_val 1058 drivers/media/platform/fsl-viu.c addr += reg_val.dma_inc; reg_val 1063 drivers/media/platform/fsl-viu.c out_be32(&vr->dma_inc, reg_val.dma_inc); reg_val 1067 drivers/media/platform/fsl-viu.c reg_val.status_cfg); reg_val 407 drivers/media/platform/qcom/venus/core.c static const struct reg_val msm8916_reg_preset[] = { reg_val 437 drivers/media/platform/qcom/venus/core.c static const struct reg_val msm8996_reg_preset[] = { reg_val 33 drivers/media/platform/qcom/venus/core.h const struct reg_val *reg_tbl; reg_val 361 drivers/media/platform/qcom/venus/hfi_venus.c const struct reg_val *tbl = res->reg_tbl; reg_val 142 drivers/media/tuners/mxl301rf.c static const struct reg_val set_idac[] = { reg_val 155 drivers/media/tuners/mxl301rf.c struct reg_val tune0[] = { reg_val 165 drivers/media/tuners/mxl301rf.c struct reg_val tune1[] = { reg_val 229 drivers/media/tuners/mxl301rf.c static const struct reg_val standby_data[] = { reg_val 288 drivers/media/usb/as102/as10x_cmd.h struct as10x_register_value reg_val; reg_val 299 drivers/media/usb/as102/as10x_cmd.h struct as10x_register_value reg_val; reg_val 315 drivers/media/usb/as102/as10x_cmd.h struct as10x_register_value reg_val; reg_val 341 drivers/media/usb/as102/as10x_cmd.h struct as10x_register_value reg_val; reg_val 63 drivers/media/usb/as102/as10x_cmd_cfg.c *pvalue = le32_to_cpu((__force __le32)prsp->body.context.rsp.reg_val.u.value32); reg_val 95 drivers/media/usb/as102/as10x_cmd_cfg.c pcmd->body.context.req.reg_val.u.value32 = (__force u32)cpu_to_le32(value); reg_val 188 drivers/memory/mtk-smi.c u32 sec_con_val, reg_val; reg_val 202 drivers/memory/mtk-smi.c reg_val = readl(common->smi_ao_base reg_val 204 drivers/memory/mtk-smi.c reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); reg_val 205 drivers/memory/mtk-smi.c reg_val |= sec_con_val; reg_val 206 drivers/memory/mtk-smi.c reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); reg_val 207 drivers/memory/mtk-smi.c writel(reg_val, reg_val 75 drivers/mfd/adp5520.c uint8_t reg_val; reg_val 80 drivers/mfd/adp5520.c ret = __adp5520_read(client, reg, ®_val); reg_val 83 drivers/mfd/adp5520.c reg_val |= bit_mask; reg_val 84 drivers/mfd/adp5520.c ret = __adp5520_write(client, reg, reg_val); reg_val 106 drivers/mfd/adp5520.c uint8_t reg_val; reg_val 111 drivers/mfd/adp5520.c ret = __adp5520_read(chip->client, reg, ®_val); reg_val 113 drivers/mfd/adp5520.c if (!ret && ((reg_val & bit_mask) != bit_mask)) { reg_val 114 drivers/mfd/adp5520.c reg_val |= bit_mask; reg_val 115 drivers/mfd/adp5520.c ret = __adp5520_write(chip->client, reg, reg_val); reg_val 126 drivers/mfd/adp5520.c uint8_t reg_val; reg_val 131 drivers/mfd/adp5520.c ret = __adp5520_read(chip->client, reg, ®_val); reg_val 133 drivers/mfd/adp5520.c if (!ret && (reg_val & bit_mask)) { reg_val 134 drivers/mfd/adp5520.c reg_val &= ~bit_mask; reg_val 135 drivers/mfd/adp5520.c ret = __adp5520_write(chip->client, reg, reg_val); reg_val 178 drivers/mfd/adp5520.c uint8_t reg_val; reg_val 181 drivers/mfd/adp5520.c ret = __adp5520_read(chip->client, ADP5520_MODE_STATUS, ®_val); reg_val 185 drivers/mfd/adp5520.c events = reg_val & (ADP5520_OVP_INT | ADP5520_CMPR_INT | reg_val 173 drivers/mfd/da903x.c uint8_t reg_val; reg_val 178 drivers/mfd/da903x.c ret = __da903x_read(chip->client, reg, ®_val); reg_val 182 drivers/mfd/da903x.c if ((reg_val & bit_mask) != bit_mask) { reg_val 183 drivers/mfd/da903x.c reg_val |= bit_mask; reg_val 184 drivers/mfd/da903x.c ret = __da903x_write(chip->client, reg, reg_val); reg_val 195 drivers/mfd/da903x.c uint8_t reg_val; reg_val 200 drivers/mfd/da903x.c ret = __da903x_read(chip->client, reg, ®_val); reg_val 204 drivers/mfd/da903x.c if (reg_val & bit_mask) { reg_val 205 drivers/mfd/da903x.c reg_val &= ~bit_mask; reg_val 206 drivers/mfd/da903x.c ret = __da903x_write(chip->client, reg, reg_val); reg_val 217 drivers/mfd/da903x.c uint8_t reg_val; reg_val 222 drivers/mfd/da903x.c ret = __da903x_read(chip->client, reg, ®_val); reg_val 226 drivers/mfd/da903x.c if ((reg_val & mask) != val) { reg_val 227 drivers/mfd/da903x.c reg_val = (reg_val & ~mask) | val; reg_val 228 drivers/mfd/da903x.c ret = __da903x_write(chip->client, reg, reg_val); reg_val 91 drivers/mfd/da9052-i2c.c int reg_val, ret; reg_val 93 drivers/mfd/da9052-i2c.c ret = regmap_read(da9052->regmap, DA9052_CONTROL_B_REG, ®_val); reg_val 97 drivers/mfd/da9052-i2c.c if (!(reg_val & DA9052_CONTROL_B_WRITEMODE)) { reg_val 98 drivers/mfd/da9052-i2c.c reg_val |= DA9052_CONTROL_B_WRITEMODE; reg_val 100 drivers/mfd/da9052-i2c.c reg_val); reg_val 262 drivers/mfd/twl6030-irq.c u8 reg_val = 0; reg_val 273 drivers/mfd/twl6030-irq.c ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val, TWL6030_MMCCTRL); reg_val 278 drivers/mfd/twl6030-irq.c reg_val &= ~VMMC_AUTO_OFF; reg_val 279 drivers/mfd/twl6030-irq.c reg_val |= SW_FC; reg_val 280 drivers/mfd/twl6030-irq.c ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL); reg_val 287 drivers/mfd/twl6030-irq.c ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val, reg_val 294 drivers/mfd/twl6030-irq.c reg_val &= ~(MMC_PU | MMC_PD); reg_val 295 drivers/mfd/twl6030-irq.c ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, reg_val 254 drivers/misc/xilinx_sdfec.c u32 reg_val; reg_val 257 drivers/misc/xilinx_sdfec.c reg_val = xsdfec_regread(xsdfec, reg_offset); reg_val 258 drivers/misc/xilinx_sdfec.c *config_value = (reg_val & bit_mask) > 0; reg_val 1113 drivers/mmc/host/omap_hsmmc.c u32 reg_val = 0; reg_val 1134 drivers/mmc/host/omap_hsmmc.c reg_val = OMAP_HSMMC_READ(host->base, HCTL); reg_val 1152 drivers/mmc/host/omap_hsmmc.c reg_val |= SDVS18; reg_val 1154 drivers/mmc/host/omap_hsmmc.c reg_val |= SDVS30; reg_val 1156 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); reg_val 278 drivers/mmc/host/sdhci-pxav3.c u8 reg_val = readb(pxa->sdio3_conf_reg); reg_val 282 drivers/mmc/host/sdhci-pxav3.c reg_val &= ~SDIO3_CONF_CLK_INV; reg_val 283 drivers/mmc/host/sdhci-pxav3.c reg_val |= SDIO3_CONF_SD_FB_CLK; reg_val 285 drivers/mmc/host/sdhci-pxav3.c reg_val &= ~SDIO3_CONF_CLK_INV; reg_val 286 drivers/mmc/host/sdhci-pxav3.c reg_val &= ~SDIO3_CONF_SD_FB_CLK; reg_val 288 drivers/mmc/host/sdhci-pxav3.c reg_val |= SDIO3_CONF_CLK_INV; reg_val 289 drivers/mmc/host/sdhci-pxav3.c reg_val &= ~SDIO3_CONF_SD_FB_CLK; reg_val 291 drivers/mmc/host/sdhci-pxav3.c writeb(reg_val, pxa->sdio3_conf_reg); reg_val 295 drivers/mtd/nand/raw/mtk_ecc.c u16 reg_val; reg_val 314 drivers/mtd/nand/raw/mtk_ecc.c reg_val = ECC_IRQ_EN; reg_val 321 drivers/mtd/nand/raw/mtk_ecc.c reg_val |= ECC_PG_IRQ_SEL; reg_val 323 drivers/mtd/nand/raw/mtk_ecc.c writew(reg_val, ecc->regs + reg_val 326 drivers/mtd/nand/raw/mtk_ecc.c writew(reg_val, ecc->regs + reg_val 103 drivers/mtd/nand/raw/omap_elm.c u32 reg_val; reg_val 121 drivers/mtd/nand/raw/omap_elm.c reg_val = (bch_type & ECC_BCH_LEVEL_MASK) | (ELM_ECC_SIZE << 16); reg_val 122 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, ELM_LOCATION_CONFIG, reg_val); reg_val 142 drivers/mtd/nand/raw/omap_elm.c u32 reg_val; reg_val 144 drivers/mtd/nand/raw/omap_elm.c reg_val = elm_read_reg(info, ELM_PAGE_CTRL); reg_val 146 drivers/mtd/nand/raw/omap_elm.c reg_val |= BIT(index); /* enable page mode */ reg_val 148 drivers/mtd/nand/raw/omap_elm.c reg_val &= ~BIT(index); /* disable page mode */ reg_val 150 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, ELM_PAGE_CTRL, reg_val); reg_val 251 drivers/mtd/nand/raw/omap_elm.c u32 reg_val; reg_val 261 drivers/mtd/nand/raw/omap_elm.c reg_val = elm_read_reg(info, offset); reg_val 262 drivers/mtd/nand/raw/omap_elm.c reg_val |= ELM_SYNDROME_VALID; reg_val 263 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, offset, reg_val); reg_val 284 drivers/mtd/nand/raw/omap_elm.c u32 reg_val; reg_val 291 drivers/mtd/nand/raw/omap_elm.c reg_val = elm_read_reg(info, offset); reg_val 294 drivers/mtd/nand/raw/omap_elm.c if (reg_val & ECC_CORRECTABLE_MASK) { reg_val 299 drivers/mtd/nand/raw/omap_elm.c err_vec[i].error_count = reg_val & reg_val 305 drivers/mtd/nand/raw/omap_elm.c reg_val = elm_read_reg(info, offset); reg_val 306 drivers/mtd/nand/raw/omap_elm.c err_vec[i].error_loc[j] = reg_val & reg_val 340 drivers/mtd/nand/raw/omap_elm.c u32 reg_val; reg_val 343 drivers/mtd/nand/raw/omap_elm.c reg_val = elm_read_reg(info, ELM_IRQSTATUS); reg_val 344 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, ELM_IRQSTATUS, reg_val & INTR_STATUS_PAGE_VALID); reg_val 357 drivers/mtd/nand/raw/omap_elm.c reg_val = elm_read_reg(info, ELM_IRQENABLE); reg_val 358 drivers/mtd/nand/raw/omap_elm.c elm_write_reg(info, ELM_IRQENABLE, reg_val & ~INTR_EN_PAGE_MASK); reg_val 365 drivers/mtd/nand/raw/omap_elm.c u32 reg_val; reg_val 368 drivers/mtd/nand/raw/omap_elm.c reg_val = elm_read_reg(info, ELM_IRQSTATUS); reg_val 371 drivers/mtd/nand/raw/omap_elm.c if (reg_val & INTR_STATUS_PAGE_VALID) { reg_val 373 drivers/mtd/nand/raw/omap_elm.c reg_val & INTR_STATUS_PAGE_VALID); reg_val 222 drivers/net/can/pch_can.c u32 reg_val = ioread32(&priv->regs->opt); reg_val 225 drivers/net/can/pch_can.c reg_val |= PCH_OPT_SILENT; reg_val 228 drivers/net/can/pch_can.c reg_val |= PCH_OPT_LBACK; reg_val 231 drivers/net/can/pch_can.c iowrite32(reg_val, &priv->regs->opt); reg_val 96 drivers/net/ethernet/allwinner/sun4i-emac.c unsigned int reg_val; reg_val 99 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); reg_val 100 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val &= ~(0x1 << 8); reg_val 102 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val |= 1 << 8; reg_val 103 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); reg_val 109 drivers/net/ethernet/allwinner/sun4i-emac.c unsigned int reg_val; reg_val 112 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); reg_val 113 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN; reg_val 115 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val |= EMAC_MAC_CTL1_DUPLEX_EN; reg_val 116 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); reg_val 258 drivers/net/ethernet/allwinner/sun4i-emac.c unsigned int reg_val; reg_val 261 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_TX_MODE_REG); reg_val 263 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN, reg_val 268 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); reg_val 269 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN | reg_val 274 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); reg_val 275 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val |= EMAC_MAC_CTL1_LEN_CHECK_EN; reg_val 276 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val |= EMAC_MAC_CTL1_CRC_EN; reg_val 277 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val |= EMAC_MAC_CTL1_PAD_EN; reg_val 278 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); reg_val 301 drivers/net/ethernet/allwinner/sun4i-emac.c unsigned int reg_val; reg_val 304 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_RX_CTL_REG); reg_val 307 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val |= EMAC_RX_CTL_PASS_ALL_EN; reg_val 309 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val &= ~EMAC_RX_CTL_PASS_ALL_EN; reg_val 311 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val | EMAC_RX_CTL_PASS_LEN_OOR_EN | reg_val 321 drivers/net/ethernet/allwinner/sun4i-emac.c unsigned int reg_val; reg_val 325 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_RX_CTL_REG); reg_val 326 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val |= 0x8; reg_val 327 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val, db->membase + EMAC_RX_CTL_REG); reg_val 332 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); reg_val 333 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val &= ~EMAC_MAC_CTL0_SOFT_RESET; reg_val 334 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val, db->membase + EMAC_MAC_CTL0_REG); reg_val 337 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_MAC_MCFG_REG); reg_val 338 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val &= (~(0xf << 2)); reg_val 339 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val |= (0xD << 2); reg_val 340 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val, db->membase + EMAC_MAC_MCFG_REG); reg_val 347 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_INT_STA_REG); reg_val 348 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val, db->membase + EMAC_INT_STA_REG); reg_val 389 drivers/net/ethernet/allwinner/sun4i-emac.c unsigned int reg_val; reg_val 397 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_CTL_REG); reg_val 398 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val | EMAC_CTL_RESET | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN, reg_val 402 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_INT_CTL_REG); reg_val 403 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val |= (0xf << 0) | (0x01 << 8); reg_val 404 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val, db->membase + EMAC_INT_CTL_REG); reg_val 518 drivers/net/ethernet/allwinner/sun4i-emac.c unsigned int reg_val; reg_val 543 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_RX_CTL_REG); reg_val 544 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val &= ~EMAC_RX_CTL_DMA_EN; reg_val 545 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val, db->membase + EMAC_RX_CTL_REG); reg_val 550 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_INT_CTL_REG); reg_val 551 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val |= (0xf << 0) | (0x01 << 8); reg_val 552 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val, db->membase + EMAC_INT_CTL_REG); reg_val 560 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_RX_IO_DATA_REG); reg_val 562 drivers/net/ethernet/allwinner/sun4i-emac.c dev_dbg(db->dev, "receive header: %x\n", reg_val); reg_val 563 drivers/net/ethernet/allwinner/sun4i-emac.c if (reg_val != EMAC_UNDOCUMENTED_MAGIC) { reg_val 565 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_CTL_REG); reg_val 566 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val & ~EMAC_CTL_RX_EN, reg_val 570 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_RX_CTL_REG); reg_val 571 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val | (1 << 3), reg_val 575 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_RX_CTL_REG); reg_val 576 drivers/net/ethernet/allwinner/sun4i-emac.c } while (reg_val & (1 << 3)); reg_val 579 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_CTL_REG); reg_val 580 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val | EMAC_CTL_RX_EN, reg_val 582 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_INT_CTL_REG); reg_val 583 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val |= (0xf << 0) | (0x01 << 8); reg_val 584 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val, db->membase + EMAC_INT_CTL_REG); reg_val 659 drivers/net/ethernet/allwinner/sun4i-emac.c unsigned int reg_val; reg_val 694 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_INT_CTL_REG); reg_val 695 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val |= (0xf << 0) | (0x01 << 8); reg_val 696 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val, db->membase + EMAC_INT_CTL_REG); reg_val 748 drivers/net/ethernet/allwinner/sun4i-emac.c unsigned int reg_val; reg_val 755 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_INT_STA_REG); reg_val 756 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val, db->membase + EMAC_INT_STA_REG); reg_val 759 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val = readl(db->membase + EMAC_CTL_REG); reg_val 760 drivers/net/ethernet/allwinner/sun4i-emac.c reg_val &= ~(EMAC_CTL_TX_EN | EMAC_CTL_RX_EN | EMAC_CTL_RESET); reg_val 761 drivers/net/ethernet/allwinner/sun4i-emac.c writel(reg_val, db->membase + EMAC_CTL_REG); reg_val 1028 drivers/net/ethernet/amazon/ena/ena_admin_defs.h u32 reg_val; reg_val 850 drivers/net/ethernet/amazon/ena/ena_com.c ret = read_resp->reg_val; reg_val 103 drivers/net/ethernet/amd/amd8111e.c unsigned int reg_val; reg_val 106 drivers/net/ethernet/amd/amd8111e.c reg_val = readl(mmio + PHY_ACCESS); reg_val 107 drivers/net/ethernet/amd/amd8111e.c while (reg_val & PHY_CMD_ACTIVE) reg_val 108 drivers/net/ethernet/amd/amd8111e.c reg_val = readl( mmio + PHY_ACCESS ); reg_val 113 drivers/net/ethernet/amd/amd8111e.c reg_val = readl(mmio + PHY_ACCESS); reg_val 115 drivers/net/ethernet/amd/amd8111e.c } while (--repeat && (reg_val & PHY_CMD_ACTIVE)); reg_val 116 drivers/net/ethernet/amd/amd8111e.c if(reg_val & PHY_RD_ERR) reg_val 119 drivers/net/ethernet/amd/amd8111e.c *val = reg_val & 0xffff; reg_val 133 drivers/net/ethernet/amd/amd8111e.c unsigned int reg_val; reg_val 135 drivers/net/ethernet/amd/amd8111e.c reg_val = readl(mmio + PHY_ACCESS); reg_val 136 drivers/net/ethernet/amd/amd8111e.c while (reg_val & PHY_CMD_ACTIVE) reg_val 137 drivers/net/ethernet/amd/amd8111e.c reg_val = readl( mmio + PHY_ACCESS ); reg_val 143 drivers/net/ethernet/amd/amd8111e.c reg_val = readl(mmio + PHY_ACCESS); reg_val 145 drivers/net/ethernet/amd/amd8111e.c } while (--repeat && (reg_val & PHY_CMD_ACTIVE)); reg_val 147 drivers/net/ethernet/amd/amd8111e.c if(reg_val & PHY_RD_ERR) reg_val 161 drivers/net/ethernet/amd/amd8111e.c unsigned int reg_val; reg_val 163 drivers/net/ethernet/amd/amd8111e.c amd8111e_read_phy(lp,phy_id,reg_num,®_val); reg_val 164 drivers/net/ethernet/amd/amd8111e.c return reg_val; reg_val 422 drivers/net/ethernet/amd/amd8111e.c int i,reg_val; reg_val 437 drivers/net/ethernet/amd/amd8111e.c reg_val = readl(mmio + CTRL1); reg_val 438 drivers/net/ethernet/amd/amd8111e.c reg_val &= ~XMTSP_MASK; reg_val 439 drivers/net/ethernet/amd/amd8111e.c writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 ); reg_val 497 drivers/net/ethernet/amd/amd8111e.c unsigned int reg_val; reg_val 534 drivers/net/ethernet/amd/amd8111e.c reg_val = readl(mmio + INT0); reg_val 535 drivers/net/ethernet/amd/amd8111e.c writel(reg_val, mmio + INT0); reg_val 568 drivers/net/ethernet/amd/amd8111e.c reg_val = readl(mmio + SRAM_SIZE); reg_val 1453 drivers/net/ethernet/amd/xgbe/xgbe-common.h u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \ reg_val 1454 drivers/net/ethernet/amd/xgbe/xgbe-common.h SET_BITS(reg_val, \ reg_val 1457 drivers/net/ethernet/amd/xgbe/xgbe-common.h XGMAC_IOWRITE((_pdata), _reg, reg_val); \ reg_val 1479 drivers/net/ethernet/amd/xgbe/xgbe-common.h u32 reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \ reg_val 1480 drivers/net/ethernet/amd/xgbe/xgbe-common.h SET_BITS(reg_val, \ reg_val 1483 drivers/net/ethernet/amd/xgbe/xgbe-common.h XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \ reg_val 1503 drivers/net/ethernet/amd/xgbe/xgbe-common.h u32 reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \ reg_val 1504 drivers/net/ethernet/amd/xgbe/xgbe-common.h SET_BITS(reg_val, \ reg_val 1507 drivers/net/ethernet/amd/xgbe/xgbe-common.h XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \ reg_val 1561 drivers/net/ethernet/amd/xgbe/xgbe-common.h u16 reg_val = XSIR0_IOREAD((_pdata), _reg); \ reg_val 1562 drivers/net/ethernet/amd/xgbe/xgbe-common.h SET_BITS(reg_val, \ reg_val 1565 drivers/net/ethernet/amd/xgbe/xgbe-common.h XSIR0_IOWRITE((_pdata), _reg, reg_val); \ reg_val 1581 drivers/net/ethernet/amd/xgbe/xgbe-common.h u16 reg_val = XSIR1_IOREAD((_pdata), _reg); \ reg_val 1582 drivers/net/ethernet/amd/xgbe/xgbe-common.h SET_BITS(reg_val, \ reg_val 1585 drivers/net/ethernet/amd/xgbe/xgbe-common.h XSIR1_IOWRITE((_pdata), _reg, reg_val); \ reg_val 1604 drivers/net/ethernet/amd/xgbe/xgbe-common.h u16 reg_val = XRXTX_IOREAD((_pdata), _reg); \ reg_val 1605 drivers/net/ethernet/amd/xgbe/xgbe-common.h SET_BITS(reg_val, \ reg_val 1608 drivers/net/ethernet/amd/xgbe/xgbe-common.h XRXTX_IOWRITE((_pdata), _reg, reg_val); \ reg_val 1637 drivers/net/ethernet/amd/xgbe/xgbe-common.h u32 reg_val = XP_IOREAD((_pdata), (_reg)); \ reg_val 1638 drivers/net/ethernet/amd/xgbe/xgbe-common.h SET_BITS(reg_val, \ reg_val 1641 drivers/net/ethernet/amd/xgbe/xgbe-common.h XP_IOWRITE((_pdata), (_reg), reg_val); \ reg_val 1670 drivers/net/ethernet/amd/xgbe/xgbe-common.h u32 reg_val = XI2C_IOREAD((_pdata), (_reg)); \ reg_val 1671 drivers/net/ethernet/amd/xgbe/xgbe-common.h SET_BITS(reg_val, \ reg_val 1674 drivers/net/ethernet/amd/xgbe/xgbe-common.h XI2C_IOWRITE((_pdata), (_reg), reg_val); \ reg_val 530 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int reg, reg_val; reg_val 542 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val = XGMAC_IOREAD(pdata, reg); reg_val 543 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0); reg_val 544 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_IOWRITE(pdata, reg, reg_val); reg_val 557 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int reg, reg_val; reg_val 586 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val = XGMAC_IOREAD(pdata, reg); reg_val 589 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1); reg_val 591 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff); reg_val 593 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_IOWRITE(pdata, reg, reg_val); reg_val 1351 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R); reg_val 1357 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val |= (1 << port); reg_val 1365 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val); reg_val 2606 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int i, j, reg, reg_val; reg_val 2638 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val = 0; reg_val 2655 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); reg_val 2660 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_IOWRITE(pdata, reg, reg_val); reg_val 2662 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val = 0; reg_val 2667 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val = 0; reg_val 2669 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3)); reg_val 2674 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_IOWRITE(pdata, reg, reg_val); reg_val 2677 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val = 0; reg_val 2715 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int mask, reg, reg_val; reg_val 2744 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val = XGMAC_IOREAD(pdata, reg); reg_val 2746 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val &= ~(0xff << ((i % MTL_TCPM_TC_PER_REG) << 3)); reg_val 2747 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val |= (mask << ((i % MTL_TCPM_TC_PER_REG) << 3)); reg_val 2749 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_IOWRITE(pdata, reg, reg_val); reg_val 3355 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int reg_val, i; reg_val 3366 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val = 0; reg_val 3368 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val |= (0x02 << (i << 1)); reg_val 3369 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); reg_val 679 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h u32 reg_val; reg_val 682 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h reg_val = REG_RD(bp, mcp_attn_ctl_regs[i].addr); reg_val 685 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h reg_val |= mcp_attn_ctl_regs[i].bits; reg_val 687 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h reg_val &= ~mcp_attn_ctl_regs[i].bits; reg_val 689 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h REG_WR(bp, mcp_attn_ctl_regs[i].addr, reg_val); reg_val 729 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h u32 reg_val, mcp_aeu_bits = reg_val 745 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i]. reg_val 747 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h if (reg_val & reg_mask) reg_val 751 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h reg_val & reg_mask); reg_val 756 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP); reg_val 757 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h if (reg_val & mcp_aeu_bits) reg_val 759 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h reg_val & mcp_aeu_bits); reg_val 5033 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 reg_val; reg_val 5038 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); reg_val 5042 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; reg_val 5044 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | reg_val 5049 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); reg_val 5055 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); reg_val 5056 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | reg_val 5058 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; reg_val 5060 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; reg_val 5062 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; reg_val 5066 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); reg_val 5072 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c ®_val); reg_val 5075 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | reg_val 5079 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | reg_val 5085 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val); reg_val 5106 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c ®_val); reg_val 5109 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; reg_val 5112 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; reg_val 5117 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val); reg_val 5120 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; reg_val 5123 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val = 0; reg_val 5127 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); reg_val 5136 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 reg_val; reg_val 5141 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); reg_val 5142 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | reg_val 5146 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; reg_val 5149 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); reg_val 5156 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_SERDES_DIGITAL_MISC1, ®_val); reg_val 5158 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); reg_val 5160 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | reg_val 5167 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | reg_val 5170 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_val |= reg_val 5176 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_SERDES_DIGITAL_MISC1, reg_val); reg_val 425 drivers/net/ethernet/cadence/macb_ptp.c u32 reg_val; reg_val 427 drivers/net/ethernet/cadence/macb_ptp.c reg_val = macb_readl(bp, NCR); reg_val 430 drivers/net/ethernet/cadence/macb_ptp.c macb_writel(bp, NCR, reg_val | MACB_BIT(OSSMODE)); reg_val 432 drivers/net/ethernet/cadence/macb_ptp.c macb_writel(bp, NCR, reg_val & ~MACB_BIT(OSSMODE)); reg_val 305 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c u64 reg_val; reg_val 314 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = reg_val 319 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = pf_num * CN23XX_MAX_RINGS_PER_PF_PASS_1_1; reg_val 322 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = pf_num * CN23XX_MAX_RINGS_PER_PF; reg_val 326 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = reg_val | reg_val 330 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val |= (temp << CN23XX_PKT_MAC_CTL_RINFO_RPVF_BIT_POS); reg_val 334 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val |= (temp << CN23XX_PKT_MAC_CTL_RINFO_NVFS_BIT_POS); reg_val 338 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val); reg_val 368 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c u64 reg_val = octeon_read_csr64(oct, reg_val 370 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) && reg_val 371 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c !(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) && reg_val 373 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c WRITE_ONCE(reg_val, octeon_read_csr64( reg_val 382 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c WRITE_ONCE(reg_val, READ_ONCE(reg_val) & reg_val 385 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c READ_ONCE(reg_val)); reg_val 387 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c WRITE_ONCE(reg_val, octeon_read_csr64( reg_val 389 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) { reg_val 404 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c u64 intr_threshold, reg_val; reg_val 423 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = oct->pcie_port << CN23XX_PKT_INPUT_CTL_MAC_NUM_POS; reg_val 433 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val |= vf_num << CN23XX_PKT_INPUT_CTL_VF_NUM_POS; reg_val 434 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val |= pf_num << CN23XX_PKT_INPUT_CTL_PF_NUM_POS; reg_val 437 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val); reg_val 453 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = reg_val 456 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val |= CN23XX_PKT_INPUT_CTL_MASK; reg_val 459 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val); reg_val 477 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c u32 reg_val; reg_val 494 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no)); reg_val 497 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val &= ~CN23XX_PKT_OUTPUT_CTL_IPTR; reg_val 500 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val |= CN23XX_PKT_OUTPUT_CTL_DPTR; reg_val 503 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE); reg_val 509 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P); reg_val 510 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P); reg_val 513 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P); reg_val 515 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P); reg_val 521 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR); reg_val 522 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR); reg_val 524 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES); reg_val 527 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no), reg_val); reg_val 630 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c u32 reg_val; reg_val 654 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = reg_val 656 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val |= CN23XX_PKT_OUTPUT_CTL_TENB; reg_val 658 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val); reg_val 662 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = reg_val 664 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val |= CN23XX_PKT_OUTPUT_CTL_CENB; reg_val 666 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val); reg_val 792 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c u64 reg_val; reg_val 802 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = octeon_read_csr64( reg_val 804 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = reg_val | CN23XX_PKT_INPUT_CTL_IS_64B; reg_val 806 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), reg_val); reg_val 814 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = octeon_read_csr64( reg_val 817 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c if (reg_val & CN23XX_PKT_INPUT_CTL_RST) { reg_val 818 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) && reg_val 819 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c !(reg_val & reg_val 822 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = octeon_read_csr64( reg_val 832 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST; reg_val 835 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val); reg_val 837 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = octeon_read_csr64( reg_val 839 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c if (reg_val & CN23XX_PKT_INPUT_CTL_RST) { reg_val 846 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = octeon_read_csr64( reg_val 848 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = reg_val | CN23XX_PKT_INPUT_CTL_RING_ENB; reg_val 850 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), reg_val); reg_val 854 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c u32 reg_val; reg_val 857 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = octeon_read_csr( reg_val 859 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val = reg_val | CN23XX_PKT_OUTPUT_CTL_RING_ENB; reg_val 861 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c reg_val); reg_val 68 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c u64 reg_val = octeon_read_csr64(oct, reg_val 70 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) && reg_val 71 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c !(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) && reg_val 73 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c WRITE_ONCE(reg_val, octeon_read_csr64( reg_val 83 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c WRITE_ONCE(reg_val, READ_ONCE(reg_val) & reg_val 86 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c READ_ONCE(reg_val)); reg_val 88 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c WRITE_ONCE(reg_val, octeon_read_csr64( reg_val 90 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) { reg_val 153 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c u32 reg_val; reg_val 160 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val = reg_val 163 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val &= 0xEFFFFFFFFFFFFFFFL; reg_val 165 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val = reg_val 169 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val &= ~CN23XX_PKT_OUTPUT_CTL_IPTR; reg_val 172 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val |= CN23XX_PKT_OUTPUT_CTL_DPTR; reg_val 175 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE); reg_val 180 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P); reg_val 181 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P); reg_val 184 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P); reg_val 186 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P); reg_val 191 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR); reg_val 192 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR); reg_val 194 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES); reg_val 198 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val); reg_val 323 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c u64 reg_val; reg_val 327 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val = octeon_read_csr64( reg_val 329 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val |= CN23XX_PKT_INPUT_CTL_IS_64B; reg_val 331 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), reg_val); reg_val 336 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val = octeon_read_csr64( reg_val 338 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val |= CN23XX_PKT_INPUT_CTL_RING_ENB; reg_val 340 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), reg_val); reg_val 344 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c u32 reg_val; reg_val 348 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val = octeon_read_csr( reg_val 350 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val |= CN23XX_PKT_OUTPUT_CTL_RING_ENB; reg_val 352 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no), reg_val); reg_val 620 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c u64 reg_val; reg_val 626 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val = octeon_read_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(0)); reg_val 628 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c oct->pf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_PF_NUM_POS) & reg_val 630 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c oct->vf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_VF_NUM_POS) & reg_val 633 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c reg_val = reg_val >> CN23XX_PKT_INPUT_CTL_RPVF_POS; reg_val 635 drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c rings_per_vf = reg_val & CN23XX_PKT_INPUT_CTL_RPVF_MASK; reg_val 523 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c u64 reg_val = 0ULL; reg_val 526 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg_val = octeon_read_csr64(oct, ctrl); reg_val 527 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg_val = reg_val >> CN23XX_PKT_INPUT_CTL_RPVF_POS; reg_val 528 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c max_combined = reg_val & CN23XX_PKT_INPUT_CTL_RPVF_MASK; reg_val 633 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c u64 reg_val = 0ULL; reg_val 636 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg_val = octeon_read_csr64(oct, ctrl); reg_val 637 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg_val = reg_val >> CN23XX_PKT_INPUT_CTL_RPVF_POS; reg_val 638 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c max_combined = reg_val & CN23XX_PKT_INPUT_CTL_RPVF_MASK; reg_val 960 drivers/net/ethernet/cavium/liquidio/octeon_device.c u64 reg_val = octeon_read_csr64( reg_val 963 drivers/net/ethernet/cavium/liquidio/octeon_device.c while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) && reg_val 964 drivers/net/ethernet/cavium/liquidio/octeon_device.c !(reg_val & CN23XX_PKT_INPUT_CTL_QUIET) && reg_val 966 drivers/net/ethernet/cavium/liquidio/octeon_device.c reg_val = octeon_read_csr64( reg_val 977 drivers/net/ethernet/cavium/liquidio/octeon_device.c reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST; reg_val 980 drivers/net/ethernet/cavium/liquidio/octeon_device.c reg_val); reg_val 982 drivers/net/ethernet/cavium/liquidio/octeon_device.c reg_val = octeon_read_csr64( reg_val 984 drivers/net/ethernet/cavium/liquidio/octeon_device.c if (reg_val & CN23XX_PKT_INPUT_CTL_RST) { reg_val 998 drivers/net/ethernet/cavium/liquidio/octeon_device.c u32 reg_val = 0; reg_val 1002 drivers/net/ethernet/cavium/liquidio/octeon_device.c reg_val = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); reg_val 1005 drivers/net/ethernet/cavium/liquidio/octeon_device.c reg_val = reg_val | (1 << q_no); reg_val 1007 drivers/net/ethernet/cavium/liquidio/octeon_device.c reg_val = reg_val & (~(1 << q_no)); reg_val 1009 drivers/net/ethernet/cavium/liquidio/octeon_device.c octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, reg_val); reg_val 35 drivers/net/ethernet/cavium/thunder/nicvf_queues.c u64 reg_val; reg_val 42 drivers/net/ethernet/cavium/thunder/nicvf_queues.c reg_val = nicvf_queue_reg_read(nic, reg, qidx); reg_val 43 drivers/net/ethernet/cavium/thunder/nicvf_queues.c if (((reg_val & bit_mask) >> bit_pos) == val) reg_val 1724 drivers/net/ethernet/cavium/thunder/nicvf_queues.c u64 reg_val; reg_val 1728 drivers/net/ethernet/cavium/thunder/nicvf_queues.c reg_val = ((1ULL << q_idx) << NICVF_INTR_CQ_SHIFT); reg_val 1731 drivers/net/ethernet/cavium/thunder/nicvf_queues.c reg_val = ((1ULL << q_idx) << NICVF_INTR_SQ_SHIFT); reg_val 1734 drivers/net/ethernet/cavium/thunder/nicvf_queues.c reg_val = ((1ULL << q_idx) << NICVF_INTR_RBDR_SHIFT); reg_val 1737 drivers/net/ethernet/cavium/thunder/nicvf_queues.c reg_val = (1ULL << NICVF_INTR_PKT_DROP_SHIFT); reg_val 1740 drivers/net/ethernet/cavium/thunder/nicvf_queues.c reg_val = (1ULL << NICVF_INTR_TCP_TIMER_SHIFT); reg_val 1743 drivers/net/ethernet/cavium/thunder/nicvf_queues.c reg_val = (1ULL << NICVF_INTR_MBOX_SHIFT); reg_val 1746 drivers/net/ethernet/cavium/thunder/nicvf_queues.c reg_val = (1ULL << NICVF_INTR_QS_ERR_SHIFT); reg_val 1749 drivers/net/ethernet/cavium/thunder/nicvf_queues.c reg_val = 0; reg_val 1752 drivers/net/ethernet/cavium/thunder/nicvf_queues.c return reg_val; reg_val 131 drivers/net/ethernet/cavium/thunder/thunder_bgx.c u64 reg_val; reg_val 134 drivers/net/ethernet/cavium/thunder/thunder_bgx.c reg_val = bgx_reg_read(bgx, lmac, reg); reg_val 135 drivers/net/ethernet/cavium/thunder/thunder_bgx.c if (zero && !(reg_val & mask)) reg_val 137 drivers/net/ethernet/cavium/thunder/thunder_bgx.c if (!zero && (reg_val & mask)) reg_val 84 drivers/net/ethernet/chelsio/cxgb3/ael1002.c static int set_phy_regs(struct cphy *phy, const struct reg_val *rv) reg_val 295 drivers/net/ethernet/chelsio/cxgb3/ael1002.c static const struct reg_val regs[] = { reg_val 327 drivers/net/ethernet/chelsio/cxgb3/ael1002.c static const struct reg_val regs[] = { reg_val 331 drivers/net/ethernet/chelsio/cxgb3/ael1002.c static const struct reg_val preemphasis[] = { reg_val 396 drivers/net/ethernet/chelsio/cxgb3/ael1002.c static const struct reg_val regs0[] = { reg_val 406 drivers/net/ethernet/chelsio/cxgb3/ael1002.c static const struct reg_val regs1[] = { reg_val 525 drivers/net/ethernet/chelsio/cxgb3/ael1002.c static const struct reg_val regs[] = { reg_val 554 drivers/net/ethernet/chelsio/cxgb3/ael1002.c static const struct reg_val uCclock40MHz[] = { reg_val 561 drivers/net/ethernet/chelsio/cxgb3/ael1002.c static const struct reg_val uCclockActivate[] = { reg_val 567 drivers/net/ethernet/chelsio/cxgb3/ael1002.c static const struct reg_val uCactivate[] = { reg_val 627 drivers/net/ethernet/chelsio/cxgb3/ael1002.c static const struct reg_val regs[] = { reg_val 667 drivers/net/ethernet/chelsio/cxgb3/ael1002.c static const struct reg_val regs[] = { reg_val 704 drivers/net/ethernet/chelsio/cxgb3/ael1002.c static const struct reg_val ael2020_reset_regs[] = { reg_val 4763 drivers/net/ethernet/emulex/benet/be_cmds.c u32 reg_val; reg_val 4767 drivers/net/ethernet/emulex/benet/be_cmds.c reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET); reg_val 4768 drivers/net/ethernet/emulex/benet/be_cmds.c if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0) reg_val 305 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c u32 reg_val = 0; reg_val 311 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c reg_val |= RESET_REQ_OR_DREQ; reg_val 312 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c reg_val |= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off; reg_val 319 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c dsaf_write_sub(dsaf_dev, reg_addr, reg_val); reg_val 454 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c u32 reg_val = 0; reg_val 457 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c reg_val |= RESET_REQ_OR_DREQ << dsaf_dev->mac_cb[port]->port_rst_off; reg_val 464 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c dsaf_write_sub(dsaf_dev, reg_addr, reg_val); reg_val 476 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c u32 reg_val; reg_val 483 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c reg_val = RESET_REQ_OR_DREQ; reg_val 490 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c reg_val = 0x100 << dsaf_dev->reset_offset; reg_val 498 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c dsaf_write_sub(dsaf_dev, reg_addr, reg_val); reg_val 373 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c u32 reg_val; reg_val 379 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c reg_val = dsaf_read_dev(rcb_common, RCB_COM_CFG_INIT_FLAG_REG); reg_val 380 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c if (0x1 != (reg_val & 0x1)) { reg_val 382 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c "RCB_COM_CFG_INIT_FLAG_REG reg = 0x%x\n", reg_val); reg_val 106 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c u32 reg_val; reg_val 113 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c reg_val = hclge_read_dev(hw, HCLGE_NIC_CSQ_DEPTH_REG); reg_val 114 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c reg_val &= HCLGE_NIC_SW_RST_RDY; reg_val 115 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c reg_val |= ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S; reg_val 116 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c hclge_write_dev(hw, HCLGE_NIC_CSQ_DEPTH_REG, reg_val); reg_val 3317 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c u32 reg_val; reg_val 3319 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); reg_val 3320 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { reg_val 3322 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); reg_val 3323 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); reg_val 3326 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { reg_val 3328 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); reg_val 3329 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); reg_val 3486 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c u32 reg_val; reg_val 3488 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg_val = hclge_read_dev(&hdev->hw, HCLGE_NIC_CSQ_DEPTH_REG); reg_val 3490 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg_val |= HCLGE_NIC_SW_RST_RDY; reg_val 3492 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg_val &= ~HCLGE_NIC_SW_RST_RDY; reg_val 3494 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c hclge_write_dev(&hdev->hw, HCLGE_NIC_CSQ_DEPTH_REG, reg_val); reg_val 3499 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c u32 reg_val; reg_val 3540 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); reg_val 3542 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); reg_val 9653 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c u32 *reg_val = data; reg_val 9688 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *reg_val++ = le32_to_cpu(*desc_data++); reg_val 9707 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c u64 *reg_val = data; reg_val 9742 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *reg_val++ = le64_to_cpu(*desc_data++); reg_val 92 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c u32 reg_val; reg_val 95 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c reg_val = (u32)ring->desc_dma_addr; reg_val 96 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_L_REG, reg_val); reg_val 97 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c reg_val = (u32)((ring->desc_dma_addr >> 31) >> 1); reg_val 98 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_H_REG, reg_val); reg_val 100 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c reg_val = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_DEPTH_REG); reg_val 101 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c reg_val &= HCLGEVF_NIC_SW_RST_RDY; reg_val 102 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c reg_val |= (ring->desc_num >> HCLGEVF_NIC_CMQ_DESC_NUM_S); reg_val 103 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_DEPTH_REG, reg_val); reg_val 108 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c reg_val = (u32)ring->desc_dma_addr; reg_val 109 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_L_REG, reg_val); reg_val 110 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c reg_val = (u32)((ring->desc_dma_addr >> 31) >> 1); reg_val 111 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_H_REG, reg_val); reg_val 113 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c reg_val = (ring->desc_num >> HCLGEVF_NIC_CMQ_DESC_NUM_S); reg_val 114 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_DEPTH_REG, reg_val); reg_val 1442 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c u32 reg_val; reg_val 1444 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG); reg_val 1446 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c reg_val |= HCLGEVF_NIC_SW_RST_RDY; reg_val 1448 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c reg_val &= ~HCLGEVF_NIC_SW_RST_RDY; reg_val 1451 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c reg_val); reg_val 283 drivers/net/ethernet/hisilicon/hns_mdio.c u16 reg_val = 0; reg_val 331 drivers/net/ethernet/hisilicon/hns_mdio.c reg_val = MDIO_GET_REG_BIT(mdio_dev, MDIO_STA_REG, MDIO_STATE_STA_B); reg_val 332 drivers/net/ethernet/hisilicon/hns_mdio.c if (reg_val) { reg_val 338 drivers/net/ethernet/hisilicon/hns_mdio.c reg_val = (u16)MDIO_GET_REG_FIELD(mdio_dev, MDIO_RDATA_REG, reg_val 341 drivers/net/ethernet/hisilicon/hns_mdio.c return reg_val; reg_val 3002 drivers/net/ethernet/intel/e1000e/netdev.c u32 reg_val; reg_val 3004 drivers/net/ethernet/intel/e1000e/netdev.c reg_val = er32(IOSFPC); reg_val 3005 drivers/net/ethernet/intel/e1000e/netdev.c reg_val |= E1000_RCTL_RDMTS_HEX; reg_val 3006 drivers/net/ethernet/intel/e1000e/netdev.c ew32(IOSFPC, reg_val); reg_val 3008 drivers/net/ethernet/intel/e1000e/netdev.c reg_val = er32(TARC(0)); reg_val 3013 drivers/net/ethernet/intel/e1000e/netdev.c reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ; reg_val 3014 drivers/net/ethernet/intel/e1000e/netdev.c reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ; reg_val 3015 drivers/net/ethernet/intel/e1000e/netdev.c ew32(TARC(0), reg_val); reg_val 1060 drivers/net/ethernet/intel/i40e/i40e_common.c u32 reg_val; reg_val 1067 drivers/net/ethernet/intel/i40e/i40e_common.c reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); reg_val 1068 drivers/net/ethernet/intel/i40e/i40e_common.c reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; reg_val 1069 drivers/net/ethernet/intel/i40e/i40e_common.c reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); reg_val 1072 drivers/net/ethernet/intel/i40e/i40e_common.c reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; reg_val 1074 drivers/net/ethernet/intel/i40e/i40e_common.c reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; reg_val 1076 drivers/net/ethernet/intel/i40e/i40e_common.c wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); reg_val 2974 drivers/net/ethernet/intel/i40e/i40e_common.c u32 reg_addr, u64 *reg_val, reg_val 2982 drivers/net/ethernet/intel/i40e/i40e_common.c if (reg_val == NULL) reg_val 2992 drivers/net/ethernet/intel/i40e/i40e_common.c *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) | reg_val 3009 drivers/net/ethernet/intel/i40e/i40e_common.c u32 reg_addr, u64 reg_val, reg_val 3020 drivers/net/ethernet/intel/i40e/i40e_common.c cmd->value_high = cpu_to_le32((u32)(reg_val >> 32)); reg_val 3021 drivers/net/ethernet/intel/i40e/i40e_common.c cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF)); reg_val 4956 drivers/net/ethernet/intel/i40e/i40e_common.c u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); reg_val 4958 drivers/net/ethernet/intel/i40e/i40e_common.c return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; reg_val 5042 drivers/net/ethernet/intel/i40e/i40e_common.c u32 *reg_val) reg_val 5049 drivers/net/ethernet/intel/i40e/i40e_common.c *reg_val = 0; reg_val 5056 drivers/net/ethernet/intel/i40e/i40e_common.c reg_val, NULL); reg_val 5064 drivers/net/ethernet/intel/i40e/i40e_common.c (u16 *)reg_val); reg_val 5076 drivers/net/ethernet/intel/i40e/i40e_common.c u32 reg_val) reg_val 5089 drivers/net/ethernet/intel/i40e/i40e_common.c reg_val, NULL); reg_val 5097 drivers/net/ethernet/intel/i40e/i40e_common.c (u16)reg_val); reg_val 5116 drivers/net/ethernet/intel/i40e/i40e_common.c u16 reg_val; reg_val 5143 drivers/net/ethernet/intel/i40e/i40e_common.c ®_val); reg_val 5146 drivers/net/ethernet/intel/i40e/i40e_common.c *val = reg_val; reg_val 5147 drivers/net/ethernet/intel/i40e/i40e_common.c if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { reg_val 5215 drivers/net/ethernet/intel/i40e/i40e_common.c u32 reg_addr, u32 *reg_val, reg_val 5223 drivers/net/ethernet/intel/i40e/i40e_common.c if (!reg_val) reg_val 5233 drivers/net/ethernet/intel/i40e/i40e_common.c *reg_val = le32_to_cpu(cmd_resp->value); reg_val 5281 drivers/net/ethernet/intel/i40e/i40e_common.c u32 reg_addr, u32 reg_val, reg_val 5292 drivers/net/ethernet/intel/i40e/i40e_common.c cmd->value = cpu_to_le32(reg_val); reg_val 5305 drivers/net/ethernet/intel/i40e/i40e_common.c void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) reg_val 5317 drivers/net/ethernet/intel/i40e/i40e_common.c reg_val, NULL); reg_val 5327 drivers/net/ethernet/intel/i40e/i40e_common.c wr32(hw, reg_addr, reg_val); reg_val 5343 drivers/net/ethernet/intel/i40e/i40e_common.c u32 reg_addr, u32 reg_val, reg_val 5357 drivers/net/ethernet/intel/i40e/i40e_common.c cmd->reg_value = cpu_to_le32(reg_val); reg_val 5377 drivers/net/ethernet/intel/i40e/i40e_common.c u32 reg_addr, u32 *reg_val, reg_val 5394 drivers/net/ethernet/intel/i40e/i40e_common.c *reg_val = le32_to_cpu(cmd->reg_value); reg_val 120 drivers/net/ethernet/intel/i40e/i40e_diag.c u16 reg_val; reg_val 123 drivers/net/ethernet/intel/i40e/i40e_diag.c ret_code = i40e_read_nvm_word(hw, I40E_SR_NVM_CONTROL_WORD, ®_val); reg_val 125 drivers/net/ethernet/intel/i40e/i40e_diag.c ((reg_val & I40E_SR_CONTROL_WORD_1_MASK) == reg_val 11607 drivers/net/ethernet/intel/i40e/i40e_main.c u32 reg_val; reg_val 11620 drivers/net/ethernet/intel/i40e/i40e_main.c reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); reg_val 11621 drivers/net/ethernet/intel/i40e/i40e_main.c reg_val = (pf->rss_table_size == 512) ? reg_val 11622 drivers/net/ethernet/intel/i40e/i40e_main.c (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) : reg_val 11623 drivers/net/ethernet/intel/i40e/i40e_main.c (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512); reg_val 11624 drivers/net/ethernet/intel/i40e/i40e_main.c i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val); reg_val 69 drivers/net/ethernet/intel/i40e/i40e_prototype.h u32 reg_addr, u64 reg_val, reg_val 72 drivers/net/ethernet/intel/i40e/i40e_prototype.h u32 reg_addr, u64 *reg_val, reg_val 405 drivers/net/ethernet/intel/i40e/i40e_prototype.h u32 reg_addr, u32 *reg_val, reg_val 409 drivers/net/ethernet/intel/i40e/i40e_prototype.h u32 reg_addr, u32 reg_val, reg_val 411 drivers/net/ethernet/intel/i40e/i40e_prototype.h void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val); reg_val 414 drivers/net/ethernet/intel/i40e/i40e_prototype.h u32 reg_addr, u32 reg_val, reg_val 418 drivers/net/ethernet/intel/i40e/i40e_prototype.h u32 reg_addr, u32 *reg_val, reg_val 1897 drivers/net/ethernet/intel/iavf/iavf_main.c u32 reg_val; reg_val 1907 drivers/net/ethernet/intel/iavf/iavf_main.c reg_val = rd32(hw, IAVF_VFGEN_RSTAT) & reg_val 1909 drivers/net/ethernet/intel/iavf/iavf_main.c if (reg_val == VIRTCHNL_VFR_VFACTIVE || reg_val 1910 drivers/net/ethernet/intel/iavf/iavf_main.c reg_val == VIRTCHNL_VFR_COMPLETED) { reg_val 1962 drivers/net/ethernet/intel/iavf/iavf_main.c reg_val = rd32(hw, IAVF_VF_ARQLEN1) & IAVF_VF_ARQLEN1_ARQENABLE_MASK; reg_val 1963 drivers/net/ethernet/intel/iavf/iavf_main.c if (!reg_val) { reg_val 2070 drivers/net/ethernet/intel/iavf/iavf_main.c u32 reg_val; reg_val 2105 drivers/net/ethernet/intel/iavf/iavf_main.c reg_val = rd32(hw, IAVF_VF_ARQLEN1) & reg_val 2107 drivers/net/ethernet/intel/iavf/iavf_main.c if (!reg_val) reg_val 2121 drivers/net/ethernet/intel/iavf/iavf_main.c reg_val = rd32(hw, IAVF_VFGEN_RSTAT) & reg_val 2123 drivers/net/ethernet/intel/iavf/iavf_main.c if (reg_val == VIRTCHNL_VFR_VFACTIVE) reg_val 2131 drivers/net/ethernet/intel/iavf/iavf_main.c reg_val); reg_val 2072 drivers/net/ethernet/intel/igb/e1000_82575.c u32 reg_val, reg_offset; reg_val 2086 drivers/net/ethernet/intel/igb/e1000_82575.c reg_val = rd32(reg_offset); reg_val 2088 drivers/net/ethernet/intel/igb/e1000_82575.c reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK | reg_val 2093 drivers/net/ethernet/intel/igb/e1000_82575.c reg_val ^= (BIT(pf) | BIT(pf + MAX_NUM_VFS)); reg_val 2095 drivers/net/ethernet/intel/igb/e1000_82575.c reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | reg_val 2098 drivers/net/ethernet/intel/igb/e1000_82575.c wr32(reg_offset, reg_val); reg_val 828 drivers/net/ethernet/intel/igb/e1000_i210.c u32 wuc, mdicnfg, ctrl, ctrl_ext, reg_val; reg_val 835 drivers/net/ethernet/intel/igb/e1000_i210.c reg_val = mdicnfg & ~E1000_MDICNFG_EXT_MDIO; reg_val 836 drivers/net/ethernet/intel/igb/e1000_i210.c wr32(E1000_MDICNFG, reg_val); reg_val 865 drivers/net/ethernet/intel/igb/e1000_i210.c reg_val = (E1000_INVM_AUTOLOAD << 4) | (tmp_nvm << 16); reg_val 866 drivers/net/ethernet/intel/igb/e1000_i210.c wr32(E1000_EEARBC_I210, reg_val); reg_val 874 drivers/net/ethernet/intel/igb/e1000_i210.c reg_val = (E1000_INVM_AUTOLOAD << 4) | (nvm_word << 16); reg_val 875 drivers/net/ethernet/intel/igb/e1000_i210.c wr32(E1000_EEARBC_I210, reg_val); reg_val 9285 drivers/net/ethernet/intel/igb/igb_main.c u32 reg_val, reg_offset; reg_val 9294 drivers/net/ethernet/intel/igb/igb_main.c reg_val = rd32(reg_offset); reg_val 9296 drivers/net/ethernet/intel/igb/igb_main.c reg_val |= (BIT(vf) | reg_val 9299 drivers/net/ethernet/intel/igb/igb_main.c reg_val &= ~(BIT(vf) | reg_val 9301 drivers/net/ethernet/intel/igb/igb_main.c wr32(reg_offset, reg_val); reg_val 177 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c u32 *reg_val) reg_val 192 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); reg_val 714 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c u32 reg_val; reg_val 738 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); reg_val 739 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c reg_val &= ~IXGBE_RXDCTL_ENABLE; reg_val 740 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c reg_val |= IXGBE_RXDCTL_SWFLSH; reg_val 741 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); reg_val 2657 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) reg_val 2660 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); reg_val 2671 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) reg_val 2673 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); reg_val 80 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val); reg_val 81 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked); reg_val 701 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c u32 reg_val; reg_val 749 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg_val = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(reg_idx)); reg_val 752 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c if (reg_val) { reg_val 753 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg_val |= IXGBE_TXDCTL_ENABLE; reg_val 754 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(reg_idx), reg_val); reg_val 755 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg_val &= ~IXGBE_TXDCTL_ENABLE; reg_val 756 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(reg_idx), reg_val); reg_val 1435 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u32 reg_val; reg_val 1440 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); reg_val 1444 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; reg_val 1447 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); reg_val 1454 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); reg_val 1458 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; reg_val 1459 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; reg_val 1460 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; reg_val 1463 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); reg_val 1469 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); reg_val 1473 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; reg_val 1474 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; reg_val 1475 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; reg_val 1478 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); reg_val 1485 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); reg_val 1489 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; reg_val 1490 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; reg_val 1491 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; reg_val 1492 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; reg_val 1495 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); reg_val 1557 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u32 reg_val; reg_val 1566 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); reg_val 1570 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; reg_val 1571 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; reg_val 1576 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; reg_val 1579 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; reg_val 1588 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); reg_val 1653 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u16 reg_slice, reg_val; reg_val 1675 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; reg_val 1677 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; reg_val 1680 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val); reg_val 1697 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u32 reg_val; reg_val 1702 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); reg_val 1706 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; reg_val 1707 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; reg_val 1708 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; reg_val 1709 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; reg_val 1714 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G; reg_val 1717 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; reg_val 1726 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); reg_val 2534 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u32 reg_val; reg_val 2538 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); reg_val 2542 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; reg_val 2543 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | reg_val 2548 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; reg_val 2552 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; reg_val 2556 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); reg_val 2562 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); reg_val 2567 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; reg_val 2568 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; reg_val 2569 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; reg_val 2570 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; reg_val 2571 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; reg_val 2575 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); reg_val 2854 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u32 reg_val; reg_val 2905 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c ®_val); reg_val 2909 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | reg_val 2912 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; reg_val 2914 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; reg_val 2918 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg_val); reg_val 157 drivers/net/ethernet/intel/ixgbevf/vf.c u32 reg_val; reg_val 168 drivers/net/ethernet/intel/ixgbevf/vf.c reg_val = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i)); reg_val 169 drivers/net/ethernet/intel/ixgbevf/vf.c if (reg_val & IXGBE_RXDCTL_ENABLE) { reg_val 170 drivers/net/ethernet/intel/ixgbevf/vf.c reg_val &= ~IXGBE_RXDCTL_ENABLE; reg_val 171 drivers/net/ethernet/intel/ixgbevf/vf.c IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val); reg_val 186 drivers/net/ethernet/intel/ixgbevf/vf.c reg_val = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i)); reg_val 187 drivers/net/ethernet/intel/ixgbevf/vf.c if (reg_val & IXGBE_TXDCTL_ENABLE) { reg_val 188 drivers/net/ethernet/intel/ixgbevf/vf.c reg_val &= ~IXGBE_TXDCTL_ENABLE; reg_val 189 drivers/net/ethernet/intel/ixgbevf/vf.c IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), reg_val); reg_val 1945 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c unsigned int mask = 0xfff, reg_val, shift; reg_val 1955 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c reg_val = mvpp2_read(priv, MVPP2_MH_REG(port->id)); reg_val 1956 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c if (reg_val & MVPP2_DSA_EXTENDED) reg_val 2053 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c unsigned int reg_val, shift; reg_val 2063 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c reg_val = mvpp2_read(priv, MVPP2_MH_REG(port->id)); reg_val 2064 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c if (reg_val & MVPP2_DSA_EXTENDED) reg_val 66 drivers/net/ethernet/marvell/octeontx2/af/rvu.c u64 reg_val; reg_val 70 drivers/net/ethernet/marvell/octeontx2/af/rvu.c reg_val = readq(reg); reg_val 71 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (zero && !(reg_val & mask)) reg_val 73 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (!zero && (reg_val & mask)) reg_val 1828 drivers/net/ethernet/mediatek/mtk_eth_soc.c u32 reg_val; reg_val 1830 drivers/net/ethernet/mediatek/mtk_eth_soc.c reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); reg_val 1833 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); reg_val 1838 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); reg_val 1843 drivers/net/ethernet/mediatek/mtk_eth_soc.c u32 reg_val; reg_val 1845 drivers/net/ethernet/mediatek/mtk_eth_soc.c reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); reg_val 1848 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); reg_val 67 drivers/net/ethernet/microchip/lan743x_ethtool.c u32 reg_val; reg_val 77 drivers/net/ethernet/microchip/lan743x_ethtool.c reg_val = lan743x_csr_read(adapter, OTP_STATUS); reg_val 78 drivers/net/ethernet/microchip/lan743x_ethtool.c } while (reg_val & OTP_STATUS_BUSY_); reg_val 306 drivers/net/ethernet/microchip/lan743x_main.h #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4) reg_val 2159 drivers/net/ethernet/qlogic/qed/qed_debug.c u32 reg_val[MAX_DBG_RESET_REGS] = { 0 }; reg_val 2165 drivers/net/ethernet/qlogic/qed/qed_debug.c reg_val[i] = qed_rd(p_hwfn, reg_val 2173 drivers/net/ethernet/qlogic/qed/qed_debug.c !(reg_val[block->reset_reg] & BIT(block->reset_bit_offset)); reg_val 2351 drivers/net/ethernet/qlogic/qed/qed_debug.c u32 reg_val[MAX_DBG_RESET_REGS] = { 0 }; reg_val 2360 drivers/net/ethernet/qlogic/qed/qed_debug.c reg_val[block->reset_reg] |= reg_val 2369 drivers/net/ethernet/qlogic/qed/qed_debug.c reg_val[i] |= reg_val 2372 drivers/net/ethernet/qlogic/qed/qed_debug.c if (reg_val[i]) reg_val 2376 drivers/net/ethernet/qlogic/qed/qed_debug.c RESET_REG_UNRESET_OFFSET, reg_val[i]); reg_val 3690 drivers/net/ethernet/qlogic/qed/qed_debug.c u32 block_size, ram_size, offset = 0, reg_val, i; reg_val 3698 drivers/net/ethernet/qlogic/qed/qed_debug.c reg_val = qed_rd(p_hwfn, p_ptt, big_ram->is_256b_reg_addr); reg_val 3699 drivers/net/ethernet/qlogic/qed/qed_debug.c block_size = reg_val & reg_val 754 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c u32 reg_val, i; reg_val 756 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val; reg_val 759 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c reg_val = qed_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY); reg_val 1043 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c u32 reg_val; reg_val 1047 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN); reg_val 1049 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, vxlan_enable); reg_val 1050 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val); reg_val 1051 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c if (reg_val) { reg_val 1052 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c reg_val = reg_val 1056 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT) reg_val 1062 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE); reg_val 1064 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, vxlan_enable); reg_val 1065 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c qed_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val); reg_val 1076 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c u32 reg_val; reg_val 1080 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN); reg_val 1082 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_gre_enable); reg_val 1084 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_gre_enable); reg_val 1085 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val); reg_val 1086 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c if (reg_val) { reg_val 1087 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c reg_val = reg_val 1091 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT) reg_val 1097 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE); reg_val 1099 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_gre_enable); reg_val 1101 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_gre_enable); reg_val 1102 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c qed_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val); reg_val 1129 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c u32 reg_val; reg_val 1133 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN); reg_val 1135 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_geneve_enable); reg_val 1137 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_geneve_enable); reg_val 1138 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val); reg_val 1139 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c if (reg_val) { reg_val 1140 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c reg_val = reg_val 1144 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT) reg_val 1175 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c u32 reg_val, cfg_mask; reg_val 1178 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_MSG_INFO); reg_val 1185 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c reg_val |= cfg_mask; reg_val 1194 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c reg_val &= ~cfg_mask; reg_val 1198 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c qed_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, reg_val); reg_val 1235 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c u32 reg_val, cam_line, ram_line_lo, ram_line_hi, search_non_ip_as_gft; reg_val 1247 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c reg_val = T_ETH_PACKET_MATCH_RFS_EVENTID << reg_val 1249 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c reg_val |= PARSER_ETH_CONN_CM_HDR << PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT; reg_val 1250 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c qed_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, reg_val); reg_val 167 drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c u32 reg_val; reg_val 169 drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c reg_val = readl(ioaddr + SXGBE_CORE_RX_CTL0_REG); reg_val 170 drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c reg_val &= ~(SXGBE_CORE_RXQ_ENABLE_MASK << queue_num); reg_val 171 drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c reg_val |= SXGBE_CORE_RXQ_ENABLE; reg_val 172 drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG); reg_val 177 drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c u32 reg_val; reg_val 179 drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c reg_val = readl(ioaddr + SXGBE_CORE_RX_CTL0_REG); reg_val 180 drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c reg_val &= ~(SXGBE_CORE_RXQ_ENABLE_MASK << queue_num); reg_val 181 drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c reg_val |= SXGBE_CORE_RXQ_DISABLE; reg_val 182 drivers/net/ethernet/samsung/sxgbe/sxgbe_core.c writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG); reg_val 23 drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c u32 reg_val; reg_val 25 drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c reg_val = readl(ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); reg_val 33 drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c reg_val |= SXGBE_DMA_AXI_UNDEF_BURST; reg_val 36 drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c reg_val |= (burst_map << SXGBE_DMA_BLENMAP_LSHIFT); reg_val 38 drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); reg_val 47 drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c u32 reg_val; reg_val 50 drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); reg_val 53 drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c reg_val |= SXGBE_DMA_PBL_X8MODE; reg_val 54 drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); reg_val 56 drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); reg_val 57 drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c reg_val |= (pbl << SXGBE_DMA_TXPBL_LSHIFT); reg_val 58 drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); reg_val 60 drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c reg_val = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); reg_val 61 drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c reg_val |= (pbl << SXGBE_DMA_RXPBL_LSHIFT); reg_val 62 drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); reg_val 365 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c u32 reg_val = 0; reg_val 382 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c reg_val = SXGBE_CORE_RSS_CTL_TCP4TE; reg_val 391 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c reg_val = SXGBE_CORE_RSS_CTL_UDP4TE; reg_val 408 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c reg_val = SXGBE_CORE_RSS_CTL_IP2TE; reg_val 415 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c reg_val |= readl(priv->ioaddr + SXGBE_CORE_RSS_CTL_REG); reg_val 416 drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c writel(reg_val, priv->ioaddr + SXGBE_CORE_RSS_CTL_REG); reg_val 23 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c u32 reg_val; reg_val 25 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG); reg_val 26 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val &= ETS_RST; reg_val 31 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val &= ETS_WRR; reg_val 34 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= ETS_WFQ; reg_val 37 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= ETS_DWRR; reg_val 40 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); reg_val 44 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val &= RAA_SP; reg_val 47 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= RAA_WSP; reg_val 50 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); reg_val 64 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c u32 fifo_bits, reg_val; reg_val 68 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); reg_val 69 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= (fifo_bits << SXGBE_MTL_FIFO_LSHIFT); reg_val 70 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); reg_val 76 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c u32 fifo_bits, reg_val; reg_val 80 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); reg_val 81 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= (fifo_bits << SXGBE_MTL_FIFO_LSHIFT); reg_val 82 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); reg_val 87 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c u32 reg_val; reg_val 89 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); reg_val 90 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= SXGBE_MTL_ENABLE_QUEUE; reg_val 91 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); reg_val 96 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c u32 reg_val; reg_val 98 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); reg_val 99 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val &= ~SXGBE_MTL_ENABLE_QUEUE; reg_val 100 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); reg_val 106 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c u32 reg_val; reg_val 108 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); reg_val 109 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val &= ~(SXGBE_MTL_FCMASK << RX_FC_ACTIVE); reg_val 110 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= (threshold << RX_FC_ACTIVE); reg_val 112 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); reg_val 117 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c u32 reg_val; reg_val 119 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); reg_val 120 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= SXGBE_MTL_ENABLE_FC; reg_val 121 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); reg_val 127 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c u32 reg_val; reg_val 129 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); reg_val 130 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val &= ~(SXGBE_MTL_FCMASK << RX_FC_DEACTIVE); reg_val 131 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= (threshold << RX_FC_DEACTIVE); reg_val 133 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); reg_val 138 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c u32 reg_val; reg_val 140 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); reg_val 141 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= SXGBE_MTL_RXQ_OP_FEP; reg_val 143 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); reg_val 148 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c u32 reg_val; reg_val 150 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); reg_val 151 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val &= ~(SXGBE_MTL_RXQ_OP_FEP); reg_val 153 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); reg_val 158 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c u32 reg_val; reg_val 160 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); reg_val 161 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= SXGBE_MTL_RXQ_OP_FUP; reg_val 163 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); reg_val 168 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c u32 reg_val; reg_val 170 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); reg_val 171 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val &= ~(SXGBE_MTL_RXQ_OP_FUP); reg_val 173 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); reg_val 180 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c u32 reg_val; reg_val 182 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); reg_val 185 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= SXGBE_MTL_SFMODE; reg_val 189 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= MTL_CONTROL_TTC_64; reg_val 191 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= MTL_CONTROL_TTC_96; reg_val 193 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= MTL_CONTROL_TTC_128; reg_val 195 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= MTL_CONTROL_TTC_192; reg_val 197 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= MTL_CONTROL_TTC_256; reg_val 199 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= MTL_CONTROL_TTC_384; reg_val 201 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= MTL_CONTROL_TTC_512; reg_val 205 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); reg_val 211 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c u32 reg_val; reg_val 213 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); reg_val 216 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= SXGBE_RX_MTL_SFMODE; reg_val 219 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= MTL_CONTROL_RTC_64; reg_val 221 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= MTL_CONTROL_RTC_96; reg_val 223 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c reg_val |= MTL_CONTROL_RTC_128; reg_val 227 drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); reg_val 2726 drivers/net/ethernet/sun/niu.c static u64 vlan_entry_set_parity(u64 reg_val) reg_val 2734 drivers/net/ethernet/sun/niu.c if (hweight64(reg_val & port01_mask) & 1) reg_val 2735 drivers/net/ethernet/sun/niu.c reg_val |= ENET_VLAN_TBL_PARITY0; reg_val 2737 drivers/net/ethernet/sun/niu.c reg_val &= ~ENET_VLAN_TBL_PARITY0; reg_val 2739 drivers/net/ethernet/sun/niu.c if (hweight64(reg_val & port23_mask) & 1) reg_val 2740 drivers/net/ethernet/sun/niu.c reg_val |= ENET_VLAN_TBL_PARITY1; reg_val 2742 drivers/net/ethernet/sun/niu.c reg_val &= ~ENET_VLAN_TBL_PARITY1; reg_val 2744 drivers/net/ethernet/sun/niu.c return reg_val; reg_val 2750 drivers/net/ethernet/sun/niu.c u64 reg_val = nr64(ENET_VLAN_TBL(index)); reg_val 2752 drivers/net/ethernet/sun/niu.c reg_val &= ~((ENET_VLAN_TBL_VPR | reg_val 2756 drivers/net/ethernet/sun/niu.c reg_val |= (ENET_VLAN_TBL_VPR << reg_val 2758 drivers/net/ethernet/sun/niu.c reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port)); reg_val 2760 drivers/net/ethernet/sun/niu.c reg_val = vlan_entry_set_parity(reg_val); reg_val 2762 drivers/net/ethernet/sun/niu.c nw64(ENET_VLAN_TBL(index), reg_val); reg_val 250 drivers/net/ethernet/sun/sungem.c static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits) reg_val 517 drivers/net/ethernet/sun/sungem.c u32 reg_val, changed_bits; reg_val 519 drivers/net/ethernet/sun/sungem.c reg_val = (mif_status & MIF_STATUS_DATA) >> 16; reg_val 522 drivers/net/ethernet/sun/sungem.c gem_handle_mif_event(gp, reg_val, changed_bits); reg_val 502 drivers/net/phy/mscc.c u16 reg_val; reg_val 505 drivers/net/phy/mscc.c reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL); reg_val 506 drivers/net/phy/mscc.c reg_val &= ~LED_MODE_SEL_MASK(led_num); reg_val 507 drivers/net/phy/mscc.c reg_val |= LED_MODE_SEL(led_num, (u16)mode); reg_val 508 drivers/net/phy/mscc.c rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val); reg_val 516 drivers/net/phy/mscc.c u16 reg_val; reg_val 518 drivers/net/phy/mscc.c reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL); reg_val 519 drivers/net/phy/mscc.c if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK) reg_val 530 drivers/net/phy/mscc.c u16 reg_val; reg_val 532 drivers/net/phy/mscc.c reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL); reg_val 534 drivers/net/phy/mscc.c reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK | reg_val 538 drivers/net/phy/mscc.c reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK | reg_val 542 drivers/net/phy/mscc.c rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val); reg_val 546 drivers/net/phy/mscc.c reg_val = 0; reg_val 549 drivers/net/phy/mscc.c reg_val = FORCE_MDI_CROSSOVER_MDI; reg_val 551 drivers/net/phy/mscc.c reg_val = FORCE_MDI_CROSSOVER_MDIX; reg_val 555 drivers/net/phy/mscc.c reg_val); reg_val 564 drivers/net/phy/mscc.c int reg_val; reg_val 566 drivers/net/phy/mscc.c reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED, reg_val 568 drivers/net/phy/mscc.c if (reg_val < 0) reg_val 569 drivers/net/phy/mscc.c return reg_val; reg_val 571 drivers/net/phy/mscc.c reg_val &= DOWNSHIFT_CNTL_MASK; reg_val 572 drivers/net/phy/mscc.c if (!(reg_val & DOWNSHIFT_EN)) reg_val 575 drivers/net/phy/mscc.c *count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2; reg_val 602 drivers/net/phy/mscc.c u16 reg_val; reg_val 642 drivers/net/phy/mscc.c reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); reg_val 644 drivers/net/phy/mscc.c reg_val |= SECURE_ON_ENABLE; reg_val 646 drivers/net/phy/mscc.c reg_val &= ~SECURE_ON_ENABLE; reg_val 647 drivers/net/phy/mscc.c __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val); reg_val 655 drivers/net/phy/mscc.c reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); reg_val 656 drivers/net/phy/mscc.c reg_val |= MII_VSC85XX_INT_MASK_WOL; reg_val 657 drivers/net/phy/mscc.c rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); reg_val 662 drivers/net/phy/mscc.c reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); reg_val 663 drivers/net/phy/mscc.c reg_val &= (~MII_VSC85XX_INT_MASK_WOL); reg_val 664 drivers/net/phy/mscc.c rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); reg_val 669 drivers/net/phy/mscc.c reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS); reg_val 681 drivers/net/phy/mscc.c u16 reg_val; reg_val 691 drivers/net/phy/mscc.c reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); reg_val 692 drivers/net/phy/mscc.c if (reg_val & SECURE_ON_ENABLE) reg_val 813 drivers/net/phy/mscc.c u16 reg_val; reg_val 816 drivers/net/phy/mscc.c reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); reg_val 817 drivers/net/phy/mscc.c reg_val &= ~(MAC_IF_SELECTION_MASK); reg_val 820 drivers/net/phy/mscc.c reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS); reg_val 823 drivers/net/phy/mscc.c reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS); reg_val 827 drivers/net/phy/mscc.c reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS); reg_val 833 drivers/net/phy/mscc.c rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val); reg_val 848 drivers/net/phy/mscc.c u16 reg_val; reg_val 853 drivers/net/phy/mscc.c reg_val = RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS; reg_val 857 drivers/net/phy/mscc.c reg_val); reg_val 898 drivers/net/phy/mscc.c const struct reg_val init_seq[] = { reg_val 942 drivers/net/phy/mscc.c const struct reg_val init_eee[] = { reg_val 1018 drivers/net/phy/mscc.c u16 reg_val; reg_val 1027 drivers/net/phy/mscc.c reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD); reg_val 1029 drivers/net/phy/mscc.c (reg_val & PROC_CMD_NCOMPLETED) && reg_val 1030 drivers/net/phy/mscc.c !(reg_val & PROC_CMD_FAILED)); reg_val 1034 drivers/net/phy/mscc.c if (reg_val & PROC_CMD_FAILED) reg_val 1037 drivers/net/phy/mscc.c if (reg_val & PROC_CMD_NCOMPLETED) reg_val 1227 drivers/net/phy/mscc.c const struct reg_val pre_init1[] = { reg_val 1275 drivers/net/phy/mscc.c const struct reg_val pre_init2[] = { reg_val 1430 drivers/net/phy/mscc.c const struct reg_val pre_init1[] = { reg_val 1454 drivers/net/phy/mscc.c const struct reg_val pre_init2[] = { reg_val 1789 drivers/net/phy/mscc.c const struct reg_val pre_init1[] = { reg_val 201 drivers/net/wireless/ath/ath10k/bmi.c int ath10k_bmi_write_soc_reg(struct ath10k *ar, u32 address, u32 reg_val) reg_val 209 drivers/net/wireless/ath/ath10k/bmi.c address, reg_val); reg_val 218 drivers/net/wireless/ath/ath10k/bmi.c cmd.write_soc_reg.value = __cpu_to_le32(reg_val); reg_val 230 drivers/net/wireless/ath/ath10k/bmi.c int ath10k_bmi_read_soc_reg(struct ath10k *ar, u32 address, u32 *reg_val) reg_val 256 drivers/net/wireless/ath/ath10k/bmi.c *reg_val = __le32_to_cpu(resp.read_soc_reg.value); reg_val 259 drivers/net/wireless/ath/ath10k/bmi.c *reg_val); reg_val 263 drivers/net/wireless/ath/ath10k/bmi.h int ath10k_bmi_read_soc_reg(struct ath10k *ar, u32 address, u32 *reg_val); reg_val 264 drivers/net/wireless/ath/ath10k/bmi.h int ath10k_bmi_write_soc_reg(struct ath10k *ar, u32 address, u32 reg_val); reg_val 687 drivers/net/wireless/ath/ath10k/debug.c u32 reg_addr, reg_val; reg_val 700 drivers/net/wireless/ath/ath10k/debug.c reg_val = ath10k_hif_read32(ar, reg_addr); reg_val 701 drivers/net/wireless/ath/ath10k/debug.c len = scnprintf(buf, sizeof(buf), "0x%08x:0x%08x\n", reg_addr, reg_val); reg_val 716 drivers/net/wireless/ath/ath10k/debug.c u32 reg_addr, reg_val; reg_val 729 drivers/net/wireless/ath/ath10k/debug.c ret = kstrtou32_from_user(user_buf, count, 0, ®_val); reg_val 733 drivers/net/wireless/ath/ath10k/debug.c ath10k_hif_write32(ar, reg_addr, reg_val); reg_val 740 drivers/net/wireless/ath/ath10k/hw.c u32 addr, reg_val, mem_val; reg_val 757 drivers/net/wireless/ath/ath10k/hw.c ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); reg_val 762 drivers/net/wireless/ath/ath10k/hw.c if (MS(reg_val, EFUSE_XTAL_SEL) > ATH10K_HW_REFCLK_COUNT) reg_val 765 drivers/net/wireless/ath/ath10k/hw.c hw_clk = &hw->hw_clk[MS(reg_val, EFUSE_XTAL_SEL)]; reg_val 769 drivers/net/wireless/ath/ath10k/hw.c ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); reg_val 773 drivers/net/wireless/ath/ath10k/hw.c reg_val &= ~(BB_PLL_CONFIG_FRAC_MASK | BB_PLL_CONFIG_OUTDIV_MASK); reg_val 774 drivers/net/wireless/ath/ath10k/hw.c reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) | reg_val 776 drivers/net/wireless/ath/ath10k/hw.c ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); reg_val 782 drivers/net/wireless/ath/ath10k/hw.c ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); reg_val 786 drivers/net/wireless/ath/ath10k/hw.c reg_val &= ~WLAN_PLL_SETTLE_TIME_MASK; reg_val 787 drivers/net/wireless/ath/ath10k/hw.c reg_val |= SM(hw_clk->settle_time, WLAN_PLL_SETTLE_TIME); reg_val 788 drivers/net/wireless/ath/ath10k/hw.c ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); reg_val 794 drivers/net/wireless/ath/ath10k/hw.c ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); reg_val 798 drivers/net/wireless/ath/ath10k/hw.c reg_val &= ~SOC_CORE_CLK_CTRL_DIV_MASK; reg_val 799 drivers/net/wireless/ath/ath10k/hw.c reg_val |= SM(1, SOC_CORE_CLK_CTRL_DIV); reg_val 800 drivers/net/wireless/ath/ath10k/hw.c ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); reg_val 813 drivers/net/wireless/ath/ath10k/hw.c ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); reg_val 817 drivers/net/wireless/ath/ath10k/hw.c reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) | reg_val 820 drivers/net/wireless/ath/ath10k/hw.c ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); reg_val 828 drivers/net/wireless/ath/ath10k/hw.c ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); reg_val 832 drivers/net/wireless/ath/ath10k/hw.c if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING)) reg_val 840 drivers/net/wireless/ath/ath10k/hw.c if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING)) reg_val 845 drivers/net/wireless/ath/ath10k/hw.c ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); reg_val 849 drivers/net/wireless/ath/ath10k/hw.c reg_val &= ~WLAN_PLL_CONTROL_BYPASS_MASK; reg_val 850 drivers/net/wireless/ath/ath10k/hw.c reg_val |= SM(0, WLAN_PLL_CONTROL_BYPASS); reg_val 851 drivers/net/wireless/ath/ath10k/hw.c ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); reg_val 859 drivers/net/wireless/ath/ath10k/hw.c ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); reg_val 863 drivers/net/wireless/ath/ath10k/hw.c if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING)) reg_val 871 drivers/net/wireless/ath/ath10k/hw.c if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING)) reg_val 876 drivers/net/wireless/ath/ath10k/hw.c ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); reg_val 880 drivers/net/wireless/ath/ath10k/hw.c reg_val &= ~SOC_CPU_CLOCK_STANDARD_MASK; reg_val 881 drivers/net/wireless/ath/ath10k/hw.c reg_val |= SM(1, SOC_CPU_CLOCK_STANDARD); reg_val 882 drivers/net/wireless/ath/ath10k/hw.c ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); reg_val 888 drivers/net/wireless/ath/ath10k/hw.c ret = ath10k_bmi_read_soc_reg(ar, addr, ®_val); reg_val 892 drivers/net/wireless/ath/ath10k/hw.c reg_val &= ~WLAN_PLL_CONTROL_NOPWD_MASK; reg_val 893 drivers/net/wireless/ath/ath10k/hw.c ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); reg_val 945 drivers/net/wireless/ath/ath6kl/debug.c __le32 reg_val; reg_val 967 drivers/net/wireless/ath/ath6kl/debug.c (u32 *)®_val); reg_val 972 drivers/net/wireless/ath/ath6kl/debug.c "0x%06x 0x%08x\n", addr, le32_to_cpu(reg_val)); reg_val 983 drivers/net/wireless/ath/ath6kl/debug.c (u32 *)®_val); reg_val 989 drivers/net/wireless/ath/ath6kl/debug.c addr, le32_to_cpu(reg_val)); reg_val 1084 drivers/net/wireless/ath/ath6kl/debug.c u32 reg_addr, reg_val; reg_val 1103 drivers/net/wireless/ath/ath6kl/debug.c if (kstrtou32(sptr, 0, ®_val)) reg_val 1107 drivers/net/wireless/ath/ath6kl/debug.c ar->debug.diag_reg_val_wr = reg_val; reg_val 3956 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c u32 reg_val; reg_val 4003 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg_val = le32_to_cpu(pBase->swreg); reg_val 4004 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c REG_WRITE(ah, AR_PHY_PMU1, reg_val); reg_val 4010 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg_val = le32_to_cpu(pBase->swreg); reg_val 4014 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val); reg_val 4039 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) | reg_val 4041 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val); reg_val 3901 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c u32 reg_val; reg_val 3990 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c reg_val = brcmf_sdiod_func0_rb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err); reg_val 3994 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET; reg_val 3996 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c brcmf_sdiod_func0_wb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err); reg_val 4002 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c reg_val = brcmf_sdiod_readl(sdiodev, reg_addr, &err); reg_val 4006 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT); reg_val 4008 drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c brcmf_sdiod_writel(sdiodev, reg_addr, reg_val, &err); reg_val 5168 drivers/net/wireless/intel/iwlegacy/4965-mac.c u32 reg_val; reg_val 5196 drivers/net/wireless/intel/iwlegacy/4965-mac.c reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG); reg_val 5198 drivers/net/wireless/intel/iwlegacy/4965-mac.c reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); reg_val 2003 drivers/net/wireless/intel/iwlwifi/dvm/main.c u32 reg_val = reg_val 2015 drivers/net/wireless/intel/iwlwifi/dvm/main.c reg_val); reg_val 144 drivers/net/wireless/intel/iwlwifi/mvm/ops.c u32 reg_val = 0; reg_val 155 drivers/net/wireless/intel/iwlwifi/mvm/ops.c reg_val |= CSR_HW_REV_STEP(mvm->trans->hw_rev) << reg_val 157 drivers/net/wireless/intel/iwlwifi/mvm/ops.c reg_val |= CSR_HW_REV_DASH(mvm->trans->hw_rev) << reg_val 161 drivers/net/wireless/intel/iwlwifi/mvm/ops.c reg_val |= radio_cfg_type << CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE; reg_val 162 drivers/net/wireless/intel/iwlwifi/mvm/ops.c reg_val |= radio_cfg_step << CSR_HW_IF_CONFIG_REG_POS_PHY_STEP; reg_val 163 drivers/net/wireless/intel/iwlwifi/mvm/ops.c reg_val |= radio_cfg_dash << CSR_HW_IF_CONFIG_REG_POS_PHY_DASH; reg_val 177 drivers/net/wireless/intel/iwlwifi/mvm/ops.c reg_val |= CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI; reg_val 180 drivers/net/wireless/intel/iwlwifi/mvm/ops.c reg_val |= CSR_HW_IF_CONFIG_REG_D3_DEBUG; reg_val 191 drivers/net/wireless/intel/iwlwifi/mvm/ops.c reg_val); reg_val 753 drivers/net/wireless/intel/iwlwifi/pcie/tx.c u32 reg_val; reg_val 795 drivers/net/wireless/intel/iwlwifi/pcie/tx.c reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); reg_val 797 drivers/net/wireless/intel/iwlwifi/pcie/tx.c reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); reg_val 387 drivers/net/wireless/mediatek/mt76/mt76.h __le32 reg_val; reg_val 863 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u32 val, tx_alc, reg_val; reg_val 887 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c reg_val = mt76_rr(dev, MT_BBP(IBI, 9)); reg_val 906 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_wr(dev, MT_BBP(IBI, 9), reg_val); reg_val 88 drivers/net/wireless/mediatek/mt76/usb.c 0, offset, &usb->reg_val, sizeof(__le32)); reg_val 90 drivers/net/wireless/mediatek/mt76/usb.c data = le32_to_cpu(usb->reg_val); reg_val 124 drivers/net/wireless/mediatek/mt76/usb.c usb->reg_val = cpu_to_le32(val); reg_val 127 drivers/net/wireless/mediatek/mt76/usb.c offset, &usb->reg_val, sizeof(__le32)); reg_val 126 drivers/ntb/hw/amd/ntb_hw_amd.c u64 base_addr, limit, reg_val; reg_val 156 drivers/ntb/hw/amd/ntb_hw_amd.c reg_val = read64(peer_mmio + xlat_reg); reg_val 157 drivers/ntb/hw/amd/ntb_hw_amd.c if (reg_val != addr) { reg_val 164 drivers/ntb/hw/amd/ntb_hw_amd.c reg_val = read64(peer_mmio + limit_reg); reg_val 165 drivers/ntb/hw/amd/ntb_hw_amd.c if (reg_val != limit) { reg_val 179 drivers/ntb/hw/amd/ntb_hw_amd.c reg_val = read64(peer_mmio + xlat_reg); reg_val 180 drivers/ntb/hw/amd/ntb_hw_amd.c if (reg_val != addr) { reg_val 187 drivers/ntb/hw/amd/ntb_hw_amd.c reg_val = readl(peer_mmio + limit_reg); reg_val 188 drivers/ntb/hw/amd/ntb_hw_amd.c if (reg_val != limit) { reg_val 846 drivers/ntb/hw/intel/ntb_hw_gen1.c u64 base, limit, reg_val; reg_val 890 drivers/ntb/hw/intel/ntb_hw_gen1.c reg_val = ioread64(mmio + xlat_reg); reg_val 891 drivers/ntb/hw/intel/ntb_hw_gen1.c if (reg_val != addr) { reg_val 898 drivers/ntb/hw/intel/ntb_hw_gen1.c reg_val = ioread64(mmio + limit_reg); reg_val 899 drivers/ntb/hw/intel/ntb_hw_gen1.c if (reg_val != limit) { reg_val 921 drivers/ntb/hw/intel/ntb_hw_gen1.c reg_val = ioread32(mmio + xlat_reg); reg_val 922 drivers/ntb/hw/intel/ntb_hw_gen1.c if (reg_val != addr) { reg_val 929 drivers/ntb/hw/intel/ntb_hw_gen1.c reg_val = ioread32(mmio + limit_reg); reg_val 930 drivers/ntb/hw/intel/ntb_hw_gen1.c if (reg_val != limit) { reg_val 1217 drivers/ntb/hw/intel/ntb_hw_gen1.c u16 reg_val; reg_val 1225 drivers/ntb/hw/intel/ntb_hw_gen1.c XEON_LINK_STATUS_OFFSET, ®_val); reg_val 1229 drivers/ntb/hw/intel/ntb_hw_gen1.c if (reg_val == ndev->lnk_sta) reg_val 1232 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->lnk_sta = reg_val; reg_val 95 drivers/ntb/hw/intel/ntb_hw_gen3.c u16 reg_val; reg_val 103 drivers/ntb/hw/intel/ntb_hw_gen3.c GEN3_LINK_STATUS_OFFSET, ®_val); reg_val 107 drivers/ntb/hw/intel/ntb_hw_gen3.c if (reg_val == ndev->lnk_sta) reg_val 110 drivers/ntb/hw/intel/ntb_hw_gen3.c ndev->lnk_sta = reg_val; reg_val 451 drivers/ntb/hw/intel/ntb_hw_gen3.c u64 base, limit, reg_val; reg_val 492 drivers/ntb/hw/intel/ntb_hw_gen3.c reg_val = ioread64(mmio + xlat_reg); reg_val 493 drivers/ntb/hw/intel/ntb_hw_gen3.c if (reg_val != addr) { reg_val 498 drivers/ntb/hw/intel/ntb_hw_gen3.c dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXBASE: %#Lx\n", bar, reg_val); reg_val 502 drivers/ntb/hw/intel/ntb_hw_gen3.c reg_val = ioread64(mmio + limit_reg); reg_val 503 drivers/ntb/hw/intel/ntb_hw_gen3.c if (reg_val != limit) { reg_val 509 drivers/ntb/hw/intel/ntb_hw_gen3.c dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXLMT: %#Lx\n", bar, reg_val); reg_val 523 drivers/ntb/hw/intel/ntb_hw_gen3.c reg_val = ioread64(mmio + limit_reg); reg_val 524 drivers/ntb/hw/intel/ntb_hw_gen3.c if (reg_val != limit) { reg_val 530 drivers/ntb/hw/intel/ntb_hw_gen3.c dev_dbg(&ntb->pdev->dev, "BAR %d EMBARXLMT: %#Lx\n", bar, reg_val); reg_val 54 drivers/nvmem/sunxi_sid.c u32 reg_val; reg_val 58 drivers/nvmem/sunxi_sid.c reg_val = (offset & SUN8I_SID_OFFSET_MASK) reg_val 60 drivers/nvmem/sunxi_sid.c reg_val |= SUN8I_SID_OP_LOCK | SUN8I_SID_READ; reg_val 61 drivers/nvmem/sunxi_sid.c writel(reg_val, sid->base + SUN8I_SID_PRCTL); reg_val 63 drivers/nvmem/sunxi_sid.c ret = readl_poll_timeout(sid->base + SUN8I_SID_PRCTL, reg_val, reg_val 64 drivers/nvmem/sunxi_sid.c !(reg_val & SUN8I_SID_READ), 100, 250000); reg_val 131 drivers/pci/controller/dwc/pcie-al.c u8 reg_val; reg_val 239 drivers/pci/controller/dwc/pcie-al.c if (busnr_reg != target_bus_cfg->reg_val) { reg_val 241 drivers/pci/controller/dwc/pcie-al.c target_bus_cfg->reg_val, busnr_reg); reg_val 242 drivers/pci/controller/dwc/pcie-al.c target_bus_cfg->reg_val = busnr_reg; reg_val 244 drivers/pci/controller/dwc/pcie-al.c target_bus_cfg->reg_val, reg_val 318 drivers/pci/controller/dwc/pcie-al.c target_bus_cfg->reg_val = pp->busn->start & target_bus_cfg->reg_mask; reg_val 320 drivers/pci/controller/dwc/pcie-al.c al_pcie_target_bus_set(pcie, target_bus_cfg->reg_val, reg_val 149 drivers/pci/controller/dwc/pcie-hisi.c u32 reg_val; reg_val 150 drivers/pci/controller/dwc/pcie-hisi.c void *walker = ®_val; reg_val 155 drivers/pci/controller/dwc/pcie-hisi.c reg_val = dw_pcie_readl_dbi(pci, reg); reg_val 162 drivers/pci/controller/dwc/pcie-hisi.c *val = reg_val; reg_val 173 drivers/pci/controller/dwc/pcie-hisi.c u32 reg_val; reg_val 175 drivers/pci/controller/dwc/pcie-hisi.c void *walker = ®_val; reg_val 183 drivers/pci/controller/dwc/pcie-hisi.c reg_val = dw_pcie_readl_dbi(pci, reg); reg_val 185 drivers/pci/controller/dwc/pcie-hisi.c dw_pcie_writel_dbi(pci, reg, reg_val); reg_val 187 drivers/pci/controller/dwc/pcie-hisi.c reg_val = dw_pcie_readl_dbi(pci, reg); reg_val 189 drivers/pci/controller/dwc/pcie-hisi.c dw_pcie_writel_dbi(pci, reg, reg_val); reg_val 186 drivers/pci/controller/dwc/pcie-kirin.c u32 reg_val; reg_val 188 drivers/pci/controller/dwc/pcie-kirin.c reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1); reg_val 189 drivers/pci/controller/dwc/pcie-kirin.c reg_val &= ~PHY_REF_PAD_BIT; reg_val 190 drivers/pci/controller/dwc/pcie-kirin.c kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1); reg_val 192 drivers/pci/controller/dwc/pcie-kirin.c reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL0); reg_val 193 drivers/pci/controller/dwc/pcie-kirin.c reg_val &= ~PHY_PWR_DOWN_BIT; reg_val 194 drivers/pci/controller/dwc/pcie-kirin.c kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL0); reg_val 197 drivers/pci/controller/dwc/pcie-kirin.c reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1); reg_val 198 drivers/pci/controller/dwc/pcie-kirin.c reg_val &= ~PHY_RST_ACK_BIT; reg_val 199 drivers/pci/controller/dwc/pcie-kirin.c kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1); reg_val 202 drivers/pci/controller/dwc/pcie-kirin.c reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_STATUS0); reg_val 203 drivers/pci/controller/dwc/pcie-kirin.c if (reg_val & PIPE_CLK_STABLE) { reg_val 56 drivers/pinctrl/actions/pinctrl-owl.c u32 reg_val; reg_val 58 drivers/pinctrl/actions/pinctrl-owl.c reg_val = readl_relaxed(base); reg_val 60 drivers/pinctrl/actions/pinctrl-owl.c reg_val = (reg_val & ~mask) | (val & mask); reg_val 62 drivers/pinctrl/actions/pinctrl-owl.c writel_relaxed(reg_val, base); reg_val 971 drivers/pinctrl/bcm/pinctrl-bcm281xx.c static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask, reg_val 975 drivers/pinctrl/bcm/pinctrl-bcm281xx.c *reg_val &= ~param_mask; reg_val 976 drivers/pinctrl/bcm/pinctrl-bcm281xx.c *reg_val |= (param_val << param_shift) & param_mask; reg_val 734 drivers/pinctrl/pinctrl-lpc18xx.c u32 reg_val; reg_val 737 drivers/pinctrl/pinctrl-lpc18xx.c reg_val = readl(addr); reg_val 739 drivers/pinctrl/pinctrl-lpc18xx.c if ((reg_val & LPC18XX_SCU_PINTSEL_VAL_MASK) == val) reg_val 742 drivers/pinctrl/pinctrl-lpc18xx.c reg_val >>= BITS_PER_BYTE; reg_val 985 drivers/pinctrl/pinctrl-lpc18xx.c u32 val, reg_val, reg_offset = LPC18XX_SCU_PINTSEL0; reg_val 999 drivers/pinctrl/pinctrl-lpc18xx.c reg_val = readl(scu->base + reg_offset); reg_val 1000 drivers/pinctrl/pinctrl-lpc18xx.c reg_val &= ~LPC18XX_SCU_PINTSEL_VAL(LPC18XX_SCU_PINTSEL_VAL_MASK, param_val); reg_val 1001 drivers/pinctrl/pinctrl-lpc18xx.c reg_val |= LPC18XX_SCU_PINTSEL_VAL(val, param_val); reg_val 1002 drivers/pinctrl/pinctrl-lpc18xx.c writel(reg_val, scu->base + reg_offset); reg_val 216 drivers/pinctrl/ti/pinctrl-ti-iodelay.c u32 reg_mask, reg_val, tmp_val; reg_val 236 drivers/pinctrl/ti/pinctrl-ti-iodelay.c reg_val = reg->signature_value << __ffs(reg->signature_mask); reg_val 245 drivers/pinctrl/ti/pinctrl-ti-iodelay.c reg_val |= tmp_val; reg_val 254 drivers/pinctrl/ti/pinctrl-ti-iodelay.c reg_val |= tmp_val; reg_val 263 drivers/pinctrl/ti/pinctrl-ti-iodelay.c reg_val |= reg->unlock_val << __ffs(reg->lock_mask); reg_val 264 drivers/pinctrl/ti/pinctrl-ti-iodelay.c r = regmap_update_bits(iod->regmap, cfg->offset, reg_mask, reg_val); reg_val 268 drivers/pinctrl/ti/pinctrl-ti-iodelay.c f_elements, reg_val); reg_val 47 drivers/power/avs/smartreflex.c u32 reg_val; reg_val 63 drivers/power/avs/smartreflex.c reg_val = __raw_readl(sr->base + offset); reg_val 64 drivers/power/avs/smartreflex.c reg_val &= ~mask; reg_val 68 drivers/power/avs/smartreflex.c reg_val |= value; reg_val 70 drivers/power/avs/smartreflex.c __raw_writel(reg_val, (sr->base + offset)); reg_val 535 drivers/power/supply/ab8500_fg.c u8 reg_val; reg_val 542 drivers/power/supply/ab8500_fg.c AB8500_RTC_CC_CONF_REG, ®_val); reg_val 546 drivers/power/supply/ab8500_fg.c if (!(reg_val & CC_PWR_UP_ENA)) { reg_val 145 drivers/power/supply/axp288_charger.c u8 reg_val; reg_val 153 drivers/power/supply/axp288_charger.c reg_val = (cc - CHRG_CCCV_CC_OFFSET) / CHRG_CCCV_CC_LSB_RES; reg_val 154 drivers/power/supply/axp288_charger.c cc = (reg_val * CHRG_CCCV_CC_LSB_RES) + CHRG_CCCV_CC_OFFSET; reg_val 155 drivers/power/supply/axp288_charger.c reg_val = reg_val << CHRG_CCCV_CC_BIT_POS; reg_val 159 drivers/power/supply/axp288_charger.c CHRG_CCCV_CC_MASK, reg_val); reg_val 168 drivers/power/supply/axp288_charger.c u8 reg_val; reg_val 172 drivers/power/supply/axp288_charger.c reg_val = CHRG_CCCV_CV_4100MV; reg_val 175 drivers/power/supply/axp288_charger.c reg_val = CHRG_CCCV_CV_4150MV; reg_val 178 drivers/power/supply/axp288_charger.c reg_val = CHRG_CCCV_CV_4200MV; reg_val 181 drivers/power/supply/axp288_charger.c reg_val = CHRG_CCCV_CV_4350MV; reg_val 185 drivers/power/supply/axp288_charger.c reg_val = reg_val << CHRG_CCCV_CV_BIT_POS; reg_val 189 drivers/power/supply/axp288_charger.c CHRG_CCCV_CV_MASK, reg_val); reg_val 234 drivers/power/supply/axp288_charger.c u8 reg_val; reg_val 237 drivers/power/supply/axp288_charger.c reg_val = CHRG_VBUS_ILIM_4000MA << CHRG_VBUS_ILIM_BIT_POS; reg_val 239 drivers/power/supply/axp288_charger.c reg_val = CHRG_VBUS_ILIM_3500MA << CHRG_VBUS_ILIM_BIT_POS; reg_val 241 drivers/power/supply/axp288_charger.c reg_val = CHRG_VBUS_ILIM_3000MA << CHRG_VBUS_ILIM_BIT_POS; reg_val 243 drivers/power/supply/axp288_charger.c reg_val = CHRG_VBUS_ILIM_2500MA << CHRG_VBUS_ILIM_BIT_POS; reg_val 245 drivers/power/supply/axp288_charger.c reg_val = CHRG_VBUS_ILIM_2000MA << CHRG_VBUS_ILIM_BIT_POS; reg_val 247 drivers/power/supply/axp288_charger.c reg_val = CHRG_VBUS_ILIM_1500MA << CHRG_VBUS_ILIM_BIT_POS; reg_val 249 drivers/power/supply/axp288_charger.c reg_val = CHRG_VBUS_ILIM_900MA << CHRG_VBUS_ILIM_BIT_POS; reg_val 251 drivers/power/supply/axp288_charger.c reg_val = CHRG_VBUS_ILIM_500MA << CHRG_VBUS_ILIM_BIT_POS; reg_val 253 drivers/power/supply/axp288_charger.c reg_val = CHRG_VBUS_ILIM_100MA << CHRG_VBUS_ILIM_BIT_POS; reg_val 256 drivers/power/supply/axp288_charger.c CHRG_VBUS_ILIM_MASK, reg_val); reg_val 171 drivers/power/supply/wm831x_power.c int reg_val; reg_val 251 drivers/power/supply/wm831x_power.c *reg |= map[i].reg_val; reg_val 59 drivers/ptp/ptp_dte.c u32 reg_val[DTE_NUM_REGS_TO_RESTORE]; reg_val 292 drivers/ptp/ptp_dte.c ptp_dte->reg_val[i] = reg_val 309 drivers/ptp/ptp_dte.c writel(ptp_dte->reg_val[i], reg_val 312 drivers/ptp/ptp_dte.c writel(((ptp_dte->reg_val[i] & reg_val 1348 drivers/rapidio/rio.c u32 reg_val; reg_val 1353 drivers/rapidio/rio.c ®_val); reg_val 1356 drivers/rapidio/rio.c RIO_ASM_INFO_CAR, ®_val); reg_val 1357 drivers/rapidio/rio.c return reg_val & RIO_EXT_FTR_PTR_MASK; reg_val 1360 drivers/rapidio/rio.c rio_local_read_config_32(port, from, ®_val); reg_val 1363 drivers/rapidio/rio.c from, ®_val); reg_val 1364 drivers/rapidio/rio.c return RIO_GET_BLOCK_ID(reg_val); reg_val 157 drivers/regulator/da903x.c uint8_t reg_val; reg_val 160 drivers/regulator/da903x.c ret = da903x_read(da9034_dev, info->enable_reg, ®_val); reg_val 164 drivers/regulator/da903x.c return !!(reg_val & (1 << info->enable_bit)); reg_val 115 drivers/regulator/da9052-regulator.c int reg_val = 0; reg_val 127 drivers/regulator/da9052-regulator.c reg_val = i; reg_val 142 drivers/regulator/da9052-regulator.c reg_val << 2); reg_val 147 drivers/regulator/da9052-regulator.c reg_val << 6); reg_val 310 drivers/regulator/da9211-regulator.c int reg_val, err, ret = IRQ_NONE; reg_val 312 drivers/regulator/da9211-regulator.c err = regmap_read(chip->regmap, DA9211_REG_EVENT_B, ®_val); reg_val 316 drivers/regulator/da9211-regulator.c if (reg_val & DA9211_E_OV_CURR_A) { reg_val 330 drivers/regulator/da9211-regulator.c if (reg_val & DA9211_E_OV_CURR_B) { reg_val 389 drivers/regulator/hi6421-regulator.c u32 reg_val; reg_val 391 drivers/regulator/hi6421-regulator.c regmap_read(rdev->regmap, rdev->desc->enable_reg, ®_val); reg_val 392 drivers/regulator/hi6421-regulator.c if (reg_val & info->mode_mask) reg_val 401 drivers/regulator/hi6421-regulator.c u32 reg_val; reg_val 403 drivers/regulator/hi6421-regulator.c regmap_read(rdev->regmap, rdev->desc->enable_reg, ®_val); reg_val 404 drivers/regulator/hi6421-regulator.c if (reg_val & info->mode_mask) reg_val 115 drivers/regulator/hi6421v530-regulator.c unsigned int reg_val; reg_val 118 drivers/regulator/hi6421v530-regulator.c regmap_read(rdev->regmap, rdev->desc->enable_reg, ®_val); reg_val 120 drivers/regulator/hi6421v530-regulator.c if (reg_val & (info->mode_mask)) reg_val 80 drivers/regulator/max8660.c u8 reg_val = (max8660->shadow_regs[reg] & mask) | val; reg_val 83 drivers/regulator/max8660.c max8660_addresses[reg], reg_val); reg_val 86 drivers/regulator/max8660.c max8660_addresses[reg], reg_val); reg_val 88 drivers/regulator/max8660.c max8660->shadow_regs[reg] = reg_val; reg_val 228 drivers/regulator/pv88060-regulator.c int i, reg_val, err, ret = IRQ_NONE; reg_val 230 drivers/regulator/pv88060-regulator.c err = regmap_read(chip->regmap, PV88060_REG_EVENT_A, ®_val); reg_val 234 drivers/regulator/pv88060-regulator.c if (reg_val & PV88060_E_VDD_FLT) { reg_val 253 drivers/regulator/pv88060-regulator.c if (reg_val & PV88060_E_OVER_TEMP) { reg_val 329 drivers/regulator/pv88080-regulator.c int i, reg_val, err, ret = IRQ_NONE; reg_val 331 drivers/regulator/pv88080-regulator.c err = regmap_read(chip->regmap, PV88080_REG_EVENT_A, ®_val); reg_val 335 drivers/regulator/pv88080-regulator.c if (reg_val & PV88080_E_VDD_FLT) { reg_val 354 drivers/regulator/pv88080-regulator.c if (reg_val & PV88080_E_OVER_TEMP) { reg_val 221 drivers/regulator/pv88090-regulator.c int i, reg_val, err, ret = IRQ_NONE; reg_val 223 drivers/regulator/pv88090-regulator.c err = regmap_read(chip->regmap, PV88090_REG_EVENT_A, ®_val); reg_val 227 drivers/regulator/pv88090-regulator.c if (reg_val & PV88090_E_VDD_FLT) { reg_val 246 drivers/regulator/pv88090-regulator.c if (reg_val & PV88090_E_OVER_TEMP) { reg_val 928 drivers/regulator/tps65910-regulator.c u8 reg_val = srvsel & VDD1_OP_SEL_MASK; reg_val 931 drivers/regulator/tps65910-regulator.c reg_val); reg_val 90 drivers/regulator/tps80031-regulator.c u8 reg_val; reg_val 97 drivers/regulator/tps80031-regulator.c ®_val); reg_val 103 drivers/regulator/tps80031-regulator.c return (reg_val & TPS80031_STATE_MASK) == TPS80031_STATE_ON; reg_val 169 drivers/regulator/tps80031-regulator.c u8 reg_val; reg_val 173 drivers/regulator/tps80031-regulator.c ri->rinfo->force_reg, ®_val); reg_val 179 drivers/regulator/tps80031-regulator.c if (!(reg_val & SMPS_CMD_MASK)) { reg_val 540 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c u32 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME); reg_val 542 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c reg_val |= CFG_AGING_TIME_ITCT_REL_MSK; reg_val 543 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val); reg_val 547 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME); reg_val 548 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c reg_val &= ~CFG_AGING_TIME_ITCT_REL_MSK; reg_val 549 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val); reg_val 983 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); reg_val 989 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) reg_val 994 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); reg_val 995 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); reg_val 1327 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c int i, reg_val; reg_val 1333 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL); reg_val 1334 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c if (!(reg_val & BIT(0))) { reg_val 1348 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c int i, reg_val; reg_val 1350 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c reg_val = hisi_sas_read32(hisi_hba, PHY_STATE); reg_val 1351 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c for (i = 0; i < hisi_hba->n_phy && reg_val; i++) { reg_val 1355 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c if (reg_val & BIT(i)) { reg_val 3092 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); reg_val 3093 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c u32 dev_id = reg_val & ITCT_DEV_MSK; reg_val 804 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); reg_val 809 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) reg_val 814 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); reg_val 815 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); reg_val 2058 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c u32 reg_val; reg_val 2060 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val = hisi_sas_read32(hisi_hba, reg_val 2063 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; reg_val 2065 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c AM_CTRL_GLOBAL, reg_val); reg_val 2072 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); reg_val 2073 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c u32 dev_id = reg_val & ITCT_DEV_MSK; reg_val 2523 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c u32 status, reg_val; reg_val 2534 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + reg_val 2536 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; reg_val 2538 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c AM_CTRL_GLOBAL, reg_val); reg_val 2946 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c u32 reg_val; reg_val 2953 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, SERDES_CFG); reg_val 2954 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val |= CFG_ALOS_CHK_DISABLE_MSK; reg_val 2955 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c hisi_sas_phy_write32(hisi_hba, phy_id, SERDES_CFG, reg_val); reg_val 2960 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c u32 reg_val; reg_val 2964 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, SAS_PHY_BIST_CTRL); reg_val 2965 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val &= ~(CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK | reg_val 2967 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c hisi_sas_phy_write32(hisi_hba, phy_id, SAS_PHY_BIST_CTRL, reg_val); reg_val 2970 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, SERDES_CFG); reg_val 2971 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val &= ~CFG_ALOS_CHK_DISABLE_MSK; reg_val 2972 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c hisi_sas_phy_write32(hisi_hba, phy_id, SERDES_CFG, reg_val); reg_val 2975 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, PROG_PHY_LINK_RATE); reg_val 2977 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val &= ~CFG_PROG_PHY_LINK_RATE_MSK; reg_val 2978 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val |= (0x8 << CFG_PROG_PHY_LINK_RATE_OFF); reg_val 2979 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c hisi_sas_phy_write32(hisi_hba, phy_id, PROG_PHY_LINK_RATE, reg_val); reg_val 2989 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c u32 reg_val, mode_tmp; reg_val 3004 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, reg_val 3006 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val &= ~CFG_PROG_PHY_LINK_RATE_MSK; reg_val 3007 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val |= (linkrate << CFG_PROG_PHY_LINK_RATE_OFF); reg_val 3009 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c PROG_PHY_LINK_RATE, reg_val); reg_val 3012 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, reg_val 3014 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val &= ~(CFG_BIST_MODE_SEL_MSK | reg_val 3019 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val |= ((code_mode << CFG_BIST_MODE_SEL_OFF) | reg_val 3023 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c SAS_PHY_BIST_CTRL, reg_val); reg_val 3034 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK); reg_val 3036 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c SAS_PHY_BIST_CTRL, reg_val); reg_val 1524 drivers/scsi/lpfc/lpfc_attr.c uint32_t reg_val; reg_val 1559 drivers/scsi/lpfc/lpfc_attr.c reg_val = readl(phba->sli4_hba.conf_regs_memmap_p + reg_val 1563 drivers/scsi/lpfc/lpfc_attr.c reg_val |= LPFC_FW_DUMP_REQUEST; reg_val 1565 drivers/scsi/lpfc/lpfc_attr.c reg_val |= LPFC_CTL_PDEV_CTL_FRST; reg_val 1567 drivers/scsi/lpfc/lpfc_attr.c reg_val |= LPFC_CTL_PDEV_CTL_DRST; reg_val 1569 drivers/scsi/lpfc/lpfc_attr.c writel(reg_val, phba->sli4_hba.conf_regs_memmap_p + reg_val 1581 drivers/scsi/lpfc/lpfc_attr.c "access: x%x\n", reg_val); reg_val 1586 drivers/scsi/lpfc/lpfc_attr.c "access: x%x\n", reg_val); reg_val 4491 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t drb_reg_id, value, reg_val = 0; reg_val 4547 drivers/scsi/lpfc/lpfc_debugfs.c reg_val = value; reg_val 4549 drivers/scsi/lpfc/lpfc_debugfs.c reg_val = readl(drb_reg); reg_val 4550 drivers/scsi/lpfc/lpfc_debugfs.c reg_val |= value; reg_val 4553 drivers/scsi/lpfc/lpfc_debugfs.c reg_val = readl(drb_reg); reg_val 4554 drivers/scsi/lpfc/lpfc_debugfs.c reg_val &= ~value; reg_val 4556 drivers/scsi/lpfc/lpfc_debugfs.c writel(reg_val, drb_reg); reg_val 4706 drivers/scsi/lpfc/lpfc_debugfs.c uint32_t ctl_reg_id, value, reg_val = 0; reg_val 4771 drivers/scsi/lpfc/lpfc_debugfs.c reg_val = value; reg_val 4773 drivers/scsi/lpfc/lpfc_debugfs.c reg_val = readl(ctl_reg); reg_val 4774 drivers/scsi/lpfc/lpfc_debugfs.c reg_val |= value; reg_val 4777 drivers/scsi/lpfc/lpfc_debugfs.c reg_val = readl(ctl_reg); reg_val 4778 drivers/scsi/lpfc/lpfc_debugfs.c reg_val &= ~value; reg_val 4780 drivers/scsi/lpfc/lpfc_debugfs.c writel(reg_val, ctl_reg); reg_val 52 drivers/scsi/pm8001/pm80xx_hwi.c u32 reg_val; reg_val 58 drivers/scsi/pm8001/pm80xx_hwi.c reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER); reg_val 59 drivers/scsi/pm8001/pm80xx_hwi.c } while ((reg_val != shift_value) && time_before(jiffies, start)); reg_val 60 drivers/scsi/pm8001/pm80xx_hwi.c if (reg_val != shift_value) { reg_val 63 drivers/scsi/pm8001/pm80xx_hwi.c " = 0x%x\n", reg_val)); reg_val 94 drivers/scsi/pm8001/pm80xx_hwi.c u32 accum_len , reg_val, index, *temp; reg_val 228 drivers/scsi/pm8001/pm80xx_hwi.c reg_val = pm8001_mr32(fatal_table_address, reg_val 230 drivers/scsi/pm8001/pm80xx_hwi.c } while ((reg_val) && time_before(jiffies, start)); reg_val 232 drivers/scsi/pm8001/pm80xx_hwi.c if (reg_val != 0) { reg_val 235 drivers/scsi/pm8001/pm80xx_hwi.c " = 0x%x\n", reg_val)); reg_val 532 drivers/scsi/qla2xxx/qla_mr.c uint32_t reg_val; reg_val 546 drivers/scsi/qla2xxx/qla_mr.c reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60840); reg_val 547 drivers/scsi/qla2xxx/qla_mr.c reg_val &= ~(1<<12); reg_val 548 drivers/scsi/qla2xxx/qla_mr.c QLAFX00_SET_HBA_SOC_REG(ha, 0x60840, reg_val); reg_val 550 drivers/scsi/qla2xxx/qla_mr.c reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60844); reg_val 551 drivers/scsi/qla2xxx/qla_mr.c reg_val &= ~(1<<12); reg_val 552 drivers/scsi/qla2xxx/qla_mr.c QLAFX00_SET_HBA_SOC_REG(ha, 0x60844, reg_val); reg_val 554 drivers/scsi/qla2xxx/qla_mr.c reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60848); reg_val 555 drivers/scsi/qla2xxx/qla_mr.c reg_val &= ~(1<<12); reg_val 556 drivers/scsi/qla2xxx/qla_mr.c QLAFX00_SET_HBA_SOC_REG(ha, 0x60848, reg_val); reg_val 558 drivers/scsi/qla2xxx/qla_mr.c reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x6084C); reg_val 559 drivers/scsi/qla2xxx/qla_mr.c reg_val &= ~(1<<12); reg_val 560 drivers/scsi/qla2xxx/qla_mr.c QLAFX00_SET_HBA_SOC_REG(ha, 0x6084C, reg_val); reg_val 266 drivers/scsi/qla4xxx/ql4_os.c u32 reg_val = 0; reg_val 270 drivers/scsi/qla4xxx/ql4_os.c reg_val = readl(&ha->qla4_82xx_reg->host_status); reg_val 272 drivers/scsi/qla4xxx/ql4_os.c reg_val = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER); reg_val 274 drivers/scsi/qla4xxx/ql4_os.c reg_val = readw(&ha->reg->ctrl_status); reg_val 276 drivers/scsi/qla4xxx/ql4_os.c if (reg_val == QL4_ISP_REG_DISCONNECT) reg_val 27 drivers/soc/sunxi/sunxi_sram.c u32 reg_val; reg_val 48 drivers/soc/sunxi/sunxi_sram.c .reg_val = _reg_val, \ reg_val 147 drivers/soc/sunxi/sunxi_sram.c func->reg_val == val ? reg_val 202 drivers/soc/sunxi/sunxi_sram.c *reg_value = func->reg_val; reg_val 180 drivers/spi/spi-mt65xx.c u32 reg_val; reg_val 183 drivers/spi/spi-mt65xx.c reg_val = readl(mdata->base + SPI_CMD_REG); reg_val 184 drivers/spi/spi-mt65xx.c reg_val |= SPI_CMD_RST; reg_val 185 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CMD_REG); reg_val 187 drivers/spi/spi-mt65xx.c reg_val = readl(mdata->base + SPI_CMD_REG); reg_val 188 drivers/spi/spi-mt65xx.c reg_val &= ~SPI_CMD_RST; reg_val 189 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CMD_REG); reg_val 196 drivers/spi/spi-mt65xx.c u32 reg_val; reg_val 204 drivers/spi/spi-mt65xx.c reg_val = readl(mdata->base + SPI_CMD_REG); reg_val 206 drivers/spi/spi-mt65xx.c reg_val |= SPI_CMD_CPHA; reg_val 208 drivers/spi/spi-mt65xx.c reg_val &= ~SPI_CMD_CPHA; reg_val 210 drivers/spi/spi-mt65xx.c reg_val |= SPI_CMD_CPOL; reg_val 212 drivers/spi/spi-mt65xx.c reg_val &= ~SPI_CMD_CPOL; reg_val 216 drivers/spi/spi-mt65xx.c reg_val &= ~SPI_CMD_TXMSBF; reg_val 217 drivers/spi/spi-mt65xx.c reg_val &= ~SPI_CMD_RXMSBF; reg_val 219 drivers/spi/spi-mt65xx.c reg_val |= SPI_CMD_TXMSBF; reg_val 220 drivers/spi/spi-mt65xx.c reg_val |= SPI_CMD_RXMSBF; reg_val 225 drivers/spi/spi-mt65xx.c reg_val &= ~SPI_CMD_TX_ENDIAN; reg_val 226 drivers/spi/spi-mt65xx.c reg_val &= ~SPI_CMD_RX_ENDIAN; reg_val 228 drivers/spi/spi-mt65xx.c reg_val |= SPI_CMD_TX_ENDIAN; reg_val 229 drivers/spi/spi-mt65xx.c reg_val |= SPI_CMD_RX_ENDIAN; reg_val 234 drivers/spi/spi-mt65xx.c reg_val |= SPI_CMD_CS_POL; reg_val 236 drivers/spi/spi-mt65xx.c reg_val &= ~SPI_CMD_CS_POL; reg_val 238 drivers/spi/spi-mt65xx.c reg_val |= SPI_CMD_SAMPLE_SEL; reg_val 240 drivers/spi/spi-mt65xx.c reg_val &= ~SPI_CMD_SAMPLE_SEL; reg_val 244 drivers/spi/spi-mt65xx.c reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE; reg_val 247 drivers/spi/spi-mt65xx.c reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); reg_val 250 drivers/spi/spi-mt65xx.c reg_val &= ~SPI_CMD_DEASSERT; reg_val 252 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CMD_REG); reg_val 264 drivers/spi/spi-mt65xx.c u32 reg_val; reg_val 267 drivers/spi/spi-mt65xx.c reg_val = readl(mdata->base + SPI_CMD_REG); reg_val 269 drivers/spi/spi-mt65xx.c reg_val |= SPI_CMD_PAUSE_EN; reg_val 270 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CMD_REG); reg_val 272 drivers/spi/spi-mt65xx.c reg_val &= ~SPI_CMD_PAUSE_EN; reg_val 273 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CMD_REG); reg_val 282 drivers/spi/spi-mt65xx.c u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0; reg_val 295 drivers/spi/spi-mt65xx.c reg_val |= (((sck_time - 1) & 0xffff) reg_val 297 drivers/spi/spi-mt65xx.c reg_val |= (((sck_time - 1) & 0xffff) reg_val 299 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CFG2_REG); reg_val 300 drivers/spi/spi-mt65xx.c reg_val |= (((cs_time - 1) & 0xffff) reg_val 302 drivers/spi/spi-mt65xx.c reg_val |= (((cs_time - 1) & 0xffff) reg_val 304 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CFG0_REG); reg_val 306 drivers/spi/spi-mt65xx.c reg_val |= (((sck_time - 1) & 0xff) reg_val 308 drivers/spi/spi-mt65xx.c reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); reg_val 309 drivers/spi/spi-mt65xx.c reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); reg_val 310 drivers/spi/spi-mt65xx.c reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET); reg_val 311 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CFG0_REG); reg_val 314 drivers/spi/spi-mt65xx.c reg_val = readl(mdata->base + SPI_CFG1_REG); reg_val 315 drivers/spi/spi-mt65xx.c reg_val &= ~SPI_CFG1_CS_IDLE_MASK; reg_val 316 drivers/spi/spi-mt65xx.c reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); reg_val 317 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CFG1_REG); reg_val 322 drivers/spi/spi-mt65xx.c u32 packet_size, packet_loop, reg_val; reg_val 328 drivers/spi/spi-mt65xx.c reg_val = readl(mdata->base + SPI_CFG1_REG); reg_val 329 drivers/spi/spi-mt65xx.c reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK); reg_val 330 drivers/spi/spi-mt65xx.c reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; reg_val 331 drivers/spi/spi-mt65xx.c reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; reg_val 332 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_CFG1_REG); reg_val 419 drivers/spi/spi-mt65xx.c u32 reg_val; reg_val 433 drivers/spi/spi-mt65xx.c reg_val = 0; reg_val 434 drivers/spi/spi-mt65xx.c memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder); reg_val 435 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_TX_DATA_REG); reg_val 523 drivers/spi/spi-mt65xx.c u32 cmd, reg_val, cnt, remainder, len; reg_val 528 drivers/spi/spi-mt65xx.c reg_val = readl(mdata->base + SPI_STATUS0_REG); reg_val 529 drivers/spi/spi-mt65xx.c if (reg_val & MTK_SPI_PAUSE_INT_STATUS) reg_val 541 drivers/spi/spi-mt65xx.c reg_val = readl(mdata->base + SPI_RX_DATA_REG); reg_val 545 drivers/spi/spi-mt65xx.c ®_val, reg_val 566 drivers/spi/spi-mt65xx.c reg_val = 0; reg_val 567 drivers/spi/spi-mt65xx.c memcpy(®_val, reg_val 570 drivers/spi/spi-mt65xx.c writel(reg_val, mdata->base + SPI_TX_DATA_REG); reg_val 83 drivers/spi/spi-slave-mt27xx.c u32 reg_val; reg_val 85 drivers/spi/spi-slave-mt27xx.c reg_val = readl(mdata->base + SPIS_DMA_CFG_REG); reg_val 86 drivers/spi/spi-slave-mt27xx.c reg_val &= ~RX_DMA_EN; reg_val 87 drivers/spi/spi-slave-mt27xx.c reg_val &= ~TX_DMA_EN; reg_val 88 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_DMA_CFG_REG); reg_val 93 drivers/spi/spi-slave-mt27xx.c u32 reg_val; reg_val 95 drivers/spi/spi-slave-mt27xx.c reg_val = readl(mdata->base + SPIS_CFG_REG); reg_val 96 drivers/spi/spi-slave-mt27xx.c reg_val &= ~SPIS_TX_EN; reg_val 97 drivers/spi/spi-slave-mt27xx.c reg_val &= ~SPIS_RX_EN; reg_val 98 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_CFG_REG); reg_val 118 drivers/spi/spi-slave-mt27xx.c u32 reg_val; reg_val 123 drivers/spi/spi-slave-mt27xx.c reg_val = readl(mdata->base + SPIS_CFG_REG); reg_val 125 drivers/spi/spi-slave-mt27xx.c reg_val |= SPIS_CPHA; reg_val 127 drivers/spi/spi-slave-mt27xx.c reg_val &= ~SPIS_CPHA; reg_val 129 drivers/spi/spi-slave-mt27xx.c reg_val |= SPIS_CPOL; reg_val 131 drivers/spi/spi-slave-mt27xx.c reg_val &= ~SPIS_CPOL; reg_val 134 drivers/spi/spi-slave-mt27xx.c reg_val &= ~(SPIS_TXMSBF | SPIS_RXMSBF); reg_val 136 drivers/spi/spi-slave-mt27xx.c reg_val |= SPIS_TXMSBF | SPIS_RXMSBF; reg_val 138 drivers/spi/spi-slave-mt27xx.c reg_val &= ~SPIS_TX_ENDIAN; reg_val 139 drivers/spi/spi-slave-mt27xx.c reg_val &= ~SPIS_RX_ENDIAN; reg_val 140 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_CFG_REG); reg_val 150 drivers/spi/spi-slave-mt27xx.c int reg_val, cnt, remainder, ret; reg_val 154 drivers/spi/spi-slave-mt27xx.c reg_val = readl(mdata->base + SPIS_CFG_REG); reg_val 156 drivers/spi/spi-slave-mt27xx.c reg_val |= SPIS_RX_EN; reg_val 158 drivers/spi/spi-slave-mt27xx.c reg_val |= SPIS_TX_EN; reg_val 159 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_CFG_REG); reg_val 168 drivers/spi/spi-slave-mt27xx.c reg_val = 0; reg_val 169 drivers/spi/spi-slave-mt27xx.c memcpy(®_val, xfer->tx_buf + cnt * 4, remainder); reg_val 170 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_TX_DATA_REG); reg_val 188 drivers/spi/spi-slave-mt27xx.c int reg_val, ret; reg_val 221 drivers/spi/spi-slave-mt27xx.c reg_val = readl(mdata->base + SPIS_CFG_REG); reg_val 223 drivers/spi/spi-slave-mt27xx.c reg_val |= SPIS_TX_EN; reg_val 225 drivers/spi/spi-slave-mt27xx.c reg_val |= SPIS_RX_EN; reg_val 226 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_CFG_REG); reg_val 229 drivers/spi/spi-slave-mt27xx.c reg_val = 0; reg_val 230 drivers/spi/spi-slave-mt27xx.c reg_val |= (xfer->len - 1) & TX_DMA_LEN; reg_val 231 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_DMA_CFG_REG); reg_val 233 drivers/spi/spi-slave-mt27xx.c reg_val = readl(mdata->base + SPIS_DMA_CFG_REG); reg_val 235 drivers/spi/spi-slave-mt27xx.c reg_val |= TX_DMA_EN; reg_val 237 drivers/spi/spi-slave-mt27xx.c reg_val |= RX_DMA_EN; reg_val 238 drivers/spi/spi-slave-mt27xx.c reg_val |= TX_DMA_TRIG_EN; reg_val 239 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_DMA_CFG_REG); reg_val 284 drivers/spi/spi-slave-mt27xx.c u32 reg_val; reg_val 286 drivers/spi/spi-slave-mt27xx.c reg_val = DMA_DONE_EN | DATA_DONE_EN | reg_val 288 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_IRQ_EN_REG); reg_val 290 drivers/spi/spi-slave-mt27xx.c reg_val = DMA_DONE_MASK | DATA_DONE_MASK | reg_val 292 drivers/spi/spi-slave-mt27xx.c writel(reg_val, mdata->base + SPIS_IRQ_MASK_REG); reg_val 315 drivers/spi/spi-slave-mt27xx.c u32 int_status, reg_val, cnt, remainder; reg_val 348 drivers/spi/spi-slave-mt27xx.c reg_val = readl(mdata->base + SPIS_RX_DATA_REG); reg_val 350 drivers/spi/spi-slave-mt27xx.c ®_val, remainder); reg_val 614 drivers/staging/octeon/ethernet.c (const struct device_node *parent, int reg_val) reg_val 625 drivers/staging/octeon/ethernet.c if (addr && (be32_to_cpu(*addr) == reg_val)) reg_val 13 drivers/staging/qlge/qlge_dbg.c u32 reg_val; reg_val 20 drivers/staging/qlge/qlge_dbg.c status = ql_read_mpi_reg(qdev, register_to_read, ®_val); reg_val 24 drivers/staging/qlge/qlge_dbg.c return reg_val; reg_val 29 drivers/staging/qlge/qlge_dbg.c u32 reg, u32 reg_val) reg_val 38 drivers/staging/qlge/qlge_dbg.c status = ql_write_mpi_reg(qdev, register_to_read, reg_val); reg_val 684 drivers/staging/qlge/qlge_dbg.c u32 func_num, reg, reg_val; reg_val 691 drivers/staging/qlge/qlge_dbg.c status = ql_read_mpi_reg(qdev, reg, ®_val); reg_val 692 drivers/staging/qlge/qlge_dbg.c *buf = reg_val; reg_val 774 drivers/staging/rtl8723bs/hal/sdio_halinit.c u8 reg_val = 0; reg_val 779 drivers/staging/rtl8723bs/hal/sdio_halinit.c reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN); reg_val 780 drivers/staging/rtl8723bs/hal/sdio_halinit.c reg_val &= ~(BIT(0) | BIT(1)); reg_val 781 drivers/staging/rtl8723bs/hal/sdio_halinit.c rtw_write8(padapter, REG_SYS_FUNC_EN, reg_val); reg_val 787 drivers/staging/rtl8723bs/hal/sdio_halinit.c reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN + 1); reg_val 788 drivers/staging/rtl8723bs/hal/sdio_halinit.c reg_val &= ~(BIT(4) | BIT(7)); reg_val 789 drivers/staging/rtl8723bs/hal/sdio_halinit.c rtw_write8(padapter, REG_SYS_FUNC_EN + 1, reg_val); reg_val 790 drivers/staging/rtl8723bs/hal/sdio_halinit.c reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN + 1); reg_val 791 drivers/staging/rtl8723bs/hal/sdio_halinit.c reg_val |= BIT(4) | BIT(7); reg_val 792 drivers/staging/rtl8723bs/hal/sdio_halinit.c rtw_write8(padapter, REG_SYS_FUNC_EN + 1, reg_val); reg_val 1506 drivers/staging/rts5208/xd.c u8 reg_val, page_cnt; reg_val 1571 drivers/staging/rts5208/xd.c retval = rtsx_read_register(chip, XD_PAGE_STATUS, ®_val); reg_val 1575 drivers/staging/rts5208/xd.c if (reg_val != XD_GPG) reg_val 1578 drivers/staging/rts5208/xd.c retval = rtsx_read_register(chip, XD_CTL, ®_val); reg_val 1582 drivers/staging/rts5208/xd.c if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) == reg_val 1584 drivers/staging/rts5208/xd.c ((reg_val & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) == reg_val 1709 drivers/staging/rts5208/xd.c u8 page_cnt, reg_val; reg_val 1789 drivers/staging/rts5208/xd.c retval = rtsx_read_register(chip, XD_DAT, ®_val); reg_val 1792 drivers/staging/rts5208/xd.c if (reg_val & PROGRAM_ERROR) { reg_val 160 drivers/thermal/intel/intel_bxt_pmic_thermal.c u8 reg_val, mask, irq_stat; reg_val 181 drivers/thermal/intel/intel_bxt_pmic_thermal.c reg_val = (u8)ret; reg_val 201 drivers/thermal/intel/intel_bxt_pmic_thermal.c regmap_write(regmap, reg, reg_val & mask); reg_val 291 drivers/thermal/rcar_gen3_thermal.c u32 reg_val; reg_val 293 drivers/thermal/rcar_gen3_thermal.c reg_val = rcar_gen3_thermal_read(tsc, REG_GEN3_THCTR); reg_val 294 drivers/thermal/rcar_gen3_thermal.c reg_val &= ~THCTR_PONM; reg_val 295 drivers/thermal/rcar_gen3_thermal.c rcar_gen3_thermal_write(tsc, REG_GEN3_THCTR, reg_val); reg_val 303 drivers/thermal/rcar_gen3_thermal.c reg_val = rcar_gen3_thermal_read(tsc, REG_GEN3_THCTR); reg_val 304 drivers/thermal/rcar_gen3_thermal.c reg_val |= THCTR_THSST; reg_val 305 drivers/thermal/rcar_gen3_thermal.c rcar_gen3_thermal_write(tsc, REG_GEN3_THCTR, reg_val); reg_val 351 drivers/thermal/ti-soc-thermal/ti-bandgap.c int reg_val; reg_val 355 drivers/thermal/ti-soc-thermal/ti-bandgap.c reg_val = ti_bandgap_readl(bgp, tsr->bgap_mask_ctrl); reg_val 356 drivers/thermal/ti-soc-thermal/ti-bandgap.c reg_val = (reg_val & tsr->mask_counter_delay_mask) >> reg_val 358 drivers/thermal/ti-soc-thermal/ti-bandgap.c switch (reg_val) { reg_val 379 drivers/thermal/ti-soc-thermal/ti-bandgap.c reg_val); reg_val 798 drivers/tty/serial/sirfsoc_uart.c clk_div_reg = baudrate_to_regv[ic].reg_val; reg_val 396 drivers/tty/serial/sirfsoc_uart.h unsigned int reg_val; reg_val 37 drivers/usb/musb/tusb6010.c #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf) reg_val 38 drivers/usb/musb/tusb6010.c #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf) reg_val 83 drivers/video/backlight/adp5520_bl.c uint8_t reg_val; reg_val 85 drivers/video/backlight/adp5520_bl.c error = adp5520_read(data->master, ADP5520_BL_VALUE, ®_val); reg_val 87 drivers/video/backlight/adp5520_bl.c return error ? data->current_brightness : reg_val; reg_val 147 drivers/video/backlight/adp5520_bl.c uint8_t reg_val; reg_val 150 drivers/video/backlight/adp5520_bl.c ret = adp5520_read(data->master, reg, ®_val); reg_val 156 drivers/video/backlight/adp5520_bl.c return sprintf(buf, "%u\n", reg_val); reg_val 141 drivers/video/backlight/adp8860_bl.c uint8_t reg_val; reg_val 146 drivers/video/backlight/adp8860_bl.c ret = adp8860_read(client, reg, ®_val); reg_val 148 drivers/video/backlight/adp8860_bl.c if (!ret && ((reg_val & bit_mask) != bit_mask)) { reg_val 149 drivers/video/backlight/adp8860_bl.c reg_val |= bit_mask; reg_val 150 drivers/video/backlight/adp8860_bl.c ret = adp8860_write(client, reg, reg_val); reg_val 160 drivers/video/backlight/adp8860_bl.c uint8_t reg_val; reg_val 165 drivers/video/backlight/adp8860_bl.c ret = adp8860_read(client, reg, ®_val); reg_val 167 drivers/video/backlight/adp8860_bl.c if (!ret && (reg_val & bit_mask)) { reg_val 168 drivers/video/backlight/adp8860_bl.c reg_val &= ~bit_mask; reg_val 169 drivers/video/backlight/adp8860_bl.c ret = adp8860_write(client, reg, reg_val); reg_val 433 drivers/video/backlight/adp8860_bl.c uint8_t reg_val; reg_val 436 drivers/video/backlight/adp8860_bl.c error = adp8860_read(data->client, reg, ®_val); reg_val 442 drivers/video/backlight/adp8860_bl.c return sprintf(buf, "%u\n", reg_val); reg_val 563 drivers/video/backlight/adp8860_bl.c uint8_t reg_val; reg_val 567 drivers/video/backlight/adp8860_bl.c error = adp8860_read(data->client, ADP8860_PH1LEVL, ®_val); reg_val 569 drivers/video/backlight/adp8860_bl.c ret_val = reg_val; reg_val 570 drivers/video/backlight/adp8860_bl.c error = adp8860_read(data->client, ADP8860_PH1LEVH, ®_val); reg_val 578 drivers/video/backlight/adp8860_bl.c ret_val += (reg_val & 0x1F) << 8; reg_val 590 drivers/video/backlight/adp8860_bl.c uint8_t reg_val; reg_val 593 drivers/video/backlight/adp8860_bl.c error = adp8860_read(data->client, ADP8860_CFGR, ®_val); reg_val 600 drivers/video/backlight/adp8860_bl.c ((reg_val >> CFGR_BLV_SHIFT) & CFGR_BLV_MASK) + 1); reg_val 609 drivers/video/backlight/adp8860_bl.c uint8_t reg_val; reg_val 625 drivers/video/backlight/adp8860_bl.c ret = adp8860_read(data->client, ADP8860_CFGR, ®_val); reg_val 627 drivers/video/backlight/adp8860_bl.c reg_val &= ~(CFGR_BLV_MASK << CFGR_BLV_SHIFT); reg_val 628 drivers/video/backlight/adp8860_bl.c reg_val |= (val - 1) << CFGR_BLV_SHIFT; reg_val 629 drivers/video/backlight/adp8860_bl.c adp8860_write(data->client, ADP8860_CFGR, reg_val); reg_val 667 drivers/video/backlight/adp8860_bl.c uint8_t reg_val; reg_val 685 drivers/video/backlight/adp8860_bl.c ret = adp8860_read(client, ADP8860_MFDVID, ®_val); reg_val 689 drivers/video/backlight/adp8860_bl.c switch (ADP8860_MANID(reg_val)) { reg_val 706 drivers/video/backlight/adp8860_bl.c data->revid = ADP8860_DEVID(reg_val); reg_val 156 drivers/video/backlight/adp8870_bl.c uint8_t reg_val; reg_val 161 drivers/video/backlight/adp8870_bl.c ret = adp8870_read(client, reg, ®_val); reg_val 163 drivers/video/backlight/adp8870_bl.c if (!ret && ((reg_val & bit_mask) != bit_mask)) { reg_val 164 drivers/video/backlight/adp8870_bl.c reg_val |= bit_mask; reg_val 165 drivers/video/backlight/adp8870_bl.c ret = adp8870_write(client, reg, reg_val); reg_val 175 drivers/video/backlight/adp8870_bl.c uint8_t reg_val; reg_val 180 drivers/video/backlight/adp8870_bl.c ret = adp8870_read(client, reg, ®_val); reg_val 182 drivers/video/backlight/adp8870_bl.c if (!ret && (reg_val & bit_mask)) { reg_val 183 drivers/video/backlight/adp8870_bl.c reg_val &= ~bit_mask; reg_val 184 drivers/video/backlight/adp8870_bl.c ret = adp8870_write(client, reg, reg_val); reg_val 554 drivers/video/backlight/adp8870_bl.c uint8_t reg_val; reg_val 557 drivers/video/backlight/adp8870_bl.c error = adp8870_read(data->client, reg, ®_val); reg_val 563 drivers/video/backlight/adp8870_bl.c return sprintf(buf, "%u\n", reg_val); reg_val 745 drivers/video/backlight/adp8870_bl.c uint8_t reg_val; reg_val 749 drivers/video/backlight/adp8870_bl.c error = adp8870_read(data->client, ADP8870_PH1LEVL, ®_val); reg_val 754 drivers/video/backlight/adp8870_bl.c ret_val = reg_val; reg_val 755 drivers/video/backlight/adp8870_bl.c error = adp8870_read(data->client, ADP8870_PH1LEVH, ®_val); reg_val 762 drivers/video/backlight/adp8870_bl.c ret_val += (reg_val & 0x1F) << 8; reg_val 774 drivers/video/backlight/adp8870_bl.c uint8_t reg_val; reg_val 777 drivers/video/backlight/adp8870_bl.c error = adp8870_read(data->client, ADP8870_CFGR, ®_val); reg_val 784 drivers/video/backlight/adp8870_bl.c ((reg_val >> CFGR_BLV_SHIFT) & CFGR_BLV_MASK) + 1); reg_val 793 drivers/video/backlight/adp8870_bl.c uint8_t reg_val; reg_val 809 drivers/video/backlight/adp8870_bl.c ret = adp8870_read(data->client, ADP8870_CFGR, ®_val); reg_val 811 drivers/video/backlight/adp8870_bl.c reg_val &= ~(CFGR_BLV_MASK << CFGR_BLV_SHIFT); reg_val 812 drivers/video/backlight/adp8870_bl.c reg_val |= (val - 1) << CFGR_BLV_SHIFT; reg_val 813 drivers/video/backlight/adp8870_bl.c adp8870_write(data->client, ADP8870_CFGR, reg_val); reg_val 855 drivers/video/backlight/adp8870_bl.c uint8_t reg_val; reg_val 869 drivers/video/backlight/adp8870_bl.c ret = adp8870_read(client, ADP8870_MFDVID, ®_val); reg_val 873 drivers/video/backlight/adp8870_bl.c if (ADP8870_MANID(reg_val) != ADP8870_MANUFID) { reg_val 882 drivers/video/backlight/adp8870_bl.c data->revid = ADP8870_DEVID(reg_val); reg_val 59 drivers/video/backlight/lm3630a_bl.c unsigned int reg_val; reg_val 61 drivers/video/backlight/lm3630a_bl.c rval = regmap_read(pchip->regmap, reg, ®_val); reg_val 64 drivers/video/backlight/lm3630a_bl.c return reg_val & 0xFF; reg_val 50 drivers/video/backlight/lm3639_bl.c unsigned int reg_val; reg_val 60 drivers/video/backlight/lm3639_bl.c reg_val = (pdata->pin_pwm & 0x40) | pdata->pin_strobe | pdata->pin_tx; reg_val 61 drivers/video/backlight/lm3639_bl.c ret = regmap_update_bits(pchip->regmap, REG_IO_CTRL, 0x7C, reg_val); reg_val 76 drivers/video/backlight/lm3639_bl.c reg_val = pdata->fled_pins; reg_val 77 drivers/video/backlight/lm3639_bl.c reg_val |= pdata->bled_pins; reg_val 79 drivers/video/backlight/lm3639_bl.c reg_val = pdata->fled_pins; reg_val 80 drivers/video/backlight/lm3639_bl.c reg_val |= pdata->bled_pins | 0x01; reg_val 83 drivers/video/backlight/lm3639_bl.c ret = regmap_update_bits(pchip->regmap, REG_ENABLE, 0x79, reg_val); reg_val 97 drivers/video/backlight/lm3639_bl.c unsigned int reg_val; reg_val 101 drivers/video/backlight/lm3639_bl.c ret = regmap_read(pchip->regmap, REG_FLAG, ®_val); reg_val 105 drivers/video/backlight/lm3639_bl.c if (reg_val != 0) reg_val 106 drivers/video/backlight/lm3639_bl.c dev_info(pchip->dev, "last flag is 0x%x\n", reg_val); reg_val 143 drivers/video/backlight/lm3639_bl.c unsigned int reg_val; reg_val 156 drivers/video/backlight/lm3639_bl.c ret = regmap_read(pchip->regmap, REG_BL_CONF_1, ®_val); reg_val 159 drivers/video/backlight/lm3639_bl.c if (reg_val & 0x10) reg_val 160 drivers/video/backlight/lm3639_bl.c ret = regmap_read(pchip->regmap, REG_BL_CONF_4, ®_val); reg_val 162 drivers/video/backlight/lm3639_bl.c ret = regmap_read(pchip->regmap, REG_BL_CONF_3, ®_val); reg_val 165 drivers/video/backlight/lm3639_bl.c bl->props.brightness = reg_val; reg_val 223 drivers/video/backlight/lm3639_bl.c unsigned int reg_val; reg_val 228 drivers/video/backlight/lm3639_bl.c ret = regmap_read(pchip->regmap, REG_FLAG, ®_val); reg_val 231 drivers/video/backlight/lm3639_bl.c if (reg_val != 0) reg_val 232 drivers/video/backlight/lm3639_bl.c dev_info(pchip->dev, "last flag is 0x%x\n", reg_val); reg_val 260 drivers/video/backlight/lm3639_bl.c unsigned int reg_val; reg_val 265 drivers/video/backlight/lm3639_bl.c ret = regmap_read(pchip->regmap, REG_FLAG, ®_val); reg_val 268 drivers/video/backlight/lm3639_bl.c if (reg_val != 0) reg_val 269 drivers/video/backlight/lm3639_bl.c dev_info(pchip->dev, "last flag is 0x%x\n", reg_val); reg_val 242 drivers/video/fbdev/aty/radeon_base.c static reg_val common_regs[] = { reg_val 1133 drivers/video/fbdev/via/viafbdev.c u8 reg_val = 0; reg_val 1145 drivers/video/fbdev/via/viafbdev.c if (kstrtou8(value, 0, ®_val) < 0) reg_val 1148 drivers/video/fbdev/via/viafbdev.c reg_val); reg_val 1152 drivers/video/fbdev/via/viafbdev.c reg_val, 0x0f); reg_val 1156 drivers/video/fbdev/via/viafbdev.c reg_val << 4, BIT5); reg_val 1158 drivers/video/fbdev/via/viafbdev.c reg_val << 1, BIT1); reg_val 1162 drivers/video/fbdev/via/viafbdev.c reg_val << 3, BIT4); reg_val 1164 drivers/video/fbdev/via/viafbdev.c reg_val << 2, BIT2); reg_val 1204 drivers/video/fbdev/via/viafbdev.c u8 reg_val = 0; reg_val 1216 drivers/video/fbdev/via/viafbdev.c if (kstrtou8(value, 0, ®_val) < 0) reg_val 1221 drivers/video/fbdev/via/viafbdev.c reg_val, 0x0f); reg_val 1225 drivers/video/fbdev/via/viafbdev.c reg_val << 2, 0x0c); reg_val 1229 drivers/video/fbdev/via/viafbdev.c reg_val, 0x03); reg_val 1267 drivers/video/fbdev/via/viafbdev.c u8 reg_val; reg_val 1268 drivers/video/fbdev/via/viafbdev.c err = kstrtou8_from_user(buffer, count, 0, ®_val); reg_val 1272 drivers/video/fbdev/via/viafbdev.c viafb_write_reg_mask(CR97, VIACR, reg_val, 0x0f); reg_val 1302 drivers/video/fbdev/via/viafbdev.c u8 reg_val; reg_val 1303 drivers/video/fbdev/via/viafbdev.c err = kstrtou8_from_user(buffer, count, 0, ®_val); reg_val 1307 drivers/video/fbdev/via/viafbdev.c viafb_write_reg_mask(CR99, VIACR, reg_val, 0x0f); reg_val 1361 drivers/video/fbdev/via/viafbdev.c struct IODATA reg_val; reg_val 1375 drivers/video/fbdev/via/viafbdev.c if (kstrtou8(value, 0, ®_val.Data) < 0) reg_val 1379 drivers/video/fbdev/via/viafbdev.c reg_val.Index = 0x08; reg_val 1380 drivers/video/fbdev/via/viafbdev.c reg_val.Mask = 0x0f; reg_val 1385 drivers/video/fbdev/via/viafbdev.c reg_val); reg_val 1388 drivers/video/fbdev/via/viafbdev.c reg_val.Index = 0x09; reg_val 1389 drivers/video/fbdev/via/viafbdev.c reg_val.Mask = 0x1f; reg_val 1394 drivers/video/fbdev/via/viafbdev.c reg_val); reg_val 1412 drivers/video/fbdev/via/viafbdev.c if (kstrtou8(value, 0, ®_val.Data) < 0) reg_val 1416 drivers/video/fbdev/via/viafbdev.c reg_val.Index = 0x08; reg_val 1417 drivers/video/fbdev/via/viafbdev.c reg_val.Mask = 0x0f; reg_val 1422 drivers/video/fbdev/via/viafbdev.c reg_val); reg_val 1425 drivers/video/fbdev/via/viafbdev.c reg_val.Index = 0x09; reg_val 1426 drivers/video/fbdev/via/viafbdev.c reg_val.Mask = 0x1f; reg_val 1431 drivers/video/fbdev/via/viafbdev.c reg_val); reg_val 34 drivers/watchdog/da9052_wdt.c u8 reg_val; reg_val 84 drivers/watchdog/da9052_wdt.c da9052_wdt_maps[i].reg_val); reg_val 37 drivers/watchdog/da9055_wdt.c u8 reg_val; reg_val 68 drivers/watchdog/da9055_wdt.c da9055_wdt_maps[i].reg_val << reg_val 38 drivers/watchdog/rn5t618_wdt.c u8 reg_val; reg_val 63 drivers/watchdog/rn5t618_wdt.c rn5t618_wdt_map[i].reg_val); reg_val 652 include/linux/mfd/axp20x.h unsigned int reg_val, result; reg_val 655 include/linux/mfd/axp20x.h err = regmap_read(regmap, reg, ®_val); reg_val 659 include/linux/mfd/axp20x.h result = reg_val << (width - 8); reg_val 661 include/linux/mfd/axp20x.h err = regmap_read(regmap, reg + 1, ®_val); reg_val 665 include/linux/mfd/axp20x.h result |= reg_val; reg_val 186 include/linux/mfd/da9052/da9052.h unsigned char reg_val) reg_val 190 include/linux/mfd/da9052/da9052.h ret = regmap_update_bits(da9052->regmap, reg, bit_mask, reg_val); reg_val 69 include/linux/mfd/da9055/core.h unsigned char reg_val) reg_val 71 include/linux/mfd/da9055/core.h return regmap_update_bits(da9055->regmap, reg, bit_mask, reg_val); reg_val 126 sound/drivers/opl3/opl3_drums.c unsigned char reg_val; reg_val 130 sound/drivers/opl3/opl3_drums.c reg_val = data->ksl_level; reg_val 131 sound/drivers/opl3/opl3_drums.c snd_opl3_calc_volume(®_val, vel, chan); reg_val 133 sound/drivers/opl3/opl3_drums.c opl3->command(opl3, opl3_reg, reg_val); reg_val 137 sound/drivers/opl3/opl3_drums.c reg_val = data->feedback_connection | OPL3_STEREO_BITS; reg_val 139 sound/drivers/opl3/opl3_drums.c reg_val &= ~OPL3_VOICE_TO_RIGHT; reg_val 141 sound/drivers/opl3/opl3_drums.c reg_val &= ~OPL3_VOICE_TO_LEFT; reg_val 143 sound/drivers/opl3/opl3_drums.c opl3->command(opl3, opl3_reg, reg_val); reg_val 293 sound/drivers/opl3/opl3_midi.c unsigned char reg_val; reg_val 396 sound/drivers/opl3/opl3_midi.c reg_val = vp->keyon_reg & ~OPL3_KEYON_BIT; reg_val 397 sound/drivers/opl3/opl3_midi.c opl3->command(opl3, opl3_reg, reg_val); reg_val 404 sound/drivers/opl3/opl3_midi.c reg_val = vp->keyon_reg & ~OPL3_KEYON_BIT; reg_val 405 sound/drivers/opl3/opl3_midi.c opl3->command(opl3, opl3_reg, reg_val); reg_val 467 sound/drivers/opl3/opl3_midi.c reg_val = fm->op[i].am_vib; reg_val 469 sound/drivers/opl3/opl3_midi.c opl3->command(opl3, opl3_reg, reg_val); reg_val 472 sound/drivers/opl3/opl3_midi.c reg_val = vol_op[i]; reg_val 474 sound/drivers/opl3/opl3_midi.c opl3->command(opl3, opl3_reg, reg_val); reg_val 477 sound/drivers/opl3/opl3_midi.c reg_val = fm->op[i].attack_decay; reg_val 479 sound/drivers/opl3/opl3_midi.c opl3->command(opl3, opl3_reg, reg_val); reg_val 482 sound/drivers/opl3/opl3_midi.c reg_val = fm->op[i].sustain_release; reg_val 484 sound/drivers/opl3/opl3_midi.c opl3->command(opl3, opl3_reg, reg_val); reg_val 487 sound/drivers/opl3/opl3_midi.c reg_val = fm->op[i].wave_select; reg_val 489 sound/drivers/opl3/opl3_midi.c opl3->command(opl3, opl3_reg, reg_val); reg_val 493 sound/drivers/opl3/opl3_midi.c reg_val = fm->feedback_connection[0]; reg_val 495 sound/drivers/opl3/opl3_midi.c reg_val |= OPL3_STEREO_BITS; reg_val 497 sound/drivers/opl3/opl3_midi.c reg_val &= ~OPL3_VOICE_TO_RIGHT; reg_val 499 sound/drivers/opl3/opl3_midi.c reg_val &= ~OPL3_VOICE_TO_LEFT; reg_val 501 sound/drivers/opl3/opl3_midi.c opl3->command(opl3, opl3_reg, reg_val); reg_val 505 sound/drivers/opl3/opl3_midi.c reg_val = fm->feedback_connection[1] & OPL3_CONNECTION_BIT; reg_val 507 sound/drivers/opl3/opl3_midi.c reg_val |= OPL3_STEREO_BITS; reg_val 509 sound/drivers/opl3/opl3_midi.c reg_val &= ~OPL3_VOICE_TO_RIGHT; reg_val 511 sound/drivers/opl3/opl3_midi.c reg_val &= ~OPL3_VOICE_TO_LEFT; reg_val 514 sound/drivers/opl3/opl3_midi.c opl3->command(opl3, opl3_reg, reg_val); reg_val 394 sound/drivers/opl3/opl3_synth.c unsigned char reg_val; reg_val 414 sound/drivers/opl3/opl3_synth.c reg_val = (unsigned char) note->fnum; reg_val 416 sound/drivers/opl3/opl3_synth.c opl3->command(opl3, opl3_reg, reg_val); reg_val 418 sound/drivers/opl3/opl3_synth.c reg_val = 0x00; reg_val 421 sound/drivers/opl3/opl3_synth.c reg_val |= OPL3_KEYON_BIT; reg_val 423 sound/drivers/opl3/opl3_synth.c reg_val |= (note->octave << 2) & OPL3_BLOCKNUM_MASK; reg_val 425 sound/drivers/opl3/opl3_synth.c reg_val |= (unsigned char) (note->fnum >> 8) & OPL3_FNUM_HIGH_MASK; reg_val 429 sound/drivers/opl3/opl3_synth.c opl3->command(opl3, opl3_reg, reg_val); reg_val 442 sound/drivers/opl3/opl3_synth.c unsigned char reg_val; reg_val 468 sound/drivers/opl3/opl3_synth.c reg_val = 0x00; reg_val 471 sound/drivers/opl3/opl3_synth.c reg_val |= OPL3_TREMOLO_ON; reg_val 474 sound/drivers/opl3/opl3_synth.c reg_val |= OPL3_VIBRATO_ON; reg_val 477 sound/drivers/opl3/opl3_synth.c reg_val |= OPL3_SUSTAIN_ON; reg_val 480 sound/drivers/opl3/opl3_synth.c reg_val |= OPL3_KSR; reg_val 482 sound/drivers/opl3/opl3_synth.c reg_val |= voice->harmonic & OPL3_MULTIPLE_MASK; reg_val 486 sound/drivers/opl3/opl3_synth.c opl3->command(opl3, opl3_reg, reg_val); reg_val 489 sound/drivers/opl3/opl3_synth.c reg_val = (voice->scale_level << 6) & OPL3_KSL_MASK; reg_val 491 sound/drivers/opl3/opl3_synth.c reg_val |= ~voice->volume & OPL3_TOTAL_LEVEL_MASK; reg_val 495 sound/drivers/opl3/opl3_synth.c opl3->command(opl3, opl3_reg, reg_val); reg_val 498 sound/drivers/opl3/opl3_synth.c reg_val = (voice->attack << 4) & OPL3_ATTACK_MASK; reg_val 500 sound/drivers/opl3/opl3_synth.c reg_val |= voice->decay & OPL3_DECAY_MASK; reg_val 504 sound/drivers/opl3/opl3_synth.c opl3->command(opl3, opl3_reg, reg_val); reg_val 507 sound/drivers/opl3/opl3_synth.c reg_val = (voice->sustain << 4) & OPL3_SUSTAIN_MASK; reg_val 509 sound/drivers/opl3/opl3_synth.c reg_val |= voice->release & OPL3_RELEASE_MASK; reg_val 513 sound/drivers/opl3/opl3_synth.c opl3->command(opl3, opl3_reg, reg_val); reg_val 516 sound/drivers/opl3/opl3_synth.c reg_val = (voice->feedback << 1) & OPL3_FEEDBACK_MASK; reg_val 519 sound/drivers/opl3/opl3_synth.c reg_val |= OPL3_CONNECTION_BIT; reg_val 523 sound/drivers/opl3/opl3_synth.c reg_val |= OPL3_VOICE_TO_LEFT; reg_val 525 sound/drivers/opl3/opl3_synth.c reg_val |= OPL3_VOICE_TO_RIGHT; reg_val 529 sound/drivers/opl3/opl3_synth.c opl3->command(opl3, opl3_reg, reg_val); reg_val 532 sound/drivers/opl3/opl3_synth.c reg_val = voice->waveform & OPL3_WAVE_SELECT_MASK; reg_val 534 sound/drivers/opl3/opl3_synth.c opl3->command(opl3, opl3_reg, reg_val); reg_val 541 sound/drivers/opl3/opl3_synth.c unsigned char reg_val; reg_val 543 sound/drivers/opl3/opl3_synth.c reg_val = 0x00; reg_val 546 sound/drivers/opl3/opl3_synth.c reg_val |= OPL3_KEYBOARD_SPLIT; reg_val 547 sound/drivers/opl3/opl3_synth.c opl3->command(opl3, OPL3_LEFT | OPL3_REG_KBD_SPLIT, reg_val); reg_val 549 sound/drivers/opl3/opl3_synth.c reg_val = 0x00; reg_val 552 sound/drivers/opl3/opl3_synth.c reg_val |= OPL3_TREMOLO_DEPTH; reg_val 555 sound/drivers/opl3/opl3_synth.c reg_val |= OPL3_VIBRATO_DEPTH; reg_val 558 sound/drivers/opl3/opl3_synth.c reg_val |= OPL3_PERCUSSION_ENABLE; reg_val 565 sound/drivers/opl3/opl3_synth.c reg_val |= OPL3_BASSDRUM_ON; reg_val 567 sound/drivers/opl3/opl3_synth.c reg_val |= OPL3_SNAREDRUM_ON; reg_val 569 sound/drivers/opl3/opl3_synth.c reg_val |= OPL3_TOMTOM_ON; reg_val 571 sound/drivers/opl3/opl3_synth.c reg_val |= OPL3_CYMBAL_ON; reg_val 573 sound/drivers/opl3/opl3_synth.c reg_val |= OPL3_HIHAT_ON; reg_val 575 sound/drivers/opl3/opl3_synth.c opl3->command(opl3, OPL3_LEFT | OPL3_REG_PERCUSSION, reg_val); reg_val 593 sound/drivers/opl3/opl3_synth.c unsigned char reg_val; reg_val 599 sound/drivers/opl3/opl3_synth.c reg_val = connection & (OPL3_RIGHT_4OP_0 | OPL3_RIGHT_4OP_1 | OPL3_RIGHT_4OP_2 | reg_val 602 sound/drivers/opl3/opl3_synth.c opl3->command(opl3, OPL3_RIGHT | OPL3_REG_CONNECTION_SELECT, reg_val); reg_val 431 sound/pci/aw2/aw2-saa7146.c unsigned int reg_val = READREG(GPIO_CTRL); reg_val 432 sound/pci/aw2/aw2-saa7146.c if ((reg_val & 0xFF) == 0x40) reg_val 655 sound/pci/azt3328.c unsigned short reg_val = 0; reg_val 664 sound/pci/azt3328.c reg_val = snd_azf3328_mixer_inw(chip, reg_val 681 sound/pci/azt3328.c reg_val |= azf_emulated_ac97_caps; reg_val 684 sound/pci/azt3328.c reg_val |= azf_emulated_ac97_powerdown; reg_val 689 sound/pci/azt3328.c reg_val |= 0; reg_val 692 sound/pci/azt3328.c reg_val = azf_emulated_ac97_vendor_id >> 16; reg_val 695 sound/pci/azt3328.c reg_val = azf_emulated_ac97_vendor_id & 0xffff; reg_val 706 sound/pci/azt3328.c return reg_val; reg_val 193 sound/soc/codecs/da7213.c static int da7213_get_alc_data(struct snd_soc_component *component, u8 reg_val) reg_val 202 sound/soc/codecs/da7213.c snd_soc_component_write(component, DA7213_ALC_CIC_OP_LVL_CTRL, reg_val); reg_val 206 sound/soc/codecs/da7213.c reg_val | DA7213_ALC_DATA_MIDDLE); reg_val 211 sound/soc/codecs/da7213.c reg_val | DA7213_ALC_DATA_TOP); reg_val 222 sound/soc/codecs/da7213.c u8 reg_val; reg_val 237 sound/soc/codecs/da7213.c reg_val = (offset_l & DA7213_ALC_OFFSET_15_8) >> 8; reg_val 238 sound/soc/codecs/da7213.c snd_soc_component_write(component, DA7213_ALC_OFFSET_MAN_M_L, reg_val); reg_val 239 sound/soc/codecs/da7213.c reg_val = (offset_l & DA7213_ALC_OFFSET_19_16) >> 16; reg_val 240 sound/soc/codecs/da7213.c snd_soc_component_write(component, DA7213_ALC_OFFSET_MAN_U_L, reg_val); reg_val 242 sound/soc/codecs/da7213.c reg_val = (offset_r & DA7213_ALC_OFFSET_15_8) >> 8; reg_val 243 sound/soc/codecs/da7213.c snd_soc_component_write(component, DA7213_ALC_OFFSET_MAN_M_R, reg_val); reg_val 244 sound/soc/codecs/da7213.c reg_val = (offset_r & DA7213_ALC_OFFSET_19_16) >> 16; reg_val 245 sound/soc/codecs/da7213.c snd_soc_component_write(component, DA7213_ALC_OFFSET_MAN_U_R, reg_val); reg_val 450 sound/soc/codecs/da9055.c static int da9055_get_alc_data(struct snd_soc_component *component, u8 reg_val) reg_val 459 sound/soc/codecs/da9055.c snd_soc_component_write(component, DA9055_ALC_CIC_OP_LVL_CTRL, reg_val); reg_val 463 sound/soc/codecs/da9055.c reg_val | DA9055_ALC_DATA_MIDDLE); reg_val 468 sound/soc/codecs/da9055.c reg_val | DA9055_ALC_DATA_TOP); reg_val 481 sound/soc/codecs/da9055.c u8 reg_val, adc_left, adc_right, mic_left, mic_right; reg_val 522 sound/soc/codecs/da9055.c reg_val = (offset_l & DA9055_ALC_OFFSET_15_8) >> 8; reg_val 523 sound/soc/codecs/da9055.c snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2M_L, reg_val); reg_val 524 sound/soc/codecs/da9055.c reg_val = (offset_l & DA9055_ALC_OFFSET_17_16) >> 16; reg_val 525 sound/soc/codecs/da9055.c snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2U_L, reg_val); reg_val 527 sound/soc/codecs/da9055.c reg_val = (offset_r & DA9055_ALC_OFFSET_15_8) >> 8; reg_val 528 sound/soc/codecs/da9055.c snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2M_R, reg_val); reg_val 529 sound/soc/codecs/da9055.c reg_val = (offset_r & DA9055_ALC_OFFSET_17_16) >> 16; reg_val 530 sound/soc/codecs/da9055.c snd_soc_component_write(component, DA9055_ALC_OFFSET_OP2U_R, reg_val); reg_val 459 sound/soc/codecs/msm8916-wcd-analog.c u32 coarse, fine, reg_val, reg_addr; reg_val 491 sound/soc/codecs/msm8916-wcd-analog.c reg_val = (coarse << CDC_A_MBHC_BTN_VREF_COARSE_SHIFT) | reg_val 495 sound/soc/codecs/msm8916-wcd-analog.c reg_val); reg_val 170 sound/soc/codecs/nau8810.c int i, reg, reg_val; reg_val 176 sound/soc/codecs/nau8810.c regmap_read(nau8810->regmap, reg + i, ®_val); reg_val 180 sound/soc/codecs/nau8810.c reg_val = cpu_to_be16(reg_val); reg_val 181 sound/soc/codecs/nau8810.c memcpy(val + i, ®_val, sizeof(reg_val)); reg_val 186 sound/soc/codecs/nau8822.c u16 reg_val, *val; reg_val 191 sound/soc/codecs/nau8822.c reg_val = snd_soc_component_read32(component, reg + i); reg_val 195 sound/soc/codecs/nau8822.c reg_val = cpu_to_be16(reg_val); reg_val 196 sound/soc/codecs/nau8822.c memcpy(val + i, ®_val, sizeof(reg_val)); reg_val 1633 sound/soc/codecs/rt1011.c unsigned int reg_val = 0, reg_bclk_inv = 0; reg_val 1639 sound/soc/codecs/rt1011.c reg_val |= RT1011_I2S_TDM_MS_S; reg_val 1659 sound/soc/codecs/rt1011.c reg_val |= RT1011_I2S_TDM_DF_LEFT; reg_val 1662 sound/soc/codecs/rt1011.c reg_val |= RT1011_I2S_TDM_DF_PCM_A; reg_val 1665 sound/soc/codecs/rt1011.c reg_val |= RT1011_I2S_TDM_DF_PCM_B; reg_val 1675 sound/soc/codecs/rt1011.c reg_val); reg_val 1694 sound/soc/codecs/rt1011.c unsigned int reg_val = 0; reg_val 1705 sound/soc/codecs/rt1011.c reg_val |= RT1011_FS_SYS_PRE_MCLK; reg_val 1710 sound/soc/codecs/rt1011.c reg_val |= RT1011_FS_SYS_PRE_BCLK; reg_val 1713 sound/soc/codecs/rt1011.c reg_val |= RT1011_FS_SYS_PRE_PLL1; reg_val 1716 sound/soc/codecs/rt1011.c reg_val |= RT1011_FS_SYS_PRE_RCCLK; reg_val 1723 sound/soc/codecs/rt1011.c RT1011_FS_SYS_PRE_MASK, reg_val); reg_val 699 sound/soc/codecs/rt1305.c unsigned int reg_val = 0, reg1_val = 0; reg_val 703 sound/soc/codecs/rt1305.c reg_val |= RT1305_SEL_I2S_OUT_MODE_M; reg_val 707 sound/soc/codecs/rt1305.c reg_val |= RT1305_SEL_I2S_OUT_MODE_S; reg_val 743 sound/soc/codecs/rt1305.c RT1305_SEL_I2S_OUT_MODE_MASK, reg_val); reg_val 759 sound/soc/codecs/rt1305.c unsigned int reg_val = 0; reg_val 766 sound/soc/codecs/rt1305.c reg_val |= RT1305_SEL_FS_SYS_PRE_MCLK; reg_val 772 sound/soc/codecs/rt1305.c reg_val |= RT1305_SEL_FS_SYS_PRE_PLL; reg_val 775 sound/soc/codecs/rt1305.c reg_val |= RT1305_SEL_FS_SYS_PRE_RCCLK; reg_val 782 sound/soc/codecs/rt1305.c RT1305_SEL_FS_SYS_PRE_MASK, reg_val); reg_val 525 sound/soc/codecs/rt1308.c unsigned int reg_val = 0, reg1_val = 0; reg_val 539 sound/soc/codecs/rt1308.c reg_val |= RT1308_I2S_DF_SEL_LEFT; reg_val 542 sound/soc/codecs/rt1308.c reg_val |= RT1308_I2S_DF_SEL_PCM_A; reg_val 545 sound/soc/codecs/rt1308.c reg_val |= RT1308_I2S_DF_SEL_PCM_B; reg_val 565 sound/soc/codecs/rt1308.c reg_val); reg_val 581 sound/soc/codecs/rt1308.c unsigned int reg_val = 0; reg_val 588 sound/soc/codecs/rt1308.c reg_val |= RT1308_SEL_FS_SYS_SRC_MCLK; reg_val 594 sound/soc/codecs/rt1308.c reg_val |= RT1308_SEL_FS_SYS_SRC_BCLK; reg_val 597 sound/soc/codecs/rt1308.c reg_val |= RT1308_SEL_FS_SYS_SRC_PLL; reg_val 600 sound/soc/codecs/rt1308.c reg_val |= RT1308_SEL_FS_SYS_SRC_RCCLK; reg_val 607 sound/soc/codecs/rt1308.c RT1308_SEL_FS_SYS_MASK, reg_val); reg_val 813 sound/soc/codecs/rt5514.c unsigned int reg_val = 0; reg_val 820 sound/soc/codecs/rt5514.c reg_val |= RT5514_I2S_LR_INV; reg_val 824 sound/soc/codecs/rt5514.c reg_val |= RT5514_I2S_BP_INV; reg_val 828 sound/soc/codecs/rt5514.c reg_val |= RT5514_I2S_BP_INV | RT5514_I2S_LR_INV; reg_val 840 sound/soc/codecs/rt5514.c reg_val |= RT5514_I2S_DF_LEFT; reg_val 844 sound/soc/codecs/rt5514.c reg_val |= RT5514_I2S_DF_PCM_A; reg_val 848 sound/soc/codecs/rt5514.c reg_val |= RT5514_I2S_DF_PCM_B; reg_val 857 sound/soc/codecs/rt5514.c reg_val); reg_val 867 sound/soc/codecs/rt5514.c unsigned int reg_val = 0; reg_val 874 sound/soc/codecs/rt5514.c reg_val |= RT5514_CLK_SYS_PRE_SEL_MCLK; reg_val 878 sound/soc/codecs/rt5514.c reg_val |= RT5514_CLK_SYS_PRE_SEL_PLL; reg_val 887 sound/soc/codecs/rt5514.c RT5514_CLK_SYS_PRE_SEL_MASK, reg_val); reg_val 1015 sound/soc/codecs/rt5616.c unsigned int reg_val = 0; reg_val 1022 sound/soc/codecs/rt5616.c reg_val |= RT5616_I2S_MS_S; reg_val 1033 sound/soc/codecs/rt5616.c reg_val |= RT5616_I2S_BP_INV; reg_val 1043 sound/soc/codecs/rt5616.c reg_val |= RT5616_I2S_DF_LEFT; reg_val 1046 sound/soc/codecs/rt5616.c reg_val |= RT5616_I2S_DF_PCM_A; reg_val 1049 sound/soc/codecs/rt5616.c reg_val |= RT5616_I2S_DF_PCM_B; reg_val 1057 sound/soc/codecs/rt5616.c RT5616_I2S_DF_MASK, reg_val); reg_val 1067 sound/soc/codecs/rt5616.c unsigned int reg_val = 0; reg_val 1074 sound/soc/codecs/rt5616.c reg_val |= RT5616_SCLK_SRC_MCLK; reg_val 1077 sound/soc/codecs/rt5616.c reg_val |= RT5616_SCLK_SRC_PLL1; reg_val 1085 sound/soc/codecs/rt5616.c RT5616_SCLK_SRC_MASK, reg_val); reg_val 1209 sound/soc/codecs/rt5631.c u16 reg_val; reg_val 1216 sound/soc/codecs/rt5631.c u16 reg_val; reg_val 1395 sound/soc/codecs/rt5631.c coeff_div[coeff].reg_val); reg_val 1494 sound/soc/codecs/rt5631.c codec_master_pll_div[i].reg_val); reg_val 1513 sound/soc/codecs/rt5631.c codec_slave_pll_div[i].reg_val); reg_val 1773 sound/soc/codecs/rt5640.c unsigned int reg_val = 0; reg_val 1781 sound/soc/codecs/rt5640.c reg_val |= RT5640_I2S_MS_S; reg_val 1792 sound/soc/codecs/rt5640.c reg_val |= RT5640_I2S_BP_INV; reg_val 1802 sound/soc/codecs/rt5640.c reg_val |= RT5640_I2S_DF_LEFT; reg_val 1805 sound/soc/codecs/rt5640.c reg_val |= RT5640_I2S_DF_PCM_A; reg_val 1808 sound/soc/codecs/rt5640.c reg_val |= RT5640_I2S_DF_PCM_B; reg_val 1822 sound/soc/codecs/rt5640.c RT5640_I2S_DF_MASK, reg_val); reg_val 1827 sound/soc/codecs/rt5640.c RT5640_I2S_DF_MASK, reg_val); reg_val 1838 sound/soc/codecs/rt5640.c unsigned int reg_val = 0; reg_val 1846 sound/soc/codecs/rt5640.c reg_val |= RT5640_SCLK_SRC_MCLK; reg_val 1849 sound/soc/codecs/rt5640.c reg_val |= RT5640_SCLK_SRC_PLL1; reg_val 1853 sound/soc/codecs/rt5640.c reg_val |= RT5640_SCLK_SRC_RCCLK; reg_val 1862 sound/soc/codecs/rt5640.c RT5640_SCLK_SRC_MASK, reg_val); reg_val 2812 sound/soc/codecs/rt5645.c unsigned int reg_val = 0, pol_sft; reg_val 2828 sound/soc/codecs/rt5645.c reg_val |= RT5645_I2S_MS_S; reg_val 2839 sound/soc/codecs/rt5645.c reg_val |= (1 << pol_sft); reg_val 2849 sound/soc/codecs/rt5645.c reg_val |= RT5645_I2S_DF_LEFT; reg_val 2852 sound/soc/codecs/rt5645.c reg_val |= RT5645_I2S_DF_PCM_A; reg_val 2855 sound/soc/codecs/rt5645.c reg_val |= RT5645_I2S_DF_PCM_B; reg_val 2864 sound/soc/codecs/rt5645.c RT5645_I2S_DF_MASK, reg_val); reg_val 2869 sound/soc/codecs/rt5645.c RT5645_I2S_DF_MASK, reg_val); reg_val 2883 sound/soc/codecs/rt5645.c unsigned int reg_val = 0; reg_val 2890 sound/soc/codecs/rt5645.c reg_val |= RT5645_SCLK_SRC_MCLK; reg_val 2893 sound/soc/codecs/rt5645.c reg_val |= RT5645_SCLK_SRC_PLL1; reg_val 2896 sound/soc/codecs/rt5645.c reg_val |= RT5645_SCLK_SRC_RCCLK; reg_val 2903 sound/soc/codecs/rt5645.c RT5645_SCLK_SRC_MASK, reg_val); reg_val 1352 sound/soc/codecs/rt5651.c unsigned int reg_val = 0; reg_val 1359 sound/soc/codecs/rt5651.c reg_val |= RT5651_I2S_MS_S; reg_val 1370 sound/soc/codecs/rt5651.c reg_val |= RT5651_I2S_BP_INV; reg_val 1380 sound/soc/codecs/rt5651.c reg_val |= RT5651_I2S_DF_LEFT; reg_val 1383 sound/soc/codecs/rt5651.c reg_val |= RT5651_I2S_DF_PCM_A; reg_val 1386 sound/soc/codecs/rt5651.c reg_val |= RT5651_I2S_DF_PCM_B; reg_val 1396 sound/soc/codecs/rt5651.c RT5651_I2S_DF_MASK, reg_val); reg_val 1401 sound/soc/codecs/rt5651.c RT5651_I2S_DF_MASK, reg_val); reg_val 1415 sound/soc/codecs/rt5651.c unsigned int reg_val = 0; reg_val 1423 sound/soc/codecs/rt5651.c reg_val |= RT5651_SCLK_SRC_MCLK; reg_val 1426 sound/soc/codecs/rt5651.c reg_val |= RT5651_SCLK_SRC_PLL1; reg_val 1430 sound/soc/codecs/rt5651.c reg_val |= RT5651_SCLK_SRC_RCCLK; reg_val 1439 sound/soc/codecs/rt5651.c RT5651_SCLK_SRC_MASK, reg_val); reg_val 3398 sound/soc/codecs/rt5659.c unsigned int reg_val = 0; reg_val 3405 sound/soc/codecs/rt5659.c reg_val |= RT5659_I2S_MS_S; reg_val 3416 sound/soc/codecs/rt5659.c reg_val |= RT5659_I2S_BP_INV; reg_val 3426 sound/soc/codecs/rt5659.c reg_val |= RT5659_I2S_DF_LEFT; reg_val 3429 sound/soc/codecs/rt5659.c reg_val |= RT5659_I2S_DF_PCM_A; reg_val 3432 sound/soc/codecs/rt5659.c reg_val |= RT5659_I2S_DF_PCM_B; reg_val 3442 sound/soc/codecs/rt5659.c RT5659_I2S_DF_MASK, reg_val); reg_val 3447 sound/soc/codecs/rt5659.c RT5659_I2S_DF_MASK, reg_val); reg_val 3452 sound/soc/codecs/rt5659.c RT5659_I2S_DF_MASK, reg_val); reg_val 3465 sound/soc/codecs/rt5659.c unsigned int reg_val = 0; reg_val 3472 sound/soc/codecs/rt5659.c reg_val |= RT5659_SCLK_SRC_MCLK; reg_val 3475 sound/soc/codecs/rt5659.c reg_val |= RT5659_SCLK_SRC_PLL1; reg_val 3478 sound/soc/codecs/rt5659.c reg_val |= RT5659_SCLK_SRC_RCCLK; reg_val 3485 sound/soc/codecs/rt5659.c RT5659_SCLK_SRC_MASK, reg_val); reg_val 907 sound/soc/codecs/rt5660.c unsigned int reg_val = 0; reg_val 915 sound/soc/codecs/rt5660.c reg_val |= RT5660_I2S_MS_S; reg_val 928 sound/soc/codecs/rt5660.c reg_val |= RT5660_I2S_BP_INV; reg_val 940 sound/soc/codecs/rt5660.c reg_val |= RT5660_I2S_DF_LEFT; reg_val 944 sound/soc/codecs/rt5660.c reg_val |= RT5660_I2S_DF_PCM_A; reg_val 948 sound/soc/codecs/rt5660.c reg_val |= RT5660_I2S_DF_PCM_B; reg_val 959 sound/soc/codecs/rt5660.c RT5660_I2S_DF_MASK, reg_val); reg_val 975 sound/soc/codecs/rt5660.c unsigned int reg_val = 0; reg_val 982 sound/soc/codecs/rt5660.c reg_val |= RT5660_SCLK_SRC_MCLK; reg_val 986 sound/soc/codecs/rt5660.c reg_val |= RT5660_SCLK_SRC_PLL1; reg_val 990 sound/soc/codecs/rt5660.c reg_val |= RT5660_SCLK_SRC_RCCLK; reg_val 999 sound/soc/codecs/rt5660.c reg_val); reg_val 2813 sound/soc/codecs/rt5663.c unsigned int reg_val = 0; reg_val 2819 sound/soc/codecs/rt5663.c reg_val |= RT5663_I2S_MS_S; reg_val 2829 sound/soc/codecs/rt5663.c reg_val |= RT5663_I2S_BP_INV; reg_val 2839 sound/soc/codecs/rt5663.c reg_val |= RT5663_I2S_DF_LEFT; reg_val 2842 sound/soc/codecs/rt5663.c reg_val |= RT5663_I2S_DF_PCM_A; reg_val 2845 sound/soc/codecs/rt5663.c reg_val |= RT5663_I2S_DF_PCM_B; reg_val 2852 sound/soc/codecs/rt5663.c RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val); reg_val 2862 sound/soc/codecs/rt5663.c unsigned int reg_val = 0; reg_val 2869 sound/soc/codecs/rt5663.c reg_val |= RT5663_SCLK_SRC_MCLK; reg_val 2872 sound/soc/codecs/rt5663.c reg_val |= RT5663_SCLK_SRC_PLL1; reg_val 2875 sound/soc/codecs/rt5663.c reg_val |= RT5663_SCLK_SRC_RCCLK; reg_val 2882 sound/soc/codecs/rt5663.c reg_val); reg_val 4220 sound/soc/codecs/rt5665.c unsigned int reg_val = 0; reg_val 4227 sound/soc/codecs/rt5665.c reg_val |= RT5665_I2S_MS_S; reg_val 4238 sound/soc/codecs/rt5665.c reg_val |= RT5665_I2S_BP_INV; reg_val 4248 sound/soc/codecs/rt5665.c reg_val |= RT5665_I2S_DF_LEFT; reg_val 4251 sound/soc/codecs/rt5665.c reg_val |= RT5665_I2S_DF_PCM_A; reg_val 4254 sound/soc/codecs/rt5665.c reg_val |= RT5665_I2S_DF_PCM_B; reg_val 4265 sound/soc/codecs/rt5665.c RT5665_I2S_DF_MASK, reg_val); reg_val 4271 sound/soc/codecs/rt5665.c RT5665_I2S_DF_MASK, reg_val); reg_val 4276 sound/soc/codecs/rt5665.c RT5665_I2S_DF_MASK, reg_val); reg_val 4289 sound/soc/codecs/rt5665.c unsigned int reg_val = 0, src = 0; reg_val 4296 sound/soc/codecs/rt5665.c reg_val |= RT5665_SCLK_SRC_MCLK; reg_val 4300 sound/soc/codecs/rt5665.c reg_val |= RT5665_SCLK_SRC_PLL1; reg_val 4304 sound/soc/codecs/rt5665.c reg_val |= RT5665_SCLK_SRC_RCCLK; reg_val 4312 sound/soc/codecs/rt5665.c RT5665_SCLK_SRC_MASK, reg_val); reg_val 2008 sound/soc/codecs/rt5668.c unsigned int reg_val = 0, tdm_ctrl = 0; reg_val 2025 sound/soc/codecs/rt5668.c reg_val |= RT5668_I2S_BP_INV; reg_val 2049 sound/soc/codecs/rt5668.c reg_val |= RT5668_I2S_DF_LEFT; reg_val 2053 sound/soc/codecs/rt5668.c reg_val |= RT5668_I2S_DF_PCM_A; reg_val 2057 sound/soc/codecs/rt5668.c reg_val |= RT5668_I2S_DF_PCM_B; reg_val 2067 sound/soc/codecs/rt5668.c RT5668_I2S_DF_MASK, reg_val); reg_val 2076 sound/soc/codecs/rt5668.c reg_val |= RT5668_I2S2_MS_S; reg_val 2079 sound/soc/codecs/rt5668.c RT5668_I2S_DF_MASK, reg_val); reg_val 2092 sound/soc/codecs/rt5668.c unsigned int reg_val = 0, src = 0; reg_val 2099 sound/soc/codecs/rt5668.c reg_val |= RT5668_SCLK_SRC_MCLK; reg_val 2103 sound/soc/codecs/rt5668.c reg_val |= RT5668_SCLK_SRC_PLL1; reg_val 2107 sound/soc/codecs/rt5668.c reg_val |= RT5668_SCLK_SRC_PLL2; reg_val 2111 sound/soc/codecs/rt5668.c reg_val |= RT5668_SCLK_SRC_RCCLK; reg_val 2119 sound/soc/codecs/rt5668.c RT5668_SCLK_SRC_MASK, reg_val); reg_val 2338 sound/soc/codecs/rt5670.c unsigned int reg_val = 0; reg_val 2345 sound/soc/codecs/rt5670.c reg_val |= RT5670_I2S_MS_S; reg_val 2356 sound/soc/codecs/rt5670.c reg_val |= RT5670_I2S_BP_INV; reg_val 2366 sound/soc/codecs/rt5670.c reg_val |= RT5670_I2S_DF_LEFT; reg_val 2369 sound/soc/codecs/rt5670.c reg_val |= RT5670_I2S_DF_PCM_A; reg_val 2372 sound/soc/codecs/rt5670.c reg_val |= RT5670_I2S_DF_PCM_B; reg_val 2382 sound/soc/codecs/rt5670.c RT5670_I2S_DF_MASK, reg_val); reg_val 2387 sound/soc/codecs/rt5670.c RT5670_I2S_DF_MASK, reg_val); reg_val 2400 sound/soc/codecs/rt5670.c unsigned int reg_val = 0; reg_val 2404 sound/soc/codecs/rt5670.c reg_val |= RT5670_SCLK_SRC_MCLK; reg_val 2407 sound/soc/codecs/rt5670.c reg_val |= RT5670_SCLK_SRC_PLL1; reg_val 2410 sound/soc/codecs/rt5670.c reg_val |= RT5670_SCLK_SRC_RCCLK; reg_val 2417 sound/soc/codecs/rt5670.c RT5670_SCLK_SRC_MASK, reg_val); reg_val 4192 sound/soc/codecs/rt5677.c unsigned int reg_val = 0; reg_val 4199 sound/soc/codecs/rt5677.c reg_val |= RT5677_I2S_MS_S; reg_val 4210 sound/soc/codecs/rt5677.c reg_val |= RT5677_I2S_BP_INV; reg_val 4220 sound/soc/codecs/rt5677.c reg_val |= RT5677_I2S_DF_LEFT; reg_val 4223 sound/soc/codecs/rt5677.c reg_val |= RT5677_I2S_DF_PCM_A; reg_val 4226 sound/soc/codecs/rt5677.c reg_val |= RT5677_I2S_DF_PCM_B; reg_val 4236 sound/soc/codecs/rt5677.c RT5677_I2S_DF_MASK, reg_val); reg_val 4241 sound/soc/codecs/rt5677.c RT5677_I2S_DF_MASK, reg_val); reg_val 4246 sound/soc/codecs/rt5677.c RT5677_I2S_DF_MASK, reg_val); reg_val 4251 sound/soc/codecs/rt5677.c RT5677_I2S_DF_MASK, reg_val); reg_val 4266 sound/soc/codecs/rt5677.c unsigned int reg_val = 0; reg_val 4273 sound/soc/codecs/rt5677.c reg_val |= RT5677_SCLK_SRC_MCLK; reg_val 4276 sound/soc/codecs/rt5677.c reg_val |= RT5677_SCLK_SRC_PLL1; reg_val 4279 sound/soc/codecs/rt5677.c reg_val |= RT5677_SCLK_SRC_RCCLK; reg_val 4286 sound/soc/codecs/rt5677.c RT5677_SCLK_SRC_MASK, reg_val); reg_val 2086 sound/soc/codecs/rt5682.c unsigned int reg_val = 0, tdm_ctrl = 0; reg_val 2103 sound/soc/codecs/rt5682.c reg_val |= RT5682_I2S_BP_INV; reg_val 2127 sound/soc/codecs/rt5682.c reg_val |= RT5682_I2S_DF_LEFT; reg_val 2131 sound/soc/codecs/rt5682.c reg_val |= RT5682_I2S_DF_PCM_A; reg_val 2135 sound/soc/codecs/rt5682.c reg_val |= RT5682_I2S_DF_PCM_B; reg_val 2145 sound/soc/codecs/rt5682.c RT5682_I2S_DF_MASK, reg_val); reg_val 2154 sound/soc/codecs/rt5682.c reg_val |= RT5682_I2S2_MS_S; reg_val 2157 sound/soc/codecs/rt5682.c RT5682_I2S_DF_MASK, reg_val); reg_val 2170 sound/soc/codecs/rt5682.c unsigned int reg_val = 0, src = 0; reg_val 2177 sound/soc/codecs/rt5682.c reg_val |= RT5682_SCLK_SRC_MCLK; reg_val 2181 sound/soc/codecs/rt5682.c reg_val |= RT5682_SCLK_SRC_PLL1; reg_val 2185 sound/soc/codecs/rt5682.c reg_val |= RT5682_SCLK_SRC_PLL2; reg_val 2189 sound/soc/codecs/rt5682.c reg_val |= RT5682_SCLK_SRC_RCCLK; reg_val 2197 sound/soc/codecs/rt5682.c RT5682_SCLK_SRC_MASK, reg_val); reg_val 304 sound/soc/codecs/tas6424.c unsigned int reg_val; reg_val 306 sound/soc/codecs/tas6424.c if (!regmap_read(tas6424->regmap, TAS6424_DC_DIAG_CTRL1, ®_val)) reg_val 307 sound/soc/codecs/tas6424.c no_auto_diags = reg_val & TAS6424_LDGBYPASS_MASK; reg_val 118 sound/soc/fsl/fsl_audmix.c unsigned int reg_val, val, mix_clk; reg_val 122 sound/soc/fsl/fsl_audmix.c ret = snd_soc_component_read(comp, FSL_AUDMIX_CTR, ®_val); reg_val 126 sound/soc/fsl/fsl_audmix.c mix_clk = ((reg_val & FSL_AUDMIX_CTR_MIXCLK_MASK) reg_val 161 sound/soc/fsl/fsl_audmix.c unsigned int reg_val, val, mask = 0, ctr = 0; reg_val 165 sound/soc/fsl/fsl_audmix.c ret = snd_soc_component_read(comp, FSL_AUDMIX_CTR, ®_val); reg_val 170 sound/soc/fsl/fsl_audmix.c out_src = ((reg_val & FSL_AUDMIX_CTR_OUTSRC_MASK) reg_val 172 sound/soc/fsl/fsl_audmix.c mix_clk = ((reg_val & FSL_AUDMIX_CTR_MIXCLK_MASK) reg_val 1203 sound/soc/fsl/fsl_ssi.c u32 reg_val; reg_val 1222 sound/soc/fsl/fsl_ssi.c regmap_read(regs, REG_SSI_SACDAT, ®_val); reg_val 1223 sound/soc/fsl/fsl_ssi.c val = (reg_val >> 4) & 0xffff; reg_val 3290 sound/soc/soc-dapm.c unsigned int reg_val, val, rval = 0; reg_val 3295 sound/soc/soc-dapm.c ret = soc_dapm_read(dapm, reg, ®_val); reg_val 3296 sound/soc/soc-dapm.c val = (reg_val >> shift) & mask; reg_val 3299 sound/soc/soc-dapm.c ret = soc_dapm_read(dapm, mc->rreg, ®_val); reg_val 3302 sound/soc/soc-dapm.c rval = (reg_val >> mc->rshift) & mask; reg_val 3304 sound/soc/soc-dapm.c reg_val = dapm_kcontrol_get_value(kcontrol); reg_val 3305 sound/soc/soc-dapm.c val = reg_val & mask; reg_val 3308 sound/soc/soc-dapm.c rval = (reg_val >> width) & mask; reg_val 3438 sound/soc/soc-dapm.c unsigned int reg_val, val; reg_val 3442 sound/soc/soc-dapm.c int ret = soc_dapm_read(dapm, e->reg, ®_val); reg_val 3448 sound/soc/soc-dapm.c reg_val = dapm_kcontrol_get_value(kcontrol); reg_val 3452 sound/soc/soc-dapm.c val = (reg_val >> e->shift_l) & e->mask; reg_val 3455 sound/soc/soc-dapm.c val = (reg_val >> e->shift_r) & e->mask; reg_val 65 sound/soc/soc-ops.c unsigned int reg_val; reg_val 68 sound/soc/soc-ops.c ret = snd_soc_component_read(component, e->reg, ®_val); reg_val 71 sound/soc/soc-ops.c val = (reg_val >> e->shift_l) & e->mask; reg_val 75 sound/soc/soc-ops.c val = (reg_val >> e->shift_r) & e->mask; reg_val 266 sound/soc/sunxi/sun4i-spdif.c u32 reg_val; reg_val 349 sound/soc/sunxi/sun4i-spdif.c reg_val = 0; reg_val 350 sound/soc/sunxi/sun4i-spdif.c reg_val |= SUN4I_SPDIF_TXCFG_ASS; reg_val 351 sound/soc/sunxi/sun4i-spdif.c reg_val |= fmt; /* set non audio and bit depth */ reg_val 352 sound/soc/sunxi/sun4i-spdif.c reg_val |= SUN4I_SPDIF_TXCFG_CHSTMODE; reg_val 353 sound/soc/sunxi/sun4i-spdif.c reg_val |= SUN4I_SPDIF_TXCFG_TXRATIO(mclk_div - 1); reg_val 354 sound/soc/sunxi/sun4i-spdif.c regmap_write(host->regmap, SUN4I_SPDIF_TXCFG, reg_val);