reg_num 37 arch/arm/include/asm/kvm_emulate.h unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num); reg_num 39 arch/arm/include/asm/kvm_emulate.h static inline unsigned long *vcpu_reg32(struct kvm_vcpu *vcpu, u8 reg_num) reg_num 41 arch/arm/include/asm/kvm_emulate.h return vcpu_reg(vcpu, reg_num); reg_num 62 arch/arm/include/asm/kvm_emulate.h u8 reg_num) reg_num 64 arch/arm/include/asm/kvm_emulate.h return *vcpu_reg(vcpu, reg_num); reg_num 67 arch/arm/include/asm/kvm_emulate.h static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num, reg_num 70 arch/arm/include/asm/kvm_emulate.h *vcpu_reg(vcpu, reg_num) = val; reg_num 46 arch/arm/include/asm/kvm_host.h u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode); reg_num 101 arch/arm/kvm/emulate.c unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num) reg_num 127 arch/arm/kvm/emulate.c return reg_array + vcpu_reg_offsets[mode][reg_num]; reg_num 25 arch/arm64/include/asm/kvm_emulate.h unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num); reg_num 165 arch/arm64/include/asm/kvm_emulate.h u8 reg_num) reg_num 167 arch/arm64/include/asm/kvm_emulate.h return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs.regs[reg_num]; reg_num 170 arch/arm64/include/asm/kvm_emulate.h static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num, reg_num 173 arch/arm64/include/asm/kvm_emulate.h if (reg_num != 31) reg_num 174 arch/arm64/include/asm/kvm_emulate.h vcpu_gp_regs(vcpu)->regs.regs[reg_num] = val; reg_num 339 arch/arm64/kvm/guest.c unsigned int reg_num; reg_num 355 arch/arm64/kvm/guest.c reg_num = (reg->id & SVE_REG_ID_MASK) >> SVE_REG_ID_SHIFT; reg_num 363 arch/arm64/kvm/guest.c reqoffset = SVE_SIG_ZREG_OFFSET(vq, reg_num) - reg_num 373 arch/arm64/kvm/guest.c reqoffset = SVE_SIG_PREG_OFFSET(vq, reg_num) - reg_num 101 arch/arm64/kvm/regmap.c unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num) reg_num 127 arch/arm64/kvm/regmap.c return reg_array + vcpu_reg_offsets[mode][reg_num]; reg_num 616 arch/ia64/include/asm/pal.h reg_num : 7, /* Register number */ reg_num 1700 arch/ia64/include/asm/pal.h ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid) reg_num 1703 arch/ia64/include/asm/pal.h PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer)); reg_num 86 arch/ia64/include/uapi/asm/perfmon.h unsigned int reg_num; /* which register */ reg_num 2803 arch/ia64/kernel/perfmon.c cnum = req->reg_num; reg_num 3046 arch/ia64/kernel/perfmon.c cnum = req->reg_num; reg_num 3257 arch/ia64/kernel/perfmon.c cnum = req->reg_num; reg_num 4065 arch/ia64/kernel/perfmon.c cnum = req->reg_num; reg_num 33 arch/powerpc/include/asm/mpic_msgr.h extern struct mpic_msgr *mpic_msgr_get(unsigned int reg_num); reg_num 82 arch/powerpc/platforms/powernv/opal-fadump.h __be32 reg_num; reg_num 87 arch/powerpc/platforms/powernv/opal-fadump.h u32 reg_type, u32 reg_num, reg_num 91 arch/powerpc/platforms/powernv/opal-fadump.h if (reg_num < 32) reg_num 92 arch/powerpc/platforms/powernv/opal-fadump.h regs->gpr[reg_num] = reg_val; reg_num 96 arch/powerpc/platforms/powernv/opal-fadump.h switch (reg_num) { reg_num 141 arch/powerpc/platforms/powernv/opal-fadump.h be32_to_cpu(reg_entry->reg_num), reg_num 47 arch/powerpc/sysdev/mpic_msgr.c struct mpic_msgr *mpic_msgr_get(unsigned int reg_num) reg_num 55 arch/powerpc/sysdev/mpic_msgr.c if (reg_num >= mpic_msgr_count) reg_num 59 arch/powerpc/sysdev/mpic_msgr.c msgr = mpic_msgrs[reg_num]; reg_num 63 arch/sh/kernel/dwarf.c unsigned int reg_num) reg_num 77 arch/sh/kernel/dwarf.c reg->number = reg_num; reg_num 105 arch/sh/kernel/dwarf.c unsigned int reg_num) reg_num 110 arch/sh/kernel/dwarf.c if (reg->number == reg_num) reg_num 3445 arch/sparc/include/asm/hypervisor.h unsigned long sun4v_vt_get_perfreg(unsigned long reg_num, reg_num 3447 arch/sparc/include/asm/hypervisor.h unsigned long sun4v_vt_set_perfreg(unsigned long reg_num, reg_num 3455 arch/sparc/include/asm/hypervisor.h unsigned long sun4v_t5_get_perfreg(unsigned long reg_num, reg_num 3457 arch/sparc/include/asm/hypervisor.h unsigned long sun4v_t5_set_perfreg(unsigned long reg_num, reg_num 3466 arch/sparc/include/asm/hypervisor.h unsigned long sun4v_m7_get_perfreg(unsigned long reg_num, reg_num 3468 arch/sparc/include/asm/hypervisor.h unsigned long sun4v_m7_set_perfreg(unsigned long reg_num, reg_num 55 arch/sparc/kernel/pcr.c static u64 direct_pcr_read(unsigned long reg_num) reg_num 59 arch/sparc/kernel/pcr.c WARN_ON_ONCE(reg_num != 0); reg_num 64 arch/sparc/kernel/pcr.c static void direct_pcr_write(unsigned long reg_num, u64 val) reg_num 66 arch/sparc/kernel/pcr.c WARN_ON_ONCE(reg_num != 0); reg_num 70 arch/sparc/kernel/pcr.c static u64 direct_pic_read(unsigned long reg_num) reg_num 74 arch/sparc/kernel/pcr.c WARN_ON_ONCE(reg_num != 0); reg_num 79 arch/sparc/kernel/pcr.c static void direct_pic_write(unsigned long reg_num, u64 val) reg_num 81 arch/sparc/kernel/pcr.c WARN_ON_ONCE(reg_num != 0); reg_num 111 arch/sparc/kernel/pcr.c static void n2_pcr_write(unsigned long reg_num, u64 val) reg_num 115 arch/sparc/kernel/pcr.c WARN_ON_ONCE(reg_num != 0); reg_num 119 arch/sparc/kernel/pcr.c direct_pcr_write(reg_num, val); reg_num 121 arch/sparc/kernel/pcr.c direct_pcr_write(reg_num, val); reg_num 144 arch/sparc/kernel/pcr.c static u64 n4_pcr_read(unsigned long reg_num) reg_num 148 arch/sparc/kernel/pcr.c (void) sun4v_vt_get_perfreg(reg_num, &val); reg_num 153 arch/sparc/kernel/pcr.c static void n4_pcr_write(unsigned long reg_num, u64 val) reg_num 155 arch/sparc/kernel/pcr.c (void) sun4v_vt_set_perfreg(reg_num, val); reg_num 158 arch/sparc/kernel/pcr.c static u64 n4_pic_read(unsigned long reg_num) reg_num 164 arch/sparc/kernel/pcr.c : "r" (reg_num * 0x8UL), "i" (ASI_PIC)); reg_num 169 arch/sparc/kernel/pcr.c static void n4_pic_write(unsigned long reg_num, u64 val) reg_num 173 arch/sparc/kernel/pcr.c : "r" (val), "r" (reg_num * 0x8UL), "i" (ASI_PIC)); reg_num 195 arch/sparc/kernel/pcr.c static u64 n5_pcr_read(unsigned long reg_num) reg_num 199 arch/sparc/kernel/pcr.c (void) sun4v_t5_get_perfreg(reg_num, &val); reg_num 204 arch/sparc/kernel/pcr.c static void n5_pcr_write(unsigned long reg_num, u64 val) reg_num 206 arch/sparc/kernel/pcr.c (void) sun4v_t5_set_perfreg(reg_num, val); reg_num 221 arch/sparc/kernel/pcr.c static u64 m7_pcr_read(unsigned long reg_num) reg_num 225 arch/sparc/kernel/pcr.c (void) sun4v_m7_get_perfreg(reg_num, &val); reg_num 230 arch/sparc/kernel/pcr.c static void m7_pcr_write(unsigned long reg_num, u64 val) reg_num 232 arch/sparc/kernel/pcr.c (void) sun4v_m7_set_perfreg(reg_num, val); reg_num 179 arch/sparc/kernel/unaligned_32.c static int do_int_store(int reg_num, int size, unsigned long *dst_addr, reg_num 185 arch/sparc/kernel/unaligned_32.c if (reg_num) reg_num 186 arch/sparc/kernel/unaligned_32.c src_val = fetch_reg_addr(reg_num, regs); reg_num 203 arch/sparc/kernel/unaligned_64.c static inline int do_int_store(int reg_num, int size, unsigned long *dst_addr, reg_num 212 arch/sparc/kernel/unaligned_64.c zero = (((long)(reg_num ? reg_num 213 arch/sparc/kernel/unaligned_64.c (unsigned int)fetch_reg(reg_num, regs) : 0)) << 32) | reg_num 214 arch/sparc/kernel/unaligned_64.c (unsigned int)fetch_reg(reg_num + 1, regs); reg_num 215 arch/sparc/kernel/unaligned_64.c } else if (reg_num) { reg_num 216 arch/sparc/kernel/unaligned_64.c src_val_p = fetch_reg_addr(reg_num, regs); reg_num 212 drivers/crypto/qat/qat_common/adf_common_drv.h unsigned short reg_num, unsigned int regdata); reg_num 216 drivers/crypto/qat/qat_common/adf_common_drv.h unsigned short reg_num, unsigned int regdata); reg_num 220 drivers/crypto/qat/qat_common/adf_common_drv.h unsigned short reg_num, unsigned int regdata); reg_num 223 drivers/crypto/qat/qat_common/adf_common_drv.h unsigned short reg_num, unsigned int regdata); reg_num 267 drivers/crypto/qat/qat_common/qat_hal.c unsigned short reg_num) reg_num 274 drivers/crypto/qat/qat_common/qat_hal.c reg_addr = 0x80 | (reg_num & 0x7f); reg_num 278 drivers/crypto/qat/qat_common/qat_hal.c reg_addr = reg_num & 0x1f; reg_num 283 drivers/crypto/qat/qat_common/qat_hal.c reg_addr = 0x180 | (reg_num & 0x1f); reg_num 286 drivers/crypto/qat/qat_common/qat_hal.c reg_addr = 0x140 | ((reg_num & 0x3) << 1); reg_num 291 drivers/crypto/qat/qat_common/qat_hal.c reg_addr = 0x1c0 | (reg_num & 0x1f); reg_num 294 drivers/crypto/qat/qat_common/qat_hal.c reg_addr = 0x100 | ((reg_num & 0x3) << 1); reg_num 297 drivers/crypto/qat/qat_common/qat_hal.c reg_addr = 0x280 | (reg_num & 0x1f); reg_num 306 drivers/crypto/qat/qat_common/qat_hal.c reg_addr = 0x300 | (reg_num & 0xff); reg_num 969 drivers/crypto/qat/qat_common/qat_hal.c unsigned short reg_num, unsigned int *data) reg_num 977 drivers/crypto/qat/qat_common/qat_hal.c reg_addr = qat_hal_get_reg_addr(reg_type, reg_num); reg_num 1030 drivers/crypto/qat/qat_common/qat_hal.c unsigned short reg_num, unsigned int data) reg_num 1042 drivers/crypto/qat/qat_common/qat_hal.c dest_addr = qat_hal_get_reg_addr(reg_type, reg_num); reg_num 1184 drivers/crypto/qat/qat_common/qat_hal.c unsigned short reg_num, unsigned int val) reg_num 1203 drivers/crypto/qat/qat_common/qat_hal.c if (reg_num & ~mask) reg_num 1205 drivers/crypto/qat/qat_common/qat_hal.c reg_addr = reg_num + (ctx << 0x5); reg_num 1225 drivers/crypto/qat/qat_common/qat_hal.c unsigned short reg_num, unsigned int data) reg_num 1252 drivers/crypto/qat/qat_common/qat_hal.c if (reg_num & reg_mask) reg_num 1254 drivers/crypto/qat/qat_common/qat_hal.c xfr_addr = qat_hal_get_reg_addr(reg_type, reg_num); reg_num 1319 drivers/crypto/qat/qat_common/qat_hal.c unsigned short reg_num, unsigned int regdata) reg_num 1326 drivers/crypto/qat/qat_common/qat_hal.c if (reg_num >= ICP_QAT_UCLO_MAX_GPR_REG) reg_num 1331 drivers/crypto/qat/qat_common/qat_hal.c qat_hal_convert_abs_to_rel(handle, ae, reg_num, ®, reg_num 1335 drivers/crypto/qat/qat_common/qat_hal.c reg = reg_num; reg_num 1353 drivers/crypto/qat/qat_common/qat_hal.c unsigned short reg_num, unsigned int regdata) reg_num 1360 drivers/crypto/qat/qat_common/qat_hal.c if (reg_num >= ICP_QAT_UCLO_MAX_XFER_REG) reg_num 1365 drivers/crypto/qat/qat_common/qat_hal.c qat_hal_convert_abs_to_rel(handle, ae, reg_num, ®, reg_num 1369 drivers/crypto/qat/qat_common/qat_hal.c reg = reg_num; reg_num 1388 drivers/crypto/qat/qat_common/qat_hal.c unsigned short reg_num, unsigned int regdata) reg_num 1395 drivers/crypto/qat/qat_common/qat_hal.c if (reg_num >= ICP_QAT_UCLO_MAX_XFER_REG) reg_num 1400 drivers/crypto/qat/qat_common/qat_hal.c qat_hal_convert_abs_to_rel(handle, ae, reg_num, ®, reg_num 1404 drivers/crypto/qat/qat_common/qat_hal.c reg = reg_num; reg_num 1422 drivers/crypto/qat/qat_common/qat_hal.c unsigned short reg_num, unsigned int regdata) reg_num 1433 drivers/crypto/qat/qat_common/qat_hal.c stat = qat_hal_put_rel_nn(handle, ae, ctx, reg_num, regdata); reg_num 1604 drivers/gpu/drm/amd/display/dc/core/dc_link.c settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; reg_num 1616 drivers/gpu/drm/amd/display/dc/core/dc_link.c settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; reg_num 1628 drivers/gpu/drm/amd/display/dc/core/dc_link.c settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; reg_num 1640 drivers/gpu/drm/amd/display/dc/core/dc_link.c settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; reg_num 1658 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (settings->reg_num > 9) reg_num 1663 drivers/gpu/drm/amd/display/dc/core/dc_link.c for (i = 0; i < settings->reg_num; i++) { reg_num 1723 drivers/gpu/drm/amd/display/dc/core/dc_link.c for (i = 0; i < settings->reg_num; i++) { reg_num 173 drivers/gpu/drm/amd/display/dc/dm_services.h #define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\ reg_num 176 drivers/gpu/drm/amd/display/dc/dm_services.h block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ reg_num 177 drivers/gpu/drm/amd/display/dc/dm_services.h block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) reg_num 179 drivers/gpu/drm/amd/display/dc/dm_services.h #define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\ reg_num 183 drivers/gpu/drm/amd/display/dc/dm_services.h block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ reg_num 184 drivers/gpu/drm/amd/display/dc/dm_services.h block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) reg_num 91 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c #define hpd_int_entry(reg_num)\ reg_num 92 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ reg_num 93 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\ reg_num 99 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\ reg_num 102 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\ reg_num 106 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c #define hpd_rx_int_entry(reg_num)\ reg_num 107 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ reg_num 108 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\ reg_num 113 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\ reg_num 116 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\ reg_num 119 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c #define pflip_int_entry(reg_num)\ reg_num 120 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ reg_num 121 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c .enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\ reg_num 127 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c .ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\ reg_num 130 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c .status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\ reg_num 134 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c #define vupdate_int_entry(reg_num)\ reg_num 135 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ reg_num 136 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c .enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\ reg_num 142 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c .ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\ reg_num 150 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c #define vblank_int_entry(reg_num)\ reg_num 151 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ reg_num 152 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\ reg_num 158 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\ reg_num 164 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\ reg_num 172 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c #define i2c_int_entry(reg_num) \ reg_num 173 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() reg_num 175 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c #define dp_sink_int_entry(reg_num) \ reg_num 176 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() reg_num 178 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c #define gpio_pad_int_entry(reg_num) \ reg_num 179 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() reg_num 181 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c #define dc_underflow_int_entry(reg_num) \ reg_num 182 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() reg_num 105 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ reg_num 106 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c .enable_reg = SRI(reg1, block, reg_num),\ reg_num 108 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ reg_num 110 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ reg_num 111 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ reg_num 113 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c .ack_reg = SRI(reg2, block, reg_num),\ reg_num 115 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ reg_num 117 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ reg_num 119 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c #define hpd_int_entry(reg_num)\ reg_num 120 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ reg_num 121 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c IRQ_REG_ENTRY(HPD, reg_num,\ reg_num 124 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ reg_num 128 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c #define hpd_rx_int_entry(reg_num)\ reg_num 129 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ reg_num 130 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c IRQ_REG_ENTRY(HPD, reg_num,\ reg_num 133 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ reg_num 136 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c #define pflip_int_entry(reg_num)\ reg_num 137 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ reg_num 138 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c IRQ_REG_ENTRY(DCP, reg_num, \ reg_num 141 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c .status_reg = SRI(GRPH_INTERRUPT_STATUS, DCP, reg_num),\ reg_num 145 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c #define vupdate_int_entry(reg_num)\ reg_num 146 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ reg_num 147 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c IRQ_REG_ENTRY(CRTC, reg_num,\ reg_num 153 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c #define vblank_int_entry(reg_num)\ reg_num 154 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ reg_num 155 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c IRQ_REG_ENTRY(CRTC, reg_num,\ reg_num 159 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\ reg_num 167 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c #define i2c_int_entry(reg_num) \ reg_num 168 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() reg_num 170 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c #define dp_sink_int_entry(reg_num) \ reg_num 171 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() reg_num 173 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c #define gpio_pad_int_entry(reg_num) \ reg_num 174 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() reg_num 176 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c #define dc_underflow_int_entry(reg_num) \ reg_num 177 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() reg_num 94 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c #define hpd_int_entry(reg_num)\ reg_num 95 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c [DC_IRQ_SOURCE_INVALID + reg_num] = {\ reg_num 96 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ reg_num 102 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ reg_num 105 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\ reg_num 109 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c #define hpd_rx_int_entry(reg_num)\ reg_num 110 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c [DC_IRQ_SOURCE_HPD6 + reg_num] = {\ reg_num 111 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ reg_num 116 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ reg_num 119 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\ reg_num 123 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c #define pflip_int_entry(reg_num)\ reg_num 124 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ reg_num 125 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c .enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\ reg_num 131 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c .ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\ reg_num 134 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c .status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\ reg_num 138 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c #define vupdate_int_entry(reg_num)\ reg_num 139 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ reg_num 140 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c .enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\ reg_num 146 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c .ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\ reg_num 154 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c #define vblank_int_entry(reg_num)\ reg_num 155 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ reg_num 156 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\ reg_num 162 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\ reg_num 168 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\ reg_num 176 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c #define i2c_int_entry(reg_num) \ reg_num 177 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() reg_num 179 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c #define dp_sink_int_entry(reg_num) \ reg_num 180 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() reg_num 182 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c #define gpio_pad_int_entry(reg_num) \ reg_num 183 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() reg_num 185 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c #define dc_underflow_int_entry(reg_num) \ reg_num 186 drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() reg_num 186 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ reg_num 187 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c .enable_reg = SRI(reg1, block, reg_num),\ reg_num 189 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ reg_num 191 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ reg_num 192 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ reg_num 194 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c .ack_reg = SRI(reg2, block, reg_num),\ reg_num 196 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ reg_num 198 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ reg_num 200 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c #define hpd_int_entry(reg_num)\ reg_num 201 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ reg_num 202 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c IRQ_REG_ENTRY(HPD, reg_num,\ reg_num 205 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ reg_num 209 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c #define hpd_rx_int_entry(reg_num)\ reg_num 210 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ reg_num 211 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c IRQ_REG_ENTRY(HPD, reg_num,\ reg_num 214 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ reg_num 217 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c #define pflip_int_entry(reg_num)\ reg_num 218 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ reg_num 219 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c IRQ_REG_ENTRY(HUBPREQ, reg_num,\ reg_num 228 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c #define vupdate_no_lock_int_entry(reg_num)\ reg_num 229 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ reg_num 230 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c IRQ_REG_ENTRY(OTG, reg_num,\ reg_num 236 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c #define vblank_int_entry(reg_num)\ reg_num 237 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ reg_num 238 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c IRQ_REG_ENTRY(OTG, reg_num,\ reg_num 249 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c #define i2c_int_entry(reg_num) \ reg_num 250 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() reg_num 252 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c #define dp_sink_int_entry(reg_num) \ reg_num 253 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() reg_num 255 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c #define gpio_pad_int_entry(reg_num) \ reg_num 256 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() reg_num 258 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c #define dc_underflow_int_entry(reg_num) \ reg_num 259 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() reg_num 188 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ reg_num 189 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c .enable_reg = SRI(reg1, block, reg_num),\ reg_num 191 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ reg_num 193 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ reg_num 194 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ reg_num 196 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c .ack_reg = SRI(reg2, block, reg_num),\ reg_num 198 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ reg_num 200 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ reg_num 204 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c #define hpd_int_entry(reg_num)\ reg_num 205 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ reg_num 206 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c IRQ_REG_ENTRY(HPD, reg_num,\ reg_num 209 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ reg_num 213 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c #define hpd_rx_int_entry(reg_num)\ reg_num 214 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ reg_num 215 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c IRQ_REG_ENTRY(HPD, reg_num,\ reg_num 218 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ reg_num 221 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c #define pflip_int_entry(reg_num)\ reg_num 222 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ reg_num 223 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c IRQ_REG_ENTRY(HUBPREQ, reg_num,\ reg_num 232 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c #define vupdate_no_lock_int_entry(reg_num)\ reg_num 233 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ reg_num 234 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c IRQ_REG_ENTRY(OTG, reg_num,\ reg_num 240 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c #define vblank_int_entry(reg_num)\ reg_num 241 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ reg_num 242 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c IRQ_REG_ENTRY(OTG, reg_num,\ reg_num 253 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c #define i2c_int_entry(reg_num) \ reg_num 254 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() reg_num 256 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c #define dp_sink_int_entry(reg_num) \ reg_num 257 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() reg_num 259 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c #define gpio_pad_int_entry(reg_num) \ reg_num 260 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() reg_num 262 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c #define dc_underflow_int_entry(reg_num) \ reg_num 263 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() reg_num 184 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ reg_num 185 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c .enable_reg = SRI(reg1, block, reg_num),\ reg_num 187 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ reg_num 189 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ reg_num 190 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ reg_num 192 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c .ack_reg = SRI(reg2, block, reg_num),\ reg_num 194 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ reg_num 196 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ reg_num 200 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c #define hpd_int_entry(reg_num)\ reg_num 201 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ reg_num 202 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c IRQ_REG_ENTRY(HPD, reg_num,\ reg_num 205 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ reg_num 209 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c #define hpd_rx_int_entry(reg_num)\ reg_num 210 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ reg_num 211 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c IRQ_REG_ENTRY(HPD, reg_num,\ reg_num 214 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ reg_num 217 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c #define pflip_int_entry(reg_num)\ reg_num 218 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ reg_num 219 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c IRQ_REG_ENTRY(HUBPREQ, reg_num,\ reg_num 225 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c #define vupdate_int_entry(reg_num)\ reg_num 226 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ reg_num 227 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c IRQ_REG_ENTRY(OTG, reg_num,\ reg_num 233 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c #define vblank_int_entry(reg_num)\ reg_num 234 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ reg_num 235 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c IRQ_REG_ENTRY(OTG, reg_num,\ reg_num 246 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c #define i2c_int_entry(reg_num) \ reg_num 247 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() reg_num 249 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c #define dp_sink_int_entry(reg_num) \ reg_num 250 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() reg_num 252 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c #define gpio_pad_int_entry(reg_num) \ reg_num 253 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() reg_num 255 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c #define dc_underflow_int_entry(reg_num) \ reg_num 256 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() reg_num 275 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h unsigned char reg_num; reg_num 96 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c u32 bit_ofst, reg_num; reg_num 99 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c reg_num = bit_num / 32; reg_num 101 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c ade_update_bits(base + ADE_RELOAD_DIS(reg_num), bit_ofst, reg_num 107 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c u32 tmp, bit_ofst, reg_num; reg_num 110 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c reg_num = bit_num / 32; reg_num 112 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c tmp = readl(base + ADE_RELOAD_DIS(reg_num)); reg_num 4157 drivers/gpu/drm/radeon/evergreen.c u32 dws, data, i, j, k, reg_num; reg_num 4299 drivers/gpu/drm/radeon/evergreen.c reg_num = cs_data[i].section[j].reg_count; reg_num 4308 drivers/gpu/drm/radeon/evergreen.c data = 0x08000000 | (reg_num * 4); reg_num 4312 drivers/gpu/drm/radeon/evergreen.c for (k = 0; k < reg_num; k++) { reg_num 4316 drivers/gpu/drm/radeon/evergreen.c reg_list_mc_addr += reg_num * 4; reg_num 4317 drivers/gpu/drm/radeon/evergreen.c reg_list_blk_index += reg_num; reg_num 103 drivers/input/keyboard/bcm-keypad.c static void bcm_kp_report_keys(struct bcm_kp *kp, int reg_num, int pull_mode) reg_num 112 drivers/input/keyboard/bcm-keypad.c writel(0xFFFFFFFF, kp->base + KPICRN_OFFSET(reg_num)); reg_num 114 drivers/input/keyboard/bcm-keypad.c state = readl(kp->base + KPSSRN_OFFSET(reg_num)); reg_num 115 drivers/input/keyboard/bcm-keypad.c change = kp->last_state[reg_num] ^ state; reg_num 116 drivers/input/keyboard/bcm-keypad.c kp->last_state[reg_num] = state; reg_num 122 drivers/input/keyboard/bcm-keypad.c row = BIT_TO_ROW_SSRN(bit_nr, reg_num); reg_num 133 drivers/input/keyboard/bcm-keypad.c int reg_num; reg_num 135 drivers/input/keyboard/bcm-keypad.c for (reg_num = 0; reg_num <= 1; reg_num++) reg_num 136 drivers/input/keyboard/bcm-keypad.c bcm_kp_report_keys(kp, reg_num, pull_mode); reg_num 104 drivers/input/rmi4/rmi_f30.c unsigned int reg_num = button >> 3; reg_num 107 drivers/input/rmi4/rmi_f30.c bool key_down = !(f30->data_regs[reg_num] & BIT(bit_num)); reg_num 33 drivers/irqchip/irq-imx-irqsteer.c int reg_num; reg_num 42 drivers/irqchip/irq-imx-irqsteer.c return (data->reg_num - irqnum / 32 - 1); reg_num 53 drivers/irqchip/irq-imx-irqsteer.c val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); reg_num 55 drivers/irqchip/irq-imx-irqsteer.c writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); reg_num 67 drivers/irqchip/irq-imx-irqsteer.c val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); reg_num 69 drivers/irqchip/irq-imx-irqsteer.c writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); reg_num 127 drivers/irqchip/irq-imx-irqsteer.c if (hwirq >= data->reg_num * 32) reg_num 131 drivers/irqchip/irq-imx-irqsteer.c CHANSTATUS(idx, data->reg_num)); reg_num 182 drivers/irqchip/irq-imx-irqsteer.c data->reg_num = irqs_num / 32; reg_num 186 drivers/irqchip/irq-imx-irqsteer.c sizeof(u32) * data->reg_num, reg_num 201 drivers/irqchip/irq-imx-irqsteer.c data->domain = irq_domain_add_linear(np, data->reg_num * 32, reg_num 255 drivers/irqchip/irq-imx-irqsteer.c for (i = 0; i < data->reg_num; i++) reg_num 257 drivers/irqchip/irq-imx-irqsteer.c CHANMASK(i, data->reg_num)); reg_num 265 drivers/irqchip/irq-imx-irqsteer.c for (i = 0; i < data->reg_num; i++) reg_num 267 drivers/irqchip/irq-imx-irqsteer.c data->regs + CHANMASK(i, data->reg_num)); reg_num 284 drivers/media/i2c/ov2640.c u8 reg_num; reg_num 659 drivers/media/i2c/ov2640.c while ((vals->reg_num != 0xff) || (vals->value != 0xff)) { reg_num 661 drivers/media/i2c/ov2640.c vals->reg_num, vals->value); reg_num 663 drivers/media/i2c/ov2640.c vals->reg_num, vals->value); reg_num 279 drivers/media/i2c/ov7670.c unsigned char reg_num; reg_num 598 drivers/media/i2c/ov7670.c while (vals->reg_num != 0xff || vals->value != 0xff) { reg_num 599 drivers/media/i2c/ov7670.c int ret = ov7670_write(sd, vals->reg_num, vals->value); reg_num 133 drivers/media/i2c/ov7740.c u32 reg_num; reg_num 140 drivers/media/i2c/ov7740.c u32 reg_num; reg_num 265 drivers/media/i2c/ov7740.c .reg_num = ARRAY_SIZE(ov7740_vga), reg_num 598 drivers/media/i2c/ov7740.c ov7740->fmt->reg_num); reg_num 606 drivers/media/i2c/ov7740.c ov7740->frmsize->reg_num); reg_num 700 drivers/media/i2c/ov7740.c .reg_num = ARRAY_SIZE(ov7740_format_yuyv), reg_num 706 drivers/media/i2c/ov7740.c .reg_num = ARRAY_SIZE(ov7740_format_bggr8), reg_num 216 drivers/media/i2c/tw9910.c unsigned char reg_num; reg_num 77 drivers/mfd/ezx-pcap.c int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value) reg_num 85 drivers/mfd/ezx-pcap.c | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); reg_num 93 drivers/mfd/ezx-pcap.c int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value) reg_num 100 drivers/mfd/ezx-pcap.c | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); reg_num 109 drivers/mfd/ezx-pcap.c int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val) reg_num 114 drivers/mfd/ezx-pcap.c (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); reg_num 123 drivers/mfd/ezx-pcap.c (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); reg_num 468 drivers/net/bonding/bond_main.c mii->reg_num = MII_BMSR; reg_num 3544 drivers/net/bonding/bond_main.c if (mii->reg_num == 1) { reg_num 1044 drivers/net/ethernet/3com/3c574_cs.c data->phy_id, data->reg_num, data->val_in, data->val_out); reg_num 1059 drivers/net/ethernet/3com/3c574_cs.c data->reg_num & 0x1f); reg_num 1073 drivers/net/ethernet/3com/3c574_cs.c data->reg_num & 0x1f, data->val_in); reg_num 615 drivers/net/ethernet/8390/axnet_cs.c data->val_out = mdio_read(mii_addr, data->phy_id, data->reg_num & 0x1f); reg_num 618 drivers/net/ethernet/8390/axnet_cs.c mdio_write(mii_addr, data->phy_id, data->reg_num & 0x1f, data->val_in); reg_num 1113 drivers/net/ethernet/8390/pcnet_cs.c data->val_out = mdio_read(mii_addr, data->phy_id, data->reg_num & 0x1f); reg_num 1116 drivers/net/ethernet/8390/pcnet_cs.c mdio_write(mii_addr, data->phy_id, data->reg_num & 0x1f, data->val_in); reg_num 158 drivers/net/ethernet/amd/amd8111e.c static int amd8111e_mdio_read(struct net_device *dev, int phy_id, int reg_num) reg_num 163 drivers/net/ethernet/amd/amd8111e.c amd8111e_read_phy(lp,phy_id,reg_num,®_val); reg_num 170 drivers/net/ethernet/amd/amd8111e.c int phy_id, int reg_num, int val) reg_num 174 drivers/net/ethernet/amd/amd8111e.c amd8111e_write_phy(lp, phy_id, reg_num, val); reg_num 1478 drivers/net/ethernet/amd/amd8111e.c data->reg_num & PHY_REG_ADDR_MASK, &mii_regval); reg_num 1488 drivers/net/ethernet/amd/amd8111e.c data->reg_num & PHY_REG_ADDR_MASK, data->val_in); reg_num 325 drivers/net/ethernet/amd/pcnet32.c static int mdio_read(struct net_device *dev, int phy_id, int reg_num); reg_num 326 drivers/net/ethernet/amd/pcnet32.c static void mdio_write(struct net_device *dev, int phy_id, int reg_num, reg_num 2756 drivers/net/ethernet/amd/pcnet32.c static int mdio_read(struct net_device *dev, int phy_id, int reg_num) reg_num 2765 drivers/net/ethernet/amd/pcnet32.c lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); reg_num 2772 drivers/net/ethernet/amd/pcnet32.c static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val) reg_num 2780 drivers/net/ethernet/amd/pcnet32.c lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); reg_num 56 drivers/net/ethernet/arc/emac_mdio.c static int arc_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num) reg_num 63 drivers/net/ethernet/arc/emac_mdio.c 0x60020000 | (phy_addr << 23) | (reg_num << 18)); reg_num 72 drivers/net/ethernet/arc/emac_mdio.c phy_addr, reg_num, value); reg_num 89 drivers/net/ethernet/arc/emac_mdio.c int reg_num, u16 value) reg_num 95 drivers/net/ethernet/arc/emac_mdio.c phy_addr, reg_num, value); reg_num 98 drivers/net/ethernet/arc/emac_mdio.c 0x50020000 | (phy_addr << 23) | (reg_num << 18) | value); reg_num 559 drivers/net/ethernet/atheros/atl1c/atl1c_main.c static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num) reg_num 564 drivers/net/ethernet/atheros/atl1c/atl1c_main.c atl1c_read_phy_reg(&adapter->hw, reg_num, &result); reg_num 569 drivers/net/ethernet/atheros/atl1c/atl1c_main.c int reg_num, int val) reg_num 573 drivers/net/ethernet/atheros/atl1c/atl1c_main.c atl1c_write_phy_reg(&adapter->hw, reg_num, val); reg_num 595 drivers/net/ethernet/atheros/atl1c/atl1c_main.c if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, reg_num 603 drivers/net/ethernet/atheros/atl1c/atl1c_main.c if (data->reg_num & ~(0x1F)) { reg_num 609 drivers/net/ethernet/atheros/atl1c/atl1c_main.c data->reg_num, data->val_in); reg_num 611 drivers/net/ethernet/atheros/atl1c/atl1c_main.c data->reg_num, data->val_in)) { reg_num 449 drivers/net/ethernet/atheros/atl1e/atl1e_main.c static int atl1e_mdio_read(struct net_device *netdev, int phy_id, int reg_num) reg_num 454 drivers/net/ethernet/atheros/atl1e/atl1e_main.c atl1e_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result); reg_num 459 drivers/net/ethernet/atheros/atl1e/atl1e_main.c int reg_num, int val) reg_num 464 drivers/net/ethernet/atheros/atl1e/atl1e_main.c reg_num & MDIO_REG_ADDR_MASK, val)) reg_num 486 drivers/net/ethernet/atheros/atl1e/atl1e_main.c if (atl1e_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, reg_num 494 drivers/net/ethernet/atheros/atl1e/atl1e_main.c if (data->reg_num & ~(0x1F)) { reg_num 500 drivers/net/ethernet/atheros/atl1e/atl1e_main.c data->reg_num, data->val_in); reg_num 502 drivers/net/ethernet/atheros/atl1e/atl1e_main.c data->reg_num, data->val_in)) { reg_num 981 drivers/net/ethernet/atheros/atlx/atl1.c static int mdio_read(struct net_device *netdev, int phy_id, int reg_num) reg_num 986 drivers/net/ethernet/atheros/atlx/atl1.c atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result); reg_num 991 drivers/net/ethernet/atheros/atlx/atl1.c static void mdio_write(struct net_device *netdev, int phy_id, int reg_num, reg_num 996 drivers/net/ethernet/atheros/atlx/atl1.c atl1_write_phy_reg(&adapter->hw, reg_num, val); reg_num 961 drivers/net/ethernet/atheros/atlx/atl2.c data->reg_num & 0x1F, &data->val_out)) { reg_num 968 drivers/net/ethernet/atheros/atlx/atl2.c if (data->reg_num & ~(0x1F)) reg_num 971 drivers/net/ethernet/atheros/atlx/atl2.c if (atl2_write_phy_reg(&adapter->hw, data->reg_num, reg_num 7872 drivers/net/ethernet/broadcom/bnx2.c err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval); reg_num 7888 drivers/net/ethernet/broadcom/bnx2.c err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); reg_num 12936 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c mdio->phy_id, mdio->reg_num, mdio->val_in); reg_num 9407 drivers/net/ethernet/broadcom/bnxt/bnxt.c rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num, reg_num 9417 drivers/net/ethernet/broadcom/bnxt/bnxt.c return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num, reg_num 14024 drivers/net/ethernet/broadcom/tg3.c data->reg_num & 0x1f, &mii_regval); reg_num 14041 drivers/net/ethernet/broadcom/tg3.c data->reg_num & 0x1f, data->val_in); reg_num 2638 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c data->reg_num &= 0x1f; reg_num 2645 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c data->reg_num, &data->val_out); reg_num 2648 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c data->reg_num, data->val_in); reg_num 914 drivers/net/ethernet/dec/tulip/tulip_core.c unsigned int regnum = data->reg_num; reg_num 1461 drivers/net/ethernet/dec/tulip/winbond-840.c data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f); reg_num 1467 drivers/net/ethernet/dec/tulip/winbond-840.c mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in); reg_num 89 drivers/net/ethernet/dlink/dl2k.c static int mii_read (struct net_device *dev, int phy_addr, int reg_num); reg_num 90 drivers/net/ethernet/dlink/dl2k.c static int mii_write (struct net_device *dev, int phy_addr, int reg_num, reg_num 1363 drivers/net/ethernet/dlink/dl2k.c miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num); reg_num 1368 drivers/net/ethernet/dlink/dl2k.c mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in); reg_num 1438 drivers/net/ethernet/dlink/dl2k.c mii_read (struct net_device *dev, int phy_addr, int reg_num) reg_num 1448 drivers/net/ethernet/dlink/dl2k.c cmd = (0x06 << 10 | phy_addr << 5 | reg_num); reg_num 1466 drivers/net/ethernet/dlink/dl2k.c mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data) reg_num 1474 drivers/net/ethernet/dlink/dl2k.c cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data; reg_num 1989 drivers/net/ethernet/hisilicon/hns/hns_enet.c u32 *data, reg_num, i; reg_num 1992 drivers/net/ethernet/hisilicon/hns/hns_enet.c reg_num = ops->get_regs_len(priv->ae_handle); reg_num 1993 drivers/net/ethernet/hisilicon/hns/hns_enet.c reg_num = (reg_num + 3ul) & ~3ul; reg_num 1994 drivers/net/ethernet/hisilicon/hns/hns_enet.c data = kcalloc(reg_num, sizeof(u32), GFP_KERNEL); reg_num 1997 drivers/net/ethernet/hisilicon/hns/hns_enet.c for (i = 0; i < reg_num; i += 4) reg_num 1135 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c u32 reg_num; reg_num 1145 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c reg_num = ops->get_regs_len(priv->ae_handle); reg_num 1146 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c if (reg_num > 0) reg_num 1147 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c return reg_num * sizeof(u32); reg_num 1149 drivers/net/ethernet/hisilicon/hns/hns_ethtool.c return reg_num; /* error code */ reg_num 501 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c u32 reg_num; reg_num 510 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg_num = le32_to_cpu(*desc_data); reg_num 512 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *desc_num = 1 + ((reg_num - 3) >> 2) + reg_num 513 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c (u32)(((reg_num - 3) & 0x3) ? 1 : 0); reg_num 9831 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c int entries_per_desc, reg_num, separator_num, desc_index, index, i; reg_num 9836 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg_num = entries_per_desc * bd_num; reg_num 9837 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c separator_num = REG_NUM_PER_LINE - (reg_num & REG_NUM_REMAIN_MASK); reg_num 9838 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c for (i = 0; i < reg_num; i++) { reg_num 9846 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c return reg_num + separator_num; reg_num 9924 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c int i, j, reg_num, separator_num; reg_num 9929 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg_num = ARRAY_SIZE(cmdq_reg_addr_list); reg_num 9930 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); reg_num 9931 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c for (i = 0; i < reg_num; i++) reg_num 9935 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c data_num_sum = reg_num + separator_num; reg_num 9937 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg_num = ARRAY_SIZE(common_reg_addr_list); reg_num 9938 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); reg_num 9939 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c for (i = 0; i < reg_num; i++) reg_num 9943 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c data_num_sum += reg_num + separator_num; reg_num 9945 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg_num = ARRAY_SIZE(ring_reg_addr_list); reg_num 9946 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); reg_num 9948 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c for (i = 0; i < reg_num; i++) reg_num 9955 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c data_num_sum += (reg_num + separator_num) * kinfo->num_tqps; reg_num 9957 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg_num = ARRAY_SIZE(tqp_intr_reg_addr_list); reg_num 9958 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); reg_num 9960 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c for (i = 0; i < reg_num; i++) reg_num 9967 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c data_num_sum += (reg_num + separator_num) * (hdev->num_msi_used - 1); reg_num 10021 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c int i, reg_num, separator_num, ret; reg_num 10041 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg_num = regs_num_32_bit; reg_num 10042 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg += reg_num; reg_num 10043 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); reg_num 10053 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg_num = regs_num_64_bit * 2; reg_num 10054 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg += reg_num; reg_num 10055 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); reg_num 2326 drivers/net/ethernet/ibm/emac/core.c data->reg_num); reg_num 2330 drivers/net/ethernet/ibm/emac/core.c emac_mdio_write(ndev, dev->phy.address, data->reg_num, reg_num 4761 drivers/net/ethernet/intel/e1000/e1000_main.c if (e1000_read_phy_reg(hw, data->reg_num & 0x1F, reg_num 4769 drivers/net/ethernet/intel/e1000/e1000_main.c if (data->reg_num & ~(0x1F)) reg_num 4773 drivers/net/ethernet/intel/e1000/e1000_main.c if (e1000_write_phy_reg(hw, data->reg_num, reg_num 4780 drivers/net/ethernet/intel/e1000/e1000_main.c switch (data->reg_num) { reg_num 4815 drivers/net/ethernet/intel/e1000/e1000_main.c switch (data->reg_num) { reg_num 6095 drivers/net/ethernet/intel/e1000e/netdev.c switch (data->reg_num & 0x1F) { reg_num 8528 drivers/net/ethernet/intel/igb/igb_main.c if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, reg_num 2456 drivers/net/ethernet/marvell/skge.c err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); reg_num 2458 drivers/net/ethernet/marvell/skge.c err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); reg_num 2467 drivers/net/ethernet/marvell/skge.c err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f, reg_num 2470 drivers/net/ethernet/marvell/skge.c err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f, reg_num 1383 drivers/net/ethernet/marvell/sky2.c err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); reg_num 1392 drivers/net/ethernet/marvell/sky2.c err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, reg_num 5845 drivers/net/ethernet/micrel/ksz884x.c if (data->phy_id != priv->id || data->reg_num >= 6) reg_num 5848 drivers/net/ethernet/micrel/ksz884x.c hw_r_phy(hw, port->linked->port_id, data->reg_num, reg_num 5856 drivers/net/ethernet/micrel/ksz884x.c else if (data->phy_id != priv->id || data->reg_num >= 6) reg_num 5859 drivers/net/ethernet/micrel/ksz884x.c hw_w_phy(hw, port->linked->port_id, data->reg_num, reg_num 5886 drivers/net/ethernet/micrel/ksz884x.c static int mdio_read(struct net_device *dev, int phy_id, int reg_num) reg_num 5893 drivers/net/ethernet/micrel/ksz884x.c hw_r_phy(hw, port->linked->port_id, reg_num << 1, &val_out); reg_num 5906 drivers/net/ethernet/micrel/ksz884x.c static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val) reg_num 5915 drivers/net/ethernet/micrel/ksz884x.c hw_w_phy(hw, pi, reg_num << 1, val); reg_num 3094 drivers/net/ethernet/natsemi/natsemi.c data->reg_num & 0x1f); reg_num 3100 drivers/net/ethernet/natsemi/natsemi.c data->reg_num & 0x1f); reg_num 3107 drivers/net/ethernet/natsemi/natsemi.c if ((data->reg_num & 0x1f) == MII_ADVERTISE) reg_num 3109 drivers/net/ethernet/natsemi/natsemi.c mdio_write(dev, data->reg_num & 0x1f, reg_num 3114 drivers/net/ethernet/natsemi/natsemi.c if ((data->reg_num & 0x1f) == MII_ADVERTISE) reg_num 3119 drivers/net/ethernet/natsemi/natsemi.c data->reg_num & 0x1f, reg_num 1349 drivers/net/ethernet/packetengines/yellowfin.c data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f); reg_num 1355 drivers/net/ethernet/packetengines/yellowfin.c switch (data->reg_num) { reg_num 1366 drivers/net/ethernet/packetengines/yellowfin.c mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in); reg_num 2225 drivers/net/ethernet/sis/sis900.c data->val_out = mdio_read(net_dev, data->phy_id & 0x1f, data->reg_num & 0x1f); reg_num 2229 drivers/net/ethernet/sis/sis900.c mdio_write(net_dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in); reg_num 4782 drivers/net/ethernet/sun/cassini.c data->val_out = cas_phy_read(cp, data->reg_num & 0x1f); reg_num 4791 drivers/net/ethernet/sun/cassini.c rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in); reg_num 2716 drivers/net/ethernet/sun/sungem.c data->reg_num & 0x1f); reg_num 2721 drivers/net/ethernet/sun/sungem.c __sungem_phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f, reg_num 975 drivers/net/ethernet/ti/tlan.c data->reg_num & 0x1f, &data->val_out); reg_num 981 drivers/net/ethernet/ti/tlan.c data->reg_num & 0x1f, data->val_in); reg_num 2382 drivers/net/ethernet/via/via-velocity.c if (velocity_mii_read(vptr->mac_regs, miidata->reg_num & 0x1f, &(miidata->val_out)) < 0) reg_num 2387 drivers/net/ethernet/via/via-velocity.c err = velocity_mii_write(vptr->mac_regs, miidata->reg_num & 0x1f, miidata->val_in); reg_num 1429 drivers/net/ethernet/xircom/xirc2ps_cs.c data->phy_id, data->reg_num, data->val_in, data->val_out); reg_num 1440 drivers/net/ethernet/xircom/xirc2ps_cs.c data->reg_num & 0x1f); reg_num 1443 drivers/net/ethernet/xircom/xirc2ps_cs.c mii_wr(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in, reg_num 531 drivers/net/mdio.c u16 addr = mii_data->reg_num; reg_num 595 drivers/net/mii.c mii_data->reg_num &= mii_if->reg_num_mask; reg_num 605 drivers/net/mii.c mii_data->reg_num); reg_num 612 drivers/net/mii.c switch(mii_data->reg_num) { reg_num 638 drivers/net/mii.c mii_data->reg_num, val); reg_num 75 drivers/net/phy/fixed_phy.c static int fixed_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num) reg_num 97 drivers/net/phy/fixed_phy.c return swphy_read_reg(reg_num, &state); reg_num 104 drivers/net/phy/fixed_phy.c static int fixed_mdio_write(struct mii_bus *bus, int phy_addr, int reg_num, reg_num 414 drivers/net/phy/phy.c devad = MII_ADDR_C45 | devad << 16 | mii_data->reg_num; reg_num 417 drivers/net/phy/phy.c devad = mii_data->reg_num; reg_num 427 drivers/net/phy/phy.c devad = MII_ADDR_C45 | devad << 16 | mii_data->reg_num; reg_num 430 drivers/net/phy/phy.c devad = mii_data->reg_num; reg_num 1637 drivers/net/phy/phylink.c ret = phylink_phy_read(pl, mii->phy_id, mii->reg_num); reg_num 1645 drivers/net/phy/phylink.c ret = phylink_phy_write(pl, mii->phy_id, mii->reg_num, reg_num 1660 drivers/net/phy/phylink.c ret = phylink_mii_read(pl, mii->phy_id, mii->reg_num); reg_num 1668 drivers/net/phy/phylink.c ret = phylink_mii_write(pl, mii->phy_id, mii->reg_num, reg_num 5413 drivers/net/usb/r8152.c data->val_out = r8152_mdio_read(tp, data->reg_num); reg_num 5423 drivers/net/usb/r8152.c r8152_mdio_write(tp, data->reg_num, data->val_in); reg_num 2091 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw8822c_dpk_restore_registers(struct rtw_dev *rtwdev, u32 reg_num, reg_num 2094 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_restore_reg(rtwdev, bckp, reg_num); reg_num 2101 drivers/net/wireless/realtek/rtw88/rtw8822c.c u32 reg_num, struct rtw_backup_info *bckp) reg_num 2105 drivers/net/wireless/realtek/rtw88/rtw8822c.c for (i = 0; i < reg_num; i++) { reg_num 27 drivers/pinctrl/intel/pinctrl-cannonlake.c .reg_num = (r), \ reg_num 25 drivers/pinctrl/intel/pinctrl-cedarfork.c .reg_num = (r), \ reg_num 25 drivers/pinctrl/intel/pinctrl-denverton.c .reg_num = (n), \ reg_num 26 drivers/pinctrl/intel/pinctrl-icelake.c .reg_num = (r), \ reg_num 220 drivers/pinctrl/intel/pinctrl-intel.c offset = community->hostown_offset + padgrp->reg_num * 4; reg_num 270 drivers/pinctrl/intel/pinctrl-intel.c offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8; reg_num 275 drivers/pinctrl/intel/pinctrl-intel.c offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; reg_num 986 drivers/pinctrl/intel/pinctrl-intel.c gpp = padgrp->reg_num; reg_num 1011 drivers/pinctrl/intel/pinctrl-intel.c gpp = padgrp->reg_num; reg_num 1126 drivers/pinctrl/intel/pinctrl-intel.c padgrp->reg_num * 4); reg_num 1128 drivers/pinctrl/intel/pinctrl-intel.c padgrp->reg_num * 4); reg_num 1291 drivers/pinctrl/intel/pinctrl-intel.c gpps[i].reg_num = i; reg_num 61 drivers/pinctrl/intel/pinctrl-intel.h unsigned int reg_num; reg_num 41 drivers/pinctrl/intel/pinctrl-sunrisepoint.c .reg_num = (r), \ reg_num 342 drivers/power/supply/max1721x_battery.c "max1721x-%012X", (unsigned int)sl->reg_num.id); reg_num 5886 drivers/s390/net/qeth_core_main.c mii_data->phy_id, mii_data->reg_num); reg_num 167 drivers/scsi/wd33c93.c read_wd33c93(const wd33c93_regs regs, uchar reg_num) reg_num 171 drivers/scsi/wd33c93.c outb(reg_num, regs.SASR); reg_num 195 drivers/scsi/wd33c93.c write_wd33c93(const wd33c93_regs regs, uchar reg_num, uchar value) reg_num 197 drivers/scsi/wd33c93.c outb(reg_num, regs.SASR); reg_num 225 drivers/scsi/wd33c93.c read_wd33c93(const wd33c93_regs regs, uchar reg_num) reg_num 227 drivers/scsi/wd33c93.c *regs.SASR = reg_num; reg_num 253 drivers/scsi/wd33c93.c write_wd33c93(const wd33c93_regs regs, uchar reg_num, uchar value) reg_num 255 drivers/scsi/wd33c93.c *regs.SASR = reg_num; reg_num 90 drivers/soc/fsl/qe/ucc.c unsigned int *reg_num, unsigned int *shift) reg_num 94 drivers/soc/fsl/qe/ucc.c *reg_num = cmx + 1; reg_num 102 drivers/soc/fsl/qe/ucc.c unsigned int reg_num; reg_num 109 drivers/soc/fsl/qe/ucc.c get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift); reg_num 123 drivers/soc/fsl/qe/ucc.c unsigned int reg_num; reg_num 135 drivers/soc/fsl/qe/ucc.c get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift); reg_num 137 drivers/soc/fsl/qe/ucc.c switch (reg_num) { reg_num 533 drivers/staging/android/vsoc.c u32 reg_num; reg_num 540 drivers/staging/android/vsoc.c reg_num = iminor(file_inode(filp)); reg_num 541 drivers/staging/android/vsoc.c reg_data = vsoc_dev.regions_data + reg_num; reg_num 583 drivers/staging/android/vsoc.c writel(reg_num, vsoc_dev.regs + DOORBELL); reg_num 591 drivers/staging/android/vsoc.c writel(reg_num, vsoc_dev.regs + DOORBELL); reg_num 723 drivers/staging/android/vsoc.c int reg_num = region_data - vsoc_dev.regions_data; reg_num 728 drivers/staging/android/vsoc.c if (unlikely(reg_num < 0 || reg_num 729 drivers/staging/android/vsoc.c reg_num >= vsoc_dev.layout->region_count)) { reg_num 732 drivers/staging/android/vsoc.c region_data, reg_num); reg_num 735 drivers/staging/android/vsoc.c if (unlikely(vsoc_dev.regions_data + reg_num != region_data)) { reg_num 738 drivers/staging/android/vsoc.c region_data, reg_num); reg_num 137 drivers/staging/media/hantro/hantro_g1_h264_dec.c int reg_num; reg_num 184 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg_num = 0; reg_num 192 drivers/staging/media/hantro/hantro_g1_h264_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_BD_REF_PIC(reg_num++)); reg_num 212 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg_num = 0; reg_num 220 drivers/staging/media/hantro/hantro_g1_h264_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(reg_num++)); reg_num 153 drivers/staging/media/meson/vdec/vdec_helpers.c u32 reg_base[], u32 reg_num[]) reg_num 191 drivers/staging/media/meson/vdec/vdec_helpers.c if (reg_num_cur >= reg_num[reg_base_cur]) { reg_num 20 drivers/staging/media/meson/vdec/vdec_helpers.h u32 reg_base[], u32 reg_num[]); reg_num 86 drivers/staging/media/soc_camera/soc_ov5642.c u16 reg_num; reg_num 724 drivers/staging/media/soc_camera/soc_ov5642.c while (vals->reg_num != 0xffff || vals->value != 0xff) { reg_num 725 drivers/staging/media/soc_camera/soc_ov5642.c int ret = reg_write(client, vals->reg_num, vals->value); reg_num 1022 drivers/video/fbdev/via/hw.c iga1_fetch_count_reg.reg_num; reg_num 1029 drivers/video/fbdev/via/hw.c iga2_fetch_count_reg.reg_num; reg_num 1161 drivers/video/fbdev/via/hw.c display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num; reg_num 1169 drivers/video/fbdev/via/hw.c iga1_fifo_threshold_select_reg.reg_num; reg_num 1180 drivers/video/fbdev/via/hw.c iga1_fifo_high_threshold_select_reg.reg_num; reg_num 1192 drivers/video/fbdev/via/hw.c iga1_display_queue_expire_num_reg.reg_num; reg_num 1315 drivers/video/fbdev/via/hw.c iga2_fifo_depth_select_reg.reg_num; reg_num 1328 drivers/video/fbdev/via/hw.c iga2_fifo_depth_select_reg.reg_num; reg_num 1340 drivers/video/fbdev/via/hw.c iga2_fifo_threshold_select_reg.reg_num; reg_num 1351 drivers/video/fbdev/via/hw.c iga2_fifo_high_threshold_select_reg.reg_num; reg_num 1363 drivers/video/fbdev/via/hw.c iga2_display_queue_expire_num_reg.reg_num; reg_num 355 drivers/video/fbdev/via/hw.h int reg_num; reg_num 361 drivers/video/fbdev/via/hw.h int reg_num; reg_num 367 drivers/video/fbdev/via/hw.h int reg_num; reg_num 373 drivers/video/fbdev/via/hw.h int reg_num; reg_num 379 drivers/video/fbdev/via/hw.h int reg_num; reg_num 385 drivers/video/fbdev/via/hw.h int reg_num; reg_num 391 drivers/video/fbdev/via/hw.h int reg_num; reg_num 397 drivers/video/fbdev/via/hw.h int reg_num; reg_num 403 drivers/video/fbdev/via/hw.h int reg_num; reg_num 409 drivers/video/fbdev/via/hw.h int reg_num; reg_num 420 drivers/video/fbdev/via/hw.h int reg_num; reg_num 425 drivers/video/fbdev/via/hw.h int reg_num; reg_num 436 drivers/video/fbdev/via/hw.h int reg_num; reg_num 441 drivers/video/fbdev/via/hw.h int reg_num; reg_num 446 drivers/video/fbdev/via/hw.h int reg_num; reg_num 451 drivers/video/fbdev/via/hw.h int reg_num; reg_num 464 drivers/video/fbdev/via/hw.h int reg_num; reg_num 469 drivers/video/fbdev/via/hw.h int reg_num; reg_num 500 drivers/video/fbdev/via/hw.h int reg_num; reg_num 505 drivers/video/fbdev/via/hw.h int reg_num; reg_num 510 drivers/video/fbdev/via/hw.h int reg_num; reg_num 515 drivers/video/fbdev/via/hw.h int reg_num; reg_num 520 drivers/video/fbdev/via/hw.h int reg_num; reg_num 525 drivers/video/fbdev/via/hw.h int reg_num; reg_num 530 drivers/video/fbdev/via/hw.h int reg_num; reg_num 535 drivers/video/fbdev/via/hw.h int reg_num; reg_num 357 drivers/video/fbdev/via/lcd.c reg_num; reg_num 378 drivers/video/fbdev/via/lcd.c lcd_scaling_factor.lcd_hor_scaling_factor.reg_num; reg_num 401 drivers/video/fbdev/via/lcd.c reg_num; reg_num 422 drivers/video/fbdev/via/lcd.c lcd_scaling_factor.lcd_ver_scaling_factor.reg_num; reg_num 69 drivers/video/fbdev/via/vt1636.c int reg_num, i; reg_num 72 drivers/video/fbdev/via/vt1636.c reg_num = ARRAY_SIZE(common_init_data); reg_num 73 drivers/video/fbdev/via/vt1636.c for (i = 0; i < reg_num; i++) reg_num 30 drivers/w1/slaves/w1_ds2405.c u64 dev_addr = le64_to_cpu(*(u64 *)&sl->reg_num); reg_num 182 drivers/w1/slaves/w1_ds2405.c u64 dev_addr = le64_to_cpu(*(u64 *)&sl->reg_num); reg_num 295 drivers/w1/slaves/w1_ds2408.c u64 rn = le64_to_cpu(*((u64*)&sl->reg_num)); reg_num 203 drivers/w1/slaves/w1_ds250x.c sl->master->bus_master->dev_id, sl->reg_num.family, reg_num 204 drivers/w1/slaves/w1_ds250x.c (unsigned long long)sl->reg_num.id); reg_num 208 drivers/w1/slaves/w1_ds250x.c sl->reg_num.family, reg_num 209 drivers/w1/slaves/w1_ds250x.c (unsigned long long)sl->reg_num.id); reg_num 651 drivers/w1/slaves/w1_therm.c struct w1_reg_num *reg_num; reg_num 676 drivers/w1/slaves/w1_therm.c reg_num = (struct w1_reg_num *) &rn; reg_num 677 drivers/w1/slaves/w1_therm.c if (reg_num->family == W1_42_FINISHED_BYTE) reg_num 679 drivers/w1/slaves/w1_therm.c if (sl->reg_num.id == reg_num->id) reg_num 100 drivers/w1/w1.c ssize_t count = sizeof(sl->reg_num); reg_num 102 drivers/w1/w1.c memcpy(buf, (u8 *)&sl->reg_num, count); reg_num 446 drivers/w1/w1.c if (sl->reg_num.family == rn->family && reg_num 447 drivers/w1/w1.c sl->reg_num.id == rn->id && reg_num 448 drivers/w1/w1.c sl->reg_num.crc == rn->crc) { reg_num 604 drivers/w1/w1.c err = add_uevent_var(env, "W1_FID=%02X", sl->reg_num.family); reg_num 609 drivers/w1/w1.c (unsigned long long)sl->reg_num.id); reg_num 685 drivers/w1/w1.c (unsigned int) sl->reg_num.family, reg_num 686 drivers/w1/w1.c (unsigned long long) sl->reg_num.id); reg_num 689 drivers/w1/w1.c (unsigned int) sl->reg_num.family, reg_num 690 drivers/w1/w1.c (unsigned long long) sl->reg_num.id); reg_num 739 drivers/w1/w1.c memcpy(&sl->reg_num, rn, sizeof(sl->reg_num)); reg_num 799 drivers/w1/w1.c memcpy(msg.id.id, &sl->reg_num, sizeof(msg.id)); reg_num 857 drivers/w1/w1.c if (sl->reg_num.family == id->family && reg_num 858 drivers/w1/w1.c sl->reg_num.id == id->id && reg_num 859 drivers/w1/w1.c sl->reg_num.crc == id->crc) { reg_num 894 drivers/w1/w1.c && sl->reg_num.family == f->fid) || reg_num 899 drivers/w1/w1.c memcpy(&rn, &sl->reg_num, sizeof(rn)); reg_num 396 drivers/w1/w1_io.c u64 rn = le64_to_cpu(*((u64*)&sl->reg_num)); reg_num 276 drivers/w1/w1_netlink.c memcpy(&rn, &sl->reg_num, sizeof(rn)); reg_num 391 drivers/w1/w1_netlink.c __func__, sl->reg_num.family, (unsigned long long)sl->reg_num.id, reg_num 392 drivers/w1/w1_netlink.c sl->reg_num.crc, cmd->cmd, cmd->len); reg_num 985 include/linux/mlx5/driver.h u16 reg_num, int arg, int write); reg_num 69 include/linux/w1.h struct w1_reg_num reg_num; reg_num 161 include/uapi/linux/mii.h __u16 reg_num;