reg_name 40 arch/alpha/lib/stacktrace.c static char reg_name[][4] = { reg_name 62 arch/alpha/lib/stacktrace.c printk("\t\t%s / 0x%016lx\n", reg_name[reg], value); reg_name 29 drivers/cpufreq/cpufreq-dt.c const char *reg_name; reg_name 209 drivers/cpufreq/cpufreq-dt.c priv->reg_name = name; reg_name 319 drivers/cpufreq/cpufreq-dt.c if (priv->reg_name) reg_name 575 drivers/crypto/cavium/zip/zip_main.c while (zipregs[i].reg_name) { reg_name 579 drivers/crypto/cavium/zip/zip_main.c zipregs[i].reg_name, val); reg_name 67 drivers/crypto/cavium/zip/zip_main.h char *reg_name; reg_name 100 drivers/crypto/ccree/cc_driver.h #define CC_REG(reg_name) CC_ ## reg_name ## _REG_OFFSET reg_name 893 drivers/crypto/hisilicon/qm.c char *reg_name; reg_name 943 drivers/crypto/hisilicon/qm.c while (regs->reg_name) { reg_name 945 drivers/crypto/hisilicon/qm.c seq_printf(s, "%s= 0x%08x\n", regs->reg_name, val); reg_name 23 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_SET_BITS(reg_name, mask) \ reg_name 24 drivers/crypto/ux500/cryp/cryp_p.h writel_relaxed((readl_relaxed(reg_name) | mask), reg_name) reg_name 26 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_WRITE_BIT(reg_name, val, mask) \ reg_name 27 drivers/crypto/ux500/cryp/cryp_p.h writel_relaxed(((readl_relaxed(reg_name) & ~(mask)) |\ reg_name 28 drivers/crypto/ux500/cryp/cryp_p.h ((val) & (mask))), reg_name) reg_name 30 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_TEST_BITS(reg_name, val) \ reg_name 31 drivers/crypto/ux500/cryp/cryp_p.h (readl_relaxed(reg_name) & (val)) reg_name 98 drivers/crypto/ux500/hash/hash_alg.h #define HASH_SET_BITS(reg_name, mask) \ reg_name 99 drivers/crypto/ux500/hash/hash_alg.h writel_relaxed((readl_relaxed(reg_name) | mask), reg_name) reg_name 101 drivers/crypto/ux500/hash/hash_alg.h #define HASH_CLEAR_BITS(reg_name, mask) \ reg_name 102 drivers/crypto/ux500/hash/hash_alg.h writel_relaxed((readl_relaxed(reg_name) & ~mask), reg_name) reg_name 54 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c #define FN(reg_name, field_name) \ reg_name 50 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c #define FN(reg_name, field_name) \ reg_name 35 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c #define SR(reg_name)\ reg_name 36 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c .reg_name = mm ## reg_name reg_name 39 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c #define SRI(reg_name, block, id)\ reg_name 40 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c .reg_name = mm ## block ## id ## _ ## reg_name reg_name 37 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c #define SR(reg_name)\ reg_name 38 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c .reg_name = mm ## reg_name reg_name 41 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c #define SRI(reg_name, block, id)\ reg_name 42 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c .reg_name = mm ## block ## id ## _ ## reg_name reg_name 43 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c #define CLK_REG(reg_name, block, inst)\ reg_name 44 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ reg_name 45 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c mm ## block ## _ ## inst ## _ ## reg_name reg_name 47 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c #define REG(reg_name) \ reg_name 48 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c CLK_REG(reg_name, CLK0, 0) reg_name 62 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c #define REG(reg_name) \ reg_name 63 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c (MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) reg_name 65 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c #define FN(reg_name, field) \ reg_name 66 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c FD(reg_name##__##field) reg_name 41 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c #define FN(reg_name, field_name) \ reg_name 51 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c #define SR(reg_name)\ reg_name 52 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ reg_name 53 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c mm ## reg_name reg_name 52 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c #define REG(reg_name) \ reg_name 53 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) reg_name 35 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c #define REG(reg_name) \ reg_name 36 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c (MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) reg_name 38 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c #define FN(reg_name, field) \ reg_name 39 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c FD(reg_name##__##field) reg_name 44 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c #define FN(reg_name, field_name) \ reg_name 86 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h #define ABM_SF(reg_name, field_name, post_fix)\ reg_name 87 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 45 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c #define FN(reg_name, field_name) \ reg_name 51 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c #define AZ_REG_READ(reg_name) \ reg_name 52 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c read_indirect_azalia_reg(audio, IX_REG(reg_name)) reg_name 54 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c #define AZ_REG_WRITE(reg_name, value) \ reg_name 55 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c write_indirect_azalia_reg(audio, IX_REG(reg_name), value) reg_name 44 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h #define SF(reg_name, field_name, post_fix)\ reg_name 45 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 37 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c #define REG(reg_name)\ reg_name 38 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c (aux110->regs->reg_name) reg_name 42 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c #define FN(reg_name, field_name) \ reg_name 51 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c #define FN(reg_name, field_name) \ reg_name 45 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h #define CS_SF(reg_name, field_name, post_fix)\ reg_name 46 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 44 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c #define FN(reg_name, field_name) \ reg_name 74 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h #define DMCU_SF(reg_name, field_name, post_fix)\ reg_name 75 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 37 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c #define FN(reg_name, field_name) \ reg_name 442 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ reg_name 443 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix reg_name 445 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\ reg_name 446 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix reg_name 40 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c #define FN(reg_name, field_name) \ reg_name 98 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h #define I2C_SF(reg_name, field_name, post_fix)\ reg_name 99 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 36 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c #define FN(reg_name, field_name) \ reg_name 64 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h #define IPP_SF(reg_name, field_name, post_fix)\ reg_name 65 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 36 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c #define FN(reg_name, field_name) \ reg_name 126 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h #define SFB(blk_name, reg_name, field_name, post_fix)\ reg_name 127 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix reg_name 39 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c #define FN(reg_name, field_name) \ reg_name 84 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h #define OPP_SF(reg_name, field_name, post_fix)\ reg_name 85 drivers/gpu/drm/amd/display/dc/dce/dce_opp.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 41 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c #define FN(reg_name, field_name) \ reg_name 115 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h #define SE_SF(reg_name, field_name, post_fix)\ reg_name 116 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 36 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c #define FN(reg_name, field_name) \ reg_name 111 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h #define XFM_SF(reg_name, field_name, post_fix)\ reg_name 112 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 134 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c #define SR(reg_name)\ reg_name 135 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c .reg_name = mm ## reg_name reg_name 138 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c #define SRI(reg_name, block, id)\ reg_name 139 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c .reg_name = mm ## block ## id ## _ ## reg_name reg_name 450 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c #define SRII(reg_name, block, id)\ reg_name 451 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c .reg_name[id] = mm ## block ## id ## _ ## reg_name reg_name 82 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c #define FN(reg_name, field_name) \ reg_name 145 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c #define SR(reg_name)\ reg_name 146 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c .reg_name = mm ## reg_name reg_name 149 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c #define SRI(reg_name, block, id)\ reg_name 150 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c .reg_name = mm ## block ## id ## _ ## reg_name reg_name 492 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c #define SRII(reg_name, block, id)\ reg_name 493 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c .reg_name[id] = mm ## block ## id ## _ ## reg_name reg_name 144 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c #define SR(reg_name)\ reg_name 145 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c .reg_name = mm ## reg_name reg_name 148 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c #define SRI(reg_name, block, id)\ reg_name 149 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c .reg_name = mm ## block ## id ## _ ## reg_name reg_name 470 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c #define SRII(reg_name, block, id)\ reg_name 471 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c .reg_name[id] = mm ## block ## id ## _ ## reg_name reg_name 46 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c #define FN(reg_name, field_name) \ reg_name 137 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c #define SR(reg_name)\ reg_name 138 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ reg_name 139 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c mm ## reg_name reg_name 141 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c #define SRI(reg_name, block, id)\ reg_name 142 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 143 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c mm ## block ## id ## _ ## reg_name reg_name 152 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c #define MMHUB_SR(reg_name)\ reg_name 153 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ reg_name 154 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c mm ## reg_name reg_name 703 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c #define SRII(reg_name, block, id)\ reg_name 704 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 705 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c mm ## block ## id ## _ ## reg_name reg_name 42 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c #define CRTC_REG_UPDATE_N(reg_name, n, ...) \ reg_name 43 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c generic_reg_update_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__) reg_name 45 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c #define CRTC_REG_SET_N(reg_name, n, ...) \ reg_name 46 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c generic_reg_set_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__) reg_name 151 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c #define SR(reg_name)\ reg_name 152 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c .reg_name = mm ## reg_name reg_name 155 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c #define SRI(reg_name, block, id)\ reg_name 156 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c .reg_name = mm ## block ## id ## _ ## reg_name reg_name 562 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c #define SRII(reg_name, block, id)\ reg_name 563 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c .reg_name[id] = mm ## block ## id ## _ ## reg_name reg_name 38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c #define FN(reg_name, field_name) \ reg_name 48 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c #define FN(reg_name, field_name) \ reg_name 37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h #define TF_SF(reg_name, field_name, post_fix)\ reg_name 38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h #define TF2_SF(reg_name, field_name, post_fix)\ reg_name 42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h .field_name = reg_name ## _ ## field_name ## post_fix reg_name 49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c #define FN(reg_name, field_name) \ reg_name 49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c #define FN(reg_name, field_name) \ reg_name 41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c #define FN(reg_name, field_name) \ reg_name 36 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h #define SR(reg_name)\ reg_name 37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ reg_name 38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h mm ## reg_name reg_name 40 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h #define SRI(reg_name, block, id)\ reg_name 41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h mm ## block ## id ## _ ## reg_name reg_name 45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h #define SRII(reg_name, block, id)\ reg_name 46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 47 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h mm ## block ## id ## _ ## reg_name reg_name 49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h #define SF(reg_name, field_name, post_fix)\ reg_name 50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c #define FN(reg_name, field_name) \ reg_name 147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h #define HUBBUB_SF(reg_name, field_name, post_fix)\ reg_name 148 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c #define FN(reg_name, field_name) \ reg_name 238 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h #define HUBP_SF(reg_name, field_name, post_fix)\ reg_name 239 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 64 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c #define FN(reg_name, field_name) \ reg_name 36 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c #define FN(reg_name, field_name) \ reg_name 74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h #define IPP_SF(reg_name, field_name, post_fix)\ reg_name 75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c #define FN(reg_name, field_name) \ reg_name 1340 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c #define HPD_REG_READ(reg_name) \ reg_name 1341 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c dm_read_reg(CTX, HPD_REG(reg_name)) reg_name 1343 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c #define HPD_REG_UPDATE_N(reg_name, n, ...) \ reg_name 1345 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c HPD_REG(reg_name), \ reg_name 1348 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c #define HPD_REG_UPDATE(reg_name, field, val) \ reg_name 1349 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c HPD_REG_UPDATE_N(reg_name, 1, \ reg_name 1350 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c FN(reg_name, field), val) reg_name 1372 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c #define AUX_REG_READ(reg_name) \ reg_name 1373 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c dm_read_reg(CTX, AUX_REG(reg_name)) reg_name 1375 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c #define AUX_REG_UPDATE_N(reg_name, n, ...) \ reg_name 1377 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c AUX_REG(reg_name), \ reg_name 1380 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c #define AUX_REG_UPDATE(reg_name, field, val) \ reg_name 1381 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c AUX_REG_UPDATE_N(reg_name, 1, \ reg_name 1382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c FN(reg_name, field), val) reg_name 128 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h #define LE_SF(reg_name, field_name, post_fix)\ reg_name 129 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 36 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c #define FN(reg_name, field_name) \ reg_name 36 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c #define FN(reg_name, field_name) \ reg_name 33 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h #define OPP_SF(reg_name, field_name, post_fix)\ reg_name 34 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c #define FN(reg_name, field_name) \ reg_name 169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c #define SR(reg_name)\ reg_name 170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ reg_name 171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c mm ## reg_name reg_name 173 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c #define SRI(reg_name, block, id)\ reg_name 174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 175 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c mm ## block ## id ## _ ## reg_name reg_name 178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c #define SRII(reg_name, block, id)\ reg_name 179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 180 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c mm ## block ## id ## _ ## reg_name reg_name 189 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c #define NBIO_SR(reg_name)\ reg_name 190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ reg_name 191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c mm ## reg_name reg_name 200 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c #define MMHUB_SR(reg_name)\ reg_name 201 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ reg_name 202 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c mm ## reg_name reg_name 41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c #define FN(reg_name, field_name) \ reg_name 178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h #define SE_SF(reg_name, field_name, post_fix)\ reg_name 179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c #define FN(reg_name, field_name) \ reg_name 44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h #define DCCG_SF(reg_name, field_name, post_fix)\ reg_name 45 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h #define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\ reg_name 48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h .field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix reg_name 48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c #define FN(reg_name, field_name) \ reg_name 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c #define FN(reg_name, field_name) \ reg_name 68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c #define FN(reg_name, field_name) \ reg_name 88 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h #define DSC_SF(reg_name, field_name, post_fix)\ reg_name 89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h #define DSC2_SF(reg_name, field_name, post_fix)\ reg_name 93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h .field_name = reg_name ## _ ## field_name ## post_fix reg_name 42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c #define FN(reg_name, field_name) \ reg_name 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h #define SR(reg_name)\ reg_name 38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ reg_name 39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h mm ## reg_name reg_name 41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h #define SRI(reg_name, block, id)\ reg_name 42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h mm ## block ## id ## _ ## reg_name reg_name 45 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h #define SRI2(reg_name, block, id)\ reg_name 46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ reg_name 47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h mm ## reg_name reg_name 49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h #define SRII(reg_name, block, id)\ reg_name 50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h mm ## block ## id ## _ ## reg_name reg_name 53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h #define SF(reg_name, field_name, post_fix)\ reg_name 54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c #define FN(reg_name, field_name) \ reg_name 38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c #define FN(reg_name, field_name) \ reg_name 48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c #define FN(reg_name, field_name) \ reg_name 40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c #define FN(reg_name, field_name) \ reg_name 64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c #define FN(reg_name, field_name) \ reg_name 46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c #define FN(reg_name, field_name) \ reg_name 269 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c #define AUX_REG_READ(reg_name) \ reg_name 270 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c dm_read_reg(CTX, AUX_REG(reg_name)) reg_name 272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c #define AUX_REG_WRITE(reg_name, val) \ reg_name 273 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c dm_write_reg(CTX, AUX_REG(reg_name), val) reg_name 40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c #define FN(reg_name, field_name) \ reg_name 39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h #define SR(reg_name)\ reg_name 40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ reg_name 41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h mm ## reg_name reg_name 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h #define SRI(reg_name, block, id)\ reg_name 44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 45 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h mm ## block ## id ## _ ## reg_name reg_name 47 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h #define SRI2(reg_name, block, id)\ reg_name 48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ reg_name 49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h mm ## reg_name reg_name 51 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h #define SRII(reg_name, block, id)\ reg_name 52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 53 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h mm ## block ## id ## _ ## reg_name reg_name 55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h #define SF(reg_name, field_name, post_fix)\ reg_name 56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c #define FN(reg_name, field_name) \ reg_name 34 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c #define FN(reg_name, field_name) \ reg_name 33 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h #define OPP_SF(reg_name, field_name, post_fix)\ reg_name 34 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c #define FN(reg_name, field_name) \ reg_name 423 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c #define SR(reg_name)\ reg_name 424 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ reg_name 425 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c mm ## reg_name reg_name 427 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c #define SRI(reg_name, block, id)\ reg_name 428 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 429 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c mm ## block ## id ## _ ## reg_name reg_name 431 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c #define SRIR(var_name, reg_name, block, id)\ reg_name 432 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 433 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c mm ## block ## id ## _ ## reg_name reg_name 435 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c #define SRII(reg_name, block, id)\ reg_name 436 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 437 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c mm ## block ## id ## _ ## reg_name reg_name 439 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c #define DCCG_SRII(reg_name, block, id)\ reg_name 440 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 441 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c mm ## block ## id ## _ ## reg_name reg_name 450 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c #define NBIO_SR(reg_name)\ reg_name 451 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ reg_name 452 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c mm ## reg_name reg_name 461 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c #define MMHUB_SR(reg_name)\ reg_name 462 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ reg_name 463 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c mmMM ## reg_name reg_name 41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c #define FN(reg_name, field_name) \ reg_name 38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c #define FN(reg_name, field_name) \ reg_name 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h #define SRI(reg_name, block, id)\ reg_name 38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h mm ## block ## id ## _ ## reg_name reg_name 41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h #define SF(reg_name, field_name, post_fix)\ reg_name 42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 39 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c #define FN(reg_name, field_name) \ reg_name 49 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c #define FN(reg_name, field_name) \ reg_name 37 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c #define FN(reg_name, field_name) \ reg_name 286 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c #define SR(reg_name)\ reg_name 287 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ reg_name 288 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c mm ## reg_name reg_name 290 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c #define SRI(reg_name, block, id)\ reg_name 291 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 292 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c mm ## block ## id ## _ ## reg_name reg_name 294 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c #define SRIR(var_name, reg_name, block, id)\ reg_name 295 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 296 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c mm ## block ## id ## _ ## reg_name reg_name 298 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c #define SRII(reg_name, block, id)\ reg_name 299 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 300 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c mm ## block ## id ## _ ## reg_name reg_name 302 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c #define DCCG_SRII(reg_name, block, id)\ reg_name 303 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 304 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c mm ## block ## id ## _ ## reg_name reg_name 313 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c #define NBIO_SR(reg_name)\ reg_name 314 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ reg_name 315 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c mm ## reg_name reg_name 324 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c #define MMHUB_SR(reg_name)\ reg_name 325 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ reg_name 326 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c mmMM ## reg_name reg_name 111 drivers/gpu/drm/amd/display/dc/dm_services.h #define get_reg_field_value(reg_value, reg_name, reg_field)\ reg_name 114 drivers/gpu/drm/amd/display/dc/dm_services.h reg_name ## __ ## reg_field ## _MASK,\ reg_name 115 drivers/gpu/drm/amd/display/dc/dm_services.h reg_name ## __ ## reg_field ## __SHIFT) reg_name 127 drivers/gpu/drm/amd/display/dc/dm_services.h #define set_reg_field_value(reg_value, value, reg_name, reg_field)\ reg_name 131 drivers/gpu/drm/amd/display/dc/dm_services.h reg_name ## __ ## reg_field ## _MASK,\ reg_name 132 drivers/gpu/drm/amd/display/dc/dm_services.h reg_name ## __ ## reg_field ## __SHIFT) reg_name 165 drivers/gpu/drm/amd/display/dc/dm_services.h #define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\ reg_name 166 drivers/gpu/drm/amd/display/dc/dm_services.h generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \ reg_name 169 drivers/gpu/drm/amd/display/dc/dm_services.h #define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\ reg_name 170 drivers/gpu/drm/amd/display/dc/dm_services.h generic_reg_set_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \ reg_name 173 drivers/gpu/drm/amd/display/dc/dm_services.h #define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\ reg_name 176 drivers/gpu/drm/amd/display/dc/dm_services.h block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ reg_name 177 drivers/gpu/drm/amd/display/dc/dm_services.h block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) reg_name 179 drivers/gpu/drm/amd/display/dc/dm_services.h #define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\ reg_name 183 drivers/gpu/drm/amd/display/dc/dm_services.h block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ reg_name 184 drivers/gpu/drm/amd/display/dc/dm_services.h block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) reg_name 42 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c #define SF_HPD(reg_name, field_name, post_fix)\ reg_name 43 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c .field_name = reg_name ## __ ## field_name ## post_fix reg_name 45 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c #define REG(reg_name)\ reg_name 46 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c mm ## reg_name reg_name 48 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c #define REGI(reg_name, block, id)\ reg_name 49 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c mm ## block ## id ## _ ## reg_name reg_name 83 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c #define SF_DDC(reg_name, field_name, post_fix)\ reg_name 84 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c .field_name = reg_name ## __ ## field_name ## post_fix reg_name 46 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c #define SF_HPD(reg_name, field_name, post_fix)\ reg_name 47 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix reg_name 50 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c #define SF_HPD(reg_name, field_name, post_fix)\ reg_name 51 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix reg_name 60 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c #define REG(reg_name)\ reg_name 61 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name reg_name 63 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c #define REGI(reg_name, block, id)\ reg_name 64 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 65 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c mm ## block ## id ## _ ## reg_name reg_name 96 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c #define SF_DDC(reg_name, field_name, post_fix)\ reg_name 97 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c .field_name = reg_name ## __ ## field_name ## post_fix reg_name 51 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c #define REG(reg_name)\ reg_name 52 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name reg_name 54 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c #define REGI(reg_name, block, id)\ reg_name 55 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 56 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c mm ## block ## id ## _ ## reg_name reg_name 41 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c #define REG(reg_name)\ reg_name 42 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c mm ## reg_name reg_name 83 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c #define SF_DDC(reg_name, field_name, post_fix)\ reg_name 84 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c .field_name = reg_name ## __ ## field_name ## post_fix reg_name 47 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c #define SF_HPD(reg_name, field_name, post_fix)\ reg_name 48 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix reg_name 57 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c #define REG(reg_name)\ reg_name 58 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name reg_name 60 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c #define REGI(reg_name, block, id)\ reg_name 61 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 62 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c mm ## block ## id ## _ ## reg_name reg_name 92 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c #define SF_DDC(reg_name, field_name, post_fix)\ reg_name 93 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c .field_name = reg_name ## __ ## field_name ## post_fix reg_name 128 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c #define SF_GENERIC(reg_name, field_name, post_fix)\ reg_name 129 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c .field_name = reg_name ## __ ## field_name ## post_fix reg_name 51 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c #define REG(reg_name)\ reg_name 52 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name reg_name 54 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c #define REGI(reg_name, block, id)\ reg_name 55 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 56 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c mm ## block ## id ## _ ## reg_name reg_name 60 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c #define REG(reg_name)\ reg_name 61 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name reg_name 63 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c #define SF_HPD(reg_name, field_name, post_fix)\ reg_name 64 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix reg_name 66 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c #define REGI(reg_name, block, id)\ reg_name 67 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 68 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c mm ## block ## id ## _ ## reg_name reg_name 70 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c #define SF(reg_name, field_name, post_fix)\ reg_name 71 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c .field_name = reg_name ## __ ## field_name ## post_fix reg_name 103 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c #define SF_DDC(reg_name, field_name, post_fix)\ reg_name 104 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c .field_name = reg_name ## __ ## field_name ## post_fix reg_name 145 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c #define SF_GENERIC(reg_name, field_name, post_fix)\ reg_name 146 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c .field_name = reg_name ## __ ## field_name ## post_fix reg_name 56 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c #define REG(reg_name)\ reg_name 57 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name reg_name 58 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c #define SF_HPD(reg_name, field_name, post_fix)\ reg_name 59 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c .field_name = reg_name ## __ ## field_name ## post_fix reg_name 58 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c #define REG(reg_name)\ reg_name 59 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name reg_name 61 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c #define SF_HPD(reg_name, field_name, post_fix)\ reg_name 62 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix reg_name 64 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c #define REGI(reg_name, block, id)\ reg_name 65 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 66 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c mm ## block ## id ## _ ## reg_name reg_name 68 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c #define SF(reg_name, field_name, post_fix)\ reg_name 69 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c .field_name = reg_name ## __ ## field_name ## post_fix reg_name 100 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c #define SF_DDC(reg_name, field_name, post_fix)\ reg_name 101 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c .field_name = reg_name ## __ ## field_name ## post_fix reg_name 140 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c #define SF_GENERIC(reg_name, field_name, post_fix)\ reg_name 141 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c .field_name = reg_name ## __ ## field_name ## post_fix reg_name 56 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c #define REG(reg_name)\ reg_name 57 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name reg_name 58 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c #define SF_HPD(reg_name, field_name, post_fix)\ reg_name 59 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c .field_name = reg_name ## __ ## field_name ## post_fix reg_name 41 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c #define FN(reg_name, field_name) \ reg_name 39 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c #define FN(reg_name, field_name) \ reg_name 34 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c #define FN(reg_name, field_name) \ reg_name 39 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c #define FN(reg_name, field_name) \ reg_name 83 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h #define CLK_SRI(reg_name, block, inst)\ reg_name 84 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ reg_name 85 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h mm ## block ## _ ## inst ## _ ## reg_name reg_name 106 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h #define CLK_SF(reg_name, field_name, post_fix)\ reg_name 107 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h .field_name = reg_name ## __ ## field_name ## post_fix reg_name 39 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_READ(reg_name) \ reg_name 40 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h dm_read_reg(CTX, REG(reg_name)) reg_name 42 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_WRITE(reg_name, value) \ reg_name 43 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h dm_write_reg(CTX, REG(reg_name), value) reg_name 54 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_N(reg_name, n, initial_val, ...) \ reg_name 56 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG(reg_name), \ reg_name 60 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define FN(reg_name, field) \ reg_name 61 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FD(reg_name##__##field) reg_name 63 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET(reg_name, initial_val, field, val) \ reg_name 64 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_SET_N(reg_name, 1, initial_val, \ reg_name 65 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, field), val) reg_name 156 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET(reg_name, field, val) \ reg_name 157 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h generic_reg_get(CTX, REG(reg_name), \ reg_name 158 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, field), val) reg_name 160 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_2(reg_name, f1, v1, f2, v2) \ reg_name 161 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h generic_reg_get2(CTX, REG(reg_name), \ reg_name 162 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f1), v1, \ reg_name 163 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f2), v2) reg_name 165 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3) \ reg_name 166 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h generic_reg_get3(CTX, REG(reg_name), \ reg_name 167 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f1), v1, \ reg_name 168 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f2), v2, \ reg_name 169 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f3), v3) reg_name 171 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4) \ reg_name 172 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h generic_reg_get4(CTX, REG(reg_name), \ reg_name 173 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f1), v1, \ reg_name 174 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f2), v2, \ reg_name 175 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f3), v3, \ reg_name 176 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f4), v4) reg_name 178 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ reg_name 179 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h generic_reg_get5(CTX, REG(reg_name), \ reg_name 180 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f1), v1, \ reg_name 181 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f2), v2, \ reg_name 182 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f3), v3, \ reg_name 183 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f4), v4, \ reg_name 184 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f5), v5) reg_name 186 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ reg_name 187 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h generic_reg_get6(CTX, REG(reg_name), \ reg_name 188 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f1), v1, \ reg_name 189 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f2), v2, \ reg_name 190 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f3), v3, \ reg_name 191 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f4), v4, \ reg_name 192 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f5), v5, \ reg_name 193 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f6), v6) reg_name 195 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ reg_name 196 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h generic_reg_get7(CTX, REG(reg_name), \ reg_name 197 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f1), v1, \ reg_name 198 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f2), v2, \ reg_name 199 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f3), v3, \ reg_name 200 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f4), v4, \ reg_name 201 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f5), v5, \ reg_name 202 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f6), v6, \ reg_name 203 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f7), v7) reg_name 205 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ reg_name 206 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h generic_reg_get8(CTX, REG(reg_name), \ reg_name 207 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f1), v1, \ reg_name 208 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f2), v2, \ reg_name 209 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f3), v3, \ reg_name 210 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f4), v4, \ reg_name 211 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f5), v5, \ reg_name 212 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f6), v6, \ reg_name 213 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f7), v7, \ reg_name 214 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f8), v8) reg_name 218 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \ reg_name 220 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG(reg_name), FN(reg_name, field), val,\ reg_name 225 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_N(reg_name, n, ...) \ reg_name 227 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG(reg_name), \ reg_name 230 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE(reg_name, field, val) \ reg_name 231 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_UPDATE_N(reg_name, 1, \ reg_name 232 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, field), val) reg_name 100 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c #define SRI(reg_name, block, id)\ reg_name 101 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 102 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c mm ## block ## id ## _ ## reg_name reg_name 181 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c #define SRI(reg_name, block, id)\ reg_name 182 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 183 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c mm ## block ## id ## _ ## reg_name reg_name 183 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c #define SRI(reg_name, block, id)\ reg_name 184 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 185 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c mm ## block ## id ## _ ## reg_name reg_name 179 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c #define SRI(reg_name, block, id)\ reg_name 180 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ reg_name 181 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c mm ## block ## id ## _ ## reg_name reg_name 276 drivers/gpu/drm/i915/gvt/trace.h TP_PROTO(int id, char *reg_name, unsigned int reg, unsigned int new_val, reg_name 279 drivers/gpu/drm/i915/gvt/trace.h TP_ARGS(id, reg_name, reg, new_val, old_val, changed), reg_name 292 drivers/gpu/drm/i915/gvt/trace.h snprintf(__entry->buf, GVT_TEMP_STR_LEN, "%s", reg_name); reg_name 136 drivers/gpu/drm/omapdrm/dss/video-pll.c const char * const reg_name[] = { "pll1", "pll2" }; reg_name 149 drivers/gpu/drm/omapdrm/dss/video-pll.c res = platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[id]); reg_name 190 drivers/gpu/drm/rockchip/rockchip_drm_vop.c const char *reg_name) reg_name 195 drivers/gpu/drm/rockchip/rockchip_drm_vop.c DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name); reg_name 317 drivers/leds/leds-bd2802.c #define BD2802_SET_REGISTER(reg_addr, reg_name) \ reg_name 335 drivers/leds/leds-bd2802.c .attr = {.name = reg_name, .mode = 0644}, \ reg_name 39 drivers/media/dvb-frontends/au8522_decoder.c u16 reg_name; reg_name 283 drivers/media/dvb-frontends/au8522_decoder.c au8522_writereg(state, filter_coef[i].reg_name, reg_name 405 drivers/media/dvb-frontends/au8522_decoder.c au8522_writereg(state, lpfilter_coef[i].reg_name, reg_name 315 drivers/mtd/nand/raw/tegra_nand.c const char *reg_name = tegra_nand_reg_names[i]; reg_name 317 drivers/mtd/nand/raw/tegra_nand.c if (!reg_name) reg_name 321 drivers/mtd/nand/raw/tegra_nand.c dev_err(ctrl->dev, "%s: 0x%08x\n", reg_name, reg); reg_name 3290 drivers/net/ethernet/intel/e1000/e1000_main.c static const char * const reg_name[] = { reg_name 3346 drivers/net/ethernet/intel/e1000/e1000_main.c pr_info("%-15s %08x\n", reg_name[i], regs_buff[i]); reg_name 118 drivers/net/ethernet/sun/niu.c const char *reg_name) reg_name 126 drivers/net/ethernet/sun/niu.c (unsigned long long)bits, reg_name, reg_name 153 drivers/net/ethernet/sun/niu.c const char *reg_name) reg_name 165 drivers/net/ethernet/sun/niu.c (unsigned long long)bits, reg_name, reg_name 197 drivers/net/ethernet/sun/niu.c const char *reg_name) reg_name 205 drivers/net/ethernet/sun/niu.c (unsigned long long)bits, reg_name, reg_name 25 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c #define READ_RADIO_REG2(pi, radio_type, jspace, core, reg_name) \ reg_name 26 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c read_radio_reg(pi, radio_type##_##jspace##_##reg_name | \ reg_name 31 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c #define WRITE_RADIO_REG2(pi, radio_type, jspace, core, reg_name, value) \ reg_name 32 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_radio_reg(pi, radio_type##_##jspace##_##reg_name | \ reg_name 37 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c #define WRITE_RADIO_SYN(pi, radio_type, reg_name, value) \ reg_name 38 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c write_radio_reg(pi, radio_type##_##SYN##_##reg_name, value) reg_name 40 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c #define READ_RADIO_REG3(pi, radio_type, jspace, core, reg_name) \ reg_name 42 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c radio_type##_##jspace##0##_##reg_name : \ reg_name 43 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c radio_type##_##jspace##1##_##reg_name)) reg_name 45 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c #define WRITE_RADIO_REG3(pi, radio_type, jspace, core, reg_name, value) \ reg_name 47 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c radio_type##_##jspace##0##_##reg_name : \ reg_name 48 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c radio_type##_##jspace##1##_##reg_name), \ reg_name 51 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c #define READ_RADIO_REG4(pi, radio_type, jspace, core, reg_name) \ reg_name 53 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c radio_type##_##reg_name##_##jspace##0 : \ reg_name 54 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c radio_type##_##reg_name##_##jspace##1)) reg_name 56 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c #define WRITE_RADIO_REG4(pi, radio_type, jspace, core, reg_name, value) \ reg_name 58 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c radio_type##_##reg_name##_##jspace##0 : \ reg_name 59 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c radio_type##_##reg_name##_##jspace##1), \ reg_name 219 drivers/opp/ti-opp-supply.c char *reg_name) reg_name 251 drivers/opp/ti-opp-supply.c dev_dbg(dev, "%s scaling to %luuV[min %luuV max %luuV]\n", reg_name, reg_name 261 drivers/opp/ti-opp-supply.c reg_name, vdd_uv, supply->u_volt_min, reg_name 128 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c const char * const reg_name[] = { "pll1", "pll2" }; reg_name 141 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c res = platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[id]); reg_name 187 drivers/watchdog/octeon-wdt-main.c static const char reg_name[][3] = { reg_name 229 drivers/watchdog/octeon-wdt-main.c octeon_wdt_write_string(reg_name[i]); reg_name 30 sound/soc/sh/rcar/gen.c const char *reg_name[REG_MAX]; reg_name 34 sound/soc/sh/rcar/gen.c #define rsnd_reg_name(gen, id) ((gen)->reg_name[id]) reg_name 40 sound/soc/sh/rcar/gen.c const char *reg_name; reg_name 48 sound/soc/sh/rcar/gen.c .reg_name = n, \ reg_name 203 sound/soc/sh/rcar/gen.c gen->reg_name[conf[i].idx] = conf[i].reg_name; reg_name 59 tools/objtool/orc_dump.c printf("%s%+d", reg_name(reg), offset);