reg_enable        228 arch/arm64/kernel/hw_breakpoint.c 	int i, max_slots, ctrl_reg, val_reg, reg_enable;
reg_enable        238 arch/arm64/kernel/hw_breakpoint.c 		reg_enable = !debug_info->bps_disabled;
reg_enable        245 arch/arm64/kernel/hw_breakpoint.c 		reg_enable = !debug_info->wps_disabled;
reg_enable        268 arch/arm64/kernel/hw_breakpoint.c 			     reg_enable ? ctrl | 0x1 : ctrl & ~0x1);
reg_enable         69 drivers/irqchip/irq-bcm2835.c static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
reg_enable        150 drivers/irqchip/irq-bcm2835.c 		intc.enable[b] = base + reg_enable[b];
reg_enable        138 drivers/irqchip/irq-bcm6345-l1.c 		pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx));
reg_enable        161 drivers/irqchip/irq-bcm6345-l1.c 		intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
reg_enable        173 drivers/irqchip/irq-bcm6345-l1.c 		intc->cpus[cpu_idx]->map_base + reg_enable(intc, word));
reg_enable        266 drivers/irqchip/irq-bcm6345-l1.c 		__raw_writel(0, cpu->map_base + reg_enable(intc, i));