reg_clear         716 drivers/gpu/drm/i2c/tda998x_drv.c 	reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
reg_clear         840 drivers/gpu/drm/i2c/tda998x_drv.c 	reg_clear(priv, REG_DIP_IF_FLAGS, bit);
reg_clear         877 drivers/gpu/drm/i2c/tda998x_drv.c 		reg_clear(priv, REG_DIP_IF_FLAGS, DIP_IF_FLAGS_IF1);
reg_clear         994 drivers/gpu/drm/i2c/tda998x_drv.c 		reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
reg_clear         997 drivers/gpu/drm/i2c/tda998x_drv.c 		reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
reg_clear        1019 drivers/gpu/drm/i2c/tda998x_drv.c 	reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
reg_clear        1041 drivers/gpu/drm/i2c/tda998x_drv.c 	reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
reg_clear        1291 drivers/gpu/drm/i2c/tda998x_drv.c 		reg_clear(priv, REG_TX4, TX4_PD_RAM);
reg_clear        1537 drivers/gpu/drm/i2c/tda998x_drv.c 	reg_clear(priv, REG_TX33, TX33_HDMI);
reg_clear        1548 drivers/gpu/drm/i2c/tda998x_drv.c 	reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
reg_clear        1549 drivers/gpu/drm/i2c/tda998x_drv.c 	reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
reg_clear        1569 drivers/gpu/drm/i2c/tda998x_drv.c 		reg_clear(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
reg_clear        1780 drivers/gpu/drm/i2c/tda998x_drv.c 	reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
reg_clear         456 drivers/gpu/drm/stm/ltdc.c 	reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN);
reg_clear         459 drivers/gpu/drm/stm/ltdc.c 	reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
reg_clear         668 drivers/gpu/drm/stm/ltdc.c 	reg_clear(ldev->regs, LTDC_IER, IER_LIE);
reg_clear         879 drivers/gpu/drm/stm/ltdc.c 	reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN);
reg_clear        1206 drivers/gpu/drm/stm/ltdc.c 	reg_clear(ldev->regs, LTDC_IER,
reg_clear         411 drivers/iommu/exynos-iommu.c 	unsigned short reg_status, reg_clear;
reg_clear         418 drivers/iommu/exynos-iommu.c 		reg_clear = REG_INT_CLEAR;
reg_clear         423 drivers/iommu/exynos-iommu.c 		reg_clear = REG_V5_INT_CLEAR;
reg_clear         449 drivers/iommu/exynos-iommu.c 	writel(1 << itype, data->sfrbase + reg_clear);
reg_clear         521 drivers/media/i2c/mt9m001.c 			ret = reg_clear(client, MT9M001_READ_OPTIONS2, 0x8000);
reg_clear         445 drivers/media/i2c/mt9m111.c 		ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE
reg_clear         836 drivers/media/i2c/mt9m111.c 	return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
reg_clear         845 drivers/media/i2c/mt9m111.c 	return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
reg_clear         930 drivers/media/i2c/mt9m111.c 		ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE);
reg_clear         869 drivers/media/platform/stm32/stm32-dcmi.c 	reg_clear(dcmi->regs, DCMI_IER, IT_FRAME | IT_OVR | IT_ERR);
reg_clear         872 drivers/media/platform/stm32/stm32-dcmi.c 	reg_clear(dcmi->regs, DCMI_CR, CR_ENABLE);
reg_clear         155 drivers/staging/media/soc_camera/mt9t031.c 		ret = reg_clear(client, MT9T031_OUTPUT_CONTROL, 2);
reg_clear         170 drivers/staging/media/soc_camera/mt9t031.c 		ret = reg_clear(client, MT9T031_OUTPUT_CONTROL, 2);
reg_clear         282 drivers/staging/media/soc_camera/mt9t031.c 		ret = reg_clear(client, MT9T031_OUTPUT_CONTROL, 1);
reg_clear         470 drivers/staging/media/soc_camera/mt9t031.c 			data = reg_clear(client, MT9T031_READ_MODE_2, 0x8000);
reg_clear         478 drivers/staging/media/soc_camera/mt9t031.c 			data = reg_clear(client, MT9T031_READ_MODE_2, 0x4000);
reg_clear         719 drivers/staging/media/soc_camera/mt9t031.c 		return reg_clear(client, MT9T031_PIXEL_CLOCK_CONTROL, 0x8000);
reg_clear         229 drivers/staging/media/soc_camera/soc_mt9v022.c 		ret = reg_clear(client, MT9V022_BLACK_LEVEL_CALIB_CTRL, 1);
reg_clear         252 drivers/staging/media/soc_camera/soc_mt9v022.c 			if (reg_clear(client, MT9V022_REG32, 0x204))
reg_clear         580 drivers/staging/media/soc_camera/soc_mt9v022.c 			data = reg_clear(client, MT9V022_READ_MODE, 0x10);
reg_clear         588 drivers/staging/media/soc_camera/soc_mt9v022.c 			data = reg_clear(client, MT9V022_READ_MODE, 0x20);
reg_clear         611 drivers/staging/media/soc_camera/soc_mt9v022.c 			if (reg_clear(client, MT9V022_AEC_AGC_ENABLE, 0x2) < 0)
reg_clear         633 drivers/staging/media/soc_camera/soc_mt9v022.c 			data = reg_clear(client, MT9V022_AEC_AGC_ENABLE, 0x1);