reg_cfg           979 arch/arm/mach-davinci/include/mach/mux.h extern int davinci_cfg_reg(unsigned long reg_cfg);
reg_cfg           983 arch/arm/mach-davinci/include/mach/mux.h static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
reg_cfg           432 arch/arm/mach-omap1/include/mach/mux.h extern int omap_cfg_reg(unsigned long reg_cfg);
reg_cfg           436 arch/arm/mach-omap1/include/mach/mux.h static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
reg_cfg            90 drivers/ata/pata_octeon_cf.c 	union cvmx_mio_boot_reg_cfgx reg_cfg;
reg_cfg           108 drivers/ata/pata_octeon_cf.c 	reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
reg_cfg           109 drivers/ata/pata_octeon_cf.c 	reg_cfg.s.dmack = 0;	/* Don't assert DMACK on access */
reg_cfg           110 drivers/ata/pata_octeon_cf.c 	reg_cfg.s.tim_mult = tim_mult;	/* Timing mutiplier */
reg_cfg           111 drivers/ata/pata_octeon_cf.c 	reg_cfg.s.rd_dly = 0;	/* Sample on falling edge of BOOT_OE */
reg_cfg           112 drivers/ata/pata_octeon_cf.c 	reg_cfg.s.sam = 0;	/* Don't combine write and output enable */
reg_cfg           113 drivers/ata/pata_octeon_cf.c 	reg_cfg.s.we_ext = 0;	/* No write enable extension */
reg_cfg           114 drivers/ata/pata_octeon_cf.c 	reg_cfg.s.oe_ext = 0;	/* No read enable extension */
reg_cfg           115 drivers/ata/pata_octeon_cf.c 	reg_cfg.s.en = 1;	/* Enable this region */
reg_cfg           116 drivers/ata/pata_octeon_cf.c 	reg_cfg.s.orbit = 0;	/* Don't combine with previous region */
reg_cfg           117 drivers/ata/pata_octeon_cf.c 	reg_cfg.s.ale = 0;	/* Don't do address multiplexing */
reg_cfg           118 drivers/ata/pata_octeon_cf.c 	cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), reg_cfg.u64);
reg_cfg           150 drivers/clk/sprd/pll.c 	struct reg_cfg *cfg;
reg_cfg           812 drivers/dma/ste_dma40.c 	writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
reg_cfg           817 drivers/dma/ste_dma40.c 	writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
reg_cfg           136 drivers/dma/ste_dma40_ll.c 			    u32 reg_cfg,
reg_cfg           171 drivers/dma/ste_dma40_ll.c 	lli->reg_cfg = reg_cfg;
reg_cfg           181 drivers/dma/ste_dma40_ll.c 		lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS);
reg_cfg           183 drivers/dma/ste_dma40_ll.c 		lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);
reg_cfg           213 drivers/dma/ste_dma40_ll.c 		   dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg,
reg_cfg           249 drivers/dma/ste_dma40_ll.c 				       reg_cfg, info, flags);
reg_cfg           270 drivers/dma/ste_dma40_ll.c 		      u32 reg_cfg,
reg_cfg           298 drivers/dma/ste_dma40_ll.c 					 reg_cfg, info, otherinfo, flags);
reg_cfg           363 drivers/dma/ste_dma40_ll.c 			     u32 reg_cfg,
reg_cfg           369 drivers/dma/ste_dma40_ll.c 	lli->lcsp13 = reg_cfg;
reg_cfg           345 drivers/dma/ste_dma40_ll.h 	u32 reg_cfg;
reg_cfg           446 drivers/dma/ste_dma40_ll.h 		      u32 reg_cfg,
reg_cfg            14 drivers/gpu/drm/msm/dsi/dsi_cfg.c 	.reg_cfg = {
reg_cfg            34 drivers/gpu/drm/msm/dsi/dsi_cfg.c 	.reg_cfg = {
reg_cfg            55 drivers/gpu/drm/msm/dsi/dsi_cfg.c 	.reg_cfg = {
reg_cfg            71 drivers/gpu/drm/msm/dsi/dsi_cfg.c 	.reg_cfg = {
reg_cfg            99 drivers/gpu/drm/msm/dsi/dsi_cfg.c 	.reg_cfg = {
reg_cfg           119 drivers/gpu/drm/msm/dsi/dsi_cfg.c 	.reg_cfg = {
reg_cfg           138 drivers/gpu/drm/msm/dsi/dsi_cfg.c 	.reg_cfg = {
reg_cfg            29 drivers/gpu/drm/msm/dsi/dsi_cfg.h 	struct dsi_reg_config reg_cfg;
reg_cfg           263 drivers/gpu/drm/msm/dsi/dsi_host.c 	const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
reg_cfg           264 drivers/gpu/drm/msm/dsi/dsi_host.c 	int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
reg_cfg           279 drivers/gpu/drm/msm/dsi/dsi_host.c 	const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
reg_cfg           280 drivers/gpu/drm/msm/dsi/dsi_host.c 	int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
reg_cfg           313 drivers/gpu/drm/msm/dsi/dsi_host.c 	const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
reg_cfg           314 drivers/gpu/drm/msm/dsi/dsi_host.c 	int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
reg_cfg           389 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 	const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
reg_cfg           391 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 	int num = phy->cfg->reg_cfg.num;
reg_cfg           414 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 	const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
reg_cfg           415 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 	int num = phy->cfg->reg_cfg.num;
reg_cfg           429 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 	const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
reg_cfg           431 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 	int num = phy->cfg->reg_cfg.num;
reg_cfg            28 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h 	struct dsi_reg_config reg_cfg;
reg_cfg           215 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c 	.reg_cfg = {
reg_cfg           233 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c 	.reg_cfg = {
reg_cfg           150 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c 	.reg_cfg = {
reg_cfg           130 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c 	.reg_cfg = {
reg_cfg           130 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c 	.reg_cfg = {
reg_cfg           148 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c 	.reg_cfg = {
reg_cfg           179 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c 	.reg_cfg = {
reg_cfg          2375 drivers/net/wireless/marvell/mwifiex/fw.h 		struct host_cmd_ds_chan_region_cfg reg_cfg;
reg_cfg          1620 drivers/net/wireless/marvell/mwifiex/sta_cmd.c 	struct host_cmd_ds_chan_region_cfg *reg = &cmd->params.reg_cfg;
reg_cfg          1108 drivers/net/wireless/marvell/mwifiex/sta_cmdresp.c 	struct host_cmd_ds_chan_region_cfg *reg = &resp->params.reg_cfg;