reg 137 arch/alpha/include/asm/core_irongate.h #define IGCSR(dev,fun,reg) ( IRONGATE_CONF | \ reg 140 arch/alpha/include/asm/core_irongate.h (reg) ) reg 71 arch/alpha/include/asm/fpu.h extern unsigned long alpha_read_fp_reg (unsigned long reg); reg 72 arch/alpha/include/asm/fpu.h extern void alpha_write_fp_reg (unsigned long reg, unsigned long val); reg 73 arch/alpha/include/asm/fpu.h extern unsigned long alpha_read_fp_reg_s (unsigned long reg); reg 74 arch/alpha/include/asm/fpu.h extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val); reg 50 arch/alpha/include/uapi/asm/reg.h #define CORE_REG(reg, ubase) \ reg 51 arch/alpha/include/uapi/asm/reg.h (((unsigned long *)((unsigned long)(ubase)))[reg]) reg 26 arch/alpha/kernel/pc873xx.c static unsigned char __init pc873xx_read(unsigned int base, int reg) reg 28 arch/alpha/kernel/pc873xx.c outb(reg, base); reg 32 arch/alpha/kernel/pc873xx.c static void __init pc873xx_write(unsigned int base, int reg, unsigned char data) reg 37 arch/alpha/kernel/pc873xx.c outb(reg, base); reg 159 arch/alpha/kernel/proto.h extern void alpha_write_fp_reg (unsigned long reg, unsigned long val); reg 160 arch/alpha/kernel/proto.h extern unsigned long alpha_read_fp_reg (unsigned long reg); reg 76 arch/alpha/kernel/ptrace.c #define PT_REG(reg) \ reg 77 arch/alpha/kernel/ptrace.c (PAGE_SIZE*2 - sizeof(struct pt_regs) + offsetof(struct pt_regs, reg)) reg 79 arch/alpha/kernel/ptrace.c #define SW_REG(reg) \ reg 81 arch/alpha/kernel/ptrace.c + offsetof(struct switch_stack, reg)) reg 437 arch/alpha/kernel/traps.c do_entUna(void * va, unsigned long opcode, unsigned long reg, reg 467 arch/alpha/kernel/traps.c una_reg(reg) = tmp1|tmp2; reg 483 arch/alpha/kernel/traps.c una_reg(reg) = (int)(tmp1|tmp2); reg 499 arch/alpha/kernel/traps.c una_reg(reg) = tmp1|tmp2; reg 524 arch/alpha/kernel/traps.c : "r"(va), "r"(una_reg(reg)), "0"(0)); reg 548 arch/alpha/kernel/traps.c : "r"(va), "r"(una_reg(reg)), "0"(0)); reg 572 arch/alpha/kernel/traps.c : "r"(va), "r"(una_reg(reg)), "0"(0)); reg 579 arch/alpha/kernel/traps.c pc, va, opcode, reg); reg 723 arch/alpha/kernel/traps.c unsigned long reg, struct pt_regs *regs) reg 739 arch/alpha/kernel/traps.c regs->pc - 4, va, opcode, reg); reg 760 arch/alpha/kernel/traps.c if (reg < 30) { reg 762 arch/alpha/kernel/traps.c ((char *)regs + unauser_reg_offsets[reg]); reg 763 arch/alpha/kernel/traps.c } else if (reg == 30) { reg 806 arch/alpha/kernel/traps.c alpha_write_fp_reg(reg, s_mem_to_reg((int)(tmp1|tmp2))); reg 822 arch/alpha/kernel/traps.c alpha_write_fp_reg(reg, tmp1|tmp2); reg 885 arch/alpha/kernel/traps.c fake_reg = s_reg_to_mem(alpha_read_fp_reg(reg)); reg 913 arch/alpha/kernel/traps.c fake_reg = alpha_read_fp_reg(reg); reg 946 arch/alpha/kernel/traps.c if (reg == 30) reg 12 arch/alpha/lib/fpreg.c #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val)); reg 14 arch/alpha/lib/fpreg.c #define STT(reg,val) asm volatile ("stt $f"#reg",%0" : "=m"(val)); reg 18 arch/alpha/lib/fpreg.c alpha_read_fp_reg (unsigned long reg) reg 22 arch/alpha/lib/fpreg.c switch (reg) { reg 62 arch/alpha/lib/fpreg.c #define LDT(reg,val) asm volatile ("itoft %0,$f"#reg : : "r"(val)); reg 64 arch/alpha/lib/fpreg.c #define LDT(reg,val) asm volatile ("ldt $f"#reg",%0" : : "m"(val)); reg 68 arch/alpha/lib/fpreg.c alpha_write_fp_reg (unsigned long reg, unsigned long val) reg 70 arch/alpha/lib/fpreg.c switch (reg) { reg 108 arch/alpha/lib/fpreg.c #define STS(reg,val) asm volatile ("ftois $f"#reg",%0" : "=r"(val)); reg 110 arch/alpha/lib/fpreg.c #define STS(reg,val) asm volatile ("sts $f"#reg",%0" : "=m"(val)); reg 114 arch/alpha/lib/fpreg.c alpha_read_fp_reg_s (unsigned long reg) reg 118 arch/alpha/lib/fpreg.c switch (reg) { reg 158 arch/alpha/lib/fpreg.c #define LDS(reg,val) asm volatile ("itofs %0,$f"#reg : : "r"(val)); reg 160 arch/alpha/lib/fpreg.c #define LDS(reg,val) asm volatile ("lds $f"#reg",%0" : : "m"(val)); reg 164 arch/alpha/lib/fpreg.c alpha_write_fp_reg_s (unsigned long reg, unsigned long val) reg 166 arch/alpha/lib/fpreg.c switch (reg) { reg 52 arch/alpha/lib/stacktrace.c int reg; reg 58 arch/alpha/lib/stacktrace.c reg = (*pro_pc & MEM_REG) >> 21; reg 60 arch/alpha/lib/stacktrace.c if (reg == 26) reg 62 arch/alpha/lib/stacktrace.c printk("\t\t%s / 0x%016lx\n", reg_name[reg], value); reg 48 arch/alpha/math-emu/math.c extern unsigned long alpha_read_fp_reg (unsigned long reg); reg 49 arch/alpha/math-emu/math.c extern void alpha_write_fp_reg (unsigned long reg, unsigned long val); reg 50 arch/alpha/math-emu/math.c extern unsigned long alpha_read_fp_reg_s (unsigned long reg); reg 51 arch/alpha/math-emu/math.c extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val); reg 32 arch/alpha/oprofile/common.c static struct op_register_config reg; reg 45 arch/alpha/oprofile/common.c if ((reg.need_reset >> which) & 1) reg 46 arch/alpha/oprofile/common.c model->reset_ctr(®, which); reg 62 arch/alpha/oprofile/common.c reg.enable = e; reg 65 arch/alpha/oprofile/common.c model->reg_setup(®, ctr, &sys); reg 68 arch/alpha/oprofile/common.c smp_call_function(model->cpu_setup, ®, 1); reg 69 arch/alpha/oprofile/common.c model->cpu_setup(®); reg 83 arch/alpha/oprofile/common.c wrperfmon(1, reg.enable); reg 20 arch/alpha/oprofile/op_model_ev4.c ev4_reg_setup(struct op_register_config *reg, reg 64 arch/alpha/oprofile/op_model_ev4.c reg->mux_select = ctl; reg 70 arch/alpha/oprofile/op_model_ev4.c reg->proc_mode = 0; reg 73 arch/alpha/oprofile/op_model_ev4.c reg->freq = 0; reg 76 arch/alpha/oprofile/op_model_ev4.c reg->reset_values = 0; reg 77 arch/alpha/oprofile/op_model_ev4.c reg->need_reset = 0; reg 86 arch/alpha/oprofile/op_model_ev4.c struct op_register_config *reg = x; reg 88 arch/alpha/oprofile/op_model_ev4.c wrperfmon(2, reg->mux_select); reg 89 arch/alpha/oprofile/op_model_ev4.c wrperfmon(3, reg->proc_mode); reg 25 arch/alpha/oprofile/op_model_ev5.c common_reg_setup(struct op_register_config *reg, reg 73 arch/alpha/oprofile/op_model_ev5.c reg->mux_select = ctl; reg 82 arch/alpha/oprofile/op_model_ev5.c reg->proc_mode = ctl; reg 110 arch/alpha/oprofile/op_model_ev5.c reg->freq = ctl; reg 111 arch/alpha/oprofile/op_model_ev5.c reg->reset_values = reset; reg 112 arch/alpha/oprofile/op_model_ev5.c reg->need_reset = need_reset; reg 116 arch/alpha/oprofile/op_model_ev5.c ev5_reg_setup(struct op_register_config *reg, reg 120 arch/alpha/oprofile/op_model_ev5.c common_reg_setup(reg, ctr, sys, 19, 22); reg 124 arch/alpha/oprofile/op_model_ev5.c pca56_reg_setup(struct op_register_config *reg, reg 128 arch/alpha/oprofile/op_model_ev5.c common_reg_setup(reg, ctr, sys, 8, 11); reg 136 arch/alpha/oprofile/op_model_ev5.c struct op_register_config *reg = x; reg 138 arch/alpha/oprofile/op_model_ev5.c wrperfmon(2, reg->mux_select); reg 139 arch/alpha/oprofile/op_model_ev5.c wrperfmon(3, reg->proc_mode); reg 140 arch/alpha/oprofile/op_model_ev5.c wrperfmon(4, reg->freq); reg 141 arch/alpha/oprofile/op_model_ev5.c wrperfmon(6, reg->reset_values); reg 157 arch/alpha/oprofile/op_model_ev5.c ev5_reset_ctr(struct op_register_config *reg, unsigned long ctr) reg 167 arch/alpha/oprofile/op_model_ev5.c reset_values = reg->reset_values; reg 169 arch/alpha/oprofile/op_model_ev5.c if ((reg->proc_mode & not_pk) == not_pk) { reg 178 arch/alpha/oprofile/op_model_ev5.c wrperfmon(1, reg->enable); reg 20 arch/alpha/oprofile/op_model_ev6.c ev6_reg_setup(struct op_register_config *reg, reg 33 arch/alpha/oprofile/op_model_ev6.c reg->mux_select = ctl; reg 39 arch/alpha/oprofile/op_model_ev6.c reg->proc_mode = 0; reg 58 arch/alpha/oprofile/op_model_ev6.c reg->reset_values = reset; reg 59 arch/alpha/oprofile/op_model_ev6.c reg->need_reset = need_reset; reg 67 arch/alpha/oprofile/op_model_ev6.c struct op_register_config *reg = x; reg 69 arch/alpha/oprofile/op_model_ev6.c wrperfmon(2, reg->mux_select); reg 70 arch/alpha/oprofile/op_model_ev6.c wrperfmon(3, reg->proc_mode); reg 71 arch/alpha/oprofile/op_model_ev6.c wrperfmon(6, reg->reset_values | 3); reg 79 arch/alpha/oprofile/op_model_ev6.c ev6_reset_ctr(struct op_register_config *reg, unsigned long ctr) reg 81 arch/alpha/oprofile/op_model_ev6.c wrperfmon(6, reg->reset_values | (1 << ctr)); reg 21 arch/alpha/oprofile/op_model_ev67.c ev67_reg_setup(struct op_register_config *reg, reg 38 arch/alpha/oprofile/op_model_ev67.c reg->mux_select = ctl; reg 44 arch/alpha/oprofile/op_model_ev67.c reg->proc_mode = 0; reg 63 arch/alpha/oprofile/op_model_ev67.c reg->reset_values = reset; reg 64 arch/alpha/oprofile/op_model_ev67.c reg->need_reset = need_reset; reg 72 arch/alpha/oprofile/op_model_ev67.c struct op_register_config *reg = x; reg 74 arch/alpha/oprofile/op_model_ev67.c wrperfmon(2, reg->mux_select); reg 75 arch/alpha/oprofile/op_model_ev67.c wrperfmon(3, reg->proc_mode); reg 76 arch/alpha/oprofile/op_model_ev67.c wrperfmon(6, reg->reset_values | 3); reg 84 arch/alpha/oprofile/op_model_ev67.c ev67_reset_ctr(struct op_register_config *reg, unsigned long ctr) reg 86 arch/alpha/oprofile/op_model_ev67.c wrperfmon(6, reg->reset_values | (1 << ctr)); reg 109 arch/arc/include/asm/disasm.h long get_reg(int reg, struct pt_regs *regs, struct callee_regs *cregs); reg 110 arch/arc/include/asm/disasm.h void set_reg(int reg, long val, struct pt_regs *regs, reg 80 arch/arc/include/asm/entry-arcv2.h ; (B) Manually save the complete reg file below reg 153 arch/arc/include/asm/entry-arcv2.h ; ISA requires ADD.nz to have same dest and src reg operands reg 265 arch/arc/include/asm/entry-arcv2.h .macro GET_CURR_THR_INFO_FROM_SP reg reg 270 arch/arc/include/asm/entry-arcv2.h .macro GET_CPU_ID reg reg 132 arch/arc/include/asm/entry-compact.h .macro PROLOG_FREEUP_REG reg, mem reg 140 arch/arc/include/asm/entry-compact.h .macro PROLOG_RESTORE_REG reg, mem reg 326 arch/arc/include/asm/entry-compact.h .macro GET_CURR_THR_INFO_FROM_SP reg reg 332 arch/arc/include/asm/entry-compact.h .macro GET_CPU_ID reg reg 33 arch/arc/include/asm/entry.h .macro PUSH reg reg 42 arch/arc/include/asm/entry.h .macro POP reg reg 225 arch/arc/include/asm/entry.h .macro GET_CURR_THR_INFO_FLAGS reg reg 237 arch/arc/include/asm/entry.h .macro GET_CURR_TASK_ON_CPU reg reg 265 arch/arc/include/asm/entry.h .macro GET_CURR_TASK_ON_CPU reg reg 285 arch/arc/include/asm/entry.h .macro GET_CURR_TASK_FIELD_PTR off, reg reg 291 arch/arc/include/asm/entry.h .macro GET_CURR_TASK_FIELD_PTR off, reg reg 138 arch/arc/include/asm/ptrace.h #define syscall_wont_restart(reg) (reg->state |= STATE_SCALL_RESTARTED) reg 139 arch/arc/include/asm/ptrace.h #define syscall_restartable(reg) !(reg->state & STATE_SCALL_RESTARTED) reg 432 arch/arc/kernel/disasm.c long __kprobes get_reg(int reg, struct pt_regs *regs, reg 437 arch/arc/kernel/disasm.c if (reg <= 12) { reg 439 arch/arc/kernel/disasm.c return p[-reg]; reg 442 arch/arc/kernel/disasm.c if (cregs && (reg <= 25)) { reg 444 arch/arc/kernel/disasm.c return p[13-reg]; reg 447 arch/arc/kernel/disasm.c if (reg == 26) reg 449 arch/arc/kernel/disasm.c if (reg == 27) reg 451 arch/arc/kernel/disasm.c if (reg == 28) reg 453 arch/arc/kernel/disasm.c if (reg == 31) reg 459 arch/arc/kernel/disasm.c void __kprobes set_reg(int reg, long val, struct pt_regs *regs, reg 464 arch/arc/kernel/disasm.c switch (reg) { reg 467 arch/arc/kernel/disasm.c p[-reg] = val; reg 472 arch/arc/kernel/disasm.c p[13-reg] = val; reg 145 arch/arc/kernel/unwind.c uleb128_t reg, offs; reg 675 arch/arc/kernel/unwind.c static void set_rule(uleb128_t reg, enum item_location where, uleb128_t value, reg 678 arch/arc/kernel/unwind.c if (reg < ARRAY_SIZE(state->regs)) { reg 679 arch/arc/kernel/unwind.c state->regs[reg].where = where; reg 680 arch/arc/kernel/unwind.c state->regs[reg].value = value; reg 683 arch/arc/kernel/unwind.c unw_debug("r%lu: ", reg); reg 828 arch/arc/kernel/unwind.c state->cfa.reg = get_uleb128(&ptr.p8, end); reg 829 arch/arc/kernel/unwind.c unw_debug("cfa_def_cfa: r%lu ", state->cfa.reg); reg 837 arch/arc/kernel/unwind.c state->cfa.reg = get_uleb128(&ptr.p8, end); reg 845 arch/arc/kernel/unwind.c state->cfa.reg = get_uleb128(&ptr.p8, end); reg 1148 arch/arc/kernel/unwind.c || state.cfa.reg >= ARRAY_SIZE(reg_info) reg 1149 arch/arc/kernel/unwind.c || reg_info[state.cfa.reg].width != sizeof(unsigned long) reg 1186 arch/arc/kernel/unwind.c cfa = FRAME_REG(state.cfa.reg, unsigned long) + state.cfa.offs; reg 1195 arch/arc/kernel/unwind.c state.cfa.reg, state.cfa.offs, cfa); reg 525 arch/arc/mm/cache.c unsigned int reg; reg 528 arch/arc/mm/cache.c while ((reg = read_aux_reg(ctl)) & DC_CTRL_FLUSH_STATUS) reg 533 arch/arc/mm/cache.c write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH); reg 200 arch/arc/plat-eznps/include/plat/ctop.h .macro GET_CPU_ID reg reg 11 arch/arc/plat-eznps/include/plat/mtm.h static inline void *nps_mtm_reg_addr(u32 cpu, u32 reg) reg 20 arch/arc/plat-eznps/include/plat/mtm.h return nps_host_reg(cpu, blkid, reg); reg 240 arch/arc/plat-hsdk/platform.c u32 reg; reg 247 arch/arc/plat-hsdk/platform.c reg = readl(CREG_AXI_M_HS_CORE_BOOT) & (~0x3); reg 248 arch/arc/plat-hsdk/platform.c writel(reg, CREG_AXI_M_HS_CORE_BOOT); reg 485 arch/arm/common/sa1111.c void __iomem *reg = sachip->base + SA1111_GPIO; reg 488 arch/arm/common/sa1111.c return reg + SA1111_GPIO_PADDR; reg 490 arch/arm/common/sa1111.c return reg + SA1111_GPIO_PBDDR; reg 492 arch/arm/common/sa1111.c return reg + SA1111_GPIO_PCDDR; reg 507 arch/arm/common/sa1111.c static void sa1111_gpio_modify(void __iomem *reg, u32 mask, u32 set) reg 511 arch/arm/common/sa1111.c val = readl_relaxed(reg); reg 514 arch/arm/common/sa1111.c writel_relaxed(val, reg); reg 520 arch/arm/common/sa1111.c void __iomem *reg = sa1111_gpio_map_reg(sachip, offset); reg 523 arch/arm/common/sa1111.c return !!(readl_relaxed(reg + SA1111_GPIO_PXDDR) & mask); reg 530 arch/arm/common/sa1111.c void __iomem *reg = sa1111_gpio_map_reg(sachip, offset); reg 534 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, mask); reg 535 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, mask); reg 546 arch/arm/common/sa1111.c void __iomem *reg = sa1111_gpio_map_reg(sachip, offset); reg 550 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0); reg 551 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0); reg 552 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, 0); reg 553 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, 0); reg 562 arch/arm/common/sa1111.c void __iomem *reg = sa1111_gpio_map_reg(sachip, offset); reg 565 arch/arm/common/sa1111.c return !!(readl_relaxed(reg + SA1111_GPIO_PXDRR) & mask); reg 572 arch/arm/common/sa1111.c void __iomem *reg = sa1111_gpio_map_reg(sachip, offset); reg 576 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0); reg 577 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0); reg 586 arch/arm/common/sa1111.c void __iomem *reg = sachip->base + SA1111_GPIO; reg 593 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PADWR, msk & 15, val); reg 594 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PASSR, msk & 15, val); reg 595 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PBDWR, (msk >> 4) & 255, val >> 4); reg 596 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PBSSR, (msk >> 4) & 255, val >> 4); reg 597 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PCDWR, (msk >> 12) & 255, val >> 12); reg 598 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PCSSR, (msk >> 12) & 255, val >> 12); reg 124 arch/arm/common/scoop.c unsigned short read_scoop_reg(struct device *dev, unsigned short reg) reg 127 arch/arm/common/scoop.c return ioread16(sdev->base + reg); reg 130 arch/arm/common/scoop.c void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data) reg 133 arch/arm/common/scoop.c iowrite16(data, sdev->base + reg); reg 27 arch/arm/include/asm/arch_timer.h void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) reg 30 arch/arm/include/asm/arch_timer.h switch (reg) { reg 39 arch/arm/include/asm/arch_timer.h switch (reg) { reg 53 arch/arm/include/asm/arch_timer.h u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg) reg 58 arch/arm/include/asm/arch_timer.h switch (reg) { reg 67 arch/arm/include/asm/arch_timer.h switch (reg) { reg 323 arch/arm/include/asm/assembler.h .macro setmode, mode, reg reg 326 arch/arm/include/asm/assembler.h .macro setmode, mode, reg reg 331 arch/arm/include/asm/assembler.h .macro setmode, mode, reg reg 343 arch/arm/include/asm/assembler.h .macro safe_svcmode_maskall reg:req reg 373 arch/arm/include/asm/assembler.h .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() reg 389 arch/arm/include/asm/assembler.h .macro usracc, instr, reg, ptr, inc, cond, rept, abort reg 413 arch/arm/include/asm/assembler.h .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() reg 433 arch/arm/include/asm/assembler.h .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f reg 437 arch/arm/include/asm/assembler.h .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f reg 450 arch/arm/include/asm/assembler.h .macro ret\c, reg reg 463 arch/arm/include/asm/assembler.h .macro ret.w, reg reg 117 arch/arm/include/asm/cputype.h #define read_cpuid(reg) \ reg 120 arch/arm/include/asm/cputype.h asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \ reg 147 arch/arm/include/asm/cputype.h #define read_cpuid(reg) \ reg 164 arch/arm/include/asm/cputype.h #define read_cpuid(reg) \ reg 170 arch/arm/include/asm/cputype.h #define read_cpuid_ext(reg) read_cpuid(reg) reg 339 arch/arm/include/asm/cputype.h #define cpuid_feature_extract(reg, field) \ reg 340 arch/arm/include/asm/cputype.h cpuid_feature_extract_field(read_cpuid_ext(reg), field) reg 11 arch/arm/include/asm/hardware/cp14.h #define dbg_read(reg) RCP14_##reg() reg 12 arch/arm/include/asm/hardware/cp14.h #define dbg_write(val, reg) WCP14_##reg(val) reg 13 arch/arm/include/asm/hardware/cp14.h #define etm_read(reg) RCP14_##reg() reg 14 arch/arm/include/asm/hardware/cp14.h #define etm_write(val, reg) WCP14_##reg(val) reg 14 arch/arm/include/asm/hardware/memc.h extern void memc_write(unsigned int reg, unsigned long val); reg 66 arch/arm/include/asm/hardware/scoop.h unsigned short read_scoop_reg(struct device *dev, unsigned short reg); reg 67 arch/arm/include/asm/hardware/scoop.h void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data); reg 34 arch/arm/include/asm/hw_breakpoint.h static inline void decode_ctrl_reg(u32 reg, reg 37 arch/arm/include/asm/hw_breakpoint.h ctrl->enabled = reg & 0x1; reg 38 arch/arm/include/asm/hw_breakpoint.h reg >>= 1; reg 39 arch/arm/include/asm/hw_breakpoint.h ctrl->privilege = reg & 0x3; reg 40 arch/arm/include/asm/hw_breakpoint.h reg >>= 2; reg 41 arch/arm/include/asm/hw_breakpoint.h ctrl->type = reg & 0x3; reg 42 arch/arm/include/asm/hw_breakpoint.h reg >>= 2; reg 43 arch/arm/include/asm/hw_breakpoint.h ctrl->len = reg & 0xff; reg 44 arch/arm/include/asm/hw_breakpoint.h reg >>= 17; reg 45 arch/arm/include/asm/hw_breakpoint.h ctrl->mismatch = reg & 0x1; reg 38 arch/arm/include/asm/io.h extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set); reg 39 arch/arm/include/asm/io.h extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set); reg 229 arch/arm/include/asm/kvm_host.h int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); reg 230 arch/arm/include/asm/kvm_host.h int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); reg 102 arch/arm/include/asm/tls.h unsigned long reg = 0; reg 105 arch/arm/include/asm/tls.h __asm__("mrc p15, 0, %0, c13, c0, 2" : "=r" (reg)); reg 107 arch/arm/include/asm/tls.h return reg; reg 15 arch/arm/kernel/io.c void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set) reg 21 arch/arm/kernel/io.c value = readl_relaxed(reg) & ~mask; reg 23 arch/arm/kernel/io.c writel_relaxed(value, reg); reg 28 arch/arm/kernel/io.c void atomic_io_modify(void __iomem *reg, u32 mask, u32 set) reg 34 arch/arm/kernel/io.c value = readl_relaxed(reg) & ~mask; reg 36 arch/arm/kernel/io.c writel(value, reg); reg 424 arch/arm/kernel/ptrace.c u32 reg = 0; reg 431 arch/arm/kernel/ptrace.c reg |= debug_arch; reg 432 arch/arm/kernel/ptrace.c reg <<= 8; reg 433 arch/arm/kernel/ptrace.c reg |= wp_len; reg 434 arch/arm/kernel/ptrace.c reg <<= 8; reg 435 arch/arm/kernel/ptrace.c reg |= num_wrps; reg 436 arch/arm/kernel/ptrace.c reg <<= 8; reg 437 arch/arm/kernel/ptrace.c reg |= num_brps; reg 439 arch/arm/kernel/ptrace.c return reg; reg 461 arch/arm/kernel/ptrace.c u32 reg; reg 467 arch/arm/kernel/ptrace.c reg = ptrace_get_hbp_resource_info(); reg 477 arch/arm/kernel/ptrace.c reg = 0; reg 491 arch/arm/kernel/ptrace.c reg = bp->attr.bp_addr; reg 493 arch/arm/kernel/ptrace.c reg = encode_ctrl_reg(arch_ctrl); reg 497 arch/arm/kernel/ptrace.c if (put_user(reg, data)) reg 81 arch/arm/kernel/traps.c int reg; reg 83 arch/arm/kernel/traps.c for (reg = 10, x = 0, p = str; reg >= 0; reg--) { reg 84 arch/arm/kernel/traps.c if (instruction & BIT(reg)) { reg 85 arch/arm/kernel/traps.c p += sprintf(p, " r%d:%08x", reg, *stack--); reg 688 arch/arm/kernel/traps.c int reg = (instr >> 12) & 15; reg 689 arch/arm/kernel/traps.c if (reg == 15) reg 691 arch/arm/kernel/traps.c regs->uregs[reg] = current_thread_info()->tp_value[0]; reg 233 arch/arm/kernel/unwind.c unsigned long **vsp, unsigned int reg) reg 239 arch/arm/kernel/unwind.c ctrl->vrs[reg] = *(*vsp)++; reg 248 arch/arm/kernel/unwind.c int load_sp, reg = 4; reg 253 arch/arm/kernel/unwind.c if (unwind_pop_register(ctrl, &vsp, reg)) reg 256 arch/arm/kernel/unwind.c reg++; reg 268 arch/arm/kernel/unwind.c int reg; reg 271 arch/arm/kernel/unwind.c for (reg = 4; reg <= 4 + (insn & 7); reg++) reg 272 arch/arm/kernel/unwind.c if (unwind_pop_register(ctrl, &vsp, reg)) reg 288 arch/arm/kernel/unwind.c int reg = 0; reg 293 arch/arm/kernel/unwind.c if (unwind_pop_register(ctrl, &vsp, reg)) reg 296 arch/arm/kernel/unwind.c reg++; reg 66 arch/arm/kvm/coproc.c vcpu_cp15(vcpu, r->reg) = val & 0xffffffff; reg 67 arch/arm/kvm/coproc.c vcpu_cp15(vcpu, r->reg + 1) = val >> 32; reg 75 arch/arm/kvm/coproc.c val = vcpu_cp15(vcpu, r->reg + 1); reg 77 arch/arm/kvm/coproc.c val = val | vcpu_cp15(vcpu, r->reg); reg 224 arch/arm/kvm/coproc.c vcpu_cp15(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt1); reg 226 arch/arm/kvm/coproc.c vcpu_cp15(vcpu, r->reg + 1) = *vcpu_reg(vcpu, p->Rt2); reg 236 arch/arm/kvm/coproc.c u64 reg; reg 242 arch/arm/kvm/coproc.c reg = (u64)*vcpu_reg(vcpu, p->Rt2) << 32; reg 243 arch/arm/kvm/coproc.c reg |= *vcpu_reg(vcpu, p->Rt1) ; reg 263 arch/arm/kvm/coproc.c vgic_v3_dispatch_sgi(vcpu, reg, g1); reg 661 arch/arm/kvm/coproc.c int reg = table[i].reg; reg 664 arch/arm/kvm/coproc.c if (reg > 0 && reg < NR_CP15_REGS) { reg 665 arch/arm/kvm/coproc.c set_bit(reg, bmap); reg 667 arch/arm/kvm/coproc.c set_bit(reg + 1, bmap); reg 786 arch/arm/kvm/coproc.c if (r && !r->reg) reg 1205 arch/arm/kvm/coproc.c int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 1208 arch/arm/kvm/coproc.c void __user *uaddr = (void __user *)(long)reg->addr; reg 1211 arch/arm/kvm/coproc.c if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) reg 1212 arch/arm/kvm/coproc.c return demux_c15_get(reg->id, uaddr); reg 1214 arch/arm/kvm/coproc.c if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP) reg 1215 arch/arm/kvm/coproc.c return vfp_get_reg(vcpu, reg->id, uaddr); reg 1217 arch/arm/kvm/coproc.c r = index_to_coproc_reg(vcpu, reg->id); reg 1219 arch/arm/kvm/coproc.c return get_invariant_cp15(reg->id, uaddr); reg 1222 arch/arm/kvm/coproc.c if (KVM_REG_SIZE(reg->id) == 8) { reg 1226 arch/arm/kvm/coproc.c ret = reg_to_user(uaddr, &val, reg->id); reg 1227 arch/arm/kvm/coproc.c } else if (KVM_REG_SIZE(reg->id) == 4) { reg 1228 arch/arm/kvm/coproc.c ret = reg_to_user(uaddr, &vcpu_cp15(vcpu, r->reg), reg->id); reg 1234 arch/arm/kvm/coproc.c int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 1237 arch/arm/kvm/coproc.c void __user *uaddr = (void __user *)(long)reg->addr; reg 1240 arch/arm/kvm/coproc.c if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) reg 1241 arch/arm/kvm/coproc.c return demux_c15_set(reg->id, uaddr); reg 1243 arch/arm/kvm/coproc.c if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP) reg 1244 arch/arm/kvm/coproc.c return vfp_set_reg(vcpu, reg->id, uaddr); reg 1246 arch/arm/kvm/coproc.c r = index_to_coproc_reg(vcpu, reg->id); reg 1248 arch/arm/kvm/coproc.c return set_invariant_cp15(reg->id, uaddr); reg 1251 arch/arm/kvm/coproc.c if (KVM_REG_SIZE(reg->id) == 8) { reg 1254 arch/arm/kvm/coproc.c ret = reg_from_user(&val, uaddr, reg->id); reg 1257 arch/arm/kvm/coproc.c } else if (KVM_REG_SIZE(reg->id) == 4) { reg 1258 arch/arm/kvm/coproc.c ret = reg_from_user(&vcpu_cp15(vcpu, r->reg), uaddr, reg->id); reg 1291 arch/arm/kvm/coproc.c static u64 cp15_to_index(const struct coproc_reg *reg) reg 1294 arch/arm/kvm/coproc.c if (reg->is_64bit) { reg 1296 arch/arm/kvm/coproc.c val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT); reg 1304 arch/arm/kvm/coproc.c val |= (reg->CRn << KVM_REG_ARM_CRM_SHIFT); reg 1307 arch/arm/kvm/coproc.c val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT); reg 1308 arch/arm/kvm/coproc.c val |= (reg->Op2 << KVM_REG_ARM_32_OPC2_SHIFT); reg 1309 arch/arm/kvm/coproc.c val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT); reg 1310 arch/arm/kvm/coproc.c val |= (reg->CRn << KVM_REG_ARM_32_CRN_SHIFT); reg 1315 arch/arm/kvm/coproc.c static bool copy_reg_to_user(const struct coproc_reg *reg, u64 __user **uind) reg 1320 arch/arm/kvm/coproc.c if (put_user(cp15_to_index(reg), *uind)) reg 1348 arch/arm/kvm/coproc.c if (i1->reg) { reg 1355 arch/arm/kvm/coproc.c if (i2->reg) { reg 39 arch/arm/kvm/coproc.h unsigned long reg; reg 76 arch/arm/kvm/coproc.h BUG_ON(!r->reg); reg 77 arch/arm/kvm/coproc.h BUG_ON(r->reg >= ARRAY_SIZE(vcpu->arch.ctxt.cp15)); reg 78 arch/arm/kvm/coproc.h vcpu_cp15(vcpu, r->reg) = 0xdecafbad; reg 83 arch/arm/kvm/coproc.h BUG_ON(!r->reg); reg 84 arch/arm/kvm/coproc.h BUG_ON(r->reg >= ARRAY_SIZE(vcpu->arch.ctxt.cp15)); reg 85 arch/arm/kvm/coproc.h vcpu_cp15(vcpu, r->reg) = r->val; reg 91 arch/arm/kvm/coproc.h BUG_ON(!r->reg); reg 92 arch/arm/kvm/coproc.h BUG_ON(r->reg + 1 >= ARRAY_SIZE(vcpu->arch.ctxt.cp15)); reg 94 arch/arm/kvm/coproc.h vcpu_cp15(vcpu, r->reg) = 0xdecafbad; reg 95 arch/arm/kvm/coproc.h vcpu_cp15(vcpu, r->reg+1) = 0xd0c0ffee; reg 43 arch/arm/kvm/guest.c static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 45 arch/arm/kvm/guest.c u32 __user *uaddr = (u32 __user *)(long)reg->addr; reg 49 arch/arm/kvm/guest.c if (KVM_REG_SIZE(reg->id) != 4) reg 53 arch/arm/kvm/guest.c off = core_reg_offset_from_id(reg->id); reg 54 arch/arm/kvm/guest.c if (off >= sizeof(*regs) / KVM_REG_SIZE(reg->id)) reg 60 arch/arm/kvm/guest.c static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 62 arch/arm/kvm/guest.c u32 __user *uaddr = (u32 __user *)(long)reg->addr; reg 66 arch/arm/kvm/guest.c if (KVM_REG_SIZE(reg->id) != 4) reg 70 arch/arm/kvm/guest.c off = core_reg_offset_from_id(reg->id); reg 71 arch/arm/kvm/guest.c if (off >= sizeof(*regs) / KVM_REG_SIZE(reg->id)) reg 133 arch/arm/kvm/guest.c static int set_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 135 arch/arm/kvm/guest.c void __user *uaddr = (void __user *)(long)reg->addr; reg 139 arch/arm/kvm/guest.c ret = copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id)); reg 143 arch/arm/kvm/guest.c return kvm_arm_timer_set_reg(vcpu, reg->id, val); reg 146 arch/arm/kvm/guest.c static int get_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 148 arch/arm/kvm/guest.c void __user *uaddr = (void __user *)(long)reg->addr; reg 151 arch/arm/kvm/guest.c val = kvm_arm_timer_get_reg(vcpu, reg->id); reg 152 arch/arm/kvm/guest.c return copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id)) ? -EFAULT : 0; reg 202 arch/arm/kvm/guest.c int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 205 arch/arm/kvm/guest.c if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM >> 32) reg 209 arch/arm/kvm/guest.c if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE) reg 210 arch/arm/kvm/guest.c return get_core_reg(vcpu, reg); reg 212 arch/arm/kvm/guest.c if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_FW) reg 213 arch/arm/kvm/guest.c return kvm_arm_get_fw_reg(vcpu, reg); reg 215 arch/arm/kvm/guest.c if (is_timer_reg(reg->id)) reg 216 arch/arm/kvm/guest.c return get_timer_reg(vcpu, reg); reg 218 arch/arm/kvm/guest.c return kvm_arm_coproc_get_reg(vcpu, reg); reg 221 arch/arm/kvm/guest.c int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 224 arch/arm/kvm/guest.c if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM >> 32) reg 228 arch/arm/kvm/guest.c if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE) reg 229 arch/arm/kvm/guest.c return set_core_reg(vcpu, reg); reg 231 arch/arm/kvm/guest.c if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_FW) reg 232 arch/arm/kvm/guest.c return kvm_arm_set_fw_reg(vcpu, reg); reg 234 arch/arm/kvm/guest.c if (is_timer_reg(reg->id)) reg 235 arch/arm/kvm/guest.c return set_timer_reg(vcpu, reg); reg 237 arch/arm/kvm/guest.c return kvm_arm_coproc_set_reg(vcpu, reg); reg 12 arch/arm/kvm/vgic-v3-coproc.c u64 *reg) reg 21 arch/arm/kvm/vgic-v3-coproc.c u64 *reg) reg 45 arch/arm/mach-artpec/board-artpec6.c static void artpec6_l2c310_write_sec(unsigned long val, unsigned reg) reg 49 arch/arm/mach-artpec/board-artpec6.c arm_smccc_smc(SECURE_OP_L2C_WRITEREG, reg, val, 0, reg 184 arch/arm/mach-cns3xxx/pcie.c u32 reg; reg 187 arch/arm/mach-cns3xxx/pcie.c reg = __raw_readl(MISC_PCIE_CTRL(port)); reg 192 arch/arm/mach-cns3xxx/pcie.c reg |= 0x3; reg 193 arch/arm/mach-cns3xxx/pcie.c __raw_writel(reg, MISC_PCIE_CTRL(port)); reg 200 arch/arm/mach-cns3xxx/pcie.c reg = __raw_readl(MISC_PCIE_PM_DEBUG(port)); reg 201 arch/arm/mach-cns3xxx/pcie.c if (reg & 0x1) { reg 17 arch/arm/mach-cns3xxx/pm.c u32 reg = __raw_readl(PM_CLK_GATE_REG); reg 19 arch/arm/mach-cns3xxx/pm.c reg |= (block & PM_CLK_GATE_REG_MASK); reg 20 arch/arm/mach-cns3xxx/pm.c __raw_writel(reg, PM_CLK_GATE_REG); reg 26 arch/arm/mach-cns3xxx/pm.c u32 reg = __raw_readl(PM_CLK_GATE_REG); reg 28 arch/arm/mach-cns3xxx/pm.c reg &= ~(block & PM_CLK_GATE_REG_MASK); reg 29 arch/arm/mach-cns3xxx/pm.c __raw_writel(reg, PM_CLK_GATE_REG); reg 35 arch/arm/mach-cns3xxx/pm.c u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); reg 37 arch/arm/mach-cns3xxx/pm.c reg &= ~(block & CNS3XXX_PWR_PLL_ALL); reg 38 arch/arm/mach-cns3xxx/pm.c __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); reg 47 arch/arm/mach-cns3xxx/pm.c u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); reg 50 arch/arm/mach-cns3xxx/pm.c reg |= (block & CNS3XXX_PWR_PLL_ALL); reg 51 arch/arm/mach-cns3xxx/pm.c __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); reg 57 arch/arm/mach-cns3xxx/pm.c u32 reg = __raw_readl(PM_SOFT_RST_REG); reg 64 arch/arm/mach-cns3xxx/pm.c reg &= ~(block & PM_SOFT_RST_REG_MASK); reg 66 arch/arm/mach-cns3xxx/pm.c reg &= ~(block & PM_SOFT_RST_REG_MASK); reg 67 arch/arm/mach-cns3xxx/pm.c __raw_writel(reg, PM_SOFT_RST_REG); reg 68 arch/arm/mach-cns3xxx/pm.c reg |= (block & PM_SOFT_RST_REG_MASK); reg 71 arch/arm/mach-cns3xxx/pm.c __raw_writel(reg, PM_SOFT_RST_REG); reg 105 arch/arm/mach-cns3xxx/pm.c u32 reg = __raw_readl(PM_CLK_CTRL_REG); reg 110 arch/arm/mach-cns3xxx/pm.c cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf; reg 111 arch/arm/mach-cns3xxx/pm.c div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3; reg 624 arch/arm/mach-davinci/board-dm365-evm.c u8 reg = __raw_readb(cpld + CPLD_LEDS); reg 627 arch/arm/mach-davinci/board-dm365-evm.c reg &= ~led->mask; reg 629 arch/arm/mach-davinci/board-dm365-evm.c reg |= led->mask; reg 630 arch/arm/mach-davinci/board-dm365-evm.c __raw_writeb(reg, cpld + CPLD_LEDS); reg 636 arch/arm/mach-davinci/board-dm365-evm.c u8 reg = __raw_readb(cpld + CPLD_LEDS); reg 638 arch/arm/mach-davinci/board-dm365-evm.c return (reg & led->mask) ? LED_OFF : LED_FULL; reg 685 arch/arm/mach-davinci/da830.c .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K), reg 714 arch/arm/mach-davinci/da830.c .reg = { reg 342 arch/arm/mach-davinci/da850.c .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K), reg 635 arch/arm/mach-davinci/da850.c .reg = { reg 628 arch/arm/mach-davinci/dm355.c .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K), reg 801 arch/arm/mach-davinci/dm355.c .reg = { reg 1058 arch/arm/mach-davinci/dm365.c .reg = { reg 569 arch/arm/mach-davinci/dm644x.c .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K), reg 737 arch/arm/mach-davinci/dm644x.c .reg = { reg 509 arch/arm/mach-davinci/dm646x.c .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K), reg 698 arch/arm/mach-davinci/dm646x.c .reg = { reg 39 arch/arm/mach-davinci/mux.c unsigned int reg_orig = 0, reg = 0; reg 74 arch/arm/mach-davinci/mux.c reg = reg_orig & ~mask; reg 77 arch/arm/mach-davinci/mux.c reg |= tmp2; reg 82 arch/arm/mach-davinci/mux.c __raw_writel(reg, pinmux_base + cfg->mux_reg); reg 96 arch/arm/mach-davinci/mux.c cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); reg 22 arch/arm/mach-ebsa110/leds.c u8 reg = __raw_readb(SOFT_BASE); reg 25 arch/arm/mach-ebsa110/leds.c reg |= 0x80; reg 27 arch/arm/mach-ebsa110/leds.c reg &= ~0x80; reg 29 arch/arm/mach-ebsa110/leds.c __raw_writeb(reg, SOFT_BASE); reg 34 arch/arm/mach-ebsa110/leds.c u8 reg = __raw_readb(SOFT_BASE); reg 36 arch/arm/mach-ebsa110/leds.c return (reg & 0x80) ? LED_FULL : LED_OFF; reg 93 arch/arm/mach-ep93xx/core.c void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg) reg 100 arch/arm/mach-ep93xx/core.c __raw_writel(val, reg); reg 198 arch/arm/mach-ep93xx/soc.h void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg); reg 64 arch/arm/mach-exynos/exynos.c const __be32 *reg; reg 70 arch/arm/mach-exynos/exynos.c reg = of_get_flat_dt_prop(node, "reg", &len); reg 71 arch/arm/mach-exynos/exynos.c if (reg == NULL || len != (sizeof(unsigned long) * 2)) reg 74 arch/arm/mach-exynos/exynos.c iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0])); reg 75 arch/arm/mach-exynos/exynos.c iodesc.length = be32_to_cpu(reg[1]) - 1; reg 151 arch/arm/mach-exynos/firmware.c static void exynos_l2_write_sec(unsigned long val, unsigned reg) reg 155 arch/arm/mach-exynos/firmware.c switch (reg) { reg 177 arch/arm/mach-exynos/firmware.c WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg); reg 46 arch/arm/mach-footbridge/netwinder-hw.c static inline void wb977_wb(int reg, int val) reg 48 arch/arm/mach-footbridge/netwinder-hw.c outb(reg, 0x370); reg 52 arch/arm/mach-footbridge/netwinder-hw.c static inline void wb977_ww(int reg, int val) reg 54 arch/arm/mach-footbridge/netwinder-hw.c outb(reg, 0x370); reg 56 arch/arm/mach-footbridge/netwinder-hw.c outb(reg + 1, 0x370); reg 694 arch/arm/mach-footbridge/netwinder-hw.c u32 reg; reg 697 arch/arm/mach-footbridge/netwinder-hw.c reg = nw_gpio_read(); reg 699 arch/arm/mach-footbridge/netwinder-hw.c reg &= ~led->mask; reg 701 arch/arm/mach-footbridge/netwinder-hw.c reg |= led->mask; reg 702 arch/arm/mach-footbridge/netwinder-hw.c nw_gpio_modify_op(led->mask, reg); reg 711 arch/arm/mach-footbridge/netwinder-hw.c u32 reg; reg 714 arch/arm/mach-footbridge/netwinder-hw.c reg = nw_gpio_read(); reg 717 arch/arm/mach-footbridge/netwinder-hw.c return (reg & led->mask) ? LED_OFF : LED_FULL; reg 42 arch/arm/mach-highbank/highbank.c static void highbank_l2c310_write_sec(unsigned long val, unsigned reg) reg 44 arch/arm/mach-highbank/highbank.c if (reg == L2X0_CTRL) reg 48 arch/arm/mach-highbank/highbank.c reg); reg 71 arch/arm/mach-highbank/highbank.c int reg = -1; reg 79 arch/arm/mach-highbank/highbank.c reg = 0xc; reg 81 arch/arm/mach-highbank/highbank.c reg = 0x18; reg 83 arch/arm/mach-highbank/highbank.c reg = 0x20; reg 89 arch/arm/mach-highbank/highbank.c reg = 0; reg 91 arch/arm/mach-highbank/highbank.c reg = 4; reg 95 arch/arm/mach-highbank/highbank.c if (reg < 0) reg 99 arch/arm/mach-highbank/highbank.c val = readl(sregs_base + reg); reg 100 arch/arm/mach-highbank/highbank.c writel(val | 0xff01, sregs_base + reg); reg 111 arch/arm/mach-imx/3ds_debugboard.c u16 reg; reg 114 arch/arm/mach-imx/3ds_debugboard.c reg = imx_readw(brd_io + INTR_MASK_REG); reg 115 arch/arm/mach-imx/3ds_debugboard.c reg |= (1 << expio); reg 116 arch/arm/mach-imx/3ds_debugboard.c imx_writew(reg, brd_io + INTR_MASK_REG); reg 130 arch/arm/mach-imx/3ds_debugboard.c u16 reg; reg 133 arch/arm/mach-imx/3ds_debugboard.c reg = imx_readw(brd_io + INTR_MASK_REG); reg 134 arch/arm/mach-imx/3ds_debugboard.c reg &= ~(1 << expio); reg 135 arch/arm/mach-imx/3ds_debugboard.c imx_writew(reg, brd_io + INTR_MASK_REG); reg 43 arch/arm/mach-imx/anatop.c u32 reg, val; reg 48 arch/arm/mach-imx/anatop.c reg = ANADIG_REG_2P5; reg 49 arch/arm/mach-imx/anatop.c reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ? reg 51 arch/arm/mach-imx/anatop.c regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG); reg 42 arch/arm/mach-imx/cpu.c unsigned int reg; reg 59 arch/arm/mach-imx/cpu.c reg = imx_readl(base + 0x50) & 0x00FFFFFF; reg 60 arch/arm/mach-imx/cpu.c imx_writel(reg, base + 0x50); reg 128 arch/arm/mach-imx/gpc.c void __iomem *reg; reg 131 arch/arm/mach-imx/gpc.c reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; reg 132 arch/arm/mach-imx/gpc.c val = readl_relaxed(reg); reg 134 arch/arm/mach-imx/gpc.c writel_relaxed(val, reg); reg 139 arch/arm/mach-imx/gpc.c void __iomem *reg; reg 142 arch/arm/mach-imx/gpc.c reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; reg 143 arch/arm/mach-imx/gpc.c val = readl_relaxed(reg); reg 145 arch/arm/mach-imx/gpc.c writel_relaxed(val, reg); reg 39 arch/arm/mach-imx/iomux-imx31.c void __iomem *reg; reg 41 arch/arm/mach-imx/iomux-imx31.c reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK); reg 47 arch/arm/mach-imx/iomux-imx31.c l = imx_readl(reg); reg 50 arch/arm/mach-imx/iomux-imx31.c imx_writel(l, reg); reg 61 arch/arm/mach-imx/iomux-imx31.c void __iomem *reg; reg 64 arch/arm/mach-imx/iomux-imx31.c reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4; reg 72 arch/arm/mach-imx/iomux-imx31.c l = imx_readl(reg); reg 75 arch/arm/mach-imx/iomux-imx31.c imx_writel(l, reg); reg 39 arch/arm/mach-imx/iomux-v1.c unsigned long reg = imx_iomuxv1_readl(offset); reg 41 arch/arm/mach-imx/iomux-v1.c reg &= ~mask; reg 42 arch/arm/mach-imx/iomux-v1.c reg |= value; reg 44 arch/arm/mach-imx/iomux-v1.c imx_iomuxv1_writel(reg, offset); reg 56 arch/arm/mach-imx/mach-imx6q.c static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val) reg 59 arch/arm/mach-imx/mach-imx6q.c phy_write(dev, 0x0e, reg); reg 31 arch/arm/mach-imx/mm-imx3.c unsigned long reg = 0; reg 55 arch/arm/mach-imx/mm-imx3.c : "=r" (reg)); reg 130 arch/arm/mach-imx/mm-imx3.c int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR); reg 131 arch/arm/mach-imx/mm-imx3.c reg &= ~MXC_CCM_CCMR_LPM_MASK; reg 132 arch/arm/mach-imx/mm-imx3.c imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR); reg 222 arch/arm/mach-imx/mm-imx3.c int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR); reg 223 arch/arm/mach-imx/mm-imx3.c reg &= ~MXC_CCM_CCMR_LPM_MASK; reg 224 arch/arm/mach-imx/mm-imx3.c reg |= MXC_CCM_CCMR_LPM_WAIT_MX35; reg 225 arch/arm/mach-imx/mm-imx3.c imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR); reg 184 arch/arm/mach-imx/mmdc.c void __iomem *mmdc_base, *reg; reg 190 arch/arm/mach-imx/mmdc.c reg = mmdc_base + MMDC_MADPSR0; reg 193 arch/arm/mach-imx/mmdc.c reg = mmdc_base + MMDC_MADPSR1; reg 196 arch/arm/mach-imx/mmdc.c reg = mmdc_base + MMDC_MADPSR2; reg 199 arch/arm/mach-imx/mmdc.c reg = mmdc_base + MMDC_MADPSR3; reg 202 arch/arm/mach-imx/mmdc.c reg = mmdc_base + MMDC_MADPSR4; reg 205 arch/arm/mach-imx/mmdc.c reg = mmdc_base + MMDC_MADPSR5; reg 211 arch/arm/mach-imx/mmdc.c return readl(reg); reg 326 arch/arm/mach-imx/mmdc.c void __iomem *mmdc_base, *reg; reg 330 arch/arm/mach-imx/mmdc.c reg = mmdc_base + MMDC_MADPCR0; reg 341 arch/arm/mach-imx/mmdc.c writel(DBG_RST, reg); reg 347 arch/arm/mach-imx/mmdc.c reg = mmdc_base + MMDC_MADPCR1; reg 348 arch/arm/mach-imx/mmdc.c writel(val, reg); reg 350 arch/arm/mach-imx/mmdc.c reg = mmdc_base + MMDC_MADPCR0; reg 355 arch/arm/mach-imx/mmdc.c writel(val, reg); reg 382 arch/arm/mach-imx/mmdc.c void __iomem *mmdc_base, *reg; reg 385 arch/arm/mach-imx/mmdc.c reg = mmdc_base + MMDC_MADPCR0; reg 387 arch/arm/mach-imx/mmdc.c writel(PRF_FRZ, reg); reg 389 arch/arm/mach-imx/mmdc.c reg = mmdc_base + MMDC_MADPCR1; reg 390 arch/arm/mach-imx/mmdc.c writel(MMDC_PRF_AXI_ID_CLEAR, reg); reg 538 arch/arm/mach-imx/mmdc.c void __iomem *mmdc_base, *reg; reg 557 arch/arm/mach-imx/mmdc.c reg = mmdc_base + MMDC_MDMISC; reg 559 arch/arm/mach-imx/mmdc.c val = readl_relaxed(reg); reg 563 arch/arm/mach-imx/mmdc.c reg = mmdc_base + MMDC_MAPSR; reg 566 arch/arm/mach-imx/mmdc.c val = readl_relaxed(reg); reg 568 arch/arm/mach-imx/mmdc.c writel_relaxed(val, reg); reg 17 arch/arm/mach-iop32x/iop3xx.h #define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg)) reg 53 arch/arm/mach-iop32x/iop3xx.h #define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg)) reg 88 arch/arm/mach-mmp/devices.c u32 reg; reg 90 arch/arm/mach-mmp/devices.c reg = readl_relaxed(base + offset); reg 91 arch/arm/mach-mmp/devices.c reg |= value; reg 92 arch/arm/mach-mmp/devices.c writel_relaxed(reg, base + offset); reg 99 arch/arm/mach-mmp/devices.c u32 reg; reg 101 arch/arm/mach-mmp/devices.c reg = readl_relaxed(base + offset); reg 102 arch/arm/mach-mmp/devices.c reg &= ~value; reg 103 arch/arm/mach-mmp/devices.c writel_relaxed(reg, base + offset); reg 189 arch/arm/mach-mmp/pm-pxa910.c unsigned int idle_cfg, reg = 0; reg 192 arch/arm/mach-mmp/pm-pxa910.c reg = __raw_readl(ICU_INT_CONF(IRQ_PXA910_PMIC_INT)); reg 193 arch/arm/mach-mmp/pm-pxa910.c if ((reg & 0x3) == 0) reg 73 arch/arm/mach-mvebu/board-v7.c const __be32 *reg, *endp; reg 79 arch/arm/mach-mvebu/board-v7.c reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l); reg 80 arch/arm/mach-mvebu/board-v7.c if (reg == NULL) reg 81 arch/arm/mach-mvebu/board-v7.c reg = of_get_flat_dt_prop(node, "reg", &l); reg 82 arch/arm/mach-mvebu/board-v7.c if (reg == NULL) reg 85 arch/arm/mach-mvebu/board-v7.c endp = reg + (l / sizeof(__be32)); reg 86 arch/arm/mach-mvebu/board-v7.c while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) { reg 89 arch/arm/mach-mvebu/board-v7.c base = dt_mem_next_cell(dt_root_addr_cells, ®); reg 90 arch/arm/mach-mvebu/board-v7.c size = dt_mem_next_cell(dt_root_size_cells, ®); reg 84 arch/arm/mach-mvebu/coherency.c u32 reg; reg 89 arch/arm/mach-mvebu/coherency.c reg = readl(cpu_config_base); reg 90 arch/arm/mach-mvebu/coherency.c reg &= ~CPU_CONFIG_SHARED_L2; reg 91 arch/arm/mach-mvebu/coherency.c writel(reg, cpu_config_base); reg 29 arch/arm/mach-mvebu/cpu-reset.c u32 reg; reg 37 arch/arm/mach-mvebu/cpu-reset.c reg = readl(cpu_reset_base + CPU_RESET_OFFSET(cpu)); reg 38 arch/arm/mach-mvebu/cpu-reset.c reg &= ~CPU_RESET_ASSERT; reg 39 arch/arm/mach-mvebu/cpu-reset.c writel(reg, cpu_reset_base + CPU_RESET_OFFSET(cpu)); reg 89 arch/arm/mach-mvebu/kirkwood.c u32 reg; reg 124 arch/arm/mach-mvebu/kirkwood.c reg = readl(io + MV643XX_ETH_MAC_ADDR_HIGH); reg 125 arch/arm/mach-mvebu/kirkwood.c macaddr[0] = (reg >> 24) & 0xff; reg 126 arch/arm/mach-mvebu/kirkwood.c macaddr[1] = (reg >> 16) & 0xff; reg 127 arch/arm/mach-mvebu/kirkwood.c macaddr[2] = (reg >> 8) & 0xff; reg 128 arch/arm/mach-mvebu/kirkwood.c macaddr[3] = reg & 0xff; reg 130 arch/arm/mach-mvebu/kirkwood.c reg = readl(io + MV643XX_ETH_MAC_ADDR_LOW); reg 131 arch/arm/mach-mvebu/kirkwood.c macaddr[4] = (reg >> 8) & 0xff; reg 132 arch/arm/mach-mvebu/kirkwood.c macaddr[5] = reg & 0xff; reg 31 arch/arm/mach-mvebu/pm-board.c u32 reg, ackcmd; reg 35 arch/arm/mach-mvebu/pm-board.c reg = readl(gpio_ctrl); reg 37 arch/arm/mach-mvebu/pm-board.c reg &= ~BIT(pic_raw_gpios[i]); reg 38 arch/arm/mach-mvebu/pm-board.c reg |= BIT(pic_raw_gpios[0]); reg 39 arch/arm/mach-mvebu/pm-board.c writel(reg, gpio_ctrl); reg 41 arch/arm/mach-mvebu/pm.c u32 reg, srcmd; reg 53 arch/arm/mach-mvebu/pm.c reg = readl(sdram_ctrl + SDRAM_DLB_EVICTION_OFFS); reg 54 arch/arm/mach-mvebu/pm.c reg &= ~SDRAM_DLB_EVICTION_THRESHOLD_MASK; reg 55 arch/arm/mach-mvebu/pm.c writel(reg, sdram_ctrl + SDRAM_DLB_EVICTION_OFFS); reg 60 arch/arm/mach-mvebu/pm.c reg = readl(sdram_ctrl + SDRAM_CONFIG_OFFS); reg 61 arch/arm/mach-mvebu/pm.c reg &= ~SDRAM_CONFIG_SR_MODE_BIT; reg 62 arch/arm/mach-mvebu/pm.c writel(reg, sdram_ctrl + SDRAM_CONFIG_OFFS); reg 209 arch/arm/mach-mvebu/pmsu.c u32 reg; reg 215 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL); reg 216 arch/arm/mach-mvebu/pmsu.c reg |= L2C_NFABRIC_PM_CTL_PWR_DOWN; reg 217 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL); reg 230 arch/arm/mach-mvebu/pmsu.c u32 reg; reg 240 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); reg 241 arch/arm/mach-mvebu/pmsu.c reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT | reg 247 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); reg 249 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); reg 252 arch/arm/mach-mvebu/pmsu.c reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN; reg 255 arch/arm/mach-mvebu/pmsu.c reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ; reg 256 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); reg 260 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); reg 261 arch/arm/mach-mvebu/pmsu.c reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP; reg 262 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); reg 344 arch/arm/mach-mvebu/pmsu.c u32 reg; reg 349 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); reg 350 arch/arm/mach-mvebu/pmsu.c reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN; reg 351 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); reg 354 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); reg 355 arch/arm/mach-mvebu/pmsu.c reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP | PMSU_STATUS_AND_MASK_FIQ_WAKEUP); reg 356 arch/arm/mach-mvebu/pmsu.c reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT; reg 357 arch/arm/mach-mvebu/pmsu.c reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT; reg 358 arch/arm/mach-mvebu/pmsu.c reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK | PMSU_STATUS_AND_MASK_FIQ_MASK); reg 359 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); reg 429 arch/arm/mach-mvebu/pmsu.c u32 reg; reg 452 arch/arm/mach-mvebu/pmsu.c reg = readl(mpsoc_base + MPCORE_RESET_CTL); reg 453 arch/arm/mach-mvebu/pmsu.c reg |= MPCORE_RESET_CTL_L2; reg 454 arch/arm/mach-mvebu/pmsu.c reg |= MPCORE_RESET_CTL_DEBUG; reg 455 arch/arm/mach-mvebu/pmsu.c writel(reg, mpsoc_base + MPCORE_RESET_CTL); reg 459 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_POWERDOWN_DELAY); reg 460 arch/arm/mach-mvebu/pmsu.c reg &= ~PMSU_POWERDOWN_DELAY_MASK; reg 461 arch/arm/mach-mvebu/pmsu.c reg |= PMSU_DFLT_ARMADA38X_DELAY; reg 462 arch/arm/mach-mvebu/pmsu.c reg |= PMSU_POWERDOWN_DELAY_PMU; reg 463 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_POWERDOWN_DELAY); reg 539 arch/arm/mach-mvebu/pmsu.c u32 reg; reg 546 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu)); reg 547 arch/arm/mach-mvebu/pmsu.c reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT | reg 550 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu)); reg 553 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu)); reg 554 arch/arm/mach-mvebu/pmsu.c reg |= PMSU_CONTROL_AND_CONFIG_DFS_REQ; reg 555 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu)); reg 564 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu)); reg 565 arch/arm/mach-mvebu/pmsu.c reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT; reg 566 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu)); reg 575 arch/arm/mach-mvebu/pmsu.c u32 reg; reg 578 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); reg 579 arch/arm/mach-mvebu/pmsu.c reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE; reg 580 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); reg 583 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); reg 584 arch/arm/mach-mvebu/pmsu.c reg |= PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK; reg 585 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); reg 594 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); reg 595 arch/arm/mach-mvebu/pmsu.c if (reg & PMSU_EVENT_STATUS_AND_MASK_DFS_DONE) reg 604 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); reg 605 arch/arm/mach-mvebu/pmsu.c reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK; reg 606 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); reg 59 arch/arm/mach-mxs/mach-mxs.c static inline void __mxs_setl(u32 mask, void __iomem *reg) reg 61 arch/arm/mach-mxs/mach-mxs.c __raw_writel(mask, reg + MXS_SET_ADDR); reg 64 arch/arm/mach-mxs/mach-mxs.c static inline void __mxs_clrl(u32 mask, void __iomem *reg) reg 66 arch/arm/mach-mxs/mach-mxs.c __raw_writel(mask, reg + MXS_CLR_ADDR); reg 69 arch/arm/mach-mxs/mach-mxs.c static inline void __mxs_togl(u32 mask, void __iomem *reg) reg 71 arch/arm/mach-mxs/mach-mxs.c __raw_writel(mask, reg + MXS_TOG_ADDR); reg 39 arch/arm/mach-omap1/board-fsample.c #define fsample_cpld_read(reg) __raw_readb(reg) reg 40 arch/arm/mach-omap1/board-fsample.c #define fsample_cpld_write(val, reg) __raw_writeb(val, reg) reg 447 arch/arm/mach-omap1/board-htcherald.c u32 reg; reg 451 arch/arm/mach-omap1/board-htcherald.c reg = omap_readl(OMAP_LCDC_CONTROL); reg 452 arch/arm/mach-omap1/board-htcherald.c if (reg & OMAP_LCDC_CTRL_LCD_EN) { reg 453 arch/arm/mach-omap1/board-htcherald.c reg &= ~OMAP_LCDC_CTRL_LCD_EN; reg 454 arch/arm/mach-omap1/board-htcherald.c omap_writel(reg, OMAP_LCDC_CONTROL); reg 466 arch/arm/mach-omap1/board-htcherald.c reg = omap_readw(OMAP_DMA_LCD_CCR); reg 467 arch/arm/mach-omap1/board-htcherald.c reg &= ~(1 << 7); reg 468 arch/arm/mach-omap1/board-htcherald.c omap_writew(reg, OMAP_DMA_LCD_CCR); reg 470 arch/arm/mach-omap1/board-htcherald.c reg = omap_readw(OMAP_DMA_LCD_CTRL); reg 471 arch/arm/mach-omap1/board-htcherald.c reg &= ~(1 << 8); reg 472 arch/arm/mach-omap1/board-htcherald.c omap_writew(reg, OMAP_DMA_LCD_CTRL); reg 379 arch/arm/mach-omap1/board-innovator.c unsigned char reg; reg 389 arch/arm/mach-omap1/board-innovator.c reg = __raw_readb(OMAP1510_FPGA_POWER); reg 390 arch/arm/mach-omap1/board-innovator.c reg |= OMAP1510_FPGA_PCR_COM1_EN; reg 391 arch/arm/mach-omap1/board-innovator.c __raw_writeb(reg, OMAP1510_FPGA_POWER); reg 394 arch/arm/mach-omap1/board-innovator.c reg = __raw_readb(OMAP1510_FPGA_POWER); reg 395 arch/arm/mach-omap1/board-innovator.c reg |= OMAP1510_FPGA_PCR_COM2_EN; reg 396 arch/arm/mach-omap1/board-innovator.c __raw_writeb(reg, OMAP1510_FPGA_POWER); reg 767 arch/arm/mach-omap1/clock_data.c u32 reg; reg 778 arch/arm/mach-omap1/clock_data.c reg = omap_readw(SOFT_REQ_REG) & (1 << 4); reg 779 arch/arm/mach-omap1/clock_data.c omap_writew(reg, SOFT_REQ_REG); reg 175 arch/arm/mach-omap1/dma.c static inline void dma_write(u32 val, int reg, int lch) reg 179 arch/arm/mach-omap1/dma.c addr += reg_map[reg].offset; reg 180 arch/arm/mach-omap1/dma.c addr += reg_map[reg].stride * lch; reg 183 arch/arm/mach-omap1/dma.c if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT) reg 187 arch/arm/mach-omap1/dma.c static inline u32 dma_read(int reg, int lch) reg 192 arch/arm/mach-omap1/dma.c addr += reg_map[reg].offset; reg 193 arch/arm/mach-omap1/dma.c addr += reg_map[reg].stride * lch; reg 196 arch/arm/mach-omap1/dma.c if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT) reg 27 arch/arm/mach-omap1/include/mach/mux.h #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \ reg 28 arch/arm/mach-omap1/include/mach/mux.h .mux_reg = FUNC_MUX_CTRL_##reg, \ reg 32 arch/arm/mach-omap1/include/mach/mux.h #define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \ reg 33 arch/arm/mach-omap1/include/mach/mux.h .pull_reg = PULL_DWN_CTRL_##reg, \ reg 37 arch/arm/mach-omap1/include/mach/mux.h #define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \ reg 38 arch/arm/mach-omap1/include/mach/mux.h .pu_pd_reg = PU_PD_SEL_##reg, \ reg 41 arch/arm/mach-omap1/include/mach/mux.h #define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \ reg 42 arch/arm/mach-omap1/include/mach/mux.h .mux_reg = OMAP7XX_IO_CONF_##reg, \ reg 46 arch/arm/mach-omap1/include/mach/mux.h #define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \ reg 47 arch/arm/mach-omap1/include/mach/mux.h .pull_reg = OMAP7XX_IO_CONF_##reg, \ reg 53 arch/arm/mach-omap1/include/mach/mux.h #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ reg 57 arch/arm/mach-omap1/include/mach/mux.h #define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \ reg 61 arch/arm/mach-omap1/include/mach/mux.h #define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \ reg 64 arch/arm/mach-omap1/include/mach/mux.h #define MUX_REG_7XX(reg, mode_offset, mode) \ reg 65 arch/arm/mach-omap1/include/mach/mux.h .mux_reg = OMAP7XX_IO_CONF_##reg, \ reg 69 arch/arm/mach-omap1/include/mach/mux.h #define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \ reg 336 arch/arm/mach-omap1/mux.c unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0, reg 350 arch/arm/mach-omap1/mux.c reg = reg_orig & ~mask; reg 353 arch/arm/mach-omap1/mux.c reg |= tmp2; reg 358 arch/arm/mach-omap1/mux.c omap_writel(reg, cfg->mux_reg); reg 417 arch/arm/mach-omap1/mux.c cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); reg 460 arch/arm/mach-omap1/mux.c struct pin_config *reg; reg 481 arch/arm/mach-omap1/mux.c reg = &mux_cfg->pins[index]; reg 486 arch/arm/mach-omap1/mux.c return mux_cfg->cfg_reg(reg); reg 89 arch/arm/mach-omap1/timer32k.c static inline void omap_32k_timer_write(int val, int reg) reg 91 arch/arm/mach-omap1/timer32k.c omap_writew(val, OMAP1_32K_TIMER_BASE + reg); reg 28 arch/arm/mach-omap2/cm1_44xx.h #define OMAP44XX_CM1_REGADDR(inst, reg) \ reg 29 arch/arm/mach-omap2/cm1_44xx.h OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg)) reg 24 arch/arm/mach-omap2/cm1_54xx.h #define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg) \ reg 25 arch/arm/mach-omap2/cm1_54xx.h OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg)) reg 25 arch/arm/mach-omap2/cm1_7xx.h #define DRA7XX_CM_CORE_AON_REGADDR(inst, reg) \ reg 26 arch/arm/mach-omap2/cm1_7xx.h OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg)) reg 28 arch/arm/mach-omap2/cm2_44xx.h #define OMAP44XX_CM2_REGADDR(inst, reg) \ reg 29 arch/arm/mach-omap2/cm2_44xx.h OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg)) reg 24 arch/arm/mach-omap2/cm2_54xx.h #define OMAP54XX_CM_CORE_REGADDR(inst, reg) \ reg 25 arch/arm/mach-omap2/cm2_54xx.h OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg)) reg 25 arch/arm/mach-omap2/cm2_7xx.h #define DRA7XX_CM_CORE_REGADDR(inst, reg) \ reg 26 arch/arm/mach-omap2/cm2_7xx.h OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg)) reg 19 arch/arm/mach-omap2/cm2xxx.h #define OMAP2420_CM_REGADDR(module, reg) \ reg 20 arch/arm/mach-omap2/cm2xxx.h OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) reg 21 arch/arm/mach-omap2/cm2xxx.h #define OMAP2430_CM_REGADDR(module, reg) \ reg 22 arch/arm/mach-omap2/cm2xxx.h OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) reg 27 arch/arm/mach-omap2/cm33xx.h #define AM33XX_CM_REGADDR(inst, reg) \ reg 28 arch/arm/mach-omap2/cm33xx.h AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg)) reg 19 arch/arm/mach-omap2/cm3xxx.h #define OMAP34XX_CM_REGADDR(module, reg) \ reg 20 arch/arm/mach-omap2/cm3xxx.h OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) reg 104 arch/arm/mach-omap2/common.h void omap4_l2c310_write_sec(unsigned long val, unsigned reg); reg 22 arch/arm/mach-omap2/control.h #define OMAP242X_CTRL_REGADDR(reg) \ reg 23 arch/arm/mach-omap2/control.h OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) reg 24 arch/arm/mach-omap2/control.h #define OMAP243X_CTRL_REGADDR(reg) \ reg 25 arch/arm/mach-omap2/control.h OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) reg 26 arch/arm/mach-omap2/control.h #define OMAP343X_CTRL_REGADDR(reg) \ reg 27 arch/arm/mach-omap2/control.h OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) reg 28 arch/arm/mach-omap2/control.h #define AM33XX_CTRL_REGADDR(reg) \ reg 29 arch/arm/mach-omap2/control.h AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) reg 31 arch/arm/mach-omap2/control.h #define OMAP242X_CTRL_REGADDR(reg) \ reg 32 arch/arm/mach-omap2/control.h OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) reg 33 arch/arm/mach-omap2/control.h #define OMAP243X_CTRL_REGADDR(reg) \ reg 34 arch/arm/mach-omap2/control.h OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) reg 35 arch/arm/mach-omap2/control.h #define OMAP343X_CTRL_REGADDR(reg) \ reg 36 arch/arm/mach-omap2/control.h OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) reg 37 arch/arm/mach-omap2/control.h #define AM33XX_CTRL_REGADDR(reg) \ reg 38 arch/arm/mach-omap2/control.h AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) reg 362 arch/arm/mach-omap2/control.h #define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\ reg 363 arch/arm/mach-omap2/control.h OMAP343X_SCRATCHPAD + reg) reg 85 arch/arm/mach-omap2/display.c u32 reg; reg 104 arch/arm/mach-omap2/display.c ®); reg 108 arch/arm/mach-omap2/display.c reg &= ~enable_mask; reg 109 arch/arm/mach-omap2/display.c reg &= ~pipd_mask; reg 111 arch/arm/mach-omap2/display.c reg |= (lanes << enable_shift) & enable_mask; reg 112 arch/arm/mach-omap2/display.c reg |= (lanes << pipd_shift) & pipd_mask; reg 114 arch/arm/mach-omap2/display.c regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg); reg 85 arch/arm/mach-omap2/dma.c static inline void dma_write(u32 val, int reg, int lch) reg 89 arch/arm/mach-omap2/dma.c addr += reg_map[reg].offset; reg 90 arch/arm/mach-omap2/dma.c addr += reg_map[reg].stride * lch; reg 95 arch/arm/mach-omap2/dma.c static inline u32 dma_read(int reg, int lch) reg 99 arch/arm/mach-omap2/dma.c addr += reg_map[reg].offset; reg 100 arch/arm/mach-omap2/dma.c addr += reg_map[reg].stride * lch; reg 99 arch/arm/mach-omap2/id.c #define read_tap_reg(reg) readl_relaxed(tap_base + (reg)) reg 155 arch/arm/mach-omap2/omap-mpuss-lowpower.c u32 reg; reg 157 arch/arm/mach-omap2/omap-mpuss-lowpower.c reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, reg 159 arch/arm/mach-omap2/omap-mpuss-lowpower.c omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION, reg 165 arch/arm/mach-omap2/omap-mpuss-lowpower.c u32 reg; reg 168 arch/arm/mach-omap2/omap-mpuss-lowpower.c reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST, reg 170 arch/arm/mach-omap2/omap-mpuss-lowpower.c omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST, reg 173 arch/arm/mach-omap2/omap-mpuss-lowpower.c reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST, reg 175 arch/arm/mach-omap2/omap-mpuss-lowpower.c omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST, reg 345 arch/arm/mach-omap2/omap-mpuss-lowpower.c u32 reg; reg 347 arch/arm/mach-omap2/omap-mpuss-lowpower.c reg = omap4_prcm_mpu_read_inst_reg(OMAP54XX_PRCM_MPU_DEVICE_INST, reg 350 arch/arm/mach-omap2/omap-mpuss-lowpower.c reg |= BIT(24) | BIT(25); reg 351 arch/arm/mach-omap2/omap-mpuss-lowpower.c omap4_prcm_mpu_write_inst_reg(reg, OMAP54XX_PRCM_MPU_DEVICE_INST, reg 206 arch/arm/mach-omap2/omap-wakeupgen.c static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg) reg 211 arch/arm/mach-omap2/omap-wakeupgen.c wakeupgen_writel(reg, i, cpu); reg 219 arch/arm/mach-omap2/omap4-common.c void omap4_l2c310_write_sec(unsigned long val, unsigned reg) reg 223 arch/arm/mach-omap2/omap4-common.c switch (reg) { reg 245 arch/arm/mach-omap2/omap4-common.c WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg); reg 65 arch/arm/mach-omap2/pdata-quirks.c u32 reg; reg 67 arch/arm/mach-omap2/pdata-quirks.c reg = omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); reg 68 arch/arm/mach-omap2/pdata-quirks.c reg &= ~OMAP343X_PBIASLITEVMODE1; reg 69 arch/arm/mach-omap2/pdata-quirks.c reg |= OMAP343X_PBIASLITEPWRDNZ1; reg 70 arch/arm/mach-omap2/pdata-quirks.c omap_ctrl_writel(reg, OMAP343X_CONTROL_PBIAS_LITE); reg 72 arch/arm/mach-omap2/pdata-quirks.c reg = omap_ctrl_readl(OMAP34XX_CONTROL_WKUP_CTRL); reg 73 arch/arm/mach-omap2/pdata-quirks.c reg |= OMAP36XX_GPIO_IO_PWRDNZ; reg 74 arch/arm/mach-omap2/pdata-quirks.c omap_ctrl_writel(reg, OMAP34XX_CONTROL_WKUP_CTRL); reg 80 arch/arm/mach-omap2/pdata-quirks.c u32 reg; reg 82 arch/arm/mach-omap2/pdata-quirks.c reg = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1); reg 83 arch/arm/mach-omap2/pdata-quirks.c reg |= OMAP2_MMCSDIO2ADPCLKISEL; reg 84 arch/arm/mach-omap2/pdata-quirks.c omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1); reg 28 arch/arm/mach-omap2/prcm_mpu44xx.c u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg) reg 30 arch/arm/mach-omap2/prcm_mpu44xx.c return readl_relaxed(OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); reg 33 arch/arm/mach-omap2/prcm_mpu44xx.c void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg) reg 35 arch/arm/mach-omap2/prcm_mpu44xx.c writel_relaxed(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); reg 38 arch/arm/mach-omap2/prcm_mpu44xx.c u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) reg 42 arch/arm/mach-omap2/prcm_mpu44xx.c v = omap4_prcm_mpu_read_inst_reg(inst, reg); reg 45 arch/arm/mach-omap2/prcm_mpu44xx.c omap4_prcm_mpu_write_inst_reg(v, inst, reg); reg 29 arch/arm/mach-omap2/prcm_mpu44xx.h #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \ reg 30 arch/arm/mach-omap2/prcm_mpu44xx.h OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg)) reg 26 arch/arm/mach-omap2/prcm_mpu54xx.h #define OMAP54XX_PRCM_MPU_REGADDR(inst, reg) \ reg 27 arch/arm/mach-omap2/prcm_mpu54xx.h OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg)) reg 26 arch/arm/mach-omap2/prcm_mpu7xx.h #define DRA7XX_PRCM_MPU_REGADDR(inst, reg) \ reg 27 arch/arm/mach-omap2/prcm_mpu7xx.h OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg)) reg 20 arch/arm/mach-omap2/prm2xxx.h #define OMAP2420_PRM_REGADDR(module, reg) \ reg 21 arch/arm/mach-omap2/prm2xxx.h OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) reg 22 arch/arm/mach-omap2/prm2xxx.h #define OMAP2430_PRM_REGADDR(module, reg) \ reg 23 arch/arm/mach-omap2/prm2xxx.h OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) reg 24 arch/arm/mach-omap2/prm33xx.h #define AM33XX_PRM_REGADDR(inst, reg) \ reg 25 arch/arm/mach-omap2/prm33xx.h AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg)) reg 20 arch/arm/mach-omap2/prm3xxx.h #define OMAP34XX_PRM_REGADDR(module, reg) \ reg 21 arch/arm/mach-omap2/prm3xxx.h OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) reg 96 arch/arm/mach-omap2/prm44xx.c static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) reg 98 arch/arm/mach-omap2/prm44xx.c return readl_relaxed(prm_base.va + inst + reg); reg 102 arch/arm/mach-omap2/prm44xx.c static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) reg 104 arch/arm/mach-omap2/prm44xx.c writel_relaxed(val, prm_base.va + inst + reg); reg 108 arch/arm/mach-omap2/prm44xx.c static u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) reg 112 arch/arm/mach-omap2/prm44xx.c v = omap4_prm_read_inst_reg(inst, reg); reg 115 arch/arm/mach-omap2/prm44xx.c omap4_prm_write_inst_reg(v, inst, reg); reg 260 arch/arm/mach-omap2/prm44xx.c u16 reg; reg 263 arch/arm/mach-omap2/prm44xx.c reg = omap4_prcm_irq_setup.mask + i * 4; reg 267 arch/arm/mach-omap2/prm44xx.c reg); reg 268 arch/arm/mach-omap2/prm44xx.c omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, reg); reg 30 arch/arm/mach-omap2/prm44xx.h #define OMAP44XX_PRM_REGADDR(inst, reg) \ reg 31 arch/arm/mach-omap2/prm44xx.h OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg)) reg 26 arch/arm/mach-omap2/prm54xx.h #define OMAP54XX_PRM_REGADDR(inst, reg) \ reg 27 arch/arm/mach-omap2/prm54xx.h OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE + (inst) + (reg)) reg 28 arch/arm/mach-omap2/prm7xx.h #define DRA7XX_PRM_REGADDR(inst, reg) \ reg 29 arch/arm/mach-omap2/prm7xx.h OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg)) reg 21 arch/arm/mach-omap2/scrm44xx.h #define OMAP44XX_SCRM_REGADDR(reg) \ reg 22 arch/arm/mach-omap2/scrm44xx.h OMAP2_L4_IO_ADDRESS(OMAP4_SCRM_BASE + (reg)) reg 21 arch/arm/mach-omap2/scrm54xx.h #define OMAP54XX_SCRM_REGADDR(reg) \ reg 22 arch/arm/mach-omap2/scrm54xx.h OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg)) reg 24 arch/arm/mach-omap2/sdrc.h #define OMAP_SDRC_REGADDR(reg) (omap2_sdrc_base + (reg)) reg 25 arch/arm/mach-omap2/sdrc.h #define OMAP_SMS_REGADDR(reg) (omap2_sms_base + (reg)) reg 29 arch/arm/mach-omap2/sdrc.h static inline void sdrc_write_reg(u32 val, u16 reg) reg 31 arch/arm/mach-omap2/sdrc.h writel_relaxed(val, OMAP_SDRC_REGADDR(reg)); reg 34 arch/arm/mach-omap2/sdrc.h static inline u32 sdrc_read_reg(u16 reg) reg 36 arch/arm/mach-omap2/sdrc.h return readl_relaxed(OMAP_SDRC_REGADDR(reg)); reg 41 arch/arm/mach-omap2/sdrc.h static inline void sms_write_reg(u32 val, u16 reg) reg 43 arch/arm/mach-omap2/sdrc.h writel_relaxed(val, OMAP_SMS_REGADDR(reg)); reg 46 arch/arm/mach-omap2/sdrc.h static inline u32 sms_read_reg(u16 reg) reg 48 arch/arm/mach-omap2/sdrc.h return readl_relaxed(OMAP_SMS_REGADDR(reg)); reg 105 arch/arm/mach-omap2/sdrc.h #define OMAP242X_SDRC_REGADDR(reg) \ reg 106 arch/arm/mach-omap2/sdrc.h OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg)) reg 107 arch/arm/mach-omap2/sdrc.h #define OMAP243X_SDRC_REGADDR(reg) \ reg 108 arch/arm/mach-omap2/sdrc.h OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg)) reg 109 arch/arm/mach-omap2/sdrc.h #define OMAP34XX_SDRC_REGADDR(reg) \ reg 110 arch/arm/mach-omap2/sdrc.h OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) reg 196 arch/arm/mach-omap2/sdrc.h #define OMAP242X_SMS_REGADDR(reg) \ reg 197 arch/arm/mach-omap2/sdrc.h (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg) reg 198 arch/arm/mach-omap2/sdrc.h #define OMAP243X_SMS_REGADDR(reg) \ reg 199 arch/arm/mach-omap2/sdrc.h (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg) reg 200 arch/arm/mach-omap2/sdrc.h #define OMAP343X_SMS_REGADDR(reg) \ reg 201 arch/arm/mach-omap2/sdrc.h (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg) reg 616 arch/arm/mach-omap2/timer.c unsigned int reg; reg 653 arch/arm/mach-omap2/timer.c reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP); reg 654 arch/arm/mach-omap2/timer.c if (reg & DRA7_SPEEDSELECT_MASK) { reg 697 arch/arm/mach-omap2/timer.c reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) & reg 699 arch/arm/mach-omap2/timer.c reg |= num; reg 700 arch/arm/mach-omap2/timer.c writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET); reg 702 arch/arm/mach-omap2/timer.c reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & reg 704 arch/arm/mach-omap2/timer.c reg |= den; reg 705 arch/arm/mach-omap2/timer.c writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); reg 68 arch/arm/mach-orion5x/board-mss2.c u32 reg; reg 73 arch/arm/mach-orion5x/board-mss2.c reg = readl(RSTOUTn_MASK); reg 74 arch/arm/mach-orion5x/board-mss2.c reg |= 1 << 2; reg 75 arch/arm/mach-orion5x/board-mss2.c writel(reg, RSTOUTn_MASK); reg 77 arch/arm/mach-orion5x/board-mss2.c reg = readl(CPU_SOFT_RESET); reg 78 arch/arm/mach-orion5x/board-mss2.c reg |= 1; reg 79 arch/arm/mach-orion5x/board-mss2.c writel(reg, CPU_SOFT_RESET); reg 521 arch/arm/mach-orion5x/dns323-setup.c u32 dev, rev, i, reg; reg 546 arch/arm/mach-orion5x/dns323-setup.c reg = readl(ETH_SMI_REG); reg 547 arch/arm/mach-orion5x/dns323-setup.c if (!(reg & SMI_BUSY)) reg 558 arch/arm/mach-orion5x/dns323-setup.c reg = readl(ETH_SMI_REG); reg 559 arch/arm/mach-orion5x/dns323-setup.c if (reg & SMI_READ_VALID) reg 566 arch/arm/mach-orion5x/dns323-setup.c pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff); reg 572 arch/arm/mach-orion5x/dns323-setup.c switch(reg & 0xfff0) { reg 579 arch/arm/mach-orion5x/dns323-setup.c reg & 0xffff); reg 222 arch/arm/mach-orion5x/pci.c #define PCI_CONF_REG(reg) ((reg) & 0xfc) reg 396 arch/arm/mach-orion5x/pci.c int bus_nr, func, reg; reg 401 arch/arm/mach-orion5x/pci.c reg = PCI_CONF_REG_STAT_CMD; reg 402 arch/arm/mach-orion5x/pci.c orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); reg 404 arch/arm/mach-orion5x/pci.c orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); reg 428 arch/arm/mach-orion5x/pci.c u32 reg; reg 434 arch/arm/mach-orion5x/pci.c reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); reg 435 arch/arm/mach-orion5x/pci.c orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); reg 437 arch/arm/mach-orion5x/pci.c orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); reg 442 arch/arm/mach-orion5x/pci.c reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); reg 443 arch/arm/mach-orion5x/pci.c orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); reg 108 arch/arm/mach-prima2/rtciobrg.c static int regmap_iobg_regwrite(void *context, unsigned int reg, reg 111 arch/arm/mach-prima2/rtciobrg.c sirfsoc_rtc_iobrg_writel(val, reg); reg 115 arch/arm/mach-prima2/rtciobrg.c static int regmap_iobg_regread(void *context, unsigned int reg, reg 118 arch/arm/mach-prima2/rtciobrg.c *val = (u32)sirfsoc_rtc_iobrg_readl(reg); reg 220 arch/arm/mach-pxa/idp.c u32 reg = IDP_CPLD_LED_CONTROL; reg 223 arch/arm/mach-pxa/idp.c reg &= ~led->mask; reg 225 arch/arm/mach-pxa/idp.c reg |= led->mask; reg 227 arch/arm/mach-pxa/idp.c IDP_CPLD_LED_CONTROL = reg; reg 79 arch/arm/mach-pxa/include/mach/magician.h #define MAGICIAN_EGPIO(reg,bit) \ reg 80 arch/arm/mach-pxa/include/mach/magician.h (MAGICIAN_EGPIO_BASE + 8*reg + bit) reg 571 arch/arm/mach-pxa/lubbock.c u32 reg = LUB_DISC_BLNK_LED; reg 574 arch/arm/mach-pxa/lubbock.c reg |= led->mask; reg 576 arch/arm/mach-pxa/lubbock.c reg &= ~led->mask; reg 578 arch/arm/mach-pxa/lubbock.c LUB_DISC_BLNK_LED = reg; reg 585 arch/arm/mach-pxa/lubbock.c u32 reg = LUB_DISC_BLNK_LED; reg 587 arch/arm/mach-pxa/lubbock.c return (reg & led->mask) ? LED_FULL : LED_OFF; reg 659 arch/arm/mach-pxa/mainstone.c u32 reg = MST_LEDCTRL; reg 662 arch/arm/mach-pxa/mainstone.c reg |= led->mask; reg 664 arch/arm/mach-pxa/mainstone.c reg &= ~led->mask; reg 666 arch/arm/mach-pxa/mainstone.c MST_LEDCTRL = reg; reg 673 arch/arm/mach-pxa/mainstone.c u32 reg = MST_LEDCTRL; reg 675 arch/arm/mach-pxa/mainstone.c return (reg & led->mask) ? LED_FULL : LED_OFF; reg 69 arch/arm/mach-pxa/pcm990-baseboard.c static u8 pcm990_cpld_readb(unsigned int reg) reg 71 arch/arm/mach-pxa/pcm990-baseboard.c return readb(pcm990_cpld_base + reg); reg 74 arch/arm/mach-pxa/pcm990-baseboard.c static void pcm990_cpld_writeb(u8 value, unsigned int reg) reg 76 arch/arm/mach-pxa/pcm990-baseboard.c writeb(value, pcm990_cpld_base + reg); reg 39 arch/arm/mach-pxa/pxa3xx-ulpi.c static inline u32 u2d_readl(u32 reg) reg 41 arch/arm/mach-pxa/pxa3xx-ulpi.c return __raw_readl(u2d->mmio_base + reg); reg 44 arch/arm/mach-pxa/pxa3xx-ulpi.c static inline void u2d_writel(u32 reg, u32 val) reg 46 arch/arm/mach-pxa/pxa3xx-ulpi.c __raw_writel(val, u2d->mmio_base + reg); reg 79 arch/arm/mach-pxa/pxa3xx-ulpi.c static int pxa310_ulpi_read(struct usb_phy *otg, u32 reg) reg 88 arch/arm/mach-pxa/pxa3xx-ulpi.c u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | U2DOTGUCR_RNW | (reg << 16)); reg 98 arch/arm/mach-pxa/pxa3xx-ulpi.c static int pxa310_ulpi_write(struct usb_phy *otg, u32 val, u32 reg) reg 105 arch/arm/mach-pxa/pxa3xx-ulpi.c u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | (reg << 16) | (val << 8)); reg 81 arch/arm/mach-qcom/platsmp.c void __iomem *reg, *saw_reg; reg 101 arch/arm/mach-qcom/platsmp.c reg = of_iomap(acc_node, 0); reg 102 arch/arm/mach-qcom/platsmp.c if (!reg) { reg 120 arch/arm/mach-qcom/platsmp.c writel_relaxed(val, reg + APCS_CPU_PWR_CTL); reg 122 arch/arm/mach-qcom/platsmp.c writel_relaxed(val, reg + APCS_CPU_PWR_CTL); reg 127 arch/arm/mach-qcom/platsmp.c writel_relaxed(val, reg + APCS_CPU_PWR_CTL); reg 132 arch/arm/mach-qcom/platsmp.c writel_relaxed(val, reg + APCS_CPU_PWR_CTL); reg 137 arch/arm/mach-qcom/platsmp.c writel_relaxed(val, reg + APCS_CPU_PWR_CTL); reg 142 arch/arm/mach-qcom/platsmp.c writel_relaxed(val, reg + APCS_CPU_PWR_CTL); reg 147 arch/arm/mach-qcom/platsmp.c iounmap(reg); reg 159 arch/arm/mach-qcom/platsmp.c void __iomem *reg; reg 187 arch/arm/mach-qcom/platsmp.c reg = of_iomap(acc_node, 0); reg 188 arch/arm/mach-qcom/platsmp.c if (!reg) { reg 201 arch/arm/mach-qcom/platsmp.c writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL); reg 208 arch/arm/mach-qcom/platsmp.c writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL); reg 215 arch/arm/mach-qcom/platsmp.c writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL); reg 223 arch/arm/mach-qcom/platsmp.c writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); reg 228 arch/arm/mach-qcom/platsmp.c writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); reg 233 arch/arm/mach-qcom/platsmp.c writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); reg 237 arch/arm/mach-qcom/platsmp.c writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL); reg 244 arch/arm/mach-qcom/platsmp.c iounmap(reg); reg 71 arch/arm/mach-rockchip/pm.c u32 reg, i; reg 79 arch/arm/mach-rockchip/pm.c regmap_read(grf_regmap, reg_offset[i], ®); reg 80 arch/arm/mach-rockchip/pm.c if (!(reg & GRF_SIDDQ)) reg 196 arch/arm/mach-s3c24xx/iotiming-s3c2412.c static inline unsigned int s3c2412_decode_timing(unsigned int clock, u32 reg) reg 198 arch/arm/mach-s3c24xx/iotiming-s3c2412.c return (reg & 0xf) * clock; reg 286 arch/arm/mach-s3c64xx/common.c void __iomem *reg; reg 292 arch/arm/mach-s3c64xx/common.c reg = S3C64XX_EINT0CON0; reg 294 arch/arm/mach-s3c64xx/common.c reg = S3C64XX_EINT0CON1; reg 332 arch/arm/mach-s3c64xx/common.c ctrl = __raw_readl(reg); reg 335 arch/arm/mach-s3c64xx/common.c __raw_writel(ctrl, reg); reg 17 arch/arm/mach-s3c64xx/include/mach/regs-gpio.h #define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GPIO + (reg)) reg 20 arch/arm/mach-s3c64xx/setup-ide.c u32 reg; reg 22 arch/arm/mach-s3c64xx/setup-ide.c reg = readl(S3C_MEM_SYS_CFG) & (~0x3f); reg 25 arch/arm/mach-s3c64xx/setup-ide.c writel(reg | MEM_SYS_CFG_INDEP_CF | reg 25 arch/arm/mach-s5pv210/s5pv210.c const __be32 *reg; reg 31 arch/arm/mach-s5pv210/s5pv210.c reg = of_get_flat_dt_prop(node, "reg", &len); reg 32 arch/arm/mach-s5pv210/s5pv210.c if (reg == NULL || len != (sizeof(unsigned long) * 2)) reg 35 arch/arm/mach-s5pv210/s5pv210.c iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0])); reg 36 arch/arm/mach-s5pv210/s5pv210.c iodesc.length = be32_to_cpu(reg[1]) - 1; reg 88 arch/arm/mach-sa1100/assabet.c static int __init assabet_init_gpio(void __iomem *reg, u32 def_val) reg 92 arch/arm/mach-sa1100/assabet.c writel_relaxed(def_val, reg); reg 94 arch/arm/mach-sa1100/assabet.c gc = gpio_reg_init(NULL, reg, -1, 32, "assabet", 0xff000000, def_val, reg 171 arch/arm/mach-sa1100/assabet.c static void adv7171_write(unsigned reg, unsigned val) reg 188 arch/arm/mach-sa1100/assabet.c adv7171_send(reg); reg 206 arch/arm/mach-sa1100/neponset.c struct device *dev, const char *label, void __iomem *reg, reg 211 arch/arm/mach-sa1100/neponset.c gc = gpio_reg_init(dev, reg, -1, num, label, in ? 0xffffffff : 0, reg 212 arch/arm/mach-sa1100/neponset.c readl_relaxed(reg), names, NULL, NULL); reg 29 arch/arm/mach-shmobile/setup-r8a7740.c void __iomem *reg; reg 31 arch/arm/mach-shmobile/setup-r8a7740.c reg = ioremap_nocache(MEBUFCNTR, 4); reg 32 arch/arm/mach-shmobile/setup-r8a7740.c if (reg) { reg 33 arch/arm/mach-shmobile/setup-r8a7740.c iowrite32(0x01600164, reg); reg 34 arch/arm/mach-shmobile/setup-r8a7740.c iounmap(reg); reg 135 arch/arm/mach-shmobile/setup-rcar-gen2.c const __be32 *reg, *endp; reg 144 arch/arm/mach-shmobile/setup-rcar-gen2.c reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l); reg 145 arch/arm/mach-shmobile/setup-rcar-gen2.c if (reg == NULL) reg 146 arch/arm/mach-shmobile/setup-rcar-gen2.c reg = of_get_flat_dt_prop(node, "reg", &l); reg 147 arch/arm/mach-shmobile/setup-rcar-gen2.c if (reg == NULL) reg 150 arch/arm/mach-shmobile/setup-rcar-gen2.c endp = reg + (l / sizeof(__be32)); reg 151 arch/arm/mach-shmobile/setup-rcar-gen2.c while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) { reg 154 arch/arm/mach-shmobile/setup-rcar-gen2.c base = dt_mem_next_cell(dt_root_addr_cells, ®); reg 155 arch/arm/mach-shmobile/setup-rcar-gen2.c size = dt_mem_next_cell(dt_root_size_cells, ®); reg 23 arch/arm/mach-sti/board-dt.c static void sti_l2_write_sec(unsigned long val, unsigned reg) reg 119 arch/arm/mach-sunxi/mc_smp.c u32 reg; reg 122 arch/arm/mach-sunxi/mc_smp.c reg = readl(prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); reg 124 arch/arm/mach-sunxi/mc_smp.c if (reg == 0x00) { reg 161 arch/arm/mach-sunxi/mc_smp.c u32 reg; reg 172 arch/arm/mach-sunxi/mc_smp.c reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); reg 173 arch/arm/mach-sunxi/mc_smp.c reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu); reg 174 arch/arm/mach-sunxi/mc_smp.c writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); reg 178 arch/arm/mach-sunxi/mc_smp.c reg = readl(r_cpucfg_base + reg 180 arch/arm/mach-sunxi/mc_smp.c reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu)); reg 181 arch/arm/mach-sunxi/mc_smp.c writel(reg, r_cpucfg_base + reg 188 arch/arm/mach-sunxi/mc_smp.c reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster)); reg 189 arch/arm/mach-sunxi/mc_smp.c reg &= ~CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE(cpu); reg 190 arch/arm/mach-sunxi/mc_smp.c writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster)); reg 194 arch/arm/mach-sunxi/mc_smp.c reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); reg 195 arch/arm/mach-sunxi/mc_smp.c reg &= ~CPUCFG_CX_RST_CTRL_DBG_RST(cpu); reg 202 arch/arm/mach-sunxi/mc_smp.c reg &= ~CPUCFG_CX_RST_CTRL_ETM_RST(cpu); reg 204 arch/arm/mach-sunxi/mc_smp.c writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); reg 216 arch/arm/mach-sunxi/mc_smp.c reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster)); reg 217 arch/arm/mach-sunxi/mc_smp.c reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu); reg 218 arch/arm/mach-sunxi/mc_smp.c writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster)); reg 228 arch/arm/mach-sunxi/mc_smp.c reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); reg 229 arch/arm/mach-sunxi/mc_smp.c reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu); reg 230 arch/arm/mach-sunxi/mc_smp.c writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); reg 233 arch/arm/mach-sunxi/mc_smp.c reg = readl(r_cpucfg_base + reg 235 arch/arm/mach-sunxi/mc_smp.c reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu); reg 236 arch/arm/mach-sunxi/mc_smp.c writel(reg, r_cpucfg_base + reg 242 arch/arm/mach-sunxi/mc_smp.c reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); reg 243 arch/arm/mach-sunxi/mc_smp.c reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu); reg 244 arch/arm/mach-sunxi/mc_smp.c reg |= CPUCFG_CX_RST_CTRL_CORE_RST(cpu); reg 246 arch/arm/mach-sunxi/mc_smp.c reg |= CPUCFG_CX_RST_CTRL_ETM_RST(cpu); reg 248 arch/arm/mach-sunxi/mc_smp.c reg |= CPUCFG_CX_RST_CTRL_CX_RST(cpu); /* NEON */ reg 249 arch/arm/mach-sunxi/mc_smp.c writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); reg 256 arch/arm/mach-sunxi/mc_smp.c u32 reg; reg 264 arch/arm/mach-sunxi/mc_smp.c reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); reg 265 arch/arm/mach-sunxi/mc_smp.c reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL; /* Core Reset */ reg 266 arch/arm/mach-sunxi/mc_smp.c writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); reg 271 arch/arm/mach-sunxi/mc_smp.c reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); reg 272 arch/arm/mach-sunxi/mc_smp.c reg |= CPUCFG_CX_CTRL_REG1_ACINACTM; reg 273 arch/arm/mach-sunxi/mc_smp.c writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); reg 276 arch/arm/mach-sunxi/mc_smp.c reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); reg 277 arch/arm/mach-sunxi/mc_smp.c reg &= ~PRCM_CPU_PO_RST_CTRL_CORE_ALL; reg 278 arch/arm/mach-sunxi/mc_smp.c writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); reg 282 arch/arm/mach-sunxi/mc_smp.c reg = readl(r_cpucfg_base + reg 284 arch/arm/mach-sunxi/mc_smp.c reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL; reg 285 arch/arm/mach-sunxi/mc_smp.c writel(reg, r_cpucfg_base + reg 291 arch/arm/mach-sunxi/mc_smp.c reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); reg 292 arch/arm/mach-sunxi/mc_smp.c reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST; reg 293 arch/arm/mach-sunxi/mc_smp.c reg &= ~CPUCFG_CX_RST_CTRL_DBG_RST_ALL; reg 294 arch/arm/mach-sunxi/mc_smp.c reg &= ~CPUCFG_CX_RST_CTRL_H_RST; reg 295 arch/arm/mach-sunxi/mc_smp.c reg &= ~CPUCFG_CX_RST_CTRL_L2_RST; reg 302 arch/arm/mach-sunxi/mc_smp.c reg &= ~CPUCFG_CX_RST_CTRL_ETM_RST_ALL; reg 304 arch/arm/mach-sunxi/mc_smp.c writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); reg 307 arch/arm/mach-sunxi/mc_smp.c reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster)); reg 310 arch/arm/mach-sunxi/mc_smp.c reg &= ~CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A15; reg 313 arch/arm/mach-sunxi/mc_smp.c reg &= ~CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE_ALL; reg 314 arch/arm/mach-sunxi/mc_smp.c reg &= ~CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A7; reg 316 arch/arm/mach-sunxi/mc_smp.c writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster)); reg 319 arch/arm/mach-sunxi/mc_smp.c reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster)); reg 321 arch/arm/mach-sunxi/mc_smp.c reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I; reg 323 arch/arm/mach-sunxi/mc_smp.c reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I; reg 324 arch/arm/mach-sunxi/mc_smp.c writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster)); reg 328 arch/arm/mach-sunxi/mc_smp.c reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); reg 329 arch/arm/mach-sunxi/mc_smp.c reg |= CPUCFG_CX_RST_CTRL_DBG_SOC_RST; reg 330 arch/arm/mach-sunxi/mc_smp.c reg |= CPUCFG_CX_RST_CTRL_H_RST; reg 331 arch/arm/mach-sunxi/mc_smp.c reg |= CPUCFG_CX_RST_CTRL_L2_RST; reg 332 arch/arm/mach-sunxi/mc_smp.c writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); reg 335 arch/arm/mach-sunxi/mc_smp.c reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); reg 336 arch/arm/mach-sunxi/mc_smp.c reg &= ~CPUCFG_CX_CTRL_REG1_ACINACTM; reg 337 arch/arm/mach-sunxi/mc_smp.c writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); reg 432 arch/arm/mach-sunxi/mc_smp.c u32 reg; reg 439 arch/arm/mach-sunxi/mc_smp.c reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); reg 440 arch/arm/mach-sunxi/mc_smp.c reg |= CPUCFG_CX_CTRL_REG1_ACINACTM; reg 441 arch/arm/mach-sunxi/mc_smp.c writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); reg 483 arch/arm/mach-sunxi/mc_smp.c u32 reg; reg 494 arch/arm/mach-sunxi/mc_smp.c reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster)); reg 495 arch/arm/mach-sunxi/mc_smp.c reg |= PRCM_PWROFF_GATING_REG_CORE(gating_bit); reg 496 arch/arm/mach-sunxi/mc_smp.c writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster)); reg 507 arch/arm/mach-sunxi/mc_smp.c u32 reg; reg 515 arch/arm/mach-sunxi/mc_smp.c reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); reg 516 arch/arm/mach-sunxi/mc_smp.c reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST; reg 517 arch/arm/mach-sunxi/mc_smp.c reg &= ~CPUCFG_CX_RST_CTRL_H_RST; reg 518 arch/arm/mach-sunxi/mc_smp.c reg &= ~CPUCFG_CX_RST_CTRL_L2_RST; reg 519 arch/arm/mach-sunxi/mc_smp.c writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); reg 523 arch/arm/mach-sunxi/mc_smp.c reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster)); reg 525 arch/arm/mach-sunxi/mc_smp.c reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I; reg 527 arch/arm/mach-sunxi/mc_smp.c reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I; reg 528 arch/arm/mach-sunxi/mc_smp.c writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster)); reg 539 arch/arm/mach-sunxi/mc_smp.c u32 reg; reg 568 arch/arm/mach-sunxi/mc_smp.c reg = readl(cpucfg_base + CPUCFG_CX_STATUS(cluster)); reg 569 arch/arm/mach-sunxi/mc_smp.c if (reg & CPUCFG_CX_STATUS_STANDBYWFI(cpu)) reg 585 arch/arm/mach-sunxi/mc_smp.c ret = readl_poll_timeout(cpucfg_base + CPUCFG_CX_STATUS(cluster), reg, reg 586 arch/arm/mach-sunxi/mc_smp.c reg & CPUCFG_CX_STATUS_STANDBYWFIL2, reg 76 arch/arm/mach-sunxi/platsmp.c u32 reg; reg 92 arch/arm/mach-sunxi/platsmp.c reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG); reg 93 arch/arm/mach-sunxi/platsmp.c writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG); reg 96 arch/arm/mach-sunxi/platsmp.c reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG); reg 97 arch/arm/mach-sunxi/platsmp.c writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); reg 105 arch/arm/mach-sunxi/platsmp.c reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG); reg 106 arch/arm/mach-sunxi/platsmp.c writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG); reg 113 arch/arm/mach-sunxi/platsmp.c reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG); reg 114 arch/arm/mach-sunxi/platsmp.c writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); reg 161 arch/arm/mach-sunxi/platsmp.c u32 reg; reg 176 arch/arm/mach-sunxi/platsmp.c reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG); reg 177 arch/arm/mach-sunxi/platsmp.c writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG); reg 180 arch/arm/mach-sunxi/platsmp.c reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG); reg 181 arch/arm/mach-sunxi/platsmp.c writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG); reg 7 arch/arm/mach-tango/setup.c static void tango_l2c_write(unsigned long val, unsigned int reg) reg 9 arch/arm/mach-tango/setup.c if (reg == L2X0_CTRL) reg 36 arch/arm/mach-tegra/reset.c u32 reg; reg 44 arch/arm/mach-tegra/reset.c reg = readl(evp_cpu_reset); reg 50 arch/arm/mach-tegra/reset.c reg = readl(sb_ctrl); reg 51 arch/arm/mach-tegra/reset.c reg |= 2; reg 52 arch/arm/mach-tegra/reset.c writel(reg, sb_ctrl); reg 75 arch/arm/mach-tegra/sleep.h .macro mov32, reg, val reg 61 arch/arm/mach-ux500/cpu-db8500.c static void ux500_l2c310_write_sec(unsigned long val, unsigned reg) reg 135 arch/arm/mach-vexpress/spc.c u32 reg; reg 137 arch/arm/mach-vexpress/spc.c reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK); reg 140 arch/arm/mach-vexpress/spc.c reg |= GBL_WAKEUP_INT_MSK; reg 142 arch/arm/mach-vexpress/spc.c reg &= ~GBL_WAKEUP_INT_MSK; reg 144 arch/arm/mach-vexpress/spc.c writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK); reg 160 arch/arm/mach-vexpress/spc.c u32 mask, reg; reg 170 arch/arm/mach-vexpress/spc.c reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK); reg 173 arch/arm/mach-vexpress/spc.c reg |= mask; reg 175 arch/arm/mach-vexpress/spc.c reg &= ~mask; reg 177 arch/arm/mach-vexpress/spc.c writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK); reg 56 arch/arm/mach-zynq/pm.c u32 reg; reg 67 arch/arm/mach-zynq/pm.c reg = readl(ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS); reg 68 arch/arm/mach-zynq/pm.c reg |= DDRC_CLOCKSTOP_MASK; reg 69 arch/arm/mach-zynq/pm.c writel(reg, ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS); reg 124 arch/arm/mach-zynq/slcr.c u32 reg; reg 126 arch/arm/mach-zynq/slcr.c zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET); reg 127 arch/arm/mach-zynq/slcr.c reg &= ~(SLCR_A9_CPU_RST << cpu); reg 128 arch/arm/mach-zynq/slcr.c zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); reg 129 arch/arm/mach-zynq/slcr.c reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu); reg 130 arch/arm/mach-zynq/slcr.c zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); reg 141 arch/arm/mach-zynq/slcr.c u32 reg; reg 143 arch/arm/mach-zynq/slcr.c zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET); reg 144 arch/arm/mach-zynq/slcr.c reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu; reg 145 arch/arm/mach-zynq/slcr.c zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); reg 72 arch/arm/mm/cache-b15-rac.c u32 reg; reg 81 arch/arm/mm/cache-b15-rac.c reg = __raw_readl(b15_rac_base + rac_flush_offset); reg 82 arch/arm/mm/cache-b15-rac.c } while (reg & FLUSH_RAC); reg 87 arch/arm/mm/cache-b15-rac.c u32 reg; reg 89 arch/arm/mm/cache-b15-rac.c reg = __b15_rac_disable(); reg 91 arch/arm/mm/cache-b15-rac.c return reg; reg 293 arch/arm/mm/cache-b15-rac.c u32 reg, en_mask = 0; reg 352 arch/arm/mm/cache-b15-rac.c reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG); reg 355 arch/arm/mm/cache-b15-rac.c WARN(reg & en_mask, "Read-ahead cache not previously disabled\n"); reg 54 arch/arm/mm/cache-l2x0.c static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask) reg 57 arch/arm/mm/cache-l2x0.c while (readl_relaxed(reg) & mask) reg 65 arch/arm/mm/cache-l2x0.c static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg) reg 67 arch/arm/mm/cache-l2x0.c if (val == readl_relaxed(base + reg)) reg 70 arch/arm/mm/cache-l2x0.c outer_cache.write_sec(val, reg); reg 72 arch/arm/mm/cache-l2x0.c writel_relaxed(val, base + reg); reg 85 arch/arm/mm/cache-l2x0.c static void __l2c_op_way(void __iomem *reg) reg 87 arch/arm/mm/cache-l2x0.c writel_relaxed(l2x0_way_mask, reg); reg 88 arch/arm/mm/cache-l2x0.c l2c_wait_mask(reg, l2x0_way_mask); reg 178 arch/arm/mm/cache-l2x0.c static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start, reg 182 arch/arm/mm/cache-l2x0.c writel_relaxed(start, reg); reg 274 arch/arm/mm/cache-l2x0.c static void l2c220_op_way(void __iomem *base, unsigned reg) reg 279 arch/arm/mm/cache-l2x0.c __l2c_op_way(base + reg); reg 284 arch/arm/mm/cache-l2x0.c static unsigned long l2c220_op_pa_range(void __iomem *reg, unsigned long start, reg 293 arch/arm/mm/cache-l2x0.c l2c_wait_mask(reg, 1); reg 294 arch/arm/mm/cache-l2x0.c writel_relaxed(start, reg); reg 124 arch/arm/mm/init.c struct memblock_region *reg; reg 146 arch/arm/mm/init.c for_each_memblock(memory, reg) { reg 147 arch/arm/mm/init.c unsigned long start = memblock_region_memory_base_pfn(reg); reg 148 arch/arm/mm/init.c unsigned long end = memblock_region_memory_end_pfn(reg); reg 359 arch/arm/mm/init.c struct memblock_region *reg; reg 365 arch/arm/mm/init.c for_each_memblock(memory, reg) { reg 366 arch/arm/mm/init.c start = memblock_region_memory_base_pfn(reg); reg 395 arch/arm/mm/init.c prev_end = ALIGN(memblock_region_memory_end_pfn(reg), reg 1168 arch/arm/mm/mmu.c struct memblock_region *reg; reg 1184 arch/arm/mm/mmu.c for_each_memblock(memory, reg) { reg 1185 arch/arm/mm/mmu.c if (!memblock_is_nomap(reg)) { reg 1186 arch/arm/mm/mmu.c if (!IS_ALIGNED(reg->base, PMD_SIZE)) { reg 1189 arch/arm/mm/mmu.c len = round_up(reg->base, PMD_SIZE) - reg->base; reg 1190 arch/arm/mm/mmu.c memblock_mark_nomap(reg->base, len); reg 1196 arch/arm/mm/mmu.c for_each_memblock(memory, reg) { reg 1197 arch/arm/mm/mmu.c phys_addr_t block_start = reg->base; reg 1198 arch/arm/mm/mmu.c phys_addr_t block_end = reg->base + reg->size; reg 1200 arch/arm/mm/mmu.c if (memblock_is_nomap(reg)) reg 1203 arch/arm/mm/mmu.c if (reg->base < vmalloc_limit) { reg 1452 arch/arm/mm/mmu.c struct memblock_region *reg; reg 1457 arch/arm/mm/mmu.c for_each_memblock(memory, reg) { reg 1458 arch/arm/mm/mmu.c phys_addr_t start = reg->base; reg 1459 arch/arm/mm/mmu.c phys_addr_t end = start + reg->size; reg 1462 arch/arm/mm/mmu.c if (memblock_is_nomap(reg)) reg 37 arch/arm/mm/nommu.c unsigned long reg = get_cr(); reg 39 arch/arm/mm/nommu.c set_cr(reg | CR_V); reg 64 arch/arm/mm/nommu.c unsigned long base = 0, reg = get_cr(); reg 66 arch/arm/mm/nommu.c set_cr(reg & ~CR_V); reg 234 arch/arm/mm/pmsa-v7.c struct memblock_region *reg; reg 265 arch/arm/mm/pmsa-v7.c for_each_memblock(memory, reg) { reg 272 arch/arm/mm/pmsa-v7.c if (reg->base != phys_offset) reg 275 arch/arm/mm/pmsa-v7.c mem_start = reg->base; reg 276 arch/arm/mm/pmsa-v7.c mem_end = reg->base + reg->size; reg 277 arch/arm/mm/pmsa-v7.c specified_mem_size = reg->size; reg 286 arch/arm/mm/pmsa-v7.c &mem_end, ®->base); reg 287 arch/arm/mm/pmsa-v7.c memblock_remove(reg->base, 0 - reg->base); reg 97 arch/arm/mm/pmsa-v8.c struct memblock_region *reg; reg 100 arch/arm/mm/pmsa-v8.c for_each_memblock(memory, reg) { reg 107 arch/arm/mm/pmsa-v8.c if (reg->base != phys_offset) reg 109 arch/arm/mm/pmsa-v8.c mem_end = reg->base + reg->size; reg 118 arch/arm/mm/pmsa-v8.c &mem_end, ®->base); reg 119 arch/arm/mm/pmsa-v8.c memblock_remove(reg->base, 0 - reg->base); reg 515 arch/arm/net/bpf_jit_32.c static bool is_stacked(s8 reg) reg 517 arch/arm/net/bpf_jit_32.c return reg < 0; reg 524 arch/arm/net/bpf_jit_32.c static s8 arm_bpf_get_reg32(s8 reg, s8 tmp, struct jit_ctx *ctx) reg 526 arch/arm/net/bpf_jit_32.c if (is_stacked(reg)) { reg 527 arch/arm/net/bpf_jit_32.c emit(ARM_LDR_I(tmp, ARM_FP, EBPF_SCRATCH_TO_ARM_FP(reg)), ctx); reg 528 arch/arm/net/bpf_jit_32.c reg = tmp; reg 530 arch/arm/net/bpf_jit_32.c return reg; reg 533 arch/arm/net/bpf_jit_32.c static const s8 *arm_bpf_get_reg64(const s8 *reg, const s8 *tmp, reg 536 arch/arm/net/bpf_jit_32.c if (is_stacked(reg[1])) { reg 540 arch/arm/net/bpf_jit_32.c EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx); reg 543 arch/arm/net/bpf_jit_32.c EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx); reg 545 arch/arm/net/bpf_jit_32.c EBPF_SCRATCH_TO_ARM_FP(reg[0])), ctx); reg 547 arch/arm/net/bpf_jit_32.c reg = tmp; reg 549 arch/arm/net/bpf_jit_32.c return reg; reg 556 arch/arm/net/bpf_jit_32.c static void arm_bpf_put_reg32(s8 reg, s8 src, struct jit_ctx *ctx) reg 558 arch/arm/net/bpf_jit_32.c if (is_stacked(reg)) reg 559 arch/arm/net/bpf_jit_32.c emit(ARM_STR_I(src, ARM_FP, EBPF_SCRATCH_TO_ARM_FP(reg)), ctx); reg 560 arch/arm/net/bpf_jit_32.c else if (reg != src) reg 561 arch/arm/net/bpf_jit_32.c emit(ARM_MOV_R(reg, src), ctx); reg 564 arch/arm/net/bpf_jit_32.c static void arm_bpf_put_reg64(const s8 *reg, const s8 *src, reg 567 arch/arm/net/bpf_jit_32.c if (is_stacked(reg[1])) { reg 571 arch/arm/net/bpf_jit_32.c EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx); reg 574 arch/arm/net/bpf_jit_32.c EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx); reg 576 arch/arm/net/bpf_jit_32.c EBPF_SCRATCH_TO_ARM_FP(reg[0])), ctx); reg 579 arch/arm/net/bpf_jit_32.c if (reg[1] != src[1]) reg 580 arch/arm/net/bpf_jit_32.c emit(ARM_MOV_R(reg[1], src[1]), ctx); reg 581 arch/arm/net/bpf_jit_32.c if (reg[0] != src[0]) reg 582 arch/arm/net/bpf_jit_32.c emit(ARM_MOV_R(reg[0], src[0]), ctx); reg 83 arch/arm/plat-omap/debug-leds.c u16 reg; reg 85 arch/arm/plat-omap/debug-leds.c reg = readw_relaxed(&fpga->leds); reg 87 arch/arm/plat-omap/debug-leds.c reg |= led->mask; reg 89 arch/arm/plat-omap/debug-leds.c reg &= ~led->mask; reg 90 arch/arm/plat-omap/debug-leds.c writew_relaxed(reg, &fpga->leds); reg 96 arch/arm/plat-omap/debug-leds.c u16 reg; reg 98 arch/arm/plat-omap/debug-leds.c reg = readw_relaxed(&fpga->leds); reg 99 arch/arm/plat-omap/debug-leds.c return (reg & led->mask) ? LED_FULL : LED_OFF; reg 156 arch/arm/plat-omap/dma.c u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; reg 160 arch/arm/plat-omap/dma.c l = omap_readl(reg); reg 163 arch/arm/plat-omap/dma.c omap_writel(l, reg); reg 167 arch/arm/plat-omap/dma.c #define omap_readl(reg) 0 reg 168 arch/arm/plat-omap/dma.c #define omap_writel(val, reg) do {} while (0) reg 174 arch/arm/plat-omap/dma.c unsigned long reg; reg 180 arch/arm/plat-omap/dma.c reg = OMAP_TC_OCPT1_PRIOR; reg 183 arch/arm/plat-omap/dma.c reg = OMAP_TC_OCPT2_PRIOR; reg 186 arch/arm/plat-omap/dma.c reg = OMAP_TC_EMIFF_PRIOR; reg 189 arch/arm/plat-omap/dma.c reg = OMAP_TC_EMIFS_PRIOR; reg 195 arch/arm/plat-omap/dma.c l = omap_readl(reg); reg 198 arch/arm/plat-omap/dma.c omap_writel(l, reg); reg 727 arch/arm/plat-omap/dma.c u32 reg; reg 739 arch/arm/plat-omap/dma.c reg = 0xff & max_fifo_depth; reg 740 arch/arm/plat-omap/dma.c reg |= (0x3 & tparams) << 12; reg 741 arch/arm/plat-omap/dma.c reg |= (arb_rate & 0xff) << 16; reg 743 arch/arm/plat-omap/dma.c p->dma_write(reg, GCR, 0); reg 94 arch/arm/plat-orion/pcie.c u32 reg; reg 103 arch/arm/plat-orion/pcie.c reg = readl(base + PCIE_DEBUG_CTRL); reg 104 arch/arm/plat-orion/pcie.c reg |= PCIE_DEBUG_SOFT_RESET; reg 105 arch/arm/plat-orion/pcie.c writel(reg, base + PCIE_DEBUG_CTRL); reg 114 arch/arm/plat-orion/pcie.c reg &= ~(PCIE_DEBUG_SOFT_RESET); reg 115 arch/arm/plat-orion/pcie.c writel(reg, base + PCIE_DEBUG_CTRL); reg 43 arch/arm/plat-samsung/gpio-samsung.c void __iomem *reg = chip->base + 0x08; reg 47 arch/arm/plat-samsung/gpio-samsung.c pup = __raw_readl(reg); reg 50 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(pup, reg); reg 58 arch/arm/plat-samsung/gpio-samsung.c void __iomem *reg = chip->base + 0x08; reg 60 arch/arm/plat-samsung/gpio-samsung.c u32 pup = __raw_readl(reg); reg 112 arch/arm/plat-samsung/gpio-samsung.c void __iomem *reg = chip->base + 0x08; reg 113 arch/arm/plat-samsung/gpio-samsung.c u32 pup = __raw_readl(reg); reg 122 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(pup, reg); reg 130 arch/arm/plat-samsung/gpio-samsung.c void __iomem *reg = chip->base + 0x08; reg 131 arch/arm/plat-samsung/gpio-samsung.c u32 pup = __raw_readl(reg); reg 178 arch/arm/plat-samsung/gpio-samsung.c void __iomem *reg = chip->base; reg 190 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(reg); reg 193 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(con, reg); reg 241 arch/arm/plat-samsung/gpio-samsung.c void __iomem *reg = chip->base; reg 246 arch/arm/plat-samsung/gpio-samsung.c reg -= 4; reg 253 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(reg); reg 256 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(con, reg); reg 276 arch/arm/plat-samsung/gpio-samsung.c void __iomem *reg = chip->base; reg 281 arch/arm/plat-samsung/gpio-samsung.c reg -= 4; reg 283 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(reg); reg 306 arch/arm/plat-samsung/gpio-samsung.c void __iomem *reg = chip->base; reg 321 arch/arm/plat-samsung/gpio-samsung.c con = __raw_readl(reg); reg 324 arch/arm/plat-samsung/gpio-samsung.c __raw_writel(con, reg); reg 26 arch/arm/plat-samsung/include/plat/pm-common.h void __iomem *reg; reg 31 arch/arm/plat-samsung/include/plat/pm-common.h { .reg = (x) } reg 35 arch/arm/plat-samsung/include/plat/wakeup-mask.h extern void samsung_sync_wakemask(void __iomem *reg, reg 30 arch/arm/plat-samsung/pm-common.c ptr->val = readl_relaxed(ptr->reg); reg 31 arch/arm/plat-samsung/pm-common.c S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val); reg 50 arch/arm/plat-samsung/pm-common.c ptr->reg, ptr->val, readl_relaxed(ptr->reg)); reg 52 arch/arm/plat-samsung/pm-common.c writel_relaxed(ptr->val, ptr->reg); reg 70 arch/arm/plat-samsung/pm-common.c writel_relaxed(ptr->val, ptr->reg); reg 17 arch/arm/plat-samsung/wakeup-mask.c void samsung_sync_wakemask(void __iomem *reg, reg 23 arch/arm/plat-samsung/wakeup-mask.c val = __raw_readl(reg); reg 40 arch/arm/plat-samsung/wakeup-mask.c printk(KERN_INFO "wakemask %08x => %08x\n", __raw_readl(reg), val); reg 41 arch/arm/plat-samsung/wakeup-mask.c __raw_writel(val, reg); reg 24 arch/arm/plat-versatile/sched-clock.c void __init versatile_sched_clock_init(void __iomem *reg, unsigned long rate) reg 26 arch/arm/plat-versatile/sched-clock.c ctr = reg; reg 62 arch/arm/probes/kprobes/actions-arm.c #define BLX(reg) "blx "reg" \n\t" reg 64 arch/arm/probes/kprobes/actions-arm.c #define BLX(reg) "mov lr, pc \n\t" \ reg 65 arch/arm/probes/kprobes/actions-arm.c "mov pc, "reg" \n\t" reg 44 arch/arm/probes/kprobes/actions-common.c int reg = __ffs(reg_bit_vector); reg 47 arch/arm/probes/kprobes/actions-common.c regs->uregs[reg] = *addr++; reg 49 arch/arm/probes/kprobes/actions-common.c *addr++ = regs->uregs[reg]; reg 19 arch/arm/probes/kprobes/test-arm.c #define TEST_ARM_TO_THUMB_INTERWORK_R(code1, reg, val, code2) \ reg 20 arch/arm/probes/kprobes/test-arm.c TESTCASE_START(code1 #reg code2) \ reg 21 arch/arm/probes/kprobes/test-arm.c TEST_ARG_REG(reg, val) \ reg 25 arch/arm/probes/kprobes/test-arm.c "1: "code1 #reg code2" \n\t" \ reg 34 arch/arm/probes/kprobes/test-arm.c #define TEST_ARM_TO_THUMB_INTERWORK_P(code1, reg, val, code2) \ reg 35 arch/arm/probes/kprobes/test-arm.c TESTCASE_START(code1 #reg code2) \ reg 36 arch/arm/probes/kprobes/test-arm.c TEST_ARG_PTR(reg, val) \ reg 41 arch/arm/probes/kprobes/test-arm.c "1: "code1 #reg code2" \n\t" \ reg 236 arch/arm/probes/kprobes/test-core.c #define RET(reg) "mov pc, "#reg reg 255 arch/arm/probes/kprobes/test-core.c #define RET(reg) "bx "#reg reg 781 arch/arm/probes/kprobes/test-core.c int reg = (insn >> i) & 0xf; reg 787 arch/arm/probes/kprobes/test-core.c if (reg == 13) reg 789 arch/arm/probes/kprobes/test-core.c else if (reg == 15) reg 803 arch/arm/probes/kprobes/test-core.c if (reg != 13) reg 808 arch/arm/probes/kprobes/test-core.c if (reg != 15) reg 813 arch/arm/probes/kprobes/test-core.c if (reg == 13) reg 819 arch/arm/probes/kprobes/test-core.c if (reg == 13 || reg == 15) reg 826 arch/arm/probes/kprobes/test-core.c if (reg == 15) { reg 834 arch/arm/probes/kprobes/test-core.c if (reg == 15) reg 1132 arch/arm/probes/kprobes/test-core.c regs->uregs[arg->reg] = arg->val; reg 1138 arch/arm/probes/kprobes/test-core.c regs->uregs[arg->reg] = reg 1146 arch/arm/probes/kprobes/test-core.c if (arg->reg == 13) reg 1229 arch/arm/probes/kprobes/test-core.c result_regs.uregs[arg->reg] &= arg->val; reg 63 arch/arm/probes/kprobes/test-core.h u8 reg; reg 121 arch/arm/probes/kprobes/test-core.h #define TEST_ARG_REG(reg, val) \ reg 123 arch/arm/probes/kprobes/test-core.h ".byte "#reg" \n\t" \ reg 127 arch/arm/probes/kprobes/test-core.h #define TEST_ARG_PTR(reg, val) \ reg 129 arch/arm/probes/kprobes/test-core.h ".byte "#reg" \n\t" \ reg 139 arch/arm/probes/kprobes/test-core.h #define TEST_ARG_REG_MASKED(reg, val) \ reg 141 arch/arm/probes/kprobes/test-core.h ".byte "#reg" \n\t" \ reg 231 arch/arm/probes/kprobes/test-core.h #define TEST_R(code1, reg, val, code2) \ reg 232 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg code2) \ reg 233 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg, val) \ reg 235 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg code2) \ reg 334 arch/arm/probes/kprobes/test-core.h #define TEST_BF_R(code1, reg, val, code2) \ reg 335 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg code2) \ reg 336 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg, val) \ reg 338 arch/arm/probes/kprobes/test-core.h TEST_BRANCH_F(code1 #reg code2) \ reg 341 arch/arm/probes/kprobes/test-core.h #define TEST_BB_R(code1, reg, val, code2) \ reg 342 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg code2) \ reg 343 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg, val) \ reg 345 arch/arm/probes/kprobes/test-core.h TEST_BRANCH_B(code1 #reg code2) \ reg 368 arch/arm/probes/kprobes/test-core.h #define TEST_BF_RX(code1, reg, val, code2, codex) \ reg 369 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg code2) \ reg 370 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg, val) \ reg 372 arch/arm/probes/kprobes/test-core.h TEST_BRANCH_FX(code1 #reg code2, codex) \ reg 383 arch/arm/probes/kprobes/test-core.h #define TEST_RX(code1, reg, val, code2, codex) \ reg 384 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg code2) \ reg 385 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg, val) \ reg 387 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 __stringify(reg) code2) \ reg 402 arch/arm/probes/kprobes/test-core.h #define TEST_RMASKED(code1, reg, mask, code2) \ reg 403 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg code2) \ reg 404 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG_MASKED(reg, mask) \ reg 406 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg code2) \ reg 41 arch/arm/probes/kprobes/test-thumb.c #define TEST_THUMB_TO_ARM_INTERWORK_P(code1, reg, val, code2) \ reg 42 arch/arm/probes/kprobes/test-thumb.c TESTCASE_START(code1 #reg code2) \ reg 43 arch/arm/probes/kprobes/test-thumb.c TEST_ARG_PTR(reg, val) \ reg 49 arch/arm/probes/kprobes/test-thumb.c "1: "code1 #reg code2" \n\t" \ reg 112 arch/arm/probes/uprobes/actions-arm.c int reg; reg 114 arch/arm/probes/uprobes/actions-arm.c reg = uprobes_substitute_pc(&auprobe->ixol[0], regs); reg 115 arch/arm/probes/uprobes/actions-arm.c if (reg == 15) reg 118 arch/arm/probes/uprobes/actions-arm.c if (reg == -1) reg 121 arch/arm/probes/uprobes/actions-arm.c auprobe->pcreg = reg; reg 155 arch/arm/vfp/vfp.h asmlinkage s32 vfp_get_float(unsigned int reg); reg 156 arch/arm/vfp/vfp.h asmlinkage void vfp_put_float(s32 val, unsigned int reg); reg 270 arch/arm/vfp/vfp.h asmlinkage u64 vfp_get_double(unsigned int reg); reg 271 arch/arm/vfp/vfp.h asmlinkage void vfp_put_double(u64 val, unsigned int reg); reg 26 arch/arm/xen/mm.c struct memblock_region *reg; reg 29 arch/arm/xen/mm.c for_each_memblock(memory, reg) { reg 30 arch/arm/xen/mm.c if (reg->base < (phys_addr_t)0xffffffff) { reg 263 arch/arm64/include/asm/alternative.h .macro uao_user_alternative l, inst, alt_inst, reg, addr, post_inc reg 281 arch/arm64/include/asm/alternative.h .macro uao_user_alternative l, inst, alt_inst, reg, addr, post_inc reg 87 arch/arm64/include/asm/arch_timer.h #define arch_timer_reg_read_stable(reg) \ reg 92 arch/arm64/include/asm/arch_timer.h _val = erratum_handler(read_ ## reg)(); \ reg 104 arch/arm64/include/asm/arch_timer.h void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) reg 107 arch/arm64/include/asm/arch_timer.h switch (reg) { reg 116 arch/arm64/include/asm/arch_timer.h switch (reg) { reg 130 arch/arm64/include/asm/arch_timer.h u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg) reg 133 arch/arm64/include/asm/arch_timer.h switch (reg) { reg 140 arch/arm64/include/asm/arch_timer.h switch (reg) { reg 282 arch/arm64/include/asm/assembler.h .macro read_ctr, reg reg 296 arch/arm64/include/asm/assembler.h .macro raw_dcache_line_size, reg, tmp reg 306 arch/arm64/include/asm/assembler.h .macro dcache_line_size, reg, tmp reg 317 arch/arm64/include/asm/assembler.h .macro raw_icache_line_size, reg, tmp reg 327 arch/arm64/include/asm/assembler.h .macro icache_line_size, reg, tmp reg 509 arch/arm64/include/asm/assembler.h .macro mov_q, reg, val reg 455 arch/arm64/include/asm/cpufeature.h static inline u64 arm64_ftr_reg_user_value(const struct arm64_ftr_reg *reg) reg 457 arch/arm64/include/asm/cpufeature.h return (reg->user_val | (reg->sys_val & reg->user_mask)); reg 128 arch/arm64/include/asm/cputype.h #define read_cpuid(reg) read_sysreg_s(SYS_ ## reg) reg 44 arch/arm64/include/asm/hw_breakpoint.h static inline void decode_ctrl_reg(u32 reg, reg 47 arch/arm64/include/asm/hw_breakpoint.h ctrl->enabled = reg & 0x1; reg 48 arch/arm64/include/asm/hw_breakpoint.h reg >>= 1; reg 49 arch/arm64/include/asm/hw_breakpoint.h ctrl->privilege = reg & 0x3; reg 50 arch/arm64/include/asm/hw_breakpoint.h reg >>= 2; reg 51 arch/arm64/include/asm/hw_breakpoint.h ctrl->type = reg & 0x3; reg 52 arch/arm64/include/asm/hw_breakpoint.h reg >>= 2; reg 53 arch/arm64/include/asm/hw_breakpoint.h ctrl->len = reg & 0xff; reg 368 arch/arm64/include/asm/insn.h enum aarch64_insn_register reg, reg 375 arch/arm64/include/asm/insn.h u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg, reg 377 arch/arm64/include/asm/insn.h u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg, reg 388 arch/arm64/include/asm/insn.h u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg, reg 405 arch/arm64/include/asm/insn.h enum aarch64_insn_register reg, reg 418 arch/arm64/include/asm/insn.h enum aarch64_insn_register reg, reg 428 arch/arm64/include/asm/insn.h enum aarch64_insn_register reg, reg 439 arch/arm64/include/asm/insn.h enum aarch64_insn_register reg, reg 93 arch/arm64/include/asm/kvm_asm.h .macro hyp_adr_this_cpu reg, sym, tmp reg 99 arch/arm64/include/asm/kvm_asm.h .macro hyp_ldr_this_cpu reg, sym, tmp reg 105 arch/arm64/include/asm/kvm_asm.h .macro get_host_ctxt reg, tmp reg 388 arch/arm64/include/asm/kvm_host.h u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); reg 389 arch/arm64/include/asm/kvm_host.h void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); reg 420 arch/arm64/include/asm/kvm_host.h int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); reg 421 arch/arm64/include/asm/kvm_host.h int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); reg 20 arch/arm64/include/asm/kvm_hyp.h u64 reg; \ reg 24 arch/arm64/include/asm/kvm_hyp.h : "=r" (reg)); \ reg 25 arch/arm64/include/asm/kvm_hyp.h reg; \ reg 74 arch/arm64/include/asm/kvm_mmu.h .macro kern_hyp_va reg reg 416 arch/arm64/include/asm/kvm_mmu.h int reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); reg 418 arch/arm64/include/asm/kvm_mmu.h return (cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR1_VMIDBITS_SHIFT) == 2) ? 16 : 8; reg 751 arch/arm64/include/asm/sysreg.h __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt)) reg 755 arch/arm64/include/asm/sysreg.h __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt)) reg 255 arch/arm64/include/asm/uaccess.h #define __get_user_asm(instr, alt_instr, reg, x, addr, err, feature) \ reg 257 arch/arm64/include/asm/uaccess.h "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \ reg 258 arch/arm64/include/asm/uaccess.h alt_instr " " reg "1, [%2]\n", feature) \ reg 320 arch/arm64/include/asm/uaccess.h #define __put_user_asm(instr, alt_instr, reg, x, addr, err, feature) \ reg 322 arch/arm64/include/asm/uaccess.h "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \ reg 323 arch/arm64/include/asm/uaccess.h alt_instr " " reg "1, [%2]\n", feature) \ reg 370 arch/arm64/kernel/cpufeature.c .reg = &(struct arm64_ftr_reg){ \ reg 377 arch/arm64/kernel/cpufeature.c struct arm64_ftr_reg *reg; reg 457 arch/arm64/kernel/cpufeature.c return ret->reg; reg 461 arch/arm64/kernel/cpufeature.c static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, reg 466 arch/arm64/kernel/cpufeature.c reg &= ~mask; reg 467 arch/arm64/kernel/cpufeature.c reg |= (ftr_val << ftrp->shift) & mask; reg 468 arch/arm64/kernel/cpufeature.c return reg; reg 520 arch/arm64/kernel/cpufeature.c struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); reg 522 arch/arm64/kernel/cpufeature.c BUG_ON(!reg); reg 524 arch/arm64/kernel/cpufeature.c for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { reg 536 arch/arm64/kernel/cpufeature.c reg->user_val = arm64_ftr_set_value(ftrp, reg 537 arch/arm64/kernel/cpufeature.c reg->user_val, reg 543 arch/arm64/kernel/cpufeature.c reg->sys_val = val; reg 544 arch/arm64/kernel/cpufeature.c reg->strict_mask = strict_mask; reg 545 arch/arm64/kernel/cpufeature.c reg->user_mask = user_mask; reg 630 arch/arm64/kernel/cpufeature.c static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) reg 634 arch/arm64/kernel/cpufeature.c for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { reg 635 arch/arm64/kernel/cpufeature.c s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); reg 642 arch/arm64/kernel/cpufeature.c reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); reg 860 arch/arm64/kernel/cpufeature.c feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) reg 862 arch/arm64/kernel/cpufeature.c int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); reg 1570 arch/arm64/kernel/cpufeature.c #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ reg 1572 arch/arm64/kernel/cpufeature.c .sys_reg = reg, \ reg 1583 arch/arm64/kernel/cpufeature.c #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \ reg 1586 arch/arm64/kernel/cpufeature.c HWCAP_CPUID_MATCH(reg, field, s, min_value) \ reg 105 arch/arm64/kernel/hw_breakpoint.c static u64 read_wb_reg(int reg, int n) reg 109 arch/arm64/kernel/hw_breakpoint.c switch (reg + n) { reg 122 arch/arm64/kernel/hw_breakpoint.c static void write_wb_reg(int reg, int n, u64 val) reg 124 arch/arm64/kernel/hw_breakpoint.c switch (reg + n) { reg 580 arch/arm64/kernel/hw_breakpoint.c static void toggle_bp_registers(int reg, enum dbg_active_el el, int enable) reg 586 arch/arm64/kernel/hw_breakpoint.c switch (reg) { reg 607 arch/arm64/kernel/hw_breakpoint.c ctrl = read_wb_reg(reg, i); reg 612 arch/arm64/kernel/hw_breakpoint.c write_wb_reg(reg, i, ctrl); reg 382 arch/arm64/kernel/insn.c enum aarch64_insn_register reg) reg 389 arch/arm64/kernel/insn.c if (reg < AARCH64_INSN_REG_0 || reg > AARCH64_INSN_REG_SP) { reg 390 arch/arm64/kernel/insn.c pr_err("%s: unknown register encoding %d\n", __func__, reg); reg 417 arch/arm64/kernel/insn.c insn |= reg << shift; reg 503 arch/arm64/kernel/insn.c enum aarch64_insn_register reg, reg 537 arch/arm64/kernel/insn.c insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg); reg 573 arch/arm64/kernel/insn.c u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg, reg 593 arch/arm64/kernel/insn.c return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, reg); reg 596 arch/arm64/kernel/insn.c u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg, reg 618 arch/arm64/kernel/insn.c insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, reg); reg 691 arch/arm64/kernel/insn.c u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg, reg 714 arch/arm64/kernel/insn.c reg); reg 1009 arch/arm64/kernel/insn.c enum aarch64_insn_register reg, reg 1060 arch/arm64/kernel/insn.c insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg); reg 1110 arch/arm64/kernel/insn.c enum aarch64_insn_register reg, reg 1155 arch/arm64/kernel/insn.c return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg); reg 1203 arch/arm64/kernel/insn.c enum aarch64_insn_register reg, reg 1266 arch/arm64/kernel/insn.c insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, reg); reg 1272 arch/arm64/kernel/insn.c enum aarch64_insn_register reg, reg 1295 arch/arm64/kernel/insn.c insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, reg); reg 12 arch/arm64/kernel/module-plts.c enum aarch64_insn_register reg) reg 16 arch/arm64/kernel/module-plts.c adrp = aarch64_insn_gen_adr(pc, dst, reg, AARCH64_INSN_ADR_TYPE_ADRP); reg 17 arch/arm64/kernel/module-plts.c add = aarch64_insn_gen_add_sub_imm(reg, reg, dst % SZ_4K, reg 38 arch/arm64/kernel/pci.c unsigned int devfn, int reg, int len, u32 *val) reg 44 arch/arm64/kernel/pci.c return b->ops->read(b, devfn, reg, len, val); reg 48 arch/arm64/kernel/pci.c unsigned int devfn, int reg, int len, u32 val) reg 54 arch/arm64/kernel/pci.c return b->ops->write(b, devfn, reg, len, val); reg 31 arch/arm64/kernel/probes/simulate-insn.c static inline void set_x_reg(struct pt_regs *regs, int reg, u64 val) reg 33 arch/arm64/kernel/probes/simulate-insn.c pt_regs_write_reg(regs, reg, val); reg 36 arch/arm64/kernel/probes/simulate-insn.c static inline void set_w_reg(struct pt_regs *regs, int reg, u64 val) reg 38 arch/arm64/kernel/probes/simulate-insn.c pt_regs_write_reg(regs, reg, lower_32_bits(val)); reg 41 arch/arm64/kernel/probes/simulate-insn.c static inline u64 get_x_reg(struct pt_regs *regs, int reg) reg 43 arch/arm64/kernel/probes/simulate-insn.c return pt_regs_read_reg(regs, reg); reg 46 arch/arm64/kernel/probes/simulate-insn.c static inline u32 get_w_reg(struct pt_regs *regs, int reg) reg 48 arch/arm64/kernel/probes/simulate-insn.c return lower_32_bits(pt_regs_read_reg(regs, reg)); reg 365 arch/arm64/kernel/ptrace.c u32 reg = 0; reg 378 arch/arm64/kernel/ptrace.c reg |= debug_monitors_arch(); reg 379 arch/arm64/kernel/ptrace.c reg <<= 8; reg 380 arch/arm64/kernel/ptrace.c reg |= num; reg 382 arch/arm64/kernel/ptrace.c *info = reg; reg 1260 arch/arm64/kernel/ptrace.c compat_ulong_t reg; reg 1264 arch/arm64/kernel/ptrace.c reg = task_pt_regs(target)->pc; reg 1267 arch/arm64/kernel/ptrace.c reg = task_pt_regs(target)->pstate; reg 1268 arch/arm64/kernel/ptrace.c reg = pstate_to_compat_psr(reg); reg 1271 arch/arm64/kernel/ptrace.c reg = task_pt_regs(target)->orig_x0; reg 1274 arch/arm64/kernel/ptrace.c reg = task_pt_regs(target)->regs[idx]; reg 1278 arch/arm64/kernel/ptrace.c memcpy(kbuf, ®, sizeof(reg)); reg 1279 arch/arm64/kernel/ptrace.c kbuf += sizeof(reg); reg 1281 arch/arm64/kernel/ptrace.c ret = copy_to_user(ubuf, ®, sizeof(reg)); reg 1287 arch/arm64/kernel/ptrace.c ubuf += sizeof(reg); reg 1316 arch/arm64/kernel/ptrace.c compat_ulong_t reg; reg 1319 arch/arm64/kernel/ptrace.c memcpy(®, kbuf, sizeof(reg)); reg 1320 arch/arm64/kernel/ptrace.c kbuf += sizeof(reg); reg 1322 arch/arm64/kernel/ptrace.c ret = copy_from_user(®, ubuf, sizeof(reg)); reg 1328 arch/arm64/kernel/ptrace.c ubuf += sizeof(reg); reg 1333 arch/arm64/kernel/ptrace.c newregs.pc = reg; reg 1336 arch/arm64/kernel/ptrace.c reg = compat_psr_to_pstate(reg); reg 1337 arch/arm64/kernel/ptrace.c newregs.pstate = reg; reg 1340 arch/arm64/kernel/ptrace.c newregs.orig_x0 = reg; reg 1343 arch/arm64/kernel/ptrace.c newregs.regs[idx] = reg; reg 1595 arch/arm64/kernel/ptrace.c u32 reg = 0; reg 1602 arch/arm64/kernel/ptrace.c reg |= debug_arch; reg 1603 arch/arm64/kernel/ptrace.c reg <<= 8; reg 1604 arch/arm64/kernel/ptrace.c reg |= wp_len; reg 1605 arch/arm64/kernel/ptrace.c reg <<= 8; reg 1606 arch/arm64/kernel/ptrace.c reg |= num_wrps; reg 1607 arch/arm64/kernel/ptrace.c reg <<= 8; reg 1608 arch/arm64/kernel/ptrace.c reg |= num_brps; reg 1610 arch/arm64/kernel/ptrace.c *kdata = reg; reg 69 arch/arm64/kernel/syscall.c u32 reg, val; reg 78 arch/arm64/kernel/syscall.c reg = read_sysreg(mdscr_el1); reg 79 arch/arm64/kernel/syscall.c val = reg | DBG_MDSCR_SS | DBG_MDSCR_KDE; reg 86 arch/arm64/kernel/syscall.c write_sysreg(reg, mdscr_el1); reg 644 arch/arm64/kernel/traps.c int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT; reg 646 arch/arm64/kernel/traps.c pt_regs_write_reg(regs, reg, arch_timer_get_rate()); reg 108 arch/arm64/kvm/guest.c const struct kvm_one_reg *reg) reg 110 arch/arm64/kvm/guest.c u64 off = core_reg_offset_from_id(reg->id); reg 116 arch/arm64/kvm/guest.c if (KVM_REG_SIZE(reg->id) != size) reg 122 arch/arm64/kvm/guest.c static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 130 arch/arm64/kvm/guest.c __u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr; reg 136 arch/arm64/kvm/guest.c off = core_reg_offset_from_id(reg->id); reg 138 arch/arm64/kvm/guest.c (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs) reg 141 arch/arm64/kvm/guest.c if (validate_core_offset(vcpu, reg)) reg 144 arch/arm64/kvm/guest.c if (copy_to_user(uaddr, ((u32 *)regs) + off, KVM_REG_SIZE(reg->id))) reg 150 arch/arm64/kvm/guest.c static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 152 arch/arm64/kvm/guest.c __u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr; reg 161 arch/arm64/kvm/guest.c off = core_reg_offset_from_id(reg->id); reg 163 arch/arm64/kvm/guest.c (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs) reg 166 arch/arm64/kvm/guest.c if (validate_core_offset(vcpu, reg)) reg 169 arch/arm64/kvm/guest.c if (KVM_REG_SIZE(reg->id) > sizeof(tmp)) reg 172 arch/arm64/kvm/guest.c if (copy_from_user(valp, uaddr, KVM_REG_SIZE(reg->id))) { reg 204 arch/arm64/kvm/guest.c memcpy((u32 *)regs + off, valp, KVM_REG_SIZE(reg->id)); reg 220 arch/arm64/kvm/guest.c static int get_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 238 arch/arm64/kvm/guest.c if (copy_to_user((void __user *)reg->addr, vqs, sizeof(vqs))) reg 244 arch/arm64/kvm/guest.c static int set_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 258 arch/arm64/kvm/guest.c if (copy_from_user(vqs, (const void __user *)reg->addr, sizeof(vqs))) reg 327 arch/arm64/kvm/guest.c const struct kvm_one_reg *reg) reg 355 arch/arm64/kvm/guest.c reg_num = (reg->id & SVE_REG_ID_MASK) >> SVE_REG_ID_SHIFT; reg 357 arch/arm64/kvm/guest.c if (reg->id >= zreg_id_min && reg->id <= zreg_id_max) { reg 358 arch/arm64/kvm/guest.c if (!vcpu_has_sve(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0) reg 367 arch/arm64/kvm/guest.c } else if (reg->id >= preg_id_min && reg->id <= preg_id_max) { reg 368 arch/arm64/kvm/guest.c if (!vcpu_has_sve(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0) reg 392 arch/arm64/kvm/guest.c static int get_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 396 arch/arm64/kvm/guest.c char __user *uptr = (char __user *)reg->addr; reg 399 arch/arm64/kvm/guest.c if (reg->id == KVM_REG_ARM64_SVE_VLS) reg 400 arch/arm64/kvm/guest.c return get_sve_vls(vcpu, reg); reg 403 arch/arm64/kvm/guest.c ret = sve_reg_to_region(®ion, vcpu, reg); reg 418 arch/arm64/kvm/guest.c static int set_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 422 arch/arm64/kvm/guest.c const char __user *uptr = (const char __user *)reg->addr; reg 425 arch/arm64/kvm/guest.c if (reg->id == KVM_REG_ARM64_SVE_VLS) reg 426 arch/arm64/kvm/guest.c return set_sve_vls(vcpu, reg); reg 429 arch/arm64/kvm/guest.c ret = sve_reg_to_region(®ion, vcpu, reg); reg 460 arch/arm64/kvm/guest.c u64 reg = KVM_REG_ARM64 | KVM_REG_ARM_CORE | i; reg 468 arch/arm64/kvm/guest.c reg |= KVM_REG_SIZE_U32; reg 472 arch/arm64/kvm/guest.c reg |= KVM_REG_SIZE_U64; reg 476 arch/arm64/kvm/guest.c reg |= KVM_REG_SIZE_U128; reg 485 arch/arm64/kvm/guest.c if (put_user(reg, uindices)) reg 532 arch/arm64/kvm/guest.c static int set_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 534 arch/arm64/kvm/guest.c void __user *uaddr = (void __user *)(long)reg->addr; reg 538 arch/arm64/kvm/guest.c ret = copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id)); reg 542 arch/arm64/kvm/guest.c return kvm_arm_timer_set_reg(vcpu, reg->id, val); reg 545 arch/arm64/kvm/guest.c static int get_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 547 arch/arm64/kvm/guest.c void __user *uaddr = (void __user *)(long)reg->addr; reg 550 arch/arm64/kvm/guest.c val = kvm_arm_timer_get_reg(vcpu, reg->id); reg 551 arch/arm64/kvm/guest.c return copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id)) ? -EFAULT : 0; reg 572 arch/arm64/kvm/guest.c u64 reg; reg 586 arch/arm64/kvm/guest.c reg = KVM_REG_ARM64_SVE_VLS; reg 587 arch/arm64/kvm/guest.c if (put_user(reg, uindices++)) reg 593 arch/arm64/kvm/guest.c reg = KVM_REG_ARM64_SVE_ZREG(n, i); reg 594 arch/arm64/kvm/guest.c if (put_user(reg, uindices++)) reg 600 arch/arm64/kvm/guest.c reg = KVM_REG_ARM64_SVE_PREG(n, i); reg 601 arch/arm64/kvm/guest.c if (put_user(reg, uindices++)) reg 606 arch/arm64/kvm/guest.c reg = KVM_REG_ARM64_SVE_FFR(i); reg 607 arch/arm64/kvm/guest.c if (put_user(reg, uindices++)) reg 665 arch/arm64/kvm/guest.c int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 668 arch/arm64/kvm/guest.c if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32) reg 671 arch/arm64/kvm/guest.c switch (reg->id & KVM_REG_ARM_COPROC_MASK) { reg 672 arch/arm64/kvm/guest.c case KVM_REG_ARM_CORE: return get_core_reg(vcpu, reg); reg 673 arch/arm64/kvm/guest.c case KVM_REG_ARM_FW: return kvm_arm_get_fw_reg(vcpu, reg); reg 674 arch/arm64/kvm/guest.c case KVM_REG_ARM64_SVE: return get_sve_reg(vcpu, reg); reg 677 arch/arm64/kvm/guest.c if (is_timer_reg(reg->id)) reg 678 arch/arm64/kvm/guest.c return get_timer_reg(vcpu, reg); reg 680 arch/arm64/kvm/guest.c return kvm_arm_sys_reg_get_reg(vcpu, reg); reg 683 arch/arm64/kvm/guest.c int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 686 arch/arm64/kvm/guest.c if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32) reg 689 arch/arm64/kvm/guest.c switch (reg->id & KVM_REG_ARM_COPROC_MASK) { reg 690 arch/arm64/kvm/guest.c case KVM_REG_ARM_CORE: return set_core_reg(vcpu, reg); reg 691 arch/arm64/kvm/guest.c case KVM_REG_ARM_FW: return kvm_arm_set_fw_reg(vcpu, reg); reg 692 arch/arm64/kvm/guest.c case KVM_REG_ARM64_SVE: return set_sve_reg(vcpu, reg); reg 695 arch/arm64/kvm/guest.c if (is_timer_reg(reg->id)) reg 696 arch/arm64/kvm/guest.c return set_timer_reg(vcpu, reg); reg 698 arch/arm64/kvm/guest.c return kvm_arm_sys_reg_set_reg(vcpu, reg); reg 18 arch/arm64/kvm/hyp/debug-sr.c #define save_debug(ptr,reg,nr) \ reg 20 arch/arm64/kvm/hyp/debug-sr.c case 15: ptr[15] = read_debug(reg, 15); \ reg 22 arch/arm64/kvm/hyp/debug-sr.c case 14: ptr[14] = read_debug(reg, 14); \ reg 24 arch/arm64/kvm/hyp/debug-sr.c case 13: ptr[13] = read_debug(reg, 13); \ reg 26 arch/arm64/kvm/hyp/debug-sr.c case 12: ptr[12] = read_debug(reg, 12); \ reg 28 arch/arm64/kvm/hyp/debug-sr.c case 11: ptr[11] = read_debug(reg, 11); \ reg 30 arch/arm64/kvm/hyp/debug-sr.c case 10: ptr[10] = read_debug(reg, 10); \ reg 32 arch/arm64/kvm/hyp/debug-sr.c case 9: ptr[9] = read_debug(reg, 9); \ reg 34 arch/arm64/kvm/hyp/debug-sr.c case 8: ptr[8] = read_debug(reg, 8); \ reg 36 arch/arm64/kvm/hyp/debug-sr.c case 7: ptr[7] = read_debug(reg, 7); \ reg 38 arch/arm64/kvm/hyp/debug-sr.c case 6: ptr[6] = read_debug(reg, 6); \ reg 40 arch/arm64/kvm/hyp/debug-sr.c case 5: ptr[5] = read_debug(reg, 5); \ reg 42 arch/arm64/kvm/hyp/debug-sr.c case 4: ptr[4] = read_debug(reg, 4); \ reg 44 arch/arm64/kvm/hyp/debug-sr.c case 3: ptr[3] = read_debug(reg, 3); \ reg 46 arch/arm64/kvm/hyp/debug-sr.c case 2: ptr[2] = read_debug(reg, 2); \ reg 48 arch/arm64/kvm/hyp/debug-sr.c case 1: ptr[1] = read_debug(reg, 1); \ reg 50 arch/arm64/kvm/hyp/debug-sr.c default: ptr[0] = read_debug(reg, 0); \ reg 53 arch/arm64/kvm/hyp/debug-sr.c #define restore_debug(ptr,reg,nr) \ reg 55 arch/arm64/kvm/hyp/debug-sr.c case 15: write_debug(ptr[15], reg, 15); \ reg 57 arch/arm64/kvm/hyp/debug-sr.c case 14: write_debug(ptr[14], reg, 14); \ reg 59 arch/arm64/kvm/hyp/debug-sr.c case 13: write_debug(ptr[13], reg, 13); \ reg 61 arch/arm64/kvm/hyp/debug-sr.c case 12: write_debug(ptr[12], reg, 12); \ reg 63 arch/arm64/kvm/hyp/debug-sr.c case 11: write_debug(ptr[11], reg, 11); \ reg 65 arch/arm64/kvm/hyp/debug-sr.c case 10: write_debug(ptr[10], reg, 10); \ reg 67 arch/arm64/kvm/hyp/debug-sr.c case 9: write_debug(ptr[9], reg, 9); \ reg 69 arch/arm64/kvm/hyp/debug-sr.c case 8: write_debug(ptr[8], reg, 8); \ reg 71 arch/arm64/kvm/hyp/debug-sr.c case 7: write_debug(ptr[7], reg, 7); \ reg 73 arch/arm64/kvm/hyp/debug-sr.c case 6: write_debug(ptr[6], reg, 6); \ reg 75 arch/arm64/kvm/hyp/debug-sr.c case 5: write_debug(ptr[5], reg, 5); \ reg 77 arch/arm64/kvm/hyp/debug-sr.c case 4: write_debug(ptr[4], reg, 4); \ reg 79 arch/arm64/kvm/hyp/debug-sr.c case 3: write_debug(ptr[3], reg, 3); \ reg 81 arch/arm64/kvm/hyp/debug-sr.c case 2: write_debug(ptr[2], reg, 2); \ reg 83 arch/arm64/kvm/hyp/debug-sr.c case 1: write_debug(ptr[1], reg, 1); \ reg 85 arch/arm64/kvm/hyp/debug-sr.c default: write_debug(ptr[0], reg, 0); \ reg 90 arch/arm64/kvm/hyp/debug-sr.c u64 reg; reg 101 arch/arm64/kvm/hyp/debug-sr.c reg = read_sysreg_s(SYS_PMBIDR_EL1); reg 102 arch/arm64/kvm/hyp/debug-sr.c if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) reg 106 arch/arm64/kvm/hyp/debug-sr.c reg = read_sysreg_s(SYS_PMBLIMITR_EL1); reg 107 arch/arm64/kvm/hyp/debug-sr.c if (!(reg & BIT(SYS_PMBLIMITR_EL1_E_SHIFT))) reg 345 arch/arm64/kvm/hyp/switch.c u64 reg = read_sysreg(cpacr_el1) | CPACR_EL1_FPEN; reg 348 arch/arm64/kvm/hyp/switch.c reg |= CPACR_EL1_ZEN; reg 350 arch/arm64/kvm/hyp/switch.c write_sysreg(reg, cpacr_el1); reg 68 arch/arm64/kvm/sys_regs.c u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) reg 82 arch/arm64/kvm/sys_regs.c switch (reg) { reg 109 arch/arm64/kvm/sys_regs.c return __vcpu_sys_reg(vcpu, reg); reg 112 arch/arm64/kvm/sys_regs.c void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) reg 125 arch/arm64/kvm/sys_regs.c switch (reg) { reg 152 arch/arm64/kvm/sys_regs.c __vcpu_sys_reg(vcpu, reg) = val; reg 210 arch/arm64/kvm/sys_regs.c int reg = r->reg; reg 216 arch/arm64/kvm/sys_regs.c reg = r->reg / 2; reg 221 arch/arm64/kvm/sys_regs.c val = vcpu_read_sys_reg(vcpu, reg); reg 222 arch/arm64/kvm/sys_regs.c if (r->reg % 2) reg 228 arch/arm64/kvm/sys_regs.c vcpu_write_sys_reg(vcpu, val, reg); reg 387 arch/arm64/kvm/sys_regs.c vcpu_write_sys_reg(vcpu, p->regval, r->reg); reg 390 arch/arm64/kvm/sys_regs.c p->regval = vcpu_read_sys_reg(vcpu, r->reg); reg 393 arch/arm64/kvm/sys_regs.c trace_trap_reg(__func__, r->reg, p->is_write, p->regval); reg 435 arch/arm64/kvm/sys_regs.c u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; reg 442 arch/arm64/kvm/sys_regs.c trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); reg 448 arch/arm64/kvm/sys_regs.c const struct kvm_one_reg *reg, void __user *uaddr) reg 450 arch/arm64/kvm/sys_regs.c __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; reg 452 arch/arm64/kvm/sys_regs.c if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) reg 458 arch/arm64/kvm/sys_regs.c const struct kvm_one_reg *reg, void __user *uaddr) reg 460 arch/arm64/kvm/sys_regs.c __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; reg 462 arch/arm64/kvm/sys_regs.c if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) reg 470 arch/arm64/kvm/sys_regs.c vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val; reg 477 arch/arm64/kvm/sys_regs.c u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; reg 484 arch/arm64/kvm/sys_regs.c trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); reg 490 arch/arm64/kvm/sys_regs.c const struct kvm_one_reg *reg, void __user *uaddr) reg 492 arch/arm64/kvm/sys_regs.c __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; reg 494 arch/arm64/kvm/sys_regs.c if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) reg 501 arch/arm64/kvm/sys_regs.c const struct kvm_one_reg *reg, void __user *uaddr) reg 503 arch/arm64/kvm/sys_regs.c __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; reg 505 arch/arm64/kvm/sys_regs.c if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) reg 513 arch/arm64/kvm/sys_regs.c vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val; reg 520 arch/arm64/kvm/sys_regs.c u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; reg 527 arch/arm64/kvm/sys_regs.c trace_trap_reg(__func__, rd->reg, p->is_write, reg 528 arch/arm64/kvm/sys_regs.c vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]); reg 534 arch/arm64/kvm/sys_regs.c const struct kvm_one_reg *reg, void __user *uaddr) reg 536 arch/arm64/kvm/sys_regs.c __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; reg 538 arch/arm64/kvm/sys_regs.c if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) reg 544 arch/arm64/kvm/sys_regs.c const struct kvm_one_reg *reg, void __user *uaddr) reg 546 arch/arm64/kvm/sys_regs.c __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; reg 548 arch/arm64/kvm/sys_regs.c if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) reg 556 arch/arm64/kvm/sys_regs.c vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val; reg 563 arch/arm64/kvm/sys_regs.c u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; reg 570 arch/arm64/kvm/sys_regs.c trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); reg 576 arch/arm64/kvm/sys_regs.c const struct kvm_one_reg *reg, void __user *uaddr) reg 578 arch/arm64/kvm/sys_regs.c __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; reg 580 arch/arm64/kvm/sys_regs.c if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) reg 586 arch/arm64/kvm/sys_regs.c const struct kvm_one_reg *reg, void __user *uaddr) reg 588 arch/arm64/kvm/sys_regs.c __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; reg 590 arch/arm64/kvm/sys_regs.c if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) reg 598 arch/arm64/kvm/sys_regs.c vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val; reg 637 arch/arm64/kvm/sys_regs.c __vcpu_sys_reg(vcpu, r->reg) = val; reg 642 arch/arm64/kvm/sys_regs.c u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); reg 643 arch/arm64/kvm/sys_regs.c bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); reg 818 arch/arm64/kvm/sys_regs.c u64 idx, reg; reg 829 arch/arm64/kvm/sys_regs.c reg = PMEVTYPER0_EL0 + idx; reg 833 arch/arm64/kvm/sys_regs.c reg = PMCCFILTR_EL0; reg 836 arch/arm64/kvm/sys_regs.c reg = PMEVTYPER0_EL0 + idx; reg 846 arch/arm64/kvm/sys_regs.c __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK; reg 849 arch/arm64/kvm/sys_regs.c p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; reg 1043 arch/arm64/kvm/sys_regs.c u64 reg = reg_to_encoding(r); reg 1045 arch/arm64/kvm/sys_regs.c switch (reg) { reg 1123 arch/arm64/kvm/sys_regs.c static u64 sys_reg_to_index(const struct sys_reg_desc *reg); reg 1167 arch/arm64/kvm/sys_regs.c const struct kvm_one_reg *reg, void __user *uaddr) reg 1175 arch/arm64/kvm/sys_regs.c return reg_to_user(uaddr, &val, reg->id); reg 1180 arch/arm64/kvm/sys_regs.c const struct kvm_one_reg *reg, void __user *uaddr) reg 1237 arch/arm64/kvm/sys_regs.c const struct kvm_one_reg *reg, void __user *uaddr) reg 1243 arch/arm64/kvm/sys_regs.c const struct kvm_one_reg *reg, void __user *uaddr) reg 1249 arch/arm64/kvm/sys_regs.c const struct kvm_one_reg *reg, void __user *uaddr) reg 1255 arch/arm64/kvm/sys_regs.c const struct kvm_one_reg *reg, void __user *uaddr) reg 1283 arch/arm64/kvm/sys_regs.c int reg = r->reg; reg 1287 arch/arm64/kvm/sys_regs.c reg = r->reg / 2; reg 1290 arch/arm64/kvm/sys_regs.c vcpu_write_sys_reg(vcpu, p->regval, reg); reg 1292 arch/arm64/kvm/sys_regs.c p->regval = vcpu_read_sys_reg(vcpu, reg); reg 1677 arch/arm64/kvm/sys_regs.c vcpu_cp14(vcpu, r->reg) = p->regval; reg 1680 arch/arm64/kvm/sys_regs.c p->regval = vcpu_cp14(vcpu, r->reg); reg 1701 arch/arm64/kvm/sys_regs.c u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; reg 1715 arch/arm64/kvm/sys_regs.c trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); reg 2274 arch/arm64/kvm/sys_regs.c int reg = table[i].reg; reg 2277 arch/arm64/kvm/sys_regs.c if (reg > 0 && reg < NR_SYS_REGS) reg 2278 arch/arm64/kvm/sys_regs.c set_bit(reg, bmap); reg 2378 arch/arm64/kvm/sys_regs.c if (r && !(r->reg || r->get_user)) reg 2392 arch/arm64/kvm/sys_regs.c #define FUNCTION_INVARIANT(reg) \ reg 2393 arch/arm64/kvm/sys_regs.c static void get_##reg(struct kvm_vcpu *v, \ reg 2396 arch/arm64/kvm/sys_regs.c ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ reg 2550 arch/arm64/kvm/sys_regs.c int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 2553 arch/arm64/kvm/sys_regs.c void __user *uaddr = (void __user *)(unsigned long)reg->addr; reg 2555 arch/arm64/kvm/sys_regs.c if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) reg 2556 arch/arm64/kvm/sys_regs.c return demux_c15_get(reg->id, uaddr); reg 2558 arch/arm64/kvm/sys_regs.c if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) reg 2561 arch/arm64/kvm/sys_regs.c r = index_to_sys_reg_desc(vcpu, reg->id); reg 2563 arch/arm64/kvm/sys_regs.c return get_invariant_sys_reg(reg->id, uaddr); reg 2570 arch/arm64/kvm/sys_regs.c return (r->get_user)(vcpu, r, reg, uaddr); reg 2572 arch/arm64/kvm/sys_regs.c return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id); reg 2575 arch/arm64/kvm/sys_regs.c int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 2578 arch/arm64/kvm/sys_regs.c void __user *uaddr = (void __user *)(unsigned long)reg->addr; reg 2580 arch/arm64/kvm/sys_regs.c if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) reg 2581 arch/arm64/kvm/sys_regs.c return demux_c15_set(reg->id, uaddr); reg 2583 arch/arm64/kvm/sys_regs.c if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) reg 2586 arch/arm64/kvm/sys_regs.c r = index_to_sys_reg_desc(vcpu, reg->id); reg 2588 arch/arm64/kvm/sys_regs.c return set_invariant_sys_reg(reg->id, uaddr); reg 2595 arch/arm64/kvm/sys_regs.c return (r->set_user)(vcpu, r, reg, uaddr); reg 2597 arch/arm64/kvm/sys_regs.c return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id); reg 2627 arch/arm64/kvm/sys_regs.c static u64 sys_reg_to_index(const struct sys_reg_desc *reg) reg 2631 arch/arm64/kvm/sys_regs.c (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | reg 2632 arch/arm64/kvm/sys_regs.c (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | reg 2633 arch/arm64/kvm/sys_regs.c (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | reg 2634 arch/arm64/kvm/sys_regs.c (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | reg 2635 arch/arm64/kvm/sys_regs.c (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); reg 2638 arch/arm64/kvm/sys_regs.c static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) reg 2643 arch/arm64/kvm/sys_regs.c if (put_user(sys_reg_to_index(reg), *uind)) reg 2659 arch/arm64/kvm/sys_regs.c if (!(rd->reg || rd->get_user)) reg 46 arch/arm64/kvm/sys_regs.h int reg; reg 53 arch/arm64/kvm/sys_regs.h const struct kvm_one_reg *reg, void __user *uaddr); reg 55 arch/arm64/kvm/sys_regs.h const struct kvm_one_reg *reg, void __user *uaddr); reg 89 arch/arm64/kvm/sys_regs.h BUG_ON(!r->reg); reg 90 arch/arm64/kvm/sys_regs.h BUG_ON(r->reg >= NR_SYS_REGS); reg 91 arch/arm64/kvm/sys_regs.h __vcpu_sys_reg(vcpu, r->reg) = 0x1de7ec7edbadc0deULL; reg 96 arch/arm64/kvm/sys_regs.h BUG_ON(!r->reg); reg 97 arch/arm64/kvm/sys_regs.h BUG_ON(r->reg >= NR_SYS_REGS); reg 98 arch/arm64/kvm/sys_regs.h __vcpu_sys_reg(vcpu, r->reg) = r->val; reg 149 arch/arm64/kvm/sys_regs.h #define SYS_DESC(reg) \ reg 150 arch/arm64/kvm/sys_regs.h .name = #reg, \ reg 151 arch/arm64/kvm/sys_regs.h Op0(sys_reg_Op0(reg)), Op1(sys_reg_Op1(reg)), \ reg 152 arch/arm64/kvm/sys_regs.h CRn(sys_reg_CRn(reg)), CRm(sys_reg_CRm(reg)), \ reg 153 arch/arm64/kvm/sys_regs.h Op2(sys_reg_Op2(reg)) reg 121 arch/arm64/kvm/trace.h TP_PROTO(const char *fn, int reg, bool is_write, u64 write_value), reg 122 arch/arm64/kvm/trace.h TP_ARGS(fn, reg, is_write, write_value), reg 126 arch/arm64/kvm/trace.h __field(int, reg) reg 133 arch/arm64/kvm/trace.h __entry->reg = reg; reg 138 arch/arm64/kvm/trace.h TP_printk("%s %s reg %d (0x%08llx)", __entry->fn, __entry->is_write?"write to":"read from", __entry->reg, __entry->write_value) reg 157 arch/arm64/kvm/trace.h TP_PROTO(unsigned long vcpu_pc, struct sys_reg_params *params, const struct sys_reg_desc *reg), reg 158 arch/arm64/kvm/trace.h TP_ARGS(vcpu_pc, params, reg), reg 174 arch/arm64/kvm/trace.h __entry->name = reg->name; reg 175 arch/arm64/kvm/trace.h __entry->Op0 = reg->Op0; reg 176 arch/arm64/kvm/trace.h __entry->Op0 = reg->Op0; reg 177 arch/arm64/kvm/trace.h __entry->Op1 = reg->Op1; reg 178 arch/arm64/kvm/trace.h __entry->CRn = reg->CRn; reg 179 arch/arm64/kvm/trace.h __entry->CRm = reg->CRm; reg 180 arch/arm64/kvm/trace.h __entry->Op2 = reg->Op2; reg 264 arch/arm64/kvm/vgic-sys-reg-v3.c u64 *reg) reg 269 arch/arm64/kvm/vgic-sys-reg-v3.c params.regval = *reg; reg 282 arch/arm64/kvm/vgic-sys-reg-v3.c u64 *reg) reg 289 arch/arm64/kvm/vgic-sys-reg-v3.c params.regval = *reg; reg 303 arch/arm64/kvm/vgic-sys-reg-v3.c *reg = params.regval; reg 126 arch/arm64/mm/init.c const __be32 *reg; reg 132 arch/arm64/mm/init.c reg = of_get_flat_dt_prop(node, "linux,elfcorehdr", &len); reg 133 arch/arm64/mm/init.c if (!reg || (len < (dt_root_addr_cells + dt_root_size_cells))) reg 136 arch/arm64/mm/init.c elfcorehdr_addr = dt_mem_next_cell(dt_root_addr_cells, ®); reg 137 arch/arm64/mm/init.c elfcorehdr_size = dt_mem_next_cell(dt_root_size_cells, ®); reg 201 arch/arm64/mm/init.c struct memblock_region *reg; reg 216 arch/arm64/mm/init.c for_each_memblock(memory, reg) { reg 217 arch/arm64/mm/init.c unsigned long start = memblock_region_memory_base_pfn(reg); reg 218 arch/arm64/mm/init.c unsigned long end = memblock_region_memory_end_pfn(reg); reg 280 arch/arm64/mm/init.c const __be32 *reg; reg 286 arch/arm64/mm/init.c reg = of_get_flat_dt_prop(node, "linux,usable-memory-range", &len); reg 287 arch/arm64/mm/init.c if (!reg || (len < (dt_root_addr_cells + dt_root_size_cells))) reg 290 arch/arm64/mm/init.c usablemem->base = dt_mem_next_cell(dt_root_addr_cells, ®); reg 291 arch/arm64/mm/init.c usablemem->size = dt_mem_next_cell(dt_root_size_cells, ®); reg 298 arch/arm64/mm/init.c struct memblock_region reg = { reg 302 arch/arm64/mm/init.c of_scan_flat_dt(early_init_dt_scan_usablemem, ®); reg 304 arch/arm64/mm/init.c if (reg.size) reg 305 arch/arm64/mm/init.c memblock_cap_memory_range(reg.base, reg.size); reg 494 arch/arm64/mm/init.c struct memblock_region *reg; reg 496 arch/arm64/mm/init.c for_each_memblock(memory, reg) { reg 497 arch/arm64/mm/init.c start = __phys_to_pfn(reg->base); reg 518 arch/arm64/mm/init.c prev_end = ALIGN(__phys_to_pfn(reg->base + reg->size), reg 204 arch/arm64/mm/kasan_init.c struct memblock_region *reg; reg 238 arch/arm64/mm/kasan_init.c for_each_memblock(memory, reg) { reg 239 arch/arm64/mm/kasan_init.c void *start = (void *)__phys_to_virt(reg->base); reg 240 arch/arm64/mm/kasan_init.c void *end = (void *)__phys_to_virt(reg->base + reg->size); reg 463 arch/arm64/mm/mmu.c struct memblock_region *reg; reg 483 arch/arm64/mm/mmu.c for_each_memblock(memory, reg) { reg 484 arch/arm64/mm/mmu.c phys_addr_t start = reg->base; reg 485 arch/arm64/mm/mmu.c phys_addr_t end = start + reg->size; reg 489 arch/arm64/mm/mmu.c if (memblock_is_nomap(reg)) reg 71 arch/arm64/net/bpf_jit_comp.c static inline void emit_a64_mov_i(const int is64, const int reg, reg 79 arch/arm64/net/bpf_jit_comp.c emit(A64_MOVN(is64, reg, (u16)~lo, 0), ctx); reg 81 arch/arm64/net/bpf_jit_comp.c emit(A64_MOVN(is64, reg, (u16)~hi, 16), ctx); reg 83 arch/arm64/net/bpf_jit_comp.c emit(A64_MOVK(is64, reg, lo, 0), ctx); reg 86 arch/arm64/net/bpf_jit_comp.c emit(A64_MOVZ(is64, reg, lo, 0), ctx); reg 88 arch/arm64/net/bpf_jit_comp.c emit(A64_MOVK(is64, reg, hi, 16), ctx); reg 100 arch/arm64/net/bpf_jit_comp.c static inline void emit_a64_mov_i64(const int reg, const u64 val, reg 108 arch/arm64/net/bpf_jit_comp.c return emit_a64_mov_i(0, reg, (u32)val, ctx); reg 114 arch/arm64/net/bpf_jit_comp.c emit(A64_MOVN(1, reg, (rev_tmp >> shift) & 0xffff, shift), ctx); reg 116 arch/arm64/net/bpf_jit_comp.c emit(A64_MOVZ(1, reg, (nrm_tmp >> shift) & 0xffff, shift), ctx); reg 120 arch/arm64/net/bpf_jit_comp.c emit(A64_MOVK(1, reg, (nrm_tmp >> shift) & 0xffff, shift), ctx); reg 130 arch/arm64/net/bpf_jit_comp.c static inline void emit_addr_mov_i64(const int reg, const u64 val, reg 136 arch/arm64/net/bpf_jit_comp.c emit(A64_MOVN(1, reg, ~tmp & 0xffff, shift), ctx); reg 140 arch/arm64/net/bpf_jit_comp.c emit(A64_MOVK(1, reg, tmp & 0xffff, shift), ctx); reg 357 arch/arm64/net/bpf_jit_comp.c u8 jmp_cond, reg; reg 752 arch/arm64/net/bpf_jit_comp.c reg = dst; reg 756 arch/arm64/net/bpf_jit_comp.c reg = tmp; reg 759 arch/arm64/net/bpf_jit_comp.c emit(A64_STADD(isdw, reg, src), ctx); reg 761 arch/arm64/net/bpf_jit_comp.c emit(A64_LDXR(isdw, tmp2, reg), ctx); reg 763 arch/arm64/net/bpf_jit_comp.c emit(A64_STXR(isdw, tmp2, reg, tmp3), ctx); reg 12 arch/c6x/include/asm/special_insns.h #define get_creg(reg) \ reg 14 arch/c6x/include/asm/special_insns.h asm volatile ("mvc .s2 " #reg ",%0\n" : "=b"(__x)); __x; }) reg 16 arch/c6x/include/asm/special_insns.h #define set_creg(reg, v) \ reg 18 arch/c6x/include/asm/special_insns.h asm volatile ("mvc .s2 %0," #reg "\n" : : "b"(__x)); \ reg 21 arch/c6x/include/asm/special_insns.h #define or_creg(reg, n) \ reg 23 arch/c6x/include/asm/special_insns.h asm volatile ("mvc .s2 " #reg ",%0\n" \ reg 25 arch/c6x/include/asm/special_insns.h "mvc .s2 %0," #reg "\n" \ reg 30 arch/c6x/include/asm/special_insns.h #define and_creg(reg, n) \ reg 32 arch/c6x/include/asm/special_insns.h asm volatile ("mvc .s2 " #reg ",%0\n" \ reg 34 arch/c6x/include/asm/special_insns.h "mvc .s2 %0," #reg "\n" \ reg 290 arch/c6x/kernel/setup.c struct memblock_region *reg; reg 354 arch/c6x/kernel/setup.c for_each_memblock(memory, reg) reg 355 arch/c6x/kernel/setup.c enable_caching(CACHE_REGION_START(reg->base), reg 356 arch/c6x/kernel/setup.c CACHE_REGION_START(reg->base + reg->size - 1)); reg 109 arch/c6x/platforms/cache.c #define imcr_get(reg) soc_readl(cache_base + (reg)) reg 110 arch/c6x/platforms/cache.c #define imcr_set(reg, value) \ reg 112 arch/c6x/platforms/cache.c soc_writel((value), cache_base + (reg)); \ reg 113 arch/c6x/platforms/cache.c soc_readl(cache_base + (reg)); \ reg 42 arch/c6x/platforms/dscr.c u32 reg; reg 51 arch/c6x/platforms/dscr.c u32 reg; /* offset from base */ reg 64 arch/c6x/platforms/dscr.c u32 reg; /* register holding the control bits */ reg 83 arch/c6x/platforms/dscr.c u32 reg; /* register holding the status bits */ reg 116 arch/c6x/platforms/dscr.c static struct locked_reg *find_locked_reg(u32 reg) reg 121 arch/c6x/platforms/dscr.c if (dscr.locked[i].key && reg == dscr.locked[i].reg) reg 129 arch/c6x/platforms/dscr.c static void dscr_write_locked1(u32 reg, u32 val, reg 132 arch/c6x/platforms/dscr.c void __iomem *reg_addr = dscr.base + reg; reg 158 arch/c6x/platforms/dscr.c static void dscr_write_locked2(u32 reg, u32 val, reg 164 arch/c6x/platforms/dscr.c soc_writel(val, dscr.base + reg); reg 169 arch/c6x/platforms/dscr.c static void dscr_write(u32 reg, u32 val) reg 173 arch/c6x/platforms/dscr.c lock = find_locked_reg(reg); reg 175 arch/c6x/platforms/dscr.c dscr_write_locked1(reg, val, lock->lockreg, lock->key); reg 177 arch/c6x/platforms/dscr.c dscr_write_locked2(reg, val, dscr.kick_reg[0], dscr.kick_key[0], reg 180 arch/c6x/platforms/dscr.c soc_writel(val, dscr.base + reg); reg 227 arch/c6x/platforms/dscr.c val = soc_readl(dscr.base + ctl->reg); reg 231 arch/c6x/platforms/dscr.c dscr_write(ctl->reg, val); reg 246 arch/c6x/platforms/dscr.c val = soc_readl(dscr.base + stat->reg); reg 271 arch/c6x/platforms/dscr.c val = soc_readl(dscr.base + r->reg); reg 273 arch/c6x/platforms/dscr.c dscr_write(r->reg, val | r->mask); reg 275 arch/c6x/platforms/dscr.c dscr_write(r->reg, val & ~(r->mask)); reg 358 arch/c6x/platforms/dscr.c dscr.rmii_resets[i].reg = be32_to_cpup(p++); reg 410 arch/c6x/platforms/dscr.c r->reg = be32_to_cpup(p++); reg 485 arch/c6x/platforms/dscr.c r->reg = be32_to_cpup(p++); reg 541 arch/c6x/platforms/dscr.c r->reg = be32_to_cpup(p++); reg 200 arch/c6x/platforms/pll.c static u32 pll_read(struct pll_data *pll, int reg) reg 202 arch/c6x/platforms/pll.c return soc_readl(pll->base + reg); reg 8 arch/csky/abiv1/inc/abi/reg_ops.h #define cprcr(reg) \ reg 11 arch/csky/abiv1/inc/abi/reg_ops.h asm volatile("cprcr %0, "reg"\n":"=b"(tmp)); \ reg 15 arch/csky/abiv1/inc/abi/reg_ops.h #define cpwcr(reg, val) \ reg 17 arch/csky/abiv1/inc/abi/reg_ops.h asm volatile("cpwcr %0, "reg"\n"::"b"(val)); \ reg 6 arch/csky/include/asm/reg_ops.h #define mfcr(reg) \ reg 10 arch/csky/include/asm/reg_ops.h "mfcr %0, "reg"\n" \ reg 17 arch/csky/include/asm/reg_ops.h #define mtcr(reg, val) \ reg 20 arch/csky/include/asm/reg_ops.h "mtcr %0, "reg"\n" \ reg 51 arch/csky/kernel/perf_event.c #define cprgr(reg) \ reg 54 arch/csky/kernel/perf_event.c asm volatile("cprgr %0, "reg"\n" \ reg 61 arch/csky/kernel/perf_event.c #define cpwgr(reg, val) \ reg 64 arch/csky/kernel/perf_event.c "cpwgr %0, "reg"\n" \ reg 70 arch/csky/kernel/perf_event.c #define cprcr(reg) \ reg 73 arch/csky/kernel/perf_event.c asm volatile("cprcr %0, "reg"\n" \ reg 80 arch/csky/kernel/perf_event.c #define cpwcr(reg, val) \ reg 83 arch/csky/kernel/perf_event.c "cpwcr %0, "reg"\n" \ reg 9 arch/csky/kernel/syscall.c struct pt_regs *reg = current_pt_regs(); reg 11 arch/csky/kernel/syscall.c reg->tls = addr; reg 95 arch/h8300/kernel/ptrace.c long *reg = (long *)®s; reg 100 arch/h8300/kernel/ptrace.c *reg++ = h8300_get_reg(target, r); reg 114 arch/h8300/kernel/ptrace.c long *reg; reg 118 arch/h8300/kernel/ptrace.c for (reg = (long *)®s, r = 0; r < sizeof(regs) / sizeof(long); r++) reg 119 arch/h8300/kernel/ptrace.c *reg++ = h8300_get_reg(target, r); reg 127 arch/h8300/kernel/ptrace.c for (reg = (long *)®s, r = 0; r < sizeof(regs) / sizeof(long); r++) reg 128 arch/h8300/kernel/ptrace.c h8300_put_reg(target, r, *reg++); reg 74 arch/h8300/kernel/ptrace_h.c OPTABLE(0x59, 0xfb, 1, reg), /* 0x59/0x5b */ reg 190 arch/h8300/kernel/ptrace_h.c case reg: reg 77 arch/ia64/include/asm/asmmacro.h #define LOAD_PHYSICAL(pr, reg, obj) \ reg 78 arch/ia64/include/asm/asmmacro.h [1:](pr)movl reg = obj; \ reg 113 arch/ia64/include/asm/asmmacro.h #define LOAD_PHYS_STACK_REG_SIZE(reg) \ reg 114 arch/ia64/include/asm/asmmacro.h [1:] adds reg=IA64_NUM_PHYS_STACK_REG*8+8,r0; \ reg 66 arch/ia64/include/asm/iosapic.h __ia64_native_iosapic_read(char __iomem *iosapic, unsigned int reg) reg 68 arch/ia64/include/asm/iosapic.h writel(reg, iosapic + IOSAPIC_REG_SELECT); reg 73 arch/ia64/include/asm/iosapic.h __ia64_native_iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val) reg 75 arch/ia64/include/asm/iosapic.h writel(reg, iosapic + IOSAPIC_REG_SELECT); reg 55 arch/ia64/include/asm/mca_asm.h #define GET_THIS_PADDR(reg, var) \ reg 56 arch/ia64/include/asm/mca_asm.h mov reg = IA64_KR(PER_CPU_DATA);; \ reg 57 arch/ia64/include/asm/mca_asm.h addl reg = THIS_CPU(var), reg reg 11 arch/ia64/include/asm/native/inst.h #define MOV_FROM_IFA(reg) \ reg 12 arch/ia64/include/asm/native/inst.h mov reg = cr.ifa reg 14 arch/ia64/include/asm/native/inst.h #define MOV_FROM_ITIR(reg) \ reg 15 arch/ia64/include/asm/native/inst.h mov reg = cr.itir reg 17 arch/ia64/include/asm/native/inst.h #define MOV_FROM_ISR(reg) \ reg 18 arch/ia64/include/asm/native/inst.h mov reg = cr.isr reg 20 arch/ia64/include/asm/native/inst.h #define MOV_FROM_IHA(reg) \ reg 21 arch/ia64/include/asm/native/inst.h mov reg = cr.iha reg 23 arch/ia64/include/asm/native/inst.h #define MOV_FROM_IPSR(pred, reg) \ reg 24 arch/ia64/include/asm/native/inst.h (pred) mov reg = cr.ipsr reg 26 arch/ia64/include/asm/native/inst.h #define MOV_FROM_IIM(reg) \ reg 27 arch/ia64/include/asm/native/inst.h mov reg = cr.iim reg 29 arch/ia64/include/asm/native/inst.h #define MOV_FROM_IIP(reg) \ reg 30 arch/ia64/include/asm/native/inst.h mov reg = cr.iip reg 32 arch/ia64/include/asm/native/inst.h #define MOV_FROM_IVR(reg, clob) \ reg 33 arch/ia64/include/asm/native/inst.h mov reg = cr.ivr reg 35 arch/ia64/include/asm/native/inst.h #define MOV_FROM_PSR(pred, reg, clob) \ reg 36 arch/ia64/include/asm/native/inst.h (pred) mov reg = psr reg 38 arch/ia64/include/asm/native/inst.h #define MOV_FROM_ITC(pred, pred_clob, reg, clob) \ reg 39 arch/ia64/include/asm/native/inst.h (pred) mov reg = ar.itc reg 41 arch/ia64/include/asm/native/inst.h #define MOV_TO_IFA(reg, clob) \ reg 42 arch/ia64/include/asm/native/inst.h mov cr.ifa = reg reg 44 arch/ia64/include/asm/native/inst.h #define MOV_TO_ITIR(pred, reg, clob) \ reg 45 arch/ia64/include/asm/native/inst.h (pred) mov cr.itir = reg reg 47 arch/ia64/include/asm/native/inst.h #define MOV_TO_IHA(pred, reg, clob) \ reg 48 arch/ia64/include/asm/native/inst.h (pred) mov cr.iha = reg reg 50 arch/ia64/include/asm/native/inst.h #define MOV_TO_IPSR(pred, reg, clob) \ reg 51 arch/ia64/include/asm/native/inst.h (pred) mov cr.ipsr = reg reg 53 arch/ia64/include/asm/native/inst.h #define MOV_TO_IFS(pred, reg, clob) \ reg 54 arch/ia64/include/asm/native/inst.h (pred) mov cr.ifs = reg reg 56 arch/ia64/include/asm/native/inst.h #define MOV_TO_IIP(reg, clob) \ reg 57 arch/ia64/include/asm/native/inst.h mov cr.iip = reg reg 59 arch/ia64/include/asm/native/inst.h #define MOV_TO_KR(kr, reg, clob0, clob1) \ reg 60 arch/ia64/include/asm/native/inst.h mov IA64_KR(kr) = reg reg 62 arch/ia64/include/asm/native/inst.h #define ITC_I(pred, reg, clob) \ reg 63 arch/ia64/include/asm/native/inst.h (pred) itc.i reg reg 65 arch/ia64/include/asm/native/inst.h #define ITC_D(pred, reg, clob) \ reg 66 arch/ia64/include/asm/native/inst.h (pred) itc.d reg reg 68 arch/ia64/include/asm/native/inst.h #define ITC_I_AND_D(pred_i, pred_d, reg, clob) \ reg 69 arch/ia64/include/asm/native/inst.h (pred_i) itc.i reg; \ reg 70 arch/ia64/include/asm/native/inst.h (pred_d) itc.d reg reg 132 arch/ia64/include/asm/page.h unsigned long reg : 3; /* region number */ reg 144 arch/ia64/include/asm/page.h #define __pa(x) ({ia64_va _v; _v.l = (long) (x); _v.f.reg = 0; _v.l;}) reg 145 arch/ia64/include/asm/page.h #define __va(x) ({ia64_va _v; _v.l = (long) (x); _v.f.reg = -1; _v.p;}) reg 147 arch/ia64/include/asm/page.h #define REGION_NUMBER(x) ({ia64_va _v; _v.l = (long) (x); _v.f.reg;}) reg 553 arch/ia64/include/asm/processor.h unsigned int reg = vector / 64; reg 557 arch/ia64/include/asm/processor.h switch (reg) { reg 40 arch/ia64/kernel/cyclone.c u64 __iomem *reg; reg 53 arch/ia64/kernel/cyclone.c reg = ioremap_nocache(offset, sizeof(u64)); reg 54 arch/ia64/kernel/cyclone.c if(!reg){ reg 60 arch/ia64/kernel/cyclone.c base = readq(reg); reg 61 arch/ia64/kernel/cyclone.c iounmap(reg); reg 71 arch/ia64/kernel/cyclone.c reg = ioremap_nocache(offset, sizeof(u64)); reg 72 arch/ia64/kernel/cyclone.c if(!reg){ reg 78 arch/ia64/kernel/cyclone.c writel(0x00000001,reg); reg 79 arch/ia64/kernel/cyclone.c iounmap(reg); reg 83 arch/ia64/kernel/cyclone.c reg = ioremap_nocache(offset, sizeof(u64)); reg 84 arch/ia64/kernel/cyclone.c if(!reg){ reg 90 arch/ia64/kernel/cyclone.c writel(0x00000001,reg); reg 91 arch/ia64/kernel/cyclone.c iounmap(reg); reg 150 arch/ia64/kernel/iosapic.c iosapic_write(struct iosapic *iosapic, unsigned int reg, u32 val) reg 155 arch/ia64/kernel/iosapic.c __iosapic_write(iosapic->addr, reg, val); reg 999 arch/ia64/kernel/mca.c if (va.f.reg == 0) { reg 1000 arch/ia64/kernel/mca.c va.f.reg = 7; reg 1004 arch/ia64/kernel/mca.c if (va.f.reg == 0) { reg 1005 arch/ia64/kernel/mca.c va.f.reg = 7; reg 1011 arch/ia64/kernel/mca.c if (va.f.reg == 0) { reg 1012 arch/ia64/kernel/mca.c va.f.reg = 7; reg 1016 arch/ia64/kernel/mca.c if (va.f.reg == 0) { reg 1017 arch/ia64/kernel/mca.c va.f.reg = 7; reg 1063 arch/ia64/kernel/mca.c if (va.f.reg < 5) { reg 2660 arch/ia64/kernel/perfmon.c pfm_new_counter_value (pfm_counter_t *reg, int is_long_reset) reg 2662 arch/ia64/kernel/perfmon.c unsigned long val = is_long_reset ? reg->long_reset : reg->short_reset; reg 2663 arch/ia64/kernel/perfmon.c unsigned long new_seed, old_seed = reg->seed, mask = reg->mask; reg 2666 arch/ia64/kernel/perfmon.c if (reg->flags & PFM_REGFL_RANDOM) { reg 2672 arch/ia64/kernel/perfmon.c reg->seed = new_seed; reg 2674 arch/ia64/kernel/perfmon.c reg->lval = val; reg 248 arch/ia64/kernel/unaligned.c # define F(reg) case reg: ia64_invala_gr(reg); break reg 275 arch/ia64/kernel/unaligned.c # define F(reg) case reg: ia64_invala_fr(reg); break reg 299 arch/ia64/kernel/unaligned.c rotate_reg (unsigned long sor, unsigned long rrb, unsigned long reg) reg 301 arch/ia64/kernel/unaligned.c reg += rrb; reg 302 arch/ia64/kernel/unaligned.c if (reg >= sor) reg 303 arch/ia64/kernel/unaligned.c reg -= sor; reg 304 arch/ia64/kernel/unaligned.c return reg; reg 252 arch/ia64/kernel/unwind.c pt_regs_off (unsigned long reg) reg 256 arch/ia64/kernel/unwind.c if (reg < ARRAY_SIZE(unw.pt_regs_offsets)) reg 257 arch/ia64/kernel/unwind.c off = unw.pt_regs_offsets[reg]; reg 260 arch/ia64/kernel/unwind.c UNW_DPRINT(0, "unwind.%s: bad scratch reg r%lu\n", __func__, reg); reg 707 arch/ia64/kernel/unwind.c set_reg (struct unw_reg_info *reg, enum unw_where where, int when, unsigned long val) reg 709 arch/ia64/kernel/unwind.c reg->val = val; reg 710 arch/ia64/kernel/unwind.c reg->where = where; reg 711 arch/ia64/kernel/unwind.c if (reg->when == UNW_WHEN_NEVER) reg 712 arch/ia64/kernel/unwind.c reg->when = when; reg 719 arch/ia64/kernel/unwind.c struct unw_reg_info *reg; reg 721 arch/ia64/kernel/unwind.c for (reg = hi; reg >= lo; --reg) { reg 722 arch/ia64/kernel/unwind.c if (reg->where == UNW_WHERE_SPILL_HOME) { reg 723 arch/ia64/kernel/unwind.c reg->where = UNW_WHERE_PSPREL; reg 725 arch/ia64/kernel/unwind.c reg->val = *offp; reg 733 arch/ia64/kernel/unwind.c struct unw_reg_info *reg; reg 735 arch/ia64/kernel/unwind.c for (reg = *regp; reg <= lim; ++reg) { reg 736 arch/ia64/kernel/unwind.c if (reg->where == UNW_WHERE_SPILL_HOME) { reg 737 arch/ia64/kernel/unwind.c reg->when = t; reg 738 arch/ia64/kernel/unwind.c *regp = reg + 1; reg 748 arch/ia64/kernel/unwind.c struct unw_reg_info *reg; reg 757 arch/ia64/kernel/unwind.c reg = sr->curr.reg + unw.save_order[i]; reg 758 arch/ia64/kernel/unwind.c if (reg->where == UNW_WHERE_GR_SAVE) { reg 759 arch/ia64/kernel/unwind.c reg->where = UNW_WHERE_GR; reg 760 arch/ia64/kernel/unwind.c reg->val = sr->gr_save_loc++; reg 778 arch/ia64/kernel/unwind.c regs[0] = sr->curr.reg + UNW_REG_F2; reg 779 arch/ia64/kernel/unwind.c regs[1] = sr->curr.reg + UNW_REG_R4; reg 780 arch/ia64/kernel/unwind.c regs[2] = sr->curr.reg + UNW_REG_B1; reg 787 arch/ia64/kernel/unwind.c spill_next_when(®s[kind - 1], sr->curr.reg + limit[kind - 1], reg 796 arch/ia64/kernel/unwind.c alloc_spill_area(&off, 16, sr->curr.reg + UNW_REG_F2, sr->curr.reg + UNW_REG_F31); reg 797 arch/ia64/kernel/unwind.c alloc_spill_area(&off, 8, sr->curr.reg + UNW_REG_B1, sr->curr.reg + UNW_REG_B5); reg 798 arch/ia64/kernel/unwind.c alloc_spill_area(&off, 8, sr->curr.reg + UNW_REG_R4, sr->curr.reg + UNW_REG_R7); reg 838 arch/ia64/kernel/unwind.c set_reg(sr->curr.reg + unw.save_order[i], UNW_WHERE_GR, reg 872 arch/ia64/kernel/unwind.c set_reg(sr->curr.reg + UNW_REG_B1 + i, UNW_WHERE_GR, reg 885 arch/ia64/kernel/unwind.c set_reg(sr->curr.reg + UNW_REG_B1 + i, UNW_WHERE_SPILL_HOME, reg 900 arch/ia64/kernel/unwind.c set_reg(sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_SPILL_HOME, reg 909 arch/ia64/kernel/unwind.c set_reg(sr->curr.reg + base + i, UNW_WHERE_SPILL_HOME, reg 924 arch/ia64/kernel/unwind.c set_reg(sr->curr.reg + UNW_REG_F2 + i, UNW_WHERE_SPILL_HOME, reg 939 arch/ia64/kernel/unwind.c set_reg(sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_GR, reg 952 arch/ia64/kernel/unwind.c set_reg(sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_SPILL_HOME, reg 963 arch/ia64/kernel/unwind.c set_reg(sr->curr.reg + UNW_REG_PSP, UNW_WHERE_NONE, reg 970 arch/ia64/kernel/unwind.c sr->curr.reg[UNW_REG_PSP].when = sr->region_start + min_t(int, t, sr->region_len - 1); reg 974 arch/ia64/kernel/unwind.c desc_reg_gr (unsigned char reg, unsigned char dst, struct unw_state_record *sr) reg 976 arch/ia64/kernel/unwind.c set_reg(sr->curr.reg + reg, UNW_WHERE_GR, sr->region_start + sr->region_len - 1, dst); reg 980 arch/ia64/kernel/unwind.c desc_reg_psprel (unsigned char reg, unw_word pspoff, struct unw_state_record *sr) reg 982 arch/ia64/kernel/unwind.c set_reg(sr->curr.reg + reg, UNW_WHERE_PSPREL, sr->region_start + sr->region_len - 1, reg 987 arch/ia64/kernel/unwind.c desc_reg_sprel (unsigned char reg, unw_word spoff, struct unw_state_record *sr) reg 989 arch/ia64/kernel/unwind.c set_reg(sr->curr.reg + reg, UNW_WHERE_SPREL, sr->region_start + sr->region_len - 1, reg 1002 arch/ia64/kernel/unwind.c struct unw_reg_info *reg = sr->curr.reg + regnum; reg 1004 arch/ia64/kernel/unwind.c if (reg->where == UNW_WHERE_NONE) reg 1005 arch/ia64/kernel/unwind.c reg->where = UNW_WHERE_GR_SAVE; reg 1006 arch/ia64/kernel/unwind.c reg->when = sr->region_start + min_t(int, t, sr->region_len - 1); reg 1092 arch/ia64/kernel/unwind.c r = sr->curr.reg + decode_abreg(abreg, 0); reg 1113 arch/ia64/kernel/unwind.c r = sr->curr.reg + decode_abreg(abreg, 0); reg 1128 arch/ia64/kernel/unwind.c r = sr->curr.reg + decode_abreg(abreg, 1); reg 1143 arch/ia64/kernel/unwind.c r = sr->curr.reg + decode_abreg(abreg, 1); reg 1359 arch/ia64/kernel/unwind.c struct unw_reg_info *r = sr->curr.reg + i; reg 1404 arch/ia64/kernel/unwind.c struct unw_reg_info *r = sr->curr.reg + i; reg 1546 arch/ia64/kernel/unwind.c for (r = sr.curr.reg; r < sr.curr.reg + UNW_NUM_REGS; ++r) reg 1588 arch/ia64/kernel/unwind.c sr.curr.reg[UNW_REG_RP].where = UNW_WHERE_BR; reg 1589 arch/ia64/kernel/unwind.c sr.curr.reg[UNW_REG_RP].when = -1; reg 1590 arch/ia64/kernel/unwind.c sr.curr.reg[UNW_REG_RP].val = 0; reg 1612 arch/ia64/kernel/unwind.c sr.curr.reg[UNW_REG_PSP].val = 0; reg 1613 arch/ia64/kernel/unwind.c sr.curr.reg[UNW_REG_PSP].where = UNW_WHERE_NONE; reg 1614 arch/ia64/kernel/unwind.c sr.curr.reg[UNW_REG_PSP].when = UNW_WHEN_NEVER; reg 1615 arch/ia64/kernel/unwind.c for (r = sr.curr.reg; r < sr.curr.reg + UNW_NUM_REGS; ++r) reg 1631 arch/ia64/kernel/unwind.c if (sr.curr.reg[UNW_REG_RP].when >= sr.when_target) { reg 1632 arch/ia64/kernel/unwind.c sr.curr.reg[UNW_REG_RP].where = UNW_WHERE_BR; reg 1633 arch/ia64/kernel/unwind.c sr.curr.reg[UNW_REG_RP].when = -1; reg 1634 arch/ia64/kernel/unwind.c sr.curr.reg[UNW_REG_RP].val = sr.return_link_reg; reg 1636 arch/ia64/kernel/unwind.c __func__, ip, sr.curr.reg[UNW_REG_RP].where, reg 1637 arch/ia64/kernel/unwind.c sr.curr.reg[UNW_REG_RP].val); reg 1643 arch/ia64/kernel/unwind.c for (r = sr.curr.reg; r < sr.curr.reg + UNW_NUM_REGS; ++r) { reg 1645 arch/ia64/kernel/unwind.c UNW_DPRINT(1, " %s <- ", unw.preg_name[r - sr.curr.reg]); reg 1653 arch/ia64/kernel/unwind.c UNW_DPRINT(1, "%s+0x%lx", unw.preg_name[r - sr.curr.reg], r->val); reg 1673 arch/ia64/kernel/unwind.c if (sr.when_target > sr.curr.reg[UNW_REG_PSP].when reg 1674 arch/ia64/kernel/unwind.c && (sr.curr.reg[UNW_REG_PSP].where == UNW_WHERE_NONE) reg 1675 arch/ia64/kernel/unwind.c && sr.curr.reg[UNW_REG_PSP].val != 0) { reg 1679 arch/ia64/kernel/unwind.c insn.val = sr.curr.reg[UNW_REG_PSP].val; /* frame size */ reg 1684 arch/ia64/kernel/unwind.c if (sr.when_target < sr.curr.reg[UNW_REG_PRI_UNAT_GR].when) reg 1686 arch/ia64/kernel/unwind.c else if (sr.when_target < sr.curr.reg[UNW_REG_PRI_UNAT_MEM].when) reg 1688 arch/ia64/kernel/unwind.c else if (sr.curr.reg[UNW_REG_PRI_UNAT_MEM].when > sr.curr.reg[UNW_REG_PRI_UNAT_GR].when) reg 85 arch/ia64/kernel/unwind_i.h struct unw_reg_info reg[UNW_NUM_REGS]; /* register save locations */ reg 40 arch/ia64/pci/pci.c #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \ reg 41 arch/ia64/pci/pci.c (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg)) reg 45 arch/ia64/pci/pci.c #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \ reg 46 arch/ia64/pci/pci.c (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg)) reg 49 arch/ia64/pci/pci.c int reg, int len, u32 *value) reg 54 arch/ia64/pci/pci.c if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) reg 57 arch/ia64/pci/pci.c if ((seg | reg) <= 255) { reg 58 arch/ia64/pci/pci.c addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); reg 61 arch/ia64/pci/pci.c addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); reg 76 arch/ia64/pci/pci.c int reg, int len, u32 value) reg 81 arch/ia64/pci/pci.c if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) reg 84 arch/ia64/pci/pci.c if ((seg | reg) <= 255) { reg 85 arch/ia64/pci/pci.c addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); reg 88 arch/ia64/pci/pci.c addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); reg 186 arch/m68k/atari/debug.c #define SCC_WRITE(reg, val) \ reg 188 arch/m68k/atari/debug.c atari_scc.cha_b_ctrl = (reg); \ reg 123 arch/m68k/atari/time.c #define RTC_READ(reg) \ reg 125 arch/m68k/atari/time.c (void) atari_writeb(reg,&tt_rtc.regsel); \ reg 130 arch/m68k/atari/time.c #define RTC_WRITE(reg,val) \ reg 132 arch/m68k/atari/time.c atari_writeb(reg,&tt_rtc.regsel); \ reg 137 arch/m68k/fpsp040/fpsp.h .set FPSR_SHADOW,LV-64 | fpsr shadow reg reg 139 arch/m68k/fpsp040/fpsp.h .set FPIARCU,LV-60 | Instr. addr. reg. for CU (4 bytes) reg 141 arch/m68k/fpsp040/fpsp.h .set CMDREG2B,LV-52 | cmd reg for machine 2 reg 142 arch/m68k/fpsp040/fpsp.h .set CMDREG3B,LV-48 | cmd reg for E3 exceptions (2 bytes) reg 172 arch/m68k/fpsp040/fpsp.h .set CMDREG1B,LV-36 | cmd reg for E1 exceptions (2 bytes) reg 150 arch/m68k/hp300/config.c static inline unsigned char hp300_rtc_read(unsigned char reg) reg 160 arch/m68k/hp300/config.c rtc_write_data(reg); reg 175 arch/m68k/hp300/config.c static inline unsigned char hp300_rtc_write(unsigned char reg, reg 186 arch/m68k/hp300/config.c rtc_write_data((val << 4) | reg); reg 22 arch/m68k/include/asm/MC68328.h #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) reg 23 arch/m68k/include/asm/MC68EZ328.h #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) reg 25 arch/m68k/include/asm/MC68VZ328.h #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) reg 470 arch/m68k/include/asm/atarihw.h u_long reg[256]; reg 117 arch/m68k/include/asm/atariints.h { unsigned char mask, *reg; reg 120 arch/m68k/include/asm/atariints.h reg = (unsigned char *)&st_mfp.int_en_a + type*4 + reg 122 arch/m68k/include/asm/atariints.h return( *reg & mask ); reg 127 arch/m68k/include/asm/atariints.h { unsigned char mask, *reg; reg 130 arch/m68k/include/asm/atariints.h reg = (unsigned char *)&st_mfp.int_en_a + type*4 + reg 133 arch/m68k/include/asm/atariints.h : : "di" (mask), "m" (*reg) : "memory" ); reg 138 arch/m68k/include/asm/atariints.h { unsigned char mask, *reg; reg 141 arch/m68k/include/asm/atariints.h reg = (unsigned char *)&st_mfp.int_en_a + type*4 + reg 145 arch/m68k/include/asm/atariints.h : : "di" (mask), "m" (*reg) : "memory" ); reg 148 arch/m68k/include/asm/atariints.h : : "di" (mask), "m" (*reg) : "memory" ); reg 229 arch/m68k/include/asm/entry.h .macro get_current reg=%d0 reg 93 arch/m68k/include/asm/mcfwdebug.h static inline void wdebug(int reg, unsigned long data) { reg 101 arch/m68k/include/asm/mcfwdebug.h dbg[0] = 0x2c80 | (reg & 0xf); reg 38 arch/m68k/include/asm/uaccess_mm.h #define __put_user_asm(res, x, ptr, bwl, reg, err) \ reg 54 arch/m68k/include/asm/uaccess_mm.h : #reg (x), "i" (err)) reg 109 arch/m68k/include/asm/uaccess_mm.h #define __get_user_asm(res, x, ptr, type, bwl, reg, err) ({ \ reg 125 arch/m68k/include/asm/uaccess_mm.h : "+d" (res), "=&" #reg (__gu_val) \ reg 100 arch/m68k/include/asm/uaccess_no.h #define __get_user_asm(err,x,ptr,bwl,reg) \ reg 44 arch/m68k/kernel/ptrace.c #define PT_REG(reg) ((long)&((struct pt_regs *)0)->reg) reg 45 arch/m68k/kernel/ptrace.c #define SW_REG(reg) ((long)&((struct switch_stack *)0)->reg \ reg 99 arch/m68k/mac/misc.c int i, reg; reg 102 arch/m68k/mac/misc.c reg = via1[vBufB] & ~VIA1B_vRTCClk; reg 112 arch/m68k/mac/misc.c via1[vBufB] = reg; reg 113 arch/m68k/mac/misc.c via1[vBufB] = reg | VIA1B_vRTCClk; reg 126 arch/m68k/mac/misc.c int i, reg, bit; reg 128 arch/m68k/mac/misc.c reg = via1[vBufB] & ~(VIA1B_vRTCClk | VIA1B_vRTCData); reg 135 arch/m68k/mac/misc.c via1[vBufB] = reg | bit; reg 136 arch/m68k/mac/misc.c via1[vBufB] = reg | bit | VIA1B_vRTCClk; reg 102 arch/m68k/math-emu/fp_decode.h | decode destination format for fmove reg,ea reg 107 arch/m68k/math-emu/fp_decode.h | decode source register for fmove reg,ea reg 271 arch/m68k/math-emu/fp_decode.h lea (-12,%a0),%a1 | setup to addr of 1st reg to move reg 65 arch/m68k/math-emu/fp_emu.h register struct fp_ext *reg asm ("a0") = fpreg; \ reg 69 arch/m68k/math-emu/fp_emu.h : "=d" (res) : "a" (reg) \ reg 21 arch/m68k/math-emu/multi_arith.h static inline void fp_denormalize(struct fp_ext *reg, unsigned int cnt) reg 23 arch/m68k/math-emu/multi_arith.h reg->exp += cnt; reg 27 arch/m68k/math-emu/multi_arith.h reg->lowmant = reg->mant.m32[1] << (8 - cnt); reg 28 arch/m68k/math-emu/multi_arith.h reg->mant.m32[1] = (reg->mant.m32[1] >> cnt) | reg 29 arch/m68k/math-emu/multi_arith.h (reg->mant.m32[0] << (32 - cnt)); reg 30 arch/m68k/math-emu/multi_arith.h reg->mant.m32[0] = reg->mant.m32[0] >> cnt; reg 33 arch/m68k/math-emu/multi_arith.h reg->lowmant = reg->mant.m32[1] >> (cnt - 8); reg 34 arch/m68k/math-emu/multi_arith.h if (reg->mant.m32[1] << (40 - cnt)) reg 35 arch/m68k/math-emu/multi_arith.h reg->lowmant |= 1; reg 36 arch/m68k/math-emu/multi_arith.h reg->mant.m32[1] = (reg->mant.m32[1] >> cnt) | reg 37 arch/m68k/math-emu/multi_arith.h (reg->mant.m32[0] << (32 - cnt)); reg 38 arch/m68k/math-emu/multi_arith.h reg->mant.m32[0] = reg->mant.m32[0] >> cnt; reg 41 arch/m68k/math-emu/multi_arith.h asm volatile ("bfextu %1{%2,#8},%0" : "=d" (reg->lowmant) reg 42 arch/m68k/math-emu/multi_arith.h : "m" (reg->mant.m32[0]), "d" (64 - cnt)); reg 43 arch/m68k/math-emu/multi_arith.h if (reg->mant.m32[1] << (40 - cnt)) reg 44 arch/m68k/math-emu/multi_arith.h reg->lowmant |= 1; reg 45 arch/m68k/math-emu/multi_arith.h reg->mant.m32[1] = reg->mant.m32[0] >> (cnt - 32); reg 46 arch/m68k/math-emu/multi_arith.h reg->mant.m32[0] = 0; reg 49 arch/m68k/math-emu/multi_arith.h reg->lowmant = reg->mant.m32[0] >> (cnt - 40); reg 50 arch/m68k/math-emu/multi_arith.h if ((reg->mant.m32[0] << (72 - cnt)) || reg->mant.m32[1]) reg 51 arch/m68k/math-emu/multi_arith.h reg->lowmant |= 1; reg 52 arch/m68k/math-emu/multi_arith.h reg->mant.m32[1] = reg->mant.m32[0] >> (cnt - 32); reg 53 arch/m68k/math-emu/multi_arith.h reg->mant.m32[0] = 0; reg 56 arch/m68k/math-emu/multi_arith.h reg->lowmant = reg->mant.m32[0] || reg->mant.m32[1]; reg 57 arch/m68k/math-emu/multi_arith.h reg->mant.m32[0] = 0; reg 58 arch/m68k/math-emu/multi_arith.h reg->mant.m32[1] = 0; reg 63 arch/m68k/math-emu/multi_arith.h static inline int fp_overnormalize(struct fp_ext *reg) reg 67 arch/m68k/math-emu/multi_arith.h if (reg->mant.m32[0]) { reg 68 arch/m68k/math-emu/multi_arith.h asm ("bfffo %1{#0,#32},%0" : "=d" (shift) : "dm" (reg->mant.m32[0])); reg 69 arch/m68k/math-emu/multi_arith.h reg->mant.m32[0] = (reg->mant.m32[0] << shift) | (reg->mant.m32[1] >> (32 - shift)); reg 70 arch/m68k/math-emu/multi_arith.h reg->mant.m32[1] = (reg->mant.m32[1] << shift); reg 72 arch/m68k/math-emu/multi_arith.h asm ("bfffo %1{#0,#32},%0" : "=d" (shift) : "dm" (reg->mant.m32[1])); reg 73 arch/m68k/math-emu/multi_arith.h reg->mant.m32[0] = (reg->mant.m32[1] << shift); reg 74 arch/m68k/math-emu/multi_arith.h reg->mant.m32[1] = 0; reg 97 arch/m68k/math-emu/multi_arith.h static inline int fp_addcarry(struct fp_ext *reg) reg 99 arch/m68k/math-emu/multi_arith.h if (++reg->exp == 0x7fff) { reg 100 arch/m68k/math-emu/multi_arith.h if (reg->mant.m64) reg 102 arch/m68k/math-emu/multi_arith.h reg->mant.m64 = 0; reg 106 arch/m68k/math-emu/multi_arith.h reg->lowmant = (reg->mant.m32[1] << 7) | (reg->lowmant ? 1 : 0); reg 107 arch/m68k/math-emu/multi_arith.h reg->mant.m32[1] = (reg->mant.m32[1] >> 1) | reg 108 arch/m68k/math-emu/multi_arith.h (reg->mant.m32[0] << 31); reg 109 arch/m68k/math-emu/multi_arith.h reg->mant.m32[0] = (reg->mant.m32[0] >> 1) | 0x80000000; reg 116 arch/microblaze/mm/init.c struct memblock_region *reg; reg 122 arch/microblaze/mm/init.c for_each_memblock(memory, reg) { reg 123 arch/microblaze/mm/init.c memory_start = (u32)reg->base; reg 124 arch/microblaze/mm/init.c lowmem_size = reg->size; reg 173 arch/microblaze/mm/init.c for_each_memblock(memory, reg) { reg 176 arch/microblaze/mm/init.c start_pfn = memblock_region_memory_base_pfn(reg); reg 177 arch/microblaze/mm/init.c end_pfn = memblock_region_memory_end_pfn(reg); reg 24 arch/microblaze/pci/indirect_pci.c u32 bus_no, reg; reg 41 arch/microblaze/pci/indirect_pci.c reg = ((offset & 0xf00) << 16) | (offset & 0xfc); reg 43 arch/microblaze/pci/indirect_pci.c reg = offset & 0xfc; /* Only 3 bits for function */ reg 47 arch/microblaze/pci/indirect_pci.c (devfn << 8) | reg | cfg_type)); reg 50 arch/microblaze/pci/indirect_pci.c (devfn << 8) | reg | cfg_type)); reg 78 arch/microblaze/pci/indirect_pci.c u32 bus_no, reg; reg 95 arch/microblaze/pci/indirect_pci.c reg = ((offset & 0xf00) << 16) | (offset & 0xfc); reg 97 arch/microblaze/pci/indirect_pci.c reg = offset & 0xfc; reg 101 arch/microblaze/pci/indirect_pci.c (devfn << 8) | reg | cfg_type)); reg 104 arch/microblaze/pci/indirect_pci.c (devfn << 8) | reg | cfg_type)); reg 807 arch/microblaze/pci/pci-common.c u32 reg; reg 808 arch/microblaze/pci/pci-common.c pci_read_config_dword(dev, dev->rom_base_reg, ®); reg 809 arch/microblaze/pci/pci-common.c if (reg & PCI_ROM_ADDRESS_ENABLE) { reg 814 arch/microblaze/pci/pci-common.c reg & ~PCI_ROM_ADDRESS_ENABLE); reg 174 arch/mips/alchemy/common/clock.c unsigned long reg; /* au1300 has also AUXPLL2 */ reg 184 arch/mips/alchemy/common/clock.c return (alchemy_rdsys(a->reg) & 0xff) * parent_rate; reg 203 arch/mips/alchemy/common/clock.c alchemy_wrsys(d, a->reg); reg 235 arch/mips/alchemy/common/clock.c unsigned long reg) reg 251 arch/mips/alchemy/common/clock.c a->reg = reg; reg 361 arch/mips/alchemy/common/clock.c unsigned long reg; /* SYS_FREQCTRL0/1 */ reg 490 arch/mips/alchemy/common/clock.c v = alchemy_rdsys(c->reg); reg 492 arch/mips/alchemy/common/clock.c alchemy_wrsys(v, c->reg); reg 501 arch/mips/alchemy/common/clock.c unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 1); reg 512 arch/mips/alchemy/common/clock.c v = alchemy_rdsys(c->reg); reg 514 arch/mips/alchemy/common/clock.c alchemy_wrsys(v, c->reg); reg 524 arch/mips/alchemy/common/clock.c v = alchemy_rdsys(c->reg); reg 529 arch/mips/alchemy/common/clock.c alchemy_wrsys(v, c->reg); reg 539 arch/mips/alchemy/common/clock.c return (alchemy_rdsys(c->reg) >> c->shift) & 1; reg 553 arch/mips/alchemy/common/clock.c v = alchemy_rdsys(c->reg); reg 556 arch/mips/alchemy/common/clock.c alchemy_wrsys(v, c->reg); reg 566 arch/mips/alchemy/common/clock.c unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 2); reg 592 arch/mips/alchemy/common/clock.c unsigned long v = alchemy_rdsys(c->reg); reg 596 arch/mips/alchemy/common/clock.c alchemy_wrsys(v, c->reg); reg 617 arch/mips/alchemy/common/clock.c return ((alchemy_rdsys(c->reg) >> c->shift) & 3) != 0; reg 626 arch/mips/alchemy/common/clock.c v = alchemy_rdsys(c->reg); reg 628 arch/mips/alchemy/common/clock.c alchemy_wrsys(v, c->reg); reg 673 arch/mips/alchemy/common/clock.c v = alchemy_rdsys(c->reg) & (1 << 30); /* test "scale" bit */ reg 678 arch/mips/alchemy/common/clock.c v = alchemy_rdsys(c->reg); reg 681 arch/mips/alchemy/common/clock.c alchemy_wrsys(v, c->reg); reg 694 arch/mips/alchemy/common/clock.c v = alchemy_rdsys(c->reg); reg 708 arch/mips/alchemy/common/clock.c if (alchemy_rdsys(c->reg) & (1 << 30)) { reg 778 arch/mips/alchemy/common/clock.c a->reg = AU1000_SYS_FREQCTRL1; reg 781 arch/mips/alchemy/common/clock.c a->reg = AU1000_SYS_FREQCTRL0; reg 789 arch/mips/alchemy/common/clock.c v = alchemy_rdsys(a->reg); reg 815 arch/mips/alchemy/common/clock.c unsigned long v = alchemy_rdsys(c->reg); reg 822 arch/mips/alchemy/common/clock.c unsigned long v = alchemy_rdsys(c->reg); reg 826 arch/mips/alchemy/common/clock.c alchemy_wrsys(v, c->reg); reg 849 arch/mips/alchemy/common/clock.c v = alchemy_rdsys(c->reg); reg 851 arch/mips/alchemy/common/clock.c alchemy_wrsys(v, c->reg); reg 881 arch/mips/alchemy/common/clock.c unsigned long v = (alchemy_rdsys(c->reg) >> c->shift) & 3; reg 910 arch/mips/alchemy/common/clock.c v = alchemy_rdsys(c->reg); reg 913 arch/mips/alchemy/common/clock.c alchemy_wrsys(v, c->reg); reg 1001 arch/mips/alchemy/common/clock.c a->reg = AU1000_SYS_CLKSRC; reg 1008 arch/mips/alchemy/common/clock.c v = alchemy_rdsys(a->reg); reg 392 arch/mips/alchemy/common/usb.c static inline int au1000_usb_init(unsigned long rb, int reg) reg 394 arch/mips/alchemy/common/usb.c void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg); reg 50 arch/mips/alchemy/devboards/bcsr.c unsigned short bcsr_read(enum bcsr_id reg) reg 55 arch/mips/alchemy/devboards/bcsr.c spin_lock_irqsave(&bcsr_regs[reg].lock, flags); reg 56 arch/mips/alchemy/devboards/bcsr.c r = __raw_readw(bcsr_regs[reg].raddr); reg 57 arch/mips/alchemy/devboards/bcsr.c spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags); reg 62 arch/mips/alchemy/devboards/bcsr.c void bcsr_write(enum bcsr_id reg, unsigned short val) reg 66 arch/mips/alchemy/devboards/bcsr.c spin_lock_irqsave(&bcsr_regs[reg].lock, flags); reg 67 arch/mips/alchemy/devboards/bcsr.c __raw_writew(val, bcsr_regs[reg].raddr); reg 69 arch/mips/alchemy/devboards/bcsr.c spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags); reg 73 arch/mips/alchemy/devboards/bcsr.c void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set) reg 78 arch/mips/alchemy/devboards/bcsr.c spin_lock_irqsave(&bcsr_regs[reg].lock, flags); reg 79 arch/mips/alchemy/devboards/bcsr.c r = __raw_readw(bcsr_regs[reg].raddr); reg 82 arch/mips/alchemy/devboards/bcsr.c __raw_writew(r, bcsr_regs[reg].raddr); reg 84 arch/mips/alchemy/devboards/bcsr.c spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags); reg 198 arch/mips/ar7/gpio.c u32 reg; reg 269 arch/mips/ar7/gpio.c pin_sel_reg = gpio_cfg.reg - 1; reg 19 arch/mips/ar7/irq.c #define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10) reg 20 arch/mips/ar7/irq.c #define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8) reg 37 arch/mips/ath25/ar2315.c static inline u32 ar2315_rst_reg_read(u32 reg) reg 39 arch/mips/ath25/ar2315.c return __raw_readl(ar2315_rst_base + reg); reg 42 arch/mips/ath25/ar2315.c static inline void ar2315_rst_reg_write(u32 reg, u32 val) reg 44 arch/mips/ath25/ar2315.c __raw_writel(val, ar2315_rst_base + reg); reg 47 arch/mips/ath25/ar2315.c static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val) reg 49 arch/mips/ath25/ar2315.c u32 ret = ar2315_rst_reg_read(reg); reg 53 arch/mips/ath25/ar2315.c ar2315_rst_reg_write(reg, ret); reg 38 arch/mips/ath25/ar5312.c static inline u32 ar5312_rst_reg_read(u32 reg) reg 40 arch/mips/ath25/ar5312.c return __raw_readl(ar5312_rst_base + reg); reg 43 arch/mips/ath25/ar5312.c static inline void ar5312_rst_reg_write(u32 reg, u32 val) reg 45 arch/mips/ath25/ar5312.c __raw_writel(val, ar5312_rst_base + reg); reg 48 arch/mips/ath25/ar5312.c static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val) reg 50 arch/mips/ath25/ar5312.c u32 ret = ar5312_rst_reg_read(reg); reg 54 arch/mips/ath25/ar5312.c ar5312_rst_reg_write(reg, ret); reg 18 arch/mips/ath25/early_printk.c static inline void prom_uart_wr(void __iomem *base, unsigned reg, reg 21 arch/mips/ath25/early_printk.c __raw_writel(ch, base + 4 * reg); reg 24 arch/mips/ath25/early_printk.c static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) reg 26 arch/mips/ath25/early_printk.c return __raw_readl(base + 4 * reg); reg 56 arch/mips/ath79/common.c void ath79_ddr_wb_flush(u32 reg) reg 58 arch/mips/ath79/common.c void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4); reg 90 arch/mips/ath79/common.c u32 reg; reg 94 arch/mips/ath79/common.c reg = AR71XX_RESET_REG_RESET_MODULE; reg 96 arch/mips/ath79/common.c reg = AR724X_RESET_REG_RESET_MODULE; reg 98 arch/mips/ath79/common.c reg = AR913X_RESET_REG_RESET_MODULE; reg 100 arch/mips/ath79/common.c reg = AR933X_RESET_REG_RESET_MODULE; reg 102 arch/mips/ath79/common.c reg = AR934X_RESET_REG_RESET_MODULE; reg 104 arch/mips/ath79/common.c reg = QCA953X_RESET_REG_RESET_MODULE; reg 106 arch/mips/ath79/common.c reg = QCA955X_RESET_REG_RESET_MODULE; reg 108 arch/mips/ath79/common.c reg = QCA956X_RESET_REG_RESET_MODULE; reg 113 arch/mips/ath79/common.c t = ath79_reset_rr(reg); reg 114 arch/mips/ath79/common.c ath79_reset_wr(reg, t | mask); reg 122 arch/mips/ath79/common.c u32 reg; reg 126 arch/mips/ath79/common.c reg = AR71XX_RESET_REG_RESET_MODULE; reg 128 arch/mips/ath79/common.c reg = AR724X_RESET_REG_RESET_MODULE; reg 130 arch/mips/ath79/common.c reg = AR913X_RESET_REG_RESET_MODULE; reg 132 arch/mips/ath79/common.c reg = AR933X_RESET_REG_RESET_MODULE; reg 134 arch/mips/ath79/common.c reg = AR934X_RESET_REG_RESET_MODULE; reg 136 arch/mips/ath79/common.c reg = QCA953X_RESET_REG_RESET_MODULE; reg 138 arch/mips/ath79/common.c reg = QCA955X_RESET_REG_RESET_MODULE; reg 140 arch/mips/ath79/common.c reg = QCA956X_RESET_REG_RESET_MODULE; reg 145 arch/mips/ath79/common.c t = ath79_reset_rr(reg); reg 146 arch/mips/ath79/common.c ath79_reset_wr(reg, t & ~mask); reg 21 arch/mips/ath79/early_printk.c static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val) reg 26 arch/mips/ath79/early_printk.c t = __raw_readl(reg); reg 45 arch/mips/bcm63xx/clk.c u32 reg; reg 47 arch/mips/bcm63xx/clk.c reg = bcm_perf_readl(PERF_CKCTL_REG); reg 49 arch/mips/bcm63xx/clk.c reg |= mask; reg 51 arch/mips/bcm63xx/clk.c reg &= ~mask; reg 52 arch/mips/bcm63xx/clk.c bcm_perf_writel(reg, PERF_CKCTL_REG); reg 41 arch/mips/bcm63xx/gpio.c u32 reg; reg 50 arch/mips/bcm63xx/gpio.c reg = gpio_out_low_reg; reg 54 arch/mips/bcm63xx/gpio.c reg = GPIO_DATA_HI_REG; reg 64 arch/mips/bcm63xx/gpio.c bcm_gpio_writel(*v, reg); reg 70 arch/mips/bcm63xx/gpio.c u32 reg; reg 77 arch/mips/bcm63xx/gpio.c reg = gpio_out_low_reg; reg 80 arch/mips/bcm63xx/gpio.c reg = GPIO_DATA_HI_REG; reg 84 arch/mips/bcm63xx/gpio.c return !!(bcm_gpio_readl(reg) & mask); reg 90 arch/mips/bcm63xx/gpio.c u32 reg; reg 99 arch/mips/bcm63xx/gpio.c reg = GPIO_CTL_LO_REG; reg 102 arch/mips/bcm63xx/gpio.c reg = GPIO_CTL_HI_REG; reg 107 arch/mips/bcm63xx/gpio.c tmp = bcm_gpio_readl(reg); reg 112 arch/mips/bcm63xx/gpio.c bcm_gpio_writel(tmp, reg); reg 116 arch/mips/bcm63xx/irq.c unsigned reg = (irq / 32) ^ (width/32 - 1); \ reg 126 arch/mips/bcm63xx/irq.c val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\ reg 128 arch/mips/bcm63xx/irq.c bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\ reg 138 arch/mips/bcm63xx/irq.c unsigned reg = (irq / 32) ^ (width/32 - 1); \ reg 148 arch/mips/bcm63xx/irq.c val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\ reg 153 arch/mips/bcm63xx/irq.c bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\ reg 216 arch/mips/bcm63xx/irq.c u32 reg, regaddr; reg 221 arch/mips/bcm63xx/irq.c reg = bcm_perf_readl(regaddr); reg 224 arch/mips/bcm63xx/irq.c reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4); reg 226 arch/mips/bcm63xx/irq.c reg &= ~EXTIRQ_CFG_MASK(irq % 4); reg 228 arch/mips/bcm63xx/irq.c bcm_perf_writel(reg, regaddr); reg 238 arch/mips/bcm63xx/irq.c u32 reg, regaddr; reg 243 arch/mips/bcm63xx/irq.c reg = bcm_perf_readl(regaddr); reg 246 arch/mips/bcm63xx/irq.c reg |= EXTIRQ_CFG_MASK_6348(irq % 4); reg 248 arch/mips/bcm63xx/irq.c reg |= EXTIRQ_CFG_MASK(irq % 4); reg 250 arch/mips/bcm63xx/irq.c bcm_perf_writel(reg, regaddr); reg 261 arch/mips/bcm63xx/irq.c u32 reg, regaddr; reg 266 arch/mips/bcm63xx/irq.c reg = bcm_perf_readl(regaddr); reg 269 arch/mips/bcm63xx/irq.c reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4); reg 271 arch/mips/bcm63xx/irq.c reg |= EXTIRQ_CFG_CLEAR(irq % 4); reg 273 arch/mips/bcm63xx/irq.c bcm_perf_writel(reg, regaddr); reg 281 arch/mips/bcm63xx/irq.c u32 reg, regaddr; reg 319 arch/mips/bcm63xx/irq.c reg = bcm_perf_readl(regaddr); reg 325 arch/mips/bcm63xx/irq.c reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq); reg 327 arch/mips/bcm63xx/irq.c reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq); reg 329 arch/mips/bcm63xx/irq.c reg |= EXTIRQ_CFG_SENSE_6348(irq); reg 331 arch/mips/bcm63xx/irq.c reg &= ~EXTIRQ_CFG_SENSE_6348(irq); reg 333 arch/mips/bcm63xx/irq.c reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq); reg 335 arch/mips/bcm63xx/irq.c reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); reg 346 arch/mips/bcm63xx/irq.c reg |= EXTIRQ_CFG_LEVELSENSE(irq); reg 348 arch/mips/bcm63xx/irq.c reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); reg 350 arch/mips/bcm63xx/irq.c reg |= EXTIRQ_CFG_SENSE(irq); reg 352 arch/mips/bcm63xx/irq.c reg &= ~EXTIRQ_CFG_SENSE(irq); reg 354 arch/mips/bcm63xx/irq.c reg |= EXTIRQ_CFG_BOTHEDGE(irq); reg 356 arch/mips/bcm63xx/irq.c reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); reg 362 arch/mips/bcm63xx/irq.c bcm_perf_writel(reg, regaddr); reg 23 arch/mips/bcm63xx/prom.c u32 reg, mask; reg 51 arch/mips/bcm63xx/prom.c reg = bcm_perf_readl(PERF_CKCTL_REG); reg 52 arch/mips/bcm63xx/prom.c reg &= ~mask; reg 53 arch/mips/bcm63xx/prom.c bcm_perf_writel(reg, PERF_CKCTL_REG); reg 66 arch/mips/bcm63xx/prom.c reg = bcm_readl(BCM_6328_OTP_BASE + reg 69 arch/mips/bcm63xx/prom.c if (reg & OTP_6328_REG3_TP1_DISABLED) reg 34 arch/mips/bcm63xx/setup.c u32 reg; reg 38 arch/mips/bcm63xx/setup.c reg = bcm_perf_readl(PERF_SOFTRESET_REG); reg 39 arch/mips/bcm63xx/setup.c reg &= ~SOFTRESET_6348_ALL; reg 40 arch/mips/bcm63xx/setup.c bcm_perf_writel(reg, PERF_SOFTRESET_REG); reg 43 arch/mips/bcm63xx/setup.c reg = bcm_perf_readl(PERF_SOFTRESET_REG); reg 44 arch/mips/bcm63xx/setup.c reg |= SOFTRESET_6348_ALL; reg 45 arch/mips/bcm63xx/setup.c bcm_perf_writel(reg, PERF_SOFTRESET_REG); reg 67 arch/mips/bcm63xx/setup.c u32 reg, perf_regs[2] = { 0, 0 }; reg 99 arch/mips/bcm63xx/setup.c reg = bcm_perf_readl(perf_regs[i]); reg 101 arch/mips/bcm63xx/setup.c reg &= ~EXTIRQ_CFG_MASK_ALL_6348; reg 102 arch/mips/bcm63xx/setup.c reg |= EXTIRQ_CFG_CLEAR_ALL_6348; reg 104 arch/mips/bcm63xx/setup.c reg &= ~EXTIRQ_CFG_MASK_ALL; reg 105 arch/mips/bcm63xx/setup.c reg |= EXTIRQ_CFG_CLEAR_ALL; reg 107 arch/mips/bcm63xx/setup.c bcm_perf_writel(reg, perf_regs[i]); reg 117 arch/mips/bcm63xx/setup.c reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG); reg 118 arch/mips/bcm63xx/setup.c reg |= SYS_PLL_SOFT_RESET; reg 119 arch/mips/bcm63xx/setup.c bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG); reg 59 arch/mips/bcm63xx/timer.c u32 reg; reg 67 arch/mips/bcm63xx/timer.c reg = bcm_timer_readl(TIMER_CTLx_REG(id)); reg 68 arch/mips/bcm63xx/timer.c reg |= TIMER_CTL_ENABLE_MASK; reg 69 arch/mips/bcm63xx/timer.c bcm_timer_writel(reg, TIMER_CTLx_REG(id)); reg 71 arch/mips/bcm63xx/timer.c reg = bcm_timer_readl(TIMER_IRQSTAT_REG); reg 72 arch/mips/bcm63xx/timer.c reg |= TIMER_IRQSTAT_TIMER_IR_EN(id); reg 73 arch/mips/bcm63xx/timer.c bcm_timer_writel(reg, TIMER_IRQSTAT_REG); reg 83 arch/mips/bcm63xx/timer.c u32 reg; reg 91 arch/mips/bcm63xx/timer.c reg = bcm_timer_readl(TIMER_CTLx_REG(id)); reg 92 arch/mips/bcm63xx/timer.c reg &= ~TIMER_CTL_ENABLE_MASK; reg 93 arch/mips/bcm63xx/timer.c bcm_timer_writel(reg, TIMER_CTLx_REG(id)); reg 95 arch/mips/bcm63xx/timer.c reg = bcm_timer_readl(TIMER_IRQSTAT_REG); reg 96 arch/mips/bcm63xx/timer.c reg &= ~TIMER_IRQSTAT_TIMER_IR_EN(id); reg 97 arch/mips/bcm63xx/timer.c bcm_timer_writel(reg, TIMER_IRQSTAT_REG); reg 153 arch/mips/bcm63xx/timer.c u32 reg, countdown; reg 164 arch/mips/bcm63xx/timer.c reg = bcm_timer_readl(TIMER_CTLx_REG(id)); reg 167 arch/mips/bcm63xx/timer.c reg &= ~TIMER_CTL_MONOTONIC_MASK; reg 169 arch/mips/bcm63xx/timer.c reg |= TIMER_CTL_MONOTONIC_MASK; reg 171 arch/mips/bcm63xx/timer.c reg &= ~TIMER_CTL_COUNTDOWN_MASK; reg 172 arch/mips/bcm63xx/timer.c reg |= countdown; reg 173 arch/mips/bcm63xx/timer.c bcm_timer_writel(reg, TIMER_CTLx_REG(id)); reg 184 arch/mips/bcm63xx/timer.c u32 reg; reg 186 arch/mips/bcm63xx/timer.c reg = bcm_timer_readl(TIMER_IRQSTAT_REG); reg 187 arch/mips/bcm63xx/timer.c reg &= ~TIMER_IRQSTAT_TIMER0_IR_EN; reg 188 arch/mips/bcm63xx/timer.c reg &= ~TIMER_IRQSTAT_TIMER1_IR_EN; reg 189 arch/mips/bcm63xx/timer.c reg &= ~TIMER_IRQSTAT_TIMER2_IR_EN; reg 190 arch/mips/bcm63xx/timer.c bcm_timer_writel(reg, TIMER_IRQSTAT_REG); reg 482 arch/mips/cavium-octeon/octeon-platform.c const __be32 *reg; reg 546 arch/mips/cavium-octeon/octeon-platform.c reg = fdt_getprop(initial_boot_params, phy, "reg", NULL); reg 547 arch/mips/cavium-octeon/octeon-platform.c if (phy_addr == be32_to_cpup(reg)) reg 66 arch/mips/emma/markeins/irq.c u32 reg; reg 68 arch/mips/emma/markeins/irq.c reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); reg 69 arch/mips/emma/markeins/irq.c reg |= 1 << irq; reg 70 arch/mips/emma/markeins/irq.c emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); reg 76 arch/mips/emma/markeins/irq.c u32 reg; reg 78 arch/mips/emma/markeins/irq.c reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); reg 79 arch/mips/emma/markeins/irq.c reg &= ~(1 << irq); reg 80 arch/mips/emma/markeins/irq.c emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); reg 102 arch/mips/emma/markeins/irq.c u32 reg; reg 104 arch/mips/emma/markeins/irq.c reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); reg 105 arch/mips/emma/markeins/irq.c reg |= 1 << irq; reg 106 arch/mips/emma/markeins/irq.c emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); reg 112 arch/mips/emma/markeins/irq.c u32 reg; reg 114 arch/mips/emma/markeins/irq.c reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); reg 115 arch/mips/emma/markeins/irq.c reg &= ~(1 << irq); reg 116 arch/mips/emma/markeins/irq.c emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); reg 129 arch/mips/emma/markeins/irq.c u32 reg; reg 133 arch/mips/emma/markeins/irq.c reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); reg 134 arch/mips/emma/markeins/irq.c reg &= ~(1 << irq); reg 135 arch/mips/emma/markeins/irq.c emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); reg 238 arch/mips/emma/markeins/irq.c u32 reg; reg 255 arch/mips/emma/markeins/irq.c reg = emma2rh_in32(EMMA2RH_GPIO_DIR); reg 256 arch/mips/emma/markeins/irq.c emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI); reg 258 arch/mips/emma/markeins/irq.c reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); reg 259 arch/mips/emma/markeins/irq.c emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI); reg 261 arch/mips/emma/markeins/irq.c reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE); reg 262 arch/mips/emma/markeins/irq.c emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI); reg 263 arch/mips/emma/markeins/irq.c reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A); reg 264 arch/mips/emma/markeins/irq.c emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI)); reg 52 arch/mips/emma/markeins/setup.c u32 reg; reg 55 arch/mips/emma/markeins/setup.c reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0); reg 56 arch/mips/emma/markeins/setup.c reg = (reg >> 4) & 0x3; reg 58 arch/mips/emma/markeins/setup.c return emma2rh_clock[reg]; reg 63 arch/mips/emma/markeins/setup.c u32 reg; reg 67 arch/mips/emma/markeins/setup.c reg = emma2rh_in32(EMMA2RH_BHIF_STRAP_0); reg 68 arch/mips/emma/markeins/setup.c if ((reg & 0x3) == 0) reg 69 arch/mips/emma/markeins/setup.c reg = (reg >> 6) & 0x3; reg 71 arch/mips/emma/markeins/setup.c reg = emma2rh_in32(EMMA2RH_BHIF_MAIN_CTRL); reg 72 arch/mips/emma/markeins/setup.c reg = (reg >> 4) & 0x3; reg 74 arch/mips/emma/markeins/setup.c mips_hpt_frequency = (bus_frequency * (4 + reg)) / 4 / 2; reg 19 arch/mips/include/asm/asm-eva.h #define kernel_ll(reg, addr) "ll " reg ", " addr "\n" reg 20 arch/mips/include/asm/asm-eva.h #define kernel_sc(reg, addr) "sc " reg ", " addr "\n" reg 21 arch/mips/include/asm/asm-eva.h #define kernel_lw(reg, addr) "lw " reg ", " addr "\n" reg 22 arch/mips/include/asm/asm-eva.h #define kernel_lwl(reg, addr) "lwl " reg ", " addr "\n" reg 23 arch/mips/include/asm/asm-eva.h #define kernel_lwr(reg, addr) "lwr " reg ", " addr "\n" reg 24 arch/mips/include/asm/asm-eva.h #define kernel_lh(reg, addr) "lh " reg ", " addr "\n" reg 25 arch/mips/include/asm/asm-eva.h #define kernel_lb(reg, addr) "lb " reg ", " addr "\n" reg 26 arch/mips/include/asm/asm-eva.h #define kernel_lbu(reg, addr) "lbu " reg ", " addr "\n" reg 27 arch/mips/include/asm/asm-eva.h #define kernel_sw(reg, addr) "sw " reg ", " addr "\n" reg 28 arch/mips/include/asm/asm-eva.h #define kernel_swl(reg, addr) "swl " reg ", " addr "\n" reg 29 arch/mips/include/asm/asm-eva.h #define kernel_swr(reg, addr) "swr " reg ", " addr "\n" reg 30 arch/mips/include/asm/asm-eva.h #define kernel_sh(reg, addr) "sh " reg ", " addr "\n" reg 31 arch/mips/include/asm/asm-eva.h #define kernel_sb(reg, addr) "sb " reg ", " addr "\n" reg 38 arch/mips/include/asm/asm-eva.h #define kernel_sd(reg, addr) user_sw(reg, addr) reg 39 arch/mips/include/asm/asm-eva.h #define kernel_ld(reg, addr) user_lw(reg, addr) reg 41 arch/mips/include/asm/asm-eva.h #define kernel_sd(reg, addr) "sd " reg", " addr "\n" reg 42 arch/mips/include/asm/asm-eva.h #define kernel_ld(reg, addr) "ld " reg", " addr "\n" reg 47 arch/mips/include/asm/asm-eva.h #define __BUILD_EVA_INSN(insn, reg, addr) \ reg 51 arch/mips/include/asm/asm-eva.h " "insn" "reg", "addr "\n" \ reg 56 arch/mips/include/asm/asm-eva.h #define user_ll(reg, addr) __BUILD_EVA_INSN("lle", reg, addr) reg 57 arch/mips/include/asm/asm-eva.h #define user_sc(reg, addr) __BUILD_EVA_INSN("sce", reg, addr) reg 58 arch/mips/include/asm/asm-eva.h #define user_lw(reg, addr) __BUILD_EVA_INSN("lwe", reg, addr) reg 59 arch/mips/include/asm/asm-eva.h #define user_lwl(reg, addr) __BUILD_EVA_INSN("lwle", reg, addr) reg 60 arch/mips/include/asm/asm-eva.h #define user_lwr(reg, addr) __BUILD_EVA_INSN("lwre", reg, addr) reg 61 arch/mips/include/asm/asm-eva.h #define user_lh(reg, addr) __BUILD_EVA_INSN("lhe", reg, addr) reg 62 arch/mips/include/asm/asm-eva.h #define user_lb(reg, addr) __BUILD_EVA_INSN("lbe", reg, addr) reg 63 arch/mips/include/asm/asm-eva.h #define user_lbu(reg, addr) __BUILD_EVA_INSN("lbue", reg, addr) reg 65 arch/mips/include/asm/asm-eva.h #define user_ld(reg, addr) user_lw(reg, addr) reg 66 arch/mips/include/asm/asm-eva.h #define user_sw(reg, addr) __BUILD_EVA_INSN("swe", reg, addr) reg 67 arch/mips/include/asm/asm-eva.h #define user_swl(reg, addr) __BUILD_EVA_INSN("swle", reg, addr) reg 68 arch/mips/include/asm/asm-eva.h #define user_swr(reg, addr) __BUILD_EVA_INSN("swre", reg, addr) reg 69 arch/mips/include/asm/asm-eva.h #define user_sh(reg, addr) __BUILD_EVA_INSN("she", reg, addr) reg 70 arch/mips/include/asm/asm-eva.h #define user_sb(reg, addr) __BUILD_EVA_INSN("sbe", reg, addr) reg 72 arch/mips/include/asm/asm-eva.h #define user_sd(reg, addr) user_sw(reg, addr) reg 78 arch/mips/include/asm/asm-eva.h #define user_ll(reg, addr) kernel_ll(reg, addr) reg 79 arch/mips/include/asm/asm-eva.h #define user_sc(reg, addr) kernel_sc(reg, addr) reg 80 arch/mips/include/asm/asm-eva.h #define user_lw(reg, addr) kernel_lw(reg, addr) reg 81 arch/mips/include/asm/asm-eva.h #define user_lwl(reg, addr) kernel_lwl(reg, addr) reg 82 arch/mips/include/asm/asm-eva.h #define user_lwr(reg, addr) kernel_lwr(reg, addr) reg 83 arch/mips/include/asm/asm-eva.h #define user_lh(reg, addr) kernel_lh(reg, addr) reg 84 arch/mips/include/asm/asm-eva.h #define user_lb(reg, addr) kernel_lb(reg, addr) reg 85 arch/mips/include/asm/asm-eva.h #define user_lbu(reg, addr) kernel_lbu(reg, addr) reg 86 arch/mips/include/asm/asm-eva.h #define user_sw(reg, addr) kernel_sw(reg, addr) reg 87 arch/mips/include/asm/asm-eva.h #define user_swl(reg, addr) kernel_swl(reg, addr) reg 88 arch/mips/include/asm/asm-eva.h #define user_swr(reg, addr) kernel_swr(reg, addr) reg 89 arch/mips/include/asm/asm-eva.h #define user_sh(reg, addr) kernel_sh(reg, addr) reg 90 arch/mips/include/asm/asm-eva.h #define user_sb(reg, addr) kernel_sb(reg, addr) reg 93 arch/mips/include/asm/asm-eva.h #define user_sd(reg, addr) kernel_sw(reg, addr) reg 94 arch/mips/include/asm/asm-eva.h #define user_ld(reg, addr) kernel_lw(reg, addr) reg 96 arch/mips/include/asm/asm-eva.h #define user_sd(reg, addr) kernel_sd(reg, addr) reg 97 arch/mips/include/asm/asm-eva.h #define user_ld(reg, addr) kernel_ld(reg, addr) reg 106 arch/mips/include/asm/asm-eva.h #define kernel_ll(reg, addr) ll reg, addr reg 107 arch/mips/include/asm/asm-eva.h #define kernel_sc(reg, addr) sc reg, addr reg 108 arch/mips/include/asm/asm-eva.h #define kernel_lw(reg, addr) lw reg, addr reg 109 arch/mips/include/asm/asm-eva.h #define kernel_lwl(reg, addr) lwl reg, addr reg 110 arch/mips/include/asm/asm-eva.h #define kernel_lwr(reg, addr) lwr reg, addr reg 111 arch/mips/include/asm/asm-eva.h #define kernel_lh(reg, addr) lh reg, addr reg 112 arch/mips/include/asm/asm-eva.h #define kernel_lb(reg, addr) lb reg, addr reg 113 arch/mips/include/asm/asm-eva.h #define kernel_lbu(reg, addr) lbu reg, addr reg 114 arch/mips/include/asm/asm-eva.h #define kernel_sw(reg, addr) sw reg, addr reg 115 arch/mips/include/asm/asm-eva.h #define kernel_swl(reg, addr) swl reg, addr reg 116 arch/mips/include/asm/asm-eva.h #define kernel_swr(reg, addr) swr reg, addr reg 117 arch/mips/include/asm/asm-eva.h #define kernel_sh(reg, addr) sh reg, addr reg 118 arch/mips/include/asm/asm-eva.h #define kernel_sb(reg, addr) sb reg, addr reg 125 arch/mips/include/asm/asm-eva.h #define kernel_sd(reg, addr) user_sw(reg, addr) reg 126 arch/mips/include/asm/asm-eva.h #define kernel_ld(reg, addr) user_lw(reg, addr) reg 128 arch/mips/include/asm/asm-eva.h #define kernel_sd(reg, addr) sd reg, addr reg 129 arch/mips/include/asm/asm-eva.h #define kernel_ld(reg, addr) ld reg, addr reg 134 arch/mips/include/asm/asm-eva.h #define __BUILD_EVA_INSN(insn, reg, addr) \ reg 138 arch/mips/include/asm/asm-eva.h insn reg, addr; \ reg 143 arch/mips/include/asm/asm-eva.h #define user_ll(reg, addr) __BUILD_EVA_INSN(lle, reg, addr) reg 144 arch/mips/include/asm/asm-eva.h #define user_sc(reg, addr) __BUILD_EVA_INSN(sce, reg, addr) reg 145 arch/mips/include/asm/asm-eva.h #define user_lw(reg, addr) __BUILD_EVA_INSN(lwe, reg, addr) reg 146 arch/mips/include/asm/asm-eva.h #define user_lwl(reg, addr) __BUILD_EVA_INSN(lwle, reg, addr) reg 147 arch/mips/include/asm/asm-eva.h #define user_lwr(reg, addr) __BUILD_EVA_INSN(lwre, reg, addr) reg 148 arch/mips/include/asm/asm-eva.h #define user_lh(reg, addr) __BUILD_EVA_INSN(lhe, reg, addr) reg 149 arch/mips/include/asm/asm-eva.h #define user_lb(reg, addr) __BUILD_EVA_INSN(lbe, reg, addr) reg 150 arch/mips/include/asm/asm-eva.h #define user_lbu(reg, addr) __BUILD_EVA_INSN(lbue, reg, addr) reg 152 arch/mips/include/asm/asm-eva.h #define user_ld(reg, addr) user_lw(reg, addr) reg 153 arch/mips/include/asm/asm-eva.h #define user_sw(reg, addr) __BUILD_EVA_INSN(swe, reg, addr) reg 154 arch/mips/include/asm/asm-eva.h #define user_swl(reg, addr) __BUILD_EVA_INSN(swle, reg, addr) reg 155 arch/mips/include/asm/asm-eva.h #define user_swr(reg, addr) __BUILD_EVA_INSN(swre, reg, addr) reg 156 arch/mips/include/asm/asm-eva.h #define user_sh(reg, addr) __BUILD_EVA_INSN(she, reg, addr) reg 157 arch/mips/include/asm/asm-eva.h #define user_sb(reg, addr) __BUILD_EVA_INSN(sbe, reg, addr) reg 159 arch/mips/include/asm/asm-eva.h #define user_sd(reg, addr) user_sw(reg, addr) reg 164 arch/mips/include/asm/asm-eva.h #define user_ll(reg, addr) kernel_ll(reg, addr) reg 165 arch/mips/include/asm/asm-eva.h #define user_sc(reg, addr) kernel_sc(reg, addr) reg 166 arch/mips/include/asm/asm-eva.h #define user_lw(reg, addr) kernel_lw(reg, addr) reg 167 arch/mips/include/asm/asm-eva.h #define user_lwl(reg, addr) kernel_lwl(reg, addr) reg 168 arch/mips/include/asm/asm-eva.h #define user_lwr(reg, addr) kernel_lwr(reg, addr) reg 169 arch/mips/include/asm/asm-eva.h #define user_lh(reg, addr) kernel_lh(reg, addr) reg 170 arch/mips/include/asm/asm-eva.h #define user_lb(reg, addr) kernel_lb(reg, addr) reg 171 arch/mips/include/asm/asm-eva.h #define user_lbu(reg, addr) kernel_lbu(reg, addr) reg 172 arch/mips/include/asm/asm-eva.h #define user_sw(reg, addr) kernel_sw(reg, addr) reg 173 arch/mips/include/asm/asm-eva.h #define user_swl(reg, addr) kernel_swl(reg, addr) reg 174 arch/mips/include/asm/asm-eva.h #define user_swr(reg, addr) kernel_swr(reg, addr) reg 175 arch/mips/include/asm/asm-eva.h #define user_sh(reg, addr) kernel_sh(reg, addr) reg 176 arch/mips/include/asm/asm-eva.h #define user_sb(reg, addr) kernel_sb(reg, addr) reg 179 arch/mips/include/asm/asm-eva.h #define user_sd(reg, addr) kernel_sw(reg, addr) reg 180 arch/mips/include/asm/asm-eva.h #define user_ld(reg, addr) kernel_lw(reg, addr) reg 182 arch/mips/include/asm/asm-eva.h #define user_sd(reg, addr) kernel_sd(reg, addr) reg 183 arch/mips/include/asm/asm-eva.h #define user_ld(reg, addr) kernel_sd(reg, addr) reg 48 arch/mips/include/asm/asmmacro.h .macro local_irq_enable reg=t0 reg 53 arch/mips/include/asm/asmmacro.h .macro local_irq_disable reg=t0 reg 58 arch/mips/include/asm/asmmacro.h .macro local_irq_enable reg=t0 reg 65 arch/mips/include/asm/asmmacro.h .macro local_irq_disable reg=t0 reg 217 arch/mips/include/asm/asmmacro.h .macro DMT reg=0 reg 221 arch/mips/include/asm/asmmacro.h .macro EMT reg=0 reg 225 arch/mips/include/asm/asmmacro.h .macro DVPE reg=0 reg 229 arch/mips/include/asm/asmmacro.h .macro EVPE reg=0 reg 20 arch/mips/include/asm/dec/ioasic.h static inline void ioasic_write(unsigned int reg, u32 v) reg 22 arch/mips/include/asm/dec/ioasic.h ioasic_base[reg / 4] = v; reg 25 arch/mips/include/asm/dec/ioasic.h static inline u32 ioasic_read(unsigned int reg) reg 27 arch/mips/include/asm/dec/ioasic.h return ioasic_base[reg / 4]; reg 266 arch/mips/include/asm/ip32/mace.h struct reg { reg 269 arch/mips/include/asm/ip32/mace.h } reg; reg 195 arch/mips/include/asm/kvm_host.h unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; reg 412 arch/mips/include/asm/kvm_host.h static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg, reg 424 arch/mips/include/asm/kvm_host.h : "=&r" (temp), "+m" (*reg) reg 429 arch/mips/include/asm/kvm_host.h static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg, reg 441 arch/mips/include/asm/kvm_host.h : "=&r" (temp), "+m" (*reg) reg 446 arch/mips/include/asm/kvm_host.h static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg, reg 460 arch/mips/include/asm/kvm_host.h : "=&r" (temp), "+m" (*reg) reg 478 arch/mips/include/asm/kvm_host.h return cop0->reg[(_reg)][(sel)]; \ reg 483 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] = val; \ reg 491 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] |= val; \ reg 496 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] &= ~val; \ reg 503 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] &= ~_mask; \ reg 504 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] |= val & _mask; \ reg 512 arch/mips/include/asm/kvm_host.h _kvm_atomic_set_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \ reg 517 arch/mips/include/asm/kvm_host.h _kvm_atomic_clear_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \ reg 523 arch/mips/include/asm/kvm_host.h _kvm_atomic_change_c0_guest_reg(&cop0->reg[(_reg)][(sel)], mask, \ reg 567 arch/mips/include/asm/kvm_host.h write_gc0_##name(cop0->reg[(_reg)][(sel)]); \ reg 571 arch/mips/include/asm/kvm_host.h cop0->reg[(_reg)][(sel)] = read_gc0_##name(); \ reg 814 arch/mips/include/asm/kvm_host.h const struct kvm_one_reg *reg, s64 *v); reg 816 arch/mips/include/asm/kvm_host.h const struct kvm_one_reg *reg, s64 v); reg 148 arch/mips/include/asm/mach-ath79/ath79.h void ath79_ddr_wb_flush(unsigned int reg); reg 154 arch/mips/include/asm/mach-ath79/ath79.h static inline void ath79_pll_wr(unsigned reg, u32 val) reg 156 arch/mips/include/asm/mach-ath79/ath79.h __raw_writel(val, ath79_pll_base + reg); reg 159 arch/mips/include/asm/mach-ath79/ath79.h static inline u32 ath79_pll_rr(unsigned reg) reg 161 arch/mips/include/asm/mach-ath79/ath79.h return __raw_readl(ath79_pll_base + reg); reg 164 arch/mips/include/asm/mach-ath79/ath79.h static inline void ath79_reset_wr(unsigned reg, u32 val) reg 166 arch/mips/include/asm/mach-ath79/ath79.h __raw_writel(val, ath79_reset_base + reg); reg 167 arch/mips/include/asm/mach-ath79/ath79.h (void) __raw_readl(ath79_reset_base + reg); /* flush */ reg 170 arch/mips/include/asm/mach-ath79/ath79.h static inline u32 ath79_reset_rr(unsigned reg) reg 172 arch/mips/include/asm/mach-ath79/ath79.h return __raw_readl(ath79_reset_base + reg); reg 40 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h int phy_id, int reg), reg 42 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h int phy_id, int reg, int val)); reg 118 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg) reg 122 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h return bcm63xx_regs_enetdmac[reg]; reg 250 arch/mips/include/asm/mach-db1x00/bcsr.h unsigned short bcsr_read(enum bcsr_id reg); reg 253 arch/mips/include/asm/mach-db1x00/bcsr.h void bcsr_write(enum bcsr_id reg, unsigned short val); reg 256 arch/mips/include/asm/mach-db1x00/bcsr.h void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set); reg 55 arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h #define ltq_sys1_w32_mask(clear, set, reg) \ reg 56 arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg) reg 14 arch/mips/include/asm/mach-lantiq/lantiq.h #define ltq_r32(reg) __raw_readl(reg) reg 15 arch/mips/include/asm/mach-lantiq/lantiq.h #define ltq_w32(val, reg) __raw_writel(val, reg) reg 16 arch/mips/include/asm/mach-lantiq/lantiq.h #define ltq_w32_mask(clear, set, reg) \ reg 17 arch/mips/include/asm/mach-lantiq/lantiq.h ltq_w32((ltq_r32(reg) & ~(clear)) | (set), reg) reg 18 arch/mips/include/asm/mach-lantiq/lantiq.h #define ltq_r8(reg) __raw_readb(reg) reg 19 arch/mips/include/asm/mach-lantiq/lantiq.h #define ltq_w8(val, reg) __raw_writeb(val, reg) reg 18 arch/mips/include/asm/mach-loongson64/cs5536/cs5536_pci.h extern void cs5536_pci_conf_write4(int function, int reg, u32 value); reg 19 arch/mips/include/asm/mach-loongson64/cs5536/cs5536_pci.h extern u32 cs5536_pci_conf_read4(int function, int reg); reg 14 arch/mips/include/asm/mach-loongson64/cs5536/cs5536_vsm.h typedef void (*cs5536_pci_vsm_write)(int reg, u32 value); reg 15 arch/mips/include/asm/mach-loongson64/cs5536/cs5536_vsm.h typedef u32 (*cs5536_pci_vsm_read)(int reg); reg 18 arch/mips/include/asm/mach-loongson64/cs5536/cs5536_vsm.h extern void pci_##name##_write_reg(int reg, u32 value); \ reg 19 arch/mips/include/asm/mach-loongson64/cs5536/cs5536_vsm.h extern u32 pci_##name##_read_reg(int reg); reg 598 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h #define CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq) (reg &= ~EXT_INT_EDGE(eirq)) reg 599 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h #define CIC_EXT_SET_TRIGGER_EDGE(reg, eirq) (reg |= EXT_INT_EDGE(eirq)) reg 600 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h #define CIC_EXT_SET_ACTIVE_HI(reg, eirq) (reg |= EXT_INT_POL(eirq)) reg 601 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h #define CIC_EXT_SET_ACTIVE_LO(reg, eirq) (reg &= ~EXT_INT_POL(eirq)) reg 605 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h #define CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) \ reg 606 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h ((reg & EXT_INT_EDGE(eirq)) == 0) reg 607 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h #define CIC_EXT_IS_TRIGGER_EDGE(reg, eirq) (reg & EXT_INT_EDGE(eirq)) reg 608 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h #define CIC_EXT_IS_ACTIVE_HI(reg, eirq) (reg & EXT_INT_POL(eirq)) reg 609 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h #define CIC_EXT_IS_ACTIVE_LO(reg, eirq) \ reg 610 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h ((reg & EXT_INT_POL(eirq)) == 0) reg 626 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h #define DDRC_INDIRECT_WRITE(reg, mask, value) \ reg 628 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h *MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \ reg 22 arch/mips/include/asm/mach-pnx833x/gpio.h #define SET_REG_BIT(reg, bit) do { (reg |= (1 << (bit))); } while (0) reg 23 arch/mips/include/asm/mach-pnx833x/gpio.h #define CLEAR_REG_BIT(reg, bit) do { (reg &= ~(1 << (bit))); } while (0) reg 20 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field) reg 21 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX833X_REGBIT(reg, field) PNX833X_BIT(PNX833X_##reg, reg, field) reg 24 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX_FIELD(cpu, val, reg, field) \ reg 25 arch/mips/include/asm/mach-pnx833x/pnx833x.h (((val) & PNX##cpu##_##reg##_##field##_MASK) >> \ reg 26 arch/mips/include/asm/mach-pnx833x/pnx833x.h PNX##cpu##_##reg##_##field##_SHIFT) reg 27 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field) reg 28 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field) reg 29 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field) reg 32 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX833X_REGFIELD(reg, field) PNX833X_FIELD(PNX833X_##reg, reg, field) reg 33 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX8330_REGFIELD(reg, field) PNX8330_FIELD(PNX8330_##reg, reg, field) reg 34 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX8335_REGFIELD(reg, field) PNX8335_FIELD(PNX8335_##reg, reg, field) reg 37 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX_WRITEFIELD(cpu, val, reg, field) \ reg 38 arch/mips/include/asm/mach-pnx833x/pnx833x.h (PNX##cpu##_##reg = (PNX##cpu##_##reg & ~(PNX##cpu##_##reg##_##field##_MASK)) | \ reg 39 arch/mips/include/asm/mach-pnx833x/pnx833x.h ((val) << PNX##cpu##_##reg##_##field##_SHIFT)) reg 40 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX833X_WRITEFIELD(val, reg, field) \ reg 41 arch/mips/include/asm/mach-pnx833x/pnx833x.h PNX_WRITEFIELD(833X, val, reg, field) reg 42 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX8330_WRITEFIELD(val, reg, field) \ reg 43 arch/mips/include/asm/mach-pnx833x/pnx833x.h PNX_WRITEFIELD(8330, val, reg, field) reg 44 arch/mips/include/asm/mach-pnx833x/pnx833x.h #define PNX8335_WRITEFIELD(val, reg, field) \ reg 45 arch/mips/include/asm/mach-pnx833x/pnx833x.h PNX_WRITEFIELD(8335, val, reg, field) reg 35 arch/mips/include/asm/mach-ralink/ralink_regs.h static inline void rt_sysc_w32(u32 val, unsigned reg) reg 37 arch/mips/include/asm/mach-ralink/ralink_regs.h __raw_writel(val, rt_sysc_membase + reg); reg 40 arch/mips/include/asm/mach-ralink/ralink_regs.h static inline u32 rt_sysc_r32(unsigned reg) reg 42 arch/mips/include/asm/mach-ralink/ralink_regs.h return __raw_readl(rt_sysc_membase + reg); reg 45 arch/mips/include/asm/mach-ralink/ralink_regs.h static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg) reg 47 arch/mips/include/asm/mach-ralink/ralink_regs.h u32 val = rt_sysc_r32(reg) & ~clr; reg 49 arch/mips/include/asm/mach-ralink/ralink_regs.h __raw_writel(val | set, rt_sysc_membase + reg); reg 52 arch/mips/include/asm/mach-ralink/ralink_regs.h static inline void rt_memc_w32(u32 val, unsigned reg) reg 54 arch/mips/include/asm/mach-ralink/ralink_regs.h __raw_writel(val, rt_memc_membase + reg); reg 57 arch/mips/include/asm/mach-ralink/ralink_regs.h static inline u32 rt_memc_r32(unsigned reg) reg 59 arch/mips/include/asm/mach-ralink/ralink_regs.h return __raw_readl(rt_memc_membase + reg); reg 28 arch/mips/include/asm/mips-boards/malta.h static inline unsigned long get_gt_port_base(unsigned long reg) reg 31 arch/mips/include/asm/mips-boards/malta.h addr = GT_READ(reg); reg 35 arch/mips/include/asm/mips-boards/malta.h static inline unsigned long get_msc_port_base(unsigned long reg) reg 38 arch/mips/include/asm/mips-boards/malta.h MSC_READ(reg, addr); reg 217 arch/mips/include/asm/mips-boards/msc01_pci.h #define MSC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0) reg 218 arch/mips/include/asm/mips-boards/msc01_pci.h #define MSC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0) reg 1435 arch/mips/include/asm/mipsregs.h #define __read_ulong_c0_register(reg, sel) \ reg 1437 arch/mips/include/asm/mipsregs.h (unsigned long) __read_32bit_c0_register(reg, sel) : \ reg 1438 arch/mips/include/asm/mipsregs.h (unsigned long) __read_64bit_c0_register(reg, sel)) reg 1440 arch/mips/include/asm/mipsregs.h #define __read_const_ulong_c0_register(reg, sel) \ reg 1442 arch/mips/include/asm/mipsregs.h (unsigned long) __read_const_32bit_c0_register(reg, sel) : \ reg 1443 arch/mips/include/asm/mipsregs.h (unsigned long) __read_const_64bit_c0_register(reg, sel)) reg 1445 arch/mips/include/asm/mipsregs.h #define __write_ulong_c0_register(reg, sel, val) \ reg 1448 arch/mips/include/asm/mipsregs.h __write_32bit_c0_register(reg, sel, val); \ reg 1450 arch/mips/include/asm/mipsregs.h __write_64bit_c0_register(reg, sel, val); \ reg 2056 arch/mips/include/asm/mipsregs.h #define __read_ulong_gc0_register(reg, sel) \ reg 2058 arch/mips/include/asm/mipsregs.h (unsigned long) __read_32bit_gc0_register(reg, sel) : \ reg 2059 arch/mips/include/asm/mipsregs.h (unsigned long) __read_64bit_gc0_register(reg, sel)) reg 2061 arch/mips/include/asm/mipsregs.h #define __write_ulong_gc0_register(reg, sel, val) \ reg 2064 arch/mips/include/asm/mipsregs.h __write_32bit_gc0_register(reg, sel, val); \ reg 2066 arch/mips/include/asm/mipsregs.h __write_64bit_gc0_register(reg, sel, val); \ reg 2607 arch/mips/include/asm/mipsregs.h #define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000) reg 2608 arch/mips/include/asm/mipsregs.h #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000) reg 2610 arch/mips/include/asm/mipsregs.h #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000)) reg 2611 arch/mips/include/asm/mipsregs.h #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000)) reg 2615 arch/mips/include/asm/mipsregs.h #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) reg 2616 arch/mips/include/asm/mipsregs.h #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) reg 2618 arch/mips/include/asm/mipsregs.h #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) reg 2619 arch/mips/include/asm/mipsregs.h #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) reg 180 arch/mips/include/asm/msa.h unsigned int reg; \ reg 186 arch/mips/include/asm/msa.h : "=r"(reg)); \ reg 187 arch/mips/include/asm/msa.h return reg; \ reg 46 arch/mips/include/asm/netlogic/haldefs.h nlm_read_reg(uint64_t base, uint32_t reg) reg 48 arch/mips/include/asm/netlogic/haldefs.h volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; reg 54 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val) reg 56 arch/mips/include/asm/netlogic/haldefs.h volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; reg 71 arch/mips/include/asm/netlogic/haldefs.h nlm_read_reg64(uint64_t base, uint32_t reg) reg 73 arch/mips/include/asm/netlogic/haldefs.h uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); reg 98 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val) reg 100 arch/mips/include/asm/netlogic/haldefs.h uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); reg 129 arch/mips/include/asm/netlogic/haldefs.h nlm_read_reg_xkphys(uint64_t base, uint32_t reg) reg 131 arch/mips/include/asm/netlogic/haldefs.h return nlm_read_reg(base, reg); reg 135 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val) reg 137 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg(base, reg, val); reg 141 arch/mips/include/asm/netlogic/haldefs.h nlm_read_reg64_xkphys(uint64_t base, uint32_t reg) reg 143 arch/mips/include/asm/netlogic/haldefs.h return nlm_read_reg64(base, reg); reg 147 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val) reg 149 arch/mips/include/asm/netlogic/haldefs.h nlm_write_reg64(base, reg, val); reg 285 arch/mips/include/asm/netlogic/mips-extns.h #define __write_32bit_c2_register(reg, sel, value) \ reg 290 arch/mips/include/asm/netlogic/mips-extns.h "mtc2\t%z0, " #reg "\n\t" \ reg 296 arch/mips/include/asm/netlogic/mips-extns.h "mtc2\t%z0, " #reg ", " #sel "\n\t" \ reg 305 arch/mips/include/asm/netlogic/xlp-hal/pic.h uint64_t reg; reg 308 arch/mips/include/asm/netlogic/xlp-hal/pic.h reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt)); reg 309 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22)); reg 311 arch/mips/include/asm/netlogic/xlp-hal/pic.h reg = nlm_read_pic_reg(base, PIC_IRT(irt)); reg 312 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31)); reg 319 arch/mips/include/asm/netlogic/xlp-hal/pic.h uint64_t reg; reg 322 arch/mips/include/asm/netlogic/xlp-hal/pic.h reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt)); reg 323 arch/mips/include/asm/netlogic/xlp-hal/pic.h reg &= ~((uint64_t)1 << 22); reg 324 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg); reg 326 arch/mips/include/asm/netlogic/xlp-hal/pic.h reg = nlm_read_pic_reg(base, PIC_IRT(irt)); reg 327 arch/mips/include/asm/netlogic/xlp-hal/pic.h reg &= ~((uint64_t)1 << 31); reg 328 arch/mips/include/asm/netlogic/xlp-hal/pic.h nlm_write_pic_reg(base, PIC_IRT(irt), reg); reg 225 arch/mips/include/asm/netlogic/xlr/pic.h uint32_t reg; reg 227 arch/mips/include/asm/netlogic/xlr/pic.h reg = nlm_read_reg(base, PIC_IRT_1(irt)); reg 228 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31)); reg 234 arch/mips/include/asm/netlogic/xlr/pic.h uint32_t reg; reg 236 arch/mips/include/asm/netlogic/xlr/pic.h reg = nlm_read_reg(base, PIC_IRT_1(irt)); reg 237 arch/mips/include/asm/netlogic/xlr/pic.h nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31)); reg 129 arch/mips/include/asm/octeon/cvmx-fau.h static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg) reg 133 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); reg 152 arch/mips/include/asm/octeon/cvmx-fau.h static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, reg 158 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); reg 170 arch/mips/include/asm/octeon/cvmx-fau.h static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, reg 173 arch/mips/include/asm/octeon/cvmx-fau.h return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value)); reg 185 arch/mips/include/asm/octeon/cvmx-fau.h static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, reg 188 arch/mips/include/asm/octeon/cvmx-fau.h reg ^= SWIZZLE_32; reg 189 arch/mips/include/asm/octeon/cvmx-fau.h return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value)); reg 200 arch/mips/include/asm/octeon/cvmx-fau.h static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg, reg 203 arch/mips/include/asm/octeon/cvmx-fau.h reg ^= SWIZZLE_16; reg 204 arch/mips/include/asm/octeon/cvmx-fau.h return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value)); reg 214 arch/mips/include/asm/octeon/cvmx-fau.h static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) reg 216 arch/mips/include/asm/octeon/cvmx-fau.h reg ^= SWIZZLE_8; reg 217 arch/mips/include/asm/octeon/cvmx-fau.h return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value)); reg 233 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value) reg 240 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value)); reg 257 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value) reg 263 arch/mips/include/asm/octeon/cvmx-fau.h reg ^= SWIZZLE_32; reg 265 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value)); reg 281 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value) reg 287 arch/mips/include/asm/octeon/cvmx-fau.h reg ^= SWIZZLE_16; reg 289 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value)); reg 304 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) reg 310 arch/mips/include/asm/octeon/cvmx-fau.h reg ^= SWIZZLE_8; reg 311 arch/mips/include/asm/octeon/cvmx-fau.h result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value)); reg 340 arch/mips/include/asm/octeon/cvmx-fau.h uint64_t reg) reg 348 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); reg 364 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_fau_reg_64_t reg, reg 368 arch/mips/include/asm/octeon/cvmx-fau.h (scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg)); reg 384 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_fau_reg_32_t reg, reg 388 arch/mips/include/asm/octeon/cvmx-fau.h (scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg)); reg 403 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_fau_reg_16_t reg, reg 407 arch/mips/include/asm/octeon/cvmx-fau.h (scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg)); reg 421 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_fau_reg_8_t reg, reg 425 arch/mips/include/asm/octeon/cvmx-fau.h (scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg)); reg 444 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_fau_reg_64_t reg, reg 448 arch/mips/include/asm/octeon/cvmx-fau.h (scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg)); reg 467 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_fau_reg_32_t reg, reg 471 arch/mips/include/asm/octeon/cvmx-fau.h (scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg)); reg 490 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_fau_reg_16_t reg, reg 494 arch/mips/include/asm/octeon/cvmx-fau.h (scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg)); reg 512 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_fau_reg_8_t reg, reg 516 arch/mips/include/asm/octeon/cvmx-fau.h (scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg)); reg 526 arch/mips/include/asm/octeon/cvmx-fau.h static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value) reg 528 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value); reg 538 arch/mips/include/asm/octeon/cvmx-fau.h static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value) reg 540 arch/mips/include/asm/octeon/cvmx-fau.h reg ^= SWIZZLE_32; reg 541 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value); reg 551 arch/mips/include/asm/octeon/cvmx-fau.h static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value) reg 553 arch/mips/include/asm/octeon/cvmx-fau.h reg ^= SWIZZLE_16; reg 554 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value); reg 563 arch/mips/include/asm/octeon/cvmx-fau.h static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value) reg 565 arch/mips/include/asm/octeon/cvmx-fau.h reg ^= SWIZZLE_8; reg 566 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value); reg 576 arch/mips/include/asm/octeon/cvmx-fau.h static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value) reg 578 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value); reg 588 arch/mips/include/asm/octeon/cvmx-fau.h static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value) reg 590 arch/mips/include/asm/octeon/cvmx-fau.h reg ^= SWIZZLE_32; reg 591 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value); reg 601 arch/mips/include/asm/octeon/cvmx-fau.h static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value) reg 603 arch/mips/include/asm/octeon/cvmx-fau.h reg ^= SWIZZLE_16; reg 604 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value); reg 613 arch/mips/include/asm/octeon/cvmx-fau.h static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value) reg 615 arch/mips/include/asm/octeon/cvmx-fau.h reg ^= SWIZZLE_8; reg 616 arch/mips/include/asm/octeon/cvmx-fau.h cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value); reg 161 arch/mips/include/asm/pci/bridge.h u32 reg; /* 0x0002{04,,,3C} */ reg 166 arch/mips/include/asm/pci/bridge.h u32 reg; /* 0x0002{44,,,7C} */ reg 171 arch/mips/include/asm/pci/bridge.h u32 reg; /* 0x0002{84,,,8C} */ reg 173 arch/mips/include/asm/pci/bridge.h #define b_even_resp b_rrb_map[0].reg /* 0x000284 */ reg 174 arch/mips/include/asm/pci/bridge.h #define b_odd_resp b_rrb_map[1].reg /* 0x00028C */ reg 816 arch/mips/include/asm/pci/bridge.h #define bridge_read(bc, reg) __raw_readl(&bc->base->reg) reg 817 arch/mips/include/asm/pci/bridge.h #define bridge_write(bc, reg, val) __raw_writel(val, &bc->base->reg) reg 818 arch/mips/include/asm/pci/bridge.h #define bridge_set(bc, reg, val) \ reg 819 arch/mips/include/asm/pci/bridge.h __raw_writel(__raw_readl(&bc->base->reg) | (val), &bc->base->reg) reg 820 arch/mips/include/asm/pci/bridge.h #define bridge_clr(bc, reg, val) \ reg 821 arch/mips/include/asm/pci/bridge.h __raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg) reg 77 arch/mips/include/asm/sgi/ip22.h extern unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg); reg 78 arch/mips/include/asm/sgi/ip22.h extern unsigned short ip22_nvram_read(int reg); reg 77 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_MC_REGISTER(ctlid, reg) (A_BCM1480_MC_BASE(ctlid)+(reg)) reg 210 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_DUART_CHANREG(chan, reg) \ reg 212 arch/mips/include/asm/sibyte/bcm1480_regs.h BCM1480_DUART_CHANREG_SPACING * (((chan) & 1) + 1) + (reg)) reg 213 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_DUART_CTRLREG(chan, reg) \ reg 215 arch/mips/include/asm/sibyte/bcm1480_regs.h BCM1480_DUART_CHANREG_SPACING * 3 + (reg)) reg 362 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_IMR_REGISTER(cpu, reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg)) reg 403 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu, reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg)) reg 417 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_MAILBOX_REGISTER(num, reg, cpu) \ reg 421 arch/mips/include/asm/sibyte/bcm1480_regs.h (R_BCM1480_IMR_MAILBOX_0_CPU + reg)) reg 540 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_HR_REGISTER(idx, reg) (A_BCM1480_HR_BASE(idx) + (reg)) reg 589 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PMI_LCL_REGISTER(idx, reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg)) reg 591 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_PMO_LCL_REGISTER(idx, reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg)) reg 711 arch/mips/include/asm/sibyte/bcm1480_regs.h #define A_BCM1480_HSP_REGISTER(idx, reg) (A_BCM1480_HSP_BASE(idx) + (reg)) reg 56 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_MC_REGISTER(ctlid, reg) (A_MC_BASE(ctlid)+(reg)) reg 156 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_MAC_REGISTER(macnum,reg) \ reg 158 arch/mips/include/asm/sibyte/sb1250_regs.h MAC_SPACING*(macnum) + (reg)) reg 174 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg) \ reg 176 arch/mips/include/asm/sibyte/sb1250_regs.h (reg)) reg 178 arch/mips/include/asm/sibyte/sb1250_regs.h #define R_MAC_DMA_REGISTER(txrx, chan, reg) \ reg 180 arch/mips/include/asm/sibyte/sb1250_regs.h (reg)) reg 269 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_DUART_CHANREG(chan, reg) \ reg 270 arch/mips/include/asm/sibyte/sb1250_regs.h (A_DUART + DUART_CHANREG_SPACING * ((chan) + 1) + (reg)) reg 297 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_DUART_CTRLREG(reg) \ reg 298 arch/mips/include/asm/sibyte/sb1250_regs.h (A_DUART + DUART_CHANREG_SPACING * 3 + (reg)) reg 393 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_SER_REGISTER(sernum,reg) \ reg 395 arch/mips/include/asm/sibyte/sb1250_regs.h SER_SPACING*(sernum) + (reg)) reg 405 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_SER_DMA_REGISTER(sernum, txrx, reg) \ reg 407 arch/mips/include/asm/sibyte/sb1250_regs.h (reg)) reg 489 arch/mips/include/asm/sibyte/sb1250_regs.h #define R_IO_EXT_REG(reg, cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) reg 577 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_SMB_REGISTER(idx, reg) (A_SMB_BASE(idx)+(reg)) reg 704 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg)) reg 729 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_MAILBOX_REGISTER(reg,cpu) \ reg 730 arch/mips/include/asm/sibyte/sb1250_regs.h (A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg) reg 811 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_DM_REGISTER(idx, reg) (A_DM_BASE(idx) + (reg)) reg 833 arch/mips/include/asm/sibyte/sb1250_regs.h #define A_DM_CRC_REGISTER(idx, reg) (A_DM_CRC_BASE(idx) + (reg)) reg 23 arch/mips/include/asm/stackframe.h .macro cfi_rel_offset reg offset=0 docfi=0 reg 29 arch/mips/include/asm/stackframe.h .macro cfi_st reg offset=0 docfi=0 reg 34 arch/mips/include/asm/stackframe.h .macro cfi_restore reg offset=0 docfi=0 reg 40 arch/mips/include/asm/stackframe.h .macro cfi_ld reg offset=0 docfi=0 reg 65 arch/mips/include/asm/txx9/smsc_fdc37m81x.h u8 smsc_fdc37m81x_config_get(u8 reg); reg 66 arch/mips/include/asm/txx9/smsc_fdc37m81x.h void smsc_fdc37m81x_config_set(u8 reg, u8 val); reg 246 arch/mips/include/asm/uaccess.h #define _loadd(reg, addr) "ld " reg ", " addr reg 248 arch/mips/include/asm/uaccess.h #define _loadw(reg, addr) "lw " reg ", " addr reg 249 arch/mips/include/asm/uaccess.h #define _loadh(reg, addr) "lh " reg ", " addr reg 250 arch/mips/include/asm/uaccess.h #define _loadb(reg, addr) "lb " reg ", " addr reg 382 arch/mips/include/asm/uaccess.h #define _stored(reg, addr) "ld " reg ", " addr reg 385 arch/mips/include/asm/uaccess.h #define _storew(reg, addr) "sw " reg ", " addr reg 386 arch/mips/include/asm/uaccess.h #define _storeh(reg, addr) "sh " reg ", " addr reg 387 arch/mips/include/asm/uaccess.h #define _storeb(reg, addr) "sb " reg ", " addr reg 310 arch/mips/include/asm/uasm.h void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg, reg 312 arch/mips/include/asm/uasm.h void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg, reg 316 arch/mips/include/asm/uasm.h void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); reg 317 arch/mips/include/asm/uasm.h void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); reg 318 arch/mips/include/asm/uasm.h void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); reg 319 arch/mips/include/asm/uasm.h void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); reg 320 arch/mips/include/asm/uasm.h void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); reg 323 arch/mips/include/asm/uasm.h void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); reg 686 arch/mips/kernel/branch.c unsigned int bit, fcr31, reg; reg 693 arch/mips/kernel/branch.c reg = insn.i_format.rt; reg 694 arch/mips/kernel/branch.c bit = get_fpr32(¤t->thread.fpu.fpr[reg], 0) & 0x1; reg 21 arch/mips/kernel/irq-msc01.c #define MSCIC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0) reg 22 arch/mips/kernel/irq-msc01.c #define MSCIC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0) reg 240 arch/mips/kernel/kgdb.c int reg; reg 247 arch/mips/kernel/kgdb.c for (reg = 0; reg < 16; reg++) reg 260 arch/mips/kernel/kgdb.c for (reg = 24; reg < 28; reg++) reg 935 arch/mips/kernel/ptrace.c #define REG_OFFSET_NAME(reg, r) { \ reg 936 arch/mips/kernel/ptrace.c .name = #reg, \ reg 563 arch/mips/kernel/traps.c unsigned long reg; reg 578 arch/mips/kernel/traps.c reg = (opcode & RT) >> 16; reg 586 arch/mips/kernel/traps.c regs->regs[reg] = 0; reg 593 arch/mips/kernel/traps.c if (put_user(regs->regs[reg], vaddr)) reg 596 arch/mips/kernel/traps.c regs->regs[reg] = 1; reg 1396 arch/mips/kernel/unaligned.c unsigned int reg = 0, rvar; reg 1454 arch/mips/kernel/unaligned.c reg = insn.mm_x_format.rd; reg 1463 arch/mips/kernel/unaligned.c reg = insn.mm_m_format.rd; reg 1464 arch/mips/kernel/unaligned.c if (reg == 31) reg 1473 arch/mips/kernel/unaligned.c regs->regs[reg] = value; reg 1478 arch/mips/kernel/unaligned.c regs->regs[reg + 1] = value; reg 1482 arch/mips/kernel/unaligned.c reg = insn.mm_m_format.rd; reg 1483 arch/mips/kernel/unaligned.c if (reg == 31) reg 1489 arch/mips/kernel/unaligned.c value = regs->regs[reg]; reg 1494 arch/mips/kernel/unaligned.c value = regs->regs[reg + 1]; reg 1502 arch/mips/kernel/unaligned.c reg = insn.mm_m_format.rd; reg 1503 arch/mips/kernel/unaligned.c if (reg == 31) reg 1512 arch/mips/kernel/unaligned.c regs->regs[reg] = value; reg 1517 arch/mips/kernel/unaligned.c regs->regs[reg + 1] = value; reg 1525 arch/mips/kernel/unaligned.c reg = insn.mm_m_format.rd; reg 1526 arch/mips/kernel/unaligned.c if (reg == 31) reg 1532 arch/mips/kernel/unaligned.c value = regs->regs[reg]; reg 1537 arch/mips/kernel/unaligned.c value = regs->regs[reg + 1]; reg 1547 arch/mips/kernel/unaligned.c reg = insn.mm_m_format.rd; reg 1548 arch/mips/kernel/unaligned.c rvar = reg & 0xf; reg 1549 arch/mips/kernel/unaligned.c if ((rvar > 9) || !reg) reg 1551 arch/mips/kernel/unaligned.c if (reg & 0x10) { reg 1567 arch/mips/kernel/unaligned.c if ((reg & 0xf) == 9) { reg 1574 arch/mips/kernel/unaligned.c if (reg & 0x10) { reg 1583 arch/mips/kernel/unaligned.c reg = insn.mm_m_format.rd; reg 1584 arch/mips/kernel/unaligned.c rvar = reg & 0xf; reg 1585 arch/mips/kernel/unaligned.c if ((rvar > 9) || !reg) reg 1587 arch/mips/kernel/unaligned.c if (reg & 0x10) { reg 1603 arch/mips/kernel/unaligned.c if ((reg & 0xf) == 9) { reg 1610 arch/mips/kernel/unaligned.c if (reg & 0x10) { reg 1620 arch/mips/kernel/unaligned.c reg = insn.mm_m_format.rd; reg 1621 arch/mips/kernel/unaligned.c rvar = reg & 0xf; reg 1622 arch/mips/kernel/unaligned.c if ((rvar > 9) || !reg) reg 1624 arch/mips/kernel/unaligned.c if (reg & 0x10) { reg 1641 arch/mips/kernel/unaligned.c if ((reg & 0xf) == 9) { reg 1648 arch/mips/kernel/unaligned.c if (reg & 0x10) { reg 1661 arch/mips/kernel/unaligned.c reg = insn.mm_m_format.rd; reg 1662 arch/mips/kernel/unaligned.c rvar = reg & 0xf; reg 1663 arch/mips/kernel/unaligned.c if ((rvar > 9) || !reg) reg 1665 arch/mips/kernel/unaligned.c if (reg & 0x10) { reg 1682 arch/mips/kernel/unaligned.c if ((reg & 0xf) == 9) { reg 1689 arch/mips/kernel/unaligned.c if (reg & 0x10) { reg 1708 arch/mips/kernel/unaligned.c reg = insn.mm_m_format.rd; reg 1756 arch/mips/kernel/unaligned.c reg = insn.mm_i_format.rt; reg 1760 arch/mips/kernel/unaligned.c reg = insn.mm_i_format.rt; reg 1764 arch/mips/kernel/unaligned.c reg = insn.mm_i_format.rt; reg 1768 arch/mips/kernel/unaligned.c reg = insn.mm_i_format.rt; reg 1772 arch/mips/kernel/unaligned.c reg = insn.mm_i_format.rt; reg 1776 arch/mips/kernel/unaligned.c reg = insn.mm_i_format.rt; reg 1780 arch/mips/kernel/unaligned.c reg = insn.mm_i_format.rt; reg 1786 arch/mips/kernel/unaligned.c reg = insn.mm16_m_format.rlist; reg 1787 arch/mips/kernel/unaligned.c rvar = reg + 1; reg 1806 arch/mips/kernel/unaligned.c reg = insn.mm16_m_format.rlist; reg 1807 arch/mips/kernel/unaligned.c rvar = reg + 1; reg 1830 arch/mips/kernel/unaligned.c reg = reg16to32[insn.mm16_rb_format.rt]; reg 1834 arch/mips/kernel/unaligned.c reg = reg16to32[insn.mm16_rb_format.rt]; reg 1838 arch/mips/kernel/unaligned.c reg = reg16to32st[insn.mm16_rb_format.rt]; reg 1842 arch/mips/kernel/unaligned.c reg = reg16to32st[insn.mm16_rb_format.rt]; reg 1846 arch/mips/kernel/unaligned.c reg = insn.mm16_r5_format.rt; reg 1850 arch/mips/kernel/unaligned.c reg = insn.mm16_r5_format.rt; reg 1854 arch/mips/kernel/unaligned.c reg = reg16to32[insn.mm16_r3_format.rt]; reg 1868 arch/mips/kernel/unaligned.c regs->regs[reg] = value; reg 1878 arch/mips/kernel/unaligned.c regs->regs[reg] = value; reg 1888 arch/mips/kernel/unaligned.c regs->regs[reg] = value; reg 1906 arch/mips/kernel/unaligned.c regs->regs[reg] = value; reg 1928 arch/mips/kernel/unaligned.c regs->regs[reg] = value; reg 1939 arch/mips/kernel/unaligned.c value = regs->regs[reg]; reg 1949 arch/mips/kernel/unaligned.c value = regs->regs[reg]; reg 1967 arch/mips/kernel/unaligned.c value = regs->regs[reg]; reg 2014 arch/mips/kernel/unaligned.c int reg; reg 2052 arch/mips/kernel/unaligned.c reg = reg16to32[mips16inst.ri64.ry]; reg 2056 arch/mips/kernel/unaligned.c reg = reg16to32[mips16inst.ri64.ry]; reg 2060 arch/mips/kernel/unaligned.c reg = 29; /* GPRSP */ reg 2067 arch/mips/kernel/unaligned.c reg = reg16to32[mips16inst.ri.rx]; reg 2082 arch/mips/kernel/unaligned.c reg = reg16to32[mips16inst.ri.rx]; reg 2086 arch/mips/kernel/unaligned.c reg = reg16to32[mips16inst.ri.rx]; reg 2106 arch/mips/kernel/unaligned.c reg = 29; /* GPRSP */ reg 2110 arch/mips/kernel/unaligned.c reg = reg16to32[mips16inst.rri.ry]; reg 2129 arch/mips/kernel/unaligned.c regs->regs[reg] = value; reg 2140 arch/mips/kernel/unaligned.c regs->regs[reg] = value; reg 2153 arch/mips/kernel/unaligned.c regs->regs[reg] = value; reg 2172 arch/mips/kernel/unaligned.c regs->regs[reg] = value; reg 2196 arch/mips/kernel/unaligned.c regs->regs[reg] = value; reg 2208 arch/mips/kernel/unaligned.c value = regs->regs[reg]; reg 2221 arch/mips/kernel/unaligned.c value = regs->regs[reg]; reg 2241 arch/mips/kernel/unaligned.c value = regs->regs[reg]; reg 114 arch/mips/kvm/dyntrans.c offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]); reg 116 arch/mips/kvm/dyntrans.c if (sizeof(vcpu->arch.cop0->reg[0][0]) == 8) reg 136 arch/mips/kvm/dyntrans.c offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]); reg 138 arch/mips/kvm/dyntrans.c if (sizeof(vcpu->arch.cop0->reg[0][0]) == 8) reg 1329 arch/mips/kvm/emulate.c vcpu->arch.gprs[rt] = (s32)cop0->reg[rd][sel]; reg 1342 arch/mips/kvm/emulate.c vcpu->arch.gprs[rt] = cop0->reg[rd][sel]; reg 1519 arch/mips/kvm/emulate.c cop0->reg[rd][sel] = vcpu->arch.gprs[rt] & mask; reg 1521 arch/mips/kvm/emulate.c cop0->reg[rd][sel] = vcpu->arch.gprs[rt]; reg 1559 arch/mips/kvm/emulate.c u32 css = cop0->reg[MIPS_CP0_STATUS][2] & 0xf; reg 1561 arch/mips/kvm/emulate.c (cop0->reg[MIPS_CP0_STATUS][2] >> 6) & 0xf; reg 189 arch/mips/kvm/entry.c static inline void build_set_exc_base(u32 **p, unsigned int reg) reg 193 arch/mips/kvm/entry.c uasm_i_ori(p, reg, reg, MIPS_EBASE_WG); reg 194 arch/mips/kvm/entry.c UASM_i_MTC0(p, reg, C0_EBASE); reg 196 arch/mips/kvm/entry.c uasm_i_mtc0(p, reg, C0_EBASE); reg 370 arch/mips/kvm/entry.c UASM_i_LW(&p, T0, offsetof(struct mips_coproc, reg[MIPS_CP0_STATUS][0]), reg 645 arch/mips/kvm/mips.c const struct kvm_one_reg *reg) reg 654 arch/mips/kvm/mips.c switch (reg->id) { reg 657 arch/mips/kvm/mips.c v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0]; reg 675 arch/mips/kvm/mips.c idx = reg->id - KVM_REG_MIPS_FPR_32(0); reg 685 arch/mips/kvm/mips.c idx = reg->id - KVM_REG_MIPS_FPR_64(0); reg 709 arch/mips/kvm/mips.c idx = reg->id - KVM_REG_MIPS_VEC_128(0); reg 733 arch/mips/kvm/mips.c ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v); reg 738 arch/mips/kvm/mips.c if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { reg 739 arch/mips/kvm/mips.c u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; reg 742 arch/mips/kvm/mips.c } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { reg 743 arch/mips/kvm/mips.c u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; reg 747 arch/mips/kvm/mips.c } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { reg 748 arch/mips/kvm/mips.c void __user *uaddr = (void __user *)(long)reg->addr; reg 757 arch/mips/kvm/mips.c const struct kvm_one_reg *reg) reg 765 arch/mips/kvm/mips.c if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { reg 766 arch/mips/kvm/mips.c u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; reg 770 arch/mips/kvm/mips.c } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { reg 771 arch/mips/kvm/mips.c u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; reg 777 arch/mips/kvm/mips.c } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { reg 778 arch/mips/kvm/mips.c void __user *uaddr = (void __user *)(long)reg->addr; reg 785 arch/mips/kvm/mips.c switch (reg->id) { reg 791 arch/mips/kvm/mips.c vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v; reg 809 arch/mips/kvm/mips.c idx = reg->id - KVM_REG_MIPS_FPR_32(0); reg 819 arch/mips/kvm/mips.c idx = reg->id - KVM_REG_MIPS_FPR_64(0); reg 840 arch/mips/kvm/mips.c idx = reg->id - KVM_REG_MIPS_VEC_128(0); reg 864 arch/mips/kvm/mips.c return kvm_mips_callbacks->set_one_reg(vcpu, reg, v); reg 928 arch/mips/kvm/mips.c struct kvm_one_reg reg; reg 931 arch/mips/kvm/mips.c if (copy_from_user(®, argp, sizeof(reg))) reg 934 arch/mips/kvm/mips.c r = kvm_mips_set_reg(vcpu, ®); reg 936 arch/mips/kvm/mips.c r = kvm_mips_get_reg(vcpu, ®); reg 954 arch/mips/kvm/mips.c r = kvm_mips_copy_reg_indices(vcpu, user_list->reg); reg 203 arch/mips/kvm/trace.h TP_PROTO(struct kvm_vcpu *vcpu, unsigned int op, unsigned int reg, reg 205 arch/mips/kvm/trace.h TP_ARGS(vcpu, op, reg, val), reg 208 arch/mips/kvm/trace.h __field(u16, reg) reg 214 arch/mips/kvm/trace.h __entry->reg = reg; reg 221 arch/mips/kvm/trace.h __print_symbolic(__entry->reg, reg 223 arch/mips/kvm/trace.h __print_symbolic(__entry->reg >> 8, reg 225 arch/mips/kvm/trace.h (__entry->reg >> 3) & 0x1f, reg 226 arch/mips/kvm/trace.h __entry->reg & 0x7, reg 766 arch/mips/kvm/trap_emul.c const struct kvm_one_reg *reg, reg 771 arch/mips/kvm/trap_emul.c switch (reg->id) { reg 884 arch/mips/kvm/trap_emul.c const struct kvm_one_reg *reg, reg 891 arch/mips/kvm/trap_emul.c switch (reg->id) { reg 976 arch/mips/kvm/vz.c val = cop0->reg[rd][sel]; reg 1823 arch/mips/kvm/vz.c const struct kvm_one_reg *reg, reg 1829 arch/mips/kvm/vz.c switch (reg->id) { reg 1985 arch/mips/kvm/vz.c idx = reg->id - KVM_REG_MIPS_CP0_MAAR(0); reg 2004 arch/mips/kvm/vz.c idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2; reg 2044 arch/mips/kvm/vz.c const struct kvm_one_reg *reg, reg 2052 arch/mips/kvm/vz.c switch (reg->id) { reg 2254 arch/mips/kvm/vz.c idx = reg->id - KVM_REG_MIPS_CP0_MAAR(0); reg 2273 arch/mips/kvm/vz.c idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2; reg 2593 arch/mips/kvm/vz.c cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL]); reg 2700 arch/mips/kvm/vz.c cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL] = reg 3098 arch/mips/kvm/vz.c cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL] = 0; reg 66 arch/mips/lantiq/falcon/sysctrl.c #define sysctl_w32_mask(m, clear, set, reg) \ reg 67 arch/mips/lantiq/falcon/sysctrl.c sysctl_w32(m, (sysctl_r32(m, reg) & ~(clear)) | (set), reg) reg 81 arch/mips/lantiq/falcon/sysctrl.c unsigned int test, unsigned int reg) reg 85 arch/mips/lantiq/falcon/sysctrl.c do {} while (--err && ((sysctl_r32(clk->module, reg) reg 90 arch/mips/lantiq/falcon/sysctrl.c sysctl_r32(clk->module, reg) & clk->bits); reg 25 arch/mips/lasat/at93c.c *at93c->reg = val; reg 30 arch/mips/lasat/at93c.c u32 tmp = *at93c->reg; reg 10 arch/mips/lasat/at93c.h volatile u32 *reg; reg 27 arch/mips/lasat/ds1603.c *ds1603->reg = val; reg 32 arch/mips/lasat/ds1603.c unsigned long tmp = *ds1603->reg; reg 12 arch/mips/lasat/ds1603.h volatile u32 *reg; reg 27 arch/mips/lasat/picvue.c *picvue->reg = val; reg 32 arch/mips/lasat/picvue.c u32 tmp = *picvue->reg; reg 9 arch/mips/lasat/picvue.h volatile u32 *reg; reg 68 arch/mips/lasat/prom.c .reg = (void *)AT93C_REG_100, reg 75 arch/mips/lasat/prom.c .reg = (void *)AT93C_REG_200, reg 15 arch/mips/loongson64/common/cs5536/cs5536_acc.c void pci_acc_write_reg(int reg, u32 value) reg 19 arch/mips/loongson64/common/cs5536/cs5536_acc.c switch (reg) { reg 62 arch/mips/loongson64/common/cs5536/cs5536_acc.c u32 pci_acc_read_reg(int reg) reg 67 arch/mips/loongson64/common/cs5536/cs5536_acc.c switch (reg) { reg 15 arch/mips/loongson64/common/cs5536/cs5536_ehci.c void pci_ehci_write_reg(int reg, u32 value) reg 19 arch/mips/loongson64/common/cs5536/cs5536_ehci.c switch (reg) { reg 75 arch/mips/loongson64/common/cs5536/cs5536_ehci.c u32 pci_ehci_read_reg(int reg) reg 80 arch/mips/loongson64/common/cs5536/cs5536_ehci.c switch (reg) { reg 15 arch/mips/loongson64/common/cs5536/cs5536_ide.c void pci_ide_write_reg(int reg, u32 value) reg 19 arch/mips/loongson64/common/cs5536/cs5536_ide.c switch (reg) { reg 96 arch/mips/loongson64/common/cs5536/cs5536_ide.c u32 pci_ide_read_reg(int reg) reg 101 arch/mips/loongson64/common/cs5536/cs5536_ide.c switch (reg) { reg 134 arch/mips/loongson64/common/cs5536/cs5536_isa.c void pci_isa_write_reg(int reg, u32 value) reg 139 arch/mips/loongson64/common/cs5536/cs5536_isa.c switch (reg) { reg 228 arch/mips/loongson64/common/cs5536/cs5536_isa.c u32 pci_isa_read_reg(int reg) reg 233 arch/mips/loongson64/common/cs5536/cs5536_isa.c switch (reg) { reg 15 arch/mips/loongson64/common/cs5536/cs5536_ohci.c void pci_ohci_write_reg(int reg, u32 value) reg 19 arch/mips/loongson64/common/cs5536/cs5536_ohci.c switch (reg) { reg 70 arch/mips/loongson64/common/cs5536/cs5536_ohci.c u32 pci_ohci_read_reg(int reg) reg 75 arch/mips/loongson64/common/cs5536/cs5536_ohci.c switch (reg) { reg 55 arch/mips/loongson64/common/cs5536/cs5536_pci.c void cs5536_pci_conf_write4(int function, int reg, u32 value) reg 59 arch/mips/loongson64/common/cs5536/cs5536_pci.c if ((reg < 0) || (reg > 0x100) || ((reg & 0x03) != 0)) reg 63 arch/mips/loongson64/common/cs5536/cs5536_pci.c vsm_conf_write[function](reg, value); reg 69 arch/mips/loongson64/common/cs5536/cs5536_pci.c u32 cs5536_pci_conf_read4(int function, int reg) reg 75 arch/mips/loongson64/common/cs5536/cs5536_pci.c if ((reg < 0) || ((reg & 0x03) != 0)) reg 77 arch/mips/loongson64/common/cs5536/cs5536_pci.c if (reg > 0x100) reg 81 arch/mips/loongson64/common/cs5536/cs5536_pci.c data = vsm_conf_read[function](reg); reg 32 arch/mips/loongson64/loongson-3/acpi_init.c static void pmio_write_index(u16 index, u8 reg, u8 value) reg 34 arch/mips/loongson64/loongson-3/acpi_init.c outb(reg, index); reg 38 arch/mips/loongson64/loongson-3/acpi_init.c static u8 pmio_read_index(u16 index, u8 reg) reg 40 arch/mips/loongson64/loongson-3/acpi_init.c outb(reg, index); reg 44 arch/mips/loongson64/loongson-3/acpi_init.c void pm_iowrite(u8 reg, u8 value) reg 46 arch/mips/loongson64/loongson-3/acpi_init.c pmio_write_index(PM_INDEX, reg, value); reg 50 arch/mips/loongson64/loongson-3/acpi_init.c u8 pm_ioread(u8 reg) reg 52 arch/mips/loongson64/loongson-3/acpi_init.c return pmio_read_index(PM_INDEX, reg); reg 56 arch/mips/loongson64/loongson-3/acpi_init.c void pm2_iowrite(u8 reg, u8 value) reg 58 arch/mips/loongson64/loongson-3/acpi_init.c pmio_write_index(PM2_INDEX, reg, value); reg 62 arch/mips/loongson64/loongson-3/acpi_init.c u8 pm2_ioread(u8 reg) reg 64 arch/mips/loongson64/loongson-3/acpi_init.c return pmio_read_index(PM2_INDEX, reg); reg 367 arch/mips/mm/page.c static void build_copy_load(u32 **buf, int reg, int off) reg 370 arch/mips/mm/page.c uasm_i_ld(buf, reg, off, A1); reg 372 arch/mips/mm/page.c uasm_i_lw(buf, reg, off, A1); reg 376 arch/mips/mm/page.c static void build_copy_store(u32 **buf, int reg, int off) reg 379 arch/mips/mm/page.c uasm_i_sd(buf, reg, off, A0); reg 381 arch/mips/mm/page.c uasm_i_sw(buf, reg, off, A0); reg 298 arch/mips/mm/tlbex.c # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) reg 300 arch/mips/mm/tlbex.c # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) reg 625 arch/mips/mm/tlbex.c unsigned int reg) reg 634 arch/mips/mm/tlbex.c UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); reg 636 arch/mips/mm/tlbex.c UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); reg 637 arch/mips/mm/tlbex.c UASM_i_ROTR(p, reg, reg, reg 642 arch/mips/mm/tlbex.c uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); reg 644 arch/mips/mm/tlbex.c UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); reg 558 arch/mips/mm/uasm.c void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, reg 562 arch/mips/mm/uasm.c uasm_i_bltz(p, reg, 0); reg 581 arch/mips/mm/uasm.c void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, reg 585 arch/mips/mm/uasm.c uasm_i_beqz(p, reg, 0); reg 589 arch/mips/mm/uasm.c void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, reg 593 arch/mips/mm/uasm.c uasm_i_beqzl(p, reg, 0); reg 605 arch/mips/mm/uasm.c void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, reg 609 arch/mips/mm/uasm.c uasm_i_bnez(p, reg, 0); reg 613 arch/mips/mm/uasm.c void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, reg 617 arch/mips/mm/uasm.c uasm_i_bgezl(p, reg, 0); reg 621 arch/mips/mm/uasm.c void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, reg 625 arch/mips/mm/uasm.c uasm_i_bgez(p, reg, 0); reg 629 arch/mips/mm/uasm.c void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg, reg 633 arch/mips/mm/uasm.c uasm_i_bbit0(p, reg, bit, 0); reg 637 arch/mips/mm/uasm.c void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg, reg 641 arch/mips/mm/uasm.c uasm_i_bbit1(p, reg, bit, 0); reg 113 arch/mips/net/ebpf_jit.c static void set_reg_val_type(u64 *rvt, int reg, enum reg_val_type type) reg 115 arch/mips/net/ebpf_jit.c *rvt &= ~(7ull << (reg * 3)); reg 116 arch/mips/net/ebpf_jit.c *rvt |= ((u64)type << (reg * 3)); reg 120 arch/mips/net/ebpf_jit.c int index, int reg) reg 122 arch/mips/net/ebpf_jit.c return (ctx->reg_val_types[index] >> (reg * 3)) & 7; reg 408 arch/mips/net/ebpf_jit.c static void gen_imm_to_reg(const struct bpf_insn *insn, int reg, reg 412 arch/mips/net/ebpf_jit.c emit_instr(ctx, addiu, reg, MIPS_R_ZERO, insn->imm); reg 417 arch/mips/net/ebpf_jit.c emit_instr(ctx, lui, reg, upper >> 16); reg 418 arch/mips/net/ebpf_jit.c emit_instr(ctx, addiu, reg, reg, lower); reg 1567 arch/mips/net/ebpf_jit.c int reg; reg 1709 arch/mips/net/ebpf_jit.c for (reg = BPF_REG_0; reg <= BPF_REG_5; reg++) reg 1710 arch/mips/net/ebpf_jit.c set_reg_val_type(&exit_rvt, reg, REG_64BIT); reg 1740 arch/mips/net/ebpf_jit.c int reg; reg 1750 arch/mips/net/ebpf_jit.c for (reg = BPF_REG_1; reg <= BPF_REG_5; reg++) reg 1751 arch/mips/net/ebpf_jit.c set_reg_val_type(&exit_rvt, reg, REG_64BIT); reg 205 arch/mips/netlogic/xlp/ahci-init-xlp2.c u32 port, i, reg; reg 209 arch/mips/netlogic/xlp/ahci-init-xlp2.c for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++) reg 210 arch/mips/netlogic/xlp/ahci-init-xlp2.c write_phy_reg(regbase, reg, port, sata_phy_config1[i]); reg 212 arch/mips/netlogic/xlp/ahci-init-xlp2.c for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++) reg 213 arch/mips/netlogic/xlp/ahci-init-xlp2.c write_phy_reg(regbase, reg, port, sata_phy_config2[i]); reg 240 arch/mips/netlogic/xlp/ahci-init-xlp2.c u32 port, i, reg; reg 243 arch/mips/netlogic/xlp/ahci-init-xlp2.c for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++) reg 244 arch/mips/netlogic/xlp/ahci-init-xlp2.c check_phy_register(regbase, reg, port, reg 247 arch/mips/netlogic/xlp/ahci-init-xlp2.c for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++) reg 248 arch/mips/netlogic/xlp/ahci-init-xlp2.c check_phy_register(regbase, reg, port, reg 41 arch/mips/oprofile/op_model_loongson2.c } reg; reg 56 arch/mips/oprofile/op_model_loongson2.c reg.reset_counter1 = 0; reg 57 arch/mips/oprofile/op_model_loongson2.c reg.reset_counter2 = 0; reg 65 arch/mips/oprofile/op_model_loongson2.c reg.reset_counter1 = 0x80000000ULL - cfg[0].count; reg 70 arch/mips/oprofile/op_model_loongson2.c reg.reset_counter2 = 0x80000000ULL - cfg[1].count; reg 81 arch/mips/oprofile/op_model_loongson2.c reg.ctrl = ctrl; reg 83 arch/mips/oprofile/op_model_loongson2.c reg.cnt1_enabled = cfg[0].enabled; reg 84 arch/mips/oprofile/op_model_loongson2.c reg.cnt2_enabled = cfg[1].enabled; reg 89 arch/mips/oprofile/op_model_loongson2.c write_c0_perfcnt((reg.reset_counter2 << 32) | reg.reset_counter1); reg 95 arch/mips/oprofile/op_model_loongson2.c if (reg.cnt1_enabled || reg.cnt2_enabled) reg 96 arch/mips/oprofile/op_model_loongson2.c write_c0_perfctrl(reg.ctrl); reg 103 arch/mips/oprofile/op_model_loongson2.c memset(®, 0, sizeof(reg)); reg 116 arch/mips/oprofile/op_model_loongson2.c enabled = reg.cnt1_enabled | reg.cnt2_enabled; reg 125 arch/mips/oprofile/op_model_loongson2.c if (reg.cnt1_enabled) reg 127 arch/mips/oprofile/op_model_loongson2.c counter1 = reg.reset_counter1; reg 130 arch/mips/oprofile/op_model_loongson2.c if (reg.cnt2_enabled) reg 132 arch/mips/oprofile/op_model_loongson2.c counter2 = reg.reset_counter2; reg 51 arch/mips/oprofile/op_model_loongson3.c } reg; reg 67 arch/mips/oprofile/op_model_loongson3.c reg.reset_counter1 = 0; reg 68 arch/mips/oprofile/op_model_loongson3.c reg.reset_counter2 = 0; reg 78 arch/mips/oprofile/op_model_loongson3.c reg.reset_counter1 = 0x8000000000000000ULL - ctr[0].count; reg 88 arch/mips/oprofile/op_model_loongson3.c reg.reset_counter2 = 0x8000000000000000ULL - ctr[1].count; reg 96 arch/mips/oprofile/op_model_loongson3.c reg.control1 = control1; reg 97 arch/mips/oprofile/op_model_loongson3.c reg.control2 = control2; reg 98 arch/mips/oprofile/op_model_loongson3.c reg.ctr1_enable = ctr[0].enabled; reg 99 arch/mips/oprofile/op_model_loongson3.c reg.ctr2_enable = ctr[1].enabled; reg 107 arch/mips/oprofile/op_model_loongson3.c perfcount1 = reg.reset_counter1; reg 108 arch/mips/oprofile/op_model_loongson3.c perfcount2 = reg.reset_counter2; reg 116 arch/mips/oprofile/op_model_loongson3.c reg.control1 |= (LOONGSON3_PERFCTRL_W|LOONGSON3_PERFCTRL_M); reg 117 arch/mips/oprofile/op_model_loongson3.c reg.control2 |= (LOONGSON3_PERFCTRL_W|LOONGSON3_PERFCTRL_M); reg 119 arch/mips/oprofile/op_model_loongson3.c if (reg.ctr1_enable) reg 120 arch/mips/oprofile/op_model_loongson3.c write_c0_perflo1(reg.control1); reg 121 arch/mips/oprofile/op_model_loongson3.c if (reg.ctr2_enable) reg 122 arch/mips/oprofile/op_model_loongson3.c write_c0_perflo2(reg.control2); reg 130 arch/mips/oprofile/op_model_loongson3.c memset(®, 0, sizeof(reg)); reg 150 arch/mips/oprofile/op_model_loongson3.c if (reg.ctr1_enable) reg 152 arch/mips/oprofile/op_model_loongson3.c counter1 = reg.reset_counter1; reg 155 arch/mips/oprofile/op_model_loongson3.c if (reg.ctr2_enable) reg 157 arch/mips/oprofile/op_model_loongson3.c counter2 = reg.reset_counter2; reg 173 arch/mips/oprofile/op_model_loongson3.c write_c0_perflo1(reg.control1); reg 174 arch/mips/oprofile/op_model_loongson3.c write_c0_perflo2(reg.control2); reg 131 arch/mips/oprofile/op_model_mipsxx.c } reg; reg 142 arch/mips/oprofile/op_model_mipsxx.c reg.control[i] = 0; reg 143 arch/mips/oprofile/op_model_mipsxx.c reg.counter[i] = 0; reg 148 arch/mips/oprofile/op_model_mipsxx.c reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) | reg 151 arch/mips/oprofile/op_model_mipsxx.c reg.control[i] |= MIPS_PERFCTRL_K; reg 153 arch/mips/oprofile/op_model_mipsxx.c reg.control[i] |= MIPS_PERFCTRL_U; reg 155 arch/mips/oprofile/op_model_mipsxx.c reg.control[i] |= MIPS_PERFCTRL_EXL; reg 157 arch/mips/oprofile/op_model_mipsxx.c reg.control[i] |= XLR_PERFCTRL_ALLTHREADS; reg 158 arch/mips/oprofile/op_model_mipsxx.c reg.counter[i] = 0x80000000 - ctr[i].count; reg 174 arch/mips/oprofile/op_model_mipsxx.c w_c0_perfcntr3(reg.counter[3]); reg 178 arch/mips/oprofile/op_model_mipsxx.c w_c0_perfcntr2(reg.counter[2]); reg 182 arch/mips/oprofile/op_model_mipsxx.c w_c0_perfcntr1(reg.counter[1]); reg 186 arch/mips/oprofile/op_model_mipsxx.c w_c0_perfcntr0(reg.counter[0]); reg 200 arch/mips/oprofile/op_model_mipsxx.c w_c0_perfctrl3(WHAT | reg.control[3]); reg 203 arch/mips/oprofile/op_model_mipsxx.c w_c0_perfctrl2(WHAT | reg.control[2]); reg 206 arch/mips/oprofile/op_model_mipsxx.c w_c0_perfctrl1(WHAT | reg.control[1]); reg 209 arch/mips/oprofile/op_model_mipsxx.c w_c0_perfctrl0(WHAT | reg.control[0]); reg 255 arch/mips/oprofile/op_model_mipsxx.c w_c0_perfcntr ## n(reg.counter[n]); \ reg 37 arch/mips/pci/fixup-cobalt.c #define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char)(reg) >> 4) reg 67 arch/mips/pci/ops-bcm63xx.c unsigned int slot, func, reg; reg 72 arch/mips/pci/ops-bcm63xx.c reg = where >> 2; reg 81 arch/mips/pci/ops-bcm63xx.c if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT)) reg 85 arch/mips/pci/ops-bcm63xx.c val = (reg << MPI_L2PCFG_REG_SHIFT); reg 210 arch/mips/pci/ops-bcm63xx.c unsigned int reg; reg 214 arch/mips/pci/ops-bcm63xx.c reg = where >> 2; reg 215 arch/mips/pci/ops-bcm63xx.c switch (reg) { reg 293 arch/mips/pci/ops-bcm63xx.c unsigned int reg; reg 303 arch/mips/pci/ops-bcm63xx.c reg = where >> 2; reg 304 arch/mips/pci/ops-bcm63xx.c switch (reg) { reg 487 arch/mips/pci/ops-bcm63xx.c u32 reg = where & ~3; reg 493 arch/mips/pci/ops-bcm63xx.c reg += PCIE_DEVICE_OFFSET; reg 495 arch/mips/pci/ops-bcm63xx.c data = bcm_pcie_readl(reg); reg 507 arch/mips/pci/ops-bcm63xx.c u32 reg = where & ~3; reg 513 arch/mips/pci/ops-bcm63xx.c reg += PCIE_DEVICE_OFFSET; reg 516 arch/mips/pci/ops-bcm63xx.c data = bcm_pcie_readl(reg); reg 519 arch/mips/pci/ops-bcm63xx.c bcm_pcie_writel(data, reg); reg 35 arch/mips/pci/ops-bonito64.c int reg = where & ~3; reg 42 arch/mips/pci/ops-bonito64.c addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg; reg 46 arch/mips/pci/ops-bonito64.c addr = (busnum << 16) | (device << 11) | (function << 8) | reg; reg 43 arch/mips/pci/ops-loongson2.c int reg = where & ~3; reg 57 arch/mips/pci/ops-loongson2.c if ((PCI_IDSEL_CS5536 == device) && (reg < PCI_MSR_CTRL)) { reg 60 arch/mips/pci/ops-loongson2.c *data = cs5536_pci_conf_read4(function, reg); reg 63 arch/mips/pci/ops-loongson2.c cs5536_pci_conf_write4(function, reg, *data); reg 73 arch/mips/pci/ops-loongson2.c addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg; reg 77 arch/mips/pci/ops-loongson2.c addr = (busnum << 16) | (device << 11) | (function << 8) | reg; reg 23 arch/mips/pci/ops-loongson3.c int reg = where & ~3; reg 28 arch/mips/pci/ops-loongson3.c addr = (busnum << 16) | (device << 11) | (function << 8) | reg; reg 47 arch/mips/pci/ops-loongson3.c addr |= busnum << 20 | device << 15 | function << 12 | reg; reg 31 arch/mips/pci/ops-mace.c unsigned int reg) reg 35 arch/mips/pci/ops-mace.c (reg & 0xfc); reg 41 arch/mips/pci/ops-mace.c int reg, int size, u32 *val) reg 47 arch/mips/pci/ops-mace.c mace->pci.config_addr = mkaddr(bus, devfn, reg); reg 50 arch/mips/pci/ops-mace.c *val = mace->pci.config_data.b[(reg & 3) ^ 3]; reg 53 arch/mips/pci/ops-mace.c *val = mace->pci.config_data.w[((reg >> 1) & 1) ^ 1]; reg 66 arch/mips/pci/ops-mace.c if (bus->number == 0 && reg == 0x40 && size == 4 && reg 70 arch/mips/pci/ops-mace.c DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val); reg 77 arch/mips/pci/ops-mace.c int reg, int size, u32 val) reg 79 arch/mips/pci/ops-mace.c mace->pci.config_addr = mkaddr(bus, devfn, reg); reg 82 arch/mips/pci/ops-mace.c mace->pci.config_data.b[(reg & 3) ^ 3] = val; reg 85 arch/mips/pci/ops-mace.c mace->pci.config_data.w[((reg >> 1) & 1) ^ 1] = val; reg 92 arch/mips/pci/ops-mace.c DPRINTK("write%d: reg=%08x,val=%02x\n", size * 8, reg, val); reg 12 arch/mips/pci/ops-nile4.c #define LO(reg) (reg / 4) reg 13 arch/mips/pci/ops-nile4.c #define HI(reg) (reg / 4 + 1) reg 24 arch/mips/pci/ops-sni.c static int set_config_address(unsigned int busno, unsigned int devfn, int reg) reg 26 arch/mips/pci/ops-sni.c if ((devfn > 255) || (reg > 255)) reg 35 arch/mips/pci/ops-sni.c (reg & 0xfc); reg 40 arch/mips/pci/ops-sni.c static int pcimt_read(struct pci_bus *bus, unsigned int devfn, int reg, reg 45 arch/mips/pci/ops-sni.c if ((res = set_config_address(bus->number, devfn, reg))) reg 50 arch/mips/pci/ops-sni.c *val = inb(PCIMT_CONFIG_DATA + (reg & 3)); reg 53 arch/mips/pci/ops-sni.c *val = inw(PCIMT_CONFIG_DATA + (reg & 2)); reg 63 arch/mips/pci/ops-sni.c static int pcimt_write(struct pci_bus *bus, unsigned int devfn, int reg, reg 68 arch/mips/pci/ops-sni.c if ((res = set_config_address(bus->number, devfn, reg))) reg 73 arch/mips/pci/ops-sni.c outb(val, PCIMT_CONFIG_DATA + (reg & 3)); reg 76 arch/mips/pci/ops-sni.c outw(val, PCIMT_CONFIG_DATA + (reg & 2)); reg 91 arch/mips/pci/ops-sni.c static int pcit_set_config_address(unsigned int busno, unsigned int devfn, int reg) reg 93 arch/mips/pci/ops-sni.c if ((devfn > 255) || (reg > 255) || (busno > 255)) reg 96 arch/mips/pci/ops-sni.c outl((1 << 31) | ((busno & 0xff) << 16) | ((devfn & 0xff) << 8) | (reg & 0xfc), 0xcf8); reg 100 arch/mips/pci/ops-sni.c static int pcit_read(struct pci_bus *bus, unsigned int devfn, int reg, reg 120 arch/mips/pci/ops-sni.c if ((res = pcit_set_config_address(bus->number, devfn, reg))) reg 125 arch/mips/pci/ops-sni.c *val = inb(PCIMT_CONFIG_DATA + (reg & 3)); reg 128 arch/mips/pci/ops-sni.c *val = inw(PCIMT_CONFIG_DATA + (reg & 2)); reg 137 arch/mips/pci/ops-sni.c static int pcit_write(struct pci_bus *bus, unsigned int devfn, int reg, reg 142 arch/mips/pci/ops-sni.c if ((res = pcit_set_config_address(bus->number, devfn, reg))) reg 147 arch/mips/pci/ops-sni.c outb(val, PCIMT_CONFIG_DATA + (reg & 3)); reg 150 arch/mips/pci/ops-sni.c outw(val, PCIMT_CONFIG_DATA + (reg & 2)); reg 190 arch/mips/pci/pci-ar2315.c static inline u32 ar2315_pci_reg_read(struct ar2315_pci_ctrl *apc, u32 reg) reg 192 arch/mips/pci/pci-ar2315.c return __raw_readl(apc->mmr_mem + reg); reg 195 arch/mips/pci/pci-ar2315.c static inline void ar2315_pci_reg_write(struct ar2315_pci_ctrl *apc, u32 reg, reg 198 arch/mips/pci/pci-ar2315.c __raw_writel(val, apc->mmr_mem + reg); reg 201 arch/mips/pci/pci-ar2315.c static inline void ar2315_pci_reg_mask(struct ar2315_pci_ctrl *apc, u32 reg, reg 204 arch/mips/pci/pci-ar2315.c u32 ret = ar2315_pci_reg_read(apc, reg); reg 208 arch/mips/pci/pci-ar2315.c ar2315_pci_reg_write(apc, reg, ret); reg 192 arch/mips/pci/pci-bcm1480.c uint64_t reg; reg 210 arch/mips/pci/pci-bcm1480.c reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG)); reg 211 arch/mips/pci/pci-bcm1480.c if (!(reg & M_BCM1480_SYS_PCI_HOST)) { reg 98 arch/mips/pci/pci-bcm63xx.c static u32 bcm63xx_int_cfg_readl(u32 reg) reg 102 arch/mips/pci/pci-bcm63xx.c tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK; reg 109 arch/mips/pci/pci-bcm63xx.c static void bcm63xx_int_cfg_writel(u32 val, u32 reg) reg 113 arch/mips/pci/pci-bcm63xx.c tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK; reg 124 arch/mips/pci/pci-bcm63xx.c u32 reg; reg 128 arch/mips/pci/pci-bcm63xx.c reg = MISC_SERDES_CTRL_6328_REG; reg 130 arch/mips/pci/pci-bcm63xx.c reg = MISC_SERDES_CTRL_6362_REG; reg 132 arch/mips/pci/pci-bcm63xx.c val = bcm_misc_readl(reg); reg 134 arch/mips/pci/pci-bcm63xx.c bcm_misc_writel(val, reg); reg 79 arch/mips/pci/pci-mt7620.c static inline void bridge_w32(u32 val, unsigned reg) reg 81 arch/mips/pci/pci-mt7620.c iowrite32(val, bridge_base + reg); reg 84 arch/mips/pci/pci-mt7620.c static inline u32 bridge_r32(unsigned reg) reg 86 arch/mips/pci/pci-mt7620.c return ioread32(bridge_base + reg); reg 89 arch/mips/pci/pci-mt7620.c static inline void pcie_w32(u32 val, unsigned reg) reg 91 arch/mips/pci/pci-mt7620.c iowrite32(val, pcie_base + reg); reg 94 arch/mips/pci/pci-mt7620.c static inline u32 pcie_r32(unsigned reg) reg 96 arch/mips/pci/pci-mt7620.c return ioread32(pcie_base + reg); reg 99 arch/mips/pci/pci-mt7620.c static inline void pcie_m32(u32 clr, u32 set, unsigned reg) reg 101 arch/mips/pci/pci-mt7620.c u32 val = pcie_r32(reg); reg 105 arch/mips/pci/pci-mt7620.c pcie_w32(val, reg); reg 56 arch/mips/pci/pci-octeon.c uint64_t reg:8; reg 258 arch/mips/pci/pci-octeon.c int reg, int size, u32 *val) reg 271 arch/mips/pci/pci-octeon.c pci_addr.s.reg = reg; reg 292 arch/mips/pci/pci-octeon.c int reg, int size, u32 val) reg 305 arch/mips/pci/pci-octeon.c pci_addr.s.reg = reg; reg 46 arch/mips/pci/pci-rt2880.c static u32 rt2880_pci_reg_read(u32 reg) reg 48 arch/mips/pci/pci-rt2880.c return readl(rt2880_pci_base + reg); reg 51 arch/mips/pci/pci-rt2880.c static void rt2880_pci_reg_write(u32 val, u32 reg) reg 53 arch/mips/pci/pci-rt2880.c writel(val, rt2880_pci_base + reg); reg 152 arch/mips/pci/pci-rt2880.c static inline u32 rt2880_pci_read_u32(unsigned long reg) reg 158 arch/mips/pci/pci-rt2880.c address = rt2880_pci_get_cfgaddr(0, 0, 0, reg); reg 168 arch/mips/pci/pci-rt2880.c static inline void rt2880_pci_write_u32(unsigned long reg, u32 val) reg 173 arch/mips/pci/pci-rt2880.c address = rt2880_pci_get_cfgaddr(0, 0, 0, reg); reg 81 arch/mips/pci/pci-rt3883.c unsigned reg) reg 83 arch/mips/pci/pci-rt3883.c return ioread32(rpc->base + reg); reg 87 arch/mips/pci/pci-rt3883.c u32 val, unsigned reg) reg 89 arch/mips/pci/pci-rt3883.c iowrite32(val, rpc->base + reg); reg 101 arch/mips/pci/pci-rt3883.c unsigned func, unsigned reg) reg 107 arch/mips/pci/pci-rt3883.c address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); reg 117 arch/mips/pci/pci-rt3883.c unsigned func, unsigned reg, u32 val) reg 122 arch/mips/pci/pci-rt3883.c address = rt3883_pci_get_cfgaddr(bus, slot, func, reg); reg 200 arch/mips/pci/pci-sb1250.c uint64_t reg; reg 219 arch/mips/pci/pci-sb1250.c reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG)); reg 220 arch/mips/pci/pci-sb1250.c if (!(reg & M_SYS_PCI_HOST)) { reg 44 arch/mips/pci/pci-virtio-guest.c unsigned int devfn, int reg) reg 48 arch/mips/pci/pci-virtio-guest.c pca.register_number = reg; reg 57 arch/mips/pci/pci-virtio-guest.c unsigned int devfn, int reg, int size, u32 val) reg 59 arch/mips/pci/pci-virtio-guest.c pci_virtio_guest_write_config_addr(bus, devfn, reg); reg 63 arch/mips/pci/pci-virtio-guest.c outb(val, PCI_CONFIG_DATA + (reg & 3)); reg 66 arch/mips/pci/pci-virtio-guest.c outw(val, PCI_CONFIG_DATA + (reg & 2)); reg 77 arch/mips/pci/pci-virtio-guest.c int reg, int size, u32 *val) reg 79 arch/mips/pci/pci-virtio-guest.c pci_virtio_guest_write_config_addr(bus, devfn, reg); reg 83 arch/mips/pci/pci-virtio-guest.c *val = inb(PCI_CONFIG_DATA + (reg & 3)); reg 86 arch/mips/pci/pci-virtio-guest.c *val = inw(PCI_CONFIG_DATA + (reg & 2)); reg 31 arch/mips/pci/pci-vr41xx.h #define EA(reg) ((reg) &0xfffffffc) reg 64 arch/mips/pci/pci-vr41xx.h #define RTRYCNT(reg) ((reg) & 0x000000ffU) reg 242 arch/mips/pci/pci-xlp.c u32 reg; reg 252 arch/mips/pci/pci-xlp.c reg = nlm_read_bridge_reg(nbubase, reg 254 arch/mips/pci/pci-xlp.c nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_MEM_BASE, reg); reg 256 arch/mips/pci/pci-xlp.c reg = nlm_read_bridge_reg(nbubase, reg 259 arch/mips/pci/pci-xlp.c PCIE_9XX_BYTE_SWAP_MEM_LIM, reg | 0xfff); reg 261 arch/mips/pci/pci-xlp.c reg = nlm_read_bridge_reg(nbubase, reg 263 arch/mips/pci/pci-xlp.c nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_IO_BASE, reg); reg 265 arch/mips/pci/pci-xlp.c reg = nlm_read_bridge_reg(nbubase, reg 268 arch/mips/pci/pci-xlp.c PCIE_9XX_BYTE_SWAP_IO_LIM, reg | 0xfff); reg 270 arch/mips/pci/pci-xlp.c reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link); reg 271 arch/mips/pci/pci-xlp.c nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg); reg 273 arch/mips/pci/pci-xlp.c reg = nlm_read_bridge_reg(nbubase, reg 275 arch/mips/pci/pci-xlp.c nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff); reg 277 arch/mips/pci/pci-xlp.c reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link); reg 278 arch/mips/pci/pci-xlp.c nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg); reg 280 arch/mips/pci/pci-xlp.c reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link); reg 281 arch/mips/pci/pci-xlp.c nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); reg 293 arch/mips/pci/pci-xlp.c u32 reg; reg 315 arch/mips/pci/pci-xlp.c reg = nlm_read_pci_reg(pciebase, 0xf); reg 316 arch/mips/pci/pci-xlp.c reg &= ~0x1ffu; reg 317 arch/mips/pci/pci-xlp.c reg |= (1 << 8) | PIC_PCIE_LINK_LEGACY_IRQ(link); reg 318 arch/mips/pci/pci-xlp.c nlm_write_pci_reg(pciebase, 0xf, reg); reg 75 arch/mips/pci/pci-xtalk-bridge.c bridge_clr(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR); reg 514 arch/mips/pci/pci-xtalk-bridge.c bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR); reg 71 arch/mips/pci/pcie-octeon.c uint64_t reg:12; reg 229 arch/mips/pci/pcie-octeon.c int dev, int fn, int reg) reg 250 arch/mips/pci/pcie-octeon.c pcie_addr.config.reg = reg; reg 266 arch/mips/pci/pcie-octeon.c int fn, int reg) reg 269 arch/mips/pci/pcie-octeon.c __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg); reg 288 arch/mips/pci/pcie-octeon.c int fn, int reg) reg 291 arch/mips/pci/pcie-octeon.c __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg); reg 310 arch/mips/pci/pcie-octeon.c int fn, int reg) reg 313 arch/mips/pci/pcie-octeon.c __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg); reg 331 arch/mips/pci/pcie-octeon.c int reg, uint8_t val) reg 334 arch/mips/pci/pcie-octeon.c __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg); reg 350 arch/mips/pci/pcie-octeon.c int reg, uint16_t val) reg 353 arch/mips/pci/pcie-octeon.c __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg); reg 369 arch/mips/pci/pcie-octeon.c int reg, uint32_t val) reg 372 arch/mips/pci/pcie-octeon.c __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg); reg 1538 arch/mips/pci/pcie-octeon.c unsigned int devfn, int reg, int size, reg 1668 arch/mips/pci/pcie-octeon.c " size=%d ", pcie_port, bus_number, devfn, reg, size); reg 1673 arch/mips/pci/pcie-octeon.c devfn >> 3, devfn & 0x7, reg); reg 1677 arch/mips/pci/pcie-octeon.c devfn >> 3, devfn & 0x7, reg); reg 1681 arch/mips/pci/pcie-octeon.c devfn >> 3, devfn & 0x7, reg); reg 1710 arch/mips/pci/pcie-octeon.c int reg, int size, u32 *val) reg 1712 arch/mips/pci/pcie-octeon.c return octeon_pcie_read_config(0, bus, devfn, reg, size, val); reg 1716 arch/mips/pci/pcie-octeon.c int reg, int size, u32 *val) reg 1718 arch/mips/pci/pcie-octeon.c return octeon_pcie_read_config(1, bus, devfn, reg, size, val); reg 1722 arch/mips/pci/pcie-octeon.c int reg, int size, u32 *val) reg 1731 arch/mips/pci/pcie-octeon.c unsigned int devfn, int reg, reg 1743 arch/mips/pci/pcie-octeon.c reg, size, val); reg 1749 arch/mips/pci/pcie-octeon.c devfn & 0x7, reg, val); reg 1753 arch/mips/pci/pcie-octeon.c devfn & 0x7, reg, val); reg 1757 arch/mips/pci/pcie-octeon.c devfn & 0x7, reg, val); reg 1766 arch/mips/pci/pcie-octeon.c int reg, int size, u32 val) reg 1768 arch/mips/pci/pcie-octeon.c return octeon_pcie_write_config(0, bus, devfn, reg, size, val); reg 1772 arch/mips/pci/pcie-octeon.c int reg, int size, u32 val) reg 1774 arch/mips/pci/pcie-octeon.c return octeon_pcie_write_config(1, bus, devfn, reg, size, val); reg 1778 arch/mips/pci/pcie-octeon.c int reg, int size, u32 val) reg 26 arch/mips/pic32/common/reset.c void __iomem *reg = reg 32 arch/mips/pic32/common/reset.c __raw_writel(1, reg); reg 33 arch/mips/pic32/common/reset.c (void)__raw_readl(reg); reg 68 arch/mips/pic32/pic32mzda/early_pin.c int reg; reg 130 arch/mips/pic32/pic32mzda/early_pin.c __raw_writel(pin, pps_base + input_pin_reg[i].reg); reg 196 arch/mips/pic32/pic32mzda/early_pin.c int reg; reg 261 arch/mips/pic32/pic32mzda/early_pin.c pps_base + output_pin_reg[i].reg); reg 285 arch/mips/pnx833x/common/interrupts.c unsigned long reg = PNX833X_CLOCK_CPUCP_CTL; reg 287 arch/mips/pnx833x/common/interrupts.c if (!(PNX833X_BIT(reg, CLOCK_CPUCP_CTL, EXIT_RESET))) { reg 296 arch/mips/pnx833x/common/interrupts.c mips_hpt_frequency = freq[PNX833X_FIELD(reg, CLOCK_CPUCP_CTL, DIV_CLOCK)]; reg 35 arch/mips/ralink/early_printk.c static inline void uart_w32(u32 val, unsigned reg) reg 37 arch/mips/ralink/early_printk.c __raw_writel(val, uart_membase + reg); reg 40 arch/mips/ralink/early_printk.c static inline u32 uart_r32(unsigned reg) reg 42 arch/mips/ralink/early_printk.c return __raw_readl(uart_membase + reg); reg 59 arch/mips/ralink/early_printk.c u32 reg = uart_r32(UART_REG_LCR + (0x100 * i)); reg 61 arch/mips/ralink/early_printk.c if (!reg) reg 59 arch/mips/ralink/irq.c static inline void rt_intc_w32(u32 val, unsigned reg) reg 61 arch/mips/ralink/irq.c __raw_writel(val, rt_intc_membase + rt_intc_regs[reg]); reg 64 arch/mips/ralink/irq.c static inline u32 rt_intc_r32(unsigned reg) reg 66 arch/mips/ralink/irq.c return __raw_readl(rt_intc_membase + rt_intc_regs[reg]); reg 384 arch/mips/ralink/mt7620.c u32 reg; reg 386 arch/mips/ralink/mt7620.c reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); reg 387 arch/mips/ralink/mt7620.c if (reg & SYSCFG0_XTAL_FREQ_SEL) reg 396 arch/mips/ralink/mt7620.c u32 reg; reg 398 arch/mips/ralink/mt7620.c reg = rt_sysc_r32(SYSC_REG_CLKCFG0); reg 399 arch/mips/ralink/mt7620.c if (reg & CLKCFG0_PERI_CLK_SEL) reg 410 arch/mips/ralink/mt7620.c u32 reg; reg 414 arch/mips/ralink/mt7620.c reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0); reg 415 arch/mips/ralink/mt7620.c if (reg & CPLL_CFG0_BYPASS_REF_CLK) reg 418 arch/mips/ralink/mt7620.c if ((reg & CPLL_CFG0_SW_CFG) == 0) reg 421 arch/mips/ralink/mt7620.c mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) & reg 424 arch/mips/ralink/mt7620.c if (reg & CPLL_CFG0_LC_CURFCK) reg 427 arch/mips/ralink/mt7620.c div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) & reg 438 arch/mips/ralink/mt7620.c u32 reg; reg 440 arch/mips/ralink/mt7620.c reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1); reg 441 arch/mips/ralink/mt7620.c if (reg & CPLL_CFG1_CPU_AUX1) reg 444 arch/mips/ralink/mt7620.c if (reg & CPLL_CFG1_CPU_AUX0) reg 453 arch/mips/ralink/mt7620.c u32 reg; reg 457 arch/mips/ralink/mt7620.c reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); reg 459 arch/mips/ralink/mt7620.c mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK; reg 460 arch/mips/ralink/mt7620.c div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) & reg 486 arch/mips/ralink/mt7620.c u32 reg; reg 490 arch/mips/ralink/mt7620.c reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); reg 492 arch/mips/ralink/mt7620.c ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) & reg 37 arch/mips/ralink/timer.c static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val) reg 39 arch/mips/ralink/timer.c __raw_writel(val, rt->membase + reg); reg 42 arch/mips/ralink/timer.c static inline u32 rt_timer_r32(struct rt_timer *rt, u8 reg) reg 44 arch/mips/ralink/timer.c return __raw_readl(rt->membase + reg); reg 56 arch/mips/sgi-ip22/ip22-nvram.c static inline void eeprom_cmd(unsigned int *ctrl, unsigned cmd, unsigned reg) reg 61 arch/mips/sgi-ip22/ip22-nvram.c ser_cmd = cmd | (reg << (16 - BITS_IN_COMMAND)); reg 77 arch/mips/sgi-ip22/ip22-nvram.c unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg) reg 84 arch/mips/sgi-ip22/ip22-nvram.c eeprom_cmd(ctrl, EEPROM_READ, reg); reg 107 arch/mips/sgi-ip22/ip22-nvram.c unsigned short ip22_nvram_read(int reg) reg 112 arch/mips/sgi-ip22/ip22-nvram.c return ip22_eeprom_read(&hpc3c0->eeprom, reg); reg 116 arch/mips/sgi-ip22/ip22-nvram.c reg <<= 1; reg 117 arch/mips/sgi-ip22/ip22-nvram.c tmp = hpc3c0->bbram[reg++] & 0xff; reg 118 arch/mips/sgi-ip22/ip22-nvram.c return (tmp << 8) | (hpc3c0->bbram[reg] & 0xff); reg 81 arch/mips/sibyte/swarm/rtc_m41t81.c #define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg)) reg 56 arch/mips/sibyte/swarm/rtc_xicor1241.c #define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg)) reg 158 arch/mips/sibyte/swarm/setup.c void *reg; reg 162 arch/mips/sibyte/swarm/setup.c reg = IOADDR(LEDS_PHYS) + 0x20 + ((3 - i) << 3); reg 165 arch/mips/sibyte/swarm/setup.c writeb(' ', reg); reg 167 arch/mips/sibyte/swarm/setup.c writeb(str[i], reg); reg 86 arch/mips/txx9/generic/smsc_fdc37m81x.c u8 smsc_fdc37m81x_config_get(u8 reg) reg 91 arch/mips/txx9/generic/smsc_fdc37m81x.c val = smsc_fdc37m81x_rd(reg); reg 96 arch/mips/txx9/generic/smsc_fdc37m81x.c void smsc_fdc37m81x_config_set(u8 reg, u8 val) reg 99 arch/mips/txx9/generic/smsc_fdc37m81x.c smsc_dc37m81x_wr(reg, val); reg 127 arch/mips/txx9/generic/smsc_fdc37m81x.c static void smsc_fdc37m81x_config_dump_one(const char *key, u8 dev, u8 reg) reg 129 arch/mips/txx9/generic/smsc_fdc37m81x.c pr_info("%s: dev=0x%02x reg=0x%02x val=0x%02x\n", key, dev, reg, reg 130 arch/mips/txx9/generic/smsc_fdc37m81x.c smsc_fdc37m81x_rd(reg)); reg 32 arch/nds32/include/asm/assembler.h #define USER(insn, reg, addr, opr) \ reg 33 arch/nds32/include/asm/assembler.h 9999: insn reg, addr, opr; \ reg 283 arch/nios2/include/asm/asm-macros.h .macro PUSH reg reg 292 arch/nios2/include/asm/asm-macros.h .macro POP reg reg 51 arch/nios2/kernel/misaligned.c static inline u32 get_reg_val(struct pt_regs *fp, int reg) reg 53 arch/nios2/kernel/misaligned.c u8 *p = ((u8 *)fp) + reg_offsets[reg]; reg 57 arch/nios2/kernel/misaligned.c static inline void put_reg_val(struct pt_regs *fp, int reg, u32 val) reg 59 arch/nios2/kernel/misaligned.c u8 *p = ((u8 *)fp) + reg_offsets[reg]; reg 227 arch/openrisc/kernel/setup.c static inline unsigned long extract_value_bits(unsigned long reg, reg 230 arch/openrisc/kernel/setup.c return (reg >> bit_nr) & (0 << width); reg 233 arch/openrisc/kernel/setup.c static inline unsigned long extract_value(unsigned long reg, unsigned long mask) reg 236 arch/openrisc/kernel/setup.c reg = reg >> 1; reg 239 arch/openrisc/kernel/setup.c return mask & reg; reg 19 arch/openrisc/mm/cache.c static void cache_loop(struct page *page, const unsigned int reg) reg 25 arch/openrisc/mm/cache.c mtspr(reg, line); reg 11 arch/parisc/include/asm/asmregs.h rp: .reg %r2 reg 12 arch/parisc/include/asm/asmregs.h arg3: .reg %r23 reg 13 arch/parisc/include/asm/asmregs.h arg2: .reg %r24 reg 14 arch/parisc/include/asm/asmregs.h arg1: .reg %r25 reg 15 arch/parisc/include/asm/asmregs.h arg0: .reg %r26 reg 16 arch/parisc/include/asm/asmregs.h dp: .reg %r27 reg 17 arch/parisc/include/asm/asmregs.h ret0: .reg %r28 reg 18 arch/parisc/include/asm/asmregs.h ret1: .reg %r29 reg 19 arch/parisc/include/asm/asmregs.h sl: .reg %r29 reg 20 arch/parisc/include/asm/asmregs.h sp: .reg %r30 reg 24 arch/parisc/include/asm/asmregs.h arg7: .reg r19 reg 25 arch/parisc/include/asm/asmregs.h arg6: .reg r20 reg 26 arch/parisc/include/asm/asmregs.h arg5: .reg r21 reg 27 arch/parisc/include/asm/asmregs.h arg4: .reg r22 reg 28 arch/parisc/include/asm/asmregs.h gp: .reg r27 reg 29 arch/parisc/include/asm/asmregs.h ap: .reg r29 reg 33 arch/parisc/include/asm/asmregs.h r0: .reg %r0 reg 34 arch/parisc/include/asm/asmregs.h r1: .reg %r1 reg 35 arch/parisc/include/asm/asmregs.h r2: .reg %r2 reg 36 arch/parisc/include/asm/asmregs.h r3: .reg %r3 reg 37 arch/parisc/include/asm/asmregs.h r4: .reg %r4 reg 38 arch/parisc/include/asm/asmregs.h r5: .reg %r5 reg 39 arch/parisc/include/asm/asmregs.h r6: .reg %r6 reg 40 arch/parisc/include/asm/asmregs.h r7: .reg %r7 reg 41 arch/parisc/include/asm/asmregs.h r8: .reg %r8 reg 42 arch/parisc/include/asm/asmregs.h r9: .reg %r9 reg 43 arch/parisc/include/asm/asmregs.h r10: .reg %r10 reg 44 arch/parisc/include/asm/asmregs.h r11: .reg %r11 reg 45 arch/parisc/include/asm/asmregs.h r12: .reg %r12 reg 46 arch/parisc/include/asm/asmregs.h r13: .reg %r13 reg 47 arch/parisc/include/asm/asmregs.h r14: .reg %r14 reg 48 arch/parisc/include/asm/asmregs.h r15: .reg %r15 reg 49 arch/parisc/include/asm/asmregs.h r16: .reg %r16 reg 50 arch/parisc/include/asm/asmregs.h r17: .reg %r17 reg 51 arch/parisc/include/asm/asmregs.h r18: .reg %r18 reg 52 arch/parisc/include/asm/asmregs.h r19: .reg %r19 reg 53 arch/parisc/include/asm/asmregs.h r20: .reg %r20 reg 54 arch/parisc/include/asm/asmregs.h r21: .reg %r21 reg 55 arch/parisc/include/asm/asmregs.h r22: .reg %r22 reg 56 arch/parisc/include/asm/asmregs.h r23: .reg %r23 reg 57 arch/parisc/include/asm/asmregs.h r24: .reg %r24 reg 58 arch/parisc/include/asm/asmregs.h r25: .reg %r25 reg 59 arch/parisc/include/asm/asmregs.h r26: .reg %r26 reg 60 arch/parisc/include/asm/asmregs.h r27: .reg %r27 reg 61 arch/parisc/include/asm/asmregs.h r28: .reg %r28 reg 62 arch/parisc/include/asm/asmregs.h r29: .reg %r29 reg 63 arch/parisc/include/asm/asmregs.h r30: .reg %r30 reg 64 arch/parisc/include/asm/asmregs.h r31: .reg %r31 reg 69 arch/parisc/include/asm/asmregs.h sr0: .reg %sr0 reg 70 arch/parisc/include/asm/asmregs.h sr1: .reg %sr1 reg 71 arch/parisc/include/asm/asmregs.h sr2: .reg %sr2 reg 72 arch/parisc/include/asm/asmregs.h sr3: .reg %sr3 reg 73 arch/parisc/include/asm/asmregs.h sr4: .reg %sr4 reg 74 arch/parisc/include/asm/asmregs.h sr5: .reg %sr5 reg 75 arch/parisc/include/asm/asmregs.h sr6: .reg %sr6 reg 76 arch/parisc/include/asm/asmregs.h sr7: .reg %sr7 reg 81 arch/parisc/include/asm/asmregs.h fr0: .reg %fr0 reg 82 arch/parisc/include/asm/asmregs.h fr1: .reg %fr1 reg 83 arch/parisc/include/asm/asmregs.h fr2: .reg %fr2 reg 84 arch/parisc/include/asm/asmregs.h fr3: .reg %fr3 reg 85 arch/parisc/include/asm/asmregs.h fr4: .reg %fr4 reg 86 arch/parisc/include/asm/asmregs.h fr5: .reg %fr5 reg 87 arch/parisc/include/asm/asmregs.h fr6: .reg %fr6 reg 88 arch/parisc/include/asm/asmregs.h fr7: .reg %fr7 reg 89 arch/parisc/include/asm/asmregs.h fr8: .reg %fr8 reg 90 arch/parisc/include/asm/asmregs.h fr9: .reg %fr9 reg 91 arch/parisc/include/asm/asmregs.h fr10: .reg %fr10 reg 92 arch/parisc/include/asm/asmregs.h fr11: .reg %fr11 reg 93 arch/parisc/include/asm/asmregs.h fr12: .reg %fr12 reg 94 arch/parisc/include/asm/asmregs.h fr13: .reg %fr13 reg 95 arch/parisc/include/asm/asmregs.h fr14: .reg %fr14 reg 96 arch/parisc/include/asm/asmregs.h fr15: .reg %fr15 reg 97 arch/parisc/include/asm/asmregs.h fr16: .reg %fr16 reg 98 arch/parisc/include/asm/asmregs.h fr17: .reg %fr17 reg 99 arch/parisc/include/asm/asmregs.h fr18: .reg %fr18 reg 100 arch/parisc/include/asm/asmregs.h fr19: .reg %fr19 reg 101 arch/parisc/include/asm/asmregs.h fr20: .reg %fr20 reg 102 arch/parisc/include/asm/asmregs.h fr21: .reg %fr21 reg 103 arch/parisc/include/asm/asmregs.h fr22: .reg %fr22 reg 104 arch/parisc/include/asm/asmregs.h fr23: .reg %fr23 reg 105 arch/parisc/include/asm/asmregs.h fr24: .reg %fr24 reg 106 arch/parisc/include/asm/asmregs.h fr25: .reg %fr25 reg 107 arch/parisc/include/asm/asmregs.h fr26: .reg %fr26 reg 108 arch/parisc/include/asm/asmregs.h fr27: .reg %fr27 reg 109 arch/parisc/include/asm/asmregs.h fr28: .reg %fr28 reg 110 arch/parisc/include/asm/asmregs.h fr29: .reg %fr29 reg 111 arch/parisc/include/asm/asmregs.h fr30: .reg %fr30 reg 112 arch/parisc/include/asm/asmregs.h fr31: .reg %fr31 reg 117 arch/parisc/include/asm/asmregs.h rctr: .reg %cr0 reg 118 arch/parisc/include/asm/asmregs.h pidr1: .reg %cr8 reg 119 arch/parisc/include/asm/asmregs.h pidr2: .reg %cr9 reg 120 arch/parisc/include/asm/asmregs.h ccr: .reg %cr10 reg 121 arch/parisc/include/asm/asmregs.h sar: .reg %cr11 reg 122 arch/parisc/include/asm/asmregs.h pidr3: .reg %cr12 reg 123 arch/parisc/include/asm/asmregs.h pidr4: .reg %cr13 reg 124 arch/parisc/include/asm/asmregs.h iva: .reg %cr14 reg 125 arch/parisc/include/asm/asmregs.h eiem: .reg %cr15 reg 126 arch/parisc/include/asm/asmregs.h itmr: .reg %cr16 reg 127 arch/parisc/include/asm/asmregs.h pcsq: .reg %cr17 reg 128 arch/parisc/include/asm/asmregs.h pcoq: .reg %cr18 reg 129 arch/parisc/include/asm/asmregs.h iir: .reg %cr19 reg 130 arch/parisc/include/asm/asmregs.h isr: .reg %cr20 reg 131 arch/parisc/include/asm/asmregs.h ior: .reg %cr21 reg 132 arch/parisc/include/asm/asmregs.h ipsw: .reg %cr22 reg 133 arch/parisc/include/asm/asmregs.h eirr: .reg %cr23 reg 134 arch/parisc/include/asm/asmregs.h tr0: .reg %cr24 reg 135 arch/parisc/include/asm/asmregs.h tr1: .reg %cr25 reg 136 arch/parisc/include/asm/asmregs.h tr2: .reg %cr26 reg 137 arch/parisc/include/asm/asmregs.h tr3: .reg %cr27 reg 138 arch/parisc/include/asm/asmregs.h tr4: .reg %cr28 reg 139 arch/parisc/include/asm/asmregs.h tr5: .reg %cr29 reg 140 arch/parisc/include/asm/asmregs.h tr6: .reg %cr30 reg 141 arch/parisc/include/asm/asmregs.h tr7: .reg %cr31 reg 144 arch/parisc/include/asm/asmregs.h cr0: .reg %cr0 reg 145 arch/parisc/include/asm/asmregs.h cr8: .reg %cr8 reg 146 arch/parisc/include/asm/asmregs.h cr9: .reg %cr9 reg 147 arch/parisc/include/asm/asmregs.h cr10: .reg %cr10 reg 148 arch/parisc/include/asm/asmregs.h cr11: .reg %cr11 reg 149 arch/parisc/include/asm/asmregs.h cr12: .reg %cr12 reg 150 arch/parisc/include/asm/asmregs.h cr13: .reg %cr13 reg 151 arch/parisc/include/asm/asmregs.h cr14: .reg %cr14 reg 152 arch/parisc/include/asm/asmregs.h cr15: .reg %cr15 reg 153 arch/parisc/include/asm/asmregs.h cr16: .reg %cr16 reg 154 arch/parisc/include/asm/asmregs.h cr17: .reg %cr17 reg 155 arch/parisc/include/asm/asmregs.h cr18: .reg %cr18 reg 156 arch/parisc/include/asm/asmregs.h cr19: .reg %cr19 reg 157 arch/parisc/include/asm/asmregs.h cr20: .reg %cr20 reg 158 arch/parisc/include/asm/asmregs.h cr21: .reg %cr21 reg 159 arch/parisc/include/asm/asmregs.h cr22: .reg %cr22 reg 160 arch/parisc/include/asm/asmregs.h cr23: .reg %cr23 reg 161 arch/parisc/include/asm/asmregs.h cr24: .reg %cr24 reg 162 arch/parisc/include/asm/asmregs.h cr25: .reg %cr25 reg 163 arch/parisc/include/asm/asmregs.h cr26: .reg %cr26 reg 164 arch/parisc/include/asm/asmregs.h cr27: .reg %cr27 reg 165 arch/parisc/include/asm/asmregs.h cr28: .reg %cr28 reg 166 arch/parisc/include/asm/asmregs.h cr29: .reg %cr29 reg 167 arch/parisc/include/asm/asmregs.h cr30: .reg %cr30 reg 168 arch/parisc/include/asm/asmregs.h cr31: .reg %cr31 reg 142 arch/parisc/include/asm/assembly.h .macro load32 value, reg reg 29 arch/parisc/include/asm/special_insns.h #define mfctl(reg) ({ \ reg 32 arch/parisc/include/asm/special_insns.h "mfctl " #reg ",%0" : \ reg 51 arch/parisc/include/asm/special_insns.h #define mfsp(reg) ({ \ reg 54 arch/parisc/include/asm/special_insns.h "mfsp " #reg ",%0" : \ reg 401 arch/parisc/kernel/ptrace.c __u64 reg; reg 403 arch/parisc/kernel/ptrace.c pos /= sizeof(reg); reg 404 arch/parisc/kernel/ptrace.c count /= sizeof(reg); reg 416 arch/parisc/kernel/ptrace.c pos *= sizeof(reg); reg 417 arch/parisc/kernel/ptrace.c count *= sizeof(reg); reg 419 arch/parisc/kernel/ptrace.c ELF_NFPREG * sizeof(reg), -1); reg 430 arch/parisc/kernel/ptrace.c __u64 reg; reg 432 arch/parisc/kernel/ptrace.c pos /= sizeof(reg); reg 433 arch/parisc/kernel/ptrace.c count /= sizeof(reg); reg 440 arch/parisc/kernel/ptrace.c if (__get_user(reg, u++)) reg 442 arch/parisc/kernel/ptrace.c regs->fr[pos++] = reg; reg 447 arch/parisc/kernel/ptrace.c pos *= sizeof(reg); reg 448 arch/parisc/kernel/ptrace.c count *= sizeof(reg); reg 450 arch/parisc/kernel/ptrace.c ELF_NFPREG * sizeof(reg), -1); reg 453 arch/parisc/kernel/ptrace.c #define RI(reg) (offsetof(struct user_regs_struct,reg) / sizeof(long)) reg 537 arch/parisc/kernel/ptrace.c unsigned long reg; reg 539 arch/parisc/kernel/ptrace.c pos /= sizeof(reg); reg 540 arch/parisc/kernel/ptrace.c count /= sizeof(reg); reg 551 arch/parisc/kernel/ptrace.c pos *= sizeof(reg); reg 552 arch/parisc/kernel/ptrace.c count *= sizeof(reg); reg 554 arch/parisc/kernel/ptrace.c ELF_NGREG * sizeof(reg), -1); reg 565 arch/parisc/kernel/ptrace.c unsigned long reg; reg 567 arch/parisc/kernel/ptrace.c pos /= sizeof(reg); reg 568 arch/parisc/kernel/ptrace.c count /= sizeof(reg); reg 575 arch/parisc/kernel/ptrace.c if (__get_user(reg, u++)) reg 577 arch/parisc/kernel/ptrace.c set_reg(regs, pos++, reg); reg 582 arch/parisc/kernel/ptrace.c pos *= sizeof(reg); reg 583 arch/parisc/kernel/ptrace.c count *= sizeof(reg); reg 585 arch/parisc/kernel/ptrace.c ELF_NGREG * sizeof(reg), -1); reg 617 arch/parisc/kernel/ptrace.c compat_ulong_t reg; reg 619 arch/parisc/kernel/ptrace.c pos /= sizeof(reg); reg 620 arch/parisc/kernel/ptrace.c count /= sizeof(reg); reg 632 arch/parisc/kernel/ptrace.c pos *= sizeof(reg); reg 633 arch/parisc/kernel/ptrace.c count *= sizeof(reg); reg 635 arch/parisc/kernel/ptrace.c ELF_NGREG * sizeof(reg), -1); reg 646 arch/parisc/kernel/ptrace.c compat_ulong_t reg; reg 648 arch/parisc/kernel/ptrace.c pos /= sizeof(reg); reg 649 arch/parisc/kernel/ptrace.c count /= sizeof(reg); reg 656 arch/parisc/kernel/ptrace.c if (__get_user(reg, u++)) reg 658 arch/parisc/kernel/ptrace.c set_reg(regs, pos++, reg); reg 663 arch/parisc/kernel/ptrace.c pos *= sizeof(reg); reg 664 arch/parisc/kernel/ptrace.c count *= sizeof(reg); reg 666 arch/parisc/kernel/ptrace.c ELF_NGREG * sizeof(reg), -1); reg 202 arch/powerpc/boot/cpm-serial.c u32 reg[2]; reg 262 arch/powerpc/boot/cpm-serial.c if (getprop(muram, "reg", reg, 8) < 8) reg 265 arch/powerpc/boot/cpm-serial.c muram_offset = reg[0]; reg 266 arch/powerpc/boot/cpm-serial.c muram_size = reg[1]; reg 23 arch/powerpc/boot/cuboot-52xx.c void *soc, *reg; reg 45 arch/powerpc/boot/cuboot-52xx.c if (!dt_xlate_reg(soc, 0, (void*)®, NULL)) reg 47 arch/powerpc/boot/cuboot-52xx.c div = in_8(reg + 0x204) & 0x0020 ? 8 : 4; reg 45 arch/powerpc/boot/dcr.h #define SDRAM_CONFIG_BANK_SIZE(reg) \ reg 46 arch/powerpc/boot/dcr.h (0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17)) reg 63 arch/powerpc/boot/dcr.h #define EBC_BXCR_BANK_SIZE(reg) \ reg 64 arch/powerpc/boot/dcr.h (0x100000 << (((reg) & EBC_BXCR_BS) >> 17)) reg 98 arch/powerpc/boot/dcr.h #define CPC0_SYS0_FBDV(reg) \ reg 99 arch/powerpc/boot/dcr.h ((((((reg) & CPC0_SYS0_FBDV_MASK) >> 18) - 1) & 0xf) + 1) reg 100 arch/powerpc/boot/dcr.h #define CPC0_SYS0_FWDVA(reg) \ reg 101 arch/powerpc/boot/dcr.h (8 - (((reg) & CPC0_SYS0_FWDVA_MASK) >> 15)) reg 102 arch/powerpc/boot/dcr.h #define CPC0_SYS0_FWDVB(reg) \ reg 103 arch/powerpc/boot/dcr.h (8 - (((reg) & CPC0_SYS0_FWDVB_MASK) >> 12)) reg 104 arch/powerpc/boot/dcr.h #define CPC0_SYS0_OPDV(reg) \ reg 105 arch/powerpc/boot/dcr.h ((((reg) & CPC0_SYS0_OPDV_MASK) >> 10) + 1) reg 106 arch/powerpc/boot/dcr.h #define CPC0_SYS0_EPDV(reg) \ reg 107 arch/powerpc/boot/dcr.h ((((reg) & CPC0_SYS0_EPDV_MASK) >> 8) + 1) reg 137 arch/powerpc/boot/dcr.h #define CPC0_CR0_UDIV(reg) \ reg 138 arch/powerpc/boot/dcr.h ((((reg) & CPC0_CR0_UDIV_MASK) >> 16) + 1) reg 148 arch/powerpc/boot/devtree.c static int sub_reg(u32 *reg, u32 *sub) reg 154 arch/powerpc/boot/devtree.c borrow = reg[i] < sub[i] + prev_borrow; reg 155 arch/powerpc/boot/devtree.c reg[i] -= sub[i] + prev_borrow; reg 161 arch/powerpc/boot/devtree.c static int add_reg(u32 *reg, u32 *add, int naddr) reg 166 arch/powerpc/boot/devtree.c u64 tmp = (u64)reg[i] + add[i] + carry; reg 168 arch/powerpc/boot/devtree.c reg[i] = (u32)tmp; reg 177 arch/powerpc/boot/devtree.c static int compare_reg(u32 *reg, u32 *range, u32 *rangesize) reg 183 arch/powerpc/boot/devtree.c if (reg[i] < range[i]) reg 185 arch/powerpc/boot/devtree.c if (reg[i] > range[i]) reg 192 arch/powerpc/boot/devtree.c if (reg[i] < end) reg 194 arch/powerpc/boot/devtree.c if (reg[i] > end) reg 198 arch/powerpc/boot/devtree.c return reg[i] != end; reg 202 arch/powerpc/boot/devtree.c static int find_range(u32 *reg, u32 *ranges, int nregaddr, reg 215 arch/powerpc/boot/devtree.c if (compare_reg(reg, range_addr, range_size)) reg 37 arch/powerpc/boot/ebony.c u32 reg[3] = {0x0, 0x0, 0x80000}; reg 56 arch/powerpc/boot/ebony.c if (getprop(devp, "reg", reg, sizeof(reg)) != sizeof(reg)) reg 62 arch/powerpc/boot/ebony.c reg[1] ^= 0x80000; reg 64 arch/powerpc/boot/ebony.c setprop(devp, "reg", reg, sizeof(reg)); reg 46 arch/powerpc/boot/ep405.c u32 reg[3] = { 4, 0x200000, 0}; reg 47 arch/powerpc/boot/ep405.c getprop(nvrtc, "reg", reg, 3); reg 48 arch/powerpc/boot/ep405.c reg[2] = (val << 10) & 0xffffffff; reg 49 arch/powerpc/boot/ep405.c setprop(nvrtc, "reg", reg, 3); reg 28 arch/powerpc/boot/simpleboot.c const u32 *na, *ns, *reg, *timebase; reg 52 arch/powerpc/boot/simpleboot.c reg = fdt_getprop(_dtb_start, node, "reg", &size); reg 58 arch/powerpc/boot/simpleboot.c if (*reg++ != 0) reg 64 arch/powerpc/boot/simpleboot.c memsize64 = (memsize64 << 32) | *reg++; reg 52 arch/powerpc/boot/treeboot-akebono.c u32 reg; reg 57 arch/powerpc/boot/treeboot-akebono.c reg = mfdcrx(DDR3_MR0CF + i); reg 59 arch/powerpc/boot/treeboot-akebono.c if (!(reg & 1)) reg 62 arch/powerpc/boot/treeboot-akebono.c reg &= 0x0000f000; reg 63 arch/powerpc/boot/treeboot-akebono.c reg >>= 12; reg 64 arch/powerpc/boot/treeboot-akebono.c memsize += (0x800000ULL << reg); reg 73 arch/powerpc/boot/treeboot-akebono.c u32 reg; reg 81 arch/powerpc/boot/treeboot-akebono.c reg = mfdcrx(CCTL0_MCO2) & ~0x2; reg 82 arch/powerpc/boot/treeboot-akebono.c mtdcrx(CCTL0_MCO2, reg); reg 41 arch/powerpc/boot/treeboot-currituck.c u32 reg; reg 46 arch/powerpc/boot/treeboot-currituck.c reg = mfdcrx(DDR3_MR0CF + i); reg 48 arch/powerpc/boot/treeboot-currituck.c if (!(reg & 1)) reg 51 arch/powerpc/boot/treeboot-currituck.c reg &= 0x0000f000; reg 52 arch/powerpc/boot/treeboot-currituck.c reg >>= 12; reg 53 arch/powerpc/boot/treeboot-currituck.c memsize += (0x800000ULL << reg); reg 38 arch/powerpc/boot/treeboot-iss4xx.c u32 reg[3]; reg 44 arch/powerpc/boot/treeboot-iss4xx.c getprop(memory, "reg", reg, sizeof(reg)); reg 45 arch/powerpc/boot/treeboot-iss4xx.c if (reg[2]) reg 47 arch/powerpc/boot/treeboot-iss4xx.c ibm4xx_memstart = reg[1]; reg 40 arch/powerpc/boot/uartlite.c u32 reg = ULITE_STATUS_TXFULL; reg 41 arch/powerpc/boot/uartlite.c while (reg & ULITE_STATUS_TXFULL) /* spin on TXFULL bit */ reg 42 arch/powerpc/boot/uartlite.c reg = in_be32(reg_base + ULITE_STATUS); reg 48 arch/powerpc/boot/uartlite.c u32 reg = 0; reg 49 arch/powerpc/boot/uartlite.c while (!(reg & ULITE_STATUS_RXVALID)) /* spin waiting for RXVALID bit */ reg 50 arch/powerpc/boot/uartlite.c reg = in_be32(reg_base + ULITE_STATUS); reg 56 arch/powerpc/boot/uartlite.c u32 reg = in_be32(reg_base + ULITE_STATUS); reg 57 arch/powerpc/boot/uartlite.c return reg & ULITE_STATUS_RXVALID; reg 102 arch/powerpc/boot/wii.c u32 reg[4]; reg 112 arch/powerpc/boot/wii.c len = getprop(mem, "reg", reg, sizeof(reg)); reg 113 arch/powerpc/boot/wii.c if (len != sizeof(reg)) { reg 125 arch/powerpc/boot/wii.c if (mem2_boundary > reg[2] && mem2_boundary < reg[2] + reg[3]) { reg 126 arch/powerpc/boot/wii.c reg[3] = mem2_boundary - reg[2]; reg 127 arch/powerpc/boot/wii.c printf("top of MEM2 @ %08X\n", reg[2] + reg[3]); reg 128 arch/powerpc/boot/wii.c setprop(mem, "reg", reg, sizeof(reg)); reg 59 arch/powerpc/include/asm/book3s/64/kup-radix.h #include <asm/reg.h> reg 73 arch/powerpc/include/asm/cell-pmu.h extern u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg); reg 74 arch/powerpc/include/asm/cell-pmu.h extern void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val); reg 33 arch/powerpc/include/asm/dcr-native.h extern void __mtdcr(unsigned int reg, unsigned int val); reg 34 arch/powerpc/include/asm/dcr-native.h extern unsigned int __mfdcr(unsigned int reg); reg 39 arch/powerpc/include/asm/dcr-native.h static inline unsigned int mfdcrx(unsigned int reg) reg 43 arch/powerpc/include/asm/dcr-native.h : "=r" (ret) : "r" (reg)); reg 47 arch/powerpc/include/asm/dcr-native.h static inline void mtdcrx(unsigned int reg, unsigned int val) reg 50 arch/powerpc/include/asm/dcr-native.h : : "r" (val), "r" (reg)); reg 78 arch/powerpc/include/asm/dcr-native.h static inline unsigned __mfdcri(int base_addr, int base_data, int reg) reg 85 arch/powerpc/include/asm/dcr-native.h mtdcrx(base_addr, reg); reg 88 arch/powerpc/include/asm/dcr-native.h __mtdcr(base_addr, reg); reg 95 arch/powerpc/include/asm/dcr-native.h static inline void __mtdcri(int base_addr, int base_data, int reg, reg 102 arch/powerpc/include/asm/dcr-native.h mtdcrx(base_addr, reg); reg 105 arch/powerpc/include/asm/dcr-native.h __mtdcr(base_addr, reg); reg 111 arch/powerpc/include/asm/dcr-native.h static inline void __dcri_clrset(int base_addr, int base_data, int reg, reg 119 arch/powerpc/include/asm/dcr-native.h mtdcrx(base_addr, reg); reg 123 arch/powerpc/include/asm/dcr-native.h __mtdcr(base_addr, reg); reg 130 arch/powerpc/include/asm/dcr-native.h #define mfdcri(base, reg) __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \ reg 132 arch/powerpc/include/asm/dcr-native.h reg) reg 134 arch/powerpc/include/asm/dcr-native.h #define mtdcri(base, reg, data) __mtdcri(DCRN_ ## base ## _CONFIG_ADDR, \ reg 136 arch/powerpc/include/asm/dcr-native.h reg, data) reg 138 arch/powerpc/include/asm/dcr-native.h #define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \ reg 140 arch/powerpc/include/asm/dcr-native.h reg, clr, set) reg 395 arch/powerpc/include/asm/kvm_ppc.h #define get_reg_val(id, reg) ({ \ reg 398 arch/powerpc/include/asm/kvm_ppc.h case 4: __u.wval = (reg); break; \ reg 399 arch/powerpc/include/asm/kvm_ppc.h case 8: __u.dval = (reg); break; \ reg 422 arch/powerpc/include/asm/kvm_ppc.h int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg); reg 423 arch/powerpc/include/asm/kvm_ppc.h int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg); reg 914 arch/powerpc/include/asm/kvm_ppc.h #define SPRNG_WRAPPER_GET(reg, bookehv_spr) \ reg 915 arch/powerpc/include/asm/kvm_ppc.h static inline ulong kvmppc_get_##reg(struct kvm_vcpu *vcpu) \ reg 920 arch/powerpc/include/asm/kvm_ppc.h #define SPRNG_WRAPPER_SET(reg, bookehv_spr) \ reg 921 arch/powerpc/include/asm/kvm_ppc.h static inline void kvmppc_set_##reg(struct kvm_vcpu *vcpu, ulong val) \ reg 926 arch/powerpc/include/asm/kvm_ppc.h #define SHARED_WRAPPER_GET(reg, size) \ reg 927 arch/powerpc/include/asm/kvm_ppc.h static inline u##size kvmppc_get_##reg(struct kvm_vcpu *vcpu) \ reg 930 arch/powerpc/include/asm/kvm_ppc.h return be##size##_to_cpu(vcpu->arch.shared->reg); \ reg 932 arch/powerpc/include/asm/kvm_ppc.h return le##size##_to_cpu(vcpu->arch.shared->reg); \ reg 935 arch/powerpc/include/asm/kvm_ppc.h #define SHARED_WRAPPER_SET(reg, size) \ reg 936 arch/powerpc/include/asm/kvm_ppc.h static inline void kvmppc_set_##reg(struct kvm_vcpu *vcpu, u##size val) \ reg 939 arch/powerpc/include/asm/kvm_ppc.h vcpu->arch.shared->reg = cpu_to_be##size(val); \ reg 941 arch/powerpc/include/asm/kvm_ppc.h vcpu->arch.shared->reg = cpu_to_le##size(val); \ reg 944 arch/powerpc/include/asm/kvm_ppc.h #define SHARED_WRAPPER(reg, size) \ reg 945 arch/powerpc/include/asm/kvm_ppc.h SHARED_WRAPPER_GET(reg, size) \ reg 946 arch/powerpc/include/asm/kvm_ppc.h SHARED_WRAPPER_SET(reg, size) \ reg 948 arch/powerpc/include/asm/kvm_ppc.h #define SPRNG_WRAPPER(reg, bookehv_spr) \ reg 949 arch/powerpc/include/asm/kvm_ppc.h SPRNG_WRAPPER_GET(reg, bookehv_spr) \ reg 950 arch/powerpc/include/asm/kvm_ppc.h SPRNG_WRAPPER_SET(reg, bookehv_spr) \ reg 954 arch/powerpc/include/asm/kvm_ppc.h #define SHARED_SPRNG_WRAPPER(reg, size, bookehv_spr) \ reg 955 arch/powerpc/include/asm/kvm_ppc.h SPRNG_WRAPPER(reg, bookehv_spr) \ reg 959 arch/powerpc/include/asm/kvm_ppc.h #define SHARED_SPRNG_WRAPPER(reg, size, bookehv_spr) \ reg 960 arch/powerpc/include/asm/kvm_ppc.h SHARED_WRAPPER(reg, size) \ reg 34 arch/powerpc/include/asm/nohash/32/kup-8xx.h #include <asm/reg.h> reg 484 arch/powerpc/include/asm/pasemi_dma.h extern unsigned int pasemi_read_iob_reg(unsigned int reg); reg 485 arch/powerpc/include/asm/pasemi_dma.h extern void pasemi_write_iob_reg(unsigned int reg, unsigned int val); reg 487 arch/powerpc/include/asm/pasemi_dma.h extern unsigned int pasemi_read_mac_reg(int intf, unsigned int reg); reg 488 arch/powerpc/include/asm/pasemi_dma.h extern void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val); reg 490 arch/powerpc/include/asm/pasemi_dma.h extern unsigned int pasemi_read_dma_reg(unsigned int reg); reg 491 arch/powerpc/include/asm/pasemi_dma.h extern void pasemi_write_dma_reg(unsigned int reg, unsigned int val); reg 308 arch/powerpc/include/asm/ppc_asm.h #define LOAD_REG_ADDR_PIC(reg, name) \ reg 310 arch/powerpc/include/asm/ppc_asm.h 0: mflr reg; \ reg 311 arch/powerpc/include/asm/ppc_asm.h addis reg,reg,(name - 0b)@ha; \ reg 312 arch/powerpc/include/asm/ppc_asm.h addi reg,reg,(name - 0b)@l; reg 348 arch/powerpc/include/asm/ppc_asm.h #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr reg 350 arch/powerpc/include/asm/ppc_asm.h #define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \ reg 352 arch/powerpc/include/asm/ppc_asm.h lis reg, (expr)@__AS_ATHIGH; \ reg 354 arch/powerpc/include/asm/ppc_asm.h ori reg, reg, (expr)@l; \ reg 355 arch/powerpc/include/asm/ppc_asm.h rldimi reg, tmp, 32, 0 reg 357 arch/powerpc/include/asm/ppc_asm.h #define LOAD_REG_ADDR(reg,name) \ reg 358 arch/powerpc/include/asm/ppc_asm.h ld reg,name@got(r2) reg 360 arch/powerpc/include/asm/ppc_asm.h #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) reg 368 arch/powerpc/include/asm/ppc_asm.h #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr reg 370 arch/powerpc/include/asm/ppc_asm.h #define LOAD_REG_IMMEDIATE_SYM(reg,expr) \ reg 371 arch/powerpc/include/asm/ppc_asm.h lis reg,(expr)@ha; \ reg 372 arch/powerpc/include/asm/ppc_asm.h addi reg,reg,(expr)@l; reg 374 arch/powerpc/include/asm/ppc_asm.h #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE_SYM(reg, name) reg 376 arch/powerpc/include/asm/ppc_asm.h #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha reg 511 arch/powerpc/include/asm/ppc_asm.h #define MTMSR_EERI(reg) mtmsrd reg,1 reg 519 arch/powerpc/include/asm/ppc_asm.h #define MTMSR_EERI(reg) mtmsr reg reg 828 arch/powerpc/include/asm/ppc_asm.h #define BTB_FLUSH(reg) \ reg 829 arch/powerpc/include/asm/ppc_asm.h lis reg,BUCSR_INIT@h; \ reg 830 arch/powerpc/include/asm/ppc_asm.h ori reg,reg,BUCSR_INIT@l; \ reg 831 arch/powerpc/include/asm/ppc_asm.h mtspr SPRN_BUCSR,reg; \ reg 834 arch/powerpc/include/asm/ppc_asm.h #define BTB_FLUSH(reg) reg 501 arch/powerpc/include/asm/ps3.h u32 ps3_read_pm(u32 cpu, enum pm_reg_name reg); reg 502 arch/powerpc/include/asm/ps3.h void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val); reg 456 arch/powerpc/include/asm/rtas.h static inline u32 rtas_config_addr(int busno, int devfn, int reg) reg 458 arch/powerpc/include/asm/rtas.h return ((reg & 0xf00) << 20) | ((busno & 0xff) << 16) | reg 459 arch/powerpc/include/asm/rtas.h (devfn << 8) | (reg & 0xff); reg 102 arch/powerpc/include/asm/sstep.h int reg; reg 141 arch/powerpc/include/asm/sstep.h void emulate_update_regs(struct pt_regs *reg, struct instruction_op *op); reg 163 arch/powerpc/include/asm/sstep.h extern void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg, reg 166 arch/powerpc/include/asm/sstep.h const union vsx_reg *reg, void *mem, reg 106 arch/powerpc/kernel/align.c static int emulate_spe(struct pt_regs *regs, unsigned int reg, reg 117 arch/powerpc/kernel/align.c unsigned long *evr = ¤t->thread.evr[reg]; reg 149 arch/powerpc/kernel/align.c data.w[1] = regs->gpr[reg]; reg 153 arch/powerpc/kernel/align.c data.h[3] = regs->gpr[reg] >> 16; reg 157 arch/powerpc/kernel/align.c data.h[3] = regs->gpr[reg] & 0xffff; reg 163 arch/powerpc/kernel/align.c data.w[1] = regs->gpr[reg]; reg 277 arch/powerpc/kernel/align.c regs->gpr[reg] = data.w[1]; reg 317 arch/powerpc/kernel/align.c int reg = (instr >> 21) & 0x1f; reg 319 arch/powerpc/kernel/align.c return emulate_spe(regs, reg, instr); reg 167 arch/powerpc/kernel/fadump.c struct memblock_region *reg; reg 171 arch/powerpc/kernel/fadump.c for_each_memblock(memory, reg) { reg 172 arch/powerpc/kernel/fadump.c start = max_t(u64, d_start, reg->base); reg 173 arch/powerpc/kernel/fadump.c end = min_t(u64, d_end, (reg->base + reg->size)); reg 400 arch/powerpc/kernel/fadump.c struct memblock_region *reg; reg 408 arch/powerpc/kernel/fadump.c for_each_memblock(memory, reg) { reg 409 arch/powerpc/kernel/fadump.c base = reg->base; reg 410 arch/powerpc/kernel/fadump.c size = reg->size; reg 878 arch/powerpc/kernel/fadump.c struct memblock_region *reg; reg 898 arch/powerpc/kernel/fadump.c for_each_memblock(memory, reg) { reg 899 arch/powerpc/kernel/fadump.c start = (u64)reg->base; reg 900 arch/powerpc/kernel/fadump.c end = start + (u64)reg->size; reg 1136 arch/powerpc/kernel/fadump.c struct memblock_region *reg; reg 1140 arch/powerpc/kernel/fadump.c for_each_memblock(memory, reg) { reg 1141 arch/powerpc/kernel/fadump.c tstart = max_t(u64, spfn, memblock_region_memory_base_pfn(reg)); reg 1142 arch/powerpc/kernel/fadump.c tend = min_t(u64, epfn, memblock_region_memory_end_pfn(reg)); reg 1537 arch/powerpc/kernel/fadump.c struct memblock_region *reg; reg 1540 arch/powerpc/kernel/fadump.c for_each_memblock(memory, reg) { reg 1541 arch/powerpc/kernel/fadump.c mstart = reg->base; reg 1542 arch/powerpc/kernel/fadump.c msize = reg->size; reg 21 arch/powerpc/kernel/head_booke.h #define ALLOC_STACK_FRAME(reg, val) \ reg 22 arch/powerpc/kernel/head_booke.h addi reg,reg,val reg 24 arch/powerpc/kernel/head_booke.h #define ALLOC_STACK_FRAME(reg, val) \ reg 25 arch/powerpc/kernel/head_booke.h addis reg,reg,val@ha; \ reg 26 arch/powerpc/kernel/head_booke.h addi reg,reg,val@l reg 38 arch/powerpc/kernel/head_booke.h #define BOOKE_CLEAR_BTB(reg) \ reg 40 arch/powerpc/kernel/head_booke.h BTB_FLUSH(reg) \ reg 43 arch/powerpc/kernel/head_booke.h #define BOOKE_CLEAR_BTB(reg) reg 198 arch/powerpc/kernel/kgdb.c int reg; reg 203 arch/powerpc/kernel/kgdb.c for (reg = 0; reg < 3; reg++) reg 204 arch/powerpc/kernel/kgdb.c PACK64(ptr, regs->gpr[reg]); reg 210 arch/powerpc/kernel/kgdb.c for (reg = 14; reg < 32; reg++) reg 211 arch/powerpc/kernel/kgdb.c PACK64(ptr, regs->gpr[reg]); reg 215 arch/powerpc/kernel/kgdb.c for (reg = 0; reg < 32; reg++) reg 216 arch/powerpc/kernel/kgdb.c PACK64(ptr, p->thread.evr[reg]); reg 206 arch/powerpc/kernel/legacy_serial.c const __be32 *reg; reg 214 arch/powerpc/kernel/legacy_serial.c reg = of_get_property(np, "reg", NULL); reg 215 arch/powerpc/kernel/legacy_serial.c if (reg == NULL) reg 219 arch/powerpc/kernel/legacy_serial.c if (!(be32_to_cpu(reg[0]) & 0x00000001)) reg 239 arch/powerpc/kernel/legacy_serial.c taddr = of_translate_address(np, reg); reg 246 arch/powerpc/kernel/legacy_serial.c return add_legacy_port(np, index, UPIO_PORT, be32_to_cpu(reg[1]), reg 295 arch/powerpc/kernel/legacy_serial.c const __be32 *reg = of_get_property(np, "reg", NULL); reg 296 arch/powerpc/kernel/legacy_serial.c if (reg && (be32_to_cpup(reg) < 4)) reg 297 arch/powerpc/kernel/legacy_serial.c index = lindex = be32_to_cpup(reg); reg 809 arch/powerpc/kernel/pci-common.c struct pci_bus_region reg; reg 818 arch/powerpc/kernel/pci-common.c pcibios_resource_to_bus(dev->bus, ®, res); reg 820 arch/powerpc/kernel/pci-common.c (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { reg 1285 arch/powerpc/kernel/pci-common.c u32 reg; reg 1286 arch/powerpc/kernel/pci-common.c pci_read_config_dword(dev, dev->rom_base_reg, ®); reg 1287 arch/powerpc/kernel/pci-common.c if (reg & PCI_ROM_ADDRESS_ENABLE) { reg 1292 arch/powerpc/kernel/pci-common.c reg & ~PCI_ROM_ADDRESS_ENABLE); reg 92 arch/powerpc/kernel/pci_32.c const unsigned int *class_code, *reg; reg 98 arch/powerpc/kernel/pci_32.c reg = of_get_property(node, "reg", NULL); reg 99 arch/powerpc/kernel/pci_32.c if (!reg) reg 102 arch/powerpc/kernel/pci_32.c ((reg[0] >> 8) & 0xff)); reg 164 arch/powerpc/kernel/pci_32.c const __be32 *reg; reg 171 arch/powerpc/kernel/pci_32.c reg = of_get_property(node, "reg", &size); reg 172 arch/powerpc/kernel/pci_32.c if (!reg || size < 5 * sizeof(u32)) reg 175 arch/powerpc/kernel/pci_32.c *bus = (be32_to_cpup(®[0]) >> 16) & 0xff; reg 176 arch/powerpc/kernel/pci_32.c *devfn = (be32_to_cpup(®[0]) >> 8) & 0xff; reg 352 arch/powerpc/kernel/pci_of_scan.c const __be32 *reg; reg 362 arch/powerpc/kernel/pci_of_scan.c reg = of_get_property(dn, "reg", ®len); reg 363 arch/powerpc/kernel/pci_of_scan.c if (reg == NULL || reglen < 20) reg 365 arch/powerpc/kernel/pci_of_scan.c devfn = (of_read_number(reg, 1) >> 8) & 0xff; reg 2107 arch/powerpc/kernel/prom_init.c __be32 reg; reg 2119 arch/powerpc/kernel/prom_init.c reg = cpu_to_be32(-1); /* make sparse happy */ reg 2120 arch/powerpc/kernel/prom_init.c prom_getprop(node, "reg", ®, sizeof(reg)); reg 2121 arch/powerpc/kernel/prom_init.c cpu_no = be32_to_cpu(reg); reg 382 arch/powerpc/kernel/ptrace.c unsigned long reg; reg 392 arch/powerpc/kernel/ptrace.c 0, PT_MSR * sizeof(reg)); reg 395 arch/powerpc/kernel/ptrace.c ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, reg 396 arch/powerpc/kernel/ptrace.c PT_MSR * sizeof(reg), reg 397 arch/powerpc/kernel/ptrace.c (PT_MSR + 1) * sizeof(reg)); reg 399 arch/powerpc/kernel/ptrace.c ret = set_user_msr(target, reg); reg 408 arch/powerpc/kernel/ptrace.c PT_ORIG_R3 * sizeof(reg), reg 409 arch/powerpc/kernel/ptrace.c (PT_MAX_PUT_REG + 1) * sizeof(reg)); reg 414 arch/powerpc/kernel/ptrace.c (PT_MAX_PUT_REG + 1) * sizeof(reg), reg 415 arch/powerpc/kernel/ptrace.c PT_TRAP * sizeof(reg)); reg 418 arch/powerpc/kernel/ptrace.c ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, reg 419 arch/powerpc/kernel/ptrace.c PT_TRAP * sizeof(reg), reg 420 arch/powerpc/kernel/ptrace.c (PT_TRAP + 1) * sizeof(reg)); reg 422 arch/powerpc/kernel/ptrace.c ret = set_user_trap(target, reg); reg 428 arch/powerpc/kernel/ptrace.c (PT_TRAP + 1) * sizeof(reg), -1); reg 573 arch/powerpc/kernel/ptrace.c elf_vrreg_t reg; reg 623 arch/powerpc/kernel/ptrace.c elf_vrreg_t reg; reg 902 arch/powerpc/kernel/ptrace.c unsigned long reg; reg 917 arch/powerpc/kernel/ptrace.c 0, PT_MSR * sizeof(reg)); reg 920 arch/powerpc/kernel/ptrace.c ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, reg 921 arch/powerpc/kernel/ptrace.c PT_MSR * sizeof(reg), reg 922 arch/powerpc/kernel/ptrace.c (PT_MSR + 1) * sizeof(reg)); reg 924 arch/powerpc/kernel/ptrace.c ret = set_user_ckpt_msr(target, reg); reg 933 arch/powerpc/kernel/ptrace.c PT_ORIG_R3 * sizeof(reg), reg 934 arch/powerpc/kernel/ptrace.c (PT_MAX_PUT_REG + 1) * sizeof(reg)); reg 939 arch/powerpc/kernel/ptrace.c (PT_MAX_PUT_REG + 1) * sizeof(reg), reg 940 arch/powerpc/kernel/ptrace.c PT_TRAP * sizeof(reg)); reg 943 arch/powerpc/kernel/ptrace.c ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, reg 944 arch/powerpc/kernel/ptrace.c PT_TRAP * sizeof(reg), reg 945 arch/powerpc/kernel/ptrace.c (PT_TRAP + 1) * sizeof(reg)); reg 947 arch/powerpc/kernel/ptrace.c ret = set_user_ckpt_trap(target, reg); reg 953 arch/powerpc/kernel/ptrace.c (PT_TRAP + 1) * sizeof(reg), -1); reg 1147 arch/powerpc/kernel/ptrace.c elf_vrreg_t reg; reg 1208 arch/powerpc/kernel/ptrace.c elf_vrreg_t reg; reg 2027 arch/powerpc/kernel/ptrace.c compat_ulong_t reg; reg 2029 arch/powerpc/kernel/ptrace.c pos /= sizeof(reg); reg 2030 arch/powerpc/kernel/ptrace.c count /= sizeof(reg); reg 2041 arch/powerpc/kernel/ptrace.c reg = get_user_msr(target); reg 2043 arch/powerpc/kernel/ptrace.c *k++ = reg; reg 2044 arch/powerpc/kernel/ptrace.c else if (__put_user(reg, u++)) reg 2060 arch/powerpc/kernel/ptrace.c pos *= sizeof(reg); reg 2061 arch/powerpc/kernel/ptrace.c count *= sizeof(reg); reg 2063 arch/powerpc/kernel/ptrace.c PT_REGS_COUNT * sizeof(reg), -1); reg 2074 arch/powerpc/kernel/ptrace.c compat_ulong_t reg; reg 2076 arch/powerpc/kernel/ptrace.c pos /= sizeof(reg); reg 2077 arch/powerpc/kernel/ptrace.c count /= sizeof(reg); reg 2084 arch/powerpc/kernel/ptrace.c if (__get_user(reg, u++)) reg 2086 arch/powerpc/kernel/ptrace.c regs[pos++] = reg; reg 2092 arch/powerpc/kernel/ptrace.c reg = *k++; reg 2093 arch/powerpc/kernel/ptrace.c else if (__get_user(reg, u++)) reg 2095 arch/powerpc/kernel/ptrace.c set_user_msr(target, reg); reg 2107 arch/powerpc/kernel/ptrace.c if (__get_user(reg, u++)) reg 2109 arch/powerpc/kernel/ptrace.c regs[pos++] = reg; reg 2112 arch/powerpc/kernel/ptrace.c if (__get_user(reg, u++)) reg 2118 arch/powerpc/kernel/ptrace.c reg = *k++; reg 2119 arch/powerpc/kernel/ptrace.c else if (__get_user(reg, u++)) reg 2121 arch/powerpc/kernel/ptrace.c set_user_trap(target, reg); reg 2128 arch/powerpc/kernel/ptrace.c pos *= sizeof(reg); reg 2129 arch/powerpc/kernel/ptrace.c count *= sizeof(reg); reg 2131 arch/powerpc/kernel/ptrace.c (PT_TRAP + 1) * sizeof(reg), -1); reg 1075 arch/powerpc/kernel/smp.c const __be32 *reg; reg 1082 arch/powerpc/kernel/smp.c reg = of_get_property(np, "reg", NULL); reg 1083 arch/powerpc/kernel/smp.c if (!reg) reg 1086 arch/powerpc/kernel/smp.c id = be32_to_cpup(reg); reg 42 arch/powerpc/kernel/udbg_16550.c static u8 (*udbg_uart_in)(unsigned int reg); reg 43 arch/powerpc/kernel/udbg_16550.c static void (*udbg_uart_out)(unsigned int reg, u8 data); reg 165 arch/powerpc/kernel/udbg_16550.c static u8 udbg_uart_in_pio(unsigned int reg) reg 167 arch/powerpc/kernel/udbg_16550.c return inb(udbg_uart.pio_base + (reg * udbg_uart_stride)); reg 170 arch/powerpc/kernel/udbg_16550.c static void udbg_uart_out_pio(unsigned int reg, u8 data) reg 172 arch/powerpc/kernel/udbg_16550.c outb(data, udbg_uart.pio_base + (reg * udbg_uart_stride)); reg 186 arch/powerpc/kernel/udbg_16550.c static u8 udbg_uart_in_mmio(unsigned int reg) reg 188 arch/powerpc/kernel/udbg_16550.c return in_8(udbg_uart.mmio_base + (reg * udbg_uart_stride)); reg 191 arch/powerpc/kernel/udbg_16550.c static void udbg_uart_out_mmio(unsigned int reg, u8 data) reg 193 arch/powerpc/kernel/udbg_16550.c out_8(udbg_uart.mmio_base + (reg * udbg_uart_stride), data); reg 212 arch/powerpc/kernel/udbg_16550.c static u8 udbg_uart_in_maple(unsigned int reg) reg 214 arch/powerpc/kernel/udbg_16550.c return real_readb(UDBG_UART_MAPLE_ADDR + reg); reg 217 arch/powerpc/kernel/udbg_16550.c static void udbg_uart_out_maple(unsigned int reg, u8 val) reg 219 arch/powerpc/kernel/udbg_16550.c real_writeb(val, UDBG_UART_MAPLE_ADDR + reg); reg 235 arch/powerpc/kernel/udbg_16550.c static u8 udbg_uart_in_pas(unsigned int reg) reg 237 arch/powerpc/kernel/udbg_16550.c return real_205_readb(UDBG_UART_PAS_ADDR + reg); reg 240 arch/powerpc/kernel/udbg_16550.c static void udbg_uart_out_pas(unsigned int reg, u8 val) reg 242 arch/powerpc/kernel/udbg_16550.c real_205_writeb(val, UDBG_UART_PAS_ADDR + reg); reg 258 arch/powerpc/kernel/udbg_16550.c static u8 udbg_uart_in_44x_as1(unsigned int reg) reg 260 arch/powerpc/kernel/udbg_16550.c return as1_readb((void __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR + reg); reg 263 arch/powerpc/kernel/udbg_16550.c static void udbg_uart_out_44x_as1(unsigned int reg, u8 val) reg 265 arch/powerpc/kernel/udbg_16550.c as1_writeb(val, (void __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR + reg); reg 279 arch/powerpc/kernel/udbg_16550.c static u8 udbg_uart_in_40x(unsigned int reg) reg 282 arch/powerpc/kernel/udbg_16550.c + reg); reg 285 arch/powerpc/kernel/udbg_16550.c static void udbg_uart_out_40x(unsigned int reg, u8 val) reg 288 arch/powerpc/kernel/udbg_16550.c + reg); reg 98 arch/powerpc/kvm/book3s_hv_builtin.c struct memblock_region *reg; reg 110 arch/powerpc/kvm/book3s_hv_builtin.c for_each_memblock(memory, reg) reg 111 arch/powerpc/kvm/book3s_hv_builtin.c selected_size += memblock_region_memory_end_pfn(reg) - reg 112 arch/powerpc/kvm/book3s_hv_builtin.c memblock_region_memory_base_pfn(reg); reg 681 arch/powerpc/kvm/e500_mmu.c u32 reg = set_reg_val(id, *val); reg 682 arch/powerpc/kvm/e500_mmu.c if (reg != vcpu->arch.mmucfg) reg 687 arch/powerpc/kvm/e500_mmu.c u32 reg = set_reg_val(id, *val); reg 688 arch/powerpc/kvm/e500_mmu.c if (reg != vcpu->arch.eptcfg) reg 697 arch/powerpc/kvm/e500_mmu.c u32 reg = set_reg_val(id, *val); reg 699 arch/powerpc/kvm/e500_mmu.c if (reg != vcpu->arch.tlbcfg[i]) reg 707 arch/powerpc/kvm/e500_mmu.c u32 reg = set_reg_val(id, *val); reg 709 arch/powerpc/kvm/e500_mmu.c if (reg != vcpu->arch.tlbps[i]) reg 108 arch/powerpc/kvm/emulate_loadstore.c op.reg, size, !instr_byte_swap); reg 111 arch/powerpc/kvm/emulate_loadstore.c op.reg, size, !instr_byte_swap); reg 128 arch/powerpc/kvm/emulate_loadstore.c KVM_MMIO_REG_FPR|op.reg, size, 1); reg 131 arch/powerpc/kvm/emulate_loadstore.c KVM_MMIO_REG_FPR|op.reg, size, 1); reg 168 arch/powerpc/kvm/emulate_loadstore.c vcpu, KVM_MMIO_REG_VMX|op.reg, reg 173 arch/powerpc/kvm/emulate_loadstore.c KVM_MMIO_REG_VMX|op.reg, reg 221 arch/powerpc/kvm/emulate_loadstore.c KVM_MMIO_REG_VSX|op.reg, io_size_each, reg 254 arch/powerpc/kvm/emulate_loadstore.c VCPU_FPR(vcpu, op.reg), size, 1); reg 294 arch/powerpc/kvm/emulate_loadstore.c vcpu, op.reg, 8, 1); reg 298 arch/powerpc/kvm/emulate_loadstore.c vcpu, op.reg, size, 1); reg 342 arch/powerpc/kvm/emulate_loadstore.c op.reg, io_size_each, 1); reg 1375 arch/powerpc/kvm/powerpc.c union kvmppc_one_reg reg; reg 1393 arch/powerpc/kvm/powerpc.c reg.vval = VCPU_VSX_VR(vcpu, rs - 32); reg 1394 arch/powerpc/kvm/powerpc.c *val = reg.vsxval[vsx_offset]; reg 1410 arch/powerpc/kvm/powerpc.c reg.vsxval[0] = VCPU_VSX_FPR(vcpu, rs, dword_offset); reg 1411 arch/powerpc/kvm/powerpc.c *val = reg.vsx32val[word_offset]; reg 1413 arch/powerpc/kvm/powerpc.c reg.vval = VCPU_VSX_VR(vcpu, rs - 32); reg 1414 arch/powerpc/kvm/powerpc.c *val = reg.vsx32val[vsx_offset]; reg 1518 arch/powerpc/kvm/powerpc.c union kvmppc_one_reg reg; reg 1528 arch/powerpc/kvm/powerpc.c reg.vval = VCPU_VSX_VR(vcpu, index); reg 1529 arch/powerpc/kvm/powerpc.c *val = reg.vsxval[vmx_offset]; reg 1536 arch/powerpc/kvm/powerpc.c union kvmppc_one_reg reg; reg 1546 arch/powerpc/kvm/powerpc.c reg.vval = VCPU_VSX_VR(vcpu, index); reg 1547 arch/powerpc/kvm/powerpc.c *val = reg.vsx32val[vmx_offset]; reg 1554 arch/powerpc/kvm/powerpc.c union kvmppc_one_reg reg; reg 1564 arch/powerpc/kvm/powerpc.c reg.vval = VCPU_VSX_VR(vcpu, index); reg 1565 arch/powerpc/kvm/powerpc.c *val = reg.vsx16val[vmx_offset]; reg 1572 arch/powerpc/kvm/powerpc.c union kvmppc_one_reg reg; reg 1582 arch/powerpc/kvm/powerpc.c reg.vval = VCPU_VSX_VR(vcpu, index); reg 1583 arch/powerpc/kvm/powerpc.c *val = reg.vsx8val[vmx_offset]; reg 1671 arch/powerpc/kvm/powerpc.c int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg) reg 1677 arch/powerpc/kvm/powerpc.c size = one_reg_size(reg->id); reg 1681 arch/powerpc/kvm/powerpc.c r = kvmppc_get_one_reg(vcpu, reg->id, &val); reg 1684 arch/powerpc/kvm/powerpc.c switch (reg->id) { reg 1691 arch/powerpc/kvm/powerpc.c val.vval = vcpu->arch.vr.vr[reg->id - KVM_REG_PPC_VR0]; reg 1698 arch/powerpc/kvm/powerpc.c val = get_reg_val(reg->id, vcpu->arch.vr.vscr.u[3]); reg 1701 arch/powerpc/kvm/powerpc.c val = get_reg_val(reg->id, vcpu->arch.vrsave); reg 1713 arch/powerpc/kvm/powerpc.c if (copy_to_user((char __user *)(unsigned long)reg->addr, &val, size)) reg 1719 arch/powerpc/kvm/powerpc.c int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg) reg 1725 arch/powerpc/kvm/powerpc.c size = one_reg_size(reg->id); reg 1729 arch/powerpc/kvm/powerpc.c if (copy_from_user(&val, (char __user *)(unsigned long)reg->addr, size)) reg 1732 arch/powerpc/kvm/powerpc.c r = kvmppc_set_one_reg(vcpu, reg->id, &val); reg 1735 arch/powerpc/kvm/powerpc.c switch (reg->id) { reg 1742 arch/powerpc/kvm/powerpc.c vcpu->arch.vr.vr[reg->id - KVM_REG_PPC_VR0] = val.vval; reg 1749 arch/powerpc/kvm/powerpc.c vcpu->arch.vr.vscr.u[3] = set_reg_val(reg->id, val); reg 1756 arch/powerpc/kvm/powerpc.c vcpu->arch.vrsave = set_reg_val(reg->id, val); reg 2049 arch/powerpc/kvm/powerpc.c struct kvm_one_reg reg; reg 2051 arch/powerpc/kvm/powerpc.c if (copy_from_user(®, argp, sizeof(reg))) reg 2054 arch/powerpc/kvm/powerpc.c r = kvm_vcpu_ioctl_set_one_reg(vcpu, ®); reg 2056 arch/powerpc/kvm/powerpc.c r = kvm_vcpu_ioctl_get_one_reg(vcpu, ®); reg 474 arch/powerpc/lib/sstep.c rn = op->reg; reg 524 arch/powerpc/lib/sstep.c rn = op->reg; reg 612 arch/powerpc/lib/sstep.c int reg, bool cross_endian) reg 620 arch/powerpc/lib/sstep.c err = do_lq(ea, ®s->gpr[reg]); reg 622 arch/powerpc/lib/sstep.c err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs); reg 624 arch/powerpc/lib/sstep.c err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs); reg 627 arch/powerpc/lib/sstep.c do_byte_reverse(®s->gpr[reg], 16); reg 632 arch/powerpc/lib/sstep.c int reg, bool cross_endian) reg 639 arch/powerpc/lib/sstep.c vals[0] = regs->gpr[reg]; reg 640 arch/powerpc/lib/sstep.c vals[1] = regs->gpr[reg + 1]; reg 656 arch/powerpc/lib/sstep.c void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg, reg 666 arch/powerpc/lib/sstep.c reg->d[0] = reg->d[1] = 0; reg 673 arch/powerpc/lib/sstep.c memcpy(reg, mem, size); reg 677 arch/powerpc/lib/sstep.c do_byte_reverse(reg, 16); reg 683 arch/powerpc/lib/sstep.c memcpy(®->b[i], mem, read_size); reg 685 arch/powerpc/lib/sstep.c do_byte_reverse(®->b[i], 8); reg 689 arch/powerpc/lib/sstep.c reg->d[IS_LE] = (signed int) reg->d[IS_LE]; reg 692 arch/powerpc/lib/sstep.c conv_sp_to_dp(®->fp[1 + IS_LE], reg 693 arch/powerpc/lib/sstep.c ®->dp[IS_LE]); reg 699 arch/powerpc/lib/sstep.c reg->d[IS_BE] = !rev ? v : byterev_8(v); reg 701 arch/powerpc/lib/sstep.c reg->d[IS_BE] = reg->d[IS_LE]; reg 709 arch/powerpc/lib/sstep.c reg->w[i] = !rev ? *wp++ : byterev_4(*wp++); reg 712 arch/powerpc/lib/sstep.c u32 val = reg->w[IS_LE ? 3 : 0]; reg 715 arch/powerpc/lib/sstep.c reg->w[i] = val; reg 724 arch/powerpc/lib/sstep.c reg->h[i] = !rev ? *hp++ : byterev_2(*hp++); reg 732 arch/powerpc/lib/sstep.c reg->b[i] = *bp++; reg 740 arch/powerpc/lib/sstep.c void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg, reg 761 arch/powerpc/lib/sstep.c buf.d[0] = byterev_8(reg->d[1]); reg 762 arch/powerpc/lib/sstep.c buf.d[1] = byterev_8(reg->d[0]); reg 763 arch/powerpc/lib/sstep.c reg = &buf; reg 765 arch/powerpc/lib/sstep.c memcpy(mem, reg, size); reg 774 arch/powerpc/lib/sstep.c conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]); reg 776 arch/powerpc/lib/sstep.c reg = &buf; reg 778 arch/powerpc/lib/sstep.c memcpy(mem, ®->b[i], write_size); reg 780 arch/powerpc/lib/sstep.c memcpy(mem + 8, ®->d[IS_BE], 8); reg 792 arch/powerpc/lib/sstep.c *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]); reg 800 arch/powerpc/lib/sstep.c *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]); reg 808 arch/powerpc/lib/sstep.c *bp++ = reg->b[i]; reg 820 arch/powerpc/lib/sstep.c int reg = op->reg; reg 830 arch/powerpc/lib/sstep.c if (reg < 32) { reg 833 arch/powerpc/lib/sstep.c load_vsrn(reg, &buf); reg 835 arch/powerpc/lib/sstep.c current->thread.fp_state.fpr[reg][0] = buf.d[0]; reg 836 arch/powerpc/lib/sstep.c current->thread.fp_state.fpr[reg][1] = buf.d[1]; reg 840 arch/powerpc/lib/sstep.c load_vsrn(reg, &buf); reg 842 arch/powerpc/lib/sstep.c current->thread.vr_state.vr[reg - 32] = buf.v; reg 852 arch/powerpc/lib/sstep.c int reg = op->reg; reg 861 arch/powerpc/lib/sstep.c if (reg < 32) { reg 864 arch/powerpc/lib/sstep.c store_vsrn(reg, &buf); reg 866 arch/powerpc/lib/sstep.c buf.d[0] = current->thread.fp_state.fpr[reg][0]; reg 867 arch/powerpc/lib/sstep.c buf.d[1] = current->thread.fp_state.fpr[reg][1]; reg 871 arch/powerpc/lib/sstep.c store_vsrn(reg, &buf); reg 873 arch/powerpc/lib/sstep.c buf.v = current->thread.vr_state.vr[reg - 32]; reg 983 arch/powerpc/lib/sstep.c op->reg = rd; reg 1522 arch/powerpc/lib/sstep.c op->reg = rd; reg 1528 arch/powerpc/lib/sstep.c op->reg = rd; reg 1536 arch/powerpc/lib/sstep.c op->reg = rd; reg 1573 arch/powerpc/lib/sstep.c op->reg = rd; reg 1993 arch/powerpc/lib/sstep.c op->reg = rd; reg 1999 arch/powerpc/lib/sstep.c op->reg = rd; reg 2020 arch/powerpc/lib/sstep.c op->reg = rd; reg 2274 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2280 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2286 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2292 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2301 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2313 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2320 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2327 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2336 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2348 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2355 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2361 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2368 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2374 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2380 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2387 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2394 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2401 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2407 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2414 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2420 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2427 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2434 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2441 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2447 arch/powerpc/lib/sstep.c op->reg = rd | ((instr & 1) << 5); reg 2555 arch/powerpc/lib/sstep.c op->reg = rd + 32; reg 2561 arch/powerpc/lib/sstep.c op->reg = rd + 32; reg 2599 arch/powerpc/lib/sstep.c op->reg = rd + 32; reg 2608 arch/powerpc/lib/sstep.c op->reg = rd + 32; reg 2617 arch/powerpc/lib/sstep.c op->reg = rd + 32; reg 2626 arch/powerpc/lib/sstep.c op->reg = rd + 32; reg 2669 arch/powerpc/lib/sstep.c op->reg = ra; reg 2677 arch/powerpc/lib/sstep.c op->reg = rd; reg 2763 arch/powerpc/lib/sstep.c regs->gpr[op->reg] = op->val; reg 2802 arch/powerpc/lib/sstep.c regs->gpr[op->reg] = regs->xer & 0xffffffffUL; reg 2805 arch/powerpc/lib/sstep.c regs->gpr[op->reg] = regs->link; reg 2808 arch/powerpc/lib/sstep.c regs->gpr[op->reg] = regs->ctr; reg 2887 arch/powerpc/lib/sstep.c err = do_lqarx(ea, ®s->gpr[op->reg]); reg 2898 arch/powerpc/lib/sstep.c regs->gpr[op->reg] = val; reg 2924 arch/powerpc/lib/sstep.c err = do_stqcx(ea, regs->gpr[op->reg], reg 2925 arch/powerpc/lib/sstep.c regs->gpr[op->reg + 1], &cr); reg 2942 arch/powerpc/lib/sstep.c err = emulate_lq(regs, ea, op->reg, cross_endian); reg 2946 arch/powerpc/lib/sstep.c err = read_mem(®s->gpr[op->reg], ea, size, regs); reg 2949 arch/powerpc/lib/sstep.c do_signext(®s->gpr[op->reg], size); reg 2951 arch/powerpc/lib/sstep.c do_byterev(®s->gpr[op->reg], size); reg 2972 arch/powerpc/lib/sstep.c err = do_vec_load(op->reg, ea, size, regs, cross_endian); reg 2983 arch/powerpc/lib/sstep.c if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC)) reg 2994 arch/powerpc/lib/sstep.c rd = op->reg; reg 3016 arch/powerpc/lib/sstep.c err = emulate_stq(regs, ea, op->reg, cross_endian); reg 3021 arch/powerpc/lib/sstep.c op->reg == 1 && op->update_reg == 1 && reg 3043 arch/powerpc/lib/sstep.c err = do_vec_store(op->reg, ea, size, regs, cross_endian); reg 3054 arch/powerpc/lib/sstep.c if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC)) reg 3065 arch/powerpc/lib/sstep.c rd = op->reg; reg 3142 arch/powerpc/lib/sstep.c if (op.reg == 0) reg 3146 arch/powerpc/lib/sstep.c if (op.reg == 0) reg 3163 arch/powerpc/lib/sstep.c regs->gpr[op.reg] = regs->msr & MSR_MASK; reg 3167 arch/powerpc/lib/sstep.c val = regs->gpr[op.reg]; reg 842 arch/powerpc/mm/book3s64/hash_utils.c struct memblock_region *reg; reg 931 arch/powerpc/mm/book3s64/hash_utils.c for_each_memblock(memory, reg) { reg 932 arch/powerpc/mm/book3s64/hash_utils.c base = (unsigned long)__va(reg->base); reg 933 arch/powerpc/mm/book3s64/hash_utils.c size = reg->size; reg 314 arch/powerpc/mm/book3s64/radix_pgtable.c struct memblock_region *reg; reg 321 arch/powerpc/mm/book3s64/radix_pgtable.c for_each_memblock(memory, reg) { reg 328 arch/powerpc/mm/book3s64/radix_pgtable.c if ((reg->base + reg->size) >= RADIX_VMALLOC_START) { reg 333 arch/powerpc/mm/book3s64/radix_pgtable.c WARN_ON(create_physical_mapping(reg->base, reg 334 arch/powerpc/mm/book3s64/radix_pgtable.c reg->base + reg->size, reg 135 arch/powerpc/mm/kasan/kasan_init_32.c struct memblock_region *reg; reg 144 arch/powerpc/mm/kasan/kasan_init_32.c for_each_memblock(memory, reg) { reg 145 arch/powerpc/mm/kasan/kasan_init_32.c phys_addr_t base = reg->base; reg 146 arch/powerpc/mm/kasan/kasan_init_32.c phys_addr_t top = min(base + reg->size, total_lowmem); reg 201 arch/powerpc/mm/mem.c struct memblock_region *reg, *prev = NULL; reg 203 arch/powerpc/mm/mem.c for_each_memblock(memory, reg) { reg 205 arch/powerpc/mm/mem.c memblock_region_memory_end_pfn(prev) < memblock_region_memory_base_pfn(reg)) reg 207 arch/powerpc/mm/mem.c memblock_region_memory_base_pfn(reg)); reg 208 arch/powerpc/mm/mem.c prev = reg; reg 592 arch/powerpc/mm/mem.c struct memblock_region *reg; reg 594 arch/powerpc/mm/mem.c for_each_memblock(memory, reg) { reg 596 arch/powerpc/mm/mem.c unsigned long base = reg->base; reg 597 arch/powerpc/mm/mem.c unsigned long size = reg->size; reg 746 arch/powerpc/mm/numa.c struct memblock_region *reg; reg 753 arch/powerpc/mm/numa.c for_each_memblock(memory, reg) { reg 754 arch/powerpc/mm/numa.c start_pfn = memblock_region_memory_base_pfn(reg); reg 755 arch/powerpc/mm/numa.c end_pfn = memblock_region_memory_end_pfn(reg); reg 111 arch/powerpc/mm/pgtable_32.c struct memblock_region *reg; reg 113 arch/powerpc/mm/pgtable_32.c for_each_memblock(memory, reg) { reg 114 arch/powerpc/mm/pgtable_32.c phys_addr_t base = reg->base; reg 115 arch/powerpc/mm/pgtable_32.c phys_addr_t top = min(base + reg->size, total_lowmem); reg 121 arch/powerpc/mm/pgtable_32.c __mapin_ram_chunk(reg->base, top); reg 77 arch/powerpc/net/bpf_jit_comp64.c static int bpf_jit_stack_offsetof(struct codegen_context *ctx, int reg) reg 79 arch/powerpc/net/bpf_jit_comp64.c if (reg >= BPF_PPC_NVR_MIN && reg < 32) reg 82 arch/powerpc/net/bpf_jit_comp64.c - (8 * (32 - reg)); reg 145 arch/powerpc/perf/imc-pmu.c u32 reg; reg 147 arch/powerpc/perf/imc-pmu.c if (of_property_read_u32(np, "reg", ®)) reg 150 arch/powerpc/perf/imc-pmu.c event->value = base + reg; reg 247 arch/powerpc/platforms/44x/fsp2.h #define mtcmu(reg, data) \ reg 249 arch/powerpc/platforms/44x/fsp2.h mtdcr(DCRN_CMU_ADDR, reg); \ reg 253 arch/powerpc/platforms/44x/fsp2.h #define mfcmu(reg)\ reg 255 arch/powerpc/platforms/44x/fsp2.h mtdcr(DCRN_CMU_ADDR, reg); \ reg 259 arch/powerpc/platforms/44x/fsp2.h #define mtl2(reg, data) \ reg 261 arch/powerpc/platforms/44x/fsp2.h mtdcr(DCRN_L2CDCRAI, reg); \ reg 265 arch/powerpc/platforms/44x/fsp2.h #define mfl2(reg) \ reg 267 arch/powerpc/platforms/44x/fsp2.h mtdcr(DCRN_L2CDCRAI, reg); \ reg 222 arch/powerpc/platforms/44x/ppc476.c int reg; reg 228 arch/powerpc/platforms/44x/ppc476.c reg = 0; reg 231 arch/powerpc/platforms/44x/ppc476.c reg = 2; reg 242 arch/powerpc/platforms/44x/ppc476.c board_rev = ioread8(fpga + reg) & 0x03; reg 92 arch/powerpc/platforms/4xx/pci.c void __iomem *reg, reg 206 arch/powerpc/platforms/4xx/pci.c void __iomem *reg, reg 244 arch/powerpc/platforms/4xx/pci.c writel(plb_addr, reg + PCIL0_PMM0LA + (0x10 * index)); reg 245 arch/powerpc/platforms/4xx/pci.c writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * index)); reg 246 arch/powerpc/platforms/4xx/pci.c writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * index)); reg 247 arch/powerpc/platforms/4xx/pci.c writel(ma, reg + PCIL0_PMM0MA + (0x10 * index)); reg 253 arch/powerpc/platforms/4xx/pci.c void __iomem *reg) reg 271 arch/powerpc/platforms/4xx/pci.c if (ppc4xx_setup_one_pci_PMM(hose, reg, reg 289 arch/powerpc/platforms/4xx/pci.c if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0, reg 296 arch/powerpc/platforms/4xx/pci.c void __iomem *reg, reg 307 arch/powerpc/platforms/4xx/pci.c writel(0, reg + PCIL0_PTM1LA); reg 308 arch/powerpc/platforms/4xx/pci.c writel(sa, reg + PCIL0_PTM1MS); reg 326 arch/powerpc/platforms/4xx/pci.c void __iomem *reg = NULL; reg 357 arch/powerpc/platforms/4xx/pci.c reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg)); reg 358 arch/powerpc/platforms/4xx/pci.c if (reg == NULL) { reg 375 arch/powerpc/platforms/4xx/pci.c writel(0, reg + PCIL0_PMM0MA); reg 376 arch/powerpc/platforms/4xx/pci.c writel(0, reg + PCIL0_PMM1MA); reg 377 arch/powerpc/platforms/4xx/pci.c writel(0, reg + PCIL0_PMM2MA); reg 378 arch/powerpc/platforms/4xx/pci.c writel(0, reg + PCIL0_PTM1MS); reg 379 arch/powerpc/platforms/4xx/pci.c writel(0, reg + PCIL0_PTM2MS); reg 385 arch/powerpc/platforms/4xx/pci.c if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0) reg 389 arch/powerpc/platforms/4xx/pci.c ppc4xx_configure_pci_PMMs(hose, reg); reg 392 arch/powerpc/platforms/4xx/pci.c ppc4xx_configure_pci_PTMs(hose, reg, &dma_window); reg 395 arch/powerpc/platforms/4xx/pci.c iounmap(reg); reg 401 arch/powerpc/platforms/4xx/pci.c if (reg) reg 402 arch/powerpc/platforms/4xx/pci.c iounmap(reg); reg 410 arch/powerpc/platforms/4xx/pci.c void __iomem *reg, reg 435 arch/powerpc/platforms/4xx/pci.c writel(lah, reg + PCIX0_POM0LAH); reg 436 arch/powerpc/platforms/4xx/pci.c writel(lal, reg + PCIX0_POM0LAL); reg 437 arch/powerpc/platforms/4xx/pci.c writel(pciah, reg + PCIX0_POM0PCIAH); reg 438 arch/powerpc/platforms/4xx/pci.c writel(pcial, reg + PCIX0_POM0PCIAL); reg 439 arch/powerpc/platforms/4xx/pci.c writel(sa, reg + PCIX0_POM0SA); reg 441 arch/powerpc/platforms/4xx/pci.c writel(lah, reg + PCIX0_POM1LAH); reg 442 arch/powerpc/platforms/4xx/pci.c writel(lal, reg + PCIX0_POM1LAL); reg 443 arch/powerpc/platforms/4xx/pci.c writel(pciah, reg + PCIX0_POM1PCIAH); reg 444 arch/powerpc/platforms/4xx/pci.c writel(pcial, reg + PCIX0_POM1PCIAL); reg 445 arch/powerpc/platforms/4xx/pci.c writel(sa, reg + PCIX0_POM1SA); reg 452 arch/powerpc/platforms/4xx/pci.c void __iomem *reg) reg 470 arch/powerpc/platforms/4xx/pci.c if (ppc4xx_setup_one_pcix_POM(hose, reg, reg 488 arch/powerpc/platforms/4xx/pci.c if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0, reg 495 arch/powerpc/platforms/4xx/pci.c void __iomem *reg, reg 504 arch/powerpc/platforms/4xx/pci.c writel(0x00000000, reg + PCIX0_PIM0LAH); reg 505 arch/powerpc/platforms/4xx/pci.c writel(0x00000000, reg + PCIX0_PIM0LAL); reg 514 arch/powerpc/platforms/4xx/pci.c writel(sa, reg + PCIX0_PIM0SA); reg 516 arch/powerpc/platforms/4xx/pci.c writel(0xffffffff, reg + PCIX0_PIM0SAH); reg 519 arch/powerpc/platforms/4xx/pci.c writel(0x00000000, reg + PCIX0_BAR0H); reg 520 arch/powerpc/platforms/4xx/pci.c writel(res->start, reg + PCIX0_BAR0L); reg 521 arch/powerpc/platforms/4xx/pci.c writew(0x0006, reg + PCIX0_COMMAND); reg 530 arch/powerpc/platforms/4xx/pci.c void __iomem *reg = NULL; reg 563 arch/powerpc/platforms/4xx/pci.c reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg)); reg 564 arch/powerpc/platforms/4xx/pci.c if (reg == NULL) { reg 582 arch/powerpc/platforms/4xx/pci.c writel(0, reg + PCIX0_POM0SA); reg 583 arch/powerpc/platforms/4xx/pci.c writel(0, reg + PCIX0_POM1SA); reg 584 arch/powerpc/platforms/4xx/pci.c writel(0, reg + PCIX0_POM2SA); reg 585 arch/powerpc/platforms/4xx/pci.c writel(0, reg + PCIX0_PIM0SA); reg 586 arch/powerpc/platforms/4xx/pci.c writel(0, reg + PCIX0_PIM1SA); reg 587 arch/powerpc/platforms/4xx/pci.c writel(0, reg + PCIX0_PIM2SA); reg 589 arch/powerpc/platforms/4xx/pci.c writel(0, reg + PCIX0_PIM0SAH); reg 590 arch/powerpc/platforms/4xx/pci.c writel(0, reg + PCIX0_PIM2SAH); reg 597 arch/powerpc/platforms/4xx/pci.c if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0) reg 601 arch/powerpc/platforms/4xx/pci.c ppc4xx_configure_pcix_POMs(hose, reg); reg 604 arch/powerpc/platforms/4xx/pci.c ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi); reg 607 arch/powerpc/platforms/4xx/pci.c iounmap(reg); reg 613 arch/powerpc/platforms/4xx/pci.c if (reg) reg 614 arch/powerpc/platforms/4xx/pci.c iounmap(reg); reg 236 arch/powerpc/platforms/512x/clock-commonclk.c u32 __iomem *reg, u8 pos, u8 len, int divflags) reg 240 arch/powerpc/platforms/512x/clock-commonclk.c reg, pos, len, divflags, &clklock); reg 245 arch/powerpc/platforms/512x/clock-commonclk.c u32 __iomem *reg, u8 pos, u8 len, reg 252 arch/powerpc/platforms/512x/clock-commonclk.c reg, pos, len, divflags, reg 258 arch/powerpc/platforms/512x/clock-commonclk.c u32 __iomem *reg, u8 pos) reg 266 arch/powerpc/platforms/512x/clock-commonclk.c reg, pos, gateflags, &clklock); reg 271 arch/powerpc/platforms/512x/clock-commonclk.c u32 __iomem *reg, u8 pos, u8 len) reg 280 arch/powerpc/platforms/512x/clock-commonclk.c reg, pos, len, muxflags, &clklock); reg 286 arch/powerpc/platforms/512x/clock-commonclk.c static inline int get_bit_field(uint32_t __iomem *reg, uint8_t pos, uint8_t len) reg 290 arch/powerpc/platforms/512x/clock-commonclk.c val = in_be32(reg); reg 32 arch/powerpc/platforms/512x/pdm360ng.c u32 reg; reg 34 arch/powerpc/platforms/512x/pdm360ng.c reg = in_be32(pdm360ng_gpio_base + 0xc); reg 35 arch/powerpc/platforms/512x/pdm360ng.c if (reg & 0x40) reg 38 arch/powerpc/platforms/512x/pdm360ng.c reg = in_be32(pdm360ng_gpio_base + 0x8); reg 41 arch/powerpc/platforms/512x/pdm360ng.c return (reg & 0x40) == 0; reg 177 arch/powerpc/platforms/52xx/mpc52xx_common.c u16 __iomem *reg; reg 187 arch/powerpc/platforms/52xx/mpc52xx_common.c case 1: reg = &mpc52xx_cdm->mclken_div_psc1; mask = 0x20; break; reg 188 arch/powerpc/platforms/52xx/mpc52xx_common.c case 2: reg = &mpc52xx_cdm->mclken_div_psc2; mask = 0x40; break; reg 189 arch/powerpc/platforms/52xx/mpc52xx_common.c case 3: reg = &mpc52xx_cdm->mclken_div_psc3; mask = 0x80; break; reg 190 arch/powerpc/platforms/52xx/mpc52xx_common.c case 6: reg = &mpc52xx_cdm->mclken_div_psc6; mask = 0x10; break; reg 197 arch/powerpc/platforms/52xx/mpc52xx_common.c out_be16(reg, mclken_div); reg 166 arch/powerpc/platforms/52xx/mpc52xx_gpt.c u32 reg; reg 171 arch/powerpc/platforms/52xx/mpc52xx_gpt.c reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK; reg 173 arch/powerpc/platforms/52xx/mpc52xx_gpt.c reg |= MPC52xx_GPT_MODE_ICT_RISING; reg 175 arch/powerpc/platforms/52xx/mpc52xx_gpt.c reg |= MPC52xx_GPT_MODE_ICT_FALLING; reg 176 arch/powerpc/platforms/52xx/mpc52xx_gpt.c out_be32(&gpt->regs->mode, reg); reg 66 arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c void __iomem *reg; reg 94 arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c reg = lpbfifo.regs + LPBFIFO_REG_FIFO_DATA; reg 97 arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c out_be32(reg, *data++); reg 223 arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c void __iomem *reg; reg 268 arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c reg = lpbfifo.regs + LPBFIFO_REG_FIFO_DATA; reg 271 arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c *data++ = in_be32(reg); reg 346 arch/powerpc/platforms/52xx/mpc52xx_pic.c u32 reg; reg 356 arch/powerpc/platforms/52xx/mpc52xx_pic.c reg = in_be32(&intr->ctrl); reg 357 arch/powerpc/platforms/52xx/mpc52xx_pic.c type = mpc52xx_map_senses[(reg >> (22 - l2irq * 2)) & 0x3]; reg 134 arch/powerpc/platforms/85xx/ge_imp3a.c unsigned int reg; reg 136 arch/powerpc/platforms/85xx/ge_imp3a.c reg = ioread16(imp3a_regs); reg 137 arch/powerpc/platforms/85xx/ge_imp3a.c return (reg >> 8) & 0xff; reg 143 arch/powerpc/platforms/85xx/ge_imp3a.c unsigned int reg; reg 145 arch/powerpc/platforms/85xx/ge_imp3a.c reg = ioread16(imp3a_regs + 0x2); reg 146 arch/powerpc/platforms/85xx/ge_imp3a.c return reg & 0xff; reg 152 arch/powerpc/platforms/85xx/ge_imp3a.c unsigned int reg; reg 154 arch/powerpc/platforms/85xx/ge_imp3a.c reg = ioread16(imp3a_regs + 0x2); reg 155 arch/powerpc/platforms/85xx/ge_imp3a.c return (reg >> 8) & 0xff; reg 161 arch/powerpc/platforms/85xx/ge_imp3a.c unsigned int reg; reg 163 arch/powerpc/platforms/85xx/ge_imp3a.c reg = ioread16(imp3a_regs + 0x6); reg 164 arch/powerpc/platforms/85xx/ge_imp3a.c return (reg & 0x0f00) >> 8; reg 170 arch/powerpc/platforms/85xx/ge_imp3a.c unsigned int reg; reg 172 arch/powerpc/platforms/85xx/ge_imp3a.c reg = ioread16(imp3a_regs + 0x6); reg 173 arch/powerpc/platforms/85xx/ge_imp3a.c return reg & (1 << 12); reg 54 arch/powerpc/platforms/85xx/socrates_fpga_pic.c static inline uint32_t socrates_fpga_pic_read(int reg) reg 56 arch/powerpc/platforms/85xx/socrates_fpga_pic.c return in_be32(socrates_fpga_pic_iobase + reg); reg 59 arch/powerpc/platforms/85xx/socrates_fpga_pic.c static inline void socrates_fpga_pic_write(int reg, uint32_t val) reg 61 arch/powerpc/platforms/85xx/socrates_fpga_pic.c out_be32(socrates_fpga_pic_iobase + reg, val); reg 98 arch/powerpc/platforms/86xx/gef_ppc9a.c unsigned int reg; reg 100 arch/powerpc/platforms/86xx/gef_ppc9a.c reg = ioread32be(ppc9a_regs); reg 101 arch/powerpc/platforms/86xx/gef_ppc9a.c return (reg >> 16) & 0xff; reg 107 arch/powerpc/platforms/86xx/gef_ppc9a.c unsigned int reg; reg 109 arch/powerpc/platforms/86xx/gef_ppc9a.c reg = ioread32be(ppc9a_regs); reg 110 arch/powerpc/platforms/86xx/gef_ppc9a.c return (reg >> 8) & 0xff; reg 116 arch/powerpc/platforms/86xx/gef_ppc9a.c unsigned int reg; reg 118 arch/powerpc/platforms/86xx/gef_ppc9a.c reg = ioread32be(ppc9a_regs); reg 119 arch/powerpc/platforms/86xx/gef_ppc9a.c return reg & 0xf; reg 125 arch/powerpc/platforms/86xx/gef_ppc9a.c unsigned int reg; reg 127 arch/powerpc/platforms/86xx/gef_ppc9a.c reg = ioread32be(ppc9a_regs + 0x4); reg 128 arch/powerpc/platforms/86xx/gef_ppc9a.c return reg & 0x1f; reg 134 arch/powerpc/platforms/86xx/gef_ppc9a.c unsigned int reg; reg 136 arch/powerpc/platforms/86xx/gef_ppc9a.c reg = ioread32be(ppc9a_regs + 0x4); reg 137 arch/powerpc/platforms/86xx/gef_ppc9a.c return (reg >> 9) & 0x1; reg 97 arch/powerpc/platforms/86xx/gef_sbc310.c unsigned int reg; reg 99 arch/powerpc/platforms/86xx/gef_sbc310.c reg = ioread32(sbc310_regs); reg 100 arch/powerpc/platforms/86xx/gef_sbc310.c return reg & 0xff; reg 106 arch/powerpc/platforms/86xx/gef_sbc310.c unsigned int reg; reg 108 arch/powerpc/platforms/86xx/gef_sbc310.c reg = ioread32(sbc310_regs); reg 109 arch/powerpc/platforms/86xx/gef_sbc310.c return (reg >> 8) & 0xff; reg 115 arch/powerpc/platforms/86xx/gef_sbc310.c unsigned int reg; reg 117 arch/powerpc/platforms/86xx/gef_sbc310.c reg = ioread32(sbc310_regs); reg 118 arch/powerpc/platforms/86xx/gef_sbc310.c return (reg >> 16) & 0xff; reg 124 arch/powerpc/platforms/86xx/gef_sbc310.c unsigned int reg; reg 126 arch/powerpc/platforms/86xx/gef_sbc310.c reg = ioread32(sbc310_regs); reg 127 arch/powerpc/platforms/86xx/gef_sbc310.c return (reg >> 24) & 0xf; reg 98 arch/powerpc/platforms/86xx/gef_sbc610.c unsigned int reg; reg 100 arch/powerpc/platforms/86xx/gef_sbc610.c reg = ioread32(sbc610_regs); reg 101 arch/powerpc/platforms/86xx/gef_sbc610.c return (reg >> 8) & 0xff; reg 107 arch/powerpc/platforms/86xx/gef_sbc610.c unsigned int reg; reg 109 arch/powerpc/platforms/86xx/gef_sbc610.c reg = ioread32(sbc610_regs); reg 110 arch/powerpc/platforms/86xx/gef_sbc610.c return (reg >> 16) & 0xff; reg 116 arch/powerpc/platforms/86xx/gef_sbc610.c unsigned int reg; reg 118 arch/powerpc/platforms/86xx/gef_sbc610.c reg = ioread32(sbc610_regs); reg 119 arch/powerpc/platforms/86xx/gef_sbc610.c return (reg >> 24) & 0xf; reg 43 arch/powerpc/platforms/86xx/mvme7100.c u8 reg; reg 64 arch/powerpc/platforms/86xx/mvme7100.c reg = readb(mvme7100_regs + MVME7100_INTERRUPT_REG_2_OFFSET); reg 65 arch/powerpc/platforms/86xx/mvme7100.c reg |= MVME7100_DS1375_MASK | MVME7100_MAX6649_MASK reg 67 arch/powerpc/platforms/86xx/mvme7100.c writeb(reg, mvme7100_regs + MVME7100_INTERRUPT_REG_2_OFFSET); reg 401 arch/powerpc/platforms/8xx/cpm1.c u32 __iomem *reg; reg 462 arch/powerpc/platforms/8xx/cpm1.c reg = &mpc8xx_immr->im_cpm.cp_sicr; reg 467 arch/powerpc/platforms/8xx/cpm1.c reg = &mpc8xx_immr->im_cpm.cp_sicr; reg 472 arch/powerpc/platforms/8xx/cpm1.c reg = &mpc8xx_immr->im_cpm.cp_sicr; reg 477 arch/powerpc/platforms/8xx/cpm1.c reg = &mpc8xx_immr->im_cpm.cp_sicr; reg 482 arch/powerpc/platforms/8xx/cpm1.c reg = &mpc8xx_immr->im_cpm.cp_simode; reg 487 arch/powerpc/platforms/8xx/cpm1.c reg = &mpc8xx_immr->im_cpm.cp_simode; reg 511 arch/powerpc/platforms/8xx/cpm1.c if (reg == &mpc8xx_immr->im_cpm.cp_sicr) { reg 521 arch/powerpc/platforms/8xx/cpm1.c out_be32(reg, (in_be32(reg) & ~mask) | bits); reg 77 arch/powerpc/platforms/cell/cbe_thermal.c static u8 spu_read_register_value(struct device *dev, union spe_reg __iomem *reg) reg 83 arch/powerpc/platforms/cell/cbe_thermal.c value.val = in_be64(®->val); reg 132 arch/powerpc/platforms/cell/iommu.c u64 __iomem *reg; reg 136 arch/powerpc/platforms/cell/iommu.c reg = iommu->xlate_regs + IOC_IOPT_CacheInvd; reg 145 arch/powerpc/platforms/cell/iommu.c out_be64(reg, val); reg 146 arch/powerpc/platforms/cell/iommu.c while (in_be64(reg) & IOC_IOPT_CacheInvd_Busy) reg 322 arch/powerpc/platforms/cell/iommu.c unsigned long reg, segments, pages_per_segment, ptab_size, reg 349 arch/powerpc/platforms/cell/iommu.c reg = IOSTE_V | ((n_pte_pages - 1) << 5); reg 352 arch/powerpc/platforms/cell/iommu.c case 12: reg |= IOSTE_PS_4K; break; reg 353 arch/powerpc/platforms/cell/iommu.c case 16: reg |= IOSTE_PS_64K; break; reg 354 arch/powerpc/platforms/cell/iommu.c case 20: reg |= IOSTE_PS_1M; break; reg 355 arch/powerpc/platforms/cell/iommu.c case 24: reg |= IOSTE_PS_16M; break; reg 368 arch/powerpc/platforms/cell/iommu.c iommu->stab[i] = reg | (__pa(ptab) + (n_pte_pages << 12) * reg 379 arch/powerpc/platforms/cell/iommu.c unsigned long reg, xlate_base; reg 393 arch/powerpc/platforms/cell/iommu.c reg = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat); reg 395 arch/powerpc/platforms/cell/iommu.c reg & ~IOC_IO_ExcpStat_V); reg 407 arch/powerpc/platforms/cell/iommu.c reg = IOC_IOST_Origin_E | __pa(iommu->stab) | IOC_IOST_Origin_HW; reg 408 arch/powerpc/platforms/cell/iommu.c out_be64(iommu->xlate_regs + IOC_IOST_Origin, reg); reg 412 arch/powerpc/platforms/cell/iommu.c reg = in_be64(iommu->cmd_regs + IOC_IOCmd_Cfg) | IOC_IOCmd_Cfg_TE; reg 413 arch/powerpc/platforms/cell/iommu.c out_be64(iommu->cmd_regs + IOC_IOCmd_Cfg, reg); reg 31 arch/powerpc/platforms/cell/pmu.c #define WRITE_WO_MMIO(reg, x) \ reg 38 arch/powerpc/platforms/cell/pmu.c out_be64(&(pmd_regs->reg), (((u64)_x) << 32)); \ reg 39 arch/powerpc/platforms/cell/pmu.c shadow_regs->reg = _x; \ reg 42 arch/powerpc/platforms/cell/pmu.c #define READ_SHADOW_REG(val, reg) \ reg 46 arch/powerpc/platforms/cell/pmu.c (val) = shadow_regs->reg; \ reg 49 arch/powerpc/platforms/cell/pmu.c #define READ_MMIO_UPPER32(val, reg) \ reg 53 arch/powerpc/platforms/cell/pmu.c (val) = (u32)(in_be64(&pmd_regs->reg) >> 32); \ reg 174 arch/powerpc/platforms/cell/pmu.c u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg) reg 178 arch/powerpc/platforms/cell/pmu.c switch (reg) { reg 216 arch/powerpc/platforms/cell/pmu.c void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val) reg 218 arch/powerpc/platforms/cell/pmu.c switch (reg) { reg 364 arch/powerpc/platforms/cell/spu_manage.c static struct spu *spu_lookup_reg(int node, u32 reg) reg 371 arch/powerpc/platforms/cell/spu_manage.c if (*spu_reg == reg) reg 381 arch/powerpc/platforms/cell/spu_manage.c u32 reg; reg 386 arch/powerpc/platforms/cell/spu_manage.c reg = qs20_reg_idxs[i]; reg 387 arch/powerpc/platforms/cell/spu_manage.c spu = spu_lookup_reg(node, reg); reg 390 arch/powerpc/platforms/cell/spu_manage.c spu->has_mem_affinity = qs20_reg_memory[reg]; reg 167 arch/powerpc/platforms/chrp/pci.c u32 __iomem *reg; reg 177 arch/powerpc/platforms/chrp/pci.c reg = ioremap(r.start + 0xf6000, 0x40); reg 178 arch/powerpc/platforms/chrp/pci.c BUG_ON(!reg); reg 179 arch/powerpc/platforms/chrp/pci.c val = in_be32(®[12]); reg 181 arch/powerpc/platforms/chrp/pci.c out_be32(®[12], val & ~PRG_CL_RESET_VALID); reg 182 arch/powerpc/platforms/chrp/pci.c in_be32(®[12]); reg 184 arch/powerpc/platforms/chrp/pci.c iounmap(reg); reg 201 arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c const unsigned int *reg; reg 203 arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c reg = of_get_property(np, "reg", NULL); reg 204 arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c if (reg) { reg 205 arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c paddr = of_translate_address(np, reg); reg 207 arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c exi_io_base = ioremap(paddr, reg[1]); reg 44 arch/powerpc/platforms/pasemi/dma_lib.c unsigned int pasemi_read_iob_reg(unsigned int reg) reg 46 arch/powerpc/platforms/pasemi/dma_lib.c return in_le32(iob_regs+reg); reg 54 arch/powerpc/platforms/pasemi/dma_lib.c void pasemi_write_iob_reg(unsigned int reg, unsigned int val) reg 56 arch/powerpc/platforms/pasemi/dma_lib.c out_le32(iob_regs+reg, val); reg 64 arch/powerpc/platforms/pasemi/dma_lib.c unsigned int pasemi_read_mac_reg(int intf, unsigned int reg) reg 66 arch/powerpc/platforms/pasemi/dma_lib.c return in_le32(mac_regs[intf]+reg); reg 75 arch/powerpc/platforms/pasemi/dma_lib.c void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val) reg 77 arch/powerpc/platforms/pasemi/dma_lib.c out_le32(mac_regs[intf]+reg, val); reg 84 arch/powerpc/platforms/pasemi/dma_lib.c unsigned int pasemi_read_dma_reg(unsigned int reg) reg 86 arch/powerpc/platforms/pasemi/dma_lib.c return in_le32(dma_regs+reg); reg 94 arch/powerpc/platforms/pasemi/dma_lib.c void pasemi_write_dma_reg(unsigned int reg, unsigned int val) reg 96 arch/powerpc/platforms/pasemi/dma_lib.c out_le32(dma_regs+reg, val); reg 306 arch/powerpc/platforms/pasemi/dma_lib.c int reg, retries; reg 310 arch/powerpc/platforms/pasemi/dma_lib.c reg = PAS_DMA_RXCHAN_CCMDSTA(chan->chno); reg 311 arch/powerpc/platforms/pasemi/dma_lib.c pasemi_write_dma_reg(reg, PAS_DMA_RXCHAN_CCMDSTA_ST); reg 313 arch/powerpc/platforms/pasemi/dma_lib.c sta = pasemi_read_dma_reg(reg); reg 315 arch/powerpc/platforms/pasemi/dma_lib.c pasemi_write_dma_reg(reg, 0); reg 321 arch/powerpc/platforms/pasemi/dma_lib.c reg = PAS_DMA_TXCHAN_TCMDSTA(chan->chno); reg 322 arch/powerpc/platforms/pasemi/dma_lib.c pasemi_write_dma_reg(reg, PAS_DMA_TXCHAN_TCMDSTA_ST); reg 324 arch/powerpc/platforms/pasemi/dma_lib.c sta = pasemi_read_dma_reg(reg); reg 326 arch/powerpc/platforms/pasemi/dma_lib.c pasemi_write_dma_reg(reg, 0); reg 85 arch/powerpc/platforms/pasemi/gpio_mdio.c static void bitbang_pre(struct mii_bus *bus, int read, u8 addr, u8 reg) reg 110 arch/powerpc/platforms/pasemi/gpio_mdio.c clock_out(bus, (reg & 0x10) != 0); reg 111 arch/powerpc/platforms/pasemi/gpio_mdio.c reg <<= 1; reg 120 arch/powerpc/platforms/pasemi/gpio_mdio.c u8 reg = location & 0xff; reg 122 arch/powerpc/platforms/pasemi/gpio_mdio.c bitbang_pre(bus, 1, addr, reg); reg 159 arch/powerpc/platforms/pasemi/gpio_mdio.c u8 reg = location & 0xff; reg 162 arch/powerpc/platforms/pasemi/gpio_mdio.c bitbang_pre(bus, 0, addr, reg); reg 51 arch/powerpc/platforms/pasemi/pci.c static inline int is_5945_reg(int reg) reg 53 arch/powerpc/platforms/pasemi/pci.c return (((reg >= 0x18) && (reg < 0x34)) || reg 54 arch/powerpc/platforms/pasemi/pci.c ((reg >= 0x158) && (reg < 0x178))); reg 162 arch/powerpc/platforms/pasemi/setup.c int reg; reg 166 arch/powerpc/platforms/pasemi/setup.c reg = 0; reg 169 arch/powerpc/platforms/pasemi/setup.c while (dev && reg < MAX_MCE_REGS) { reg 170 arch/powerpc/platforms/pasemi/setup.c mce_regs[reg].name = kasprintf(GFP_KERNEL, reg 171 arch/powerpc/platforms/pasemi/setup.c "mc%d_mcdebug_errsta", reg); reg 172 arch/powerpc/platforms/pasemi/setup.c mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730); reg 174 arch/powerpc/platforms/pasemi/setup.c reg++; reg 178 arch/powerpc/platforms/pasemi/setup.c if (dev && reg+4 < MAX_MCE_REGS) { reg 179 arch/powerpc/platforms/pasemi/setup.c mce_regs[reg].name = "iobdbg_IntStatus1"; reg 180 arch/powerpc/platforms/pasemi/setup.c mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438); reg 181 arch/powerpc/platforms/pasemi/setup.c reg++; reg 182 arch/powerpc/platforms/pasemi/setup.c mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg"; reg 183 arch/powerpc/platforms/pasemi/setup.c mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454); reg 184 arch/powerpc/platforms/pasemi/setup.c reg++; reg 185 arch/powerpc/platforms/pasemi/setup.c mce_regs[reg].name = "iobiom_IntStatus"; reg 186 arch/powerpc/platforms/pasemi/setup.c mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10); reg 187 arch/powerpc/platforms/pasemi/setup.c reg++; reg 188 arch/powerpc/platforms/pasemi/setup.c mce_regs[reg].name = "iobiom_IntDbgReg"; reg 189 arch/powerpc/platforms/pasemi/setup.c mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c); reg 190 arch/powerpc/platforms/pasemi/setup.c reg++; reg 194 arch/powerpc/platforms/pasemi/setup.c if (dev && reg+2 < MAX_MCE_REGS) { reg 195 arch/powerpc/platforms/pasemi/setup.c mce_regs[reg].name = "l2csts_IntStatus"; reg 196 arch/powerpc/platforms/pasemi/setup.c mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200); reg 197 arch/powerpc/platforms/pasemi/setup.c reg++; reg 198 arch/powerpc/platforms/pasemi/setup.c mce_regs[reg].name = "l2csts_Cnt"; reg 199 arch/powerpc/platforms/pasemi/setup.c mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214); reg 200 arch/powerpc/platforms/pasemi/setup.c reg++; reg 203 arch/powerpc/platforms/pasemi/setup.c num_mce_regs = reg; reg 137 arch/powerpc/platforms/powermac/feature.c int reg, u32 mask, int value) reg 147 arch/powerpc/platforms/powermac/feature.c MACIO_BIS(reg, mask); reg 149 arch/powerpc/platforms/powermac/feature.c MACIO_BIC(reg, mask); reg 150 arch/powerpc/platforms/powermac/feature.c (void)MACIO_IN32(reg); reg 1088 arch/powerpc/platforms/powermac/feature.c u32 reg; reg 1136 arch/powerpc/platforms/powermac/feature.c reg = MACIO_IN32(KEYLARGO_FCR4); reg 1137 arch/powerpc/platforms/powermac/feature.c reg &= ~(KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) | reg 1139 arch/powerpc/platforms/powermac/feature.c reg &= ~(KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) | reg 1141 arch/powerpc/platforms/powermac/feature.c MACIO_OUT32(KEYLARGO_FCR4, reg); reg 1145 arch/powerpc/platforms/powermac/feature.c reg = MACIO_IN32(KEYLARGO_FCR3); reg 1146 arch/powerpc/platforms/powermac/feature.c reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) | reg 1148 arch/powerpc/platforms/powermac/feature.c reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) | reg 1150 arch/powerpc/platforms/powermac/feature.c MACIO_OUT32(KEYLARGO_FCR3, reg); reg 1190 arch/powerpc/platforms/powermac/feature.c reg = MACIO_IN32(KEYLARGO_FCR4); reg 1191 arch/powerpc/platforms/powermac/feature.c reg |= KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) | reg 1193 arch/powerpc/platforms/powermac/feature.c reg |= KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) | reg 1195 arch/powerpc/platforms/powermac/feature.c MACIO_OUT32(KEYLARGO_FCR4, reg); reg 1199 arch/powerpc/platforms/powermac/feature.c reg = MACIO_IN32(KEYLARGO_FCR3); reg 1200 arch/powerpc/platforms/powermac/feature.c reg |= KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) | reg 1202 arch/powerpc/platforms/powermac/feature.c reg |= KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) | reg 1204 arch/powerpc/platforms/powermac/feature.c MACIO_OUT32(KEYLARGO_FCR3, reg); reg 194 arch/powerpc/platforms/powermac/low_i2c.c static inline u8 __kw_read_reg(struct pmac_i2c_host_kw *host, reg_t reg) reg 196 arch/powerpc/platforms/powermac/low_i2c.c return readb(host->base + (((unsigned int)reg) << host->bsteps)); reg 200 arch/powerpc/platforms/powermac/low_i2c.c reg_t reg, u8 val) reg 202 arch/powerpc/platforms/powermac/low_i2c.c writeb(val, host->base + (((unsigned)reg) << host->bsteps)); reg 206 arch/powerpc/platforms/powermac/low_i2c.c #define kw_write_reg(reg, val) __kw_write_reg(host, reg, val) reg 207 arch/powerpc/platforms/powermac/low_i2c.c #define kw_read_reg(reg) __kw_read_reg(host, reg) reg 634 arch/powerpc/platforms/powermac/low_i2c.c const u32 *reg = of_get_property(child, reg 636 arch/powerpc/platforms/powermac/low_i2c.c if (reg == NULL) reg 638 arch/powerpc/platforms/powermac/low_i2c.c kw_i2c_add(host, np, child, *reg); reg 898 arch/powerpc/platforms/powermac/low_i2c.c const u32 *reg; reg 920 arch/powerpc/platforms/powermac/low_i2c.c reg = of_get_property(busnode, "reg", NULL); reg 921 arch/powerpc/platforms/powermac/low_i2c.c if (reg == NULL) reg 932 arch/powerpc/platforms/powermac/low_i2c.c bus->channel = *reg; reg 965 arch/powerpc/platforms/powermac/low_i2c.c const u32 *reg; reg 966 arch/powerpc/platforms/powermac/low_i2c.c reg = of_get_property(prev, "reg", reg 968 arch/powerpc/platforms/powermac/low_i2c.c if (!reg) reg 970 arch/powerpc/platforms/powermac/low_i2c.c if (((*reg) >> 8) != bus->channel) reg 988 arch/powerpc/platforms/powermac/low_i2c.c const u32 *reg = of_get_property(device, "reg", NULL); reg 990 arch/powerpc/platforms/powermac/low_i2c.c if (reg == NULL) reg 993 arch/powerpc/platforms/powermac/low_i2c.c return (*reg) & 0xff; reg 1193 arch/powerpc/platforms/powermac/pci.c u32 reg; reg 1224 arch/powerpc/platforms/powermac/pci.c reg = ((region->start >> 16) & 0xfff0) | (region->end & 0xfff00000); reg 1225 arch/powerpc/platforms/powermac/pci.c pci_write_config_dword(dev, PCI_MEMORY_BASE, reg); reg 118 arch/powerpc/platforms/powermac/pfunc_base.c const u32 *reg = of_get_property(gp, "reg", NULL); reg 120 arch/powerpc/platforms/powermac/pfunc_base.c if (reg == NULL) reg 122 arch/powerpc/platforms/powermac/pfunc_base.c offset = *reg; reg 571 arch/powerpc/platforms/powermac/smp.c const u32 *reg; reg 585 arch/powerpc/platforms/powermac/smp.c reg = of_get_property(cc, "reg", NULL); reg 586 arch/powerpc/platforms/powermac/smp.c if (reg == NULL) reg 588 arch/powerpc/platforms/powermac/smp.c switch (*reg) { reg 67 arch/powerpc/platforms/powermac/udbg_scc.c const u32 *reg; reg 95 arch/powerpc/platforms/powermac/udbg_scc.c reg = of_get_property(escc, "reg", NULL); reg 96 arch/powerpc/platforms/powermac/udbg_scc.c if (reg == NULL) reg 98 arch/powerpc/platforms/powermac/udbg_scc.c addr = reg[0]; reg 101 arch/powerpc/platforms/powermac/udbg_scc.c reg = of_get_property(macio, "assigned-addresses", NULL); reg 102 arch/powerpc/platforms/powermac/udbg_scc.c if (reg == NULL) reg 104 arch/powerpc/platforms/powermac/udbg_scc.c addr += reg[2]; reg 178 arch/powerpc/platforms/powernv/eeh-powernv.c #define PNV_EEH_DBGFS_ENTRY(name, reg) \ reg 181 arch/powerpc/platforms/powernv/eeh-powernv.c return pnv_eeh_dbgfs_set(data, reg, val); \ reg 186 arch/powerpc/platforms/powernv/eeh-powernv.c return pnv_eeh_dbgfs_get(data, reg, val); \ reg 976 arch/powerpc/platforms/powernv/eeh-powernv.c u32 reg = 0; reg 981 arch/powerpc/platforms/powernv/eeh-powernv.c eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); reg 982 arch/powerpc/platforms/powernv/eeh-powernv.c if (!(reg & PCI_EXP_DEVCAP_FLR)) reg 992 arch/powerpc/platforms/powernv/eeh-powernv.c 4, ®); reg 993 arch/powerpc/platforms/powernv/eeh-powernv.c reg |= PCI_EXP_DEVCTL_BCR_FLR; reg 995 arch/powerpc/platforms/powernv/eeh-powernv.c 4, reg); reg 1000 arch/powerpc/platforms/powernv/eeh-powernv.c 4, ®); reg 1001 arch/powerpc/platforms/powernv/eeh-powernv.c reg &= ~PCI_EXP_DEVCTL_BCR_FLR; reg 1003 arch/powerpc/platforms/powernv/eeh-powernv.c 4, reg); reg 400 arch/powerpc/platforms/powernv/ocxl.c u64 reg; reg 411 arch/powerpc/platforms/powernv/ocxl.c "ibm,opal-xsl-mmio", i, ®); reg 414 arch/powerpc/platforms/powernv/ocxl.c regs[i] = ioremap(reg, 8); reg 55 arch/powerpc/platforms/powernv/opal-xscom.c static int opal_scom_read(uint32_t chip, uint64_t addr, u64 reg, u64 *value) reg 60 arch/powerpc/platforms/powernv/opal-xscom.c reg = opal_scom_unmangle(addr + reg); reg 61 arch/powerpc/platforms/powernv/opal-xscom.c rc = opal_xscom_read(chip, reg, (__be64 *)__pa(&v)); reg 70 arch/powerpc/platforms/powernv/opal-xscom.c static int opal_scom_write(uint32_t chip, uint64_t addr, u64 reg, u64 value) reg 74 arch/powerpc/platforms/powernv/opal-xscom.c reg = opal_scom_unmangle(addr + reg); reg 75 arch/powerpc/platforms/powernv/opal-xscom.c rc = opal_xscom_write(chip, reg, value); reg 94 arch/powerpc/platforms/powernv/opal-xscom.c u64 reg, reg_base, reg_cnt, val; reg 102 arch/powerpc/platforms/powernv/opal-xscom.c for (reg = 0; reg < reg_cnt; reg++) { reg 103 arch/powerpc/platforms/powernv/opal-xscom.c rc = opal_scom_read(ent->chip, reg_base, reg, &val); reg 125 arch/powerpc/platforms/powernv/opal-xscom.c u64 reg, reg_base, reg_cnt, val; reg 133 arch/powerpc/platforms/powernv/opal-xscom.c for (reg = 0; reg < reg_cnt; reg++) { reg 136 arch/powerpc/platforms/powernv/opal-xscom.c rc = opal_scom_write(ent->chip, reg_base, reg, val); reg 51 arch/powerpc/platforms/powernv/vas-debug.c char *name, u32 reg) reg 53 arch/powerpc/platforms/powernv/vas-debug.c seq_printf(s, "0x%016llx %s\n", read_hvwc_reg(win, name, reg), name); reg 420 arch/powerpc/platforms/powernv/vas.h s32 reg, u64 val) reg 424 arch/powerpc/platforms/powernv/vas.h regptr = win->uwc_map + reg; reg 431 arch/powerpc/platforms/powernv/vas.h s32 reg, u64 val) reg 435 arch/powerpc/platforms/powernv/vas.h regptr = win->hvwc_map + reg; reg 442 arch/powerpc/platforms/powernv/vas.h char *name __maybe_unused, s32 reg) reg 444 arch/powerpc/platforms/powernv/vas.h return in_be64(win->hvwc_map+reg); reg 269 arch/powerpc/platforms/pseries/pci.c unsigned int reg; reg 275 arch/powerpc/platforms/pseries/pci.c pci_read_config_dword(dev, 0x40, ®); reg 277 arch/powerpc/platforms/pseries/pci.c pci_write_config_dword(dev, 0x40, reg | (1<<11)); reg 715 arch/powerpc/platforms/pseries/setup.c const __be32 *reg; reg 719 arch/powerpc/platforms/pseries/setup.c reg = of_get_property(dn, "ibm,is-open-sriov-pf", NULL); reg 720 arch/powerpc/platforms/pseries/setup.c if (!reg) reg 145 arch/powerpc/sysdev/cpm2.c u32 __iomem *reg; reg 211 arch/powerpc/sysdev/cpm2.c reg = &im_cpmux->cmx_scr; reg 215 arch/powerpc/sysdev/cpm2.c reg = &im_cpmux->cmx_scr; reg 219 arch/powerpc/sysdev/cpm2.c reg = &im_cpmux->cmx_scr; reg 223 arch/powerpc/sysdev/cpm2.c reg = &im_cpmux->cmx_scr; reg 227 arch/powerpc/sysdev/cpm2.c reg = &im_cpmux->cmx_fcr; reg 231 arch/powerpc/sysdev/cpm2.c reg = &im_cpmux->cmx_fcr; reg 235 arch/powerpc/sysdev/cpm2.c reg = &im_cpmux->cmx_fcr; reg 263 arch/powerpc/sysdev/cpm2.c out_be32(reg, (in_be32(reg) & ~mask) | bits); reg 275 arch/powerpc/sysdev/cpm2.c u8 __iomem *reg; reg 293 arch/powerpc/sysdev/cpm2.c reg = &im_cpmux->cmx_smr; reg 298 arch/powerpc/sysdev/cpm2.c reg = &im_cpmux->cmx_smr; reg 319 arch/powerpc/sysdev/cpm2.c out_8(reg, (in_8(reg) & ~mask) | bits); reg 62 arch/powerpc/sysdev/dart_iommu.c unsigned int reg, inv_bit; reg 82 arch/powerpc/sysdev/dart_iommu.c reg = DART_IN(DART_CNTL); reg 83 arch/powerpc/sysdev/dart_iommu.c reg |= inv_bit; reg 84 arch/powerpc/sysdev/dart_iommu.c DART_OUT(DART_CNTL, reg); reg 91 arch/powerpc/sysdev/dart_iommu.c reg = DART_IN(DART_CNTL); reg 92 arch/powerpc/sysdev/dart_iommu.c reg &= ~inv_bit; reg 93 arch/powerpc/sysdev/dart_iommu.c DART_OUT(DART_CNTL, reg); reg 105 arch/powerpc/sysdev/dart_iommu.c unsigned int reg; reg 111 arch/powerpc/sysdev/dart_iommu.c reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE | reg 113 arch/powerpc/sysdev/dart_iommu.c DART_OUT(DART_CNTL, reg); reg 52 arch/powerpc/sysdev/fsl_msi.c static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg) reg 54 arch/powerpc/sysdev/fsl_msi.c return in_be32(base + (reg >> 2)); reg 149 arch/powerpc/sysdev/fsl_msi.c const __be64 *reg; reg 152 arch/powerpc/sysdev/fsl_msi.c reg = of_get_property(hose->dn, "msi-address-64", &len); reg 153 arch/powerpc/sysdev/fsl_msi.c if (reg && (len == sizeof(u64))) reg 154 arch/powerpc/sysdev/fsl_msi.c address = be64_to_cpup(reg); reg 202 arch/powerpc/sysdev/fsl_pci.c const u64 *reg; reg 330 arch/powerpc/sysdev/fsl_pci.c reg = of_get_property(hose->dn, "msi-address-64", &len); reg 331 arch/powerpc/sysdev/fsl_pci.c if (reg && (len == sizeof(u64))) { reg 332 arch/powerpc/sysdev/fsl_pci.c u64 address = be64_to_cpup(reg); reg 750 arch/powerpc/sysdev/fsl_pci.c struct resource *reg) reg 760 arch/powerpc/sysdev/fsl_pci.c pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); reg 25 arch/powerpc/sysdev/indirect_pci.c u32 bus_no, reg; reg 46 arch/powerpc/sysdev/indirect_pci.c reg = ((offset & 0xf00) << 16) | (offset & 0xfc); reg 48 arch/powerpc/sysdev/indirect_pci.c reg = offset & 0xfc; reg 52 arch/powerpc/sysdev/indirect_pci.c (devfn << 8) | reg | cfg_type)); reg 55 arch/powerpc/sysdev/indirect_pci.c (devfn << 8) | reg | cfg_type)); reg 91 arch/powerpc/sysdev/indirect_pci.c u32 bus_no, reg; reg 112 arch/powerpc/sysdev/indirect_pci.c reg = ((offset & 0xf00) << 16) | (offset & 0xfc); reg 114 arch/powerpc/sysdev/indirect_pci.c reg = offset & 0xfc; reg 118 arch/powerpc/sysdev/indirect_pci.c (devfn << 8) | reg | cfg_type)); reg 121 arch/powerpc/sysdev/indirect_pci.c (devfn << 8) | reg | cfg_type)); reg 505 arch/powerpc/sysdev/ipic.c static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg) reg 507 arch/powerpc/sysdev/ipic.c return in_be32(base + (reg >> 2)); reg 510 arch/powerpc/sysdev/ipic.c static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value) reg 512 arch/powerpc/sysdev/ipic.c out_be32(base + (reg >> 2), value); reg 175 arch/powerpc/sysdev/mpic.c unsigned int reg) reg 180 arch/powerpc/sysdev/mpic.c return dcr_read(rb->dhost, reg); reg 183 arch/powerpc/sysdev/mpic.c return in_be32(rb->base + (reg >> 2)); reg 186 arch/powerpc/sysdev/mpic.c return in_le32(rb->base + (reg >> 2)); reg 192 arch/powerpc/sysdev/mpic.c unsigned int reg, u32 value) reg 197 arch/powerpc/sysdev/mpic.c dcr_write(rb->dhost, reg, value); reg 201 arch/powerpc/sysdev/mpic.c out_be32(rb->base + (reg >> 2), value); reg 205 arch/powerpc/sysdev/mpic.c out_le32(rb->base + (reg >> 2), value); reg 251 arch/powerpc/sysdev/mpic.c static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) reg 255 arch/powerpc/sysdev/mpic.c return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); reg 258 arch/powerpc/sysdev/mpic.c static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) reg 262 arch/powerpc/sysdev/mpic.c _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); reg 265 arch/powerpc/sysdev/mpic.c static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) reg 272 arch/powerpc/sysdev/mpic.c reg + (idx * MPIC_INFO(IRQ_STRIDE))); reg 274 arch/powerpc/sysdev/mpic.c if (reg == 0) reg 282 arch/powerpc/sysdev/mpic.c unsigned int reg, u32 value) reg 288 arch/powerpc/sysdev/mpic.c reg + (idx * MPIC_INFO(IRQ_STRIDE)), value); reg 291 arch/powerpc/sysdev/mpic.c if (reg == 0) reg 1669 arch/powerpc/sysdev/mpic.c u32 reg; reg 1676 arch/powerpc/sysdev/mpic.c reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & reg 1679 arch/powerpc/sysdev/mpic.c reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); reg 1681 arch/powerpc/sysdev/mpic.c reg = mpic_tm_read(src - mpic->timer_vecs[0]) & reg 1684 arch/powerpc/sysdev/mpic.c reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); reg 1686 arch/powerpc/sysdev/mpic.c reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) reg 1689 arch/powerpc/sysdev/mpic.c reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); reg 1769 arch/powerpc/sysdev/mpic.c static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) reg 1773 arch/powerpc/sysdev/mpic.c src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK); reg 1775 arch/powerpc/sysdev/mpic.c DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); reg 675 arch/powerpc/sysdev/xive/spapr.c const __be32 *reg; reg 685 arch/powerpc/sysdev/xive/spapr.c reg = of_get_property(rootdn, "ibm,plat-res-int-priorities", &len); reg 686 arch/powerpc/sysdev/xive/spapr.c if (!reg) { reg 706 arch/powerpc/sysdev/xive/spapr.c int base = be32_to_cpu(reg[2 * i]); reg 707 arch/powerpc/sysdev/xive/spapr.c int range = be32_to_cpu(reg[2 * i + 1]); reg 784 arch/powerpc/sysdev/xive/spapr.c const __be32 *reg; reg 813 arch/powerpc/sysdev/xive/spapr.c reg = of_get_property(np, "ibm,xive-lisn-ranges", &len); reg 814 arch/powerpc/sysdev/xive/spapr.c if (!reg) { reg 824 arch/powerpc/sysdev/xive/spapr.c for (i = 0; i < len / (2 * sizeof(u32)); i++, reg += 2) reg 825 arch/powerpc/sysdev/xive/spapr.c xive_irq_bitmap_add(be32_to_cpu(reg[0]), reg 826 arch/powerpc/sysdev/xive/spapr.c be32_to_cpu(reg[1])); reg 829 arch/powerpc/sysdev/xive/spapr.c of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) { reg 92 arch/riscv/mm/init.c struct memblock_region *reg; reg 98 arch/riscv/mm/init.c for_each_memblock(memory, reg) { reg 99 arch/riscv/mm/init.c phys_addr_t end = reg->base + reg->size; reg 101 arch/riscv/mm/init.c if (reg->base <= vmlinux_start && vmlinux_end <= end) { reg 102 arch/riscv/mm/init.c mem_size = min(reg->size, (phys_addr_t)-PAGE_OFFSET); reg 108 arch/riscv/mm/init.c if (reg->base + mem_size < end) reg 109 arch/riscv/mm/init.c memblock_remove(reg->base + mem_size, reg 110 arch/riscv/mm/init.c end - reg->base - mem_size); reg 136 arch/riscv/mm/init.c for_each_memblock(memory, reg) { reg 137 arch/riscv/mm/init.c unsigned long start_pfn = memblock_region_memory_base_pfn(reg); reg 138 arch/riscv/mm/init.c unsigned long end_pfn = memblock_region_memory_end_pfn(reg); reg 414 arch/riscv/mm/init.c struct memblock_region *reg; reg 425 arch/riscv/mm/init.c for_each_memblock(memory, reg) { reg 426 arch/riscv/mm/init.c start = reg->base; reg 427 arch/riscv/mm/init.c end = start + reg->size; reg 431 arch/riscv/mm/init.c if (memblock_is_nomap(reg)) reg 94 arch/riscv/net/bpf_jit_comp.c u8 reg = regmap[bpf_reg]; reg 96 arch/riscv/net/bpf_jit_comp.c switch (reg) { reg 103 arch/riscv/net/bpf_jit_comp.c __set_bit(reg, &ctx->flags); reg 105 arch/riscv/net/bpf_jit_comp.c return reg; reg 108 arch/riscv/net/bpf_jit_comp.c static bool seen_reg(int reg, struct rv_jit_context *ctx) reg 110 arch/riscv/net/bpf_jit_comp.c switch (reg) { reg 118 arch/riscv/net/bpf_jit_comp.c return test_bit(reg, &ctx->flags); reg 567 arch/riscv/net/bpf_jit_comp.c static void __build_epilogue(u8 reg, struct rv_jit_context *ctx) reg 604 arch/riscv/net/bpf_jit_comp.c if (reg == RV_REG_RA) reg 606 arch/riscv/net/bpf_jit_comp.c emit(rv_jalr(RV_REG_ZERO, reg, 0), ctx); reg 609 arch/riscv/net/bpf_jit_comp.c static void emit_zext_32(u8 reg, struct rv_jit_context *ctx) reg 611 arch/riscv/net/bpf_jit_comp.c emit(rv_slli(reg, reg, 32), ctx); reg 612 arch/riscv/net/bpf_jit_comp.c emit(rv_srli(reg, reg, 32), ctx); reg 60 arch/s390/include/asm/ctl_reg.h unsigned long reg; reg 62 arch/s390/include/asm/ctl_reg.h __ctl_store(reg, cr, cr); reg 63 arch/s390/include/asm/ctl_reg.h reg |= 1UL << bit; reg 64 arch/s390/include/asm/ctl_reg.h __ctl_load(reg, cr, cr); reg 69 arch/s390/include/asm/ctl_reg.h unsigned long reg; reg 71 arch/s390/include/asm/ctl_reg.h __ctl_store(reg, cr, cr); reg 72 arch/s390/include/asm/ctl_reg.h reg &= ~(1UL << bit); reg 73 arch/s390/include/asm/ctl_reg.h __ctl_load(reg, cr, cr); reg 54 arch/s390/include/asm/nospec-insn.h .macro __DECODE_RR expand,reg,ruse reg 92 arch/s390/include/asm/nospec-insn.h .macro __DECODE_DRR expand,disp,reg,ruse reg 109 arch/s390/include/asm/nospec-insn.h .macro __THUNK_EX_BR reg,ruse reg 129 arch/s390/include/asm/nospec-insn.h .macro __THUNK_EX_BC disp,reg,ruse reg 141 arch/s390/include/asm/nospec-insn.h .macro GEN_BR_THUNK reg,ruse=%r1 reg 147 arch/s390/include/asm/nospec-insn.h .macro GEN_B_THUNK disp,reg,ruse=%r1 reg 153 arch/s390/include/asm/nospec-insn.h .macro BR_EX reg,ruse=%r1 reg 160 arch/s390/include/asm/nospec-insn.h .macro B_EX disp,reg,ruse=%r1 reg 175 arch/s390/include/asm/nospec-insn.h .macro GEN_BR_THUNK reg,ruse=%r1 reg 178 arch/s390/include/asm/nospec-insn.h .macro GEN_B_THUNK disp,reg,ruse=%r1 reg 181 arch/s390/include/asm/nospec-insn.h .macro BR_EX reg,ruse=%r1 reg 185 arch/s390/include/asm/nospec-insn.h .macro B_EX disp,reg,ruse=%r1 reg 495 arch/s390/kernel/kprobes.c int reg = (p->ainsn.insn[0] & 0xf0) >> 4; reg 496 arch/s390/kernel/kprobes.c regs->gprs[reg] += (unsigned long) p->addr - reg 848 arch/s390/kernel/perf_cpum_sf.c hwc->extra_reg.reg = REG_OVERFLOW; reg 502 arch/s390/kernel/setup.c struct memblock_region *reg; reg 512 arch/s390/kernel/setup.c for_each_memblock(memory, reg) { reg 520 arch/s390/kernel/setup.c res->start = reg->base; reg 521 arch/s390/kernel/setup.c res->end = reg->base + reg->size - 1; reg 842 arch/s390/kernel/setup.c struct memblock_region *reg; reg 847 arch/s390/kernel/setup.c for_each_memblock(memory, reg) { reg 848 arch/s390/kernel/setup.c storage_key_init_range(reg->base, reg->base + reg->size); reg 91 arch/s390/kernel/uprobes.c int reg = (auprobe->insn[0] & 0xf0) >> 4; reg 93 arch/s390/kernel/uprobes.c regs->gprs[reg] += utask->vaddr - utask->xol_vaddr; reg 232 arch/s390/kernel/uprobes.c u8 reg : 4; reg 278 arch/s390/kernel/uprobes.c rx = (union split_register *) ®s->gprs[insn->reg]; reg 174 arch/s390/kvm/diag.c unsigned int reg = vcpu->arch.sie_block->ipa & 0xf; reg 175 arch/s390/kvm/diag.c unsigned long subcode = vcpu->run->s.regs.gprs[reg] & 0xffff; reg 3193 arch/s390/kvm/kvm-s390.c struct kvm_one_reg *reg) reg 3197 arch/s390/kvm/kvm-s390.c switch (reg->id) { reg 3200 arch/s390/kvm/kvm-s390.c (u32 __user *)reg->addr); reg 3204 arch/s390/kvm/kvm-s390.c (u64 __user *)reg->addr); reg 3208 arch/s390/kvm/kvm-s390.c (u64 __user *)reg->addr); reg 3212 arch/s390/kvm/kvm-s390.c (u64 __user *)reg->addr); reg 3216 arch/s390/kvm/kvm-s390.c (u64 __user *)reg->addr); reg 3220 arch/s390/kvm/kvm-s390.c (u64 __user *)reg->addr); reg 3224 arch/s390/kvm/kvm-s390.c (u64 __user *)reg->addr); reg 3228 arch/s390/kvm/kvm-s390.c (u64 __user *)reg->addr); reg 3232 arch/s390/kvm/kvm-s390.c (u64 __user *)reg->addr); reg 3242 arch/s390/kvm/kvm-s390.c struct kvm_one_reg *reg) reg 3247 arch/s390/kvm/kvm-s390.c switch (reg->id) { reg 3250 arch/s390/kvm/kvm-s390.c (u32 __user *)reg->addr); reg 3254 arch/s390/kvm/kvm-s390.c (u64 __user *)reg->addr); reg 3257 arch/s390/kvm/kvm-s390.c r = get_user(val, (u64 __user *)reg->addr); reg 3263 arch/s390/kvm/kvm-s390.c (u64 __user *)reg->addr); reg 3267 arch/s390/kvm/kvm-s390.c (u64 __user *)reg->addr); reg 3273 arch/s390/kvm/kvm-s390.c (u64 __user *)reg->addr); reg 3277 arch/s390/kvm/kvm-s390.c (u64 __user *)reg->addr); reg 3281 arch/s390/kvm/kvm-s390.c (u64 __user *)reg->addr); reg 3285 arch/s390/kvm/kvm-s390.c (u64 __user *)reg->addr); reg 4375 arch/s390/kvm/kvm-s390.c struct kvm_one_reg reg; reg 4377 arch/s390/kvm/kvm-s390.c if (copy_from_user(®, argp, sizeof(reg))) reg 4380 arch/s390/kvm/kvm-s390.c r = kvm_arch_vcpu_ioctl_set_one_reg(vcpu, ®); reg 4382 arch/s390/kvm/kvm-s390.c r = kvm_arch_vcpu_ioctl_get_one_reg(vcpu, ®); reg 1278 arch/s390/kvm/priv.c int reg, rc, nr_regs; reg 1300 arch/s390/kvm/priv.c reg = reg1; reg 1303 arch/s390/kvm/priv.c vcpu->arch.sie_block->gcr[reg] &= 0xffffffff00000000ul; reg 1304 arch/s390/kvm/priv.c vcpu->arch.sie_block->gcr[reg] |= ctl_array[nr_regs++]; reg 1305 arch/s390/kvm/priv.c if (reg == reg3) reg 1307 arch/s390/kvm/priv.c reg = (reg + 1) % 16; reg 1317 arch/s390/kvm/priv.c int reg, rc, nr_regs; reg 1335 arch/s390/kvm/priv.c reg = reg1; reg 1338 arch/s390/kvm/priv.c ctl_array[nr_regs++] = vcpu->arch.sie_block->gcr[reg]; reg 1339 arch/s390/kvm/priv.c if (reg == reg3) reg 1341 arch/s390/kvm/priv.c reg = (reg + 1) % 16; reg 1351 arch/s390/kvm/priv.c int reg, rc, nr_regs; reg 1373 arch/s390/kvm/priv.c reg = reg1; reg 1376 arch/s390/kvm/priv.c vcpu->arch.sie_block->gcr[reg] = ctl_array[nr_regs++]; reg 1377 arch/s390/kvm/priv.c if (reg == reg3) reg 1379 arch/s390/kvm/priv.c reg = (reg + 1) % 16; reg 1389 arch/s390/kvm/priv.c int reg, rc, nr_regs; reg 1407 arch/s390/kvm/priv.c reg = reg1; reg 1410 arch/s390/kvm/priv.c ctl_array[nr_regs++] = vcpu->arch.sie_block->gcr[reg]; reg 1411 arch/s390/kvm/priv.c if (reg == reg3) reg 1413 arch/s390/kvm/priv.c reg = (reg + 1) % 16; reg 21 arch/s390/kvm/sigp.c u64 *reg) reg 31 arch/s390/kvm/sigp.c *reg &= 0xffffffff00000000UL; reg 33 arch/s390/kvm/sigp.c *reg |= SIGP_STATUS_EXT_CALL_PENDING; reg 35 arch/s390/kvm/sigp.c *reg |= SIGP_STATUS_STOPPED; reg 68 arch/s390/kvm/sigp.c u16 asn, u64 *reg) reg 87 arch/s390/kvm/sigp.c *reg &= 0xffffffff00000000UL; reg 88 arch/s390/kvm/sigp.c *reg |= SIGP_STATUS_INCORRECT_STATE; reg 94 arch/s390/kvm/sigp.c struct kvm_vcpu *dst_vcpu, u64 *reg) reg 104 arch/s390/kvm/sigp.c *reg &= 0xffffffff00000000UL; reg 105 arch/s390/kvm/sigp.c *reg |= SIGP_STATUS_EXT_CALL_PENDING; reg 133 arch/s390/kvm/sigp.c struct kvm_vcpu *dst_vcpu, u64 *reg) reg 174 arch/s390/kvm/sigp.c u32 address, u64 *reg) reg 188 arch/s390/kvm/sigp.c *reg &= 0xffffffff00000000UL; reg 189 arch/s390/kvm/sigp.c *reg |= SIGP_STATUS_INVALID_PARAMETER; reg 195 arch/s390/kvm/sigp.c *reg &= 0xffffffff00000000UL; reg 196 arch/s390/kvm/sigp.c *reg |= SIGP_STATUS_INCORRECT_STATE; reg 205 arch/s390/kvm/sigp.c u32 addr, u64 *reg) reg 210 arch/s390/kvm/sigp.c *reg &= 0xffffffff00000000UL; reg 211 arch/s390/kvm/sigp.c *reg |= SIGP_STATUS_INCORRECT_STATE; reg 218 arch/s390/kvm/sigp.c *reg &= 0xffffffff00000000UL; reg 219 arch/s390/kvm/sigp.c *reg |= SIGP_STATUS_INVALID_PARAMETER; reg 226 arch/s390/kvm/sigp.c struct kvm_vcpu *dst_vcpu, u64 *reg) reg 231 arch/s390/kvm/sigp.c *reg &= 0xffffffff00000000UL; reg 232 arch/s390/kvm/sigp.c *reg |= SIGP_STATUS_INVALID_ORDER; reg 241 arch/s390/kvm/sigp.c *reg &= 0xffffffff00000000UL; reg 242 arch/s390/kvm/sigp.c *reg |= SIGP_STATUS_NOT_RUNNING; reg 186 arch/s390/mm/page-states.c struct memblock_region *reg; reg 196 arch/s390/mm/page-states.c for_each_memblock(memory, reg) { reg 197 arch/s390/mm/page-states.c start = memblock_region_memory_base_pfn(reg); reg 198 arch/s390/mm/page-states.c end = memblock_region_memory_end_pfn(reg); reg 403 arch/s390/mm/vmem.c struct memblock_region *reg; reg 405 arch/s390/mm/vmem.c for_each_memblock(memory, reg) reg 406 arch/s390/mm/vmem.c vmem_add_mem(reg->base, reg->size); reg 432 arch/s390/mm/vmem.c struct memblock_region *reg; reg 436 arch/s390/mm/vmem.c for_each_memblock(memory, reg) { reg 440 arch/s390/mm/vmem.c seg->start = reg->base; reg 441 arch/s390/mm/vmem.c seg->size = reg->size; reg 108 arch/s390/net/bpf_jit_comp.c static inline u32 reg_high(u32 reg) reg 110 arch/s390/net/bpf_jit_comp.c return reg2hex[reg] << 4; reg 141 arch/s390/net/bpf_jit_comp.c _EMIT2(op | reg(b1, b2)); \ reg 155 arch/s390/net/bpf_jit_comp.c _EMIT4(op | reg(b1, b2)); \ reg 162 arch/s390/net/bpf_jit_comp.c _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \ reg 220 arch/s390/net/bpf_jit_comp.c _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \ reg 230 arch/s390/net/bpf_jit_comp.c _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \ reg 249 arch/s390/net/bpf_jit_comp.c _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \ reg 58 arch/sh/boards/mach-cayman/irq.c unsigned int reg; reg 62 arch/sh/boards/mach-cayman/irq.c reg = EPLD_MASK_BASE + ((irq / 8) << 2); reg 65 arch/sh/boards/mach-cayman/irq.c mask = __raw_readl(reg); reg 67 arch/sh/boards/mach-cayman/irq.c __raw_writel(mask, reg); reg 76 arch/sh/boards/mach-cayman/irq.c unsigned int reg; reg 80 arch/sh/boards/mach-cayman/irq.c reg = EPLD_MASK_BASE + ((irq / 8) << 2); reg 83 arch/sh/boards/mach-cayman/irq.c mask = __raw_readl(reg); reg 85 arch/sh/boards/mach-cayman/irq.c __raw_writel(mask, reg); reg 51 arch/sh/boards/mach-migor/lcd_qvga.c unsigned short reg, unsigned short data) reg 53 arch/sh/boards/mach-migor/lcd_qvga.c sys_ops->write_index(sys_ops_handle, adjust_reg18(reg << 8 | data)); reg 58 arch/sh/boards/mach-migor/lcd_qvga.c unsigned short reg, unsigned short data) reg 60 arch/sh/boards/mach-migor/lcd_qvga.c sys_ops->write_index(sys_ops_handle, adjust_reg18(reg)); reg 66 arch/sh/boards/mach-migor/lcd_qvga.c unsigned short reg) reg 70 arch/sh/boards/mach-migor/lcd_qvga.c sys_ops->write_index(sys_ops_handle, adjust_reg18(reg)); reg 23 arch/sh/drivers/pci/ops-sh7786.c int dev, func, type, reg; reg 28 arch/sh/drivers/pci/ops-sh7786.c reg = where & ~3; reg 51 arch/sh/drivers/pci/ops-sh7786.c *data = pci_read_reg(chan, PCI_REG(reg)); reg 53 arch/sh/drivers/pci/ops-sh7786.c pci_write_reg(chan, *data, PCI_REG(reg)); reg 65 arch/sh/drivers/pci/ops-sh7786.c (func << 16) | reg, SH4A_PCIEPAR); reg 171 arch/sh/drivers/pci/pci-sh4.h unsigned long val, unsigned long reg) reg 173 arch/sh/drivers/pci/pci-sh4.h __raw_writel(val, chan->reg_base + reg); reg 177 arch/sh/drivers/pci/pci-sh4.h unsigned long reg) reg 179 arch/sh/drivers/pci/pci-sh4.h return __raw_readl(chan->reg_base + reg); reg 87 arch/sh/drivers/pci/pci-sh5.h #define SH5PCI_WRITE(reg,val) __raw_writel((u32)(val),PCISH5_ICR_REG(reg)) reg 88 arch/sh/drivers/pci/pci-sh5.h #define SH5PCI_WRITE_SHORT(reg,val) __raw_writew((u16)(val),PCISH5_ICR_REG(reg)) reg 89 arch/sh/drivers/pci/pci-sh5.h #define SH5PCI_WRITE_BYTE(reg,val) __raw_writeb((u8)(val),PCISH5_ICR_REG(reg)) reg 92 arch/sh/drivers/pci/pci-sh5.h #define SH5PCI_READ(reg) __raw_readl(PCISH5_ICR_REG(reg)) reg 93 arch/sh/drivers/pci/pci-sh5.h #define SH5PCI_READ_SHORT(reg) __raw_readw(PCISH5_ICR_REG(reg)) reg 94 arch/sh/drivers/pci/pci-sh5.h #define SH5PCI_READ_BYTE(reg) __raw_readb(PCISH5_ICR_REG(reg)) reg 79 arch/sh/drivers/pci/pci-sh7751.c u32 word, reg; reg 94 arch/sh/drivers/pci/pci-sh7751.c reg = __raw_readl(SH7751_BCR1); reg 95 arch/sh/drivers/pci/pci-sh7751.c reg |= 0x80000; reg 96 arch/sh/drivers/pci/pci-sh7751.c __raw_writel(reg, SH7751_BCR1); reg 566 arch/sh/drivers/pci/pcie-sh7786.h pci_write_reg(struct pci_channel *chan, unsigned long val, unsigned long reg) reg 568 arch/sh/drivers/pci/pcie-sh7786.h __raw_writel(val, chan->reg_base + reg); reg 572 arch/sh/drivers/pci/pcie-sh7786.h pci_read_reg(struct pci_channel *chan, unsigned long reg) reg 574 arch/sh/drivers/pci/pcie-sh7786.h return __raw_readl(chan->reg_base + reg); reg 203 arch/sh/include/asm/dwarf.h static __always_inline unsigned long dwarf_read_arch_reg(unsigned int reg) reg 207 arch/sh/include/asm/dwarf.h switch (reg) { reg 19 arch/sh/include/mach-common/mach/magicpanelr2.h #define SETBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) | mask, reg) reg 20 arch/sh/include/mach-common/mach/magicpanelr2.h #define SETBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) | mask, reg) reg 21 arch/sh/include/mach-common/mach/magicpanelr2.h #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg) reg 22 arch/sh/include/mach-common/mach/magicpanelr2.h #define CLRBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) & ~mask, reg) reg 23 arch/sh/include/mach-common/mach/magicpanelr2.h #define CLRBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) & ~mask, reg) reg 24 arch/sh/include/mach-common/mach/magicpanelr2.h #define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg) reg 138 arch/sh/include/mach-sdk7786/mach/fpga.h #define SDK7786_FPGA_REGADDR(reg) (sdk7786_fpga_base + (reg)) reg 144 arch/sh/include/mach-sdk7786/mach/fpga.h #define SDK7786_FPGA_I2CADDR(reg) ((reg) >> 3) reg 146 arch/sh/include/mach-sdk7786/mach/fpga.h static inline u16 fpga_read_reg(unsigned int reg) reg 148 arch/sh/include/mach-sdk7786/mach/fpga.h return ioread16(sdk7786_fpga_base + reg); reg 151 arch/sh/include/mach-sdk7786/mach/fpga.h static inline void fpga_write_reg(u16 val, unsigned int reg) reg 153 arch/sh/include/mach-sdk7786/mach/fpga.h iowrite16(val, sdk7786_fpga_base + reg); reg 81 arch/sh/kernel/cpu/irq/intc-sh5.c unsigned long reg; reg 88 arch/sh/kernel/cpu/irq/intc-sh5.c reg = INTC_INTENB_0; reg 91 arch/sh/kernel/cpu/irq/intc-sh5.c reg = INTC_INTENB_1; reg 95 arch/sh/kernel/cpu/irq/intc-sh5.c __raw_writel(bitmask, reg); reg 101 arch/sh/kernel/cpu/irq/intc-sh5.c unsigned long reg; reg 105 arch/sh/kernel/cpu/irq/intc-sh5.c reg = INTC_INTDSB_0; reg 108 arch/sh/kernel/cpu/irq/intc-sh5.c reg = INTC_INTDSB_1; reg 112 arch/sh/kernel/cpu/irq/intc-sh5.c __raw_writel(bitmask, reg); reg 124 arch/sh/kernel/cpu/irq/intc-sh5.c unsigned long reg; reg 142 arch/sh/kernel/cpu/irq/intc-sh5.c for (reg = INTC_INTPRI_0, i = 0; i < INTC_INTPRI_PREGS; i++, reg += 8) reg 143 arch/sh/kernel/cpu/irq/intc-sh5.c __raw_writel( NO_PRIORITY, reg); reg 160 arch/sh/kernel/cpu/irq/intc-sh5.c reg = INTC_ICR_CLEAR; reg 165 arch/sh/kernel/cpu/irq/intc-sh5.c reg = INTC_ICR_SET; reg 168 arch/sh/kernel/cpu/irq/intc-sh5.c __raw_writel(INTC_ICR_IRLM, reg); reg 171 arch/sh/kernel/cpu/irq/intc-sh5.c for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) { reg 176 arch/sh/kernel/cpu/irq/intc-sh5.c __raw_writel(data, reg); reg 178 arch/sh/kernel/cpu/irq/intc-sh5.c reg += 8; reg 65 arch/sh/kernel/dwarf.c struct dwarf_reg *reg; reg 67 arch/sh/kernel/dwarf.c reg = mempool_alloc(dwarf_reg_pool, GFP_ATOMIC); reg 68 arch/sh/kernel/dwarf.c if (!reg) { reg 77 arch/sh/kernel/dwarf.c reg->number = reg_num; reg 78 arch/sh/kernel/dwarf.c reg->addr = 0; reg 79 arch/sh/kernel/dwarf.c reg->flags = 0; reg 81 arch/sh/kernel/dwarf.c list_add(®->link, &frame->reg_list); reg 83 arch/sh/kernel/dwarf.c return reg; reg 88 arch/sh/kernel/dwarf.c struct dwarf_reg *reg, *n; reg 90 arch/sh/kernel/dwarf.c list_for_each_entry_safe(reg, n, &frame->reg_list, link) { reg 91 arch/sh/kernel/dwarf.c list_del(®->link); reg 92 arch/sh/kernel/dwarf.c mempool_free(reg, dwarf_reg_pool); reg 107 arch/sh/kernel/dwarf.c struct dwarf_reg *reg; reg 109 arch/sh/kernel/dwarf.c list_for_each_entry(reg, &frame->reg_list, link) { reg 110 arch/sh/kernel/dwarf.c if (reg->number == reg_num) reg 111 arch/sh/kernel/dwarf.c return reg; reg 405 arch/sh/kernel/dwarf.c unsigned int count, delta, reg, expr_len, offset; reg 425 arch/sh/kernel/dwarf.c reg = DW_CFA_operand(insn); reg 429 arch/sh/kernel/dwarf.c regp = dwarf_frame_alloc_reg(frame, reg); reg 435 arch/sh/kernel/dwarf.c reg = DW_CFA_operand(insn); reg 462 arch/sh/kernel/dwarf.c count = dwarf_read_uleb128(current_insn, ®); reg 469 arch/sh/kernel/dwarf.c count = dwarf_read_uleb128(current_insn, ®); reg 473 arch/sh/kernel/dwarf.c count = dwarf_read_uleb128(current_insn, ®); reg 475 arch/sh/kernel/dwarf.c regp = dwarf_frame_alloc_reg(frame, reg); reg 510 arch/sh/kernel/dwarf.c count = dwarf_read_uleb128(current_insn, ®); reg 515 arch/sh/kernel/dwarf.c regp = dwarf_frame_alloc_reg(frame, reg); reg 520 arch/sh/kernel/dwarf.c count = dwarf_read_uleb128(current_insn, ®); reg 524 arch/sh/kernel/dwarf.c regp = dwarf_frame_alloc_reg(frame, reg); reg 533 arch/sh/kernel/dwarf.c count = dwarf_read_uleb128(current_insn, ®); reg 538 arch/sh/kernel/dwarf.c regp = dwarf_frame_alloc_reg(frame, reg); reg 580 arch/sh/kernel/dwarf.c struct dwarf_reg *reg; reg 671 arch/sh/kernel/dwarf.c reg = dwarf_frame_reg(prev, frame->cfa_register); reg 672 arch/sh/kernel/dwarf.c UNWINDER_BUG_ON(!reg); reg 673 arch/sh/kernel/dwarf.c UNWINDER_BUG_ON(reg->flags != DWARF_REG_OFFSET); reg 675 arch/sh/kernel/dwarf.c addr = prev->cfa + reg->addr; reg 695 arch/sh/kernel/dwarf.c reg = dwarf_frame_reg(frame, DWARF_ARCH_RA_REG); reg 702 arch/sh/kernel/dwarf.c if (!reg || reg->flags == DWARF_UNDEFINED) reg 705 arch/sh/kernel/dwarf.c UNWINDER_BUG_ON(reg->flags != DWARF_REG_OFFSET); reg 707 arch/sh/kernel/dwarf.c addr = frame->cfa + reg->addr; reg 226 arch/sh/kernel/kgdb.c int reg; reg 229 arch/sh/kernel/kgdb.c for (reg = 0; reg < DBG_MAX_REG_NUM; reg++) reg 230 arch/sh/kernel/kgdb.c gdb_regs[reg] = 0; reg 239 arch/sh/kernel/kgdb.c for (reg = GDB_R8; reg < GDB_R15; reg++) reg 240 arch/sh/kernel/kgdb.c gdb_regs[reg] = thread_regs->regs[reg]; reg 434 arch/sh/math-emu/math.c unsigned long *reg = (code & 0x0010) ? &FPUL : &FPSCR; reg 439 arch/sh/math-emu/math.c Rn = *reg; reg 443 arch/sh/math-emu/math.c *reg = Rn; reg 448 arch/sh/math-emu/math.c WRITE(*reg, Rn); reg 452 arch/sh/math-emu/math.c READ(*reg, Rn); reg 220 arch/sh/mm/init.c struct memblock_region *reg; reg 223 arch/sh/mm/init.c for_each_memblock(memory, reg) { reg 225 arch/sh/mm/init.c start_pfn = memblock_region_memory_base_pfn(reg); reg 226 arch/sh/mm/init.c end_pfn = memblock_region_memory_end_pfn(reg); reg 236 arch/sh/mm/init.c for_each_memblock(memory, reg) { reg 237 arch/sh/mm/init.c int nid = memblock_get_region_node(reg); reg 239 arch/sh/mm/init.c memory_present(nid, memblock_region_memory_base_pfn(reg), reg 240 arch/sh/mm/init.c memblock_region_memory_end_pfn(reg)); reg 49 arch/sparc/include/asm/backoff.h #define BACKOFF_SETUP(reg) \ reg 50 arch/sparc/include/asm/backoff.h mov 1, reg reg 55 arch/sparc/include/asm/backoff.h #define BACKOFF_SPIN(reg, tmp, label) \ reg 56 arch/sparc/include/asm/backoff.h mov reg, tmp; \ reg 69 arch/sparc/include/asm/backoff.h cmp reg, tmp; \ reg 73 arch/sparc/include/asm/backoff.h sllx reg, 1, reg; reg 77 arch/sparc/include/asm/backoff.h #define BACKOFF_SETUP(reg) reg 82 arch/sparc/include/asm/backoff.h #define BACKOFF_SPIN(reg, tmp, label) reg 447 arch/sparc/include/asm/floppy_64.h unsigned long reg) reg 454 arch/sparc/include/asm/floppy_64.h outb(val, reg); reg 3234 arch/sparc/include/asm/hypervisor.h unsigned long sun4v_niagara_getperf(unsigned long reg, reg 3236 arch/sparc/include/asm/hypervisor.h unsigned long sun4v_niagara_setperf(unsigned long reg, reg 3238 arch/sparc/include/asm/hypervisor.h unsigned long sun4v_niagara2_getperf(unsigned long reg, reg 3240 arch/sparc/include/asm/hypervisor.h unsigned long sun4v_niagara2_setperf(unsigned long reg, reg 57 arch/sparc/include/asm/ptrace.h struct global_reg_snapshot reg; reg 16 arch/sparc/include/asm/winmacro.h #define STORE_WINDOW(reg) \ reg 17 arch/sparc/include/asm/winmacro.h std %l0, [%reg + RW_L0]; \ reg 18 arch/sparc/include/asm/winmacro.h std %l2, [%reg + RW_L2]; \ reg 19 arch/sparc/include/asm/winmacro.h std %l4, [%reg + RW_L4]; \ reg 20 arch/sparc/include/asm/winmacro.h std %l6, [%reg + RW_L6]; \ reg 21 arch/sparc/include/asm/winmacro.h std %i0, [%reg + RW_I0]; \ reg 22 arch/sparc/include/asm/winmacro.h std %i2, [%reg + RW_I2]; \ reg 23 arch/sparc/include/asm/winmacro.h std %i4, [%reg + RW_I4]; \ reg 24 arch/sparc/include/asm/winmacro.h std %i6, [%reg + RW_I6]; reg 27 arch/sparc/include/asm/winmacro.h #define LOAD_WINDOW(reg) \ reg 28 arch/sparc/include/asm/winmacro.h ldd [%reg + RW_L0], %l0; \ reg 29 arch/sparc/include/asm/winmacro.h ldd [%reg + RW_L2], %l2; \ reg 30 arch/sparc/include/asm/winmacro.h ldd [%reg + RW_L4], %l4; \ reg 31 arch/sparc/include/asm/winmacro.h ldd [%reg + RW_L6], %l6; \ reg 32 arch/sparc/include/asm/winmacro.h ldd [%reg + RW_I0], %i0; \ reg 33 arch/sparc/include/asm/winmacro.h ldd [%reg + RW_I2], %i2; \ reg 34 arch/sparc/include/asm/winmacro.h ldd [%reg + RW_I4], %i4; \ reg 35 arch/sparc/include/asm/winmacro.h ldd [%reg + RW_I6], %i6; reg 39 arch/sparc/kernel/central.c u8 reg = upa_readb(p->clock_regs + CLOCK_STAT1) & 0xc0; reg 41 arch/sparc/kernel/central.c switch (reg) { reg 49 arch/sparc/kernel/central.c reg = 0; reg 51 arch/sparc/kernel/central.c reg = upa_readb(p->clock_ver_reg); reg 52 arch/sparc/kernel/central.c if (reg) { reg 53 arch/sparc/kernel/central.c if (reg & 0x80) reg 164 arch/sparc/kernel/central.c u32 reg; reg 183 arch/sparc/kernel/central.c reg = upa_readl(p->pregs + FHC_PREGS_BSR); reg 184 arch/sparc/kernel/central.c p->board_num = ((reg >> 16) & 1) | ((reg >> 12) & 0x0e); reg 214 arch/sparc/kernel/central.c reg = upa_readl(p->pregs + FHC_PREGS_CTRL); reg 217 arch/sparc/kernel/central.c reg |= FHC_CONTROL_IXIST; reg 219 arch/sparc/kernel/central.c reg &= ~(FHC_CONTROL_AOFF | reg 223 arch/sparc/kernel/central.c upa_writel(reg, p->pregs + FHC_PREGS_CTRL); reg 226 arch/sparc/kernel/central.c reg = upa_readl(p->pregs + FHC_PREGS_ID); reg 229 arch/sparc/kernel/central.c (reg & FHC_ID_VERS) >> 28, reg 230 arch/sparc/kernel/central.c (reg & FHC_ID_PARTID) >> 12, reg 231 arch/sparc/kernel/central.c (reg & FHC_ID_MANUF) >> 1, reg 277 arch/sparc/kernel/of_device_32.c const u32 *reg = (preg + (index * ((na + ns) * 4))); reg 286 arch/sparc/kernel/of_device_32.c size = of_read_addr(reg + na, ns); reg 288 arch/sparc/kernel/of_device_32.c memcpy(addr, reg, na * 4); reg 290 arch/sparc/kernel/of_device_32.c flags = bus->get_flags(reg, 0); reg 355 arch/sparc/kernel/of_device_64.c const u32 *reg = (preg + (index * ((na + ns) * 4))); reg 364 arch/sparc/kernel/of_device_64.c size = of_read_addr(reg + na, ns); reg 365 arch/sparc/kernel/of_device_64.c memcpy(addr, reg, na * 4); reg 429 arch/sparc/kernel/of_device_64.c const u32 *reg; reg 435 arch/sparc/kernel/of_device_64.c reg = of_get_property(dp, "reg", &num_reg); reg 436 arch/sparc/kernel/of_device_64.c if (!reg || !num_reg) reg 445 arch/sparc/kernel/of_device_64.c if ((reg[j] & imask[j]) != imap[j]) reg 547 arch/sparc/kernel/pci.c const u32 *reg; reg 560 arch/sparc/kernel/pci.c reg = of_get_property(child, "reg", ®len); reg 561 arch/sparc/kernel/pci.c if (reg == NULL || reglen < 20) reg 564 arch/sparc/kernel/pci.c devfn = (reg[0] >> 8) & 0xff; reg 22 arch/sparc/kernel/pci_common.c unsigned long reg) reg 33 arch/sparc/kernel/pci_common.c unsigned long reg) reg 37 arch/sparc/kernel/pci_common.c if (config_out_of_range(pbm, bus, devfn, reg)) reg 40 arch/sparc/kernel/pci_common.c reg = (reg & ((1 << rbits) - 1)); reg 44 arch/sparc/kernel/pci_common.c return (void *) (pbm->config_space | bus | devfn | reg); reg 211 arch/sparc/kernel/process_64.c rp = &global_cpu_snapshot[this_cpu].reg; reg 279 arch/sparc/kernel/process_64.c gp = &global_cpu_snapshot[cpu].reg; reg 58 arch/sparc/kernel/ptrace_32.c unsigned long reg; reg 63 arch/sparc/kernel/ptrace_32.c pos /= sizeof(reg); reg 64 arch/sparc/kernel/ptrace_32.c count /= sizeof(reg); reg 85 arch/sparc/kernel/ptrace_32.c if (get_user(reg, ®_window[pos++]) || reg 86 arch/sparc/kernel/ptrace_32.c put_user(reg, u++)) reg 93 arch/sparc/kernel/ptrace_32.c reg = regs->psr; reg 96 arch/sparc/kernel/ptrace_32.c reg = regs->pc; reg 99 arch/sparc/kernel/ptrace_32.c reg = regs->npc; reg 102 arch/sparc/kernel/ptrace_32.c reg = regs->y; reg 106 arch/sparc/kernel/ptrace_32.c reg = 0; reg 113 arch/sparc/kernel/ptrace_32.c *k++ = reg; reg 114 arch/sparc/kernel/ptrace_32.c else if (put_user(reg, u++)) reg 120 arch/sparc/kernel/ptrace_32.c pos *= sizeof(reg); reg 121 arch/sparc/kernel/ptrace_32.c count *= sizeof(reg); reg 124 arch/sparc/kernel/ptrace_32.c 38 * sizeof(reg), -1); reg 136 arch/sparc/kernel/ptrace_32.c unsigned long reg; reg 141 arch/sparc/kernel/ptrace_32.c pos /= sizeof(reg); reg 142 arch/sparc/kernel/ptrace_32.c count /= sizeof(reg); reg 156 arch/sparc/kernel/ptrace_32.c if (get_user(reg, u++)) reg 158 arch/sparc/kernel/ptrace_32.c regs->u_regs[pos++] = reg; reg 164 arch/sparc/kernel/ptrace_32.c if (get_user(reg, u++) || reg 165 arch/sparc/kernel/ptrace_32.c put_user(reg, ®_window[pos++])) reg 173 arch/sparc/kernel/ptrace_32.c reg = *k++; reg 174 arch/sparc/kernel/ptrace_32.c else if (get_user(reg, u++)) reg 181 arch/sparc/kernel/ptrace_32.c psr |= (reg & (PSR_ICC | PSR_SYSCALL)); reg 185 arch/sparc/kernel/ptrace_32.c regs->pc = reg; reg 188 arch/sparc/kernel/ptrace_32.c regs->npc = reg; reg 191 arch/sparc/kernel/ptrace_32.c regs->y = reg; reg 204 arch/sparc/kernel/ptrace_32.c pos *= sizeof(reg); reg 205 arch/sparc/kernel/ptrace_32.c count *= sizeof(reg); reg 208 arch/sparc/kernel/ptrace_32.c 38 * sizeof(reg), -1); reg 525 arch/sparc/kernel/ptrace_64.c compat_ulong_t reg; reg 530 arch/sparc/kernel/ptrace_64.c pos /= sizeof(reg); reg 531 arch/sparc/kernel/ptrace_64.c count /= sizeof(reg); reg 567 arch/sparc/kernel/ptrace_64.c if (get_user(reg, ®_window[pos++]) || reg 568 arch/sparc/kernel/ptrace_64.c put_user(reg, u++)) reg 576 arch/sparc/kernel/ptrace_64.c ®, sizeof(reg), reg 578 arch/sparc/kernel/ptrace_64.c != sizeof(reg)) reg 582 arch/sparc/kernel/ptrace_64.c ®, sizeof(reg), reg 584 arch/sparc/kernel/ptrace_64.c != sizeof(reg)) reg 594 arch/sparc/kernel/ptrace_64.c reg = tstate_to_psr(regs->tstate); reg 597 arch/sparc/kernel/ptrace_64.c reg = regs->tpc; reg 600 arch/sparc/kernel/ptrace_64.c reg = regs->tnpc; reg 603 arch/sparc/kernel/ptrace_64.c reg = regs->y; reg 607 arch/sparc/kernel/ptrace_64.c reg = 0; reg 614 arch/sparc/kernel/ptrace_64.c *k++ = reg; reg 615 arch/sparc/kernel/ptrace_64.c else if (put_user(reg, u++)) reg 621 arch/sparc/kernel/ptrace_64.c pos *= sizeof(reg); reg 622 arch/sparc/kernel/ptrace_64.c count *= sizeof(reg); reg 625 arch/sparc/kernel/ptrace_64.c 38 * sizeof(reg), -1); reg 637 arch/sparc/kernel/ptrace_64.c compat_ulong_t reg; reg 642 arch/sparc/kernel/ptrace_64.c pos /= sizeof(reg); reg 643 arch/sparc/kernel/ptrace_64.c count /= sizeof(reg); reg 672 arch/sparc/kernel/ptrace_64.c if (get_user(reg, u++)) reg 674 arch/sparc/kernel/ptrace_64.c regs->u_regs[pos++] = reg; reg 681 arch/sparc/kernel/ptrace_64.c if (get_user(reg, u++) || reg 682 arch/sparc/kernel/ptrace_64.c put_user(reg, ®_window[pos++])) reg 690 arch/sparc/kernel/ptrace_64.c ®, sizeof(reg), reg 692 arch/sparc/kernel/ptrace_64.c != sizeof(reg)) reg 697 arch/sparc/kernel/ptrace_64.c ®, sizeof(reg), reg 699 arch/sparc/kernel/ptrace_64.c != sizeof(reg)) reg 710 arch/sparc/kernel/ptrace_64.c reg = *k++; reg 711 arch/sparc/kernel/ptrace_64.c else if (get_user(reg, u++)) reg 718 arch/sparc/kernel/ptrace_64.c tstate |= psr_to_tstate_icc(reg); reg 719 arch/sparc/kernel/ptrace_64.c if (reg & PSR_SYSCALL) reg 724 arch/sparc/kernel/ptrace_64.c regs->tpc = reg; reg 727 arch/sparc/kernel/ptrace_64.c regs->tnpc = reg; reg 730 arch/sparc/kernel/ptrace_64.c regs->y = reg; reg 743 arch/sparc/kernel/ptrace_64.c pos *= sizeof(reg); reg 744 arch/sparc/kernel/ptrace_64.c count *= sizeof(reg); reg 747 arch/sparc/kernel/ptrace_64.c 38 * sizeof(reg), -1); reg 423 arch/sparc/kernel/sun4d_irq.c const u32 *reg; reg 437 arch/sparc/kernel/sun4d_irq.c reg = of_get_property(dp, "reg", NULL); reg 438 arch/sparc/kernel/sun4d_irq.c if (!reg) { reg 451 arch/sparc/kernel/sun4d_irq.c res.start = reg[1]; reg 452 arch/sparc/kernel/sun4d_irq.c res.end = reg[2] - 1; reg 453 arch/sparc/kernel/sun4d_irq.c res.flags = reg[0] & 0xff; reg 93 arch/sparc/kernel/unaligned_32.c static inline unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs) reg 97 arch/sparc/kernel/unaligned_32.c if(reg < 16) reg 98 arch/sparc/kernel/unaligned_32.c return (!reg ? 0 : regs->u_regs[reg]); reg 102 arch/sparc/kernel/unaligned_32.c return win->locals[reg - 16]; /* yes, I know what this does... */ reg 105 arch/sparc/kernel/unaligned_32.c static inline unsigned long safe_fetch_reg(unsigned int reg, struct pt_regs *regs) reg 110 arch/sparc/kernel/unaligned_32.c if (reg < 16) reg 111 arch/sparc/kernel/unaligned_32.c return (!reg ? 0 : regs->u_regs[reg]); reg 119 arch/sparc/kernel/unaligned_32.c if (get_user(ret, &win->locals[reg - 16])) reg 125 arch/sparc/kernel/unaligned_32.c static inline unsigned long *fetch_reg_addr(unsigned int reg, struct pt_regs *regs) reg 129 arch/sparc/kernel/unaligned_32.c if(reg < 16) reg 130 arch/sparc/kernel/unaligned_32.c return ®s->u_regs[reg]; reg 132 arch/sparc/kernel/unaligned_32.c return &win->locals[reg - 16]; reg 280 arch/sparc/kernel/unaligned_32.c unsigned int reg; reg 290 arch/sparc/kernel/unaligned_32.c reg = (insn >> 25) & 0x1f; reg 291 arch/sparc/kernel/unaligned_32.c if (reg >= 16) { reg 292 arch/sparc/kernel/unaligned_32.c if (!access_ok(WINREG_ADDR(reg - 16), size)) reg 295 arch/sparc/kernel/unaligned_32.c reg = (insn >> 14) & 0x1f; reg 296 arch/sparc/kernel/unaligned_32.c if (reg >= 16) { reg 297 arch/sparc/kernel/unaligned_32.c if (!access_ok(WINREG_ADDR(reg - 16), size)) reg 301 arch/sparc/kernel/unaligned_32.c reg = (insn & 0x1f); reg 302 arch/sparc/kernel/unaligned_32.c if (reg >= 16) { reg 303 arch/sparc/kernel/unaligned_32.c if (!access_ok(WINREG_ADDR(reg - 16), size)) reg 120 arch/sparc/kernel/unaligned_64.c static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs) reg 124 arch/sparc/kernel/unaligned_64.c if (reg < 16) reg 125 arch/sparc/kernel/unaligned_64.c return (!reg ? 0 : regs->u_regs[reg]); reg 132 arch/sparc/kernel/unaligned_64.c value = win->locals[reg - 16]; reg 136 arch/sparc/kernel/unaligned_64.c get_user(value, &win32->locals[reg - 16]); reg 140 arch/sparc/kernel/unaligned_64.c get_user(value, &win->locals[reg - 16]); reg 145 arch/sparc/kernel/unaligned_64.c static unsigned long *fetch_reg_addr(unsigned int reg, struct pt_regs *regs) reg 149 arch/sparc/kernel/unaligned_64.c if (reg < 16) reg 150 arch/sparc/kernel/unaligned_64.c return ®s->u_regs[reg]; reg 157 arch/sparc/kernel/unaligned_64.c return &win->locals[reg - 16]; reg 161 arch/sparc/kernel/unaligned_64.c return (unsigned long *)&win32->locals[reg - 16]; reg 165 arch/sparc/kernel/unaligned_64.c return &win->locals[reg - 16]; reg 574 arch/sparc/kernel/unaligned_64.c unsigned long *reg; reg 579 arch/sparc/kernel/unaligned_64.c reg = fetch_reg_addr(rd, regs); reg 581 arch/sparc/kernel/unaligned_64.c reg[0] = 0; reg 583 arch/sparc/kernel/unaligned_64.c reg[1] = 0; reg 585 arch/sparc/kernel/unaligned_64.c put_user(0, (int __user *) reg); reg 587 arch/sparc/kernel/unaligned_64.c put_user(0, ((int __user *) reg) + 1); reg 589 arch/sparc/kernel/unaligned_64.c put_user(0, (unsigned long __user *) reg); reg 591 arch/sparc/kernel/unaligned_64.c put_user(0, (unsigned long __user *) reg + 1); reg 151 arch/sparc/kernel/visemul.c static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs) reg 155 arch/sparc/kernel/visemul.c if (reg < 16) reg 156 arch/sparc/kernel/visemul.c return (!reg ? 0 : regs->u_regs[reg]); reg 163 arch/sparc/kernel/visemul.c value = win->locals[reg - 16]; reg 167 arch/sparc/kernel/visemul.c get_user(value, &win32->locals[reg - 16]); reg 171 arch/sparc/kernel/visemul.c get_user(value, &win->locals[reg - 16]); reg 176 arch/sparc/kernel/visemul.c static inline unsigned long __user *__fetch_reg_addr_user(unsigned int reg, reg 181 arch/sparc/kernel/visemul.c BUG_ON(reg < 16); reg 187 arch/sparc/kernel/visemul.c return (unsigned long __user *)&win32->locals[reg - 16]; reg 191 arch/sparc/kernel/visemul.c return &win->locals[reg - 16]; reg 195 arch/sparc/kernel/visemul.c static inline unsigned long *__fetch_reg_addr_kern(unsigned int reg, reg 198 arch/sparc/kernel/visemul.c BUG_ON(reg >= 16); reg 201 arch/sparc/kernel/visemul.c return ®s->u_regs[reg]; reg 1224 arch/sparc/mm/init_64.c struct memblock_region *reg; reg 1230 arch/sparc/mm/init_64.c for_each_memblock(memory, reg) { reg 1231 arch/sparc/mm/init_64.c unsigned long size = reg->size; reg 1234 arch/sparc/mm/init_64.c start = reg->base; reg 267 arch/sparc/net/bpf_jit_comp_64.c static void emit_set_const(s32 K, u32 reg, struct jit_ctx *ctx) reg 269 arch/sparc/net/bpf_jit_comp_64.c emit(SETHI(K, reg), ctx); reg 270 arch/sparc/net/bpf_jit_comp_64.c emit(OR_LO(K, reg), ctx); reg 274 arch/sparc/net/bpf_jit_comp_64.c static void emit_set_const_sext(s32 K, u32 reg, struct jit_ctx *ctx) reg 277 arch/sparc/net/bpf_jit_comp_64.c emit(SETHI(K, reg), ctx); reg 278 arch/sparc/net/bpf_jit_comp_64.c emit(OR_LO(K, reg), ctx); reg 283 arch/sparc/net/bpf_jit_comp_64.c emit(SETHI(hbits, reg), ctx); reg 284 arch/sparc/net/bpf_jit_comp_64.c emit(XOR | IMMED | RS1(reg) | S13(lbits) | RD(reg), ctx); reg 34 arch/sparc/prom/memory.c struct linux_prom_registers reg[64]; reg 39 arch/sparc/prom/memory.c size = prom_getproperty(node, "available", (char *) reg, sizeof(reg)); reg 43 arch/sparc/prom/memory.c sp_banks[i].base_addr = reg[i].phys_addr; reg 44 arch/sparc/prom/memory.c sp_banks[i].num_bytes = reg[i].reg_size; reg 236 arch/sparc/prom/tree_32.c struct linux_prom_registers reg[PROMREG_MAX]; reg 258 arch/sparc/prom/tree_32.c if (prom_getproperty (node2, "reg", (char *)reg, sizeof (reg)) > 0) { reg 259 arch/sparc/prom/tree_32.c if (which_io == reg[0].which_io && phys_addr == reg[0].phys_addr) { reg 100 arch/um/include/asm/processor-generic.h #define KSTK_REG(tsk, reg) get_thread_reg(reg, &tsk->thread.switch_buf) reg 22 arch/um/include/shared/registers.h extern unsigned long get_thread_reg(int reg, jmp_buf *buf); reg 97 arch/unicore32/include/asm/assembler.h .macro usracc, instr, reg, ptr, inc, cond, rept, abort reg 116 arch/unicore32/include/asm/assembler.h .macro strusr, reg, ptr, inc, cond = al, rept = 1, abort = 9001f reg 120 arch/unicore32/include/asm/assembler.h .macro ldrusr, reg, ptr, inc, cond = al, rept = 1, abort = 9001f reg 17 arch/unicore32/include/asm/cputype.h #define read_cpuid(reg) \ reg 20 arch/unicore32/include/asm/cputype.h asm("movc %0, p0.c0, #" __stringify(reg) \ reg 68 arch/unicore32/mm/init.c struct memblock_region *reg; reg 87 arch/unicore32/mm/init.c for_each_memblock(memory, reg) { reg 88 arch/unicore32/mm/init.c unsigned long start = memblock_region_memory_base_pfn(reg); reg 89 arch/unicore32/mm/init.c unsigned long end = memblock_region_memory_end_pfn(reg); reg 394 arch/unicore32/mm/mmu.c struct memblock_region *reg; reg 397 arch/unicore32/mm/mmu.c for_each_memblock(memory, reg) { reg 398 arch/unicore32/mm/mmu.c phys_addr_t start = reg->base; reg 399 arch/unicore32/mm/mmu.c phys_addr_t end = start + reg->size; reg 19 arch/x86/boot/regs.c void initregs(struct biosregs *reg) reg 21 arch/x86/boot/regs.c memset(reg, 0, sizeof(*reg)); reg 22 arch/x86/boot/regs.c reg->eflags |= X86_EFLAGS_CF; reg 23 arch/x86/boot/regs.c reg->ds = ds(); reg 24 arch/x86/boot/regs.c reg->es = ds(); reg 25 arch/x86/boot/regs.c reg->fs = fs(); reg 26 arch/x86/boot/regs.c reg->gs = gs(); reg 189 arch/x86/entry/calling.h .macro SET_NOFLUSH_BIT reg:req reg 193 arch/x86/entry/calling.h .macro ADJUST_KERNEL_CR3 reg:req reg 367 arch/x86/entry/calling.h #define GET_CR2_INTO(reg) GET_CR2_INTO_AX ; _ASM_MOV %_ASM_AX, reg reg 369 arch/x86/entry/calling.h #define GET_CR2_INTO(reg) _ASM_MOV %cr2, reg reg 244 arch/x86/events/amd/iommu.c u64 reg = 0ULL; reg 246 arch/x86/events/amd/iommu.c reg = GET_CSOURCE(hwc); reg 247 arch/x86/events/amd/iommu.c amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_COUNTER_SRC_REG, ®); reg 249 arch/x86/events/amd/iommu.c reg = GET_DEVID_MASK(hwc); reg 250 arch/x86/events/amd/iommu.c reg = GET_DEVID(hwc) | (reg << 32); reg 251 arch/x86/events/amd/iommu.c if (reg) reg 252 arch/x86/events/amd/iommu.c reg |= BIT(31); reg 253 arch/x86/events/amd/iommu.c amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DEVID_MATCH_REG, ®); reg 255 arch/x86/events/amd/iommu.c reg = GET_PASID_MASK(hwc); reg 256 arch/x86/events/amd/iommu.c reg = GET_PASID(hwc) | (reg << 32); reg 257 arch/x86/events/amd/iommu.c if (reg) reg 258 arch/x86/events/amd/iommu.c reg |= BIT(31); reg 259 arch/x86/events/amd/iommu.c amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_PASID_MATCH_REG, ®); reg 261 arch/x86/events/amd/iommu.c reg = GET_DOMID_MASK(hwc); reg 262 arch/x86/events/amd/iommu.c reg = GET_DOMID(hwc) | (reg << 32); reg 263 arch/x86/events/amd/iommu.c if (reg) reg 264 arch/x86/events/amd/iommu.c reg |= BIT(31); reg 265 arch/x86/events/amd/iommu.c amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DOMID_MATCH_REG, ®); reg 272 arch/x86/events/amd/iommu.c u64 reg = 0ULL; reg 275 arch/x86/events/amd/iommu.c IOMMU_PC_COUNTER_SRC_REG, ®); reg 116 arch/x86/events/core.c struct hw_perf_event_extra *reg; reg 119 arch/x86/events/core.c reg = &event->hw.extra_reg; reg 133 arch/x86/events/core.c reg->idx = er->idx; reg 134 arch/x86/events/core.c reg->config = event->attr.config1; reg 135 arch/x86/events/core.c reg->reg = er->msr; reg 196 arch/x86/events/core.c int i, reg, reg_fail = -1, ret = 0; reg 205 arch/x86/events/core.c reg = x86_pmu_config_addr(i); reg 206 arch/x86/events/core.c ret = rdmsrl_safe(reg, &val); reg 212 arch/x86/events/core.c reg_fail = reg; reg 219 arch/x86/events/core.c reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; reg 220 arch/x86/events/core.c ret = rdmsrl_safe(reg, &val); reg 227 arch/x86/events/core.c reg_fail = reg; reg 239 arch/x86/events/core.c reg = reg_safe; reg 248 arch/x86/events/core.c reg = x86_pmu_event_addr(reg_safe); reg 249 arch/x86/events/core.c if (rdmsrl_safe(reg, &val)) reg 252 arch/x86/events/core.c ret = wrmsrl_safe(reg, val); reg 253 arch/x86/events/core.c ret |= rdmsrl_safe(reg, &val_new); reg 274 arch/x86/events/core.c reg, val_new); reg 2624 arch/x86/events/intel/core.c event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; reg 2628 arch/x86/events/intel/core.c event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; reg 2642 arch/x86/events/intel/core.c struct hw_perf_event_extra *reg) reg 2647 arch/x86/events/intel/core.c int idx = reg->idx; reg 2654 arch/x86/events/intel/core.c if (reg->alloc && !cpuc->is_fake) reg 2665 arch/x86/events/intel/core.c if (!atomic_read(&era->ref) || era->config == reg->config) { reg 2678 arch/x86/events/intel/core.c if (idx != reg->idx) reg 2687 arch/x86/events/intel/core.c reg->alloc = 1; reg 2691 arch/x86/events/intel/core.c era->config = reg->config; reg 2692 arch/x86/events/intel/core.c era->reg = reg->reg; reg 2703 arch/x86/events/intel/core.c idx = intel_alt_er(idx, reg->config); reg 2704 arch/x86/events/intel/core.c if (idx != reg->idx) { reg 2716 arch/x86/events/intel/core.c struct hw_perf_event_extra *reg) reg 2728 arch/x86/events/intel/core.c if (!reg->alloc || cpuc->is_fake) reg 2731 arch/x86/events/intel/core.c era = &cpuc->shared_regs->regs[reg->idx]; reg 2737 arch/x86/events/intel/core.c reg->alloc = 0; reg 3091 arch/x86/events/intel/core.c struct hw_perf_event_extra *reg; reg 3093 arch/x86/events/intel/core.c reg = &event->hw.extra_reg; reg 3094 arch/x86/events/intel/core.c if (reg->idx != EXTRA_REG_NONE) reg 3095 arch/x86/events/intel/core.c __intel_shared_reg_put_constraints(cpuc, reg); reg 3097 arch/x86/events/intel/core.c reg = &event->hw.branch_reg; reg 3098 arch/x86/events/intel/core.c if (reg->idx != EXTRA_REG_NONE) reg 3099 arch/x86/events/intel/core.c __intel_shared_reg_put_constraints(cpuc, reg); reg 465 arch/x86/events/intel/lbr.c cpuc->br_sel = event->hw.branch_reg.reg; reg 747 arch/x86/events/intel/lbr.c event->hw.branch_reg.reg = mask; reg 758 arch/x86/events/intel/lbr.c struct hw_perf_event_extra *reg; reg 775 arch/x86/events/intel/lbr.c reg = &event->hw.branch_reg; reg 776 arch/x86/events/intel/lbr.c reg->idx = EXTRA_REG_LBR; reg 785 arch/x86/events/intel/lbr.c reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK); reg 790 arch/x86/events/intel/lbr.c reg->config |= LBR_NO_INFO; reg 1342 arch/x86/events/intel/p4.c int i, reg; reg 1371 arch/x86/events/intel/p4.c reg = x86_pmu_config_addr(i); reg 1372 arch/x86/events/intel/p4.c wrmsrl_safe(reg, 0ULL); reg 45 arch/x86/events/intel/pt.c .reg = _r, .mask = _m } reg 50 arch/x86/events/intel/pt.c u8 reg; reg 74 arch/x86/events/intel/pt.c u32 c = caps[cd->leaf * PT_CPUID_REGS_NUM + cd->reg]; reg 184 arch/x86/events/intel/pt.c u64 reg; reg 188 arch/x86/events/intel/pt.c rdmsrl(MSR_PLATFORM_INFO, reg); reg 189 arch/x86/events/intel/pt.c pt_pmu.max_nonturbo_ratio = (reg & 0xff00) >> 8; reg 224 arch/x86/events/intel/pt.c rdmsrl(MSR_IA32_VMX_MISC, reg); reg 225 arch/x86/events/intel/pt.c if (reg & BIT(14)) reg 472 arch/x86/events/intel/pt.c u64 reg; reg 480 arch/x86/events/intel/pt.c reg = pt_config_filters(event); reg 481 arch/x86/events/intel/pt.c reg |= RTIT_CTL_TOPA | RTIT_CTL_TRACEEN; reg 491 arch/x86/events/intel/pt.c reg |= event->attr.config & RTIT_CTL_BRANCH_EN; reg 493 arch/x86/events/intel/pt.c reg |= RTIT_CTL_BRANCH_EN; reg 497 arch/x86/events/intel/pt.c reg |= RTIT_CTL_OS; reg 499 arch/x86/events/intel/pt.c reg |= RTIT_CTL_USR; reg 501 arch/x86/events/intel/pt.c reg |= (event->attr.config & PT_CONFIG_MASK); reg 503 arch/x86/events/intel/pt.c event->hw.config = reg; reg 507 arch/x86/events/intel/pt.c wrmsrl(MSR_IA32_RTIT_CTL, reg); reg 539 arch/x86/events/intel/pt.c u64 reg; reg 543 arch/x86/events/intel/pt.c reg = 0x7f | ((u64)topa_idx << 7) | ((u64)output_off << 32); reg 545 arch/x86/events/intel/pt.c wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, reg); reg 368 arch/x86/events/intel/uncore_nhmex.c reg1->reg = NHMEX_B0_MSR_MATCH; reg 370 arch/x86/events/intel/uncore_nhmex.c reg1->reg = NHMEX_B1_MSR_MATCH; reg 384 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg, reg1->config); reg 385 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg + 1, reg2->config); reg 453 arch/x86/events/intel/uncore_nhmex.c reg1->reg = NHMEX_S0_MSR_MM_CFG; reg 455 arch/x86/events/intel/uncore_nhmex.c reg1->reg = NHMEX_S1_MSR_MM_CFG; reg 469 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg, 0); reg 470 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg + 1, reg1->config); reg 471 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg + 2, reg2->config); reg 472 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg, NHMEX_S_PMON_MM_CFG_EN); reg 795 arch/x86/events/intel/uncore_nhmex.c reg1->reg &= ~(0xffff << (reg_idx * 16)); reg 797 arch/x86/events/intel/uncore_nhmex.c reg1->reg |= msr << (reg_idx * 16); reg 812 arch/x86/events/intel/uncore_nhmex.c reg2->reg = NHMEX_M0_MSR_PMU_MM_CFG; reg 814 arch/x86/events/intel/uncore_nhmex.c reg2->reg = NHMEX_M1_MSR_PMU_MM_CFG; reg 844 arch/x86/events/intel/uncore_nhmex.c wrmsrl(__BITS_VALUE(reg1->reg, 0, 16), reg 848 arch/x86/events/intel/uncore_nhmex.c wrmsrl(__BITS_VALUE(reg1->reg, 1, 16), reg 852 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg2->reg, 0); reg 854 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg2->reg + 1, reg 856 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg2->reg + 2, NHMEX_M_PMON_ADDR_MASK_MASK & reg 858 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg2->reg, NHMEX_M_PMON_MM_CFG_EN); reg 555 arch/x86/events/intel/uncore_snbep.c wrmsrl(reg1->reg, uncore_shared_reg_config(box, 0)); reg 939 arch/x86/events/intel/uncore_snbep.c reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER + reg 1050 arch/x86/events/intel/uncore_snbep.c reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER; reg 1107 arch/x86/events/intel/uncore_snbep.c reg1->reg = SNBEP_Q_Py_PCI_PMON_PKT_MATCH0; reg 1109 arch/x86/events/intel/uncore_snbep.c reg2->reg = SNBEP_Q_Py_PCI_PMON_PKT_MASK0; reg 1128 arch/x86/events/intel/uncore_snbep.c pci_write_config_dword(filter_pdev, reg1->reg, reg 1130 arch/x86/events/intel/uncore_snbep.c pci_write_config_dword(filter_pdev, reg1->reg + 4, reg 1132 arch/x86/events/intel/uncore_snbep.c pci_write_config_dword(filter_pdev, reg2->reg, reg 1134 arch/x86/events/intel/uncore_snbep.c pci_write_config_dword(filter_pdev, reg2->reg + 4, reg 1623 arch/x86/events/intel/uncore_snbep.c reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER + reg 1638 arch/x86/events/intel/uncore_snbep.c wrmsrl(reg1->reg, filter & 0xffffffff); reg 1639 arch/x86/events/intel/uncore_snbep.c wrmsrl(reg1->reg + 6, filter >> 32); reg 2051 arch/x86/events/intel/uncore_snbep.c reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 + reg 2463 arch/x86/events/intel/uncore_snbep.c reg1->reg = HSWEP_U_MSR_PMON_FILTER; reg 2606 arch/x86/events/intel/uncore_snbep.c reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 + reg 2622 arch/x86/events/intel/uncore_snbep.c wrmsrl(reg1->reg, filter & 0xffffffff); reg 2623 arch/x86/events/intel/uncore_snbep.c wrmsrl(reg1->reg + 1, filter >> 32); reg 2717 arch/x86/events/intel/uncore_snbep.c reg1->reg = HSWEP_PCU_MSR_PMON_BOX_FILTER; reg 3499 arch/x86/events/intel/uncore_snbep.c reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 + reg 4071 arch/x86/events/intel/uncore_snbep.c reg1->reg = SNR_C0_MSR_PMON_BOX_FILTER0 + reg 4086 arch/x86/events/intel/uncore_snbep.c wrmsrl(reg1->reg, reg1->config); reg 4182 arch/x86/events/intel/uncore_snbep.c reg1->reg = SNR_PCU_MSR_PMON_BOX_FILTER; reg 137 arch/x86/events/perf_event.h u64 reg; /* extra MSR number */ reg 840 arch/x86/events/perf_event.h if (hwc->extra_reg.reg) reg 841 arch/x86/events/perf_event.h wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config); reg 56 arch/x86/hyperv/hv_apic.c static u32 hv_apic_read(u32 reg) reg 60 arch/x86/hyperv/hv_apic.c switch (reg) { reg 69 arch/x86/hyperv/hv_apic.c return native_apic_mem_read(reg); reg 73 arch/x86/hyperv/hv_apic.c static void hv_apic_write(u32 reg, u32 val) reg 75 arch/x86/hyperv/hv_apic.c switch (reg) { reg 83 arch/x86/hyperv/hv_apic.c native_apic_mem_write(reg, val); reg 87 arch/x86/hyperv/hv_apic.c static void hv_apic_eoi_write(u32 reg, u32 val) reg 28 arch/x86/include/asm/amd_nb.h extern int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo); reg 103 arch/x86/include/asm/apic.h static inline void native_apic_mem_write(u32 reg, u32 v) reg 105 arch/x86/include/asm/apic.h volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); reg 112 arch/x86/include/asm/apic.h static inline u32 native_apic_mem_read(u32 reg) reg 114 arch/x86/include/asm/apic.h return *((volatile u32 *)(APIC_BASE + reg)); reg 210 arch/x86/include/asm/apic.h static inline void native_apic_msr_write(u32 reg, u32 v) reg 212 arch/x86/include/asm/apic.h if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || reg 213 arch/x86/include/asm/apic.h reg == APIC_LVR) reg 216 arch/x86/include/asm/apic.h wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); reg 219 arch/x86/include/asm/apic.h static inline void native_apic_msr_eoi_write(u32 reg, u32 v) reg 224 arch/x86/include/asm/apic.h static inline u32 native_apic_msr_read(u32 reg) reg 228 arch/x86/include/asm/apic.h if (reg == APIC_DFR) reg 231 arch/x86/include/asm/apic.h rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); reg 292 arch/x86/include/asm/apic.h void (*eoi_write)(u32 reg, u32 v); reg 293 arch/x86/include/asm/apic.h void (*native_eoi_write)(u32 reg, u32 v); reg 294 arch/x86/include/asm/apic.h void (*write)(u32 reg, u32 v); reg 295 arch/x86/include/asm/apic.h u32 (*read)(u32 reg); reg 396 arch/x86/include/asm/apic.h static inline u32 apic_read(u32 reg) reg 398 arch/x86/include/asm/apic.h return apic->read(reg); reg 401 arch/x86/include/asm/apic.h static inline void apic_write(u32 reg, u32 val) reg 403 arch/x86/include/asm/apic.h apic->write(reg, val); reg 431 arch/x86/include/asm/apic.h extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); reg 435 arch/x86/include/asm/apic.h static inline u32 apic_read(u32 reg) { return 0; } reg 436 arch/x86/include/asm/apic.h static inline void apic_write(u32 reg, u32 val) { } reg 442 arch/x86/include/asm/apic.h static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} reg 495 arch/x86/include/asm/apic.h unsigned int reg = apic_read(APIC_ID); reg 497 arch/x86/include/asm/apic.h return apic->get_apic_id(reg); reg 21 arch/x86/include/asm/asm-prototypes.h #define INDIRECT_THUNK(reg) extern asmlinkage void __x86_indirect_thunk_e ## reg(void); reg 23 arch/x86/include/asm/asm-prototypes.h #define INDIRECT_THUNK(reg) extern asmlinkage void __x86_indirect_thunk_r ## reg(void); reg 27 arch/x86/include/asm/asm.h #define __ASM_REG(reg) __ASM_SEL_RAW(e##reg, r##reg) reg 178 arch/x86/include/asm/inst.h .macro REG_TYPE type reg reg 5 arch/x86/include/asm/intel_mid_vrtc.h extern unsigned char vrtc_cmos_read(unsigned char reg); reg 6 arch/x86/include/asm/intel_mid_vrtc.h extern void vrtc_cmos_write(unsigned char val, unsigned char reg); reg 47 arch/x86/include/asm/io.h #define build_mmio_read(name, size, type, reg, barrier) \ reg 49 arch/x86/include/asm/io.h { type ret; asm volatile("mov" size " %1,%0":reg (ret) \ reg 52 arch/x86/include/asm/io.h #define build_mmio_write(name, size, type, reg, barrier) \ reg 54 arch/x86/include/asm/io.h { asm volatile("mov" size " %0,%1": :reg (val), \ reg 185 arch/x86/include/asm/io_apic.h extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg); reg 188 arch/x86/include/asm/io_apic.h static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) reg 190 arch/x86/include/asm/io_apic.h return x86_apic_ops.io_apic_read(apic, reg); reg 96 arch/x86/include/asm/kvm_emulate.h ulong (*read_gpr)(struct x86_emulate_ctxt *ctxt, unsigned reg); reg 103 arch/x86/include/asm/kvm_emulate.h void (*write_gpr)(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val); reg 247 arch/x86/include/asm/kvm_emulate.h unsigned long *reg; reg 1059 arch/x86/include/asm/kvm_host.h void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); reg 41 arch/x86/include/asm/mc146818rtc.h static inline void lock_cmos(unsigned char reg) reg 44 arch/x86/include/asm/mc146818rtc.h new = ((smp_processor_id() + 1) << 8) | reg; reg 70 arch/x86/include/asm/mc146818rtc.h #define lock_cmos_prefix(reg) \ reg 74 arch/x86/include/asm/mc146818rtc.h lock_cmos(reg) reg 76 arch/x86/include/asm/mc146818rtc.h #define lock_cmos_suffix(reg) \ reg 81 arch/x86/include/asm/mc146818rtc.h #define lock_cmos_prefix(reg) do {} while (0) reg 82 arch/x86/include/asm/mc146818rtc.h #define lock_cmos_suffix(reg) do {} while (0) reg 83 arch/x86/include/asm/mc146818rtc.h #define lock_cmos(reg) do { } while (0) reg 53 arch/x86/include/asm/mcsafe_test.h .macro MCSAFE_TEST_SRC reg count target reg 59 arch/x86/include/asm/mcsafe_test.h .macro MCSAFE_TEST_DST reg count target reg 68 arch/x86/include/asm/mcsafe_test.h .macro MCSAFE_TEST_SRC reg count target reg 71 arch/x86/include/asm/mcsafe_test.h .macro MCSAFE_TEST_DST reg count target reg 26 arch/x86/include/asm/msr.h struct msr reg; reg 42 arch/x86/include/asm/mtrr.h extern int mtrr_del(int reg, unsigned long base, unsigned long size); reg 43 arch/x86/include/asm/mtrr.h extern int mtrr_del_page(int reg, unsigned long base, unsigned long size); reg 72 arch/x86/include/asm/mtrr.h static inline int mtrr_del(int reg, unsigned long base, unsigned long size) reg 76 arch/x86/include/asm/mtrr.h static inline int mtrr_del_page(int reg, unsigned long base, unsigned long size) reg 47 arch/x86/include/asm/nospec-branch.h #define __FILL_RETURN_BUFFER(reg, nr, sp) \ reg 48 arch/x86/include/asm/nospec-branch.h mov $(nr/2), reg; \ reg 62 arch/x86/include/asm/nospec-branch.h dec reg; \ reg 85 arch/x86/include/asm/nospec-branch.h .macro RETPOLINE_JMP reg:req reg 100 arch/x86/include/asm/nospec-branch.h .macro RETPOLINE_CALL reg:req reg 113 arch/x86/include/asm/nospec-branch.h .macro JMP_NOSPEC reg:req reg 124 arch/x86/include/asm/nospec-branch.h .macro CALL_NOSPEC reg:req reg 139 arch/x86/include/asm/nospec-branch.h .macro FILL_RETURN_BUFFER reg:req nr:req ftr:req reg 97 arch/x86/include/asm/paravirt.h static inline unsigned long paravirt_get_debugreg(int reg) reg 99 arch/x86/include/asm/paravirt.h return PVOP_CALL1(unsigned long, cpu.get_debugreg, reg); reg 101 arch/x86/include/asm/paravirt.h #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg) reg 102 arch/x86/include/asm/paravirt.h static inline void set_debugreg(unsigned long val, int reg) reg 104 arch/x86/include/asm/paravirt.h PVOP_VCALL2(cpu.set_debugreg, reg, val); reg 811 arch/x86/include/asm/paravirt.h #define COND_PUSH(set, mask, reg) \ reg 812 arch/x86/include/asm/paravirt.h .if ((~(set)) & mask); push %reg; .endif reg 813 arch/x86/include/asm/paravirt.h #define COND_POP(set, mask, reg) \ reg 814 arch/x86/include/asm/paravirt.h .if ((~(set)) & mask); pop %reg; .endif reg 22 arch/x86/include/asm/pci_64.h int reg, int len, u32 *value); reg 24 arch/x86/include/asm/pci_64.h int reg, int len, u32 value); reg 104 arch/x86/include/asm/pci_x86.h int reg, int len, u32 *val); reg 106 arch/x86/include/asm/pci_x86.h int reg, int len, u32 val); reg 28 arch/x86/include/asm/percpu.h #define PER_CPU(var, reg) \ reg 29 arch/x86/include/asm/percpu.h __percpu_mov_op %__percpu_seg:this_cpu_off, reg; \ reg 30 arch/x86/include/asm/percpu.h lea var(reg), reg reg 33 arch/x86/include/asm/percpu.h #define PER_CPU(var, reg) __percpu_mov_op $var, reg reg 8 arch/x86/include/asm/processor-cyrix.h static inline u8 getCx86(u8 reg) reg 10 arch/x86/include/asm/processor-cyrix.h outb(reg, 0x22); reg 14 arch/x86/include/asm/processor-cyrix.h static inline void setCx86(u8 reg, u8 data) reg 16 arch/x86/include/asm/processor-cyrix.h outb(reg, 0x22); reg 210 arch/x86/include/asm/processor.h #define native_cpuid_reg(reg) \ reg 211 arch/x86/include/asm/processor.h static inline unsigned int native_cpuid_##reg(unsigned int op) \ reg 217 arch/x86/include/asm/processor.h return reg; \ reg 524 arch/x86/include/asm/processor.h unsigned int reg; reg 532 arch/x86/include/asm/processor.h : "=&r" (reg) reg 295 arch/x86/include/asm/x86_init.h unsigned int (*io_apic_read) (unsigned int apic, unsigned int reg); reg 312 arch/x86/include/asm/xen/hypercall.h HYPERVISOR_set_debugreg(int reg, unsigned long value) reg 314 arch/x86/include/asm/xen/hypercall.h return _hypercall2(int, set_debugreg, reg, value); reg 318 arch/x86/include/asm/xen/hypercall.h HYPERVISOR_get_debugreg(int reg) reg 320 arch/x86/include/asm/xen/hypercall.h return _hypercall1(unsigned long, get_debugreg, reg); reg 399 arch/x86/include/asm/xen/hypercall.h HYPERVISOR_set_segment_base(int reg, unsigned long value) reg 401 arch/x86/include/asm/xen/hypercall.h return _hypercall2(int, set_segment_base, reg, value); reg 39 arch/x86/include/asm/xor_avx.h #define BLOCK(i, reg) \ reg 41 arch/x86/include/asm/xor_avx.h asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p1[i / sizeof(*p1)])); \ reg 42 arch/x86/include/asm/xor_avx.h asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ reg 44 arch/x86/include/asm/xor_avx.h asm volatile("vmovdqa %%ymm" #reg ", %0" : \ reg 66 arch/x86/include/asm/xor_avx.h #define BLOCK(i, reg) \ reg 68 arch/x86/include/asm/xor_avx.h asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p2[i / sizeof(*p2)])); \ reg 69 arch/x86/include/asm/xor_avx.h asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ reg 71 arch/x86/include/asm/xor_avx.h asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ reg 73 arch/x86/include/asm/xor_avx.h asm volatile("vmovdqa %%ymm" #reg ", %0" : \ reg 96 arch/x86/include/asm/xor_avx.h #define BLOCK(i, reg) \ reg 98 arch/x86/include/asm/xor_avx.h asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p3[i / sizeof(*p3)])); \ reg 99 arch/x86/include/asm/xor_avx.h asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ reg 101 arch/x86/include/asm/xor_avx.h asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ reg 103 arch/x86/include/asm/xor_avx.h asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ reg 105 arch/x86/include/asm/xor_avx.h asm volatile("vmovdqa %%ymm" #reg ", %0" : \ reg 129 arch/x86/include/asm/xor_avx.h #define BLOCK(i, reg) \ reg 131 arch/x86/include/asm/xor_avx.h asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p4[i / sizeof(*p4)])); \ reg 132 arch/x86/include/asm/xor_avx.h asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ reg 134 arch/x86/include/asm/xor_avx.h asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ reg 136 arch/x86/include/asm/xor_avx.h asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ reg 138 arch/x86/include/asm/xor_avx.h asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \ reg 140 arch/x86/include/asm/xor_avx.h asm volatile("vmovdqa %%ymm" #reg ", %0" : \ reg 92 arch/x86/include/uapi/asm/mtrr.h #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) reg 93 arch/x86/include/uapi/asm/mtrr.h #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) reg 17 arch/x86/kernel/acpi/cppc_msr.c int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val) reg 21 arch/x86/kernel/acpi/cppc_msr.c err = rdmsrl_safe_on_cpu(cpunum, reg->address, val); reg 23 arch/x86/kernel/acpi/cppc_msr.c u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1, reg 24 arch/x86/kernel/acpi/cppc_msr.c reg->bit_offset); reg 27 arch/x86/kernel/acpi/cppc_msr.c *val >>= reg->bit_offset; reg 32 arch/x86/kernel/acpi/cppc_msr.c int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) reg 37 arch/x86/kernel/acpi/cppc_msr.c err = rdmsrl_safe_on_cpu(cpunum, reg->address, &rd_val); reg 39 arch/x86/kernel/acpi/cppc_msr.c u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1, reg 40 arch/x86/kernel/acpi/cppc_msr.c reg->bit_offset); reg 42 arch/x86/kernel/acpi/cppc_msr.c val <<= reg->bit_offset; reg 46 arch/x86/kernel/acpi/cppc_msr.c err = wrmsrl_safe_on_cpu(cpunum, reg->address, rd_val); reg 146 arch/x86/kernel/acpi/cstate.c struct acpi_processor_cx *cx, struct acpi_power_register *reg) reg 155 arch/x86/kernel/acpi/cstate.c if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT) reg 177 arch/x86/kernel/acpi/cstate.c if ((c->x86_vendor == X86_VENDOR_INTEL) && !(reg->access_size & 0x2)) reg 181 arch/x86/kernel/amd_nb.c int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo) reg 195 arch/x86/kernel/amd_nb.c ficaa |= reg & 0x3FC; reg 396 arch/x86/kernel/amd_nb.c unsigned int reg; reg 411 arch/x86/kernel/amd_nb.c pci_read_config_dword(nb->misc, 0x1b8, ®); reg 412 arch/x86/kernel/amd_nb.c pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000); reg 422 arch/x86/kernel/amd_nb.c pci_read_config_dword(nb->link, 0x1d4, ®); reg 423 arch/x86/kernel/amd_nb.c if (reg == reset) { reg 424 arch/x86/kernel/amd_nb.c pci_read_config_dword(nb->misc, 0x1b8, ®); reg 425 arch/x86/kernel/amd_nb.c reg &= ~0x180000; reg 426 arch/x86/kernel/amd_nb.c pci_write_config_dword(nb->misc, 0x1b8, reg | ban); reg 431 arch/x86/kernel/apic/apic.c unsigned long reg = APIC_EILVTn(offset); reg 435 arch/x86/kernel/apic/apic.c old = apic_read(reg); reg 442 arch/x86/kernel/apic/apic.c smp_processor_id(), reg, offset, new, reserved); reg 450 arch/x86/kernel/apic/apic.c smp_processor_id(), reg, offset, new, old); reg 454 arch/x86/kernel/apic/apic.c apic_write(reg, new); reg 2527 arch/x86/kernel/apic/apic.c void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) reg 71 arch/x86/kernel/apic/apic_noop.c static u32 noop_apic_read(u32 reg) reg 77 arch/x86/kernel/apic/apic_noop.c static void noop_apic_write(u32 reg, u32 v) reg 286 arch/x86/kernel/apic/io_apic.c unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) reg 289 arch/x86/kernel/apic/io_apic.c writel(reg, &io_apic->index); reg 293 arch/x86/kernel/apic/io_apic.c static void io_apic_write(unsigned int apic, unsigned int reg, reg 298 arch/x86/kernel/apic/io_apic.c writel(reg, &io_apic->index); reg 1712 arch/x86/kernel/apic/io_apic.c unsigned int reg; reg 1716 arch/x86/kernel/apic/io_apic.c reg = io_apic_read(entry->apic, 0x10 + pin*2); reg 1718 arch/x86/kernel/apic/io_apic.c if (reg & IO_APIC_REDIR_REMOTE_IRR) { reg 338 arch/x86/kernel/cpu/cacheinfo.c unsigned int reg = 0; reg 340 arch/x86/kernel/cpu/cacheinfo.c pci_read_config_dword(nb->misc, 0x1BC + slot * 4, ®); reg 343 arch/x86/kernel/cpu/cacheinfo.c if (reg & (3UL << 30)) reg 344 arch/x86/kernel/cpu/cacheinfo.c return reg & 0xfff; reg 384 arch/x86/kernel/cpu/cacheinfo.c u32 reg = idx | (i << 20); reg 389 arch/x86/kernel/cpu/cacheinfo.c pci_write_config_dword(nb->misc, 0x1BC + slot * 4, reg); reg 398 arch/x86/kernel/cpu/cacheinfo.c reg |= BIT(31); reg 399 arch/x86/kernel/cpu/cacheinfo.c pci_write_config_dword(nb->misc, 0x1BC + slot * 4, reg); reg 64 arch/x86/kernel/cpu/mce/inject.c #define MCE_INJECT_SET(reg) \ reg 65 arch/x86/kernel/cpu/mce/inject.c static int inj_##reg##_set(void *data, u64 val) \ reg 69 arch/x86/kernel/cpu/mce/inject.c m->reg = val; \ reg 78 arch/x86/kernel/cpu/mce/inject.c #define MCE_INJECT_GET(reg) \ reg 79 arch/x86/kernel/cpu/mce/inject.c static int inj_##reg##_get(void *data, u64 *val) \ reg 83 arch/x86/kernel/cpu/mce/inject.c *val = m->reg; \ reg 10 arch/x86/kernel/cpu/mtrr/amd.c amd_get_mtrr(unsigned int reg, unsigned long *base, reg 17 arch/x86/kernel/cpu/mtrr/amd.c if (reg == 1) reg 60 arch/x86/kernel/cpu/mtrr/amd.c amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type) reg 72 arch/x86/kernel/cpu/mtrr/amd.c regs[reg] = 0; reg 83 arch/x86/kernel/cpu/mtrr/amd.c regs[reg] = (-size >> (15 - PAGE_SHIFT) & 0x0001FFFC) reg 58 arch/x86/kernel/cpu/mtrr/centaur.c centaur_get_mcr(unsigned int reg, unsigned long *base, reg 61 arch/x86/kernel/cpu/mtrr/centaur.c *base = centaur_mcr[reg].high >> PAGE_SHIFT; reg 62 arch/x86/kernel/cpu/mtrr/centaur.c *size = -(centaur_mcr[reg].low & 0xfffff000) >> PAGE_SHIFT; reg 65 arch/x86/kernel/cpu/mtrr/centaur.c if (centaur_mcr_type == 1 && ((centaur_mcr[reg].low & 31) & 2)) reg 67 arch/x86/kernel/cpu/mtrr/centaur.c if (centaur_mcr_type == 1 && (centaur_mcr[reg].low & 31) == 25) reg 69 arch/x86/kernel/cpu/mtrr/centaur.c if (centaur_mcr_type == 0 && (centaur_mcr[reg].low & 31) == 31) reg 74 arch/x86/kernel/cpu/mtrr/centaur.c centaur_set_mcr(unsigned int reg, unsigned long base, reg 94 arch/x86/kernel/cpu/mtrr/centaur.c centaur_mcr[reg].high = high; reg 95 arch/x86/kernel/cpu/mtrr/centaur.c centaur_mcr[reg].low = low; reg 96 arch/x86/kernel/cpu/mtrr/centaur.c wrmsr(MSR_IDT_MCR0 + reg, low, high); reg 47 arch/x86/kernel/cpu/mtrr/cleanup.c unsigned int reg; reg 175 arch/x86/kernel/cpu/mtrr/cleanup.c set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek, reg 182 arch/x86/kernel/cpu/mtrr/cleanup.c fill_mtrr_var_range(reg, 0, 0, 0, 0); reg 200 arch/x86/kernel/cpu/mtrr/cleanup.c fill_mtrr_var_range(reg, base_lo, base_hi, mask_lo, mask_hi); reg 204 arch/x86/kernel/cpu/mtrr/cleanup.c save_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek, reg 207 arch/x86/kernel/cpu/mtrr/cleanup.c range_state[reg].base_pfn = basek >> (PAGE_SHIFT - 10); reg 208 arch/x86/kernel/cpu/mtrr/cleanup.c range_state[reg].size_pfn = sizek >> (PAGE_SHIFT - 10); reg 209 arch/x86/kernel/cpu/mtrr/cleanup.c range_state[reg].type = type; reg 216 arch/x86/kernel/cpu/mtrr/cleanup.c unsigned int reg; reg 218 arch/x86/kernel/cpu/mtrr/cleanup.c for (reg = 0; reg < num_var_ranges; reg++) { reg 219 arch/x86/kernel/cpu/mtrr/cleanup.c basek = range_state[reg].base_pfn << (PAGE_SHIFT - 10); reg 220 arch/x86/kernel/cpu/mtrr/cleanup.c sizek = range_state[reg].size_pfn << (PAGE_SHIFT - 10); reg 221 arch/x86/kernel/cpu/mtrr/cleanup.c type = range_state[reg].type; reg 223 arch/x86/kernel/cpu/mtrr/cleanup.c set_var_mtrr(reg, basek, sizek, type, address_bits); reg 249 arch/x86/kernel/cpu/mtrr/cleanup.c range_to_mtrr(unsigned int reg, unsigned long range_startk, reg 252 arch/x86/kernel/cpu/mtrr/cleanup.c if (!range_sizek || (reg >= num_var_ranges)) reg 253 arch/x86/kernel/cpu/mtrr/cleanup.c return reg; reg 279 arch/x86/kernel/cpu/mtrr/cleanup.c reg, start_base, start_factor, reg 285 arch/x86/kernel/cpu/mtrr/cleanup.c save_var_mtrr(reg++, range_startk, sizek, type); reg 288 arch/x86/kernel/cpu/mtrr/cleanup.c if (reg >= num_var_ranges) reg 291 arch/x86/kernel/cpu/mtrr/cleanup.c return reg; reg 335 arch/x86/kernel/cpu/mtrr/cleanup.c state->reg = range_to_mtrr(state->reg, range0_basek, reg 380 arch/x86/kernel/cpu/mtrr/cleanup.c state->reg = range_to_mtrr(state->reg, range0_basek, reg 392 arch/x86/kernel/cpu/mtrr/cleanup.c state->reg = range_to_mtrr(state->reg, range_basek, reg 401 arch/x86/kernel/cpu/mtrr/cleanup.c state->reg = range_to_mtrr(state->reg, hole_basek, reg 415 arch/x86/kernel/cpu/mtrr/cleanup.c if (state->reg >= num_var_ranges) reg 482 arch/x86/kernel/cpu/mtrr/cleanup.c var_state.reg = 0; reg 498 arch/x86/kernel/cpu/mtrr/cleanup.c num_reg = var_state.reg; reg 500 arch/x86/kernel/cpu/mtrr/cleanup.c while (var_state.reg < num_var_ranges) { reg 501 arch/x86/kernel/cpu/mtrr/cleanup.c save_var_mtrr(var_state.reg, 0, 0, 0); reg 502 arch/x86/kernel/cpu/mtrr/cleanup.c var_state.reg++; reg 14 arch/x86/kernel/cpu/mtrr/cyrix.c cyrix_get_arr(unsigned int reg, unsigned long *base, reg 20 arch/x86/kernel/cpu/mtrr/cyrix.c arr = CX86_ARR_BASE + (reg << 1) + reg; /* avoid multiplication by 3 */ reg 29 arch/x86/kernel/cpu/mtrr/cyrix.c rcr = getCx86(CX86_RCR_BASE + reg); reg 42 arch/x86/kernel/cpu/mtrr/cyrix.c *size = (reg < 7 ? 0x1UL : 0x40UL) << (shift - 1); reg 47 arch/x86/kernel/cpu/mtrr/cyrix.c if (reg < 7) { reg 179 arch/x86/kernel/cpu/mtrr/cyrix.c static void cyrix_set_arr(unsigned int reg, unsigned long base, reg 184 arch/x86/kernel/cpu/mtrr/cyrix.c arr = CX86_ARR_BASE + (reg << 1) + reg; /* avoid multiplication by 3 */ reg 187 arch/x86/kernel/cpu/mtrr/cyrix.c if (reg >= 7) reg 194 arch/x86/kernel/cpu/mtrr/cyrix.c if (reg < 7) { reg 232 arch/x86/kernel/cpu/mtrr/cyrix.c setCx86(CX86_RCR_BASE + reg, arr_type); reg 579 arch/x86/kernel/cpu/mtrr/generic.c static void generic_get_mtrr(unsigned int reg, unsigned long *base, reg 592 arch/x86/kernel/cpu/mtrr/generic.c rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); reg 602 arch/x86/kernel/cpu/mtrr/generic.c rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi); reg 831 arch/x86/kernel/cpu/mtrr/generic.c static void generic_set_mtrr(unsigned int reg, unsigned long base, reg 837 arch/x86/kernel/cpu/mtrr/generic.c vr = &mtrr_state.var_ranges[reg]; reg 847 arch/x86/kernel/cpu/mtrr/generic.c mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0); reg 855 arch/x86/kernel/cpu/mtrr/generic.c mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi); reg 856 arch/x86/kernel/cpu/mtrr/generic.c mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi); reg 42 arch/x86/kernel/cpu/mtrr/if.c int reg, max; reg 57 arch/x86/kernel/cpu/mtrr/if.c reg = mtrr_add_page(base, size, type, true); reg 58 arch/x86/kernel/cpu/mtrr/if.c if (reg >= 0) reg 59 arch/x86/kernel/cpu/mtrr/if.c ++fcount[reg]; reg 60 arch/x86/kernel/cpu/mtrr/if.c return reg; reg 68 arch/x86/kernel/cpu/mtrr/if.c int reg; reg 76 arch/x86/kernel/cpu/mtrr/if.c reg = mtrr_del_page(-1, base, size); reg 77 arch/x86/kernel/cpu/mtrr/if.c if (reg < 0) reg 78 arch/x86/kernel/cpu/mtrr/if.c return reg; reg 80 arch/x86/kernel/cpu/mtrr/if.c return reg; reg 81 arch/x86/kernel/cpu/mtrr/if.c if (fcount[reg] < 1) reg 83 arch/x86/kernel/cpu/mtrr/if.c --fcount[reg]; reg 84 arch/x86/kernel/cpu/mtrr/if.c return reg; reg 97 arch/x86/kernel/cpu/mtrr/if.c unsigned long reg; reg 120 arch/x86/kernel/cpu/mtrr/if.c reg = simple_strtoul(line + 8, &ptr, 0); reg 121 arch/x86/kernel/cpu/mtrr/if.c err = mtrr_del_page(reg, 0, 0); reg 80 arch/x86/kernel/cpu/mtrr/mtrr.c static void set_mtrr(unsigned int reg, unsigned long base, reg 230 arch/x86/kernel/cpu/mtrr/mtrr.c set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type) reg 232 arch/x86/kernel/cpu/mtrr/mtrr.c struct set_mtrr_data data = { .smp_reg = reg, reg 241 arch/x86/kernel/cpu/mtrr/mtrr.c static void set_mtrr_cpuslocked(unsigned int reg, unsigned long base, reg 244 arch/x86/kernel/cpu/mtrr/mtrr.c struct set_mtrr_data data = { .smp_reg = reg, reg 253 arch/x86/kernel/cpu/mtrr/mtrr.c static void set_mtrr_from_inactive_cpu(unsigned int reg, unsigned long base, reg 256 arch/x86/kernel/cpu/mtrr/mtrr.c struct set_mtrr_data data = { .smp_reg = reg, reg 478 arch/x86/kernel/cpu/mtrr/mtrr.c int mtrr_del_page(int reg, unsigned long base, unsigned long size) reg 492 arch/x86/kernel/cpu/mtrr/mtrr.c if (reg < 0) { reg 497 arch/x86/kernel/cpu/mtrr/mtrr.c reg = i; reg 501 arch/x86/kernel/cpu/mtrr/mtrr.c if (reg < 0) { reg 507 arch/x86/kernel/cpu/mtrr/mtrr.c if (reg >= max) { reg 508 arch/x86/kernel/cpu/mtrr/mtrr.c pr_warn("register: %d too big\n", reg); reg 511 arch/x86/kernel/cpu/mtrr/mtrr.c mtrr_if->get(reg, &lbase, &lsize, <ype); reg 513 arch/x86/kernel/cpu/mtrr/mtrr.c pr_warn("MTRR %d not used\n", reg); reg 516 arch/x86/kernel/cpu/mtrr/mtrr.c if (mtrr_usage_table[reg] < 1) { reg 517 arch/x86/kernel/cpu/mtrr/mtrr.c pr_warn("reg: %d has count=0\n", reg); reg 520 arch/x86/kernel/cpu/mtrr/mtrr.c if (--mtrr_usage_table[reg] < 1) reg 521 arch/x86/kernel/cpu/mtrr/mtrr.c set_mtrr_cpuslocked(reg, 0, 0, 0); reg 522 arch/x86/kernel/cpu/mtrr/mtrr.c error = reg; reg 543 arch/x86/kernel/cpu/mtrr/mtrr.c int mtrr_del(int reg, unsigned long base, unsigned long size) reg 549 arch/x86/kernel/cpu/mtrr/mtrr.c return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT); reg 18 arch/x86/kernel/cpu/mtrr/mtrr.h void (*set)(unsigned int reg, unsigned long base, reg 22 arch/x86/kernel/cpu/mtrr/mtrr.h void (*get)(unsigned int reg, unsigned long *base, reg 15 arch/x86/kernel/cpu/scattered.c u8 reg; reg 65 arch/x86/kernel/cpu/scattered.c if (regs[cb->reg] & (1 << cb->bit)) reg 616 arch/x86/kernel/early-quirks.c #define bcma_aread32(reg) ioread32(mmio + 1 * BCMA_CORE_SIZE + reg) reg 617 arch/x86/kernel/early-quirks.c #define bcma_awrite32(reg, val) iowrite32(val, mmio + 1 * BCMA_CORE_SIZE + reg) reg 295 arch/x86/kernel/kvm.c static notrace void kvm_guest_apic_eoi_write(u32 reg, u32 val) reg 120 arch/x86/kernel/mmconf-fam10h_64.c u32 reg; reg 123 arch/x86/kernel/mmconf-fam10h_64.c reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3)); reg 124 arch/x86/kernel/mmconf-fam10h_64.c if (!(reg & 3)) reg 127 arch/x86/kernel/mmconf-fam10h_64.c start = (u64)(reg & 0xffffff00) << 8; /* 39:16 on 31:8*/ reg 128 arch/x86/kernel/mmconf-fam10h_64.c reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3)); reg 129 arch/x86/kernel/mmconf-fam10h_64.c end = ((u64)(reg & 0xffffff00) << 8) | 0xffff; /* 39:16 on 31:8*/ reg 50 arch/x86/kernel/msr.c u32 reg = *ppos; reg 59 arch/x86/kernel/msr.c err = rdmsr_safe_on_cpu(cpu, reg, &data[0], &data[1]); reg 78 arch/x86/kernel/msr.c u32 reg = *ppos; reg 95 arch/x86/kernel/msr.c err = wrmsr_safe_on_cpu(cpu, reg, data[0], data[1]); reg 396 arch/x86/kernel/unwind_orc.c unsigned int reg = reg_off/8; reg 402 arch/x86/kernel/unwind_orc.c *val = ((unsigned long *)state->regs)[reg]; reg 407 arch/x86/kernel/unwind_orc.c *val = ((unsigned long *)state->prev_regs)[reg]; reg 337 arch/x86/kernel/uprobes.c u8 reg; reg 412 arch/x86/kernel/uprobes.c reg = MODRM_REG(insn); /* Fetch modrm.reg */ reg 430 arch/x86/kernel/uprobes.c if (reg != 6 && reg2 != 6) { reg 433 arch/x86/kernel/uprobes.c } else if (reg != 7 && reg2 != 7) { reg 452 arch/x86/kernel/uprobes.c *cursor = 0x80 | (reg << 3) | reg2; reg 38 arch/x86/kvm/cpuid.h int reg; reg 77 arch/x86/kvm/cpuid.h switch (cpuid.reg) { reg 94 arch/x86/kvm/cpuid.h int *reg; reg 100 arch/x86/kvm/cpuid.h reg = guest_cpuid_get_register(vcpu, x86_feature); reg 101 arch/x86/kvm/cpuid.h if (!reg) reg 104 arch/x86/kvm/cpuid.h return *reg & bit(x86_feature); reg 109 arch/x86/kvm/cpuid.h int *reg; reg 111 arch/x86/kvm/cpuid.h reg = guest_cpuid_get_register(vcpu, x86_feature); reg 112 arch/x86/kvm/cpuid.h if (reg) reg 113 arch/x86/kvm/cpuid.h *reg &= ~bit(x86_feature); reg 289 arch/x86/kvm/emulate.c unsigned reg; reg 291 arch/x86/kvm/emulate.c for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16) reg 292 arch/x86/kvm/emulate.c ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]); reg 520 arch/x86/kvm/emulate.c static void assign_register(unsigned long *reg, u64 val, int bytes) reg 525 arch/x86/kvm/emulate.c *(u8 *)reg = (u8)val; reg 528 arch/x86/kvm/emulate.c *(u16 *)reg = (u16)val; reg 531 arch/x86/kvm/emulate.c *reg = (u32)val; reg 534 arch/x86/kvm/emulate.c *reg = val; reg 562 arch/x86/kvm/emulate.c address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) reg 565 arch/x86/kvm/emulate.c return reg; reg 567 arch/x86/kvm/emulate.c return reg & ad_mask(ctxt); reg 571 arch/x86/kvm/emulate.c register_address(struct x86_emulate_ctxt *ctxt, int reg) reg 573 arch/x86/kvm/emulate.c return address_mask(ctxt, reg_read(ctxt, reg)); reg 576 arch/x86/kvm/emulate.c static void masked_increment(ulong *reg, ulong mask, int inc) reg 578 arch/x86/kvm/emulate.c assign_masked(reg, *reg + inc, mask); reg 582 arch/x86/kvm/emulate.c register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc) reg 584 arch/x86/kvm/emulate.c ulong *preg = reg_rmw(ctxt, reg); reg 1065 arch/x86/kvm/emulate.c op->val = *(u8 *)op->addr.reg; reg 1068 arch/x86/kvm/emulate.c op->val = *(u16 *)op->addr.reg; reg 1071 arch/x86/kvm/emulate.c op->val = *(u32 *)op->addr.reg; reg 1074 arch/x86/kvm/emulate.c op->val = *(u64 *)op->addr.reg; reg 1093 arch/x86/kvm/emulate.c static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) reg 1096 arch/x86/kvm/emulate.c switch (reg) { reg 1121 arch/x86/kvm/emulate.c int reg) reg 1124 arch/x86/kvm/emulate.c switch (reg) { reg 1148 arch/x86/kvm/emulate.c static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) reg 1151 arch/x86/kvm/emulate.c switch (reg) { reg 1165 arch/x86/kvm/emulate.c static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) reg 1168 arch/x86/kvm/emulate.c switch (reg) { reg 1228 arch/x86/kvm/emulate.c unsigned reg = ctxt->modrm_reg; reg 1231 arch/x86/kvm/emulate.c reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); reg 1236 arch/x86/kvm/emulate.c op->addr.xmm = reg; reg 1237 arch/x86/kvm/emulate.c read_sse_reg(ctxt, &op->vec_val, reg); reg 1241 arch/x86/kvm/emulate.c reg &= 7; reg 1244 arch/x86/kvm/emulate.c op->addr.mm = reg; reg 1250 arch/x86/kvm/emulate.c op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp); reg 1282 arch/x86/kvm/emulate.c op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, reg 1836 arch/x86/kvm/emulate.c return assign_register(op->addr.reg, op->val, op->bytes); reg 1963 arch/x86/kvm/emulate.c ctxt->dst.addr.reg = &ctxt->eflags; reg 2033 arch/x86/kvm/emulate.c int reg = VCPU_REGS_RAX; reg 2035 arch/x86/kvm/emulate.c while (reg <= VCPU_REGS_RDI) { reg 2036 arch/x86/kvm/emulate.c (reg == VCPU_REGS_RSP) ? reg 2037 arch/x86/kvm/emulate.c (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); reg 2043 arch/x86/kvm/emulate.c ++reg; reg 2058 arch/x86/kvm/emulate.c int reg = VCPU_REGS_RDI; reg 2061 arch/x86/kvm/emulate.c while (reg >= VCPU_REGS_RAX) { reg 2062 arch/x86/kvm/emulate.c if (reg == VCPU_REGS_RSP) { reg 2064 arch/x86/kvm/emulate.c --reg; reg 2070 arch/x86/kvm/emulate.c assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes); reg 2071 arch/x86/kvm/emulate.c --reg; reg 2353 arch/x86/kvm/emulate.c ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); reg 3429 arch/x86/kvm/emulate.c static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg, reg 3434 arch/x86/kvm/emulate.c register_address_increment(ctxt, reg, df * op->bytes); reg 3435 arch/x86/kvm/emulate.c op->addr.mem.ea = register_address(ctxt, reg); reg 3609 arch/x86/kvm/emulate.c ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); reg 5044 arch/x86/kvm/emulate.c op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); reg 5051 arch/x86/kvm/emulate.c op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); reg 5062 arch/x86/kvm/emulate.c op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); reg 5078 arch/x86/kvm/emulate.c op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); reg 5103 arch/x86/kvm/emulate.c ctxt->memop.addr.reg = decode_register(ctxt, reg 5730 arch/x86/kvm/emulate.c if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX)) reg 41 arch/x86/kvm/kvm_cache_regs.h enum kvm_reg reg) reg 43 arch/x86/kvm/kvm_cache_regs.h if (!test_bit(reg, (unsigned long *)&vcpu->arch.regs_avail)) reg 44 arch/x86/kvm/kvm_cache_regs.h kvm_x86_ops->cache_reg(vcpu, reg); reg 46 arch/x86/kvm/kvm_cache_regs.h return vcpu->arch.regs[reg]; reg 50 arch/x86/kvm/kvm_cache_regs.h enum kvm_reg reg, reg 53 arch/x86/kvm/kvm_cache_regs.h vcpu->arch.regs[reg] = val; reg 54 arch/x86/kvm/kvm_cache_regs.h __set_bit(reg, (unsigned long *)&vcpu->arch.regs_dirty); reg 55 arch/x86/kvm/kvm_cache_regs.h __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); reg 359 arch/x86/kvm/lapic.c u32 *reg; reg 363 arch/x86/kvm/lapic.c reg = bitmap + REG_POS(vec); reg 364 arch/x86/kvm/lapic.c if (*reg) reg 365 arch/x86/kvm/lapic.c return __fls(*reg) + vec; reg 374 arch/x86/kvm/lapic.c u32 *reg; reg 378 arch/x86/kvm/lapic.c reg = bitmap + REG_POS(vec); reg 379 arch/x86/kvm/lapic.c count += hweight32(*reg); reg 1297 arch/x86/kvm/lapic.c #define APIC_REG_MASK(reg) (1ull << ((reg) >> 4)) reg 1443 arch/x86/kvm/lapic.c u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT); reg 1446 arch/x86/kvm/lapic.c int vec = reg & APIC_VECTOR_MASK; reg 1850 arch/x86/kvm/lapic.c int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) reg 1854 arch/x86/kvm/lapic.c trace_kvm_apic_write(reg, val); reg 1856 arch/x86/kvm/lapic.c switch (reg) { reg 1937 arch/x86/kvm/lapic.c (reg - APIC_LVTT) >> 4, size); reg 1939 arch/x86/kvm/lapic.c kvm_lapic_set_reg(apic, reg, val); reg 2240 arch/x86/kvm/lapic.c u32 reg = kvm_lapic_get_reg(apic, lvt_type); reg 2243 arch/x86/kvm/lapic.c if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { reg 2244 arch/x86/kvm/lapic.c vector = reg & APIC_VECTOR_MASK; reg 2245 arch/x86/kvm/lapic.c mode = reg & APIC_MODE_MASK; reg 2246 arch/x86/kvm/lapic.c trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; reg 2612 arch/x86/kvm/lapic.c u32 reg = (msr - APIC_BASE_MSR) << 4; reg 2617 arch/x86/kvm/lapic.c if (reg == APIC_ICR2) reg 2621 arch/x86/kvm/lapic.c if (reg == APIC_ICR) reg 2623 arch/x86/kvm/lapic.c return kvm_lapic_reg_write(apic, reg, (u32)data); reg 2629 arch/x86/kvm/lapic.c u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0; reg 2634 arch/x86/kvm/lapic.c if (reg == APIC_DFR || reg == APIC_ICR2) reg 2637 arch/x86/kvm/lapic.c if (kvm_lapic_reg_read(apic, reg, 4, &low)) reg 2639 arch/x86/kvm/lapic.c if (reg == APIC_ICR) reg 2647 arch/x86/kvm/lapic.c int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) reg 2655 arch/x86/kvm/lapic.c if (reg == APIC_ICR) reg 2657 arch/x86/kvm/lapic.c return kvm_lapic_reg_write(apic, reg, (u32)data); reg 2660 arch/x86/kvm/lapic.c int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) reg 2668 arch/x86/kvm/lapic.c if (kvm_lapic_reg_read(apic, reg, 4, &low)) reg 2670 arch/x86/kvm/lapic.c if (reg == APIC_ICR) reg 81 arch/x86/kvm/lapic.h int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val); reg 2411 arch/x86/kvm/svm.c static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) reg 2413 arch/x86/kvm/svm.c switch (reg) { reg 4031 arch/x86/kvm/svm.c int reg, cr; reg 4041 arch/x86/kvm/svm.c reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; reg 4050 arch/x86/kvm/svm.c val = kvm_register_read(&svm->vcpu, reg); reg 4095 arch/x86/kvm/svm.c kvm_register_write(&svm->vcpu, reg, val); reg 4102 arch/x86/kvm/svm.c int reg, dr; reg 4119 arch/x86/kvm/svm.c reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK; reg 4125 arch/x86/kvm/svm.c val = kvm_register_read(&svm->vcpu, reg); reg 4131 arch/x86/kvm/svm.c kvm_register_write(&svm->vcpu, reg, val); reg 195 arch/x86/kvm/trace.h TP_PROTO(unsigned int rw, unsigned int reg, unsigned int val), reg 196 arch/x86/kvm/trace.h TP_ARGS(rw, reg, val), reg 200 arch/x86/kvm/trace.h __field( unsigned int, reg ) reg 206 arch/x86/kvm/trace.h __entry->reg = reg; reg 212 arch/x86/kvm/trace.h __print_symbolic(__entry->reg, kvm_trace_symbol_apic), reg 216 arch/x86/kvm/trace.h #define trace_kvm_apic_read(reg, val) trace_kvm_apic(0, reg, val) reg 217 arch/x86/kvm/trace.h #define trace_kvm_apic_write(reg, val) trace_kvm_apic(1, reg, val) reg 5221 arch/x86/kvm/vmx/nested.c int reg; reg 5226 arch/x86/kvm/vmx/nested.c reg = (exit_qualification >> 8) & 15; reg 5227 arch/x86/kvm/vmx/nested.c val = kvm_register_readl(vcpu, reg); reg 2164 arch/x86/kvm/vmx/vmx.c static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) reg 2166 arch/x86/kvm/vmx/vmx.c __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); reg 2167 arch/x86/kvm/vmx/vmx.c switch (reg) { reg 4805 arch/x86/kvm/vmx/vmx.c int reg; reg 4811 arch/x86/kvm/vmx/vmx.c reg = (exit_qualification >> 8) & 15; reg 4814 arch/x86/kvm/vmx/vmx.c val = kvm_register_readl(vcpu, reg); reg 4856 arch/x86/kvm/vmx/vmx.c kvm_register_write(vcpu, reg, val); reg 4861 arch/x86/kvm/vmx/vmx.c kvm_register_write(vcpu, reg, val); reg 4884 arch/x86/kvm/vmx/vmx.c int dr, dr7, reg; reg 4930 arch/x86/kvm/vmx/vmx.c reg = DEBUG_REG_ACCESS_REG(exit_qualification); reg 4936 arch/x86/kvm/vmx/vmx.c kvm_register_write(vcpu, reg, val); reg 4938 arch/x86/kvm/vmx/vmx.c if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) reg 6241 arch/x86/kvm/x86.c static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) reg 6243 arch/x86/kvm/x86.c return kvm_register_read(emul_to_vcpu(ctxt), reg); reg 6246 arch/x86/kvm/x86.c static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) reg 6248 arch/x86/kvm/x86.c kvm_register_write(emul_to_vcpu(ctxt), reg, val); reg 242 arch/x86/kvm/x86.h enum kvm_reg reg) reg 244 arch/x86/kvm/x86.h unsigned long val = kvm_register_read(vcpu, reg); reg 250 arch/x86/kvm/x86.h enum kvm_reg reg, reg 255 arch/x86/kvm/x86.h return kvm_register_write(vcpu, reg, val); reg 11 arch/x86/lib/msr-smp.c struct msr *reg; reg 15 arch/x86/lib/msr-smp.c reg = per_cpu_ptr(rv->msrs, this_cpu); reg 17 arch/x86/lib/msr-smp.c reg = &rv->reg; reg 19 arch/x86/lib/msr-smp.c rdmsr(rv->msr_no, reg->l, reg->h); reg 25 arch/x86/lib/msr-smp.c struct msr *reg; reg 29 arch/x86/lib/msr-smp.c reg = per_cpu_ptr(rv->msrs, this_cpu); reg 31 arch/x86/lib/msr-smp.c reg = &rv->reg; reg 33 arch/x86/lib/msr-smp.c wrmsr(rv->msr_no, reg->l, reg->h); reg 45 arch/x86/lib/msr-smp.c *l = rv.reg.l; reg 46 arch/x86/lib/msr-smp.c *h = rv.reg.h; reg 61 arch/x86/lib/msr-smp.c *q = rv.reg.q; reg 75 arch/x86/lib/msr-smp.c rv.reg.l = l; reg 76 arch/x86/lib/msr-smp.c rv.reg.h = h; reg 91 arch/x86/lib/msr-smp.c rv.reg.q = q; reg 158 arch/x86/lib/msr-smp.c rv->msr.err = rdmsr_safe(rv->msr.msr_no, &rv->msr.reg.l, &rv->msr.reg.h); reg 166 arch/x86/lib/msr-smp.c rv->err = wrmsr_safe(rv->msr_no, rv->reg.l, rv->reg.h); reg 187 arch/x86/lib/msr-smp.c *l = rv.msr.reg.l; reg 188 arch/x86/lib/msr-smp.c *h = rv.msr.reg.h; reg 202 arch/x86/lib/msr-smp.c rv.reg.l = l; reg 203 arch/x86/lib/msr-smp.c rv.reg.h = h; reg 218 arch/x86/lib/msr-smp.c rv.reg.q = q; reg 62 arch/x86/mm/amdtopology.c u32 nodeid, reg; reg 74 arch/x86/mm/amdtopology.c reg = read_pci_config(0, nb, 0, 0x60); reg 75 arch/x86/mm/amdtopology.c numnodes = ((reg >> 4) & 0xF) + 1; reg 397 arch/x86/mm/pf_in.c int reg; reg 420 arch/x86/mm/pf_in.c reg = arg_AX; reg 423 arch/x86/mm/pf_in.c reg = ((mod_rm >> 3) & 0x7) | (prf.rexr << 3); reg 427 arch/x86/mm/pf_in.c return *get_reg_w8(reg, prf.rex, regs); reg 430 arch/x86/mm/pf_in.c return *(unsigned short *)get_reg_w32(reg, regs); reg 433 arch/x86/mm/pf_in.c return *(unsigned int *)get_reg_w32(reg, regs); reg 437 arch/x86/mm/pf_in.c return *(unsigned long *)get_reg_w32(reg, regs); reg 441 arch/x86/mm/pf_in.c printk(KERN_ERR "mmiotrace: Error width# %d\n", reg); reg 131 arch/x86/net/bpf_jit_comp.c static bool is_ereg(u32 reg) reg 133 arch/x86/net/bpf_jit_comp.c return (1 << reg) & (BIT(BPF_REG_5) | reg 146 arch/x86/net/bpf_jit_comp.c static bool is_ereg_8l(u32 reg) reg 148 arch/x86/net/bpf_jit_comp.c return is_ereg(reg) || reg 149 arch/x86/net/bpf_jit_comp.c (1 << reg) & (BIT(BPF_REG_1) | reg 154 arch/x86/net/bpf_jit_comp.c static bool is_axreg(u32 reg) reg 156 arch/x86/net/bpf_jit_comp.c return reg == BPF_REG_0; reg 160 arch/x86/net/bpf_jit_comp.c static u8 add_1mod(u8 byte, u32 reg) reg 162 arch/x86/net/bpf_jit_comp.c if (is_ereg(reg)) reg 70 arch/x86/pci/amd_bus.c u32 reg; reg 117 arch/x86/pci/amd_bus.c reg = read_pci_config(bus, slot, 1, reg 121 arch/x86/pci/amd_bus.c if ((reg & 7) != 3) reg 124 arch/x86/pci/amd_bus.c min_bus = (reg >> 16) & 0xff; reg 125 arch/x86/pci/amd_bus.c max_bus = (reg >> 24) & 0xff; reg 126 arch/x86/pci/amd_bus.c node = (reg >> 4) & 0x07; reg 127 arch/x86/pci/amd_bus.c link = (reg >> 8) & 0x03; reg 144 arch/x86/pci/amd_bus.c reg = read_pci_config(bus, slot, 0, AMD_NB_F0_NODE_ID); reg 145 arch/x86/pci/amd_bus.c def_node = (reg >> 8) & 0x07; reg 146 arch/x86/pci/amd_bus.c reg = read_pci_config(bus, slot, 0, AMD_NB_F0_UNIT_ID); reg 147 arch/x86/pci/amd_bus.c def_link = (reg >> 8) & 0x03; reg 153 arch/x86/pci/amd_bus.c reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3)); reg 154 arch/x86/pci/amd_bus.c if (!(reg & 3)) reg 157 arch/x86/pci/amd_bus.c start = reg & 0xfff000; reg 158 arch/x86/pci/amd_bus.c reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3)); reg 159 arch/x86/pci/amd_bus.c node = reg & 0x07; reg 160 arch/x86/pci/amd_bus.c link = (reg >> 4) & 0x03; reg 161 arch/x86/pci/amd_bus.c end = (reg & 0xfff000) | 0xfff; reg 219 arch/x86/pci/amd_bus.c reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3)); reg 220 arch/x86/pci/amd_bus.c if (!(reg & 3)) reg 223 arch/x86/pci/amd_bus.c start = reg & 0xffffff00; /* 39:16 on 31:8*/ reg 225 arch/x86/pci/amd_bus.c reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3)); reg 226 arch/x86/pci/amd_bus.c node = reg & 0x07; reg 227 arch/x86/pci/amd_bus.c link = (reg >> 4) & 0x03; reg 228 arch/x86/pci/amd_bus.c end = (reg & 0xffffff00); reg 334 arch/x86/pci/amd_bus.c u64 reg; reg 336 arch/x86/pci/amd_bus.c rdmsrl(MSR_AMD64_NB_CFG, reg); reg 337 arch/x86/pci/amd_bus.c if (!(reg & ENABLE_CF8_EXT_CFG)) { reg 338 arch/x86/pci/amd_bus.c reg |= ENABLE_CF8_EXT_CFG; reg 339 arch/x86/pci/amd_bus.c wrmsrl(MSR_AMD64_NB_CFG, reg); reg 31 arch/x86/pci/ce4100.c int reg; reg 32 arch/x86/pci/ce4100.c void (*init)(struct sim_dev_reg *reg); reg 33 arch/x86/pci/ce4100.c void (*read)(struct sim_dev_reg *reg, u32 *value); reg 34 arch/x86/pci/ce4100.c void (*write)(struct sim_dev_reg *reg, u32 value); reg 39 arch/x86/pci/ce4100.c void (*init)(struct sim_dev_reg *reg); reg 40 arch/x86/pci/ce4100.c void (*read)(struct sim_dev_reg *reg, u32 value); reg 41 arch/x86/pci/ce4100.c void (*write)(struct sim_dev_reg *reg, u32 value); reg 55 arch/x86/pci/ce4100.c static void reg_init(struct sim_dev_reg *reg) reg 57 arch/x86/pci/ce4100.c pci_direct_conf1.read(0, 1, reg->dev_func, reg->reg, 4, reg 58 arch/x86/pci/ce4100.c ®->sim_reg.value); reg 61 arch/x86/pci/ce4100.c static void reg_read(struct sim_dev_reg *reg, u32 *value) reg 63 arch/x86/pci/ce4100.c *value = reg->sim_reg.value; reg 66 arch/x86/pci/ce4100.c static void reg_write(struct sim_dev_reg *reg, u32 value) reg 68 arch/x86/pci/ce4100.c reg->sim_reg.value = (value & reg->sim_reg.mask) | reg 69 arch/x86/pci/ce4100.c (reg->sim_reg.value & ~reg->sim_reg.mask); reg 72 arch/x86/pci/ce4100.c static void sata_reg_init(struct sim_dev_reg *reg) reg 75 arch/x86/pci/ce4100.c ®->sim_reg.value); reg 76 arch/x86/pci/ce4100.c reg->sim_reg.value += 0x400; reg 79 arch/x86/pci/ce4100.c static void ehci_reg_read(struct sim_dev_reg *reg, u32 *value) reg 81 arch/x86/pci/ce4100.c reg_read(reg, value); reg 82 arch/x86/pci/ce4100.c if (*value != reg->sim_reg.mask) reg 86 arch/x86/pci/ce4100.c void sata_revid_init(struct sim_dev_reg *reg) reg 88 arch/x86/pci/ce4100.c reg->sim_reg.value = 0x01060100; reg 89 arch/x86/pci/ce4100.c reg->sim_reg.mask = 0; reg 92 arch/x86/pci/ce4100.c static void sata_revid_read(struct sim_dev_reg *reg, u32 *value) reg 94 arch/x86/pci/ce4100.c reg_read(reg, value); reg 97 arch/x86/pci/ce4100.c static void reg_noirq_read(struct sim_dev_reg *reg, u32 *value) reg 100 arch/x86/pci/ce4100.c *value = reg->sim_reg.value & 0xfff00ff; reg 166 arch/x86/pci/ce4100.c static inline void extract_bytes(u32 *value, int reg, int len) reg 170 arch/x86/pci/ce4100.c *value >>= ((reg & 3) * 8); reg 175 arch/x86/pci/ce4100.c int bridge_read(unsigned int devfn, int reg, int len, u32 *value) reg 180 arch/x86/pci/ce4100.c switch (reg) { reg 214 arch/x86/pci/ce4100.c if (reg == PCI_MEMORY_LIMIT) reg 243 arch/x86/pci/ce4100.c static int ce4100_bus1_read(unsigned int devfn, int reg, int len, u32 *value) reg 250 arch/x86/pci/ce4100.c bus1_fixups[i].reg == (reg & ~3) && reg 256 arch/x86/pci/ce4100.c extract_bytes(value, reg, len); reg 264 arch/x86/pci/ce4100.c unsigned int devfn, int reg, int len, u32 *value) reg 268 arch/x86/pci/ce4100.c if (bus == 1 && !ce4100_bus1_read(devfn, reg, len, value)) reg 272 arch/x86/pci/ce4100.c !bridge_read(devfn, reg, len, value)) reg 275 arch/x86/pci/ce4100.c return pci_direct_conf1.read(seg, bus, devfn, reg, len, value); reg 278 arch/x86/pci/ce4100.c static int ce4100_bus1_write(unsigned int devfn, int reg, int len, u32 value) reg 285 arch/x86/pci/ce4100.c bus1_fixups[i].reg == (reg & ~3) && reg 298 arch/x86/pci/ce4100.c unsigned int devfn, int reg, int len, u32 value) reg 302 arch/x86/pci/ce4100.c if (bus == 1 && !ce4100_bus1_write(devfn, reg, len, value)) reg 307 arch/x86/pci/ce4100.c ((reg & ~3) == PCI_BASE_ADDRESS_0)) reg 310 arch/x86/pci/ce4100.c return pci_direct_conf1.write(seg, bus, devfn, reg, len, value); reg 40 arch/x86/pci/common.c int reg, int len, u32 *val) reg 42 arch/x86/pci/common.c if (domain == 0 && reg < 256 && raw_pci_ops) reg 43 arch/x86/pci/common.c return raw_pci_ops->read(domain, bus, devfn, reg, len, val); reg 45 arch/x86/pci/common.c return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val); reg 50 arch/x86/pci/common.c int reg, int len, u32 val) reg 52 arch/x86/pci/common.c if (domain == 0 && reg < 256 && raw_pci_ops) reg 53 arch/x86/pci/common.c return raw_pci_ops->write(domain, bus, devfn, reg, len, val); reg 55 arch/x86/pci/common.c return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val); reg 17 arch/x86/pci/direct.c #define PCI_CONF1_ADDRESS(bus, devfn, reg) \ reg 18 arch/x86/pci/direct.c (0x80000000 | ((reg & 0xF00) << 16) | (bus << 16) \ reg 19 arch/x86/pci/direct.c | (devfn << 8) | (reg & 0xFC)) reg 22 arch/x86/pci/direct.c unsigned int devfn, int reg, int len, u32 *value) reg 26 arch/x86/pci/direct.c if (seg || (bus > 255) || (devfn > 255) || (reg > 4095)) { reg 33 arch/x86/pci/direct.c outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); reg 37 arch/x86/pci/direct.c *value = inb(0xCFC + (reg & 3)); reg 40 arch/x86/pci/direct.c *value = inw(0xCFC + (reg & 2)); reg 53 arch/x86/pci/direct.c unsigned int devfn, int reg, int len, u32 value) reg 57 arch/x86/pci/direct.c if (seg || (bus > 255) || (devfn > 255) || (reg > 4095)) reg 62 arch/x86/pci/direct.c outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); reg 66 arch/x86/pci/direct.c outb((u8)value, 0xCFC + (reg & 3)); reg 69 arch/x86/pci/direct.c outw((u16)value, 0xCFC + (reg & 2)); reg 93 arch/x86/pci/direct.c #define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg) reg 96 arch/x86/pci/direct.c unsigned int devfn, int reg, int len, u32 *value) reg 102 arch/x86/pci/direct.c if ((bus > 255) || (devfn > 255) || (reg > 255)) { reg 120 arch/x86/pci/direct.c *value = inb(PCI_CONF2_ADDRESS(dev, reg)); reg 123 arch/x86/pci/direct.c *value = inw(PCI_CONF2_ADDRESS(dev, reg)); reg 126 arch/x86/pci/direct.c *value = inl(PCI_CONF2_ADDRESS(dev, reg)); reg 138 arch/x86/pci/direct.c unsigned int devfn, int reg, int len, u32 value) reg 144 arch/x86/pci/direct.c if ((bus > 255) || (devfn > 255) || (reg > 255)) reg 160 arch/x86/pci/direct.c outb((u8)value, PCI_CONF2_ADDRESS(dev, reg)); reg 163 arch/x86/pci/direct.c outw((u16)value, PCI_CONF2_ADDRESS(dev, reg)); reg 166 arch/x86/pci/direct.c outl((u32)value, PCI_CONF2_ADDRESS(dev, reg)); reg 18 arch/x86/pci/fixup.c int pxb, reg; reg 22 arch/x86/pci/fixup.c reg = 0xd0; reg 24 arch/x86/pci/fixup.c pci_read_config_byte(d, reg++, &busno); reg 25 arch/x86/pci/fixup.c pci_read_config_byte(d, reg++, &suba); reg 26 arch/x86/pci/fixup.c pci_read_config_byte(d, reg++, &subb); reg 297 arch/x86/pci/i386.c u32 reg; reg 300 arch/x86/pci/i386.c pci_read_config_dword(dev, dev->rom_base_reg, ®); reg 302 arch/x86/pci/i386.c reg & ~PCI_ROM_ADDRESS_ENABLE); reg 95 arch/x86/pci/intel_mid_pci.c int reg, int len, u32 val, int offset) reg 99 arch/x86/pci/intel_mid_pci.c int bar = (reg - PCI_BASE_ADDRESS_0) >> 2; reg 130 arch/x86/pci/intel_mid_pci.c return raw_pci_ext_ops->write(domain, busnum, devfn, reg, 4, reg 135 arch/x86/pci/intel_mid_pci.c return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val); reg 148 arch/x86/pci/intel_mid_pci.c static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg) reg 158 arch/x86/pci/intel_mid_pci.c if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE) reg 179 arch/x86/pci/irq.c unsigned reg = offset + (nr >> 1); reg 181 arch/x86/pci/irq.c pci_read_config_byte(router, reg, &x); reg 189 arch/x86/pci/irq.c unsigned reg = offset + (nr >> 1); reg 191 arch/x86/pci/irq.c pci_read_config_byte(router, reg, &x); reg 193 arch/x86/pci/irq.c pci_write_config_byte(router, reg, x); reg 399 arch/x86/pci/irq.c int reg; reg 401 arch/x86/pci/irq.c reg = pirq; reg 402 arch/x86/pci/irq.c if (reg >= 0x01 && reg <= 0x04) reg 403 arch/x86/pci/irq.c reg += 0x40; reg 404 arch/x86/pci/irq.c pci_read_config_byte(router, reg, &x); reg 411 arch/x86/pci/irq.c int reg; reg 413 arch/x86/pci/irq.c reg = pirq; reg 414 arch/x86/pci/irq.c if (reg >= 0x01 && reg <= 0x04) reg 415 arch/x86/pci/irq.c reg += 0x40; reg 416 arch/x86/pci/irq.c pci_read_config_byte(router, reg, &x); reg 419 arch/x86/pci/irq.c pci_write_config_byte(router, reg, x); reg 52 arch/x86/pci/mmconfig_32.c unsigned int devfn, int reg, int len, u32 *value) reg 57 arch/x86/pci/mmconfig_32.c if ((bus > 255) || (devfn > 255) || (reg > 4095)) { reg 75 arch/x86/pci/mmconfig_32.c *value = mmio_config_readb(mmcfg_virt_addr + reg); reg 78 arch/x86/pci/mmconfig_32.c *value = mmio_config_readw(mmcfg_virt_addr + reg); reg 81 arch/x86/pci/mmconfig_32.c *value = mmio_config_readl(mmcfg_virt_addr + reg); reg 91 arch/x86/pci/mmconfig_32.c unsigned int devfn, int reg, int len, u32 value) reg 96 arch/x86/pci/mmconfig_32.c if ((bus > 255) || (devfn > 255) || (reg > 4095)) reg 112 arch/x86/pci/mmconfig_32.c mmio_config_writeb(mmcfg_virt_addr + reg, value); reg 115 arch/x86/pci/mmconfig_32.c mmio_config_writew(mmcfg_virt_addr + reg, value); reg 118 arch/x86/pci/mmconfig_32.c mmio_config_writel(mmcfg_virt_addr + reg, value); reg 29 arch/x86/pci/mmconfig_64.c unsigned int devfn, int reg, int len, u32 *value) reg 34 arch/x86/pci/mmconfig_64.c if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) { reg 48 arch/x86/pci/mmconfig_64.c *value = mmio_config_readb(addr + reg); reg 51 arch/x86/pci/mmconfig_64.c *value = mmio_config_readw(addr + reg); reg 54 arch/x86/pci/mmconfig_64.c *value = mmio_config_readl(addr + reg); reg 63 arch/x86/pci/mmconfig_64.c unsigned int devfn, int reg, int len, u32 value) reg 68 arch/x86/pci/mmconfig_64.c if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) reg 80 arch/x86/pci/mmconfig_64.c mmio_config_writeb(addr + reg, value); reg 83 arch/x86/pci/mmconfig_64.c mmio_config_writew(addr + reg, value); reg 86 arch/x86/pci/mmconfig_64.c mmio_config_writel(addr + reg, value); reg 31 arch/x86/pci/numachip.c unsigned int devfn, int reg, int len, u32 *value) reg 36 arch/x86/pci/numachip.c if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) { reg 56 arch/x86/pci/numachip.c *value = mmio_config_readb(addr + reg); reg 59 arch/x86/pci/numachip.c *value = mmio_config_readw(addr + reg); reg 62 arch/x86/pci/numachip.c *value = mmio_config_readl(addr + reg); reg 71 arch/x86/pci/numachip.c unsigned int devfn, int reg, int len, u32 value) reg 76 arch/x86/pci/numachip.c if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) reg 92 arch/x86/pci/numachip.c mmio_config_writeb(addr + reg, value); reg 95 arch/x86/pci/numachip.c mmio_config_writew(addr + reg, value); reg 98 arch/x86/pci/numachip.c mmio_config_writel(addr + reg, value); reg 179 arch/x86/pci/olpc.c static uint32_t *hdr_addr(const uint32_t *hdr, int reg) reg 194 arch/x86/pci/olpc.c addr = (uint32_t)hdr + reg + (bar_probing ? -0x10 : 0x20); reg 201 arch/x86/pci/olpc.c unsigned int devfn, int reg, int len, uint32_t *value) reg 209 arch/x86/pci/olpc.c return pci_direct_conf1.read(seg, bus, devfn, reg, len, value); reg 215 arch/x86/pci/olpc.c if (reg >= 0x70) reg 220 arch/x86/pci/olpc.c addr = hdr_addr(is_lx ? lxnb_hdr : gxnb_hdr, reg); reg 223 arch/x86/pci/olpc.c addr = hdr_addr(is_lx ? lxfb_hdr : gxfb_hdr, reg); reg 226 arch/x86/pci/olpc.c addr = is_lx ? hdr_addr(aes_hdr, reg) : &ff_loc; reg 229 arch/x86/pci/olpc.c addr = hdr_addr(isa_hdr, reg); reg 232 arch/x86/pci/olpc.c addr = hdr_addr(ac97_hdr, reg); reg 235 arch/x86/pci/olpc.c addr = hdr_addr(ohci_hdr, reg); reg 238 arch/x86/pci/olpc.c addr = hdr_addr(ehci_hdr, reg); reg 263 arch/x86/pci/olpc.c unsigned int devfn, int reg, int len, uint32_t value) reg 269 arch/x86/pci/olpc.c return pci_direct_conf1.write(seg, bus, devfn, reg, len, value); reg 281 arch/x86/pci/olpc.c if ((reg >= 0x10) && (reg < 0x2c)) { reg 290 arch/x86/pci/olpc.c if ((reg != PCI_ROM_ADDRESS) && (reg != PCI_COMMAND_MASTER) && reg 291 arch/x86/pci/olpc.c (reg != PCI_LATENCY_TIMER) && reg 292 arch/x86/pci/olpc.c (reg != PCI_CACHE_LINE_SIZE) && (reg != 0x44)) reg 294 arch/x86/pci/olpc.c " %x reg %x value %x\n", devfn, reg, value); reg 184 arch/x86/pci/pcbios.c unsigned int devfn, int reg, int len, u32 *value) reg 192 arch/x86/pci/pcbios.c if (!value || (bus > 255) || (devfn > 255) || (reg > 255)) reg 219 arch/x86/pci/pcbios.c "D" ((long)reg), reg 234 arch/x86/pci/pcbios.c unsigned int devfn, int reg, int len, u32 value) reg 242 arch/x86/pci/pcbios.c if ((bus > 255) || (devfn > 255) || (reg > 255)) reg 267 arch/x86/pci/pcbios.c "D" ((long)reg), reg 45 arch/x86/platform/atom/punit_atom_debug.c int reg; reg 89 arch/x86/platform/atom/punit_atom_debug.c punit_devp->reg, &punit_pwr_status); reg 30 arch/x86/platform/intel-mid/intel_mid_vrtc.c unsigned char vrtc_cmos_read(unsigned char reg) reg 35 arch/x86/platform/intel-mid/intel_mid_vrtc.c if (reg > 0xd || !vrtc_virt_base) reg 38 arch/x86/platform/intel-mid/intel_mid_vrtc.c lock_cmos_prefix(reg); reg 39 arch/x86/platform/intel-mid/intel_mid_vrtc.c retval = __raw_readb(vrtc_virt_base + (reg << 2)); reg 40 arch/x86/platform/intel-mid/intel_mid_vrtc.c lock_cmos_suffix(reg); reg 45 arch/x86/platform/intel-mid/intel_mid_vrtc.c void vrtc_cmos_write(unsigned char val, unsigned char reg) reg 47 arch/x86/platform/intel-mid/intel_mid_vrtc.c if (reg > 0xd || !vrtc_virt_base) reg 50 arch/x86/platform/intel-mid/intel_mid_vrtc.c lock_cmos_prefix(reg); reg 51 arch/x86/platform/intel-mid/intel_mid_vrtc.c __raw_writeb(val, vrtc_virt_base + (reg << 2)); reg 52 arch/x86/platform/intel-mid/intel_mid_vrtc.c lock_cmos_suffix(reg); reg 106 arch/x86/platform/intel-mid/pwr.c static u32 mid_pwr_get_state(struct mid_pwr *pwr, int reg) reg 108 arch/x86/platform/intel-mid/pwr.c return readl(pwr->regs + PM_SSS(reg)); reg 111 arch/x86/platform/intel-mid/pwr.c static void mid_pwr_set_state(struct mid_pwr *pwr, int reg, u32 value) reg 113 arch/x86/platform/intel-mid/pwr.c writel(value, pwr->regs + PM_SSC(reg)); reg 116 arch/x86/platform/intel-mid/pwr.c static void mid_pwr_set_wake(struct mid_pwr *pwr, int reg, u32 value) reg 118 arch/x86/platform/intel-mid/pwr.c writel(value, pwr->regs + PM_WKC(reg)); reg 153 arch/x86/platform/intel-mid/pwr.c static int __update_power_state(struct mid_pwr *pwr, int reg, int bit, int new) reg 160 arch/x86/platform/intel-mid/pwr.c power = mid_pwr_get_state(pwr, reg); reg 166 arch/x86/platform/intel-mid/pwr.c mid_pwr_set_state(pwr, reg, (power & ~(3 << bit)) | (new << bit)); reg 174 arch/x86/platform/intel-mid/pwr.c power = mid_pwr_get_state(pwr, reg); reg 214 arch/x86/platform/intel-mid/pwr.c pci_power_t state, int id, int reg, int bit) reg 222 arch/x86/platform/intel-mid/pwr.c ret = __update_power_state(pwr, reg, bit, (__force int)state); reg 235 arch/x86/platform/intel-mid/pwr.c int id, reg, bit; reg 242 arch/x86/platform/intel-mid/pwr.c reg = (id * LSS_PWS_BITS) / 32; reg 252 arch/x86/platform/intel-mid/pwr.c ret = __set_power_state(pwr, pdev, state, id, reg, bit); reg 274 arch/x86/platform/intel-mid/pwr.c int id, reg, bit; reg 284 arch/x86/platform/intel-mid/pwr.c reg = (id * LSS_PWS_BITS) / 32; reg 286 arch/x86/platform/intel-mid/pwr.c power = mid_pwr_get_state(pwr, reg); reg 110 arch/x86/platform/intel-quark/imr.c u32 reg = imr_id * IMR_NUM_REGS + idev->reg_base; reg 113 arch/x86/platform/intel-quark/imr.c ret = iosf_mbi_read(QRK_MBI_UNIT_MM, MBI_REG_READ, reg++, &imr->addr_lo); reg 117 arch/x86/platform/intel-quark/imr.c ret = iosf_mbi_read(QRK_MBI_UNIT_MM, MBI_REG_READ, reg++, &imr->addr_hi); reg 121 arch/x86/platform/intel-quark/imr.c ret = iosf_mbi_read(QRK_MBI_UNIT_MM, MBI_REG_READ, reg++, &imr->rmask); reg 125 arch/x86/platform/intel-quark/imr.c return iosf_mbi_read(QRK_MBI_UNIT_MM, MBI_REG_READ, reg++, &imr->wmask); reg 142 arch/x86/platform/intel-quark/imr.c u32 reg = imr_id * IMR_NUM_REGS + idev->reg_base; reg 147 arch/x86/platform/intel-quark/imr.c ret = iosf_mbi_write(QRK_MBI_UNIT_MM, MBI_REG_WRITE, reg++, imr->addr_lo); reg 151 arch/x86/platform/intel-quark/imr.c ret = iosf_mbi_write(QRK_MBI_UNIT_MM, MBI_REG_WRITE, reg++, imr->addr_hi); reg 155 arch/x86/platform/intel-quark/imr.c ret = iosf_mbi_write(QRK_MBI_UNIT_MM, MBI_REG_WRITE, reg++, imr->rmask); reg 159 arch/x86/platform/intel-quark/imr.c ret = iosf_mbi_write(QRK_MBI_UNIT_MM, MBI_REG_WRITE, reg++, imr->wmask); reg 304 arch/x86/platform/intel-quark/imr.c int reg; reg 337 arch/x86/platform/intel-quark/imr.c reg = -1; reg 351 arch/x86/platform/intel-quark/imr.c reg = i; reg 356 arch/x86/platform/intel-quark/imr.c if (reg == -1) { reg 362 arch/x86/platform/intel-quark/imr.c reg, &base, &end, raw_size, rmask, wmask); reg 370 arch/x86/platform/intel-quark/imr.c ret = imr_write(idev, reg, &imr); reg 381 arch/x86/platform/intel-quark/imr.c imr_write(idev, reg, &imr); reg 405 arch/x86/platform/intel-quark/imr.c static int __imr_remove_range(int reg, phys_addr_t base, size_t size) reg 422 arch/x86/platform/intel-quark/imr.c if (reg == -1) { reg 434 arch/x86/platform/intel-quark/imr.c if (reg >= 0) { reg 436 arch/x86/platform/intel-quark/imr.c ret = imr_read(idev, reg, &imr); reg 458 arch/x86/platform/intel-quark/imr.c reg = i; reg 469 arch/x86/platform/intel-quark/imr.c pr_debug("remove %d phys %pa-%pa size %zx\n", reg, &base, &end, raw_size); reg 477 arch/x86/platform/intel-quark/imr.c ret = imr_write(idev, reg, &imr); reg 516 arch/x86/platform/intel-quark/imr.c static inline int imr_clear(int reg) reg 518 arch/x86/platform/intel-quark/imr.c return __imr_remove_range(reg, 0, 0); reg 43 arch/x86/power/cpu.c msr->valid = !rdmsrl_safe(msr->info.msr_no, &msr->info.reg.q); reg 55 arch/x86/power/cpu.c wrmsrl(msr->info.msr_no, msr->info.reg.q); reg 426 arch/x86/power/cpu.c msr_array[i].info.reg.q = 0; reg 145 arch/x86/um/os-Linux/registers.c unsigned long get_thread_reg(int reg, jmp_buf *buf) reg 147 arch/x86/um/os-Linux/registers.c switch (reg) { reg 165 arch/x86/um/os-Linux/registers.c reg); reg 14 arch/x86/xen/apic.c static unsigned int xen_io_apic_read(unsigned apic, unsigned reg) reg 20 arch/x86/xen/apic.c apic_op.reg = reg; reg 26 arch/x86/xen/apic.c if (reg == 0x1) reg 28 arch/x86/xen/apic.c else if (reg == 0x0) reg 45 arch/x86/xen/apic.c static u32 xen_apic_read(u32 reg) reg 59 arch/x86/xen/apic.c if (reg == APIC_LVR) reg 62 arch/x86/xen/apic.c if (reg == APIC_LDR) reg 65 arch/x86/xen/apic.c if (reg != APIC_ID) reg 75 arch/x86/xen/apic.c static void xen_apic_write(u32 reg, u32 val) reg 77 arch/x86/xen/apic.c if (reg == APIC_LVTPC) { reg 78 arch/x86/xen/apic.c (void)pmu_apic_update(reg); reg 83 arch/x86/xen/apic.c WARN(1,"register: %x, value: %x\n", reg, val); reg 321 arch/x86/xen/enlighten_pv.c static void xen_set_debugreg(int reg, unsigned long val) reg 323 arch/x86/xen/enlighten_pv.c HYPERVISOR_set_debugreg(reg, val); reg 326 arch/x86/xen/enlighten_pv.c static unsigned long xen_get_debugreg(int reg) reg 328 arch/x86/xen/enlighten_pv.c return HYPERVISOR_get_debugreg(reg); reg 192 arch/x86/xen/pmu.c uint64_t *reg = NULL; reg 207 arch/x86/xen/pmu.c reg = &ctxt->global_ovf_ctrl; reg 210 arch/x86/xen/pmu.c reg = &ctxt->global_status; reg 213 arch/x86/xen/pmu.c reg = &ctxt->global_ctrl; reg 216 arch/x86/xen/pmu.c reg = &ctxt->fixed_ctrl; reg 222 arch/x86/xen/pmu.c reg = &fix_counters[index]; reg 226 arch/x86/xen/pmu.c reg = &arch_cntr_pair[index].counter; reg 230 arch/x86/xen/pmu.c reg = &arch_cntr_pair[index].control; reg 237 arch/x86/xen/pmu.c if (reg) { reg 239 arch/x86/xen/pmu.c *val = *reg; reg 241 arch/x86/xen/pmu.c *reg = *val; reg 254 arch/x86/xen/pmu.c uint64_t *reg = NULL; reg 272 arch/x86/xen/pmu.c reg = &ctrl_regs[i]; reg 276 arch/x86/xen/pmu.c reg = &counter_regs[i]; reg 282 arch/x86/xen/pmu.c if (reg) { reg 284 arch/x86/xen/pmu.c *val = *reg; reg 286 arch/x86/xen/pmu.c *reg = *val; reg 18 arch/x86/xen/pmu.h int pmu_apic_update(uint32_t reg); reg 31 arch/xtensa/include/asm/current.h #define GET_CURRENT(reg,sp) \ reg 32 arch/xtensa/include/asm/current.h GET_THREAD_INFO(reg,sp); \ reg 33 arch/xtensa/include/asm/current.h l32i reg, reg, TI_TASK \ reg 123 arch/xtensa/include/asm/processor.h #define SPILL_SLOT(sp, reg) (*(((unsigned long *)(sp)) - 4 + (reg))) reg 128 arch/xtensa/include/asm/processor.h #define SPILL_SLOT_CALL8(sp, reg) (*(((unsigned long *)(sp)) - 12 + (reg))) reg 133 arch/xtensa/include/asm/processor.h #define SPILL_SLOT_CALL12(sp, reg) (*(((unsigned long *)(sp)) - 16 + (reg))) reg 64 arch/xtensa/include/asm/syscall.h static const unsigned int reg[] = XTENSA_SYSCALL_ARGUMENT_REGS; reg 68 arch/xtensa/include/asm/syscall.h args[i] = regs->areg[reg[i]]; reg 75 arch/xtensa/include/asm/syscall.h static const unsigned int reg[] = XTENSA_SYSCALL_ARGUMENT_REGS; reg 79 arch/xtensa/include/asm/syscall.h regs->areg[reg[i]] = args[i]; reg 95 arch/xtensa/include/asm/thread_info.h #define GET_THREAD_INFO(reg,sp) \ reg 96 arch/xtensa/include/asm/thread_info.h extui reg, sp, 0, CURRENT_SHIFT; \ reg 97 arch/xtensa/include/asm/thread_info.h xor reg, sp, reg reg 147 arch/xtensa/kernel/hw_breakpoint.c static void set_ibreak_regs(int reg, struct perf_event *bp) reg 152 arch/xtensa/kernel/hw_breakpoint.c xtensa_wsr(info->address, SREG_IBREAKA + reg); reg 154 arch/xtensa/kernel/hw_breakpoint.c xtensa_set_sr(ibreakenable | (1 << reg), SREG_IBREAKENABLE); reg 157 arch/xtensa/kernel/hw_breakpoint.c static void set_dbreak_regs(int reg, struct perf_event *bp) reg 167 arch/xtensa/kernel/hw_breakpoint.c xtensa_wsr(info->address, SREG_DBREAKA + reg); reg 168 arch/xtensa/kernel/hw_breakpoint.c xtensa_wsr(dbreakc, SREG_DBREAKC + reg); reg 319 block/ioctl.c struct pr_registration reg; reg 325 block/ioctl.c if (copy_from_user(®, arg, sizeof(reg))) reg 328 block/ioctl.c if (reg.flags & ~PR_FL_IGNORE_KEY) reg 330 block/ioctl.c return ops->pr_register(bdev, reg.old_key, reg.new_key, reg.flags); reg 715 drivers/acpi/acpi_lpss.c static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) reg 717 drivers/acpi/acpi_lpss.c return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); reg 721 drivers/acpi/acpi_lpss.c unsigned int reg) reg 723 drivers/acpi/acpi_lpss.c writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); reg 726 drivers/acpi/acpi_lpss.c static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) reg 747 drivers/acpi/acpi_lpss.c *val = __lpss_reg_read(pdata, reg); reg 758 drivers/acpi/acpi_lpss.c unsigned int reg; reg 761 drivers/acpi/acpi_lpss.c reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; reg 762 drivers/acpi/acpi_lpss.c ret = lpss_reg_read(dev, reg, <r_value); reg 32 drivers/acpi/acpica/achware.h acpi_hw_validate_register(struct acpi_generic_address *reg, reg 35 drivers/acpi/acpica/achware.h acpi_status acpi_hw_read(u64 *value, struct acpi_generic_address *reg); reg 37 drivers/acpi/acpica/achware.h acpi_status acpi_hw_write(u64 value, struct acpi_generic_address *reg); reg 322 drivers/acpi/acpica/acmacros.h #define ACPI_REGISTER_INSERT_VALUE(reg, pos, mask, val) \ reg 323 drivers/acpi/acpica/acmacros.h reg = (reg & (~(mask))) | ACPI_REGISTER_PREPARE_BITS(val, pos, mask) reg 20 drivers/acpi/acpica/hwregs.c struct acpi_generic_address *reg, reg 51 drivers/acpi/acpica/hwregs.c struct acpi_generic_address *reg, u8 max_bit_width) reg 69 drivers/acpi/acpica/hwregs.c if (!reg->bit_offset && reg->bit_width && reg 70 drivers/acpi/acpica/hwregs.c ACPI_IS_POWER_OF_TWO(reg->bit_width) && reg 71 drivers/acpi/acpica/hwregs.c ACPI_IS_ALIGNED(reg->bit_width, 8)) { reg 72 drivers/acpi/acpica/hwregs.c access_bit_width = reg->bit_width; reg 73 drivers/acpi/acpica/hwregs.c } else if (reg->access_width) { reg 74 drivers/acpi/acpica/hwregs.c access_bit_width = ACPI_ACCESS_BIT_WIDTH(reg->access_width); reg 77 drivers/acpi/acpica/hwregs.c ACPI_ROUND_UP_POWER_OF_TWO_8(reg->bit_offset + reg 78 drivers/acpi/acpica/hwregs.c reg->bit_width); reg 90 drivers/acpi/acpica/hwregs.c if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) { reg 122 drivers/acpi/acpica/hwregs.c acpi_hw_validate_register(struct acpi_generic_address *reg, reg 130 drivers/acpi/acpica/hwregs.c if (!reg) { reg 139 drivers/acpi/acpica/hwregs.c ACPI_MOVE_64_TO_64(address, ®->address); reg 146 drivers/acpi/acpica/hwregs.c if ((reg->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) && reg 147 drivers/acpi/acpica/hwregs.c (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO)) { reg 149 drivers/acpi/acpica/hwregs.c "Unsupported address space: 0x%X", reg->space_id)); reg 155 drivers/acpi/acpica/hwregs.c if (reg->access_width > 4) { reg 158 drivers/acpi/acpica/hwregs.c reg->access_width)); reg 165 drivers/acpi/acpica/hwregs.c acpi_hw_get_access_bit_width(*address, reg, max_bit_width); reg 167 drivers/acpi/acpica/hwregs.c ACPI_ROUND_UP(reg->bit_offset + reg->bit_width, access_width); reg 195 drivers/acpi/acpica/hwregs.c acpi_status acpi_hw_read(u64 *value, struct acpi_generic_address *reg) reg 210 drivers/acpi/acpica/hwregs.c status = acpi_hw_validate_register(reg, 64, &address); reg 220 drivers/acpi/acpica/hwregs.c access_width = acpi_hw_get_access_bit_width(address, reg, 64); reg 221 drivers/acpi/acpica/hwregs.c bit_width = reg->bit_offset + reg->bit_width; reg 222 drivers/acpi/acpica/hwregs.c bit_offset = reg->bit_offset; reg 234 drivers/acpi/acpica/hwregs.c if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { reg 271 drivers/acpi/acpica/hwregs.c acpi_ut_get_region_name(reg->space_id))); reg 290 drivers/acpi/acpica/hwregs.c acpi_status acpi_hw_write(u64 value, struct acpi_generic_address *reg) reg 304 drivers/acpi/acpica/hwregs.c status = acpi_hw_validate_register(reg, 64, &address); reg 311 drivers/acpi/acpica/hwregs.c access_width = acpi_hw_get_access_bit_width(address, reg, 64); reg 312 drivers/acpi/acpica/hwregs.c bit_width = reg->bit_offset + reg->bit_width; reg 313 drivers/acpi/acpica/hwregs.c bit_offset = reg->bit_offset; reg 331 drivers/acpi/acpica/hwregs.c if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { reg 364 drivers/acpi/acpica/hwregs.c acpi_ut_get_region_name(reg->space_id))); reg 92 drivers/acpi/acpica/hwxface.c acpi_status acpi_read(u64 *return_value, struct acpi_generic_address *reg) reg 98 drivers/acpi/acpica/hwxface.c status = acpi_hw_read(return_value, reg); reg 116 drivers/acpi/acpica/hwxface.c acpi_status acpi_write(u64 value, struct acpi_generic_address *reg) reg 122 drivers/acpi/acpica/hwxface.c status = acpi_hw_write(value, reg); reg 571 drivers/acpi/apei/apei-base.c static int apei_check_gar(struct acpi_generic_address *reg, u64 *paddr, reg 576 drivers/acpi/apei/apei-base.c bit_width = reg->bit_width; reg 577 drivers/acpi/apei/apei-base.c bit_offset = reg->bit_offset; reg 578 drivers/acpi/apei/apei-base.c access_size_code = reg->access_width; reg 579 drivers/acpi/apei/apei-base.c space_id = reg->space_id; reg 580 drivers/acpi/apei/apei-base.c *paddr = get_unaligned(®->address); reg 626 drivers/acpi/apei/apei-base.c int apei_map_generic_address(struct acpi_generic_address *reg) reg 632 drivers/acpi/apei/apei-base.c rc = apei_check_gar(reg, &address, &access_bit_width); reg 635 drivers/acpi/apei/apei-base.c return acpi_os_map_generic_address(reg); reg 640 drivers/acpi/apei/apei-base.c int apei_read(u64 *val, struct acpi_generic_address *reg) reg 647 drivers/acpi/apei/apei-base.c rc = apei_check_gar(reg, &address, &access_bit_width); reg 652 drivers/acpi/apei/apei-base.c switch(reg->space_id) { reg 674 drivers/acpi/apei/apei-base.c int apei_write(u64 val, struct acpi_generic_address *reg) reg 681 drivers/acpi/apei/apei-base.c rc = apei_check_gar(reg, &address, &access_bit_width); reg 685 drivers/acpi/apei/apei-base.c switch (reg->space_id) { reg 710 drivers/acpi/apei/apei-base.c struct acpi_generic_address *reg = &entry->register_region; reg 719 drivers/acpi/apei/apei-base.c rc = apei_check_gar(reg, &paddr, &access_bit_width); reg 723 drivers/acpi/apei/apei-base.c switch (reg->space_id) { reg 73 drivers/acpi/apei/apei-internal.h int apei_map_generic_address(struct acpi_generic_address *reg); reg 75 drivers/acpi/apei/apei-internal.h static inline void apei_unmap_generic_address(struct acpi_generic_address *reg) reg 77 drivers/acpi/apei/apei-internal.h acpi_os_unmap_generic_address(reg); reg 80 drivers/acpi/apei/apei-internal.h int apei_read(u64 *val, struct acpi_generic_address *reg); reg 81 drivers/acpi/apei/apei-internal.h int apei_write(u64 val, struct acpi_generic_address *reg); reg 100 drivers/acpi/cppc_acpi.c (cpc)->cpc_entry.reg.space_id == \ reg 104 drivers/acpi/cppc_acpi.c #define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \ reg 105 drivers/acpi/cppc_acpi.c (reg)->address == 0 && \ reg 106 drivers/acpi/cppc_acpi.c (reg)->bit_width == 0 && \ reg 107 drivers/acpi/cppc_acpi.c (reg)->bit_offset == 0 && \ reg 108 drivers/acpi/cppc_acpi.c (reg)->access_width == 0) reg 113 drivers/acpi/cppc_acpi.c !IS_NULL_REG(&(cpc)->cpc_entry.reg)) reg 814 drivers/acpi/cppc_acpi.c memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t)); reg 941 drivers/acpi/cppc_acpi.c int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val) reg 956 drivers/acpi/cppc_acpi.c int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) reg 972 drivers/acpi/cppc_acpi.c struct cpc_reg *reg = ®_res->cpc_entry.reg; reg 980 drivers/acpi/cppc_acpi.c if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) reg 981 drivers/acpi/cppc_acpi.c vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); reg 982 drivers/acpi/cppc_acpi.c else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) reg 984 drivers/acpi/cppc_acpi.c else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) reg 985 drivers/acpi/cppc_acpi.c return cpc_read_ffh(cpu, reg, val); reg 987 drivers/acpi/cppc_acpi.c return acpi_os_read_memory((acpi_physical_address)reg->address, reg 988 drivers/acpi/cppc_acpi.c val, reg->bit_width); reg 990 drivers/acpi/cppc_acpi.c switch (reg->bit_width) { reg 1005 drivers/acpi/cppc_acpi.c reg->bit_width, pcc_ss_id); reg 1017 drivers/acpi/cppc_acpi.c struct cpc_reg *reg = ®_res->cpc_entry.reg; reg 1019 drivers/acpi/cppc_acpi.c if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) reg 1020 drivers/acpi/cppc_acpi.c vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); reg 1021 drivers/acpi/cppc_acpi.c else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) reg 1023 drivers/acpi/cppc_acpi.c else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) reg 1024 drivers/acpi/cppc_acpi.c return cpc_write_ffh(cpu, reg, val); reg 1026 drivers/acpi/cppc_acpi.c return acpi_os_write_memory((acpi_physical_address)reg->address, reg 1027 drivers/acpi/cppc_acpi.c val, reg->bit_width); reg 1029 drivers/acpi/cppc_acpi.c switch (reg->bit_width) { reg 1044 drivers/acpi/cppc_acpi.c reg->bit_width, pcc_ss_id); reg 1153 drivers/acpi/cppc_acpi.c IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) { reg 780 drivers/acpi/osl.c acpi_os_read_pci_configuration(struct acpi_pci_id * pci_id, u32 reg, reg 805 drivers/acpi/osl.c reg, size, &value32); reg 812 drivers/acpi/osl.c acpi_os_write_pci_configuration(struct acpi_pci_id * pci_id, u32 reg, reg 833 drivers/acpi/osl.c reg, size, value); reg 35 drivers/acpi/pmic/intel_pmic.c int count, int *reg, int *bit) reg 41 drivers/acpi/pmic/intel_pmic.c *reg = table[i].reg; reg 57 drivers/acpi/pmic/intel_pmic.c int reg, bit, result; reg 66 drivers/acpi/pmic/intel_pmic.c d->power_table_count, ®, &bit); reg 73 drivers/acpi/pmic/intel_pmic.c d->get_power(regmap, reg, bit, value64) : reg 74 drivers/acpi/pmic/intel_pmic.c d->update_power(regmap, reg, bit, *value64 == 1); reg 82 drivers/acpi/pmic/intel_pmic.c int reg, u64 *value) reg 89 drivers/acpi/pmic/intel_pmic.c raw_temp = opregion->data->get_raw_temp(opregion->regmap, reg); reg 106 drivers/acpi/pmic/intel_pmic.c static int pmic_thermal_temp(struct intel_pmic_opregion *opregion, int reg, reg 110 drivers/acpi/pmic/intel_pmic.c pmic_read_temp(opregion, reg, value) : -EINVAL; reg 113 drivers/acpi/pmic/intel_pmic.c static int pmic_thermal_aux(struct intel_pmic_opregion *opregion, int reg, reg 119 drivers/acpi/pmic/intel_pmic.c return pmic_read_temp(opregion, reg, value); reg 132 drivers/acpi/pmic/intel_pmic.c return opregion->data->update_aux(opregion->regmap, reg, raw_temp); reg 135 drivers/acpi/pmic/intel_pmic.c static int pmic_thermal_pen(struct intel_pmic_opregion *opregion, int reg, reg 145 drivers/acpi/pmic/intel_pmic.c return d->get_policy(regmap, reg, bit, value); reg 150 drivers/acpi/pmic/intel_pmic.c return d->update_policy(regmap, reg, bit, *value); reg 175 drivers/acpi/pmic/intel_pmic.c int reg, bit, result; reg 181 drivers/acpi/pmic/intel_pmic.c d->thermal_table_count, ®, &bit); reg 188 drivers/acpi/pmic/intel_pmic.c result = pmic_thermal_temp(opregion, reg, function, value64); reg 190 drivers/acpi/pmic/intel_pmic.c result = pmic_thermal_aux(opregion, reg, function, value64); reg 192 drivers/acpi/pmic/intel_pmic.c result = pmic_thermal_pen(opregion, reg, bit, reg 7 drivers/acpi/pmic/intel_pmic.h int reg; /* corresponding thermal register */ reg 12 drivers/acpi/pmic/intel_pmic.h int (*get_power)(struct regmap *r, int reg, int bit, u64 *value); reg 13 drivers/acpi/pmic/intel_pmic.h int (*update_power)(struct regmap *r, int reg, int bit, bool on); reg 14 drivers/acpi/pmic/intel_pmic.h int (*get_raw_temp)(struct regmap *r, int reg); reg 15 drivers/acpi/pmic/intel_pmic.h int (*update_aux)(struct regmap *r, int reg, int raw_temp); reg 16 drivers/acpi/pmic/intel_pmic.h int (*get_policy)(struct regmap *r, int reg, int bit, u64 *value); reg 17 drivers/acpi/pmic/intel_pmic.h int (*update_policy)(struct regmap *r, int reg, int bit, int enable); reg 30 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x63, reg 35 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x65, reg 40 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x67, reg 45 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x6d, reg 50 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x6f, reg 55 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x70, reg 60 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x71, reg 65 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x72, reg 70 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x73, reg 75 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x74, reg 80 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x75, reg 85 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x76, reg 90 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x77, reg 95 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x78, reg 100 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x78, reg 105 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x78, reg 110 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x7b, reg 115 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0xA0, reg 120 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0xA1, reg 125 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0xA2, reg 130 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0xA3, reg 135 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0xA4, reg 140 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0xA5, reg 145 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0xA6, reg 150 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0xA7, reg 155 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0xA8, reg 160 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0xA9, reg 165 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0xAA, reg 170 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x36, reg 175 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x36, reg 183 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F39 reg 187 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F24 reg 191 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F26 reg 195 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F3B reg 199 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F28 reg 203 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F2A reg 207 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F3D reg 211 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F2C reg 215 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F2E reg 219 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F3F reg 223 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F30 reg 227 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F41 reg 231 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F32 reg 235 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F43 reg 239 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F34 reg 243 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F6A, reg 248 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F6A, reg 253 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F6A, reg 258 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F6A, reg 263 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F6A, reg 268 drivers/acpi/pmic/intel_pmic_bxtwc.c .reg = 0x4F6A, reg 273 drivers/acpi/pmic/intel_pmic_bxtwc.c static int intel_bxtwc_pmic_get_power(struct regmap *regmap, int reg, reg 278 drivers/acpi/pmic/intel_pmic_bxtwc.c if (regmap_read(regmap, reg, &data)) reg 285 drivers/acpi/pmic/intel_pmic_bxtwc.c static int intel_bxtwc_pmic_update_power(struct regmap *regmap, int reg, reg 295 drivers/acpi/pmic/intel_pmic_bxtwc.c return regmap_update_bits(regmap, reg, mask, val); reg 298 drivers/acpi/pmic/intel_pmic_bxtwc.c static int intel_bxtwc_pmic_get_raw_temp(struct regmap *regmap, int reg) reg 307 drivers/acpi/pmic/intel_pmic_bxtwc.c if (regmap_read(regmap, reg, &val)) reg 311 drivers/acpi/pmic/intel_pmic_bxtwc.c if (regmap_read(regmap, (reg - 1), &val)) reg 324 drivers/acpi/pmic/intel_pmic_bxtwc.c intel_bxtwc_pmic_update_aux(struct regmap *regmap, int reg, int raw) reg 341 drivers/acpi/pmic/intel_pmic_bxtwc.c reg - 1, reg 347 drivers/acpi/pmic/intel_pmic_bxtwc.c return regmap_write(regmap, reg, alrt_l); reg 351 drivers/acpi/pmic/intel_pmic_bxtwc.c intel_bxtwc_pmic_get_policy(struct regmap *regmap, int reg, int bit, u64 *value) reg 356 drivers/acpi/pmic/intel_pmic_bxtwc.c if (regmap_read(regmap, reg, &val)) reg 365 drivers/acpi/pmic/intel_pmic_bxtwc.c int reg, int bit, int enable) reg 369 drivers/acpi/pmic/intel_pmic_bxtwc.c return regmap_update_bits(regmap, reg, mask, val); reg 23 drivers/acpi/pmic/intel_pmic_chtdc_ti.c { .address = 0x00, .reg = 0x41 }, reg 24 drivers/acpi/pmic/intel_pmic_chtdc_ti.c { .address = 0x04, .reg = 0x42 }, reg 25 drivers/acpi/pmic/intel_pmic_chtdc_ti.c { .address = 0x08, .reg = 0x43 }, reg 26 drivers/acpi/pmic/intel_pmic_chtdc_ti.c { .address = 0x0c, .reg = 0x45 }, reg 27 drivers/acpi/pmic/intel_pmic_chtdc_ti.c { .address = 0x10, .reg = 0x46 }, reg 28 drivers/acpi/pmic/intel_pmic_chtdc_ti.c { .address = 0x14, .reg = 0x47 }, reg 29 drivers/acpi/pmic/intel_pmic_chtdc_ti.c { .address = 0x18, .reg = 0x48 }, reg 30 drivers/acpi/pmic/intel_pmic_chtdc_ti.c { .address = 0x1c, .reg = 0x49 }, reg 31 drivers/acpi/pmic/intel_pmic_chtdc_ti.c { .address = 0x20, .reg = 0x4a }, reg 32 drivers/acpi/pmic/intel_pmic_chtdc_ti.c { .address = 0x24, .reg = 0x4b }, reg 33 drivers/acpi/pmic/intel_pmic_chtdc_ti.c { .address = 0x28, .reg = 0x4c }, reg 34 drivers/acpi/pmic/intel_pmic_chtdc_ti.c { .address = 0x2c, .reg = 0x4d }, reg 35 drivers/acpi/pmic/intel_pmic_chtdc_ti.c { .address = 0x30, .reg = 0x4e }, reg 41 drivers/acpi/pmic/intel_pmic_chtdc_ti.c .reg = CHTDC_TI_GPADC reg 45 drivers/acpi/pmic/intel_pmic_chtdc_ti.c .reg = CHTDC_TI_GPADC reg 50 drivers/acpi/pmic/intel_pmic_chtdc_ti.c .reg = CHTDC_TI_GPADC reg 55 drivers/acpi/pmic/intel_pmic_chtdc_ti.c .reg = CHTDC_TI_BPTHERM reg 59 drivers/acpi/pmic/intel_pmic_chtdc_ti.c .reg = CHTDC_TI_GPADC reg 64 drivers/acpi/pmic/intel_pmic_chtdc_ti.c .reg = CHTDC_TI_DIETEMP reg 68 drivers/acpi/pmic/intel_pmic_chtdc_ti.c static int chtdc_ti_pmic_get_power(struct regmap *regmap, int reg, int bit, reg 73 drivers/acpi/pmic/intel_pmic_chtdc_ti.c if (regmap_read(regmap, reg, &data)) reg 80 drivers/acpi/pmic/intel_pmic_chtdc_ti.c static int chtdc_ti_pmic_update_power(struct regmap *regmap, int reg, int bit, reg 83 drivers/acpi/pmic/intel_pmic_chtdc_ti.c return regmap_update_bits(regmap, reg, 1, on); reg 86 drivers/acpi/pmic/intel_pmic_chtdc_ti.c static int chtdc_ti_pmic_get_raw_temp(struct regmap *regmap, int reg) reg 90 drivers/acpi/pmic/intel_pmic_chtdc_ti.c if (regmap_bulk_read(regmap, reg, buf, 2)) reg 76 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_V1P8A_CTRL, reg 81 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_V1P8SX_CTRL, reg 86 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_VDDQ_CTRL, reg 91 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_V1P2A_CTRL, reg 96 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_V1P2SX_CTRL, reg 101 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_V2P8SX_CTRL, reg 106 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_V3P3A_CTRL, reg 111 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_V3P3SD_CTRL, reg 116 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_VSDIO_CTRL, reg 141 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_VPROG1A_CTRL, reg 146 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_VPROG1B_CTRL, reg 151 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_VPROG1F_CTRL, reg 156 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_VPROG2D_CTRL, reg 161 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_VPROG3A_CTRL, reg 166 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_VPROG3B_CTRL, reg 171 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_VPROG4A_CTRL, reg 176 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_VPROG4B_CTRL, reg 181 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_VPROG4C_CTRL, reg 186 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_VPROG4D_CTRL, reg 191 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_VPROG5A_CTRL, reg 196 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_VPROG5B_CTRL, reg 201 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_VPROG6A_CTRL, reg 206 drivers/acpi/pmic/intel_pmic_chtwc.c .reg = CHT_WC_VPROG6B_CTRL, reg 216 drivers/acpi/pmic/intel_pmic_chtwc.c static int intel_cht_wc_pmic_get_power(struct regmap *regmap, int reg, reg 221 drivers/acpi/pmic/intel_pmic_chtwc.c if (regmap_read(regmap, reg, &data)) reg 228 drivers/acpi/pmic/intel_pmic_chtwc.c static int intel_cht_wc_pmic_update_power(struct regmap *regmap, int reg, reg 231 drivers/acpi/pmic/intel_pmic_chtwc.c return regmap_update_bits(regmap, reg, bitmask, on ? 1 : 0); reg 27 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x63, reg 32 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x62, reg 37 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x64, reg 42 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x6a, reg 47 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x6b, reg 52 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x6c, reg 57 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x6d, reg 67 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x66, reg 77 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x69, reg 82 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x68, reg 92 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x5c, reg 97 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x5d, reg 102 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x5b, reg 107 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x61, reg 112 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x60, reg 122 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x56, reg 127 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x57, reg 132 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x59, reg 140 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x75 reg 144 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x95 reg 148 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x97 reg 152 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x77 reg 156 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x9a reg 160 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x9c reg 164 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x79 reg 168 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x9f reg 172 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0xa1 reg 176 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x94 reg 180 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x99 reg 184 drivers/acpi/pmic/intel_pmic_crc.c .reg = 0x9e reg 188 drivers/acpi/pmic/intel_pmic_crc.c static int intel_crc_pmic_get_power(struct regmap *regmap, int reg, reg 193 drivers/acpi/pmic/intel_pmic_crc.c if (regmap_read(regmap, reg, &data)) reg 200 drivers/acpi/pmic/intel_pmic_crc.c static int intel_crc_pmic_update_power(struct regmap *regmap, int reg, reg 205 drivers/acpi/pmic/intel_pmic_crc.c if (regmap_read(regmap, reg, &data)) reg 215 drivers/acpi/pmic/intel_pmic_crc.c if (regmap_write(regmap, reg, data)) reg 220 drivers/acpi/pmic/intel_pmic_crc.c static int intel_crc_pmic_get_raw_temp(struct regmap *regmap, int reg) reg 228 drivers/acpi/pmic/intel_pmic_crc.c if (regmap_read(regmap, reg, &temp_l) || reg 229 drivers/acpi/pmic/intel_pmic_crc.c regmap_read(regmap, reg - 1, &temp_h)) reg 235 drivers/acpi/pmic/intel_pmic_crc.c static int intel_crc_pmic_update_aux(struct regmap *regmap, int reg, int raw) reg 237 drivers/acpi/pmic/intel_pmic_crc.c return regmap_write(regmap, reg, raw) || reg 238 drivers/acpi/pmic/intel_pmic_crc.c regmap_update_bits(regmap, reg - 1, 0x3, raw >> 8) ? -EIO : 0; reg 242 drivers/acpi/pmic/intel_pmic_crc.c int reg, int bit, u64 *value) reg 246 drivers/acpi/pmic/intel_pmic_crc.c if (regmap_read(regmap, reg, &pen)) reg 253 drivers/acpi/pmic/intel_pmic_crc.c int reg, int bit, int enable) reg 264 drivers/acpi/pmic/intel_pmic_crc.c if (regmap_update_bits(regmap, reg, 0x80, enable << 7)) reg 32 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x13, reg 37 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x13, reg 42 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x13, reg 47 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x12, reg 52 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x12, reg 57 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x12, reg 62 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x12, reg 67 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x12, reg 72 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x12, reg 77 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x12, reg 82 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x13, reg 87 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x13, reg 92 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x13, reg 97 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x10, reg 102 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x10, reg 107 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x10, reg 112 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x10, reg 117 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x10, reg 122 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x10, reg 127 drivers/acpi/pmic/intel_pmic_xpower.c .reg = 0x92, reg 135 drivers/acpi/pmic/intel_pmic_xpower.c .reg = XPOWER_GPADC_LOW reg 139 drivers/acpi/pmic/intel_pmic_xpower.c .reg = XPOWER_GPADC_LOW reg 143 drivers/acpi/pmic/intel_pmic_xpower.c .reg = XPOWER_GPADC_LOW reg 147 drivers/acpi/pmic/intel_pmic_xpower.c .reg = XPOWER_GPADC_LOW reg 151 drivers/acpi/pmic/intel_pmic_xpower.c .reg = XPOWER_GPADC_LOW reg 155 drivers/acpi/pmic/intel_pmic_xpower.c .reg = XPOWER_GPADC_LOW reg 159 drivers/acpi/pmic/intel_pmic_xpower.c static int intel_xpower_pmic_get_power(struct regmap *regmap, int reg, reg 164 drivers/acpi/pmic/intel_pmic_xpower.c if (regmap_read(regmap, reg, &data)) reg 168 drivers/acpi/pmic/intel_pmic_xpower.c if (reg == XPOWER_GPI1_CTRL) reg 176 drivers/acpi/pmic/intel_pmic_xpower.c static int intel_xpower_pmic_update_power(struct regmap *regmap, int reg, reg 182 drivers/acpi/pmic/intel_pmic_xpower.c if (reg == XPOWER_GPI1_CTRL) reg 183 drivers/acpi/pmic/intel_pmic_xpower.c return regmap_update_bits(regmap, reg, GPI1_LDO_MASK, reg 190 drivers/acpi/pmic/intel_pmic_xpower.c if (regmap_read(regmap, reg, &data)) { reg 200 drivers/acpi/pmic/intel_pmic_xpower.c if (regmap_write(regmap, reg, data)) reg 216 drivers/acpi/pmic/intel_pmic_xpower.c static int intel_xpower_pmic_get_raw_temp(struct regmap *regmap, int reg) reg 20 drivers/acpi/pmic/tps68470_pmic.c u32 reg; /* corresponding register */ reg 39 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_S_I2C_CTL, reg 45 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_VCMCTL, reg 51 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_VAUX1CTL, reg 57 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_VAUX2CTL, reg 63 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_VACTL, reg 69 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_VDCTL, reg 79 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_VSIOVAL, reg 85 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_VIOVAL, reg 91 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_VCMVAL, reg 97 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_VAUX1VAL, reg 103 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_VAUX2VAL, reg 109 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_VAVAL, reg 115 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_VDVAL, reg 125 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_POSTDIV2, reg 131 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_BOOSTDIV, reg 137 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_BUCKDIV, reg 143 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_PLLSWR, reg 149 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_XTALDIV, reg 155 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_PLLDIV, reg 161 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_POSTDIV, reg 171 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_PLLCTL, reg 177 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_PLLCTL2, reg 183 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_CLKCFG1, reg 190 drivers/acpi/pmic/tps68470_pmic.c .reg = TPS68470_REG_CLKCFG2, reg 199 drivers/acpi/pmic/tps68470_pmic.c const unsigned int table_size, int *reg, reg 208 drivers/acpi/pmic/tps68470_pmic.c if (!reg || !bitmask) reg 211 drivers/acpi/pmic/tps68470_pmic.c *reg = table[i].reg; reg 217 drivers/acpi/pmic/tps68470_pmic.c static int tps68470_pmic_get_power(struct regmap *regmap, int reg, reg 222 drivers/acpi/pmic/tps68470_pmic.c if (regmap_read(regmap, reg, &data)) reg 229 drivers/acpi/pmic/tps68470_pmic.c static int tps68470_pmic_get_vr_val(struct regmap *regmap, int reg, reg 234 drivers/acpi/pmic/tps68470_pmic.c if (regmap_read(regmap, reg, &data)) reg 241 drivers/acpi/pmic/tps68470_pmic.c static int tps68470_pmic_get_clk(struct regmap *regmap, int reg, reg 246 drivers/acpi/pmic/tps68470_pmic.c if (regmap_read(regmap, reg, &data)) reg 253 drivers/acpi/pmic/tps68470_pmic.c static int tps68470_pmic_get_clk_freq(struct regmap *regmap, int reg, reg 258 drivers/acpi/pmic/tps68470_pmic.c if (regmap_read(regmap, reg, &data)) reg 265 drivers/acpi/pmic/tps68470_pmic.c static int ti_tps68470_regmap_update_bits(struct regmap *regmap, int reg, reg 268 drivers/acpi/pmic/tps68470_pmic.c return regmap_update_bits(regmap, reg, bitmask, value); reg 284 drivers/acpi/pmic/tps68470_pmic.c int reg, ret, bitmask; reg 289 drivers/acpi/pmic/tps68470_pmic.c ret = pmic_get_reg_bit(address, tbl, tbl_size, ®, &bitmask); reg 299 drivers/acpi/pmic/tps68470_pmic.c get(regmap, reg, bitmask, value) : reg 300 drivers/acpi/pmic/tps68470_pmic.c update(regmap, reg, bitmask, *value); reg 344 drivers/acpi/processor_idle.c struct acpi_power_register *reg; reg 361 drivers/acpi/processor_idle.c reg = (struct acpi_power_register *)obj->buffer.pointer; reg 363 drivers/acpi/processor_idle.c if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && reg 364 drivers/acpi/processor_idle.c (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) reg 380 drivers/acpi/processor_idle.c cx.address = reg->address; reg 384 drivers/acpi/processor_idle.c if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { reg 386 drivers/acpi/processor_idle.c (pr->id, &cx, reg) == 0) { reg 1017 drivers/acpi/processor_idle.c struct acpi_power_register *reg; reg 1019 drivers/acpi/processor_idle.c reg = (struct acpi_power_register *)obj->buffer.pointer; reg 1020 drivers/acpi/processor_idle.c if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && reg 1021 drivers/acpi/processor_idle.c reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) reg 1024 drivers/acpi/processor_idle.c lpi_state->address = reg->address; reg 1026 drivers/acpi/processor_idle.c reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE ? reg 145 drivers/ata/ahci_brcm.c u32 reg; reg 152 drivers/ata/ahci_brcm.c reg = brcm_sata_readreg(p); reg 153 drivers/ata/ahci_brcm.c reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE; reg 154 drivers/ata/ahci_brcm.c brcm_sata_writereg(reg, p); reg 158 drivers/ata/ahci_brcm.c reg = brcm_sata_readreg(p); reg 159 drivers/ata/ahci_brcm.c reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB | reg 161 drivers/ata/ahci_brcm.c reg |= SATA_TOP_CTRL_2_SW_RST_TX; reg 162 drivers/ata/ahci_brcm.c brcm_sata_writereg(reg, p); reg 163 drivers/ata/ahci_brcm.c reg = brcm_sata_readreg(p); reg 164 drivers/ata/ahci_brcm.c reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET; reg 165 drivers/ata/ahci_brcm.c brcm_sata_writereg(reg, p); reg 166 drivers/ata/ahci_brcm.c reg = brcm_sata_readreg(p); reg 167 drivers/ata/ahci_brcm.c reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET; reg 168 drivers/ata/ahci_brcm.c brcm_sata_writereg(reg, p); reg 177 drivers/ata/ahci_brcm.c u32 reg; reg 184 drivers/ata/ahci_brcm.c reg = brcm_sata_readreg(p); reg 185 drivers/ata/ahci_brcm.c reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB | reg 188 drivers/ata/ahci_brcm.c brcm_sata_writereg(reg, p); reg 192 drivers/ata/ahci_brcm.c reg = brcm_sata_readreg(p); reg 193 drivers/ata/ahci_brcm.c reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE; reg 194 drivers/ata/ahci_brcm.c brcm_sata_writereg(reg, p); reg 447 drivers/ata/ahci_imx.c u32 val, reg; reg 491 drivers/ata/ahci_imx.c IMX8QM_CSR_PCIE_CTRL2_OFFSET, ®); reg 492 drivers/ata/ahci_imx.c if ((reg & IMX8QM_CTRL_LTSSM_ENABLE) == 0) { reg 501 drivers/ata/ahci_imx.c if (((reg | val) & IMX8QM_CTRL_LTSSM_ENABLE) == 0) { reg 596 drivers/ata/ahci_imx.c reg = IMX8QM_CSR_PHYX1_OFFSET + reg 598 drivers/ata/ahci_imx.c regmap_read(imxpriv->gpr, reg, &val); reg 613 drivers/ata/ahci_imx.c reg = readb(imxpriv->phy_base + reg 615 drivers/ata/ahci_imx.c if (unlikely(reg != imxpriv->imped_ratio)) reg 617 drivers/ata/ahci_imx.c reg = readb(imxpriv->phy_base + reg 619 drivers/ata/ahci_imx.c if (unlikely(reg != imxpriv->imped_ratio)) reg 88 drivers/ata/ahci_mvebu.c u32 reg; reg 92 drivers/ata/ahci_mvebu.c reg = readl(hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA); reg 93 drivers/ata/ahci_mvebu.c reg |= BIT(6); reg 94 drivers/ata/ahci_mvebu.c writel(reg, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA); reg 53 drivers/ata/ahci_sunxi.c static void sunxi_clrbits(void __iomem *reg, u32 clr_val) reg 57 drivers/ata/ahci_sunxi.c reg_val = readl(reg); reg 59 drivers/ata/ahci_sunxi.c writel(reg_val, reg); reg 62 drivers/ata/ahci_sunxi.c static void sunxi_setbits(void __iomem *reg, u32 set_val) reg 66 drivers/ata/ahci_sunxi.c reg_val = readl(reg); reg 68 drivers/ata/ahci_sunxi.c writel(reg_val, reg); reg 71 drivers/ata/ahci_sunxi.c static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val) reg 75 drivers/ata/ahci_sunxi.c reg_val = readl(reg); reg 78 drivers/ata/ahci_sunxi.c writel(reg_val, reg); reg 81 drivers/ata/ahci_sunxi.c static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift) reg 83 drivers/ata/ahci_sunxi.c return (readl(reg) >> shift) & mask; reg 113 drivers/ata/ahci_xgene.c void __iomem *reg, unsigned reg 120 drivers/ata/ahci_xgene.c tmp = ioread32(reg); reg 125 drivers/ata/ahci_xgene.c tmp = ioread32(reg); reg 776 drivers/ata/ata_piix.c static void piix_sidpr_sel(struct ata_link *link, unsigned int reg) reg 781 drivers/ata/ata_piix.c iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg], reg 786 drivers/ata/ata_piix.c unsigned int reg, u32 *val) reg 790 drivers/ata/ata_piix.c if (reg >= ARRAY_SIZE(piix_sidx_map)) reg 793 drivers/ata/ata_piix.c piix_sidpr_sel(link, reg); reg 799 drivers/ata/ata_piix.c unsigned int reg, u32 val) reg 803 drivers/ata/ata_piix.c if (reg >= ARRAY_SIZE(piix_sidx_map)) reg 806 drivers/ata/ata_piix.c piix_sidpr_sel(link, reg); reg 5518 drivers/ata/libata-core.c int sata_scr_read(struct ata_link *link, int reg, u32 *val) reg 5522 drivers/ata/libata-core.c return link->ap->ops->scr_read(link, reg, val); reg 5526 drivers/ata/libata-core.c return sata_pmp_scr_read(link, reg, val); reg 5545 drivers/ata/libata-core.c int sata_scr_write(struct ata_link *link, int reg, u32 val) reg 5549 drivers/ata/libata-core.c return link->ap->ops->scr_write(link, reg, val); reg 5553 drivers/ata/libata-core.c return sata_pmp_scr_write(link, reg, val); reg 5571 drivers/ata/libata-core.c int sata_scr_write_flush(struct ata_link *link, int reg, u32 val) reg 5577 drivers/ata/libata-core.c rc = link->ap->ops->scr_write(link, reg, val); reg 5579 drivers/ata/libata-core.c rc = link->ap->ops->scr_read(link, reg, &val); reg 5585 drivers/ata/libata-core.c return sata_pmp_scr_write(link, reg, val); reg 6793 drivers/ata/libata-core.c pci_read_config_byte(pdev, bits->reg, &tmp8); reg 6799 drivers/ata/libata-core.c pci_read_config_word(pdev, bits->reg, &tmp16); reg 6805 drivers/ata/libata-core.c pci_read_config_dword(pdev, bits->reg, &tmp32); reg 7175 drivers/ata/libata-core.c u32 ata_wait_register(struct ata_port *ap, void __iomem *reg, u32 mask, u32 val, reg 7181 drivers/ata/libata-core.c tmp = ioread32(reg); reg 7191 drivers/ata/libata-core.c tmp = ioread32(reg); reg 38 drivers/ata/libata-pmp.c static unsigned int sata_pmp_read(struct ata_link *link, int reg, u32 *r_val) reg 49 drivers/ata/libata-pmp.c tf.feature = reg; reg 75 drivers/ata/libata-pmp.c static unsigned int sata_pmp_write(struct ata_link *link, int reg, u32 val) reg 85 drivers/ata/libata-pmp.c tf.feature = reg; reg 141 drivers/ata/libata-pmp.c int sata_pmp_scr_read(struct ata_link *link, int reg, u32 *r_val) reg 145 drivers/ata/libata-pmp.c if (reg > SATA_PMP_PSCR_CONTROL) reg 148 drivers/ata/libata-pmp.c err_mask = sata_pmp_read(link, reg, r_val); reg 151 drivers/ata/libata-pmp.c reg, err_mask); reg 172 drivers/ata/libata-pmp.c int sata_pmp_scr_write(struct ata_link *link, int reg, u32 val) reg 176 drivers/ata/libata-pmp.c if (reg > SATA_PMP_PSCR_CONTROL) reg 179 drivers/ata/libata-pmp.c err_mask = sata_pmp_write(link, reg, val); reg 182 drivers/ata/libata-pmp.c reg, err_mask); reg 229 drivers/ata/libata-pmp.c int reg = gscr_to_read[i]; reg 232 drivers/ata/libata-pmp.c err_mask = sata_pmp_read(dev->link, reg, &gscr[reg]); reg 235 drivers/ata/libata-pmp.c reg, err_mask); reg 296 drivers/ata/libata-pmp.c u32 reg; reg 298 drivers/ata/libata-pmp.c err_mask = sata_pmp_read(&ap->link, PMP_GSCR_SII_POL, ®); reg 304 drivers/ata/libata-pmp.c reg &= ~0x1; reg 305 drivers/ata/libata-pmp.c err_mask = sata_pmp_write(&ap->link, PMP_GSCR_SII_POL, reg); reg 170 drivers/ata/libata.h extern int sata_pmp_scr_read(struct ata_link *link, int reg, u32 *val); reg 171 drivers/ata/libata.h extern int sata_pmp_scr_write(struct ata_link *link, int reg, u32 val); reg 176 drivers/ata/libata.h static inline int sata_pmp_scr_read(struct ata_link *link, int reg, u32 *val) reg 181 drivers/ata/libata.h static inline int sata_pmp_scr_write(struct ata_link *link, int reg, u32 val) reg 322 drivers/ata/pata_artop.c u8 reg; reg 328 drivers/ata/pata_artop.c pci_read_config_byte(pdev, 0x49, ®); reg 329 drivers/ata/pata_artop.c pci_write_config_byte(pdev, 0x49, reg & ~0x30); reg 334 drivers/ata/pata_artop.c pci_read_config_byte(pdev, PCI_LATENCY_TIMER, ®); reg 335 drivers/ata/pata_artop.c if (reg <= 0x80) reg 339 drivers/ata/pata_artop.c pci_read_config_byte(pdev, 0x4a, ®); reg 340 drivers/ata/pata_artop.c pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80); reg 59 drivers/ata/pata_cmd640.c u8 reg; reg 101 drivers/ata/pata_cmd640.c pci_read_config_byte(pdev, arttim, ®); reg 102 drivers/ata/pata_cmd640.c reg &= 0x3F; reg 103 drivers/ata/pata_cmd640.c reg |= t.setup; reg 104 drivers/ata/pata_cmd640.c pci_write_config_byte(pdev, arttim, reg); reg 112 drivers/ata/pata_cmd640.c pci_read_config_byte(pdev, ARTIM23, ®); reg 113 drivers/ata/pata_cmd640.c reg &= 0x3F; reg 114 drivers/ata/pata_cmd640.c reg |= t.setup; reg 115 drivers/ata/pata_cmd640.c pci_write_config_byte(pdev, ARTIM23, reg); reg 101 drivers/ata/pata_cmd64x.c u8 reg; reg 160 drivers/ata/pata_cmd64x.c pci_read_config_byte(pdev, arttim, ®); reg 161 drivers/ata/pata_cmd64x.c reg &= 0x3F; reg 162 drivers/ata/pata_cmd64x.c reg |= t.setup; reg 163 drivers/ata/pata_cmd64x.c pci_write_config_byte(pdev, arttim, reg); reg 431 drivers/ata/pata_cmd64x.c u8 reg; reg 475 drivers/ata/pata_cmd64x.c pci_read_config_byte(pdev, CNTRL, ®); reg 478 drivers/ata/pata_cmd64x.c if (port_ok && cntrl_ch0_ok && !(reg & CNTRL_CH0)) { reg 483 drivers/ata/pata_cmd64x.c if (port_ok && !(reg & CNTRL_CH1)) { reg 77 drivers/ata/pata_cs5530.c u8 reg; reg 112 drivers/ata/pata_cs5530.c reg = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); reg 113 drivers/ata/pata_cs5530.c reg |= (1 << (5 + adev->devno)); reg 114 drivers/ata/pata_cs5530.c iowrite8(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); reg 93 drivers/ata/pata_cs5535.c u32 reg, dummy; reg 113 drivers/ata/pata_cs5535.c rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy); reg 114 drivers/ata/pata_cs5535.c wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg | 0x80000000UL, 0); reg 132 drivers/ata/pata_cs5535.c u32 reg, dummy; reg 135 drivers/ata/pata_cs5535.c rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy); reg 136 drivers/ata/pata_cs5535.c reg &= 0x80000000UL; reg 138 drivers/ata/pata_cs5535.c reg |= udma_timings[mode - XFER_UDMA_0]; reg 140 drivers/ata/pata_cs5535.c reg |= mwdma_timings[mode - XFER_MW_DMA_0]; reg 141 drivers/ata/pata_cs5535.c wrmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, 0); reg 86 drivers/ata/pata_cs5536.c static int cs5536_read(struct pci_dev *pdev, int reg, u32 *val) reg 91 drivers/ata/pata_cs5536.c rdmsr(MSR_IDE_CFG + reg, *val, dummy); reg 95 drivers/ata/pata_cs5536.c return pci_read_config_dword(pdev, PCI_IDE_CFG + reg * 4, val); reg 98 drivers/ata/pata_cs5536.c static int cs5536_write(struct pci_dev *pdev, int reg, int val) reg 101 drivers/ata/pata_cs5536.c wrmsr(MSR_IDE_CFG + reg, val, 0); reg 105 drivers/ata/pata_cs5536.c return pci_write_config_dword(pdev, PCI_IDE_CFG + reg * 4, val); reg 103 drivers/ata/pata_cypress.c int reg = CY82_INDEX_CHANNEL0 + ap->port_no; reg 106 drivers/ata/pata_cypress.c outb(reg, 0x22); reg 264 drivers/ata/pata_ep93xx.c bool reg) reg 268 drivers/ata/pata_ep93xx.c unsigned long t0 = reg ? t->cyc8b : t->cycle; reg 269 drivers/ata/pata_ep93xx.c unsigned long t2 = reg ? t->act8b : t->active; reg 270 drivers/ata/pata_ep93xx.c unsigned long t2i = reg ? t->rec8b : t->recover; reg 298 drivers/ata/pata_ep93xx.c bool reg) reg 302 drivers/ata/pata_ep93xx.c unsigned long t0 = reg ? t->cyc8b : t->cycle; reg 303 drivers/ata/pata_ep93xx.c unsigned long t2 = reg ? t->act8b : t->active; reg 304 drivers/ata/pata_ep93xx.c unsigned long t2i = reg ? t->rec8b : t->recover; reg 234 drivers/ata/pata_hpt366.c u32 mask, reg, t; reg 251 drivers/ata/pata_hpt366.c pci_read_config_dword(pdev, addr, ®); reg 252 drivers/ata/pata_hpt366.c reg = ((reg & ~mask) | (t & mask)) & ~0xc0000000; reg 253 drivers/ata/pata_hpt366.c pci_write_config_dword(pdev, addr, reg); reg 413 drivers/ata/pata_hpt37x.c u32 reg, timing, mask; reg 435 drivers/ata/pata_hpt37x.c pci_read_config_dword(pdev, addr1, ®); reg 436 drivers/ata/pata_hpt37x.c reg = (reg & ~mask) | (timing & mask); reg 437 drivers/ata/pata_hpt37x.c pci_write_config_dword(pdev, addr1, reg); reg 507 drivers/ata/pata_hpt37x.c u32 reg, timing, mask; reg 528 drivers/ata/pata_hpt37x.c pci_read_config_dword(pdev, addr1, ®); reg 529 drivers/ata/pata_hpt37x.c reg = (reg & ~mask) | (timing & mask); reg 530 drivers/ata/pata_hpt37x.c pci_write_config_dword(pdev, addr1, reg); reg 187 drivers/ata/pata_hpt3x2n.c u32 reg, timing, mask; reg 208 drivers/ata/pata_hpt3x2n.c pci_read_config_dword(pdev, addr1, ®); reg 209 drivers/ata/pata_hpt3x2n.c reg = (reg & ~mask) | (timing & mask); reg 210 drivers/ata/pata_hpt3x2n.c pci_write_config_dword(pdev, addr1, reg); reg 426 drivers/ata/pata_legacy.c static u8 opti_syscfg(u8 reg) reg 433 drivers/ata/pata_legacy.c outb(reg, 0x22); reg 753 drivers/ata/pata_legacy.c static void winbond_writecfg(unsigned long port, u8 reg, u8 val) reg 757 drivers/ata/pata_legacy.c outb(reg, port + 0x01); reg 762 drivers/ata/pata_legacy.c static u8 winbond_readcfg(unsigned long port, u8 reg) reg 768 drivers/ata/pata_legacy.c outb(reg, port + 0x01); reg 780 drivers/ata/pata_legacy.c u8 reg; reg 783 drivers/ata/pata_legacy.c reg = winbond_readcfg(ld_winbond->timing, 0x81); reg 786 drivers/ata/pata_legacy.c if (reg & 0x40) /* Fast VLB bus, assume 50MHz */ reg 794 drivers/ata/pata_legacy.c winbond_writecfg(ld_winbond->timing, timing, reg); reg 798 drivers/ata/pata_legacy.c reg = 0x35; reg 800 drivers/ata/pata_legacy.c reg |= 0x08; /* FIFO off */ reg 802 drivers/ata/pata_legacy.c reg |= 0x02; /* IORDY off */ reg 803 drivers/ata/pata_legacy.c reg |= (clamp_val(t.setup, 0, 3) << 6); reg 804 drivers/ata/pata_legacy.c winbond_writecfg(ld_winbond->timing, timing + 1, reg); reg 863 drivers/ata/pata_legacy.c u8 reg = winbond_readcfg(winbond, 0x81); reg 864 drivers/ata/pata_legacy.c reg |= 0x80; /* jumpered mode off */ reg 865 drivers/ata/pata_legacy.c winbond_writecfg(winbond, 0x81, reg); reg 866 drivers/ata/pata_legacy.c reg = winbond_readcfg(winbond, 0x83); reg 867 drivers/ata/pata_legacy.c reg |= 0xF0; /* local control */ reg 868 drivers/ata/pata_legacy.c winbond_writecfg(winbond, 0x83, reg); reg 869 drivers/ata/pata_legacy.c reg = winbond_readcfg(winbond, 0x85); reg 870 drivers/ata/pata_legacy.c reg |= 0xF0; /* programmable timing */ reg 871 drivers/ata/pata_legacy.c winbond_writecfg(winbond, 0x85, reg); reg 873 drivers/ata/pata_legacy.c reg = winbond_readcfg(winbond, 0x81); reg 875 drivers/ata/pata_legacy.c if (reg & mask) reg 609 drivers/ata/pata_macio.c u32 reg = priv->treg[dev][0]; reg 612 drivers/ata/pata_macio.c reg += 0x00800000; reg 613 drivers/ata/pata_macio.c writel(reg, rbase + IDE_TIMING_CONFIG); reg 81 drivers/ata/pata_opti.c static void opti_write_reg(struct ata_port *ap, u8 val, int reg) reg 91 drivers/ata/pata_opti.c iowrite8(val, regio + reg); reg 65 drivers/ata/pata_rz1000.c u16 reg; reg 67 drivers/ata/pata_rz1000.c if (pci_read_config_word(pdev, 0x40, ®) != 0) reg 69 drivers/ata/pata_rz1000.c reg &= 0xDFFF; reg 70 drivers/ata/pata_rz1000.c if (pci_write_config_word(pdev, 0x40, reg) != 0) reg 78 drivers/ata/pata_samsung_cf.c u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG); reg 79 drivers/ata/pata_samsung_cf.c reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg | S3C_ATA_CFG_SWAP); reg 80 drivers/ata/pata_samsung_cf.c writel(reg, s3c_ide_regbase + S3C_ATA_CFG); reg 149 drivers/ata/pata_samsung_cf.c static void ata_outb(struct ata_host *host, u8 addr, void __iomem *reg) reg 154 drivers/ata/pata_samsung_cf.c writeb(addr, reg); reg 160 drivers/ata/pata_samsung_cf.c static u8 ata_inb(struct ata_host *host, void __iomem *reg) reg 166 drivers/ata/pata_samsung_cf.c (void) readb(reg); reg 452 drivers/ata/pata_samsung_cf.c u32 reg; reg 454 drivers/ata/pata_samsung_cf.c reg = readl(info->ide_addr + S3C_ATA_IRQ); reg 455 drivers/ata/pata_samsung_cf.c writel(reg, info->ide_addr + S3C_ATA_IRQ); reg 87 drivers/ata/pata_sc1200.c unsigned int reg = 0x40 + 0x10 * ap->port_no; reg 90 drivers/ata/pata_sc1200.c pci_read_config_dword(pdev, reg + 4, &format); reg 93 drivers/ata/pata_sc1200.c pci_write_config_dword(pdev, reg + 8 * adev->devno, reg 122 drivers/ata/pata_sc1200.c unsigned int reg = 0x40 + 0x10 * ap->port_no; reg 134 drivers/ata/pata_sc1200.c pci_read_config_dword(pdev, reg + 4, &timings); reg 137 drivers/ata/pata_sc1200.c pci_write_config_dword(pdev, reg + 4, timings); reg 139 drivers/ata/pata_sc1200.c pci_write_config_dword(pdev, reg + 12, format); reg 281 drivers/ata/pata_serverworks.c u32 reg; reg 285 drivers/ata/pata_serverworks.c pci_read_config_dword(isa_dev, 0x64, ®); reg 286 drivers/ata/pata_serverworks.c reg &= ~0x00002000; /* disable 600ns interrupt mask */ reg 287 drivers/ata/pata_serverworks.c if (!(reg & 0x00004000)) reg 289 drivers/ata/pata_serverworks.c reg |= 0x00004000; /* enable UDMA/33 support */ reg 290 drivers/ata/pata_serverworks.c pci_write_config_dword(isa_dev, 0x64, reg); reg 122 drivers/ata/pata_sil680.c u16 reg; reg 133 drivers/ata/pata_sil680.c pci_read_config_word(pdev, tfaddr-2, ®); reg 136 drivers/ata/pata_sil680.c reg &= ~0x0200; /* Clear IORDY */ reg 140 drivers/ata/pata_sil680.c reg |= 0x0200; /* Enable IORDY */ reg 143 drivers/ata/pata_sil680.c pci_write_config_word(pdev, tfaddr-2, reg); reg 657 drivers/ata/pata_sis.c u8 reg; reg 673 drivers/ata/pata_sis.c pci_read_config_byte(pdev, 0x49, ®); reg 674 drivers/ata/pata_sis.c if (!(reg & 0x01)) reg 675 drivers/ata/pata_sis.c pci_write_config_byte(pdev, 0x49, reg | 0x01); reg 683 drivers/ata/pata_sis.c pci_read_config_byte(pdev, 0x52, ®); reg 684 drivers/ata/pata_sis.c if (!(reg & 0x04)) reg 685 drivers/ata/pata_sis.c pci_write_config_byte(pdev, 0x52, reg | 0x04); reg 690 drivers/ata/pata_sis.c pci_read_config_byte(pdev, PCI_CLASS_PROG, ®); reg 691 drivers/ata/pata_sis.c if (( reg & 0x0F ) != 0x00) reg 692 drivers/ata/pata_sis.c pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0); reg 699 drivers/ata/pata_sis.c pci_read_config_byte(pdev, 0x52, ®); reg 700 drivers/ata/pata_sis.c if (!(reg & 0x08)) reg 701 drivers/ata/pata_sis.c pci_write_config_byte(pdev, 0x52, reg|0x08); reg 1010 drivers/ata/sata_dwc_460ex.c u32 reg; reg 1037 drivers/ata/sata_dwc_460ex.c sata_dwc_scr_read(&ap->link, SCR_ERROR, ®); reg 1038 drivers/ata/sata_dwc_460ex.c if (reg & SATA_DWC_SERROR_ERR_BITS) { reg 1040 drivers/ata/sata_dwc_460ex.c __func__, reg); reg 1222 drivers/ata/sata_mv.c u32 reg = readl(port_mmio + EDMA_CMD); reg 1223 drivers/ata/sata_mv.c if (!(reg & EDMA_EN)) reg 1962 drivers/ata/sata_mv.c u32 reg, status; reg 1968 drivers/ata/sata_mv.c reg = readl(port_mmio + BMDMA_STATUS); reg 1969 drivers/ata/sata_mv.c if (reg & ATA_DMA_ACTIVE) reg 1971 drivers/ata/sata_mv.c else if (reg & ATA_DMA_ERR) reg 1972 drivers/ata/sata_mv.c status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR; reg 3155 drivers/ata/sata_mv.c #define ZERO(reg) writel(0, port_mmio + (reg)) reg 3179 drivers/ata/sata_mv.c #define ZERO(reg) writel(0, hc_mmio + (reg)) reg 3215 drivers/ata/sata_mv.c #define ZERO(reg) writel(0, mmio + (reg)) reg 3262 drivers/ata/sata_mv.c void __iomem *reg = mmio + PCI_MAIN_CMD_STS; reg 3269 drivers/ata/sata_mv.c t = readl(reg); reg 3270 drivers/ata/sata_mv.c writel(t | STOP_PCI_MASTER, reg); reg 3274 drivers/ata/sata_mv.c t = readl(reg); reg 3287 drivers/ata/sata_mv.c writel(t | GLOB_SFT_RST, reg); reg 3288 drivers/ata/sata_mv.c t = readl(reg); reg 3301 drivers/ata/sata_mv.c writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); reg 3302 drivers/ata/sata_mv.c t = readl(reg); reg 3437 drivers/ata/sata_mv.c #define ZERO(reg) writel(0, port_mmio + (reg)) reg 3462 drivers/ata/sata_mv.c #define ZERO(reg) writel(0, hc_mmio + (reg)) reg 3504 drivers/ata/sata_mv.c u32 reg; reg 3506 drivers/ata/sata_mv.c reg = readl(port_mmio + PHY_MODE3); reg 3507 drivers/ata/sata_mv.c reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */ reg 3508 drivers/ata/sata_mv.c reg |= (0x1 << 27); reg 3509 drivers/ata/sata_mv.c reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */ reg 3510 drivers/ata/sata_mv.c reg |= (0x1 << 29); reg 3511 drivers/ata/sata_mv.c writel(reg, port_mmio + PHY_MODE3); reg 3513 drivers/ata/sata_mv.c reg = readl(port_mmio + PHY_MODE4); reg 3514 drivers/ata/sata_mv.c reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */ reg 3515 drivers/ata/sata_mv.c reg |= (0x1 << 16); reg 3516 drivers/ata/sata_mv.c writel(reg, port_mmio + PHY_MODE4); reg 3518 drivers/ata/sata_mv.c reg = readl(port_mmio + PHY_MODE9_GEN2); reg 3519 drivers/ata/sata_mv.c reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ reg 3520 drivers/ata/sata_mv.c reg |= 0x8; reg 3521 drivers/ata/sata_mv.c reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ reg 3522 drivers/ata/sata_mv.c writel(reg, port_mmio + PHY_MODE9_GEN2); reg 3524 drivers/ata/sata_mv.c reg = readl(port_mmio + PHY_MODE9_GEN1); reg 3525 drivers/ata/sata_mv.c reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ reg 3526 drivers/ata/sata_mv.c reg |= 0x8; reg 3527 drivers/ata/sata_mv.c reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ reg 3528 drivers/ata/sata_mv.c writel(reg, port_mmio + PHY_MODE9_GEN1); reg 3593 drivers/ata/sata_mv.c u32 reg = readl(port_mmio + SATA_IFCTL); reg 3594 drivers/ata/sata_mv.c int old = reg & 0xf; reg 3597 drivers/ata/sata_mv.c reg = (reg & ~0xf) | pmp; reg 3598 drivers/ata/sata_mv.c writelfl(reg, port_mmio + SATA_IFCTL); reg 3731 drivers/ata/sata_mv.c u32 reg; reg 3735 drivers/ata/sata_mv.c reg = readl(mmio + MV_PCI_MODE); reg 3736 drivers/ata/sata_mv.c if ((reg & MV_PCI_MODE_MASK) == 0) reg 3745 drivers/ata/sata_mv.c u32 reg; reg 3748 drivers/ata/sata_mv.c reg = readl(mmio + MV_PCI_COMMAND); reg 3749 drivers/ata/sata_mv.c if (reg & MV_PCI_COMMAND_MRDTRIG) reg 3762 drivers/ata/sata_mv.c u32 reg = readl(mmio + MV_PCI_COMMAND); reg 3763 drivers/ata/sata_mv.c writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND); reg 170 drivers/ata/sata_rcar.c static void sata_rcar_gen1_phy_write(struct sata_rcar_priv *priv, u16 reg, reg 184 drivers/ata/sata_rcar.c reg |= SATAPHYADDR_PHYRATEMODE; reg 186 drivers/ata/sata_rcar.c iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG); reg 246 drivers/ata/sata_rcar.c static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count) reg 251 drivers/ata/sata_rcar.c u16 data = ioread32(reg); reg 257 drivers/ata/sata_rcar.c static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count) reg 262 drivers/ata/sata_rcar.c iowrite32(*ptr++, reg); reg 322 drivers/ata/sata_svw.c const u32 *reg = of_get_property(np, "reg", NULL); reg 323 drivers/ata/sata_svw.c if (!reg) reg 325 drivers/ata/sata_svw.c if (index == *reg) { reg 1147 drivers/ata/sata_sx4.c unsigned int reg; reg 1169 drivers/ata/sata_sx4.c pdc_i2c_read_data[i].reg, reg 160 drivers/atm/eni.c #define eni_in(r) readl(eni_dev->reg+(r)*4) reg 161 drivers/atm/eni.c #define eni_out(v,r) writel((v),eni_dev->reg+(r)*4) reg 1750 drivers/atm/eni.c eni_dev->reg = base+REG_BASE; reg 78 drivers/atm/eni.h void __iomem *reg; /* register base */ reg 240 drivers/atm/firestream.c int reg, val; reg 1325 drivers/atm/firestream.c while (reginit->reg != PHY_EOF) { reg 1326 drivers/atm/firestream.c if (reginit->reg == PHY_CLEARALL) { reg 1332 drivers/atm/firestream.c write_phy (dev, reginit->reg, reginit->val); reg 1753 drivers/atm/fore200e.c opcode.reg = 0; reg 1780 drivers/atm/fore200e.c fore200e_set_oc3(struct fore200e* fore200e, u32 reg, u32 value, u32 mask) reg 1787 drivers/atm/fore200e.c DPRINTK(2, "set OC-3 reg = 0x%02x, value = 0x%02x, mask = 0x%02x\n", reg, value, mask); reg 1792 drivers/atm/fore200e.c opcode.reg = reg; reg 1807 drivers/atm/fore200e.c printk(FORE200E "unable to set OC-3 reg 0x%02x of device %s\n", reg, fore200e->name); reg 321 drivers/atm/fore200e.h u32 reg[ 128 ]; /* see the PMC Sierra PC5346 S/UNI-155-Lite reg 332 drivers/atm/fore200e.h u32 reg : 8, /* register index */ reg 176 drivers/atm/he.c #define he_writel(dev, val, reg) do { writel(val, (dev)->membase + (reg)); wmb(); } while (0) reg 177 drivers/atm/he.c #define he_readl(dev, reg) readl((dev)->membase + (reg)) reg 191 drivers/atm/he.c #define he_writel_rcm(dev, val, reg) \ reg 192 drivers/atm/he.c he_writel_internal(dev, val, reg, CON_CTL_RCM) reg 194 drivers/atm/he.c #define he_writel_tcm(dev, val, reg) \ reg 195 drivers/atm/he.c he_writel_internal(dev, val, reg, CON_CTL_TCM) reg 197 drivers/atm/he.c #define he_writel_mbox(dev, val, reg) \ reg 198 drivers/atm/he.c he_writel_internal(dev, val, reg, CON_CTL_MBOX) reg 208 drivers/atm/he.c #define he_readl_rcm(dev, reg) \ reg 209 drivers/atm/he.c he_readl_internal(dev, reg, CON_CTL_RCM) reg 211 drivers/atm/he.c #define he_readl_tcm(dev, reg) \ reg 212 drivers/atm/he.c he_readl_internal(dev, reg, CON_CTL_TCM) reg 214 drivers/atm/he.c #define he_readl_mbox(dev, reg) \ reg 215 drivers/atm/he.c he_readl_internal(dev, reg, CON_CTL_MBOX) reg 558 drivers/atm/he.c int reg; reg 562 drivers/atm/he.c for (reg = 0; reg < 0x20; ++reg) reg 563 drivers/atm/he.c he_writel_mbox(he_dev, 0x0, CS_STTIM0 + reg); reg 571 drivers/atm/he.c for (reg = 0; reg < 0x10; ++reg) { reg 579 drivers/atm/he.c he_writel_mbox(he_dev, period, CS_TGRLD0 + reg); reg 645 drivers/atm/he.c for (reg = 0; reg < 0x8; ++reg) reg 646 drivers/atm/he.c he_writel_mbox(he_dev, 0x0, CS_HGRRT0 + reg); reg 654 drivers/atm/he.c int i, j, reg; reg 666 drivers/atm/he.c for (reg = 0x0; reg < 0xff; ++reg) reg 667 drivers/atm/he.c he_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg); reg 671 drivers/atm/he.c for (reg = 0x100; reg < 0x1ff; ++reg) reg 672 drivers/atm/he.c he_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg); reg 755 drivers/atm/he.c reg = (reg << 16) | ((i << 8) | buf); reg 760 drivers/atm/he.c he_writel_rcm(he_dev, reg, reg 984 drivers/atm/he.c unsigned int status, reg; reg 1496 drivers/atm/he.c reg = he_readl_mbox(he_dev, CS_ERCTL0); reg 1497 drivers/atm/he.c reg |= TX_ENABLE|ER_ENABLE; reg 1498 drivers/atm/he.c he_writel_mbox(he_dev, reg, CS_ERCTL0); reg 1500 drivers/atm/he.c reg = he_readl(he_dev, RC_CONFIG); reg 1501 drivers/atm/he.c reg |= RX_ENABLE; reg 1502 drivers/atm/he.c he_writel(he_dev, reg, RC_CONFIG); reg 1531 drivers/atm/he.c u32 gen_cntl_0, reg; reg 1547 drivers/atm/he.c reg = he_readl_mbox(he_dev, CS_ERCTL0); reg 1548 drivers/atm/he.c reg &= ~(TX_ENABLE|ER_ENABLE); reg 1549 drivers/atm/he.c he_writel_mbox(he_dev, reg, CS_ERCTL0); reg 1551 drivers/atm/he.c reg = he_readl(he_dev, RC_CONFIG); reg 1552 drivers/atm/he.c reg &= ~(RX_ENABLE); reg 1553 drivers/atm/he.c he_writel(he_dev, reg, RC_CONFIG); reg 2124 drivers/atm/he.c unsigned cid, rsr0, rsr1, rsr4, tsr0, tsr0_aal, tsr4, period, reg, clock; reg 2209 drivers/atm/he.c for (reg = 0; reg < HE_NUM_CS_STPER; ++reg) reg 2210 drivers/atm/he.c if (he_dev->cs_stper[reg].inuse == 0 || reg 2211 drivers/atm/he.c he_dev->cs_stper[reg].pcr == pcr_goal) reg 2214 drivers/atm/he.c if (reg == HE_NUM_CS_STPER) { reg 2222 drivers/atm/he.c he_vcc->rc_index = reg; reg 2223 drivers/atm/he.c ++he_dev->cs_stper[reg].inuse; reg 2224 drivers/atm/he.c he_dev->cs_stper[reg].pcr = pcr_goal; reg 2230 drivers/atm/he.c reg, period); reg 2233 drivers/atm/he.c CS_STPER0 + reg); reg 2237 drivers/atm/he.c TSR0_RC_INDEX(reg); reg 2467 drivers/atm/he.c int reg = he_vcc->rc_index; reg 2469 drivers/atm/he.c HPRINTK("cs_stper reg = %d\n", reg); reg 2471 drivers/atm/he.c if (he_dev->cs_stper[reg].inuse == 0) reg 2472 drivers/atm/he.c hprintk("cs_stper[%d].inuse = 0!\n", reg); reg 2474 drivers/atm/he.c --he_dev->cs_stper[reg].inuse; reg 2476 drivers/atm/he.c he_dev->total_bw -= he_dev->cs_stper[reg].pcr; reg 2615 drivers/atm/he.c struct he_ioctl_reg reg; reg 2623 drivers/atm/he.c if (copy_from_user(®, arg, reg 2628 drivers/atm/he.c switch (reg.type) { reg 2630 drivers/atm/he.c if (reg.addr >= HE_REGMAP_SIZE) { reg 2635 drivers/atm/he.c reg.val = he_readl(he_dev, reg.addr); reg 2638 drivers/atm/he.c reg.val = reg 2639 drivers/atm/he.c he_readl_rcm(he_dev, reg.addr); reg 2642 drivers/atm/he.c reg.val = reg 2643 drivers/atm/he.c he_readl_tcm(he_dev, reg.addr); reg 2646 drivers/atm/he.c reg.val = reg 2647 drivers/atm/he.c he_readl_mbox(he_dev, reg.addr); reg 2655 drivers/atm/he.c if (copy_to_user(arg, ®, reg 2692 drivers/atm/he.c unsigned reg; reg 2695 drivers/atm/he.c reg = he_readl(he_dev, FRAMER + (addr*4)); reg 2698 drivers/atm/he.c HPRINTK("phy_get(addr 0x%lx) =0x%x\n", addr, reg); reg 2699 drivers/atm/he.c return reg; reg 356 drivers/atm/horizon.c static inline void wr_regl (const hrz_dev * dev, unsigned char reg, u32 data) { reg 357 drivers/atm/horizon.c outl (cpu_to_le32 (data), dev->iobase + reg); reg 360 drivers/atm/horizon.c static inline u32 rd_regl (const hrz_dev * dev, unsigned char reg) { reg 361 drivers/atm/horizon.c return le32_to_cpu (inl (dev->iobase + reg)); reg 364 drivers/atm/horizon.c static inline void wr_regw (const hrz_dev * dev, unsigned char reg, u16 data) { reg 365 drivers/atm/horizon.c outw (cpu_to_le16 (data), dev->iobase + reg); reg 368 drivers/atm/horizon.c static inline u16 rd_regw (const hrz_dev * dev, unsigned char reg) { reg 369 drivers/atm/horizon.c return le16_to_cpu (inw (dev->iobase + reg)); reg 372 drivers/atm/horizon.c static inline void wrs_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) { reg 373 drivers/atm/horizon.c outsb (dev->iobase + reg, addr, len); reg 376 drivers/atm/horizon.c static inline void rds_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) { reg 377 drivers/atm/horizon.c insb (dev->iobase + reg, addr, len); reg 46 drivers/atm/idt77105.c #define PUT(val,reg) dev->ops->phy_put(dev,val,IDT77105_##reg) reg 47 drivers/atm/idt77105.c #define GET(reg) dev->ops->phy_get(dev,IDT77105_##reg) reg 723 drivers/atm/iphase.c t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); reg 725 drivers/atm/iphase.c t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); reg 822 drivers/atm/iphase.c static u32 ia_phy_read32(struct iadev_priv *ia, unsigned int reg) reg 824 drivers/atm/iphase.c return readl(ia->phy + (reg >> 2)); reg 827 drivers/atm/iphase.c static void ia_phy_write32(struct iadev_priv *ia, unsigned int reg, u32 val) reg 829 drivers/atm/iphase.c writel(val, ia->phy + (reg >> 2)); reg 869 drivers/atm/iphase.c u16 reg; reg 877 drivers/atm/iphase.c ia_phy_write32(iadev, regs->reg, regs->val); reg 2231 drivers/atm/iphase.c while( (status = readl(iadev->reg+IPHASE5575_BUS_STATUS_REG) & 0x7f)) reg 2244 drivers/atm/iphase.c writel(STAT_DLERINT, iadev->reg + IPHASE5575_BUS_STATUS_REG); reg 2255 drivers/atm/iphase.c writel(STAT_DLETINT, iadev->reg + IPHASE5575_BUS_STATUS_REG); reg 2279 drivers/atm/iphase.c iadev->reg+IPHASE5575_MAC1))); reg 2280 drivers/atm/iphase.c mac2 = cpu_to_be16(le16_to_cpu(readl(iadev->reg+IPHASE5575_MAC2))); reg 2301 drivers/atm/iphase.c writel(0, iadev->reg+IPHASE5575_EXT_RESET); reg 2385 drivers/atm/iphase.c iadev->reg = base + REG_BASE; reg 2400 drivers/atm/iphase.c iadev->reg,iadev->seg_reg,iadev->reass_reg, reg 2443 drivers/atm/iphase.c ctrl_reg = readl(ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG); reg 2447 drivers/atm/iphase.c writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG); reg 2453 drivers/atm/iphase.c writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG); reg 2535 drivers/atm/iphase.c readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));) reg 2536 drivers/atm/iphase.c ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG); reg 2552 drivers/atm/iphase.c writel(ctrl_reg, iadev->reg+IPHASE5575_BUS_CONTROL_REG); reg 2555 drivers/atm/iphase.c readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG)); reg 2557 drivers/atm/iphase.c readl(iadev->reg+IPHASE5575_BUS_STATUS_REG));) reg 2567 drivers/atm/iphase.c ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG); reg 2568 drivers/atm/iphase.c writel(ctrl_reg | CTRL_FE_RST, iadev->reg+IPHASE5575_BUS_CONTROL_REG); reg 2570 drivers/atm/iphase.c readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));) reg 992 drivers/atm/iphase.h u32 __iomem *reg; /* Base pointer to SAR registers. */ reg 1375 drivers/atm/iphase.h t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \ reg 1377 drivers/atm/iphase.h writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \ reg 1389 drivers/atm/iphase.h t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \ reg 1391 drivers/atm/iphase.h writel(t, iadev->reg+IPHASE5575_EEPROM_ACCESS); \ reg 1448 drivers/atm/iphase.h _t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS); \ reg 469 drivers/atm/lanai.c enum lanai_register reg) reg 471 drivers/atm/lanai.c return lanai->base + reg; reg 475 drivers/atm/lanai.c enum lanai_register reg) reg 478 drivers/atm/lanai.c t = readl(reg_addr(lanai, reg)); reg 480 drivers/atm/lanai.c (int) reg, t); reg 485 drivers/atm/lanai.c enum lanai_register reg) reg 488 drivers/atm/lanai.c (int) reg, val); reg 489 drivers/atm/lanai.c writel(val, reg_addr(lanai, reg)); reg 109 drivers/atm/nicstarmac.c #define NICSTAR_REG_WRITE(bs, reg, val) \ reg 111 drivers/atm/nicstarmac.c writel((val),(base)+(reg)) reg 112 drivers/atm/nicstarmac.c #define NICSTAR_REG_READ(bs, reg) \ reg 113 drivers/atm/nicstarmac.c readl((base)+(reg)) reg 41 drivers/atm/suni.c #define PUT(val,reg) dev->ops->phy_put(dev,val,SUNI_##reg) reg 42 drivers/atm/suni.c #define GET(reg) dev->ops->phy_get(dev,SUNI_##reg) reg 43 drivers/atm/suni.c #define REG_CHANGE(mask,shift,value,reg) \ reg 44 drivers/atm/suni.c PUT((GET(reg) & ~(mask)) | ((value) << (shift)),reg) reg 108 drivers/atm/suni.c #define HANDLE_FLAG(flag,reg,bit) \ reg 110 drivers/atm/suni.c if (set) PUT(GET(reg) | bit,reg); \ reg 111 drivers/atm/suni.c else PUT(GET(reg) & ~bit,reg); \ reg 156 drivers/atm/suni.c int reg, dle, lle; reg 159 drivers/atm/suni.c reg = SUNI_MCM; reg 163 drivers/atm/suni.c reg = SUNI_MCT; reg 168 drivers/atm/suni.c control = dev->ops->phy_get(dev, reg) & ~(dle | lle); reg 181 drivers/atm/suni.c dev->ops->phy_put(dev, control, reg); reg 37 drivers/atm/uPD98402.c #define PUT(val,reg) dev->ops->phy_put(dev,val,uPD98402_##reg) reg 38 drivers/atm/uPD98402.c #define GET(reg) dev->ops->phy_get(dev,uPD98402_##reg) reg 36 drivers/base/regmap/internal.h unsigned int reg, unsigned int val); reg 37 drivers/base/regmap/internal.h void (*format_reg)(void *buf, unsigned int reg, unsigned int shift); reg 90 drivers/base/regmap/internal.h bool (*writeable_reg)(struct device *dev, unsigned int reg); reg 91 drivers/base/regmap/internal.h bool (*readable_reg)(struct device *dev, unsigned int reg); reg 92 drivers/base/regmap/internal.h bool (*volatile_reg)(struct device *dev, unsigned int reg); reg 93 drivers/base/regmap/internal.h bool (*precious_reg)(struct device *dev, unsigned int reg); reg 94 drivers/base/regmap/internal.h bool (*writeable_noinc_reg)(struct device *dev, unsigned int reg); reg 95 drivers/base/regmap/internal.h bool (*readable_noinc_reg)(struct device *dev, unsigned int reg); reg 103 drivers/base/regmap/internal.h int (*reg_read)(void *context, unsigned int reg, unsigned int *val); reg 104 drivers/base/regmap/internal.h int (*reg_write)(void *context, unsigned int reg, unsigned int val); reg 105 drivers/base/regmap/internal.h int (*reg_update_bits)(void *context, unsigned int reg, reg 174 drivers/base/regmap/internal.h int (*read)(struct regmap *map, unsigned int reg, unsigned int *value); reg 175 drivers/base/regmap/internal.h int (*write)(struct regmap *map, unsigned int reg, unsigned int value); reg 180 drivers/base/regmap/internal.h bool regmap_cached(struct regmap *map, unsigned int reg); reg 181 drivers/base/regmap/internal.h bool regmap_writeable(struct regmap *map, unsigned int reg); reg 182 drivers/base/regmap/internal.h bool regmap_readable(struct regmap *map, unsigned int reg); reg 183 drivers/base/regmap/internal.h bool regmap_volatile(struct regmap *map, unsigned int reg); reg 184 drivers/base/regmap/internal.h bool regmap_precious(struct regmap *map, unsigned int reg); reg 185 drivers/base/regmap/internal.h bool regmap_writeable_noinc(struct regmap *map, unsigned int reg); reg 186 drivers/base/regmap/internal.h bool regmap_readable_noinc(struct regmap *map, unsigned int reg); reg 188 drivers/base/regmap/internal.h int _regmap_write(struct regmap *map, unsigned int reg, reg 212 drivers/base/regmap/internal.h unsigned int reg; reg 239 drivers/base/regmap/internal.h unsigned int reg, unsigned int *value); reg 241 drivers/base/regmap/internal.h unsigned int reg, unsigned int value); reg 259 drivers/base/regmap/internal.h int regcache_lookup_reg(struct regmap *map, unsigned int reg); reg 261 drivers/base/regmap/internal.h int _regmap_raw_write(struct regmap *map, unsigned int reg, reg 292 drivers/base/regmap/internal.h unsigned int reg) reg 294 drivers/base/regmap/internal.h return reg >> map->reg_stride_order; reg 16 drivers/base/regmap/regcache-flat.c unsigned int reg) reg 18 drivers/base/regmap/regcache-flat.c return regcache_get_index_by_order(map, reg); reg 37 drivers/base/regmap/regcache-flat.c unsigned int reg = map->reg_defaults[i].reg; reg 38 drivers/base/regmap/regcache-flat.c unsigned int index = regcache_flat_get_index(map, reg); reg 55 drivers/base/regmap/regcache-flat.c unsigned int reg, unsigned int *value) reg 58 drivers/base/regmap/regcache-flat.c unsigned int index = regcache_flat_get_index(map, reg); reg 65 drivers/base/regmap/regcache-flat.c static int regcache_flat_write(struct regmap *map, unsigned int reg, reg 69 drivers/base/regmap/regcache-flat.c unsigned int index = regcache_flat_get_index(map, reg); reg 105 drivers/base/regmap/regcache-lzo.c unsigned int reg) reg 107 drivers/base/regmap/regcache-lzo.c return ((reg / map->reg_stride) * map->cache_word_size) / reg 113 drivers/base/regmap/regcache-lzo.c unsigned int reg) reg 115 drivers/base/regmap/regcache-lzo.c return (reg / map->reg_stride) % reg 229 drivers/base/regmap/regcache-lzo.c unsigned int reg, unsigned int *value) reg 237 drivers/base/regmap/regcache-lzo.c blkindex = regcache_lzo_get_blkindex(map, reg); reg 239 drivers/base/regmap/regcache-lzo.c blkpos = regcache_lzo_get_blkpos(map, reg); reg 266 drivers/base/regmap/regcache-lzo.c unsigned int reg, unsigned int value) reg 274 drivers/base/regmap/regcache-lzo.c blkindex = regcache_lzo_get_blkindex(map, reg); reg 276 drivers/base/regmap/regcache-lzo.c blkpos = regcache_lzo_get_blkpos(map, reg); reg 314 drivers/base/regmap/regcache-lzo.c set_bit(reg / map->reg_stride, lzo_block->sync_bmp); reg 17 drivers/base/regmap/regcache-rbtree.c static int regcache_rbtree_write(struct regmap *map, unsigned int reg, reg 63 drivers/base/regmap/regcache-rbtree.c unsigned int reg) reg 74 drivers/base/regmap/regcache-rbtree.c if (reg >= base_reg && reg <= top_reg) reg 83 drivers/base/regmap/regcache-rbtree.c if (reg >= base_reg && reg <= top_reg) { reg 86 drivers/base/regmap/regcache-rbtree.c } else if (reg > top_reg) { reg 88 drivers/base/regmap/regcache-rbtree.c } else if (reg < base_reg) { reg 200 drivers/base/regmap/regcache-rbtree.c map->reg_defaults[i].reg, reg 243 drivers/base/regmap/regcache-rbtree.c unsigned int reg, unsigned int *value) reg 248 drivers/base/regmap/regcache-rbtree.c rbnode = regcache_rbtree_lookup(map, reg); reg 250 drivers/base/regmap/regcache-rbtree.c reg_tmp = (reg - rbnode->base_reg) / map->reg_stride; reg 266 drivers/base/regmap/regcache-rbtree.c unsigned int reg, reg 275 drivers/base/regmap/regcache-rbtree.c pos = (reg - base_reg) / map->reg_stride; reg 318 drivers/base/regmap/regcache-rbtree.c regcache_rbtree_node_alloc(struct regmap *map, unsigned int reg) reg 331 drivers/base/regmap/regcache-rbtree.c if (regmap_reg_in_range(reg, reg 346 drivers/base/regmap/regcache-rbtree.c rbnode->base_reg = reg; reg 369 drivers/base/regmap/regcache-rbtree.c static int regcache_rbtree_write(struct regmap *map, unsigned int reg, reg 383 drivers/base/regmap/regcache-rbtree.c rbnode = regcache_rbtree_lookup(map, reg); reg 385 drivers/base/regmap/regcache-rbtree.c reg_tmp = (reg - rbnode->base_reg) / map->reg_stride; reg 396 drivers/base/regmap/regcache-rbtree.c if (reg < max_dist) reg 399 drivers/base/regmap/regcache-rbtree.c min = reg - max_dist; reg 400 drivers/base/regmap/regcache-rbtree.c max = reg + max_dist; reg 412 drivers/base/regmap/regcache-rbtree.c if (reg < base_reg) reg 413 drivers/base/regmap/regcache-rbtree.c dist = base_reg - reg; reg 414 drivers/base/regmap/regcache-rbtree.c else if (reg > top_reg) reg 415 drivers/base/regmap/regcache-rbtree.c dist = reg - top_reg; reg 421 drivers/base/regmap/regcache-rbtree.c new_base_reg = min(reg, base_reg); reg 422 drivers/base/regmap/regcache-rbtree.c new_top_reg = max(reg, top_reg); reg 431 drivers/base/regmap/regcache-rbtree.c if (reg < base_reg) reg 433 drivers/base/regmap/regcache-rbtree.c else if (reg > top_reg) reg 442 drivers/base/regmap/regcache-rbtree.c new_top_reg, reg, reg 453 drivers/base/regmap/regcache-rbtree.c rbnode = regcache_rbtree_node_alloc(map, reg); reg 457 drivers/base/regmap/regcache-rbtree.c reg - rbnode->base_reg, value); reg 31 drivers/base/regmap/regcache.c unsigned int reg, val; reg 79 drivers/base/regmap/regcache.c reg = i * map->reg_stride; reg 81 drivers/base/regmap/regcache.c if (!regmap_readable(map, reg)) reg 84 drivers/base/regmap/regcache.c if (regmap_volatile(map, reg)) reg 93 drivers/base/regmap/regcache.c ret = regmap_read(map, reg, &val); reg 97 drivers/base/regmap/regcache.c reg, ret); reg 102 drivers/base/regmap/regcache.c map->reg_defaults[j].reg = reg; reg 137 drivers/base/regmap/regcache.c if (config->reg_defaults[i].reg % map->reg_stride) reg 234 drivers/base/regmap/regcache.c unsigned int reg, unsigned int *value) reg 243 drivers/base/regmap/regcache.c if (!regmap_volatile(map, reg)) { reg 244 drivers/base/regmap/regcache.c ret = map->cache_ops->read(map, reg, value); reg 247 drivers/base/regmap/regcache.c trace_regmap_reg_read_cache(map, reg, *value); reg 265 drivers/base/regmap/regcache.c unsigned int reg, unsigned int value) reg 272 drivers/base/regmap/regcache.c if (!regmap_volatile(map, reg)) reg 273 drivers/base/regmap/regcache.c return map->cache_ops->write(map, reg, value); reg 278 drivers/base/regmap/regcache.c static bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg, reg 288 drivers/base/regmap/regcache.c ret = regcache_lookup_reg(map, reg); reg 297 drivers/base/regmap/regcache.c unsigned int reg; reg 299 drivers/base/regmap/regcache.c for (reg = min; reg <= max; reg += map->reg_stride) { reg 303 drivers/base/regmap/regcache.c if (regmap_volatile(map, reg) || reg 304 drivers/base/regmap/regcache.c !regmap_writeable(map, reg)) reg 307 drivers/base/regmap/regcache.c ret = regcache_read(map, reg, &val); reg 311 drivers/base/regmap/regcache.c if (!regcache_reg_needs_sync(map, reg, val)) reg 315 drivers/base/regmap/regcache.c ret = _regmap_write(map, reg, val); reg 319 drivers/base/regmap/regcache.c reg, ret); reg 322 drivers/base/regmap/regcache.c dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val); reg 364 drivers/base/regmap/regcache.c ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def); reg 367 drivers/base/regmap/regcache.c map->patch[i].reg, map->patch[i].def, ret); reg 640 drivers/base/regmap/regcache.c return _a->reg - _b->reg; reg 643 drivers/base/regmap/regcache.c int regcache_lookup_reg(struct regmap *map, unsigned int reg) reg 648 drivers/base/regmap/regcache.c key.reg = reg; reg 17 drivers/base/regmap/regmap-ac97.c bool regmap_ac97_default_volatile(struct device *dev, unsigned int reg) reg 19 drivers/base/regmap/regmap-ac97.c switch (reg) { reg 44 drivers/base/regmap/regmap-ac97.c static int regmap_ac97_reg_read(void *context, unsigned int reg, reg 49 drivers/base/regmap/regmap-ac97.c *val = ac97->bus->ops->read(ac97, reg); reg 54 drivers/base/regmap/regmap-ac97.c static int regmap_ac97_reg_write(void *context, unsigned int reg, reg 59 drivers/base/regmap/regmap-ac97.c ac97->bus->ops->write(ac97, reg, val); reg 81 drivers/base/regmap/regmap-debugfs.c static bool regmap_printable(struct regmap *map, unsigned int reg) reg 83 drivers/base/regmap/regmap-debugfs.c if (regmap_precious(map, reg)) reg 86 drivers/base/regmap/regmap-debugfs.c if (!regmap_readable(map, reg) && !regmap_cached(map, reg)) reg 194 drivers/base/regmap/regmap-debugfs.c static int regmap_next_readable_reg(struct regmap *map, int reg) reg 199 drivers/base/regmap/regmap-debugfs.c if (regmap_printable(map, reg + map->reg_stride)) { reg 200 drivers/base/regmap/regmap-debugfs.c ret = reg + map->reg_stride; reg 204 drivers/base/regmap/regmap-debugfs.c if (reg > c->max_reg) reg 206 drivers/base/regmap/regmap-debugfs.c if (reg < c->base_reg) { reg 306 drivers/base/regmap/regmap-debugfs.c unsigned long reg, value; reg 317 drivers/base/regmap/regmap-debugfs.c reg = simple_strtoul(start, &start, 16); reg 326 drivers/base/regmap/regmap-debugfs.c ret = regmap_write(map, reg, value); reg 15 drivers/base/regmap/regmap-i2c.c static int regmap_smbus_byte_reg_read(void *context, unsigned int reg, reg 22 drivers/base/regmap/regmap-i2c.c if (reg > 0xff) reg 25 drivers/base/regmap/regmap-i2c.c ret = i2c_smbus_read_byte_data(i2c, reg); reg 34 drivers/base/regmap/regmap-i2c.c static int regmap_smbus_byte_reg_write(void *context, unsigned int reg, reg 40 drivers/base/regmap/regmap-i2c.c if (val > 0xff || reg > 0xff) reg 43 drivers/base/regmap/regmap-i2c.c return i2c_smbus_write_byte_data(i2c, reg, val); reg 51 drivers/base/regmap/regmap-i2c.c static int regmap_smbus_word_reg_read(void *context, unsigned int reg, reg 58 drivers/base/regmap/regmap-i2c.c if (reg > 0xff) reg 61 drivers/base/regmap/regmap-i2c.c ret = i2c_smbus_read_word_data(i2c, reg); reg 70 drivers/base/regmap/regmap-i2c.c static int regmap_smbus_word_reg_write(void *context, unsigned int reg, reg 76 drivers/base/regmap/regmap-i2c.c if (val > 0xffff || reg > 0xff) reg 79 drivers/base/regmap/regmap-i2c.c return i2c_smbus_write_word_data(i2c, reg, val); reg 87 drivers/base/regmap/regmap-i2c.c static int regmap_smbus_word_read_swapped(void *context, unsigned int reg, reg 94 drivers/base/regmap/regmap-i2c.c if (reg > 0xff) reg 97 drivers/base/regmap/regmap-i2c.c ret = i2c_smbus_read_word_swapped(i2c, reg); reg 106 drivers/base/regmap/regmap-i2c.c static int regmap_smbus_word_write_swapped(void *context, unsigned int reg, reg 112 drivers/base/regmap/regmap-i2c.c if (val > 0xffff || reg > 0xff) reg 115 drivers/base/regmap/regmap-i2c.c return i2c_smbus_write_word_swapped(i2c, reg, val); reg 139 drivers/base/regmap/regmap-i2c.c const void *reg, size_t reg_size, reg 156 drivers/base/regmap/regmap-i2c.c xfer[0].buf = (void *)reg; reg 173 drivers/base/regmap/regmap-i2c.c const void *reg, size_t reg_size, reg 184 drivers/base/regmap/regmap-i2c.c xfer[0].buf = (void *)reg; reg 222 drivers/base/regmap/regmap-i2c.c static int regmap_i2c_smbus_i2c_read(void *context, const void *reg, reg 233 drivers/base/regmap/regmap-i2c.c ret = i2c_smbus_read_i2c_block_data(i2c, ((u8 *)reg)[0], val_size, val); reg 25 drivers/base/regmap/regmap-i3c.c const void *reg, size_t reg_size, reg 34 drivers/base/regmap/regmap-i3c.c xfers[0].data.out = reg; reg 63 drivers/base/regmap/regmap-irq.c unsigned int reg, unsigned int mask, reg 67 drivers/base/regmap/regmap-irq.c return regmap_write_bits(d->map, reg, mask, val); reg 69 drivers/base/regmap/regmap-irq.c return regmap_update_bits(d->map, reg, mask, val); reg 77 drivers/base/regmap/regmap-irq.c u32 reg; reg 90 drivers/base/regmap/regmap-irq.c reg = d->chip->status_base + reg 93 drivers/base/regmap/regmap-irq.c ret = regmap_read(map, reg, &val); reg 111 drivers/base/regmap/regmap-irq.c reg = d->chip->mask_base + reg 114 drivers/base/regmap/regmap-irq.c ret = regmap_irq_update_bits(d, reg, reg 118 drivers/base/regmap/regmap-irq.c ret = regmap_irq_update_bits(d, reg, reg 123 drivers/base/regmap/regmap-irq.c reg); reg 128 drivers/base/regmap/regmap-irq.c reg + unmask_offset, reg 132 drivers/base/regmap/regmap-irq.c ret = regmap_irq_update_bits(d, reg, reg 137 drivers/base/regmap/regmap-irq.c reg); reg 139 drivers/base/regmap/regmap-irq.c reg = d->chip->wake_base + reg 143 drivers/base/regmap/regmap-irq.c ret = regmap_irq_update_bits(d, reg, reg 147 drivers/base/regmap/regmap-irq.c ret = regmap_irq_update_bits(d, reg, reg 153 drivers/base/regmap/regmap-irq.c reg, ret); reg 164 drivers/base/regmap/regmap-irq.c reg = d->chip->ack_base + reg 168 drivers/base/regmap/regmap-irq.c ret = regmap_write(map, reg, ~d->mask_buf[i]); reg 170 drivers/base/regmap/regmap-irq.c ret = regmap_write(map, reg, d->mask_buf[i]); reg 173 drivers/base/regmap/regmap-irq.c reg, ret); reg 182 drivers/base/regmap/regmap-irq.c reg = d->chip->type_base + reg 185 drivers/base/regmap/regmap-irq.c ret = regmap_irq_update_bits(d, reg, reg 188 drivers/base/regmap/regmap-irq.c ret = regmap_irq_update_bits(d, reg, reg 192 drivers/base/regmap/regmap-irq.c reg); reg 257 drivers/base/regmap/regmap-irq.c int reg; reg 263 drivers/base/regmap/regmap-irq.c reg = t->type_reg_offset / map->reg_stride; reg 266 drivers/base/regmap/regmap-irq.c d->type_buf[reg] &= ~t->type_reg_mask; reg 268 drivers/base/regmap/regmap-irq.c d->type_buf[reg] &= ~(t->type_falling_val | reg 274 drivers/base/regmap/regmap-irq.c d->type_buf[reg] |= t->type_falling_val; reg 278 drivers/base/regmap/regmap-irq.c d->type_buf[reg] |= t->type_rising_val; reg 282 drivers/base/regmap/regmap-irq.c d->type_buf[reg] |= (t->type_falling_val | reg 287 drivers/base/regmap/regmap-irq.c d->type_buf[reg] |= t->type_level_high_val; reg 291 drivers/base/regmap/regmap-irq.c d->type_buf[reg] |= t->type_level_low_val; reg 363 drivers/base/regmap/regmap-irq.c u32 reg; reg 494 drivers/base/regmap/regmap-irq.c reg = chip->ack_base + reg 496 drivers/base/regmap/regmap-irq.c ret = regmap_write(map, reg, data->status_buf[i]); reg 499 drivers/base/regmap/regmap-irq.c reg, ret); reg 567 drivers/base/regmap/regmap-irq.c u32 reg; reg 679 drivers/base/regmap/regmap-irq.c reg = chip->mask_base + reg 682 drivers/base/regmap/regmap-irq.c ret = regmap_irq_update_bits(d, reg, reg 688 drivers/base/regmap/regmap-irq.c reg + unmask_offset, reg 692 drivers/base/regmap/regmap-irq.c ret = regmap_irq_update_bits(d, reg, reg 696 drivers/base/regmap/regmap-irq.c reg, ret); reg 704 drivers/base/regmap/regmap-irq.c reg = chip->status_base + reg 706 drivers/base/regmap/regmap-irq.c ret = regmap_read(map, reg, &d->status_buf[i]); reg 714 drivers/base/regmap/regmap-irq.c reg = chip->ack_base + reg 717 drivers/base/regmap/regmap-irq.c ret = regmap_write(map, reg, reg 720 drivers/base/regmap/regmap-irq.c ret = regmap_write(map, reg, reg 724 drivers/base/regmap/regmap-irq.c reg, ret); reg 734 drivers/base/regmap/regmap-irq.c reg = chip->wake_base + reg 738 drivers/base/regmap/regmap-irq.c ret = regmap_irq_update_bits(d, reg, reg 742 drivers/base/regmap/regmap-irq.c ret = regmap_irq_update_bits(d, reg, reg 747 drivers/base/regmap/regmap-irq.c reg, ret); reg 755 drivers/base/regmap/regmap-irq.c reg = chip->type_base + reg 758 drivers/base/regmap/regmap-irq.c ret = regmap_read(map, reg, &d->type_buf_def[i]); reg 765 drivers/base/regmap/regmap-irq.c reg, ret); reg 24 drivers/base/regmap/regmap-mmio.c unsigned int reg, unsigned int val); reg 26 drivers/base/regmap/regmap-mmio.c unsigned int reg); reg 72 drivers/base/regmap/regmap-mmio.c unsigned int reg, reg 75 drivers/base/regmap/regmap-mmio.c writeb(val, ctx->regs + reg); reg 79 drivers/base/regmap/regmap-mmio.c unsigned int reg, reg 82 drivers/base/regmap/regmap-mmio.c writew(val, ctx->regs + reg); reg 86 drivers/base/regmap/regmap-mmio.c unsigned int reg, reg 89 drivers/base/regmap/regmap-mmio.c iowrite16be(val, ctx->regs + reg); reg 93 drivers/base/regmap/regmap-mmio.c unsigned int reg, reg 96 drivers/base/regmap/regmap-mmio.c writel(val, ctx->regs + reg); reg 100 drivers/base/regmap/regmap-mmio.c unsigned int reg, reg 103 drivers/base/regmap/regmap-mmio.c iowrite32be(val, ctx->regs + reg); reg 108 drivers/base/regmap/regmap-mmio.c unsigned int reg, reg 111 drivers/base/regmap/regmap-mmio.c writeq(val, ctx->regs + reg); reg 115 drivers/base/regmap/regmap-mmio.c static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val) reg 126 drivers/base/regmap/regmap-mmio.c ctx->reg_write(ctx, reg, val); reg 135 drivers/base/regmap/regmap-mmio.c unsigned int reg) reg 137 drivers/base/regmap/regmap-mmio.c return readb(ctx->regs + reg); reg 141 drivers/base/regmap/regmap-mmio.c unsigned int reg) reg 143 drivers/base/regmap/regmap-mmio.c return readw(ctx->regs + reg); reg 147 drivers/base/regmap/regmap-mmio.c unsigned int reg) reg 149 drivers/base/regmap/regmap-mmio.c return ioread16be(ctx->regs + reg); reg 153 drivers/base/regmap/regmap-mmio.c unsigned int reg) reg 155 drivers/base/regmap/regmap-mmio.c return readl(ctx->regs + reg); reg 159 drivers/base/regmap/regmap-mmio.c unsigned int reg) reg 161 drivers/base/regmap/regmap-mmio.c return ioread32be(ctx->regs + reg); reg 166 drivers/base/regmap/regmap-mmio.c unsigned int reg) reg 168 drivers/base/regmap/regmap-mmio.c return readq(ctx->regs + reg); reg 172 drivers/base/regmap/regmap-mmio.c static int regmap_mmio_read(void *context, unsigned int reg, unsigned int *val) reg 183 drivers/base/regmap/regmap-mmio.c *val = ctx->reg_read(ctx, reg); reg 40 drivers/base/regmap/regmap-sccb.c static int regmap_sccb_read(void *context, unsigned int reg, unsigned int *val) reg 50 drivers/base/regmap/regmap-sccb.c I2C_SMBUS_WRITE, reg, I2C_SMBUS_BYTE, NULL); reg 75 drivers/base/regmap/regmap-sccb.c static int regmap_sccb_write(void *context, unsigned int reg, unsigned int val) reg 80 drivers/base/regmap/regmap-sccb.c return i2c_smbus_write_byte_data(i2c, reg, val); reg 10 drivers/base/regmap/regmap-sdw.c static int regmap_sdw_write(void *context, unsigned int reg, unsigned int val) reg 15 drivers/base/regmap/regmap-sdw.c return sdw_write(slave, reg, val); reg 18 drivers/base/regmap/regmap-sdw.c static int regmap_sdw_read(void *context, unsigned int reg, unsigned int *val) reg 24 drivers/base/regmap/regmap-sdw.c read = sdw_read(slave, reg); reg 17 drivers/base/regmap/regmap-slimbus.c static int regmap_slimbus_read(void *context, const void *reg, size_t reg_size, reg 22 drivers/base/regmap/regmap-slimbus.c return slim_read(sdev, *(u16 *)reg, val_size, val); reg 37 drivers/base/regmap/regmap-spi.c const void *reg, size_t reg_len, reg 43 drivers/base/regmap/regmap-spi.c struct spi_transfer t[2] = { { .tx_buf = reg, .len = reg_len, }, reg 54 drivers/base/regmap/regmap-spi.c const void *reg, size_t reg_len, reg 64 drivers/base/regmap/regmap-spi.c async->t[0].tx_buf = reg; reg 92 drivers/base/regmap/regmap-spi.c const void *reg, size_t reg_size, reg 98 drivers/base/regmap/regmap-spi.c return spi_write_then_read(spi, reg, reg_size, val, val_size); reg 17 drivers/base/regmap/regmap-spmi.c const void *reg, size_t reg_size, reg 20 drivers/base/regmap/regmap-spmi.c u8 addr = *(u8 *)reg; reg 32 drivers/base/regmap/regmap-spmi.c const void *reg, size_t reg_size, reg 36 drivers/base/regmap/regmap-spmi.c u8 addr = *(u8 *)reg; reg 106 drivers/base/regmap/regmap-spmi.c const void *reg, size_t reg_size, reg 115 drivers/base/regmap/regmap-spmi.c addr = *(u16 *)reg; reg 150 drivers/base/regmap/regmap-spmi.c const void *reg, size_t reg_size, reg 159 drivers/base/regmap/regmap-spmi.c addr = *(u16 *)reg; reg 21 drivers/base/regmap/regmap-w1.c static int w1_reg_a8_v8_read(void *context, unsigned int reg, unsigned int *val) reg 27 drivers/base/regmap/regmap-w1.c if (reg > 255) reg 33 drivers/base/regmap/regmap-w1.c w1_write_8(sl->master, reg); reg 43 drivers/base/regmap/regmap-w1.c static int w1_reg_a8_v8_write(void *context, unsigned int reg, unsigned int val) reg 49 drivers/base/regmap/regmap-w1.c if (reg > 255) reg 55 drivers/base/regmap/regmap-w1.c w1_write_8(sl->master, reg); reg 69 drivers/base/regmap/regmap-w1.c static int w1_reg_a8_v16_read(void *context, unsigned int reg, reg 76 drivers/base/regmap/regmap-w1.c if (reg > 255) reg 82 drivers/base/regmap/regmap-w1.c w1_write_8(sl->master, reg); reg 93 drivers/base/regmap/regmap-w1.c static int w1_reg_a8_v16_write(void *context, unsigned int reg, reg 100 drivers/base/regmap/regmap-w1.c if (reg > 255) reg 106 drivers/base/regmap/regmap-w1.c w1_write_8(sl->master, reg); reg 121 drivers/base/regmap/regmap-w1.c static int w1_reg_a16_v16_read(void *context, unsigned int reg, reg 128 drivers/base/regmap/regmap-w1.c if (reg > 65535) reg 134 drivers/base/regmap/regmap-w1.c w1_write_8(sl->master, reg & 0x00FF); reg 135 drivers/base/regmap/regmap-w1.c w1_write_8(sl->master, reg>>8 & 0x00FF); reg 146 drivers/base/regmap/regmap-w1.c static int w1_reg_a16_v16_write(void *context, unsigned int reg, reg 153 drivers/base/regmap/regmap-w1.c if (reg > 65535) reg 159 drivers/base/regmap/regmap-w1.c w1_write_8(sl->master, reg & 0x00FF); reg 160 drivers/base/regmap/regmap-w1.c w1_write_8(sl->master, reg>>8 & 0x00FF); reg 44 drivers/base/regmap/regmap.c static int _regmap_update_bits(struct regmap *map, unsigned int reg, reg 48 drivers/base/regmap/regmap.c static int _regmap_bus_reg_read(void *context, unsigned int reg, reg 50 drivers/base/regmap/regmap.c static int _regmap_bus_read(void *context, unsigned int reg, reg 52 drivers/base/regmap/regmap.c static int _regmap_bus_formatted_write(void *context, unsigned int reg, reg 54 drivers/base/regmap/regmap.c static int _regmap_bus_reg_write(void *context, unsigned int reg, reg 56 drivers/base/regmap/regmap.c static int _regmap_bus_raw_write(void *context, unsigned int reg, reg 59 drivers/base/regmap/regmap.c bool regmap_reg_in_ranges(unsigned int reg, reg 67 drivers/base/regmap/regmap.c if (regmap_reg_in_range(reg, r)) reg 73 drivers/base/regmap/regmap.c bool regmap_check_range_table(struct regmap *map, unsigned int reg, reg 77 drivers/base/regmap/regmap.c if (regmap_reg_in_ranges(reg, table->no_ranges, table->n_no_ranges)) reg 84 drivers/base/regmap/regmap.c return regmap_reg_in_ranges(reg, table->yes_ranges, reg 89 drivers/base/regmap/regmap.c bool regmap_writeable(struct regmap *map, unsigned int reg) reg 91 drivers/base/regmap/regmap.c if (map->max_register && reg > map->max_register) reg 95 drivers/base/regmap/regmap.c return map->writeable_reg(map->dev, reg); reg 98 drivers/base/regmap/regmap.c return regmap_check_range_table(map, reg, map->wr_table); reg 103 drivers/base/regmap/regmap.c bool regmap_cached(struct regmap *map, unsigned int reg) reg 114 drivers/base/regmap/regmap.c if (map->max_register && reg > map->max_register) reg 118 drivers/base/regmap/regmap.c ret = regcache_read(map, reg, &val); reg 126 drivers/base/regmap/regmap.c bool regmap_readable(struct regmap *map, unsigned int reg) reg 131 drivers/base/regmap/regmap.c if (map->max_register && reg > map->max_register) reg 138 drivers/base/regmap/regmap.c return map->readable_reg(map->dev, reg); reg 141 drivers/base/regmap/regmap.c return regmap_check_range_table(map, reg, map->rd_table); reg 146 drivers/base/regmap/regmap.c bool regmap_volatile(struct regmap *map, unsigned int reg) reg 148 drivers/base/regmap/regmap.c if (!map->format.format_write && !regmap_readable(map, reg)) reg 152 drivers/base/regmap/regmap.c return map->volatile_reg(map->dev, reg); reg 155 drivers/base/regmap/regmap.c return regmap_check_range_table(map, reg, map->volatile_table); reg 163 drivers/base/regmap/regmap.c bool regmap_precious(struct regmap *map, unsigned int reg) reg 165 drivers/base/regmap/regmap.c if (!regmap_readable(map, reg)) reg 169 drivers/base/regmap/regmap.c return map->precious_reg(map->dev, reg); reg 172 drivers/base/regmap/regmap.c return regmap_check_range_table(map, reg, map->precious_table); reg 177 drivers/base/regmap/regmap.c bool regmap_writeable_noinc(struct regmap *map, unsigned int reg) reg 180 drivers/base/regmap/regmap.c return map->writeable_noinc_reg(map->dev, reg); reg 183 drivers/base/regmap/regmap.c return regmap_check_range_table(map, reg, map->wr_noinc_table); reg 188 drivers/base/regmap/regmap.c bool regmap_readable_noinc(struct regmap *map, unsigned int reg) reg 191 drivers/base/regmap/regmap.c return map->readable_noinc_reg(map->dev, reg); reg 194 drivers/base/regmap/regmap.c return regmap_check_range_table(map, reg, map->rd_noinc_table); reg 199 drivers/base/regmap/regmap.c static bool regmap_volatile_range(struct regmap *map, unsigned int reg, reg 205 drivers/base/regmap/regmap.c if (!regmap_volatile(map, reg + regmap_get_offset(map, i))) reg 212 drivers/base/regmap/regmap.c unsigned int reg, unsigned int val) reg 216 drivers/base/regmap/regmap.c *out = (reg << 6) | val; reg 220 drivers/base/regmap/regmap.c unsigned int reg, unsigned int val) reg 223 drivers/base/regmap/regmap.c *out = cpu_to_be16((reg << 12) | val); reg 227 drivers/base/regmap/regmap.c unsigned int reg, unsigned int val) reg 230 drivers/base/regmap/regmap.c *out = cpu_to_be16((reg << 9) | val); reg 234 drivers/base/regmap/regmap.c unsigned int reg, unsigned int val) reg 239 drivers/base/regmap/regmap.c out[1] = (val >> 8) | (reg << 6); reg 240 drivers/base/regmap/regmap.c out[0] = reg >> 2; reg 557 drivers/base/regmap/regmap.c unsigned int reg) reg 565 drivers/base/regmap/regmap.c if (reg < this->range_min) reg 567 drivers/base/regmap/regmap.c else if (reg > this->range_max) reg 1209 drivers/base/regmap/regmap.c rm_field->reg = reg_field.reg; reg 1414 drivers/base/regmap/regmap.c static int _regmap_select_page(struct regmap *map, unsigned int *reg, reg 1424 drivers/base/regmap/regmap.c win_offset = (*reg - range->range_min) % range->window_len; reg 1425 drivers/base/regmap/regmap.c win_page = (*reg - range->range_min) / range->window_len; reg 1429 drivers/base/regmap/regmap.c if (*reg + val_num - 1 > range->range_max) reg 1457 drivers/base/regmap/regmap.c *reg = range->window_start + win_offset; reg 1477 drivers/base/regmap/regmap.c static int _regmap_raw_write_impl(struct regmap *map, unsigned int reg, reg 1494 drivers/base/regmap/regmap.c if (!regmap_writeable_noinc(map, reg)) { reg 1497 drivers/base/regmap/regmap.c reg + regmap_get_offset(map, i); reg 1510 drivers/base/regmap/regmap.c reg + regmap_get_offset(map, i), reg 1515 drivers/base/regmap/regmap.c reg + i, ret); reg 1525 drivers/base/regmap/regmap.c range = _regmap_range_lookup(map, reg); reg 1528 drivers/base/regmap/regmap.c int win_offset = (reg - range->range_min) % range->window_len; reg 1535 drivers/base/regmap/regmap.c ret = _regmap_raw_write_impl(map, reg, val, reg 1541 drivers/base/regmap/regmap.c reg += win_residue; reg 1546 drivers/base/regmap/regmap.c win_offset = (reg - range->range_min) % reg 1551 drivers/base/regmap/regmap.c ret = _regmap_select_page(map, ®, range, val_num); reg 1556 drivers/base/regmap/regmap.c map->format.format_reg(map->work_buf, reg, map->reg_shift); reg 1573 drivers/base/regmap/regmap.c trace_regmap_async_write_start(map, reg, val_len); reg 1631 drivers/base/regmap/regmap.c trace_regmap_hw_write_start(map, reg, val_len / map->format.val_bytes); reg 1668 drivers/base/regmap/regmap.c map->cache_ops->drop(map, reg, reg + 1); reg 1671 drivers/base/regmap/regmap.c trace_regmap_hw_write_done(map, reg, val_len / map->format.val_bytes); reg 1710 drivers/base/regmap/regmap.c static int _regmap_bus_formatted_write(void *context, unsigned int reg, reg 1719 drivers/base/regmap/regmap.c range = _regmap_range_lookup(map, reg); reg 1721 drivers/base/regmap/regmap.c ret = _regmap_select_page(map, ®, range, 1); reg 1726 drivers/base/regmap/regmap.c map->format.format_write(map, reg, val); reg 1728 drivers/base/regmap/regmap.c trace_regmap_hw_write_start(map, reg, 1); reg 1733 drivers/base/regmap/regmap.c trace_regmap_hw_write_done(map, reg, 1); reg 1738 drivers/base/regmap/regmap.c static int _regmap_bus_reg_write(void *context, unsigned int reg, reg 1743 drivers/base/regmap/regmap.c return map->bus->reg_write(map->bus_context, reg, val); reg 1746 drivers/base/regmap/regmap.c static int _regmap_bus_raw_write(void *context, unsigned int reg, reg 1755 drivers/base/regmap/regmap.c return _regmap_raw_write_impl(map, reg, reg 1767 drivers/base/regmap/regmap.c int _regmap_write(struct regmap *map, unsigned int reg, reg 1773 drivers/base/regmap/regmap.c if (!regmap_writeable(map, reg)) reg 1777 drivers/base/regmap/regmap.c ret = regcache_write(map, reg, val); reg 1787 drivers/base/regmap/regmap.c dev_info(map->dev, "%x <= %x\n", reg, val); reg 1789 drivers/base/regmap/regmap.c trace_regmap_reg_write(map, reg, val); reg 1791 drivers/base/regmap/regmap.c return map->reg_write(context, reg, val); reg 1804 drivers/base/regmap/regmap.c int regmap_write(struct regmap *map, unsigned int reg, unsigned int val) reg 1808 drivers/base/regmap/regmap.c if (!IS_ALIGNED(reg, map->reg_stride)) reg 1813 drivers/base/regmap/regmap.c ret = _regmap_write(map, reg, val); reg 1831 drivers/base/regmap/regmap.c int regmap_write_async(struct regmap *map, unsigned int reg, unsigned int val) reg 1835 drivers/base/regmap/regmap.c if (!IS_ALIGNED(reg, map->reg_stride)) reg 1842 drivers/base/regmap/regmap.c ret = _regmap_write(map, reg, val); reg 1852 drivers/base/regmap/regmap.c int _regmap_raw_write(struct regmap *map, unsigned int reg, reg 1874 drivers/base/regmap/regmap.c ret = _regmap_raw_write_impl(map, reg, val, chunk_bytes); reg 1878 drivers/base/regmap/regmap.c reg += regmap_get_offset(map, chunk_regs); reg 1885 drivers/base/regmap/regmap.c ret = _regmap_raw_write_impl(map, reg, val, val_len); reg 1906 drivers/base/regmap/regmap.c int regmap_raw_write(struct regmap *map, unsigned int reg, reg 1918 drivers/base/regmap/regmap.c ret = _regmap_raw_write(map, reg, val, val_len); reg 1947 drivers/base/regmap/regmap.c int regmap_noinc_write(struct regmap *map, unsigned int reg, reg 1959 drivers/base/regmap/regmap.c if (!IS_ALIGNED(reg, map->reg_stride)) reg 1966 drivers/base/regmap/regmap.c if (!regmap_volatile(map, reg) || !regmap_writeable_noinc(map, reg)) { reg 1976 drivers/base/regmap/regmap.c ret = _regmap_raw_write(map, reg, val, write_len); reg 2012 drivers/base/regmap/regmap.c return regmap_update_bits_base(field->regmap, field->reg, reg 2043 drivers/base/regmap/regmap.c field->reg + (field->id_offset * id), reg 2063 drivers/base/regmap/regmap.c int regmap_bulk_write(struct regmap *map, unsigned int reg, const void *val, reg 2069 drivers/base/regmap/regmap.c if (!IS_ALIGNED(reg, map->reg_stride)) reg 2102 drivers/base/regmap/regmap.c reg + regmap_get_offset(map, i), reg 2119 drivers/base/regmap/regmap.c ret = regmap_raw_write(map, reg, wval, val_bytes * val_count); reg 2160 drivers/base/regmap/regmap.c unsigned int reg = regs[i].reg; reg 2162 drivers/base/regmap/regmap.c trace_regmap_hw_write_start(map, reg, 1); reg 2163 drivers/base/regmap/regmap.c map->format.format_reg(u8, reg, map->reg_shift); reg 2176 drivers/base/regmap/regmap.c int reg = regs[i].reg; reg 2177 drivers/base/regmap/regmap.c trace_regmap_hw_write_done(map, reg, 1); reg 2183 drivers/base/regmap/regmap.c unsigned int reg, reg 2186 drivers/base/regmap/regmap.c unsigned int win_page = (reg - range->range_min) / range->window_len; reg 2208 drivers/base/regmap/regmap.c unsigned int reg = regs[i].reg; reg 2211 drivers/base/regmap/regmap.c range = _regmap_range_lookup(map, reg); reg 2213 drivers/base/regmap/regmap.c unsigned int win_page = _regmap_register_page(map, reg, reg 2252 drivers/base/regmap/regmap.c &base[n].reg, reg 2277 drivers/base/regmap/regmap.c ret = _regmap_write(map, regs[i].reg, regs[i].def); reg 2292 drivers/base/regmap/regmap.c int reg = regs[i].reg; reg 2293 drivers/base/regmap/regmap.c if (!map->writeable_reg(map->dev, reg)) reg 2295 drivers/base/regmap/regmap.c if (!IS_ALIGNED(reg, map->reg_stride)) reg 2302 drivers/base/regmap/regmap.c unsigned int reg = regs[i].reg; reg 2303 drivers/base/regmap/regmap.c ret = regcache_write(map, reg, val); reg 2307 drivers/base/regmap/regmap.c reg, ret); reg 2320 drivers/base/regmap/regmap.c unsigned int reg = regs[i].reg; reg 2326 drivers/base/regmap/regmap.c range = _regmap_range_lookup(map, reg); reg 2439 drivers/base/regmap/regmap.c int regmap_raw_write_async(struct regmap *map, unsigned int reg, reg 2446 drivers/base/regmap/regmap.c if (!IS_ALIGNED(reg, map->reg_stride)) reg 2453 drivers/base/regmap/regmap.c ret = _regmap_raw_write(map, reg, val, val_len); reg 2463 drivers/base/regmap/regmap.c static int _regmap_raw_read(struct regmap *map, unsigned int reg, void *val, reg 2474 drivers/base/regmap/regmap.c range = _regmap_range_lookup(map, reg); reg 2476 drivers/base/regmap/regmap.c ret = _regmap_select_page(map, ®, range, reg 2482 drivers/base/regmap/regmap.c map->format.format_reg(map->work_buf, reg, map->reg_shift); reg 2485 drivers/base/regmap/regmap.c trace_regmap_hw_read_start(map, reg, val_len / map->format.val_bytes); reg 2491 drivers/base/regmap/regmap.c trace_regmap_hw_read_done(map, reg, val_len / map->format.val_bytes); reg 2496 drivers/base/regmap/regmap.c static int _regmap_bus_reg_read(void *context, unsigned int reg, reg 2501 drivers/base/regmap/regmap.c return map->bus->reg_read(map->bus_context, reg, val); reg 2504 drivers/base/regmap/regmap.c static int _regmap_bus_read(void *context, unsigned int reg, reg 2515 drivers/base/regmap/regmap.c ret = _regmap_raw_read(map, reg, work_val, map->format.val_bytes); reg 2522 drivers/base/regmap/regmap.c static int _regmap_read(struct regmap *map, unsigned int reg, reg 2529 drivers/base/regmap/regmap.c ret = regcache_read(map, reg, val); reg 2537 drivers/base/regmap/regmap.c if (!regmap_readable(map, reg)) reg 2540 drivers/base/regmap/regmap.c ret = map->reg_read(context, reg, val); reg 2543 drivers/base/regmap/regmap.c dev_info(map->dev, "%x => %x\n", reg, *val); reg 2545 drivers/base/regmap/regmap.c trace_regmap_reg_read(map, reg, *val); reg 2548 drivers/base/regmap/regmap.c regcache_write(map, reg, *val); reg 2564 drivers/base/regmap/regmap.c int regmap_read(struct regmap *map, unsigned int reg, unsigned int *val) reg 2568 drivers/base/regmap/regmap.c if (!IS_ALIGNED(reg, map->reg_stride)) reg 2573 drivers/base/regmap/regmap.c ret = _regmap_read(map, reg, val); reg 2592 drivers/base/regmap/regmap.c int regmap_raw_read(struct regmap *map, unsigned int reg, void *val, reg 2604 drivers/base/regmap/regmap.c if (!IS_ALIGNED(reg, map->reg_stride)) reg 2611 drivers/base/regmap/regmap.c if (regmap_volatile_range(map, reg, val_count) || map->cache_bypass || reg 2631 drivers/base/regmap/regmap.c ret = _regmap_raw_read(map, reg, val, chunk_bytes); reg 2635 drivers/base/regmap/regmap.c reg += regmap_get_offset(map, chunk_regs); reg 2642 drivers/base/regmap/regmap.c ret = _regmap_raw_read(map, reg, val, val_len); reg 2651 drivers/base/regmap/regmap.c ret = _regmap_read(map, reg + regmap_get_offset(map, i), reg 2688 drivers/base/regmap/regmap.c int regmap_noinc_read(struct regmap *map, unsigned int reg, reg 2700 drivers/base/regmap/regmap.c if (!IS_ALIGNED(reg, map->reg_stride)) reg 2707 drivers/base/regmap/regmap.c if (!regmap_volatile(map, reg) || !regmap_readable_noinc(map, reg)) { reg 2717 drivers/base/regmap/regmap.c ret = _regmap_raw_read(map, reg, val, read_len); reg 2743 drivers/base/regmap/regmap.c ret = regmap_read(field->regmap, field->reg, ®_val); reg 2775 drivers/base/regmap/regmap.c field->reg + (field->id_offset * id), reg 2799 drivers/base/regmap/regmap.c int regmap_bulk_read(struct regmap *map, unsigned int reg, void *val, reg 2804 drivers/base/regmap/regmap.c bool vol = regmap_volatile_range(map, reg, val_count); reg 2806 drivers/base/regmap/regmap.c if (!IS_ALIGNED(reg, map->reg_stride)) reg 2812 drivers/base/regmap/regmap.c ret = regmap_raw_read(map, reg, val, val_bytes * val_count); reg 2831 drivers/base/regmap/regmap.c ret = _regmap_read(map, reg + regmap_get_offset(map, i), reg 2865 drivers/base/regmap/regmap.c static int _regmap_update_bits(struct regmap *map, unsigned int reg, reg 2875 drivers/base/regmap/regmap.c if (regmap_volatile(map, reg) && map->reg_update_bits) { reg 2876 drivers/base/regmap/regmap.c ret = map->reg_update_bits(map->bus_context, reg, mask, val); reg 2880 drivers/base/regmap/regmap.c ret = _regmap_read(map, reg, &orig); reg 2888 drivers/base/regmap/regmap.c ret = _regmap_write(map, reg, tmp); reg 2919 drivers/base/regmap/regmap.c int regmap_update_bits_base(struct regmap *map, unsigned int reg, reg 2929 drivers/base/regmap/regmap.c ret = _regmap_update_bits(map, reg, mask, val, change, force); reg 18 drivers/base/regmap/trace.h TP_PROTO(struct regmap *map, unsigned int reg, reg 21 drivers/base/regmap/trace.h TP_ARGS(map, reg, val), reg 25 drivers/base/regmap/trace.h __field( unsigned int, reg ) reg 31 drivers/base/regmap/trace.h __entry->reg = reg; reg 36 drivers/base/regmap/trace.h (unsigned int)__entry->reg, reg 42 drivers/base/regmap/trace.h TP_PROTO(struct regmap *map, unsigned int reg, reg 45 drivers/base/regmap/trace.h TP_ARGS(map, reg, val) reg 51 drivers/base/regmap/trace.h TP_PROTO(struct regmap *map, unsigned int reg, reg 54 drivers/base/regmap/trace.h TP_ARGS(map, reg, val) reg 60 drivers/base/regmap/trace.h TP_PROTO(struct regmap *map, unsigned int reg, reg 63 drivers/base/regmap/trace.h TP_ARGS(map, reg, val) reg 69 drivers/base/regmap/trace.h TP_PROTO(struct regmap *map, unsigned int reg, int count), reg 71 drivers/base/regmap/trace.h TP_ARGS(map, reg, count), reg 75 drivers/base/regmap/trace.h __field( unsigned int, reg ) reg 81 drivers/base/regmap/trace.h __entry->reg = reg; reg 86 drivers/base/regmap/trace.h (unsigned int)__entry->reg, reg 92 drivers/base/regmap/trace.h TP_PROTO(struct regmap *map, unsigned int reg, int count), reg 94 drivers/base/regmap/trace.h TP_ARGS(map, reg, count) reg 99 drivers/base/regmap/trace.h TP_PROTO(struct regmap *map, unsigned int reg, int count), reg 101 drivers/base/regmap/trace.h TP_ARGS(map, reg, count) reg 106 drivers/base/regmap/trace.h TP_PROTO(struct regmap *map, unsigned int reg, int count), reg 108 drivers/base/regmap/trace.h TP_ARGS(map, reg, count) reg 113 drivers/base/regmap/trace.h TP_PROTO(struct regmap *map, unsigned int reg, int count), reg 115 drivers/base/regmap/trace.h TP_ARGS(map, reg, count) reg 197 drivers/base/regmap/trace.h TP_PROTO(struct regmap *map, unsigned int reg, int count), reg 199 drivers/base/regmap/trace.h TP_ARGS(map, reg, count) reg 24 drivers/bcma/bcma_private.h bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value, reg 12 drivers/bcma/core.c static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask, reg 19 drivers/bcma/core.c val = bcma_aread32(core, reg); reg 26 drivers/bcma/core.c bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg); reg 232 drivers/bcma/driver_pci_host.c int reg, int size, u32 *val) reg 244 drivers/bcma/driver_pci_host.c PCI_FUNC(devfn), reg, val, size); reg 252 drivers/bcma/driver_pci_host.c int reg, int size, u32 val) reg 264 drivers/bcma/driver_pci_host.c PCI_FUNC(devfn), reg, &val, size); reg 99 drivers/bcma/main.c bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value, reg 106 drivers/bcma/main.c val = bcma_read32(core, reg); reg 113 drivers/bcma/main.c bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg); reg 144 drivers/bcma/main.c const __be32 *reg; reg 150 drivers/bcma/main.c reg = of_get_address(node, 0, &size, NULL); reg 151 drivers/bcma/main.c if (!reg) reg 153 drivers/bcma/main.c if (of_translate_address(node, reg) == core->addr) reg 312 drivers/block/ataflop.c #define FDC_READ(reg) ({ \ reg 316 drivers/block/ataflop.c dma_wd.dma_mode_status = 0x80 | (reg); \ reg 324 drivers/block/ataflop.c #define FDC_WRITE(reg,val) \ reg 328 drivers/block/ataflop.c dma_wd.dma_mode_status = 0x80 | (reg); \ reg 59 drivers/block/paride/bpck6.c static int bpck6_read_regr(PIA *pi, int cont, int reg) reg 64 drivers/block/paride/bpck6.c if (reg<0 || reg>7 || cont<0 || cont>2) reg 68 drivers/block/paride/bpck6.c out=ppc6_rd_port(PPCSTRUCT(pi),cont?reg|8:reg); reg 72 drivers/block/paride/bpck6.c static void bpck6_write_regr(PIA *pi, int cont, int reg, int val) reg 75 drivers/block/paride/bpck6.c if (reg>=0 && reg<=7 && cont>=0 && cont<=1) reg 77 drivers/block/paride/bpck6.c ppc6_wr_port(PPCSTRUCT(pi),cont?reg|8:reg,(u8)val); reg 367 drivers/block/paride/pcd.c static inline int read_reg(struct pcd_unit *cd, int reg) reg 369 drivers/block/paride/pcd.c return pi_read_regr(cd->pi, 0, reg); reg 372 drivers/block/paride/pcd.c static inline void write_reg(struct pcd_unit *cd, int reg, int val) reg 374 drivers/block/paride/pcd.c pi_write_regr(cd->pi, 0, reg, val); reg 264 drivers/block/paride/pd.c static inline int read_reg(struct pd_unit *disk, int reg) reg 266 drivers/block/paride/pd.c return pi_read_regr(disk->pi, 0, reg); reg 274 drivers/block/paride/pd.c static inline void write_reg(struct pd_unit *disk, int reg, int val) reg 276 drivers/block/paride/pd.c pi_write_regr(disk->pi, 0, reg, val); reg 416 drivers/block/paride/pf.c static inline int read_reg(struct pf_unit *pf, int reg) reg 418 drivers/block/paride/pf.c return pi_read_regr(pf->pi, 0, reg); reg 421 drivers/block/paride/pf.c static inline void write_reg(struct pf_unit *pf, int reg, int val) reg 423 drivers/block/paride/pf.c pi_write_regr(pf->pi, 0, reg, val); reg 268 drivers/block/paride/pg.c static inline int read_reg(struct pg *dev, int reg) reg 270 drivers/block/paride/pg.c return pi_read_regr(dev->pi, 0, reg); reg 273 drivers/block/paride/pg.c static inline void write_reg(struct pg *dev, int reg, int val) reg 275 drivers/block/paride/pg.c pi_write_regr(dev->pi, 0, reg, val); reg 257 drivers/block/paride/pt.c static inline int read_reg(struct pi_adapter *pi, int reg) reg 259 drivers/block/paride/pt.c return pi_read_regr(pi, 0, reg); reg 262 drivers/block/paride/pt.c static inline void write_reg(struct pi_adapter *pi, int reg, int val) reg 264 drivers/block/paride/pt.c pi_write_regr(pi, 0, reg, val); reg 62 drivers/block/swim.c #define swim_write(base, reg, v) out_8(&(base)->write_##reg, (v)) reg 63 drivers/block/swim.c #define swim_read(base, reg) in_8(&(base)->read_##reg) reg 86 drivers/block/swim.c #define iwm_write(base, reg, v) out_8(&(base)->reg, (v)) reg 87 drivers/block/swim.c #define iwm_read(base, reg) in_8(&(base)->reg) reg 224 drivers/block/xsysace.c u16(*in) (struct ace_device * ace, int reg); reg 225 drivers/block/xsysace.c void (*out) (struct ace_device * ace, int reg, u16 val); reg 231 drivers/block/xsysace.c static u16 ace_in_8(struct ace_device *ace, int reg) reg 233 drivers/block/xsysace.c void __iomem *r = ace->baseaddr + reg; reg 237 drivers/block/xsysace.c static void ace_out_8(struct ace_device *ace, int reg, u16 val) reg 239 drivers/block/xsysace.c void __iomem *r = ace->baseaddr + reg; reg 272 drivers/block/xsysace.c static u16 ace_in_be16(struct ace_device *ace, int reg) reg 274 drivers/block/xsysace.c return in_be16(ace->baseaddr + reg); reg 277 drivers/block/xsysace.c static void ace_out_be16(struct ace_device *ace, int reg, u16 val) reg 279 drivers/block/xsysace.c out_be16(ace->baseaddr + reg, val); reg 301 drivers/block/xsysace.c static u16 ace_in_le16(struct ace_device *ace, int reg) reg 303 drivers/block/xsysace.c return in_le16(ace->baseaddr + reg); reg 306 drivers/block/xsysace.c static void ace_out_le16(struct ace_device *ace, int reg, u16 val) reg 308 drivers/block/xsysace.c out_le16(ace->baseaddr + reg, val); reg 343 drivers/block/xsysace.c static inline u16 ace_in(struct ace_device *ace, int reg) reg 345 drivers/block/xsysace.c return ace->reg_ops->in(ace, reg); reg 348 drivers/block/xsysace.c static inline u32 ace_in32(struct ace_device *ace, int reg) reg 350 drivers/block/xsysace.c return ace_in(ace, reg) | (ace_in(ace, reg + 2) << 16); reg 353 drivers/block/xsysace.c static inline void ace_out(struct ace_device *ace, int reg, u16 val) reg 355 drivers/block/xsysace.c ace->reg_ops->out(ace, reg, val); reg 358 drivers/block/xsysace.c static inline void ace_out32(struct ace_device *ace, int reg, u32 val) reg 360 drivers/block/xsysace.c ace_out(ace, reg, val); reg 361 drivers/block/xsysace.c ace_out(ace, reg + 2, val >> 16); reg 499 drivers/bluetooth/bluecard_cs.c unsigned char reg; reg 516 drivers/bluetooth/bluecard_cs.c reg = inb(iobase + REG_INTERRUPT); reg 518 drivers/bluetooth/bluecard_cs.c if ((reg != 0x00) && (reg != 0xff)) { reg 520 drivers/bluetooth/bluecard_cs.c if (reg & 0x04) { reg 526 drivers/bluetooth/bluecard_cs.c if (reg & 0x08) { reg 532 drivers/bluetooth/bluecard_cs.c if (reg & 0x01) { reg 538 drivers/bluetooth/bluecard_cs.c if (reg & 0x02) { reg 287 drivers/bluetooth/btmrvl_sdio.c .reg = &btmrvl_reg_8688, reg 296 drivers/bluetooth/btmrvl_sdio.c .reg = &btmrvl_reg_87xx, reg 305 drivers/bluetooth/btmrvl_sdio.c .reg = &btmrvl_reg_87xx, reg 314 drivers/bluetooth/btmrvl_sdio.c .reg = &btmrvl_reg_8887, reg 323 drivers/bluetooth/btmrvl_sdio.c .reg = &btmrvl_reg_8897, reg 332 drivers/bluetooth/btmrvl_sdio.c .reg = &btmrvl_reg_8977, reg 341 drivers/bluetooth/btmrvl_sdio.c .reg = &btmrvl_reg_8987, reg 350 drivers/bluetooth/btmrvl_sdio.c .reg = &btmrvl_reg_8997, reg 392 drivers/bluetooth/btmrvl_sdio.c u8 reg; reg 395 drivers/bluetooth/btmrvl_sdio.c reg = sdio_readb(card->func, card->reg->card_rx_unit, &ret); reg 397 drivers/bluetooth/btmrvl_sdio.c card->rx_unit = reg; reg 409 drivers/bluetooth/btmrvl_sdio.c fws0 = sdio_readb(card->func, card->reg->card_fw_status0, &ret); reg 413 drivers/bluetooth/btmrvl_sdio.c fws1 = sdio_readb(card->func, card->reg->card_fw_status1, &ret); reg 424 drivers/bluetooth/btmrvl_sdio.c u8 reg; reg 427 drivers/bluetooth/btmrvl_sdio.c reg = sdio_readb(card->func, card->reg->card_rx_len, &ret); reg 429 drivers/bluetooth/btmrvl_sdio.c *dat = (u16) reg << card->rx_unit; reg 439 drivers/bluetooth/btmrvl_sdio.c sdio_writeb(card->func, mask, card->reg->host_int_mask, &ret); reg 454 drivers/bluetooth/btmrvl_sdio.c host_int_mask = sdio_readb(card->func, card->reg->host_int_mask, &ret); reg 460 drivers/bluetooth/btmrvl_sdio.c sdio_writeb(card->func, host_int_mask, card->reg->host_int_mask, &ret); reg 476 drivers/bluetooth/btmrvl_sdio.c status = sdio_readb(card->func, card->reg->card_status, &ret); reg 669 drivers/bluetooth/btmrvl_sdio.c card->reg->sq_read_base_addr_a0, &ret); reg 679 drivers/bluetooth/btmrvl_sdio.c card->reg->sq_read_base_addr_a1, &ret); reg 739 drivers/bluetooth/btmrvl_sdio.c card->reg->cfg, &ret); reg 919 drivers/bluetooth/btmrvl_sdio.c *ireg = adapter->hw_regs[card->reg->host_intstatus]; reg 920 drivers/bluetooth/btmrvl_sdio.c BT_DBG("hw_regs[%#x]=%#x", card->reg->host_intstatus, *ireg); reg 929 drivers/bluetooth/btmrvl_sdio.c *ireg = sdio_readb(card->func, card->reg->host_intstatus, &ret); reg 945 drivers/bluetooth/btmrvl_sdio.c card->reg->host_intstatus, &ret); reg 975 drivers/bluetooth/btmrvl_sdio.c if (card->reg->int_read_to_clear) reg 993 drivers/bluetooth/btmrvl_sdio.c u8 reg; reg 1027 drivers/bluetooth/btmrvl_sdio.c reg = sdio_readb(func, card->reg->io_port_0, &ret); reg 1033 drivers/bluetooth/btmrvl_sdio.c card->ioport = reg; reg 1035 drivers/bluetooth/btmrvl_sdio.c reg = sdio_readb(func, card->reg->io_port_1, &ret); reg 1041 drivers/bluetooth/btmrvl_sdio.c card->ioport |= (reg << 8); reg 1043 drivers/bluetooth/btmrvl_sdio.c reg = sdio_readb(func, card->reg->io_port_2, &ret); reg 1049 drivers/bluetooth/btmrvl_sdio.c card->ioport |= (reg << 16); reg 1053 drivers/bluetooth/btmrvl_sdio.c if (card->reg->int_read_to_clear) { reg 1054 drivers/bluetooth/btmrvl_sdio.c reg = sdio_readb(func, card->reg->host_int_rsr, &ret); reg 1059 drivers/bluetooth/btmrvl_sdio.c sdio_writeb(func, reg | 0x3f, card->reg->host_int_rsr, &ret); reg 1065 drivers/bluetooth/btmrvl_sdio.c reg = sdio_readb(func, card->reg->card_misc_cfg, &ret); reg 1070 drivers/bluetooth/btmrvl_sdio.c sdio_writeb(func, reg | 0x10, card->reg->card_misc_cfg, &ret); reg 1217 drivers/bluetooth/btmrvl_sdio.c fws0 = sdio_readb(card->func, card->reg->card_fw_status0, &ret); reg 1276 drivers/bluetooth/btmrvl_sdio.c sdio_writeb(card->func, HOST_POWER_UP, card->reg->cfg, &ret); reg 1289 drivers/bluetooth/btmrvl_sdio.c unsigned int reg, reg_start, reg_end; reg 1314 drivers/bluetooth/btmrvl_sdio.c for (reg = reg_start; reg <= reg_end; reg++) { reg 1316 drivers/bluetooth/btmrvl_sdio.c data = sdio_f0_readb(card->func, reg, &ret); reg 1318 drivers/bluetooth/btmrvl_sdio.c data = sdio_readb(card->func, reg, &ret); reg 1343 drivers/bluetooth/btmrvl_sdio.c sdio_writeb(card->func, FW_DUMP_HOST_READY, card->reg->fw_dump_ctrl, reg 1352 drivers/bluetooth/btmrvl_sdio.c ctrl_data = sdio_readb(card->func, card->reg->fw_dump_ctrl, reg 1367 drivers/bluetooth/btmrvl_sdio.c card->reg->fw_dump_ctrl, &ret); reg 1391 drivers/bluetooth/btmrvl_sdio.c unsigned int reg, reg_start, reg_end; reg 1427 drivers/bluetooth/btmrvl_sdio.c reg = card->reg->fw_dump_start; reg 1429 drivers/bluetooth/btmrvl_sdio.c dump_num = sdio_readb(card->func, reg, &ret); reg 1445 drivers/bluetooth/btmrvl_sdio.c reg = card->reg->fw_dump_start; reg 1447 drivers/bluetooth/btmrvl_sdio.c read_reg = sdio_readb(card->func, reg, &ret); reg 1453 drivers/bluetooth/btmrvl_sdio.c reg++; reg 1459 drivers/bluetooth/btmrvl_sdio.c card->reg->fw_dump_ctrl, &ret); reg 1493 drivers/bluetooth/btmrvl_sdio.c reg_start = card->reg->fw_dump_start; reg 1494 drivers/bluetooth/btmrvl_sdio.c reg_end = card->reg->fw_dump_end; reg 1495 drivers/bluetooth/btmrvl_sdio.c for (reg = reg_start; reg <= reg_end; reg++) { reg 1496 drivers/bluetooth/btmrvl_sdio.c *dbg_ptr = sdio_readb(card->func, reg, &ret); reg 1588 drivers/bluetooth/btmrvl_sdio.c card->reg = data->reg; reg 98 drivers/bluetooth/btmrvl_sdio.h const struct btmrvl_sdio_card_reg *reg; reg 111 drivers/bluetooth/btmrvl_sdio.h const struct btmrvl_sdio_card_reg *reg; reg 2887 drivers/bluetooth/btusb.c static int btusb_mtk_reg_read(struct btusb_data *data, u32 reg, u32 *val) reg 2899 drivers/bluetooth/btusb.c reg >> 16, reg & 0xffff, reg 100 drivers/bluetooth/hci_bcsp.c u16 reg = *crc; reg 102 drivers/bluetooth/hci_bcsp.c reg = (reg >> 4) ^ crc_table[(reg ^ d) & 0x000f]; reg 103 drivers/bluetooth/hci_bcsp.c reg = (reg >> 4) ^ crc_table[(reg ^ (d >> 4)) & 0x000f]; reg 105 drivers/bluetooth/hci_bcsp.c *crc = reg; reg 100 drivers/bus/brcmstb_gisb.c static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg) reg 102 drivers/bus/brcmstb_gisb.c int offset = gdev->gisb_offsets[reg]; reg 106 drivers/bus/brcmstb_gisb.c if (reg == ARB_ERR_CAP_MASTER) reg 128 drivers/bus/brcmstb_gisb.c static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg) reg 130 drivers/bus/brcmstb_gisb.c int offset = gdev->gisb_offsets[reg]; reg 54 drivers/bus/da8xx-mstpri.c int reg; reg 61 drivers/bus/da8xx-mstpri.c .reg = DA8XX_MSTPRI0_OFFSET, reg 66 drivers/bus/da8xx-mstpri.c .reg = DA8XX_MSTPRI0_OFFSET, reg 71 drivers/bus/da8xx-mstpri.c .reg = DA8XX_MSTPRI0_OFFSET, reg 76 drivers/bus/da8xx-mstpri.c .reg = DA8XX_MSTPRI0_OFFSET, reg 81 drivers/bus/da8xx-mstpri.c .reg = DA8XX_MSTPRI1_OFFSET, reg 86 drivers/bus/da8xx-mstpri.c .reg = DA8XX_MSTPRI1_OFFSET, reg 91 drivers/bus/da8xx-mstpri.c .reg = DA8XX_MSTPRI1_OFFSET, reg 96 drivers/bus/da8xx-mstpri.c .reg = DA8XX_MSTPRI1_OFFSET, reg 101 drivers/bus/da8xx-mstpri.c .reg = DA8XX_MSTPRI1_OFFSET, reg 106 drivers/bus/da8xx-mstpri.c .reg = DA8XX_MSTPRI1_OFFSET, reg 111 drivers/bus/da8xx-mstpri.c .reg = DA8XX_MSTPRI1_OFFSET, reg 116 drivers/bus/da8xx-mstpri.c .reg = DA8XX_MSTPRI2_OFFSET, reg 121 drivers/bus/da8xx-mstpri.c .reg = DA8XX_MSTPRI2_OFFSET, reg 126 drivers/bus/da8xx-mstpri.c .reg = DA8XX_MSTPRI2_OFFSET, reg 131 drivers/bus/da8xx-mstpri.c .reg = DA8XX_MSTPRI2_OFFSET, reg 136 drivers/bus/da8xx-mstpri.c .reg = DA8XX_MSTPRI2_OFFSET, reg 141 drivers/bus/da8xx-mstpri.c .reg = DA8XX_MSTPRI2_OFFSET, reg 213 drivers/bus/da8xx-mstpri.c u32 reg; reg 233 drivers/bus/da8xx-mstpri.c if (prio_descr->reg + sizeof(u32) > resource_size(res)) { reg 238 drivers/bus/da8xx-mstpri.c reg = readl(mstpri + prio_descr->reg); reg 239 drivers/bus/da8xx-mstpri.c reg &= ~prio_descr->mask; reg 240 drivers/bus/da8xx-mstpri.c reg |= prio->val << prio_descr->shift; reg 242 drivers/bus/da8xx-mstpri.c writel(reg, mstpri + prio_descr->reg); reg 198 drivers/bus/imx-weim.c u32 reg; reg 208 drivers/bus/imx-weim.c reg = readl(base + devtype->wcr_offset); reg 209 drivers/bus/imx-weim.c writel(reg | devtype->wcr_bcm, reg 1280 drivers/bus/mvebu-mbus.c u32 reg[2]; reg 1292 drivers/bus/mvebu-mbus.c ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg)); reg 1294 drivers/bus/mvebu-mbus.c mem->start = reg[0]; reg 1295 drivers/bus/mvebu-mbus.c mem->end = mem->start + reg[1] - 1; reg 1299 drivers/bus/mvebu-mbus.c ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg)); reg 1301 drivers/bus/mvebu-mbus.c io->start = reg[0]; reg 1302 drivers/bus/mvebu-mbus.c io->end = io->start + reg[1] - 1; reg 32 drivers/bus/omap-ocp2scp.c u32 reg; reg 69 drivers/bus/omap-ocp2scp.c reg = readl_relaxed(regs + OCP2SCP_TIMING); reg 70 drivers/bus/omap-ocp2scp.c reg &= ~(SYNC2_MASK); reg 71 drivers/bus/omap-ocp2scp.c reg |= 0x6; reg 72 drivers/bus/omap-ocp2scp.c writel_relaxed(reg, regs + OCP2SCP_TIMING); reg 22 drivers/bus/omap_l3_smx.c static inline u64 omap3_l3_readll(void __iomem *base, u16 reg) reg 24 drivers/bus/omap_l3_smx.c return __raw_readll(base + reg); reg 27 drivers/bus/omap_l3_smx.c static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value) reg 29 drivers/bus/omap_l3_smx.c __raw_writell(value, base + reg); reg 399 drivers/bus/sunxi-rsb.c static int regmap_sunxi_rsb_reg_read(void *context, unsigned int reg, reg 405 drivers/bus/sunxi-rsb.c if (reg > 0xff) reg 408 drivers/bus/sunxi-rsb.c return sunxi_rsb_read(rdev->rsb, rdev->rtaddr, reg, val, ctx->size); reg 411 drivers/bus/sunxi-rsb.c static int regmap_sunxi_rsb_reg_write(void *context, unsigned int reg, reg 417 drivers/bus/sunxi-rsb.c return sunxi_rsb_write(rdev->rsb, rdev->rtaddr, reg, &val, ctx->size); reg 496 drivers/bus/sunxi-rsb.c u32 reg; reg 502 drivers/bus/sunxi-rsb.c readl_poll_timeout(rsb->regs + RSB_DMCR, reg, reg 503 drivers/bus/sunxi-rsb.c !(reg & RSB_DMCR_DEVICE_START), 100, 250000); reg 504 drivers/bus/sunxi-rsb.c if (reg & RSB_DMCR_DEVICE_START) reg 632 drivers/bus/sunxi-rsb.c u32 reg; reg 690 drivers/bus/sunxi-rsb.c readl_poll_timeout(rsb->regs + RSB_CTRL, reg, reg 691 drivers/bus/sunxi-rsb.c !(reg & RSB_CTRL_SOFT_RST), 1000, 100000); reg 661 drivers/bus/ti-sysc.c static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) reg 666 drivers/bus/ti-sysc.c switch (reg) { reg 670 drivers/bus/ti-sysc.c name = reg_names[reg]; reg 679 drivers/bus/ti-sysc.c ddata->offsets[reg] = -ENODEV; reg 684 drivers/bus/ti-sysc.c ddata->offsets[reg] = res->start - ddata->module_pa; reg 685 drivers/bus/ti-sysc.c if (reg == SYSC_REVISION) reg 829 drivers/bus/ti-sysc.c char *bufp, enum sysc_registers reg) reg 831 drivers/bus/ti-sysc.c if (ddata->offsets[reg] < 0) reg 834 drivers/bus/ti-sysc.c return sprintf(bufp, ":%x", ddata->offsets[reg]); reg 874 drivers/bus/ti-sysc.c u32 reg, idlemodes, best_mode; reg 881 drivers/bus/ti-sysc.c reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); reg 887 drivers/bus/ti-sysc.c reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift; reg 907 drivers/bus/ti-sysc.c reg |= BIT(regbits->enwkup_shift); reg 910 drivers/bus/ti-sysc.c reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); reg 911 drivers/bus/ti-sysc.c reg |= best_mode << regbits->sidle_shift; reg 912 drivers/bus/ti-sysc.c sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); reg 929 drivers/bus/ti-sysc.c reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); reg 930 drivers/bus/ti-sysc.c reg |= best_mode << regbits->midle_shift; reg 931 drivers/bus/ti-sysc.c sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); reg 937 drivers/bus/ti-sysc.c reg |= 1 << regbits->autoidle_shift; reg 938 drivers/bus/ti-sysc.c sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); reg 966 drivers/bus/ti-sysc.c u32 reg, idlemodes, best_mode; reg 977 drivers/bus/ti-sysc.c reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); reg 994 drivers/bus/ti-sysc.c reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); reg 995 drivers/bus/ti-sysc.c reg |= best_mode << regbits->midle_shift; reg 996 drivers/bus/ti-sysc.c sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); reg 1014 drivers/bus/ti-sysc.c reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); reg 1015 drivers/bus/ti-sysc.c reg |= best_mode << regbits->sidle_shift; reg 1018 drivers/bus/ti-sysc.c reg |= 1 << regbits->autoidle_shift; reg 1019 drivers/bus/ti-sysc.c sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); reg 210 drivers/char/agp/amd-k7-agp.c phys_addr_t reg; reg 218 drivers/char/agp/amd-k7-agp.c reg = pci_resource_start(agp_bridge->dev, AMD_MMBASE_BAR); reg 219 drivers/char/agp/amd-k7-agp.c amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096); reg 201 drivers/char/agp/ati-agp.c phys_addr_t reg; reg 205 drivers/char/agp/ati-agp.c reg = pci_resource_start(agp_bridge->dev, ATI_GART_MMBASE_BAR); reg 206 drivers/char/agp/ati-agp.c ati_generic_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096); reg 746 drivers/char/agp/intel-gtt.c u8 __iomem *reg; reg 773 drivers/char/agp/intel-gtt.c reg = intel_private.registers+I810_PGETBL_CTL; reg 774 drivers/char/agp/intel-gtt.c writel(intel_private.PGETBL_save, reg); reg 775 drivers/char/agp/intel-gtt.c if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { reg 778 drivers/char/agp/intel-gtt.c readl(reg), intel_private.PGETBL_save); reg 432 drivers/char/agp/via-agp.c u8 reg; reg 434 drivers/char/agp/via-agp.c pci_read_config_byte(bridge->dev, VIA_AGPSEL, ®); reg 436 drivers/char/agp/via-agp.c if ((reg & (1<<1))==0) reg 163 drivers/char/hw_random/omap-rng.c static inline u32 omap_rng_read(struct omap_rng_dev *priv, u16 reg) reg 165 drivers/char/hw_random/omap-rng.c return __raw_readl(priv->base + priv->pdata->regs[reg]); reg 168 drivers/char/hw_random/omap-rng.c static inline void omap_rng_write(struct omap_rng_dev *priv, u16 reg, reg 171 drivers/char/hw_random/omap-rng.c __raw_writel(val, priv->base + priv->pdata->regs[reg]); reg 78 drivers/char/ipmi/bt-bmc.c static u8 bt_inb(struct bt_bmc *bt_bmc, int reg) reg 83 drivers/char/ipmi/bt-bmc.c rc = regmap_read(bt_bmc->map, bt_bmc->offset + reg, &val); reg 89 drivers/char/ipmi/bt-bmc.c static void bt_outb(struct bt_bmc *bt_bmc, u8 data, int reg) reg 93 drivers/char/ipmi/bt-bmc.c rc = regmap_write(bt_bmc->map, bt_bmc->offset + reg, data); reg 378 drivers/char/ipmi/bt-bmc.c u32 reg; reg 381 drivers/char/ipmi/bt-bmc.c rc = regmap_read(bt_bmc->map, bt_bmc->offset + BT_CR2, ®); reg 385 drivers/char/ipmi/bt-bmc.c reg &= BT_CR2_IRQ_H2B | BT_CR2_IRQ_HBUSY; reg 386 drivers/char/ipmi/bt-bmc.c if (!reg) reg 390 drivers/char/ipmi/bt-bmc.c regmap_write(bt_bmc->map, bt_bmc->offset + BT_CR2, reg); reg 77 drivers/char/ipmi/kcs_bmc.h u8 (*io_inputb)(struct kcs_bmc *kcs_bmc, u32 reg); reg 78 drivers/char/ipmi/kcs_bmc.h void (*io_outputb)(struct kcs_bmc *kcs_bmc, u32 reg, u8 b); reg 69 drivers/char/ipmi/kcs_bmc_aspeed.c static u8 aspeed_kcs_inb(struct kcs_bmc *kcs_bmc, u32 reg) reg 75 drivers/char/ipmi/kcs_bmc_aspeed.c rc = regmap_read(priv->map, reg, &val); reg 81 drivers/char/ipmi/kcs_bmc_aspeed.c static void aspeed_kcs_outb(struct kcs_bmc *kcs_bmc, u32 reg, u8 data) reg 86 drivers/char/ipmi/kcs_bmc_aspeed.c rc = regmap_write(priv->map, reg, data); reg 70 drivers/char/ipmi/kcs_bmc_npcm7xx.c const struct npcm7xx_kcs_reg *reg; reg 79 drivers/char/ipmi/kcs_bmc_npcm7xx.c static u8 npcm7xx_kcs_inb(struct kcs_bmc *kcs_bmc, u32 reg) reg 85 drivers/char/ipmi/kcs_bmc_npcm7xx.c rc = regmap_read(priv->map, reg, &val); reg 91 drivers/char/ipmi/kcs_bmc_npcm7xx.c static void npcm7xx_kcs_outb(struct kcs_bmc *kcs_bmc, u32 reg, u8 data) reg 96 drivers/char/ipmi/kcs_bmc_npcm7xx.c rc = regmap_write(priv->map, reg, data); reg 104 drivers/char/ipmi/kcs_bmc_npcm7xx.c regmap_update_bits(priv->map, priv->reg->ctl, KCS_CTL_IBFIE, reg 107 drivers/char/ipmi/kcs_bmc_npcm7xx.c regmap_update_bits(priv->map, priv->reg->ie, KCS_IE_IRQE | KCS_IE_HIRQE, reg 159 drivers/char/ipmi/kcs_bmc_npcm7xx.c priv->reg = &npcm7xx_kcs_reg_tbl[chan - 1]; reg 161 drivers/char/ipmi/kcs_bmc_npcm7xx.c kcs_bmc->ioreg.idr = priv->reg->dib; reg 162 drivers/char/ipmi/kcs_bmc_npcm7xx.c kcs_bmc->ioreg.odr = priv->reg->dob; reg 163 drivers/char/ipmi/kcs_bmc_npcm7xx.c kcs_bmc->ioreg.str = priv->reg->sts; reg 321 drivers/char/pcmcia/synclink_cs.c #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg)) reg 322 drivers/char/pcmcia/synclink_cs.c #define read_reg(info, reg) inb((info)->io_base + (reg)) reg 324 drivers/char/pcmcia/synclink_cs.c #define read_reg16(info, reg) inw((info)->io_base + (reg)) reg 325 drivers/char/pcmcia/synclink_cs.c #define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg)) reg 327 drivers/char/pcmcia/synclink_cs.c #define set_reg_bits(info, reg, mask) \ reg 328 drivers/char/pcmcia/synclink_cs.c write_reg(info, (reg), \ reg 329 drivers/char/pcmcia/synclink_cs.c (unsigned char) (read_reg(info, (reg)) | (mask))) reg 330 drivers/char/pcmcia/synclink_cs.c #define clear_reg_bits(info, reg, mask) \ reg 331 drivers/char/pcmcia/synclink_cs.c write_reg(info, (reg), \ reg 332 drivers/char/pcmcia/synclink_cs.c (unsigned char) (read_reg(info, (reg)) & ~(mask))) reg 517 drivers/char/ppdev.c unsigned char reg; reg 526 drivers/char/ppdev.c reg = parport_read_status(port); reg 527 drivers/char/ppdev.c if (copy_to_user(argp, ®, sizeof(reg))) reg 531 drivers/char/ppdev.c reg = parport_read_data(port); reg 532 drivers/char/ppdev.c if (copy_to_user(argp, ®, sizeof(reg))) reg 536 drivers/char/ppdev.c reg = parport_read_control(port); reg 537 drivers/char/ppdev.c if (copy_to_user(argp, ®, sizeof(reg))) reg 556 drivers/char/ppdev.c if (copy_from_user(®, argp, sizeof(reg))) reg 558 drivers/char/ppdev.c parport_write_control(port, reg); reg 562 drivers/char/ppdev.c if (copy_from_user(®, argp, sizeof(reg))) reg 564 drivers/char/ppdev.c parport_write_data(port, reg); reg 571 drivers/char/ppdev.c if (copy_from_user(®, 1 + (unsigned char __user *) arg, reg 572 drivers/char/ppdev.c sizeof(reg))) reg 574 drivers/char/ppdev.c parport_frob_control(port, mask, reg); reg 602 drivers/char/ppdev.c if (copy_from_user(®, argp, sizeof(reg))) reg 607 drivers/char/ppdev.c pp->irqctl = reg; reg 45 drivers/char/tpm/tpm_atmel.h const unsigned int *reg; reg 60 drivers/char/tpm/tpm_atmel.h reg = of_get_property(dn, "reg", ®len); reg 68 drivers/char/tpm/tpm_atmel.h address = ((unsigned long) reg[0] << 32) | reg[1]; reg 70 drivers/char/tpm/tpm_atmel.h address = reg[0]; reg 74 drivers/char/tpm/tpm_atmel.h ((unsigned long) reg[naddrc] << 32) | reg[naddrc + 1]; reg 76 drivers/char/tpm/tpm_atmel.h size = reg[naddrc]; reg 111 drivers/char/tpm/tpm_crb.c static bool crb_wait_for_reg_32(u32 __iomem *reg, u32 mask, u32 value, reg 121 drivers/char/tpm/tpm_crb.c if ((ioread32(reg) & mask) == value) reg 127 drivers/char/tpm/tpm_crb.c return ((ioread32(reg) & mask) == value); reg 770 drivers/char/tpm/tpm_tis_core.c u32 reg = TPM_INT_ENABLE(priv->locality); reg 776 drivers/char/tpm/tpm_tis_core.c rc = tpm_tis_read32(priv, reg, &interrupt); reg 780 drivers/char/tpm/tpm_tis_core.c tpm_tis_write32(priv, reg, ~TPM_GLOBAL_INT_ENABLE & interrupt); reg 265 drivers/char/xilinx_hwicap/xilinx_hwicap.c u32 reg, u32 *reg_data) reg 295 drivers/char/xilinx_hwicap/xilinx_hwicap.c buffer[index++] = hwicap_type_1_read(reg) | 1; reg 204 drivers/char/xilinx_hwicap/xilinx_hwicap.h static inline u32 hwicap_type_1_read(u32 reg) reg 207 drivers/char/xilinx_hwicap/xilinx_hwicap.h (reg << XHI_REGISTER_SHIFT) | reg 217 drivers/char/xilinx_hwicap/xilinx_hwicap.h static inline u32 hwicap_type_1_write(u32 reg) reg 220 drivers/char/xilinx_hwicap/xilinx_hwicap.h (reg << XHI_REGISTER_SHIFT) | reg 40 drivers/clk/actions/owl-divider.c unsigned int reg; reg 42 drivers/clk/actions/owl-divider.c regmap_read(common->regmap, div_hw->reg, ®); reg 43 drivers/clk/actions/owl-divider.c val = reg >> div_hw->shift; reg 67 drivers/clk/actions/owl-divider.c unsigned int reg; reg 72 drivers/clk/actions/owl-divider.c regmap_read(common->regmap, div_hw->reg, ®); reg 73 drivers/clk/actions/owl-divider.c reg &= ~GENMASK(div_hw->width + div_hw->shift - 1, div_hw->shift); reg 75 drivers/clk/actions/owl-divider.c regmap_write(common->regmap, div_hw->reg, reg 76 drivers/clk/actions/owl-divider.c reg | (val << div_hw->shift)); reg 17 drivers/clk/actions/owl-divider.h u32 reg; reg 31 drivers/clk/actions/owl-divider.h .reg = _reg, \ reg 150 drivers/clk/actions/owl-factor.c u32 reg, val, mul, div; reg 155 drivers/clk/actions/owl-factor.c regmap_read(common->regmap, factor_hw->reg, ®); reg 157 drivers/clk/actions/owl-factor.c val = reg >> factor_hw->shift; reg 189 drivers/clk/actions/owl-factor.c u32 val, reg; reg 196 drivers/clk/actions/owl-factor.c regmap_read(common->regmap, factor_hw->reg, ®); reg 198 drivers/clk/actions/owl-factor.c reg &= ~(div_mask(factor_hw) << factor_hw->shift); reg 199 drivers/clk/actions/owl-factor.c reg |= val << factor_hw->shift; reg 201 drivers/clk/actions/owl-factor.c regmap_write(common->regmap, factor_hw->reg, reg); reg 23 drivers/clk/actions/owl-factor.h u32 reg; reg 37 drivers/clk/actions/owl-factor.h .reg = _reg, \ reg 20 drivers/clk/actions/owl-gate.c u32 reg; reg 24 drivers/clk/actions/owl-gate.c regmap_read(common->regmap, gate_hw->reg, ®); reg 27 drivers/clk/actions/owl-gate.c reg |= BIT(gate_hw->bit_idx); reg 29 drivers/clk/actions/owl-gate.c reg &= ~BIT(gate_hw->bit_idx); reg 31 drivers/clk/actions/owl-gate.c regmap_write(common->regmap, gate_hw->reg, reg); reg 55 drivers/clk/actions/owl-gate.c u32 reg; reg 57 drivers/clk/actions/owl-gate.c regmap_read(common->regmap, gate_hw->reg, ®); reg 60 drivers/clk/actions/owl-gate.c reg ^= BIT(gate_hw->bit_idx); reg 62 drivers/clk/actions/owl-gate.c return !!(reg & BIT(gate_hw->bit_idx)); reg 17 drivers/clk/actions/owl-gate.h u32 reg; reg 29 drivers/clk/actions/owl-gate.h .reg = _reg, \ reg 19 drivers/clk/actions/owl-mux.c u32 reg; reg 22 drivers/clk/actions/owl-mux.c regmap_read(common->regmap, mux_hw->reg, ®); reg 23 drivers/clk/actions/owl-mux.c parent = reg >> mux_hw->shift; reg 39 drivers/clk/actions/owl-mux.c u32 reg; reg 41 drivers/clk/actions/owl-mux.c regmap_read(common->regmap, mux_hw->reg, ®); reg 42 drivers/clk/actions/owl-mux.c reg &= ~GENMASK(mux_hw->width + mux_hw->shift - 1, mux_hw->shift); reg 43 drivers/clk/actions/owl-mux.c regmap_write(common->regmap, mux_hw->reg, reg 44 drivers/clk/actions/owl-mux.c reg | (index << mux_hw->shift)); reg 17 drivers/clk/actions/owl-mux.h u32 reg; reg 29 drivers/clk/actions/owl-mux.h .reg = _reg, \ reg 90 drivers/clk/actions/owl-pll.c regmap_read(common->regmap, pll_hw->reg, &val); reg 102 drivers/clk/actions/owl-pll.c regmap_read(common->regmap, pll_hw->reg, &val); reg 115 drivers/clk/actions/owl-pll.c u32 reg; reg 117 drivers/clk/actions/owl-pll.c regmap_read(common->regmap, pll_hw->reg, ®); reg 119 drivers/clk/actions/owl-pll.c return !!(reg & BIT(pll_hw->bit_idx)); reg 125 drivers/clk/actions/owl-pll.c u32 reg; reg 127 drivers/clk/actions/owl-pll.c regmap_read(common->regmap, pll_hw->reg, ®); reg 130 drivers/clk/actions/owl-pll.c reg |= BIT(pll_hw->bit_idx); reg 132 drivers/clk/actions/owl-pll.c reg &= ~BIT(pll_hw->bit_idx); reg 134 drivers/clk/actions/owl-pll.c regmap_write(common->regmap, pll_hw->reg, reg); reg 162 drivers/clk/actions/owl-pll.c u32 val, reg; reg 175 drivers/clk/actions/owl-pll.c regmap_read(common->regmap, pll_hw->reg, ®); reg 177 drivers/clk/actions/owl-pll.c reg &= ~mul_mask(pll_hw); reg 178 drivers/clk/actions/owl-pll.c reg |= val << pll_hw->shift; reg 180 drivers/clk/actions/owl-pll.c regmap_write(common->regmap, pll_hw->reg, reg); reg 25 drivers/clk/actions/owl-pll.h u32 reg; reg 44 drivers/clk/actions/owl-pll.h .reg = _reg, \ reg 20 drivers/clk/actions/owl-reset.c return regmap_update_bits(reset->regmap, map->reg, map->bit, 0); reg 29 drivers/clk/actions/owl-reset.c return regmap_update_bits(reset->regmap, map->reg, map->bit, map->bit); reg 47 drivers/clk/actions/owl-reset.c u32 reg; reg 50 drivers/clk/actions/owl-reset.c ret = regmap_read(reset->regmap, map->reg, ®); reg 58 drivers/clk/actions/owl-reset.c return !(map->bit & reg); reg 14 drivers/clk/actions/owl-reset.h u32 reg; reg 19 drivers/clk/at91/clk-pll.c #define PLL_DIV(reg) ((reg) & PLL_DIV_MASK) reg 20 drivers/clk/at91/clk-pll.c #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \ reg 67 drivers/clk/axs10x/i2s_pll_clock.c static inline void i2s_pll_write(struct i2s_pll_clk *clk, unsigned int reg, reg 70 drivers/clk/axs10x/i2s_pll_clock.c writel_relaxed(val, clk->base + reg); reg 74 drivers/clk/axs10x/i2s_pll_clock.c unsigned int reg) reg 76 drivers/clk/axs10x/i2s_pll_clock.c return readl_relaxed(clk->base + reg); reg 40 drivers/clk/axs10x/pll_clock.c #define PLL_REG_GET_LOW(reg) \ reg 41 drivers/clk/axs10x/pll_clock.c (((reg) & (0x3F << 0)) >> 0) reg 42 drivers/clk/axs10x/pll_clock.c #define PLL_REG_GET_HIGH(reg) \ reg 43 drivers/clk/axs10x/pll_clock.c (((reg) & (0x3F << 6)) >> 6) reg 44 drivers/clk/axs10x/pll_clock.c #define PLL_REG_GET_EDGE(reg) \ reg 45 drivers/clk/axs10x/pll_clock.c (((reg) & (BIT(12))) ? 1 : 0) reg 46 drivers/clk/axs10x/pll_clock.c #define PLL_REG_GET_BYPASS(reg) \ reg 47 drivers/clk/axs10x/pll_clock.c (((reg) & (BIT(13))) ? 1 : 0) reg 48 drivers/clk/axs10x/pll_clock.c #define PLL_REG_GET_NOUPD(reg) \ reg 49 drivers/clk/axs10x/pll_clock.c (((reg) & (BIT(14))) ? 1 : 0) reg 50 drivers/clk/axs10x/pll_clock.c #define PLL_REG_GET_PAD(reg) \ reg 51 drivers/clk/axs10x/pll_clock.c (((reg) & (0x1FFFF << 15)) >> 15) reg 53 drivers/clk/axs10x/pll_clock.c #define PLL_REG_SET_LOW(reg, value) \ reg 54 drivers/clk/axs10x/pll_clock.c { reg |= (((value) & 0x3F) << 0); } reg 55 drivers/clk/axs10x/pll_clock.c #define PLL_REG_SET_HIGH(reg, value) \ reg 56 drivers/clk/axs10x/pll_clock.c { reg |= (((value) & 0x3F) << 6); } reg 57 drivers/clk/axs10x/pll_clock.c #define PLL_REG_SET_EDGE(reg, value) \ reg 58 drivers/clk/axs10x/pll_clock.c { reg |= (((value) & 0x01) << 12); } reg 59 drivers/clk/axs10x/pll_clock.c #define PLL_REG_SET_BYPASS(reg, value) \ reg 60 drivers/clk/axs10x/pll_clock.c { reg |= (((value) & 0x01) << 13); } reg 61 drivers/clk/axs10x/pll_clock.c #define PLL_REG_SET_NOUPD(reg, value) \ reg 62 drivers/clk/axs10x/pll_clock.c { reg |= (((value) & 0x01) << 14); } reg 63 drivers/clk/axs10x/pll_clock.c #define PLL_REG_SET_PAD(reg, value) \ reg 64 drivers/clk/axs10x/pll_clock.c { reg |= (((value) & 0x1FFFF) << 15); } reg 102 drivers/clk/axs10x/pll_clock.c static inline void axs10x_pll_write(struct axs10x_pll_clk *clk, u32 reg, reg 105 drivers/clk/axs10x/pll_clock.c iowrite32(val, clk->base + reg); reg 108 drivers/clk/axs10x/pll_clock.c static inline u32 axs10x_pll_read(struct axs10x_pll_clk *clk, u32 reg) reg 110 drivers/clk/axs10x/pll_clock.c return ioread32(clk->base + reg); reg 118 drivers/clk/axs10x/pll_clock.c static inline u32 axs10x_div_get_value(u32 reg) reg 120 drivers/clk/axs10x/pll_clock.c if (PLL_REG_GET_BYPASS(reg)) reg 123 drivers/clk/axs10x/pll_clock.c return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg); reg 23 drivers/clk/bcm/clk-bcm2835-aux.c void __iomem *reg, *gate; reg 31 drivers/clk/bcm/clk-bcm2835-aux.c reg = devm_ioremap_resource(dev, res); reg 32 drivers/clk/bcm/clk-bcm2835-aux.c if (IS_ERR(reg)) reg 33 drivers/clk/bcm/clk-bcm2835-aux.c return PTR_ERR(reg); reg 43 drivers/clk/bcm/clk-bcm2835-aux.c gate = reg + BCM2835_AUXENB; reg 333 drivers/clk/bcm/clk-bcm2835.c static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val) reg 335 drivers/clk/bcm/clk-bcm2835.c writel(CM_PASSWORD | val, cprman->regs + reg); reg 338 drivers/clk/bcm/clk-bcm2835.c static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg) reg 340 drivers/clk/bcm/clk-bcm2835.c return readl(cprman->regs + reg); reg 1358 drivers/clk/bcm/clk-bcm2835.c divider->div.reg = cprman->regs + data->a2w_reg; reg 116 drivers/clk/berlin/berlin2-avpll.c u32 reg; reg 118 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(vco->base + VCO_CTRL0); reg 120 drivers/clk/berlin/berlin2-avpll.c reg >>= 4; reg 122 drivers/clk/berlin/berlin2-avpll.c return !!(reg & VCO_POWERUP); reg 128 drivers/clk/berlin/berlin2-avpll.c u32 reg; reg 130 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(vco->base + VCO_CTRL0); reg 132 drivers/clk/berlin/berlin2-avpll.c reg |= VCO_POWERUP << 4; reg 134 drivers/clk/berlin/berlin2-avpll.c reg |= VCO_POWERUP; reg 135 drivers/clk/berlin/berlin2-avpll.c writel_relaxed(reg, vco->base + VCO_CTRL0); reg 143 drivers/clk/berlin/berlin2-avpll.c u32 reg; reg 145 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(vco->base + VCO_CTRL0); reg 147 drivers/clk/berlin/berlin2-avpll.c reg &= ~(VCO_POWERUP << 4); reg 149 drivers/clk/berlin/berlin2-avpll.c reg &= ~VCO_POWERUP; reg 150 drivers/clk/berlin/berlin2-avpll.c writel_relaxed(reg, vco->base + VCO_CTRL0); reg 159 drivers/clk/berlin/berlin2-avpll.c u32 reg, refdiv, fbdiv; reg 163 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(vco->base + VCO_CTRL1); reg 164 drivers/clk/berlin/berlin2-avpll.c refdiv = (reg & VCO_REFDIV_MASK) >> VCO_REFDIV_SHIFT; reg 166 drivers/clk/berlin/berlin2-avpll.c fbdiv = (reg & VCO_FBDIV_MASK) >> VCO_FBDIV_SHIFT; reg 215 drivers/clk/berlin/berlin2-avpll.c u32 reg; reg 220 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL10); reg 221 drivers/clk/berlin/berlin2-avpll.c reg &= VCO_POWERUP_CH1 << ch->index; reg 223 drivers/clk/berlin/berlin2-avpll.c return !!reg; reg 229 drivers/clk/berlin/berlin2-avpll.c u32 reg; reg 231 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL10); reg 232 drivers/clk/berlin/berlin2-avpll.c reg |= VCO_POWERUP_CH1 << ch->index; reg 233 drivers/clk/berlin/berlin2-avpll.c writel_relaxed(reg, ch->base + VCO_CTRL10); reg 241 drivers/clk/berlin/berlin2-avpll.c u32 reg; reg 243 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL10); reg 244 drivers/clk/berlin/berlin2-avpll.c reg &= ~(VCO_POWERUP_CH1 << ch->index); reg 245 drivers/clk/berlin/berlin2-avpll.c writel_relaxed(reg, ch->base + VCO_CTRL10); reg 255 drivers/clk/berlin/berlin2-avpll.c u32 reg, div_av2, div_av3, divider = 1; reg 258 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL30); reg 259 drivers/clk/berlin/berlin2-avpll.c if ((reg & (VCO_DPLL_CH1_ENABLE << ch->index)) == 0) reg 267 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_SYNC1n(ch->index)); reg 270 drivers/clk/berlin/berlin2-avpll.c reg >>= 4; reg 271 drivers/clk/berlin/berlin2-avpll.c divider = reg & VCO_SYNC1_MASK; reg 273 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_SYNC2n(ch->index)); reg 274 drivers/clk/berlin/berlin2-avpll.c freq *= reg & VCO_SYNC2_MASK; reg 284 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL11) >> 7; reg 285 drivers/clk/berlin/berlin2-avpll.c reg = (reg >> (ch->index * 3)); reg 286 drivers/clk/berlin/berlin2-avpll.c if (reg & BIT(2)) reg 287 drivers/clk/berlin/berlin2-avpll.c divider *= div_hdmi[reg & 0x3]; reg 294 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL11); reg 295 drivers/clk/berlin/berlin2-avpll.c reg >>= 28; reg 297 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL12); reg 298 drivers/clk/berlin/berlin2-avpll.c reg >>= (ch->index-1) * 3; reg 300 drivers/clk/berlin/berlin2-avpll.c if (reg & BIT(2)) reg 301 drivers/clk/berlin/berlin2-avpll.c divider *= div_av1[reg & 0x3]; reg 308 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL12); reg 309 drivers/clk/berlin/berlin2-avpll.c reg >>= 18 + (ch->index * 7); reg 311 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL13); reg 312 drivers/clk/berlin/berlin2-avpll.c reg >>= (ch->index - 2) * 7; reg 314 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL14); reg 316 drivers/clk/berlin/berlin2-avpll.c div_av2 = reg & 0x7f; reg 326 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL14); reg 327 drivers/clk/berlin/berlin2-avpll.c reg >>= 7 + (ch->index * 4); reg 329 drivers/clk/berlin/berlin2-avpll.c reg = readl_relaxed(ch->base + VCO_CTRL15); reg 331 drivers/clk/berlin/berlin2-avpll.c div_av3 = reg & 0xf; reg 69 drivers/clk/berlin/berlin2-div.c u32 reg; reg 74 drivers/clk/berlin/berlin2-div.c reg = readl_relaxed(div->base + map->gate_offs); reg 75 drivers/clk/berlin/berlin2-div.c reg >>= map->gate_shift; reg 80 drivers/clk/berlin/berlin2-div.c return (reg & 0x1); reg 87 drivers/clk/berlin/berlin2-div.c u32 reg; reg 92 drivers/clk/berlin/berlin2-div.c reg = readl_relaxed(div->base + map->gate_offs); reg 93 drivers/clk/berlin/berlin2-div.c reg |= BIT(map->gate_shift); reg 94 drivers/clk/berlin/berlin2-div.c writel_relaxed(reg, div->base + map->gate_offs); reg 106 drivers/clk/berlin/berlin2-div.c u32 reg; reg 111 drivers/clk/berlin/berlin2-div.c reg = readl_relaxed(div->base + map->gate_offs); reg 112 drivers/clk/berlin/berlin2-div.c reg &= ~BIT(map->gate_shift); reg 113 drivers/clk/berlin/berlin2-div.c writel_relaxed(reg, div->base + map->gate_offs); reg 123 drivers/clk/berlin/berlin2-div.c u32 reg; reg 129 drivers/clk/berlin/berlin2-div.c reg = readl_relaxed(div->base + map->pll_switch_offs); reg 131 drivers/clk/berlin/berlin2-div.c reg &= ~BIT(map->pll_switch_shift); reg 133 drivers/clk/berlin/berlin2-div.c reg |= BIT(map->pll_switch_shift); reg 134 drivers/clk/berlin/berlin2-div.c writel_relaxed(reg, div->base + map->pll_switch_offs); reg 138 drivers/clk/berlin/berlin2-div.c reg = readl_relaxed(div->base + map->pll_select_offs); reg 139 drivers/clk/berlin/berlin2-div.c reg &= ~(PLL_SELECT_MASK << map->pll_select_shift); reg 140 drivers/clk/berlin/berlin2-div.c reg |= (index - 1) << map->pll_select_shift; reg 141 drivers/clk/berlin/berlin2-div.c writel_relaxed(reg, div->base + map->pll_select_offs); reg 154 drivers/clk/berlin/berlin2-div.c u32 reg; reg 161 drivers/clk/berlin/berlin2-div.c reg = readl_relaxed(div->base + map->pll_switch_offs); reg 162 drivers/clk/berlin/berlin2-div.c reg &= BIT(map->pll_switch_shift); reg 163 drivers/clk/berlin/berlin2-div.c if (reg) { reg 164 drivers/clk/berlin/berlin2-div.c reg = readl_relaxed(div->base + map->pll_select_offs); reg 165 drivers/clk/berlin/berlin2-div.c reg >>= map->pll_select_shift; reg 166 drivers/clk/berlin/berlin2-div.c reg &= PLL_SELECT_MASK; reg 167 drivers/clk/berlin/berlin2-div.c index = 1 + reg; reg 199 drivers/clk/berlin/berlin2-div.c u32 reg; reg 200 drivers/clk/berlin/berlin2-div.c reg = readl_relaxed(div->base + map->div_select_offs); reg 201 drivers/clk/berlin/berlin2-div.c reg >>= map->div_select_shift; reg 202 drivers/clk/berlin/berlin2-div.c reg &= DIV_SELECT_MASK; reg 203 drivers/clk/berlin/berlin2-div.c divider = clk_div[reg]; reg 67 drivers/clk/clk-asm9260.c u32 reg; reg 74 drivers/clk/clk-asm9260.c u32 reg; reg 302 drivers/clk/clk-asm9260.c base + gd->reg, gd->bit_idx, 0, &asm9260_clk_lock); reg 311 drivers/clk/clk-asm9260.c base + dc->reg, 0, 8, CLK_DIVIDER_ONE_BASED, reg 320 drivers/clk/clk-asm9260.c gd->parent_name, gd->flags, base + gd->reg, reg 189 drivers/clk/clk-aspeed.c u32 reg; reg 198 drivers/clk/clk-aspeed.c regmap_read(gate->map, ASPEED_RESET_CTRL, ®); reg 199 drivers/clk/clk-aspeed.c if (reg & rst) reg 203 drivers/clk/clk-aspeed.c regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®); reg 205 drivers/clk/clk-aspeed.c return ((reg & clk) == enval) ? 1 : 0; reg 292 drivers/clk/clk-aspeed.c u32 reg = ASPEED_RESET_CTRL; reg 297 drivers/clk/clk-aspeed.c reg = ASPEED_RESET_CTRL2; reg 300 drivers/clk/clk-aspeed.c return regmap_update_bits(ar->map, reg, BIT(bit), 0); reg 307 drivers/clk/clk-aspeed.c u32 reg = ASPEED_RESET_CTRL; reg 312 drivers/clk/clk-aspeed.c reg = ASPEED_RESET_CTRL2; reg 315 drivers/clk/clk-aspeed.c return regmap_update_bits(ar->map, reg, BIT(bit), BIT(bit)); reg 322 drivers/clk/clk-aspeed.c u32 reg = ASPEED_RESET_CTRL; reg 328 drivers/clk/clk-aspeed.c reg = ASPEED_RESET_CTRL2; reg 331 drivers/clk/clk-aspeed.c ret = regmap_read(ar->map, reg, &val); reg 223 drivers/clk/clk-ast2600.c u32 reg; reg 233 drivers/clk/clk-ast2600.c regmap_read(gate->map, get_reset_reg(gate), ®); reg 235 drivers/clk/clk-ast2600.c if (reg & rst) reg 239 drivers/clk/clk-ast2600.c regmap_read(gate->map, get_clock_reg(gate), ®); reg 243 drivers/clk/clk-ast2600.c return ((reg & clk) == enval) ? 1 : 0; reg 317 drivers/clk/clk-ast2600.c u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL; reg 320 drivers/clk/clk-ast2600.c return regmap_write(ar->map, reg + 0x04, rst); reg 328 drivers/clk/clk-ast2600.c u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL; reg 330 drivers/clk/clk-ast2600.c return regmap_write(ar->map, reg, rst); reg 340 drivers/clk/clk-ast2600.c u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL; reg 342 drivers/clk/clk-ast2600.c ret = regmap_read(ar->map, reg, &val); reg 161 drivers/clk/clk-axi-clkgen.c unsigned int reg, unsigned int val) reg 163 drivers/clk/clk-axi-clkgen.c writel(val, axi_clkgen->base + reg); reg 167 drivers/clk/clk-axi-clkgen.c unsigned int reg, unsigned int *val) reg 169 drivers/clk/clk-axi-clkgen.c *val = readl(axi_clkgen->base + reg); reg 188 drivers/clk/clk-axi-clkgen.c unsigned int reg, unsigned int *val) reg 198 drivers/clk/clk-axi-clkgen.c reg_val |= (reg << 16); reg 212 drivers/clk/clk-axi-clkgen.c unsigned int reg, unsigned int val, unsigned int mask) reg 222 drivers/clk/clk-axi-clkgen.c axi_clkgen_mmcm_read(axi_clkgen, reg, ®_val); reg 226 drivers/clk/clk-axi-clkgen.c reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask); reg 321 drivers/clk/clk-axi-clkgen.c unsigned int reg; reg 324 drivers/clk/clk-axi-clkgen.c axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_2, ®); reg 325 drivers/clk/clk-axi-clkgen.c if (reg & MMCM_CLKOUT_NOCOUNT) { reg 328 drivers/clk/clk-axi-clkgen.c axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_1, ®); reg 329 drivers/clk/clk-axi-clkgen.c dout = (reg & 0x3f) + ((reg >> 6) & 0x3f); reg 332 drivers/clk/clk-axi-clkgen.c axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, ®); reg 333 drivers/clk/clk-axi-clkgen.c if (reg & MMCM_CLK_DIV_NOCOUNT) reg 336 drivers/clk/clk-axi-clkgen.c d = (reg & 0x3f) + ((reg >> 6) & 0x3f); reg 338 drivers/clk/clk-axi-clkgen.c axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB2, ®); reg 339 drivers/clk/clk-axi-clkgen.c if (reg & MMCM_CLKOUT_NOCOUNT) { reg 342 drivers/clk/clk-axi-clkgen.c axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB1, ®); reg 343 drivers/clk/clk-axi-clkgen.c m = (reg & 0x3f) + ((reg >> 6) & 0x3f); reg 39 drivers/clk/clk-axm5516.c u32 reg; reg 55 drivers/clk/clk-axm5516.c regmap_read(aclk->regmap, pll->reg, &control); reg 77 drivers/clk/clk-axm5516.c u32 reg; reg 93 drivers/clk/clk-axm5516.c regmap_read(aclk->regmap, divclk->reg, &ctrl); reg 112 drivers/clk/clk-axm5516.c u32 reg; reg 127 drivers/clk/clk-axm5516.c regmap_read(aclk->regmap, mux->reg, &ctrl); reg 151 drivers/clk/clk-axm5516.c .reg = 0x01800, reg 163 drivers/clk/clk-axm5516.c .reg = 0x02000, reg 175 drivers/clk/clk-axm5516.c .reg = 0x02800, reg 187 drivers/clk/clk-axm5516.c .reg = 0x03000, reg 199 drivers/clk/clk-axm5516.c .reg = 0x03800, reg 215 drivers/clk/clk-axm5516.c .reg = 0x10008, reg 229 drivers/clk/clk-axm5516.c .reg = 0x10008, reg 243 drivers/clk/clk-axm5516.c .reg = 0x10008, reg 257 drivers/clk/clk-axm5516.c .reg = 0x10008, reg 271 drivers/clk/clk-axm5516.c .reg = 0x1000c, reg 285 drivers/clk/clk-axm5516.c .reg = 0x1000c, reg 299 drivers/clk/clk-axm5516.c .reg = 0x1000c, reg 313 drivers/clk/clk-axm5516.c .reg = 0x1000c, reg 327 drivers/clk/clk-axm5516.c .reg = 0x1000c, reg 348 drivers/clk/clk-axm5516.c .reg = 0x10000, reg 365 drivers/clk/clk-axm5516.c .reg = 0x10000, reg 382 drivers/clk/clk-axm5516.c .reg = 0x10000, reg 399 drivers/clk/clk-axm5516.c .reg = 0x10000, reg 416 drivers/clk/clk-axm5516.c .reg = 0x10004, reg 433 drivers/clk/clk-axm5516.c .reg = 0x10004, reg 450 drivers/clk/clk-axm5516.c .reg = 0x10004, reg 465 drivers/clk/clk-axm5516.c .reg = 0x10004, reg 480 drivers/clk/clk-axm5516.c .reg = 0x10004, reg 18 drivers/clk/clk-bd718x7.c u8 reg; reg 28 drivers/clk/clk-bd718x7.c return regmap_update_bits(c->mfd->regmap, c->reg, c->mask, status); reg 52 drivers/clk/clk-bd718x7.c rval = regmap_read(c->mfd->regmap, c->reg, &enabled); reg 93 drivers/clk/clk-bd718x7.c c->reg = BD718XX_REG_OUT32K; reg 97 drivers/clk/clk-bd718x7.c c->reg = BD70528_REG_CLK_OUT; reg 112 drivers/clk/clk-cdce706.c static int cdce706_reg_read(struct cdce706_dev_data *dev_data, unsigned reg, reg 115 drivers/clk/clk-cdce706.c int rc = regmap_read(dev_data->regmap, reg | 0x80, val); reg 118 drivers/clk/clk-cdce706.c dev_err(&dev_data->client->dev, "error reading reg %u", reg); reg 122 drivers/clk/clk-cdce706.c static int cdce706_reg_write(struct cdce706_dev_data *dev_data, unsigned reg, reg 125 drivers/clk/clk-cdce706.c int rc = regmap_write(dev_data->regmap, reg | 0x80, val); reg 128 drivers/clk/clk-cdce706.c dev_err(&dev_data->client->dev, "error writing reg %u", reg); reg 132 drivers/clk/clk-cdce706.c static int cdce706_reg_update(struct cdce706_dev_data *dev_data, unsigned reg, reg 135 drivers/clk/clk-cdce706.c int rc = regmap_update_bits(dev_data->regmap, reg | 0x80, mask, val); reg 138 drivers/clk/clk-cdce706.c dev_err(&dev_data->client->dev, "error updating reg %u", reg); reg 551 drivers/clk/clk-cdce925.c const void *reg, size_t reg_size, void *val, size_t val_size) reg 567 drivers/clk/clk-cdce925.c CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)reg)[0]; reg 571 drivers/clk/clk-cdce925.c CDCE925_I2C_COMMAND_BLOCK_TRANSFER | ((u8 *)reg)[0]; reg 31 drivers/clk/clk-divider.c return ioread32be(divider->reg); reg 33 drivers/clk/clk-divider.c return readl(divider->reg); reg 39 drivers/clk/clk-divider.c iowrite32be(val, divider->reg); reg 41 drivers/clk/clk-divider.c writel(val, divider->reg); reg 468 drivers/clk/clk-divider.c void __iomem *reg, u8 shift, u8 width, reg 499 drivers/clk/clk-divider.c div->reg = reg; reg 532 drivers/clk/clk-divider.c void __iomem *reg, u8 shift, u8 width, reg 537 drivers/clk/clk-divider.c hw = _register_divider(dev, name, parent_name, flags, reg, shift, reg 559 drivers/clk/clk-divider.c void __iomem *reg, u8 shift, u8 width, reg 562 drivers/clk/clk-divider.c return _register_divider(dev, name, parent_name, flags, reg, shift, reg 583 drivers/clk/clk-divider.c void __iomem *reg, u8 shift, u8 width, reg 589 drivers/clk/clk-divider.c hw = _register_divider(dev, name, parent_name, flags, reg, shift, reg 613 drivers/clk/clk-divider.c void __iomem *reg, u8 shift, u8 width, reg 617 drivers/clk/clk-divider.c return _register_divider(dev, name, parent_name, flags, reg, shift, reg 20 drivers/clk/clk-fractional-divider.c return ioread32be(fd->reg); reg 22 drivers/clk/clk-fractional-divider.c return readl(fd->reg); reg 28 drivers/clk/clk-fractional-divider.c iowrite32be(val, fd->reg); reg 30 drivers/clk/clk-fractional-divider.c writel(val, fd->reg); reg 157 drivers/clk/clk-fractional-divider.c void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, reg 175 drivers/clk/clk-fractional-divider.c fd->reg = reg; reg 199 drivers/clk/clk-fractional-divider.c void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, reg 205 drivers/clk/clk-fractional-divider.c reg, mshift, mwidth, nshift, nwidth, clk_divider_flags, reg 29 drivers/clk/clk-gate.c return ioread32be(gate->reg); reg 31 drivers/clk/clk-gate.c return readl(gate->reg); reg 37 drivers/clk/clk-gate.c iowrite32be(val, gate->reg); reg 39 drivers/clk/clk-gate.c writel(val, gate->reg); reg 60 drivers/clk/clk-gate.c u32 reg; reg 70 drivers/clk/clk-gate.c reg = BIT(gate->bit_idx + 16); reg 72 drivers/clk/clk-gate.c reg |= BIT(gate->bit_idx); reg 74 drivers/clk/clk-gate.c reg = clk_gate_readl(gate); reg 77 drivers/clk/clk-gate.c reg |= BIT(gate->bit_idx); reg 79 drivers/clk/clk-gate.c reg &= ~BIT(gate->bit_idx); reg 82 drivers/clk/clk-gate.c clk_gate_writel(gate, reg); reg 104 drivers/clk/clk-gate.c u32 reg; reg 107 drivers/clk/clk-gate.c reg = clk_gate_readl(gate); reg 111 drivers/clk/clk-gate.c reg ^= BIT(gate->bit_idx); reg 113 drivers/clk/clk-gate.c reg &= BIT(gate->bit_idx); reg 115 drivers/clk/clk-gate.c return reg ? 1 : 0; reg 139 drivers/clk/clk-gate.c void __iomem *reg, u8 bit_idx, reg 166 drivers/clk/clk-gate.c gate->reg = reg; reg 185 drivers/clk/clk-gate.c void __iomem *reg, u8 bit_idx, reg 190 drivers/clk/clk-gate.c hw = clk_hw_register_gate(dev, name, parent_name, flags, reg, reg 39 drivers/clk/clk-highbank.c void __iomem *reg; reg 47 drivers/clk/clk-highbank.c u32 reg; reg 49 drivers/clk/clk-highbank.c reg = readl(hbclk->reg); reg 50 drivers/clk/clk-highbank.c reg &= ~HB_PLL_RESET; reg 51 drivers/clk/clk-highbank.c writel(reg, hbclk->reg); reg 53 drivers/clk/clk-highbank.c while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) reg 55 drivers/clk/clk-highbank.c while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) reg 64 drivers/clk/clk-highbank.c u32 reg; reg 66 drivers/clk/clk-highbank.c reg = readl(hbclk->reg); reg 67 drivers/clk/clk-highbank.c reg |= HB_PLL_RESET; reg 68 drivers/clk/clk-highbank.c writel(reg, hbclk->reg); reg 74 drivers/clk/clk-highbank.c u32 reg; reg 76 drivers/clk/clk-highbank.c reg = readl(hbclk->reg); reg 77 drivers/clk/clk-highbank.c reg |= HB_PLL_EXT_ENA; reg 78 drivers/clk/clk-highbank.c writel(reg, hbclk->reg); reg 86 drivers/clk/clk-highbank.c u32 reg; reg 88 drivers/clk/clk-highbank.c reg = readl(hbclk->reg); reg 89 drivers/clk/clk-highbank.c reg &= ~HB_PLL_EXT_ENA; reg 90 drivers/clk/clk-highbank.c writel(reg, hbclk->reg); reg 97 drivers/clk/clk-highbank.c unsigned long divf, divq, vco_freq, reg; reg 99 drivers/clk/clk-highbank.c reg = readl(hbclk->reg); reg 100 drivers/clk/clk-highbank.c if (reg & HB_PLL_EXT_BYPASS) reg 103 drivers/clk/clk-highbank.c divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT; reg 104 drivers/clk/clk-highbank.c divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT; reg 150 drivers/clk/clk-highbank.c u32 reg; reg 154 drivers/clk/clk-highbank.c reg = readl(hbclk->reg); reg 155 drivers/clk/clk-highbank.c if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) { reg 157 drivers/clk/clk-highbank.c reg |= HB_PLL_EXT_BYPASS; reg 158 drivers/clk/clk-highbank.c writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); reg 160 drivers/clk/clk-highbank.c writel(reg | HB_PLL_RESET, hbclk->reg); reg 161 drivers/clk/clk-highbank.c reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK); reg 162 drivers/clk/clk-highbank.c reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT); reg 163 drivers/clk/clk-highbank.c writel(reg | HB_PLL_RESET, hbclk->reg); reg 164 drivers/clk/clk-highbank.c writel(reg, hbclk->reg); reg 166 drivers/clk/clk-highbank.c while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) reg 168 drivers/clk/clk-highbank.c while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) reg 170 drivers/clk/clk-highbank.c reg |= HB_PLL_EXT_ENA; reg 171 drivers/clk/clk-highbank.c reg &= ~HB_PLL_EXT_BYPASS; reg 173 drivers/clk/clk-highbank.c writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); reg 174 drivers/clk/clk-highbank.c reg &= ~HB_PLL_DIVQ_MASK; reg 175 drivers/clk/clk-highbank.c reg |= divq << HB_PLL_DIVQ_SHIFT; reg 176 drivers/clk/clk-highbank.c writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); reg 178 drivers/clk/clk-highbank.c writel(reg, hbclk->reg); reg 197 drivers/clk/clk-highbank.c u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4; reg 209 drivers/clk/clk-highbank.c u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT; reg 224 drivers/clk/clk-highbank.c div = readl(hbclk->reg) & 0x1f; reg 253 drivers/clk/clk-highbank.c writel(div >> 1, hbclk->reg); reg 265 drivers/clk/clk-highbank.c u32 reg; reg 273 drivers/clk/clk-highbank.c rc = of_property_read_u32(node, "reg", ®); reg 283 drivers/clk/clk-highbank.c hb_clk->reg = of_iomap(srnp, 0); reg 285 drivers/clk/clk-highbank.c BUG_ON(!hb_clk->reg); reg 286 drivers/clk/clk-highbank.c hb_clk->reg += reg; reg 122 drivers/clk/clk-hsdk-pll.c static inline void hsdk_pll_write(struct hsdk_pll_clk *clk, u32 reg, u32 val) reg 124 drivers/clk/clk-hsdk-pll.c iowrite32(val, clk->regs + reg); reg 127 drivers/clk/clk-hsdk-pll.c static inline u32 hsdk_pll_read(struct hsdk_pll_clk *clk, u32 reg) reg 129 drivers/clk/clk-hsdk-pll.c return ioread32(clk->regs + reg); reg 285 drivers/clk/clk-milbeaut.c val = readl(mux->reg) >> mux->shift; reg 296 drivers/clk/clk-milbeaut.c u32 reg; reg 304 drivers/clk/clk-milbeaut.c reg = readl(mux->reg); reg 305 drivers/clk/clk-milbeaut.c reg &= ~(mux->mask << mux->shift); reg 308 drivers/clk/clk-milbeaut.c reg |= val; reg 309 drivers/clk/clk-milbeaut.c writel(reg, mux->reg); reg 327 drivers/clk/clk-milbeaut.c u8 num_parents, unsigned long flags, void __iomem *reg, reg 346 drivers/clk/clk-milbeaut.c mux->reg = reg; reg 367 drivers/clk/clk-milbeaut.c void __iomem *reg; reg 382 drivers/clk/clk-milbeaut.c val = readl(divider->reg) >> divider->shift; reg 398 drivers/clk/clk-milbeaut.c val = readl(divider->reg) >> divider->shift; reg 429 drivers/clk/clk-milbeaut.c val = readl(divider->reg); reg 433 drivers/clk/clk-milbeaut.c writel(val, divider->reg); reg 459 drivers/clk/clk-milbeaut.c void __iomem *reg, u8 shift, u8 width, reg 478 drivers/clk/clk-milbeaut.c div->reg = reg; reg 18 drivers/clk/clk-multiplier.c return ioread32be(mult->reg); reg 20 drivers/clk/clk-multiplier.c return readl(mult->reg); reg 26 drivers/clk/clk-multiplier.c iowrite32be(val, mult->reg); reg 28 drivers/clk/clk-multiplier.c writel(val, mult->reg); reg 29 drivers/clk/clk-mux.c return ioread32be(mux->reg); reg 31 drivers/clk/clk-mux.c return readl(mux->reg); reg 37 drivers/clk/clk-mux.c iowrite32be(val, mux->reg); reg 39 drivers/clk/clk-mux.c writel(val, mux->reg); reg 103 drivers/clk/clk-mux.c u32 reg; reg 111 drivers/clk/clk-mux.c reg = mux->mask << (mux->shift + 16); reg 113 drivers/clk/clk-mux.c reg = clk_mux_readl(mux); reg 114 drivers/clk/clk-mux.c reg &= ~(mux->mask << mux->shift); reg 117 drivers/clk/clk-mux.c reg |= val; reg 118 drivers/clk/clk-mux.c clk_mux_writel(mux, reg); reg 151 drivers/clk/clk-mux.c void __iomem *reg, u8 shift, u32 mask, reg 183 drivers/clk/clk-mux.c mux->reg = reg; reg 205 drivers/clk/clk-mux.c void __iomem *reg, u8 shift, u32 mask, reg 211 drivers/clk/clk-mux.c flags, reg, shift, mask, clk_mux_flags, reg 222 drivers/clk/clk-mux.c void __iomem *reg, u8 shift, u8 width, reg 228 drivers/clk/clk-mux.c flags, reg, shift, mask, clk_mux_flags, reg 236 drivers/clk/clk-mux.c void __iomem *reg, u8 shift, u8 width, reg 242 drivers/clk/clk-mux.c flags, reg, shift, mask, clk_mux_flags, reg 133 drivers/clk/clk-npcm7xx.c u32 reg; reg 179 drivers/clk/clk-npcm7xx.c u32 reg; reg 195 drivers/clk/clk-npcm7xx.c u32 reg; reg 575 drivers/clk/clk-npcm7xx.c hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg, reg 628 drivers/clk/clk-npcm7xx.c clk_base + div_data->reg, reg 99 drivers/clk/clk-qoriq.c static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg) reg 102 drivers/clk/clk-qoriq.c iowrite32(val, reg); reg 104 drivers/clk/clk-qoriq.c iowrite32be(val, reg); reg 107 drivers/clk/clk-qoriq.c static u32 cg_in(struct clockgen *cg, u32 __iomem *reg) reg 112 drivers/clk/clk-qoriq.c val = ioread32(reg); reg 114 drivers/clk/clk-qoriq.c val = ioread32be(reg); reg 434 drivers/clk/clk-qoriq.c u32 reg; reg 436 drivers/clk/clk-qoriq.c reg = ioread32be(&cg->guts->rcwsr[7]); reg 438 drivers/clk/clk-qoriq.c if (reg & RCWSR7_FM1_CLK_SEL) reg 446 drivers/clk/clk-qoriq.c u32 reg; reg 448 drivers/clk/clk-qoriq.c reg = ioread32be(&cg->guts->rcwsr[7]); reg 450 drivers/clk/clk-qoriq.c if (reg & RCWSR7_FM1_CLK_SEL) reg 455 drivers/clk/clk-qoriq.c if (reg & RCWSR7_FM2_CLK_SEL) reg 463 drivers/clk/clk-qoriq.c u32 reg; reg 466 drivers/clk/clk-qoriq.c reg = ioread32be(&cg->guts->rcwsr[7]); reg 467 drivers/clk/clk-qoriq.c if (reg & RCWSR7_HWA_ASYNC_DIV) reg 470 drivers/clk/clk-qoriq.c if (reg & RCWSR7_FM1_CLK_SEL) reg 478 drivers/clk/clk-qoriq.c u32 reg; reg 481 drivers/clk/clk-qoriq.c reg = ioread32be(&cg->guts->rcwsr[7]); reg 482 drivers/clk/clk-qoriq.c if (reg & RCWSR7_HWA_ASYNC_DIV) reg 485 drivers/clk/clk-qoriq.c if (reg & RCWSR7_FM1_CLK_SEL) reg 490 drivers/clk/clk-qoriq.c if (reg & RCWSR7_FM2_CLK_SEL) reg 776 drivers/clk/clk-qoriq.c u32 __iomem *reg; reg 795 drivers/clk/clk-qoriq.c cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); reg 806 drivers/clk/clk-qoriq.c clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; reg 810 drivers/clk/clk-qoriq.c pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg); reg 919 drivers/clk/clk-qoriq.c hwc->reg = cg->regs + 0x70000 + 0x20 * idx; reg 921 drivers/clk/clk-qoriq.c hwc->reg = cg->regs + 0x20 * idx; reg 932 drivers/clk/clk-qoriq.c clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; reg 962 drivers/clk/clk-qoriq.c hwc->reg = cg->regs + 0x20 * idx + 0x10; reg 1143 drivers/clk/clk-qoriq.c u32 __iomem *reg; reg 1162 drivers/clk/clk-qoriq.c reg = cg->regs + 0x60080; reg 1165 drivers/clk/clk-qoriq.c reg = cg->regs + 0x80; reg 1168 drivers/clk/clk-qoriq.c reg = cg->regs + 0xa0; reg 1171 drivers/clk/clk-qoriq.c reg = cg->regs + 0x10080; reg 1174 drivers/clk/clk-qoriq.c reg = cg->regs + 0x100a0; reg 1182 drivers/clk/clk-qoriq.c reg = cg->regs + 0xc00; reg 1184 drivers/clk/clk-qoriq.c reg = cg->regs + 0x800 + 0x20 * (idx - 1); reg 1188 drivers/clk/clk-qoriq.c mult = cg_in(cg, reg); reg 1192 drivers/clk/clk-qoriq.c pr_debug("%s(): pll %p disabled\n", __func__, reg); reg 29 drivers/clk/clk-s2mps11.c unsigned int reg; reg 42 drivers/clk/clk-s2mps11.c s2mps11->reg, reg 50 drivers/clk/clk-s2mps11.c regmap_update_bits(s2mps11->iodev->regmap_pmic, s2mps11->reg, reg 61 drivers/clk/clk-s2mps11.c s2mps11->reg, &val); reg 169 drivers/clk/clk-s2mps11.c s2mps11_clks[i].reg = s2mps11_reg; reg 100 drivers/clk/clk-si514.c u8 reg[7]; reg 103 drivers/clk/clk-si514.c reg, ARRAY_SIZE(reg)); reg 107 drivers/clk/clk-si514.c settings->m_frac = reg[0] | reg[1] << 8 | reg[2] << 16 | reg 108 drivers/clk/clk-si514.c (reg[3] & 0x1F) << 24; reg 109 drivers/clk/clk-si514.c settings->m_int = (reg[4] & 0x3f) << 3 | reg[3] >> 5; reg 110 drivers/clk/clk-si514.c settings->ls_div_bits = (reg[6] >> 4) & 0x07; reg 111 drivers/clk/clk-si514.c settings->hs_div = (reg[6] & 0x03) << 8 | reg[5]; reg 119 drivers/clk/clk-si514.c u8 reg[7]; reg 146 drivers/clk/clk-si514.c reg[0] = settings->m_frac; reg 147 drivers/clk/clk-si514.c reg[1] = settings->m_frac >> 8; reg 148 drivers/clk/clk-si514.c reg[2] = settings->m_frac >> 16; reg 149 drivers/clk/clk-si514.c reg[3] = settings->m_frac >> 24 | settings->m_int << 5; reg 150 drivers/clk/clk-si514.c reg[4] = settings->m_int >> 3; reg 151 drivers/clk/clk-si514.c reg[5] = settings->hs_div; reg 152 drivers/clk/clk-si514.c reg[6] = (settings->hs_div >> 8) | (settings->ls_div_bits << 4); reg 154 drivers/clk/clk-si514.c err = regmap_bulk_write(data->regmap, SI514_REG_HS_DIV, reg + 5, 2); reg 161 drivers/clk/clk-si514.c return regmap_bulk_write(data->regmap, SI514_REG_M_FRAC1, reg, 5); reg 296 drivers/clk/clk-si514.c static bool si514_regmap_is_volatile(struct device *dev, unsigned int reg) reg 298 drivers/clk/clk-si514.c switch (reg) { reg 307 drivers/clk/clk-si514.c static bool si514_regmap_is_writeable(struct device *dev, unsigned int reg) reg 309 drivers/clk/clk-si514.c switch (reg) { reg 310 drivers/clk/clk-si5341.c static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg, reg 316 drivers/clk/clk-si5341.c err = regmap_bulk_read(regmap, reg, r, 10); reg 327 drivers/clk/clk-si5341.c static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg, reg 346 drivers/clk/clk-si5341.c return regmap_bulk_write(regmap, reg, r, sizeof(r)); reg 823 drivers/clk/clk-si5341.c u8 reg[4]; reg 826 drivers/clk/clk-si5341.c err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg, reg 827 drivers/clk/clk-si5341.c ARRAY_SIZE(reg)); reg 833 drivers/clk/clk-si5341.c model = get_unaligned_le16(reg); reg 836 drivers/clk/clk-si5341.c model, reg[2], reg[3]); reg 83 drivers/clk/clk-si5351.c static inline u8 si5351_reg_read(struct si5351_driver_data *drvdata, u8 reg) reg 88 drivers/clk/clk-si5351.c ret = regmap_read(drvdata->regmap, reg, &val); reg 91 drivers/clk/clk-si5351.c "unable to read from reg%02x\n", reg); reg 99 drivers/clk/clk-si5351.c u8 reg, u8 count, u8 *buf) reg 101 drivers/clk/clk-si5351.c return regmap_bulk_read(drvdata->regmap, reg, buf, count); reg 105 drivers/clk/clk-si5351.c u8 reg, u8 val) reg 107 drivers/clk/clk-si5351.c return regmap_write(drvdata->regmap, reg, val); reg 111 drivers/clk/clk-si5351.c u8 reg, u8 count, const u8 *buf) reg 113 drivers/clk/clk-si5351.c return regmap_raw_write(drvdata->regmap, reg, buf, count); reg 117 drivers/clk/clk-si5351.c u8 reg, u8 mask, u8 val) reg 119 drivers/clk/clk-si5351.c return regmap_update_bits(drvdata->regmap, reg, mask, val); reg 130 drivers/clk/clk-si5351.c u8 reg, struct si5351_parameters *params) reg 134 drivers/clk/clk-si5351.c switch (reg) { reg 137 drivers/clk/clk-si5351.c buf[0] = si5351_reg_read(drvdata, reg); reg 143 drivers/clk/clk-si5351.c si5351_bulk_read(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf); reg 152 drivers/clk/clk-si5351.c u8 reg, struct si5351_parameters *params) reg 156 drivers/clk/clk-si5351.c switch (reg) { reg 160 drivers/clk/clk-si5351.c si5351_reg_write(drvdata, reg, buf[0]); reg 166 drivers/clk/clk-si5351.c buf[2] = si5351_reg_read(drvdata, reg + 2) & ~0x03; reg 174 drivers/clk/clk-si5351.c si5351_bulk_write(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf); reg 178 drivers/clk/clk-si5351.c static bool si5351_regmap_is_volatile(struct device *dev, unsigned int reg) reg 180 drivers/clk/clk-si5351.c switch (reg) { reg 189 drivers/clk/clk-si5351.c static bool si5351_regmap_is_writeable(struct device *dev, unsigned int reg) reg 192 drivers/clk/clk-si5351.c if (reg >= 4 && reg <= 8) reg 194 drivers/clk/clk-si5351.c if (reg >= 10 && reg <= 14) reg 196 drivers/clk/clk-si5351.c if (reg >= 173 && reg <= 176) reg 198 drivers/clk/clk-si5351.c if (reg >= 178 && reg <= 182) reg 201 drivers/clk/clk-si5351.c if (reg == SI5351_DEVICE_STATUS) reg 419 drivers/clk/clk-si5351.c u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS : reg 424 drivers/clk/clk-si5351.c si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params); reg 507 drivers/clk/clk-si5351.c u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS : reg 511 drivers/clk/clk-si5351.c si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params); reg 604 drivers/clk/clk-si5351.c u8 reg = si5351_msynth_params_address(hwdata->num); reg 609 drivers/clk/clk-si5351.c si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params); reg 620 drivers/clk/clk-si5351.c } else if ((si5351_reg_read(hwdata->drvdata, reg + 2) & reg 760 drivers/clk/clk-si5351.c u8 reg = si5351_msynth_params_address(hwdata->num); reg 764 drivers/clk/clk-si5351.c si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params); reg 771 drivers/clk/clk-si5351.c si5351_set_bits(hwdata->drvdata, reg + 2, reg 871 drivers/clk/clk-si5351.c u8 reg = (num < 4) ? SI5351_CLK3_0_DISABLE_STATE : reg 897 drivers/clk/clk-si5351.c si5351_set_bits(drvdata, reg, mask, val << shift); reg 1009 drivers/clk/clk-si5351.c unsigned char reg; reg 1013 drivers/clk/clk-si5351.c reg = si5351_msynth_params_address(hwdata->num) + 2; reg 1015 drivers/clk/clk-si5351.c reg = SI5351_CLK6_7_OUTPUT_DIVIDER; reg 1017 drivers/clk/clk-si5351.c rdiv = si5351_reg_read(hwdata->drvdata, reg); reg 129 drivers/clk/clk-si544.c u8 reg[6]; reg 131 drivers/clk/clk-si544.c err = regmap_bulk_read(data->regmap, SI544_REG_HS_DIV, reg, 2); reg 135 drivers/clk/clk-si544.c settings->ls_div_bits = (reg[1] >> 4) & 0x07; reg 136 drivers/clk/clk-si544.c settings->hs_div = (reg[1] & 0x07) << 8 | reg[0]; reg 138 drivers/clk/clk-si544.c err = regmap_bulk_read(data->regmap, SI544_REG_FBDIV0, reg, 6); reg 142 drivers/clk/clk-si544.c settings->fb_div_int = reg[4] | (reg[5] & 0x07) << 8; reg 143 drivers/clk/clk-si544.c settings->fb_div_frac = reg[0] | reg[1] << 8 | reg[2] << 16 | reg 144 drivers/clk/clk-si544.c reg[3] << 24; reg 146 drivers/clk/clk-si544.c err = regmap_bulk_read(data->regmap, SI544_REG_ADPLL_DELTA_M0, reg, 3); reg 151 drivers/clk/clk-si544.c settings->delta_m = reg[0] << 8 | reg[1] << 16 | reg[2] << 24; reg 159 drivers/clk/clk-si544.c u8 reg[3]; reg 161 drivers/clk/clk-si544.c reg[0] = delta_m; reg 162 drivers/clk/clk-si544.c reg[1] = delta_m >> 8; reg 163 drivers/clk/clk-si544.c reg[2] = delta_m >> 16; reg 166 drivers/clk/clk-si544.c reg, 3); reg 173 drivers/clk/clk-si544.c u8 reg[6]; reg 175 drivers/clk/clk-si544.c reg[0] = settings->hs_div; reg 176 drivers/clk/clk-si544.c reg[1] = settings->hs_div >> 8 | settings->ls_div_bits << 4; reg 178 drivers/clk/clk-si544.c err = regmap_bulk_write(data->regmap, SI544_REG_HS_DIV, reg, 2); reg 182 drivers/clk/clk-si544.c reg[0] = settings->fb_div_frac; reg 183 drivers/clk/clk-si544.c reg[1] = settings->fb_div_frac >> 8; reg 184 drivers/clk/clk-si544.c reg[2] = settings->fb_div_frac >> 16; reg 185 drivers/clk/clk-si544.c reg[3] = settings->fb_div_frac >> 24; reg 186 drivers/clk/clk-si544.c reg[4] = settings->fb_div_int; reg 187 drivers/clk/clk-si544.c reg[5] = settings->fb_div_int >> 8; reg 193 drivers/clk/clk-si544.c return regmap_bulk_write(data->regmap, SI544_REG_FBDIV0, reg, 6); reg 435 drivers/clk/clk-si544.c static bool si544_regmap_is_volatile(struct device *dev, unsigned int reg) reg 437 drivers/clk/clk-si544.c switch (reg) { reg 98 drivers/clk/clk-si570.c u8 reg[6]; reg 102 drivers/clk/clk-si570.c reg, ARRAY_SIZE(reg)); reg 106 drivers/clk/clk-si570.c *hs_div = ((reg[0] & HS_DIV_MASK) >> HS_DIV_SHIFT) + HS_DIV_OFFSET; reg 107 drivers/clk/clk-si570.c *n1 = ((reg[0] & N1_6_2_MASK) << 2) + ((reg[1] & N1_1_0_MASK) >> 6) + 1; reg 112 drivers/clk/clk-si570.c tmp = reg[1] & RFREQ_37_32_MASK; reg 113 drivers/clk/clk-si570.c tmp = (tmp << 8) + reg[2]; reg 114 drivers/clk/clk-si570.c tmp = (tmp << 8) + reg[3]; reg 115 drivers/clk/clk-si570.c tmp = (tmp << 8) + reg[4]; reg 116 drivers/clk/clk-si570.c tmp = (tmp << 8) + reg[5]; reg 161 drivers/clk/clk-si570.c u8 reg[5]; reg 163 drivers/clk/clk-si570.c reg[0] = ((data->n1 - 1) << 6) | reg 165 drivers/clk/clk-si570.c reg[1] = (data->rfreq >> 24) & 0xff; reg 166 drivers/clk/clk-si570.c reg[2] = (data->rfreq >> 16) & 0xff; reg 167 drivers/clk/clk-si570.c reg[3] = (data->rfreq >> 8) & 0xff; reg 168 drivers/clk/clk-si570.c reg[4] = data->rfreq & 0xff; reg 171 drivers/clk/clk-si570.c data->div_offset, reg, ARRAY_SIZE(reg)); reg 366 drivers/clk/clk-si570.c static bool si570_regmap_is_volatile(struct device *dev, unsigned int reg) reg 368 drivers/clk/clk-si570.c switch (reg) { reg 376 drivers/clk/clk-si570.c static bool si570_regmap_is_writeable(struct device *dev, unsigned int reg) reg 378 drivers/clk/clk-si570.c switch (reg) { reg 622 drivers/clk/clk-stm32f4.c bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx)); reg 747 drivers/clk/clk-stm32f4.c void __iomem *reg, u8 shift, u8 width, reg 768 drivers/clk/clk-stm32f4.c pll_div->div.reg = reg; reg 794 drivers/clk/clk-stm32f4.c void __iomem *reg; reg 814 drivers/clk/clk-stm32f4.c pll->gate.reg = base + STM32F4_RCC_CR; reg 823 drivers/clk/clk-stm32f4.c reg = base + pll->offset; reg 837 drivers/clk/clk-stm32f4.c reg, reg 934 drivers/clk/clk-stm32f4.c bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy_idx)); reg 963 drivers/clk/clk-stm32f4.c void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx, reg 984 drivers/clk/clk-stm32f4.c rgate->gate.reg = reg; reg 1058 drivers/clk/clk-stm32f4.c void __iomem *reg, u8 bit_idx, u8 shift, unsigned long flags, reg 1078 drivers/clk/clk-stm32f4.c gate->reg = reg; reg 1083 drivers/clk/clk-stm32f4.c mux->reg = reg; reg 1645 drivers/clk/clk-stm32f4.c gate->reg = base + offset_gate; reg 1660 drivers/clk/clk-stm32f4.c mux->reg = base + offset_mux; reg 178 drivers/clk/clk-stm32h7.c bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy)); reg 201 drivers/clk/clk-stm32h7.c bit_status = !!(readl(gate->reg) & BIT(rgate->bit_rdy)); reg 217 drivers/clk/clk-stm32h7.c void __iomem *reg, u8 bit_idx, u8 bit_rdy, reg 237 drivers/clk/clk-stm32h7.c rgate->gate.reg = reg; reg 295 drivers/clk/clk-stm32h7.c static struct clk_mux *_get_cmux(void __iomem *reg, u8 shift, u8 width, reg 304 drivers/clk/clk-stm32h7.c mux->reg = reg; reg 313 drivers/clk/clk-stm32h7.c static struct clk_divider *_get_cdiv(void __iomem *reg, u8 shift, u8 width, reg 323 drivers/clk/clk-stm32h7.c div->reg = reg; reg 332 drivers/clk/clk-stm32h7.c static struct clk_gate *_get_cgate(void __iomem *reg, u8 bit_idx, u32 flags, reg 341 drivers/clk/clk-stm32h7.c gate->reg = reg; reg 812 drivers/clk/clk-stm32h7.c rgate->gate.reg = base + RCC_CR; reg 461 drivers/clk/clk-stm32mp1.c writel_relaxed(BIT(gate->bit_idx), gate->reg + RCC_CLR); reg 485 drivers/clk/clk-stm32mp1.c mmux->mux.reg = cfg->mux->reg_off + base; reg 500 drivers/clk/clk-stm32mp1.c mux->reg = cfg->mux->reg_off + base; reg 523 drivers/clk/clk-stm32mp1.c div->reg = cfg->div->reg_off + base; reg 546 drivers/clk/clk-stm32mp1.c mgate->gate.reg = cfg->gate->reg_off + base; reg 561 drivers/clk/clk-stm32mp1.c gate->reg = cfg->gate->reg_off + base; reg 732 drivers/clk/clk-stm32mp1.c void __iomem *reg; reg 753 drivers/clk/clk-stm32mp1.c return readl_relaxed(clk_elem->reg) & PLL_ON; reg 761 drivers/clk/clk-stm32mp1.c u32 reg; reg 771 drivers/clk/clk-stm32mp1.c reg = readl_relaxed(clk_elem->reg); reg 772 drivers/clk/clk-stm32mp1.c reg |= PLL_ON; reg 773 drivers/clk/clk-stm32mp1.c writel_relaxed(reg, clk_elem->reg); reg 781 drivers/clk/clk-stm32mp1.c bit_status = !(readl_relaxed(clk_elem->reg) & PLL_RDY); reg 797 drivers/clk/clk-stm32mp1.c u32 reg; reg 802 drivers/clk/clk-stm32mp1.c reg = readl_relaxed(clk_elem->reg); reg 803 drivers/clk/clk-stm32mp1.c reg &= ~PLL_ON; reg 804 drivers/clk/clk-stm32mp1.c writel_relaxed(reg, clk_elem->reg); reg 812 drivers/clk/clk-stm32mp1.c u32 reg, frac = 0; reg 814 drivers/clk/clk-stm32mp1.c reg = readl_relaxed(clk_elem->reg + FRAC_OFFSET); reg 815 drivers/clk/clk-stm32mp1.c if (reg & FRACLE) reg 816 drivers/clk/clk-stm32mp1.c frac = (reg >> FRAC_SHIFT) & FRAC_MASK; reg 825 drivers/clk/clk-stm32mp1.c u32 reg; reg 829 drivers/clk/clk-stm32mp1.c reg = readl_relaxed(clk_elem->reg + 4); reg 831 drivers/clk/clk-stm32mp1.c divm = ((reg >> DIVM_SHIFT) & DIVM_MASK) + 1; reg 832 drivers/clk/clk-stm32mp1.c divn = ((reg >> DIVN_SHIFT) & DIVN_MASK) + 1; reg 868 drivers/clk/clk-stm32mp1.c void __iomem *reg, reg 888 drivers/clk/clk-stm32mp1.c element->reg = reg; reg 31 drivers/clk/clk-twl6040.c unsigned int reg) reg 36 drivers/clk/clk-twl6040.c ret = twl6040_set_bits(pdmclk->twl6040, reg, reset_mask); reg 40 drivers/clk/clk-twl6040.c ret = twl6040_clear_bits(pdmclk->twl6040, reg, reset_mask); reg 1068 drivers/clk/clk-u300.c u16 reg; reg 1102 drivers/clk/clk-u300.c reg = readw(syscon_vbase + U300_SYSCON_MMF0R) & reg 1104 drivers/clk/clk-u300.c writew(reg | val, syscon_vbase + U300_SYSCON_MMF0R); reg 190 drivers/clk/clk-versaclock5.c static bool vc5_regmap_is_writeable(struct device *dev, unsigned int reg) reg 193 drivers/clk/clk-versaclock5.c if (reg <= 0xf) reg 197 drivers/clk/clk-versaclock5.c if (reg == 0x14 || reg == 0x1c || reg == 0x1d) reg 43 drivers/clk/clk-vt8500.c void __iomem *reg; reg 589 drivers/clk/clk-vt8500.c writel(pll_val, pll->reg); reg 640 drivers/clk/clk-vt8500.c u32 pll_val = readl(pll->reg); reg 675 drivers/clk/clk-vt8500.c u32 reg; reg 686 drivers/clk/clk-vt8500.c rc = of_property_read_u32(node, "reg", ®); reg 694 drivers/clk/clk-vt8500.c pll_clk->reg = pmc_base + reg; reg 49 drivers/clk/clk-xgene.c void __iomem *reg; reg 63 drivers/clk/clk-xgene.c data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); reg 81 drivers/clk/clk-xgene.c pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); reg 125 drivers/clk/clk-xgene.c unsigned long flags, void __iomem *reg, u32 pll_offset, reg 144 drivers/clk/clk-xgene.c apmclk->reg = reg; reg 173 drivers/clk/clk-xgene.c void __iomem *reg; reg 176 drivers/clk/clk-xgene.c reg = of_iomap(np, 0); reg 177 drivers/clk/clk-xgene.c if (!reg) { reg 184 drivers/clk/clk-xgene.c 0, reg, 0, pll_type, &clk_lock, reg 223 drivers/clk/clk-xgene.c void __iomem *reg; reg 250 drivers/clk/clk-xgene.c val = readl(fd->reg); reg 321 drivers/clk/clk-xgene.c val = readl(fd->reg); reg 324 drivers/clk/clk-xgene.c writel(val, fd->reg); reg 343 drivers/clk/clk-xgene.c unsigned long flags, void __iomem *reg, u8 shift, reg 360 drivers/clk/clk-xgene.c fd->reg = reg; reg 35 drivers/clk/davinci/da8xx-cfgchip.c u32 reg; reg 46 drivers/clk/davinci/da8xx-cfgchip.c return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask); reg 53 drivers/clk/davinci/da8xx-cfgchip.c regmap_write_bits(clk->regmap, clk->reg, clk->mask, 0); reg 61 drivers/clk/davinci/da8xx-cfgchip.c regmap_read(clk->regmap, clk->reg, &val); reg 118 drivers/clk/davinci/da8xx-cfgchip.c gate->reg = info->cfgchip; reg 206 drivers/clk/davinci/da8xx-cfgchip.c u32 reg; reg 218 drivers/clk/davinci/da8xx-cfgchip.c return regmap_write_bits(clk->regmap, clk->reg, clk->mask, val); reg 226 drivers/clk/davinci/da8xx-cfgchip.c regmap_read(clk->regmap, clk->reg, &val); reg 258 drivers/clk/davinci/da8xx-cfgchip.c mux->reg = info->cfgchip; reg 237 drivers/clk/davinci/pll.c void __iomem *reg, reg 252 drivers/clk/davinci/pll.c gate->reg = reg; reg 261 drivers/clk/davinci/pll.c divider->reg = reg; reg 588 drivers/clk/davinci/pll.c mux->reg = base + OCSEL; reg 598 drivers/clk/davinci/pll.c gate->reg = base + CKEN; reg 607 drivers/clk/davinci/pll.c divider->reg = base + OSCDIV; reg 685 drivers/clk/davinci/pll.c u32 reg; reg 691 drivers/clk/davinci/pll.c reg = PLLDIV1 + 4 * (info->id - 1); reg 693 drivers/clk/davinci/pll.c reg = PLLDIV4 + 4 * (info->id - 4); reg 699 drivers/clk/davinci/pll.c gate->reg = base + reg; reg 708 drivers/clk/davinci/pll.c divider->reg = base + reg; reg 18 drivers/clk/hisilicon/clk-hisi-phase.c void __iomem *reg; reg 47 drivers/clk/hisilicon/clk-hisi-phase.c regval = readl(phase->reg); reg 78 drivers/clk/hisilicon/clk-hisi-phase.c val = readl(phase->reg); reg 81 drivers/clk/hisilicon/clk-hisi-phase.c writel(val, phase->reg); reg 110 drivers/clk/hisilicon/clk-hisi-phase.c phase->reg = base + clks->offset; reg 111 drivers/clk/hisilicon/clk.h const char *parent_name, unsigned long flags, void __iomem *reg, reg 34 drivers/clk/hisilicon/clkdivider-hi6220.c void __iomem *reg; reg 51 drivers/clk/hisilicon/clkdivider-hi6220.c val = readl_relaxed(dclk->reg) >> dclk->shift; reg 81 drivers/clk/hisilicon/clkdivider-hi6220.c data = readl_relaxed(dclk->reg); reg 86 drivers/clk/hisilicon/clkdivider-hi6220.c writel_relaxed(data, dclk->reg); reg 101 drivers/clk/hisilicon/clkdivider-hi6220.c const char *parent_name, unsigned long flags, void __iomem *reg, reg 138 drivers/clk/hisilicon/clkdivider-hi6220.c div->reg = reg; reg 36 drivers/clk/hisilicon/clkgate-separated.c u32 reg; reg 41 drivers/clk/hisilicon/clkgate-separated.c reg = BIT(sclk->bit_idx); reg 42 drivers/clk/hisilicon/clkgate-separated.c writel_relaxed(reg, sclk->enable); reg 53 drivers/clk/hisilicon/clkgate-separated.c u32 reg; reg 58 drivers/clk/hisilicon/clkgate-separated.c reg = BIT(sclk->bit_idx); reg 59 drivers/clk/hisilicon/clkgate-separated.c writel_relaxed(reg, sclk->enable + CLKGATE_SEPERATED_DISABLE); reg 68 drivers/clk/hisilicon/clkgate-separated.c u32 reg; reg 71 drivers/clk/hisilicon/clkgate-separated.c reg = readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); reg 72 drivers/clk/hisilicon/clkgate-separated.c reg &= BIT(sclk->bit_idx); reg 74 drivers/clk/hisilicon/clkgate-separated.c return reg ? 1 : 0; reg 86 drivers/clk/hisilicon/clkgate-separated.c void __iomem *reg, u8 bit_idx, reg 103 drivers/clk/hisilicon/clkgate-separated.c sclk->enable = reg + CLKGATE_SEPERATED_ENABLE; reg 48 drivers/clk/hisilicon/reset.c u32 offset, reg; reg 56 drivers/clk/hisilicon/reset.c reg = readl(rstc->membase + offset); reg 57 drivers/clk/hisilicon/reset.c writel(reg | BIT(bit), rstc->membase + offset); reg 69 drivers/clk/hisilicon/reset.c u32 offset, reg; reg 77 drivers/clk/hisilicon/reset.c reg = readl(rstc->membase + offset); reg 78 drivers/clk/hisilicon/reset.c writel(reg & ~BIT(bit), rstc->membase + offset); reg 15 drivers/clk/imx/clk-busy.c static int clk_busy_wait(void __iomem *reg, u8 shift) reg 19 drivers/clk/imx/clk-busy.c while (readl_relaxed(reg) & (1 << shift)) reg 29 drivers/clk/imx/clk-busy.c void __iomem *reg; reg 64 drivers/clk/imx/clk-busy.c ret = clk_busy_wait(busy->reg, busy->shift); reg 76 drivers/clk/imx/clk-busy.c void __iomem *reg, u8 shift, u8 width, reg 88 drivers/clk/imx/clk-busy.c busy->reg = busy_reg; reg 91 drivers/clk/imx/clk-busy.c busy->div.reg = reg; reg 119 drivers/clk/imx/clk-busy.c void __iomem *reg; reg 144 drivers/clk/imx/clk-busy.c ret = clk_busy_wait(busy->reg, busy->shift); reg 154 drivers/clk/imx/clk-busy.c struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift, reg 167 drivers/clk/imx/clk-busy.c busy->reg = busy_reg; reg 170 drivers/clk/imx/clk-busy.c busy->mux.reg = reg; reg 28 drivers/clk/imx/clk-composite-7ulp.c void __iomem *reg) reg 41 drivers/clk/imx/clk-composite-7ulp.c mux->reg = reg; reg 53 drivers/clk/imx/clk-composite-7ulp.c fd->reg = reg; reg 71 drivers/clk/imx/clk-composite-7ulp.c gate->reg = reg; reg 34 drivers/clk/imx/clk-composite-8m.c prediv_value = readl(divider->reg) >> divider->shift; reg 41 drivers/clk/imx/clk-composite-8m.c div_value = readl(divider->reg) >> PCG_DIV_SHIFT; reg 107 drivers/clk/imx/clk-composite-8m.c val = readl(divider->reg); reg 113 drivers/clk/imx/clk-composite-8m.c writel(val, divider->reg); reg 128 drivers/clk/imx/clk-composite-8m.c int num_parents, void __iomem *reg, reg 142 drivers/clk/imx/clk-composite-8m.c mux->reg = reg; reg 152 drivers/clk/imx/clk-composite-8m.c div->reg = reg; reg 163 drivers/clk/imx/clk-composite-8m.c gate->reg = reg; reg 32 drivers/clk/imx/clk-divider-gate.c val = readl(div->reg) >> div->shift; reg 54 drivers/clk/imx/clk-divider-gate.c val = readl(div->reg) >> div->shift; reg 90 drivers/clk/imx/clk-divider-gate.c val = readl(div->reg); reg 93 drivers/clk/imx/clk-divider-gate.c writel(val, div->reg); reg 117 drivers/clk/imx/clk-divider-gate.c val = readl(div->reg); reg 119 drivers/clk/imx/clk-divider-gate.c writel(val, div->reg); reg 136 drivers/clk/imx/clk-divider-gate.c val = readl(div->reg) >> div->shift; reg 139 drivers/clk/imx/clk-divider-gate.c writel(0, div->reg); reg 149 drivers/clk/imx/clk-divider-gate.c val = readl(div->reg) >> div->shift; reg 177 drivers/clk/imx/clk-divider-gate.c unsigned long flags, void __iomem *reg, reg 201 drivers/clk/imx/clk-divider-gate.c div_gate->divider.reg = reg; reg 209 drivers/clk/imx/clk-divider-gate.c val = readl(reg) >> shift; reg 71 drivers/clk/imx/clk-fixup-div.c val = readl(div->reg); reg 75 drivers/clk/imx/clk-fixup-div.c writel(val, div->reg); reg 89 drivers/clk/imx/clk-fixup-div.c void __iomem *reg, u8 shift, u8 width, reg 110 drivers/clk/imx/clk-fixup-div.c fixup_div->divider.reg = reg; reg 50 drivers/clk/imx/clk-fixup-mux.c val = readl(mux->reg); reg 54 drivers/clk/imx/clk-fixup-mux.c writel(val, mux->reg); reg 66 drivers/clk/imx/clk-fixup-mux.c struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg, reg 88 drivers/clk/imx/clk-fixup-mux.c fixup_mux->mux.reg = reg; reg 34 drivers/clk/imx/clk-gate-exclusive.c u32 val = readl(gate->reg); reg 59 drivers/clk/imx/clk-gate-exclusive.c void __iomem *reg, u8 shift, u32 exclusive_mask) reg 81 drivers/clk/imx/clk-gate-exclusive.c gate->reg = reg; reg 29 drivers/clk/imx/clk-gate2.c void __iomem *reg; reg 42 drivers/clk/imx/clk-gate2.c u32 reg; reg 50 drivers/clk/imx/clk-gate2.c reg = readl(gate->reg); reg 51 drivers/clk/imx/clk-gate2.c reg &= ~(3 << gate->bit_idx); reg 52 drivers/clk/imx/clk-gate2.c reg |= gate->cgr_val << gate->bit_idx; reg 53 drivers/clk/imx/clk-gate2.c writel(reg, gate->reg); reg 64 drivers/clk/imx/clk-gate2.c u32 reg; reg 76 drivers/clk/imx/clk-gate2.c reg = readl(gate->reg); reg 77 drivers/clk/imx/clk-gate2.c reg &= ~(3 << gate->bit_idx); reg 78 drivers/clk/imx/clk-gate2.c writel(reg, gate->reg); reg 84 drivers/clk/imx/clk-gate2.c static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx) reg 86 drivers/clk/imx/clk-gate2.c u32 val = readl(reg); reg 98 drivers/clk/imx/clk-gate2.c return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx); reg 105 drivers/clk/imx/clk-gate2.c u32 reg; reg 110 drivers/clk/imx/clk-gate2.c reg = readl(gate->reg); reg 111 drivers/clk/imx/clk-gate2.c reg &= ~(3 << gate->bit_idx); reg 112 drivers/clk/imx/clk-gate2.c writel(reg, gate->reg); reg 127 drivers/clk/imx/clk-gate2.c void __iomem *reg, u8 bit_idx, u8 cgr_val, reg 141 drivers/clk/imx/clk-gate2.c gate->reg = reg; reg 274 drivers/clk/imx/clk-imx6q.c unsigned int reg; reg 280 drivers/clk/imx/clk-imx6q.c reg = readl_relaxed(ccm_base + CCM_CCSR); reg 281 drivers/clk/imx/clk-imx6q.c reg |= CCSR_PLL3_SW_CLK_SEL; reg 282 drivers/clk/imx/clk-imx6q.c writel_relaxed(reg, ccm_base + CCM_CCSR); reg 287 drivers/clk/imx/clk-imx6q.c unsigned int reg; reg 290 drivers/clk/imx/clk-imx6q.c reg = readl_relaxed(ccm_base + CCM_CCSR); reg 291 drivers/clk/imx/clk-imx6q.c reg &= ~CCSR_PLL3_SW_CLK_SEL; reg 292 drivers/clk/imx/clk-imx6q.c writel_relaxed(reg, ccm_base + CCM_CCSR); reg 326 drivers/clk/imx/clk-imx6q.c unsigned int reg; reg 330 drivers/clk/imx/clk-imx6q.c reg = readl_relaxed(ccm_base + CCM_CS2CDR); reg 331 drivers/clk/imx/clk-imx6q.c sel[0][0] = (reg >> CS2CDR_LDB_DI0_CLK_SEL_SHIFT) & 7; reg 332 drivers/clk/imx/clk-imx6q.c sel[1][0] = (reg >> CS2CDR_LDB_DI1_CLK_SEL_SHIFT) & 7; reg 375 drivers/clk/imx/clk-imx6q.c reg = readl_relaxed(ccm_base + CCM_CS2CDR); reg 376 drivers/clk/imx/clk-imx6q.c reg &= ~((7 << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) | reg 378 drivers/clk/imx/clk-imx6q.c reg |= ((sel[0][i] << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) | reg 380 drivers/clk/imx/clk-imx6q.c writel_relaxed(reg, ccm_base + CCM_CS2CDR); reg 399 drivers/clk/imx/clk-imx6q.c unsigned int reg; reg 402 drivers/clk/imx/clk-imx6q.c reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_528); reg 406 drivers/clk/imx/clk-imx6q.c reg |= PFD0_CLKGATE | PFD1_CLKGATE; reg 408 drivers/clk/imx/clk-imx6q.c reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE; reg 409 drivers/clk/imx/clk-imx6q.c writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_528); reg 412 drivers/clk/imx/clk-imx6q.c reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_480); reg 413 drivers/clk/imx/clk-imx6q.c reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE | PFD3_CLKGATE; reg 414 drivers/clk/imx/clk-imx6q.c writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_480); reg 417 drivers/clk/imx/clk-imx6q.c reg = readl_relaxed(anatop_base + CCM_ANALOG_PLL_VIDEO); reg 418 drivers/clk/imx/clk-imx6q.c reg &= ~PLL_ENABLE; reg 419 drivers/clk/imx/clk-imx6q.c writel_relaxed(reg, anatop_base + CCM_ANALOG_PLL_VIDEO); reg 33 drivers/clk/imx/clk-lpcg-scu.c void __iomem *reg; reg 44 drivers/clk/imx/clk-lpcg-scu.c u32 reg, val; reg 48 drivers/clk/imx/clk-lpcg-scu.c reg = readl_relaxed(clk->reg); reg 49 drivers/clk/imx/clk-lpcg-scu.c reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); reg 55 drivers/clk/imx/clk-lpcg-scu.c reg |= val << clk->bit_idx; reg 56 drivers/clk/imx/clk-lpcg-scu.c writel(reg, clk->reg); reg 67 drivers/clk/imx/clk-lpcg-scu.c u32 reg; reg 71 drivers/clk/imx/clk-lpcg-scu.c reg = readl_relaxed(clk->reg); reg 72 drivers/clk/imx/clk-lpcg-scu.c reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); reg 73 drivers/clk/imx/clk-lpcg-scu.c writel(reg, clk->reg); reg 84 drivers/clk/imx/clk-lpcg-scu.c unsigned long flags, void __iomem *reg, reg 96 drivers/clk/imx/clk-lpcg-scu.c clk->reg = reg; reg 25 drivers/clk/imx/clk-pfd.c void __iomem *reg; reg 39 drivers/clk/imx/clk-pfd.c writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR); reg 48 drivers/clk/imx/clk-pfd.c writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); reg 56 drivers/clk/imx/clk-pfd.c u8 frac = (readl_relaxed(pfd->reg) >> (pfd->idx * 8)) & 0x3f; reg 99 drivers/clk/imx/clk-pfd.c writel_relaxed(0x3f << (pfd->idx * 8), pfd->reg + CLR); reg 100 drivers/clk/imx/clk-pfd.c writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET); reg 109 drivers/clk/imx/clk-pfd.c if (readl_relaxed(pfd->reg) & (1 << ((pfd->idx + 1) * 8 - 1))) reg 125 drivers/clk/imx/clk-pfd.c void __iomem *reg, u8 idx) reg 136 drivers/clk/imx/clk-pfd.c pfd->reg = reg; reg 29 drivers/clk/imx/clk-pfdv2.c void __iomem *reg; reg 47 drivers/clk/imx/clk-pfdv2.c return readl_poll_timeout(pfd->reg, val, val & (1 << pfd->vld_bit), reg 58 drivers/clk/imx/clk-pfdv2.c val = readl_relaxed(pfd->reg); reg 60 drivers/clk/imx/clk-pfdv2.c writel_relaxed(val, pfd->reg); reg 73 drivers/clk/imx/clk-pfdv2.c val = readl_relaxed(pfd->reg); reg 75 drivers/clk/imx/clk-pfdv2.c writel_relaxed(val, pfd->reg); reg 86 drivers/clk/imx/clk-pfdv2.c frac = (readl_relaxed(pfd->reg) >> pfd->frac_off) reg 127 drivers/clk/imx/clk-pfdv2.c if (readl_relaxed(pfd->reg) & (1 << pfd->gate_bit)) reg 151 drivers/clk/imx/clk-pfdv2.c val = readl_relaxed(pfd->reg); reg 154 drivers/clk/imx/clk-pfdv2.c writel_relaxed(val, pfd->reg); reg 170 drivers/clk/imx/clk-pfdv2.c void __iomem *reg, u8 idx) reg 183 drivers/clk/imx/clk-pfdv2.c pfd->reg = reg; reg 59 drivers/clk/imx/clk-pllv1.c u32 reg; reg 62 drivers/clk/imx/clk-pllv1.c reg = readl(pll->base); reg 74 drivers/clk/imx/clk-pllv1.c mfi = (reg >> 10) & 0xf; reg 75 drivers/clk/imx/clk-pllv1.c mfn = reg & 0x3ff; reg 76 drivers/clk/imx/clk-pllv1.c mfd = (reg >> 16) & 0x3ff; reg 77 drivers/clk/imx/clk-pllv1.c pd = (reg >> 26) & 0xf; reg 129 drivers/clk/imx/clk-pllv2.c u32 reg; reg 146 drivers/clk/imx/clk-pllv2.c reg = mfi << 4 | pdf; reg 148 drivers/clk/imx/clk-pllv2.c *dp_op = reg; reg 198 drivers/clk/imx/clk-pllv2.c u32 reg; reg 203 drivers/clk/imx/clk-pllv2.c reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; reg 204 drivers/clk/imx/clk-pllv2.c __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); reg 208 drivers/clk/imx/clk-pllv2.c reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); reg 209 drivers/clk/imx/clk-pllv2.c if (reg & MXC_PLL_DP_CTL_LRF) reg 226 drivers/clk/imx/clk-pllv2.c u32 reg; reg 230 drivers/clk/imx/clk-pllv2.c reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; reg 231 drivers/clk/imx/clk-pllv2.c __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); reg 30 drivers/clk/imx/clk-scu.h unsigned long flags, void __iomem *reg, reg 28 drivers/clk/imx/clk.c unsigned int reg; reg 30 drivers/clk/imx/clk.c reg = readl_relaxed(ccm_base + CCM_CCDR); reg 31 drivers/clk/imx/clk.c reg |= chn == 0 ? CCDR_MMDC_CH0_MASK : CCDR_MMDC_CH1_MASK; reg 32 drivers/clk/imx/clk.c writel_relaxed(reg, ccm_base + CCM_CCDR); reg 56 drivers/clk/imx/clk.h #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ reg 58 drivers/clk/imx/clk.h to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ reg 64 drivers/clk/imx/clk.h #define imx_clk_pfd(name, parent_name, reg, idx) \ reg 65 drivers/clk/imx/clk.h to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx)) reg 67 drivers/clk/imx/clk.h #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ reg 68 drivers/clk/imx/clk.h to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask)) reg 73 drivers/clk/imx/clk.h #define imx_clk_divider2(name, parent, reg, shift, width) \ reg 74 drivers/clk/imx/clk.h to_clk(imx_clk_hw_divider2(name, parent, reg, shift, width)) reg 76 drivers/clk/imx/clk.h #define imx_clk_gate_dis(name, parent, reg, shift) \ reg 77 drivers/clk/imx/clk.h to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift)) reg 79 drivers/clk/imx/clk.h #define imx_clk_gate2(name, parent, reg, shift) \ reg 80 drivers/clk/imx/clk.h to_clk(imx_clk_hw_gate2(name, parent, reg, shift)) reg 82 drivers/clk/imx/clk.h #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \ reg 83 drivers/clk/imx/clk.h to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags)) reg 85 drivers/clk/imx/clk.h #define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \ reg 86 drivers/clk/imx/clk.h to_clk(imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count)) reg 88 drivers/clk/imx/clk.h #define imx_clk_gate3(name, parent, reg, shift) \ reg 89 drivers/clk/imx/clk.h to_clk(imx_clk_hw_gate3(name, parent, reg, shift)) reg 91 drivers/clk/imx/clk.h #define imx_clk_gate4(name, parent, reg, shift) \ reg 92 drivers/clk/imx/clk.h to_clk(imx_clk_hw_gate4(name, parent, reg, shift)) reg 94 drivers/clk/imx/clk.h #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \ reg 95 drivers/clk/imx/clk.h to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents)) reg 154 drivers/clk/imx/clk.h void __iomem *reg, u8 bit_idx, u8 cgr_val, reg 168 drivers/clk/imx/clk.h void __iomem *reg, u8 shift, u32 exclusive_mask); reg 171 drivers/clk/imx/clk.h void __iomem *reg, u8 idx); reg 174 drivers/clk/imx/clk.h void __iomem *reg, u8 idx); reg 177 drivers/clk/imx/clk.h void __iomem *reg, u8 shift, u8 width, reg 180 drivers/clk/imx/clk.h struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift, reg 188 drivers/clk/imx/clk.h void __iomem *reg); reg 191 drivers/clk/imx/clk.h void __iomem *reg, u8 shift, u8 width, reg 194 drivers/clk/imx/clk.h struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg, reg 215 drivers/clk/imx/clk.h static inline struct clk_hw *imx_clk_hw_mux_ldb(const char *name, void __iomem *reg, reg 220 drivers/clk/imx/clk.h CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg, reg 232 drivers/clk/imx/clk.h void __iomem *reg, u8 shift, u8 width) reg 235 drivers/clk/imx/clk.h reg, shift, width, 0, &imx_ccm_lock); reg 240 drivers/clk/imx/clk.h void __iomem *reg, u8 shift, reg 244 drivers/clk/imx/clk.h reg, shift, width, 0, &imx_ccm_lock); reg 248 drivers/clk/imx/clk.h const char *parent, void __iomem *reg, u8 shift, u8 width, reg 252 drivers/clk/imx/clk.h reg, shift, width, 0, &imx_ccm_lock); reg 257 drivers/clk/imx/clk.h void __iomem *reg, u8 shift, reg 261 drivers/clk/imx/clk.h reg, shift, width, 0, &imx_ccm_lock); reg 265 drivers/clk/imx/clk.h void __iomem *reg, u8 shift, u8 width) reg 269 drivers/clk/imx/clk.h reg, shift, width, 0, &imx_ccm_lock); reg 273 drivers/clk/imx/clk.h const char *parent, void __iomem *reg, u8 shift, u8 width, reg 278 drivers/clk/imx/clk.h reg, shift, width, 0, &imx_ccm_lock); reg 282 drivers/clk/imx/clk.h void __iomem *reg, u8 shift) reg 284 drivers/clk/imx/clk.h return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, reg 289 drivers/clk/imx/clk.h void __iomem *reg, u8 shift, unsigned long flags) reg 291 drivers/clk/imx/clk.h return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, reg 296 drivers/clk/imx/clk.h void __iomem *reg, u8 shift) reg 298 drivers/clk/imx/clk.h return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, reg 303 drivers/clk/imx/clk.h void __iomem *reg, u8 shift) reg 305 drivers/clk/imx/clk.h return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, reg 310 drivers/clk/imx/clk.h void __iomem *reg, u8 shift, unsigned long flags) reg 312 drivers/clk/imx/clk.h return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, reg 317 drivers/clk/imx/clk.h void __iomem *reg, u8 shift) reg 319 drivers/clk/imx/clk.h return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, reg 324 drivers/clk/imx/clk.h void __iomem *reg, u8 shift, unsigned long flags) reg 326 drivers/clk/imx/clk.h return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, reg 331 drivers/clk/imx/clk.h const char *parent, void __iomem *reg, u8 shift, reg 334 drivers/clk/imx/clk.h return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, reg 339 drivers/clk/imx/clk.h const char *parent, void __iomem *reg, u8 shift, reg 343 drivers/clk/imx/clk.h CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, reg 348 drivers/clk/imx/clk.h const char *parent, void __iomem *reg, u8 shift, u8 cgr_val) reg 350 drivers/clk/imx/clk.h return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, reg 355 drivers/clk/imx/clk.h void __iomem *reg, u8 shift) reg 359 drivers/clk/imx/clk.h reg, shift, 0, &imx_ccm_lock); reg 363 drivers/clk/imx/clk.h const char *parent, void __iomem *reg, u8 shift, reg 368 drivers/clk/imx/clk.h reg, shift, 0, &imx_ccm_lock); reg 372 drivers/clk/imx/clk.h void __iomem *reg, u8 shift) reg 376 drivers/clk/imx/clk.h reg, shift, 0x3, 0, &imx_ccm_lock, NULL); reg 380 drivers/clk/imx/clk.h const char *parent, void __iomem *reg, u8 shift, reg 385 drivers/clk/imx/clk.h reg, shift, 0x3, 0, &imx_ccm_lock, NULL); reg 388 drivers/clk/imx/clk.h static inline struct clk_hw *imx_clk_hw_mux(const char *name, void __iomem *reg, reg 393 drivers/clk/imx/clk.h CLK_SET_RATE_NO_REPARENT, reg, shift, reg 397 drivers/clk/imx/clk.h static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, reg 403 drivers/clk/imx/clk.h reg, shift, width, 0, &imx_ccm_lock); reg 406 drivers/clk/imx/clk.h static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iomem *reg, reg 414 drivers/clk/imx/clk.h reg, shift, width, 0, &imx_ccm_lock); reg 418 drivers/clk/imx/clk.h void __iomem *reg, u8 shift, u8 width, reg 423 drivers/clk/imx/clk.h flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0, reg 428 drivers/clk/imx/clk.h void __iomem *reg, u8 shift, u8 width, reg 434 drivers/clk/imx/clk.h reg, shift, width, 0, &imx_ccm_lock); reg 438 drivers/clk/imx/clk.h void __iomem *reg, u8 shift, reg 446 drivers/clk/imx/clk.h reg, shift, width, 0, &imx_ccm_lock); reg 455 drivers/clk/imx/clk.h int num_parents, void __iomem *reg, reg 458 drivers/clk/imx/clk.h #define __imx8m_clk_composite(name, parent_names, reg, flags) \ reg 460 drivers/clk/imx/clk.h ARRAY_SIZE(parent_names), reg, \ reg 463 drivers/clk/imx/clk.h #define imx8m_clk_composite(name, parent_names, reg) \ reg 464 drivers/clk/imx/clk.h __imx8m_clk_composite(name, parent_names, reg, 0) reg 466 drivers/clk/imx/clk.h #define imx8m_clk_composite_critical(name, parent_names, reg) \ reg 467 drivers/clk/imx/clk.h __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL) reg 470 drivers/clk/imx/clk.h unsigned long flags, void __iomem *reg, u8 shift, u8 width, reg 38 drivers/clk/ingenic/cgu.c return !!(readl(cgu->base + info->reg) & BIT(info->bit)) reg 56 drivers/clk/ingenic/cgu.c u32 clkgr = readl(cgu->base + info->reg); reg 63 drivers/clk/ingenic/cgu.c writel(clkgr, cgu->base + info->reg); reg 87 drivers/clk/ingenic/cgu.c ctl = readl(cgu->base + pll_info->reg); reg 186 drivers/clk/ingenic/cgu.c ctl = readl(cgu->base + pll_info->reg); reg 197 drivers/clk/ingenic/cgu.c writel(ctl, cgu->base + pll_info->reg); reg 215 drivers/clk/ingenic/cgu.c ctl = readl(cgu->base + pll_info->reg); reg 220 drivers/clk/ingenic/cgu.c writel(ctl, cgu->base + pll_info->reg); reg 224 drivers/clk/ingenic/cgu.c ctl = readl(cgu->base + pll_info->reg); reg 248 drivers/clk/ingenic/cgu.c ctl = readl(cgu->base + pll_info->reg); reg 252 drivers/clk/ingenic/cgu.c writel(ctl, cgu->base + pll_info->reg); reg 266 drivers/clk/ingenic/cgu.c ctl = readl(cgu->base + pll_info->reg); reg 291 drivers/clk/ingenic/cgu.c u32 reg; reg 297 drivers/clk/ingenic/cgu.c reg = readl(cgu->base + clk_info->mux.reg); reg 298 drivers/clk/ingenic/cgu.c hw_idx = (reg >> clk_info->mux.shift) & reg 321 drivers/clk/ingenic/cgu.c u32 reg, mask; reg 351 drivers/clk/ingenic/cgu.c reg = readl(cgu->base + clk_info->mux.reg); reg 352 drivers/clk/ingenic/cgu.c reg &= ~mask; reg 353 drivers/clk/ingenic/cgu.c reg |= hw_idx << clk_info->mux.shift; reg 354 drivers/clk/ingenic/cgu.c writel(reg, cgu->base + clk_info->mux.reg); reg 375 drivers/clk/ingenic/cgu.c div_reg = readl(cgu->base + clk_info->div.reg); reg 466 drivers/clk/ingenic/cgu.c u32 reg, mask; reg 484 drivers/clk/ingenic/cgu.c reg = readl(cgu->base + clk_info->div.reg); reg 488 drivers/clk/ingenic/cgu.c reg &= ~(mask << clk_info->div.shift); reg 489 drivers/clk/ingenic/cgu.c reg |= hw_div << clk_info->div.shift; reg 493 drivers/clk/ingenic/cgu.c reg &= ~BIT(clk_info->div.stop_bit); reg 497 drivers/clk/ingenic/cgu.c reg |= BIT(clk_info->div.ce_bit); reg 500 drivers/clk/ingenic/cgu.c writel(reg, cgu->base + clk_info->div.reg); reg 505 drivers/clk/ingenic/cgu.c reg = readl(cgu->base + clk_info->div.reg); reg 506 drivers/clk/ingenic/cgu.c if (!(reg & BIT(clk_info->div.busy_bit))) reg 46 drivers/clk/ingenic/cgu.h unsigned reg; reg 65 drivers/clk/ingenic/cgu.h unsigned reg; reg 87 drivers/clk/ingenic/cgu.h unsigned reg; reg 113 drivers/clk/ingenic/cgu.h unsigned reg; reg 56 drivers/clk/ingenic/jz4725b-cgu.c .reg = CGU_REG_CPPCR, reg 71 drivers/clk/ingenic/jz4740-cgu.c .reg = CGU_REG_CPPCR, reg 104 drivers/clk/ingenic/jz4770-cgu.c .reg = CGU_REG_CPPCR0, reg 126 drivers/clk/ingenic/jz4770-cgu.c .reg = CGU_REG_CPPCR1, reg 223 drivers/clk/ingenic/jz4780-cgu.c .reg = CGU_REG_ ## name, \ reg 251 drivers/clk/keystone/pll.c void __iomem *reg; reg 257 drivers/clk/keystone/pll.c reg = of_iomap(node, 0); reg 258 drivers/clk/keystone/pll.c if (!reg) { reg 266 drivers/clk/keystone/pll.c iounmap(reg); reg 272 drivers/clk/keystone/pll.c iounmap(reg); reg 278 drivers/clk/keystone/pll.c iounmap(reg); reg 282 drivers/clk/keystone/pll.c clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift, reg 288 drivers/clk/keystone/pll.c iounmap(reg); reg 299 drivers/clk/keystone/pll.c void __iomem *reg; reg 306 drivers/clk/keystone/pll.c reg = of_iomap(node, 0); reg 307 drivers/clk/keystone/pll.c if (!reg) { reg 329 drivers/clk/keystone/pll.c ARRAY_SIZE(parents) , 0, reg, shift, mask, reg 73 drivers/clk/mediatek/clk-apmixed.c const char *parent_name, void __iomem *reg) reg 83 drivers/clk/mediatek/clk-apmixed.c tx->base_addr = reg; reg 24 drivers/clk/mediatek/clk-cpumux.c regmap_read(mux->regmap, mux->reg, &val); reg 40 drivers/clk/mediatek/clk-cpumux.c return regmap_update_bits(mux->regmap, mux->reg, mask, val); reg 66 drivers/clk/mediatek/clk-cpumux.c cpumux->reg = mux->mux_reg; reg 13 drivers/clk/mediatek/clk-cpumux.h u32 reg; reg 922 drivers/clk/mediatek/clk-mt2701.c .reg = _reg, \ reg 1172 drivers/clk/mediatek/clk-mt2712.c .reg = _reg, \ reg 1149 drivers/clk/mediatek/clk-mt6779.c .reg = _reg, \ reg 619 drivers/clk/mediatek/clk-mt6797.c .reg = _reg, \ reg 29 drivers/clk/mediatek/clk-mt7622.c .reg = _reg, \ reg 29 drivers/clk/mediatek/clk-mt7629.c .reg = _reg, \ reg 599 drivers/clk/mediatek/clk-mt8135.c .reg = _reg, \ reg 1030 drivers/clk/mediatek/clk-mt8173.c .reg = _reg, \ reg 1074 drivers/clk/mediatek/clk-mt8183.c .reg = _reg, \ reg 741 drivers/clk/mediatek/clk-mt8516.c .reg = _reg, \ reg 168 drivers/clk/mediatek/clk-mtk.c mux->reg = base + mc->mux_reg; reg 191 drivers/clk/mediatek/clk-mtk.c gate->reg = base + mc->gate_reg; reg 207 drivers/clk/mediatek/clk-mtk.c div->reg = base + mc->divider_reg; reg 216 drivers/clk/mediatek/clk-mtk.h uint32_t reg; reg 243 drivers/clk/mediatek/clk-mtk.h const char *parent_name, void __iomem *reg); reg 312 drivers/clk/mediatek/clk-pll.c pll->base_addr = base + data->reg; reg 26 drivers/clk/mediatek/reset.c unsigned int reg = data->regofs + ((id / 32) << 4); reg 28 drivers/clk/mediatek/reset.c return regmap_write(data->regmap, reg, 1); reg 35 drivers/clk/mediatek/reset.c unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4; reg 37 drivers/clk/mediatek/reset.c return regmap_write(data->regmap, reg, 1); reg 930 drivers/clk/meson/axg-audio.c unsigned int *reg, reg 935 drivers/clk/meson/axg-audio.c *reg = (id / (stride * BITS_PER_BYTE)) * stride; reg 936 drivers/clk/meson/axg-audio.c *reg += rst->offset; reg 179 drivers/clk/meson/axg.c { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, reg 180 drivers/clk/meson/axg.c { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, reg 181 drivers/clk/meson/axg.c { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, reg 182 drivers/clk/meson/axg.c { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, reg 183 drivers/clk/meson/axg.c { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, reg 251 drivers/clk/meson/axg.c { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 }, reg 252 drivers/clk/meson/axg.c { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be }, reg 253 drivers/clk/meson/axg.c { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 }, reg 254 drivers/clk/meson/axg.c { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d }, reg 255 drivers/clk/meson/axg.c { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 }, reg 702 drivers/clk/meson/axg.c { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa }, reg 703 drivers/clk/meson/axg.c { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be }, reg 704 drivers/clk/meson/axg.c { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e }, reg 705 drivers/clk/meson/axg.c { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d }, reg 706 drivers/clk/meson/axg.c { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 }, reg 707 drivers/clk/meson/axg.c { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 }, reg 708 drivers/clk/meson/axg.c { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 }, reg 1602 drivers/clk/meson/g12a.c { .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 }, reg 1603 drivers/clk/meson/g12a.c { .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 }, reg 1604 drivers/clk/meson/g12a.c { .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 }, reg 1605 drivers/clk/meson/g12a.c { .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 }, reg 1606 drivers/clk/meson/g12a.c { .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 }, reg 1607 drivers/clk/meson/g12a.c { .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000 }, reg 1742 drivers/clk/meson/g12a.c { .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 }, reg 1743 drivers/clk/meson/g12a.c { .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 }, reg 1744 drivers/clk/meson/g12a.c { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 }, reg 1745 drivers/clk/meson/g12a.c { .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 }, reg 1746 drivers/clk/meson/g12a.c { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 }, reg 1747 drivers/clk/meson/g12a.c { .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 }, reg 1822 drivers/clk/meson/g12a.c { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496 }, reg 1823 drivers/clk/meson/g12a.c { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496 }, reg 1824 drivers/clk/meson/g12a.c { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000 }, reg 1825 drivers/clk/meson/g12a.c { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100 }, reg 1826 drivers/clk/meson/g12a.c { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00 }, reg 1827 drivers/clk/meson/g12a.c { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0 }, reg 1828 drivers/clk/meson/g12a.c { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048 }, reg 1829 drivers/clk/meson/g12a.c { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 }, reg 1830 drivers/clk/meson/g12a.c { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 }, reg 1831 drivers/clk/meson/g12a.c { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496 }, reg 1832 drivers/clk/meson/g12a.c { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 }, reg 1833 drivers/clk/meson/g12a.c { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000 }, reg 2188 drivers/clk/meson/g12a.c { .reg = HHI_MPLL_CNTL2, .def = 0x40000033 }, reg 2242 drivers/clk/meson/g12a.c { .reg = HHI_MPLL_CNTL4, .def = 0x40000033 }, reg 2296 drivers/clk/meson/g12a.c { .reg = HHI_MPLL_CNTL6, .def = 0x40000033 }, reg 2350 drivers/clk/meson/g12a.c { .reg = HHI_MPLL_CNTL8, .def = 0x40000033 }, reg 4883 drivers/clk/meson/g12a.c { .reg = HHI_MPLL_CNTL0, .def = 0x00000543 }, reg 429 drivers/clk/meson/gxbb.c { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 }, reg 430 drivers/clk/meson/gxbb.c { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 }, reg 431 drivers/clk/meson/gxbb.c { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d }, reg 476 drivers/clk/meson/gxbb.c { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, reg 477 drivers/clk/meson/gxbb.c { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, reg 478 drivers/clk/meson/gxbb.c { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, reg 479 drivers/clk/meson/gxbb.c { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, reg 480 drivers/clk/meson/gxbb.c { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, reg 3492 drivers/clk/meson/meson8b.c u32 reg; reg 3496 drivers/clk/meson/meson8b.c .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 30 reg 3499 drivers/clk/meson/meson8b.c .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 29 reg 3502 drivers/clk/meson/meson8b.c .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 28 reg 3505 drivers/clk/meson/meson8b.c .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 27 reg 3508 drivers/clk/meson/meson8b.c .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 26 reg 3511 drivers/clk/meson/meson8b.c .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 25 reg 3514 drivers/clk/meson/meson8b.c .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 24 reg 3517 drivers/clk/meson/meson8b.c .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 18 reg 3520 drivers/clk/meson/meson8b.c .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 17 reg 3523 drivers/clk/meson/meson8b.c .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 16 reg 3526 drivers/clk/meson/meson8b.c .reg = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 30 reg 3529 drivers/clk/meson/meson8b.c .reg = HHI_VID_CLK_CNTL, .bit_idx = 15 reg 3532 drivers/clk/meson/meson8b.c .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 7 reg 3535 drivers/clk/meson/meson8b.c .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 3 reg 3538 drivers/clk/meson/meson8b.c .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 1 reg 3541 drivers/clk/meson/meson8b.c .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 0 reg 3561 drivers/clk/meson/meson8b.c regmap_update_bits(meson8b_clk_reset->regmap, reset->reg, reg 3564 drivers/clk/meson/meson8b.c regmap_update_bits(meson8b_clk_reset->regmap, reset->reg, reg 17 drivers/clk/meson/parm.h #define PARM_GET(width, shift, reg) \ reg 18 drivers/clk/meson/parm.h (((reg) & SETPMASK(width, shift)) >> (shift)) reg 19 drivers/clk/meson/parm.h #define PARM_SET(width, shift, reg, val) \ reg 20 drivers/clk/meson/parm.h (((reg) & CLRPMASK(width, shift)) | ((val) << (shift))) reg 37 drivers/clk/mmp/clk-gate.c tmp = readl(gate->reg); reg 40 drivers/clk/mmp/clk-gate.c writel(tmp, gate->reg); reg 63 drivers/clk/mmp/clk-gate.c tmp = readl(gate->reg); reg 66 drivers/clk/mmp/clk-gate.c writel(tmp, gate->reg); reg 81 drivers/clk/mmp/clk-gate.c tmp = readl(gate->reg); reg 97 drivers/clk/mmp/clk-gate.c void __iomem *reg, u32 mask, u32 val_enable, u32 val_disable, reg 116 drivers/clk/mmp/clk-gate.c gate->reg = reg; reg 293 drivers/clk/mmp/clk-of-mmp2.c cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset; reg 241 drivers/clk/mmp/clk-of-pxa168.c cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset; reg 198 drivers/clk/mmp/clk-of-pxa1928.c cells[base + i].reg = reg 250 drivers/clk/mmp/clk-of-pxa910.c cells[base + i].reg = reg 260 drivers/clk/mmp/clk-of-pxa910.c cells[base + i].reg = reg 112 drivers/clk/mmp/clk.h void __iomem *reg; reg 123 drivers/clk/mmp/clk.h void __iomem *reg, u32 mask, u32 val_enable, reg 46 drivers/clk/mmp/reset.c val = readl(cell->reg); reg 48 drivers/clk/mmp/reset.c writel(val, cell->reg); reg 68 drivers/clk/mmp/reset.c val = readl(cell->reg); reg 70 drivers/clk/mmp/reset.c writel(val, cell->reg); reg 11 drivers/clk/mmp/reset.h void __iomem *reg; reg 164 drivers/clk/mvebu/ap-cpu-clk.c int ret, reg, divider = parent_rate / rate; reg 174 drivers/clk/mvebu/ap-cpu-clk.c regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, ®); reg 175 drivers/clk/mvebu/ap-cpu-clk.c reg &= ~(clk->pll_regs->divider_mask); reg 176 drivers/clk/mvebu/ap-cpu-clk.c reg |= (divider << clk->pll_regs->divider_offset); reg 183 drivers/clk/mvebu/ap-cpu-clk.c reg &= ~(AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK); reg 184 drivers/clk/mvebu/ap-cpu-clk.c reg |= ((divider * clk->pll_regs->divider_ratio) << reg 187 drivers/clk/mvebu/ap-cpu-clk.c regmap_write(clk->pll_cr_base, cpu_clkdiv_reg, reg); reg 202 drivers/clk/mvebu/ap-cpu-clk.c clk->pll_regs->ratio_state_reg, reg, reg 203 drivers/clk/mvebu/ap-cpu-clk.c reg & stable_bit, STATUS_POLL_PERIOD_US, reg 137 drivers/clk/mvebu/ap806-system-controller.c u32 reg; reg 146 drivers/clk/mvebu/ap806-system-controller.c ret = regmap_read(regmap, AP806_SAR_REG, ®); reg 152 drivers/clk/mvebu/ap806-system-controller.c freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK; reg 60 drivers/clk/mvebu/armada-37xx-periph.c void __iomem *reg; reg 130 drivers/clk/mvebu/armada-37xx-periph.c .reg = (void *)CLK_DIS, \ reg 139 drivers/clk/mvebu/armada-37xx-periph.c .reg = (void *)TBG_SEL, \ reg 160 drivers/clk/mvebu/armada-37xx-periph.c .reg = (void *)_reg, \ reg 324 drivers/clk/mvebu/armada-37xx-periph.c static unsigned int get_div(void __iomem *reg, int shift) reg 328 drivers/clk/mvebu/armada-37xx-periph.c val = (readl(reg) >> shift) & 0x7; reg 351 drivers/clk/mvebu/armada-37xx-periph.c unsigned int *reg, reg 355 drivers/clk/mvebu/armada-37xx-periph.c *reg = ARMADA_37XX_NB_L0L1; reg 357 drivers/clk/mvebu/armada-37xx-periph.c *reg = ARMADA_37XX_NB_L2L3; reg 366 drivers/clk/mvebu/armada-37xx-periph.c unsigned int val, reg = ARMADA_37XX_NB_DYN_MOD; reg 371 drivers/clk/mvebu/armada-37xx-periph.c regmap_read(base, reg, &val); reg 378 drivers/clk/mvebu/armada-37xx-periph.c unsigned int reg = ARMADA_37XX_NB_CPU_LOAD; reg 387 drivers/clk/mvebu/armada-37xx-periph.c regmap_read(base, reg, &load_level); reg 394 drivers/clk/mvebu/armada-37xx-periph.c armada_3700_pm_dvfs_update_regs(load_level, ®, &offset); reg 396 drivers/clk/mvebu/armada-37xx-periph.c regmap_read(base, reg, &div); reg 403 drivers/clk/mvebu/armada-37xx-periph.c unsigned int reg = ARMADA_37XX_NB_CPU_LOAD; reg 412 drivers/clk/mvebu/armada-37xx-periph.c regmap_read(base, reg, &load_level); reg 419 drivers/clk/mvebu/armada-37xx-periph.c armada_3700_pm_dvfs_update_regs(load_level, ®, &offset); reg 421 drivers/clk/mvebu/armada-37xx-periph.c regmap_read(base, reg, &sel); reg 456 drivers/clk/mvebu/armada-37xx-periph.c unsigned int reg, mask, val, reg 459 drivers/clk/mvebu/armada-37xx-periph.c armada_3700_pm_dvfs_update_regs(load_level, ®, &offset); reg 463 drivers/clk/mvebu/armada-37xx-periph.c regmap_update_bits(base, reg, mask, val); reg 493 drivers/clk/mvebu/armada-37xx-periph.c unsigned int reg, val, offset = ARMADA_37XX_NB_TBG_DIV_OFF; reg 495 drivers/clk/mvebu/armada-37xx-periph.c armada_3700_pm_dvfs_update_regs(load_level, ®, &offset); reg 497 drivers/clk/mvebu/armada-37xx-periph.c regmap_read(base, reg, &val); reg 561 drivers/clk/mvebu/armada-37xx-periph.c unsigned int reg, mask, val, reg 564 drivers/clk/mvebu/armada-37xx-periph.c armada_3700_pm_dvfs_update_regs(load_level, ®, &offset); reg 566 drivers/clk/mvebu/armada-37xx-periph.c regmap_read(base, reg, &val); reg 576 drivers/clk/mvebu/armada-37xx-periph.c reg = ARMADA_37XX_NB_CPU_LOAD; reg 581 drivers/clk/mvebu/armada-37xx-periph.c regmap_update_bits(base, reg, mask, load_level); reg 608 drivers/clk/mvebu/armada-37xx-periph.c void __iomem *reg, spinlock_t *lock, reg 622 drivers/clk/mvebu/armada-37xx-periph.c mux->reg = reg + (u64)mux->reg; reg 632 drivers/clk/mvebu/armada-37xx-periph.c gate->reg = reg + (u64)gate->reg; reg 643 drivers/clk/mvebu/armada-37xx-periph.c rate->reg1 = reg + (u64)rate->reg1; reg 644 drivers/clk/mvebu/armada-37xx-periph.c rate->reg2 = reg + (u64)rate->reg2; reg 650 drivers/clk/mvebu/armada-37xx-periph.c rate->reg = reg + (u64)rate->reg; reg 664 drivers/clk/mvebu/armada-37xx-periph.c pmcpu_clk->reg_mux = reg + (u64)pmcpu_clk->reg_mux; reg 665 drivers/clk/mvebu/armada-37xx-periph.c pmcpu_clk->reg_div = reg + (u64)pmcpu_clk->reg_div; reg 689 drivers/clk/mvebu/armada-37xx-periph.c data->tbg_sel = readl(data->reg + TBG_SEL); reg 690 drivers/clk/mvebu/armada-37xx-periph.c data->div_sel0 = readl(data->reg + DIV_SEL0); reg 691 drivers/clk/mvebu/armada-37xx-periph.c data->div_sel1 = readl(data->reg + DIV_SEL1); reg 692 drivers/clk/mvebu/armada-37xx-periph.c data->div_sel2 = readl(data->reg + DIV_SEL2); reg 693 drivers/clk/mvebu/armada-37xx-periph.c data->clk_sel = readl(data->reg + CLK_SEL); reg 694 drivers/clk/mvebu/armada-37xx-periph.c data->clk_dis = readl(data->reg + CLK_DIS); reg 704 drivers/clk/mvebu/armada-37xx-periph.c writel(data->clk_dis, data->reg + CLK_DIS); reg 705 drivers/clk/mvebu/armada-37xx-periph.c writel(data->div_sel0, data->reg + DIV_SEL0); reg 706 drivers/clk/mvebu/armada-37xx-periph.c writel(data->div_sel1, data->reg + DIV_SEL1); reg 707 drivers/clk/mvebu/armada-37xx-periph.c writel(data->div_sel2, data->reg + DIV_SEL2); reg 708 drivers/clk/mvebu/armada-37xx-periph.c writel(data->tbg_sel, data->reg + TBG_SEL); reg 709 drivers/clk/mvebu/armada-37xx-periph.c writel(data->clk_sel, data->reg + CLK_SEL); reg 748 drivers/clk/mvebu/armada-37xx-periph.c driver_data->reg = devm_ioremap_resource(dev, res); reg 749 drivers/clk/mvebu/armada-37xx-periph.c if (IS_ERR(driver_data->reg)) reg 750 drivers/clk/mvebu/armada-37xx-periph.c return PTR_ERR(driver_data->reg); reg 756 drivers/clk/mvebu/armada-37xx-periph.c if (armada_3700_add_composite_clk(&data[i], driver_data->reg, reg 54 drivers/clk/mvebu/armada-37xx-tbg.c static unsigned int tbg_get_mult(void __iomem *reg, const struct tbg_def *ptbg) reg 58 drivers/clk/mvebu/armada-37xx-tbg.c val = readl(reg + TBG_CTRL0); reg 63 drivers/clk/mvebu/armada-37xx-tbg.c static unsigned int tbg_get_div(void __iomem *reg, const struct tbg_def *ptbg) reg 68 drivers/clk/mvebu/armada-37xx-tbg.c val = readl(reg + TBG_CTRL7); reg 73 drivers/clk/mvebu/armada-37xx-tbg.c val = readl(reg + ptbg->vcodiv_reg); reg 89 drivers/clk/mvebu/armada-37xx-tbg.c void __iomem *reg; reg 109 drivers/clk/mvebu/armada-37xx-tbg.c reg = devm_ioremap_resource(dev, res); reg 110 drivers/clk/mvebu/armada-37xx-tbg.c if (IS_ERR(reg)) reg 111 drivers/clk/mvebu/armada-37xx-tbg.c return PTR_ERR(reg); reg 118 drivers/clk/mvebu/armada-37xx-tbg.c mult = tbg_get_mult(reg, &tbg[i]); reg 119 drivers/clk/mvebu/armada-37xx-tbg.c div = tbg_get_div(reg, &tbg[i]); reg 27 drivers/clk/mvebu/armada-37xx-xtal.c u32 reg; reg 48 drivers/clk/mvebu/armada-37xx-xtal.c ret = regmap_read(regmap, NB_GPIO1_LATCH, ®); reg 54 drivers/clk/mvebu/armada-37xx-xtal.c if (reg & XTAL_MODE) reg 19 drivers/clk/mvebu/armada_ap_cp_helper.c const __be32 *reg; reg 26 drivers/clk/mvebu/armada_ap_cp_helper.c reg = of_get_property(np, "reg", NULL); reg 27 drivers/clk/mvebu/armada_ap_cp_helper.c addr = of_translate_address(np, reg); reg 56 drivers/clk/mvebu/clk-corediv.c void __iomem *reg; reg 86 drivers/clk/mvebu/clk-corediv.c return !!(readl(corediv->reg) & enable_mask); reg 95 drivers/clk/mvebu/clk-corediv.c u32 reg; reg 99 drivers/clk/mvebu/clk-corediv.c reg = readl(corediv->reg); reg 100 drivers/clk/mvebu/clk-corediv.c reg |= (BIT(desc->fieldbit) << soc_desc->enable_bit_offset); reg 101 drivers/clk/mvebu/clk-corediv.c writel(reg, corediv->reg); reg 114 drivers/clk/mvebu/clk-corediv.c u32 reg; reg 118 drivers/clk/mvebu/clk-corediv.c reg = readl(corediv->reg); reg 119 drivers/clk/mvebu/clk-corediv.c reg &= ~(BIT(desc->fieldbit) << soc_desc->enable_bit_offset); reg 120 drivers/clk/mvebu/clk-corediv.c writel(reg, corediv->reg); reg 131 drivers/clk/mvebu/clk-corediv.c u32 reg, div; reg 133 drivers/clk/mvebu/clk-corediv.c reg = readl(corediv->reg + soc_desc->ratio_offset); reg 134 drivers/clk/mvebu/clk-corediv.c div = (reg >> desc->offset) & desc->mask; reg 160 drivers/clk/mvebu/clk-corediv.c u32 reg, div; reg 167 drivers/clk/mvebu/clk-corediv.c reg = readl(corediv->reg + soc_desc->ratio_offset); reg 168 drivers/clk/mvebu/clk-corediv.c reg &= ~(desc->mask << desc->offset); reg 169 drivers/clk/mvebu/clk-corediv.c reg |= (div & desc->mask) << desc->offset; reg 170 drivers/clk/mvebu/clk-corediv.c writel(reg, corediv->reg + soc_desc->ratio_offset); reg 173 drivers/clk/mvebu/clk-corediv.c reg = readl(corediv->reg) | BIT(desc->fieldbit); reg 174 drivers/clk/mvebu/clk-corediv.c writel(reg, corediv->reg); reg 177 drivers/clk/mvebu/clk-corediv.c reg = readl(corediv->reg) | soc_desc->ratio_reload; reg 178 drivers/clk/mvebu/clk-corediv.c writel(reg, corediv->reg); reg 185 drivers/clk/mvebu/clk-corediv.c reg &= ~(CORE_CLK_DIV_RATIO_MASK | soc_desc->ratio_reload); reg 186 drivers/clk/mvebu/clk-corediv.c writel(reg, corediv->reg); reg 294 drivers/clk/mvebu/clk-corediv.c corediv[i].reg = base; reg 52 drivers/clk/mvebu/clk-cpu.c u32 reg, div; reg 54 drivers/clk/mvebu/clk-cpu.c reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); reg 55 drivers/clk/mvebu/clk-cpu.c div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK; reg 79 drivers/clk/mvebu/clk-cpu.c u32 reg, div; reg 83 drivers/clk/mvebu/clk-cpu.c reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET) reg 86 drivers/clk/mvebu/clk-cpu.c writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); reg 90 drivers/clk/mvebu/clk-cpu.c reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) reg 92 drivers/clk/mvebu/clk-cpu.c writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); reg 95 drivers/clk/mvebu/clk-cpu.c reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) reg 97 drivers/clk/mvebu/clk-cpu.c writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); reg 101 drivers/clk/mvebu/clk-cpu.c reg &= ~(reload_mask | 1 << 24); reg 102 drivers/clk/mvebu/clk-cpu.c writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); reg 111 drivers/clk/mvebu/clk-cpu.c u32 reg; reg 124 drivers/clk/mvebu/clk-cpu.c reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET); reg 125 drivers/clk/mvebu/clk-cpu.c fabric_div = (reg >> SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT) & reg 138 drivers/clk/mvebu/clk-cpu.c reg = readl(cpuclk->pmu_dfs); reg 139 drivers/clk/mvebu/clk-cpu.c reg &= ~(PMU_DFS_RATIO_MASK << PMU_DFS_RATIO_SHIFT); reg 140 drivers/clk/mvebu/clk-cpu.c reg |= (target_div << PMU_DFS_RATIO_SHIFT); reg 141 drivers/clk/mvebu/clk-cpu.c writel(reg, cpuclk->pmu_dfs); reg 143 drivers/clk/mvebu/clk-cpu.c reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); reg 144 drivers/clk/mvebu/clk-cpu.c reg |= (SYS_CTRL_CLK_DIVIDER_CTRL_RESET_ALL << reg 146 drivers/clk/mvebu/clk-cpu.c writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); reg 28 drivers/clk/mvebu/common.c #define SSCG_CONF_MODE(reg) (((reg) >> 16) & 0x3) reg 32 drivers/clk/mvebu/common.c #define SSCG_CONF_LOW(reg) (((reg) >> 8) & 0xFF) reg 33 drivers/clk/mvebu/common.c #define SSCG_CONF_HIGH(reg) ((reg) & 0xFF) reg 24 drivers/clk/mxs/clk-div.c void __iomem *reg; reg 59 drivers/clk/mxs/clk-div.c ret = mxs_clk_wait(div->reg, div->busy); reg 71 drivers/clk/mxs/clk-div.c void __iomem *reg, u8 shift, u8 width, u8 busy) reg 87 drivers/clk/mxs/clk-div.c div->reg = reg; reg 90 drivers/clk/mxs/clk-div.c div->divider.reg = reg; reg 25 drivers/clk/mxs/clk-frac.c void __iomem *reg; reg 40 drivers/clk/mxs/clk-frac.c div = readl_relaxed(frac->reg) >> frac->shift; reg 94 drivers/clk/mxs/clk-frac.c val = readl_relaxed(frac->reg); reg 97 drivers/clk/mxs/clk-frac.c writel_relaxed(val, frac->reg); reg 101 drivers/clk/mxs/clk-frac.c return mxs_clk_wait(frac->reg, frac->busy); reg 111 drivers/clk/mxs/clk-frac.c void __iomem *reg, u8 shift, u8 width, u8 busy) reg 127 drivers/clk/mxs/clk-frac.c frac->reg = reg; reg 25 drivers/clk/mxs/clk-ref.c void __iomem *reg; reg 35 drivers/clk/mxs/clk-ref.c writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + CLR); reg 44 drivers/clk/mxs/clk-ref.c writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET); reg 52 drivers/clk/mxs/clk-ref.c u8 frac = (readl_relaxed(ref->reg) >> (ref->idx * 8)) & 0x3f; reg 103 drivers/clk/mxs/clk-ref.c val = readl_relaxed(ref->reg); reg 106 drivers/clk/mxs/clk-ref.c writel_relaxed(val, ref->reg); reg 122 drivers/clk/mxs/clk-ref.c void __iomem *reg, u8 idx) reg 138 drivers/clk/mxs/clk-ref.c ref->reg = reg; reg 14 drivers/clk/mxs/clk.c int mxs_clk_wait(void __iomem *reg, u8 shift) reg 18 drivers/clk/mxs/clk.c while (readl_relaxed(reg) & (1 << shift)) reg 19 drivers/clk/mxs/clk.h int mxs_clk_wait(void __iomem *reg, u8 shift); reg 25 drivers/clk/mxs/clk.h void __iomem *reg, u8 idx); reg 28 drivers/clk/mxs/clk.h void __iomem *reg, u8 shift, u8 width, u8 busy); reg 31 drivers/clk/mxs/clk.h void __iomem *reg, u8 shift, u8 width, u8 busy); reg 39 drivers/clk/mxs/clk.h const char *parent_name, void __iomem *reg, u8 shift) reg 42 drivers/clk/mxs/clk.h reg, shift, CLK_GATE_SET_TO_DISABLE, reg 46 drivers/clk/mxs/clk.h static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg, reg 51 drivers/clk/mxs/clk.h reg, shift, width, 0, &mxs_lock); reg 146 drivers/clk/nxp/clk-lpc18xx-ccu.c val = readl(gate->reg); reg 159 drivers/clk/nxp/clk-lpc18xx-ccu.c writel(val, gate->reg); reg 164 drivers/clk/nxp/clk-lpc18xx-ccu.c writel(val, gate->reg); reg 218 drivers/clk/nxp/clk-lpc18xx-ccu.c div->reg = branch->offset + reg_base; reg 227 drivers/clk/nxp/clk-lpc18xx-ccu.c branch->gate.reg = branch->offset + reg_base; reg 255 drivers/clk/nxp/clk-lpc18xx-cgu.c void __iomem *reg; reg 356 drivers/clk/nxp/clk-lpc18xx-cgu.c ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL); reg 357 drivers/clk/nxp/clk-lpc18xx-cgu.c mdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV); reg 358 drivers/clk/nxp/clk-lpc18xx-cgu.c npdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV); reg 419 drivers/clk/nxp/clk-lpc18xx-cgu.c ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL); reg 423 drivers/clk/nxp/clk-lpc18xx-cgu.c writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL); reg 426 drivers/clk/nxp/clk-lpc18xx-cgu.c writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV); reg 427 drivers/clk/nxp/clk-lpc18xx-cgu.c writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV); reg 431 drivers/clk/nxp/clk-lpc18xx-cgu.c writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL); reg 434 drivers/clk/nxp/clk-lpc18xx-cgu.c stat = readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT); reg 437 drivers/clk/nxp/clk-lpc18xx-cgu.c writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL); reg 462 drivers/clk/nxp/clk-lpc18xx-cgu.c stat = readl(pll->reg + LPC18XX_CGU_PLL1_STAT); reg 463 drivers/clk/nxp/clk-lpc18xx-cgu.c ctrl = readl(pll->reg + LPC18XX_CGU_PLL1_CTRL); reg 537 drivers/clk/nxp/clk-lpc18xx-cgu.c void __iomem *reg = base + LPC18XX_CGU_IDIV_CTRL(n); reg 541 drivers/clk/nxp/clk-lpc18xx-cgu.c clk->div.reg = reg; reg 542 drivers/clk/nxp/clk-lpc18xx-cgu.c clk->mux.reg = reg; reg 543 drivers/clk/nxp/clk-lpc18xx-cgu.c clk->gate.reg = reg; reg 557 drivers/clk/nxp/clk-lpc18xx-cgu.c void __iomem *reg = reg_base + LPC18XX_CGU_BASE_CLK(n); reg 564 drivers/clk/nxp/clk-lpc18xx-cgu.c clk->mux.reg = reg; reg 565 drivers/clk/nxp/clk-lpc18xx-cgu.c clk->gate.reg = reg; reg 588 drivers/clk/nxp/clk-lpc18xx-cgu.c clk->pll.reg = base; reg 589 drivers/clk/nxp/clk-lpc18xx-cgu.c clk->mux.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET; reg 590 drivers/clk/nxp/clk-lpc18xx-cgu.c clk->gate.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET; reg 36 drivers/clk/nxp/clk-lpc18xx-creg.c struct regmap *reg; reg 53 drivers/clk/nxp/clk-lpc18xx-creg.c ret = regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0, reg 70 drivers/clk/nxp/clk-lpc18xx-creg.c regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0, reg 78 drivers/clk/nxp/clk-lpc18xx-creg.c u32 reg; reg 80 drivers/clk/nxp/clk-lpc18xx-creg.c regmap_read(creg->reg, LPC18XX_CREG_CREG0, ®); reg 82 drivers/clk/nxp/clk-lpc18xx-creg.c return !(reg & LPC18XX_CREG_CREG0_PD32KHZ) && reg 83 drivers/clk/nxp/clk-lpc18xx-creg.c !(reg & LPC18XX_CREG_CREG0_RESET32KHZ); reg 96 drivers/clk/nxp/clk-lpc18xx-creg.c return regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0, reg 104 drivers/clk/nxp/clk-lpc18xx-creg.c regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0, reg 111 drivers/clk/nxp/clk-lpc18xx-creg.c u32 reg; reg 113 drivers/clk/nxp/clk-lpc18xx-creg.c regmap_read(creg->reg, LPC18XX_CREG_CREG0, ®); reg 115 drivers/clk/nxp/clk-lpc18xx-creg.c return !!(reg & creg->en_mask); reg 152 drivers/clk/nxp/clk-lpc18xx-creg.c creg_clk->reg = syscon; reg 304 drivers/clk/nxp/clk-lpc32xx.c u32 reg; reg 324 drivers/clk/nxp/clk-lpc32xx.c u32 reg; reg 343 drivers/clk/nxp/clk-lpc32xx.c u32 reg; reg 352 drivers/clk/nxp/clk-lpc32xx.c u32 reg; reg 361 drivers/clk/nxp/clk-lpc32xx.c u32 reg; reg 393 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); reg 398 drivers/clk/nxp/clk-lpc32xx.c return regmap_update_bits(clk_regmap, clk->reg, reg 406 drivers/clk/nxp/clk-lpc32xx.c regmap_update_bits(clk_regmap, clk->reg, reg 415 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); reg 431 drivers/clk/nxp/clk-lpc32xx.c regmap_update_bits(clk_regmap, clk->reg, clk->enable, clk->enable); reg 434 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); reg 449 drivers/clk/nxp/clk-lpc32xx.c regmap_update_bits(clk_regmap, clk->reg, clk->enable, 0x0); reg 457 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); reg 480 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); reg 579 drivers/clk/nxp/clk-lpc32xx.c return regmap_update_bits(clk_regmap, clk->reg, 0x1FFFF, val); reg 718 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); reg 730 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); reg 741 drivers/clk/nxp/clk-lpc32xx.c return regmap_update_bits(clk_regmap, clk->reg, reg 754 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); reg 773 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); reg 890 drivers/clk/nxp/clk-lpc32xx.c return regmap_update_bits(clk_regmap, clk->reg, mask, val); reg 899 drivers/clk/nxp/clk-lpc32xx.c regmap_update_bits(clk_regmap, clk->reg, mask, val); reg 908 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, clk->reg, &val); reg 949 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, divider->reg, &val); reg 966 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, divider->reg, &bestdiv); reg 987 drivers/clk/nxp/clk-lpc32xx.c return regmap_update_bits(clk_regmap, divider->reg, reg 1004 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, mux->reg, &val); reg 1030 drivers/clk/nxp/clk-lpc32xx.c return regmap_update_bits(clk_regmap, mux->reg, reg 1101 drivers/clk/nxp/clk-lpc32xx.c .reg = LPC32XX_CLKPWR_ ## _reg, \ reg 1119 drivers/clk/nxp/clk-lpc32xx.c .reg = LPC32XX_CLKPWR_ ## _reg, \ reg 1138 drivers/clk/nxp/clk-lpc32xx.c .reg = LPC32XX_CLKPWR_ ## _reg, \ reg 1157 drivers/clk/nxp/clk-lpc32xx.c .reg = LPC32XX_CLKPWR_ ## _reg, \ reg 1174 drivers/clk/nxp/clk-lpc32xx.c .reg = LPC32XX_CLKPWR_ ## _reg, \ reg 1475 drivers/clk/nxp/clk-lpc32xx.c static void __init lpc32xx_clk_div_quirk(u32 reg, u32 div_mask, u32 gate) reg 1479 drivers/clk/nxp/clk-lpc32xx.c regmap_read(clk_regmap, reg, &val); reg 1486 drivers/clk/nxp/clk-lpc32xx.c regmap_update_bits(clk_regmap, reg, gate | div_mask, val); reg 78 drivers/clk/pistachio/clk-pll.c static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg) reg 80 drivers/clk/pistachio/clk-pll.c return readl(pll->base + reg); reg 83 drivers/clk/pistachio/clk-pll.c static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg) reg 85 drivers/clk/pistachio/clk-pll.c writel(val, pll->base + reg); reg 67 drivers/clk/pistachio/clk.c p->base + gate[i].reg, gate[i].shift, reg 84 drivers/clk/pistachio/clk.c p->base + mux[i].reg, mux[i].shift, reg 100 drivers/clk/pistachio/clk.c 0, p->base + div[i].reg, 0, reg 13 drivers/clk/pistachio/clk.h unsigned long reg; reg 22 drivers/clk/pistachio/clk.h .reg = _reg, \ reg 30 drivers/clk/pistachio/clk.h unsigned long reg; reg 42 drivers/clk/pistachio/clk.h .reg = _reg, \ reg 52 drivers/clk/pistachio/clk.h unsigned long reg; reg 62 drivers/clk/pistachio/clk.h .reg = _reg, \ reg 72 drivers/clk/pistachio/clk.h .reg = _reg, \ reg 126 drivers/clk/pxa/clk-pxa.h .gate = { .reg = (void __iomem *)_cken_reg, .bit_idx = _cken_bit }, \ reg 68 drivers/clk/qcom/clk-rcg.c u32 ns, reg; reg 73 drivers/clk/qcom/clk-rcg.c ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); reg 76 drivers/clk/qcom/clk-rcg.c bank = reg_to_bank(rcg, reg); reg 200 drivers/clk/qcom/clk-rcg.c u32 ns, md, reg; reg 213 drivers/clk/qcom/clk-rcg.c ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); reg 216 drivers/clk/qcom/clk-rcg.c bank = reg_to_bank(rcg, reg); reg 252 drivers/clk/qcom/clk-rcg.c reg = mn_to_reg(mn, f->m, f->n, reg); reg 254 drivers/clk/qcom/clk-rcg.c reg); reg 280 drivers/clk/qcom/clk-rcg.c ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); reg 283 drivers/clk/qcom/clk-rcg.c reg ^= BIT(rcg->mux_sel_bit); reg 284 drivers/clk/qcom/clk-rcg.c ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg); reg 294 drivers/clk/qcom/clk-rcg.c u32 ns, md, reg; reg 300 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); reg 301 drivers/clk/qcom/clk-rcg.c bank = reg_to_bank(rcg, reg); reg 370 drivers/clk/qcom/clk-rcg.c u32 m, n, pre_div, ns, md, mode, reg; reg 376 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); reg 377 drivers/clk/qcom/clk-rcg.c bank = reg_to_bank(rcg, reg); reg 389 drivers/clk/qcom/clk-rcg.c reg = ns; reg 390 drivers/clk/qcom/clk-rcg.c mode = reg_to_mnctr_mode(mn, reg); reg 448 drivers/clk/qcom/clk-rcg.c u32 reg; reg 452 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); reg 453 drivers/clk/qcom/clk-rcg.c bank = reg_to_bank(rcg, reg); reg 25 drivers/clk/qcom/clk-regmap-divider.c regmap_read(clkr->regmap, divider->reg, &val); reg 52 drivers/clk/qcom/clk-regmap-divider.c return regmap_update_bits(clkr->regmap, divider->reg, reg 64 drivers/clk/qcom/clk-regmap-divider.c regmap_read(clkr->regmap, divider->reg, &div); reg 13 drivers/clk/qcom/clk-regmap-divider.h u32 reg; reg 25 drivers/clk/qcom/clk-regmap-mux.c regmap_read(clkr->regmap, mux->reg, &val); reg 49 drivers/clk/qcom/clk-regmap-mux.c return regmap_update_bits(clkr->regmap, mux->reg, mask, val); reg 14 drivers/clk/qcom/clk-regmap-mux.h u32 reg; reg 89 drivers/clk/qcom/common.c qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count) reg 95 drivers/clk/qcom/common.c regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0); reg 102 drivers/clk/qcom/common.c regmap_update_bits(map, reg, mask, val); reg 105 drivers/clk/qcom/common.c regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA); reg 49 drivers/clk/qcom/common.h qcom_pll_set_fsm_mode(struct regmap *m, u32 reg, u8 bias_count, u8 lock_count); reg 305 drivers/clk/qcom/dispcc-sdm845.c .reg = 0x20e8, reg 360 drivers/clk/qcom/dispcc-sdm845.c .reg = 0x2104, reg 58 drivers/clk/qcom/gcc-ipq4019.c u32 reg; reg 1217 drivers/clk/qcom/gcc-ipq4019.c regmap_read(pll_div->cdiv.clkr.regmap, pll_vco->reg, &cdiv); reg 1235 drivers/clk/qcom/gcc-ipq4019.c .reg = 0x2e020, reg 1243 drivers/clk/qcom/gcc-ipq4019.c .reg = 0x2f020, reg 1287 drivers/clk/qcom/gcc-ipq4019.c pll->cdiv.reg, mask, reg 1312 drivers/clk/qcom/gcc-ipq4019.c regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv); reg 1356 drivers/clk/qcom/gcc-ipq4019.c .cdiv.reg = 0x2e020, reg 1392 drivers/clk/qcom/gcc-ipq4019.c regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv); reg 1495 drivers/clk/qcom/gcc-ipq4019.c .cdiv.reg = 0x2f020, reg 1513 drivers/clk/qcom/gcc-ipq4019.c .cdiv.reg = 0x2f020, reg 997 drivers/clk/qcom/gcc-ipq8074.c .reg = 0x7501c, reg 1040 drivers/clk/qcom/gcc-ipq8074.c .reg = 0x7601c, reg 1177 drivers/clk/qcom/gcc-ipq8074.c .reg = 0x3e048, reg 1235 drivers/clk/qcom/gcc-ipq8074.c .reg = 0x3f048, reg 1416 drivers/clk/qcom/gcc-ipq8074.c .reg = 0x68118, reg 1447 drivers/clk/qcom/gcc-ipq8074.c .reg = 0x68138, reg 1555 drivers/clk/qcom/gcc-ipq8074.c .reg = 0x68400, reg 1592 drivers/clk/qcom/gcc-ipq8074.c .reg = 0x68404, reg 1622 drivers/clk/qcom/gcc-ipq8074.c .reg = 0x68410, reg 1652 drivers/clk/qcom/gcc-ipq8074.c .reg = 0x68414, reg 1682 drivers/clk/qcom/gcc-ipq8074.c .reg = 0x68420, reg 1712 drivers/clk/qcom/gcc-ipq8074.c .reg = 0x68424, reg 1742 drivers/clk/qcom/gcc-ipq8074.c .reg = 0x68430, reg 1772 drivers/clk/qcom/gcc-ipq8074.c .reg = 0x68434, reg 1812 drivers/clk/qcom/gcc-ipq8074.c .reg = 0x68440, reg 1852 drivers/clk/qcom/gcc-ipq8074.c .reg = 0x68444, reg 1892 drivers/clk/qcom/gcc-ipq8074.c .reg = 0x68450, reg 1932 drivers/clk/qcom/gcc-ipq8074.c .reg = 0x68454, reg 53 drivers/clk/qcom/gdsc.c unsigned int reg; reg 58 drivers/clk/qcom/gdsc.c reg = sc->gdscr + CFG_GDSCR_OFFSET; reg 60 drivers/clk/qcom/gdsc.c reg = sc->gds_hw_ctrl; reg 62 drivers/clk/qcom/gdsc.c reg = sc->gdscr; reg 64 drivers/clk/qcom/gdsc.c ret = regmap_read(sc->regmap, reg, &val); reg 163 drivers/clk/qcom/lcc-ipq806x.c .reg = 0x48, reg 195 drivers/clk/qcom/lcc-ipq806x.c .reg = 0x48, reg 273 drivers/clk/qcom/lcc-ipq806x.c .reg = 0x54, reg 146 drivers/clk/qcom/lcc-mdm9615.c .reg = 0x48, reg 179 drivers/clk/qcom/lcc-mdm9615.c .reg = 0x48, reg 252 drivers/clk/qcom/lcc-mdm9615.c .reg = _ns, \ reg 285 drivers/clk/qcom/lcc-mdm9615.c .reg = _ns, \ reg 392 drivers/clk/qcom/lcc-mdm9615.c .reg = 0x54, reg 144 drivers/clk/qcom/lcc-msm8960.c .reg = 0x48, reg 177 drivers/clk/qcom/lcc-msm8960.c .reg = 0x48, reg 250 drivers/clk/qcom/lcc-msm8960.c .reg = _ns, \ reg 283 drivers/clk/qcom/lcc-msm8960.c .reg = _ns, \ reg 390 drivers/clk/qcom/lcc-msm8960.c .reg = 0x54, reg 33 drivers/clk/qcom/reset.c return regmap_update_bits(rst->regmap, map->reg, mask, mask); reg 47 drivers/clk/qcom/reset.c return regmap_update_bits(rst->regmap, map->reg, mask, 0); reg 12 drivers/clk/qcom/reset.h unsigned int reg; reg 38 drivers/clk/renesas/clk-div6.c void __iomem *reg; reg 53 drivers/clk/renesas/clk-div6.c val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP)) reg 55 drivers/clk/renesas/clk-div6.c writel(val, clock->reg); reg 65 drivers/clk/renesas/clk-div6.c val = readl(clock->reg); reg 75 drivers/clk/renesas/clk-div6.c writel(val, clock->reg); reg 82 drivers/clk/renesas/clk-div6.c return !(readl(clock->reg) & CPG_DIV6_CKSTP); reg 122 drivers/clk/renesas/clk-div6.c val = readl(clock->reg) & ~CPG_DIV6_DIV_MASK; reg 125 drivers/clk/renesas/clk-div6.c writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg); reg 139 drivers/clk/renesas/clk-div6.c hw_index = (readl(clock->reg) >> clock->src_shift) & reg 163 drivers/clk/renesas/clk-div6.c writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift), reg 164 drivers/clk/renesas/clk-div6.c clock->reg); reg 215 drivers/clk/renesas/clk-div6.c void __iomem *reg, reg 228 drivers/clk/renesas/clk-div6.c clock->reg = reg; reg 234 drivers/clk/renesas/clk-div6.c clock->div = (readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; reg 297 drivers/clk/renesas/clk-div6.c void __iomem *reg; reg 313 drivers/clk/renesas/clk-div6.c reg = of_iomap(np, 0); reg 314 drivers/clk/renesas/clk-div6.c if (reg == NULL) { reg 326 drivers/clk/renesas/clk-div6.c clk = cpg_div6_register(clk_name, num_parents, parent_names, reg, NULL); reg 339 drivers/clk/renesas/clk-div6.c if (reg) reg 340 drivers/clk/renesas/clk-div6.c iounmap(reg); reg 6 drivers/clk/renesas/clk-div6.h const char **parent_names, void __iomem *reg, reg 67 drivers/clk/renesas/clk-emev2.c u32 reg[2]; reg 70 drivers/clk/renesas/clk-emev2.c if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2))) reg 75 drivers/clk/renesas/clk-emev2.c smu_base + reg[0], reg[1], 8, 0, &lock); reg 85 drivers/clk/renesas/clk-emev2.c u32 reg[2]; reg 88 drivers/clk/renesas/clk-emev2.c if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2))) reg 93 drivers/clk/renesas/clk-emev2.c smu_base + reg[0], reg[1], 0, &lock); reg 64 drivers/clk/renesas/clk-mstp.c u32 __iomem *reg) reg 66 drivers/clk/renesas/clk-mstp.c return group->width_8bit ? readb(reg) : readl(reg); reg 70 drivers/clk/renesas/clk-mstp.c u32 __iomem *reg) reg 72 drivers/clk/renesas/clk-mstp.c group->width_8bit ? writeb(val, reg) : writel(val, reg); reg 21 drivers/clk/renesas/clk-r8a73a4.c void __iomem *reg; reg 38 drivers/clk/renesas/clk-r8a73a4.c unsigned int reg; reg 66 drivers/clk/renesas/clk-r8a73a4.c unsigned int shift, reg; reg 72 drivers/clk/renesas/clk-r8a73a4.c u32 ckscr = readl(cpg->reg + CPG_CKSCR); reg 96 drivers/clk/renesas/clk-r8a73a4.c u32 value = readl(cpg->reg + CPG_PLL0CR); reg 103 drivers/clk/renesas/clk-r8a73a4.c u32 value = readl(cpg->reg + CPG_PLL1CR); reg 126 drivers/clk/renesas/clk-r8a73a4.c value = readl(cpg->reg + cr); reg 162 drivers/clk/renesas/clk-r8a73a4.c mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f); reg 175 drivers/clk/renesas/clk-r8a73a4.c reg = c->reg; reg 184 drivers/clk/renesas/clk-r8a73a4.c cpg->reg + reg, shift, 4, 0, reg 216 drivers/clk/renesas/clk-r8a73a4.c cpg->reg = of_iomap(np, 0); reg 217 drivers/clk/renesas/clk-r8a73a4.c if (WARN_ON(cpg->reg == NULL)) reg 21 drivers/clk/renesas/clk-r8a7740.c void __iomem *reg; reg 34 drivers/clk/renesas/clk-r8a7740.c unsigned int reg; reg 68 drivers/clk/renesas/clk-r8a7740.c unsigned int shift, reg; reg 99 drivers/clk/renesas/clk-r8a7740.c u32 value = readl(cpg->reg + CPG_FRQCRC); reg 103 drivers/clk/renesas/clk-r8a7740.c u32 value = readl(cpg->reg + CPG_FRQCRA); reg 108 drivers/clk/renesas/clk-r8a7740.c u32 value = readl(cpg->reg + CPG_PLLC2CR); reg 112 drivers/clk/renesas/clk-r8a7740.c u32 value = readl(cpg->reg + CPG_USBCKCR); reg 126 drivers/clk/renesas/clk-r8a7740.c reg = c->reg; reg 140 drivers/clk/renesas/clk-r8a7740.c cpg->reg + reg, shift, 4, 0, reg 175 drivers/clk/renesas/clk-r8a7740.c cpg->reg = of_iomap(np, 0); reg 176 drivers/clk/renesas/clk-r8a7740.c if (WARN_ON(cpg->reg == NULL)) reg 17 drivers/clk/renesas/clk-r8a7778.c void __iomem *reg; reg 117 drivers/clk/renesas/clk-r8a7778.c cpg->reg = of_iomap(np, 0); reg 118 drivers/clk/renesas/clk-r8a7778.c if (WARN_ON(cpg->reg == NULL)) reg 27 drivers/clk/renesas/clk-r8a7779.c void __iomem *reg; reg 25 drivers/clk/renesas/clk-rcar-gen2.c void __iomem *reg; reg 50 drivers/clk/renesas/clk-rcar-gen2.c void __iomem *reg; reg 63 drivers/clk/renesas/clk-rcar-gen2.c val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT; reg 98 drivers/clk/renesas/clk-rcar-gen2.c val = readl(zclk->reg); reg 101 drivers/clk/renesas/clk-rcar-gen2.c writel(val, zclk->reg); reg 153 drivers/clk/renesas/clk-rcar-gen2.c zclk->reg = cpg->reg + CPG_FRQCRC; reg 154 drivers/clk/renesas/clk-rcar-gen2.c zclk->kick_reg = cpg->reg + CPG_FRQCRB; reg 185 drivers/clk/renesas/clk-rcar-gen2.c gate->reg = cpg->reg + CPG_RCANCKCR; reg 219 drivers/clk/renesas/clk-rcar-gen2.c div->reg = cpg->reg + CPG_ADSPCKCR; reg 230 drivers/clk/renesas/clk-rcar-gen2.c gate->reg = cpg->reg + CPG_ADSPCKCR; reg 332 drivers/clk/renesas/clk-rcar-gen2.c u32 value = readl(cpg->reg + CPG_PLL0CR); reg 376 drivers/clk/renesas/clk-rcar-gen2.c cpg->reg + CPG_SDCKCR, shift, reg 431 drivers/clk/renesas/clk-rcar-gen2.c cpg->reg = of_iomap(np, 0); reg 432 drivers/clk/renesas/clk-rcar-gen2.c if (WARN_ON(cpg->reg == NULL)) reg 20 drivers/clk/renesas/clk-rz.c void __iomem *reg; reg 68 drivers/clk/renesas/clk-rz.c if (!cpg->reg) reg 76 drivers/clk/renesas/clk-rz.c val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3; reg 78 drivers/clk/renesas/clk-rz.c val = readl(cpg->reg + CPG_FRQCR2) & 3; reg 104 drivers/clk/renesas/clk-rz.c cpg->reg = of_iomap(np, 0); reg 21 drivers/clk/renesas/clk-sh73a0.c void __iomem *reg; reg 43 drivers/clk/renesas/clk-sh73a0.c unsigned int reg; reg 79 drivers/clk/renesas/clk-sh73a0.c unsigned int shift, reg, width; reg 86 drivers/clk/renesas/clk-sh73a0.c u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3; reg 91 drivers/clk/renesas/clk-sh73a0.c void __iomem *enable_reg = cpg->reg; reg 111 drivers/clk/renesas/clk-sh73a0.c if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { reg 120 drivers/clk/renesas/clk-sh73a0.c void __iomem *dsi_reg = cpg->reg + reg 132 drivers/clk/renesas/clk-sh73a0.c reg = CPG_FRQCRB; reg 142 drivers/clk/renesas/clk-sh73a0.c reg = c->reg; reg 157 drivers/clk/renesas/clk-sh73a0.c cpg->reg + reg, shift, width, 0, reg 189 drivers/clk/renesas/clk-sh73a0.c cpg->reg = of_iomap(np, 0); reg 190 drivers/clk/renesas/clk-sh73a0.c if (WARN_ON(cpg->reg == NULL)) reg 194 drivers/clk/renesas/clk-sh73a0.c writel(0x108, cpg->reg + CPG_SD0CKCR); reg 195 drivers/clk/renesas/clk-sh73a0.c writel(0x108, cpg->reg + CPG_SD1CKCR); reg 196 drivers/clk/renesas/clk-sh73a0.c writel(0x108, cpg->reg + CPG_SD2CKCR); reg 43 drivers/clk/renesas/r9a06g032-clocks.c unsigned int div_min : 10, div_max : 10, reg: 10; reg 82 drivers/clk/renesas/r9a06g032-clocks.c .reg = _reg, .div_min = _min, .div_max = _max, \ reg 315 drivers/clk/renesas/r9a06g032-clocks.c void __iomem *reg; reg 323 drivers/clk/renesas/r9a06g032-clocks.c u32 __iomem *reg = clocks->reg + (4 * (one >> 5)); reg 324 drivers/clk/renesas/r9a06g032-clocks.c u32 val = readl(reg); reg 327 drivers/clk/renesas/r9a06g032-clocks.c writel(val, reg); reg 334 drivers/clk/renesas/r9a06g032-clocks.c u32 __iomem *reg = clocks->reg + (4 * (one >> 5)); reg 335 drivers/clk/renesas/r9a06g032-clocks.c u32 val = readl(reg); reg 546 drivers/clk/renesas/r9a06g032-clocks.c u16 reg; reg 560 drivers/clk/renesas/r9a06g032-clocks.c u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg); reg 561 drivers/clk/renesas/r9a06g032-clocks.c u32 div = readl(reg); reg 647 drivers/clk/renesas/r9a06g032-clocks.c u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg); reg 659 drivers/clk/renesas/r9a06g032-clocks.c writel(div | BIT(31), reg); reg 692 drivers/clk/renesas/r9a06g032-clocks.c div->reg = desc->reg; reg 921 drivers/clk/renesas/r9a06g032-clocks.c clocks->reg = of_iomap(np, 0); reg 922 drivers/clk/renesas/r9a06g032-clocks.c if (WARN_ON(!clocks->reg)) reg 47 drivers/clk/renesas/rcar-gen2-cpg.c void __iomem *reg; reg 60 drivers/clk/renesas/rcar-gen2-cpg.c val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT; reg 95 drivers/clk/renesas/rcar-gen2-cpg.c val = readl(zclk->reg); reg 98 drivers/clk/renesas/rcar-gen2-cpg.c writel(val, zclk->reg); reg 151 drivers/clk/renesas/rcar-gen2-cpg.c zclk->reg = base + CPG_FRQCRC; reg 183 drivers/clk/renesas/rcar-gen2-cpg.c gate->reg = base + CPG_RCANCKCR; reg 218 drivers/clk/renesas/rcar-gen2-cpg.c div->reg = base + CPG_ADSPCKCR; reg 229 drivers/clk/renesas/rcar-gen2-cpg.c gate->reg = base + CPG_ADSPCKCR; reg 36 drivers/clk/renesas/rcar-gen3-cpg.c static void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set) reg 42 drivers/clk/renesas/rcar-gen3-cpg.c val = readl(reg); reg 45 drivers/clk/renesas/rcar-gen3-cpg.c writel(val, reg); reg 51 drivers/clk/renesas/rcar-gen3-cpg.c void __iomem *reg; reg 63 drivers/clk/renesas/rcar-gen3-cpg.c csn->saved = readl(csn->reg); reg 67 drivers/clk/renesas/rcar-gen3-cpg.c writel(csn->saved, csn->reg); reg 95 drivers/clk/renesas/rcar-gen3-cpg.c void __iomem *reg; reg 110 drivers/clk/renesas/rcar-gen3-cpg.c val = readl(zclk->reg) & zclk->mask; reg 145 drivers/clk/renesas/rcar-gen3-cpg.c cpg_reg_modify(zclk->reg, zclk->mask, reg 181 drivers/clk/renesas/rcar-gen3-cpg.c void __iomem *reg, reg 199 drivers/clk/renesas/rcar-gen3-cpg.c zclk->reg = reg + CPG_FRQCRC; reg 200 drivers/clk/renesas/rcar-gen3-cpg.c zclk->kick_reg = reg + CPG_FRQCRB; reg 282 drivers/clk/renesas/rcar-gen3-cpg.c cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK, reg 293 drivers/clk/renesas/rcar-gen3-cpg.c cpg_reg_modify(clock->csn.reg, 0, CPG_SD_STP_MASK); reg 300 drivers/clk/renesas/rcar-gen3-cpg.c return !(readl(clock->csn.reg) & CPG_SD_STP_MASK); reg 357 drivers/clk/renesas/rcar-gen3-cpg.c cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK | CPG_SD_FC_MASK, reg 398 drivers/clk/renesas/rcar-gen3-cpg.c clock->csn.reg = base + offset; reg 408 drivers/clk/renesas/rcar-gen3-cpg.c val = readl(clock->csn.reg) & ~CPG_SD_FC_MASK; reg 410 drivers/clk/renesas/rcar-gen3-cpg.c writel(val, clock->csn.reg); reg 453 drivers/clk/renesas/rcar-gen3-cpg.c rpc->div.reg = base + CPG_RPCCKCR; reg 458 drivers/clk/renesas/rcar-gen3-cpg.c rpc->gate.reg = base + CPG_RPCCKCR; reg 463 drivers/clk/renesas/rcar-gen3-cpg.c rpc->csn.reg = base + CPG_RPCCKCR; reg 497 drivers/clk/renesas/rcar-gen3-cpg.c rpcd2->gate.reg = base + CPG_RPCCKCR; reg 621 drivers/clk/renesas/rcar-gen3-cpg.c csn->reg = base + CPG_RCKCR; reg 627 drivers/clk/renesas/rcar-gen3-cpg.c value = readl(csn->reg) & 0x3f; reg 634 drivers/clk/renesas/rcar-gen3-cpg.c writel(value, csn->reg); reg 168 drivers/clk/renesas/renesas-cpg-mssr.c unsigned int reg = clock->index / 32; reg 176 drivers/clk/renesas/renesas-cpg-mssr.c dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk, reg 181 drivers/clk/renesas/renesas-cpg-mssr.c value = readb(priv->base + STBCR(reg)); reg 186 drivers/clk/renesas/renesas-cpg-mssr.c writeb(value, priv->base + STBCR(reg)); reg 189 drivers/clk/renesas/renesas-cpg-mssr.c readb(priv->base + STBCR(reg)); reg 190 drivers/clk/renesas/renesas-cpg-mssr.c barrier_data(priv->base + STBCR(reg)); reg 192 drivers/clk/renesas/renesas-cpg-mssr.c value = readl(priv->base + SMSTPCR(reg)); reg 197 drivers/clk/renesas/renesas-cpg-mssr.c writel(value, priv->base + SMSTPCR(reg)); reg 206 drivers/clk/renesas/renesas-cpg-mssr.c if (!(readl(priv->base + MSTPSR(reg)) & bitmask)) reg 213 drivers/clk/renesas/renesas-cpg-mssr.c priv->base + SMSTPCR(reg), bit); reg 573 drivers/clk/renesas/renesas-cpg-mssr.c unsigned int reg = id / 32; reg 577 drivers/clk/renesas/renesas-cpg-mssr.c dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); reg 580 drivers/clk/renesas/renesas-cpg-mssr.c writel(bitmask, priv->base + SRCR(reg)); reg 586 drivers/clk/renesas/renesas-cpg-mssr.c writel(bitmask, priv->base + SRSTCLR(reg)); reg 594 drivers/clk/renesas/renesas-cpg-mssr.c unsigned int reg = id / 32; reg 598 drivers/clk/renesas/renesas-cpg-mssr.c dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); reg 600 drivers/clk/renesas/renesas-cpg-mssr.c writel(bitmask, priv->base + SRCR(reg)); reg 608 drivers/clk/renesas/renesas-cpg-mssr.c unsigned int reg = id / 32; reg 612 drivers/clk/renesas/renesas-cpg-mssr.c dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit); reg 614 drivers/clk/renesas/renesas-cpg-mssr.c writel(bitmask, priv->base + SRSTCLR(reg)); reg 622 drivers/clk/renesas/renesas-cpg-mssr.c unsigned int reg = id / 32; reg 626 drivers/clk/renesas/renesas-cpg-mssr.c return !!(readl(priv->base + SRCR(reg)) & bitmask); reg 794 drivers/clk/renesas/renesas-cpg-mssr.c unsigned int reg; reg 801 drivers/clk/renesas/renesas-cpg-mssr.c for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { reg 802 drivers/clk/renesas/renesas-cpg-mssr.c if (priv->smstpcr_saved[reg].mask) reg 803 drivers/clk/renesas/renesas-cpg-mssr.c priv->smstpcr_saved[reg].val = reg 804 drivers/clk/renesas/renesas-cpg-mssr.c readl(priv->base + SMSTPCR(reg)); reg 816 drivers/clk/renesas/renesas-cpg-mssr.c unsigned int reg, i; reg 827 drivers/clk/renesas/renesas-cpg-mssr.c for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) { reg 828 drivers/clk/renesas/renesas-cpg-mssr.c mask = priv->smstpcr_saved[reg].mask; reg 833 drivers/clk/renesas/renesas-cpg-mssr.c oldval = readb(priv->base + STBCR(reg)); reg 835 drivers/clk/renesas/renesas-cpg-mssr.c oldval = readl(priv->base + SMSTPCR(reg)); reg 837 drivers/clk/renesas/renesas-cpg-mssr.c newval |= priv->smstpcr_saved[reg].val & mask; reg 842 drivers/clk/renesas/renesas-cpg-mssr.c writeb(newval, priv->base + STBCR(reg)); reg 844 drivers/clk/renesas/renesas-cpg-mssr.c readb(priv->base + STBCR(reg)); reg 845 drivers/clk/renesas/renesas-cpg-mssr.c barrier_data(priv->base + STBCR(reg)); reg 848 drivers/clk/renesas/renesas-cpg-mssr.c writel(newval, priv->base + SMSTPCR(reg)); reg 851 drivers/clk/renesas/renesas-cpg-mssr.c mask &= ~priv->smstpcr_saved[reg].val; reg 856 drivers/clk/renesas/renesas-cpg-mssr.c oldval = readl(priv->base + MSTPSR(reg)); reg 864 drivers/clk/renesas/renesas-cpg-mssr.c priv->base + SMSTPCR(reg), oldval & mask); reg 111 drivers/clk/rockchip/clk-cpu.c if (!clksel->reg) reg 115 drivers/clk/rockchip/clk-cpu.c __func__, clksel->reg, clksel->val); reg 116 drivers/clk/rockchip/clk-cpu.c writel(clksel->val, cpuclk->reg_base + clksel->reg); reg 28 drivers/clk/rockchip/clk-half-divider.c val = readl(divider->reg) >> divider->shift; reg 128 drivers/clk/rockchip/clk-half-divider.c val = readl(divider->reg); reg 132 drivers/clk/rockchip/clk-half-divider.c writel(val, divider->reg); reg 182 drivers/clk/rockchip/clk-half-divider.c mux->reg = base + muxdiv_offset; reg 197 drivers/clk/rockchip/clk-half-divider.c gate->reg = base + gate_offset; reg 209 drivers/clk/rockchip/clk-half-divider.c div->reg = base + muxdiv_offset; reg 15 drivers/clk/rockchip/clk-inverter.c void __iomem *reg; reg 30 drivers/clk/rockchip/clk-inverter.c val = readl(inv_clock->reg) >> inv_clock->shift; reg 50 drivers/clk/rockchip/clk-inverter.c inv_clock->reg); reg 53 drivers/clk/rockchip/clk-inverter.c u32 reg; reg 57 drivers/clk/rockchip/clk-inverter.c reg = readl(inv_clock->reg); reg 58 drivers/clk/rockchip/clk-inverter.c reg &= ~BIT(inv_clock->shift); reg 59 drivers/clk/rockchip/clk-inverter.c reg |= val; reg 60 drivers/clk/rockchip/clk-inverter.c writel(reg, inv_clock->reg); reg 75 drivers/clk/rockchip/clk-inverter.c void __iomem *reg, int shift, int flags, reg 93 drivers/clk/rockchip/clk-inverter.c inv_clock->reg = reg; reg 16 drivers/clk/rockchip/clk-mmc-phase.c void __iomem *reg; reg 58 drivers/clk/rockchip/clk-mmc-phase.c raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); reg 139 drivers/clk/rockchip/clk-mmc-phase.c mmc_clock->reg); reg 143 drivers/clk/rockchip/clk-mmc-phase.c mmc_clock->reg, raw_value>>(mmc_clock->shift), reg 193 drivers/clk/rockchip/clk-mmc-phase.c void __iomem *reg, int shift) reg 211 drivers/clk/rockchip/clk-mmc-phase.c mmc_clock->reg = reg; reg 13 drivers/clk/rockchip/clk-muxgrf.c u32 reg; reg 27 drivers/clk/rockchip/clk-muxgrf.c regmap_read(mux->regmap, mux->reg, &val); reg 45 drivers/clk/rockchip/clk-muxgrf.c return regmap_write(mux->regmap, mux->reg, val | (mask << 16)); reg 47 drivers/clk/rockchip/clk-muxgrf.c return regmap_update_bits(mux->regmap, mux->reg, mask, val); reg 58 drivers/clk/rockchip/clk-muxgrf.c int flags, struct regmap *regmap, int reg, reg 82 drivers/clk/rockchip/clk-muxgrf.c muxgrf_clock->reg = reg; reg 862 drivers/clk/rockchip/clk-pll.c pll_mux->reg = ctx->reg_base + mode_offset; reg 80 drivers/clk/rockchip/clk-px30.c .reg = PX30_CLKSEL_CON(0), \ reg 85 drivers/clk/rockchip/clk-rk3036.c .reg = RK2928_CLKSEL_CON(1), \ reg 82 drivers/clk/rockchip/clk-rk3128.c .reg = RK2928_CLKSEL_CON(1), \ reg 111 drivers/clk/rockchip/clk-rk3188.c .reg = RK2928_CLKSEL_CON(0), \ reg 117 drivers/clk/rockchip/clk-rk3188.c .reg = RK2928_CLKSEL_CON(1), \ reg 162 drivers/clk/rockchip/clk-rk3188.c .reg = RK2928_CLKSEL_CON(1), \ reg 83 drivers/clk/rockchip/clk-rk3228.c .reg = RK2928_CLKSEL_CON(1), \ reg 132 drivers/clk/rockchip/clk-rk3288.c .reg = RK3288_CLKSEL_CON(0), \ reg 140 drivers/clk/rockchip/clk-rk3288.c .reg = RK3288_CLKSEL_CON(37), \ reg 76 drivers/clk/rockchip/clk-rk3308.c .reg = RK3308_CLKSEL_CON(0), \ reg 95 drivers/clk/rockchip/clk-rk3328.c .reg = RK3328_CLKSEL_CON(1), \ reg 185 drivers/clk/rockchip/clk-rk3368.c .reg = RK3368_CLKSEL_CON(0 + _offs), \ reg 191 drivers/clk/rockchip/clk-rk3368.c .reg = RK3368_CLKSEL_CON(1 + _offs), \ reg 320 drivers/clk/rockchip/clk-rk3399.c .reg = RK3399_CLKSEL_CON(0 + _offs), \ reg 326 drivers/clk/rockchip/clk-rk3399.c .reg = RK3399_CLKSEL_CON(1 + _offs), \ reg 74 drivers/clk/rockchip/clk-rv1108.c .reg = RV1108_CLKSEL_CON(1), \ reg 59 drivers/clk/rockchip/clk.c mux->reg = base + muxdiv_offset; reg 76 drivers/clk/rockchip/clk.c gate->reg = base + gate_offset; reg 91 drivers/clk/rockchip/clk.c div->reg = base + div_offset; reg 93 drivers/clk/rockchip/clk.c div->reg = base + muxdiv_offset; reg 239 drivers/clk/rockchip/clk.c gate->reg = base + gate_offset; reg 247 drivers/clk/rockchip/clk.c div->reg = base + muxdiv_offset; reg 279 drivers/clk/rockchip/clk.c frac_mux->reg = base + child->muxdiv_offset; reg 339 drivers/clk/rockchip/clk.c gate->reg = base + gate_offset; reg 626 drivers/clk/rockchip/clk.c unsigned int reg, reg 632 drivers/clk/rockchip/clk.c reg_restart = reg; reg 321 drivers/clk/rockchip/clk.h int reg; reg 359 drivers/clk/rockchip/clk.h void __iomem *reg, int shift); reg 379 drivers/clk/rockchip/clk.h void __iomem *reg, int shift, int flags, reg 384 drivers/clk/rockchip/clk.h int flags, struct regmap *grf, int reg, reg 851 drivers/clk/rockchip/clk.h unsigned int reg, void (*cb)(void)); reg 36 drivers/clk/rockchip/softrst.c u32 reg; reg 40 drivers/clk/rockchip/softrst.c reg = readl(softrst->reg_base + (bank * 4)); reg 41 drivers/clk/rockchip/softrst.c writel(reg | BIT(offset), softrst->reg_base + (bank * 4)); reg 62 drivers/clk/rockchip/softrst.c u32 reg; reg 66 drivers/clk/rockchip/softrst.c reg = readl(softrst->reg_base + (bank * 4)); reg 67 drivers/clk/rockchip/softrst.c writel(reg & ~BIT(offset), softrst->reg_base + (bank * 4)); reg 30 drivers/clk/samsung/clk-exynos-clkout.c void __iomem *reg; reg 39 drivers/clk/samsung/clk-exynos-clkout.c clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG); reg 46 drivers/clk/samsung/clk-exynos-clkout.c writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG); reg 87 drivers/clk/samsung/clk-exynos-clkout.c clkout->reg = of_iomap(node, 0); reg 88 drivers/clk/samsung/clk-exynos-clkout.c if (!clkout->reg) reg 91 drivers/clk/samsung/clk-exynos-clkout.c clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG; reg 96 drivers/clk/samsung/clk-exynos-clkout.c clkout->mux.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG; reg 121 drivers/clk/samsung/clk-exynos-clkout.c iounmap(clkout->reg); reg 336 drivers/clk/sirf/clk-atlas7.c static inline unsigned long clkc_readl(unsigned reg) reg 338 drivers/clk/sirf/clk-atlas7.c return readl(sirfsoc_clk_vbase + reg); reg 341 drivers/clk/sirf/clk-atlas7.c static inline void clkc_writel(u32 val, unsigned reg) reg 343 drivers/clk/sirf/clk-atlas7.c writel(val, sirfsoc_clk_vbase + reg); reg 489 drivers/clk/sirf/clk-atlas7.c int reg; reg 491 drivers/clk/sirf/clk-atlas7.c reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; reg 493 drivers/clk/sirf/clk-atlas7.c return !!(clkc_readl(reg) & BIT(0)); reg 498 drivers/clk/sirf/clk-atlas7.c u32 val, reg; reg 501 drivers/clk/sirf/clk-atlas7.c reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; reg 503 drivers/clk/sirf/clk-atlas7.c val = clkc_readl(reg) | BIT(0); reg 504 drivers/clk/sirf/clk-atlas7.c clkc_writel(val, reg); reg 510 drivers/clk/sirf/clk-atlas7.c u32 val, reg; reg 513 drivers/clk/sirf/clk-atlas7.c reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; reg 515 drivers/clk/sirf/clk-atlas7.c val = clkc_readl(reg) & ~BIT(0); reg 516 drivers/clk/sirf/clk-atlas7.c clkc_writel(val, reg); reg 1206 drivers/clk/sirf/clk-atlas7.c u32 reg; reg 1208 drivers/clk/sirf/clk-atlas7.c reg = clk->regofs + SIRFSOC_CLKC_ROOT_CLK_EN0_STAT - SIRFSOC_CLKC_ROOT_CLK_EN0_SET; reg 1210 drivers/clk/sirf/clk-atlas7.c return !!(clkc_readl(reg) & BIT(clk->bit)); reg 1215 drivers/clk/sirf/clk-atlas7.c u32 reg; reg 1219 drivers/clk/sirf/clk-atlas7.c reg = clk->regofs; reg 1222 drivers/clk/sirf/clk-atlas7.c clkc_writel(BIT(clk->bit), reg); reg 1234 drivers/clk/sirf/clk-atlas7.c u32 reg; reg 1239 drivers/clk/sirf/clk-atlas7.c reg = clk->regofs + SIRFSOC_CLKC_ROOT_CLK_EN0_CLR - SIRFSOC_CLKC_ROOT_CLK_EN0_SET; reg 1259 drivers/clk/sirf/clk-atlas7.c clkc_writel(BIT(clk->bit), reg); reg 59 drivers/clk/sirf/clk-common.c static inline unsigned long clkc_readl(unsigned reg) reg 61 drivers/clk/sirf/clk-common.c return readl(sirfsoc_clk_vbase + reg); reg 64 drivers/clk/sirf/clk-common.c static inline void clkc_writel(u32 val, unsigned reg) reg 66 drivers/clk/sirf/clk-common.c writel(val, sirfsoc_clk_vbase + reg); reg 130 drivers/clk/sirf/clk-common.c unsigned long fin, nf, nr, od, reg; reg 149 drivers/clk/sirf/clk-common.c reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19); reg 150 drivers/clk/sirf/clk-common.c clkc_writel(reg, clk->regofs); reg 152 drivers/clk/sirf/clk-common.c reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0; reg 153 drivers/clk/sirf/clk-common.c clkc_writel((nf >> 1) - 1, reg); reg 155 drivers/clk/sirf/clk-common.c reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0; reg 156 drivers/clk/sirf/clk-common.c while (!(clkc_readl(reg) & BIT(6))) reg 244 drivers/clk/sirf/clk-common.c u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); reg 245 drivers/clk/sirf/clk-common.c reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS); reg 246 drivers/clk/sirf/clk-common.c writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); reg 256 drivers/clk/sirf/clk-common.c u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); reg 257 drivers/clk/sirf/clk-common.c reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS); reg 258 drivers/clk/sirf/clk-common.c writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); reg 263 drivers/clk/sirf/clk-common.c u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); reg 264 drivers/clk/sirf/clk-common.c return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ; reg 380 drivers/clk/sirf/clk-common.c unsigned ratio, wait, hold, reg; reg 395 drivers/clk/sirf/clk-common.c reg = clkc_readl(clk->regofs); reg 396 drivers/clk/sirf/clk-common.c reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20)); reg 397 drivers/clk/sirf/clk-common.c reg |= (wait << 16) | (hold << 20) | BIT(25); reg 398 drivers/clk/sirf/clk-common.c clkc_writel(reg, clk->regofs); reg 637 drivers/clk/sirf/clk-common.c u32 reg; reg 642 drivers/clk/sirf/clk-common.c reg = clk->enable_bit / 32; reg 643 drivers/clk/sirf/clk-common.c reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); reg 645 drivers/clk/sirf/clk-common.c return !!(clkc_readl(reg) & BIT(bit)); reg 650 drivers/clk/sirf/clk-common.c u32 val, reg; reg 657 drivers/clk/sirf/clk-common.c reg = clk->enable_bit / 32; reg 658 drivers/clk/sirf/clk-common.c reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); reg 660 drivers/clk/sirf/clk-common.c val = clkc_readl(reg) | BIT(bit); reg 661 drivers/clk/sirf/clk-common.c clkc_writel(val, reg); reg 667 drivers/clk/sirf/clk-common.c u32 val, reg; reg 674 drivers/clk/sirf/clk-common.c reg = clk->enable_bit / 32; reg 675 drivers/clk/sirf/clk-common.c reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); reg 677 drivers/clk/sirf/clk-common.c val = clkc_readl(reg) & ~BIT(bit); reg 678 drivers/clk/sirf/clk-common.c clkc_writel(val, reg); reg 117 drivers/clk/socfpga/clk-gate-a10.c socfpga_clk->hw.reg = clk_mgr_a10_base_addr + clk_gate[0]; reg 85 drivers/clk/socfpga/clk-gate-s10.c socfpga_clk->hw.reg = regbase + gate_reg; reg 198 drivers/clk/socfpga/clk-gate.c socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0]; reg 33 drivers/clk/socfpga/clk-periph-a10.c div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1); reg 45 drivers/clk/socfpga/clk-periph-a10.c clk_src = readl(socfpgaclk->hw.reg); reg 63 drivers/clk/socfpga/clk-periph-a10.c u32 reg; reg 73 drivers/clk/socfpga/clk-periph-a10.c of_property_read_u32(node, "reg", ®); reg 79 drivers/clk/socfpga/clk-periph-a10.c periph_clk->hw.reg = clk_mgr_a10_base_addr + reg; reg 25 drivers/clk/socfpga/clk-periph-s10.c val = readl(socfpgaclk->hw.reg); reg 41 drivers/clk/socfpga/clk-periph-s10.c if (socfpgaclk->hw.reg) reg 42 drivers/clk/socfpga/clk-periph-s10.c div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1); reg 59 drivers/clk/socfpga/clk-periph-s10.c clk_src = readl(socfpgaclk->hw.reg); reg 79 drivers/clk/socfpga/clk-periph-s10.c void __iomem *reg, unsigned long offset) reg 89 drivers/clk/socfpga/clk-periph-s10.c periph_clk->hw.reg = reg + offset; reg 124 drivers/clk/socfpga/clk-periph-s10.c periph_clk->hw.reg = regbase + offset; reg 126 drivers/clk/socfpga/clk-periph-s10.c periph_clk->hw.reg = NULL; reg 31 drivers/clk/socfpga/clk-periph.c div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1); reg 53 drivers/clk/socfpga/clk-periph.c u32 reg; reg 63 drivers/clk/socfpga/clk-periph.c of_property_read_u32(node, "reg", ®); reg 69 drivers/clk/socfpga/clk-periph.c periph_clk->hw.reg = clk_mgr_base_addr + reg; reg 38 drivers/clk/socfpga/clk-pll-a10.c unsigned long divf, divq, reg; reg 42 drivers/clk/socfpga/clk-pll-a10.c reg = readl(socfpgaclk->hw.reg + 0x4); reg 43 drivers/clk/socfpga/clk-pll-a10.c divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; reg 44 drivers/clk/socfpga/clk-pll-a10.c divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; reg 55 drivers/clk/socfpga/clk-pll-a10.c pll_src = readl(socfpgaclk->hw.reg); reg 69 drivers/clk/socfpga/clk-pll-a10.c u32 reg; reg 79 drivers/clk/socfpga/clk-pll-a10.c of_property_read_u32(node, "reg", ®); reg 89 drivers/clk/socfpga/clk-pll-a10.c pll_clk->hw.reg = clk_mgr_a10_base_addr + reg; reg 36 drivers/clk/socfpga/clk-pll-s10.c unsigned long reg; reg 40 drivers/clk/socfpga/clk-pll-s10.c reg = readl(socfpgaclk->hw.reg); reg 41 drivers/clk/socfpga/clk-pll-s10.c refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT; reg 45 drivers/clk/socfpga/clk-pll-s10.c reg = readl(socfpgaclk->hw.reg + 0x4); reg 46 drivers/clk/socfpga/clk-pll-s10.c mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT; reg 58 drivers/clk/socfpga/clk-pll-s10.c div = ((readl(socfpgaclk->hw.reg) & reg 71 drivers/clk/socfpga/clk-pll-s10.c pll_src = readl(socfpgaclk->hw.reg); reg 81 drivers/clk/socfpga/clk-pll-s10.c pll_src = readl(socfpgaclk->hw.reg); reg 89 drivers/clk/socfpga/clk-pll-s10.c u32 reg; reg 92 drivers/clk/socfpga/clk-pll-s10.c reg = readl(socfpgaclk->hw.reg); reg 93 drivers/clk/socfpga/clk-pll-s10.c reg |= SOCFPGA_PLL_RESET_MASK; reg 94 drivers/clk/socfpga/clk-pll-s10.c writel(reg, socfpgaclk->hw.reg); reg 113 drivers/clk/socfpga/clk-pll-s10.c void __iomem *reg, unsigned long offset) reg 123 drivers/clk/socfpga/clk-pll-s10.c pll_clk->hw.reg = reg + offset; reg 42 drivers/clk/socfpga/clk-pll.c unsigned long divf, divq, reg; reg 46 drivers/clk/socfpga/clk-pll.c reg = readl(socfpgaclk->hw.reg); reg 51 drivers/clk/socfpga/clk-pll.c divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; reg 52 drivers/clk/socfpga/clk-pll.c divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; reg 63 drivers/clk/socfpga/clk-pll.c pll_src = readl(socfpgaclk->hw.reg); reg 76 drivers/clk/socfpga/clk-pll.c u32 reg; reg 85 drivers/clk/socfpga/clk-pll.c of_property_read_u32(node, "reg", ®); reg 95 drivers/clk/socfpga/clk-pll.c pll_clk->hw.reg = clk_mgr_base_addr + reg; reg 75 drivers/clk/spear/clk-aux-synth.c val = readl_relaxed(aux->reg); reg 113 drivers/clk/spear/clk-aux-synth.c val = readl_relaxed(aux->reg) & reg 123 drivers/clk/spear/clk-aux-synth.c writel_relaxed(val, aux->reg); reg 138 drivers/clk/spear/clk-aux-synth.c const char *parent_name, unsigned long flags, void __iomem *reg, reg 146 drivers/clk/spear/clk-aux-synth.c if (!aux_name || !parent_name || !reg || !rtbl || !rtbl_cnt) { reg 161 drivers/clk/spear/clk-aux-synth.c aux->reg = reg; reg 181 drivers/clk/spear/clk-aux-synth.c CLK_SET_RATE_PARENT, reg, reg 78 drivers/clk/spear/clk-frac-synth.c val = readl_relaxed(frac->reg); reg 109 drivers/clk/spear/clk-frac-synth.c val = readl_relaxed(frac->reg) & ~DIV_FACTOR_MASK; reg 111 drivers/clk/spear/clk-frac-synth.c writel_relaxed(val, frac->reg); reg 126 drivers/clk/spear/clk-frac-synth.c unsigned long flags, void __iomem *reg, reg 133 drivers/clk/spear/clk-frac-synth.c if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { reg 143 drivers/clk/spear/clk-frac-synth.c frac->reg = reg; reg 65 drivers/clk/spear/clk-gpt-synth.c val = readl_relaxed(gpt->reg); reg 94 drivers/clk/spear/clk-gpt-synth.c val = readl(gpt->reg) & ~GPT_MSCALE_MASK; reg 100 drivers/clk/spear/clk-gpt-synth.c writel_relaxed(val, gpt->reg); reg 115 drivers/clk/spear/clk-gpt-synth.c long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 reg 122 drivers/clk/spear/clk-gpt-synth.c if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { reg 132 drivers/clk/spear/clk-gpt-synth.c gpt->reg = reg; reg 51 drivers/clk/spear/clk.h void __iomem *reg; reg 65 drivers/clk/spear/clk.h void __iomem *reg; reg 79 drivers/clk/spear/clk.h void __iomem *reg; reg 114 drivers/clk/spear/clk.h const char *parent_name, unsigned long flags, void __iomem *reg, reg 118 drivers/clk/spear/clk.h unsigned long flags, void __iomem *reg, reg 121 drivers/clk/spear/clk.h long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 reg 19 drivers/clk/sprd/common.h u32 reg; reg 28 drivers/clk/sprd/composite.h .reg = _reg, \ reg 36 drivers/clk/sprd/div.c unsigned int reg; reg 38 drivers/clk/sprd/div.c regmap_read(common->regmap, common->reg, ®); reg 39 drivers/clk/sprd/div.c val = reg >> div->shift; reg 61 drivers/clk/sprd/div.c unsigned int reg; reg 66 drivers/clk/sprd/div.c regmap_read(common->regmap, common->reg, ®); reg 67 drivers/clk/sprd/div.c reg &= ~GENMASK(div->width + div->shift - 1, div->shift); reg 69 drivers/clk/sprd/div.c regmap_write(common->regmap, common->reg, reg 70 drivers/clk/sprd/div.c reg | (val << div->shift)); reg 44 drivers/clk/sprd/div.h .reg = _reg, \ reg 16 drivers/clk/sprd/gate.c unsigned int reg; reg 21 drivers/clk/sprd/gate.c regmap_read(common->regmap, common->reg, ®); reg 24 drivers/clk/sprd/gate.c reg |= sg->enable_mask; reg 26 drivers/clk/sprd/gate.c reg &= ~sg->enable_mask; reg 28 drivers/clk/sprd/gate.c regmap_write(common->regmap, common->reg, reg); reg 47 drivers/clk/sprd/gate.c regmap_write(common->regmap, common->reg + offset, reg 86 drivers/clk/sprd/gate.c unsigned int reg; reg 88 drivers/clk/sprd/gate.c regmap_read(common->regmap, common->reg, ®); reg 91 drivers/clk/sprd/gate.c reg ^= sg->enable_mask; reg 93 drivers/clk/sprd/gate.c reg &= sg->enable_mask; reg 95 drivers/clk/sprd/gate.c return reg ? 1 : 0; reg 29 drivers/clk/sprd/gate.h .reg = _reg, \ reg 17 drivers/clk/sprd/mux.c unsigned int reg; reg 22 drivers/clk/sprd/mux.c regmap_read(common->regmap, common->reg, ®); reg 23 drivers/clk/sprd/mux.c parent = reg >> mux->shift; reg 50 drivers/clk/sprd/mux.c unsigned int reg; reg 55 drivers/clk/sprd/mux.c regmap_read(common->regmap, common->reg, ®); reg 56 drivers/clk/sprd/mux.c reg &= ~GENMASK(mux->width + mux->shift - 1, mux->shift); reg 57 drivers/clk/sprd/mux.c regmap_write(common->regmap, common->reg, reg 58 drivers/clk/sprd/mux.c reg | (index << mux->shift)); reg 46 drivers/clk/sprd/mux.h .reg = _reg, \ reg 47 drivers/clk/sprd/pll.c regmap_read(common->regmap, common->reg + index * 4, &val); reg 57 drivers/clk/sprd/pll.c unsigned int offset, reg; reg 63 drivers/clk/sprd/pll.c offset = common->reg + index * 4; reg 64 drivers/clk/sprd/pll.c ret = regmap_read(common->regmap, offset, ®); reg 66 drivers/clk/sprd/pll.c regmap_write(common->regmap, offset, (reg & ~msk) | val); reg 78 drivers/clk/sprd/pll.h .reg = _reg, \ reg 157 drivers/clk/st/clk-flexgen.c u32 reg; reg 163 drivers/clk/st/clk-flexgen.c reg = readl(config->reg); reg 164 drivers/clk/st/clk-flexgen.c reg &= ~BIT(config->bit_idx); reg 165 drivers/clk/st/clk-flexgen.c writel(reg, config->reg); reg 200 drivers/clk/st/clk-flexgen.c void __iomem *reg, spinlock_t *lock, u32 idx, reg 218 drivers/clk/st/clk-flexgen.c xbar_reg = reg + 0x18 + (idx & ~0x3); reg 220 drivers/clk/st/clk-flexgen.c fdiv_reg = reg + 0x164 + idx * 4; reg 225 drivers/clk/st/clk-flexgen.c fgxbar->mux.reg = xbar_reg; reg 232 drivers/clk/st/clk-flexgen.c fgxbar->pgate.reg = xbar_reg; reg 237 drivers/clk/st/clk-flexgen.c fgxbar->pdiv.reg = reg + 0x58 + idx * 4; reg 242 drivers/clk/st/clk-flexgen.c fgxbar->fgate.reg = fdiv_reg; reg 247 drivers/clk/st/clk-flexgen.c fgxbar->fdiv.reg = fdiv_reg; reg 252 drivers/clk/st/clk-flexgen.c fgxbar->sync.reg = fdiv_reg; reg 313 drivers/clk/st/clk-flexgen.c void __iomem *reg; reg 328 drivers/clk/st/clk-flexgen.c reg = of_iomap(pnode, 0); reg 330 drivers/clk/st/clk-flexgen.c if (!reg) reg 335 drivers/clk/st/clk-flexgen.c iounmap(reg); reg 387 drivers/clk/st/clk-flexgen.c reg, rlock, i, flex_flags, clk_mode); reg 401 drivers/clk/st/clk-flexgen.c iounmap(reg); reg 383 drivers/clk/st/clkgen-fsyn.c struct clkgen_quadfs_data *quadfs, void __iomem *reg, reg 407 drivers/clk/st/clkgen-fsyn.c pll->regs_base = reg; reg 822 drivers/clk/st/clkgen-fsyn.c struct clkgen_quadfs_data *quadfs, void __iomem *reg, u32 chan, reg 846 drivers/clk/st/clkgen-fsyn.c fs->regs_base = reg; reg 861 drivers/clk/st/clkgen-fsyn.c struct clkgen_quadfs_data *quadfs, void __iomem *reg, reg 899 drivers/clk/st/clkgen-fsyn.c quadfs, reg, fschan, reg 923 drivers/clk/st/clkgen-fsyn.c void __iomem *reg; reg 926 drivers/clk/st/clkgen-fsyn.c reg = of_iomap(np, 0); reg 927 drivers/clk/st/clkgen-fsyn.c if (!reg) reg 945 drivers/clk/st/clkgen-fsyn.c reg, lock); reg 954 drivers/clk/st/clkgen-fsyn.c st_of_create_quadfs_fsynths(np, pll_name, data, reg, lock); reg 56 drivers/clk/st/clkgen-mux.c void __iomem *reg; reg 60 drivers/clk/st/clkgen-mux.c reg = of_iomap(np, 0); reg 61 drivers/clk/st/clkgen-mux.c if (!reg) { reg 75 drivers/clk/st/clkgen-mux.c reg + data->offset, reg 93 drivers/clk/st/clkgen-mux.c iounmap(reg); reg 187 drivers/clk/st/clkgen-pll.c u32 reg; reg 194 drivers/clk/st/clkgen-pll.c ret = readl_relaxed_poll_timeout(base + field->offset, reg, reg 195 drivers/clk/st/clkgen-pll.c !!((reg >> field->shift) & field->mask), 0, 10000); reg 584 drivers/clk/st/clkgen-pll.c void __iomem *reg, unsigned long pll_flags, reg 603 drivers/clk/st/clkgen-pll.c pll->regs_base = reg; reg 625 drivers/clk/st/clkgen-pll.c void __iomem *reg = NULL; reg 631 drivers/clk/st/clkgen-pll.c reg = of_iomap(pnode, 0); reg 634 drivers/clk/st/clkgen-pll.c return reg; reg 638 drivers/clk/st/clkgen-pll.c void __iomem *reg, reg 656 drivers/clk/st/clkgen-pll.c gate->reg = reg + pll_data->odf_gate[odf].offset; reg 667 drivers/clk/st/clkgen-pll.c div->reg = reg + pll_data->odf[odf].offset; reg 35 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .reg = 0x000, reg 69 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .reg = 0x008, reg 85 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .reg = 0x010, reg 103 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .reg = 0x018, reg 116 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .reg = 0x018, reg 129 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .reg = 0x020, reg 143 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .reg = 0x020, reg 155 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .reg = 0x028, reg 173 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .reg = 0x028, reg 187 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .reg = 0x030, reg 204 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .reg = 0x040, reg 229 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .reg = 0x054, reg 243 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .reg = 0x054, reg 264 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .reg = 0x054, reg 611 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .reg = 0x0c4, reg 832 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .reg = 0x1f0, reg 851 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .reg = 0x1f4, reg 1431 drivers/clk/sunxi-ng/ccu-sun4i-a10.c void __iomem *reg; reg 1434 drivers/clk/sunxi-ng/ccu-sun4i-a10.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 1435 drivers/clk/sunxi-ng/ccu-sun4i-a10.c if (IS_ERR(reg)) { reg 1441 drivers/clk/sunxi-ng/ccu-sun4i-a10.c val = readl(reg + SUN4I_PLL_AUDIO_REG); reg 1452 drivers/clk/sunxi-ng/ccu-sun4i-a10.c writel(val | (1 << 26), reg + SUN4I_PLL_AUDIO_REG); reg 1463 drivers/clk/sunxi-ng/ccu-sun4i-a10.c val = readl(reg + SUN4I_AHB_REG); reg 1465 drivers/clk/sunxi-ng/ccu-sun4i-a10.c writel(val | (2 << 6), reg + SUN4I_AHB_REG); reg 1467 drivers/clk/sunxi-ng/ccu-sun4i-a10.c sunxi_ccu_probe(node, reg, desc); reg 34 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .reg = 0x000, reg 113 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .reg = 0x028, reg 127 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .reg = 0x02c, reg 180 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .reg = 0x040, reg 242 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .reg = 0x054, reg 283 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .reg = 0x05c, reg 399 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .reg = 0x074, reg 543 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .reg = 0x11c, reg 941 drivers/clk/sunxi-ng/ccu-sun50i-a64.c void __iomem *reg; reg 946 drivers/clk/sunxi-ng/ccu-sun50i-a64.c reg = devm_ioremap_resource(&pdev->dev, res); reg 947 drivers/clk/sunxi-ng/ccu-sun50i-a64.c if (IS_ERR(reg)) reg 948 drivers/clk/sunxi-ng/ccu-sun50i-a64.c return PTR_ERR(reg); reg 951 drivers/clk/sunxi-ng/ccu-sun50i-a64.c val = readl(reg + SUN50I_A64_PLL_AUDIO_REG); reg 953 drivers/clk/sunxi-ng/ccu-sun50i-a64.c writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG); reg 955 drivers/clk/sunxi-ng/ccu-sun50i-a64.c writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); reg 957 drivers/clk/sunxi-ng/ccu-sun50i-a64.c ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc); reg 43 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c .reg = 0x000, reg 58 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c .reg = 0x00c, reg 78 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c .reg = 0x010, reg 191 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c void __iomem *reg; reg 193 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 194 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c if (IS_ERR(reg)) { reg 199 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c sunxi_ccu_probe(node, reg, desc); reg 41 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0x000, reg 57 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0x010, reg 73 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0x020, reg 90 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0x028, reg 106 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0x030, reg 127 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0x040, reg 145 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0x048, reg 161 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0x058, reg 176 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0x060, reg 191 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0x070, reg 212 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0x078, reg 369 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0x800, reg 504 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0xa0c, reg 517 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0xa10, reg 530 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0xa14, reg 543 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0xa18, reg 561 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0xa20, reg 576 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0xa40, reg 591 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0xa60, reg 675 drivers/clk/sunxi-ng/ccu-sun50i-h6.c .reg = 0xb10, reg 1178 drivers/clk/sunxi-ng/ccu-sun50i-h6.c void __iomem *reg; reg 1183 drivers/clk/sunxi-ng/ccu-sun50i-h6.c reg = devm_ioremap_resource(&pdev->dev, res); reg 1184 drivers/clk/sunxi-ng/ccu-sun50i-h6.c if (IS_ERR(reg)) reg 1185 drivers/clk/sunxi-ng/ccu-sun50i-h6.c return PTR_ERR(reg); reg 1189 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val = readl(reg + pll_regs[i]); reg 1191 drivers/clk/sunxi-ng/ccu-sun50i-h6.c writel(val, reg + pll_regs[i]); reg 1200 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val = readl(reg + pll_video_regs[i]); reg 1202 drivers/clk/sunxi-ng/ccu-sun50i-h6.c writel(val, reg + pll_video_regs[i]); reg 1212 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val = readl(reg + usb2_clk_regs[i]); reg 1214 drivers/clk/sunxi-ng/ccu-sun50i-h6.c writel (val, reg + usb2_clk_regs[i]); reg 1221 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val = readl(reg + SUN50I_H6_PLL_AUDIO_REG); reg 1223 drivers/clk/sunxi-ng/ccu-sun50i-h6.c writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG); reg 1230 drivers/clk/sunxi-ng/ccu-sun50i-h6.c val = readl(reg + SUN50I_H6_HDMI_CEC_CLK_REG); reg 1232 drivers/clk/sunxi-ng/ccu-sun50i-h6.c writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG); reg 1234 drivers/clk/sunxi-ng/ccu-sun50i-h6.c return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_h6_ccu_desc); reg 33 drivers/clk/sunxi-ng/ccu-sun5i.c .reg = 0x000, reg 72 drivers/clk/sunxi-ng/ccu-sun5i.c .reg = 0x008, reg 87 drivers/clk/sunxi-ng/ccu-sun5i.c .reg = 0x010, reg 105 drivers/clk/sunxi-ng/ccu-sun5i.c .reg = 0x018, reg 118 drivers/clk/sunxi-ng/ccu-sun5i.c .reg = 0x020, reg 133 drivers/clk/sunxi-ng/ccu-sun5i.c .reg = 0x020, reg 146 drivers/clk/sunxi-ng/ccu-sun5i.c .reg = 0x028, reg 161 drivers/clk/sunxi-ng/ccu-sun5i.c .reg = 0x030, reg 188 drivers/clk/sunxi-ng/ccu-sun5i.c .reg = 0x054, reg 213 drivers/clk/sunxi-ng/ccu-sun5i.c .reg = 0x054, reg 416 drivers/clk/sunxi-ng/ccu-sun5i.c .reg = 0x0c4, reg 990 drivers/clk/sunxi-ng/ccu-sun5i.c void __iomem *reg; reg 993 drivers/clk/sunxi-ng/ccu-sun5i.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 994 drivers/clk/sunxi-ng/ccu-sun5i.c if (IS_ERR(reg)) { reg 1000 drivers/clk/sunxi-ng/ccu-sun5i.c val = readl(reg + SUN5I_PLL_AUDIO_REG); reg 1002 drivers/clk/sunxi-ng/ccu-sun5i.c writel(val | (0 << 26), reg + SUN5I_PLL_AUDIO_REG); reg 1011 drivers/clk/sunxi-ng/ccu-sun5i.c val = readl(reg + SUN5I_AHB_REG); reg 1013 drivers/clk/sunxi-ng/ccu-sun5i.c writel(val | (2 << 6), reg + SUN5I_AHB_REG); reg 1015 drivers/clk/sunxi-ng/ccu-sun5i.c sunxi_ccu_probe(node, reg, desc); reg 219 drivers/clk/sunxi-ng/ccu-sun6i-a31.c .reg = 0x054, reg 581 drivers/clk/sunxi-ng/ccu-sun6i-a31.c .reg = 0x134, reg 594 drivers/clk/sunxi-ng/ccu-sun6i-a31.c .reg = 0x138, reg 672 drivers/clk/sunxi-ng/ccu-sun6i-a31.c .reg = 0x1a0, reg 691 drivers/clk/sunxi-ng/ccu-sun6i-a31.c .reg = 0x1a4, reg 710 drivers/clk/sunxi-ng/ccu-sun6i-a31.c .reg = 0x1a8, reg 754 drivers/clk/sunxi-ng/ccu-sun6i-a31.c .reg = 0x300, reg 775 drivers/clk/sunxi-ng/ccu-sun6i-a31.c .reg = 0x304, reg 796 drivers/clk/sunxi-ng/ccu-sun6i-a31.c .reg = 0x308, reg 1231 drivers/clk/sunxi-ng/ccu-sun6i-a31.c void __iomem *reg; reg 1234 drivers/clk/sunxi-ng/ccu-sun6i-a31.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 1235 drivers/clk/sunxi-ng/ccu-sun6i-a31.c if (IS_ERR(reg)) { reg 1241 drivers/clk/sunxi-ng/ccu-sun6i-a31.c val = readl(reg + SUN6I_A31_PLL_AUDIO_REG); reg 1243 drivers/clk/sunxi-ng/ccu-sun6i-a31.c writel(val | (0 << 16), reg + SUN6I_A31_PLL_AUDIO_REG); reg 1246 drivers/clk/sunxi-ng/ccu-sun6i-a31.c val = readl(reg + SUN6I_A31_PLL_MIPI_REG); reg 1248 drivers/clk/sunxi-ng/ccu-sun6i-a31.c writel(val, reg + SUN6I_A31_PLL_MIPI_REG); reg 1251 drivers/clk/sunxi-ng/ccu-sun6i-a31.c val = readl(reg + SUN6I_A31_AHB1_REG); reg 1258 drivers/clk/sunxi-ng/ccu-sun6i-a31.c writel(val, reg + SUN6I_A31_AHB1_REG); reg 1260 drivers/clk/sunxi-ng/ccu-sun6i-a31.c sunxi_ccu_probe(node, reg, &sun6i_a31_ccu_desc); reg 37 drivers/clk/sunxi-ng/ccu-sun8i-a23.c .reg = 0x000, reg 192 drivers/clk/sunxi-ng/ccu-sun8i-a23.c .reg = 0x054, reg 729 drivers/clk/sunxi-ng/ccu-sun8i-a23.c void __iomem *reg; reg 732 drivers/clk/sunxi-ng/ccu-sun8i-a23.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 733 drivers/clk/sunxi-ng/ccu-sun8i-a23.c if (IS_ERR(reg)) { reg 739 drivers/clk/sunxi-ng/ccu-sun8i-a23.c val = readl(reg + SUN8I_A23_PLL_AUDIO_REG); reg 741 drivers/clk/sunxi-ng/ccu-sun8i-a23.c writel(val | (0 << 16), reg + SUN8I_A23_PLL_AUDIO_REG); reg 744 drivers/clk/sunxi-ng/ccu-sun8i-a23.c val = readl(reg + SUN8I_A23_PLL_MIPI_REG); reg 746 drivers/clk/sunxi-ng/ccu-sun8i-a23.c writel(val, reg + SUN8I_A23_PLL_MIPI_REG); reg 748 drivers/clk/sunxi-ng/ccu-sun8i-a23.c sunxi_ccu_probe(node, reg, &sun8i_a23_ccu_desc); reg 35 drivers/clk/sunxi-ng/ccu-sun8i-a33.c .reg = 0x000, reg 171 drivers/clk/sunxi-ng/ccu-sun8i-a33.c .reg = 0x04c, reg 202 drivers/clk/sunxi-ng/ccu-sun8i-a33.c .reg = 0x054, reg 789 drivers/clk/sunxi-ng/ccu-sun8i-a33.c void __iomem *reg; reg 792 drivers/clk/sunxi-ng/ccu-sun8i-a33.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 793 drivers/clk/sunxi-ng/ccu-sun8i-a33.c if (IS_ERR(reg)) { reg 799 drivers/clk/sunxi-ng/ccu-sun8i-a33.c val = readl(reg + SUN8I_A33_PLL_AUDIO_REG); reg 801 drivers/clk/sunxi-ng/ccu-sun8i-a33.c writel(val | (0 << 16), reg + SUN8I_A33_PLL_AUDIO_REG); reg 804 drivers/clk/sunxi-ng/ccu-sun8i-a33.c val = readl(reg + SUN8I_A33_PLL_MIPI_REG); reg 806 drivers/clk/sunxi-ng/ccu-sun8i-a33.c writel(val, reg + SUN8I_A33_PLL_MIPI_REG); reg 808 drivers/clk/sunxi-ng/ccu-sun8i-a33.c sunxi_ccu_probe(node, reg, &sun8i_a33_ccu_desc); reg 41 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .reg = SUN8I_A83T_PLL_C0CPUX_REG, reg 55 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .reg = SUN8I_A83T_PLL_C1CPUX_REG, reg 87 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .reg = SUN8I_A83T_PLL_AUDIO_REG, reg 106 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .reg = 0x010, reg 122 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .reg = 0x018, reg 138 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .reg = 0x020, reg 154 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .reg = 0x028, reg 170 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .reg = 0x038, reg 186 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .reg = 0x044, reg 202 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .reg = 0x048, reg 219 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .reg = 0x04c, reg 256 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .reg = 0x054, reg 287 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .reg = 0x05c, reg 383 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .reg = 0x078, reg 479 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c .reg = 0x0cc, reg 862 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c static void sun8i_a83t_cpu_pll_fixup(void __iomem *reg) reg 864 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c u32 val = readl(reg); reg 885 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c writel(val, reg); reg 891 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c void __iomem *reg; reg 895 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c reg = devm_ioremap_resource(&pdev->dev, res); reg 896 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c if (IS_ERR(reg)) reg 897 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c return PTR_ERR(reg); reg 900 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c val = readl(reg + SUN8I_A83T_PLL_AUDIO_REG); reg 903 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c writel(val, reg + SUN8I_A83T_PLL_AUDIO_REG); reg 906 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c sun8i_a83t_cpu_pll_fixup(reg + SUN8I_A83T_PLL_C0CPUX_REG); reg 907 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c sun8i_a83t_cpu_pll_fixup(reg + SUN8I_A83T_PLL_C1CPUX_REG); reg 909 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_a83t_ccu_desc); reg 257 drivers/clk/sunxi-ng/ccu-sun8i-de2.c void __iomem *reg; reg 266 drivers/clk/sunxi-ng/ccu-sun8i-de2.c reg = devm_ioremap_resource(&pdev->dev, res); reg 267 drivers/clk/sunxi-ng/ccu-sun8i-de2.c if (IS_ERR(reg)) reg 268 drivers/clk/sunxi-ng/ccu-sun8i-de2.c return PTR_ERR(reg); reg 316 drivers/clk/sunxi-ng/ccu-sun8i-de2.c ret = sunxi_ccu_probe(pdev->dev.of_node, reg, ccu_desc); reg 166 drivers/clk/sunxi-ng/ccu-sun8i-h3.c .reg = 0x054, reg 206 drivers/clk/sunxi-ng/ccu-sun8i-h3.c .reg = 0x05c, reg 1142 drivers/clk/sunxi-ng/ccu-sun8i-h3.c void __iomem *reg; reg 1145 drivers/clk/sunxi-ng/ccu-sun8i-h3.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 1146 drivers/clk/sunxi-ng/ccu-sun8i-h3.c if (IS_ERR(reg)) { reg 1152 drivers/clk/sunxi-ng/ccu-sun8i-h3.c val = readl(reg + SUN8I_H3_PLL_AUDIO_REG); reg 1154 drivers/clk/sunxi-ng/ccu-sun8i-h3.c writel(val | (0 << 16), reg + SUN8I_H3_PLL_AUDIO_REG); reg 1156 drivers/clk/sunxi-ng/ccu-sun8i-h3.c sunxi_ccu_probe(node, reg, desc); reg 43 drivers/clk/sunxi-ng/ccu-sun8i-r.c .reg = 0x00, reg 107 drivers/clk/sunxi-ng/ccu-sun8i-r.c .reg = 0x54, reg 260 drivers/clk/sunxi-ng/ccu-sun8i-r.c void __iomem *reg; reg 262 drivers/clk/sunxi-ng/ccu-sun8i-r.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 263 drivers/clk/sunxi-ng/ccu-sun8i-r.c if (IS_ERR(reg)) { reg 268 drivers/clk/sunxi-ng/ccu-sun8i-r.c sunxi_ccu_probe(node, reg, desc); reg 35 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .reg = 0x000, reg 106 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .reg = 0x028, reg 124 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .reg = 0x028, reg 140 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .reg = 0x02c, reg 170 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .reg = 0x034, reg 220 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .reg = 0x040, reg 274 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .reg = 0x054, reg 469 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .reg = 0x074, reg 584 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .reg = 0x0c4, reg 761 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .reg = 0x1f0, reg 780 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .reg = 0x1f4, reg 1276 drivers/clk/sunxi-ng/ccu-sun8i-r40.c unsigned int reg) reg 1278 drivers/clk/sunxi-ng/ccu-sun8i-r40.c if (reg == SUN8I_R40_GMAC_CFG_REG) reg 1301 drivers/clk/sunxi-ng/ccu-sun8i-r40.c void __iomem *reg; reg 1306 drivers/clk/sunxi-ng/ccu-sun8i-r40.c reg = devm_ioremap_resource(&pdev->dev, res); reg 1307 drivers/clk/sunxi-ng/ccu-sun8i-r40.c if (IS_ERR(reg)) reg 1308 drivers/clk/sunxi-ng/ccu-sun8i-r40.c return PTR_ERR(reg); reg 1311 drivers/clk/sunxi-ng/ccu-sun8i-r40.c val = readl(reg + SUN8I_R40_PLL_AUDIO_REG); reg 1313 drivers/clk/sunxi-ng/ccu-sun8i-r40.c writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG); reg 1316 drivers/clk/sunxi-ng/ccu-sun8i-r40.c val = readl(reg + SUN8I_R40_PLL_MIPI_REG); reg 1318 drivers/clk/sunxi-ng/ccu-sun8i-r40.c writel(val, reg + SUN8I_R40_PLL_MIPI_REG); reg 1321 drivers/clk/sunxi-ng/ccu-sun8i-r40.c val = readl(reg + SUN8I_R40_USB_CLK_REG); reg 1323 drivers/clk/sunxi-ng/ccu-sun8i-r40.c writel(val, reg + SUN8I_R40_USB_CLK_REG); reg 1331 drivers/clk/sunxi-ng/ccu-sun8i-r40.c reg + SUN8I_R40_SYS_32K_CLK_REG); reg 1333 drivers/clk/sunxi-ng/ccu-sun8i-r40.c regmap = devm_regmap_init_mmio(&pdev->dev, reg, reg 1338 drivers/clk/sunxi-ng/ccu-sun8i-r40.c ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_r40_ccu_desc); reg 151 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c .reg = 0x054, reg 191 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c .reg = 0x05c, reg 800 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c void __iomem *reg; reg 803 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 804 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c if (IS_ERR(reg)) { reg 810 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c val = readl(reg + SUN8I_V3S_PLL_AUDIO_REG); reg 812 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c writel(val | (3 << 16), reg + SUN8I_V3S_PLL_AUDIO_REG); reg 814 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c sunxi_ccu_probe(node, reg, ccu_desc); reg 209 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c void __iomem *reg; reg 213 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c reg = devm_ioremap_resource(&pdev->dev, res); reg 214 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c if (IS_ERR(reg)) reg 215 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c return PTR_ERR(reg); reg 249 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c ret = sunxi_ccu_probe(pdev->dev.of_node, reg, reg 97 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c void __iomem *reg; reg 101 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c reg = devm_ioremap_resource(&pdev->dev, res); reg 102 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c if (IS_ERR(reg)) reg 103 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c return PTR_ERR(reg); reg 120 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c ret = sunxi_ccu_probe(pdev->dev.of_node, reg, reg 40 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = SUN9I_A80_PLL_C0CPUX_REG, reg 54 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = SUN9I_A80_PLL_C1CPUX_REG, reg 76 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x008, reg 92 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x00c, reg 108 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x010, reg 124 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x014, reg 139 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x018, reg 155 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x01c, reg 171 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x020, reg 187 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x024, reg 203 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x028, reg 219 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x028, reg 269 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x060, reg 281 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x064, reg 293 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x068, reg 307 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x070, reg 319 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x074, reg 331 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x078, reg 361 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x180, reg 381 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x184, reg 493 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x42c, reg 688 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x50c, reg 704 drivers/clk/sunxi-ng/ccu-sun9i-a80.c .reg = 0x510, reg 1188 drivers/clk/sunxi-ng/ccu-sun9i-a80.c static void sun9i_a80_cpu_pll_fixup(void __iomem *reg) reg 1190 drivers/clk/sunxi-ng/ccu-sun9i-a80.c u32 val = readl(reg); reg 1211 drivers/clk/sunxi-ng/ccu-sun9i-a80.c writel(val, reg); reg 1217 drivers/clk/sunxi-ng/ccu-sun9i-a80.c void __iomem *reg; reg 1221 drivers/clk/sunxi-ng/ccu-sun9i-a80.c reg = devm_ioremap_resource(&pdev->dev, res); reg 1222 drivers/clk/sunxi-ng/ccu-sun9i-a80.c if (IS_ERR(reg)) reg 1223 drivers/clk/sunxi-ng/ccu-sun9i-a80.c return PTR_ERR(reg); reg 1226 drivers/clk/sunxi-ng/ccu-sun9i-a80.c val = readl(reg + SUN9I_A80_PLL_AUDIO_REG); reg 1228 drivers/clk/sunxi-ng/ccu-sun9i-a80.c writel(val, reg + SUN9I_A80_PLL_AUDIO_REG); reg 1231 drivers/clk/sunxi-ng/ccu-sun9i-a80.c sun9i_a80_cpu_pll_fixup(reg + SUN9I_A80_PLL_C0CPUX_REG); reg 1232 drivers/clk/sunxi-ng/ccu-sun9i-a80.c sun9i_a80_cpu_pll_fixup(reg + SUN9I_A80_PLL_C1CPUX_REG); reg 1234 drivers/clk/sunxi-ng/ccu-sun9i-a80.c return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun9i_a80_ccu_desc); reg 37 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c .reg = 0x000, reg 101 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c .reg = 0x028, reg 129 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c .reg = 0x054, reg 527 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c void __iomem *reg; reg 530 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 531 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c if (IS_ERR(reg)) { reg 537 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c val = readl(reg + SUNIV_PLL_AUDIO_REG); reg 539 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c writel(val | (3 << 16), reg + SUNIV_PLL_AUDIO_REG); reg 541 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c sunxi_ccu_probe(node, reg, &suniv_ccu_desc); reg 22 drivers/clk/sunxi-ng/ccu_common.c u32 reg; reg 30 drivers/clk/sunxi-ng/ccu_common.c addr = common->base + common->reg; reg 32 drivers/clk/sunxi-ng/ccu_common.c WARN_ON(readl_relaxed_poll_timeout(addr, reg, reg & lock, 100, 70000)); reg 82 drivers/clk/sunxi-ng/ccu_common.c int sunxi_ccu_probe(struct device_node *node, void __iomem *reg, reg 94 drivers/clk/sunxi-ng/ccu_common.c cclk->base = reg; reg 128 drivers/clk/sunxi-ng/ccu_common.c reset->base = reg; reg 28 drivers/clk/sunxi-ng/ccu_common.h u16 reg; reg 66 drivers/clk/sunxi-ng/ccu_common.h int sunxi_ccu_probe(struct device_node *node, void __iomem *reg, reg 61 drivers/clk/sunxi-ng/ccu_div.c u32 reg; reg 63 drivers/clk/sunxi-ng/ccu_div.c reg = readl(cd->common.base + cd->common.reg); reg 64 drivers/clk/sunxi-ng/ccu_div.c val = reg >> cd->div.shift; reg 94 drivers/clk/sunxi-ng/ccu_div.c u32 reg; reg 107 drivers/clk/sunxi-ng/ccu_div.c reg = readl(cd->common.base + cd->common.reg); reg 108 drivers/clk/sunxi-ng/ccu_div.c reg &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift); reg 110 drivers/clk/sunxi-ng/ccu_div.c writel(reg | (val << cd->div.shift), reg 111 drivers/clk/sunxi-ng/ccu_div.c cd->common.base + cd->common.reg); reg 95 drivers/clk/sunxi-ng/ccu_div.h .reg = _reg, \ reg 122 drivers/clk/sunxi-ng/ccu_div.h .reg = _reg, \ reg 156 drivers/clk/sunxi-ng/ccu_div.h .reg = _reg, \ reg 19 drivers/clk/sunxi-ng/ccu_frac.c return !(readl(common->base + common->reg) & cf->enable); reg 26 drivers/clk/sunxi-ng/ccu_frac.c u32 reg; reg 32 drivers/clk/sunxi-ng/ccu_frac.c reg = readl(common->base + common->reg); reg 33 drivers/clk/sunxi-ng/ccu_frac.c writel(reg & ~cf->enable, common->base + common->reg); reg 41 drivers/clk/sunxi-ng/ccu_frac.c u32 reg; reg 47 drivers/clk/sunxi-ng/ccu_frac.c reg = readl(common->base + common->reg); reg 48 drivers/clk/sunxi-ng/ccu_frac.c writel(reg | cf->enable, common->base + common->reg); reg 65 drivers/clk/sunxi-ng/ccu_frac.c u32 reg; reg 75 drivers/clk/sunxi-ng/ccu_frac.c reg = readl(common->base + common->reg); reg 78 drivers/clk/sunxi-ng/ccu_frac.c clk_hw_get_name(&common->hw), reg, cf->select); reg 80 drivers/clk/sunxi-ng/ccu_frac.c return (reg & cf->select) ? cf->rates[1] : cf->rates[0]; reg 88 drivers/clk/sunxi-ng/ccu_frac.c u32 reg, sel; reg 101 drivers/clk/sunxi-ng/ccu_frac.c reg = readl(common->base + common->reg); reg 102 drivers/clk/sunxi-ng/ccu_frac.c reg &= ~cf->select; reg 103 drivers/clk/sunxi-ng/ccu_frac.c writel(reg | sel, common->base + common->reg); reg 15 drivers/clk/sunxi-ng/ccu_gate.c u32 reg; reg 22 drivers/clk/sunxi-ng/ccu_gate.c reg = readl(common->base + common->reg); reg 23 drivers/clk/sunxi-ng/ccu_gate.c writel(reg & ~gate, common->base + common->reg); reg 38 drivers/clk/sunxi-ng/ccu_gate.c u32 reg; reg 45 drivers/clk/sunxi-ng/ccu_gate.c reg = readl(common->base + common->reg); reg 46 drivers/clk/sunxi-ng/ccu_gate.c writel(reg | gate, common->base + common->reg); reg 65 drivers/clk/sunxi-ng/ccu_gate.c return readl(common->base + common->reg) & gate; reg 23 drivers/clk/sunxi-ng/ccu_gate.h .reg = _reg, \ reg 35 drivers/clk/sunxi-ng/ccu_gate.h .reg = _reg, \ reg 47 drivers/clk/sunxi-ng/ccu_gate.h .reg = _reg, \ reg 63 drivers/clk/sunxi-ng/ccu_gate.h .reg = _reg, \ reg 75 drivers/clk/sunxi-ng/ccu_gate.h .reg = _reg, \ reg 32 drivers/clk/sunxi-ng/ccu_mmc_timing.c val = readl(cm->base + cm->reg); reg 37 drivers/clk/sunxi-ng/ccu_mmc_timing.c writel(val, cm->base + cm->reg); reg 61 drivers/clk/sunxi-ng/ccu_mmc_timing.c return !!(readl(cm->base + cm->reg) & CCU_MMC_NEW_TIMING_MODE); reg 152 drivers/clk/sunxi-ng/ccu_mp.c u32 reg; reg 158 drivers/clk/sunxi-ng/ccu_mp.c reg = readl(cmp->common.base + cmp->common.reg); reg 160 drivers/clk/sunxi-ng/ccu_mp.c m = reg >> cmp->m.shift; reg 166 drivers/clk/sunxi-ng/ccu_mp.c p = reg >> cmp->p.shift; reg 192 drivers/clk/sunxi-ng/ccu_mp.c u32 reg; reg 209 drivers/clk/sunxi-ng/ccu_mp.c reg = readl(cmp->common.base + cmp->common.reg); reg 210 drivers/clk/sunxi-ng/ccu_mp.c reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift); reg 211 drivers/clk/sunxi-ng/ccu_mp.c reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift); reg 212 drivers/clk/sunxi-ng/ccu_mp.c reg |= (m - cmp->m.offset) << cmp->m.shift; reg 213 drivers/clk/sunxi-ng/ccu_mp.c reg |= ilog2(p) << cmp->p.shift; reg 215 drivers/clk/sunxi-ng/ccu_mp.c writel(reg, cmp->common.base + cmp->common.reg); reg 271 drivers/clk/sunxi-ng/ccu_mp.c u32 val = readl(cm->base + cm->reg); reg 282 drivers/clk/sunxi-ng/ccu_mp.c u32 val = readl(cm->base + cm->reg); reg 308 drivers/clk/sunxi-ng/ccu_mp.c u32 val = readl(cm->base + cm->reg); reg 46 drivers/clk/sunxi-ng/ccu_mp.h .reg = _reg, \ reg 66 drivers/clk/sunxi-ng/ccu_mp.h .reg = _reg, \ reg 111 drivers/clk/sunxi-ng/ccu_mp.h .reg = _reg, \ reg 79 drivers/clk/sunxi-ng/ccu_mult.c u32 reg; reg 84 drivers/clk/sunxi-ng/ccu_mult.c reg = readl(cm->common.base + cm->common.reg); reg 85 drivers/clk/sunxi-ng/ccu_mult.c val = reg >> cm->mult.shift; reg 109 drivers/clk/sunxi-ng/ccu_mult.c u32 reg; reg 134 drivers/clk/sunxi-ng/ccu_mult.c reg = readl(cm->common.base + cm->common.reg); reg 135 drivers/clk/sunxi-ng/ccu_mult.c reg &= ~GENMASK(cm->mult.width + cm->mult.shift - 1, cm->mult.shift); reg 136 drivers/clk/sunxi-ng/ccu_mult.c reg |= ((_cm.mult - cm->mult.offset) << cm->mult.shift); reg 138 drivers/clk/sunxi-ng/ccu_mult.c writel(reg, cm->common.base + cm->common.reg); reg 53 drivers/clk/sunxi-ng/ccu_mult.h .reg = _reg, \ reg 20 drivers/clk/sunxi-ng/ccu_mux.c u32 reg; reg 30 drivers/clk/sunxi-ng/ccu_mux.c reg = readl(common->base + common->reg); reg 32 drivers/clk/sunxi-ng/ccu_mux.c parent_index = reg >> cm->shift; reg 51 drivers/clk/sunxi-ng/ccu_mux.c div = reg >> cm->var_predivs[i].shift; reg 159 drivers/clk/sunxi-ng/ccu_mux.c u32 reg; reg 162 drivers/clk/sunxi-ng/ccu_mux.c reg = readl(common->base + common->reg); reg 163 drivers/clk/sunxi-ng/ccu_mux.c parent = reg >> cm->shift; reg 183 drivers/clk/sunxi-ng/ccu_mux.c u32 reg; reg 190 drivers/clk/sunxi-ng/ccu_mux.c reg = readl(common->base + common->reg); reg 191 drivers/clk/sunxi-ng/ccu_mux.c reg &= ~GENMASK(cm->width + cm->shift - 1, cm->shift); reg 192 drivers/clk/sunxi-ng/ccu_mux.c writel(reg | (index << cm->shift), common->base + common->reg); reg 43 drivers/clk/sunxi-ng/ccu_mux.h u16 reg; reg 57 drivers/clk/sunxi-ng/ccu_mux.h .reg = _reg, \ reg 70 drivers/clk/sunxi-ng/ccu_nk.c u32 reg; reg 72 drivers/clk/sunxi-ng/ccu_nk.c reg = readl(nk->common.base + nk->common.reg); reg 74 drivers/clk/sunxi-ng/ccu_nk.c n = reg >> nk->n.shift; reg 80 drivers/clk/sunxi-ng/ccu_nk.c k = reg >> nk->k.shift; reg 122 drivers/clk/sunxi-ng/ccu_nk.c u32 reg; reg 136 drivers/clk/sunxi-ng/ccu_nk.c reg = readl(nk->common.base + nk->common.reg); reg 137 drivers/clk/sunxi-ng/ccu_nk.c reg &= ~GENMASK(nk->n.width + nk->n.shift - 1, nk->n.shift); reg 138 drivers/clk/sunxi-ng/ccu_nk.c reg &= ~GENMASK(nk->k.width + nk->k.shift - 1, nk->k.shift); reg 140 drivers/clk/sunxi-ng/ccu_nk.c reg |= (_nk.k - nk->k.offset) << nk->k.shift; reg 141 drivers/clk/sunxi-ng/ccu_nk.c reg |= (_nk.n - nk->n.offset) << nk->n.shift; reg 142 drivers/clk/sunxi-ng/ccu_nk.c writel(reg, nk->common.base + nk->common.reg); reg 21 drivers/clk/sunxi-ng/ccu_nk.h u16 reg; reg 45 drivers/clk/sunxi-ng/ccu_nk.h .reg = _reg, \ reg 76 drivers/clk/sunxi-ng/ccu_nkm.c u32 reg; reg 78 drivers/clk/sunxi-ng/ccu_nkm.c reg = readl(nkm->common.base + nkm->common.reg); reg 80 drivers/clk/sunxi-ng/ccu_nkm.c n = reg >> nkm->n.shift; reg 86 drivers/clk/sunxi-ng/ccu_nkm.c k = reg >> nkm->k.shift; reg 92 drivers/clk/sunxi-ng/ccu_nkm.c m = reg >> nkm->m.shift; reg 150 drivers/clk/sunxi-ng/ccu_nkm.c u32 reg; reg 166 drivers/clk/sunxi-ng/ccu_nkm.c reg = readl(nkm->common.base + nkm->common.reg); reg 167 drivers/clk/sunxi-ng/ccu_nkm.c reg &= ~GENMASK(nkm->n.width + nkm->n.shift - 1, nkm->n.shift); reg 168 drivers/clk/sunxi-ng/ccu_nkm.c reg &= ~GENMASK(nkm->k.width + nkm->k.shift - 1, nkm->k.shift); reg 169 drivers/clk/sunxi-ng/ccu_nkm.c reg &= ~GENMASK(nkm->m.width + nkm->m.shift - 1, nkm->m.shift); reg 171 drivers/clk/sunxi-ng/ccu_nkm.c reg |= (_nkm.n - nkm->n.offset) << nkm->n.shift; reg 172 drivers/clk/sunxi-ng/ccu_nkm.c reg |= (_nkm.k - nkm->k.offset) << nkm->k.shift; reg 173 drivers/clk/sunxi-ng/ccu_nkm.c reg |= (_nkm.m - nkm->m.offset) << nkm->m.shift; reg 174 drivers/clk/sunxi-ng/ccu_nkm.c writel(reg, nkm->common.base + nkm->common.reg); reg 48 drivers/clk/sunxi-ng/ccu_nkm.h .reg = _reg, \ reg 68 drivers/clk/sunxi-ng/ccu_nkm.h .reg = _reg, \ reg 96 drivers/clk/sunxi-ng/ccu_nkmp.c u32 reg; reg 98 drivers/clk/sunxi-ng/ccu_nkmp.c reg = readl(nkmp->common.base + nkmp->common.reg); reg 100 drivers/clk/sunxi-ng/ccu_nkmp.c n = reg >> nkmp->n.shift; reg 106 drivers/clk/sunxi-ng/ccu_nkmp.c k = reg >> nkmp->k.shift; reg 112 drivers/clk/sunxi-ng/ccu_nkmp.c m = reg >> nkmp->m.shift; reg 118 drivers/clk/sunxi-ng/ccu_nkmp.c p = reg >> nkmp->p.shift; reg 170 drivers/clk/sunxi-ng/ccu_nkmp.c u32 reg; reg 207 drivers/clk/sunxi-ng/ccu_nkmp.c reg = readl(nkmp->common.base + nkmp->common.reg); reg 208 drivers/clk/sunxi-ng/ccu_nkmp.c reg &= ~(n_mask | k_mask | m_mask | p_mask); reg 210 drivers/clk/sunxi-ng/ccu_nkmp.c reg |= ((_nkmp.n - nkmp->n.offset) << nkmp->n.shift) & n_mask; reg 211 drivers/clk/sunxi-ng/ccu_nkmp.c reg |= ((_nkmp.k - nkmp->k.offset) << nkmp->k.shift) & k_mask; reg 212 drivers/clk/sunxi-ng/ccu_nkmp.c reg |= ((_nkmp.m - nkmp->m.offset) << nkmp->m.shift) & m_mask; reg 213 drivers/clk/sunxi-ng/ccu_nkmp.c reg |= (ilog2(_nkmp.p) << nkmp->p.shift) & p_mask; reg 215 drivers/clk/sunxi-ng/ccu_nkmp.c writel(reg, nkmp->common.base + nkmp->common.reg); reg 49 drivers/clk/sunxi-ng/ccu_nkmp.h .reg = _reg, \ reg 84 drivers/clk/sunxi-ng/ccu_nm.c u32 reg; reg 95 drivers/clk/sunxi-ng/ccu_nm.c reg = readl(nm->common.base + nm->common.reg); reg 97 drivers/clk/sunxi-ng/ccu_nm.c n = reg >> nm->n.shift; reg 103 drivers/clk/sunxi-ng/ccu_nm.c m = reg >> nm->m.shift; reg 175 drivers/clk/sunxi-ng/ccu_nm.c u32 reg; reg 185 drivers/clk/sunxi-ng/ccu_nm.c reg = readl(nm->common.base + nm->common.reg); reg 186 drivers/clk/sunxi-ng/ccu_nm.c reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift); reg 187 drivers/clk/sunxi-ng/ccu_nm.c writel(reg, nm->common.base + nm->common.reg); reg 217 drivers/clk/sunxi-ng/ccu_nm.c reg = readl(nm->common.base + nm->common.reg); reg 218 drivers/clk/sunxi-ng/ccu_nm.c reg &= ~GENMASK(nm->n.width + nm->n.shift - 1, nm->n.shift); reg 219 drivers/clk/sunxi-ng/ccu_nm.c reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift); reg 221 drivers/clk/sunxi-ng/ccu_nm.c reg |= (_nm.n - nm->n.offset) << nm->n.shift; reg 222 drivers/clk/sunxi-ng/ccu_nm.c reg |= (_nm.m - nm->m.offset) << nm->m.shift; reg 223 drivers/clk/sunxi-ng/ccu_nm.c writel(reg, nm->common.base + nm->common.reg); reg 52 drivers/clk/sunxi-ng/ccu_nm.h .reg = _reg, \ reg 76 drivers/clk/sunxi-ng/ccu_nm.h .reg = _reg, \ reg 102 drivers/clk/sunxi-ng/ccu_nm.h .reg = _reg, \ reg 131 drivers/clk/sunxi-ng/ccu_nm.h .reg = _reg, \ reg 150 drivers/clk/sunxi-ng/ccu_nm.h .reg = _reg, \ reg 19 drivers/clk/sunxi-ng/ccu_phase.c u32 reg; reg 22 drivers/clk/sunxi-ng/ccu_phase.c reg = readl(phase->common.base + phase->common.reg); reg 23 drivers/clk/sunxi-ng/ccu_phase.c delay = (reg >> phase->shift); reg 62 drivers/clk/sunxi-ng/ccu_phase.c u32 reg; reg 111 drivers/clk/sunxi-ng/ccu_phase.c reg = readl(phase->common.base + phase->common.reg); reg 112 drivers/clk/sunxi-ng/ccu_phase.c reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift); reg 113 drivers/clk/sunxi-ng/ccu_phase.c writel(reg | (delay << phase->shift), reg 114 drivers/clk/sunxi-ng/ccu_phase.c phase->common.base + phase->common.reg); reg 25 drivers/clk/sunxi-ng/ccu_phase.h .reg = _reg, \ reg 19 drivers/clk/sunxi-ng/ccu_reset.c u32 reg; reg 23 drivers/clk/sunxi-ng/ccu_reset.c reg = readl(ccu->base + map->reg); reg 24 drivers/clk/sunxi-ng/ccu_reset.c writel(reg & ~map->bit, ccu->base + map->reg); reg 37 drivers/clk/sunxi-ng/ccu_reset.c u32 reg; reg 41 drivers/clk/sunxi-ng/ccu_reset.c reg = readl(ccu->base + map->reg); reg 42 drivers/clk/sunxi-ng/ccu_reset.c writel(reg | map->bit, ccu->base + map->reg); reg 69 drivers/clk/sunxi-ng/ccu_reset.c return !(map->bit & readl(ccu->base + map->reg)); reg 13 drivers/clk/sunxi-ng/ccu_reset.h u16 reg; reg 18 drivers/clk/sunxi-ng/ccu_sdm.c if (sdm->enable && !(readl(common->base + common->reg) & sdm->enable)) reg 30 drivers/clk/sunxi-ng/ccu_sdm.c u32 reg; reg 43 drivers/clk/sunxi-ng/ccu_sdm.c reg = readl(common->base + sdm->tuning_reg); reg 44 drivers/clk/sunxi-ng/ccu_sdm.c writel(reg | sdm->tuning_enable, common->base + sdm->tuning_reg); reg 48 drivers/clk/sunxi-ng/ccu_sdm.c reg = readl(common->base + common->reg); reg 49 drivers/clk/sunxi-ng/ccu_sdm.c writel(reg | sdm->enable, common->base + common->reg); reg 57 drivers/clk/sunxi-ng/ccu_sdm.c u32 reg; reg 63 drivers/clk/sunxi-ng/ccu_sdm.c reg = readl(common->base + common->reg); reg 64 drivers/clk/sunxi-ng/ccu_sdm.c writel(reg & ~sdm->enable, common->base + common->reg); reg 68 drivers/clk/sunxi-ng/ccu_sdm.c reg = readl(common->base + sdm->tuning_reg); reg 69 drivers/clk/sunxi-ng/ccu_sdm.c writel(reg & ~sdm->tuning_enable, common->base + sdm->tuning_reg); reg 111 drivers/clk/sunxi-ng/ccu_sdm.c u32 reg; reg 122 drivers/clk/sunxi-ng/ccu_sdm.c reg = readl(common->base + sdm->tuning_reg); reg 125 drivers/clk/sunxi-ng/ccu_sdm.c clk_hw_get_name(&common->hw), reg); reg 128 drivers/clk/sunxi-ng/ccu_sdm.c if (sdm->table[i].pattern == reg && reg 18 drivers/clk/sunxi/clk-a10-codec.c void __iomem *reg; reg 20 drivers/clk/sunxi/clk-a10-codec.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 21 drivers/clk/sunxi/clk-a10-codec.c if (IS_ERR(reg)) reg 28 drivers/clk/sunxi/clk-a10-codec.c CLK_SET_RATE_PARENT, reg, reg 39 drivers/clk/sunxi/clk-a10-hosc.c gate->reg = of_iomap(node, 0); reg 28 drivers/clk/sunxi/clk-a10-mod1.c void __iomem *reg; reg 31 drivers/clk/sunxi/clk-a10-mod1.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 32 drivers/clk/sunxi/clk-a10-mod1.c if (IS_ERR(reg)) reg 46 drivers/clk/sunxi/clk-a10-mod1.c gate->reg = reg; reg 49 drivers/clk/sunxi/clk-a10-mod1.c mux->reg = reg; reg 70 drivers/clk/sunxi/clk-a10-mod1.c iounmap(reg); reg 46 drivers/clk/sunxi/clk-a10-pll2.c void __iomem *reg; reg 49 drivers/clk/sunxi/clk-a10-pll2.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 50 drivers/clk/sunxi/clk-a10-pll2.c if (IS_ERR(reg)) reg 63 drivers/clk/sunxi/clk-a10-pll2.c parent, 0, reg, reg 78 drivers/clk/sunxi/clk-a10-pll2.c gate->reg = reg; reg 87 drivers/clk/sunxi/clk-a10-pll2.c mult->reg = reg; reg 115 drivers/clk/sunxi/clk-a10-pll2.c val = readl(reg); reg 118 drivers/clk/sunxi/clk-a10-pll2.c writel(val, reg); reg 178 drivers/clk/sunxi/clk-a10-pll2.c iounmap(reg); reg 28 drivers/clk/sunxi/clk-a10-ve.c void __iomem *reg; reg 40 drivers/clk/sunxi/clk-a10-ve.c u32 reg; reg 44 drivers/clk/sunxi/clk-a10-ve.c reg = readl(data->reg); reg 45 drivers/clk/sunxi/clk-a10-ve.c writel(reg & ~BIT(SUN4I_VE_RESET), data->reg); reg 59 drivers/clk/sunxi/clk-a10-ve.c u32 reg; reg 63 drivers/clk/sunxi/clk-a10-ve.c reg = readl(data->reg); reg 64 drivers/clk/sunxi/clk-a10-ve.c writel(reg | BIT(SUN4I_VE_RESET), data->reg); reg 93 drivers/clk/sunxi/clk-a10-ve.c void __iomem *reg; reg 96 drivers/clk/sunxi/clk-a10-ve.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 97 drivers/clk/sunxi/clk-a10-ve.c if (IS_ERR(reg)) reg 111 drivers/clk/sunxi/clk-a10-ve.c gate->reg = reg; reg 115 drivers/clk/sunxi/clk-a10-ve.c div->reg = reg; reg 136 drivers/clk/sunxi/clk-a10-ve.c reset_data->reg = reg; reg 160 drivers/clk/sunxi/clk-a10-ve.c iounmap(reg); reg 59 drivers/clk/sunxi/clk-a20-gmac.c void __iomem *reg; reg 77 drivers/clk/sunxi/clk-a20-gmac.c reg = of_iomap(node, 0); reg 78 drivers/clk/sunxi/clk-a20-gmac.c if (!reg) reg 82 drivers/clk/sunxi/clk-a20-gmac.c gate->reg = reg; reg 85 drivers/clk/sunxi/clk-a20-gmac.c mux->reg = reg; reg 105 drivers/clk/sunxi/clk-a20-gmac.c iounmap(reg); reg 35 drivers/clk/sunxi/clk-factors.c #define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit)) reg 37 drivers/clk/sunxi/clk-factors.c #define FACTOR_SET(bit, len, reg, val) \ reg 38 drivers/clk/sunxi/clk-factors.c (((reg) & CLRMASK(len, bit)) | (val << (bit))) reg 44 drivers/clk/sunxi/clk-factors.c u32 reg; reg 50 drivers/clk/sunxi/clk-factors.c reg = readl(factors->reg); reg 54 drivers/clk/sunxi/clk-factors.c n = FACTOR_GET(config->nshift, config->nwidth, reg); reg 56 drivers/clk/sunxi/clk-factors.c k = FACTOR_GET(config->kshift, config->kwidth, reg); reg 58 drivers/clk/sunxi/clk-factors.c m = FACTOR_GET(config->mshift, config->mwidth, reg); reg 60 drivers/clk/sunxi/clk-factors.c p = FACTOR_GET(config->pshift, config->pwidth, reg); reg 74 drivers/clk/sunxi/clk-factors.c (reg >> factors->mux->shift) & reg 139 drivers/clk/sunxi/clk-factors.c u32 reg; reg 150 drivers/clk/sunxi/clk-factors.c reg = readl(factors->reg); reg 153 drivers/clk/sunxi/clk-factors.c reg = FACTOR_SET(config->nshift, config->nwidth, reg, req.n); reg 154 drivers/clk/sunxi/clk-factors.c reg = FACTOR_SET(config->kshift, config->kwidth, reg, req.k); reg 155 drivers/clk/sunxi/clk-factors.c reg = FACTOR_SET(config->mshift, config->mwidth, reg, req.m); reg 156 drivers/clk/sunxi/clk-factors.c reg = FACTOR_SET(config->pshift, config->pwidth, reg, req.p); reg 159 drivers/clk/sunxi/clk-factors.c writel(reg, factors->reg); reg 178 drivers/clk/sunxi/clk-factors.c spinlock_t *lock, void __iomem *reg, reg 208 drivers/clk/sunxi/clk-factors.c factors->reg = reg; reg 223 drivers/clk/sunxi/clk-factors.c gate->reg = reg; reg 238 drivers/clk/sunxi/clk-factors.c mux->reg = reg; reg 275 drivers/clk/sunxi/clk-factors.c void __iomem *reg) reg 277 drivers/clk/sunxi/clk-factors.c return __sunxi_factors_register(node, data, lock, reg, 0); reg 283 drivers/clk/sunxi/clk-factors.c void __iomem *reg) reg 285 drivers/clk/sunxi/clk-factors.c return __sunxi_factors_register(node, data, lock, reg, CLK_IS_CRITICAL); reg 44 drivers/clk/sunxi/clk-factors.h void __iomem *reg; reg 57 drivers/clk/sunxi/clk-factors.h void __iomem *reg); reg 61 drivers/clk/sunxi/clk-factors.h void __iomem *reg); reg 70 drivers/clk/sunxi/clk-mod0.c void __iomem *reg; reg 72 drivers/clk/sunxi/clk-mod0.c reg = of_iomap(node, 0); reg 73 drivers/clk/sunxi/clk-mod0.c if (!reg) { reg 83 drivers/clk/sunxi/clk-mod0.c &sun4i_a10_mod0_lock, reg); reg 92 drivers/clk/sunxi/clk-mod0.c void __iomem *reg; reg 98 drivers/clk/sunxi/clk-mod0.c reg = devm_ioremap_resource(&pdev->dev, r); reg 99 drivers/clk/sunxi/clk-mod0.c if (IS_ERR(reg)) reg 100 drivers/clk/sunxi/clk-mod0.c return PTR_ERR(reg); reg 103 drivers/clk/sunxi/clk-mod0.c &sun4i_a10_mod0_lock, reg); reg 131 drivers/clk/sunxi/clk-mod0.c void __iomem *reg; reg 133 drivers/clk/sunxi/clk-mod0.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 134 drivers/clk/sunxi/clk-mod0.c if (IS_ERR(reg)) { reg 141 drivers/clk/sunxi/clk-mod0.c &sun4i_a10_mod0_lock, reg); reg 149 drivers/clk/sunxi/clk-mod0.c void __iomem *reg; reg 151 drivers/clk/sunxi/clk-mod0.c reg = of_iomap(node, 0); reg 152 drivers/clk/sunxi/clk-mod0.c if (!reg) { reg 159 drivers/clk/sunxi/clk-mod0.c &sun5i_a13_mbus_lock, reg); reg 166 drivers/clk/sunxi/clk-mod0.c void __iomem *reg; reg 181 drivers/clk/sunxi/clk-mod0.c value = readl(phase->reg); reg 269 drivers/clk/sunxi/clk-mod0.c value = readl(phase->reg); reg 272 drivers/clk/sunxi/clk-mod0.c writel(value, phase->reg); reg 296 drivers/clk/sunxi/clk-mod0.c void __iomem *reg; reg 299 drivers/clk/sunxi/clk-mod0.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 300 drivers/clk/sunxi/clk-mod0.c if (IS_ERR(reg)) { reg 314 drivers/clk/sunxi/clk-mod0.c clk_data->clks[0] = sunxi_factors_register(node, data, lock, reg); reg 333 drivers/clk/sunxi/clk-mod0.c phase->reg = reg; reg 27 drivers/clk/sunxi/clk-simple-gates.c void __iomem *reg; reg 33 drivers/clk/sunxi/clk-simple-gates.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 34 drivers/clk/sunxi/clk-simple-gates.c if (IS_ERR(reg)) reg 54 drivers/clk/sunxi/clk-simple-gates.c clk_reg = reg + 4 * (index / 32); reg 83 drivers/clk/sunxi/clk-simple-gates.c iounmap(reg); reg 33 drivers/clk/sunxi/clk-sun4i-display.c void __iomem *reg; reg 51 drivers/clk/sunxi/clk-sun4i-display.c u32 reg; reg 55 drivers/clk/sunxi/clk-sun4i-display.c reg = readl(data->reg); reg 56 drivers/clk/sunxi/clk-sun4i-display.c writel(reg & ~BIT(data->offset + id), data->reg); reg 68 drivers/clk/sunxi/clk-sun4i-display.c u32 reg; reg 72 drivers/clk/sunxi/clk-sun4i-display.c reg = readl(data->reg); reg 73 drivers/clk/sunxi/clk-sun4i-display.c writel(reg | BIT(data->offset + id), data->reg); reg 85 drivers/clk/sunxi/clk-sun4i-display.c return !(readl(data->reg) & BIT(data->offset + id)); reg 111 drivers/clk/sunxi/clk-sun4i-display.c void __iomem *reg; reg 117 drivers/clk/sunxi/clk-sun4i-display.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 118 drivers/clk/sunxi/clk-sun4i-display.c if (IS_ERR(reg)) { reg 133 drivers/clk/sunxi/clk-sun4i-display.c mux->reg = reg; reg 142 drivers/clk/sunxi/clk-sun4i-display.c gate->reg = reg; reg 151 drivers/clk/sunxi/clk-sun4i-display.c div->reg = reg; reg 182 drivers/clk/sunxi/clk-sun4i-display.c reset_data->reg = reg; reg 217 drivers/clk/sunxi/clk-sun4i-display.c iounmap(reg); reg 27 drivers/clk/sunxi/clk-sun4i-pll3.c void __iomem *reg; reg 34 drivers/clk/sunxi/clk-sun4i-pll3.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 35 drivers/clk/sunxi/clk-sun4i-pll3.c if (IS_ERR(reg)) { reg 44 drivers/clk/sunxi/clk-sun4i-pll3.c gate->reg = reg; reg 52 drivers/clk/sunxi/clk-sun4i-pll3.c mult->reg = reg; reg 84 drivers/clk/sunxi/clk-sun4i-pll3.c iounmap(reg); reg 29 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c void __iomem *reg; reg 38 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c u32 reg; reg 41 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c reg = readl(tclk->reg); reg 42 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c reg &= ~(TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT); reg 43 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c writel(reg, tclk->reg); reg 51 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c u32 reg; reg 54 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c reg = readl(tclk->reg); reg 55 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c reg |= TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT; reg 56 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c writel(reg, tclk->reg); reg 65 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c u32 reg; reg 67 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c reg = readl(tclk->reg); reg 68 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c return reg & (TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT); reg 74 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c u32 reg; reg 76 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c reg = readl(tclk->reg) >> TCON_CH1_SCLK2_MUX_SHIFT; reg 77 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c reg &= reg >> TCON_CH1_SCLK2_MUX_MASK; reg 79 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c return reg; reg 86 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c u32 reg; reg 89 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c reg = readl(tclk->reg); reg 90 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c reg &= ~(TCON_CH1_SCLK2_MUX_MASK << TCON_CH1_SCLK2_MUX_SHIFT); reg 91 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c reg |= index << TCON_CH1_SCLK2_MUX_SHIFT; reg 92 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c writel(reg, tclk->reg); reg 174 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c u32 reg; reg 176 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c reg = readl(tclk->reg); reg 178 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c parent_rate /= (reg & TCON_CH1_SCLK2_DIV_MASK) + 1; reg 180 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c if (reg & TCON_CH1_SCLK1_HALF_BIT) reg 193 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c u32 reg; reg 198 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c reg = readl(tclk->reg); reg 199 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c reg &= ~(TCON_CH1_SCLK2_DIV_MASK | TCON_CH1_SCLK1_HALF_BIT); reg 200 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c reg |= (div_m - 1) & TCON_CH1_SCLK2_DIV_MASK; reg 203 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c reg |= TCON_CH1_SCLK1_HALF_BIT; reg 205 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c writel(reg, tclk->reg); reg 232 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c void __iomem *reg; reg 237 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 238 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c if (IS_ERR(reg)) { reg 259 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c tclk->reg = reg; reg 282 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c iounmap(reg); reg 45 drivers/clk/sunxi/clk-sun6i-apb0-gates.c void __iomem *reg; reg 59 drivers/clk/sunxi/clk-sun6i-apb0-gates.c reg = devm_ioremap_resource(&pdev->dev, r); reg 60 drivers/clk/sunxi/clk-sun6i-apb0-gates.c if (IS_ERR(reg)) reg 61 drivers/clk/sunxi/clk-sun6i-apb0-gates.c return PTR_ERR(reg); reg 84 drivers/clk/sunxi/clk-sun6i-apb0-gates.c clk_parent, 0, reg, i, reg 36 drivers/clk/sunxi/clk-sun6i-apb0.c void __iomem *reg; reg 40 drivers/clk/sunxi/clk-sun6i-apb0.c reg = devm_ioremap_resource(&pdev->dev, r); reg 41 drivers/clk/sunxi/clk-sun6i-apb0.c if (IS_ERR(reg)) reg 42 drivers/clk/sunxi/clk-sun6i-apb0.c return PTR_ERR(reg); reg 51 drivers/clk/sunxi/clk-sun6i-apb0.c 0, reg, 0, 2, 0, sun6i_a31_apb0_divs, reg 75 drivers/clk/sunxi/clk-sun6i-ar100.c void __iomem *reg; reg 79 drivers/clk/sunxi/clk-sun6i-ar100.c reg = devm_ioremap_resource(&pdev->dev, r); reg 80 drivers/clk/sunxi/clk-sun6i-ar100.c if (IS_ERR(reg)) reg 81 drivers/clk/sunxi/clk-sun6i-ar100.c return PTR_ERR(reg); reg 84 drivers/clk/sunxi/clk-sun6i-ar100.c reg); reg 23 drivers/clk/sunxi/clk-sun8i-apb0.c void __iomem *reg) reg 37 drivers/clk/sunxi/clk-sun8i-apb0.c clk = clk_register_divider(NULL, clk_name, clk_parent, 0, reg, reg 56 drivers/clk/sunxi/clk-sun8i-apb0.c void __iomem *reg; reg 60 drivers/clk/sunxi/clk-sun8i-apb0.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 61 drivers/clk/sunxi/clk-sun8i-apb0.c if (IS_ERR(reg)) { reg 67 drivers/clk/sunxi/clk-sun8i-apb0.c if (PTR_ERR(reg) != -EINVAL) reg 73 drivers/clk/sunxi/clk-sun8i-apb0.c clk = sun8i_a23_apb0_register(node, reg); reg 80 drivers/clk/sunxi/clk-sun8i-apb0.c iounmap(reg); reg 91 drivers/clk/sunxi/clk-sun8i-apb0.c void __iomem *reg; reg 95 drivers/clk/sunxi/clk-sun8i-apb0.c reg = devm_ioremap_resource(&pdev->dev, r); reg 96 drivers/clk/sunxi/clk-sun8i-apb0.c if (IS_ERR(reg)) reg 97 drivers/clk/sunxi/clk-sun8i-apb0.c return PTR_ERR(reg); reg 99 drivers/clk/sunxi/clk-sun8i-apb0.c clk = sun8i_a23_apb0_register(np, reg); reg 30 drivers/clk/sunxi/clk-sun8i-bus-gates.c void __iomem *reg; reg 36 drivers/clk/sunxi/clk-sun8i-bus-gates.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 37 drivers/clk/sunxi/clk-sun8i-bus-gates.c if (IS_ERR(reg)) reg 78 drivers/clk/sunxi/clk-sun8i-bus-gates.c clk_reg = reg + 4 * (index / 32); reg 101 drivers/clk/sunxi/clk-sun8i-bus-gates.c iounmap(reg); reg 34 drivers/clk/sunxi/clk-sun8i-mbus.c void __iomem *reg; reg 41 drivers/clk/sunxi/clk-sun8i-mbus.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 42 drivers/clk/sunxi/clk-sun8i-mbus.c if (IS_ERR(reg)) { reg 62 drivers/clk/sunxi/clk-sun8i-mbus.c gate->reg = reg; reg 66 drivers/clk/sunxi/clk-sun8i-mbus.c div->reg = reg; reg 71 drivers/clk/sunxi/clk-sun8i-mbus.c mux->reg = reg; reg 103 drivers/clk/sunxi/clk-sun8i-mbus.c iounmap(reg); reg 78 drivers/clk/sunxi/clk-sun9i-core.c void __iomem *reg; reg 80 drivers/clk/sunxi/clk-sun9i-core.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 81 drivers/clk/sunxi/clk-sun9i-core.c if (IS_ERR(reg)) { reg 88 drivers/clk/sunxi/clk-sun9i-core.c &sun9i_a80_pll4_lock, reg); reg 132 drivers/clk/sunxi/clk-sun9i-core.c void __iomem *reg; reg 134 drivers/clk/sunxi/clk-sun9i-core.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 135 drivers/clk/sunxi/clk-sun9i-core.c if (IS_ERR(reg)) { reg 143 drivers/clk/sunxi/clk-sun9i-core.c &sun9i_a80_gt_lock, reg); reg 187 drivers/clk/sunxi/clk-sun9i-core.c void __iomem *reg; reg 189 drivers/clk/sunxi/clk-sun9i-core.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 190 drivers/clk/sunxi/clk-sun9i-core.c if (IS_ERR(reg)) { reg 197 drivers/clk/sunxi/clk-sun9i-core.c &sun9i_a80_ahb_lock, reg); reg 213 drivers/clk/sunxi/clk-sun9i-core.c void __iomem *reg; reg 215 drivers/clk/sunxi/clk-sun9i-core.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 216 drivers/clk/sunxi/clk-sun9i-core.c if (IS_ERR(reg)) { reg 223 drivers/clk/sunxi/clk-sun9i-core.c &sun9i_a80_apb0_lock, reg); reg 270 drivers/clk/sunxi/clk-sun9i-core.c void __iomem *reg; reg 272 drivers/clk/sunxi/clk-sun9i-core.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 273 drivers/clk/sunxi/clk-sun9i-core.c if (IS_ERR(reg)) { reg 280 drivers/clk/sunxi/clk-sun9i-core.c &sun9i_a80_apb1_lock, reg); reg 29 drivers/clk/sunxi/clk-sun9i-cpus.c #define SUN9I_CPUS_MUX_GET_PARENT(reg) ((reg & SUN9I_CPUS_MUX_MASK) >> \ reg 34 drivers/clk/sunxi/clk-sun9i-cpus.c #define SUN9I_CPUS_DIV_GET(reg) ((reg & SUN9I_CPUS_DIV_MASK) >> \ reg 36 drivers/clk/sunxi/clk-sun9i-cpus.c #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ reg 40 drivers/clk/sunxi/clk-sun9i-cpus.c #define SUN9I_CPUS_PLL4_DIV_GET(reg) ((reg & SUN9I_CPUS_PLL4_DIV_MASK) >> \ reg 42 drivers/clk/sunxi/clk-sun9i-cpus.c #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ reg 47 drivers/clk/sunxi/clk-sun9i-cpus.c void __iomem *reg; reg 57 drivers/clk/sunxi/clk-sun9i-cpus.c u32 reg; reg 60 drivers/clk/sunxi/clk-sun9i-cpus.c reg = readl(cpus->reg); reg 63 drivers/clk/sunxi/clk-sun9i-cpus.c if (SUN9I_CPUS_MUX_GET_PARENT(reg) == SUN9I_CPUS_MUX_PARENT_PLL4) reg 64 drivers/clk/sunxi/clk-sun9i-cpus.c parent_rate /= SUN9I_CPUS_PLL4_DIV_GET(reg) + 1; reg 67 drivers/clk/sunxi/clk-sun9i-cpus.c rate = parent_rate / (SUN9I_CPUS_DIV_GET(reg) + 1); reg 158 drivers/clk/sunxi/clk-sun9i-cpus.c u32 reg; reg 162 drivers/clk/sunxi/clk-sun9i-cpus.c reg = readl(cpus->reg); reg 165 drivers/clk/sunxi/clk-sun9i-cpus.c parent = SUN9I_CPUS_MUX_GET_PARENT(reg); reg 168 drivers/clk/sunxi/clk-sun9i-cpus.c reg = SUN9I_CPUS_DIV_SET(reg, div); reg 169 drivers/clk/sunxi/clk-sun9i-cpus.c reg = SUN9I_CPUS_PLL4_DIV_SET(reg, pre_div); reg 170 drivers/clk/sunxi/clk-sun9i-cpus.c writel(reg, cpus->reg); reg 197 drivers/clk/sunxi/clk-sun9i-cpus.c cpus->reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 198 drivers/clk/sunxi/clk-sun9i-cpus.c if (IS_ERR(cpus->reg)) reg 211 drivers/clk/sunxi/clk-sun9i-cpus.c mux->reg = cpus->reg; reg 235 drivers/clk/sunxi/clk-sun9i-cpus.c iounmap(cpus->reg); reg 42 drivers/clk/sunxi/clk-sun9i-mmc.c void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id; reg 48 drivers/clk/sunxi/clk-sun9i-mmc.c val = readl(reg); reg 49 drivers/clk/sunxi/clk-sun9i-mmc.c writel(val & ~BIT(SUN9I_MMC_RESET_BIT), reg); reg 64 drivers/clk/sunxi/clk-sun9i-mmc.c void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id; reg 70 drivers/clk/sunxi/clk-sun9i-mmc.c val = readl(reg); reg 71 drivers/clk/sunxi/clk-sun9i-mmc.c writel(val | BIT(SUN9I_MMC_RESET_BIT), reg); reg 559 drivers/clk/sunxi/clk-sunxi.c void __iomem *reg; reg 561 drivers/clk/sunxi/clk-sunxi.c reg = of_iomap(node, 0); reg 562 drivers/clk/sunxi/clk-sunxi.c if (!reg) { reg 568 drivers/clk/sunxi/clk-sunxi.c return sunxi_factors_register(node, data, &clk_lock, reg); reg 657 drivers/clk/sunxi/clk-sunxi.c void __iomem *reg; reg 660 drivers/clk/sunxi/clk-sunxi.c reg = of_iomap(node, 0); reg 661 drivers/clk/sunxi/clk-sunxi.c if (!reg) { reg 674 drivers/clk/sunxi/clk-sunxi.c CLK_SET_RATE_PARENT | flags, reg, reg 693 drivers/clk/sunxi/clk-sunxi.c iounmap(reg); reg 781 drivers/clk/sunxi/clk-sunxi.c void __iomem *reg; reg 783 drivers/clk/sunxi/clk-sunxi.c reg = of_iomap(node, 0); reg 784 drivers/clk/sunxi/clk-sunxi.c if (!reg) { reg 798 drivers/clk/sunxi/clk-sunxi.c reg, data->shift, data->width, reg 823 drivers/clk/sunxi/clk-sunxi.c iounmap(reg); reg 957 drivers/clk/sunxi/clk-sunxi.c void __iomem *reg; reg 999 drivers/clk/sunxi/clk-sunxi.c reg = of_iomap(node, 0); reg 1000 drivers/clk/sunxi/clk-sunxi.c if (!reg) { reg 1040 drivers/clk/sunxi/clk-sunxi.c gate->reg = reg; reg 1065 drivers/clk/sunxi/clk-sunxi.c divider->reg = reg; reg 1106 drivers/clk/sunxi/clk-sunxi.c iounmap(reg); reg 23 drivers/clk/sunxi/clk-usb.c void __iomem *reg; reg 36 drivers/clk/sunxi/clk-usb.c u32 reg; reg 41 drivers/clk/sunxi/clk-usb.c reg = readl(data->reg); reg 42 drivers/clk/sunxi/clk-usb.c writel(reg & ~BIT(id), data->reg); reg 57 drivers/clk/sunxi/clk-usb.c u32 reg; reg 62 drivers/clk/sunxi/clk-usb.c reg = readl(data->reg); reg 63 drivers/clk/sunxi/clk-usb.c writel(reg | BIT(id), data->reg); reg 96 drivers/clk/sunxi/clk-usb.c void __iomem *reg; reg 101 drivers/clk/sunxi/clk-usb.c reg = of_io_request_and_map(node, 0, of_node_full_name(node)); reg 102 drivers/clk/sunxi/clk-usb.c if (IS_ERR(reg)) reg 129 drivers/clk/sunxi/clk-usb.c reg, i, 0, lock); reg 157 drivers/clk/sunxi/clk-usb.c reset_data->reg = reg; reg 39 drivers/clk/tegra/clk-divider.c u32 reg; reg 43 drivers/clk/tegra/clk-divider.c reg = readl_relaxed(divider->reg) >> divider->shift; reg 44 drivers/clk/tegra/clk-divider.c div = reg & div_mask(divider); reg 90 drivers/clk/tegra/clk-divider.c val = readl_relaxed(divider->reg); reg 104 drivers/clk/tegra/clk-divider.c writel_relaxed(val, divider->reg); reg 119 drivers/clk/tegra/clk-divider.c const char *parent_name, void __iomem *reg, reg 140 drivers/clk/tegra/clk-divider.c divider->reg = reg; reg 164 drivers/clk/tegra/clk-divider.c void __iomem *reg, spinlock_t *lock) reg 168 drivers/clk/tegra/clk-divider.c reg, 16, 1, CLK_DIVIDER_READ_ONLY, reg 160 drivers/clk/tegra/clk-periph.c periph->mux.reg = clk_base + offset; reg 161 drivers/clk/tegra/clk-periph.c periph->divider.reg = div ? (clk_base + offset) : NULL; reg 21 drivers/clk/tegra/clk-pll-out.c u32 val = readl_relaxed(pll_out->reg); reg 39 drivers/clk/tegra/clk-pll-out.c val = readl_relaxed(pll_out->reg); reg 43 drivers/clk/tegra/clk-pll-out.c writel_relaxed(val, pll_out->reg); reg 61 drivers/clk/tegra/clk-pll-out.c val = readl_relaxed(pll_out->reg); reg 65 drivers/clk/tegra/clk-pll-out.c writel_relaxed(val, pll_out->reg); reg 79 drivers/clk/tegra/clk-pll-out.c const char *parent_name, void __iomem *reg, u8 enb_bit_idx, reg 97 drivers/clk/tegra/clk-pll-out.c pll_out->reg = reg; reg 50 drivers/clk/tegra/clk-sdmmc-mux.c val = readl_relaxed(sdmmc_mux->reg); reg 73 drivers/clk/tegra/clk-sdmmc-mux.c val = readl_relaxed(sdmmc_mux->reg); reg 82 drivers/clk/tegra/clk-sdmmc-mux.c writel(val, sdmmc_mux->reg); reg 95 drivers/clk/tegra/clk-sdmmc-mux.c val = readl_relaxed(sdmmc_mux->reg); reg 157 drivers/clk/tegra/clk-sdmmc-mux.c writel(val, sdmmc_mux->reg); reg 158 drivers/clk/tegra/clk-sdmmc-mux.c fence_udelay(2, sdmmc_mux->reg); reg 233 drivers/clk/tegra/clk-sdmmc-mux.c sdmmc_mux->reg = clk_base + offset; reg 37 drivers/clk/tegra/clk-super.c val = readl_relaxed(mux->reg); reg 71 drivers/clk/tegra/clk-super.c val = readl_relaxed(mux->reg); reg 94 drivers/clk/tegra/clk-super.c writel_relaxed(val, mux->reg); reg 103 drivers/clk/tegra/clk-super.c writel_relaxed(val, mux->reg); reg 161 drivers/clk/tegra/clk-super.c unsigned long flags, void __iomem *reg, u8 clk_super_flags, reg 178 drivers/clk/tegra/clk-super.c super->reg = reg; reg 197 drivers/clk/tegra/clk-super.c unsigned long flags, void __iomem *reg, u8 clk_super_flags, reg 214 drivers/clk/tegra/clk-super.c super->reg = reg; reg 218 drivers/clk/tegra/clk-super.c super->frac_div.reg = reg + 4; reg 1094 drivers/clk/tegra/clk-tegra114.c unsigned int reg; reg 1097 drivers/clk/tegra/clk-tegra114.c reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); reg 1099 drivers/clk/tegra/clk-tegra114.c } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ reg 540 drivers/clk/tegra/clk-tegra124-dfll-fcpu.c struct regulator *reg = devm_regulator_get(dev, "vdd-cpu"); reg 542 drivers/clk/tegra/clk-tegra124-dfll-fcpu.c if (IS_ERR(reg)) reg 543 drivers/clk/tegra/clk-tegra124-dfll-fcpu.c return PTR_ERR(reg); reg 545 drivers/clk/tegra/clk-tegra124-dfll-fcpu.c align->offset_uv = regulator_list_voltage(reg, 0); reg 546 drivers/clk/tegra/clk-tegra124-dfll-fcpu.c align->step_uv = regulator_get_linear_step(reg); reg 548 drivers/clk/tegra/clk-tegra124-dfll-fcpu.c devm_regulator_put(reg); reg 1190 drivers/clk/tegra/clk-tegra124.c unsigned int reg; reg 1193 drivers/clk/tegra/clk-tegra124.c reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); reg 1195 drivers/clk/tegra/clk-tegra124.c } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ reg 914 drivers/clk/tegra/clk-tegra20.c unsigned int reg; reg 917 drivers/clk/tegra/clk-tegra20.c reg = readl(clk_base + reg 920 drivers/clk/tegra/clk-tegra20.c } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ reg 941 drivers/clk/tegra/clk-tegra20.c unsigned int reg; reg 943 drivers/clk/tegra/clk-tegra20.c reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); reg 944 drivers/clk/tegra/clk-tegra20.c writel(reg & ~CPU_CLOCK(cpu), reg 947 drivers/clk/tegra/clk-tegra20.c reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); reg 952 drivers/clk/tegra/clk-tegra20.c unsigned int reg; reg 954 drivers/clk/tegra/clk-tegra20.c reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); reg 955 drivers/clk/tegra/clk-tegra20.c writel(reg | CPU_CLOCK(cpu), reg 989 drivers/clk/tegra/clk-tegra20.c unsigned int reg, policy; reg 992 drivers/clk/tegra/clk-tegra20.c reg = readl(clk_base + CCLK_BURST_POLICY); reg 993 drivers/clk/tegra/clk-tegra20.c policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF; reg 996 drivers/clk/tegra/clk-tegra20.c reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF; reg 998 drivers/clk/tegra/clk-tegra20.c reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF; reg 1002 drivers/clk/tegra/clk-tegra20.c if (reg != CCLK_BURST_POLICY_PLLX) { reg 1337 drivers/clk/tegra/clk-tegra210.c u32 reg, u32 mask) reg 1344 drivers/clk/tegra/clk-tegra210.c val = readl_relaxed(clk_base + reg); reg 2708 drivers/clk/tegra/clk-tegra210.c u32 reg; reg 2710 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); reg 2712 drivers/clk/tegra/clk-tegra210.c if (reg & UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK) { reg 2717 drivers/clk/tegra/clk-tegra210.c reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; reg 2718 drivers/clk/tegra/clk-tegra210.c writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); reg 2724 drivers/clk/tegra/clk-tegra210.c u32 reg; reg 2726 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); reg 2727 drivers/clk/tegra/clk-tegra210.c reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; reg 2728 drivers/clk/tegra/clk-tegra210.c writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); reg 2734 drivers/clk/tegra/clk-tegra210.c u32 reg; reg 2748 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); reg 2749 drivers/clk/tegra/clk-tegra210.c reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; reg 2750 drivers/clk/tegra/clk-tegra210.c writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); reg 2754 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); reg 2758 drivers/clk/tegra/clk-tegra210.c reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); reg 2759 drivers/clk/tegra/clk-tegra210.c reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); reg 2761 drivers/clk/tegra/clk-tegra210.c reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); reg 2762 drivers/clk/tegra/clk-tegra210.c reg |= reg 2764 drivers/clk/tegra/clk-tegra210.c writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); reg 2767 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); reg 2769 drivers/clk/tegra/clk-tegra210.c reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); reg 2770 drivers/clk/tegra/clk-tegra210.c reg |= reg 2773 drivers/clk/tegra/clk-tegra210.c reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); reg 2774 drivers/clk/tegra/clk-tegra210.c reg |= reg 2777 drivers/clk/tegra/clk-tegra210.c reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; reg 2778 drivers/clk/tegra/clk-tegra210.c writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); reg 2781 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); reg 2782 drivers/clk/tegra/clk-tegra210.c reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; reg 2783 drivers/clk/tegra/clk-tegra210.c reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; reg 2784 drivers/clk/tegra/clk-tegra210.c writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); reg 2789 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); reg 2790 drivers/clk/tegra/clk-tegra210.c reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP; reg 2791 drivers/clk/tegra/clk-tegra210.c reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP; reg 2792 drivers/clk/tegra/clk-tegra210.c reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP; reg 2793 drivers/clk/tegra/clk-tegra210.c reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; reg 2794 drivers/clk/tegra/clk-tegra210.c reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; reg 2795 drivers/clk/tegra/clk-tegra210.c reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN; reg 2796 drivers/clk/tegra/clk-tegra210.c writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); reg 2799 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); reg 2800 drivers/clk/tegra/clk-tegra210.c reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; reg 2801 drivers/clk/tegra/clk-tegra210.c reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; reg 2802 drivers/clk/tegra/clk-tegra210.c writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); reg 2804 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); reg 2805 drivers/clk/tegra/clk-tegra210.c reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; reg 2806 drivers/clk/tegra/clk-tegra210.c reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; reg 2807 drivers/clk/tegra/clk-tegra210.c writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); reg 2811 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); reg 2812 drivers/clk/tegra/clk-tegra210.c reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY; reg 2813 drivers/clk/tegra/clk-tegra210.c writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); reg 2818 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); reg 2819 drivers/clk/tegra/clk-tegra210.c reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; reg 2820 drivers/clk/tegra/clk-tegra210.c writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); reg 2827 drivers/clk/tegra/clk-tegra210.c u32 reg; reg 2841 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); reg 2842 drivers/clk/tegra/clk-tegra210.c reg &= ~BIT(pllu.params->iddq_bit_idx); reg 2843 drivers/clk/tegra/clk-tegra210.c writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); reg 2846 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + PLLU_BASE); reg 2847 drivers/clk/tegra/clk-tegra210.c reg &= ~GENMASK(20, 0); reg 2848 drivers/clk/tegra/clk-tegra210.c reg |= fentry->m; reg 2849 drivers/clk/tegra/clk-tegra210.c reg |= fentry->n << 8; reg 2850 drivers/clk/tegra/clk-tegra210.c reg |= fentry->p << 16; reg 2851 drivers/clk/tegra/clk-tegra210.c writel(reg, clk_base + PLLU_BASE); reg 2853 drivers/clk/tegra/clk-tegra210.c reg |= PLL_ENABLE; reg 2854 drivers/clk/tegra/clk-tegra210.c writel(reg, clk_base + PLLU_BASE); reg 2856 drivers/clk/tegra/clk-tegra210.c readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg, reg 2857 drivers/clk/tegra/clk-tegra210.c reg & PLL_BASE_LOCK, 2, 1000); reg 2858 drivers/clk/tegra/clk-tegra210.c if (!(reg & PLL_BASE_LOCK)) { reg 2868 drivers/clk/tegra/clk-tegra210.c u32 reg; reg 2873 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + PLLU_BASE); reg 2874 drivers/clk/tegra/clk-tegra210.c if (reg & PLLU_BASE_OVERRIDE) { reg 2875 drivers/clk/tegra/clk-tegra210.c if (!(reg & PLL_ENABLE)) { reg 2883 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + PLLU_BASE); reg 2884 drivers/clk/tegra/clk-tegra210.c reg &= ~PLLU_BASE_OVERRIDE; reg 2885 drivers/clk/tegra/clk-tegra210.c writel(reg, clk_base + PLLU_BASE); reg 2887 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); reg 2888 drivers/clk/tegra/clk-tegra210.c reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE | reg 2891 drivers/clk/tegra/clk-tegra210.c reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL | reg 2893 drivers/clk/tegra/clk-tegra210.c writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); reg 2895 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); reg 2896 drivers/clk/tegra/clk-tegra210.c reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK; reg 2897 drivers/clk/tegra/clk-tegra210.c writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); reg 2900 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); reg 2901 drivers/clk/tegra/clk-tegra210.c reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE; reg 2902 drivers/clk/tegra/clk-tegra210.c writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); reg 2905 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + PLLU_BASE); reg 2906 drivers/clk/tegra/clk-tegra210.c reg &= ~PLLU_BASE_CLKENABLE_USB; reg 2907 drivers/clk/tegra/clk-tegra210.c writel_relaxed(reg, clk_base + PLLU_BASE); reg 2911 drivers/clk/tegra/clk-tegra210.c reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); reg 2912 drivers/clk/tegra/clk-tegra210.c if (!(reg & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE)) reg 3276 drivers/clk/tegra/clk-tegra210.c unsigned int reg; reg 3279 drivers/clk/tegra/clk-tegra210.c reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); reg 3281 drivers/clk/tegra/clk-tegra210.c } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ reg 1088 drivers/clk/tegra/clk-tegra30.c unsigned int reg; reg 1091 drivers/clk/tegra/clk-tegra30.c reg = readl(clk_base + reg 1094 drivers/clk/tegra/clk-tegra30.c } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ reg 1115 drivers/clk/tegra/clk-tegra30.c unsigned int reg; reg 1119 drivers/clk/tegra/clk-tegra30.c reg = readl(clk_base + reg 1125 drivers/clk/tegra/clk-tegra30.c unsigned int reg; reg 1127 drivers/clk/tegra/clk-tegra30.c reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); reg 1128 drivers/clk/tegra/clk-tegra30.c writel(reg | CPU_CLOCK(cpu), reg 1169 drivers/clk/tegra/clk-tegra30.c unsigned int reg, policy; reg 1172 drivers/clk/tegra/clk-tegra30.c reg = readl(clk_base + CLK_RESET_CCLK_BURST); reg 1173 drivers/clk/tegra/clk-tegra30.c policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF; reg 1176 drivers/clk/tegra/clk-tegra30.c reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF; reg 1178 drivers/clk/tegra/clk-tegra30.c reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF; reg 1182 drivers/clk/tegra/clk-tegra30.c if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) { reg 59 drivers/clk/tegra/clk.h void __iomem *reg; reg 76 drivers/clk/tegra/clk.h const char *parent_name, void __iomem *reg, reg 80 drivers/clk/tegra/clk.h void __iomem *reg, spinlock_t *lock); reg 443 drivers/clk/tegra/clk.h void __iomem *reg; reg 454 drivers/clk/tegra/clk.h const char *parent_name, void __iomem *reg, u8 enb_bit_idx, reg 675 drivers/clk/tegra/clk.h void __iomem *reg; reg 692 drivers/clk/tegra/clk.h unsigned long flags, void __iomem *reg, u8 clk_super_flags, reg 696 drivers/clk/tegra/clk.h unsigned long flags, void __iomem *reg, u8 clk_super_flags, reg 711 drivers/clk/tegra/clk.h void __iomem *reg; reg 835 drivers/clk/tegra/clk.h #define fence_udelay(delay, reg) \ reg 837 drivers/clk/tegra/clk.h readl(reg); \ reg 252 drivers/clk/ti/adpll.c void __iomem *reg, reg 266 drivers/clk/ti/adpll.c reg, shift, width, clk_divider_flags, reg 282 drivers/clk/ti/adpll.c void __iomem *reg, reg 295 drivers/clk/ti/adpll.c reg, shift, 1, 0, &d->lock); reg 310 drivers/clk/ti/adpll.c void __iomem *reg, reg 324 drivers/clk/ti/adpll.c reg, bit_idx, clk_gate_flags, reg 629 drivers/clk/ti/adpll.c co->gate.reg = d->regs + ADPLL_CLKCTRL_OFFSET; reg 792 drivers/clk/ti/adpll.c static void ti_adpll_unlock_all(void __iomem *reg) reg 796 drivers/clk/ti/adpll.c v = readl_relaxed(reg); reg 798 drivers/clk/ti/adpll.c writel_relaxed(ADPLL_PLLSS_MMR_UNLOCK_MAGIC, reg); reg 28 drivers/clk/ti/autoidle.c struct clk_omap_reg reg; reg 119 drivers/clk/ti/autoidle.c val = ti_clk_ll_ops->clk_readl(&clk->reg); reg 126 drivers/clk/ti/autoidle.c ti_clk_ll_ops->clk_writel(val, &clk->reg); reg 133 drivers/clk/ti/autoidle.c val = ti_clk_ll_ops->clk_readl(&clk->reg); reg 140 drivers/clk/ti/autoidle.c ti_clk_ll_ops->clk_writel(val, &clk->reg); reg 199 drivers/clk/ti/autoidle.c ret = ti_clk_get_reg_addr(node, 0, &clk->reg); reg 69 drivers/clk/ti/clk-dra7-atl.c static inline void atl_write(struct dra7_atl_clock_info *cinfo, u32 reg, reg 72 drivers/clk/ti/clk-dra7-atl.c __raw_writel(val, cinfo->iobase + reg); reg 75 drivers/clk/ti/clk-dra7-atl.c static inline int atl_read(struct dra7_atl_clock_info *cinfo, u32 reg) reg 77 drivers/clk/ti/clk-dra7-atl.c return __raw_readl(cinfo->iobase + reg); reg 48 drivers/clk/ti/clk.c static void clk_memmap_writel(u32 val, const struct clk_omap_reg *reg) reg 50 drivers/clk/ti/clk.c struct clk_iomap *io = clk_memmaps[reg->index]; reg 52 drivers/clk/ti/clk.c if (reg->ptr) reg 53 drivers/clk/ti/clk.c writel_relaxed(val, reg->ptr); reg 55 drivers/clk/ti/clk.c regmap_write(io->regmap, reg->offset, val); reg 57 drivers/clk/ti/clk.c writel_relaxed(val, io->mem + reg->offset); reg 70 drivers/clk/ti/clk.c static void clk_memmap_rmw(u32 val, u32 mask, const struct clk_omap_reg *reg) reg 72 drivers/clk/ti/clk.c struct clk_iomap *io = clk_memmaps[reg->index]; reg 74 drivers/clk/ti/clk.c if (reg->ptr) { reg 75 drivers/clk/ti/clk.c _clk_rmw(val, mask, reg->ptr); reg 77 drivers/clk/ti/clk.c regmap_update_bits(io->regmap, reg->offset, mask, val); reg 79 drivers/clk/ti/clk.c _clk_rmw(val, mask, io->mem + reg->offset); reg 83 drivers/clk/ti/clk.c static u32 clk_memmap_readl(const struct clk_omap_reg *reg) reg 86 drivers/clk/ti/clk.c struct clk_iomap *io = clk_memmaps[reg->index]; reg 88 drivers/clk/ti/clk.c if (reg->ptr) reg 89 drivers/clk/ti/clk.c val = readl_relaxed(reg->ptr); reg 91 drivers/clk/ti/clk.c regmap_read(io->regmap, reg->offset, &val); reg 93 drivers/clk/ti/clk.c val = readl_relaxed(io->mem + reg->offset); reg 264 drivers/clk/ti/clk.c struct clk_omap_reg *reg) reg 279 drivers/clk/ti/clk.c reg->index = i; reg 286 drivers/clk/ti/clk.c reg->offset = val; reg 287 drivers/clk/ti/clk.c reg->ptr = NULL; reg 292 drivers/clk/ti/clk.c void ti_clk_latch(struct clk_omap_reg *reg, s8 shift) reg 301 drivers/clk/ti/clk.c ti_clk_ll_ops->clk_rmw(latch, latch, reg); reg 302 drivers/clk/ti/clk.c ti_clk_ll_ops->clk_rmw(0, latch, reg); reg 303 drivers/clk/ti/clk.c ti_clk_ll_ops->clk_readl(reg); /* OCP barrier */ reg 309 drivers/clk/ti/clkctrl.c void __iomem *reg) reg 318 drivers/clk/ti/clkctrl.c clk_hw->enable_reg.ptr = reg; reg 330 drivers/clk/ti/clkctrl.c void __iomem *reg) reg 353 drivers/clk/ti/clkctrl.c mux->reg.ptr = reg; reg 365 drivers/clk/ti/clkctrl.c void __iomem *reg) reg 375 drivers/clk/ti/clkctrl.c div->reg.ptr = reg; reg 401 drivers/clk/ti/clkctrl.c void __iomem *reg) reg 412 drivers/clk/ti/clkctrl.c bits, reg); reg 417 drivers/clk/ti/clkctrl.c bits, reg); reg 422 drivers/clk/ti/clkctrl.c bits, reg); reg 59 drivers/clk/ti/clkt_dflt.c struct clk_omap_reg *reg, reg 68 drivers/clk/ti/clkt_dflt.c if ((ti_clk_ll_ops->clk_readl(reg) & mask) == ena) reg 21 drivers/clk/ti/clock.h struct clk_omap_reg reg; reg 34 drivers/clk/ti/clock.h struct clk_omap_reg reg; reg 114 drivers/clk/ti/clock.h u16 reg; reg 124 drivers/clk/ti/clock.h u16 reg; reg 134 drivers/clk/ti/clock.h u16 reg; reg 218 drivers/clk/ti/clock.h void ti_clk_latch(struct clk_omap_reg *reg, s8 shift); reg 227 drivers/clk/ti/clock.h struct clk_omap_reg *reg); reg 103 drivers/clk/ti/divider.c val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift; reg 260 drivers/clk/ti/divider.c val = ti_clk_ll_ops->clk_readl(÷r->reg); reg 264 drivers/clk/ti/divider.c ti_clk_ll_ops->clk_writel(val, ÷r->reg); reg 266 drivers/clk/ti/divider.c ti_clk_latch(÷r->reg, divider->latch); reg 282 drivers/clk/ti/divider.c val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift; reg 299 drivers/clk/ti/divider.c val = ti_clk_ll_ops->clk_readl(÷r->reg); reg 302 drivers/clk/ti/divider.c ti_clk_ll_ops->clk_writel(val, ÷r->reg); reg 316 drivers/clk/ti/divider.c struct clk_omap_reg *reg, reg 344 drivers/clk/ti/divider.c memcpy(&div->reg, reg, sizeof(*reg)); reg 523 drivers/clk/ti/divider.c struct clk_omap_reg *reg, const struct clk_div_table **table, reg 529 drivers/clk/ti/divider.c ret = ti_clk_get_reg_addr(node, 0, reg); reg 577 drivers/clk/ti/divider.c struct clk_omap_reg reg; reg 587 drivers/clk/ti/divider.c if (ti_clk_divider_populate(node, ®, &table, &flags, reg 591 drivers/clk/ti/divider.c clk = _register_divider(NULL, node->name, parent_name, flags, ®, reg 614 drivers/clk/ti/divider.c if (ti_clk_divider_populate(node, &div->reg, &div->table, &val, reg 82 drivers/clk/ti/gate.c orig_v = ti_clk_ll_ops->clk_readl(&parent->reg); reg 87 drivers/clk/ti/gate.c ti_clk_ll_ops->clk_writel(dummy_v, &parent->reg); reg 90 drivers/clk/ti/gate.c ti_clk_ll_ops->clk_writel(orig_v, &parent->reg); reg 98 drivers/clk/ti/gate.c struct clk_omap_reg *reg, u8 bit_idx, reg 115 drivers/clk/ti/gate.c memcpy(&clk_hw->enable_reg, reg, sizeof(*reg)); reg 140 drivers/clk/ti/gate.c struct clk_omap_reg reg; reg 147 drivers/clk/ti/gate.c if (ti_clk_get_reg_addr(node, 0, ®)) reg 167 drivers/clk/ti/gate.c clk = _register_gate(NULL, node->name, parent_name, flags, ®, reg 37 drivers/clk/ti/interface.c struct clk_omap_reg *reg, u8 bit_idx, reg 50 drivers/clk/ti/interface.c memcpy(&clk_hw->enable_reg, reg, sizeof(*reg)); reg 73 drivers/clk/ti/interface.c struct clk_omap_reg reg; reg 77 drivers/clk/ti/interface.c if (ti_clk_get_reg_addr(node, 0, ®)) reg 89 drivers/clk/ti/interface.c clk = _register_interface(NULL, node->name, parent_name, ®, reg 42 drivers/clk/ti/mux.c val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift; reg 84 drivers/clk/ti/mux.c val = ti_clk_ll_ops->clk_readl(&mux->reg); reg 88 drivers/clk/ti/mux.c ti_clk_ll_ops->clk_writel(val, &mux->reg); reg 89 drivers/clk/ti/mux.c ti_clk_latch(&mux->reg, mux->latch); reg 132 drivers/clk/ti/mux.c struct clk_omap_reg *reg, u8 shift, u32 mask, reg 151 drivers/clk/ti/mux.c memcpy(&mux->reg, reg, sizeof(*reg)); reg 176 drivers/clk/ti/mux.c struct clk_omap_reg reg; reg 196 drivers/clk/ti/mux.c if (ti_clk_get_reg_addr(node, 0, ®)) reg 217 drivers/clk/ti/mux.c flags, ®, shift, mask, latch, clk_mux_flags, reg 243 drivers/clk/ti/mux.c mux->reg.index = setup->module; reg 244 drivers/clk/ti/mux.c mux->reg.offset = setup->reg; reg 267 drivers/clk/ti/mux.c if (ti_clk_get_reg_addr(node, 0, &mux->reg)) reg 16 drivers/clk/uniphier/clk-uniphier-gate.c unsigned int reg; reg 27 drivers/clk/uniphier/clk-uniphier-gate.c return regmap_write_bits(gate->regmap, gate->reg, BIT(gate->bit), reg 47 drivers/clk/uniphier/clk-uniphier-gate.c if (regmap_read(gate->regmap, gate->reg, &val) < 0) reg 79 drivers/clk/uniphier/clk-uniphier-gate.c gate->reg = data->reg; reg 38 drivers/clk/uniphier/clk-uniphier-mio.c .reg = 0x30 + 0x200 * (ch), \ reg 16 drivers/clk/uniphier/clk-uniphier-mux.c unsigned int reg; reg 27 drivers/clk/uniphier/clk-uniphier-mux.c return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index], reg 39 drivers/clk/uniphier/clk-uniphier-mux.c ret = regmap_read(mux->regmap, mux->reg, &val); reg 76 drivers/clk/uniphier/clk-uniphier-mux.c mux->reg = data->reg; reg 44 drivers/clk/uniphier/clk-uniphier.h unsigned int reg; reg 51 drivers/clk/uniphier/clk-uniphier.h unsigned int reg; reg 102 drivers/clk/uniphier/clk-uniphier.h .reg = (_reg), \ reg 16 drivers/clk/versatile/clk-vexpress-osc.c struct regmap *reg; reg 30 drivers/clk/versatile/clk-vexpress-osc.c regmap_read(osc->reg, 0, &rate); reg 54 drivers/clk/versatile/clk-vexpress-osc.c return regmap_write(osc->reg, 0, rate); reg 75 drivers/clk/versatile/clk-vexpress-osc.c osc->reg = devm_regmap_init_vexpress_config(&pdev->dev); reg 76 drivers/clk/versatile/clk-vexpress-osc.c if (IS_ERR(osc->reg)) reg 77 drivers/clk/versatile/clk-vexpress-osc.c return PTR_ERR(osc->reg); reg 38 drivers/clk/x86/clk-pmc-atom.c void __iomem *reg; reg 55 drivers/clk/x86/clk-pmc-atom.c static inline int plt_reg_to_parent(int reg) reg 57 drivers/clk/x86/clk-pmc-atom.c switch (reg & PMC_MASK_CLK_FREQ) { reg 79 drivers/clk/x86/clk-pmc-atom.c static inline int plt_reg_to_enabled(int reg) reg 81 drivers/clk/x86/clk-pmc-atom.c switch (reg & PMC_MASK_CLK_CTL) { reg 99 drivers/clk/x86/clk-pmc-atom.c tmp = readl(clk->reg); reg 101 drivers/clk/x86/clk-pmc-atom.c writel(tmp, clk->reg); reg 120 drivers/clk/x86/clk-pmc-atom.c value = readl(clk->reg); reg 146 drivers/clk/x86/clk-pmc-atom.c value = readl(clk->reg); reg 180 drivers/clk/x86/clk-pmc-atom.c pclk->reg = pmc_data->base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE; reg 197 drivers/clk/zte/clk-zx296702.c void __iomem *reg, u8 shift, u8 width, reg 200 drivers/clk/zte/clk-zx296702.c return clk_register_divider_table(NULL, name, parent, 0, reg, shift, reg 205 drivers/clk/zte/clk-zx296702.c void __iomem *reg, u8 shift, u8 width) reg 208 drivers/clk/zte/clk-zx296702.c reg, shift, width, 0, ®_lock); reg 212 drivers/clk/zte/clk-zx296702.c int num_parents, void __iomem *reg, u8 shift, u8 width) reg 215 drivers/clk/zte/clk-zx296702.c 0, reg, shift, width, 0, ®_lock); reg 219 drivers/clk/zte/clk-zx296702.c void __iomem *reg, u8 shift) reg 222 drivers/clk/zte/clk-zx296702.c reg, shift, CLK_SET_RATE_PARENT, ®_lock); reg 599 drivers/clk/zte/clk-zx296718.c top_mux_clk[i].mux.reg += (uintptr_t)reg_base; reg 611 drivers/clk/zte/clk-zx296718.c top_gate_clk[i].gate.reg += (uintptr_t)reg_base; reg 623 drivers/clk/zte/clk-zx296718.c top_div_clk[i].div.reg += (uintptr_t)reg_base; reg 766 drivers/clk/zte/clk-zx296718.c lsp0_mux_clk[i].mux.reg += (uintptr_t)reg_base; reg 778 drivers/clk/zte/clk-zx296718.c lsp0_gate_clk[i].gate.reg += (uintptr_t)reg_base; reg 790 drivers/clk/zte/clk-zx296718.c lsp0_div_clk[i].div.reg += (uintptr_t)reg_base; reg 872 drivers/clk/zte/clk-zx296718.c lsp1_mux_clk[i].mux.reg += (uintptr_t)reg_base; reg 884 drivers/clk/zte/clk-zx296718.c lsp1_gate_clk[i].gate.reg += (uintptr_t)reg_base; reg 896 drivers/clk/zte/clk-zx296718.c lsp1_div_clk[i].div.reg += (uintptr_t)reg_base; reg 987 drivers/clk/zte/clk-zx296718.c audio_mux_clk[i].mux.reg += (uintptr_t)reg_base; reg 1011 drivers/clk/zte/clk-zx296718.c audio_div_clk[i].div.reg += (uintptr_t)reg_base; reg 1023 drivers/clk/zte/clk-zx296718.c audio_gate_clk[i].gate.reg += (uintptr_t)reg_base; reg 109 drivers/clk/zte/clk.c u32 reg; reg 115 drivers/clk/zte/clk.c reg = readl_relaxed(zx_pll->reg_base); reg 116 drivers/clk/zte/clk.c writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base); reg 118 drivers/clk/zte/clk.c return readl_relaxed_poll_timeout(zx_pll->reg_base, reg, reg 119 drivers/clk/zte/clk.c reg & BIT(zx_pll->lock_bit), 0, 100); reg 125 drivers/clk/zte/clk.c u32 reg; reg 130 drivers/clk/zte/clk.c reg = readl_relaxed(zx_pll->reg_base); reg 131 drivers/clk/zte/clk.c writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base); reg 137 drivers/clk/zte/clk.c u32 reg; reg 139 drivers/clk/zte/clk.c reg = readl_relaxed(zx_pll->reg_base); reg 141 drivers/clk/zte/clk.c return !(reg & BIT(zx_pll->pd_bit)); reg 212 drivers/clk/zte/clk.c static u32 calc_rate(u32 reg, u32 parent_rate) reg 217 drivers/clk/zte/clk.c tmp = reg; reg 235 drivers/clk/zte/clk.c u32 reg; reg 237 drivers/clk/zte/clk.c reg = readl_relaxed(zx_audio->reg_base); reg 238 drivers/clk/zte/clk.c return calc_rate(reg, parent_rate); reg 244 drivers/clk/zte/clk.c u32 reg; reg 249 drivers/clk/zte/clk.c reg = calc_reg(*prate, rate); reg 250 drivers/clk/zte/clk.c return calc_rate(reg, *prate); reg 257 drivers/clk/zte/clk.c u32 reg; reg 259 drivers/clk/zte/clk.c reg = calc_reg(parent_rate, rate); reg 260 drivers/clk/zte/clk.c writel_relaxed(reg, zx_audio->reg_base); reg 269 drivers/clk/zte/clk.c u32 reg; reg 271 drivers/clk/zte/clk.c reg = readl_relaxed(zx_audio->reg_base); reg 272 drivers/clk/zte/clk.c writel_relaxed(reg & ~ZX_AUDIO_EN, zx_audio->reg_base); reg 279 drivers/clk/zte/clk.c u32 reg; reg 281 drivers/clk/zte/clk.c reg = readl_relaxed(zx_audio->reg_base); reg 282 drivers/clk/zte/clk.c writel_relaxed(reg | ZX_AUDIO_EN, zx_audio->reg_base); reg 63 drivers/clk/zte/clk.h .reg = (void __iomem *) _reg, \ reg 101 drivers/clk/zte/clk.h .reg = (void __iomem *) _reg, \ reg 125 drivers/clk/zte/clk.h .reg = (void __iomem *) _reg, \ reg 98 drivers/clk/zynq/pll.c u32 reg; reg 103 drivers/clk/zynq/pll.c reg = readl(clk->pll_ctrl); reg 107 drivers/clk/zynq/pll.c return !(reg & (PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK)); reg 118 drivers/clk/zynq/pll.c u32 reg; reg 129 drivers/clk/zynq/pll.c reg = readl(clk->pll_ctrl); reg 130 drivers/clk/zynq/pll.c reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK); reg 131 drivers/clk/zynq/pll.c writel(reg, clk->pll_ctrl); reg 148 drivers/clk/zynq/pll.c u32 reg; reg 159 drivers/clk/zynq/pll.c reg = readl(clk->pll_ctrl); reg 160 drivers/clk/zynq/pll.c reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK; reg 161 drivers/clk/zynq/pll.c writel(reg, clk->pll_ctrl); reg 190 drivers/clk/zynq/pll.c u32 reg; reg 214 drivers/clk/zynq/pll.c reg = readl(pll->pll_ctrl); reg 215 drivers/clk/zynq/pll.c reg &= ~PLLCTRL_BPQUAL_MASK; reg 216 drivers/clk/zynq/pll.c writel(reg, pll->pll_ctrl); reg 88 drivers/clocksource/arm_arch_timer.c void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val, reg 93 drivers/clocksource/arm_arch_timer.c switch (reg) { reg 103 drivers/clocksource/arm_arch_timer.c switch (reg) { reg 112 drivers/clocksource/arm_arch_timer.c arch_timer_reg_write_cp15(access, reg, val); reg 117 drivers/clocksource/arm_arch_timer.c u32 arch_timer_reg_read(int access, enum arch_timer_reg reg, reg 124 drivers/clocksource/arm_arch_timer.c switch (reg) { reg 134 drivers/clocksource/arm_arch_timer.c switch (reg) { reg 143 drivers/clocksource/arm_arch_timer.c val = arch_timer_reg_read_cp15(access, reg); reg 212 drivers/clocksource/arm_arch_timer.c #define __fsl_a008585_read_reg(reg) ({ \ reg 217 drivers/clocksource/arm_arch_timer.c _old = read_sysreg(reg); \ reg 218 drivers/clocksource/arm_arch_timer.c _new = read_sysreg(reg); \ reg 258 drivers/clocksource/arm_arch_timer.c #define __hisi_161010101_read_reg(reg) ({ \ reg 263 drivers/clocksource/arm_arch_timer.c _old = read_sysreg(reg); \ reg 264 drivers/clocksource/arm_arch_timer.c _new = read_sysreg(reg); \ reg 344 drivers/clocksource/arm_arch_timer.c #define __sun50i_a64_read_reg(reg) ({ \ reg 349 drivers/clocksource/arm_arch_timer.c _val = read_sysreg(reg); \ reg 52 drivers/clocksource/bcm_kona_timer.c uint32_t reg; reg 58 drivers/clocksource/bcm_kona_timer.c reg = readl(base + KONA_GPTIMER_STCS_OFFSET); reg 61 drivers/clocksource/bcm_kona_timer.c reg |= 1 << KONA_GPTIMER_STCS_TIMER_MATCH_SHIFT; reg 63 drivers/clocksource/bcm_kona_timer.c reg &= ~(1 << KONA_GPTIMER_STCS_COMPARE_ENABLE_SHIFT); reg 65 drivers/clocksource/bcm_kona_timer.c writel(reg, base + KONA_GPTIMER_STCS_OFFSET); reg 115 drivers/clocksource/bcm_kona_timer.c uint32_t reg; reg 126 drivers/clocksource/bcm_kona_timer.c reg = readl(timers.tmr_regs + KONA_GPTIMER_STCS_OFFSET); reg 127 drivers/clocksource/bcm_kona_timer.c reg |= (1 << KONA_GPTIMER_STCS_COMPARE_ENABLE_SHIFT); reg 128 drivers/clocksource/bcm_kona_timer.c writel(reg, timers.tmr_regs + KONA_GPTIMER_STCS_OFFSET); reg 153 drivers/clocksource/exynos_mct.c u32 reg; reg 155 drivers/clocksource/exynos_mct.c reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); reg 156 drivers/clocksource/exynos_mct.c reg |= MCT_G_TCON_START; reg 157 drivers/clocksource/exynos_mct.c exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); reg 11 drivers/clocksource/mmio.c void __iomem *reg; reg 22 drivers/clocksource/mmio.c return (u64)readl_relaxed(to_mmio_clksrc(c)->reg); reg 27 drivers/clocksource/mmio.c return ~(u64)readl_relaxed(to_mmio_clksrc(c)->reg) & c->mask; reg 32 drivers/clocksource/mmio.c return (u64)readw_relaxed(to_mmio_clksrc(c)->reg); reg 37 drivers/clocksource/mmio.c return ~(u64)readw_relaxed(to_mmio_clksrc(c)->reg) & c->mask; reg 62 drivers/clocksource/mmio.c cs->reg = base; reg 32 drivers/clocksource/mps2-timer.c void __iomem *reg; reg 51 drivers/clocksource/mps2-timer.c writel_relaxed(val, to_mps2_clkevt(c)->reg + offset); reg 84 drivers/clocksource/mps2-timer.c u32 status = readl_relaxed(ce->reg + TIMER_INT); reg 91 drivers/clocksource/mps2-timer.c writel_relaxed(1, ce->reg + TIMER_INT); reg 145 drivers/clocksource/mps2-timer.c ce->reg = base; reg 86 drivers/clocksource/samsung_pwm_timer.c u32 reg; reg 93 drivers/clocksource/samsung_pwm_timer.c reg = readl(pwm.base + REG_TCFG0); reg 94 drivers/clocksource/samsung_pwm_timer.c reg &= ~(TCFG0_PRESCALER_MASK << shift); reg 95 drivers/clocksource/samsung_pwm_timer.c reg |= (prescale - 1) << shift; reg 96 drivers/clocksource/samsung_pwm_timer.c writel(reg, pwm.base + REG_TCFG0); reg 105 drivers/clocksource/samsung_pwm_timer.c u32 reg; reg 112 drivers/clocksource/samsung_pwm_timer.c reg = readl(pwm.base + REG_TCFG1); reg 113 drivers/clocksource/samsung_pwm_timer.c reg &= ~(TCFG1_MUX_MASK << shift); reg 114 drivers/clocksource/samsung_pwm_timer.c reg |= bits << shift; reg 115 drivers/clocksource/samsung_pwm_timer.c writel(reg, pwm.base + REG_TCFG1); reg 75 drivers/clocksource/timer-davinci.c unsigned int reg) reg 77 drivers/clocksource/timer-davinci.c return readl_relaxed(clockevent->base + reg); reg 81 drivers/clocksource/timer-davinci.c unsigned int reg, unsigned int val) reg 83 drivers/clocksource/timer-davinci.c writel_relaxed(val, clockevent->base + reg); reg 257 drivers/clocksource/timer-davinci.c if (!request_mem_region(timer_cfg->reg.start, reg 258 drivers/clocksource/timer-davinci.c resource_size(&timer_cfg->reg), reg 264 drivers/clocksource/timer-davinci.c base = ioremap(timer_cfg->reg.start, resource_size(&timer_cfg->reg)); reg 344 drivers/clocksource/timer-davinci.c rv = of_address_to_resource(np, 0, &timer_cfg.reg); reg 156 drivers/clocksource/timer-imx-gpt.c void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn; reg 164 drivers/clocksource/timer-imx-gpt.c sched_clock_reg = reg; reg 167 drivers/clocksource/timer-imx-gpt.c return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32, reg 52 drivers/clocksource/timer-pxa.c #define timer_readl(reg) readl_relaxed(timer_base + (reg)) reg 53 drivers/clocksource/timer-pxa.c #define timer_writel(val, reg) writel_relaxed((val), timer_base + (reg)) reg 72 drivers/clocksource/timer-ti-dm.c static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) reg 74 drivers/clocksource/timer-ti-dm.c WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); reg 75 drivers/clocksource/timer-ti-dm.c return __omap_dm_timer_read(timer, reg, timer->posted); reg 88 drivers/clocksource/timer-ti-dm.c static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, reg 91 drivers/clocksource/timer-ti-dm.c WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); reg 92 drivers/clocksource/timer-ti-dm.c __omap_dm_timer_write(timer, reg, value, timer->posted); reg 56 drivers/cpufreq/acpi-cpufreq.c void (*cpu_freq_write)(struct acpi_pct_register *reg, u32 val); reg 57 drivers/cpufreq/acpi-cpufreq.c u32 (*cpu_freq_read)(struct acpi_pct_register *reg); reg 272 drivers/cpufreq/acpi-cpufreq.c static u32 cpu_freq_read_io(struct acpi_pct_register *reg) reg 276 drivers/cpufreq/acpi-cpufreq.c acpi_os_read_port(reg->address, &val, reg->bit_width); reg 280 drivers/cpufreq/acpi-cpufreq.c static void cpu_freq_write_io(struct acpi_pct_register *reg, u32 val) reg 282 drivers/cpufreq/acpi-cpufreq.c acpi_os_write_port(reg->address, val, reg->bit_width); reg 286 drivers/cpufreq/acpi-cpufreq.c struct acpi_pct_register *reg; reg 289 drivers/cpufreq/acpi-cpufreq.c void (*write)(struct acpi_pct_register *reg, u32 val); reg 290 drivers/cpufreq/acpi-cpufreq.c u32 (*read)(struct acpi_pct_register *reg); reg 299 drivers/cpufreq/acpi-cpufreq.c cmd->val = cmd->func.read(cmd->reg); reg 306 drivers/cpufreq/acpi-cpufreq.c .reg = &perf->control_register, reg 321 drivers/cpufreq/acpi-cpufreq.c cmd->func.write(cmd->reg, cmd->val); reg 329 drivers/cpufreq/acpi-cpufreq.c .reg = &perf->control_register, reg 129 drivers/cpufreq/armada-37xx-cpufreq.c unsigned int reg, mask, val, offset = 0; reg 132 drivers/cpufreq/armada-37xx-cpufreq.c reg = ARMADA_37XX_NB_L0L1; reg 134 drivers/cpufreq/armada-37xx-cpufreq.c reg = ARMADA_37XX_NB_L2L3; reg 161 drivers/cpufreq/armada-37xx-cpufreq.c regmap_update_bits(base, reg, mask, val); reg 295 drivers/cpufreq/armada-37xx-cpufreq.c unsigned int reg = ARMADA_37XX_NB_DYN_MOD, reg 298 drivers/cpufreq/armada-37xx-cpufreq.c regmap_update_bits(base, reg, mask, 0); reg 303 drivers/cpufreq/armada-37xx-cpufreq.c unsigned int val, reg = ARMADA_37XX_NB_CPU_LOAD, reg 308 drivers/cpufreq/armada-37xx-cpufreq.c regmap_update_bits(base, reg, mask, val); reg 311 drivers/cpufreq/armada-37xx-cpufreq.c reg = ARMADA_37XX_NB_DYN_MOD; reg 316 drivers/cpufreq/armada-37xx-cpufreq.c regmap_update_bits(base, reg, mask, mask); reg 173 drivers/cpufreq/gx-suspmod.c static void gx_write_byte(int reg, int value) reg 175 drivers/cpufreq/gx-suspmod.c pci_write_config_byte(gx_params->cs55x0, reg, value); reg 54 drivers/cpufreq/kirkwood-cpufreq.c unsigned long reg; reg 59 drivers/cpufreq/kirkwood-cpufreq.c reg = readl_relaxed(priv.base); reg 60 drivers/cpufreq/kirkwood-cpufreq.c reg |= CPU_SW_INT_BLK; reg 61 drivers/cpufreq/kirkwood-cpufreq.c writel_relaxed(reg, priv.base); reg 76 drivers/cpufreq/kirkwood-cpufreq.c reg = readl_relaxed(priv.base); reg 77 drivers/cpufreq/kirkwood-cpufreq.c reg &= ~CPU_SW_INT_BLK; reg 78 drivers/cpufreq/kirkwood-cpufreq.c writel_relaxed(reg, priv.base); reg 686 drivers/cpufreq/longhaul.c int reg; reg 690 drivers/cpufreq/longhaul.c reg = 0x78; reg 699 drivers/cpufreq/longhaul.c reg = 0x76; reg 708 drivers/cpufreq/longhaul.c pci_read_config_byte(dev, reg, &pci_cmd); reg 711 drivers/cpufreq/longhaul.c pci_write_config_byte(dev, reg, pci_cmd); reg 712 drivers/cpufreq/longhaul.c pci_read_config_byte(dev, reg, &pci_cmd); reg 381 drivers/cpufreq/pmac32-cpufreq.c const u32 *reg = of_get_property(np, "reg", NULL); reg 384 drivers/cpufreq/pmac32-cpufreq.c if (reg == NULL) reg 392 drivers/cpufreq/pmac32-cpufreq.c offset = *reg; reg 200 drivers/cpufreq/s5pv210-cpufreq.c void __iomem *reg = NULL; reg 203 drivers/cpufreq/s5pv210-cpufreq.c reg = (dmc_base[0] + 0x30); reg 205 drivers/cpufreq/s5pv210-cpufreq.c reg = (dmc_base[1] + 0x30); reg 220 drivers/cpufreq/s5pv210-cpufreq.c writel_relaxed(tmp1, reg); reg 225 drivers/cpufreq/s5pv210-cpufreq.c unsigned long reg; reg 296 drivers/cpufreq/s5pv210-cpufreq.c reg = readl_relaxed(S5P_CLK_DIV2); reg 297 drivers/cpufreq/s5pv210-cpufreq.c reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK); reg 298 drivers/cpufreq/s5pv210-cpufreq.c reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) | reg 300 drivers/cpufreq/s5pv210-cpufreq.c writel_relaxed(reg, S5P_CLK_DIV2); reg 304 drivers/cpufreq/s5pv210-cpufreq.c reg = readl_relaxed(S5P_CLKDIV_STAT0); reg 305 drivers/cpufreq/s5pv210-cpufreq.c } while (reg & ((1 << 16) | (1 << 17))); reg 311 drivers/cpufreq/s5pv210-cpufreq.c reg = readl_relaxed(S5P_CLK_SRC2); reg 312 drivers/cpufreq/s5pv210-cpufreq.c reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK); reg 313 drivers/cpufreq/s5pv210-cpufreq.c reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) | reg 315 drivers/cpufreq/s5pv210-cpufreq.c writel_relaxed(reg, S5P_CLK_SRC2); reg 318 drivers/cpufreq/s5pv210-cpufreq.c reg = readl_relaxed(S5P_CLKMUX_STAT1); reg 319 drivers/cpufreq/s5pv210-cpufreq.c } while (reg & ((1 << 7) | (1 << 3))); reg 330 drivers/cpufreq/s5pv210-cpufreq.c reg = readl_relaxed(S5P_CLK_SRC0); reg 331 drivers/cpufreq/s5pv210-cpufreq.c reg &= ~(S5P_CLKSRC0_MUX200_MASK); reg 332 drivers/cpufreq/s5pv210-cpufreq.c reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT); reg 333 drivers/cpufreq/s5pv210-cpufreq.c writel_relaxed(reg, S5P_CLK_SRC0); reg 336 drivers/cpufreq/s5pv210-cpufreq.c reg = readl_relaxed(S5P_CLKMUX_STAT0); reg 337 drivers/cpufreq/s5pv210-cpufreq.c } while (reg & (0x1 << 18)); reg 342 drivers/cpufreq/s5pv210-cpufreq.c reg = readl_relaxed(S5P_CLK_DIV0); reg 344 drivers/cpufreq/s5pv210-cpufreq.c reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK | reg 349 drivers/cpufreq/s5pv210-cpufreq.c reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) | reg 358 drivers/cpufreq/s5pv210-cpufreq.c writel_relaxed(reg, S5P_CLK_DIV0); reg 361 drivers/cpufreq/s5pv210-cpufreq.c reg = readl_relaxed(S5P_CLKDIV_STAT0); reg 362 drivers/cpufreq/s5pv210-cpufreq.c } while (reg & 0xff); reg 365 drivers/cpufreq/s5pv210-cpufreq.c reg = readl_relaxed(S5P_ARM_MCS_CON); reg 366 drivers/cpufreq/s5pv210-cpufreq.c reg &= ~0x3; reg 368 drivers/cpufreq/s5pv210-cpufreq.c reg |= 0x3; reg 370 drivers/cpufreq/s5pv210-cpufreq.c reg |= 0x1; reg 372 drivers/cpufreq/s5pv210-cpufreq.c writel_relaxed(reg, S5P_ARM_MCS_CON); reg 389 drivers/cpufreq/s5pv210-cpufreq.c reg = readl_relaxed(S5P_APLL_CON); reg 390 drivers/cpufreq/s5pv210-cpufreq.c } while (!(reg & (0x1 << 29))); reg 397 drivers/cpufreq/s5pv210-cpufreq.c reg = readl_relaxed(S5P_CLK_SRC2); reg 398 drivers/cpufreq/s5pv210-cpufreq.c reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK); reg 399 drivers/cpufreq/s5pv210-cpufreq.c reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) | reg 401 drivers/cpufreq/s5pv210-cpufreq.c writel_relaxed(reg, S5P_CLK_SRC2); reg 404 drivers/cpufreq/s5pv210-cpufreq.c reg = readl_relaxed(S5P_CLKMUX_STAT1); reg 405 drivers/cpufreq/s5pv210-cpufreq.c } while (reg & ((1 << 7) | (1 << 3))); reg 411 drivers/cpufreq/s5pv210-cpufreq.c reg = readl_relaxed(S5P_CLK_DIV2); reg 412 drivers/cpufreq/s5pv210-cpufreq.c reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK); reg 413 drivers/cpufreq/s5pv210-cpufreq.c reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) | reg 415 drivers/cpufreq/s5pv210-cpufreq.c writel_relaxed(reg, S5P_CLK_DIV2); reg 419 drivers/cpufreq/s5pv210-cpufreq.c reg = readl_relaxed(S5P_CLKDIV_STAT0); reg 420 drivers/cpufreq/s5pv210-cpufreq.c } while (reg & ((1 << 16) | (1 << 17))); reg 423 drivers/cpufreq/s5pv210-cpufreq.c reg = readl_relaxed(S5P_CLK_SRC0); reg 424 drivers/cpufreq/s5pv210-cpufreq.c reg &= ~(S5P_CLKSRC0_MUX200_MASK); reg 425 drivers/cpufreq/s5pv210-cpufreq.c reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT); reg 426 drivers/cpufreq/s5pv210-cpufreq.c writel_relaxed(reg, S5P_CLK_SRC0); reg 429 drivers/cpufreq/s5pv210-cpufreq.c reg = readl_relaxed(S5P_CLKMUX_STAT0); reg 430 drivers/cpufreq/s5pv210-cpufreq.c } while (reg & (0x1 << 18)); reg 446 drivers/cpufreq/s5pv210-cpufreq.c reg = readl_relaxed(S5P_CLK_DIV6); reg 447 drivers/cpufreq/s5pv210-cpufreq.c reg &= ~S5P_CLKDIV6_ONEDRAM_MASK; reg 448 drivers/cpufreq/s5pv210-cpufreq.c reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT); reg 449 drivers/cpufreq/s5pv210-cpufreq.c writel_relaxed(reg, S5P_CLK_DIV6); reg 452 drivers/cpufreq/s5pv210-cpufreq.c reg = readl_relaxed(S5P_CLKDIV_STAT1); reg 453 drivers/cpufreq/s5pv210-cpufreq.c } while (reg & (1 << 15)); reg 51 drivers/cpufreq/sparc-us3-cpufreq.c unsigned long reg, *new_bits = arg; reg 53 drivers/cpufreq/sparc-us3-cpufreq.c read_safari_cfg(®); reg 54 drivers/cpufreq/sparc-us3-cpufreq.c reg &= ~SAFARI_CFG_DIV_MASK; reg 55 drivers/cpufreq/sparc-us3-cpufreq.c reg |= *new_bits; reg 60 drivers/cpufreq/sparc-us3-cpufreq.c : "r" (reg), "i" (ASI_SAFARI_CONFIG) reg 88 drivers/cpufreq/sparc-us3-cpufreq.c unsigned long reg; reg 90 drivers/cpufreq/sparc-us3-cpufreq.c if (smp_call_function_single(cpu, read_safari_cfg, ®, 1)) reg 92 drivers/cpufreq/sparc-us3-cpufreq.c return get_current_freq(cpu, reg); reg 117 drivers/cpufreq/sti-cpufreq.c reg_field.reg = hw_info_offset; reg 2441 drivers/crypto/atmel-aes.c u32 reg; reg 2443 drivers/crypto/atmel-aes.c reg = atmel_aes_read(aes_dd, AES_ISR); reg 2444 drivers/crypto/atmel-aes.c if (reg & atmel_aes_read(aes_dd, AES_IMR)) { reg 2445 drivers/crypto/atmel-aes.c atmel_aes_write(aes_dd, AES_IDR, reg); reg 1432 drivers/crypto/atmel-sha.c u32 reg; reg 1434 drivers/crypto/atmel-sha.c reg = atmel_sha_read(sha_dd, SHA_ISR); reg 1435 drivers/crypto/atmel-sha.c if (reg & atmel_sha_read(sha_dd, SHA_IMR)) { reg 1436 drivers/crypto/atmel-sha.c atmel_sha_write(sha_dd, SHA_IDR, reg); reg 1131 drivers/crypto/atmel-tdes.c u32 reg; reg 1133 drivers/crypto/atmel-tdes.c reg = atmel_tdes_read(tdes_dd, TDES_ISR); reg 1134 drivers/crypto/atmel-tdes.c if (reg & atmel_tdes_read(tdes_dd, TDES_IMR)) { reg 1135 drivers/crypto/atmel-tdes.c atmel_tdes_write(tdes_dd, TDES_IDR, reg); reg 101 drivers/crypto/caam/regs.h static inline void wr_reg32(void __iomem *reg, u32 data) reg 104 drivers/crypto/caam/regs.h iowrite32(data, reg); reg 106 drivers/crypto/caam/regs.h iowrite32be(data, reg); reg 109 drivers/crypto/caam/regs.h static inline u32 rd_reg32(void __iomem *reg) reg 112 drivers/crypto/caam/regs.h return ioread32(reg); reg 114 drivers/crypto/caam/regs.h return ioread32be(reg); reg 117 drivers/crypto/caam/regs.h static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set) reg 120 drivers/crypto/caam/regs.h iowrite32((ioread32(reg) & ~clear) | set, reg); reg 122 drivers/crypto/caam/regs.h iowrite32be((ioread32be(reg) & ~clear) | set, reg); reg 142 drivers/crypto/caam/regs.h static inline void wr_reg64(void __iomem *reg, u64 data) reg 146 drivers/crypto/caam/regs.h iowrite32(data >> 32, (u32 __iomem *)(reg)); reg 147 drivers/crypto/caam/regs.h iowrite32(data, (u32 __iomem *)(reg) + 1); reg 149 drivers/crypto/caam/regs.h iowrite64(data, reg); reg 152 drivers/crypto/caam/regs.h iowrite64be(data, reg); reg 156 drivers/crypto/caam/regs.h static inline u64 rd_reg64(void __iomem *reg) reg 162 drivers/crypto/caam/regs.h high = ioread32(reg); reg 163 drivers/crypto/caam/regs.h low = ioread32(reg + sizeof(u32)); reg 167 drivers/crypto/caam/regs.h return ioread64(reg); reg 170 drivers/crypto/caam/regs.h return ioread64be(reg); reg 76 drivers/crypto/ccp/psp-dev.c int reg; reg 86 drivers/crypto/ccp/psp-dev.c reg = ioread32(psp->io_regs + psp->vdata->cmdresp_reg); reg 87 drivers/crypto/ccp/psp-dev.c if (reg & PSP_CMDRESP_RESP) { reg 100 drivers/crypto/ccp/psp-dev.c unsigned int *reg, unsigned int timeout) reg 109 drivers/crypto/ccp/psp-dev.c *reg = ioread32(psp->io_regs + psp->vdata->cmdresp_reg); reg 154 drivers/crypto/ccp/psp-dev.c unsigned int reg, ret = 0; reg 177 drivers/crypto/ccp/psp-dev.c reg = cmd; reg 178 drivers/crypto/ccp/psp-dev.c reg <<= PSP_CMDRESP_CMD_SHIFT; reg 179 drivers/crypto/ccp/psp-dev.c reg |= PSP_CMDRESP_IOC; reg 180 drivers/crypto/ccp/psp-dev.c iowrite32(reg, psp->io_regs + psp->vdata->cmdresp_reg); reg 183 drivers/crypto/ccp/psp-dev.c ret = sev_wait_cmd_ioc(psp, ®, psp_timeout); reg 197 drivers/crypto/ccp/psp-dev.c *psp_ret = reg & PSP_CMDRESP_ERR_MASK; reg 199 drivers/crypto/ccp/psp-dev.c if (reg & PSP_CMDRESP_ERR_MASK) { reg 201 drivers/crypto/ccp/psp-dev.c cmd, reg & PSP_CMDRESP_ERR_MASK); reg 222 drivers/crypto/ccree/cc_driver.h static inline void cc_iowrite(struct cc_drvdata *drvdata, u32 reg, u32 val) reg 224 drivers/crypto/ccree/cc_driver.h iowrite32(val, (drvdata->cc_base + reg)); reg 227 drivers/crypto/ccree/cc_driver.h static inline u32 cc_ioread(struct cc_drvdata *drvdata, u32 reg) reg 229 drivers/crypto/ccree/cc_driver.h return ioread32(drvdata->cc_base + reg); reg 24 drivers/crypto/ccree/cc_fips.c u32 reg; reg 26 drivers/crypto/ccree/cc_fips.c reg = cc_ioread(drvdata, CC_REG(GPR_HOST)); reg 28 drivers/crypto/ccree/cc_fips.c if (reg & CC_FIPS_SYNC_TEE_STATUS) reg 30 drivers/crypto/ccree/cc_fips.c return (reg & CC_FIPS_SYNC_MODULE_OK); reg 189 drivers/crypto/ccree/cc_request_mgr.c void __iomem *reg = drvdata->cc_base + CC_REG(DSCRPTR_QUEUE_WORD0); reg 199 drivers/crypto/ccree/cc_request_mgr.c writel_relaxed(seq[i].word[w], reg); reg 628 drivers/crypto/hifn_795x.c static inline u32 hifn_read_0(struct hifn_device *dev, u32 reg) reg 630 drivers/crypto/hifn_795x.c return readl(dev->bar[0] + reg); reg 633 drivers/crypto/hifn_795x.c static inline u32 hifn_read_1(struct hifn_device *dev, u32 reg) reg 635 drivers/crypto/hifn_795x.c return readl(dev->bar[1] + reg); reg 638 drivers/crypto/hifn_795x.c static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val) reg 640 drivers/crypto/hifn_795x.c writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg); reg 643 drivers/crypto/hifn_795x.c static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val) reg 645 drivers/crypto/hifn_795x.c writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg); reg 725 drivers/crypto/img-hash.c u32 reg; reg 727 drivers/crypto/img-hash.c reg = img_hash_read(hdev, CR_INTSTAT); reg 728 drivers/crypto/img-hash.c img_hash_write(hdev, CR_INTCLEAR, reg); reg 730 drivers/crypto/img-hash.c if (reg & CR_INT_NEW_RESULTS_SET) { reg 741 drivers/crypto/img-hash.c } else if (reg & CR_INT_RESULTS_AVAILABLE) { reg 744 drivers/crypto/img-hash.c } else if (reg & CR_INT_RESULT_READ_ERR) { reg 747 drivers/crypto/img-hash.c } else if (reg & CR_INT_MESSAGE_WRITE_ERROR) { reg 22 drivers/crypto/inside-secure/safexcel.h #define EIP197_REG_LO16(reg) (reg & 0xffff) reg 23 drivers/crypto/inside-secure/safexcel.h #define EIP197_REG_HI16(reg) ((reg >> 16) & 0xffff) reg 24 drivers/crypto/inside-secure/safexcel.h #define EIP197_VERSION_MASK(reg) ((reg >> 16) & 0xfff) reg 25 drivers/crypto/inside-secure/safexcel.h #define EIP197_VERSION_SWAP(reg) (((reg & 0xf0) << 4) | \ reg 26 drivers/crypto/inside-secure/safexcel.h ((reg >> 4) & 0xf0) | \ reg 27 drivers/crypto/inside-secure/safexcel.h ((reg >> 12) & 0xf)) reg 1842 drivers/crypto/n2_core.c const unsigned int *reg; reg 1845 drivers/crypto/n2_core.c reg = of_get_property(dev->dev.of_node, "reg", NULL); reg 1846 drivers/crypto/n2_core.c if (!reg) reg 1857 drivers/crypto/n2_core.c if (!chdl || (*chdl != *reg)) reg 1128 drivers/crypto/omap-aes.c u32 reg; reg 1165 drivers/crypto/omap-aes.c reg = omap_aes_read(dd, AES_REG_REV(dd)); reg 1170 drivers/crypto/omap-aes.c (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, reg 1171 drivers/crypto/omap-aes.c (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); reg 982 drivers/crypto/omap-des.c u32 reg; reg 1023 drivers/crypto/omap-des.c reg = omap_des_read(dd, DES_REG_REV(dd)); reg 1028 drivers/crypto/omap-des.c (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, reg 1029 drivers/crypto/omap-des.c (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); reg 86 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c u32 reg; reg 90 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK3); reg 91 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c reg &= ~ADF_DH895XCC_ERRMSK3_VF2PF_L_MASK(vf_mask); reg 92 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK3, reg); reg 97 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK5); reg 98 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c reg &= ~ADF_DH895XCC_ERRMSK5_VF2PF_U_MASK(vf_mask); reg 99 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK5, reg); reg 109 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c u32 reg; reg 113 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK3) | reg 115 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK3, reg); reg 120 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c reg = ADF_CSR_RD(pmisc_addr, ADF_DH895XCC_ERRMSK5) | reg 122 drivers/crypto/qat/qat_common/adf_pf2vf_msg.c ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK5, reg); reg 120 drivers/crypto/qat/qat_common/adf_sriov.c u32 reg; reg 139 drivers/crypto/qat/qat_common/adf_sriov.c reg = READ_CSR_ME2FUNCTION_MAP_A(pmisc_addr, i); reg 140 drivers/crypto/qat/qat_common/adf_sriov.c reg |= ME2FUNCTION_MAP_VALID; reg 141 drivers/crypto/qat/qat_common/adf_sriov.c WRITE_CSR_ME2FUNCTION_MAP_A(pmisc_addr, i, reg); reg 146 drivers/crypto/qat/qat_common/adf_sriov.c reg = READ_CSR_ME2FUNCTION_MAP_B(pmisc_addr, i); reg 147 drivers/crypto/qat/qat_common/adf_sriov.c reg |= ME2FUNCTION_MAP_VALID; reg 148 drivers/crypto/qat/qat_common/adf_sriov.c WRITE_CSR_ME2FUNCTION_MAP_B(pmisc_addr, i, reg); reg 179 drivers/crypto/qat/qat_common/adf_sriov.c u32 reg; reg 194 drivers/crypto/qat/qat_common/adf_sriov.c reg = READ_CSR_ME2FUNCTION_MAP_A(pmisc_addr, i); reg 195 drivers/crypto/qat/qat_common/adf_sriov.c reg &= ~ME2FUNCTION_MAP_VALID; reg 196 drivers/crypto/qat/qat_common/adf_sriov.c WRITE_CSR_ME2FUNCTION_MAP_A(pmisc_addr, i, reg); reg 201 drivers/crypto/qat/qat_common/adf_sriov.c reg = READ_CSR_ME2FUNCTION_MAP_B(pmisc_addr, i); reg 202 drivers/crypto/qat/qat_common/adf_sriov.c reg &= ~ME2FUNCTION_MAP_VALID; reg 203 drivers/crypto/qat/qat_common/adf_sriov.c WRITE_CSR_ME2FUNCTION_MAP_B(pmisc_addr, i, reg); reg 150 drivers/crypto/qat/qat_common/icp_qat_hal.h #define AE_XFER_ADDR(handle, ae, reg) (AE_XFER(handle, ae) + \ reg 151 drivers/crypto/qat/qat_common/icp_qat_hal.h ((reg & 0xff) << 2)) reg 152 drivers/crypto/qat/qat_common/icp_qat_hal.h #define SET_AE_XFER(handle, ae, reg, val) \ reg 153 drivers/crypto/qat/qat_common/icp_qat_hal.h ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val) reg 617 drivers/crypto/qat/qat_common/qat_hal.c unsigned short reg; reg 620 drivers/crypto/qat/qat_common/qat_hal.c for (reg = 0; reg < ICP_QAT_UCLO_MAX_GPR_REG; reg++) { reg 622 drivers/crypto/qat/qat_common/qat_hal.c reg, 0); reg 624 drivers/crypto/qat/qat_common/qat_hal.c reg, 0); reg 1322 drivers/crypto/qat/qat_common/qat_hal.c unsigned short reg; reg 1331 drivers/crypto/qat/qat_common/qat_hal.c qat_hal_convert_abs_to_rel(handle, ae, reg_num, ®, reg 1335 drivers/crypto/qat/qat_common/qat_hal.c reg = reg_num; reg 1340 drivers/crypto/qat/qat_common/qat_hal.c stat = qat_hal_wr_rel_reg(handle, ae, ctx, type, reg, regdata); reg 1356 drivers/crypto/qat/qat_common/qat_hal.c unsigned short reg; reg 1365 drivers/crypto/qat/qat_common/qat_hal.c qat_hal_convert_abs_to_rel(handle, ae, reg_num, ®, reg 1369 drivers/crypto/qat/qat_common/qat_hal.c reg = reg_num; reg 1374 drivers/crypto/qat/qat_common/qat_hal.c stat = qat_hal_put_rel_wr_xfer(handle, ae, ctx, type, reg, reg 1391 drivers/crypto/qat/qat_common/qat_hal.c unsigned short reg; reg 1400 drivers/crypto/qat/qat_common/qat_hal.c qat_hal_convert_abs_to_rel(handle, ae, reg_num, ®, reg 1404 drivers/crypto/qat/qat_common/qat_hal.c reg = reg_num; reg 1409 drivers/crypto/qat/qat_common/qat_hal.c stat = qat_hal_put_rel_rd_xfer(handle, ae, ctx, type, reg, reg 494 drivers/crypto/qat/qat_common/qat_uclo.c static unsigned int qat_uclo_calc_checksum(unsigned int reg, int ch) reg 498 drivers/crypto/qat/qat_common/qat_uclo.c unsigned int inbyte = (unsigned int)((reg >> 0x18) ^ ch); reg 500 drivers/crypto/qat/qat_common/qat_uclo.c reg ^= inbyte << 0x8; reg 502 drivers/crypto/qat/qat_common/qat_uclo.c if (reg & topbit) reg 503 drivers/crypto/qat/qat_common/qat_uclo.c reg = (reg << 1) ^ 0x1021; reg 505 drivers/crypto/qat/qat_common/qat_uclo.c reg <<= 1; reg 507 drivers/crypto/qat/qat_common/qat_uclo.c return reg & 0xFFFF; reg 341 drivers/crypto/rockchip/rk3288_crypto.c crypto_info->reg = devm_platform_ioremap_resource(pdev, 0); reg 342 drivers/crypto/rockchip/rk3288_crypto.c if (IS_ERR(crypto_info->reg)) { reg 343 drivers/crypto/rockchip/rk3288_crypto.c err = PTR_ERR(crypto_info->reg); reg 180 drivers/crypto/rockchip/rk3288_crypto.h readl_relaxed(((dev)->reg + (offset))) reg 182 drivers/crypto/rockchip/rk3288_crypto.h writel_relaxed((val), ((dev)->reg + (offset))) reg 191 drivers/crypto/rockchip/rk3288_crypto.h void __iomem *reg; reg 42 drivers/crypto/rockchip/rk3288_crypto_ablkcipher.c memcpy_toio(ctx->dev->reg + RK_CRYPTO_AES_KEY_0, key, keylen); reg 57 drivers/crypto/rockchip/rk3288_crypto_ablkcipher.c memcpy_toio(ctx->dev->reg + RK_CRYPTO_TDES_KEY1_0, key, keylen); reg 72 drivers/crypto/rockchip/rk3288_crypto_ablkcipher.c memcpy_toio(ctx->dev->reg + RK_CRYPTO_TDES_KEY1_0, key, keylen); reg 214 drivers/crypto/rockchip/rk3288_crypto_ablkcipher.c memcpy_toio(dev->reg + RK_CRYPTO_TDES_IV_0, req->info, ivsize); reg 226 drivers/crypto/rockchip/rk3288_crypto_ablkcipher.c memcpy_toio(dev->reg + RK_CRYPTO_AES_IV_0, req->info, ivsize); reg 330 drivers/crypto/rockchip/rk3288_crypto_ablkcipher.c memcpy_toio(dev->reg + RK_CRYPTO_TDES_IV_0, new_iv, ivsize); reg 332 drivers/crypto/rockchip/rk3288_crypto_ablkcipher.c memcpy_toio(dev->reg + RK_CRYPTO_AES_IV_0, new_iv, ivsize); reg 61 drivers/crypto/rockchip/rk3288_crypto_ahash.c memset_io(dev->reg + RK_CRYPTO_HASH_DOUT_0, 0, 32); reg 262 drivers/crypto/rockchip/rk3288_crypto_ahash.c memcpy_fromio(req->result, dev->reg + RK_CRYPTO_HASH_DOUT_0, reg 144 drivers/crypto/s5p-sss.c #define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg)) reg 145 drivers/crypto/s5p-sss.c #define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg)) reg 146 drivers/crypto/s5p-sss.c #define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg)) reg 148 drivers/crypto/s5p-sss.c #define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg) reg 149 drivers/crypto/s5p-sss.c #define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \ reg 150 drivers/crypto/s5p-sss.c SSS_AES_REG(dev, reg)) reg 231 drivers/crypto/sahara.c static inline void sahara_write(struct sahara_dev *dev, u32 data, u32 reg) reg 233 drivers/crypto/sahara.c writel(data, dev->regs_base + reg); reg 236 drivers/crypto/sahara.c static inline unsigned int sahara_read(struct sahara_dev *dev, u32 reg) reg 238 drivers/crypto/sahara.c return readl(dev->regs_base + reg); reg 215 drivers/crypto/stm32/stm32-hash.c u32 reg; reg 217 drivers/crypto/stm32/stm32-hash.c reg = stm32_hash_read(hdev, HASH_STR); reg 218 drivers/crypto/stm32/stm32-hash.c reg &= ~(HASH_STR_NBLW_MASK); reg 219 drivers/crypto/stm32/stm32-hash.c reg |= (8U * ((length) % 4U)); reg 220 drivers/crypto/stm32/stm32-hash.c stm32_hash_write(hdev, HASH_STR, reg); reg 227 drivers/crypto/stm32/stm32-hash.c u32 reg; reg 240 drivers/crypto/stm32/stm32-hash.c reg = stm32_hash_read(hdev, HASH_STR); reg 241 drivers/crypto/stm32/stm32-hash.c reg |= HASH_STR_DCAL; reg 242 drivers/crypto/stm32/stm32-hash.c stm32_hash_write(hdev, HASH_STR, reg); reg 256 drivers/crypto/stm32/stm32-hash.c u32 reg = HASH_CR_INIT; reg 261 drivers/crypto/stm32/stm32-hash.c reg |= HASH_CR_ALGO_MD5; reg 264 drivers/crypto/stm32/stm32-hash.c reg |= HASH_CR_ALGO_SHA1; reg 267 drivers/crypto/stm32/stm32-hash.c reg |= HASH_CR_ALGO_SHA224; reg 270 drivers/crypto/stm32/stm32-hash.c reg |= HASH_CR_ALGO_SHA256; reg 273 drivers/crypto/stm32/stm32-hash.c reg |= HASH_CR_ALGO_MD5; reg 276 drivers/crypto/stm32/stm32-hash.c reg |= (rctx->data_type << HASH_CR_DATATYPE_POS); reg 280 drivers/crypto/stm32/stm32-hash.c reg |= HASH_CR_MODE; reg 282 drivers/crypto/stm32/stm32-hash.c reg |= HASH_CR_LKEY; reg 287 drivers/crypto/stm32/stm32-hash.c stm32_hash_write(hdev, HASH_CR, reg); reg 291 drivers/crypto/stm32/stm32-hash.c dev_dbg(hdev->dev, "Write Control %x\n", reg); reg 334 drivers/crypto/stm32/stm32-hash.c u32 reg; reg 364 drivers/crypto/stm32/stm32-hash.c reg = stm32_hash_read(hdev, HASH_STR); reg 365 drivers/crypto/stm32/stm32-hash.c reg |= HASH_STR_DCAL; reg 366 drivers/crypto/stm32/stm32-hash.c stm32_hash_write(hdev, HASH_STR, reg); reg 412 drivers/crypto/stm32/stm32-hash.c u32 reg; reg 430 drivers/crypto/stm32/stm32-hash.c reg = stm32_hash_read(hdev, HASH_CR); reg 433 drivers/crypto/stm32/stm32-hash.c reg |= HASH_CR_MDMAT; reg 435 drivers/crypto/stm32/stm32-hash.c reg &= ~HASH_CR_MDMAT; reg 437 drivers/crypto/stm32/stm32-hash.c reg |= HASH_CR_DMAE; reg 439 drivers/crypto/stm32/stm32-hash.c stm32_hash_write(hdev, HASH_CR, reg); reg 544 drivers/crypto/stm32/stm32-hash.c int err = 0, len = 0, reg, ncp = 0; reg 606 drivers/crypto/stm32/stm32-hash.c reg = stm32_hash_read(hdev, HASH_CR); reg 607 drivers/crypto/stm32/stm32-hash.c reg &= ~HASH_CR_DMAE; reg 608 drivers/crypto/stm32/stm32-hash.c reg |= HASH_CR_DMAA; reg 609 drivers/crypto/stm32/stm32-hash.c stm32_hash_write(hdev, HASH_CR, reg); reg 618 drivers/crypto/stm32/stm32-hash.c reg = stm32_hash_read(hdev, HASH_STR); reg 619 drivers/crypto/stm32/stm32-hash.c reg |= HASH_STR_DCAL; reg 620 drivers/crypto/stm32/stm32-hash.c stm32_hash_write(hdev, HASH_STR, reg); reg 993 drivers/crypto/stm32/stm32-hash.c u32 reg; reg 1005 drivers/crypto/stm32/stm32-hash.c reg = *preg++ | HASH_CR_INIT; reg 1006 drivers/crypto/stm32/stm32-hash.c stm32_hash_write(hdev, HASH_CR, reg); reg 1106 drivers/crypto/stm32/stm32-hash.c u32 reg; reg 1108 drivers/crypto/stm32/stm32-hash.c reg = stm32_hash_read(hdev, HASH_SR); reg 1109 drivers/crypto/stm32/stm32-hash.c if (reg & HASH_SR_OUTPUT_READY) { reg 1110 drivers/crypto/stm32/stm32-hash.c reg &= ~HASH_SR_OUTPUT_READY; reg 1111 drivers/crypto/stm32/stm32-hash.c stm32_hash_write(hdev, HASH_SR, reg); reg 145 drivers/crypto/talitos.c setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, reg 148 drivers/crypto/talitos.c while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR_LO) & reg 152 drivers/crypto/talitos.c setbits32(priv->chan[ch].reg + TALITOS_CCCR, reg 155 drivers/crypto/talitos.c while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & reg 166 drivers/crypto/talitos.c setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE | reg 170 drivers/crypto/talitos.c setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, reg 175 drivers/crypto/talitos.c setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, reg 188 drivers/crypto/talitos.c setbits32(priv->reg + TALITOS_MCR, mcr); reg 190 drivers/crypto/talitos.c while ((in_be32(priv->reg + TALITOS_MCR) & mcr) reg 196 drivers/crypto/talitos.c setbits32(priv->reg + TALITOS_MCR, mcr); reg 239 drivers/crypto/talitos.c clrbits32(priv->reg + TALITOS_IMR, TALITOS1_IMR_INIT); reg 240 drivers/crypto/talitos.c clrbits32(priv->reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT); reg 244 drivers/crypto/talitos.c setbits32(priv->reg + TALITOS_IMR, TALITOS2_IMR_INIT); reg 245 drivers/crypto/talitos.c setbits32(priv->reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT); reg 313 drivers/crypto/talitos.c out_be32(priv->chan[ch].reg + TALITOS_FF, reg 315 drivers/crypto/talitos.c out_be32(priv->chan[ch].reg + TALITOS_FF_LO, reg 423 drivers/crypto/talitos.c clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \ reg 424 drivers/crypto/talitos.c clrbits32(priv->reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT); \ reg 450 drivers/crypto/talitos.c setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \ reg 451 drivers/crypto/talitos.c setbits32(priv->reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT); \ reg 469 drivers/crypto/talitos.c cur_desc = ((u64)in_be32(priv->chan[ch].reg + TALITOS_CDPR)) << 32; reg 470 drivers/crypto/talitos.c cur_desc |= in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO); reg 510 drivers/crypto/talitos.c desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF); reg 572 drivers/crypto/talitos.c in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i), reg 573 drivers/crypto/talitos.c in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i)); reg 601 drivers/crypto/talitos.c v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO); reg 644 drivers/crypto/talitos.c setbits32(priv->chan[ch].reg + TALITOS_CCCR, reg 646 drivers/crypto/talitos.c setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0); reg 647 drivers/crypto/talitos.c while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & reg 684 drivers/crypto/talitos.c isr = in_be32(priv->reg + TALITOS_ISR); \ reg 685 drivers/crypto/talitos.c isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \ reg 687 drivers/crypto/talitos.c out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \ reg 688 drivers/crypto/talitos.c out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \ reg 697 drivers/crypto/talitos.c setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \ reg 719 drivers/crypto/talitos.c isr = in_be32(priv->reg + TALITOS_ISR); \ reg 720 drivers/crypto/talitos.c isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \ reg 722 drivers/crypto/talitos.c out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \ reg 723 drivers/crypto/talitos.c out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \ reg 732 drivers/crypto/talitos.c clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \ reg 3313 drivers/crypto/talitos.c priv->reg = devm_ioremap(dev, res->start, resource_size(res)); reg 3314 drivers/crypto/talitos.c if (!priv->reg) { reg 3346 drivers/crypto/talitos.c priv->reg_deu = priv->reg + TALITOS12_DEU; reg 3347 drivers/crypto/talitos.c priv->reg_aesu = priv->reg + TALITOS12_AESU; reg 3348 drivers/crypto/talitos.c priv->reg_mdeu = priv->reg + TALITOS12_MDEU; reg 3351 drivers/crypto/talitos.c priv->reg_deu = priv->reg + TALITOS10_DEU; reg 3352 drivers/crypto/talitos.c priv->reg_aesu = priv->reg + TALITOS10_AESU; reg 3353 drivers/crypto/talitos.c priv->reg_mdeu = priv->reg + TALITOS10_MDEU; reg 3354 drivers/crypto/talitos.c priv->reg_afeu = priv->reg + TALITOS10_AFEU; reg 3355 drivers/crypto/talitos.c priv->reg_rngu = priv->reg + TALITOS10_RNGU; reg 3356 drivers/crypto/talitos.c priv->reg_pkeu = priv->reg + TALITOS10_PKEU; reg 3359 drivers/crypto/talitos.c priv->reg_deu = priv->reg + TALITOS2_DEU; reg 3360 drivers/crypto/talitos.c priv->reg_aesu = priv->reg + TALITOS2_AESU; reg 3361 drivers/crypto/talitos.c priv->reg_mdeu = priv->reg + TALITOS2_MDEU; reg 3362 drivers/crypto/talitos.c priv->reg_afeu = priv->reg + TALITOS2_AFEU; reg 3363 drivers/crypto/talitos.c priv->reg_rngu = priv->reg + TALITOS2_RNGU; reg 3364 drivers/crypto/talitos.c priv->reg_pkeu = priv->reg + TALITOS2_PKEU; reg 3365 drivers/crypto/talitos.c priv->reg_keu = priv->reg + TALITOS2_KEU; reg 3366 drivers/crypto/talitos.c priv->reg_crcu = priv->reg + TALITOS2_CRCU; reg 3409 drivers/crypto/talitos.c priv->chan[i].reg = priv->reg + stride * (i + 1); reg 3411 drivers/crypto/talitos.c priv->chan[i].reg += TALITOS_CH_BASE_OFFSET; reg 90 drivers/crypto/talitos.h void __iomem *reg; reg 112 drivers/crypto/talitos.h void __iomem *reg; reg 355 drivers/crypto/ux500/cryp/cryp.c struct cryp_register __iomem *reg = device_data->base; reg 365 drivers/crypto/ux500/cryp/cryp.c writel_relaxed(ctx->key_4_l, ®->key_4_l); reg 366 drivers/crypto/ux500/cryp/cryp.c writel_relaxed(ctx->key_4_r, ®->key_4_r); reg 370 drivers/crypto/ux500/cryp/cryp.c writel_relaxed(ctx->key_3_l, ®->key_3_l); reg 371 drivers/crypto/ux500/cryp/cryp.c writel_relaxed(ctx->key_3_r, ®->key_3_r); reg 375 drivers/crypto/ux500/cryp/cryp.c writel_relaxed(ctx->key_2_l, ®->key_2_l); reg 376 drivers/crypto/ux500/cryp/cryp.c writel_relaxed(ctx->key_2_r, ®->key_2_r); reg 380 drivers/crypto/ux500/cryp/cryp.c writel_relaxed(ctx->key_1_l, ®->key_1_l); reg 381 drivers/crypto/ux500/cryp/cryp.c writel_relaxed(ctx->key_1_r, ®->key_1_r); reg 388 drivers/crypto/ux500/cryp/cryp.c writel_relaxed(ctx->init_vect_0_l, ®->init_vect_0_l); reg 389 drivers/crypto/ux500/cryp/cryp.c writel_relaxed(ctx->init_vect_0_r, ®->init_vect_0_r); reg 390 drivers/crypto/ux500/cryp/cryp.c writel_relaxed(ctx->init_vect_1_l, ®->init_vect_1_l); reg 391 drivers/crypto/ux500/cryp/cryp.c writel_relaxed(ctx->init_vect_1_r, ®->init_vect_1_r); reg 33 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_PUT_BITS(reg, val, shift, mask) \ reg 34 drivers/crypto/ux500/cryp/cryp_p.h writel_relaxed(((readl_relaxed(reg) & ~(mask)) | \ reg 35 drivers/crypto/ux500/cryp/cryp_p.h (((u32)val << shift) & (mask))), reg) reg 104 drivers/crypto/ux500/hash/hash_alg.h #define HASH_PUT_BITS(reg, val, shift, mask) \ reg 105 drivers/crypto/ux500/hash/hash_alg.h writel_relaxed(((readl(reg) & ~(mask)) | \ reg 106 drivers/crypto/ux500/hash/hash_alg.h (((u32)val << shift) & (mask))), reg) reg 1607 drivers/dma/amba-pl08x.c u32 reg; reg 1613 drivers/dma/amba-pl08x.c .reg = PL080_BSIZE_256, reg 1617 drivers/dma/amba-pl08x.c .reg = PL080_BSIZE_128, reg 1621 drivers/dma/amba-pl08x.c .reg = PL080_BSIZE_64, reg 1625 drivers/dma/amba-pl08x.c .reg = PL080_BSIZE_32, reg 1629 drivers/dma/amba-pl08x.c .reg = PL080_BSIZE_16, reg 1633 drivers/dma/amba-pl08x.c .reg = PL080_BSIZE_8, reg 1637 drivers/dma/amba-pl08x.c .reg = PL080_BSIZE_4, reg 1641 drivers/dma/amba-pl08x.c .reg = PL080_BSIZE_1, reg 1705 drivers/dma/amba-pl08x.c return burst_sizes[i].reg; reg 1075 drivers/dma/at_hdmac.c dma_addr_t reg; reg 1104 drivers/dma/at_hdmac.c reg = sconfig->dst_addr; reg 1126 drivers/dma/at_hdmac.c desc->lli.daddr = reg; reg 1145 drivers/dma/at_hdmac.c reg = sconfig->src_addr; reg 1166 drivers/dma/at_hdmac.c desc->lli.saddr = reg; reg 252 drivers/dma/at_xdmac.c #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg)) reg 253 drivers/dma/at_xdmac.c #define at_xdmac_write(atxdmac, reg, value) \ reg 254 drivers/dma/at_xdmac.c writel_relaxed((value), (atxdmac)->regs + (reg)) reg 256 drivers/dma/at_xdmac.c #define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg)) reg 257 drivers/dma/at_xdmac.c #define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg)) reg 337 drivers/dma/at_xdmac.c u32 reg; reg 348 drivers/dma/at_xdmac.c reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys) reg 350 drivers/dma/at_xdmac.c at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg); reg 358 drivers/dma/at_xdmac.c reg = AT_XDMAC_CNDC_NDVIEW_NDV1; reg 360 drivers/dma/at_xdmac.c reg = AT_XDMAC_CNDC_NDVIEW_NDV3; reg 362 drivers/dma/at_xdmac.c reg = AT_XDMAC_CNDC_NDVIEW_NDV2; reg 371 drivers/dma/at_xdmac.c reg |= AT_XDMAC_CNDC_NDDUP reg 374 drivers/dma/at_xdmac.c at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg); reg 386 drivers/dma/at_xdmac.c reg = AT_XDMAC_CIE_RBEIE | AT_XDMAC_CIE_WBEIE; reg 391 drivers/dma/at_xdmac.c reg |= AT_XDMAC_CIE_ROIE; reg 399 drivers/dma/at_xdmac.c reg | AT_XDMAC_CIE_BIE); reg 402 drivers/dma/at_xdmac.c reg | AT_XDMAC_CIE_LIE); reg 1964 drivers/dma/at_xdmac.c u32 reg; reg 1983 drivers/dma/at_xdmac.c reg = readl_relaxed(base + AT_XDMAC_GTYPE); reg 1984 drivers/dma/at_xdmac.c nr_channels = AT_XDMAC_NB_CH(reg); reg 2443 drivers/dma/coh901318.c u32 reg; reg 2451 drivers/dma/coh901318.c .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES, reg 2457 drivers/dma/coh901318.c .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES, reg 2463 drivers/dma/coh901318.c .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES, reg 2469 drivers/dma/coh901318.c .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES, reg 2475 drivers/dma/coh901318.c .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES, reg 2481 drivers/dma/coh901318.c .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES, reg 2487 drivers/dma/coh901318.c .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES, reg 2493 drivers/dma/coh901318.c .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE, reg 2568 drivers/dma/coh901318.c ctrl |= burst_sizes[i].reg; reg 157 drivers/dma/dma-axi-dmac.c static void axi_dmac_write(struct axi_dmac *axi_dmac, unsigned int reg, reg 160 drivers/dma/dma-axi-dmac.c writel(val, axi_dmac->base + reg); reg 163 drivers/dma/dma-axi-dmac.c static int axi_dmac_read(struct axi_dmac *axi_dmac, unsigned int reg) reg 165 drivers/dma/dma-axi-dmac.c return readl(axi_dmac->base + reg); reg 682 drivers/dma/dma-axi-dmac.c static bool axi_dmac_regmap_rdwr(struct device *dev, unsigned int reg) reg 684 drivers/dma/dma-axi-dmac.c switch (reg) { reg 183 drivers/dma/dma-jz4780.c unsigned int chn, unsigned int reg) reg 185 drivers/dma/dma-jz4780.c return readl(jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn)); reg 189 drivers/dma/dma-jz4780.c unsigned int chn, unsigned int reg, uint32_t val) reg 191 drivers/dma/dma-jz4780.c writel(val, jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn)); reg 195 drivers/dma/dma-jz4780.c unsigned int reg) reg 197 drivers/dma/dma-jz4780.c return readl(jzdma->ctrl_base + reg); reg 201 drivers/dma/dma-jz4780.c unsigned int reg, uint32_t val) reg 203 drivers/dma/dma-jz4780.c writel(val, jzdma->ctrl_base + reg); reg 210 drivers/dma/dma-jz4780.c unsigned int reg; reg 213 drivers/dma/dma-jz4780.c reg = JZ_DMA_REG_DCKE; reg 215 drivers/dma/dma-jz4780.c reg = JZ_DMA_REG_DCKES; reg 217 drivers/dma/dma-jz4780.c jz4780_dma_ctrl_writel(jzdma, reg, BIT(chn)); reg 45 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val) reg 47 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c iowrite32(val, chip->regs + reg); reg 50 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c static inline u32 axi_dma_ioread32(struct axi_dma_chip *chip, u32 reg) reg 52 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c return ioread32(chip->regs + reg); reg 56 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c axi_chan_iowrite32(struct axi_dma_chan *chan, u32 reg, u32 val) reg 58 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c iowrite32(val, chan->chan_regs + reg); reg 61 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c static inline u32 axi_chan_ioread32(struct axi_dma_chan *chan, u32 reg) reg 63 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c return ioread32(chan->chan_regs + reg); reg 67 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c axi_chan_iowrite64(struct axi_dma_chan *chan, u32 reg, u64 val) reg 73 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c iowrite32(lower_32_bits(val), chan->chan_regs + reg); reg 74 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4); reg 276 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c u32 reg, irq_mask; reg 288 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c reg = (DWAXIDMAC_MBLK_TYPE_LL << CH_CFG_L_DST_MULTBLK_TYPE_POS | reg 290 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c axi_chan_iowrite32(chan, CH_CFG_L, reg); reg 292 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c reg = (DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC << CH_CFG_H_TT_FC_POS | reg 296 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c axi_chan_iowrite32(chan, CH_CFG_H, reg); reg 431 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c u32 xfer_width, reg; reg 468 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c reg = CH_CTL_H_LLI_VALID; reg 472 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c reg |= (CH_CTL_H_ARLEN_EN | reg 477 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c desc->lli.ctl_hi = cpu_to_le32(reg); reg 479 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c reg = (DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS | reg 485 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c desc->lli.ctl_lo = cpu_to_le32(reg); reg 52 drivers/dma/dw-edma/dw-edma-v0-debugfs.c dma_addr_t *reg; reg 57 drivers/dma/dw-edma/dw-edma-v0-debugfs.c void __iomem *reg = (void __force __iomem *)data; reg 59 drivers/dma/dw-edma/dw-edma-v0-debugfs.c reg >= (void __iomem *)®s->type.legacy.ch) { reg 66 drivers/dma/dw-edma/dw-edma-v0-debugfs.c if (lim[0][ch].start >= reg && reg < lim[0][ch].end) { reg 67 drivers/dma/dw-edma/dw-edma-v0-debugfs.c ptr += (reg - lim[0][ch].start); reg 72 drivers/dma/dw-edma/dw-edma-v0-debugfs.c if (lim[1][ch].start >= reg && reg < lim[1][ch].end) { reg 73 drivers/dma/dw-edma/dw-edma-v0-debugfs.c ptr += (reg - lim[1][ch].start); reg 90 drivers/dma/dw-edma/dw-edma-v0-debugfs.c *val = readl(reg); reg 104 drivers/dma/dw-edma/dw-edma-v0-debugfs.c entries[i].reg, &fops_x32)) reg 634 drivers/dma/dw/core.c dma_addr_t reg; reg 654 drivers/dma/dw/core.c reg = sconfig->dst_addr; reg 681 drivers/dma/dw/core.c lli_write(desc, dar, reg); reg 704 drivers/dma/dw/core.c reg = sconfig->src_addr; reg 728 drivers/dma/dw/core.c lli_write(desc, sar, reg); reg 356 drivers/dma/dw/regs.h #define channel_set_bit(dw, reg, mask) \ reg 357 drivers/dma/dw/regs.h dma_writel(dw, reg, ((mask) << 8) | (mask)) reg 358 drivers/dma/dw/regs.h #define channel_clear_bit(dw, reg, mask) \ reg 359 drivers/dma/dw/regs.h dma_writel(dw, reg, ((mask) << 8) | 0) reg 386 drivers/dma/dw/regs.h #define lli_set(d, reg, v) ((d)->lli.reg |= cpu_to_le32(v)) reg 387 drivers/dma/dw/regs.h #define lli_clear(d, reg, v) ((d)->lli.reg &= ~cpu_to_le32(v)) reg 388 drivers/dma/dw/regs.h #define lli_read(d, reg) le32_to_cpu((d)->lli.reg) reg 389 drivers/dma/dw/regs.h #define lli_write(d, reg, v) ((d)->lli.reg = cpu_to_le32(v)) reg 573 drivers/dma/fsl-qdma.c u32 reg; reg 578 drivers/dma/fsl-qdma.c reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR); reg 579 drivers/dma/fsl-qdma.c reg |= FSL_QDMA_DMR_DQD; reg 580 drivers/dma/fsl-qdma.c qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR); reg 588 drivers/dma/fsl-qdma.c reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DSR); reg 589 drivers/dma/fsl-qdma.c if (!(reg & FSL_QDMA_DSR_DB)) reg 620 drivers/dma/fsl-qdma.c u32 reg, i, count; reg 631 drivers/dma/fsl-qdma.c reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQSR); reg 632 drivers/dma/fsl-qdma.c if (reg & FSL_QDMA_BSQSR_QE) reg 667 drivers/dma/fsl-qdma.c reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQMR); reg 668 drivers/dma/fsl-qdma.c reg |= FSL_QDMA_BSQMR_DI; reg 674 drivers/dma/fsl-qdma.c qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BSQMR); reg 680 drivers/dma/fsl-qdma.c reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQMR); reg 681 drivers/dma/fsl-qdma.c reg |= FSL_QDMA_BSQMR_DI; reg 686 drivers/dma/fsl-qdma.c qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BSQMR); reg 716 drivers/dma/fsl-qdma.c unsigned int intr, reg; reg 736 drivers/dma/fsl-qdma.c reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR); reg 737 drivers/dma/fsl-qdma.c reg |= FSL_QDMA_DMR_DQD; reg 738 drivers/dma/fsl-qdma.c qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR); reg 819 drivers/dma/fsl-qdma.c u32 reg; reg 864 drivers/dma/fsl-qdma.c reg = FSL_QDMA_BCQMR_EN; reg 865 drivers/dma/fsl-qdma.c reg |= FSL_QDMA_BCQMR_CD_THLD(ilog2(temp->n_cq) - 4); reg 866 drivers/dma/fsl-qdma.c reg |= FSL_QDMA_BCQMR_CQ_SIZE(ilog2(temp->n_cq) - 6); reg 867 drivers/dma/fsl-qdma.c qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BCQMR(i)); reg 901 drivers/dma/fsl-qdma.c reg = FSL_QDMA_BSQMR_EN; reg 902 drivers/dma/fsl-qdma.c reg |= FSL_QDMA_BSQMR_CQ_SIZE(ilog2 reg 905 drivers/dma/fsl-qdma.c qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BSQMR); reg 906 drivers/dma/fsl-qdma.c reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQMR); reg 913 drivers/dma/fsl-qdma.c reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR); reg 914 drivers/dma/fsl-qdma.c reg &= ~FSL_QDMA_DMR_DQD; reg 915 drivers/dma/fsl-qdma.c qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR); reg 939 drivers/dma/fsl-qdma.c u32 reg; reg 945 drivers/dma/fsl-qdma.c reg = qdma_readl(fsl_chan->qdma, block + FSL_QDMA_BCQSR(fsl_queue->id)); reg 946 drivers/dma/fsl-qdma.c if (reg & (FSL_QDMA_BCQSR_QF | FSL_QDMA_BCQSR_XOFF)) reg 961 drivers/dma/fsl-qdma.c reg = qdma_readl(fsl_chan->qdma, block + FSL_QDMA_BCQMR(fsl_queue->id)); reg 962 drivers/dma/fsl-qdma.c reg |= FSL_QDMA_BCQMR_EI; reg 963 drivers/dma/fsl-qdma.c qdma_writel(fsl_chan->qdma, reg, block + FSL_QDMA_BCQMR(fsl_queue->id)); reg 445 drivers/dma/hsu/hsu.c hsuc->reg = addr + i * HSU_DMA_CHAN_LENGTH; reg 85 drivers/dma/hsu/hsu.h void __iomem *reg; reg 101 drivers/dma/hsu/hsu.h return readl(hsuc->reg + offset); reg 107 drivers/dma/hsu/hsu.h writel(value, hsuc->reg + offset); reg 146 drivers/dma/idma64.h #define channel_set_bit(idma64, reg, mask) \ reg 147 drivers/dma/idma64.h dma_writel(idma64, reg, ((mask) << 8) | (mask)) reg 148 drivers/dma/idma64.h #define channel_clear_bit(idma64, reg, mask) \ reg 149 drivers/dma/idma64.h dma_writel(idma64, reg, ((mask) << 8) | 0) reg 162 drivers/dma/idma64.h #define channel_readl(idma64c, reg) \ reg 163 drivers/dma/idma64.h idma64c_readl(idma64c, IDMA64_CH_##reg) reg 164 drivers/dma/idma64.h #define channel_writel(idma64c, reg, value) \ reg 165 drivers/dma/idma64.h idma64c_writel(idma64c, IDMA64_CH_##reg, (value)) reg 178 drivers/dma/idma64.h #define channel_readq(idma64c, reg) \ reg 179 drivers/dma/idma64.h idma64c_readq(idma64c, IDMA64_CH_##reg) reg 180 drivers/dma/idma64.h #define channel_writeq(idma64c, reg, value) \ reg 181 drivers/dma/idma64.h idma64c_writeq(idma64c, IDMA64_CH_##reg, (value)) reg 208 drivers/dma/idma64.h #define dma_readl(idma64, reg) \ reg 209 drivers/dma/idma64.h idma64_readl(idma64, IDMA64_##reg) reg 210 drivers/dma/idma64.h #define dma_writel(idma64, reg, value) \ reg 211 drivers/dma/idma64.h idma64_writel(idma64, IDMA64_##reg, (value)) reg 149 drivers/dma/img-mdc-dma.c static inline u32 mdc_readl(struct mdc_dma *mdma, u32 reg) reg 151 drivers/dma/img-mdc-dma.c return readl(mdma->regs + reg); reg 154 drivers/dma/img-mdc-dma.c static inline void mdc_writel(struct mdc_dma *mdma, u32 val, u32 reg) reg 156 drivers/dma/img-mdc-dma.c writel(val, mdma->regs + reg); reg 159 drivers/dma/img-mdc-dma.c static inline u32 mdc_chan_readl(struct mdc_chan *mchan, u32 reg) reg 161 drivers/dma/img-mdc-dma.c return mdc_readl(mchan->mdma, mchan->chan_nr * 0x040 + reg); reg 164 drivers/dma/img-mdc-dma.c static inline void mdc_chan_writel(struct mdc_chan *mchan, u32 val, u32 reg) reg 166 drivers/dma/img-mdc-dma.c mdc_writel(mchan->mdma, val, mchan->chan_nr * 0x040 + reg); reg 670 drivers/dma/imx-sdma.c u32 reg; reg 675 drivers/dma/imx-sdma.c reg, !(reg & 1), 1, 500); reg 680 drivers/dma/imx-sdma.c reg = readl(sdma->regs + SDMA_H_CONFIG); reg 681 drivers/dma/imx-sdma.c if ((reg & SDMA_H_CONFIG_CSM) == 0) { reg 682 drivers/dma/imx-sdma.c reg |= SDMA_H_CONFIG_CSM; reg 683 drivers/dma/imx-sdma.c writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG); reg 1795 drivers/dma/imx-sdma.c u32 reg, val, shift, num_map, i; reg 1821 drivers/dma/imx-sdma.c ret = of_property_read_u32_index(np, propname, i, ®); reg 1842 drivers/dma/imx-sdma.c regmap_update_bits(gpr, reg, BIT(shift), val << shift); reg 43 drivers/dma/ipu/ipu_idmac.c static u32 __idmac_read_icreg(struct ipu *ipu, unsigned long reg) reg 45 drivers/dma/ipu/ipu_idmac.c return __raw_readl(ipu->reg_ic + reg); reg 48 drivers/dma/ipu/ipu_idmac.c #define idmac_read_icreg(ipu, reg) __idmac_read_icreg(ipu, reg - IC_CONF) reg 50 drivers/dma/ipu/ipu_idmac.c static void __idmac_write_icreg(struct ipu *ipu, u32 value, unsigned long reg) reg 52 drivers/dma/ipu/ipu_idmac.c __raw_writel(value, ipu->reg_ic + reg); reg 55 drivers/dma/ipu/ipu_idmac.c #define idmac_write_icreg(ipu, v, reg) __idmac_write_icreg(ipu, v, reg - IC_CONF) reg 57 drivers/dma/ipu/ipu_idmac.c static u32 idmac_read_ipureg(struct ipu *ipu, unsigned long reg) reg 59 drivers/dma/ipu/ipu_idmac.c return __raw_readl(ipu->reg_ipu + reg); reg 62 drivers/dma/ipu/ipu_idmac.c static void idmac_write_ipureg(struct ipu *ipu, u32 value, unsigned long reg) reg 64 drivers/dma/ipu/ipu_idmac.c __raw_writel(value, ipu->reg_ipu + reg); reg 511 drivers/dma/ipu/ipu_idmac.c uint32_t reg, ic_conf; reg 519 drivers/dma/ipu/ipu_idmac.c reg = (downsize_coeff << 30) | (resize_coeff << 16); reg 525 drivers/dma/ipu/ipu_idmac.c reg |= (downsize_coeff << 14) | resize_coeff; reg 540 drivers/dma/ipu/ipu_idmac.c idmac_write_icreg(ipu, reg, IC_PRP_ENC_RSC); reg 563 drivers/dma/ipu/ipu_idmac.c u32 reg = idmac_read_icreg(ipu, IDMAC_CHA_PRI); reg 566 drivers/dma/ipu/ipu_idmac.c reg |= 1UL << channel; reg 568 drivers/dma/ipu/ipu_idmac.c reg &= ~(1UL << channel); reg 570 drivers/dma/ipu/ipu_idmac.c idmac_write_icreg(ipu, reg, IDMAC_CHA_PRI); reg 606 drivers/dma/ipu/ipu_idmac.c uint32_t reg; reg 625 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_icreg(ipu, IDMAC_CHA_EN); reg 627 drivers/dma/ipu/ipu_idmac.c idmac_write_icreg(ipu, reg | (1UL << channel), IDMAC_CHA_EN); reg 662 drivers/dma/ipu/ipu_idmac.c uint32_t reg; reg 689 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL); reg 692 drivers/dma/ipu/ipu_idmac.c reg |= 1UL << channel; reg 694 drivers/dma/ipu/ipu_idmac.c reg &= ~(1UL << channel); reg 696 drivers/dma/ipu/ipu_idmac.c idmac_write_ipureg(ipu, reg, IPU_CHA_DB_MODE_SEL); reg 733 drivers/dma/ipu/ipu_idmac.c uint32_t reg; reg 739 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY); reg 740 drivers/dma/ipu/ipu_idmac.c if (reg & (1UL << channel)) { reg 750 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY); reg 751 drivers/dma/ipu/ipu_idmac.c if (reg & (1UL << channel)) { reg 757 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_ipureg(&ipu_data, IPU_CHA_DB_MODE_SEL); reg 759 drivers/dma/ipu/ipu_idmac.c if (!(reg & (1UL << channel))) reg 760 drivers/dma/ipu/ipu_idmac.c idmac_write_ipureg(&ipu_data, reg | (1UL << channel), reg 954 drivers/dma/ipu/ipu_idmac.c uint32_t reg; reg 969 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_icreg(ipu, IC_CONF); reg 970 drivers/dma/ipu/ipu_idmac.c idmac_write_icreg(ipu, reg & ~IC_CONF_CSI_MEM_WR_EN, IC_CONF); reg 974 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_ipureg(ipu, IPU_FS_PROC_FLOW); reg 975 drivers/dma/ipu/ipu_idmac.c idmac_write_ipureg(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW); reg 1011 drivers/dma/ipu/ipu_idmac.c uint32_t reg; reg 1026 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL); reg 1027 drivers/dma/ipu/ipu_idmac.c idmac_write_ipureg(ipu, reg & ~chan_mask, IPU_CHA_DB_MODE_SEL); reg 1033 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_icreg(ipu, IC_CONF); reg 1034 drivers/dma/ipu/ipu_idmac.c idmac_write_icreg(ipu, reg & ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN), reg 1038 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_icreg(ipu, IC_CONF); reg 1039 drivers/dma/ipu/ipu_idmac.c idmac_write_icreg(ipu, reg & ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1), reg 1074 drivers/dma/ipu/ipu_idmac.c uint32_t reg; reg 1115 drivers/dma/ipu/ipu_idmac.c reg = idmac_read_icreg(ipu, IDMAC_CHA_EN); reg 1116 drivers/dma/ipu/ipu_idmac.c idmac_write_icreg(ipu, reg & ~chan_mask, IDMAC_CHA_EN); reg 22 drivers/dma/ipu/ipu_irq.c static u32 ipu_read_reg(struct ipu *ipu, unsigned long reg) reg 24 drivers/dma/ipu/ipu_irq.c return __raw_readl(ipu->reg_ipu + reg); reg 27 drivers/dma/ipu/ipu_irq.c static void ipu_write_reg(struct ipu *ipu, u32 value, unsigned long reg) reg 29 drivers/dma/ipu/ipu_irq.c __raw_writel(value, ipu->reg_ipu + reg); reg 97 drivers/dma/ipu/ipu_irq.c uint32_t reg; reg 109 drivers/dma/ipu/ipu_irq.c reg = ipu_read_reg(bank->ipu, bank->control); reg 110 drivers/dma/ipu/ipu_irq.c reg |= (1UL << (map->source & 31)); reg 111 drivers/dma/ipu/ipu_irq.c ipu_write_reg(bank->ipu, reg, bank->control); reg 120 drivers/dma/ipu/ipu_irq.c uint32_t reg; reg 132 drivers/dma/ipu/ipu_irq.c reg = ipu_read_reg(bank->ipu, bank->control); reg 133 drivers/dma/ipu/ipu_irq.c reg &= ~(1UL << (map->source & 31)); reg 134 drivers/dma/ipu/ipu_irq.c ipu_write_reg(bank->ipu, reg, bank->control); reg 36 drivers/dma/lpc18xx-dmamux.c struct regmap *reg; reg 96 drivers/dma/lpc18xx-dmamux.c regmap_update_bits(dmamux->reg, LPC18XX_CREG_DMAMUX, reg 120 drivers/dma/lpc18xx-dmamux.c dmamux->reg = syscon_regmap_lookup_by_compatible("nxp,lpc1850-creg"); reg 121 drivers/dma/lpc18xx-dmamux.c if (IS_ERR(dmamux->reg)) { reg 123 drivers/dma/lpc18xx-dmamux.c return PTR_ERR(dmamux->reg); reg 169 drivers/dma/mediatek/mtk-cqdma.c static u32 mtk_dma_read(struct mtk_cqdma_pchan *pc, u32 reg) reg 171 drivers/dma/mediatek/mtk-cqdma.c return readl(pc->base + reg); reg 174 drivers/dma/mediatek/mtk-cqdma.c static void mtk_dma_write(struct mtk_cqdma_pchan *pc, u32 reg, u32 val) reg 176 drivers/dma/mediatek/mtk-cqdma.c writel_relaxed(val, pc->base + reg); reg 179 drivers/dma/mediatek/mtk-cqdma.c static void mtk_dma_rmw(struct mtk_cqdma_pchan *pc, u32 reg, reg 184 drivers/dma/mediatek/mtk-cqdma.c val = mtk_dma_read(pc, reg); reg 187 drivers/dma/mediatek/mtk-cqdma.c mtk_dma_write(pc, reg, val); reg 190 drivers/dma/mediatek/mtk-cqdma.c static void mtk_dma_set(struct mtk_cqdma_pchan *pc, u32 reg, u32 val) reg 192 drivers/dma/mediatek/mtk-cqdma.c mtk_dma_rmw(pc, reg, 0, val); reg 195 drivers/dma/mediatek/mtk-cqdma.c static void mtk_dma_clr(struct mtk_cqdma_pchan *pc, u32 reg, u32 val) reg 197 drivers/dma/mediatek/mtk-cqdma.c mtk_dma_rmw(pc, reg, val, 0); reg 269 drivers/dma/mediatek/mtk-hsdma.c static u32 mtk_dma_read(struct mtk_hsdma_device *hsdma, u32 reg) reg 271 drivers/dma/mediatek/mtk-hsdma.c return readl(hsdma->base + reg); reg 274 drivers/dma/mediatek/mtk-hsdma.c static void mtk_dma_write(struct mtk_hsdma_device *hsdma, u32 reg, u32 val) reg 276 drivers/dma/mediatek/mtk-hsdma.c writel(val, hsdma->base + reg); reg 279 drivers/dma/mediatek/mtk-hsdma.c static void mtk_dma_rmw(struct mtk_hsdma_device *hsdma, u32 reg, reg 284 drivers/dma/mediatek/mtk-hsdma.c val = mtk_dma_read(hsdma, reg); reg 287 drivers/dma/mediatek/mtk-hsdma.c mtk_dma_write(hsdma, reg, val); reg 290 drivers/dma/mediatek/mtk-hsdma.c static void mtk_dma_set(struct mtk_hsdma_device *hsdma, u32 reg, u32 val) reg 292 drivers/dma/mediatek/mtk-hsdma.c mtk_dma_rmw(hsdma, reg, 0, val); reg 295 drivers/dma/mediatek/mtk-hsdma.c static void mtk_dma_clr(struct mtk_hsdma_device *hsdma, u32 reg, u32 val) reg 297 drivers/dma/mediatek/mtk-hsdma.c mtk_dma_rmw(hsdma, reg, val, 0); reg 122 drivers/dma/mediatek/mtk-uart-apdma.c unsigned int reg, unsigned int val) reg 124 drivers/dma/mediatek/mtk-uart-apdma.c writel(val, c->base + reg); reg 127 drivers/dma/mediatek/mtk-uart-apdma.c static unsigned int mtk_uart_apdma_read(struct mtk_chan *c, unsigned int reg) reg 129 drivers/dma/mediatek/mtk-uart-apdma.c return readl(c->base + reg); reg 172 drivers/dma/mic_x100_dma.h static inline u32 mic_dma_read_reg(struct mic_dma_chan *ch, u32 reg) reg 175 drivers/dma/mic_x100_dma.h ch->ch_num * MIC_DMA_SBOX_CHAN_OFF + reg); reg 178 drivers/dma/mic_x100_dma.h static inline void mic_dma_write_reg(struct mic_dma_chan *ch, u32 reg, u32 val) reg 181 drivers/dma/mic_x100_dma.h ch->ch_num * MIC_DMA_SBOX_CHAN_OFF + reg); reg 147 drivers/dma/mmp_pdma.c u32 reg = (phy->idx << 4) + DDADR; reg 149 drivers/dma/mmp_pdma.c writel(addr, phy->base + reg); reg 154 drivers/dma/mmp_pdma.c u32 reg, dalgn; reg 159 drivers/dma/mmp_pdma.c reg = DRCMR(phy->vchan->drcmr); reg 160 drivers/dma/mmp_pdma.c writel(DRCMR_MAPVLD | phy->idx, phy->base + reg); reg 169 drivers/dma/mmp_pdma.c reg = (phy->idx << 2) + DCSR; reg 170 drivers/dma/mmp_pdma.c writel(readl(phy->base + reg) | DCSR_RUN, phy->base + reg); reg 175 drivers/dma/mmp_pdma.c u32 reg; reg 180 drivers/dma/mmp_pdma.c reg = (phy->idx << 2) + DCSR; reg 181 drivers/dma/mmp_pdma.c writel(readl(phy->base + reg) & ~DCSR_RUN, phy->base + reg); reg 188 drivers/dma/mmp_pdma.c u32 reg = (phy->idx << 2) + DCSR; reg 194 drivers/dma/mmp_pdma.c dcsr = readl(phy->base + reg); reg 195 drivers/dma/mmp_pdma.c writel(dcsr, phy->base + reg); reg 278 drivers/dma/mmp_pdma.c u32 reg; reg 284 drivers/dma/mmp_pdma.c reg = DRCMR(pchan->drcmr); reg 285 drivers/dma/mmp_pdma.c writel(0, pchan->phy->base + reg); reg 290 drivers/dma/mmp_tdma.c u32 reg = readl(tdmac->reg_base + TDISR); reg 292 drivers/dma/mmp_tdma.c if (reg & TDISR_COMP) { reg 294 drivers/dma/mmp_tdma.c reg &= ~TDISR_COMP; reg 295 drivers/dma/mmp_tdma.c writel(reg, tdmac->reg_base + TDISR); reg 304 drivers/dma/mmp_tdma.c size_t reg; reg 307 drivers/dma/mmp_tdma.c reg = __raw_readl(tdmac->reg_base + TDSAR); reg 308 drivers/dma/mmp_tdma.c reg -= tdmac->desc_arr[0].src_addr; reg 310 drivers/dma/mmp_tdma.c reg = __raw_readl(tdmac->reg_base + TDDAR); reg 311 drivers/dma/mmp_tdma.c reg -= tdmac->desc_arr[0].dst_addr; reg 315 drivers/dma/mmp_tdma.c return reg; reg 258 drivers/dma/mv_xor_v2.c u32 reg; reg 261 drivers/dma/mv_xor_v2.c reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_THRD_OFF); reg 262 drivers/dma/mv_xor_v2.c reg &= ~MV_XOR_V2_DMA_IMSG_THRD_MASK; reg 263 drivers/dma/mv_xor_v2.c reg |= MV_XOR_V2_DONE_IMSG_THRD; reg 264 drivers/dma/mv_xor_v2.c reg |= MV_XOR_V2_DMA_IMSG_TIMER_EN; reg 265 drivers/dma/mv_xor_v2.c writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_THRD_OFF); reg 268 drivers/dma/mv_xor_v2.c reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_TMOT); reg 269 drivers/dma/mv_xor_v2.c reg &= ~MV_XOR_V2_DMA_IMSG_TIMER_THRD_MASK; reg 270 drivers/dma/mv_xor_v2.c reg |= MV_XOR_V2_TIMER_THRD; reg 271 drivers/dma/mv_xor_v2.c writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_TMOT); reg 278 drivers/dma/mv_xor_v2.c u32 reg; reg 280 drivers/dma/mv_xor_v2.c reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_DONE_OFF); reg 282 drivers/dma/mv_xor_v2.c ndescs = ((reg >> MV_XOR_V2_DMA_DESQ_DONE_PENDING_SHIFT) & reg 536 drivers/dma/mv_xor_v2.c u32 reg; reg 538 drivers/dma/mv_xor_v2.c reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_DONE_OFF); reg 541 drivers/dma/mv_xor_v2.c *pending_ptr = ((reg >> MV_XOR_V2_DMA_DESQ_DONE_READ_PTR_SHIFT) & reg 545 drivers/dma/mv_xor_v2.c return ((reg >> MV_XOR_V2_DMA_DESQ_DONE_PENDING_SHIFT) & reg 627 drivers/dma/mv_xor_v2.c u32 reg; reg 648 drivers/dma/mv_xor_v2.c reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_ARATTR_OFF); reg 649 drivers/dma/mv_xor_v2.c reg &= ~MV_XOR_V2_DMA_DESQ_ATTR_CACHE_MASK; reg 650 drivers/dma/mv_xor_v2.c reg |= MV_XOR_V2_DMA_DESQ_ATTR_OUTER_SHAREABLE | reg 652 drivers/dma/mv_xor_v2.c writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_ARATTR_OFF); reg 654 drivers/dma/mv_xor_v2.c reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_AWATTR_OFF); reg 655 drivers/dma/mv_xor_v2.c reg &= ~MV_XOR_V2_DMA_DESQ_ATTR_CACHE_MASK; reg 656 drivers/dma/mv_xor_v2.c reg |= MV_XOR_V2_DMA_DESQ_ATTR_OUTER_SHAREABLE | reg 658 drivers/dma/mv_xor_v2.c writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_AWATTR_OFF); reg 667 drivers/dma/mv_xor_v2.c reg = ((MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_RD_VAL << reg 675 drivers/dma/mv_xor_v2.c writel(reg, xor_dev->glob_base + MV_XOR_V2_GLOB_BW_CTRL); reg 678 drivers/dma/mv_xor_v2.c reg = readl(xor_dev->glob_base + MV_XOR_V2_GLOB_PAUSE); reg 679 drivers/dma/mv_xor_v2.c reg |= MV_XOR_V2_GLOB_PAUSE_AXI_TIME_DIS_VAL; reg 680 drivers/dma/mv_xor_v2.c writel(reg, xor_dev->glob_base + MV_XOR_V2_GLOB_PAUSE); reg 229 drivers/dma/owl-dma.c static void pchan_update(struct owl_dma_pchan *pchan, u32 reg, reg 234 drivers/dma/owl-dma.c regval = readl(pchan->base + reg); reg 241 drivers/dma/owl-dma.c writel(val, pchan->base + reg); reg 244 drivers/dma/owl-dma.c static void pchan_writel(struct owl_dma_pchan *pchan, u32 reg, u32 data) reg 246 drivers/dma/owl-dma.c writel(data, pchan->base + reg); reg 249 drivers/dma/owl-dma.c static u32 pchan_readl(struct owl_dma_pchan *pchan, u32 reg) reg 251 drivers/dma/owl-dma.c return readl(pchan->base + reg); reg 254 drivers/dma/owl-dma.c static void dma_update(struct owl_dma *od, u32 reg, u32 val, bool state) reg 258 drivers/dma/owl-dma.c regval = readl(od->base + reg); reg 265 drivers/dma/owl-dma.c writel(val, od->base + reg); reg 268 drivers/dma/owl-dma.c static void dma_writel(struct owl_dma *od, u32 reg, u32 data) reg 270 drivers/dma/owl-dma.c writel(data, od->base + reg); reg 273 drivers/dma/owl-dma.c static u32 dma_readl(struct owl_dma *od, u32 reg) reg 275 drivers/dma/owl-dma.c return readl(od->base + reg); reg 577 drivers/dma/pch_dma.c dma_addr_t reg; reg 586 drivers/dma/pch_dma.c reg = pd_slave->rx_reg; reg 588 drivers/dma/pch_dma.c reg = pd_slave->tx_reg; reg 601 drivers/dma/pch_dma.c desc->regs.dev_addr = reg; reg 4354 drivers/dma/ppc4xx/adma.c u32 reg; reg 4358 drivers/dma/ppc4xx/adma.c reg = 0x4d; reg 4360 drivers/dma/ppc4xx/adma.c reg = dcr_read(ppc440spe_mq_dcr_host, DCRN_MQ0_CFBHL); reg 4361 drivers/dma/ppc4xx/adma.c reg >>= MQ0_CFBHL_POLY; reg 4362 drivers/dma/ppc4xx/adma.c reg &= 0xFF; reg 4366 drivers/dma/ppc4xx/adma.c "uses 0x1%02x polynomial.\n", reg); reg 4373 drivers/dma/ppc4xx/adma.c unsigned long reg, val; reg 4390 drivers/dma/ppc4xx/adma.c reg = dcr_read(ppc440spe_mq_dcr_host, DCRN_MQ0_CFBHL); reg 4391 drivers/dma/ppc4xx/adma.c reg &= ~(0xFF << MQ0_CFBHL_POLY); reg 4392 drivers/dma/ppc4xx/adma.c reg |= val << MQ0_CFBHL_POLY; reg 4393 drivers/dma/ppc4xx/adma.c dcr_write(ppc440spe_mq_dcr_host, DCRN_MQ0_CFBHL, reg); reg 411 drivers/dma/pxa_dma.c u32 reg; reg 420 drivers/dma/pxa_dma.c reg = pxad_drcmr(chan->drcmr); reg 421 drivers/dma/pxa_dma.c writel_relaxed(0, chan->phy->base + reg); reg 453 drivers/dma/pxa_dma.c u32 reg, dalgn; reg 464 drivers/dma/pxa_dma.c reg = pxad_drcmr(phy->vchan->drcmr); reg 465 drivers/dma/pxa_dma.c writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg); reg 409 drivers/dma/qcom/bam_dma.c enum bam_reg reg) reg 411 drivers/dma/qcom/bam_dma.c const struct reg_offset_data r = bdev->layout[reg]; reg 403 drivers/dma/sa11x0-dma.c unsigned reg; reg 410 drivers/dma/sa11x0-dma.c reg = DMA_DBSA; reg 412 drivers/dma/sa11x0-dma.c reg = DMA_DBSB; reg 414 drivers/dma/sa11x0-dma.c return readl_relaxed(p->base + reg); reg 296 drivers/dma/sh/rcar-dmac.c static void rcar_dmac_write(struct rcar_dmac *dmac, u32 reg, u32 data) reg 298 drivers/dma/sh/rcar-dmac.c if (reg == RCAR_DMAOR) reg 299 drivers/dma/sh/rcar-dmac.c writew(data, dmac->iomem + reg); reg 301 drivers/dma/sh/rcar-dmac.c writel(data, dmac->iomem + reg); reg 304 drivers/dma/sh/rcar-dmac.c static u32 rcar_dmac_read(struct rcar_dmac *dmac, u32 reg) reg 306 drivers/dma/sh/rcar-dmac.c if (reg == RCAR_DMAOR) reg 307 drivers/dma/sh/rcar-dmac.c return readw(dmac->iomem + reg); reg 309 drivers/dma/sh/rcar-dmac.c return readl(dmac->iomem + reg); reg 312 drivers/dma/sh/rcar-dmac.c static u32 rcar_dmac_chan_read(struct rcar_dmac_chan *chan, u32 reg) reg 314 drivers/dma/sh/rcar-dmac.c if (reg == RCAR_DMARS) reg 315 drivers/dma/sh/rcar-dmac.c return readw(chan->iomem + reg); reg 317 drivers/dma/sh/rcar-dmac.c return readl(chan->iomem + reg); reg 320 drivers/dma/sh/rcar-dmac.c static void rcar_dmac_chan_write(struct rcar_dmac_chan *chan, u32 reg, u32 data) reg 322 drivers/dma/sh/rcar-dmac.c if (reg == RCAR_DMARS) reg 323 drivers/dma/sh/rcar-dmac.c writew(data, chan->iomem + reg); reg 325 drivers/dma/sh/rcar-dmac.c writel(data, chan->iomem + reg); reg 78 drivers/dma/sh/shdmac.c static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg) reg 80 drivers/dma/sh/shdmac.c __raw_writel(data, sh_dc->base + reg); reg 83 drivers/dma/sh/shdmac.c static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg) reg 85 drivers/dma/sh/shdmac.c return __raw_readl(sh_dc->base + reg); reg 151 drivers/dma/sh/usb-dmac.c static void usb_dmac_write(struct usb_dmac *dmac, u32 reg, u32 data) reg 153 drivers/dma/sh/usb-dmac.c writel(data, dmac->iomem + reg); reg 156 drivers/dma/sh/usb-dmac.c static u32 usb_dmac_read(struct usb_dmac *dmac, u32 reg) reg 158 drivers/dma/sh/usb-dmac.c return readl(dmac->iomem + reg); reg 161 drivers/dma/sh/usb-dmac.c static u32 usb_dmac_chan_read(struct usb_dmac_chan *chan, u32 reg) reg 163 drivers/dma/sh/usb-dmac.c return readl(chan->iomem + reg); reg 166 drivers/dma/sh/usb-dmac.c static void usb_dmac_chan_write(struct usb_dmac_chan *chan, u32 reg, u32 data) reg 168 drivers/dma/sh/usb-dmac.c writel(data, chan->iomem + reg); reg 272 drivers/dma/sirf-dma.c void __iomem *reg; reg 278 drivers/dma/sirf-dma.c reg = sdma->base + SIRFSOC_DMA_CH_INT; reg 281 drivers/dma/sirf-dma.c writel_relaxed(1 << ch, reg); reg 302 drivers/dma/sirf-dma.c reg = sdma->base + SIRFSOC_DMA_INT_ATLAS7; reg 303 drivers/dma/sirf-dma.c writel_relaxed(SIRFSOC_DMA_INT_ALL_ATLAS7, reg); reg 238 drivers/dma/sprd-dma.c static void sprd_dma_glb_update(struct sprd_dma_dev *sdev, u32 reg, reg 241 drivers/dma/sprd-dma.c u32 orig = readl(sdev->glb_base + reg); reg 245 drivers/dma/sprd-dma.c writel(tmp, sdev->glb_base + reg); reg 248 drivers/dma/sprd-dma.c static void sprd_dma_chn_update(struct sprd_dma_chn *schan, u32 reg, reg 251 drivers/dma/sprd-dma.c u32 orig = readl(schan->chn_base + reg); reg 255 drivers/dma/sprd-dma.c writel(tmp, schan->chn_base + reg); reg 280 drivers/dma/ste_dma40.c unsigned int reg; reg 286 drivers/dma/ste_dma40.c { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL}, reg 289 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF}, reg 290 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF}, reg 291 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF}, reg 292 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF}, reg 293 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF}, reg 294 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF}, reg 295 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF}, reg 296 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF}, reg 297 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF}, reg 298 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF}, reg 299 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF}, reg 300 drivers/dma/ste_dma40.c { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF} reg 304 drivers/dma/ste_dma40.c { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL}, reg 307 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCMIS1, .val = 0xFFFFFFFF}, reg 308 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCMIS2, .val = 0xFFFFFFFF}, reg 309 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCMIS3, .val = 0xFFFFFFFF}, reg 310 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCMIS4, .val = 0xFFFFFFFF}, reg 311 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCMIS5, .val = 0xFFFFFFFF}, reg 312 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCICR1, .val = 0xFFFFFFFF}, reg 313 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCICR2, .val = 0xFFFFFFFF}, reg 314 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCICR3, .val = 0xFFFFFFFF}, reg 315 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCICR4, .val = 0xFFFFFFFF}, reg 316 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCICR5, .val = 0xFFFFFFFF}, reg 317 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCTIS1, .val = 0xFFFFFFFF}, reg 318 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCTIS2, .val = 0xFFFFFFFF}, reg 319 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCTIS3, .val = 0xFFFFFFFF}, reg 320 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCTIS4, .val = 0xFFFFFFFF}, reg 321 drivers/dma/ste_dma40.c { .reg = D40_DREG_CLCTIS5, .val = 0xFFFFFFFF} reg 1157 drivers/dma/ste_dma40.c int reg) reg 1159 drivers/dma/ste_dma40.c void __iomem *addr = chan_base(d40c) + reg; reg 1225 drivers/dma/ste_dma40.c __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D', reg 3332 drivers/dma/ste_dma40.c base->virtbase + dma_init_reg[i].reg); reg 236 drivers/dma/stm32-dma.c static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg) reg 238 drivers/dma/stm32-dma.c return readl_relaxed(dmadev->base + reg); reg 241 drivers/dma/stm32-dma.c static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val) reg 243 drivers/dma/stm32-dma.c writel_relaxed(val, dmadev->base + reg); reg 535 drivers/dma/stm32-dma.c struct stm32_dma_chan_reg *reg; reg 556 drivers/dma/stm32-dma.c reg = &sg_req->chan_reg; reg 558 drivers/dma/stm32-dma.c stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); reg 559 drivers/dma/stm32-dma.c stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar); reg 560 drivers/dma/stm32-dma.c stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar); reg 561 drivers/dma/stm32-dma.c stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr); reg 562 drivers/dma/stm32-dma.c stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar); reg 563 drivers/dma/stm32-dma.c stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr); reg 578 drivers/dma/stm32-dma.c reg->dma_scr |= STM32_DMA_SCR_EN; reg 579 drivers/dma/stm32-dma.c stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); reg 50 drivers/dma/stm32-dmamux.c static inline u32 stm32_dmamux_read(void __iomem *iomem, u32 reg) reg 52 drivers/dma/stm32-dmamux.c return readl_relaxed(iomem + reg); reg 55 drivers/dma/stm32-dmamux.c static inline void stm32_dmamux_write(void __iomem *iomem, u32 reg, u32 val) reg 57 drivers/dma/stm32-dmamux.c writel_relaxed(val, iomem + reg); reg 311 drivers/dma/stm32-mdma.c static u32 stm32_mdma_read(struct stm32_mdma_device *dmadev, u32 reg) reg 313 drivers/dma/stm32-mdma.c return readl_relaxed(dmadev->base + reg); reg 316 drivers/dma/stm32-mdma.c static void stm32_mdma_write(struct stm32_mdma_device *dmadev, u32 reg, u32 val) reg 318 drivers/dma/stm32-mdma.c writel_relaxed(val, dmadev->base + reg); reg 321 drivers/dma/stm32-mdma.c static void stm32_mdma_set_bits(struct stm32_mdma_device *dmadev, u32 reg, reg 324 drivers/dma/stm32-mdma.c void __iomem *addr = dmadev->base + reg; reg 329 drivers/dma/stm32-mdma.c static void stm32_mdma_clr_bits(struct stm32_mdma_device *dmadev, u32 reg, reg 332 drivers/dma/stm32-mdma.c void __iomem *addr = dmadev->base + reg; reg 430 drivers/dma/stm32-mdma.c u32 ccr, cisr, id, reg; reg 434 drivers/dma/stm32-mdma.c reg = STM32_MDMA_CCR(id); reg 437 drivers/dma/stm32-mdma.c stm32_mdma_clr_bits(dmadev, reg, STM32_MDMA_CCR_IRQ_MASK); reg 439 drivers/dma/stm32-mdma.c ccr = stm32_mdma_read(dmadev, reg); reg 441 drivers/dma/stm32-mdma.c stm32_mdma_clr_bits(dmadev, reg, STM32_MDMA_CCR_EN); reg 1122 drivers/dma/stm32-mdma.c u32 status, reg; reg 1157 drivers/dma/stm32-mdma.c reg = STM32_MDMA_CCR(id); reg 1158 drivers/dma/stm32-mdma.c stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CCR_SWRQ); reg 1207 drivers/dma/stm32-mdma.c u32 status, reg; reg 1224 drivers/dma/stm32-mdma.c reg = STM32_MDMA_CCR(chan->id); reg 1225 drivers/dma/stm32-mdma.c stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CCR_EN); reg 1229 drivers/dma/stm32-mdma.c stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CCR_SWRQ); reg 1347 drivers/dma/stm32-mdma.c u32 reg, id, ien, status, flag; reg 1389 drivers/dma/stm32-mdma.c reg = STM32_MDMA_CIFCR(chan->id); reg 1396 drivers/dma/stm32-mdma.c stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CTEIF); reg 1400 drivers/dma/stm32-mdma.c stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CCTCIF); reg 1405 drivers/dma/stm32-mdma.c stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CBRTIF); reg 1409 drivers/dma/stm32-mdma.c stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CBTIF); reg 1419 drivers/dma/stm32-mdma.c stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CLTCIF); reg 287 drivers/dma/sun4i-dma.c u32 reg; reg 293 drivers/dma/sun4i-dma.c reg = readl_relaxed(priv->base + SUN4I_DMA_IRQ_ENABLE_REG); reg 296 drivers/dma/sun4i-dma.c reg |= BIT(pchan_number * 2); reg 298 drivers/dma/sun4i-dma.c reg &= ~BIT(pchan_number * 2); reg 301 drivers/dma/sun4i-dma.c reg |= BIT(pchan_number * 2 + 1); reg 303 drivers/dma/sun4i-dma.c reg &= ~BIT(pchan_number * 2 + 1); reg 305 drivers/dma/sun4i-dma.c writel_relaxed(reg, priv->base + SUN4I_DMA_IRQ_ENABLE_REG); reg 244 drivers/dma/sun6i-dma.c phys_addr_t reg = virt_to_phys(pchan->base); reg 255 drivers/dma/sun6i-dma.c pchan->idx, ®, reg 232 drivers/dma/tegra20-apb-dma.c static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val) reg 234 drivers/dma/tegra20-apb-dma.c writel(val, tdma->base_addr + reg); reg 237 drivers/dma/tegra20-apb-dma.c static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg) reg 239 drivers/dma/tegra20-apb-dma.c return readl(tdma->base_addr + reg); reg 243 drivers/dma/tegra20-apb-dma.c u32 reg, u32 val) reg 245 drivers/dma/tegra20-apb-dma.c writel(val, tdc->chan_addr + reg); reg 248 drivers/dma/tegra20-apb-dma.c static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg) reg 250 drivers/dma/tegra20-apb-dma.c return readl(tdc->chan_addr + reg); reg 170 drivers/dma/tegra210-adma.c static inline void tdma_write(struct tegra_adma *tdma, u32 reg, u32 val) reg 172 drivers/dma/tegra210-adma.c writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg); reg 175 drivers/dma/tegra210-adma.c static inline u32 tdma_read(struct tegra_adma *tdma, u32 reg) reg 177 drivers/dma/tegra210-adma.c return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg); reg 180 drivers/dma/tegra210-adma.c static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32 val) reg 182 drivers/dma/tegra210-adma.c writel(val, tdc->chan_addr + reg); reg 185 drivers/dma/tegra210-adma.c static inline u32 tdma_ch_read(struct tegra_adma_chan *tdc, u32 reg) reg 187 drivers/dma/tegra210-adma.c return readl(tdc->chan_addr + reg); reg 436 drivers/dma/ti/cppi41.c u32 reg; reg 440 drivers/dma/ti/cppi41.c reg = GCR_CHAN_ENABLE; reg 442 drivers/dma/ti/cppi41.c reg |= GCR_STARV_RETRY; reg 443 drivers/dma/ti/cppi41.c reg |= GCR_DESC_TYPE_HOST; reg 444 drivers/dma/ti/cppi41.c reg |= c->q_comp_num; reg 447 drivers/dma/ti/cppi41.c cppi_writel(reg, c->gcr_reg); reg 470 drivers/dma/ti/cppi41.c reg = (sizeof(struct cppi41_desc) - 24) / 4; reg 471 drivers/dma/ti/cppi41.c reg |= desc_phys; reg 472 drivers/dma/ti/cppi41.c cppi_writel(reg, cdd->qmgr_mem + QMGR_QUEUE_D(c->q_num)); reg 518 drivers/dma/ti/cppi41.c u32 reg; reg 520 drivers/dma/ti/cppi41.c reg = DESC_TYPE_HOST << DESC_TYPE; reg 521 drivers/dma/ti/cppi41.c reg |= length; reg 523 drivers/dma/ti/cppi41.c return reg; reg 528 drivers/dma/ti/cppi41.c u32 reg; reg 530 drivers/dma/ti/cppi41.c reg = 0; reg 532 drivers/dma/ti/cppi41.c return reg; reg 537 drivers/dma/ti/cppi41.c u32 reg; reg 539 drivers/dma/ti/cppi41.c reg = DESC_TYPE_USB; reg 540 drivers/dma/ti/cppi41.c reg |= c->q_comp_num; reg 542 drivers/dma/ti/cppi41.c return reg; reg 547 drivers/dma/ti/cppi41.c u32 reg; reg 550 drivers/dma/ti/cppi41.c reg = length; reg 552 drivers/dma/ti/cppi41.c return reg; reg 557 drivers/dma/ti/cppi41.c u32 reg; reg 560 drivers/dma/ti/cppi41.c reg = DESC_PD_COMPLETE; reg 561 drivers/dma/ti/cppi41.c reg |= length; reg 563 drivers/dma/ti/cppi41.c return reg; reg 568 drivers/dma/ti/cppi41.c u32 reg; reg 570 drivers/dma/ti/cppi41.c reg = addr; reg 572 drivers/dma/ti/cppi41.c return reg; reg 577 drivers/dma/ti/cppi41.c u32 reg; reg 579 drivers/dma/ti/cppi41.c reg = 0; reg 581 drivers/dma/ti/cppi41.c return reg; reg 646 drivers/dma/ti/cppi41.c u32 reg; reg 660 drivers/dma/ti/cppi41.c reg = (sizeof(struct cppi41_desc) - 24) / 4; reg 661 drivers/dma/ti/cppi41.c reg |= td_desc_phys; reg 662 drivers/dma/ti/cppi41.c cppi_writel(reg, cdd->qmgr_mem + reg 665 drivers/dma/ti/cppi41.c reg = GCR_CHAN_ENABLE; reg 667 drivers/dma/ti/cppi41.c reg |= GCR_STARV_RETRY; reg 668 drivers/dma/ti/cppi41.c reg |= GCR_DESC_TYPE_HOST; reg 669 drivers/dma/ti/cppi41.c reg |= cdd->td_queue.complete; reg 671 drivers/dma/ti/cppi41.c reg |= GCR_TEARDOWN; reg 672 drivers/dma/ti/cppi41.c cppi_writel(reg, c->gcr_reg); reg 854 drivers/dma/ti/cppi41.c u32 reg; reg 868 drivers/dma/ti/cppi41.c reg = idx << QMGR_MEMCTRL_IDX_SH; reg 869 drivers/dma/ti/cppi41.c reg |= (ilog2(desc_size) - 5) << QMGR_MEMCTRL_DESC_SH; reg 870 drivers/dma/ti/cppi41.c reg |= ilog2(ALLOC_DECS_NUM) - 5; reg 879 drivers/dma/ti/cppi41.c cppi_writel(reg, cdd->qmgr_mem + QMGR_MEMCTRL(i)); reg 890 drivers/dma/ti/cppi41.c u32 reg; reg 896 drivers/dma/ti/cppi41.c reg = SCHED_ENTRY0_CHAN(ch); reg 897 drivers/dma/ti/cppi41.c reg |= SCHED_ENTRY1_CHAN(ch) | SCHED_ENTRY1_IS_RX; reg 899 drivers/dma/ti/cppi41.c reg |= SCHED_ENTRY2_CHAN(ch + 1); reg 900 drivers/dma/ti/cppi41.c reg |= SCHED_ENTRY3_CHAN(ch + 1) | SCHED_ENTRY3_IS_RX; reg 901 drivers/dma/ti/cppi41.c cppi_writel(reg, cdd->sched_mem + DMA_SCHED_WORD(word)); reg 904 drivers/dma/ti/cppi41.c reg = cdd->n_chans * 2 - 1; reg 905 drivers/dma/ti/cppi41.c reg |= DMA_SCHED_CTRL_EN; reg 906 drivers/dma/ti/cppi41.c cppi_writel(reg, cdd->sched_mem + DMA_SCHED_CTRL); reg 329 drivers/dma/ti/omap-dma.c static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val) reg 331 drivers/dma/ti/omap-dma.c const struct omap_dma_reg *r = od->reg_map + reg; reg 338 drivers/dma/ti/omap-dma.c static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg) reg 340 drivers/dma/ti/omap-dma.c const struct omap_dma_reg *r = od->reg_map + reg; reg 347 drivers/dma/ti/omap-dma.c static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val) reg 349 drivers/dma/ti/omap-dma.c const struct omap_dma_reg *r = c->reg_map + reg; reg 354 drivers/dma/ti/omap-dma.c static unsigned omap_dma_chan_read(struct omap_chan *c, unsigned reg) reg 356 drivers/dma/ti/omap-dma.c const struct omap_dma_reg *r = c->reg_map + reg; reg 749 drivers/dma/ti/omap-dma.c static uint32_t omap_dma_chan_read_3_3(struct omap_chan *c, unsigned reg) reg 754 drivers/dma/ti/omap-dma.c val = omap_dma_chan_read(c, reg); reg 756 drivers/dma/ti/omap-dma.c val = omap_dma_chan_read(c, reg); reg 456 drivers/dma/xilinx/xilinx_dma.c #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \ reg 457 drivers/dma/xilinx/xilinx_dma.c readl_poll_timeout(chan->xdev->regs + chan->ctrl_offset + reg, val, \ reg 461 drivers/dma/xilinx/xilinx_dma.c static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg) reg 463 drivers/dma/xilinx/xilinx_dma.c return ioread32(chan->xdev->regs + reg); reg 466 drivers/dma/xilinx/xilinx_dma.c static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value) reg 468 drivers/dma/xilinx/xilinx_dma.c iowrite32(value, chan->xdev->regs + reg); reg 471 drivers/dma/xilinx/xilinx_dma.c static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg, reg 474 drivers/dma/xilinx/xilinx_dma.c dma_write(chan, chan->desc_offset + reg, value); reg 477 drivers/dma/xilinx/xilinx_dma.c static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg) reg 479 drivers/dma/xilinx/xilinx_dma.c return dma_read(chan, chan->ctrl_offset + reg); reg 482 drivers/dma/xilinx/xilinx_dma.c static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg, reg 485 drivers/dma/xilinx/xilinx_dma.c dma_write(chan, chan->ctrl_offset + reg, value); reg 488 drivers/dma/xilinx/xilinx_dma.c static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg, reg 491 drivers/dma/xilinx/xilinx_dma.c dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr); reg 494 drivers/dma/xilinx/xilinx_dma.c static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg, reg 497 drivers/dma/xilinx/xilinx_dma.c dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set); reg 511 drivers/dma/xilinx/xilinx_dma.c static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg, reg 515 drivers/dma/xilinx/xilinx_dma.c writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg); reg 518 drivers/dma/xilinx/xilinx_dma.c writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4); reg 521 drivers/dma/xilinx/xilinx_dma.c static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value) reg 523 drivers/dma/xilinx/xilinx_dma.c lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg); reg 526 drivers/dma/xilinx/xilinx_dma.c static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg, reg 530 drivers/dma/xilinx/xilinx_dma.c dma_writeq(chan, reg, addr); reg 532 drivers/dma/xilinx/xilinx_dma.c dma_ctrl_write(chan, reg, addr); reg 1102 drivers/dma/xilinx/xilinx_dma.c u32 reg, j; reg 1121 drivers/dma/xilinx/xilinx_dma.c reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP); reg 1122 drivers/dma/xilinx/xilinx_dma.c reg &= ~XILINX_VDMA_ENABLE_VERTICAL_FLIP; reg 1123 drivers/dma/xilinx/xilinx_dma.c reg |= config->vflip_en; reg 1125 drivers/dma/xilinx/xilinx_dma.c reg); reg 1128 drivers/dma/xilinx/xilinx_dma.c reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); reg 1131 drivers/dma/xilinx/xilinx_dma.c reg |= XILINX_DMA_DMACR_FRAMECNT_EN; reg 1133 drivers/dma/xilinx/xilinx_dma.c reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN; reg 1137 drivers/dma/xilinx/xilinx_dma.c reg &= ~XILINX_DMA_DMACR_CIRC_EN; reg 1139 drivers/dma/xilinx/xilinx_dma.c reg |= XILINX_DMA_DMACR_CIRC_EN; reg 1141 drivers/dma/xilinx/xilinx_dma.c dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); reg 1144 drivers/dma/xilinx/xilinx_dma.c reg = dma_read(chan, XILINX_DMA_REG_PARK_PTR); reg 1146 drivers/dma/xilinx/xilinx_dma.c reg &= ~XILINX_DMA_PARK_PTR_RD_REF_MASK; reg 1147 drivers/dma/xilinx/xilinx_dma.c reg |= j << XILINX_DMA_PARK_PTR_RD_REF_SHIFT; reg 1149 drivers/dma/xilinx/xilinx_dma.c reg &= ~XILINX_DMA_PARK_PTR_WR_REF_MASK; reg 1150 drivers/dma/xilinx/xilinx_dma.c reg |= j << XILINX_DMA_PARK_PTR_WR_REF_SHIFT; reg 1152 drivers/dma/xilinx/xilinx_dma.c dma_write(chan, XILINX_DMA_REG_PARK_PTR, reg); reg 1277 drivers/dma/xilinx/xilinx_dma.c u32 reg; reg 1295 drivers/dma/xilinx/xilinx_dma.c reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); reg 1298 drivers/dma/xilinx/xilinx_dma.c reg &= ~XILINX_DMA_CR_COALESCE_MAX; reg 1299 drivers/dma/xilinx/xilinx_dma.c reg |= chan->desc_pendingcount << reg 1301 drivers/dma/xilinx/xilinx_dma.c dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); reg 1885 drivers/dma/xilinx/xilinx_dma.c u32 reg; reg 1948 drivers/dma/xilinx/xilinx_dma.c reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); reg 1949 drivers/dma/xilinx/xilinx_dma.c reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK; reg 1950 drivers/dma/xilinx/xilinx_dma.c dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); reg 2063 drivers/dma/xilinx/xilinx_dma.c u32 reg; reg 2081 drivers/dma/xilinx/xilinx_dma.c reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); reg 2082 drivers/dma/xilinx/xilinx_dma.c reg &= ~XILINX_DMA_CR_CYCLIC_BD_EN_MASK; reg 2083 drivers/dma/xilinx/xilinx_dma.c dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); reg 256 drivers/dma/xilinx/zynqmp_dma.c static inline void zynqmp_dma_writeq(struct zynqmp_dma_chan *chan, u32 reg, reg 259 drivers/dma/xilinx/zynqmp_dma.c lo_hi_writeq(value, chan->regs + reg); reg 124 drivers/edac/altera_edac.c u32 reg, read_reg; reg 172 drivers/edac/altera_edac.c reg = READ_ONCE(ptemp[0]); reg 178 drivers/edac/altera_edac.c reg, read_reg); reg 517 drivers/edac/altera_edac.c static int s10_protected_reg_write(void *context, unsigned int reg, reg 523 drivers/edac/altera_edac.c arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, offset + reg, val, 0, 0, reg 539 drivers/edac/altera_edac.c static int s10_protected_reg_read(void *context, unsigned int reg, reg 545 drivers/edac/altera_edac.c arm_smccc_smc(INTEL_SIP_SMC_REG_READ, offset + reg, 0, 0, 0, reg 92 drivers/edac/amd64_edac.c u32 reg = 0; reg 94 drivers/edac/amd64_edac.c amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); reg 95 drivers/edac/amd64_edac.c reg &= (pvt->model == 0x30) ? ~3 : ~1; reg 96 drivers/edac/amd64_edac.c reg |= dct; reg 97 drivers/edac/amd64_edac.c amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); reg 3050 drivers/edac/amd64_edac.c struct msr *reg = per_cpu_ptr(msrs, cpu); reg 3051 drivers/edac/amd64_edac.c nbe = reg->l & MSR_MCGCTL_NBE; reg 3054 drivers/edac/amd64_edac.c cpu, reg->q, reg 3083 drivers/edac/amd64_edac.c struct msr *reg = per_cpu_ptr(msrs, cpu); reg 3086 drivers/edac/amd64_edac.c if (reg->l & MSR_MCGCTL_NBE) reg 3089 drivers/edac/amd64_edac.c reg->l |= MSR_MCGCTL_NBE; reg 3095 drivers/edac/amd64_edac.c reg->l &= ~MSR_MCGCTL_NBE; reg 183 drivers/edac/amd64_edac.h #define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF) reg 4 drivers/edac/amd64_edac_dbg.c #define EDAC_DCT_ATTR_SHOW(reg) \ reg 5 drivers/edac/amd64_edac_dbg.c static ssize_t amd64_##reg##_show(struct device *dev, \ reg 11 drivers/edac/amd64_edac_dbg.c return sprintf(data, "0x%016llx\n", (u64)pvt->reg); \ reg 37 drivers/edac/amd8111_edac.c static int edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32) reg 41 drivers/edac/amd8111_edac.c ret = pci_read_config_dword(dev, reg, val32); reg 44 drivers/edac/amd8111_edac.c " PCI Access Read Error at 0x%x\n", reg); reg 49 drivers/edac/amd8111_edac.c static void edac_pci_read_byte(struct pci_dev *dev, int reg, u8 *val8) reg 53 drivers/edac/amd8111_edac.c ret = pci_read_config_byte(dev, reg, val8); reg 56 drivers/edac/amd8111_edac.c " PCI Access Read Error at 0x%x\n", reg); reg 59 drivers/edac/amd8111_edac.c static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32) reg 63 drivers/edac/amd8111_edac.c ret = pci_write_config_dword(dev, reg, val32); reg 66 drivers/edac/amd8111_edac.c " PCI Access Write Error at 0x%x\n", reg); reg 69 drivers/edac/amd8111_edac.c static void edac_pci_write_byte(struct pci_dev *dev, int reg, u8 val8) reg 73 drivers/edac/amd8111_edac.c ret = pci_write_config_byte(dev, reg, val8); reg 76 drivers/edac/amd8111_edac.c " PCI Access Write Error at 0x%x\n", reg); reg 27 drivers/edac/amd8131_edac.c static void edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32) reg 31 drivers/edac/amd8131_edac.c ret = pci_read_config_dword(dev, reg, val32); reg 34 drivers/edac/amd8131_edac.c " PCI Access Read Error at 0x%x\n", reg); reg 37 drivers/edac/amd8131_edac.c static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32) reg 41 drivers/edac/amd8131_edac.c ret = pci_write_config_dword(dev, reg, val32); reg 44 drivers/edac/amd8131_edac.c " PCI Access Write Error at 0x%x\n", reg); reg 41 drivers/edac/aspeed_edac.c static int regmap_reg_write(void *context, unsigned int reg, unsigned int val) reg 48 drivers/edac/aspeed_edac.c writel(val, regs + reg); reg 57 drivers/edac/aspeed_edac.c static int regmap_reg_read(void *context, unsigned int reg, unsigned int *val) reg 61 drivers/edac/aspeed_edac.c *val = readl(regs + reg); reg 66 drivers/edac/aspeed_edac.c static bool regmap_is_volatile(struct device *dev, unsigned int reg) reg 68 drivers/edac/aspeed_edac.c switch (reg) { reg 174 drivers/edac/cell_edac.c u64 reg; reg 184 drivers/edac/cell_edac.c reg = in_be64(®s->mic_mnt_cfg); reg 185 drivers/edac/cell_edac.c dev_dbg(&pdev->dev, "MIC_MNT_CFG = 0x%016llx\n", reg); reg 187 drivers/edac/cell_edac.c if (reg & CBE_MIC_MNT_CFG_CHAN_0_POP) reg 189 drivers/edac/cell_edac.c if (reg & CBE_MIC_MNT_CFG_CHAN_1_POP) reg 287 drivers/edac/cpc925_edac.c const unsigned int *reg, *reg_end; reg 297 drivers/edac/cpc925_edac.c reg = (const unsigned int *)of_get_property(np, "reg", &len); reg 298 drivers/edac/cpc925_edac.c reg_end = reg + len/4; reg 302 drivers/edac/cpc925_edac.c start = of_read_number(reg, aw); reg 303 drivers/edac/cpc925_edac.c reg += aw; reg 304 drivers/edac/cpc925_edac.c size = of_read_number(reg, sw); reg 305 drivers/edac/cpc925_edac.c reg += sw; reg 308 drivers/edac/cpc925_edac.c } while (reg < reg_end); reg 594 drivers/edac/cpc925_edac.c const u32 *reg = of_get_property(cpunode, "reg", NULL); reg 595 drivers/edac/cpc925_edac.c if (reg == NULL || *reg > 2) { reg 600 drivers/edac/cpc925_edac.c mask &= ~APIMASK_ADI(*reg); reg 89 drivers/edac/highbank_mc_edac.c u32 reg; reg 91 drivers/edac/highbank_mc_edac.c reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT); reg 92 drivers/edac/highbank_mc_edac.c reg &= HB_DDR_ECC_OPT_MODE_MASK; reg 93 drivers/edac/highbank_mc_edac.c reg |= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) | HB_DDR_ECC_OPT_FWC; reg 94 drivers/edac/highbank_mc_edac.c writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT); reg 22 drivers/edac/i10nm_base.c #define I10NM_GET_SCK_BAR(d, reg) \ reg 23 drivers/edac/i10nm_base.c pci_read_config_dword((d)->uracu, 0xd0, &(reg)) reg 24 drivers/edac/i10nm_base.c #define I10NM_GET_IMC_BAR(d, i, reg) \ reg 25 drivers/edac/i10nm_base.c pci_read_config_dword((d)->uracu, 0xd8 + (i) * 4, &(reg)) reg 31 drivers/edac/i10nm_base.c #define I10NM_GET_SCK_MMIO_BASE(reg) (GET_BITFIELD(reg, 0, 28) << 23) reg 32 drivers/edac/i10nm_base.c #define I10NM_GET_IMC_MMIO_OFFSET(reg) (GET_BITFIELD(reg, 0, 10) << 12) reg 33 drivers/edac/i10nm_base.c #define I10NM_GET_IMC_MMIO_SIZE(reg) ((GET_BITFIELD(reg, 13, 23) - \ reg 34 drivers/edac/i10nm_base.c GET_BITFIELD(reg, 0, 10) + 1) << 12) reg 68 drivers/edac/i10nm_base.c u32 reg, off; reg 80 drivers/edac/i10nm_base.c if (I10NM_GET_SCK_BAR(d, reg)) { reg 85 drivers/edac/i10nm_base.c base = I10NM_GET_SCK_MMIO_BASE(reg); reg 87 drivers/edac/i10nm_base.c j++, base, reg); reg 101 drivers/edac/i10nm_base.c if (I10NM_GET_IMC_BAR(d, i, reg)) { reg 106 drivers/edac/i10nm_base.c off = I10NM_GET_IMC_MMIO_OFFSET(reg); reg 107 drivers/edac/i10nm_base.c size = I10NM_GET_IMC_MMIO_SIZE(reg); reg 109 drivers/edac/i10nm_base.c i, base + off, size, reg); reg 593 drivers/edac/mv64x60_edac.c u32 reg; reg 599 drivers/edac/mv64x60_edac.c reg = readl(pdata->mc_vbase + MV64X60_SDRAM_ERR_ADDR); reg 600 drivers/edac/mv64x60_edac.c if (!reg) reg 603 drivers/edac/mv64x60_edac.c err_addr = reg & ~0x3; reg 609 drivers/edac/mv64x60_edac.c if (!(reg & 0x1)) reg 630 drivers/edac/mv64x60_edac.c u32 reg; reg 632 drivers/edac/mv64x60_edac.c reg = readl(pdata->mc_vbase + MV64X60_SDRAM_ERR_ADDR); reg 633 drivers/edac/mv64x60_edac.c if (!reg) reg 645 drivers/edac/mv64x60_edac.c const unsigned int *reg; reg 651 drivers/edac/mv64x60_edac.c reg = of_get_property(np, "reg", NULL); reg 653 drivers/edac/mv64x60_edac.c pdata->total_mem = reg[1]; reg 130 drivers/edac/octeon_edac-lmc.c #define TEMPLATE_SHOW(reg) \ reg 131 drivers/edac/octeon_edac-lmc.c static ssize_t octeon_mc_inject_##reg##_show(struct device *dev, \ reg 137 drivers/edac/octeon_edac-lmc.c return sprintf(data, "%016llu\n", (u64)pvt->reg); \ reg 140 drivers/edac/octeon_edac-lmc.c #define TEMPLATE_STORE(reg) \ reg 141 drivers/edac/octeon_edac-lmc.c static ssize_t octeon_mc_inject_##reg##_store(struct device *dev, \ reg 148 drivers/edac/octeon_edac-lmc.c if (!kstrtoul(data, 0, &pvt->reg)) \ reg 75 drivers/edac/sb_edac.c #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0) reg 76 drivers/edac/sb_edac.c #define A7MODE(reg) GET_BITFIELD(reg, 26, 26) reg 143 drivers/edac/sb_edac.c static inline int sad_pkg(const struct interleave_pkg *table, u32 reg, reg 146 drivers/edac/sb_edac.c return GET_BITFIELD(reg, table[interleave].start, reg 161 drivers/edac/sb_edac.c #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff) reg 162 drivers/edac/sb_edac.c #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff) reg 168 drivers/edac/sb_edac.c #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11) reg 170 drivers/edac/sb_edac.c #define SOURCE_ID_KNL(reg) GET_BITFIELD(reg, 12, 14) reg 183 drivers/edac/sb_edac.c #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff) reg 184 drivers/edac/sb_edac.c #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11) reg 185 drivers/edac/sb_edac.c #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9) reg 186 drivers/edac/sb_edac.c #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7) reg 187 drivers/edac/sb_edac.c #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5) reg 188 drivers/edac/sb_edac.c #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3) reg 189 drivers/edac/sb_edac.c #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1) reg 203 drivers/edac/sb_edac.c #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0) reg 224 drivers/edac/sb_edac.c #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29) reg 225 drivers/edac/sb_edac.c #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26) reg 232 drivers/edac/sb_edac.c #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31) reg 233 drivers/edac/sb_edac.c #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29) reg 245 drivers/edac/sb_edac.c #define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \ reg 246 drivers/edac/sb_edac.c GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19)) reg 248 drivers/edac/sb_edac.c #define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \ reg 249 drivers/edac/sb_edac.c GET_BITFIELD(reg, 2, 15) : GET_BITFIELD(reg, 2, 14)) reg 261 drivers/edac/sb_edac.c #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31) reg 262 drivers/edac/sb_edac.c #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30) reg 263 drivers/edac/sb_edac.c #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15) reg 264 drivers/edac/sb_edac.c #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14) reg 270 drivers/edac/sb_edac.c #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30) reg 271 drivers/edac/sb_edac.c #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14) reg 318 drivers/edac/sb_edac.c u64 (*rir_limit)(u32 reg); reg 319 drivers/edac/sb_edac.c u64 (*sad_limit)(u32 reg); reg 320 drivers/edac/sb_edac.c u32 (*interleave_mode)(u32 reg); reg 321 drivers/edac/sb_edac.c u32 (*dram_attr)(u32 reg); reg 794 drivers/edac/sb_edac.c u32 reg; reg 797 drivers/edac/sb_edac.c pci_read_config_dword(pvt->pci_sad1, TOLM, ®); reg 798 drivers/edac/sb_edac.c return GET_TOLM(reg); reg 803 drivers/edac/sb_edac.c u32 reg; reg 805 drivers/edac/sb_edac.c pci_read_config_dword(pvt->pci_sad1, TOHM, ®); reg 806 drivers/edac/sb_edac.c return GET_TOHM(reg); reg 811 drivers/edac/sb_edac.c u32 reg; reg 813 drivers/edac/sb_edac.c pci_read_config_dword(pvt->pci_br1, TOLM, ®); reg 815 drivers/edac/sb_edac.c return GET_TOLM(reg); reg 820 drivers/edac/sb_edac.c u32 reg; reg 822 drivers/edac/sb_edac.c pci_read_config_dword(pvt->pci_br1, TOHM, ®); reg 824 drivers/edac/sb_edac.c return GET_TOHM(reg); reg 827 drivers/edac/sb_edac.c static u64 rir_limit(u32 reg) reg 829 drivers/edac/sb_edac.c return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff; reg 832 drivers/edac/sb_edac.c static u64 sad_limit(u32 reg) reg 834 drivers/edac/sb_edac.c return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff; reg 837 drivers/edac/sb_edac.c static u32 interleave_mode(u32 reg) reg 839 drivers/edac/sb_edac.c return GET_BITFIELD(reg, 1, 1); reg 842 drivers/edac/sb_edac.c static u32 dram_attr(u32 reg) reg 844 drivers/edac/sb_edac.c return GET_BITFIELD(reg, 2, 3); reg 847 drivers/edac/sb_edac.c static u64 knl_sad_limit(u32 reg) reg 849 drivers/edac/sb_edac.c return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff; reg 852 drivers/edac/sb_edac.c static u32 knl_interleave_mode(u32 reg) reg 854 drivers/edac/sb_edac.c return GET_BITFIELD(reg, 1, 2); reg 861 drivers/edac/sb_edac.c static const char *get_intlv_mode_str(u32 reg, enum type t) reg 864 drivers/edac/sb_edac.c return knl_intlv_mode[knl_interleave_mode(reg)]; reg 866 drivers/edac/sb_edac.c return interleave_mode(reg) ? "[8:6]" : "[8:6]XOR[18:16]"; reg 869 drivers/edac/sb_edac.c static u32 dram_attr_knl(u32 reg) reg 871 drivers/edac/sb_edac.c return GET_BITFIELD(reg, 3, 4); reg 877 drivers/edac/sb_edac.c u32 reg; reg 882 drivers/edac/sb_edac.c ®); reg 883 drivers/edac/sb_edac.c if (GET_BITFIELD(reg, 11, 11)) reg 896 drivers/edac/sb_edac.c u32 reg; reg 904 drivers/edac/sb_edac.c HASWELL_DDRCRCLKCONTROLS, ®); reg 906 drivers/edac/sb_edac.c if (GET_BITFIELD(reg, 16, 16)) reg 909 drivers/edac/sb_edac.c pci_read_config_dword(pvt->pci_ta, MCMTR, ®); reg 910 drivers/edac/sb_edac.c if (GET_BITFIELD(reg, 14, 14)) { reg 983 drivers/edac/sb_edac.c u32 reg; reg 984 drivers/edac/sb_edac.c pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); reg 985 drivers/edac/sb_edac.c return GET_BITFIELD(reg, 0, 2); reg 990 drivers/edac/sb_edac.c u32 reg; reg 992 drivers/edac/sb_edac.c pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); reg 993 drivers/edac/sb_edac.c return GET_BITFIELD(reg, 0, 3); reg 998 drivers/edac/sb_edac.c u32 reg; reg 1000 drivers/edac/sb_edac.c pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); reg 1001 drivers/edac/sb_edac.c return GET_BITFIELD(reg, 0, 2); reg 1040 drivers/edac/sb_edac.c u32 reg; reg 1042 drivers/edac/sb_edac.c pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®); reg 1043 drivers/edac/sb_edac.c return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff; reg 1049 drivers/edac/sb_edac.c u32 reg; reg 1051 drivers/edac/sb_edac.c pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®); reg 1052 drivers/edac/sb_edac.c rc = GET_BITFIELD(reg, 26, 31); reg 1053 drivers/edac/sb_edac.c pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®); reg 1054 drivers/edac/sb_edac.c rc = ((reg << 6) | rc) << 26; reg 1061 drivers/edac/sb_edac.c u32 reg; reg 1063 drivers/edac/sb_edac.c pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, ®); reg 1064 drivers/edac/sb_edac.c return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff; reg 1079 drivers/edac/sb_edac.c static u64 haswell_rir_limit(u32 reg) reg 1081 drivers/edac/sb_edac.c return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1; reg 1228 drivers/edac/sb_edac.c static u32 knl_get_edc_route(int entry, u32 reg) reg 1231 drivers/edac/sb_edac.c return GET_BITFIELD(reg, entry*3, (entry*3)+2); reg 1251 drivers/edac/sb_edac.c static u32 knl_get_mc_route(int entry, u32 reg) reg 1257 drivers/edac/sb_edac.c mc = GET_BITFIELD(reg, entry*3, (entry*3)+2); reg 1258 drivers/edac/sb_edac.c chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1); reg 1267 drivers/edac/sb_edac.c static void knl_show_edc_route(u32 reg, char *s) reg 1272 drivers/edac/sb_edac.c s[i*2] = knl_get_edc_route(i, reg) + '0'; reg 1283 drivers/edac/sb_edac.c static void knl_show_mc_route(u32 reg, char *s) reg 1288 drivers/edac/sb_edac.c s[i*2] = knl_get_mc_route(i, reg) + '0'; reg 1299 drivers/edac/sb_edac.c #define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29) reg 1302 drivers/edac/sb_edac.c #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28) reg 1305 drivers/edac/sb_edac.c #define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29) reg 1308 drivers/edac/sb_edac.c #define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28) reg 1311 drivers/edac/sb_edac.c #define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27) reg 1568 drivers/edac/sb_edac.c u32 reg; reg 1572 drivers/edac/sb_edac.c pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®); reg 1574 drivers/edac/sb_edac.c pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); reg 1577 drivers/edac/sb_edac.c pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg); reg 1579 drivers/edac/sb_edac.c pvt->sbridge_dev->source_id = SOURCE_ID(reg); reg 1681 drivers/edac/sb_edac.c u32 reg; reg 1705 drivers/edac/sb_edac.c if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®)) { reg 1709 drivers/edac/sb_edac.c pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21); reg 1710 drivers/edac/sb_edac.c if (GET_BITFIELD(reg, 28, 28)) { reg 1716 drivers/edac/sb_edac.c if (pci_read_config_dword(pvt->pci_ras, RASENABLES, ®)) { reg 1720 drivers/edac/sb_edac.c if (IS_MIRROR_ENABLED(reg)) { reg 1758 drivers/edac/sb_edac.c u32 reg; reg 1793 drivers/edac/sb_edac.c ®); reg 1794 drivers/edac/sb_edac.c limit = pvt->info.sad_limit(reg); reg 1796 drivers/edac/sb_edac.c if (!DRAM_RULE_ENABLE(reg)) reg 1806 drivers/edac/sb_edac.c show_dram_attr(pvt->info.dram_attr(reg)), reg 1809 drivers/edac/sb_edac.c get_intlv_mode_str(reg, pvt->info.type), reg 1810 drivers/edac/sb_edac.c reg); reg 1814 drivers/edac/sb_edac.c ®); reg 1815 drivers/edac/sb_edac.c sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); reg 1817 drivers/edac/sb_edac.c u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); reg 1834 drivers/edac/sb_edac.c pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], ®); reg 1835 drivers/edac/sb_edac.c limit = TAD_LIMIT(reg); reg 1844 drivers/edac/sb_edac.c (u32)(1 << TAD_SOCK(reg)), reg 1845 drivers/edac/sb_edac.c (u32)TAD_CH(reg) + 1, reg 1846 drivers/edac/sb_edac.c (u32)TAD_TGT0(reg), reg 1847 drivers/edac/sb_edac.c (u32)TAD_TGT1(reg), reg 1848 drivers/edac/sb_edac.c (u32)TAD_TGT2(reg), reg 1849 drivers/edac/sb_edac.c (u32)TAD_TGT3(reg), reg 1850 drivers/edac/sb_edac.c reg); reg 1863 drivers/edac/sb_edac.c ®); reg 1864 drivers/edac/sb_edac.c tmp_mb = TAD_OFFSET(reg) >> 20; reg 1870 drivers/edac/sb_edac.c reg); reg 1883 drivers/edac/sb_edac.c ®); reg 1885 drivers/edac/sb_edac.c if (!IS_RIR_VALID(reg)) reg 1888 drivers/edac/sb_edac.c tmp_mb = pvt->info.rir_limit(reg) >> 20; reg 1889 drivers/edac/sb_edac.c rir_way = 1 << RIR_WAY(reg); reg 1896 drivers/edac/sb_edac.c reg); reg 1901 drivers/edac/sb_edac.c ®); reg 1902 drivers/edac/sb_edac.c tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6; reg 1909 drivers/edac/sb_edac.c (u32)RIR_RNK_TGT(pvt->info.type, reg), reg 1910 drivers/edac/sb_edac.c reg); reg 1941 drivers/edac/sb_edac.c u32 reg, dram_rule; reg 1970 drivers/edac/sb_edac.c ®); reg 1972 drivers/edac/sb_edac.c if (!DRAM_RULE_ENABLE(reg)) reg 1975 drivers/edac/sb_edac.c limit = pvt->info.sad_limit(reg); reg 1988 drivers/edac/sb_edac.c dram_rule = reg; reg 1993 drivers/edac/sb_edac.c ®); reg 1996 drivers/edac/sb_edac.c sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); reg 1998 drivers/edac/sb_edac.c u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); reg 2052 drivers/edac/sb_edac.c pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); reg 2058 drivers/edac/sb_edac.c pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®); reg 2059 drivers/edac/sb_edac.c shiftup = GET_BITFIELD(reg, 22, 22); reg 2067 drivers/edac/sb_edac.c pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); reg 2095 drivers/edac/sb_edac.c pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®); reg 2096 drivers/edac/sb_edac.c limit = TAD_LIMIT(reg); reg 2110 drivers/edac/sb_edac.c ch_way = TAD_CH(reg) + 1; reg 2111 drivers/edac/sb_edac.c sck_way = TAD_SOCK(reg); reg 2127 drivers/edac/sb_edac.c base_ch = TAD_TGT0(reg); reg 2130 drivers/edac/sb_edac.c base_ch = TAD_TGT1(reg); reg 2133 drivers/edac/sb_edac.c base_ch = TAD_TGT2(reg); reg 2136 drivers/edac/sb_edac.c base_ch = TAD_TGT3(reg); reg 2200 drivers/edac/sb_edac.c pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], ®); reg 2202 drivers/edac/sb_edac.c if (!IS_RIR_VALID(reg)) reg 2205 drivers/edac/sb_edac.c limit = pvt->info.rir_limit(reg); reg 2211 drivers/edac/sb_edac.c 1 << RIR_WAY(reg)); reg 2220 drivers/edac/sb_edac.c rir_way = RIR_WAY(reg); reg 2228 drivers/edac/sb_edac.c pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®); reg 2229 drivers/edac/sb_edac.c *rank = RIR_RNK_TGT(pvt->info.type, reg); reg 2246 drivers/edac/sb_edac.c u32 reg, channel = GET_BITFIELD(m->status, 0, 3); reg 2277 drivers/edac/sb_edac.c pci_read_config_dword(pci_ha, tad_dram_rule[0], ®); reg 2278 drivers/edac/sb_edac.c tad0 = m->addr <= TAD_LIMIT(reg); reg 79 drivers/edac/skx_base.c u32 reg; reg 126 drivers/edac/skx_base.c pci_read_config_dword(pdev, 0xB4, ®); reg 127 drivers/edac/skx_base.c if (reg != 0) { reg 129 drivers/edac/skx_base.c d->mcroute = reg; reg 130 drivers/edac/skx_base.c } else if (d->mcroute != reg) { reg 199 drivers/edac/skx_base.c #define SKX_GET_SAD(d, i, reg) \ reg 200 drivers/edac/skx_base.c pci_read_config_dword((d)->sad_all, 0x60 + 8 * (i), &(reg)) reg 201 drivers/edac/skx_base.c #define SKX_GET_ILV(d, i, reg) \ reg 202 drivers/edac/skx_base.c pci_read_config_dword((d)->sad_all, 0x64 + 8 * (i), &(reg)) reg 326 drivers/edac/skx_base.c #define SKX_GET_TADBASE(d, mc, i, reg) \ reg 327 drivers/edac/skx_base.c pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x850 + 4 * (i), &(reg)) reg 328 drivers/edac/skx_base.c #define SKX_GET_TADWAYNESS(d, mc, i, reg) \ reg 329 drivers/edac/skx_base.c pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x880 + 4 * (i), &(reg)) reg 330 drivers/edac/skx_base.c #define SKX_GET_TADCHNILVOFFSET(d, mc, ch, i, reg) \ reg 331 drivers/edac/skx_base.c pci_read_config_dword((d)->imc[mc].chan[ch].cdev, 0x90 + 4 * (i), &(reg)) reg 401 drivers/edac/skx_base.c #define SKX_GET_RIRWAYNESS(d, mc, ch, i, reg) \ reg 403 drivers/edac/skx_base.c 0x108 + 4 * (i), &(reg)) reg 404 drivers/edac/skx_base.c #define SKX_GET_RIRILV(d, mc, ch, idx, i, reg) \ reg 406 drivers/edac/skx_base.c 0x120 + 16 * (idx) + 4 * (i), &(reg)) reg 141 drivers/edac/skx_common.c u32 reg; reg 143 drivers/edac/skx_common.c if (pci_read_config_dword(d->util_all, off, ®)) { reg 148 drivers/edac/skx_common.c *id = GET_BITFIELD(reg, 12, 14); reg 154 drivers/edac/skx_common.c u32 reg; reg 156 drivers/edac/skx_common.c if (pci_read_config_dword(d->util_all, 0xf4, ®)) { reg 161 drivers/edac/skx_common.c *id = GET_BITFIELD(reg, 0, 2); reg 188 drivers/edac/skx_common.c u32 reg; reg 203 drivers/edac/skx_common.c if (pci_read_config_dword(pdev, off, ®)) { reg 210 drivers/edac/skx_common.c d->bus[0] = GET_BITFIELD(reg, 0, 7); reg 211 drivers/edac/skx_common.c d->bus[1] = GET_BITFIELD(reg, 8, 15); reg 214 drivers/edac/skx_common.c d->bus[2] = GET_BITFIELD(reg, 16, 23); reg 215 drivers/edac/skx_common.c d->bus[3] = GET_BITFIELD(reg, 24, 31); reg 217 drivers/edac/skx_common.c d->seg = GET_BITFIELD(reg, 16, 23); reg 234 drivers/edac/skx_common.c u32 reg; reg 242 drivers/edac/skx_common.c if (pci_read_config_dword(pdev, off[0], ®)) { reg 246 drivers/edac/skx_common.c skx_tolm = reg; reg 248 drivers/edac/skx_common.c if (pci_read_config_dword(pdev, off[1], ®)) { reg 252 drivers/edac/skx_common.c skx_tohm = reg; reg 254 drivers/edac/skx_common.c if (pci_read_config_dword(pdev, off[2], ®)) { reg 258 drivers/edac/skx_common.c skx_tohm |= (u64)reg << 32; reg 270 drivers/edac/skx_common.c static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add, reg 273 drivers/edac/skx_common.c u32 val = GET_BITFIELD(reg, lobit, hibit); reg 276 drivers/edac/skx_common.c edac_dbg(2, "bad %s = %d (raw=0x%x)\n", name, val, reg); reg 282 drivers/edac/skx_common.c #define numrank(reg) skx_get_dimm_attr(reg, 12, 13, 0, 0, 2, "ranks") reg 283 drivers/edac/skx_common.c #define numrow(reg) skx_get_dimm_attr(reg, 2, 4, 12, 1, 6, "rows") reg 284 drivers/edac/skx_common.c #define numcol(reg) skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols") reg 41 drivers/edac/thunderx_edac.c u64 reg[MAX_SYNDROME_REGS]; reg 52 drivers/edac/thunderx_edac.c const uint64_t reg) reg 57 drivers/edac/thunderx_edac.c if (reg & descr->mask) { reg 1351 drivers/edac/thunderx_edac.c u64 reg; reg 1448 drivers/edac/thunderx_edac.c reg = readq(ocx->regs + OCX_LNE_INT(i)); reg 1449 drivers/edac/thunderx_edac.c writeq(reg, ocx->regs + OCX_LNE_INT(i)); reg 1454 drivers/edac/thunderx_edac.c reg = readq(ocx->regs + OCX_COM_LINKX_INT(i)); reg 1455 drivers/edac/thunderx_edac.c writeq(reg, ocx->regs + OCX_COM_LINKX_INT(i)); reg 1461 drivers/edac/thunderx_edac.c reg = readq(ocx->regs + OCX_COM_INT); reg 1462 drivers/edac/thunderx_edac.c writeq(reg, ocx->regs + OCX_COM_INT); reg 79 drivers/edac/ti_edac.c void __iomem *reg; reg 84 drivers/edac/ti_edac.c return readl_relaxed(edac->reg + offset); reg 89 drivers/edac/ti_edac.c writel_relaxed(val, edac->reg + offset); reg 234 drivers/edac/ti_edac.c void __iomem *reg; reg 246 drivers/edac/ti_edac.c reg = devm_ioremap_resource(dev, res); reg 247 drivers/edac/ti_edac.c if (IS_ERR(reg)) { reg 250 drivers/edac/ti_edac.c return PTR_ERR(reg); reg 267 drivers/edac/ti_edac.c edac->reg = reg; reg 66 drivers/edac/xgene_edac.c static void xgene_edac_pcp_rd(struct xgene_edac *edac, u32 reg, u32 *val) reg 68 drivers/edac/xgene_edac.c *val = readl(edac->pcp_csr + reg); reg 71 drivers/edac/xgene_edac.c static void xgene_edac_pcp_clrbits(struct xgene_edac *edac, u32 reg, reg 77 drivers/edac/xgene_edac.c val = readl(edac->pcp_csr + reg); reg 79 drivers/edac/xgene_edac.c writel(val, edac->pcp_csr + reg); reg 83 drivers/edac/xgene_edac.c static void xgene_edac_pcp_setbits(struct xgene_edac *edac, u32 reg, reg 89 drivers/edac/xgene_edac.c val = readl(edac->pcp_csr + reg); reg 91 drivers/edac/xgene_edac.c writel(val, edac->pcp_csr + reg); reg 179 drivers/edac/xgene_edac.c u32 reg; reg 193 drivers/edac/xgene_edac.c reg = readl(ctx->mcu_csr + MCUESRR0 + rank * MCU_RANK_STRIDE); reg 196 drivers/edac/xgene_edac.c if (reg & (MCU_ESRR_DEMANDUCERR_MASK | reg 207 drivers/edac/xgene_edac.c if (reg & MCU_ESRR_CERR_MASK) { reg 230 drivers/edac/xgene_edac.c writel(reg, ctx->mcu_csr + MCUESRR0 + rank * MCU_RANK_STRIDE); reg 234 drivers/edac/xgene_edac.c reg = readl(ctx->mcu_csr + MCUGESR); reg 235 drivers/edac/xgene_edac.c if (reg) { reg 236 drivers/edac/xgene_edac.c if (reg & MCU_GESR_ADDRNOMATCH_ERR_MASK) reg 239 drivers/edac/xgene_edac.c if (reg & MCU_GESR_ADDRMULTIMATCH_ERR_MASK) reg 243 drivers/edac/xgene_edac.c writel(reg, ctx->mcu_csr + MCUGESR); reg 311 drivers/edac/xgene_edac.c unsigned int reg; reg 314 drivers/edac/xgene_edac.c if (regmap_read(ctx->edac->csw_map, CSW_CSWCR, ®)) reg 317 drivers/edac/xgene_edac.c if (reg & CSW_CSWCR_DUALMCB_MASK) { reg 322 drivers/edac/xgene_edac.c if (regmap_read(ctx->edac->mcbb_map, MCBADDRMR, ®)) reg 324 drivers/edac/xgene_edac.c mcu_mask = (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5; reg 330 drivers/edac/xgene_edac.c if (regmap_read(ctx->edac->mcba_map, MCBADDRMR, ®)) reg 332 drivers/edac/xgene_edac.c mcu_mask = (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1; reg 1394 drivers/edac/xgene_edac.c u32 reg; reg 1398 drivers/edac/xgene_edac.c reg = readl(ctx->dev_csr + XGICTRANSERRINTSTS); reg 1399 drivers/edac/xgene_edac.c if (!reg) reg 1402 drivers/edac/xgene_edac.c if (reg & RD_ACCESS_ERR_MASK) reg 1404 drivers/edac/xgene_edac.c if (reg & M_RD_ACCESS_ERR_MASK) reg 1406 drivers/edac/xgene_edac.c if (reg & WR_ACCESS_ERR_MASK) reg 1408 drivers/edac/xgene_edac.c if (reg & M_WR_ACCESS_ERR_MASK) reg 1414 drivers/edac/xgene_edac.c writel(reg, ctx->dev_csr + XGICTRANSERRINTSTS); reg 1418 drivers/edac/xgene_edac.c reg = readl(ctx->dev_csr + GLBL_ERR_STS); reg 1419 drivers/edac/xgene_edac.c if (!reg) reg 1421 drivers/edac/xgene_edac.c if (reg & SEC_ERR_MASK) { reg 1430 drivers/edac/xgene_edac.c if (reg & MSEC_ERR_MASK) { reg 1439 drivers/edac/xgene_edac.c if (reg & (SEC_ERR_MASK | MSEC_ERR_MASK)) reg 1442 drivers/edac/xgene_edac.c if (reg & DED_ERR_MASK) { reg 1451 drivers/edac/xgene_edac.c if (reg & MDED_ERR_MASK) { reg 1460 drivers/edac/xgene_edac.c if (reg & (DED_ERR_MASK | MDED_ERR_MASK)) reg 1469 drivers/edac/xgene_edac.c u32 reg; reg 1482 drivers/edac/xgene_edac.c if (regmap_read(ctx->edac->rb_map, RBCSR, ®)) reg 1484 drivers/edac/xgene_edac.c if (reg & STICKYERR_MASK) { reg 1489 drivers/edac/xgene_edac.c if (regmap_read(ctx->edac->rb_map, RBEIR, ®)) reg 1491 drivers/edac/xgene_edac.c write = reg & WRITE_ACCESS_MASK ? 1 : 0; reg 1492 drivers/edac/xgene_edac.c address = RBERRADDR_RD(reg); reg 1493 drivers/edac/xgene_edac.c if (reg & AGENT_OFFLINE_ERR_MASK) reg 1497 drivers/edac/xgene_edac.c if (reg & UNIMPL_RBPAGE_ERR_MASK) reg 1501 drivers/edac/xgene_edac.c if (reg & WORD_ALIGNED_ERR_MASK) reg 1505 drivers/edac/xgene_edac.c if (reg & PAGE_ACCESS_ERR_MASK) reg 1517 drivers/edac/xgene_edac.c reg = readl(ctx->dev_csr + IOBBATRANSERRINTSTS); reg 1518 drivers/edac/xgene_edac.c if (!reg) reg 1522 drivers/edac/xgene_edac.c if (reg & WRERR_RESP_MASK) reg 1524 drivers/edac/xgene_edac.c if (reg & M_WRERR_RESP_MASK) reg 1527 drivers/edac/xgene_edac.c if (reg & XGIC_POISONED_REQ_MASK) reg 1529 drivers/edac/xgene_edac.c if (reg & M_XGIC_POISONED_REQ_MASK) reg 1532 drivers/edac/xgene_edac.c if (reg & RBM_POISONED_REQ_MASK) reg 1534 drivers/edac/xgene_edac.c if (reg & M_RBM_POISONED_REQ_MASK) reg 1537 drivers/edac/xgene_edac.c if (reg & WDATA_CORRUPT_MASK) reg 1539 drivers/edac/xgene_edac.c if (reg & M_WDATA_CORRUPT_MASK) reg 1541 drivers/edac/xgene_edac.c if (reg & TRANS_CORRUPT_MASK) reg 1543 drivers/edac/xgene_edac.c if (reg & M_TRANS_CORRUPT_MASK) reg 1545 drivers/edac/xgene_edac.c if (reg & RIDRAM_CORRUPT_MASK) reg 1548 drivers/edac/xgene_edac.c if (reg & M_RIDRAM_CORRUPT_MASK) reg 1551 drivers/edac/xgene_edac.c if (reg & WIDRAM_CORRUPT_MASK) reg 1554 drivers/edac/xgene_edac.c if (reg & M_WIDRAM_CORRUPT_MASK) reg 1557 drivers/edac/xgene_edac.c if (reg & ILLEGAL_ACCESS_MASK) reg 1560 drivers/edac/xgene_edac.c if (reg & M_ILLEGAL_ACCESS_MASK) reg 1569 drivers/edac/xgene_edac.c if (reg & WRERR_RESP_MASK) reg 1572 drivers/edac/xgene_edac.c writel(reg, ctx->dev_csr + IOBBATRANSERRINTSTS); reg 1580 drivers/edac/xgene_edac.c u32 reg; reg 1583 drivers/edac/xgene_edac.c reg = readl(ctx->dev_csr + IOBPATRANSERRINTSTS); reg 1584 drivers/edac/xgene_edac.c if (!reg) reg 1587 drivers/edac/xgene_edac.c if (reg & IOBPA_RDATA_CORRUPT_MASK) reg 1589 drivers/edac/xgene_edac.c if (reg & IOBPA_M_RDATA_CORRUPT_MASK) reg 1592 drivers/edac/xgene_edac.c if (reg & IOBPA_WDATA_CORRUPT_MASK) reg 1594 drivers/edac/xgene_edac.c if (reg & IOBPA_M_WDATA_CORRUPT_MASK) reg 1597 drivers/edac/xgene_edac.c if (reg & IOBPA_TRANS_CORRUPT_MASK) reg 1599 drivers/edac/xgene_edac.c if (reg & IOBPA_M_TRANS_CORRUPT_MASK) reg 1601 drivers/edac/xgene_edac.c if (reg & IOBPA_REQIDRAM_CORRUPT_MASK) reg 1603 drivers/edac/xgene_edac.c if (reg & IOBPA_M_REQIDRAM_CORRUPT_MASK) reg 1606 drivers/edac/xgene_edac.c writel(reg, ctx->dev_csr + IOBPATRANSERRINTSTS); reg 1610 drivers/edac/xgene_edac.c reg = readl(ctx->dev_csr + IOBAXIS0TRANSERRINTSTS); reg 1611 drivers/edac/xgene_edac.c if (!reg) reg 1617 drivers/edac/xgene_edac.c reg & IOBAXIS0_M_ILLEGAL_ACCESS_MASK ? "Multiple " : "", reg 1620 drivers/edac/xgene_edac.c writel(reg, ctx->dev_csr + IOBAXIS0TRANSERRINTSTS); reg 1624 drivers/edac/xgene_edac.c reg = readl(ctx->dev_csr + IOBAXIS1TRANSERRINTSTS); reg 1625 drivers/edac/xgene_edac.c if (!reg) reg 1631 drivers/edac/xgene_edac.c reg & IOBAXIS0_M_ILLEGAL_ACCESS_MASK ? "Multiple " : "", reg 1634 drivers/edac/xgene_edac.c writel(reg, ctx->dev_csr + IOBAXIS1TRANSERRINTSTS); reg 1643 drivers/edac/xgene_edac.c u32 reg; reg 1648 drivers/edac/xgene_edac.c xgene_edac_pcp_rd(ctx->edac, MEMERRINTSTS, ®); reg 1651 drivers/edac/xgene_edac.c (pcp_lp_stat & CSW_SWITCH_TRACE_ERR_MASK) || reg)) reg 1669 drivers/edac/xgene_edac.c if (!reg) reg 1675 drivers/edac/xgene_edac.c reg); reg 1680 drivers/edac/xgene_edac.c if (reg & (1 << i)) { reg 1230 drivers/extcon/extcon-arizona.c int reg; reg 1233 drivers/extcon/extcon-arizona.c reg = ARIZONA_MIC_DETECT_LEVEL_4 - (index / 2); reg 1243 drivers/extcon/extcon-arizona.c regmap_update_bits(arizona->regmap, reg, mask, level); reg 147 drivers/extcon/extcon-fsa9480.c static bool fsa9480_volatile_reg(struct device *dev, unsigned int reg) reg 149 drivers/extcon/extcon-fsa9480.c switch (reg) { reg 165 drivers/extcon/extcon-fsa9480.c static int fsa9480_write_reg(struct fsa9480_usbsw *usbsw, int reg, int value) reg 169 drivers/extcon/extcon-fsa9480.c ret = regmap_write(usbsw->regmap, reg, value); reg 176 drivers/extcon/extcon-fsa9480.c static int fsa9480_read_reg(struct fsa9480_usbsw *usbsw, int reg) reg 180 drivers/extcon/extcon-fsa9480.c ret = regmap_read(usbsw->regmap, reg, &val); reg 67 drivers/extcon/extcon-intel-mrfld.c static int mrfld_extcon_clear(struct mrfld_extcon_data *data, unsigned int reg, reg 70 drivers/extcon/extcon-intel-mrfld.c return regmap_update_bits(data->regmap, reg, mask, 0x00); reg 73 drivers/extcon/extcon-intel-mrfld.c static int mrfld_extcon_set(struct mrfld_extcon_data *data, unsigned int reg, reg 76 drivers/extcon/extcon-intel-mrfld.c return regmap_update_bits(data->regmap, reg, mask, 0xff); reg 32 drivers/extcon/extcon-rt8973a.c u8 reg; reg 73 drivers/extcon/extcon-rt8973a.c .reg = RT8973A_REG_CONTROL1, reg 202 drivers/extcon/extcon-rt8973a.c static bool rt8973a_muic_volatile_reg(struct device *dev, unsigned int reg) reg 204 drivers/extcon/extcon-rt8973a.c switch (reg) { reg 524 drivers/extcon/extcon-rt8973a.c u8 reg = info->reg_data[i].reg; reg 533 drivers/extcon/extcon-rt8973a.c regmap_update_bits(info->regmap, reg, mask, val); reg 31 drivers/extcon/extcon-sm5502.c u8 reg; reg 68 drivers/extcon/extcon-sm5502.c .reg = SM5502_REG_RESET, reg 72 drivers/extcon/extcon-sm5502.c .reg = SM5502_REG_CONTROL, reg 76 drivers/extcon/extcon-sm5502.c .reg = SM5502_REG_INTMASK1, reg 82 drivers/extcon/extcon-sm5502.c .reg = SM5502_REG_INTMASK2, reg 202 drivers/extcon/extcon-sm5502.c static bool sm5502_muic_volatile_reg(struct device *dev, unsigned int reg) reg 204 drivers/extcon/extcon-sm5502.c switch (reg) { reg 544 drivers/extcon/extcon-sm5502.c regmap_write(info->regmap, info->reg_data[i].reg, val); reg 221 drivers/firewire/core-card.c int reg = short_reset ? 5 : 1; reg 224 drivers/firewire/core-card.c return card->driver->update_phy_reg(card, reg, 0, bit); reg 1089 drivers/firewire/core-transaction.c int reg = offset & ~CSR_REGISTER_BASE; reg 1094 drivers/firewire/core-transaction.c switch (reg) { reg 1115 drivers/firewire/core-transaction.c *data = cpu_to_be32(card->driver->read_csr(card, reg)); reg 1117 drivers/firewire/core-transaction.c card->driver->write_csr(card, reg, be32_to_cpu(*data)); reg 1261 drivers/firewire/ohci.c u32 reg; reg 1268 drivers/firewire/ohci.c reg = reg_read(ohci, CONTROL_SET(ctx->regs)); reg 1269 drivers/firewire/ohci.c if ((reg & CONTEXT_ACTIVE) == 0) reg 1275 drivers/firewire/ohci.c ohci_err(ohci, "DMA context still active (0x%08x)\n", reg); reg 1768 drivers/firewire/ohci.c int reg; reg 1771 drivers/firewire/ohci.c reg = write_phy_reg(ohci, 7, port_index); reg 1772 drivers/firewire/ohci.c if (reg >= 0) reg 1773 drivers/firewire/ohci.c reg = read_phy_reg(ohci, 8); reg 1775 drivers/firewire/ohci.c if (reg < 0) reg 1776 drivers/firewire/ohci.c return reg; reg 1778 drivers/firewire/ohci.c switch (reg & 0x0f) { reg 1805 drivers/firewire/ohci.c int reg; reg 1809 drivers/firewire/ohci.c reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */ reg 1810 drivers/firewire/ohci.c if (reg >= 0) { reg 1811 drivers/firewire/ohci.c reg = read_phy_reg(ohci, 8); reg 1812 drivers/firewire/ohci.c reg |= 0x40; reg 1813 drivers/firewire/ohci.c reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */ reg 1814 drivers/firewire/ohci.c if (reg >= 0) { reg 1815 drivers/firewire/ohci.c reg = read_phy_reg(ohci, 12); /* read register 12 */ reg 1816 drivers/firewire/ohci.c if (reg >= 0) { reg 1817 drivers/firewire/ohci.c if ((reg & 0x08) == 0x08) { reg 1835 drivers/firewire/ohci.c int reg, i, pos, status; reg 1839 drivers/firewire/ohci.c reg = reg_read(ohci, OHCI1394_NodeID); reg 1840 drivers/firewire/ohci.c if (!(reg & OHCI1394_NodeID_idValid)) { reg 1845 drivers/firewire/ohci.c self_id |= ((reg & 0x3f) << 24); /* phy ID */ reg 1847 drivers/firewire/ohci.c reg = ohci_read_phy_reg(&ohci->card, 4); reg 1848 drivers/firewire/ohci.c if (reg < 0) reg 1849 drivers/firewire/ohci.c return reg; reg 1850 drivers/firewire/ohci.c self_id |= ((reg & 0x07) << 8); /* power class */ reg 1852 drivers/firewire/ohci.c reg = ohci_read_phy_reg(&ohci->card, 1); reg 1853 drivers/firewire/ohci.c if (reg < 0) reg 1854 drivers/firewire/ohci.c return reg; reg 1855 drivers/firewire/ohci.c self_id |= ((reg & 0x3f) << 16); /* gap count */ reg 1882 drivers/firewire/ohci.c u32 reg; reg 1887 drivers/firewire/ohci.c reg = reg_read(ohci, OHCI1394_NodeID); reg 1888 drivers/firewire/ohci.c if (!(reg & OHCI1394_NodeID_idValid)) { reg 1893 drivers/firewire/ohci.c if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { reg 1897 drivers/firewire/ohci.c ohci->node_id = reg & (OHCI1394_NodeID_busNumber | reg 1900 drivers/firewire/ohci.c is_new_root = (reg & OHCI1394_NodeID_root) != 0; reg 1906 drivers/firewire/ohci.c reg = reg_read(ohci, OHCI1394_SelfIDCount); reg 1907 drivers/firewire/ohci.c if (reg & OHCI1394_SelfIDCount_selfIDError) { reg 1917 drivers/firewire/ohci.c self_id_count = (reg >> 3) & 0xff; reg 1920 drivers/firewire/ohci.c ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg); reg 2247 drivers/firewire/ohci.c int reg, i; reg 2249 drivers/firewire/ohci.c reg = read_phy_reg(ohci, 2); reg 2250 drivers/firewire/ohci.c if (reg < 0) reg 2251 drivers/firewire/ohci.c return reg; reg 2252 drivers/firewire/ohci.c if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS) reg 2256 drivers/firewire/ohci.c reg = read_paged_phy_reg(ohci, 1, i + 10); reg 2257 drivers/firewire/ohci.c if (reg < 0) reg 2258 drivers/firewire/ohci.c return reg; reg 2259 drivers/firewire/ohci.c if (reg != id[i]) reg 208 drivers/firmware/arm_sdei.c struct sdei_registered_event *reg; reg 236 drivers/firmware/arm_sdei.c reg = kzalloc(sizeof(*reg), GFP_KERNEL); reg 237 drivers/firmware/arm_sdei.c if (!reg) { reg 242 drivers/firmware/arm_sdei.c reg->event_num = event_num; reg 243 drivers/firmware/arm_sdei.c reg->priority = event->priority; reg 245 drivers/firmware/arm_sdei.c reg->callback = cb; reg 246 drivers/firmware/arm_sdei.c reg->callback_arg = cb_arg; reg 247 drivers/firmware/arm_sdei.c event->registered = reg; reg 259 drivers/firmware/arm_sdei.c reg = per_cpu_ptr(regs, cpu); reg 261 drivers/firmware/arm_sdei.c reg->event_num = event->event_num; reg 262 drivers/firmware/arm_sdei.c reg->priority = event->priority; reg 263 drivers/firmware/arm_sdei.c reg->callback = cb; reg 264 drivers/firmware/arm_sdei.c reg->callback_arg = cb_arg; reg 570 drivers/firmware/arm_sdei.c struct sdei_registered_event *reg; reg 575 drivers/firmware/arm_sdei.c reg = per_cpu_ptr(arg->event->private_registered, smp_processor_id()); reg 577 drivers/firmware/arm_sdei.c reg, 0, 0); reg 96 drivers/firmware/trusted_foundations.c static void tf_cache_write_sec(unsigned long val, unsigned int reg) reg 100 drivers/firmware/trusted_foundations.c switch (reg) { reg 76 drivers/fpga/socfpga-a10.c static bool socfpga_a10_fpga_writeable_reg(struct device *dev, unsigned int reg) reg 78 drivers/fpga/socfpga-a10.c switch (reg) { reg 89 drivers/fpga/socfpga-a10.c static bool socfpga_a10_fpga_readable_reg(struct device *dev, unsigned int reg) reg 91 drivers/fpga/socfpga-a10.c switch (reg) { reg 239 drivers/fpga/socfpga-a10.c u32 reg, i; reg 242 drivers/fpga/socfpga-a10.c reg = socfpga_a10_fpga_read_stat(priv); reg 244 drivers/fpga/socfpga-a10.c if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR) reg 247 drivers/fpga/socfpga-a10.c if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_READY) reg 256 drivers/fpga/socfpga-a10.c u32 reg, i; reg 259 drivers/fpga/socfpga-a10.c reg = socfpga_a10_fpga_read_stat(priv); reg 261 drivers/fpga/socfpga-a10.c if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR) reg 264 drivers/fpga/socfpga-a10.c if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE) reg 395 drivers/fpga/socfpga-a10.c u32 reg; reg 427 drivers/fpga/socfpga-a10.c reg = socfpga_a10_fpga_read_stat(priv); reg 429 drivers/fpga/socfpga-a10.c if (((reg & A10_FPGAMGR_IMGCFG_STAT_F2S_USERMODE) == 0) || reg 430 drivers/fpga/socfpga-a10.c ((reg & A10_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN) == 0) || reg 431 drivers/fpga/socfpga-a10.c ((reg & A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN) == 0)) { reg 433 drivers/fpga/socfpga-a10.c "Timeout in final check. Status=%08xf\n", reg); reg 443 drivers/fpga/socfpga-a10.c u32 reg = socfpga_a10_fpga_read_stat(priv); reg 445 drivers/fpga/socfpga-a10.c if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_USERMODE) reg 448 drivers/fpga/socfpga-a10.c if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_READY) reg 451 drivers/fpga/socfpga-a10.c if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR) reg 454 drivers/fpga/socfpga-a10.c if ((reg & A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN) == 0) reg 61 drivers/fpga/ts73xx-fpga.c u8 reg; reg 65 drivers/fpga/ts73xx-fpga.c reg, !(reg & TS73XX_FPGA_WRITE_DONE), reg 81 drivers/fpga/ts73xx-fpga.c u8 reg; reg 84 drivers/fpga/ts73xx-fpga.c reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); reg 85 drivers/fpga/ts73xx-fpga.c reg |= TS73XX_FPGA_CONFIG_LOAD; reg 86 drivers/fpga/ts73xx-fpga.c writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); reg 89 drivers/fpga/ts73xx-fpga.c reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); reg 90 drivers/fpga/ts73xx-fpga.c reg &= ~TS73XX_FPGA_CONFIG_LOAD; reg 91 drivers/fpga/ts73xx-fpga.c writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); reg 93 drivers/fpga/ts73xx-fpga.c reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); reg 94 drivers/fpga/ts73xx-fpga.c if ((reg & TS73XX_FPGA_LOAD_OK) != TS73XX_FPGA_LOAD_OK) reg 284 drivers/fsi/fsi-core.c uint32_t reg; reg 308 drivers/fsi/fsi-core.c ®, sizeof(reg)); reg 1151 drivers/fsi/fsi-master-ast-cf.c unsigned int reg = 0; reg 1153 drivers/fsi/fsi-master-ast-cf.c regmap_read(master->scu, SCU_COPRO_CTRL, ®); reg 1154 drivers/fsi/fsi-master-ast-cf.c if (!(reg & SCU_COPRO_CLK_EN)) reg 130 drivers/fsi/fsi-master-hub.c __be32 reg; reg 136 drivers/fsi/fsi-master-hub.c reg = cpu_to_be32(0x80000000 >> bit); reg 138 drivers/fsi/fsi-master-hub.c rc = fsi_device_write(hub->upstream, FSI_MSENP0 + (4 * idx), ®, 4); reg 142 drivers/fsi/fsi-master-hub.c fsi_device_read(hub->upstream, FSI_MENP0 + (4 * idx), ®, 4); reg 168 drivers/fsi/fsi-master-hub.c __be32 reg; reg 171 drivers/fsi/fsi-master-hub.c reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK reg 173 drivers/fsi/fsi-master-hub.c rc = fsi_device_write(dev, FSI_MRESP0, ®, sizeof(reg)); reg 178 drivers/fsi/fsi-master-hub.c reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK reg 180 drivers/fsi/fsi-master-hub.c rc = fsi_device_write(dev, FSI_MRESP0, ®, sizeof(reg)); reg 184 drivers/fsi/fsi-master-hub.c reg = cpu_to_be32(FSI_MECTRL_EOAE | FSI_MECTRL_P8_AUTO_TERM); reg 185 drivers/fsi/fsi-master-hub.c rc = fsi_device_write(dev, FSI_MECTRL, ®, sizeof(reg)); reg 189 drivers/fsi/fsi-master-hub.c reg = cpu_to_be32(FSI_MMODE_EIP | FSI_MMODE_ECRC | FSI_MMODE_EPC reg 192 drivers/fsi/fsi-master-hub.c rc = fsi_device_write(dev, FSI_MMODE, ®, sizeof(reg)); reg 196 drivers/fsi/fsi-master-hub.c reg = cpu_to_be32(0xffff0000); reg 197 drivers/fsi/fsi-master-hub.c rc = fsi_device_write(dev, FSI_MDLYR, ®, sizeof(reg)); reg 201 drivers/fsi/fsi-master-hub.c reg = cpu_to_be32(~0); reg 202 drivers/fsi/fsi-master-hub.c rc = fsi_device_write(dev, FSI_MSENP0, ®, sizeof(reg)); reg 209 drivers/fsi/fsi-master-hub.c rc = fsi_device_write(dev, FSI_MCENP0, ®, sizeof(reg)); reg 213 drivers/fsi/fsi-master-hub.c rc = fsi_device_read(dev, FSI_MAEB, ®, sizeof(reg)); reg 217 drivers/fsi/fsi-master-hub.c reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK); reg 218 drivers/fsi/fsi-master-hub.c rc = fsi_device_write(dev, FSI_MRESP0, ®, sizeof(reg)); reg 222 drivers/fsi/fsi-master-hub.c rc = fsi_device_read(dev, FSI_MLEVP0, ®, sizeof(reg)); reg 227 drivers/fsi/fsi-master-hub.c reg = cpu_to_be32(FSI_MRESB_RST_GEN); reg 228 drivers/fsi/fsi-master-hub.c rc = fsi_device_write(dev, FSI_MRESB0, ®, sizeof(reg)); reg 232 drivers/fsi/fsi-master-hub.c reg = cpu_to_be32(FSI_MRESB_RST_ERR); reg 233 drivers/fsi/fsi-master-hub.c return fsi_device_write(dev, FSI_MRESB0, ®, sizeof(reg)); reg 240 drivers/fsi/fsi-master-hub.c uint32_t reg, links; reg 248 drivers/fsi/fsi-master-hub.c reg = be32_to_cpu(__reg); reg 249 drivers/fsi/fsi-master-hub.c links = (reg >> 8) & 0xff; reg 250 drivers/fsi/fsi-master-hub.c dev_dbg(dev, "hub version %08x (%d links)\n", reg, links); reg 507 drivers/fsi/fsi-occ.c u32 reg; reg 525 drivers/fsi/fsi-occ.c rc = of_property_read_u32(dev->of_node, "reg", ®); reg 528 drivers/fsi/fsi-occ.c occ->idx = ida_simple_get(&occ_ida, reg, reg + 1, reg 249 drivers/fsi/fsi-sbefifo.c static int sbefifo_regr(struct sbefifo *sbefifo, int reg, u32 *word) reg 254 drivers/fsi/fsi-sbefifo.c rc = fsi_device_read(sbefifo->fsi_dev, reg, &raw_word, reg 264 drivers/fsi/fsi-sbefifo.c static int sbefifo_regw(struct sbefifo *sbefifo, int reg, u32 word) reg 268 drivers/fsi/fsi-sbefifo.c return fsi_device_write(sbefifo->fsi_dev, reg, &raw_word, reg 68 drivers/gpio/gpio-adnp.c unsigned int reg = offset >> adnp->reg_shift; reg 73 drivers/gpio/gpio-adnp.c err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value); reg 82 drivers/gpio/gpio-adnp.c unsigned int reg = offset >> adnp->reg_shift; reg 87 drivers/gpio/gpio-adnp.c err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val); reg 96 drivers/gpio/gpio-adnp.c adnp_write(adnp, GPIO_PLR(adnp) + reg, val); reg 111 drivers/gpio/gpio-adnp.c unsigned int reg = offset >> adnp->reg_shift; reg 118 drivers/gpio/gpio-adnp.c err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value); reg 124 drivers/gpio/gpio-adnp.c err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value); reg 128 drivers/gpio/gpio-adnp.c err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value); reg 148 drivers/gpio/gpio-adnp.c unsigned int reg = offset >> adnp->reg_shift; reg 155 drivers/gpio/gpio-adnp.c err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val); reg 161 drivers/gpio/gpio-adnp.c err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val); reg 165 drivers/gpio/gpio-adnp.c err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val); reg 335 drivers/gpio/gpio-adnp.c unsigned int reg = d->hwirq >> adnp->reg_shift; reg 338 drivers/gpio/gpio-adnp.c adnp->irq_enable[reg] &= ~BIT(pos); reg 345 drivers/gpio/gpio-adnp.c unsigned int reg = d->hwirq >> adnp->reg_shift; reg 348 drivers/gpio/gpio-adnp.c adnp->irq_enable[reg] |= BIT(pos); reg 355 drivers/gpio/gpio-adnp.c unsigned int reg = d->hwirq >> adnp->reg_shift; reg 359 drivers/gpio/gpio-adnp.c adnp->irq_rise[reg] |= BIT(pos); reg 361 drivers/gpio/gpio-adnp.c adnp->irq_rise[reg] &= ~BIT(pos); reg 364 drivers/gpio/gpio-adnp.c adnp->irq_fall[reg] |= BIT(pos); reg 366 drivers/gpio/gpio-adnp.c adnp->irq_fall[reg] &= ~BIT(pos); reg 369 drivers/gpio/gpio-adnp.c adnp->irq_high[reg] |= BIT(pos); reg 371 drivers/gpio/gpio-adnp.c adnp->irq_high[reg] &= ~BIT(pos); reg 374 drivers/gpio/gpio-adnp.c adnp->irq_low[reg] |= BIT(pos); reg 376 drivers/gpio/gpio-adnp.c adnp->irq_low[reg] &= ~BIT(pos); reg 45 drivers/gpio/gpio-adp5588.c static int adp5588_gpio_read(struct i2c_client *client, u8 reg) reg 47 drivers/gpio/gpio-adp5588.c int ret = i2c_smbus_read_byte_data(client, reg); reg 55 drivers/gpio/gpio-adp5588.c static int adp5588_gpio_write(struct i2c_client *client, u8 reg, u8 val) reg 57 drivers/gpio/gpio-adp5588.c int ret = i2c_smbus_write_byte_data(client, reg, val); reg 239 drivers/gpio/gpio-altera.c int reg, ret; reg 249 drivers/gpio/gpio-altera.c if (of_property_read_u32(node, "altr,ngpio", ®)) reg 253 drivers/gpio/gpio-altera.c altera_gc->mmchip.gc.ngpio = reg; reg 274 drivers/gpio/gpio-altera.c if (of_property_read_u32(node, "altr,interrupt-type", ®)) { reg 279 drivers/gpio/gpio-altera.c altera_gc->interrupt_trigger = reg; reg 54 drivers/gpio/gpio-arizona.c unsigned int reg, val; reg 57 drivers/gpio/gpio-arizona.c reg = ARIZONA_GPIO1_CTRL + offset; reg 58 drivers/gpio/gpio-arizona.c ret = regmap_read(arizona->regmap, reg, &val); reg 71 drivers/gpio/gpio-arizona.c ret = regcache_drop_region(arizona->regmap, reg, reg); reg 78 drivers/gpio/gpio-arizona.c ret = regmap_read(arizona->regmap, reg, &val); reg 210 drivers/gpio/gpio-aspeed.c const enum aspeed_gpio_reg reg) reg 212 drivers/gpio/gpio-aspeed.c switch (reg) { reg 311 drivers/gpio/gpio-aspeed.c u32 bit, reg; reg 321 drivers/gpio/gpio-aspeed.c reg = ioread32(c1); reg 323 drivers/gpio/gpio-aspeed.c reg |= bit; reg 325 drivers/gpio/gpio-aspeed.c reg &= ~bit; reg 326 drivers/gpio/gpio-aspeed.c iowrite32(reg, c1); reg 329 drivers/gpio/gpio-aspeed.c reg = ioread32(c0); reg 331 drivers/gpio/gpio-aspeed.c reg |= bit; reg 333 drivers/gpio/gpio-aspeed.c reg &= ~bit; reg 334 drivers/gpio/gpio-aspeed.c iowrite32(reg, c0); reg 395 drivers/gpio/gpio-aspeed.c u32 reg; reg 398 drivers/gpio/gpio-aspeed.c reg = gpio->dcache[GPIO_BANK(offset)]; reg 401 drivers/gpio/gpio-aspeed.c reg |= GPIO_BIT(offset); reg 403 drivers/gpio/gpio-aspeed.c reg &= ~GPIO_BIT(offset); reg 404 drivers/gpio/gpio-aspeed.c gpio->dcache[GPIO_BANK(offset)] = reg; reg 406 drivers/gpio/gpio-aspeed.c iowrite32(reg, addr); reg 433 drivers/gpio/gpio-aspeed.c u32 reg; reg 440 drivers/gpio/gpio-aspeed.c reg = ioread32(addr); reg 441 drivers/gpio/gpio-aspeed.c reg &= ~GPIO_BIT(offset); reg 444 drivers/gpio/gpio-aspeed.c iowrite32(reg, addr); reg 461 drivers/gpio/gpio-aspeed.c u32 reg; reg 468 drivers/gpio/gpio-aspeed.c reg = ioread32(addr); reg 469 drivers/gpio/gpio-aspeed.c reg |= GPIO_BIT(offset); reg 473 drivers/gpio/gpio-aspeed.c iowrite32(reg, addr); reg 558 drivers/gpio/gpio-aspeed.c u32 reg, bit; reg 572 drivers/gpio/gpio-aspeed.c reg = ioread32(addr); reg 574 drivers/gpio/gpio-aspeed.c reg |= bit; reg 576 drivers/gpio/gpio-aspeed.c reg &= ~bit; reg 577 drivers/gpio/gpio-aspeed.c iowrite32(reg, addr); reg 599 drivers/gpio/gpio-aspeed.c u32 bit, reg; reg 637 drivers/gpio/gpio-aspeed.c reg = ioread32(addr); reg 638 drivers/gpio/gpio-aspeed.c reg = (reg & ~bit) | type0; reg 639 drivers/gpio/gpio-aspeed.c iowrite32(reg, addr); reg 642 drivers/gpio/gpio-aspeed.c reg = ioread32(addr); reg 643 drivers/gpio/gpio-aspeed.c reg = (reg & ~bit) | type1; reg 644 drivers/gpio/gpio-aspeed.c iowrite32(reg, addr); reg 647 drivers/gpio/gpio-aspeed.c reg = ioread32(addr); reg 648 drivers/gpio/gpio-aspeed.c reg = (reg & ~bit) | type2; reg 649 drivers/gpio/gpio-aspeed.c iowrite32(reg, addr); reg 666 drivers/gpio/gpio-aspeed.c unsigned long reg; reg 675 drivers/gpio/gpio-aspeed.c reg = ioread32(bank_reg(data, bank, reg_irq_status)); reg 677 drivers/gpio/gpio-aspeed.c for_each_set_bit(p, ®, 32) { reg 43 drivers/gpio/gpio-ath79.c static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg) reg 45 drivers/gpio/gpio-ath79.c return readl(ctrl->base + reg); reg 49 drivers/gpio/gpio-ath79.c unsigned reg, u32 val) reg 51 drivers/gpio/gpio-ath79.c writel(val, ctrl->base + reg); reg 55 drivers/gpio/gpio-ath79.c struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits) reg 59 drivers/gpio/gpio-ath79.c old_val = ath79_gpio_read(ctrl, reg); reg 63 drivers/gpio/gpio-ath79.c ath79_gpio_write(ctrl, reg, new_val); reg 34 drivers/gpio/gpio-creg-snps.c u32 reg, reg_shift, value; reg 45 drivers/gpio/gpio-creg-snps.c reg = readl(hcg->regs); reg 46 drivers/gpio/gpio-creg-snps.c reg &= ~(GENMASK(layout->bit_per_gpio[i] - 1, 0) << reg_shift); reg 47 drivers/gpio/gpio-creg-snps.c reg |= (value << reg_shift); reg 48 drivers/gpio/gpio-creg-snps.c writel(reg, hcg->regs); reg 83 drivers/gpio/gpio-crystalcove.c int reg; reg 100 drivers/gpio/gpio-crystalcove.c reg = GPIO0P0CTLI; reg 102 drivers/gpio/gpio-crystalcove.c reg = GPIO1P0CTLI; reg 105 drivers/gpio/gpio-crystalcove.c reg = GPIO0P0CTLO; reg 107 drivers/gpio/gpio-crystalcove.c reg = GPIO1P0CTLO; reg 110 drivers/gpio/gpio-crystalcove.c return reg + gpio % 8; reg 127 drivers/gpio/gpio-crystalcove.c int reg = to_reg(gpio, CTRL_IN); reg 129 drivers/gpio/gpio-crystalcove.c regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value); reg 135 drivers/gpio/gpio-crystalcove.c int reg = to_reg(gpio, CTRL_OUT); reg 137 drivers/gpio/gpio-crystalcove.c if (reg < 0) reg 140 drivers/gpio/gpio-crystalcove.c return regmap_write(cg->regmap, reg, CTLO_INPUT_SET); reg 147 drivers/gpio/gpio-crystalcove.c int reg = to_reg(gpio, CTRL_OUT); reg 149 drivers/gpio/gpio-crystalcove.c if (reg < 0) reg 152 drivers/gpio/gpio-crystalcove.c return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value); reg 159 drivers/gpio/gpio-crystalcove.c int ret, reg = to_reg(gpio, CTRL_IN); reg 161 drivers/gpio/gpio-crystalcove.c if (reg < 0) reg 164 drivers/gpio/gpio-crystalcove.c ret = regmap_read(cg->regmap, reg, &val); reg 175 drivers/gpio/gpio-crystalcove.c int reg = to_reg(gpio, CTRL_OUT); reg 177 drivers/gpio/gpio-crystalcove.c if (reg < 0) reg 181 drivers/gpio/gpio-crystalcove.c regmap_update_bits(cg->regmap, reg, 1, 1); reg 183 drivers/gpio/gpio-crystalcove.c regmap_update_bits(cg->regmap, reg, 1, 0); reg 61 drivers/gpio/gpio-cs5535.c unsigned int reg) reg 63 drivers/gpio/gpio-cs5535.c unsigned long addr = chip->base + 0x80 + reg; reg 74 drivers/gpio/gpio-cs5535.c if (reg != GPIO_POSITIVE_EDGE_STS && reg != GPIO_NEGATIVE_EDGE_STS) { reg 84 drivers/gpio/gpio-cs5535.c unsigned int reg) reg 88 drivers/gpio/gpio-cs5535.c outl(1 << offset, chip->base + reg); reg 91 drivers/gpio/gpio-cs5535.c errata_outl(chip, 1 << (offset - 16), reg); reg 94 drivers/gpio/gpio-cs5535.c void cs5535_gpio_set(unsigned offset, unsigned int reg) reg 100 drivers/gpio/gpio-cs5535.c __cs5535_gpio_set(chip, offset, reg); reg 106 drivers/gpio/gpio-cs5535.c unsigned int reg) reg 110 drivers/gpio/gpio-cs5535.c outl(1 << (offset + 16), chip->base + reg); reg 113 drivers/gpio/gpio-cs5535.c errata_outl(chip, 1 << offset, reg); reg 116 drivers/gpio/gpio-cs5535.c void cs5535_gpio_clear(unsigned offset, unsigned int reg) reg 122 drivers/gpio/gpio-cs5535.c __cs5535_gpio_clear(chip, offset, reg); reg 127 drivers/gpio/gpio-cs5535.c int cs5535_gpio_isset(unsigned offset, unsigned int reg) reg 136 drivers/gpio/gpio-cs5535.c val = inl(chip->base + reg); reg 139 drivers/gpio/gpio-cs5535.c val = inl(chip->base + 0x80 + reg); reg 141 drivers/gpio/gpio-eic-sprd.c u16 reg, unsigned int val) reg 150 drivers/gpio/gpio-eic-sprd.c tmp = readl_relaxed(base + reg); reg 157 drivers/gpio/gpio-eic-sprd.c writel_relaxed(tmp, base + reg); reg 161 drivers/gpio/gpio-eic-sprd.c static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg) reg 167 drivers/gpio/gpio-eic-sprd.c return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset))); reg 214 drivers/gpio/gpio-eic-sprd.c u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4; reg 215 drivers/gpio/gpio-eic-sprd.c u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK; reg 218 drivers/gpio/gpio-eic-sprd.c writel_relaxed(value, base + reg); reg 508 drivers/gpio/gpio-eic-sprd.c unsigned long reg; reg 512 drivers/gpio/gpio-eic-sprd.c reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) & reg 516 drivers/gpio/gpio-eic-sprd.c reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) & reg 520 drivers/gpio/gpio-eic-sprd.c reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) & reg 524 drivers/gpio/gpio-eic-sprd.c reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) & reg 532 drivers/gpio/gpio-eic-sprd.c for_each_set_bit(n, ®, SPRD_EIC_PER_BANK_NR) { reg 126 drivers/gpio/gpio-em.c unsigned int reg, offset, shift; reg 138 drivers/gpio/gpio-em.c reg = GIO_IDT(offset >> 3); reg 149 drivers/gpio/gpio-em.c tmp = em_gio_read(p, reg); reg 152 drivers/gpio/gpio-em.c em_gio_write(p, reg, tmp); reg 199 drivers/gpio/gpio-em.c static void __em_gio_set(struct gpio_chip *chip, unsigned int reg, reg 203 drivers/gpio/gpio-em.c em_gio_write(gpio_to_priv(chip), reg, reg 34 drivers/gpio/gpio-exar.c static void exar_update(struct gpio_chip *chip, unsigned int reg, int val, reg 41 drivers/gpio/gpio-exar.c temp = readb(exar_gpio->regs + reg); reg 45 drivers/gpio/gpio-exar.c writeb(temp, exar_gpio->regs + reg); reg 61 drivers/gpio/gpio-exar.c static int exar_get(struct gpio_chip *chip, unsigned int reg) reg 67 drivers/gpio/gpio-exar.c value = readb(exar_gpio->regs + reg); reg 74 drivers/gpio/gpio-f7188x.c static inline int superio_inb(int base, int reg) reg 76 drivers/gpio/gpio-f7188x.c outb(reg, base); reg 80 drivers/gpio/gpio-f7188x.c static int superio_inw(int base, int reg) reg 84 drivers/gpio/gpio-f7188x.c outb(reg++, base); reg 86 drivers/gpio/gpio-f7188x.c outb(reg, base); reg 92 drivers/gpio/gpio-f7188x.c static inline void superio_outb(int base, int reg, int val) reg 94 drivers/gpio/gpio-f7188x.c outb(reg, base); reg 53 drivers/gpio/gpio-htc-egpio.c static inline void egpio_writew(u16 value, struct egpio_info *ei, int reg) reg 55 drivers/gpio/gpio-htc-egpio.c writew(value, ei->base_addr + (reg << ei->bus_shift)); reg 58 drivers/gpio/gpio-htc-egpio.c static inline u16 egpio_readw(struct egpio_info *ei, int reg) reg 60 drivers/gpio/gpio-htc-egpio.c return readw(ei->base_addr + (reg << ei->bus_shift)); reg 140 drivers/gpio/gpio-htc-egpio.c int reg; reg 148 drivers/gpio/gpio-htc-egpio.c reg = egpio->reg_start + egpio_pos(ei, offset); reg 153 drivers/gpio/gpio-htc-egpio.c value = egpio_readw(ei, reg); reg 155 drivers/gpio/gpio-htc-egpio.c ei->base_addr, reg << ei->bus_shift, value); reg 179 drivers/gpio/gpio-htc-egpio.c int reg; reg 188 drivers/gpio/gpio-htc-egpio.c reg = egpio->reg_start + pos; reg 192 drivers/gpio/gpio-htc-egpio.c reg, (egpio->cached_values >> shift) & ei->reg_mask); reg 199 drivers/gpio/gpio-htc-egpio.c egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg); reg 240 drivers/gpio/gpio-htc-egpio.c int reg = egpio->reg_start + egpio_pos(ei, shift); reg 245 drivers/gpio/gpio-htc-egpio.c pr_debug("EGPIO: setting %x to %x, was %x\n", reg, reg 247 drivers/gpio/gpio-htc-egpio.c egpio_readw(ei, reg)); reg 250 drivers/gpio/gpio-htc-egpio.c & ei->reg_mask, ei, reg); reg 56 drivers/gpio/gpio-ich.c #define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start) reg 57 drivers/gpio/gpio-ich.c #define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start) reg 103 drivers/gpio/gpio-ich.c static int ichx_write_bit(int reg, unsigned nr, int val, int verify) reg 112 drivers/gpio/gpio-ich.c if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) reg 115 drivers/gpio/gpio-ich.c data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], reg 122 drivers/gpio/gpio-ich.c ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr], reg 124 drivers/gpio/gpio-ich.c if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) reg 127 drivers/gpio/gpio-ich.c tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], reg 135 drivers/gpio/gpio-ich.c static int ichx_read_bit(int reg, unsigned nr) reg 144 drivers/gpio/gpio-ich.c data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], reg 147 drivers/gpio/gpio-ich.c if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) reg 72 drivers/gpio/gpio-intel-mid.c u8 reg = offset / 32; reg 74 drivers/gpio/gpio-intel-mid.c return priv->reg_base + reg_type * nreg * 4 + reg * 4; reg 82 drivers/gpio/gpio-intel-mid.c u8 reg = offset / 16; reg 84 drivers/gpio/gpio-intel-mid.c return priv->reg_base + reg_type * nreg * 4 + reg * 4; reg 299 drivers/gpio/gpio-intel-mid.c void __iomem *reg; reg 304 drivers/gpio/gpio-intel-mid.c reg = gpio_reg(&priv->chip, base, GRER); reg 305 drivers/gpio/gpio-intel-mid.c writel(0, reg); reg 307 drivers/gpio/gpio-intel-mid.c reg = gpio_reg(&priv->chip, base, GFER); reg 308 drivers/gpio/gpio-intel-mid.c writel(0, reg); reg 310 drivers/gpio/gpio-intel-mid.c reg = gpio_reg(&priv->chip, base, GEDR); reg 311 drivers/gpio/gpio-intel-mid.c writel(~0, reg); reg 105 drivers/gpio/gpio-it87.c static inline int superio_inb(int reg) reg 107 drivers/gpio/gpio-it87.c outb(reg, REG); reg 111 drivers/gpio/gpio-it87.c static inline void superio_outb(int val, int reg) reg 113 drivers/gpio/gpio-it87.c outb(reg, REG); reg 117 drivers/gpio/gpio-it87.c static inline int superio_inw(int reg) reg 121 drivers/gpio/gpio-it87.c outb(reg++, REG); reg 123 drivers/gpio/gpio-it87.c outb(reg, REG); reg 128 drivers/gpio/gpio-it87.c static inline void superio_outw(int val, int reg) reg 130 drivers/gpio/gpio-it87.c outb(reg++, REG); reg 132 drivers/gpio/gpio-it87.c outb(reg, REG); reg 136 drivers/gpio/gpio-it87.c static inline void superio_set_mask(int mask, int reg) reg 138 drivers/gpio/gpio-it87.c u8 curr_val = superio_inb(reg); reg 142 drivers/gpio/gpio-it87.c superio_outb(new_val, reg); reg 145 drivers/gpio/gpio-it87.c static inline void superio_clear_mask(int mask, int reg) reg 147 drivers/gpio/gpio-it87.c u8 curr_val = superio_inb(reg); reg 151 drivers/gpio/gpio-it87.c superio_outb(new_val, reg); reg 189 drivers/gpio/gpio-it87.c u16 reg; reg 194 drivers/gpio/gpio-it87.c reg = (gpio_num / 8) + it87_gpio->io_base; reg 196 drivers/gpio/gpio-it87.c return !!(inb(reg) & mask); reg 228 drivers/gpio/gpio-it87.c u16 reg; reg 232 drivers/gpio/gpio-it87.c reg = (gpio_num / 8) + it87_gpio->io_base; reg 234 drivers/gpio/gpio-it87.c curr_vals = inb(reg); reg 236 drivers/gpio/gpio-it87.c outb(curr_vals | mask, reg); reg 238 drivers/gpio/gpio-it87.c outb(curr_vals & ~mask, reg); reg 108 drivers/gpio/gpio-janz-ttl.c static void ttl_write_reg(struct ttl_module *mod, u8 reg, u16 val) reg 110 drivers/gpio/gpio-janz-ttl.c iowrite16be(reg, &mod->regs->control); reg 35 drivers/gpio/gpio-kempld.c u8 reg, u8 bit, u8 val) reg 39 drivers/gpio/gpio-kempld.c status = kempld_read8(pld, reg); reg 44 drivers/gpio/gpio-kempld.c kempld_write8(pld, reg, status); reg 47 drivers/gpio/gpio-kempld.c static int kempld_gpio_get_bit(struct kempld_device_data *pld, u8 reg, u8 bit) reg 52 drivers/gpio/gpio-kempld.c status = kempld_read8(pld, reg); reg 71 drivers/gpio/gpio-lp3943.c return lp3943_update_bits(lp3943, mux[offset].reg, mux[offset].mask, reg 117 drivers/gpio/gpio-lp3943.c err = lp3943_read_byte(lp3943, mux[offset].reg, &read); reg 70 drivers/gpio/gpio-lpc18xx.c u32 pin, u32 reg) reg 72 drivers/gpio/gpio-lpc18xx.c writel_relaxed(BIT(pin), ic->base + reg); reg 84 drivers/gpio/gpio-lynxpoint.c int reg) reg 89 drivers/gpio/gpio-lynxpoint.c if (reg == LP_CONFIG1 || reg == LP_CONFIG2) reg 96 drivers/gpio/gpio-lynxpoint.c return lg->reg_base + reg + reg_offset; reg 102 drivers/gpio/gpio-lynxpoint.c unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); reg 114 drivers/gpio/gpio-lynxpoint.c if (!(inl(reg) & USE_SEL_BIT)) reg 142 drivers/gpio/gpio-lynxpoint.c unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); reg 148 drivers/gpio/gpio-lynxpoint.c value = inl(reg); reg 166 drivers/gpio/gpio-lynxpoint.c outl(value, reg); reg 180 drivers/gpio/gpio-lynxpoint.c unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); reg 181 drivers/gpio/gpio-lynxpoint.c return !!(inl(reg) & IN_LVL_BIT); reg 187 drivers/gpio/gpio-lynxpoint.c unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); reg 193 drivers/gpio/gpio-lynxpoint.c outl(inl(reg) | OUT_LVL_BIT, reg); reg 195 drivers/gpio/gpio-lynxpoint.c outl(inl(reg) & ~OUT_LVL_BIT, reg); reg 203 drivers/gpio/gpio-lynxpoint.c unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); reg 207 drivers/gpio/gpio-lynxpoint.c outl(inl(reg) | DIR_BIT, reg); reg 217 drivers/gpio/gpio-lynxpoint.c unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1); reg 223 drivers/gpio/gpio-lynxpoint.c outl(inl(reg) & ~DIR_BIT, reg); reg 235 drivers/gpio/gpio-lynxpoint.c unsigned long reg, ena, pending; reg 240 drivers/gpio/gpio-lynxpoint.c reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); reg 244 drivers/gpio/gpio-lynxpoint.c pending = inl(reg) & inl(ena); reg 250 drivers/gpio/gpio-lynxpoint.c outl(BIT(pin), reg); reg 272 drivers/gpio/gpio-lynxpoint.c unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); reg 276 drivers/gpio/gpio-lynxpoint.c outl(inl(reg) | BIT(hwirq % 32), reg); reg 285 drivers/gpio/gpio-lynxpoint.c unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); reg 289 drivers/gpio/gpio-lynxpoint.c outl(inl(reg) & ~BIT(hwirq % 32), reg); reg 306 drivers/gpio/gpio-lynxpoint.c unsigned long reg; reg 311 drivers/gpio/gpio-lynxpoint.c reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); reg 312 drivers/gpio/gpio-lynxpoint.c outl(0, reg); reg 314 drivers/gpio/gpio-lynxpoint.c reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); reg 315 drivers/gpio/gpio-lynxpoint.c outl(0xffffffff, reg); reg 413 drivers/gpio/gpio-lynxpoint.c unsigned long reg; reg 419 drivers/gpio/gpio-lynxpoint.c reg = lp_gpio_reg(&lg->chip, i, LP_CONFIG2); reg 420 drivers/gpio/gpio-lynxpoint.c outl(inl(reg) & ~GPINDIS_BIT, reg); reg 16 drivers/gpio/gpio-max7300.c static int max7300_i2c_write(struct device *dev, unsigned int reg, reg 21 drivers/gpio/gpio-max7300.c return i2c_smbus_write_byte_data(client, reg, val); reg 24 drivers/gpio/gpio-max7300.c static int max7300_i2c_read(struct device *dev, unsigned int reg) reg 28 drivers/gpio/gpio-max7300.c return i2c_smbus_read_byte_data(client, reg); reg 19 drivers/gpio/gpio-max7301.c static int max7301_spi_write(struct device *dev, unsigned int reg, reg 23 drivers/gpio/gpio-max7301.c u16 word = ((reg & 0x7F) << 8) | (val & 0xFF); reg 30 drivers/gpio/gpio-max7301.c static int max7301_spi_read(struct device *dev, unsigned int reg) reg 36 drivers/gpio/gpio-max7301.c word = 0x8000 | (reg << 8); reg 23 drivers/gpio/gpio-mc9s08dz60.c static void mc9s_gpio_to_reg_and_bit(int offset, u8 *reg, u8 *bit) reg 25 drivers/gpio/gpio-mc9s08dz60.c *reg = 0x20 + offset / GPIO_NUM_PER_GROUP; reg 31 drivers/gpio/gpio-mc9s08dz60.c u8 reg, bit; reg 35 drivers/gpio/gpio-mc9s08dz60.c mc9s_gpio_to_reg_and_bit(offset, ®, &bit); reg 36 drivers/gpio/gpio-mc9s08dz60.c value = i2c_smbus_read_byte_data(mc9s->client, reg); reg 43 drivers/gpio/gpio-mc9s08dz60.c u8 reg, bit; reg 46 drivers/gpio/gpio-mc9s08dz60.c mc9s_gpio_to_reg_and_bit(offset, ®, &bit); reg 47 drivers/gpio/gpio-mc9s08dz60.c value = i2c_smbus_read_byte_data(mc9s->client, reg); reg 54 drivers/gpio/gpio-mc9s08dz60.c return i2c_smbus_write_byte_data(mc9s->client, reg, value); reg 90 drivers/gpio/gpio-merrifield.c u8 reg = offset / 32; reg 92 drivers/gpio/gpio-merrifield.c return priv->reg_base + reg_type_offset + reg * 4; reg 367 drivers/gpio/gpio-merrifield.c void __iomem *reg; reg 372 drivers/gpio/gpio-merrifield.c reg = gpio_reg(&priv->chip, base, GRER); reg 373 drivers/gpio/gpio-merrifield.c writel(0, reg); reg 375 drivers/gpio/gpio-merrifield.c reg = gpio_reg(&priv->chip, base, GFER); reg 376 drivers/gpio/gpio-merrifield.c writel(0, reg); reg 80 drivers/gpio/gpio-ml-ioh.c struct ioh_regs __iomem *reg; reg 99 drivers/gpio/gpio-ml-ioh.c reg_val = ioread32(&chip->reg->regs[chip->ch].po); reg 105 drivers/gpio/gpio-ml-ioh.c iowrite32(reg_val, &chip->reg->regs[chip->ch].po); reg 113 drivers/gpio/gpio-ml-ioh.c return !!(ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr)); reg 125 drivers/gpio/gpio-ml-ioh.c pm = ioread32(&chip->reg->regs[chip->ch].pm) & reg 128 drivers/gpio/gpio-ml-ioh.c iowrite32(pm, &chip->reg->regs[chip->ch].pm); reg 130 drivers/gpio/gpio-ml-ioh.c reg_val = ioread32(&chip->reg->regs[chip->ch].po); reg 135 drivers/gpio/gpio-ml-ioh.c iowrite32(reg_val, &chip->reg->regs[chip->ch].po); reg 149 drivers/gpio/gpio-ml-ioh.c pm = ioread32(&chip->reg->regs[chip->ch].pm) & reg 152 drivers/gpio/gpio-ml-ioh.c iowrite32(pm, &chip->reg->regs[chip->ch].pm); reg 168 drivers/gpio/gpio-ml-ioh.c ioread32(&chip->reg->regs[chip->ch].po); reg 170 drivers/gpio/gpio-ml-ioh.c ioread32(&chip->reg->regs[chip->ch].pm); reg 172 drivers/gpio/gpio-ml-ioh.c ioread32(&chip->reg->regs[chip->ch].ien); reg 174 drivers/gpio/gpio-ml-ioh.c ioread32(&chip->reg->regs[chip->ch].imask); reg 176 drivers/gpio/gpio-ml-ioh.c ioread32(&chip->reg->regs[chip->ch].im_0); reg 178 drivers/gpio/gpio-ml-ioh.c ioread32(&chip->reg->regs[chip->ch].im_1); reg 181 drivers/gpio/gpio-ml-ioh.c ioread32(&chip->reg->ioh_sel_reg[i]); reg 194 drivers/gpio/gpio-ml-ioh.c &chip->reg->regs[chip->ch].po); reg 196 drivers/gpio/gpio-ml-ioh.c &chip->reg->regs[chip->ch].pm); reg 198 drivers/gpio/gpio-ml-ioh.c &chip->reg->regs[chip->ch].ien); reg 200 drivers/gpio/gpio-ml-ioh.c &chip->reg->regs[chip->ch].imask); reg 202 drivers/gpio/gpio-ml-ioh.c &chip->reg->regs[chip->ch].im_0); reg 204 drivers/gpio/gpio-ml-ioh.c &chip->reg->regs[chip->ch].im_1); reg 207 drivers/gpio/gpio-ml-ioh.c &chip->reg->ioh_sel_reg[i]); reg 250 drivers/gpio/gpio-ml-ioh.c im_reg = &chip->reg->regs[chip->ch].im_0; reg 253 drivers/gpio/gpio-ml-ioh.c im_reg = &chip->reg->regs[chip->ch].im_1; reg 290 drivers/gpio/gpio-ml-ioh.c iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr); reg 293 drivers/gpio/gpio-ml-ioh.c iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr); reg 296 drivers/gpio/gpio-ml-ioh.c ien = ioread32(&chip->reg->regs[chip->ch].ien); reg 297 drivers/gpio/gpio-ml-ioh.c iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien); reg 310 drivers/gpio/gpio-ml-ioh.c &chip->reg->regs[chip->ch].imaskclr); reg 319 drivers/gpio/gpio-ml-ioh.c &chip->reg->regs[chip->ch].imask); reg 330 drivers/gpio/gpio-ml-ioh.c ien = ioread32(&chip->reg->regs[chip->ch].ien); reg 332 drivers/gpio/gpio-ml-ioh.c iowrite32(ien, &chip->reg->regs[chip->ch].ien); reg 344 drivers/gpio/gpio-ml-ioh.c ien = ioread32(&chip->reg->regs[chip->ch].ien); reg 346 drivers/gpio/gpio-ml-ioh.c iowrite32(ien, &chip->reg->regs[chip->ch].ien); reg 358 drivers/gpio/gpio-ml-ioh.c reg_val = ioread32(&chip->reg->regs[i].istatus); reg 365 drivers/gpio/gpio-ml-ioh.c &chip->reg->regs[chip->ch].iclr); reg 442 drivers/gpio/gpio-ml-ioh.c chip->reg = chip->base; reg 567 drivers/gpio/gpio-ml-ioh.c iowrite32(0x01, &chip->reg->srst); reg 568 drivers/gpio/gpio-ml-ioh.c iowrite32(0x00, &chip->reg->srst); reg 63 drivers/gpio/gpio-mmio.c static void bgpio_write8(void __iomem *reg, unsigned long data) reg 65 drivers/gpio/gpio-mmio.c writeb(data, reg); reg 68 drivers/gpio/gpio-mmio.c static unsigned long bgpio_read8(void __iomem *reg) reg 70 drivers/gpio/gpio-mmio.c return readb(reg); reg 73 drivers/gpio/gpio-mmio.c static void bgpio_write16(void __iomem *reg, unsigned long data) reg 75 drivers/gpio/gpio-mmio.c writew(data, reg); reg 78 drivers/gpio/gpio-mmio.c static unsigned long bgpio_read16(void __iomem *reg) reg 80 drivers/gpio/gpio-mmio.c return readw(reg); reg 83 drivers/gpio/gpio-mmio.c static void bgpio_write32(void __iomem *reg, unsigned long data) reg 85 drivers/gpio/gpio-mmio.c writel(data, reg); reg 88 drivers/gpio/gpio-mmio.c static unsigned long bgpio_read32(void __iomem *reg) reg 90 drivers/gpio/gpio-mmio.c return readl(reg); reg 94 drivers/gpio/gpio-mmio.c static void bgpio_write64(void __iomem *reg, unsigned long data) reg 96 drivers/gpio/gpio-mmio.c writeq(data, reg); reg 99 drivers/gpio/gpio-mmio.c static unsigned long bgpio_read64(void __iomem *reg) reg 101 drivers/gpio/gpio-mmio.c return readq(reg); reg 105 drivers/gpio/gpio-mmio.c static void bgpio_write16be(void __iomem *reg, unsigned long data) reg 107 drivers/gpio/gpio-mmio.c iowrite16be(data, reg); reg 110 drivers/gpio/gpio-mmio.c static unsigned long bgpio_read16be(void __iomem *reg) reg 112 drivers/gpio/gpio-mmio.c return ioread16be(reg); reg 115 drivers/gpio/gpio-mmio.c static void bgpio_write32be(void __iomem *reg, unsigned long data) reg 117 drivers/gpio/gpio-mmio.c iowrite32be(data, reg); reg 120 drivers/gpio/gpio-mmio.c static unsigned long bgpio_read32be(void __iomem *reg) reg 122 drivers/gpio/gpio-mmio.c return ioread32be(reg); reg 290 drivers/gpio/gpio-mmio.c void __iomem *reg) reg 302 drivers/gpio/gpio-mmio.c gc->write_reg(reg, gc->bgpio_data); reg 220 drivers/gpio/gpio-mpc8xxx.c void __iomem *reg; reg 225 drivers/gpio/gpio-mpc8xxx.c reg = mpc8xxx_gc->regs + GPIO_ICR; reg 228 drivers/gpio/gpio-mpc8xxx.c reg = mpc8xxx_gc->regs + GPIO_ICR2; reg 236 drivers/gpio/gpio-mpc8xxx.c gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) reg 244 drivers/gpio/gpio-mpc8xxx.c gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) reg 251 drivers/gpio/gpio-mpc8xxx.c gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))); reg 93 drivers/gpio/gpio-msic.c int reg; reg 95 drivers/gpio/gpio-msic.c reg = msic_gpio_to_oreg(offset); reg 96 drivers/gpio/gpio-msic.c if (reg < 0) reg 97 drivers/gpio/gpio-msic.c return reg; reg 99 drivers/gpio/gpio-msic.c return intel_msic_reg_update(reg, MSIC_GPIO_DIR_IN, MSIC_GPIO_DIR_MASK); reg 105 drivers/gpio/gpio-msic.c int reg; reg 111 drivers/gpio/gpio-msic.c reg = msic_gpio_to_oreg(offset); reg 112 drivers/gpio/gpio-msic.c if (reg < 0) reg 113 drivers/gpio/gpio-msic.c return reg; reg 115 drivers/gpio/gpio-msic.c return intel_msic_reg_update(reg, value, mask); reg 122 drivers/gpio/gpio-msic.c int reg; reg 124 drivers/gpio/gpio-msic.c reg = msic_gpio_to_ireg(offset); reg 125 drivers/gpio/gpio-msic.c if (reg < 0) reg 126 drivers/gpio/gpio-msic.c return reg; reg 128 drivers/gpio/gpio-msic.c ret = intel_msic_reg_read(reg, &r); reg 137 drivers/gpio/gpio-msic.c int reg; reg 139 drivers/gpio/gpio-msic.c reg = msic_gpio_to_oreg(offset); reg 140 drivers/gpio/gpio-msic.c if (reg < 0) reg 143 drivers/gpio/gpio-msic.c intel_msic_reg_update(reg, !!value , MSIC_GPIO_DOUT_MASK); reg 182 drivers/gpio/gpio-msic.c int reg; reg 191 drivers/gpio/gpio-msic.c reg = msic_gpio_to_ireg(offset); reg 192 drivers/gpio/gpio-msic.c if (reg < 0) reg 200 drivers/gpio/gpio-msic.c intel_msic_reg_update(reg, trig, MSIC_GPIO_INTCNT_MASK); reg 178 drivers/gpio/gpio-mxc.c void __iomem *reg = port->base; reg 224 drivers/gpio/gpio-mxc.c reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ reg 226 drivers/gpio/gpio-mxc.c val = readl(reg) & ~(0x3 << (bit << 1)); reg 227 drivers/gpio/gpio-mxc.c writel(val | (edge << (bit << 1)), reg); reg 237 drivers/gpio/gpio-mxc.c void __iomem *reg = port->base; reg 241 drivers/gpio/gpio-mxc.c reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ reg 243 drivers/gpio/gpio-mxc.c val = readl(reg); reg 257 drivers/gpio/gpio-mxc.c writel(val | (edge << (bit << 1)), reg); reg 54 drivers/gpio/gpio-octeon.c u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR); reg 55 drivers/gpio/gpio-octeon.c cvmx_write_csr(reg, mask); reg 92 drivers/gpio/gpio-omap.c static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set) reg 94 drivers/gpio/gpio-omap.c u32 val = readl_relaxed(reg); reg 101 drivers/gpio/gpio-omap.c writel_relaxed(val, reg); reg 118 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base; reg 122 drivers/gpio/gpio-omap.c reg += bank->regs->set_dataout; reg 125 drivers/gpio/gpio-omap.c reg += bank->regs->clr_dataout; reg 129 drivers/gpio/gpio-omap.c writel_relaxed(l, reg); reg 325 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base + bank->regs->irqctrl; reg 327 drivers/gpio/gpio-omap.c writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg); reg 334 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base; reg 340 drivers/gpio/gpio-omap.c reg += bank->regs->irqctrl; reg 342 drivers/gpio/gpio-omap.c l = readl_relaxed(reg); reg 352 drivers/gpio/gpio-omap.c writel_relaxed(l, reg); reg 355 drivers/gpio/gpio-omap.c reg += bank->regs->edgectrl2; reg 357 drivers/gpio/gpio-omap.c reg += bank->regs->edgectrl1; reg 360 drivers/gpio/gpio-omap.c l = readl_relaxed(reg); reg 366 drivers/gpio/gpio-omap.c writel_relaxed(l, reg); reg 374 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base + bank->regs->pinctrl; reg 377 drivers/gpio/gpio-omap.c writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); reg 381 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base + bank->regs->ctrl; reg 384 drivers/gpio/gpio-omap.c ctrl = readl_relaxed(reg); reg 387 drivers/gpio/gpio-omap.c writel_relaxed(ctrl, reg); reg 395 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base + bank->regs->ctrl; reg 398 drivers/gpio/gpio-omap.c ctrl = readl_relaxed(reg); reg 401 drivers/gpio/gpio-omap.c writel_relaxed(ctrl, reg); reg 408 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base + bank->regs->direction; reg 410 drivers/gpio/gpio-omap.c return readl_relaxed(reg) & BIT(offset); reg 469 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base; reg 471 drivers/gpio/gpio-omap.c reg += bank->regs->irqstatus; reg 472 drivers/gpio/gpio-omap.c writel_relaxed(gpio_mask, reg); reg 476 drivers/gpio/gpio-omap.c reg = bank->base + bank->regs->irqstatus2; reg 477 drivers/gpio/gpio-omap.c writel_relaxed(gpio_mask, reg); reg 481 drivers/gpio/gpio-omap.c readl_relaxed(reg); reg 492 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base; reg 496 drivers/gpio/gpio-omap.c reg += bank->regs->irqenable; reg 497 drivers/gpio/gpio-omap.c l = readl_relaxed(reg); reg 507 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base; reg 512 drivers/gpio/gpio-omap.c reg += bank->regs->set_irqenable; reg 515 drivers/gpio/gpio-omap.c reg += bank->regs->clr_irqenable; reg 518 drivers/gpio/gpio-omap.c writel_relaxed(gpio_mask, reg); reg 521 drivers/gpio/gpio-omap.c omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask, reg 827 drivers/gpio/gpio-omap.c void __iomem *reg; reg 830 drivers/gpio/gpio-omap.c reg = bank->base + bank->regs->datain; reg 832 drivers/gpio/gpio-omap.c reg = bank->base + bank->regs->dataout; reg 834 drivers/gpio/gpio-omap.c return (readl_relaxed(reg) & BIT(offset)) != 0; reg 920 drivers/gpio/gpio-omap.c void __iomem *reg = bank->base + bank->regs->dataout; reg 925 drivers/gpio/gpio-omap.c l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask); reg 926 drivers/gpio/gpio-omap.c writel_relaxed(l, reg); reg 33 drivers/gpio/gpio-palmas.c unsigned int reg; reg 37 drivers/gpio/gpio-palmas.c reg = (gpio16) ? PALMAS_GPIO_DATA_DIR2 : PALMAS_GPIO_DATA_DIR; reg 39 drivers/gpio/gpio-palmas.c ret = palmas_read(palmas, PALMAS_GPIO_BASE, reg, &val); reg 41 drivers/gpio/gpio-palmas.c dev_err(gc->parent, "Reg 0x%02x read failed, %d\n", reg, ret); reg 46 drivers/gpio/gpio-palmas.c reg = (gpio16) ? PALMAS_GPIO_DATA_OUT2 : PALMAS_GPIO_DATA_OUT; reg 48 drivers/gpio/gpio-palmas.c reg = (gpio16) ? PALMAS_GPIO_DATA_IN2 : PALMAS_GPIO_DATA_IN; reg 50 drivers/gpio/gpio-palmas.c ret = palmas_read(palmas, PALMAS_GPIO_BASE, reg, &val); reg 52 drivers/gpio/gpio-palmas.c dev_err(gc->parent, "Reg 0x%02x read failed, %d\n", reg, ret); reg 64 drivers/gpio/gpio-palmas.c unsigned int reg; reg 69 drivers/gpio/gpio-palmas.c reg = (value) ? reg 72 drivers/gpio/gpio-palmas.c reg = (value) ? reg 75 drivers/gpio/gpio-palmas.c ret = palmas_write(palmas, PALMAS_GPIO_BASE, reg, BIT(offset)); reg 77 drivers/gpio/gpio-palmas.c dev_err(gc->parent, "Reg 0x%02x write failed, %d\n", reg, ret); reg 86 drivers/gpio/gpio-palmas.c unsigned int reg; reg 90 drivers/gpio/gpio-palmas.c reg = (gpio16) ? PALMAS_GPIO_DATA_DIR2 : PALMAS_GPIO_DATA_DIR; reg 95 drivers/gpio/gpio-palmas.c ret = palmas_update_bits(palmas, PALMAS_GPIO_BASE, reg, reg 98 drivers/gpio/gpio-palmas.c dev_err(gc->parent, "Reg 0x%02x update failed, %d\n", reg, reg 108 drivers/gpio/gpio-palmas.c unsigned int reg; reg 112 drivers/gpio/gpio-palmas.c reg = (gpio16) ? PALMAS_GPIO_DATA_DIR2 : PALMAS_GPIO_DATA_DIR; reg 114 drivers/gpio/gpio-palmas.c ret = palmas_update_bits(palmas, PALMAS_GPIO_BASE, reg, BIT(offset), 0); reg 116 drivers/gpio/gpio-palmas.c dev_err(gc->parent, "Reg 0x%02x update failed, %d\n", reg, reg 216 drivers/gpio/gpio-pca953x.c static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, reg 220 drivers/gpio/gpio-pca953x.c int bank = (reg & REG_ADDR_MASK) >> bank_shift; reg 221 drivers/gpio/gpio-pca953x.c int offset = reg & (BIT(bank_shift) - 1); reg 224 drivers/gpio/gpio-pca953x.c if (reg & REG_ADDR_EXT) { reg 241 drivers/gpio/gpio-pca953x.c static bool pca953x_readable_register(struct device *dev, unsigned int reg) reg 261 drivers/gpio/gpio-pca953x.c return pca953x_check_register(chip, reg, bank); reg 264 drivers/gpio/gpio-pca953x.c static bool pca953x_writeable_register(struct device *dev, unsigned int reg) reg 281 drivers/gpio/gpio-pca953x.c return pca953x_check_register(chip, reg, bank); reg 284 drivers/gpio/gpio-pca953x.c static bool pca953x_volatile_register(struct device *dev, unsigned int reg) reg 297 drivers/gpio/gpio-pca953x.c return pca953x_check_register(chip, reg, bank); reg 313 drivers/gpio/gpio-pca953x.c static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off, reg 317 drivers/gpio/gpio-pca953x.c int addr = (reg & PCAL_GPIO_MASK) << bank_shift; reg 318 drivers/gpio/gpio-pca953x.c int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; reg 336 drivers/gpio/gpio-pca953x.c static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) reg 338 drivers/gpio/gpio-pca953x.c u8 regaddr = pca953x_recalc_addr(chip, reg, 0, true, true); reg 350 drivers/gpio/gpio-pca953x.c static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val) reg 352 drivers/gpio/gpio-pca953x.c u8 regaddr = pca953x_recalc_addr(chip, reg, 0, false, true); reg 899 drivers/gpio/gpio-pca953x.c struct regulator *reg; reg 933 drivers/gpio/gpio-pca953x.c reg = devm_regulator_get(&client->dev, "vcc"); reg 934 drivers/gpio/gpio-pca953x.c if (IS_ERR(reg)) { reg 935 drivers/gpio/gpio-pca953x.c ret = PTR_ERR(reg); reg 940 drivers/gpio/gpio-pca953x.c ret = regulator_enable(reg); reg 945 drivers/gpio/gpio-pca953x.c chip->regulator = reg; reg 88 drivers/gpio/gpio-pch.c struct pch_regs __iomem *reg; reg 104 drivers/gpio/gpio-pch.c reg_val = ioread32(&chip->reg->po); reg 110 drivers/gpio/gpio-pch.c iowrite32(reg_val, &chip->reg->po); reg 118 drivers/gpio/gpio-pch.c return (ioread32(&chip->reg->pi) >> nr) & 1; reg 131 drivers/gpio/gpio-pch.c reg_val = ioread32(&chip->reg->po); reg 136 drivers/gpio/gpio-pch.c iowrite32(reg_val, &chip->reg->po); reg 138 drivers/gpio/gpio-pch.c pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1); reg 140 drivers/gpio/gpio-pch.c iowrite32(pm, &chip->reg->pm); reg 154 drivers/gpio/gpio-pch.c pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1); reg 156 drivers/gpio/gpio-pch.c iowrite32(pm, &chip->reg->pm); reg 167 drivers/gpio/gpio-pch.c chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien); reg 168 drivers/gpio/gpio-pch.c chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask); reg 169 drivers/gpio/gpio-pch.c chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po); reg 170 drivers/gpio/gpio-pch.c chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm); reg 171 drivers/gpio/gpio-pch.c chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0); reg 173 drivers/gpio/gpio-pch.c chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1); reg 175 drivers/gpio/gpio-pch.c chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel); reg 183 drivers/gpio/gpio-pch.c iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien); reg 184 drivers/gpio/gpio-pch.c iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask); reg 186 drivers/gpio/gpio-pch.c iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po); reg 188 drivers/gpio/gpio-pch.c iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm); reg 189 drivers/gpio/gpio-pch.c iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0); reg 191 drivers/gpio/gpio-pch.c iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1); reg 193 drivers/gpio/gpio-pch.c iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel); reg 230 drivers/gpio/gpio-pch.c im_reg = &chip->reg->im0; reg 233 drivers/gpio/gpio-pch.c im_reg = &chip->reg->im1; reg 280 drivers/gpio/gpio-pch.c iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr); reg 288 drivers/gpio/gpio-pch.c iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask); reg 296 drivers/gpio/gpio-pch.c iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr); reg 302 drivers/gpio/gpio-pch.c unsigned long reg_val = ioread32(&chip->reg->istatus); reg 375 drivers/gpio/gpio-pch.c chip->reg = chip->base; reg 397 drivers/gpio/gpio-pch.c iowrite32(msk, &chip->reg->imask); reg 398 drivers/gpio/gpio-pch.c iowrite32(msk, &chip->reg->ien); reg 428 drivers/gpio/gpio-pch.c iowrite32(0x01, &chip->reg->reset); reg 429 drivers/gpio/gpio-pch.c iowrite32(0x00, &chip->reg->reset); reg 56 drivers/gpio/gpio-pci-idio-16.c struct idio_16_gpio_reg __iomem *reg; reg 88 drivers/gpio/gpio-pci-idio-16.c return !!(ioread8(&idio16gpio->reg->out0_7) & mask); reg 91 drivers/gpio/gpio-pci-idio-16.c return !!(ioread8(&idio16gpio->reg->out8_15) & (mask >> 8)); reg 94 drivers/gpio/gpio-pci-idio-16.c return !!(ioread8(&idio16gpio->reg->in0_7) & (mask >> 16)); reg 96 drivers/gpio/gpio-pci-idio-16.c return !!(ioread8(&idio16gpio->reg->in8_15) & (mask >> 24)); reg 112 drivers/gpio/gpio-pci-idio-16.c &idio16gpio->reg->out0_7, &idio16gpio->reg->out8_15, reg 113 drivers/gpio/gpio-pci-idio-16.c &idio16gpio->reg->in0_7, &idio16gpio->reg->in8_15, reg 161 drivers/gpio/gpio-pci-idio-16.c base = &idio16gpio->reg->out8_15; reg 163 drivers/gpio/gpio-pci-idio-16.c base = &idio16gpio->reg->out0_7; reg 188 drivers/gpio/gpio-pci-idio-16.c out_state = ioread8(&idio16gpio->reg->out0_7) & ~*mask; reg 190 drivers/gpio/gpio-pci-idio-16.c iowrite8(out_state, &idio16gpio->reg->out0_7); reg 199 drivers/gpio/gpio-pci-idio-16.c out_state = ioread8(&idio16gpio->reg->out8_15) & ~*mask; reg 201 drivers/gpio/gpio-pci-idio-16.c iowrite8(out_state, &idio16gpio->reg->out8_15); reg 223 drivers/gpio/gpio-pci-idio-16.c iowrite8(0, &idio16gpio->reg->irq_ctl); reg 242 drivers/gpio/gpio-pci-idio-16.c ioread8(&idio16gpio->reg->irq_ctl); reg 275 drivers/gpio/gpio-pci-idio-16.c irq_status = ioread8(&idio16gpio->reg->irq_status); reg 289 drivers/gpio/gpio-pci-idio-16.c iowrite8(0, &idio16gpio->reg->in0_7); reg 328 drivers/gpio/gpio-pci-idio-16.c idio16gpio->reg = pcim_iomap_table(pdev)[pci_bar_index]; reg 331 drivers/gpio/gpio-pci-idio-16.c iowrite8(0, &idio16gpio->reg->filter_ctl); reg 356 drivers/gpio/gpio-pci-idio-16.c iowrite8(0, &idio16gpio->reg->irq_ctl); reg 357 drivers/gpio/gpio-pci-idio-16.c iowrite8(0, &idio16gpio->reg->in0_7); reg 95 drivers/gpio/gpio-pcie-idio-24.c struct idio_24_gpio_reg __iomem *reg; reg 115 drivers/gpio/gpio-pcie-idio-24.c return !(ioread8(&idio24gpio->reg->ctl) & out_mode_mask); reg 131 drivers/gpio/gpio-pcie-idio-24.c ctl_state = ioread8(&idio24gpio->reg->ctl) & ~out_mode_mask; reg 132 drivers/gpio/gpio-pcie-idio-24.c iowrite8(ctl_state, &idio24gpio->reg->ctl); reg 153 drivers/gpio/gpio-pcie-idio-24.c ctl_state = ioread8(&idio24gpio->reg->ctl) | out_mode_mask; reg 154 drivers/gpio/gpio-pcie-idio-24.c iowrite8(ctl_state, &idio24gpio->reg->ctl); reg 171 drivers/gpio/gpio-pcie-idio-24.c return !!(ioread8(&idio24gpio->reg->out0_7) & offset_mask); reg 174 drivers/gpio/gpio-pcie-idio-24.c return !!(ioread8(&idio24gpio->reg->out8_15) & offset_mask); reg 177 drivers/gpio/gpio-pcie-idio-24.c return !!(ioread8(&idio24gpio->reg->out16_23) & offset_mask); reg 181 drivers/gpio/gpio-pcie-idio-24.c return !!(ioread8(&idio24gpio->reg->in0_7) & offset_mask); reg 184 drivers/gpio/gpio-pcie-idio-24.c return !!(ioread8(&idio24gpio->reg->in8_15) & offset_mask); reg 187 drivers/gpio/gpio-pcie-idio-24.c return !!(ioread8(&idio24gpio->reg->in16_23) & offset_mask); reg 190 drivers/gpio/gpio-pcie-idio-24.c if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask) reg 191 drivers/gpio/gpio-pcie-idio-24.c return !!(ioread8(&idio24gpio->reg->ttl_out0_7) & offset_mask); reg 194 drivers/gpio/gpio-pcie-idio-24.c return !!(ioread8(&idio24gpio->reg->ttl_in0_7) & offset_mask); reg 210 drivers/gpio/gpio-pcie-idio-24.c &idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15, reg 211 drivers/gpio/gpio-pcie-idio-24.c &idio24gpio->reg->out16_23, &idio24gpio->reg->in0_7, reg 212 drivers/gpio/gpio-pcie-idio-24.c &idio24gpio->reg->in8_15, &idio24gpio->reg->in16_23, reg 240 drivers/gpio/gpio-pcie-idio-24.c else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask) reg 241 drivers/gpio/gpio-pcie-idio-24.c port_state = ioread8(&idio24gpio->reg->ttl_out0_7); reg 243 drivers/gpio/gpio-pcie-idio-24.c port_state = ioread8(&idio24gpio->reg->ttl_in0_7); reg 267 drivers/gpio/gpio-pcie-idio-24.c if (offset > 47 && !(ioread8(&idio24gpio->reg->ctl) & out_mode_mask)) reg 272 drivers/gpio/gpio-pcie-idio-24.c base = &idio24gpio->reg->ttl_out0_7; reg 275 drivers/gpio/gpio-pcie-idio-24.c base = &idio24gpio->reg->out16_23; reg 277 drivers/gpio/gpio-pcie-idio-24.c base = &idio24gpio->reg->out8_15; reg 279 drivers/gpio/gpio-pcie-idio-24.c base = &idio24gpio->reg->out0_7; reg 305 drivers/gpio/gpio-pcie-idio-24.c &idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15, reg 306 drivers/gpio/gpio-pcie-idio-24.c &idio24gpio->reg->out16_23 reg 338 drivers/gpio/gpio-pcie-idio-24.c if (!ttl_mask || !(ioread8(&idio24gpio->reg->ctl) & out_mode_mask)) reg 345 drivers/gpio/gpio-pcie-idio-24.c out_state = ioread8(&idio24gpio->reg->ttl_out0_7) & ~ttl_mask; reg 347 drivers/gpio/gpio-pcie-idio-24.c iowrite8(out_state, &idio24gpio->reg->ttl_out0_7); reg 372 drivers/gpio/gpio-pcie-idio-24.c cos_enable_state = ioread8(&idio24gpio->reg->cos_enable); reg 379 drivers/gpio/gpio-pcie-idio-24.c iowrite8(cos_enable_state, &idio24gpio->reg->cos_enable); reg 401 drivers/gpio/gpio-pcie-idio-24.c cos_enable_state = ioread8(&idio24gpio->reg->cos_enable); reg 408 drivers/gpio/gpio-pcie-idio-24.c iowrite8(cos_enable_state, &idio24gpio->reg->cos_enable); reg 443 drivers/gpio/gpio-pcie-idio-24.c irq_status = ioread32(&idio24gpio->reg->cos0_7); reg 461 drivers/gpio/gpio-pcie-idio-24.c iowrite32(irq_status, &idio24gpio->reg->cos0_7); reg 503 drivers/gpio/gpio-pcie-idio-24.c idio24gpio->reg = pcim_iomap_table(pdev)[pci_bar_index]; reg 522 drivers/gpio/gpio-pcie-idio-24.c iowrite8(0, &idio24gpio->reg->soft_reset); reg 62 drivers/gpio/gpio-pmic-eic-sprd.c u8 reg[CACHE_NR_REGS]; reg 68 drivers/gpio/gpio-pmic-eic-sprd.c u16 reg, unsigned int val) reg 73 drivers/gpio/gpio-pmic-eic-sprd.c regmap_update_bits(pmic_eic->map, pmic_eic->offset + reg, reg 78 drivers/gpio/gpio-pmic-eic-sprd.c u16 reg) reg 84 drivers/gpio/gpio-pmic-eic-sprd.c ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value); reg 125 drivers/gpio/gpio-pmic-eic-sprd.c u32 reg, value; reg 128 drivers/gpio/gpio-pmic-eic-sprd.c reg = SPRD_PMIC_EIC_CTRL0 + SPRD_PMIC_EIC_BIT(offset) * 0x4; reg 129 drivers/gpio/gpio-pmic-eic-sprd.c ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value); reg 135 drivers/gpio/gpio-pmic-eic-sprd.c return regmap_write(pmic_eic->map, pmic_eic->offset + reg, value); reg 155 drivers/gpio/gpio-pmic-eic-sprd.c pmic_eic->reg[REG_IE] = 0; reg 156 drivers/gpio/gpio-pmic-eic-sprd.c pmic_eic->reg[REG_TRIG] = 0; reg 164 drivers/gpio/gpio-pmic-eic-sprd.c pmic_eic->reg[REG_IE] = 1; reg 165 drivers/gpio/gpio-pmic-eic-sprd.c pmic_eic->reg[REG_TRIG] = 1; reg 176 drivers/gpio/gpio-pmic-eic-sprd.c pmic_eic->reg[REG_IEV] = 1; reg 179 drivers/gpio/gpio-pmic-eic-sprd.c pmic_eic->reg[REG_IEV] = 0; reg 221 drivers/gpio/gpio-pmic-eic-sprd.c pmic_eic->reg[REG_IEV]); reg 226 drivers/gpio/gpio-pmic-eic-sprd.c pmic_eic->reg[REG_IE]); reg 229 drivers/gpio/gpio-pmic-eic-sprd.c pmic_eic->reg[REG_TRIG]); reg 34 drivers/gpio/gpio-rdc321x.c int reg; reg 37 drivers/gpio/gpio-rdc321x.c reg = gpio < 32 ? gpch->reg1_data_base : gpch->reg2_data_base; reg 40 drivers/gpio/gpio-rdc321x.c pci_write_config_dword(gpch->sb_pdev, reg, reg 42 drivers/gpio/gpio-rdc321x.c pci_read_config_dword(gpch->sb_pdev, reg, &value); reg 52 drivers/gpio/gpio-rdc321x.c int reg = (gpio < 32) ? 0 : 1; reg 57 drivers/gpio/gpio-rdc321x.c gpch->data_reg[reg] |= 1 << (gpio & 0x1f); reg 59 drivers/gpio/gpio-rdc321x.c gpch->data_reg[reg] &= ~(1 << (gpio & 0x1f)); reg 62 drivers/gpio/gpio-rdc321x.c reg ? gpch->reg2_data_base : gpch->reg1_data_base, reg 63 drivers/gpio/gpio-rdc321x.c gpch->data_reg[reg]); reg 83 drivers/gpio/gpio-rdc321x.c u32 reg; reg 89 drivers/gpio/gpio-rdc321x.c gpch->reg1_ctrl_base : gpch->reg2_ctrl_base, ®); reg 93 drivers/gpio/gpio-rdc321x.c reg |= 1 << (gpio & 0x1f); reg 96 drivers/gpio/gpio-rdc321x.c gpch->reg1_ctrl_base : gpch->reg2_ctrl_base, reg); reg 18 drivers/gpio/gpio-reg.c void __iomem *reg; reg 64 drivers/gpio/gpio-reg.c writel_relaxed(val, r->reg); reg 78 drivers/gpio/gpio-reg.c readl_relaxed(r->reg); reg 79 drivers/gpio/gpio-reg.c val = readl_relaxed(r->reg); reg 94 drivers/gpio/gpio-reg.c writel_relaxed(r->out, r->reg); reg 130 drivers/gpio/gpio-reg.c struct gpio_chip *gpio_reg_init(struct device *dev, void __iomem *reg, reg 161 drivers/gpio/gpio-reg.c r->reg = reg; reg 178 drivers/gpio/gpio-reg.c writel_relaxed(r->out, r->reg); reg 47 drivers/gpio/gpio-sa1100.c int reg = value ? R_GPSR : R_GPCR; reg 49 drivers/gpio/gpio-sa1100.c writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg); reg 82 drivers/gpio/gpio-sama5d2-piobu.c int reg; reg 86 drivers/gpio/gpio-sama5d2-piobu.c reg = PIOBU_BASE + pin * PIOBU_REG_SIZE; reg 88 drivers/gpio/gpio-sama5d2-piobu.c return regmap_update_bits(piobu->regmap, reg, mask, value); reg 100 drivers/gpio/gpio-sama5d2-piobu.c unsigned int val, reg; reg 103 drivers/gpio/gpio-sama5d2-piobu.c reg = PIOBU_BASE + pin * PIOBU_REG_SIZE; reg 104 drivers/gpio/gpio-sama5d2-piobu.c ret = regmap_read(piobu->regmap, reg, &val); reg 30 drivers/gpio/gpio-sch.c unsigned reg) reg 39 drivers/gpio/gpio-sch.c return base + reg + gpio / 8; reg 49 drivers/gpio/gpio-sch.c static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned gpio, unsigned reg) reg 54 drivers/gpio/gpio-sch.c offset = sch_gpio_offset(sch, gpio, reg); reg 62 drivers/gpio/gpio-sch.c static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned gpio, unsigned reg, reg 68 drivers/gpio/gpio-sch.c offset = sch_gpio_offset(sch, gpio, reg); reg 115 drivers/gpio/gpio-sch311x.c static inline int sch311x_sio_inb(int sio_config_port, int reg) reg 117 drivers/gpio/gpio-sch311x.c outb(reg, sio_config_port); reg 121 drivers/gpio/gpio-sch311x.c static inline void sch311x_sio_outb(int sio_config_port, int reg, int val) reg 123 drivers/gpio/gpio-sch311x.c outb(reg, sio_config_port); reg 350 drivers/gpio/gpio-sch311x.c int err = 0, reg; reg 359 drivers/gpio/gpio-sch311x.c reg = sch311x_sio_inb(sio_config_port, 0x20); reg 360 drivers/gpio/gpio-sch311x.c switch (reg) { reg 50 drivers/gpio/gpio-sodaville.c u32 reg; reg 57 drivers/gpio/gpio-sodaville.c reg = readl(type_reg); reg 61 drivers/gpio/gpio-sodaville.c reg &= ~BIT(4 * (d->hwirq % 8)); reg 65 drivers/gpio/gpio-sodaville.c reg |= BIT(4 * (d->hwirq % 8)); reg 72 drivers/gpio/gpio-sodaville.c writel(reg, type_reg); reg 49 drivers/gpio/gpio-sprd.c u16 reg, int val) reg 58 drivers/gpio/gpio-sprd.c tmp = readl_relaxed(base + reg); reg 65 drivers/gpio/gpio-sprd.c writel_relaxed(tmp, base + reg); reg 69 drivers/gpio/gpio-sprd.c static int sprd_gpio_read(struct gpio_chip *chip, unsigned int offset, u16 reg) reg 75 drivers/gpio/gpio-sprd.c return !!(readl_relaxed(base + reg) & BIT(SPRD_GPIO_BIT(offset))); reg 195 drivers/gpio/gpio-sprd.c unsigned long reg = readl_relaxed(base + SPRD_GPIO_MIS) & reg 198 drivers/gpio/gpio-sprd.c for_each_set_bit(n, ®, SPRD_GPIO_BANK_NR) { reg 45 drivers/gpio/gpio-stmpe.c u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)]; reg 49 drivers/gpio/gpio-stmpe.c ret = stmpe_reg_read(stmpe, reg); reg 61 drivers/gpio/gpio-stmpe.c u8 reg = stmpe->regs[which + (offset / 8)]; reg 69 drivers/gpio/gpio-stmpe.c stmpe_set_bits(stmpe, reg, mask, val ? mask : 0); reg 71 drivers/gpio/gpio-stmpe.c stmpe_reg_write(stmpe, reg, mask); reg 79 drivers/gpio/gpio-stmpe.c u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); reg 83 drivers/gpio/gpio-stmpe.c ret = stmpe_reg_read(stmpe, reg); reg 95 drivers/gpio/gpio-stmpe.c u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; reg 100 drivers/gpio/gpio-stmpe.c return stmpe_set_bits(stmpe, reg, mask, mask); reg 108 drivers/gpio/gpio-stmpe.c u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; reg 111 drivers/gpio/gpio-stmpe.c return stmpe_set_bits(stmpe, reg, mask, 0); reg 69 drivers/gpio/gpio-stp-xway.c #define xway_stp_r32(m, reg) __raw_readl(m + reg) reg 70 drivers/gpio/gpio-stp-xway.c #define xway_stp_w32(m, val, reg) __raw_writel(val, m + reg) reg 71 drivers/gpio/gpio-stp-xway.c #define xway_stp_w32_mask(m, clear, set, reg) \ reg 72 drivers/gpio/gpio-stp-xway.c xway_stp_w32(m, (xway_stp_r32(m, reg) & ~(clear)) | (set), reg) reg 41 drivers/gpio/gpio-tc3589x.c u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2; reg 45 drivers/gpio/gpio-tc3589x.c ret = tc3589x_reg_read(tc3589x, reg); reg 56 drivers/gpio/gpio-tc3589x.c u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2; reg 60 drivers/gpio/gpio-tc3589x.c tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data); reg 68 drivers/gpio/gpio-tc3589x.c u8 reg = TC3589x_GPIODIR0 + offset / 8; reg 73 drivers/gpio/gpio-tc3589x.c return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos)); reg 81 drivers/gpio/gpio-tc3589x.c u8 reg = TC3589x_GPIODIR0 + offset / 8; reg 84 drivers/gpio/gpio-tc3589x.c return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0); reg 92 drivers/gpio/gpio-tc3589x.c u8 reg = TC3589x_GPIODIR0 + offset / 8; reg 96 drivers/gpio/gpio-tc3589x.c ret = tc3589x_reg_read(tc3589x, reg); reg 97 drivers/gpio/gpio-tegra.c u32 val, u32 reg) reg 99 drivers/gpio/gpio-tegra.c __raw_writel(val, tgi->regs + reg); reg 102 drivers/gpio/gpio-tegra.c static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg) reg 104 drivers/gpio/gpio-tegra.c return __raw_readl(tgi->regs + reg); reg 113 drivers/gpio/gpio-tegra.c static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg, reg 121 drivers/gpio/gpio-tegra.c tegra_gpio_writel(tgi, val, reg); reg 127 drivers/gpio/gpio-thunderx.c void __iomem *reg = txgpio->register_base + reg 130 drivers/gpio/gpio-thunderx.c writeq(BIT_ULL(bank_bit), reg); reg 187 drivers/gpio/gpio-thunderx.c void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET; reg 197 drivers/gpio/gpio-thunderx.c orig_dat = ((readq(reg) >> bank_bit) & 1) ^ orig_invert; reg 46 drivers/gpio/gpio-timberdale.c u32 reg; reg 49 drivers/gpio/gpio-timberdale.c reg = ioread32(tgpio->membase + offset); reg 52 drivers/gpio/gpio-timberdale.c reg |= (1 << index); reg 54 drivers/gpio/gpio-timberdale.c reg &= ~(1 << index); reg 56 drivers/gpio/gpio-timberdale.c iowrite32(reg, tgpio->membase + offset); reg 33 drivers/gpio/gpio-tps68470.c unsigned int reg = TPS68470_REG_GPDO; reg 38 drivers/gpio/gpio-tps68470.c reg = TPS68470_REG_SGPO; reg 41 drivers/gpio/gpio-tps68470.c ret = regmap_read(regmap, reg, &val); reg 78 drivers/gpio/gpio-tps68470.c unsigned int reg = TPS68470_REG_GPDO; reg 81 drivers/gpio/gpio-tps68470.c reg = TPS68470_REG_SGPO; reg 85 drivers/gpio/gpio-tps68470.c regmap_update_bits(regmap, reg, BIT(offset), value ? BIT(offset) : 0); reg 44 drivers/gpio/gpio-tqmx86.c static u8 tqmx86_gpio_read(struct tqmx86_gpio_data *gd, unsigned int reg) reg 46 drivers/gpio/gpio-tqmx86.c return ioread8(gd->io_base + reg); reg 50 drivers/gpio/gpio-tqmx86.c unsigned int reg) reg 52 drivers/gpio/gpio-tqmx86.c iowrite8(val, gd->io_base + reg); reg 43 drivers/gpio/gpio-ts4900.c unsigned int reg; reg 45 drivers/gpio/gpio-ts4900.c regmap_read(priv->regmap, offset, ®); reg 47 drivers/gpio/gpio-ts4900.c return !(reg & TS4900_GPIO_OE); reg 80 drivers/gpio/gpio-ts4900.c unsigned int reg; reg 82 drivers/gpio/gpio-ts4900.c regmap_read(priv->regmap, offset, ®); reg 84 drivers/gpio/gpio-ts4900.c return !!(reg & priv->input_bit); reg 141 drivers/gpio/gpio-twl4030.c u8 reg = 0; reg 148 drivers/gpio/gpio-twl4030.c reg = ret & ~d_msk; reg 150 drivers/gpio/gpio-twl4030.c reg = ret | d_msk; reg 152 drivers/gpio/gpio-twl4030.c ret = gpio_twl4030_write(base, reg); reg 216 drivers/gpio/gpio-twl4030.c u8 reg = TWL4030_PWMAON_REG; reg 221 drivers/gpio/gpio-twl4030.c reg = TWL4030_PWMBON_REG; reg 226 drivers/gpio/gpio-twl4030.c status = twl_i2c_write_u8(TWL4030_MODULE_LED, 0x7f, reg + 1); reg 231 drivers/gpio/gpio-twl4030.c status = twl_i2c_write_u8(TWL4030_MODULE_LED, 0x7f, reg); reg 41 drivers/gpio/gpio-uniphier.c unsigned int reg; reg 43 drivers/gpio/gpio-uniphier.c reg = (bank + 1) * 8; reg 49 drivers/gpio/gpio-uniphier.c if (reg >= UNIPHIER_GPIO_IRQ_EN) reg 50 drivers/gpio/gpio-uniphier.c reg += 0x10; reg 52 drivers/gpio/gpio-uniphier.c return reg; reg 63 drivers/gpio/gpio-uniphier.c unsigned int reg, u32 mask, u32 val) reg 69 drivers/gpio/gpio-uniphier.c tmp = readl(priv->regs + reg); reg 72 drivers/gpio/gpio-uniphier.c writel(tmp, priv->regs + reg); reg 77 drivers/gpio/gpio-uniphier.c unsigned int reg, u32 mask, u32 val) reg 84 drivers/gpio/gpio-uniphier.c uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg, reg 89 drivers/gpio/gpio-uniphier.c unsigned int offset, unsigned int reg, reg 97 drivers/gpio/gpio-uniphier.c uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0); reg 101 drivers/gpio/gpio-uniphier.c unsigned int offset, unsigned int reg) reg 108 drivers/gpio/gpio-uniphier.c reg_offset = uniphier_gpio_bank_to_reg(bank) + reg; reg 434 drivers/gpio/gpio-uniphier.c unsigned int reg; reg 438 drivers/gpio/gpio-uniphier.c reg = uniphier_gpio_bank_to_reg(i); reg 440 drivers/gpio/gpio-uniphier.c *val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DATA); reg 441 drivers/gpio/gpio-uniphier.c *val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DIR); reg 456 drivers/gpio/gpio-uniphier.c unsigned int reg; reg 460 drivers/gpio/gpio-uniphier.c reg = uniphier_gpio_bank_to_reg(i); reg 462 drivers/gpio/gpio-uniphier.c writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA); reg 463 drivers/gpio/gpio-uniphier.c writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR); reg 74 drivers/gpio/gpio-vf610.c static inline void vf610_gpio_writel(u32 val, void __iomem *reg) reg 76 drivers/gpio/gpio-vf610.c writel_relaxed(val, reg); reg 79 drivers/gpio/gpio-vf610.c static inline u32 vf610_gpio_readl(void __iomem *reg) reg 81 drivers/gpio/gpio-vf610.c return readl_relaxed(reg); reg 328 drivers/gpio/gpio-vr41xx.c u16 offset, mask, reg; reg 362 drivers/gpio/gpio-vr41xx.c reg = giu_read(offset); reg 364 drivers/gpio/gpio-vr41xx.c reg |= mask; reg 366 drivers/gpio/gpio-vr41xx.c reg &= ~mask; reg 367 drivers/gpio/gpio-vr41xx.c giu_write(offset, reg); reg 376 drivers/gpio/gpio-vr41xx.c u16 reg, mask; reg 382 drivers/gpio/gpio-vr41xx.c reg = giu_read(GIUPIODL); reg 385 drivers/gpio/gpio-vr41xx.c reg = giu_read(GIUPIODH); reg 388 drivers/gpio/gpio-vr41xx.c reg = giu_read(GIUPODATL); reg 391 drivers/gpio/gpio-vr41xx.c reg = giu_read(GIUPODATH); reg 395 drivers/gpio/gpio-vr41xx.c if (reg & mask) reg 404 drivers/gpio/gpio-vr41xx.c u16 offset, mask, reg; reg 426 drivers/gpio/gpio-vr41xx.c reg = giu_read(offset); reg 428 drivers/gpio/gpio-vr41xx.c reg |= mask; reg 430 drivers/gpio/gpio-vr41xx.c reg &= ~mask; reg 431 drivers/gpio/gpio-vr41xx.c giu_write(offset, reg); reg 102 drivers/gpio/gpio-wcove.c unsigned int reg; reg 108 drivers/gpio/gpio-wcove.c reg = GPIO_IN_CTRL_BASE + gpio; reg 110 drivers/gpio/gpio-wcove.c reg = GPIO_OUT_CTRL_BASE + gpio; reg 112 drivers/gpio/gpio-wcove.c return reg; reg 117 drivers/gpio/gpio-wcove.c unsigned int reg, mask; reg 120 drivers/gpio/gpio-wcove.c reg = IRQ_MASK_BASE; reg 123 drivers/gpio/gpio-wcove.c reg = IRQ_MASK_BASE + 1; reg 128 drivers/gpio/gpio-wcove.c regmap_update_bits(wg->regmap, reg, mask, mask); reg 130 drivers/gpio/gpio-wcove.c regmap_update_bits(wg->regmap, reg, mask, 0); reg 135 drivers/gpio/gpio-wcove.c int reg = to_reg(gpio, CTRL_IN); reg 137 drivers/gpio/gpio-wcove.c if (reg < 0) reg 140 drivers/gpio/gpio-wcove.c regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt); reg 146 drivers/gpio/gpio-wcove.c int reg = to_reg(gpio, CTRL_OUT); reg 148 drivers/gpio/gpio-wcove.c if (reg < 0) reg 151 drivers/gpio/gpio-wcove.c return regmap_write(wg->regmap, reg, CTLO_INPUT_SET); reg 158 drivers/gpio/gpio-wcove.c int reg = to_reg(gpio, CTRL_OUT); reg 160 drivers/gpio/gpio-wcove.c if (reg < 0) reg 163 drivers/gpio/gpio-wcove.c return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value); reg 170 drivers/gpio/gpio-wcove.c int ret, reg = to_reg(gpio, CTRL_OUT); reg 172 drivers/gpio/gpio-wcove.c if (reg < 0) reg 175 drivers/gpio/gpio-wcove.c ret = regmap_read(wg->regmap, reg, &val); reg 186 drivers/gpio/gpio-wcove.c int ret, reg = to_reg(gpio, CTRL_IN); reg 188 drivers/gpio/gpio-wcove.c if (reg < 0) reg 191 drivers/gpio/gpio-wcove.c ret = regmap_read(wg->regmap, reg, &val); reg 201 drivers/gpio/gpio-wcove.c int reg = to_reg(gpio, CTRL_OUT); reg 203 drivers/gpio/gpio-wcove.c if (reg < 0) reg 207 drivers/gpio/gpio-wcove.c regmap_update_bits(wg->regmap, reg, 1, 1); reg 209 drivers/gpio/gpio-wcove.c regmap_update_bits(wg->regmap, reg, 1, 0); reg 216 drivers/gpio/gpio-wcove.c int reg = to_reg(gpio, CTRL_OUT); reg 218 drivers/gpio/gpio-wcove.c if (reg < 0) reg 223 drivers/gpio/gpio-wcove.c return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK, reg 226 drivers/gpio/gpio-wcove.c return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK, reg 170 drivers/gpio/gpio-winbond.c static void winbond_sio_reg_write(unsigned long base, u8 reg, u8 data) reg 172 drivers/gpio/gpio-winbond.c outb(reg, base); reg 176 drivers/gpio/gpio-winbond.c static u8 winbond_sio_reg_read(unsigned long base, u8 reg) reg 178 drivers/gpio/gpio-winbond.c outb(reg, base); reg 182 drivers/gpio/gpio-winbond.c static void winbond_sio_reg_bset(unsigned long base, u8 reg, u8 bit) reg 186 drivers/gpio/gpio-winbond.c val = winbond_sio_reg_read(base, reg); reg 188 drivers/gpio/gpio-winbond.c winbond_sio_reg_write(base, reg, val); reg 191 drivers/gpio/gpio-winbond.c static void winbond_sio_reg_bclear(unsigned long base, u8 reg, u8 bit) reg 195 drivers/gpio/gpio-winbond.c val = winbond_sio_reg_read(base, reg); reg 197 drivers/gpio/gpio-winbond.c winbond_sio_reg_write(base, reg, val); reg 200 drivers/gpio/gpio-winbond.c static bool winbond_sio_reg_btest(unsigned long base, u8 reg, u8 bit) reg 202 drivers/gpio/gpio-winbond.c return winbond_sio_reg_read(base, reg) & BIT(bit); reg 103 drivers/gpio/gpio-wm831x.c int reg = WM831X_GPIO1_CONTROL + offset; reg 106 drivers/gpio/gpio-wm831x.c ret = wm831x_reg_read(wm831x, reg); reg 126 drivers/gpio/gpio-wm831x.c return wm831x_set_bits(wm831x, reg, WM831X_GPN_FN_MASK, fn); reg 134 drivers/gpio/gpio-wm831x.c int reg = WM831X_GPIO1_CONTROL + offset; reg 138 drivers/gpio/gpio-wm831x.c return wm831x_set_bits(wm831x, reg, reg 141 drivers/gpio/gpio-wm831x.c return wm831x_set_bits(wm831x, reg, reg 162 drivers/gpio/gpio-wm831x.c int reg; reg 176 drivers/gpio/gpio-wm831x.c reg = wm831x_reg_read(wm831x, WM831X_GPIO1_CONTROL + i); reg 177 drivers/gpio/gpio-wm831x.c if (reg < 0) { reg 180 drivers/gpio/gpio-wm831x.c gpio, reg); reg 185 drivers/gpio/gpio-wm831x.c switch (reg & WM831X_GPN_PULL_MASK) { reg 203 drivers/gpio/gpio-wm831x.c if (reg & WM831X_GPN_PWR_DOM) reg 211 drivers/gpio/gpio-wm831x.c if (reg & WM831X_GPN_PWR_DOM) reg 226 drivers/gpio/gpio-wm831x.c tristated = reg & WM831X_GPN_TRI; reg 232 drivers/gpio/gpio-wm831x.c reg & WM831X_GPN_DIR ? "in" : "out", reg 236 drivers/gpio/gpio-wm831x.c reg & WM831X_GPN_POL ? "" : " inverted", reg 237 drivers/gpio/gpio-wm831x.c reg & WM831X_GPN_OD ? "open-drain" : "push-pull", reg 239 drivers/gpio/gpio-wm831x.c reg); reg 195 drivers/gpio/gpio-wm8994.c int reg; reg 209 drivers/gpio/gpio-wm8994.c reg = wm8994_reg_read(wm8994, WM8994_GPIO_1 + i); reg 210 drivers/gpio/gpio-wm8994.c if (reg < 0) { reg 213 drivers/gpio/gpio-wm8994.c gpio, reg); reg 218 drivers/gpio/gpio-wm8994.c if (reg & WM8994_GPN_DIR) reg 223 drivers/gpio/gpio-wm8994.c if (reg & WM8994_GPN_PU) reg 226 drivers/gpio/gpio-wm8994.c if (reg & WM8994_GPN_PD) reg 229 drivers/gpio/gpio-wm8994.c if (reg & WM8994_GPN_POL) reg 234 drivers/gpio/gpio-wm8994.c if (reg & WM8994_GPN_OP_CFG) reg 240 drivers/gpio/gpio-wm8994.c wm8994_gpio_fn(reg & WM8994_GPN_FN_MASK), reg); reg 62 drivers/gpio/gpio-xgene-sb.c void __iomem *reg, u32 gpio, int val) reg 66 drivers/gpio/gpio-xgene-sb.c data = gc->read_reg(reg); reg 71 drivers/gpio/gpio-xgene-sb.c gc->write_reg(reg, data); reg 46 drivers/gpio/gpio-xra1403.c static unsigned int to_reg(unsigned int reg, unsigned int offset) reg 48 drivers/gpio/gpio-xra1403.c return reg + (offset > 7); reg 117 drivers/gpio/gpio-xra1403.c int reg; reg 125 drivers/gpio/gpio-xra1403.c for (reg = 0; reg <= XRA_LAST; reg++) reg 126 drivers/gpio/gpio-xra1403.c seq_printf(s, " %2.2x", reg); reg 128 drivers/gpio/gpio-xra1403.c for (reg = 0; reg < XRA_LAST; reg++) { reg 129 drivers/gpio/gpio-xra1403.c regmap_read(xra->regmap, reg, &value[reg]); reg 130 drivers/gpio/gpio-xra1403.c seq_printf(s, " %2.2x", value[reg]); reg 298 drivers/gpio/gpio-zynq.c u32 reg; reg 313 drivers/gpio/gpio-zynq.c reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); reg 314 drivers/gpio/gpio-zynq.c reg &= ~BIT(bank_pin_num); reg 315 drivers/gpio/gpio-zynq.c writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); reg 335 drivers/gpio/gpio-zynq.c u32 reg; reg 342 drivers/gpio/gpio-zynq.c reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); reg 343 drivers/gpio/gpio-zynq.c reg |= BIT(bank_pin_num); reg 344 drivers/gpio/gpio-zynq.c writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); reg 347 drivers/gpio/gpio-zynq.c reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); reg 348 drivers/gpio/gpio-zynq.c reg |= BIT(bank_pin_num); reg 349 drivers/gpio/gpio-zynq.c writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); reg 367 drivers/gpio/gpio-zynq.c u32 reg; reg 373 drivers/gpio/gpio-zynq.c reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); reg 375 drivers/gpio/gpio-zynq.c return !(reg & BIT(bank_pin_num)); reg 91 drivers/gpio/sgpio-aspeed.c const enum aspeed_sgpio_reg reg) reg 93 drivers/gpio/sgpio-aspeed.c switch (reg) { reg 131 drivers/gpio/sgpio-aspeed.c enum aspeed_sgpio_reg reg; reg 138 drivers/gpio/sgpio-aspeed.c reg = is_input ? reg_val : reg_rdata; reg 139 drivers/gpio/sgpio-aspeed.c rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset)); reg 151 drivers/gpio/sgpio-aspeed.c u32 reg = 0; reg 154 drivers/gpio/sgpio-aspeed.c reg = ioread32(addr); reg 157 drivers/gpio/sgpio-aspeed.c reg |= GPIO_BIT(offset); reg 159 drivers/gpio/sgpio-aspeed.c reg &= ~GPIO_BIT(offset); reg 161 drivers/gpio/sgpio-aspeed.c iowrite32(reg, addr); reg 258 drivers/gpio/sgpio-aspeed.c u32 reg, bit; reg 267 drivers/gpio/sgpio-aspeed.c reg = ioread32(addr); reg 269 drivers/gpio/sgpio-aspeed.c reg |= bit; reg 271 drivers/gpio/sgpio-aspeed.c reg &= ~bit; reg 273 drivers/gpio/sgpio-aspeed.c iowrite32(reg, addr); reg 293 drivers/gpio/sgpio-aspeed.c u32 bit, reg; reg 327 drivers/gpio/sgpio-aspeed.c reg = ioread32(addr); reg 328 drivers/gpio/sgpio-aspeed.c reg = (reg & ~bit) | type0; reg 329 drivers/gpio/sgpio-aspeed.c iowrite32(reg, addr); reg 332 drivers/gpio/sgpio-aspeed.c reg = ioread32(addr); reg 333 drivers/gpio/sgpio-aspeed.c reg = (reg & ~bit) | type1; reg 334 drivers/gpio/sgpio-aspeed.c iowrite32(reg, addr); reg 337 drivers/gpio/sgpio-aspeed.c reg = ioread32(addr); reg 338 drivers/gpio/sgpio-aspeed.c reg = (reg & ~bit) | type2; reg 339 drivers/gpio/sgpio-aspeed.c iowrite32(reg, addr); reg 354 drivers/gpio/sgpio-aspeed.c unsigned long reg; reg 361 drivers/gpio/sgpio-aspeed.c reg = ioread32(bank_reg(data, bank, reg_irq_status)); reg 363 drivers/gpio/sgpio-aspeed.c for_each_set_bit(p, ®, 32) { reg 1036 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, reg 1038 drivers/gpu/drm/amd/amdgpu/amdgpu.h void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, reg 1043 drivers/gpu/drm/amd/amdgpu/amdgpu.h u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); reg 1044 drivers/gpu/drm/amd/amdgpu/amdgpu.h void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); reg 1058 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) reg 1059 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) reg 1061 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) reg 1062 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) reg 1064 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) reg 1065 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) reg 1066 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) reg 1067 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) reg 1068 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) reg 1071 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) reg 1072 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) reg 1073 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) reg 1074 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) reg 1075 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) reg 1076 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) reg 1077 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) reg 1078 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) reg 1079 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) reg 1080 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) reg 1081 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) reg 1082 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) reg 1083 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) reg 1084 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) reg 1085 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) reg 1086 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) reg 1087 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) reg 1088 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) reg 1089 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_P(reg, val, mask) \ reg 1091 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t tmp_ = RREG32(reg); \ reg 1094 drivers/gpu/drm/amd/amdgpu/amdgpu.h WREG32(reg, tmp_); \ reg 1096 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) reg 1097 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) reg 1098 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_PLL_P(reg, val, mask) \ reg 1100 drivers/gpu/drm/amd/amdgpu/amdgpu.h uint32_t tmp_ = RREG32_PLL(reg); \ reg 1103 drivers/gpu/drm/amd/amdgpu/amdgpu.h WREG32_PLL(reg, tmp_); \ reg 1105 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) reg 1106 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) reg 1107 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) reg 1109 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT reg 1110 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK reg 1112 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define REG_SET_FIELD(orig_val, reg, field, field_val) \ reg 1113 drivers/gpu/drm/amd/amdgpu/amdgpu.h (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ reg 1114 drivers/gpu/drm/amd/amdgpu/amdgpu.h (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) reg 1116 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define REG_GET_FIELD(value, reg, field) \ reg 1117 drivers/gpu/drm/amd/amdgpu/amdgpu.h (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) reg 1119 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_FIELD(reg, field, val) \ reg 1120 drivers/gpu/drm/amd/amdgpu/amdgpu.h WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) reg 1122 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ reg 1123 drivers/gpu/drm/amd/amdgpu/amdgpu.h WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) reg 209 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c uint32_t i = 0, reg; reg 217 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) reg 218 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c DUMP_REG(sdma_base_addr + reg); reg 219 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++) reg 220 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c DUMP_REG(sdma_base_addr + reg); reg 221 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; reg 222 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++) reg 223 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c DUMP_REG(sdma_base_addr + reg); reg 224 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg 225 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++) reg 226 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c DUMP_REG(sdma_base_addr + reg); reg 365 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t reg, hqd_base, data; reg 391 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c for (reg = hqd_base; reg 392 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) reg 393 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c WREG32(reg, mqd_hqd[reg - hqd_base]); reg 459 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t i = 0, reg; reg 474 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); reg 475 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) reg 476 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c DUMP_REG(reg); reg 567 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t i = 0, reg; reg 578 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) reg 579 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c DUMP_REG(sdma_base_addr + reg); reg 580 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++) reg 581 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c DUMP_REG(sdma_base_addr + reg); reg 582 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; reg 583 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++) reg 584 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c DUMP_REG(sdma_base_addr + reg); reg 585 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg 586 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++) reg 587 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c DUMP_REG(sdma_base_addr + reg); reg 785 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t reg; reg 788 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) reg 790 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; reg 796 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t reg; reg 799 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) reg 801 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK; reg 336 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t reg, wptr_val, data; reg 346 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) reg 347 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); reg 379 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t i = 0, reg; reg 399 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) reg 400 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c DUMP_REG(reg); reg 481 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t i = 0, reg; reg 489 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) reg 490 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c DUMP_REG(sdma_offset + reg); reg 491 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK; reg 492 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c reg++) reg 493 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c DUMP_REG(sdma_offset + reg); reg 764 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t reg; reg 767 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); reg 768 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; reg 774 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t reg; reg 777 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); reg 778 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK; reg 292 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t reg, wptr_val, data; reg 317 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++) reg 318 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); reg 331 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c for (reg = mmCP_HQD_EOP_EVENTS; reg <= mmCP_HQD_ERROR; reg++) reg 332 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); reg 364 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t i = 0, reg; reg 384 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++) reg 385 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c DUMP_REG(reg); reg 465 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t i = 0, reg; reg 473 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) reg 474 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c DUMP_REG(sdma_offset + reg); reg 475 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK; reg 476 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c reg++) reg 477 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c DUMP_REG(sdma_offset + reg); reg 478 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c for (reg = mmSDMA0_RLC0_CSA_ADDR_LO; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg 479 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c reg++) reg 480 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c DUMP_REG(sdma_offset + reg); reg 481 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; reg <= mmSDMA0_RLC0_DUMMY_REG; reg 482 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c reg++) reg 483 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c DUMP_REG(sdma_offset + reg); reg 484 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg 485 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c reg++) reg 486 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c DUMP_REG(sdma_offset + reg); reg 677 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t reg; reg 680 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); reg 681 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; reg 687 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t reg; reg 690 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); reg 691 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK; reg 267 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t reg, hqd_base, data; reg 292 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c for (reg = hqd_base; reg 293 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) reg 294 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c WREG32_RLC(reg, mqd_hqd[reg - hqd_base]); reg 359 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t i = 0, reg; reg 374 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); reg 375 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) reg 376 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c DUMP_REG(reg); reg 466 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t i = 0, reg; reg 474 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) reg 475 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c DUMP_REG(sdma_base_addr + reg); reg 476 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++) reg 477 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c DUMP_REG(sdma_base_addr + reg); reg 478 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; reg 479 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++) reg 480 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c DUMP_REG(sdma_base_addr + reg); reg 481 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg 482 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++) reg 483 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c DUMP_REG(sdma_base_addr + reg); reg 623 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t reg; reg 626 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) reg 628 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; reg 634 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t reg; reg 637 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) reg 639 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK; reg 184 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex); reg 203 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c u32 reg; reg 207 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c reg = amdgpu_display_hpd_get_gpio_reg(adev); reg 210 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c if (gpio->reg == reg) { reg 1827 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) reg 1841 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) reg 1855 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) reg 1869 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) reg 1883 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) reg 1887 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c WREG32(reg, val); reg 1899 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) reg 1904 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c r = RREG32(reg); reg 1917 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) reg 1921 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c WREG32_IO(reg, val); reg 1933 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) reg 1938 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c r = RREG32_IO(reg); reg 166 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, reg 172 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c return amdgpu_virt_kiq_rreg(adev, reg); reg 174 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) reg 175 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); reg 180 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); reg 184 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); reg 240 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, reg 243 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); reg 245 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { reg 250 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c return amdgpu_virt_kiq_wreg(adev, reg, v); reg 252 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) reg 253 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); reg 258 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); reg 263 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { reg 276 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) reg 278 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c if ((reg * 4) < adev->rio_mem_size) reg 279 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c return ioread32(adev->rio_mem + (reg * 4)); reg 281 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); reg 295 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 297 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { reg 301 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c if ((reg * 4) < adev->rio_mem_size) reg 302 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c iowrite32(v, adev->rio_mem + (reg * 4)); reg 304 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); reg 308 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { reg 399 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) reg 401 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); reg 416 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) reg 419 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c reg, v); reg 433 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg) reg 435 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg); reg 450 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) reg 453 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c reg, v); reg 469 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c uint32_t block, uint32_t reg) reg 472 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c reg, block); reg 490 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c uint32_t reg, uint32_t v) reg 493 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c reg, block, v); reg 540 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c u32 tmp, reg, and_mask, or_mask; reg 547 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c reg = registers[i + 0]; reg 554 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c tmp = RREG32(reg); reg 561 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c WREG32(reg, tmp); reg 827 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c uint32_t reg; reg 862 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c reg = amdgpu_asic_get_config_memsize(adev); reg 864 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c if ((reg != 0) && (reg != 0xffffffff)) reg 107 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg) reg 115 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c *reg = adev->gfx.scratch.reg_base + i; reg 129 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg) reg 131 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base); reg 349 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg); reg 350 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg); reg 481 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h u32 reg; reg 371 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, reg 377 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c if (reg >= PSP_REG_LAST) reg 384 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c psp_prep_reg_prog_cmd_buf(cmd, reg, value); reg 286 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, reg 162 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg); reg 163 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); reg 164 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg, reg 39 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h TP_PROTO(unsigned did, uint32_t reg, uint32_t value), reg 40 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h TP_ARGS(did, reg, value), reg 43 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __field(uint32_t, reg) reg 48 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __entry->reg = reg; reg 53 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h (unsigned long)__entry->reg, reg 58 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h TP_PROTO(unsigned did, uint32_t reg, uint32_t value), reg 59 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h TP_ARGS(did, reg, value), reg 62 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __field(uint32_t, reg) reg 67 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h __entry->reg = reg; reg 72 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h (unsigned long)__entry->reg, reg 25 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h #define RREG64_UMC(reg) (RREG32(reg) | \ reg 26 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h ((uint64_t)RREG32((reg) + 1) << 32)) reg 27 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h #define WREG64_UMC(reg, v) \ reg 29 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h WREG32((reg), lower_32_bits(v)); \ reg 30 drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h WREG32((reg) + 1, upper_32_bits(v)); \ reg 89 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c unsigned reg, count; reg 898 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c unsigned reg = ctx->reg + i; reg 905 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c switch (reg) { reg 921 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c DRM_ERROR("Invalid reg 0x%X!\n", reg); reg 948 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c ctx->reg = CP_PACKET0_GET_REG(cmd); reg 59 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h #define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \ reg 63 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \ reg 69 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h #define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \ reg 75 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \ reg 80 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h #define SOC15_DPG_MODE_OFFSET_2_0(ip, inst, reg) \ reg 85 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ reg 48 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg) reg 60 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c amdgpu_ring_emit_rreg(ring, reg); reg 90 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c pr_err("failed to read reg:%x\n", reg); reg 94 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) reg 106 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c amdgpu_ring_emit_wreg(ring, reg, v); reg 137 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c pr_err("failed to write reg:%x\n", reg); reg 294 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); reg 295 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); reg 76 drivers/gpu/drm/amd/amdgpu/cik.c static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg) reg 82 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmPCIE_INDEX, reg); reg 89 drivers/gpu/drm/amd/amdgpu/cik.c static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 94 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmPCIE_INDEX, reg); reg 101 drivers/gpu/drm/amd/amdgpu/cik.c static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg) reg 107 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmSMC_IND_INDEX_0, (reg)); reg 113 drivers/gpu/drm/amd/amdgpu/cik.c static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 118 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmSMC_IND_INDEX_0, (reg)); reg 123 drivers/gpu/drm/amd/amdgpu/cik.c static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) reg 129 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); reg 135 drivers/gpu/drm/amd/amdgpu/cik.c static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 140 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); reg 145 drivers/gpu/drm/amd/amdgpu/cik.c static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg) reg 151 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmDIDT_IND_INDEX, (reg)); reg 157 drivers/gpu/drm/amd/amdgpu/cik.c static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 162 drivers/gpu/drm/amd/amdgpu/cik.c WREG32(mmDIDT_IND_INDEX, (reg)); reg 875 drivers/gpu/drm/amd/amdgpu/cik_sdma.c uint32_t reg, uint32_t val) reg 878 drivers/gpu/drm/amd/amdgpu/cik_sdma.c amdgpu_ring_write(ring, reg); reg 216 drivers/gpu/drm/amd/amdgpu/cikd.h #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ reg 217 drivers/gpu/drm/amd/amdgpu/cikd.h ((reg) & 0xFFFF) | \ reg 85 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c uint32_t reg; reg 91 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c .reg = mmDISP_INTERRUPT_STATUS, reg 96 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, reg 101 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, reg 106 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, reg 111 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, reg 116 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, reg 175 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c u32 block_offset, u32 reg) reg 181 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); reg 189 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c u32 block_offset, u32 reg, u32 v) reg 194 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); reg 3093 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c u32 reg; reg 3100 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); reg 3103 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); reg 3106 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); reg 3214 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); reg 3260 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c disp_int = RREG32(interrupt_status_offsets[hpd].reg); reg 87 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c uint32_t reg; reg 93 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c .reg = mmDISP_INTERRUPT_STATUS, reg 98 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, reg 103 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, reg 108 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, reg 113 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, reg 118 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, reg 193 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c u32 block_offset, u32 reg) reg 199 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); reg 207 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c u32 block_offset, u32 reg, u32 v) reg 212 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); reg 3219 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c u32 reg; reg 3226 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); reg 3229 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); reg 3232 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); reg 3340 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); reg 3387 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c disp_int = RREG32(interrupt_status_offsets[hpd].reg); reg 88 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t reg; reg 94 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c .reg = mmDISP_INTERRUPT_STATUS, reg 99 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, reg 104 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, reg 109 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, reg 114 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, reg 119 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, reg 126 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c u32 block_offset, u32 reg) reg 132 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); reg 140 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c u32 block_offset, u32 reg, u32 v) reg 146 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK); reg 2933 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); reg 2970 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c u32 reg; reg 2977 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); reg 2980 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); reg 2983 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); reg 3054 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c disp_int = RREG32(interrupt_status_offsets[hpd].reg); reg 85 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t reg; reg 91 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c .reg = mmDISP_INTERRUPT_STATUS, reg 96 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, reg 101 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, reg 106 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, reg 111 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, reg 116 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, reg 123 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c u32 block_offset, u32 reg) reg 129 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); reg 137 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c u32 block_offset, u32 reg, u32 v) reg 142 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); reg 3025 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); reg 3062 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c u32 reg; reg 3069 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); reg 3072 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); reg 3075 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); reg 3146 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c disp_int = RREG32(interrupt_status_offsets[hpd].reg); reg 401 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c bool wc, uint32_t reg, uint32_t val) reg 406 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(ring, reg); reg 4790 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) reg 4798 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(ring, reg); reg 4806 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, reg 4824 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(ring, reg); reg 4829 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, reg 4832 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); reg 2363 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c uint32_t reg, uint32_t val) reg 2370 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c amdgpu_ring_write(ring, reg); reg 3283 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c uint32_t reg, uint32_t val) reg 3290 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c amdgpu_ring_write(ring, reg); reg 6279 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c int pipe_num, tmp, reg; reg 6288 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c reg = mmSPI_WCL_PIPE_PERCENT_GFX + pipe_num; reg 6289 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c tmp = RREG32(reg); reg 6291 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(reg, tmp); reg 6485 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) reg 6493 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(ring, reg); reg 6501 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, reg 6520 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c amdgpu_ring_write(ring, reg); reg 806 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c bool wc, uint32_t reg, uint32_t val) reg 812 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(ring, reg); reg 5158 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c int pipe_num, tmp, reg; reg 5167 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num; reg 5168 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c tmp = RREG32(reg); reg 5170 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32(reg, tmp); reg 5405 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) reg 5413 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(ring, reg); reg 5421 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, reg 5439 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(ring, reg); reg 5444 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, reg 5447 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); reg 63 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i; reg 86 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c reg = hub->vm_context0_cntl + i; reg 87 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c tmp = RREG32(reg); reg 89 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c WREG32(reg, tmp); reg 95 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c reg = hub->vm_context0_cntl + i; reg 96 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c tmp = RREG32(reg); reg 98 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c WREG32(reg, tmp); reg 105 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c reg = hub->vm_context0_cntl + i; reg 106 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c tmp = RREG32(reg); reg 108 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c WREG32(reg, tmp); reg 114 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c reg = hub->vm_context0_cntl + i; reg 115 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c tmp = RREG32(reg); reg 117 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c WREG32(reg, tmp); reg 416 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c uint32_t reg; reg 419 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; reg 421 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; reg 423 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c amdgpu_ring_emit_wreg(ring, reg, pasid); reg 374 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c uint32_t reg; reg 378 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; reg 380 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8); reg 381 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); reg 446 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c uint32_t reg; reg 449 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; reg 451 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; reg 452 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); reg 648 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c uint32_t reg; reg 651 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; reg 653 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; reg 654 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); reg 206 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c u32 bits, i, tmp, reg; reg 213 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c reg = ecc_umc_mcumc_ctrl_addrs[i]; reg 214 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c tmp = RREG32(reg); reg 216 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c WREG32(reg, tmp); reg 219 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; reg 220 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c tmp = RREG32(reg); reg 222 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c WREG32(reg, tmp); reg 227 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c reg = ecc_umc_mcumc_ctrl_addrs[i]; reg 228 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c tmp = RREG32(reg); reg 230 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c WREG32(reg, tmp); reg 233 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; reg 234 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c tmp = RREG32(reg); reg 236 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c WREG32(reg, tmp); reg 290 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c u32 tmp, reg, bits, i, j; reg 305 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c reg = hub->vm_context0_cntl + i; reg 306 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c tmp = RREG32(reg); reg 308 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c WREG32(reg, tmp); reg 316 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c reg = hub->vm_context0_cntl + i; reg 317 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c tmp = RREG32(reg); reg 319 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c WREG32(reg, tmp); reg 614 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c uint32_t reg; reg 621 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; reg 623 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; reg 625 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c amdgpu_ring_emit_wreg(ring, reg, pasid); reg 120 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h #define MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \ reg 122 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h init_table, (reg), \ reg 128 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h #define MMSCH_V1_0_INSERT_DIRECT_WT(reg, value) { \ reg 130 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h init_table, (reg), \ reg 136 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h #define MMSCH_V1_0_INSERT_DIRECT_POLL(reg, mask, wait) { \ reg 138 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h init_table, (reg), \ reg 64 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c u32 reg; reg 66 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, reg 68 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c if (reg != event) reg 83 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c u8 reg; reg 86 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c reg = RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE); reg 87 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c if (reg & 2) reg 119 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c u32 reg; reg 138 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, reg 140 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0, reg 143 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c reg); reg 319 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c u32 reg; reg 323 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); reg 324 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1); reg 325 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); reg 328 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); reg 329 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c while (reg & mask) { reg 337 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); reg 343 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c u32 reg; reg 345 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); reg 346 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, reg 348 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); reg 354 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c u32 reg; reg 356 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0); reg 357 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c reg = REG_SET_FIELD(reg, MAILBOX_MSGBUF_TRN_DW0, reg 359 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, reg); reg 367 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c u32 reg; reg 372 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); reg 373 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c if (!(reg & mask)) reg 377 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); reg 378 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c if (reg != event) reg 391 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c u32 reg; reg 393 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); reg 394 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c while (!(reg & mask)) { reg 403 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); reg 213 drivers/gpu/drm/amd/amdgpu/navi10_ih.c u32 wptr, reg, tmp; reg 220 drivers/gpu/drm/amd/amdgpu/navi10_ih.c reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); reg 221 drivers/gpu/drm/amd/amdgpu/navi10_ih.c wptr = RREG32_NO_KIQ(reg); reg 236 drivers/gpu/drm/amd/amdgpu/navi10_ih.c reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); reg 237 drivers/gpu/drm/amd/amdgpu/navi10_ih.c tmp = RREG32_NO_KIQ(reg); reg 239 drivers/gpu/drm/amd/amdgpu/navi10_ih.c WREG32_NO_KIQ(reg, tmp); reg 74 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : reg 77 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c u32 doorbell_range = RREG32(reg); reg 91 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c WREG32(reg, doorbell_range); reg 97 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); reg 99 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c u32 doorbell_range = RREG32(reg); reg 111 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c WREG32(reg, doorbell_range); reg 286 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c uint32_t reg; reg 288 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c reg = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER); reg 289 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c if (reg & 1) reg 292 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c if (reg & 0x80000000) reg 295 drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c if (!reg) { reg 73 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : reg 76 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c u32 doorbell_range = RREG32(reg); reg 84 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c WREG32(reg, doorbell_range); reg 246 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c uint32_t reg; reg 248 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c reg = RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER); reg 249 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c if (reg & 1) reg 252 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c if (reg & 0x80000000) reg 255 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c if (!reg) { reg 80 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : reg 83 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c u32 doorbell_range = RREG32(reg); reg 91 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c WREG32(reg, doorbell_range); reg 97 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); reg 99 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c u32 doorbell_range = RREG32(reg); reg 111 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c WREG32(reg, doorbell_range); reg 97 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c u32 reg, doorbell_range; reg 100 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c reg = instance + reg 111 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c reg = instance + 0x4 + reg 114 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c doorbell_range = RREG32(reg); reg 122 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c WREG32(reg, doorbell_range); reg 128 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c u32 reg; reg 132 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE); reg 134 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); reg 136 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c doorbell_range = RREG32(reg); reg 148 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c WREG32(reg, doorbell_range); reg 292 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c uint32_t reg; reg 294 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER); reg 295 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c if (reg & 1) reg 298 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c if (reg & 0x80000000) reg 301 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c if (!reg) { reg 62 drivers/gpu/drm/amd/amdgpu/nv.c static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) reg 70 drivers/gpu/drm/amd/amdgpu/nv.c WREG32(address, reg); reg 77 drivers/gpu/drm/amd/amdgpu/nv.c static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 85 drivers/gpu/drm/amd/amdgpu/nv.c WREG32(address, reg); reg 92 drivers/gpu/drm/amd/amdgpu/nv.c static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) reg 101 drivers/gpu/drm/amd/amdgpu/nv.c WREG32(address, (reg)); reg 107 drivers/gpu/drm/amd/amdgpu/nv.c static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 115 drivers/gpu/drm/amd/amdgpu/nv.c WREG32(address, (reg)); reg 39 drivers/gpu/drm/amd/amdgpu/nvd.h #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ reg 40 drivers/gpu/drm/amd/amdgpu/nvd.h ((reg) & 0xFFFF) | \ reg 596 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c uint32_t reg; reg 598 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000); reg 599 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false; reg 816 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c uint32_t reg, uint32_t val) reg 820 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c amdgpu_ring_write(ring, reg); reg 1087 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c uint32_t reg, uint32_t val) reg 1091 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c amdgpu_ring_write(ring, reg); reg 1630 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t reg, uint32_t val) reg 1634 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c amdgpu_ring_write(ring, reg); reg 1638 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, reg 1641 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); reg 1173 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t reg, uint32_t val) reg 1177 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c amdgpu_ring_write(ring, reg); reg 1181 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, reg 1187 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c amdgpu_ring_write(ring, reg << 2); reg 904 drivers/gpu/drm/amd/amdgpu/si.c static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg) reg 910 drivers/gpu/drm/amd/amdgpu/si.c WREG32(AMDGPU_PCIE_INDEX, reg); reg 917 drivers/gpu/drm/amd/amdgpu/si.c static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 922 drivers/gpu/drm/amd/amdgpu/si.c WREG32(AMDGPU_PCIE_INDEX, reg); reg 929 drivers/gpu/drm/amd/amdgpu/si.c static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg) reg 935 drivers/gpu/drm/amd/amdgpu/si.c WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); reg 942 drivers/gpu/drm/amd/amdgpu/si.c static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 947 drivers/gpu/drm/amd/amdgpu/si.c WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); reg 954 drivers/gpu/drm/amd/amdgpu/si.c static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg) reg 960 drivers/gpu/drm/amd/amdgpu/si.c WREG32(SMC_IND_INDEX_0, (reg)); reg 966 drivers/gpu/drm/amd/amdgpu/si.c static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 971 drivers/gpu/drm/amd/amdgpu/si.c WREG32(SMC_IND_INDEX_0, (reg)); reg 1782 drivers/gpu/drm/amd/amdgpu/si.c static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg) reg 1788 drivers/gpu/drm/amd/amdgpu/si.c WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); reg 1794 drivers/gpu/drm/amd/amdgpu/si.c static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 1799 drivers/gpu/drm/amd/amdgpu/si.c WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); reg 1804 drivers/gpu/drm/amd/amdgpu/si.c static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg) reg 1810 drivers/gpu/drm/amd/amdgpu/si.c WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); reg 1816 drivers/gpu/drm/amd/amdgpu/si.c static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 1821 drivers/gpu/drm/amd/amdgpu/si.c WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); reg 459 drivers/gpu/drm/amd/amdgpu/si_dma.c uint32_t reg, uint32_t val) reg 462 drivers/gpu/drm/amd/amdgpu/si_dma.c amdgpu_ring_write(ring, (0xf << 16) | reg); reg 2758 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 load_line_slope, reg; reg 2769 drivers/gpu/drm/amd/amdgpu/si_dpm.c reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; reg 2770 drivers/gpu/drm/amd/amdgpu/si_dpm.c reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); reg 2771 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(CG_CAC_CTRL, reg); reg 4838 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 reg; reg 4916 drivers/gpu/drm/amd/amdgpu/si_dpm.c reg = CG_R(0xffff) | CG_L(0); reg 4917 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->initialState.levels[0].aT = cpu_to_be32(reg); reg 4942 drivers/gpu/drm/amd/amdgpu/si_dpm.c reg = MIN_POWER_MASK | MAX_POWER_MASK; reg 4943 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); reg 4945 drivers/gpu/drm/amd/amdgpu/si_dpm.c reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; reg 4946 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); reg 4968 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 reg; reg 5084 drivers/gpu/drm/amd/amdgpu/si_dpm.c reg = MIN_POWER_MASK | MAX_POWER_MASK; reg 5085 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); reg 5087 drivers/gpu/drm/amd/amdgpu/si_dpm.c reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; reg 5088 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); reg 1649 drivers/gpu/drm/amd/amdgpu/sid.h #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ reg 1650 drivers/gpu/drm/amd/amdgpu/sid.h (((reg) >> 2) & 0xFFFF) | \ reg 55 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT); reg 57 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0); reg 58 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c WREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT, reg); reg 82 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t reg = 0; reg 84 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1); reg 85 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_RESTART_EN, 1); reg 86 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_MASTER, 0); reg 87 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_SLAVE, 0); reg 89 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MAX_SPEED_MODE, 2); reg 90 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MASTER_MODE, 1); reg 92 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CON, reg); reg 131 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t reg, reg_c_tx_abrt_source; reg 142 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); reg 144 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c } while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0); reg 150 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT); reg 152 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) { reg 229 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t bytes_sent, reg, ret = 0; reg 254 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); reg 255 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c if (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) { reg 257 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = 0; reg 263 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART, reg 265 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, data[bytes_sent]); reg 270 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP, reg 273 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 0); reg 274 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg); reg 280 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); reg 282 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c } while (numbytes && REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)); reg 340 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t reg = 0; reg 349 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART, reg 352 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, 0); reg 354 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 1); reg 359 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP, reg 362 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg); reg 380 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD); reg 381 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT); reg 402 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c uint32_t reg = 0; reg 405 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1); reg 406 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg); reg 409 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ABORT, 1); reg 410 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg); reg 97 drivers/gpu/drm/amd/amdgpu/soc15.c static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) reg 105 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, reg); reg 112 drivers/gpu/drm/amd/amdgpu/soc15.c static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 120 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, reg); reg 127 drivers/gpu/drm/amd/amdgpu/soc15.c static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) reg 136 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, reg); reg 141 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, reg + 4); reg 148 drivers/gpu/drm/amd/amdgpu/soc15.c static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) reg 157 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, reg); reg 163 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, reg + 4); reg 170 drivers/gpu/drm/amd/amdgpu/soc15.c static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) reg 179 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, ((reg) & 0x1ff)); reg 185 drivers/gpu/drm/amd/amdgpu/soc15.c static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 193 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, ((reg) & 0x1ff)); reg 198 drivers/gpu/drm/amd/amdgpu/soc15.c static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) reg 207 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, (reg)); reg 213 drivers/gpu/drm/amd/amdgpu/soc15.c static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 221 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(address, (reg)); reg 226 drivers/gpu/drm/amd/amdgpu/soc15.c static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) reg 232 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); reg 238 drivers/gpu/drm/amd/amdgpu/soc15.c static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 243 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); reg 248 drivers/gpu/drm/amd/amdgpu/soc15.c static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) reg 254 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); reg 260 drivers/gpu/drm/amd/amdgpu/soc15.c static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 265 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); reg 441 drivers/gpu/drm/amd/amdgpu/soc15.c u32 tmp, reg; reg 446 drivers/gpu/drm/amd/amdgpu/soc15.c reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; reg 451 drivers/gpu/drm/amd/amdgpu/soc15.c tmp = RREG32(reg); reg 456 drivers/gpu/drm/amd/amdgpu/soc15.c if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || reg 457 drivers/gpu/drm/amd/amdgpu/soc15.c reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || reg 458 drivers/gpu/drm/amd/amdgpu/soc15.c reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || reg 459 drivers/gpu/drm/amd/amdgpu/soc15.c reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) reg 460 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32_RLC(reg, tmp); reg 462 drivers/gpu/drm/amd/amdgpu/soc15.c WREG32(reg, tmp); reg 40 drivers/gpu/drm/amd/amdgpu/soc15.h u32 reg; reg 63 drivers/gpu/drm/amd/amdgpu/soc15.h #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg reg 67 drivers/gpu/drm/amd/amdgpu/soc15.h #define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \ reg 68 drivers/gpu/drm/amd/amdgpu/soc15.h { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask } reg 28 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) reg 30 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define WREG32_FIELD15(ip, idx, reg, field, val) \ reg 31 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ reg 32 drivers/gpu/drm/amd/amdgpu/soc15_common.h (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ reg 33 drivers/gpu/drm/amd/amdgpu/soc15_common.h & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) reg 35 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define RREG32_SOC15(ip, inst, reg) \ reg 36 drivers/gpu/drm/amd/amdgpu/soc15_common.h RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) reg 38 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \ reg 39 drivers/gpu/drm/amd/amdgpu/soc15_common.h RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset) reg 41 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define WREG32_SOC15(ip, inst, reg, value) \ reg 42 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) reg 44 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \ reg 45 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) reg 47 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \ reg 48 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value) reg 50 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask, ret) \ reg 53 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ reg 62 drivers/gpu/drm/amd/amdgpu/soc15_common.h tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ reg 66 drivers/gpu/drm/amd/amdgpu/soc15_common.h inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \ reg 74 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define WREG32_RLC(reg, value) \ reg 83 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32(r1, (reg | 0x80000000)); \ reg 92 drivers/gpu/drm/amd/amdgpu/soc15_common.h pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg); \ reg 94 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32(reg, value); \ reg 98 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \ reg 100 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\ reg 116 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define WREG32_SOC15_RLC(ip, inst, reg, value) \ reg 118 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\ reg 122 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \ reg 123 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \ reg 124 drivers/gpu/drm/amd/amdgpu/soc15_common.h (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ reg 125 drivers/gpu/drm/amd/amdgpu/soc15_common.h & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) reg 127 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \ reg 128 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset), value) reg 41 drivers/gpu/drm/amd/amdgpu/soc15d.h #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ reg 42 drivers/gpu/drm/amd/amdgpu/soc15d.h ((reg) & 0xFFFF) | \ reg 74 drivers/gpu/drm/amd/amdgpu/soc15d.h #define PACKETJ(reg, r, cond, type) ((reg & 0x3FFFF) | \ reg 1032 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c uint32_t reg, uint32_t val) reg 1035 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c amdgpu_ring_write(ring, reg << 2); reg 1272 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i); reg 1274 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c reg -= p->adev->reg_offset[UVD_HWIP][0][1]; reg 1275 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c reg += p->adev->reg_offset[UVD_HWIP][1][1]; reg 1277 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_set_ib_value(p, ib_idx, i, reg); reg 1336 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t reg, uint32_t val) reg 1342 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, reg << 2); reg 1351 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, reg 1358 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, reg << 2); reg 1404 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t reg, uint32_t val, reg 1408 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, reg << 2); reg 1426 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t reg, uint32_t val) reg 1429 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, reg << 2); reg 980 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c static void vce_v4_0_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, reg 984 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c amdgpu_ring_write(ring, reg << 2); reg 1002 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t reg, uint32_t val) reg 1005 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c amdgpu_ring_write(ring, reg << 2); reg 1540 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, uint32_t val, reg 1547 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, reg << 2); reg 1575 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, uint32_t val) reg 1581 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, reg << 2); reg 1691 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, uint32_t val, reg 1695 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, reg << 2); reg 1713 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, uint32_t val) reg 1716 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, reg << 2); reg 1935 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, uint32_t val, reg 1939 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg_offset = (reg << 2); reg 1980 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, uint32_t val) reg 1983 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg_offset = (reg << 2); reg 2031 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, reg_offset, val, mask, i; reg 2034 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW); reg 2035 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_offset = (reg << 2); reg 2040 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH); reg 2041 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_offset = (reg << 2); reg 2052 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL); reg 2053 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_offset = (reg << 2); reg 2058 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA); reg 2059 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_offset = (reg << 2); reg 2064 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL); reg 2065 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_offset = (reg << 2); reg 2091 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR); reg 2092 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_offset = (reg << 2); reg 2097 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL); reg 2098 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c reg_offset = (reg << 2); reg 1599 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, reg 1605 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, reg << 2); reg 1634 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t reg, uint32_t val) reg 1639 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, reg << 2); reg 1765 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, reg 1769 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, reg << 2); reg 1786 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) reg 1789 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, reg << 2); reg 1987 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, reg 1990 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t reg_offset = (reg << 2); reg 2029 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) reg 2031 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t reg_offset = (reg << 2); reg 34 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h extern void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, reg 39 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h uint32_t reg, uint32_t val); reg 46 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h extern void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, reg 50 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h extern void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); reg 58 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h extern void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, reg 62 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h extern void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); reg 376 drivers/gpu/drm/amd/amdgpu/vega10_ih.c u32 wptr, reg, tmp; reg 386 drivers/gpu/drm/amd/amdgpu/vega10_ih.c reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); reg 388 drivers/gpu/drm/amd/amdgpu/vega10_ih.c reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); reg 390 drivers/gpu/drm/amd/amdgpu/vega10_ih.c reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); reg 394 drivers/gpu/drm/amd/amdgpu/vega10_ih.c wptr = RREG32_NO_KIQ(reg); reg 411 drivers/gpu/drm/amd/amdgpu/vega10_ih.c reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); reg 413 drivers/gpu/drm/amd/amdgpu/vega10_ih.c reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); reg 415 drivers/gpu/drm/amd/amdgpu/vega10_ih.c reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); reg 419 drivers/gpu/drm/amd/amdgpu/vega10_ih.c tmp = RREG32_NO_KIQ(reg); reg 421 drivers/gpu/drm/amd/amdgpu/vega10_ih.c WREG32_NO_KIQ(reg, tmp); reg 85 drivers/gpu/drm/amd/amdgpu/vi.c static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) reg 91 drivers/gpu/drm/amd/amdgpu/vi.c WREG32_NO_KIQ(mmPCIE_INDEX, reg); reg 98 drivers/gpu/drm/amd/amdgpu/vi.c static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 103 drivers/gpu/drm/amd/amdgpu/vi.c WREG32_NO_KIQ(mmPCIE_INDEX, reg); reg 110 drivers/gpu/drm/amd/amdgpu/vi.c static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) reg 116 drivers/gpu/drm/amd/amdgpu/vi.c WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); reg 122 drivers/gpu/drm/amd/amdgpu/vi.c static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 127 drivers/gpu/drm/amd/amdgpu/vi.c WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); reg 136 drivers/gpu/drm/amd/amdgpu/vi.c static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg) reg 142 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmMP0PUB_IND_INDEX, (reg)); reg 148 drivers/gpu/drm/amd/amdgpu/vi.c static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 153 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmMP0PUB_IND_INDEX, (reg)); reg 158 drivers/gpu/drm/amd/amdgpu/vi.c static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) reg 164 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); reg 170 drivers/gpu/drm/amd/amdgpu/vi.c static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 175 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); reg 180 drivers/gpu/drm/amd/amdgpu/vi.c static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg) reg 186 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmDIDT_IND_INDEX, (reg)); reg 192 drivers/gpu/drm/amd/amdgpu/vi.c static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 197 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmDIDT_IND_INDEX, (reg)); reg 202 drivers/gpu/drm/amd/amdgpu/vi.c static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) reg 208 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmGC_CAC_IND_INDEX, (reg)); reg 214 drivers/gpu/drm/amd/amdgpu/vi.c static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) reg 219 drivers/gpu/drm/amd/amdgpu/vi.c WREG32(mmGC_CAC_IND_INDEX, (reg)); reg 453 drivers/gpu/drm/amd/amdgpu/vi.c uint32_t reg = 0; reg 457 drivers/gpu/drm/amd/amdgpu/vi.c reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER); reg 459 drivers/gpu/drm/amd/amdgpu/vi.c if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER)) reg 462 drivers/gpu/drm/amd/amdgpu/vi.c if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE)) reg 466 drivers/gpu/drm/amd/amdgpu/vi.c if (reg == 0) { reg 98 drivers/gpu/drm/amd/amdgpu/vid.h #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ reg 99 drivers/gpu/drm/amd/amdgpu/vid.h ((reg) & 0xFFFF) | \ reg 35 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h TP_PROTO(unsigned long *read_count, uint32_t reg, uint32_t value), reg 36 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h TP_ARGS(read_count, reg, value), reg 38 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h __field(uint32_t, reg) reg 42 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h __entry->reg = reg; reg 47 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h (unsigned long)__entry->reg, reg 52 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h TP_PROTO(unsigned long *write_count, uint32_t reg, uint32_t value), reg 53 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h TP_ARGS(write_count, reg, value), reg 55 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h __field(uint32_t, reg) reg 59 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h __entry->reg = reg; reg 64 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h (unsigned long)__entry->reg, reg 50 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c #define REG(reg)\ reg 51 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c (bios->regs->reg) reg 46 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c #define REG(reg) \ reg 47 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c (clk_mgr->regs->reg) reg 44 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c #define REG(reg) \ reg 45 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c (clk_mgr->regs->reg) reg 40 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c #define REG(reg) \ reg 41 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c (abm_dce->regs->reg) reg 41 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c #define REG(reg)\ reg 42 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c (aud->regs->reg) reg 48 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c #define IX_REG(reg)\ reg 49 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c ix ## reg reg 938 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c const struct dce_audio_registers *reg, reg 954 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c audio->regs = reg; reg 134 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h const struct dce_audio_registers *reg, reg 38 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c #define REG(reg) \ reg 39 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c (clk_mgr_dce->regs->reg) reg 42 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c #define REG(reg)\ reg 43 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c (clk_src->regs->reg) reg 40 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c #define REG(reg) \ reg 41 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c (dmcu_dce->regs->reg) reg 33 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c #define REG(reg)\ reg 34 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c hws->regs->reg reg 36 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c #define REG(reg)\ reg 37 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->regs->reg reg 32 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c #define REG(reg) \ reg 33 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c (ipp_dce->regs->reg) reg 65 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c #define REG(reg)\ reg 66 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c (enc110->link_regs->reg) reg 68 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c #define AUX_REG(reg)\ reg 69 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c (enc110->aux_regs->reg) reg 71 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c #define HPD_REG(reg)\ reg 72 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c (enc110->hpd_regs->reg) reg 94 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c #define DIG_REG(reg)\ reg 95 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c (reg + enc110->offsets.dig) reg 97 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c #define DP_REG(reg)\ reg 98 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c (reg + enc110->offsets.dp) reg 32 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c #define REG(reg)\ reg 33 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->regs->reg reg 35 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c #define REG(reg)\ reg 36 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c (opp110->regs->reg) reg 37 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c #define REG(reg)\ reg 38 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c (enc110->regs->reg) reg 32 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c #define REG(reg) \ reg 33 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c (xfm_dce->regs->reg) reg 65 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c #define HW_REG_CRTC(reg, id)\ reg 66 drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c (reg + reg_offsets[id].crtc) reg 392 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c #define REG(reg) mm ## reg reg 42 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c #define DCP_REG(reg)\ reg 43 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c (reg + cp110->offsets.dcp_offset) reg 44 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c #define DMIF_REG(reg)\ reg 45 drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c (reg + cp110->offsets.dmif_offset) reg 78 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c #define REG(reg)\ reg 79 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c hws->regs->reg reg 104 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c #define HW_REG_BLND(reg, id)\ reg 105 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c (reg + reg_offsets[id].blnd) reg 107 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c #define HW_REG_CRTC(reg, id)\ reg 108 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c (reg + reg_offsets[id].crtc) reg 433 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c #define REG(reg) mm ## reg reg 48 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c #define CRTC_REG(reg) (reg + tg110->offsets.crtc) reg 49 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c #define DCP_REG(reg) (reg + tg110->offsets.dcp) reg 41 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c #define DCP_REG(reg)\ reg 42 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c (reg + cp110->offsets.dcp_offset) reg 43 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c #define DMIF_REG(reg)\ reg 44 drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c (reg + cp110->offsets.dmif_offset) reg 62 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c #define HW_REG_CRTC(reg, id)\ reg 63 drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c (reg + reg_offsets[id].crtc) reg 410 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c #define REG(reg) mm ## reg reg 42 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c #define REG(reg)\ reg 43 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c hws->regs->reg reg 74 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c #define HW_REG_CRTC(reg, id)\ reg 75 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c (reg + reg_offsets[id].crtc) reg 48 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c #define CRTC_REG_UPDATE(reg, field, val) \ reg 49 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c CRTC_REG_UPDATE_N(reg, 1, FD(reg##__##field), val) reg 51 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c #define CRTC_REG_UPDATE_2(reg, field1, val1, field2, val2) \ reg 52 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c CRTC_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) reg 54 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c #define CRTC_REG_UPDATE_3(reg, field1, val1, field2, val2, field3, val3) \ reg 55 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3) reg 57 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c #define CRTC_REG_UPDATE_4(reg, field1, val1, field2, val2, field3, val3, field4, val4) \ reg 58 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3, FD(reg##__##field4), val4) reg 60 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c #define CRTC_REG_UPDATE_5(reg, field1, val1, field2, val2, field3, val3, field4, val4, field5, val5) \ reg 61 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3, FD(reg##__##field4), val4, FD(reg##__##field5), val5) reg 63 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c #define CRTC_REG_SET(reg, field, val) \ reg 64 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c CRTC_REG_SET_N(reg, 1, FD(reg##__##field), val) reg 66 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c #define CRTC_REG_SET_2(reg, field1, val1, field2, val2) \ reg 67 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c CRTC_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2) reg 69 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c #define CRTC_REG_SET_3(reg, field1, val1, field2, val2, field3, val3) \ reg 70 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c CRTC_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3) reg 64 drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c #define HW_REG_CRTC(reg, id)\ reg 65 drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c (reg + reg_offsets[id].crtc) reg 424 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c #define REG(reg) mm ## reg reg 83 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c #define CRTC_REG(reg) (reg + tg110->offsets.crtc) reg 84 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c #define DCP_REG(reg) (reg + tg110->offsets.dcp) reg 85 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c #define DMIF_REG(reg) (reg + tg110->offsets.dmif) reg 32 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c #define REG(reg) reg reg 39 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c reg->shifts.field_name, reg->masks.field_name reg 44 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c const struct color_matrices_reg *reg) reg 49 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c for (cur_csc_reg = reg->csc_c11_c12; reg 50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c cur_csc_reg <= reg->csc_c33_c34; reg 68 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c const struct xfer_func_reg *reg) reg 73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET_2(reg->start_cntl_b, 0, reg 76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET_2(reg->start_cntl_g, 0, reg 79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET_2(reg->start_cntl_r, 0, reg 83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET(reg->start_slope_cntl_b, 0, reg 85 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET(reg->start_slope_cntl_g, 0, reg 87 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET(reg->start_slope_cntl_r, 0, reg 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET(reg->start_end_cntl1_b, 0, reg 92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET_2(reg->start_end_cntl2_b, 0, reg 96 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET(reg->start_end_cntl1_g, 0, reg 98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET_2(reg->start_end_cntl2_g, 0, reg 102 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET(reg->start_end_cntl1_r, 0, reg 104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c REG_SET_2(reg->start_end_cntl2_r, 0, reg 108 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c for (reg_region_cur = reg->region_start; reg 109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c reg_region_cur <= reg->region_end; reg 95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h const struct color_matrices_reg *reg); reg 100 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h const struct xfer_func_reg *reg); reg 41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c #define REG(reg)\ reg 42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c dpp->tf_regs->reg reg 42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c #define REG(reg)\ reg 43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp->tf_regs->reg reg 278 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct xfer_func_reg *reg) reg 280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; reg 281 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; reg 282 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; reg 283 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; reg 284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; reg 285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; reg 286 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; reg 287 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; reg 289 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B; reg 290 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; reg 291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; reg 292 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; reg 293 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B; reg 294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B; reg 295 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; reg 296 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; reg 297 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B; reg 298 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B; reg 299 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; reg 300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; reg 305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct xfer_func_reg *reg) reg 307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET; reg 308 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET; reg 309 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; reg 310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; reg 311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET; reg 312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET; reg 313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; reg 314 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; reg 316 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_end = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_B; reg 317 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_end = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_B; reg 318 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_end_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B; reg 319 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_end_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B; reg 320 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_end_base = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_BASE_B; reg 321 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_end_base = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_BASE_B; reg 322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; reg 323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.field_region_linear_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; reg 324 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region_start = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_B; reg 325 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_region_start = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_B; reg 326 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; reg 327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; reg 42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c #define REG(reg)\ reg 43 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->tf_regs->reg reg 34 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c #define REG(reg)\ reg 35 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c dwbc10->dwbc_regs->reg reg 37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c #define REG(reg)\ reg 38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c hubbub1->regs->reg reg 31 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c #define REG(reg)\ reg 32 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1->hubp_regs->reg reg 60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c #define REG(reg)\ reg 61 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hws->regs->reg reg 32 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c #define REG(reg) \ reg 33 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c (ippn10->regs->reg) reg 45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c #define REG(reg)\ reg 46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c (enc10->link_regs->reg) reg 1337 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c #define HPD_REG(reg)\ reg 1338 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c (enc10->hpd_regs->reg) reg 1369 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c #define AUX_REG(reg)\ reg 1370 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c (enc10->aux_regs->reg) reg 1384 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c #define AUX_REG_UPDATE_2(reg, f1, v1, f2, v2) \ reg 1385 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c AUX_REG_UPDATE_N(reg, 2,\ reg 1386 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c FN(reg, f1), v1,\ reg 1387 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c FN(reg, f2), v2) reg 29 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c #define REG(reg)\ reg 30 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c mpc10->mpc_regs->reg reg 32 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c #define REG(reg) \ reg 33 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c (oppn10->regs->reg) reg 31 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c #define REG(reg)\ reg 32 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c optc1->tg_regs->reg reg 37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c #define REG(reg)\ reg 38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c (enc1->regs->reg) reg 35 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c #define REG(reg) \ reg 36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c (dccg_dcn->regs->reg) reg 41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c #define REG(reg)\ reg 42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c dpp->tf_regs->reg reg 36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c #define REG(reg)\ reg 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dpp->tf_regs->reg reg 208 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct xfer_func_reg *reg) reg 210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; reg 211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; reg 212 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; reg 213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; reg 214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; reg 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; reg 216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; reg 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; reg 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; reg 220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; reg 221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; reg 222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; reg 223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; reg 224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; reg 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; reg 226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; reg 227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B; reg 228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B; reg 229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; reg 230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; reg 64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c #define REG(reg)\ reg 65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc20->dsc_regs->reg reg 33 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c #define REG(reg)\ reg 34 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c dwbc20->dwbc_regs->reg reg 36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c #define REG(reg)\ reg 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c dwbc20->dwbc_regs->reg reg 31 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c #define REG(reg)\ reg 32 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub1->regs->reg reg 41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c #define REG(reg)\ reg 42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub1->regs->reg reg 33 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c #define REG(reg)\ reg 34 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2->hubp_regs->reg reg 60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c #define REG(reg)\ reg 61 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hws->regs->reg reg 42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c #define REG(reg)\ reg 43 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c (enc10->link_regs->reg) reg 266 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c #define AUX_REG(reg)\ reg 267 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c (enc10->aux_regs->reg) reg 33 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c #define REG(reg)\ reg 34 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c mcif_wb20->mcif_wb_regs->reg reg 33 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c #define REG(reg)\ reg 34 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc20->mpc_regs->reg reg 210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct xfer_func_reg *reg) reg 214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.exp_region0_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; reg 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; reg 216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.exp_region0_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; reg 217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; reg 218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.exp_region1_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; reg 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; reg 220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.exp_region1_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; reg 221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; reg 222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.field_region_end = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B; reg 223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; reg 224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.field_region_end_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; reg 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.field_region_end_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; reg 226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.field_region_end_base = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; reg 227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.field_region_end_base = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; reg 228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.field_region_linear_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; reg 229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.field_region_linear_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; reg 230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.exp_region_start = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_B; reg 231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_region_start = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_B; reg 232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.exp_resion_start_segment = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B; reg 233 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->masks.exp_resion_start_segment = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B; reg 30 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c #define REG(reg) \ reg 31 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c (oppn20->regs->reg) reg 30 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c #define REG(reg)\ reg 31 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c optc1->tg_regs->reg reg 37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c #define REG(reg)\ reg 38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c (enc1->regs->reg) reg 31 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c #define REG(reg)\ reg 32 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c vmid->regs->reg reg 31 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c #define REG(reg)\ reg 32 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub1->regs->reg reg 42 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c #define REG(reg)\ reg 43 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub1->regs->reg reg 30 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c #define REG(reg)\ reg 31 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c hubp21->hubp_regs->reg reg 159 drivers/gpu/drm/amd/display/dc/dm_services.h #define dm_write_reg_soc15(ctx, reg, inst_offset, value) \ reg 160 drivers/gpu/drm/amd/display/dc/dm_services.h dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__) reg 162 drivers/gpu/drm/amd/display/dc/dm_services.h #define dm_read_reg_soc15(ctx, reg, inst_offset) \ reg 163 drivers/gpu/drm/amd/display/dc/dm_services.h dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__) reg 46 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c #define REG(reg)\ reg 47 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c (ddc->regs->reg) reg 44 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c #define REG(reg)\ reg 45 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c (generic->regs->reg) reg 39 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c #define REG(reg)\ reg 40 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c (gpio->regs->reg) reg 44 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c #define REG(reg)\ reg 45 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c (hpd->regs->reg) reg 67 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ reg 68 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_SET_N(reg, 2, init_value, \ reg 69 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 70 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2) reg 72 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ reg 73 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_SET_N(reg, 3, init_value, \ reg 74 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 75 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2,\ reg 76 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3) reg 78 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ reg 79 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_SET_N(reg, 4, init_value, \ reg 80 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 81 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2,\ reg 82 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3,\ reg 83 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4) reg 85 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ reg 87 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_SET_N(reg, 5, init_value, \ reg 88 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 89 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2,\ reg 90 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3,\ reg 91 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4,\ reg 92 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5) reg 94 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ reg 96 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_SET_N(reg, 6, init_value, \ reg 97 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 98 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2,\ reg 99 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3,\ reg 100 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4,\ reg 101 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5,\ reg 102 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6) reg 104 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ reg 106 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_SET_N(reg, 7, init_value, \ reg 107 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 108 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2,\ reg 109 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3,\ reg 110 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4,\ reg 111 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5,\ reg 112 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6,\ reg 113 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7) reg 115 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_8(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ reg 117 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_SET_N(reg, 8, init_value, \ reg 118 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 119 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2,\ reg 120 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3,\ reg 121 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4,\ reg 122 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5,\ reg 123 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6,\ reg 124 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7,\ reg 125 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f8), v8) reg 127 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_9(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \ reg 129 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_SET_N(reg, 9, init_value, \ reg 130 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 131 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2, \ reg 132 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ reg 133 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ reg 134 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ reg 135 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6, \ reg 136 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7, \ reg 137 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f8), v8, \ reg 138 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f9), v9) reg 140 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \ reg 142 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_SET_N(reg, 10, init_value, \ reg 143 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 144 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2, \ reg 145 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ reg 146 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ reg 147 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ reg 148 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6, \ reg 149 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7, \ reg 150 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f8), v8, \ reg 151 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f9), v9, \ reg 152 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f10), v10) reg 234 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_2(reg, f1, v1, f2, v2) \ reg 235 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_UPDATE_N(reg, 2,\ reg 236 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 237 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2) reg 239 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \ reg 240 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_UPDATE_N(reg, 3, \ reg 241 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 242 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2, \ reg 243 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3) reg 245 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ reg 246 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_UPDATE_N(reg, 4, \ reg 247 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 248 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2, \ reg 249 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ reg 250 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4) reg 252 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ reg 253 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_UPDATE_N(reg, 5, \ reg 254 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 255 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2, \ reg 256 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ reg 257 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ reg 258 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5) reg 260 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ reg 261 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_UPDATE_N(reg, 6, \ reg 262 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 263 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2, \ reg 264 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ reg 265 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ reg 266 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ reg 267 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6) reg 269 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ reg 270 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_UPDATE_N(reg, 7, \ reg 271 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 272 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2, \ reg 273 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ reg 274 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ reg 275 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ reg 276 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6, \ reg 277 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7) reg 279 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ reg 280 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_UPDATE_N(reg, 8, \ reg 281 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 282 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2, \ reg 283 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ reg 284 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ reg 285 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ reg 286 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6, \ reg 287 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7, \ reg 288 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f8), v8) reg 290 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \ reg 291 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_UPDATE_N(reg, 9, \ reg 292 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 293 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2, \ reg 294 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ reg 295 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ reg 296 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ reg 297 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6, \ reg 298 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7, \ reg 299 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f8), v8, \ reg 300 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f9), v9) reg 302 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\ reg 303 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_UPDATE_N(reg, 10, \ reg 304 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 305 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2, \ reg 306 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ reg 307 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ reg 308 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ reg 309 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6, \ reg 310 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7, \ reg 311 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f8), v8, \ reg 312 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f9), v9, \ reg 313 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f10), v10) reg 315 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ reg 317 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_UPDATE_N(reg, 14, \ reg 318 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 319 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2, \ reg 320 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ reg 321 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ reg 322 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ reg 323 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6, \ reg 324 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7, \ reg 325 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f8), v8, \ reg 326 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f9), v9, \ reg 327 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f10), v10, \ reg 328 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f11), v11, \ reg 329 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f12), v12, \ reg 330 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f13), v13, \ reg 331 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f14), v14) reg 333 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ reg 335 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_UPDATE_N(reg, 19, \ reg 336 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 337 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2, \ reg 338 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ reg 339 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ reg 340 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ reg 341 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6, \ reg 342 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7, \ reg 343 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f8), v8, \ reg 344 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f9), v9, \ reg 345 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f10), v10, \ reg 346 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f11), v11, \ reg 347 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f12), v12, \ reg 348 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f13), v13, \ reg 349 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f14), v14, \ reg 350 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f15), v15, \ reg 351 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f16), v16, \ reg 352 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f17), v17, \ reg 353 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f18), v18, \ reg 354 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f19), v19) reg 356 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ reg 358 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_UPDATE_N(reg, 20, \ reg 359 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 360 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2, \ reg 361 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f3), v3, \ reg 362 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ reg 363 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ reg 364 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6, \ reg 365 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7, \ reg 366 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f8), v8, \ reg 367 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f9), v9, \ reg 368 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f10), v10, \ reg 369 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f11), v11, \ reg 370 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f12), v12, \ reg 371 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f13), v13, \ reg 372 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f14), v14, \ reg 373 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f15), v15, \ reg 374 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f16), v16, \ reg 375 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f17), v17, \ reg 376 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f18), v18, \ reg 377 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f19), v19, \ reg 378 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f20), v20) reg 382 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_SEQ_2(reg, f1, v1, f2, v2) \ reg 383 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h { uint32_t val = REG_UPDATE(reg, f1, v1); \ reg 384 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_SET(reg, val, f2, v2); } reg 386 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_SEQ_3(reg, f1, v1, f2, v2, f3, v3) \ reg 387 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h { uint32_t val = REG_UPDATE(reg, f1, v1); \ reg 388 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h val = REG_SET(reg, val, f2, v2); \ reg 389 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG_SET(reg, val, f3, v3); } reg 454 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 455 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2) reg 471 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f1), v1,\ reg 472 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f2), v2) reg 121 drivers/gpu/drm/amd/include/cgs_common.h #define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT reg 122 drivers/gpu/drm/amd/include/cgs_common.h #define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK reg 124 drivers/gpu/drm/amd/include/cgs_common.h #define CGS_REG_SET_FIELD(orig_val, reg, field, field_val) \ reg 125 drivers/gpu/drm/amd/include/cgs_common.h (((orig_val) & ~CGS_REG_FIELD_MASK(reg, field)) | \ reg 126 drivers/gpu/drm/amd/include/cgs_common.h (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field)))) reg 128 drivers/gpu/drm/amd/include/cgs_common.h #define CGS_REG_GET_FIELD(value, reg, field) \ reg 129 drivers/gpu/drm/amd/include/cgs_common.h (((value) & CGS_REG_FIELD_MASK(reg, field)) >> CGS_REG_FIELD_SHIFT(reg, field)) reg 131 drivers/gpu/drm/amd/include/cgs_common.h #define CGS_WREG32_FIELD(device, reg, field, val) \ reg 132 drivers/gpu/drm/amd/include/cgs_common.h cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field)) reg 134 drivers/gpu/drm/amd/include/cgs_common.h #define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \ reg 135 drivers/gpu/drm/amd/include/cgs_common.h cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field)) reg 27 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c static bool baco_wait_register(struct pp_hwmgr *hwmgr, u32 reg, u32 mask, u32 value) reg 34 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c data = RREG32(reg); reg 44 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c static bool baco_cmd_handler(struct pp_hwmgr *hwmgr, u32 command, u32 reg, u32 mask, reg 53 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c WREG32(reg, value << shift); reg 56 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c data = RREG32(reg); reg 58 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c WREG32(reg, data); reg 61 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c ret = baco_wait_register(hwmgr, reg, mask, value); reg 87 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c u32 i, reg = 0; reg 93 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c reg = adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg] reg 95 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c if (!baco_cmd_handler(hwmgr, entry[i].cmd, reg, entry[i].mask, reg 311 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t reg; reg 314 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS); reg 315 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) == reg 34 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c uint32_t reg, data; reg 44 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0); reg 46 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) reg 56 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c uint32_t reg; reg 58 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL); reg 60 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c if (reg & BACO_CNTL__BACO_MODE_MASK) reg 124 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT reg 125 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK reg 127 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_SET_FIELD(origval, reg, field, fieldval) \ reg 128 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h (((origval) & ~PHM_FIELD_MASK(reg, field)) | \ reg 129 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field)))) reg 131 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_GET_FIELD(value, reg, field) \ reg 132 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h (((value) & PHM_FIELD_MASK(reg, field)) >> \ reg 133 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_FIELD_SHIFT(reg, field)) reg 138 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_READ_FIELD(device, reg, field) \ reg 139 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field) reg 141 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \ reg 142 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ reg 143 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h reg, field) reg 145 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \ reg 146 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ reg 147 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h reg, field) reg 149 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WRITE_FIELD(device, reg, field, fieldval) \ reg 150 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h cgs_write_register(device, mm##reg, PHM_SET_FIELD( \ reg 151 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h cgs_read_register(device, mm##reg), reg, field, fieldval)) reg 153 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \ reg 154 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h cgs_write_ind_register(device, port, ix##reg, \ reg 155 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ reg 156 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h reg, field, fieldval)) reg 158 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \ reg 159 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h cgs_write_ind_register(device, port, ix##reg, \ reg 160 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ reg 161 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h reg, field, fieldval)) reg 167 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \ reg 168 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) reg 170 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \ reg 171 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \ reg 172 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) reg 178 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \ reg 179 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) reg 181 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \ reg 182 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \ reg 183 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h (fieldval) << PHM_FIELD_SHIFT(reg, field), \ reg 184 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_FIELD_MASK(reg, field) ) reg 192 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \ reg 193 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) reg 195 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \ reg 196 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \ reg 197 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h (fieldval) << PHM_FIELD_SHIFT(reg, field), \ reg 198 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_FIELD_MASK(reg, field)) reg 206 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \ reg 207 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) reg 209 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \ reg 210 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, \ reg 211 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h (fieldval) << PHM_FIELD_SHIFT(reg, field), \ reg 212 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_FIELD_MASK(reg, field)) reg 219 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \ reg 221 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h mm##reg, value, mask) reg 223 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \ reg 224 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \ reg 225 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h (fieldval) << PHM_FIELD_SHIFT(reg, field), \ reg 226 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_FIELD_MASK(reg, field)) reg 43 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c uint32_t reg; reg 50 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0); reg 52 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) reg 62 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c uint32_t reg; reg 64 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL); reg 66 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c if (reg & BACO_CNTL__BACO_MODE_MASK) reg 34 drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h uint32_t reg; reg 229 drivers/gpu/drm/amd/powerplay/smu_v12_0.c uint32_t reg; reg 233 drivers/gpu/drm/amd/powerplay/smu_v12_0.c reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL); reg 234 drivers/gpu/drm/amd/powerplay/smu_v12_0.c gfxOff_Status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK) reg 52 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c uint32_t reg; reg 54 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); reg 56 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c phm_wait_for_register_unequal(hwmgr, reg, reg 505 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c uint32_t reg, data; reg 508 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c reg = pvirus->reg; reg 510 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c if (reg != 0xffffffff) reg 511 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c cgs_write_register(hwmgr->device, reg, data); reg 61 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c uint32_t reg; reg 64 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); reg 66 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c ret = phm_wait_for_register_unequal(hwmgr, reg, reg 71 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c uint32_t reg; reg 73 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); reg 75 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c phm_wait_for_register_unequal(hwmgr, reg, reg 22 drivers/gpu/drm/arc/arcpgu.h unsigned int reg, u32 value) reg 24 drivers/gpu/drm/arc/arcpgu.h iowrite32(value, arcpgu->regs + reg); reg 28 drivers/gpu/drm/arc/arcpgu.h unsigned int reg) reg 30 drivers/gpu/drm/arc/arcpgu.h return ioread32(arcpgu->regs + reg); reg 73 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c static void get_values_from_reg(void __iomem *reg, u32 offset, reg 82 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c val[i] = malidp_read32(reg, addr); reg 88 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c static void dump_block_header(struct seq_file *sf, void __iomem *reg) reg 93 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c d71_read_block_header(reg, &hdr); reg 174 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c u32 __iomem *reg = c->reg; reg 178 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write64(reg, BLK_P2_PTR_LOW, addr[2]); reg 182 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_P1_STRIDE, fb->pitches[1] * block_h); reg 183 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write64(reg, BLK_P1_PTR_LOW, addr[1]); reg 187 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_P0_STRIDE, fb->pitches[0] * block_h); reg 188 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write64(reg, BLK_P0_PTR_LOW, addr[0]); reg 189 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, LAYER_FMT, kfb->format_caps->hw_id); reg 194 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32_mask(c->reg, BLK_CONTROL, L_EN, 0); reg 204 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c u32 __iomem *reg = c->reg; reg 210 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, AD_CONTROL, to_ad_ctrl(fb->modifier)); reg 214 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, LAYER_AD_H_CROP, HV_CROP(st->afbc_crop_l, reg 216 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, LAYER_AD_V_CROP, HV_CROP(st->afbc_crop_t, reg 224 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_P1_PTR_LOW, lower_32_bits(addr)); reg 225 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_P1_PTR_HIGH, upper_32_bits(addr)); reg 254 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, LAYER_R_CONTROL, upsampling); reg 255 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write_group(reg, LAYER_YUV_RGB_COEFF0, reg 262 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_IN_SIZE, HV_SIZE(st->hsize, st->vsize)); reg 266 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32_mask(reg, BLK_CONTROL, ctrl_mask, ctrl); reg 275 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, LAYER_INFO, 1, &v[14]); reg 286 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c dump_block_header(sf, c->reg); reg 290 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0xD0, 1, v); reg 293 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0xD4, 1, v); reg 296 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0xD8, 4, v); reg 302 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0x100, 3, v); reg 307 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0x110, 2, v); reg 311 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0x118, 1, v); reg 314 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0x120, 2, v); reg 318 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0x130, 12, v); reg 324 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, LAYER_RGB_RGB_COEFF0, 12, v); reg 329 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0x160, 3, v); reg 342 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c struct block_header *blk, u32 __iomem *reg) reg 354 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c 1, reg, "LPU%d_LAYER%d", pipe_id, layer_id); reg 361 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c layer_info = malidp_read32(reg, LAYER_INFO); reg 371 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, LAYER_PALPHA, D71_PALPHA_DEF_MAP); reg 385 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c u32 __iomem *reg = c->reg; reg 392 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_IN_SIZE, HV_SIZE(st->hsize, st->vsize)); reg 393 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_INPUT_ID0, to_d71_input_id(state, 0)); reg 394 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32_mask(reg, BLK_CONTROL, mask, ctrl); reg 401 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c dump_block_header(sf, c->reg); reg 403 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0x80, 1, v); reg 406 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0xD0, 3, v); reg 411 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0xE0, 1, v); reg 415 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0x100 + i * 0x10, 3, v); reg 421 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0x130, 12, v); reg 428 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(c->reg, BLK_INPUT_ID0, 0); reg 429 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32_mask(c->reg, BLK_CONTROL, L_EN, 0); reg 439 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c struct block_header *blk, u32 __iomem *reg) reg 450 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c 1, get_valid_inputs(blk), 0, reg, reg 468 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c u32 __iomem *reg = c->reg; reg 471 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_CONTROL, 0); reg 474 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_INPUT_ID0 + (i << 2), 0); reg 481 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, CU_INPUT0_CONTROL + reg 515 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c u32 __iomem *reg = c->reg; reg 520 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c id_reg = reg + index; reg 521 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c cfg_reg = reg + index * CU_PER_INPUT_REGS; reg 532 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_SIZE, HV_SIZE(st->hsize, st->vsize)); reg 539 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c dump_block_header(sf, c->reg); reg 541 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0x80, 5, v); reg 545 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0xA0, 5, v); reg 552 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0xD0, 2, v); reg 556 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0xDC, 1, v); reg 560 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, v[4], 3, v); reg 566 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0x130, 2, v); reg 578 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c struct block_header *blk, u32 __iomem *reg) reg 591 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c CU_NUM_OUTPUT_IDS, reg, reg 604 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c static void d71_scaler_update_filter_lut(u32 __iomem *reg, u32 hsize_in, reg 632 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, SC_COEFFTAB, val); reg 639 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c u32 __iomem *reg = c->reg; reg 642 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c d71_scaler_update_filter_lut(reg, st->hsize_in, st->vsize_in, reg 645 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_IN_SIZE, HV_SIZE(st->hsize_in, st->vsize_in)); reg 646 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, SC_OUT_SIZE, HV_SIZE(st->hsize_out, st->vsize_out)); reg 647 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, SC_H_CROP, HV_CROP(st->left_crop, st->right_crop)); reg 680 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, SC_H_INIT_PH, init_ph); reg 683 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, SC_H_DELTA_PH, delta_ph); reg 686 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, SC_V_INIT_PH, init_ph); reg 689 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, SC_V_DELTA_PH, delta_ph); reg 700 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_CONTROL, ctrl); reg 701 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_INPUT_ID0, to_d71_input_id(state, 0)); reg 708 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c dump_block_header(sf, c->reg); reg 710 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0x80, 1, v); reg 713 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0xD0, 1, v); reg 716 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0xDC, 9, v); reg 735 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c struct block_header *blk, u32 __iomem *reg) reg 746 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c 1, get_valid_inputs(blk), 1, reg, reg 763 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(c->reg, BLK_CONTROL, 0); reg 813 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c u32 __iomem *reg = c->reg; reg 815 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_INPUT_ID0, to_d71_input_id(state, 0)); reg 816 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_SIZE, HV_SIZE(st->hsize, st->vsize)); reg 817 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, SP_OVERLAP_SIZE, st->overlap & 0x1FFF); reg 818 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_CONTROL, BLK_CTRL_EN); reg 825 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c dump_block_header(sf, c->reg); reg 827 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, BLK_INPUT_ID0, 1, v); reg 830 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, BLK_CONTROL, 3, v); reg 843 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c struct block_header *blk, u32 __iomem *reg) reg 855 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c 1, get_valid_inputs(blk), 2, reg, reg 875 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c u32 __iomem *reg = c->reg; reg 879 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, MG_INPUT_ID0 + index * 4, reg 882 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, MG_SIZE, HV_SIZE(st->hsize_merged, reg 884 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_CONTROL, BLK_CTRL_EN); reg 891 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c dump_block_header(sf, c->reg); reg 893 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, MG_INPUT_ID0, 1, &v); reg 896 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, MG_INPUT_ID1, 1, &v); reg 899 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, BLK_CONTROL, 1, &v); reg 902 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, MG_SIZE, 1, &v); reg 913 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c struct block_header *blk, u32 __iomem *reg) reg 926 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c MG_NUM_OUTPUTS_IDS, reg, reg 946 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c u32 __iomem *reg = c->reg; reg 950 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_INPUT_ID0 + index * 4, reg 953 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_SIZE, HV_SIZE(st->hsize, st->vsize)); reg 960 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c dump_block_header(sf, c->reg); reg 962 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0x80, 2, v); reg 966 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0xC0, 1, v); reg 969 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0xD0, 3, v); reg 974 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0x130, 12, v); reg 978 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0x170, 12, v); reg 990 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c struct block_header *blk, u32 __iomem *reg) reg 1003 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c IPS_NUM_OUTPUT_IDS, reg, "DOU%d_IPS", pipe_id); reg 1014 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c value = malidp_read32(reg, BLK_INFO); reg 1026 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32_mask(c->reg, BLK_CONTROL, BS_CTRL_EN, 0); reg 1034 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c u32 __iomem *reg = c->reg; reg 1049 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BS_ACTIVESIZE, HV_SIZE(hactive, vactive)); reg 1050 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BS_HINTERVALS, BS_H_INTVALS(hfront_porch, reg 1052 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BS_VINTERVALS, BS_V_INTVALS(vfront_porch, reg 1058 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BS_SYNC, value); reg 1060 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BS_PROG_LINE, D71_DEFAULT_PREPRETCH_LINE - 1); reg 1061 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BS_PREFETCH_LINE, D71_DEFAULT_PREPRETCH_LINE); reg 1066 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BS_DRIFT_TO, hfront_porch + 16); reg 1070 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32(reg, BLK_CONTROL, value); reg 1078 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c dump_block_header(sf, c->reg); reg 1080 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0xC0, 1, v); reg 1083 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0xD0, 8, v); reg 1093 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0x100, 3, v); reg 1098 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0x110, 3, v); reg 1102 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c get_values_from_reg(c->reg, 0x120, 5, v); reg 1117 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c struct block_header *blk, u32 __iomem *reg) reg 1130 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c BS_NUM_OUTPUT_IDS, reg, "DOU%d_BS", pipe_id); reg 1144 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c struct block_header *blk, u32 __iomem *reg) reg 1157 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c pipe->lpu_addr = reg; reg 1161 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c err = d71_layer_init(d71, blk, reg); reg 1165 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c err = d71_wb_layer_init(d71, blk, reg); reg 1170 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c pipe->cu_addr = reg; reg 1171 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c err = d71_compiz_init(d71, blk, reg); reg 1175 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c err = d71_scaler_init(d71, blk, reg); reg 1179 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c err = d71_splitter_init(d71, blk, reg); reg 1183 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c err = d71_merger_init(d71, blk, reg); reg 1188 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c pipe->dou_addr = reg; reg 1192 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c err = d71_improc_init(d71, blk, reg); reg 1197 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c pipe->dou_ft_coeff_addr = reg; reg 1201 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c err = d71_timing_ctrlr_init(d71, blk, reg); reg 1208 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c d71->glb_scl_coeff_addr[blk_id] = reg; reg 14 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c u32 __iomem *reg = d71_pipeline->lpu_addr; reg 18 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS); reg 27 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c status = malidp_read32(reg, BLK_STATUS); reg 49 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32_mask(reg, BLK_STATUS, restore, 0); reg 53 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c tbu_status = malidp_read32(reg, LPU_TBU_STATUS); reg 75 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32_mask(reg, LPU_TBU_STATUS, restore, 0); reg 78 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32(reg, BLK_IRQ_CLEAR, raw_status); reg 84 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c u32 __iomem *reg = d71_pipeline->cu_addr; reg 88 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS); reg 93 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c status = malidp_read32(reg, BLK_STATUS) & 0x7FFFFFFF; reg 101 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32_mask(reg, BLK_STATUS, status, 0); reg 104 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32(reg, BLK_IRQ_CLEAR, raw_status); reg 111 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c u32 __iomem *reg = d71_pipeline->dou_addr; reg 115 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS); reg 124 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c status = malidp_read32(reg, BLK_STATUS); reg 143 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32_mask(reg, BLK_STATUS, restore, 0); reg 146 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32(reg, BLK_IRQ_CLEAR, raw_status); reg 310 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c void d71_read_block_header(u32 __iomem *reg, struct block_header *blk) reg 314 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c blk->block_info = malidp_read32(reg, BLK_BLOCK_INFO); reg 318 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c blk->pipeline_info = malidp_read32(reg, BLK_PIPELINE_INFO); reg 322 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c blk->input_ids[i] = malidp_read32(reg + i, BLK_VALID_INPUT_ID0); reg 324 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c blk->output_ids[i] = malidp_read32(reg + i, BLK_OUTPUT_ID0); reg 519 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c u32 __iomem *reg = d71->gcu_addr; reg 527 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32_mask(reg, BLK_CONTROL, 0x7, TBU_CONNECT_MODE); reg 529 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c ret = dp_wait_cond(has_bits(check_bits, malidp_read32(reg, BLK_STATUS)), reg 533 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32_mask(reg, BLK_CONTROL, 0x7, INACTIVE_MODE); reg 546 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c u32 __iomem *reg = d71->gcu_addr; reg 551 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32_mask(reg, BLK_CONTROL, 0x7, TBU_DISCONNECT_MODE); reg 553 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c ret = dp_wait_cond(((malidp_read32(reg, BLK_STATUS) & check_bits) == 0), reg 557 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c malidp_write32_mask(reg, BLK_CONTROL, 0x7, INACTIVE_MODE); reg 49 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.h struct block_header *blk, u32 __iomem *reg); reg 50 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.h void d71_read_block_header(u32 __iomem *reg, struct block_header *blk); reg 185 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define FROM_AXIEID(reg) ((reg) & AXIEID_MASK) reg 187 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define FROM_AXIRP(reg) (((reg) & AXIRP_MASK) >> 5) reg 188 drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h #define FROM_AXIWP(reg) (((reg) & AXIWP_MASK) >> 6) reg 63 drivers/gpu/drm/arm/display/komeda/komeda_dev.h const struct komeda_dev_funcs *(*identify)(u32 __iomem *reg, reg 203 drivers/gpu/drm/arm/display/komeda/komeda_dev.h d71_identify(u32 __iomem *reg, struct komeda_chip_info *chip); reg 163 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c u8 max_active_outputs, u32 __iomem *reg, reg 202 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c c->reg = reg; reg 90 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h u32 __iomem *reg; reg 491 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h u8 max_active_outputs, u32 __iomem *reg, reg 25 drivers/gpu/drm/arm/hdlcd_drv.h unsigned int reg, u32 value) reg 27 drivers/gpu/drm/arm/hdlcd_drv.h writel(value, hdlcd->mmio + reg); reg 30 drivers/gpu/drm/arm/hdlcd_drv.h static inline u32 hdlcd_read(struct hdlcd_drm_private *hdlcd, unsigned int reg) reg 32 drivers/gpu/drm/arm/hdlcd_drv.h return readl(hdlcd->mmio + reg); reg 256 drivers/gpu/drm/arm/malidp_hw.h static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg) reg 259 drivers/gpu/drm/arm/malidp_hw.h return readl(hwdev->regs + reg); reg 263 drivers/gpu/drm/arm/malidp_hw.h u32 value, u32 reg) reg 266 drivers/gpu/drm/arm/malidp_hw.h writel(value, hwdev->regs + reg); reg 270 drivers/gpu/drm/arm/malidp_hw.h u32 mask, u32 reg) reg 272 drivers/gpu/drm/arm/malidp_hw.h u32 data = malidp_hw_read(hwdev, reg); reg 275 drivers/gpu/drm/arm/malidp_hw.h malidp_hw_write(hwdev, data, reg); reg 279 drivers/gpu/drm/arm/malidp_hw.h u32 mask, u32 reg) reg 281 drivers/gpu/drm/arm/malidp_hw.h u32 data = malidp_hw_read(hwdev, reg); reg 284 drivers/gpu/drm/arm/malidp_hw.h malidp_hw_write(hwdev, data, reg); reg 85 drivers/gpu/drm/armada/armada_crtc.c void __iomem *reg = dcrtc->base + regs->offset; reg 90 drivers/gpu/drm/armada/armada_crtc.c val &= readl_relaxed(reg); reg 91 drivers/gpu/drm/armada/armada_crtc.c writel_relaxed(val | regs->val, reg); reg 55 drivers/gpu/drm/armada/armada_debugfs.c unsigned long reg, mask, val; reg 71 drivers/gpu/drm/armada/armada_debugfs.c if (sscanf(buf, "%lx %lx %lx", ®, &mask, &val) != 3) reg 73 drivers/gpu/drm/armada/armada_debugfs.c if (reg < 0x84 || reg > 0x1c4 || reg & 3) reg 77 drivers/gpu/drm/armada/armada_debugfs.c v = readl(dcrtc->base + reg); reg 80 drivers/gpu/drm/armada/armada_debugfs.c writel(v, dcrtc->base + reg); reg 195 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c u32 reg = readl(priv->base + CRT_CTRL1); reg 198 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(reg | CRT_CTRL_VERTICAL_INTR_STS, priv->base + CRT_CTRL1); reg 200 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c reg |= CRT_CTRL_VERTICAL_INTR_EN; reg 201 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(reg, priv->base + CRT_CTRL1); reg 209 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c u32 reg = readl(priv->base + CRT_CTRL1); reg 211 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c reg &= ~CRT_CTRL_VERTICAL_INTR_EN; reg 212 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(reg, priv->base + CRT_CTRL1); reg 215 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c writel(reg | CRT_CTRL_VERTICAL_INTR_STS, priv->base + CRT_CTRL1); reg 81 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c u32 reg; reg 83 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c reg = readl(priv->base + CRT_CTRL1); reg 85 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c if (reg & CRT_CTRL_VERTICAL_INTR_STS) { reg 87 drivers/gpu/drm/aspeed/aspeed_gfx_drv.c writel(reg, priv->base + CRT_CTRL1); reg 135 drivers/gpu/drm/ast/ast_drv.h static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \ reg 137 drivers/gpu/drm/ast/ast_drv.h val = ioread##x(ast->regs + reg); \ reg 146 drivers/gpu/drm/ast/ast_drv.h static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \ reg 148 drivers/gpu/drm/ast/ast_drv.h val = ioread##x(ast->ioregs + reg); \ reg 157 drivers/gpu/drm/ast/ast_drv.h static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\ reg 158 drivers/gpu/drm/ast/ast_drv.h iowrite##x(val, ast->regs + reg);\ reg 166 drivers/gpu/drm/ast/ast_drv.h static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\ reg 167 drivers/gpu/drm/ast/ast_drv.h iowrite##x(val, ast->ioregs + reg);\ reg 78 drivers/gpu/drm/ast/ast_post.c u8 i, index, reg; reg 109 drivers/gpu/drm/ast/ast_post.c reg = 0x04; reg 112 drivers/gpu/drm/ast/ast_post.c reg |= 0x20; reg 113 drivers/gpu/drm/ast/ast_post.c ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg); reg 372 drivers/gpu/drm/ast/ast_post.c u32 reg; reg 375 drivers/gpu/drm/ast/ast_post.c pci_read_config_dword(ast->dev->pdev, 0x04, ®); reg 376 drivers/gpu/drm/ast/ast_post.c reg |= 0x3; reg 377 drivers/gpu/drm/ast/ast_post.c pci_write_config_dword(ast->dev->pdev, 0x04, reg); reg 1606 drivers/gpu/drm/ast/ast_post.c u8 reg; reg 1608 drivers/gpu/drm/ast/ast_post.c reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); reg 1609 drivers/gpu/drm/ast/ast_post.c if ((reg & 0x80) == 0) {/* vga only */ reg 1680 drivers/gpu/drm/ast/ast_post.c reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); reg 1681 drivers/gpu/drm/ast/ast_post.c } while ((reg & 0x40) == 0); reg 2037 drivers/gpu/drm/ast/ast_post.c u8 reg; reg 2039 drivers/gpu/drm/ast/ast_post.c reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); reg 2040 drivers/gpu/drm/ast/ast_post.c if ((reg & 0x80) == 0) {/* vga only */ reg 2082 drivers/gpu/drm/ast/ast_post.c reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); reg 2083 drivers/gpu/drm/ast/ast_post.c } while ((reg & 0x40) == 0); reg 359 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h unsigned int reg, u32 val) reg 361 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h regmap_write(layer->regmap, layer->desc->regs_offset + reg, val); reg 365 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h unsigned int reg) reg 369 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h regmap_read(layer->regmap, layer->desc->regs_offset + reg, &val); reg 26 drivers/gpu/drm/bochs/bochs_hw.c static u16 bochs_dispi_read(struct bochs_device *bochs, u16 reg) reg 31 drivers/gpu/drm/bochs/bochs_hw.c int offset = 0x500 + (reg << 1); reg 34 drivers/gpu/drm/bochs/bochs_hw.c outw(reg, VBE_DISPI_IOPORT_INDEX); reg 40 drivers/gpu/drm/bochs/bochs_hw.c static void bochs_dispi_write(struct bochs_device *bochs, u16 reg, u16 val) reg 43 drivers/gpu/drm/bochs/bochs_hw.c int offset = 0x500 + (reg << 1); reg 46 drivers/gpu/drm/bochs/bochs_hw.c outw(reg, VBE_DISPI_IOPORT_INDEX); reg 77 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c static bool adv7511_register_volatile(struct device *dev, unsigned int reg) reg 79 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c switch (reg) { reg 950 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c static bool adv7511_cec_register_volatile(struct device *dev, unsigned int reg) reg 956 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c reg -= ADV7533_REG_CEC_OFFSET; reg 958 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c switch (reg) { reg 92 drivers/gpu/drm/bridge/analogix-anx78xx.c static int anx78xx_set_bits(struct regmap *map, u8 reg, u8 mask) reg 94 drivers/gpu/drm/bridge/analogix-anx78xx.c return regmap_update_bits(map, reg, mask, mask); reg 97 drivers/gpu/drm/bridge/analogix-anx78xx.c static int anx78xx_clear_bits(struct regmap *map, u8 reg, u8 mask) reg 99 drivers/gpu/drm/bridge/analogix-anx78xx.c return regmap_update_bits(map, reg, mask, 0); reg 410 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c u32 reg; reg 414 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c reg = analogix_dp_get_lane0_link_training(dp); reg 417 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c reg = analogix_dp_get_lane1_link_training(dp); reg 420 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c reg = analogix_dp_get_lane2_link_training(dp); reg 423 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c reg = analogix_dp_get_lane3_link_training(dp); reg 430 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c return reg; reg 540 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c u32 reg; reg 575 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c analogix_dp_get_link_bandwidth(dp, ®); reg 576 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.link_rate = reg; reg 580 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c analogix_dp_get_lane_count(dp, ®); reg 581 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lane_count = reg; reg 28 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 31 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); reg 32 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= HDCP_VIDEO_MUTE; reg 33 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); reg 35 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); reg 36 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~HDCP_VIDEO_MUTE; reg 37 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); reg 43 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 45 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); reg 46 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~VIDEO_EN; reg 47 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); reg 52 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 55 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | reg 58 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | reg 61 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); reg 66 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 68 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = TX_TERMINAL_CTRL_50_OHM; reg 69 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); reg 71 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = SEL_24M | TX_DVDD_BIT_1_0625V; reg 72 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); reg 75 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = REF_CLK_24M; reg 77 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg ^= REF_CLK_MASK; reg 79 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1); reg 86 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; reg 87 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3); reg 89 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | reg 91 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1); reg 93 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = CH3_AMP_400_MV | CH2_AMP_400_MV | reg 95 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL); reg 120 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 126 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N | reg 129 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | reg 133 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); reg 135 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | reg 138 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); reg 175 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 178 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = COMMON_INT_MASK_1; reg 179 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1); reg 181 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = COMMON_INT_MASK_2; reg 182 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2); reg 184 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = COMMON_INT_MASK_3; reg 185 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3); reg 187 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = COMMON_INT_MASK_4; reg 188 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); reg 190 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = INT_STA_MASK; reg 191 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); reg 196 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 199 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); reg 200 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~COMMON_INT_MASK_4; reg 201 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); reg 203 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK); reg 204 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~INT_STA_MASK; reg 205 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); reg 210 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 213 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = COMMON_INT_MASK_4; reg 214 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); reg 216 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = INT_STA_MASK; reg 217 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); reg 222 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 224 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); reg 225 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c if (reg & PLL_LOCK) reg 233 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 242 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + pd_addr); reg 244 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= mask; reg 246 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~mask; reg 247 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + pd_addr); reg 254 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 268 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + phy_pd_addr); reg 270 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= mask; reg 272 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~mask; reg 273 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + phy_pd_addr); reg 277 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + phy_pd_addr); reg 280 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= mask; reg 282 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~mask; reg 283 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + phy_pd_addr); reg 287 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + phy_pd_addr); reg 290 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= mask; reg 292 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~mask; reg 293 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + phy_pd_addr); reg 297 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + phy_pd_addr); reg 300 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= mask; reg 302 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~mask; reg 303 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + phy_pd_addr); reg 307 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + phy_pd_addr); reg 310 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= mask; reg 312 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~mask; reg 313 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + phy_pd_addr); reg 326 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + phy_pd_addr); reg 328 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= mask; reg 330 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~mask; reg 332 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + phy_pd_addr); reg 338 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = DP_ALL_PD; reg 339 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + phy_pd_addr); reg 341 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = DP_ALL_PD; reg 342 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + phy_pd_addr); reg 344 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~DP_INC_BG; reg 345 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + phy_pd_addr); reg 358 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 363 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = PLL_LOCK_CHG; reg 364 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); reg 366 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); reg 367 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); reg 368 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL); reg 385 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); reg 386 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N reg 388 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); reg 394 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 399 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = HOTPLUG_CHG | HPD_LOST | PLUG; reg 400 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); reg 402 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = INT_HPD; reg 403 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); reg 408 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 415 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg 416 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~(F_HPD | HPD_CTRL); reg 417 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg 422 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 424 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg 425 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = (F_HPD | HPD_CTRL); reg 426 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg 431 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 434 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = gpiod_get_value(dp->hpd_gpiod); reg 435 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c if (reg) reg 441 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); reg 443 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c if (reg & PLUG) reg 446 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c if (reg & HPD_LOST) reg 449 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c if (reg & HOTPLUG_CHG) reg 458 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 461 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); reg 462 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= AUX_FUNC_EN_N; reg 463 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); reg 468 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 471 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = RPLY_RECEIV | AUX_ERR; reg 472 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); reg 482 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = 0; reg 484 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3); reg 487 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= AUX_HW_RETRY_COUNT_SEL(0) | reg 490 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL); reg 493 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = DEFER_CTRL_EN | DEFER_COUNT(1); reg 494 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL); reg 497 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); reg 498 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~AUX_FUNC_EN_N; reg 499 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); reg 504 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 510 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg 511 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c if (reg & HPD_STATUS) reg 520 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 522 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); reg 523 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~SW_FUNC_EN_N; reg 524 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); reg 529 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c int reg; reg 534 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); reg 535 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= AUX_EN; reg 536 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); reg 539 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); reg 540 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c while (!(reg & RPLY_RECEIV)) { reg 546 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); reg 554 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); reg 555 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c if (reg & AUX_ERR) { reg 561 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA); reg 562 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c if ((reg & AUX_STATUS_MASK) != 0) { reg 564 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg & AUX_STATUS_MASK); reg 575 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 581 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = BUF_CLR; reg 582 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); reg 585 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = AUX_ADDR_7_0(reg_addr); reg 586 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); reg 587 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = AUX_ADDR_15_8(reg_addr); reg 588 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); reg 589 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = AUX_ADDR_19_16(reg_addr); reg 590 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); reg 593 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = (unsigned int)data; reg 594 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0); reg 601 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; reg 602 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); reg 617 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 619 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = bwtype; reg 621 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET); reg 626 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 628 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET); reg 629 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c *bwtype = reg; reg 634 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 636 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = count; reg 637 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); reg 642 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); reg 645 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c *count = reg; reg 651 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 654 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); reg 655 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= ENHANCED; reg 656 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); reg 658 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); reg 659 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~ENHANCED; reg 660 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); reg 667 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 671 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; reg 672 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); reg 675 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; reg 676 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); reg 679 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; reg 680 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); reg 683 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; reg 684 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); reg 687 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = SCRAMBLING_ENABLE | reg 690 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); reg 700 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 702 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); reg 703 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~PRE_EMPHASIS_SET_MASK; reg 704 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= level << PRE_EMPHASIS_SET_SHIFT; reg 705 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); reg 711 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 713 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); reg 714 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~PRE_EMPHASIS_SET_MASK; reg 715 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= level << PRE_EMPHASIS_SET_SHIFT; reg 716 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); reg 722 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 724 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); reg 725 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~PRE_EMPHASIS_SET_MASK; reg 726 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= level << PRE_EMPHASIS_SET_SHIFT; reg 727 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); reg 733 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 735 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); reg 736 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~PRE_EMPHASIS_SET_MASK; reg 737 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= level << PRE_EMPHASIS_SET_SHIFT; reg 738 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); reg 744 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 746 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = training_lane; reg 747 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); reg 753 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 755 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = training_lane; reg 756 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); reg 762 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 764 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = training_lane; reg 765 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); reg 771 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 773 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = training_lane; reg 774 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); reg 799 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 801 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST); reg 802 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= MACRO_RST; reg 803 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); reg 808 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~MACRO_RST; reg 809 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); reg 814 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 816 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; reg 817 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); reg 819 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = 0x0; reg 820 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); reg 822 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = CHA_CRI(4) | CHA_CTRL; reg 823 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); reg 825 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = 0x0; reg 826 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg 828 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = VID_HRES_TH(2) | VID_VRES_TH(0); reg 829 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8); reg 834 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 837 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) | reg 840 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2); reg 843 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); reg 844 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~IN_YC_COEFFI_MASK; reg 846 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= IN_YC_COEFFI_ITU709; reg 848 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= IN_YC_COEFFI_ITU601; reg 849 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); reg 854 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 856 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); reg 857 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); reg 859 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); reg 861 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c if (!(reg & DET_STA)) { reg 866 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); reg 867 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); reg 869 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); reg 872 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c if (reg & CHA_STA) { reg 884 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 887 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); reg 888 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= FIX_M_VID; reg 889 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); reg 890 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = m_value & 0xff; reg 891 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0); reg 892 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = (m_value >> 8) & 0xff; reg 893 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1); reg 894 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = (m_value >> 16) & 0xff; reg 895 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2); reg 897 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = n_value & 0xff; reg 898 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0); reg 899 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = (n_value >> 8) & 0xff; reg 900 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1); reg 901 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = (n_value >> 16) & 0xff; reg 902 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2); reg 904 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); reg 905 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~FIX_M_VID; reg 906 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); reg 916 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 919 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg 920 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~FORMAT_SEL; reg 921 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg 923 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg 924 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= FORMAT_SEL; reg 925 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg 931 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 934 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); reg 935 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~VIDEO_MODE_MASK; reg 936 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; reg 937 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); reg 939 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); reg 940 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~VIDEO_MODE_MASK; reg 941 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= VIDEO_MODE_SLAVE_MODE; reg 942 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); reg 948 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 950 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); reg 951 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= VIDEO_EN; reg 952 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); reg 957 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 959 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg 960 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg 962 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); reg 963 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c if (!(reg & STRM_VALID)) { reg 973 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 975 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); reg 977 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~(RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N); reg 979 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N); reg 980 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= MASTER_VID_FUNC_EN_N; reg 982 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); reg 984 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg 985 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~INTERACE_SCAN_CFG; reg 986 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= (dp->video_info.interlaced << 2); reg 987 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg 989 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg 990 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~VSYNC_POLARITY_CFG; reg 991 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= (dp->video_info.v_sync_polarity << 1); reg 992 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg 994 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg 995 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~HSYNC_POLARITY_CFG; reg 996 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= (dp->video_info.h_sync_polarity << 0); reg 997 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg 999 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; reg 1000 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); reg 1005 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 1007 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); reg 1008 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~SCRAMBLING_DISABLE; reg 1009 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); reg 1014 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 1016 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); reg 1017 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= SCRAMBLING_DISABLE; reg 1018 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); reg 1104 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 reg; reg 1116 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = BUF_CLR; reg 1117 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); reg 1121 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = AUX_TX_COMM_WRITE | AUX_TX_COMM_I2C_TRANSACTION; reg 1123 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= AUX_TX_COMM_MOT; reg 1127 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = AUX_TX_COMM_READ | AUX_TX_COMM_I2C_TRANSACTION; reg 1129 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= AUX_TX_COMM_MOT; reg 1133 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = AUX_TX_COMM_WRITE | AUX_TX_COMM_DP_TRANSACTION; reg 1137 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = AUX_TX_COMM_READ | AUX_TX_COMM_DP_TRANSACTION; reg 1144 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= AUX_LENGTH(msg->size); reg 1145 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); reg 1148 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = AUX_ADDR_7_0(msg->address); reg 1149 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); reg 1150 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = AUX_ADDR_15_8(msg->address); reg 1151 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); reg 1152 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = AUX_ADDR_19_16(msg->address); reg 1153 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); reg 1157 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = buffer[i]; reg 1158 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0 + reg 1165 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = AUX_EN; reg 1169 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= ADDR_ONLY; reg 1171 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); reg 1174 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg, !(reg & AUX_EN), 25, 500 * 1000); reg 1183 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg, reg & RPLY_RECEIV, 10, 20 * 1000); reg 1193 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); reg 1195 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c if ((reg & AUX_ERR) || (status_reg & AUX_STATUS_MASK)) { reg 1199 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c status_reg & AUX_STATUS_MASK, !!(reg & AUX_ERR)); reg 1205 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 + reg 1207 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c buffer[i] = (unsigned char)reg; reg 1213 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM); reg 1214 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c if (reg == AUX_RX_COMM_AUX_DEFER) reg 1216 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c else if (reg == AUX_RX_COMM_I2C_DEFER) reg 72 drivers/gpu/drm/bridge/parade-ps8622.c static int ps8622_set(struct i2c_client *client, u8 page, u8 reg, u8 val) reg 77 drivers/gpu/drm/bridge/parade-ps8622.c u8 data[] = {reg, val}; reg 87 drivers/gpu/drm/bridge/parade-ps8622.c client->addr + page, reg, val, ret); reg 182 drivers/gpu/drm/bridge/sii902x.c static int sii902x_read_unlocked(struct i2c_client *i2c, u8 reg, u8 *val) reg 188 drivers/gpu/drm/bridge/sii902x.c I2C_SMBUS_READ, reg, I2C_SMBUS_BYTE_DATA, &data); reg 197 drivers/gpu/drm/bridge/sii902x.c static int sii902x_write_unlocked(struct i2c_client *i2c, u8 reg, u8 val) reg 204 drivers/gpu/drm/bridge/sii902x.c I2C_SMBUS_WRITE, reg, I2C_SMBUS_BYTE_DATA, reg 208 drivers/gpu/drm/bridge/sii902x.c static int sii902x_update_bits_unlocked(struct i2c_client *i2c, u8 reg, u8 mask, reg 214 drivers/gpu/drm/bridge/sii902x.c ret = sii902x_read_unlocked(i2c, reg, &status); reg 219 drivers/gpu/drm/bridge/sii902x.c return sii902x_write_unlocked(i2c, reg, status); reg 112 drivers/gpu/drm/bridge/sil-sii8620.c u8 reg[4]; reg 353 drivers/gpu/drm/bridge/sil-sii8620.c if (msg->reg[0] == MHL_SET_INT && reg 354 drivers/gpu/drm/bridge/sil-sii8620.c msg->reg[1] == MHL_INT_REG(RCHANGE) && reg 355 drivers/gpu/drm/bridge/sil-sii8620.c msg->reg[2] == MHL_INT_RC_FEAT_REQ) reg 360 drivers/gpu/drm/bridge/sil-sii8620.c switch (msg->reg[0]) { reg 363 drivers/gpu/drm/bridge/sil-sii8620.c sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg + 1, 2); reg 368 drivers/gpu/drm/bridge/sil-sii8620.c sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg, 3); reg 374 drivers/gpu/drm/bridge/sil-sii8620.c sii8620_write(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg[1]); reg 380 drivers/gpu/drm/bridge/sil-sii8620.c msg->reg[0]); reg 418 drivers/gpu/drm/bridge/sil-sii8620.c msg->reg[0] = cmd; reg 419 drivers/gpu/drm/bridge/sil-sii8620.c msg->reg[1] = arg1; reg 420 drivers/gpu/drm/bridge/sil-sii8620.c msg->reg[2] = arg2; reg 424 drivers/gpu/drm/bridge/sil-sii8620.c static void sii8620_mt_write_stat(struct sii8620 *ctx, u8 reg, u8 val) reg 426 drivers/gpu/drm/bridge/sil-sii8620.c sii8620_mt_msc_cmd(ctx, MHL_WRITE_STAT, reg, val); reg 461 drivers/gpu/drm/bridge/sil-sii8620.c if (msg->reg[0] == MHL_READ_XDEVCAP) reg 545 drivers/gpu/drm/bridge/sil-sii8620.c if (msg->reg[0] == MHL_READ_XDEVCAP) reg 555 drivers/gpu/drm/bridge/sil-sii8620.c if (msg->reg[0] == MHL_READ_XDEVCAP) reg 568 drivers/gpu/drm/bridge/sil-sii8620.c msg->reg[0] = xdevcap ? MHL_READ_XDEVCAP : MHL_READ_DEVCAP; reg 576 drivers/gpu/drm/bridge/sil-sii8620.c u8 reg = msg->reg[1] & 0x7f; reg 578 drivers/gpu/drm/bridge/sil-sii8620.c if (msg->reg[1] & 0x80) reg 579 drivers/gpu/drm/bridge/sil-sii8620.c ctx->xdevcap[reg] = msg->ret; reg 581 drivers/gpu/drm/bridge/sil-sii8620.c ctx->devcap[reg] = msg->ret; reg 584 drivers/gpu/drm/bridge/sil-sii8620.c static void sii8620_mt_read_devcap_reg(struct sii8620 *ctx, u8 reg) reg 591 drivers/gpu/drm/bridge/sil-sii8620.c msg->reg[0] = (reg & 0x80) ? MHL_READ_XDEVCAP_REG : MHL_READ_DEVCAP_REG; reg 592 drivers/gpu/drm/bridge/sil-sii8620.c msg->reg[1] = reg; reg 597 drivers/gpu/drm/bridge/sil-sii8620.c static inline void sii8620_mt_read_xdevcap_reg(struct sii8620 *ctx, u8 reg) reg 599 drivers/gpu/drm/bridge/sil-sii8620.c sii8620_mt_read_devcap_reg(ctx, reg | 0x80); reg 1402 drivers/gpu/drm/bridge/sil-sii8620.c u8 reg; reg 1410 drivers/gpu/drm/bridge/sil-sii8620.c reg = sii8620_readb(ctx, REG_EMSCINTR); reg 1411 drivers/gpu/drm/bridge/sil-sii8620.c sii8620_write(ctx, REG_EMSCINTR, reg); reg 219 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) reg 221 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); reg 224 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, reg 227 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi_modb(hdmi, data << shift, mask, reg); reg 283 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) reg 285 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c writel(val, dsi->base + reg); reg 288 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) reg 290 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c return readl(dsi->base + reg); reg 434 drivers/gpu/drm/bridge/tc358767.c u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B; reg 437 drivers/gpu/drm/bridge/tc358767.c reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */ reg 439 drivers/gpu/drm/bridge/tc358767.c reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */ reg 441 drivers/gpu/drm/bridge/tc358767.c reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */ reg 443 drivers/gpu/drm/bridge/tc358767.c reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */ reg 444 drivers/gpu/drm/bridge/tc358767.c return reg; reg 666 drivers/gpu/drm/bridge/tc358767.c u8 reg; reg 682 drivers/gpu/drm/bridge/tc358767.c ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®); reg 685 drivers/gpu/drm/bridge/tc358767.c tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5; reg 687 drivers/gpu/drm/bridge/tc358767.c ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®); reg 693 drivers/gpu/drm/bridge/tc358767.c ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®); reg 696 drivers/gpu/drm/bridge/tc358767.c tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; reg 1435 drivers/gpu/drm/bridge/tc358767.c static bool tc_readable_reg(struct device *dev, unsigned int reg) reg 1437 drivers/gpu/drm/bridge/tc358767.c return reg != SYSCTRL; reg 1455 drivers/gpu/drm/bridge/tc358767.c static bool tc_writeable_reg(struct device *dev, unsigned int reg) reg 1457 drivers/gpu/drm/bridge/tc358767.c return (reg != TC_IDREG) && reg 1458 drivers/gpu/drm/bridge/tc358767.c (reg != DP0_LTSTAT) && reg 1459 drivers/gpu/drm/bridge/tc358767.c (reg != DP0_SNKLTCHGREQ); reg 121 drivers/gpu/drm/bridge/ti-sn65dsi86.c unsigned int reg, u16 val) reg 123 drivers/gpu/drm/bridge/ti-sn65dsi86.c regmap_write(pdata->regmap, reg, val & 0xFF); reg 124 drivers/gpu/drm/bridge/ti-sn65dsi86.c regmap_write(pdata->regmap, reg + 1, val >> 8); reg 164 drivers/gpu/drm/bridge/ti-sn65dsi86.c unsigned int reg, val; reg 171 drivers/gpu/drm/bridge/ti-sn65dsi86.c for (reg = 0xf0; reg <= 0xf8; reg++) { reg 172 drivers/gpu/drm/bridge/ti-sn65dsi86.c regmap_read(pdata->regmap, reg, &val); reg 173 drivers/gpu/drm/bridge/ti-sn65dsi86.c seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val); reg 425 drivers/gpu/drm/bridge/ti-tfp410.c int reg; reg 428 drivers/gpu/drm/bridge/ti-tfp410.c of_property_read_u32(client->dev.of_node, "reg", ®)) { reg 75 drivers/gpu/drm/cirrus/cirrus.c static u8 rreg_seq(struct cirrus_device *cirrus, u8 reg) reg 77 drivers/gpu/drm/cirrus/cirrus.c iowrite8(reg, cirrus->mmio + SEQ_INDEX); reg 81 drivers/gpu/drm/cirrus/cirrus.c static void wreg_seq(struct cirrus_device *cirrus, u8 reg, u8 val) reg 83 drivers/gpu/drm/cirrus/cirrus.c iowrite8(reg, cirrus->mmio + SEQ_INDEX); reg 90 drivers/gpu/drm/cirrus/cirrus.c static u8 rreg_crt(struct cirrus_device *cirrus, u8 reg) reg 92 drivers/gpu/drm/cirrus/cirrus.c iowrite8(reg, cirrus->mmio + CRT_INDEX); reg 96 drivers/gpu/drm/cirrus/cirrus.c static void wreg_crt(struct cirrus_device *cirrus, u8 reg, u8 val) reg 98 drivers/gpu/drm/cirrus/cirrus.c iowrite8(reg, cirrus->mmio + CRT_INDEX); reg 105 drivers/gpu/drm/cirrus/cirrus.c static void wreg_gfx(struct cirrus_device *cirrus, u8 reg, u8 val) reg 107 drivers/gpu/drm/cirrus/cirrus.c iowrite8(reg, cirrus->mmio + GFX_INDEX); reg 36 drivers/gpu/drm/cirrus/cirrus_drv.h #define RREG8(reg) ioread8(((void __iomem *)cdev->rmmio) + (reg)) reg 37 drivers/gpu/drm/cirrus/cirrus_drv.h #define WREG8(reg, v) iowrite8(v, ((void __iomem *)cdev->rmmio) + (reg)) reg 38 drivers/gpu/drm/cirrus/cirrus_drv.h #define RREG32(reg) ioread32(((void __iomem *)cdev->rmmio) + (reg)) reg 39 drivers/gpu/drm/cirrus/cirrus_drv.h #define WREG32(reg, v) iowrite32(v, ((void __iomem *)cdev->rmmio) + (reg)) reg 44 drivers/gpu/drm/cirrus/cirrus_drv.h #define WREG_SEQ(reg, v) \ reg 46 drivers/gpu/drm/cirrus/cirrus_drv.h WREG8(SEQ_INDEX, reg); \ reg 53 drivers/gpu/drm/cirrus/cirrus_drv.h #define WREG_CRT(reg, v) \ reg 55 drivers/gpu/drm/cirrus/cirrus_drv.h WREG8(CRT_INDEX, reg); \ reg 62 drivers/gpu/drm/cirrus/cirrus_drv.h #define WREG_GFX(reg, v) \ reg 64 drivers/gpu/drm/cirrus/cirrus_drv.h WREG8(GFX_INDEX, reg); \ reg 160 drivers/gpu/drm/drm_mipi_dsi.c u32 reg; reg 167 drivers/gpu/drm/drm_mipi_dsi.c ret = of_property_read_u32(node, "reg", ®); reg 174 drivers/gpu/drm/drm_mipi_dsi.c info.channel = reg; reg 35 drivers/gpu/drm/etnaviv/etnaviv_buffer.c u32 reg, u32 value) reg 37 drivers/gpu/drm/etnaviv/etnaviv_buffer.c u32 index = reg >> VIV_FE_LOAD_STATE_HEADER_OFFSET__SHR; reg 84 drivers/gpu/drm/etnaviv/etnaviv_dump.c struct etnaviv_dump_registers *reg = iter->data; reg 87 drivers/gpu/drm/etnaviv/etnaviv_dump.c for (i = 0; i < ARRAY_SIZE(etnaviv_dump_registers); i++, reg++) { reg 88 drivers/gpu/drm/etnaviv/etnaviv_dump.c reg->reg = etnaviv_dump_registers[i]; reg 89 drivers/gpu/drm/etnaviv/etnaviv_dump.c reg->value = gpu_read(gpu, etnaviv_dump_registers[i]); reg 92 drivers/gpu/drm/etnaviv/etnaviv_dump.c etnaviv_core_dump_header(iter, ETDUMP_BUF_REG, reg); reg 33 drivers/gpu/drm/etnaviv/etnaviv_dump.h __le32 reg; reg 150 drivers/gpu/drm/etnaviv/etnaviv_gpu.h static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) reg 152 drivers/gpu/drm/etnaviv/etnaviv_gpu.h writel(data, gpu->mmio + reg); reg 155 drivers/gpu/drm/etnaviv/etnaviv_gpu.h static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) reg 157 drivers/gpu/drm/etnaviv/etnaviv_gpu.h return readl(gpu->mmio + reg); reg 77 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c u32 reg = VIVS_HI_PROFILE_TOTAL_CYCLES; reg 82 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c reg = VIVS_MC_PROFILE_CYCLE_COUNTER; reg 84 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c return gpu_read(gpu, reg); reg 91 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c u32 reg = VIVS_HI_PROFILE_IDLE_CYCLES; reg 96 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c reg = VIVS_HI_PROFILE_TOTAL_CYCLES; reg 98 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c return gpu_read(gpu, reg); reg 95 drivers/gpu/drm/exynos/exynos5433_drm_decon.c static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, reg 98 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = (val & mask) | (readl(ctx->addr + reg) & ~mask); reg 99 drivers/gpu/drm/exynos/exynos5433_drm_decon.c writel(val, ctx->addr + reg); reg 602 drivers/gpu/drm/exynos/exynos_drm_dsi.c u32 reg; reg 616 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); reg 633 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_FREQ_BAND(band); reg 636 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); reg 644 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); reg 645 drivers/gpu/drm/exynos/exynos_drm_dsi.c } while ((reg & DSIM_PLL_STABLE) == 0); reg 654 drivers/gpu/drm/exynos/exynos_drm_dsi.c u32 reg; reg 674 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); reg 675 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK reg 678 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN reg 684 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); reg 693 drivers/gpu/drm/exynos/exynos_drm_dsi.c u32 reg; reg 699 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | reg 701 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg); reg 708 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; reg 709 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg); reg 724 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = reg_values[PHYTIMING_CLK_PREPARE] | reg 729 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg); reg 740 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | reg 742 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg); reg 747 drivers/gpu/drm/exynos/exynos_drm_dsi.c u32 reg; reg 749 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); reg 750 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK reg 752 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); reg 754 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG); reg 755 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg &= ~DSIM_PLL_EN; reg 756 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); reg 761 drivers/gpu/drm/exynos/exynos_drm_dsi.c u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG); reg 762 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | reg 764 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); reg 771 drivers/gpu/drm/exynos/exynos_drm_dsi.c u32 reg; reg 775 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); reg 776 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg &= ~0x1f; reg 777 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); reg 781 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= 0x1f; reg 782 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); reg 786 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = 0; reg 794 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_VIDEO_MODE; reg 801 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_MFLUSH_VS; reg 803 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_SYNC_INFORM; reg 805 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_BURST_MODE; reg 807 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_AUTO_MODE; reg 809 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_HSE_MODE; reg 811 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_HFP_MODE; reg 813 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_HBP_MODE; reg 815 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_HSA_MODE; reg 819 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_EOT_DISABLE; reg 823 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_MAIN_PIX_FORMAT_RGB888; reg 826 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_MAIN_PIX_FORMAT_RGB666; reg 829 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; reg 832 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_MAIN_PIX_FORMAT_RGB565; reg 849 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_CLKLANE_STOP; reg 851 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); reg 864 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); reg 865 drivers/gpu/drm/exynos/exynos_drm_dsi.c if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) reg 868 drivers/gpu/drm/exynos/exynos_drm_dsi.c } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); reg 870 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); reg 871 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg &= ~DSIM_STOP_STATE_CNT_MASK; reg 872 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); reg 873 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg); reg 875 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); reg 876 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg); reg 885 drivers/gpu/drm/exynos/exynos_drm_dsi.c u32 reg; reg 888 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = DSIM_CMD_ALLOW(0xf) reg 891 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg); reg 893 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay) reg 895 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg); reg 897 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) reg 899 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg); reg 901 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | reg 904 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); reg 911 drivers/gpu/drm/exynos/exynos_drm_dsi.c u32 reg; reg 913 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG); reg 915 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= DSIM_MAIN_STAND_BY; reg 917 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg &= ~DSIM_MAIN_STAND_BY; reg 918 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); reg 926 drivers/gpu/drm/exynos/exynos_drm_dsi.c u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); reg 928 drivers/gpu/drm/exynos/exynos_drm_dsi.c if (!(reg & DSIM_SFR_HEADER_FULL)) reg 965 drivers/gpu/drm/exynos/exynos_drm_dsi.c u32 reg; reg 977 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = get_unaligned_le32(payload); reg 978 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); reg 983 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = 0; reg 986 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= payload[2] << 16; reg 989 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= payload[1] << 8; reg 992 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg |= payload[0]; reg 993 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); reg 1001 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = get_unaligned_le32(pkt->header); reg 1013 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg); reg 1026 drivers/gpu/drm/exynos/exynos_drm_dsi.c u32 reg; reg 1029 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); reg 1031 drivers/gpu/drm/exynos/exynos_drm_dsi.c switch (reg & 0x3f) { reg 1035 drivers/gpu/drm/exynos/exynos_drm_dsi.c payload[1] = reg >> 16; reg 1041 drivers/gpu/drm/exynos/exynos_drm_dsi.c payload[0] = reg >> 8; reg 1048 drivers/gpu/drm/exynos/exynos_drm_dsi.c (reg >> 8) & 0xffff); reg 1053 drivers/gpu/drm/exynos/exynos_drm_dsi.c length = (reg >> 8) & 0xffff; reg 1068 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); reg 1069 drivers/gpu/drm/exynos/exynos_drm_dsi.c payload[0] = (reg >> 0) & 0xff; reg 1070 drivers/gpu/drm/exynos/exynos_drm_dsi.c payload[1] = (reg >> 8) & 0xff; reg 1071 drivers/gpu/drm/exynos/exynos_drm_dsi.c payload[2] = (reg >> 16) & 0xff; reg 1072 drivers/gpu/drm/exynos/exynos_drm_dsi.c payload[3] = (reg >> 24) & 0xff; reg 1078 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); reg 1081 drivers/gpu/drm/exynos/exynos_drm_dsi.c payload[2] = (reg >> 16) & 0xff; reg 1084 drivers/gpu/drm/exynos/exynos_drm_dsi.c payload[1] = (reg >> 8) & 0xff; reg 1087 drivers/gpu/drm/exynos/exynos_drm_dsi.c payload[0] = reg & 0xff; reg 1097 drivers/gpu/drm/exynos/exynos_drm_dsi.c reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); reg 1098 drivers/gpu/drm/exynos/exynos_drm_dsi.c if (reg == DSI_RX_FIFO_EMPTY) reg 115 drivers/gpu/drm/exynos/exynos_drm_fimc.c static u32 fimc_read(struct fimc_context *ctx, u32 reg) reg 117 drivers/gpu/drm/exynos/exynos_drm_fimc.c return readl(ctx->regs + reg); reg 120 drivers/gpu/drm/exynos/exynos_drm_fimc.c static void fimc_write(struct fimc_context *ctx, u32 val, u32 reg) reg 122 drivers/gpu/drm/exynos/exynos_drm_fimc.c writel(val, ctx->regs + reg); reg 125 drivers/gpu/drm/exynos/exynos_drm_fimc.c static void fimc_set_bits(struct fimc_context *ctx, u32 reg, u32 bits) reg 127 drivers/gpu/drm/exynos/exynos_drm_fimc.c void __iomem *r = ctx->regs + reg; reg 132 drivers/gpu/drm/exynos/exynos_drm_fimc.c static void fimc_clear_bits(struct fimc_context *ctx, u32 reg, u32 bits) reg 134 drivers/gpu/drm/exynos/exynos_drm_fimc.c void __iomem *r = ctx->regs + reg; reg 237 drivers/gpu/drm/exynos/exynos_drm_fimd.c static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask, reg 240 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = (val & mask) | (readl(ctx->regs + reg) & ~mask); reg 241 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + reg); reg 734 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 reg, bits, val; reg 747 drivers/gpu/drm/exynos/exynos_drm_fimd.c reg = SHADOWCON; reg 750 drivers/gpu/drm/exynos/exynos_drm_fimd.c reg = PRTCON; reg 754 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = readl(ctx->regs + reg); reg 759 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(val, ctx->regs + reg); reg 947 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 reg; reg 959 drivers/gpu/drm/exynos/exynos_drm_fimd.c reg = readl(timing_base + TRIGCON); reg 960 drivers/gpu/drm/exynos/exynos_drm_fimd.c reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE); reg 961 drivers/gpu/drm/exynos/exynos_drm_fimd.c writel(reg, timing_base + TRIGCON); reg 96 drivers/gpu/drm/exynos/exynos_drm_mic.c void __iomem *reg; reg 141 drivers/gpu/drm/exynos/exynos_drm_mic.c writel(MIC_SW_RST, mic->reg + MIC_OP); reg 144 drivers/gpu/drm/exynos/exynos_drm_mic.c ret = readl(mic->reg + MIC_OP); reg 157 drivers/gpu/drm/exynos/exynos_drm_mic.c u32 reg; reg 159 drivers/gpu/drm/exynos/exynos_drm_mic.c reg = MIC_V_PULSE_WIDTH(vm.vsync_len) + reg 162 drivers/gpu/drm/exynos/exynos_drm_mic.c writel(reg, mic->reg + MIC_V_TIMING_0); reg 164 drivers/gpu/drm/exynos/exynos_drm_mic.c reg = MIC_VBP_SIZE(vm.vback_porch) + reg 166 drivers/gpu/drm/exynos/exynos_drm_mic.c writel(reg, mic->reg + MIC_V_TIMING_1); reg 168 drivers/gpu/drm/exynos/exynos_drm_mic.c reg = MIC_V_PULSE_WIDTH(vm.hsync_len) + reg 171 drivers/gpu/drm/exynos/exynos_drm_mic.c writel(reg, mic->reg + MIC_INPUT_TIMING_0); reg 173 drivers/gpu/drm/exynos/exynos_drm_mic.c reg = MIC_VBP_SIZE(vm.hback_porch) + reg 175 drivers/gpu/drm/exynos/exynos_drm_mic.c writel(reg, mic->reg + MIC_INPUT_TIMING_1); reg 181 drivers/gpu/drm/exynos/exynos_drm_mic.c u32 reg; reg 183 drivers/gpu/drm/exynos/exynos_drm_mic.c reg = MIC_IMG_H_SIZE(vm->hactive) + reg 186 drivers/gpu/drm/exynos/exynos_drm_mic.c writel(reg, mic->reg + MIC_IMG_SIZE); reg 192 drivers/gpu/drm/exynos/exynos_drm_mic.c u32 reg, bs_size_2d; reg 196 drivers/gpu/drm/exynos/exynos_drm_mic.c reg = MIC_BS_SIZE_2D(bs_size_2d); reg 197 drivers/gpu/drm/exynos/exynos_drm_mic.c writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_2); reg 200 drivers/gpu/drm/exynos/exynos_drm_mic.c reg = MIC_H_PULSE_WIDTH_2D(vm.hsync_len) + reg 203 drivers/gpu/drm/exynos/exynos_drm_mic.c writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_0); reg 205 drivers/gpu/drm/exynos/exynos_drm_mic.c reg = MIC_HBP_SIZE_2D(vm.hback_porch) + reg 207 drivers/gpu/drm/exynos/exynos_drm_mic.c writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_1); reg 213 drivers/gpu/drm/exynos/exynos_drm_mic.c u32 reg = readl(mic->reg + MIC_OP); reg 216 drivers/gpu/drm/exynos/exynos_drm_mic.c reg &= ~(MIC_MODE_SEL_MASK | MIC_CORE_VER_CONTROL | MIC_PSR_EN); reg 217 drivers/gpu/drm/exynos/exynos_drm_mic.c reg |= (MIC_CORE_EN | MIC_BS_CHG_OUT | MIC_ON_REG); reg 219 drivers/gpu/drm/exynos/exynos_drm_mic.c reg &= ~MIC_MODE_SEL_COMMAND_MODE; reg 221 drivers/gpu/drm/exynos/exynos_drm_mic.c reg |= MIC_MODE_SEL_COMMAND_MODE; reg 223 drivers/gpu/drm/exynos/exynos_drm_mic.c reg &= ~MIC_CORE_EN; reg 226 drivers/gpu/drm/exynos/exynos_drm_mic.c reg |= MIC_UPD_REG; reg 227 drivers/gpu/drm/exynos/exynos_drm_mic.c writel(reg, mic->reg + MIC_OP); reg 397 drivers/gpu/drm/exynos/exynos_drm_mic.c mic->reg = devm_ioremap(dev, res.start, resource_size(&res)); reg 398 drivers/gpu/drm/exynos/exynos_drm_mic.c if (!mic->reg) { reg 128 drivers/gpu/drm/exynos/regs-scaler.h #define SCALER_GET(reg, hi_b, lo_b) \ reg 129 drivers/gpu/drm/exynos/regs-scaler.h (((reg) >> (lo_b)) & SCALER_MASK(hi_b, lo_b)) reg 38 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c static bool fsl_dcu_drm_is_volatile_reg(struct device *dev, unsigned int reg) reg 40 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c if (reg == DCU_INT_STATUS || reg == DCU_UPDATE_MODE) reg 117 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h #define DCU_CTRLDESCLN(layer, reg) (0x200 + (reg - 1) * 4 + (layer) * 0x40) reg 18 drivers/gpu/drm/gma500/cdv_device.h int reg); reg 42 drivers/gpu/drm/gma500/cdv_intel_crt.c u32 temp, reg; reg 43 drivers/gpu/drm/gma500/cdv_intel_crt.c reg = ADPA; reg 45 drivers/gpu/drm/gma500/cdv_intel_crt.c temp = REG_READ(reg); reg 64 drivers/gpu/drm/gma500/cdv_intel_crt.c REG_WRITE(reg, temp); reg 129 drivers/gpu/drm/gma500/cdv_intel_display.c int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val) reg 139 drivers/gpu/drm/gma500/cdv_intel_display.c REG_WRITE(SB_ADDR, reg); reg 156 drivers/gpu/drm/gma500/cdv_intel_display.c int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val) reg 163 drivers/gpu/drm/gma500/cdv_intel_display.c if (cdv_sb_read(dev, reg, &temp) == 0) reg 164 drivers/gpu/drm/gma500/cdv_intel_display.c DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp); reg 165 drivers/gpu/drm/gma500/cdv_intel_display.c DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val); reg 174 drivers/gpu/drm/gma500/cdv_intel_display.c REG_WRITE(SB_ADDR, reg); reg 188 drivers/gpu/drm/gma500/cdv_intel_display.c if (cdv_sb_read(dev, reg, &temp) == 0) reg 189 drivers/gpu/drm/gma500/cdv_intel_display.c DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp); reg 1507 drivers/gpu/drm/gma500/cdv_intel_dp.c u32 reg; reg 1513 drivers/gpu/drm/gma500/cdv_intel_dp.c reg = DP; reg 1514 drivers/gpu/drm/gma500/cdv_intel_dp.c reg |= DP_LINK_TRAIN_PAT_1; reg 1516 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_WRITE(intel_dp->output_reg, reg); reg 1532 drivers/gpu/drm/gma500/cdv_intel_dp.c reg = DP | DP_LINK_TRAIN_PAT_1; reg 1542 drivers/gpu/drm/gma500/cdv_intel_dp.c if (!cdv_intel_dp_set_link_train(encoder, reg, DP_TRAINING_PATTERN_1)) { reg 1599 drivers/gpu/drm/gma500/cdv_intel_dp.c u32 reg; reg 1608 drivers/gpu/drm/gma500/cdv_intel_dp.c reg = DP | DP_LINK_TRAIN_PAT_2; reg 1618 drivers/gpu/drm/gma500/cdv_intel_dp.c if (!cdv_intel_dp_set_link_train(encoder, reg, reg 1670 drivers/gpu/drm/gma500/cdv_intel_dp.c reg = DP | DP_LINK_TRAIN_OFF; reg 1672 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_WRITE(intel_dp->output_reg, reg); reg 279 drivers/gpu/drm/gma500/cdv_intel_hdmi.c struct psb_intel_mode_device *mode_dev, int reg) reg 319 drivers/gpu/drm/gma500/cdv_intel_hdmi.c hdmi_priv->hdmi_reg = reg; reg 334 drivers/gpu/drm/gma500/cdv_intel_hdmi.c switch (reg) { reg 344 drivers/gpu/drm/gma500/cdv_intel_hdmi.c DRM_ERROR("unknown reg 0x%x for HDMI\n", reg); reg 350 drivers/gpu/drm/gma500/cdv_intel_hdmi.c ddc_bus, (reg == SDVOB) ? "HDMIB" : "HDMIC"); reg 55 drivers/gpu/drm/gma500/intel_gmbus.c #define GMBUS_REG_READ(reg) ioread32(dev_priv->gmbus_reg + (reg)) reg 56 drivers/gpu/drm/gma500/intel_gmbus.c #define GMBUS_REG_WRITE(reg, val) iowrite32((val), dev_priv->gmbus_reg + (reg)) reg 72 drivers/gpu/drm/gma500/intel_gmbus.c u32 reg; reg 109 drivers/gpu/drm/gma500/intel_gmbus.c reserved = GMBUS_REG_READ(gpio->reg) & reg 121 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK); reg 122 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_WRITE(gpio->reg, reserved); reg 123 drivers/gpu/drm/gma500/intel_gmbus.c return (GMBUS_REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0; reg 131 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK); reg 132 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_WRITE(gpio->reg, reserved); reg 133 drivers/gpu/drm/gma500/intel_gmbus.c return (GMBUS_REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0; reg 149 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_WRITE(gpio->reg, reserved | clock_bits); reg 150 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_READ(gpio->reg); /* Posting */ reg 166 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_WRITE(gpio->reg, reserved | data_bits); reg 167 drivers/gpu/drm/gma500/intel_gmbus.c GMBUS_REG_READ(gpio->reg); reg 192 drivers/gpu/drm/gma500/intel_gmbus.c gpio->reg = map_pin_to_reg[pin]; reg 29 drivers/gpu/drm/gma500/intel_i2c.c val = REG_READ(chan->reg); reg 39 drivers/gpu/drm/gma500/intel_i2c.c val = REG_READ(chan->reg); reg 51 drivers/gpu/drm/gma500/intel_i2c.c REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | reg 59 drivers/gpu/drm/gma500/intel_i2c.c REG_WRITE(chan->reg, reserved | clock_bits); reg 71 drivers/gpu/drm/gma500/intel_i2c.c REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | reg 81 drivers/gpu/drm/gma500/intel_i2c.c REG_WRITE(chan->reg, reserved | data_bits); reg 107 drivers/gpu/drm/gma500/intel_i2c.c const u32 reg, const char *name) reg 116 drivers/gpu/drm/gma500/intel_i2c.c chan->reg = reg; reg 50 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define REG_FLD_MOD(reg, val, start, end) \ reg 51 drivers/gpu/drm/gma500/mdfld_dsi_output.h REG_WRITE(reg, FLD_MOD(REG_READ(reg), val, start, end)) reg 53 drivers/gpu/drm/gma500/mdfld_dsi_output.h static inline int REGISTER_FLD_WAIT(struct drm_device *dev, u32 reg, reg 58 drivers/gpu/drm/gma500/mdfld_dsi_output.h while (FLD_GET(REG_READ(reg), start, end) != val) { reg 66 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define REG_FLD_WAIT(reg, val, start, end) \ reg 67 drivers/gpu/drm/gma500/mdfld_dsi_output.h REGISTER_FLD_WAIT(dev, reg, val, start, end) reg 69 drivers/gpu/drm/gma500/mdfld_dsi_output.h #define REG_BIT_WAIT(reg, val, bitnum) \ reg 70 drivers/gpu/drm/gma500/mdfld_dsi_output.h REGISTER_FLD_WAIT(dev, reg, val, bitnum, bitnum) reg 35 drivers/gpu/drm/gma500/oaktrail_hdmi.c #define HDMI_READ(reg) readl(hdmi_dev->regs + (reg)) reg 36 drivers/gpu/drm/gma500/oaktrail_hdmi.c #define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg)) reg 35 drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c #define HDMI_READ(reg) readl(hdmi_dev->regs + (reg)) reg 36 drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c #define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg)) reg 63 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c #define LPC_READ_REG(chan, r) inl((chan)->reg + (r)) reg 64 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c #define LPC_WRITE_REG(chan, r, val) outl((val), (chan)->reg + (r)) reg 144 drivers/gpu/drm/gma500/oaktrail_lvds_i2c.c chan->reg = dev_priv->lpc_gpio_base; reg 811 drivers/gpu/drm/gma500/psb_drv.h static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg) reg 814 drivers/gpu/drm/gma500/psb_drv.h return ioread32(dev_priv->vdc_reg + reg); reg 817 drivers/gpu/drm/gma500/psb_drv.h static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg) reg 820 drivers/gpu/drm/gma500/psb_drv.h return ioread32(dev_priv->aux_reg + reg); reg 823 drivers/gpu/drm/gma500/psb_drv.h #define REG_READ(reg) REGISTER_READ(dev, (reg)) reg 824 drivers/gpu/drm/gma500/psb_drv.h #define REG_READ_AUX(reg) REGISTER_READ_AUX(dev, (reg)) reg 828 drivers/gpu/drm/gma500/psb_drv.h uint32_t reg, int aux) reg 833 drivers/gpu/drm/gma500/psb_drv.h val = REG_READ_AUX(reg); reg 835 drivers/gpu/drm/gma500/psb_drv.h val = REG_READ(reg); reg 840 drivers/gpu/drm/gma500/psb_drv.h #define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux)) reg 842 drivers/gpu/drm/gma500/psb_drv.h static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg, reg 846 drivers/gpu/drm/gma500/psb_drv.h iowrite32((val), dev_priv->vdc_reg + (reg)); reg 849 drivers/gpu/drm/gma500/psb_drv.h static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg, reg 853 drivers/gpu/drm/gma500/psb_drv.h iowrite32((val), dev_priv->aux_reg + (reg)); reg 856 drivers/gpu/drm/gma500/psb_drv.h #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val)) reg 857 drivers/gpu/drm/gma500/psb_drv.h #define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val)) reg 859 drivers/gpu/drm/gma500/psb_drv.h static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg, reg 863 drivers/gpu/drm/gma500/psb_drv.h REG_WRITE_AUX(reg, val); reg 865 drivers/gpu/drm/gma500/psb_drv.h REG_WRITE(reg, val); reg 868 drivers/gpu/drm/gma500/psb_drv.h #define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux)) reg 871 drivers/gpu/drm/gma500/psb_drv.h uint32_t reg, uint32_t val) reg 874 drivers/gpu/drm/gma500/psb_drv.h iowrite16((val), dev_priv->vdc_reg + (reg)); reg 877 drivers/gpu/drm/gma500/psb_drv.h #define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val)) reg 880 drivers/gpu/drm/gma500/psb_drv.h uint32_t reg, uint32_t val) reg 883 drivers/gpu/drm/gma500/psb_drv.h iowrite8((val), dev_priv->vdc_reg + (reg)); reg 886 drivers/gpu/drm/gma500/psb_drv.h #define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val)) reg 103 drivers/gpu/drm/gma500/psb_intel_drv.h u32 reg; /* GPIO reg */ reg 197 drivers/gpu/drm/gma500/psb_intel_drv.h const u32 reg, const char *name); reg 270 drivers/gpu/drm/gma500/psb_intel_drv.h extern int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val); reg 271 drivers/gpu/drm/gma500/psb_intel_drv.h extern int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val); reg 398 drivers/gpu/drm/gma500/psb_intel_sdvo.c #define IS_SDVOB(reg) (reg == SDVOB) reg 1928 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct psb_intel_sdvo *sdvo, u32 reg) reg 1932 drivers/gpu/drm/gma500/psb_intel_sdvo.c if (IS_SDVOB(reg)) reg 1945 drivers/gpu/drm/gma500/psb_intel_sdvo.c struct psb_intel_sdvo *sdvo, u32 reg) reg 1950 drivers/gpu/drm/gma500/psb_intel_sdvo.c if (IS_SDVOB(reg)) reg 76 drivers/gpu/drm/gma500/psb_irq.c u32 reg = psb_pipestat(pipe); reg 80 drivers/gpu/drm/gma500/psb_irq.c u32 writeVal = PSB_RVDC32(reg); reg 82 drivers/gpu/drm/gma500/psb_irq.c PSB_WVDC32(writeVal, reg); reg 83 drivers/gpu/drm/gma500/psb_irq.c (void) PSB_RVDC32(reg); reg 93 drivers/gpu/drm/gma500/psb_irq.c u32 reg = psb_pipestat(pipe); reg 96 drivers/gpu/drm/gma500/psb_irq.c u32 writeVal = PSB_RVDC32(reg); reg 98 drivers/gpu/drm/gma500/psb_irq.c PSB_WVDC32(writeVal, reg); reg 99 drivers/gpu/drm/gma500/psb_irq.c (void) PSB_RVDC32(reg); reg 224 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c static int tc35876x_regw(struct i2c_client *client, u16 reg, u32 value) reg 229 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c (reg >> 8) & 0xff, reg 230 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c reg & 0xff, reg 248 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c __func__, reg, value, r); reg 254 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c __func__, reg, value, r); reg 259 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c __func__, reg, value); reg 272 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c static int tc35876x_regr(struct i2c_client *client, u16 reg, u32 *value) reg 276 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c (reg >> 8) & 0xff, reg 277 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c reg & 0xff, reg 298 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c reg, r); reg 304 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c reg, r); reg 312 drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c reg, *value); reg 98 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c u32 reg; reg 125 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg = state->fb->width * (state->fb->format->cpp[0]); reg 127 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg = PADDING(16, reg); reg 131 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) | reg 136 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); reg 137 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg &= ~HIBMC_CRT_DISP_CTL_FORMAT_MASK; reg 138 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_FORMAT, reg 140 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); reg 198 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c unsigned int reg; reg 204 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg = readl(priv->mmio + HIBMC_CURRENT_GATE); reg 205 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; reg 206 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; reg 207 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg |= HIBMC_CURR_GATE_LOCALMEM(1); reg 208 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg |= HIBMC_CURR_GATE_DISPLAY(1); reg 209 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c hibmc_set_current_gate(priv, reg); reg 216 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c unsigned int reg; reg 224 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg = readl(priv->mmio + HIBMC_CURRENT_GATE); reg 225 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; reg 226 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; reg 227 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg |= HIBMC_CURR_GATE_LOCALMEM(0); reg 228 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg |= HIBMC_CURR_GATE_DISPLAY(0); reg 229 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c hibmc_set_current_gate(priv, reg); reg 398 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c unsigned int reg; reg 405 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg = readl(priv->mmio + HIBMC_CURRENT_GATE); reg 406 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; reg 407 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; reg 408 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg |= HIBMC_CURR_GATE_DISPLAY(1); reg 409 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c reg |= HIBMC_CURR_GATE_LOCALMEM(1); reg 410 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c hibmc_set_current_gate(priv, reg); reg 179 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c unsigned int reg; reg 185 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c reg = readl(priv->mmio + HIBMC_CURRENT_GATE); reg 186 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; reg 187 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; reg 188 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c reg |= HIBMC_CURR_GATE_DISPLAY(1); reg 189 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c reg |= HIBMC_CURR_GATE_LOCALMEM(1); reg 191 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c hibmc_set_current_gate(priv, reg); reg 199 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c reg = readl(priv->mmio + HIBMC_MISC_CTRL); reg 200 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK; reg 201 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c reg |= HIBMC_MSCCTL_LOCALMEM_RESET(0); reg 202 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c writel(reg, priv->mmio + HIBMC_MISC_CTRL); reg 204 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c reg &= ~HIBMC_MSCCTL_LOCALMEM_RESET_MASK; reg 205 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c reg |= HIBMC_MSCCTL_LOCALMEM_RESET(1); reg 207 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c writel(reg, priv->mmio + HIBMC_MISC_CTRL); reg 76 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c u32 reg; reg 80 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c reg = readl(priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE); reg 81 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c reg |= HIBMC_DISPLAY_CONTROL_FPVDDEN(1); reg 82 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c reg |= HIBMC_DISPLAY_CONTROL_PANELDATE(1); reg 83 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c reg |= HIBMC_DISPLAY_CONTROL_FPEN(1); reg 84 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c reg |= HIBMC_DISPLAY_CONTROL_VBIASEN(1); reg 85 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c writel(reg, priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE); reg 310 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c static void dsi_phy_tst_set(void __iomem *base, u32 reg, u32 val) reg 312 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c u32 reg_write = 0x10000 + reg; reg 150 drivers/gpu/drm/i2c/ch7006_priv.h #define setbitf(state, reg, bitfield, x) \ reg 151 drivers/gpu/drm/i2c/ch7006_priv.h state->regs[reg] = (state->regs[reg] & ~mask(reg##_##bitfield)) \ reg 152 drivers/gpu/drm/i2c/ch7006_priv.h | bitf(reg##_##bitfield, x) reg 168 drivers/gpu/drm/i2c/ch7006_priv.h #define ch7006_load_reg(client, state, reg) ch7006_write(client, reg, state->regs[reg]) reg 169 drivers/gpu/drm/i2c/ch7006_priv.h #define ch7006_save_reg(client, state, reg) state->regs[reg] = ch7006_read(client, reg) reg 102 drivers/gpu/drm/i2c/tda998x_drv.c #define REG2ADDR(reg) ((reg) & 0xff) reg 103 drivers/gpu/drm/i2c/tda998x_drv.c #define REG2PAGE(reg) (((reg) >> 8) & 0xff) reg 556 drivers/gpu/drm/i2c/tda998x_drv.c set_page(struct tda998x_priv *priv, u16 reg) reg 558 drivers/gpu/drm/i2c/tda998x_drv.c if (REG2PAGE(reg) != priv->current_page) { reg 561 drivers/gpu/drm/i2c/tda998x_drv.c REG_CURPAGE, REG2PAGE(reg) reg 566 drivers/gpu/drm/i2c/tda998x_drv.c reg, ret); reg 570 drivers/gpu/drm/i2c/tda998x_drv.c priv->current_page = REG2PAGE(reg); reg 576 drivers/gpu/drm/i2c/tda998x_drv.c reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt) reg 579 drivers/gpu/drm/i2c/tda998x_drv.c u8 addr = REG2ADDR(reg); reg 583 drivers/gpu/drm/i2c/tda998x_drv.c ret = set_page(priv, reg); reg 598 drivers/gpu/drm/i2c/tda998x_drv.c dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); reg 607 drivers/gpu/drm/i2c/tda998x_drv.c reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt) reg 620 drivers/gpu/drm/i2c/tda998x_drv.c buf[0] = REG2ADDR(reg); reg 624 drivers/gpu/drm/i2c/tda998x_drv.c ret = set_page(priv, reg); reg 630 drivers/gpu/drm/i2c/tda998x_drv.c dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); reg 636 drivers/gpu/drm/i2c/tda998x_drv.c reg_read(struct tda998x_priv *priv, u16 reg) reg 641 drivers/gpu/drm/i2c/tda998x_drv.c ret = reg_read_range(priv, reg, &val, sizeof(val)); reg 648 drivers/gpu/drm/i2c/tda998x_drv.c reg_write(struct tda998x_priv *priv, u16 reg, u8 val) reg 651 drivers/gpu/drm/i2c/tda998x_drv.c u8 buf[] = {REG2ADDR(reg), val}; reg 655 drivers/gpu/drm/i2c/tda998x_drv.c ret = set_page(priv, reg); reg 661 drivers/gpu/drm/i2c/tda998x_drv.c dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); reg 667 drivers/gpu/drm/i2c/tda998x_drv.c reg_write16(struct tda998x_priv *priv, u16 reg, u16 val) reg 670 drivers/gpu/drm/i2c/tda998x_drv.c u8 buf[] = {REG2ADDR(reg), val >> 8, val}; reg 674 drivers/gpu/drm/i2c/tda998x_drv.c ret = set_page(priv, reg); reg 680 drivers/gpu/drm/i2c/tda998x_drv.c dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); reg 686 drivers/gpu/drm/i2c/tda998x_drv.c reg_set(struct tda998x_priv *priv, u16 reg, u8 val) reg 690 drivers/gpu/drm/i2c/tda998x_drv.c old_val = reg_read(priv, reg); reg 692 drivers/gpu/drm/i2c/tda998x_drv.c reg_write(priv, reg, old_val | val); reg 696 drivers/gpu/drm/i2c/tda998x_drv.c reg_clear(struct tda998x_priv *priv, u16 reg, u8 val) reg 700 drivers/gpu/drm/i2c/tda998x_drv.c old_val = reg_read(priv, reg); reg 702 drivers/gpu/drm/i2c/tda998x_drv.c reg_write(priv, reg, old_val & ~val); reg 1432 drivers/gpu/drm/i2c/tda998x_drv.c u8 reg, div, rep, sel_clk; reg 1585 drivers/gpu/drm/i2c/tda998x_drv.c reg = VIP_CNTRL_3_SYNC_HS; reg 1592 drivers/gpu/drm/i2c/tda998x_drv.c reg |= VIP_CNTRL_3_H_TGL; reg 1594 drivers/gpu/drm/i2c/tda998x_drv.c reg |= VIP_CNTRL_3_V_TGL; reg 1595 drivers/gpu/drm/i2c/tda998x_drv.c reg_write(priv, REG_VIP_CNTRL_3, reg); reg 1628 drivers/gpu/drm/i2c/tda998x_drv.c reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN; reg 1630 drivers/gpu/drm/i2c/tda998x_drv.c reg |= TBG_CNTRL_1_H_TGL; reg 1632 drivers/gpu/drm/i2c/tda998x_drv.c reg |= TBG_CNTRL_1_V_TGL; reg 1633 drivers/gpu/drm/i2c/tda998x_drv.c reg_write(priv, REG_TBG_CNTRL_1, reg); reg 1653 drivers/gpu/drm/i2c/tda998x_drv.c reg &= ~TBG_CNTRL_1_DWIN_DIS; reg 1654 drivers/gpu/drm/i2c/tda998x_drv.c reg_write(priv, REG_TBG_CNTRL_1, reg); reg 134 drivers/gpu/drm/i810/i810_drv.h #define I810_BASE(reg) ((unsigned long) \ reg 136 drivers/gpu/drm/i810/i810_drv.h #define I810_ADDR(reg) (I810_BASE(reg) + reg) reg 137 drivers/gpu/drm/i810/i810_drv.h #define I810_DEREF(reg) (*(__volatile__ int *)I810_ADDR(reg)) reg 138 drivers/gpu/drm/i810/i810_drv.h #define I810_READ(reg) I810_DEREF(reg) reg 139 drivers/gpu/drm/i810/i810_drv.h #define I810_WRITE(reg, val) do { I810_DEREF(reg) = val; } while (0) reg 140 drivers/gpu/drm/i810/i810_drv.h #define I810_DEREF16(reg) (*(__volatile__ u16 *)I810_ADDR(reg)) reg 141 drivers/gpu/drm/i810/i810_drv.h #define I810_READ16(reg) I810_DEREF16(reg) reg 142 drivers/gpu/drm/i810/i810_drv.h #define I810_WRITE16(reg, val) do { I810_DEREF16(reg) = val; } while (0) reg 379 drivers/gpu/drm/i915/display/dvo_ch7017.c #define DUMP(reg) \ reg 381 drivers/gpu/drm/i915/display/dvo_ch7017.c ch7017_read(dvo, reg, &val); \ reg 382 drivers/gpu/drm/i915/display/dvo_ch7017.c DRM_DEBUG_KMS(#reg ": %02x\n", val); \ reg 94 drivers/gpu/drm/i915/display/intel_combo_phy.c enum phy phy, i915_reg_t reg, u32 mask, reg 97 drivers/gpu/drm/i915/display/intel_combo_phy.c u32 val = I915_READ(reg); reg 103 drivers/gpu/drm/i915/display/intel_combo_phy.c reg.reg, val, mask, expected_val); reg 987 drivers/gpu/drm/i915/display/intel_ddi.c i915_reg_t reg = DDI_BUF_CTL(port); reg 992 drivers/gpu/drm/i915/display/intel_ddi.c if (I915_READ(reg) & DDI_BUF_IS_IDLE) reg 1229 drivers/gpu/drm/i915/display/intel_ddi.c i915_reg_t reg) reg 1235 drivers/gpu/drm/i915/display/intel_ddi.c wrpll = I915_READ(reg); reg 1856 drivers/gpu/drm/i915/display/intel_ddi.c i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); reg 1857 drivers/gpu/drm/i915/display/intel_ddi.c u32 val = I915_READ(reg); reg 1866 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(reg, val); reg 3532 drivers/gpu/drm/i915/display/intel_ddi.c i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); reg 3535 drivers/gpu/drm/i915/display/intel_ddi.c val = I915_READ(reg); reg 3544 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(reg, val); reg 3545 drivers/gpu/drm/i915/display/intel_ddi.c POSTING_READ(reg); reg 3556 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(reg, val); reg 173 drivers/gpu/drm/i915/display/intel_display.c const char *name, u32 reg, int ref_freq) reg 178 drivers/gpu/drm/i915/display/intel_display.c val = vlv_cck_read(dev_priv, reg); reg 189 drivers/gpu/drm/i915/display/intel_display.c const char *name, u32 reg) reg 198 drivers/gpu/drm/i915/display/intel_display.c hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); reg 1032 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg = PIPEDSL(pipe); reg 1041 drivers/gpu/drm/i915/display/intel_display.c line1 = I915_READ(reg) & line_mask; reg 1043 drivers/gpu/drm/i915/display/intel_display.c line2 = I915_READ(reg) & line_mask; reg 1077 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg = PIPECONF(cpu_transcoder); reg 1080 drivers/gpu/drm/i915/display/intel_display.c if (intel_de_wait_for_clear(dev_priv, reg, reg 1487 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg = DPLL(crtc->pipe); reg 1502 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS); reg 1503 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, dpll); reg 1506 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 1518 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, dpll); reg 1523 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, dpll); reg 1524 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 1625 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; reg 1638 drivers/gpu/drm/i915/display/intel_display.c reg = TRANS_CHICKEN2(pipe); reg 1639 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(reg); reg 1641 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, val); reg 1644 drivers/gpu/drm/i915/display/intel_display.c reg = PCH_TRANSCONF(pipe); reg 1645 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(reg); reg 1672 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, val | TRANS_ENABLE); reg 1673 drivers/gpu/drm/i915/display/intel_display.c if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100)) reg 1709 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; reg 1719 drivers/gpu/drm/i915/display/intel_display.c reg = PCH_TRANSCONF(pipe); reg 1720 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(reg); reg 1722 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, val); reg 1724 drivers/gpu/drm/i915/display/intel_display.c if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50)) reg 1729 drivers/gpu/drm/i915/display/intel_display.c reg = TRANS_CHICKEN2(pipe); reg 1730 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(reg); reg 1732 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, val); reg 1799 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; reg 1829 drivers/gpu/drm/i915/display/intel_display.c reg = PIPECONF(cpu_transcoder); reg 1830 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(reg); reg 1837 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, val | PIPECONF_ENABLE); reg 1838 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 1857 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; reg 1870 drivers/gpu/drm/i915/display/intel_display.c reg = PIPECONF(cpu_transcoder); reg 1871 drivers/gpu/drm/i915/display/intel_display.c val = I915_READ(reg); reg 1886 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, val); reg 4441 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; reg 4445 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_TX_CTL(pipe); reg 4446 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4454 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp); reg 4456 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_CTL(pipe); reg 4457 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4465 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); reg 4468 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 4473 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | reg 4484 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; reg 4492 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_IMR(pipe); reg 4493 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4496 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp); reg 4497 drivers/gpu/drm/i915/display/intel_display.c I915_READ(reg); reg 4501 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_TX_CTL(pipe); reg 4502 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4507 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp | FDI_TX_ENABLE); reg 4509 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_CTL(pipe); reg 4510 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4513 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp | FDI_RX_ENABLE); reg 4515 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 4523 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_IIR(pipe); reg 4525 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4530 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); reg 4538 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_TX_CTL(pipe); reg 4539 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4542 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp); reg 4544 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_CTL(pipe); reg 4545 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4548 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp); reg 4550 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 4553 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_IIR(pipe); reg 4555 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4559 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); reg 4585 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; reg 4590 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_IMR(pipe); reg 4591 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4594 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp); reg 4596 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 4600 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_TX_CTL(pipe); reg 4601 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4609 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp | FDI_TX_ENABLE); reg 4614 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_CTL(pipe); reg 4615 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4623 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp | FDI_RX_ENABLE); reg 4625 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 4629 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_TX_CTL(pipe); reg 4630 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4633 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp); reg 4635 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 4639 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_IIR(pipe); reg 4640 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4643 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); reg 4656 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_TX_CTL(pipe); reg 4657 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4665 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp); reg 4667 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_CTL(pipe); reg 4668 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4676 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp); reg 4678 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 4682 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_TX_CTL(pipe); reg 4683 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4686 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp); reg 4688 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 4692 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_IIR(pipe); reg 4693 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4696 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); reg 4718 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; reg 4723 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_IMR(pipe); reg 4724 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4727 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp); reg 4729 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 4738 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_TX_CTL(pipe); reg 4739 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4742 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp); reg 4744 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_CTL(pipe); reg 4745 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4749 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp); reg 4752 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_TX_CTL(pipe); reg 4753 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4760 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp | FDI_TX_ENABLE); reg 4765 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_CTL(pipe); reg 4766 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4769 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp | FDI_RX_ENABLE); reg 4771 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 4775 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_IIR(pipe); reg 4776 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4780 drivers/gpu/drm/i915/display/intel_display.c (I915_READ(reg) & FDI_RX_BIT_LOCK)) { reg 4781 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); reg 4794 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_TX_CTL(pipe); reg 4795 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4798 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp); reg 4800 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_CTL(pipe); reg 4801 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4804 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp); reg 4806 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 4810 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_IIR(pipe); reg 4811 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4815 drivers/gpu/drm/i915/display/intel_display.c (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { reg 4816 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); reg 4836 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; reg 4840 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_CTL(pipe); reg 4841 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4845 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); reg 4847 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 4851 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4852 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp | FDI_PCDCLK); reg 4854 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 4858 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_TX_CTL(pipe); reg 4859 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4861 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); reg 4863 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 4873 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; reg 4877 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_CTL(pipe); reg 4878 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4879 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp & ~FDI_PCDCLK); reg 4882 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_TX_CTL(pipe); reg 4883 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4884 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); reg 4886 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 4889 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_CTL(pipe); reg 4890 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4891 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); reg 4894 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 4904 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; reg 4908 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_TX_CTL(pipe); reg 4909 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4910 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp & ~FDI_TX_ENABLE); reg 4911 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 4913 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_CTL(pipe); reg 4914 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4917 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp & ~FDI_RX_ENABLE); reg 4919 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 4927 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_TX_CTL(pipe); reg 4928 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4931 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp); reg 4933 drivers/gpu/drm/i915/display/intel_display.c reg = FDI_RX_CTL(pipe); reg 4934 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 4945 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp); reg 4947 drivers/gpu/drm/i915/display/intel_display.c POSTING_READ(reg); reg 5271 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg = TRANS_DP_CTL(pipe); reg 5274 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 5290 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp); reg 6599 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg; reg 6603 drivers/gpu/drm/i915/display/intel_display.c reg = TRANS_DP_CTL(pipe); reg 6604 drivers/gpu/drm/i915/display/intel_display.c temp = I915_READ(reg); reg 6608 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, temp); reg 9156 drivers/gpu/drm/i915/display/intel_display.c u32 reg, tmp; reg 9184 drivers/gpu/drm/i915/display/intel_display.c reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; reg 9185 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); reg 9187 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); reg 9195 drivers/gpu/drm/i915/display/intel_display.c u32 reg, tmp; reg 9199 drivers/gpu/drm/i915/display/intel_display.c reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; reg 9200 drivers/gpu/drm/i915/display/intel_display.c tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); reg 9202 drivers/gpu/drm/i915/display/intel_display.c intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); reg 16444 drivers/gpu/drm/i915/display/intel_display.c i915_reg_t reg = PIPECONF(cpu_transcoder); reg 16446 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(reg, reg 16447 drivers/gpu/drm/i915/display/intel_display.c I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); reg 17143 drivers/gpu/drm/i915/display/intel_display.c unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; reg 17146 drivers/gpu/drm/i915/display/intel_display.c if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { reg 17159 drivers/gpu/drm/i915/display/intel_display.c if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { reg 431 drivers/gpu/drm/i915/display/intel_display.h const char *name, u32 reg, int ref_freq); reg 433 drivers/gpu/drm/i915/display/intel_display.h const char *name, u32 reg); reg 341 drivers/gpu/drm/i915/display/intel_display_power.c if (regs->kvmr.reg) reg 1489 drivers/gpu/drm/i915/display/intel_display_power.c u32 reg, val, expected, actual; reg 1502 drivers/gpu/drm/i915/display/intel_display_power.c reg = _CHV_CMN_DW0_CH0; reg 1504 drivers/gpu/drm/i915/display/intel_display_power.c reg = _CHV_CMN_DW6_CH1; reg 1507 drivers/gpu/drm/i915/display/intel_display_power.c val = vlv_dpio_read(dev_priv, pipe, reg); reg 1544 drivers/gpu/drm/i915/display/intel_display_power.c reg, val); reg 4109 drivers/gpu/drm/i915/display/intel_display_power.c i915_reg_t reg, bool enable) reg 4113 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(reg); reg 4115 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(reg, val); reg 4116 drivers/gpu/drm/i915/display/intel_display_power.c POSTING_READ(reg); reg 4119 drivers/gpu/drm/i915/display/intel_display_power.c status = I915_READ(reg) & DBUF_POWER_STATE; reg 4468 drivers/gpu/drm/i915/display/intel_display_power.c i915_reg_t reg; reg 4472 drivers/gpu/drm/i915/display/intel_display_power.c reg = GEN7_MSG_CTL; reg 4475 drivers/gpu/drm/i915/display/intel_display_power.c reg = HSW_NDE_RSTWRN_OPT; reg 4479 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(reg); reg 4486 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(reg, val); reg 6704 drivers/gpu/drm/i915/display/intel_dp.c i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); reg 6707 drivers/gpu/drm/i915/display/intel_dp.c val = I915_READ(reg); reg 6719 drivers/gpu/drm/i915/display/intel_dp.c I915_WRITE(reg, val); reg 492 drivers/gpu/drm/i915/display/intel_dpio_phy.c i915_reg_t reg, u32 mask, u32 expected, reg 499 drivers/gpu/drm/i915/display/intel_dpio_phy.c val = I915_READ(reg); reg 509 drivers/gpu/drm/i915/display/intel_dpio_phy.c phy, &vaf, reg.reg, val, (val & ~mask) | expected, reg 526 drivers/gpu/drm/i915/display/intel_dpio_phy.c #define _CHK(reg, mask, exp, fmt, ...) \ reg 527 drivers/gpu/drm/i915/display/intel_dpio_phy.c __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \ reg 93 drivers/gpu/drm/i915/display/intel_fifo_underrun.c i915_reg_t reg = PIPESTAT(crtc->pipe); reg 98 drivers/gpu/drm/i915/display/intel_fifo_underrun.c if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) reg 102 drivers/gpu/drm/i915/display/intel_fifo_underrun.c I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); reg 103 drivers/gpu/drm/i915/display/intel_fifo_underrun.c POSTING_READ(reg); reg 114 drivers/gpu/drm/i915/display/intel_fifo_underrun.c i915_reg_t reg = PIPESTAT(pipe); reg 121 drivers/gpu/drm/i915/display/intel_fifo_underrun.c I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); reg 122 drivers/gpu/drm/i915/display/intel_fifo_underrun.c POSTING_READ(reg); reg 124 drivers/gpu/drm/i915/display/intel_fifo_underrun.c if (old && I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) reg 112 drivers/gpu/drm/i915/display/intel_hdcp.c u32 reg; reg 114 drivers/gpu/drm/i915/display/intel_hdcp.c reg = I915_READ(PORT_HDCP_STATUS(port)); reg 115 drivers/gpu/drm/i915/display/intel_hdcp.c return reg & HDCP_STATUS_ENC; reg 122 drivers/gpu/drm/i915/display/intel_hdcp.c u32 reg; reg 124 drivers/gpu/drm/i915/display/intel_hdcp.c reg = I915_READ(HDCP2_STATUS_DDI(port)); reg 125 drivers/gpu/drm/i915/display/intel_hdcp.c return reg & LINK_ENCRYPTION_STATUS; reg 583 drivers/gpu/drm/i915/display/intel_hdcp.c u32 reg[2]; reg 587 drivers/gpu/drm/i915/display/intel_hdcp.c u32 reg[2]; reg 591 drivers/gpu/drm/i915/display/intel_hdcp.c u32 reg; reg 628 drivers/gpu/drm/i915/display/intel_hdcp.c an.reg[0] = I915_READ(PORT_HDCP_ANLO(port)); reg 629 drivers/gpu/drm/i915/display/intel_hdcp.c an.reg[1] = I915_READ(PORT_HDCP_ANHI(port)); reg 647 drivers/gpu/drm/i915/display/intel_hdcp.c I915_WRITE(PORT_HDCP_BKSVLO(port), bksv.reg[0]); reg 648 drivers/gpu/drm/i915/display/intel_hdcp.c I915_WRITE(PORT_HDCP_BKSVHI(port), bksv.reg[1]); reg 688 drivers/gpu/drm/i915/display/intel_hdcp.c ri.reg = 0; reg 692 drivers/gpu/drm/i915/display/intel_hdcp.c I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg); reg 283 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); reg 284 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); reg 294 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); reg 308 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); reg 309 drivers/gpu/drm/i915/display/intel_hdmi.c POSTING_READ(reg); reg 338 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = TVIDEO_DIP_CTL(pipe); reg 339 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); reg 360 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); reg 361 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); reg 374 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); reg 388 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); reg 389 drivers/gpu/drm/i915/display/intel_hdmi.c POSTING_READ(reg); reg 436 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); reg 437 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); reg 447 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); reg 461 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); reg 462 drivers/gpu/drm/i915/display/intel_hdmi.c POSTING_READ(reg); reg 843 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = VIDEO_DIP_CTL; reg 844 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); reg 870 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); reg 871 drivers/gpu/drm/i915/display/intel_hdmi.c POSTING_READ(reg); reg 889 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); reg 890 drivers/gpu/drm/i915/display/intel_hdmi.c POSTING_READ(reg); reg 952 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg; reg 959 drivers/gpu/drm/i915/display/intel_hdmi.c reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); reg 961 drivers/gpu/drm/i915/display/intel_hdmi.c reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); reg 963 drivers/gpu/drm/i915/display/intel_hdmi.c reg = TVIDEO_DIP_GCP(crtc->pipe); reg 967 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, crtc_state->infoframes.gcp); reg 977 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg; reg 984 drivers/gpu/drm/i915/display/intel_hdmi.c reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); reg 986 drivers/gpu/drm/i915/display/intel_hdmi.c reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); reg 988 drivers/gpu/drm/i915/display/intel_hdmi.c reg = TVIDEO_DIP_GCP(crtc->pipe); reg 992 drivers/gpu/drm/i915/display/intel_hdmi.c crtc_state->infoframes.gcp = I915_READ(reg); reg 1026 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); reg 1027 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); reg 1041 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); reg 1042 drivers/gpu/drm/i915/display/intel_hdmi.c POSTING_READ(reg); reg 1062 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); reg 1063 drivers/gpu/drm/i915/display/intel_hdmi.c POSTING_READ(reg); reg 1084 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); reg 1085 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); reg 1098 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); reg 1099 drivers/gpu/drm/i915/display/intel_hdmi.c POSTING_READ(reg); reg 1111 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); reg 1112 drivers/gpu/drm/i915/display/intel_hdmi.c POSTING_READ(reg); reg 1133 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); reg 1134 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); reg 1148 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); reg 1149 drivers/gpu/drm/i915/display/intel_hdmi.c POSTING_READ(reg); reg 1169 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); reg 1170 drivers/gpu/drm/i915/display/intel_hdmi.c POSTING_READ(reg); reg 1189 drivers/gpu/drm/i915/display/intel_hdmi.c i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); reg 1190 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(reg); reg 1201 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); reg 1202 drivers/gpu/drm/i915/display/intel_hdmi.c POSTING_READ(reg); reg 1209 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, val); reg 1210 drivers/gpu/drm/i915/display/intel_hdmi.c POSTING_READ(reg); reg 1497 drivers/gpu/drm/i915/display/intel_hdmi.c u32 reg; reg 1505 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg); reg 300 drivers/gpu/drm/i915/display/intel_lspcon.c u16 reg; reg 310 drivers/gpu/drm/i915/display/intel_lspcon.c reg = LSPCON_PARADE_AVI_IF_WRITE_OFFSET; reg 312 drivers/gpu/drm/i915/display/intel_lspcon.c ret = drm_dp_dpcd_write(aux, reg, data, 8); reg 325 drivers/gpu/drm/i915/display/intel_lspcon.c reg = LSPCON_PARADE_AVI_IF_CTRL; reg 327 drivers/gpu/drm/i915/display/intel_lspcon.c ret = drm_dp_dpcd_write(aux, reg, &avi_if_ctrl, 1); reg 330 drivers/gpu/drm/i915/display/intel_lspcon.c reg, block_count); reg 379 drivers/gpu/drm/i915/display/intel_lspcon.c u16 reg; reg 382 drivers/gpu/drm/i915/display/intel_lspcon.c reg = LSPCON_MCA_AVI_IF_WRITE_OFFSET; reg 386 drivers/gpu/drm/i915/display/intel_lspcon.c ret = drm_dp_dpcd_write(aux, reg, (void *)data, 1); reg 393 drivers/gpu/drm/i915/display/intel_lspcon.c DRM_ERROR("DPCD write failed at:0x%x\n", reg); reg 397 drivers/gpu/drm/i915/display/intel_lspcon.c val++; reg++; data++; reg 401 drivers/gpu/drm/i915/display/intel_lspcon.c reg = LSPCON_MCA_AVI_IF_CTRL; reg 402 drivers/gpu/drm/i915/display/intel_lspcon.c ret = drm_dp_dpcd_read(aux, reg, &val, 1); reg 404 drivers/gpu/drm/i915/display/intel_lspcon.c DRM_ERROR("DPCD read failed, address 0x%x\n", reg); reg 412 drivers/gpu/drm/i915/display/intel_lspcon.c ret = drm_dp_dpcd_write(aux, reg, &val, 1); reg 414 drivers/gpu/drm/i915/display/intel_lspcon.c DRM_ERROR("DPCD read failed, address 0x%x\n", reg); reg 419 drivers/gpu/drm/i915/display/intel_lspcon.c ret = drm_dp_dpcd_read(aux, reg, &val, 1); reg 421 drivers/gpu/drm/i915/display/intel_lspcon.c DRM_ERROR("DPCD read failed, address 0x%x\n", reg); reg 69 drivers/gpu/drm/i915/display/intel_lvds.c i915_reg_t reg; reg 112 drivers/gpu/drm/i915/display/intel_lvds.c ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe); reg 128 drivers/gpu/drm/i915/display/intel_lvds.c tmp = I915_READ(lvds_encoder->reg); reg 302 drivers/gpu/drm/i915/display/intel_lvds.c I915_WRITE(lvds_encoder->reg, temp); reg 316 drivers/gpu/drm/i915/display/intel_lvds.c I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); reg 319 drivers/gpu/drm/i915/display/intel_lvds.c POSTING_READ(lvds_encoder->reg); reg 338 drivers/gpu/drm/i915/display/intel_lvds.c I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); reg 339 drivers/gpu/drm/i915/display/intel_lvds.c POSTING_READ(lvds_encoder->reg); reg 794 drivers/gpu/drm/i915/display/intel_lvds.c val = I915_READ(lvds_encoder->reg); reg 914 drivers/gpu/drm/i915/display/intel_lvds.c lvds_encoder->reg = lvds_reg; reg 679 drivers/gpu/drm/i915/display/intel_psr.c !regs[cpu_transcoder].reg)) reg 700 drivers/gpu/drm/i915/display/intel_psr.c i915_reg_t reg = gen9_chicken_trans_reg(dev_priv, reg 702 drivers/gpu/drm/i915/display/intel_psr.c u32 chicken = I915_READ(reg); reg 706 drivers/gpu/drm/i915/display/intel_psr.c I915_WRITE(reg, chicken); reg 974 drivers/gpu/drm/i915/display/intel_psr.c i915_reg_t reg; reg 982 drivers/gpu/drm/i915/display/intel_psr.c reg = EDP_PSR2_STATUS; reg 985 drivers/gpu/drm/i915/display/intel_psr.c reg = EDP_PSR_STATUS; reg 991 drivers/gpu/drm/i915/display/intel_psr.c err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); reg 21 drivers/gpu/drm/i915/display/intel_sdvo.h i915_reg_t reg, enum port port); reg 93 drivers/gpu/drm/i915/display/vlv_dsi.c i915_reg_t reg, reg 104 drivers/gpu/drm/i915/display/vlv_dsi.c I915_WRITE(reg, val); reg 109 drivers/gpu/drm/i915/display/vlv_dsi.c i915_reg_t reg, reg 115 drivers/gpu/drm/i915/display/vlv_dsi.c u32 val = I915_READ(reg); reg 157 drivers/gpu/drm/i915/gt/intel_engine.h intel_read_status_page(const struct intel_engine_cs *engine, int reg) reg 160 drivers/gpu/drm/i915/gt/intel_engine.h return READ_ONCE(engine->status_page.addr[reg]); reg 164 drivers/gpu/drm/i915/gt/intel_engine.h intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) reg 173 drivers/gpu/drm/i915/gt/intel_engine.h clflush(&engine->status_page.addr[reg]); reg 174 drivers/gpu/drm/i915/gt/intel_engine.h engine->status_page.addr[reg] = value; reg 175 drivers/gpu/drm/i915/gt/intel_engine.h clflush(&engine->status_page.addr[reg]); reg 178 drivers/gpu/drm/i915/gt/intel_engine.h WRITE_ONCE(engine->status_page.addr[reg], value); reg 903 drivers/gpu/drm/i915/gt/intel_engine_cs.c i915_reg_t reg) reg 918 drivers/gpu/drm/i915/gt/intel_engine_cs.c fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, reg 933 drivers/gpu/drm/i915/gt/intel_engine_cs.c val = intel_uncore_read_fw(uncore, reg); reg 32 drivers/gpu/drm/i915/gt/intel_gt.c static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set) reg 34 drivers/gpu/drm/i915/gt/intel_gt.c intel_uncore_rmw(uncore, reg, 0, set); reg 37 drivers/gpu/drm/i915/gt/intel_gt.c static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr) reg 39 drivers/gpu/drm/i915/gt/intel_gt.c intel_uncore_rmw(uncore, reg, clr, 0); reg 42 drivers/gpu/drm/i915/gt/intel_gt.c static void clear_register(struct intel_uncore *uncore, i915_reg_t reg) reg 44 drivers/gpu/drm/i915/gt/intel_gt.c intel_uncore_rmw(uncore, reg, 0, 0); reg 18 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c i915_reg_t reg; reg 21 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c reg = GEN11_GPM_WGBOXPERF_INTR_MASK; reg 24 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c reg = GEN8_GT_IMR(2); reg 26 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c reg = GEN6_PMIMR; reg 29 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c intel_uncore_write(uncore, reg, mask); reg 65 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c i915_reg_t reg = INTEL_GEN(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; reg 69 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c intel_uncore_write(uncore, reg, reset_mask); reg 70 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c intel_uncore_write(uncore, reg, reset_mask); reg 71 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c intel_uncore_posting_read(uncore, reg); reg 79 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c i915_reg_t reg; reg 82 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE; reg 85 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c reg = GEN8_GT_IER(2); reg 87 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c reg = GEN6_PMIER; reg 90 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c intel_uncore_write(uncore, reg, mask); reg 2088 drivers/gpu/drm/i915/gt/intel_lrc.c i915_reg_t reg; reg 2098 drivers/gpu/drm/i915/gt/intel_lrc.c *batch++ = i915_mmio_reg_offset(lri->reg); reg 42 drivers/gpu/drm/i915/gt/intel_lrc_reg.h #define CTX_REG(reg_state, pos, reg, val) do { \ reg 45 drivers/gpu/drm/i915/gt/intel_lrc_reg.h (reg_state__)[(pos__) + 0] = i915_mmio_reg_offset(reg); \ reg 30 drivers/gpu/drm/i915/gt/intel_reset.c static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set) reg 32 drivers/gpu/drm/i915/gt/intel_reset.c intel_uncore_rmw_fw(uncore, reg, 0, set); reg 35 drivers/gpu/drm/i915/gt/intel_reset.c static void rmw_clear_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 clr) reg 37 drivers/gpu/drm/i915/gt/intel_reset.c intel_uncore_rmw_fw(uncore, reg, clr, 0); reg 447 drivers/gpu/drm/i915/gt/intel_reset.c const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base); reg 451 drivers/gpu/drm/i915/gt/intel_reset.c ack = intel_uncore_read_fw(uncore, reg); reg 470 drivers/gpu/drm/i915/gt/intel_reset.c intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request)); reg 471 drivers/gpu/drm/i915/gt/intel_reset.c ret = __intel_wait_for_register_fw(uncore, reg, mask, ack, reg 476 drivers/gpu/drm/i915/gt/intel_reset.c intel_uncore_read_fw(uncore, reg)); reg 84 drivers/gpu/drm/i915/gt/intel_workarounds.c unsigned int addr = i915_mmio_reg_offset(wa->reg); reg 110 drivers/gpu/drm/i915/gt/intel_workarounds.c if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { reg 112 drivers/gpu/drm/i915/gt/intel_workarounds.c } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { reg 119 drivers/gpu/drm/i915/gt/intel_workarounds.c i915_mmio_reg_offset(wa_->reg), reg 138 drivers/gpu/drm/i915/gt/intel_workarounds.c GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == reg 139 drivers/gpu/drm/i915/gt/intel_workarounds.c i915_mmio_reg_offset(wa_[1].reg)); reg 140 drivers/gpu/drm/i915/gt/intel_workarounds.c if (i915_mmio_reg_offset(wa_[1].reg) > reg 141 drivers/gpu/drm/i915/gt/intel_workarounds.c i915_mmio_reg_offset(wa_[0].reg)) reg 149 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, reg 153 drivers/gpu/drm/i915/gt/intel_workarounds.c .reg = reg, reg 163 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) reg 165 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write_masked_or(wal, reg, val, _MASKED_BIT_ENABLE(val)); reg 169 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val) reg 171 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write_masked_or(wal, reg, ~0, val); reg 175 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val) reg 177 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write_masked_or(wal, reg, val, val); reg 638 drivers/gpu/drm/i915/gt/intel_workarounds.c *cs++ = i915_mmio_reg_offset(wa->reg); reg 943 drivers/gpu/drm/i915/gt/intel_workarounds.c wa->reg, reg 955 drivers/gpu/drm/i915/gt/intel_workarounds.c name, from, i915_mmio_reg_offset(wa->reg), reg 982 drivers/gpu/drm/i915/gt/intel_workarounds.c intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val); reg 985 drivers/gpu/drm/i915/gt/intel_workarounds.c intel_uncore_read_fw(uncore, wa->reg), reg 1008 drivers/gpu/drm/i915/gt/intel_workarounds.c intel_uncore_read(uncore, wa->reg), reg 1034 drivers/gpu/drm/i915/gt/intel_workarounds.c whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) reg 1037 drivers/gpu/drm/i915/gt/intel_workarounds.c .reg = reg reg 1046 drivers/gpu/drm/i915/gt/intel_workarounds.c wa.reg.reg |= flags; reg 1051 drivers/gpu/drm/i915/gt/intel_workarounds.c whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) reg 1053 drivers/gpu/drm/i915/gt/intel_workarounds.c whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); reg 1247 drivers/gpu/drm/i915/gt/intel_workarounds.c i915_mmio_reg_offset(wa->reg)); reg 1476 drivers/gpu/drm/i915/gt/intel_workarounds.c if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) reg 1485 drivers/gpu/drm/i915/gt/intel_workarounds.c u32 offset = i915_mmio_reg_offset(wa->reg); reg 1542 drivers/gpu/drm/i915/gt/intel_workarounds.c if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg))) reg 15 drivers/gpu/drm/i915/gt/intel_workarounds_types.h i915_reg_t reg; reg 23 drivers/gpu/drm/i915/gt/selftest_workarounds.c u32 reg; reg 158 drivers/gpu/drm/i915/gt/selftest_workarounds.c i915_reg_t reg = i < engine->whitelist.count ? reg 159 drivers/gpu/drm/i915/gt/selftest_workarounds.c engine->whitelist.list[i].reg : reg 162 drivers/gpu/drm/i915/gt/selftest_workarounds.c return i915_mmio_reg_offset(reg); reg 395 drivers/gpu/drm/i915/gt/selftest_workarounds.c static bool wo_register(struct intel_engine_cs *engine, u32 reg) reg 400 drivers/gpu/drm/i915/gt/selftest_workarounds.c if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == reg 406 drivers/gpu/drm/i915/gt/selftest_workarounds.c wo_registers[i].reg == reg) reg 413 drivers/gpu/drm/i915/gt/selftest_workarounds.c static bool ro_register(u32 reg) reg 415 drivers/gpu/drm/i915/gt/selftest_workarounds.c if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == reg 428 drivers/gpu/drm/i915/gt/selftest_workarounds.c u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); reg 430 drivers/gpu/drm/i915/gt/selftest_workarounds.c if (ro_register(reg)) reg 482 drivers/gpu/drm/i915/gt/selftest_workarounds.c u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); reg 490 drivers/gpu/drm/i915/gt/selftest_workarounds.c if (wo_register(engine, reg)) reg 493 drivers/gpu/drm/i915/gt/selftest_workarounds.c ro_reg = ro_register(reg); reg 501 drivers/gpu/drm/i915/gt/selftest_workarounds.c engine->name, reg); reg 511 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = reg; reg 519 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = reg; reg 524 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = reg; reg 532 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = reg; reg 537 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = reg; reg 546 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = reg; reg 581 drivers/gpu/drm/i915/gt/selftest_workarounds.c engine->name, reg); reg 599 drivers/gpu/drm/i915/gt/selftest_workarounds.c engine->name, reg); reg 629 drivers/gpu/drm/i915/gt/selftest_workarounds.c engine->name, err, reg); reg 633 drivers/gpu/drm/i915/gt/selftest_workarounds.c engine->name, reg, results[0]); reg 636 drivers/gpu/drm/i915/gt/selftest_workarounds.c engine->name, reg, results[0], rsvd); reg 787 drivers/gpu/drm/i915/gt/selftest_workarounds.c u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); reg 790 drivers/gpu/drm/i915/gt/selftest_workarounds.c reg &= ~RING_FORCE_TO_NONPRIV_ACCESS_MASK; reg 793 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = reg; reg 828 drivers/gpu/drm/i915/gt/selftest_workarounds.c u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); reg 830 drivers/gpu/drm/i915/gt/selftest_workarounds.c if (ro_register(reg)) reg 833 drivers/gpu/drm/i915/gt/selftest_workarounds.c *cs++ = reg; reg 869 drivers/gpu/drm/i915/gt/selftest_workarounds.c i915_reg_t reg; reg 874 drivers/gpu/drm/i915/gt/selftest_workarounds.c i915_reg_t reg, reg 878 drivers/gpu/drm/i915/gt/selftest_workarounds.c u32 offset = i915_mmio_reg_offset(reg); reg 882 drivers/gpu/drm/i915/gt/selftest_workarounds.c i915_mmio_reg_offset(tbl->reg) == offset) reg 890 drivers/gpu/drm/i915/gt/selftest_workarounds.c static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg) reg 898 drivers/gpu/drm/i915/gt/selftest_workarounds.c return find_reg(i915, reg, pardon, ARRAY_SIZE(pardon)); reg 902 drivers/gpu/drm/i915/gt/selftest_workarounds.c u32 a, u32 b, i915_reg_t reg) reg 904 drivers/gpu/drm/i915/gt/selftest_workarounds.c if (a != b && !pardon_reg(engine->i915, reg)) { reg 906 drivers/gpu/drm/i915/gt/selftest_workarounds.c i915_mmio_reg_offset(reg), a, b); reg 913 drivers/gpu/drm/i915/gt/selftest_workarounds.c static bool writeonly_reg(struct drm_i915_private *i915, i915_reg_t reg) reg 920 drivers/gpu/drm/i915/gt/selftest_workarounds.c return find_reg(i915, reg, wo, ARRAY_SIZE(wo)); reg 924 drivers/gpu/drm/i915/gt/selftest_workarounds.c u32 a, u32 b, i915_reg_t reg) reg 926 drivers/gpu/drm/i915/gt/selftest_workarounds.c if (a == b && !writeonly_reg(engine->i915, reg)) { reg 928 drivers/gpu/drm/i915/gt/selftest_workarounds.c i915_mmio_reg_offset(reg), a); reg 941 drivers/gpu/drm/i915/gt/selftest_workarounds.c i915_reg_t reg)) reg 960 drivers/gpu/drm/i915/gt/selftest_workarounds.c if (i915_mmio_reg_offset(wa->reg) & reg 964 drivers/gpu/drm/i915/gt/selftest_workarounds.c if (!fn(engine, a[i], b[i], wa->reg)) reg 19 drivers/gpu/drm/i915/gt/uc/intel_huc.c huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO; reg 23 drivers/gpu/drm/i915/gt/uc/intel_huc.c huc->status.reg = HUC_STATUS2; reg 150 drivers/gpu/drm/i915/gt/uc/intel_huc.c huc->status.reg, reg 189 drivers/gpu/drm/i915/gt/uc/intel_huc.c status = intel_uncore_read(gt->uncore, huc->status.reg); reg 21 drivers/gpu/drm/i915/gt/uc/intel_huc.h i915_reg_t reg; reg 132 drivers/gpu/drm/i915/gvt/aperture_gm.c struct i915_fence_reg *reg; reg 140 drivers/gpu/drm/i915/gvt/aperture_gm.c reg = vgpu->fence.regs[fence]; reg 141 drivers/gpu/drm/i915/gvt/aperture_gm.c if (WARN_ON(!reg)) reg 144 drivers/gpu/drm/i915/gvt/aperture_gm.c fence_reg_lo = FENCE_REG_GEN6_LO(reg->id); reg 145 drivers/gpu/drm/i915/gvt/aperture_gm.c fence_reg_hi = FENCE_REG_GEN6_HI(reg->id); reg 167 drivers/gpu/drm/i915/gvt/aperture_gm.c struct i915_fence_reg *reg; reg 178 drivers/gpu/drm/i915/gvt/aperture_gm.c reg = vgpu->fence.regs[i]; reg 179 drivers/gpu/drm/i915/gvt/aperture_gm.c i915_unreserve_fence(reg); reg 192 drivers/gpu/drm/i915/gvt/aperture_gm.c struct i915_fence_reg *reg; reg 201 drivers/gpu/drm/i915/gvt/aperture_gm.c reg = i915_reserve_fence(dev_priv); reg 202 drivers/gpu/drm/i915/gvt/aperture_gm.c if (IS_ERR(reg)) reg 205 drivers/gpu/drm/i915/gvt/aperture_gm.c vgpu->fence.regs[i] = reg; reg 217 drivers/gpu/drm/i915/gvt/aperture_gm.c reg = vgpu->fence.regs[i]; reg 218 drivers/gpu/drm/i915/gvt/aperture_gm.c if (!reg) reg 220 drivers/gpu/drm/i915/gvt/aperture_gm.c i915_unreserve_fence(reg); reg 429 drivers/gpu/drm/i915/gvt/edid.c int reg; reg 433 drivers/gpu/drm/i915/gvt/edid.c reg = AUX_CH_CTL; reg 436 drivers/gpu/drm/i915/gvt/edid.c reg = AUX_CH_DATA1; reg 439 drivers/gpu/drm/i915/gvt/edid.c reg = AUX_CH_DATA2; reg 442 drivers/gpu/drm/i915/gvt/edid.c reg = AUX_CH_DATA3; reg 445 drivers/gpu/drm/i915/gvt/edid.c reg = AUX_CH_DATA4; reg 448 drivers/gpu/drm/i915/gvt/edid.c reg = AUX_CH_DATA5; reg 451 drivers/gpu/drm/i915/gvt/edid.c reg = -1; reg 454 drivers/gpu/drm/i915/gvt/edid.c return reg; reg 457 drivers/gpu/drm/i915/gvt/edid.c #define AUX_CTL_MSG_LENGTH(reg) \ reg 458 drivers/gpu/drm/i915/gvt/edid.c ((reg & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> \ reg 481 drivers/gpu/drm/i915/gvt/edid.c int reg = get_aux_ch_reg(offset); reg 483 drivers/gpu/drm/i915/gvt/edid.c if (reg != AUX_CH_CTL) { reg 445 drivers/gpu/drm/i915/gvt/gvt.h #define vgpu_vreg_t(vgpu, reg) \ reg 446 drivers/gpu/drm/i915/gvt/gvt.h (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) reg 449 drivers/gpu/drm/i915/gvt/gvt.h #define vgpu_vreg64_t(vgpu, reg) \ reg 450 drivers/gpu/drm/i915/gvt/gvt.h (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) reg 490 drivers/gpu/drm/i915/gvt/handlers.c static inline bool in_whitelist(unsigned int reg) reg 498 drivers/gpu/drm/i915/gvt/handlers.c if (reg > array[mid].reg) reg 500 drivers/gpu/drm/i915/gvt/handlers.c else if (reg < array[mid].reg) reg 817 drivers/gpu/drm/i915/gvt/handlers.c unsigned int reg) reg 822 drivers/gpu/drm/i915/gvt/handlers.c if (reg == _DPA_AUX_CH_CTL) reg 824 drivers/gpu/drm/i915/gvt/handlers.c else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL) reg 826 drivers/gpu/drm/i915/gvt/handlers.c else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL) reg 828 drivers/gpu/drm/i915/gvt/handlers.c else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL) reg 840 drivers/gpu/drm/i915/gvt/handlers.c unsigned int reg, int len, bool data_valid) reg 855 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg(vgpu, reg) = value; reg 858 drivers/gpu/drm/i915/gvt/handlers.c return trigger_aux_channel_interrupt(vgpu, reg); reg 1810 drivers/gpu/drm/i915/gvt/handlers.c #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ reg 1811 drivers/gpu/drm/i915/gvt/handlers.c ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \ reg 1817 drivers/gpu/drm/i915/gvt/handlers.c #define MMIO_D(reg, d) \ reg 1818 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) reg 1820 drivers/gpu/drm/i915/gvt/handlers.c #define MMIO_DH(reg, d, r, w) \ reg 1821 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(reg, 4, 0, 0, 0, d, r, w) reg 1823 drivers/gpu/drm/i915/gvt/handlers.c #define MMIO_DFH(reg, d, f, r, w) \ reg 1824 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(reg, 4, f, 0, 0, d, r, w) reg 1826 drivers/gpu/drm/i915/gvt/handlers.c #define MMIO_GM(reg, d, r, w) \ reg 1827 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) reg 1829 drivers/gpu/drm/i915/gvt/handlers.c #define MMIO_GM_RDR(reg, d, r, w) \ reg 1830 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) reg 1832 drivers/gpu/drm/i915/gvt/handlers.c #define MMIO_RO(reg, d, f, rm, r, w) \ reg 1833 drivers/gpu/drm/i915/gvt/handlers.c MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) reg 148 drivers/gpu/drm/i915/gvt/interrupt.c unsigned int reg) reg 154 drivers/gpu/drm/i915/gvt/interrupt.c if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) reg 176 drivers/gpu/drm/i915/gvt/interrupt.c unsigned int reg, void *p_data, unsigned int bytes) reg 182 drivers/gpu/drm/i915/gvt/interrupt.c trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg), reg 183 drivers/gpu/drm/i915/gvt/interrupt.c (vgpu_vreg(vgpu, reg) ^ imr)); reg 185 drivers/gpu/drm/i915/gvt/interrupt.c vgpu_vreg(vgpu, reg) = imr; reg 206 drivers/gpu/drm/i915/gvt/interrupt.c unsigned int reg, void *p_data, unsigned int bytes) reg 211 drivers/gpu/drm/i915/gvt/interrupt.c u32 virtual_ier = vgpu_vreg(vgpu, reg); reg 213 drivers/gpu/drm/i915/gvt/interrupt.c trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier, reg 223 drivers/gpu/drm/i915/gvt/interrupt.c vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL; reg 224 drivers/gpu/drm/i915/gvt/interrupt.c vgpu_vreg(vgpu, reg) |= ier; reg 245 drivers/gpu/drm/i915/gvt/interrupt.c unsigned int reg, void *p_data, unsigned int bytes) reg 252 drivers/gpu/drm/i915/gvt/interrupt.c trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg), reg 253 drivers/gpu/drm/i915/gvt/interrupt.c (vgpu_vreg(vgpu, reg) ^ ier)); reg 255 drivers/gpu/drm/i915/gvt/interrupt.c vgpu_vreg(vgpu, reg) = ier; reg 257 drivers/gpu/drm/i915/gvt/interrupt.c info = regbase_to_irq_info(gvt, ier_to_regbase(reg)); reg 282 drivers/gpu/drm/i915/gvt/interrupt.c int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg, reg 286 drivers/gpu/drm/i915/gvt/interrupt.c iir_to_regbase(reg)); reg 289 drivers/gpu/drm/i915/gvt/interrupt.c trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg), reg 290 drivers/gpu/drm/i915/gvt/interrupt.c (vgpu_vreg(vgpu, reg) ^ iir)); reg 295 drivers/gpu/drm/i915/gvt/interrupt.c vgpu_vreg(vgpu, reg) &= ~iir; reg 220 drivers/gpu/drm/i915/gvt/interrupt.h int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg, reg 223 drivers/gpu/drm/i915/gvt/interrupt.h unsigned int reg, void *p_data, unsigned int bytes); reg 225 drivers/gpu/drm/i915/gvt/interrupt.h unsigned int reg, void *p_data, unsigned int bytes); reg 227 drivers/gpu/drm/i915/gvt/interrupt.h unsigned int reg, void *p_data, unsigned int bytes); reg 53 drivers/gpu/drm/i915/gvt/mmio.c #define reg_is_mmio(gvt, reg) \ reg 54 drivers/gpu/drm/i915/gvt/mmio.c (reg >= 0 && reg < gvt->device_info.mmio_size) reg 56 drivers/gpu/drm/i915/gvt/mmio.c #define reg_is_gtt(gvt, reg) \ reg 57 drivers/gpu/drm/i915/gvt/mmio.c (reg >= gvt->device_info.gtt_start_offset \ reg 58 drivers/gpu/drm/i915/gvt/mmio.c && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) reg 71 drivers/gpu/drm/i915/gvt/mmio.h unsigned int reg); reg 174 drivers/gpu/drm/i915/gvt/mmio_context.c offset.reg = regs[ring_id]; reg 178 drivers/gpu/drm/i915/gvt/mmio_context.c offset.reg += 4; reg 182 drivers/gpu/drm/i915/gvt/mmio_context.c offset.reg = 0xb020; reg 186 drivers/gpu/drm/i915/gvt/mmio_context.c offset.reg += 4; reg 215 drivers/gpu/drm/i915/gvt/mmio_context.c i915_mmio_reg_valid(mmio->reg); mmio++) { reg 220 drivers/gpu/drm/i915/gvt/mmio_context.c *cs++ = i915_mmio_reg_offset(mmio->reg); reg 221 drivers/gpu/drm/i915/gvt/mmio_context.c *cs++ = vgpu_vreg_t(vgpu, mmio->reg) | reg 354 drivers/gpu/drm/i915/gvt/mmio_context.c i915_reg_t reg; reg 365 drivers/gpu/drm/i915/gvt/mmio_context.c reg = _MMIO(regs[ring_id]); reg 372 drivers/gpu/drm/i915/gvt/mmio_context.c fw = intel_uncore_forcewake_for_reg(uncore, reg, reg 379 drivers/gpu/drm/i915/gvt/mmio_context.c intel_uncore_write_fw(uncore, reg, 0x1); reg 381 drivers/gpu/drm/i915/gvt/mmio_context.c if (wait_for_atomic((intel_uncore_read_fw(uncore, reg) == 0), 50)) reg 384 drivers/gpu/drm/i915/gvt/mmio_context.c vgpu_vreg_t(vgpu, reg) = 0; reg 417 drivers/gpu/drm/i915/gvt/mmio_context.c offset.reg = regs[ring_id]; reg 431 drivers/gpu/drm/i915/gvt/mmio_context.c offset.reg += 4; reg 435 drivers/gpu/drm/i915/gvt/mmio_context.c l3_offset.reg = 0xb020; reg 449 drivers/gpu/drm/i915/gvt/mmio_context.c l3_offset.reg += 4; reg 481 drivers/gpu/drm/i915/gvt/mmio_context.c i915_mmio_reg_valid(mmio->reg); mmio++) { reg 494 drivers/gpu/drm/i915/gvt/mmio_context.c vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg); reg 496 drivers/gpu/drm/i915/gvt/mmio_context.c vgpu_vreg_t(pre, mmio->reg) &= reg 498 drivers/gpu/drm/i915/gvt/mmio_context.c old_v = vgpu_vreg_t(pre, mmio->reg); reg 500 drivers/gpu/drm/i915/gvt/mmio_context.c old_v = mmio->value = I915_READ_FW(mmio->reg); reg 515 drivers/gpu/drm/i915/gvt/mmio_context.c new_v = vgpu_vreg_t(next, mmio->reg) | reg 518 drivers/gpu/drm/i915/gvt/mmio_context.c new_v = vgpu_vreg_t(next, mmio->reg); reg 528 drivers/gpu/drm/i915/gvt/mmio_context.c I915_WRITE_FW(mmio->reg, new_v); reg 533 drivers/gpu/drm/i915/gvt/mmio_context.c i915_mmio_reg_offset(mmio->reg), reg 595 drivers/gpu/drm/i915/gvt/mmio_context.c i915_mmio_reg_valid(mmio->reg); mmio++) { reg 598 drivers/gpu/drm/i915/gvt/mmio_context.c intel_gvt_mmio_set_in_ctx(gvt, mmio->reg.reg); reg 41 drivers/gpu/drm/i915/gvt/mmio_context.h i915_reg_t reg; reg 81 drivers/gpu/drm/i915/gvt/reg.h typeof(_reg) (reg) = (_reg); \ reg 82 drivers/gpu/drm/i915/gvt/reg.h (((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \ reg 83 drivers/gpu/drm/i915/gvt/reg.h (((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \ reg 84 drivers/gpu/drm/i915/gvt/reg.h (((reg) == 0x5008C || (reg) == 0x5009C) ? (PIPE_C) : \ reg 88 drivers/gpu/drm/i915/gvt/reg.h typeof(_reg) (reg) = (_reg); \ reg 89 drivers/gpu/drm/i915/gvt/reg.h (((reg) == 0x50080 || (reg) == 0x50088 || (reg) == 0x5008C) ? \ reg 91 drivers/gpu/drm/i915/gvt/reg.h (((reg) == 0x50090 || (reg) == 0x50098 || (reg) == 0x5009C) ? \ reg 216 drivers/gpu/drm/i915/gvt/scheduler.c i915_reg_t reg; reg 218 drivers/gpu/drm/i915/gvt/scheduler.c reg = RING_INSTDONE(ring_base); reg 219 drivers/gpu/drm/i915/gvt/scheduler.c vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); reg 220 drivers/gpu/drm/i915/gvt/scheduler.c reg = RING_ACTHD(ring_base); reg 221 drivers/gpu/drm/i915/gvt/scheduler.c vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); reg 222 drivers/gpu/drm/i915/gvt/scheduler.c reg = RING_ACTHD_UDW(ring_base); reg 223 drivers/gpu/drm/i915/gvt/scheduler.c vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); reg 276 drivers/gpu/drm/i915/gvt/trace.h TP_PROTO(int id, char *reg_name, unsigned int reg, unsigned int new_val, reg 279 drivers/gpu/drm/i915/gvt/trace.h TP_ARGS(id, reg_name, reg, new_val, old_val, changed), reg 284 drivers/gpu/drm/i915/gvt/trace.h __field(unsigned int, reg) reg 293 drivers/gpu/drm/i915/gvt/trace.h __entry->reg = reg; reg 300 drivers/gpu/drm/i915/gvt/trace.h __entry->id, __entry->buf, __entry->reg, __entry->new_val, reg 347 drivers/gpu/drm/i915/gvt/trace.h TP_PROTO(int old_id, int new_id, char *action, unsigned int reg, reg 350 drivers/gpu/drm/i915/gvt/trace.h TP_ARGS(old_id, new_id, action, reg, old_val, new_val), reg 356 drivers/gpu/drm/i915/gvt/trace.h __field(unsigned int, reg) reg 365 drivers/gpu/drm/i915/gvt/trace.h __entry->reg = reg; reg 372 drivers/gpu/drm/i915/gvt/trace.h __entry->buf, __entry->reg, reg 148 drivers/gpu/drm/i915/i915_cmd_parser.c } reg; reg 220 drivers/gpu/drm/i915/i915_cmd_parser.c .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), reg 222 drivers/gpu/drm/i915/i915_cmd_parser.c .reg = { .offset = 1, .mask = 0x007FFFFC }, reg 229 drivers/gpu/drm/i915/i915_cmd_parser.c .reg = { .offset = 1, .mask = 0x007FFFFC }, reg 313 drivers/gpu/drm/i915/i915_cmd_parser.c .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ), reg 477 drivers/gpu/drm/i915/i915_cmd_parser.c .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), reg 480 drivers/gpu/drm/i915/i915_cmd_parser.c .reg = { .offset = 1, .mask = 0x007FFFFC } ), reg 483 drivers/gpu/drm/i915/i915_cmd_parser.c .reg = { .offset = 1, .mask = 0x007FFFFC } ), reg 485 drivers/gpu/drm/i915/i915_cmd_parser.c .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ), reg 1118 drivers/gpu/drm/i915/i915_cmd_parser.c const struct drm_i915_reg_descriptor *reg = NULL; reg 1121 drivers/gpu/drm/i915/i915_cmd_parser.c for (; !reg && (count > 0); ++table, --count) reg 1122 drivers/gpu/drm/i915/i915_cmd_parser.c reg = __find_reg(table->regs, table->num_regs, addr); reg 1124 drivers/gpu/drm/i915/i915_cmd_parser.c return reg; reg 1224 drivers/gpu/drm/i915/i915_cmd_parser.c const u32 step = desc->reg.step ? desc->reg.step : length; reg 1227 drivers/gpu/drm/i915/i915_cmd_parser.c for (offset = desc->reg.offset; offset < length; reg 1229 drivers/gpu/drm/i915/i915_cmd_parser.c const u32 reg_addr = cmd[offset] & desc->reg.mask; reg 1230 drivers/gpu/drm/i915/i915_cmd_parser.c const struct drm_i915_reg_descriptor *reg = reg 1233 drivers/gpu/drm/i915/i915_cmd_parser.c if (!reg) { reg 1243 drivers/gpu/drm/i915/i915_cmd_parser.c if (reg->mask) { reg 1258 drivers/gpu/drm/i915/i915_cmd_parser.c (cmd[offset + 1] & reg->mask) != reg->value)) { reg 655 drivers/gpu/drm/i915/i915_debugfs.c struct i915_fence_reg *reg = &i915->ggtt.fence_regs[i]; reg 656 drivers/gpu/drm/i915/i915_debugfs.c struct i915_vma *vma = reg->vma; reg 659 drivers/gpu/drm/i915/i915_debugfs.c i, atomic_read(®->pin_count)); reg 1158 drivers/gpu/drm/i915/i915_debugfs.c const i915_reg_t reg) reg 1163 drivers/gpu/drm/i915/i915_debugfs.c title, I915_READ(reg), reg 1164 drivers/gpu/drm/i915/i915_debugfs.c intel_rc6_residency_us(dev_priv, reg)); reg 1361 drivers/gpu/drm/i915/i915_debugfs.c u32 reg; reg 1368 drivers/gpu/drm/i915/i915_debugfs.c reg = I915_READ(ILK_DPFC_CONTROL); reg 1372 drivers/gpu/drm/i915/i915_debugfs.c (reg | FBC_CTL_FALSE_COLOR) : reg 1373 drivers/gpu/drm/i915/i915_debugfs.c (reg & ~FBC_CTL_FALSE_COLOR)); reg 2407 drivers/gpu/drm/i915/i915_debugfs.c if (dc6_reg.reg) reg 2892 drivers/gpu/drm/i915/i915_debugfs.c i915_mmio_reg_offset(wa->reg), reg 162 drivers/gpu/drm/i915/i915_drv.c int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; reg 168 drivers/gpu/drm/i915/i915_drv.c pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); reg 169 drivers/gpu/drm/i915/i915_drv.c pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); reg 195 drivers/gpu/drm/i915/i915_drv.c pci_write_config_dword(dev_priv->bridge_dev, reg + 4, reg 198 drivers/gpu/drm/i915/i915_drv.c pci_write_config_dword(dev_priv->bridge_dev, reg, reg 2419 drivers/gpu/drm/i915/i915_drv.c i915_reg_t reg = VLV_GTLC_PW_STATUS; reg 2431 drivers/gpu/drm/i915/i915_drv.c intel_uncore_read_notrace(&i915->uncore, reg)) & mask) reg 2435 drivers/gpu/drm/i915/i915_drv.c trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true); reg 868 drivers/gpu/drm/i915/i915_gem.c struct i915_fence_reg *reg = &i915->ggtt.fence_regs[i]; reg 882 drivers/gpu/drm/i915/i915_gem.c if (!reg->vma) reg 885 drivers/gpu/drm/i915/i915_gem.c GEM_BUG_ON(i915_vma_has_userfault(reg->vma)); reg 886 drivers/gpu/drm/i915/i915_gem.c reg->dirty = true; reg 152 drivers/gpu/drm/i915/i915_gem_fence_reg.c i915_reg_t reg = FENCE_REG(fence->id); reg 154 drivers/gpu/drm/i915/i915_gem_fence_reg.c intel_uncore_write_fw(uncore, reg, val); reg 155 drivers/gpu/drm/i915/i915_gem_fence_reg.c intel_uncore_posting_read_fw(uncore, reg); reg 184 drivers/gpu/drm/i915/i915_gem_fence_reg.c i915_reg_t reg = FENCE_REG(fence->id); reg 186 drivers/gpu/drm/i915/i915_gem_fence_reg.c intel_uncore_write_fw(uncore, reg, val); reg 187 drivers/gpu/drm/i915/i915_gem_fence_reg.c intel_uncore_posting_read_fw(uncore, reg); reg 484 drivers/gpu/drm/i915/i915_gem_fence_reg.c struct i915_fence_reg *reg = &i915->ggtt.fence_regs[i]; reg 485 drivers/gpu/drm/i915/i915_gem_fence_reg.c struct i915_vma *vma = READ_ONCE(reg->vma); reg 487 drivers/gpu/drm/i915/i915_gem_fence_reg.c GEM_BUG_ON(vma && vma->fence != reg); reg 496 drivers/gpu/drm/i915/i915_gem_fence_reg.c fence_write(reg, vma); reg 210 drivers/gpu/drm/i915/i915_irq.c static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg) reg 212 drivers/gpu/drm/i915/i915_irq.c u32 val = intel_uncore_read(uncore, reg); reg 218 drivers/gpu/drm/i915/i915_irq.c i915_mmio_reg_offset(reg), val); reg 219 drivers/gpu/drm/i915/i915_irq.c intel_uncore_write(uncore, reg, 0xffffffff); reg 220 drivers/gpu/drm/i915/i915_irq.c intel_uncore_posting_read(uncore, reg); reg 221 drivers/gpu/drm/i915/i915_irq.c intel_uncore_write(uncore, reg, 0xffffffff); reg 222 drivers/gpu/drm/i915/i915_irq.c intel_uncore_posting_read(uncore, reg); reg 637 drivers/gpu/drm/i915/i915_irq.c i915_reg_t reg = PIPESTAT(pipe); reg 653 drivers/gpu/drm/i915/i915_irq.c I915_WRITE(reg, enable_mask | status_mask); reg 654 drivers/gpu/drm/i915/i915_irq.c POSTING_READ(reg); reg 660 drivers/gpu/drm/i915/i915_irq.c i915_reg_t reg = PIPESTAT(pipe); reg 676 drivers/gpu/drm/i915/i915_irq.c I915_WRITE(reg, enable_mask | status_mask); reg 677 drivers/gpu/drm/i915/i915_irq.c POSTING_READ(reg); reg 1302 drivers/gpu/drm/i915/i915_irq.c i915_reg_t reg; reg 1310 drivers/gpu/drm/i915/i915_irq.c reg = GEN7_L3CDERRST1(slice); reg 1312 drivers/gpu/drm/i915/i915_irq.c error_status = I915_READ(reg); reg 1317 drivers/gpu/drm/i915/i915_irq.c I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); reg 1318 drivers/gpu/drm/i915/i915_irq.c POSTING_READ(reg); reg 1729 drivers/gpu/drm/i915/i915_irq.c i915_reg_t reg; reg 1760 drivers/gpu/drm/i915/i915_irq.c reg = PIPESTAT(pipe); reg 1761 drivers/gpu/drm/i915/i915_irq.c pipe_stats[pipe] = I915_READ(reg) & status_mask; reg 1774 drivers/gpu/drm/i915/i915_irq.c I915_WRITE(reg, pipe_stats[pipe]); reg 1775 drivers/gpu/drm/i915/i915_irq.c I915_WRITE(reg, enable_mask); reg 1571 drivers/gpu/drm/i915/i915_perf.c const struct i915_oa_reg *reg = regs + i; reg 1573 drivers/gpu/drm/i915/i915_perf.c I915_WRITE(reg->addr, reg->value); reg 1647 drivers/gpu/drm/i915/i915_perf.c i915_reg_t reg) reg 1649 drivers/gpu/drm/i915/i915_perf.c u32 mmio = i915_mmio_reg_offset(reg); reg 1711 drivers/gpu/drm/i915/i915_perf.c i915_reg_t reg; reg 1756 drivers/gpu/drm/i915/i915_perf.c *cs++ = i915_mmio_reg_offset(flex->reg); reg 1892 drivers/gpu/drm/i915/i915_perf.c regs[i].value = oa_config_flex_reg(oa_config, regs[i].reg); reg 3198 drivers/gpu/drm/i915/i915_perf.c static u32 mask_reg_value(u32 reg, u32 val) reg 3204 drivers/gpu/drm/i915/i915_perf.c if (i915_mmio_reg_offset(HALF_SLICE_CHICKEN2) == reg) reg 3211 drivers/gpu/drm/i915/i915_perf.c if (i915_mmio_reg_offset(WAIT_FOR_RC6_EXIT) == reg) reg 182 drivers/gpu/drm/i915/i915_reg.h u32 reg; reg 185 drivers/gpu/drm/i915/i915_reg.h #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) reg 189 drivers/gpu/drm/i915/i915_reg.h static inline u32 i915_mmio_reg_offset(i915_reg_t reg) reg 191 drivers/gpu/drm/i915/i915_reg.h return reg.reg; reg 199 drivers/gpu/drm/i915/i915_reg.h static inline bool i915_mmio_reg_valid(i915_reg_t reg) reg 201 drivers/gpu/drm/i915/i915_reg.h return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); reg 251 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \ reg 252 drivers/gpu/drm/i915/i915_reg.h INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \ reg 254 drivers/gpu/drm/i915/i915_reg.h #define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \ reg 255 drivers/gpu/drm/i915/i915_reg.h INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \ reg 257 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_TRANS2(tran, reg) _MMIO(_TRANS2(tran, reg)) reg 258 drivers/gpu/drm/i915/i915_reg.h #define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \ reg 259 drivers/gpu/drm/i915/i915_reg.h INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \ reg 1626 drivers/gpu/drm/i915/i915_reg.h #define _BXT_PHY(phy, reg) \ reg 1627 drivers/gpu/drm/i915/i915_reg.h _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) reg 4704 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \ reg 4705 drivers/gpu/drm/i915/i915_reg.h PPS_BASE + (reg) + \ reg 6588 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_CHV_SPCSC(plane_id, reg) \ reg 6589 drivers/gpu/drm/i915/i915_reg.h _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) reg 8936 drivers/gpu/drm/i915/i915_reg.h #define GEN7_PARITY_ERROR_ROW(reg) \ reg 8937 drivers/gpu/drm/i915/i915_reg.h (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) reg 8938 drivers/gpu/drm/i915/i915_reg.h #define GEN7_PARITY_ERROR_BANK(reg) \ reg 8939 drivers/gpu/drm/i915/i915_reg.h (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) reg 8940 drivers/gpu/drm/i915/i915_reg.h #define GEN7_PARITY_ERROR_SUBBANK(reg) \ reg 8941 drivers/gpu/drm/i915/i915_reg.h (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) reg 46 drivers/gpu/drm/i915/i915_sysfs.c i915_reg_t reg) reg 52 drivers/gpu/drm/i915/i915_sysfs.c res = intel_rc6_residency_us(dev_priv, reg); reg 868 drivers/gpu/drm/i915/i915_trace.h TP_PROTO(bool write, i915_reg_t reg, u64 val, int len, bool trace), reg 870 drivers/gpu/drm/i915/i915_trace.h TP_ARGS(write, reg, val, len, trace), reg 876 drivers/gpu/drm/i915/i915_trace.h __field(u32, reg) reg 883 drivers/gpu/drm/i915/i915_trace.h __entry->reg = i915_mmio_reg_offset(reg); reg 890 drivers/gpu/drm/i915/i915_trace.h __entry->reg, __entry->len, reg 866 drivers/gpu/drm/i915/intel_pm.c u32 reg; reg 892 drivers/gpu/drm/i915/intel_pm.c reg = I915_READ(DSPFW1); reg 893 drivers/gpu/drm/i915/intel_pm.c reg &= ~DSPFW_SR_MASK; reg 894 drivers/gpu/drm/i915/intel_pm.c reg |= FW_WM(wm, SR); reg 895 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(DSPFW1, reg); reg 896 drivers/gpu/drm/i915/intel_pm.c DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); reg 902 drivers/gpu/drm/i915/intel_pm.c reg = I915_READ(DSPFW3); reg 903 drivers/gpu/drm/i915/intel_pm.c reg &= ~DSPFW_CURSOR_SR_MASK; reg 904 drivers/gpu/drm/i915/intel_pm.c reg |= FW_WM(wm, CURSOR_SR); reg 905 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(DSPFW3, reg); reg 911 drivers/gpu/drm/i915/intel_pm.c reg = I915_READ(DSPFW3); reg 912 drivers/gpu/drm/i915/intel_pm.c reg &= ~DSPFW_HPLL_SR_MASK; reg 913 drivers/gpu/drm/i915/intel_pm.c reg |= FW_WM(wm, HPLL_SR); reg 914 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(DSPFW3, reg); reg 920 drivers/gpu/drm/i915/intel_pm.c reg = I915_READ(DSPFW3); reg 921 drivers/gpu/drm/i915/intel_pm.c reg &= ~DSPFW_HPLL_CURSOR_MASK; reg 922 drivers/gpu/drm/i915/intel_pm.c reg |= FW_WM(wm, HPLL_CURSOR); reg 923 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(DSPFW3, reg); reg 924 drivers/gpu/drm/i915/intel_pm.c DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); reg 3974 drivers/gpu/drm/i915/intel_pm.c struct skl_ddb_entry *entry, u32 reg) reg 3977 drivers/gpu/drm/i915/intel_pm.c entry->start = reg & DDB_ENTRY_MASK; reg 3978 drivers/gpu/drm/i915/intel_pm.c entry->end = (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK; reg 5122 drivers/gpu/drm/i915/intel_pm.c i915_reg_t reg, reg 5126 drivers/gpu/drm/i915/intel_pm.c I915_WRITE_FW(reg, (entry->end - 1) << 16 | entry->start); reg 5128 drivers/gpu/drm/i915/intel_pm.c I915_WRITE_FW(reg, 0); reg 5132 drivers/gpu/drm/i915/intel_pm.c i915_reg_t reg, reg 5144 drivers/gpu/drm/i915/intel_pm.c I915_WRITE_FW(reg, val); reg 9119 drivers/gpu/drm/i915/intel_pm.c u32 reg = I915_READ(GEN7_FF_THREAD_MODE); reg 9127 drivers/gpu/drm/i915/intel_pm.c reg &= ~GEN7_FF_SCHED_MASK; reg 9128 drivers/gpu/drm/i915/intel_pm.c reg |= GEN7_FF_TS_SCHED_HW; reg 9129 drivers/gpu/drm/i915/intel_pm.c reg |= GEN7_FF_VS_SCHED_HW; reg 9130 drivers/gpu/drm/i915/intel_pm.c reg |= GEN7_FF_DS_SCHED_HW; reg 9132 drivers/gpu/drm/i915/intel_pm.c I915_WRITE(GEN7_FF_THREAD_MODE, reg); reg 9931 drivers/gpu/drm/i915/intel_pm.c const i915_reg_t reg) reg 9954 drivers/gpu/drm/i915/intel_pm.c upper = I915_READ_FW(reg); reg 9960 drivers/gpu/drm/i915/intel_pm.c lower = I915_READ_FW(reg); reg 9964 drivers/gpu/drm/i915/intel_pm.c upper = I915_READ_FW(reg); reg 9977 drivers/gpu/drm/i915/intel_pm.c const i915_reg_t reg) reg 9996 drivers/gpu/drm/i915/intel_pm.c i = (i915_mmio_reg_offset(reg) - reg 10001 drivers/gpu/drm/i915/intel_pm.c fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ); reg 10011 drivers/gpu/drm/i915/intel_pm.c time_hw = vlv_residency_raw(dev_priv, reg); reg 10023 drivers/gpu/drm/i915/intel_pm.c time_hw = intel_uncore_read_fw(uncore, reg); reg 10052 drivers/gpu/drm/i915/intel_pm.c i915_reg_t reg) reg 10054 drivers/gpu/drm/i915/intel_pm.c return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000); reg 78 drivers/gpu/drm/i915/intel_pm.h u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, i915_reg_t reg); reg 79 drivers/gpu/drm/i915/intel_pm.h u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg); reg 158 drivers/gpu/drm/i915/intel_sideband.c u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg) reg 163 drivers/gpu/drm/i915/intel_sideband.c SB_CRRDDA_NP, reg, &val); reg 168 drivers/gpu/drm/i915/intel_sideband.c void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val) reg 171 drivers/gpu/drm/i915/intel_sideband.c SB_CRWRDA_NP, reg, &val); reg 184 drivers/gpu/drm/i915/intel_sideband.c u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg) reg 189 drivers/gpu/drm/i915/intel_sideband.c SB_CRRDDA_NP, reg, &val); reg 195 drivers/gpu/drm/i915/intel_sideband.c u8 port, u32 reg, u32 val) reg 198 drivers/gpu/drm/i915/intel_sideband.c SB_CRWRDA_NP, reg, &val); reg 201 drivers/gpu/drm/i915/intel_sideband.c u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg) reg 206 drivers/gpu/drm/i915/intel_sideband.c SB_CRRDDA_NP, reg, &val); reg 211 drivers/gpu/drm/i915/intel_sideband.c void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val) reg 214 drivers/gpu/drm/i915/intel_sideband.c SB_CRWRDA_NP, reg, &val); reg 217 drivers/gpu/drm/i915/intel_sideband.c u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg) reg 222 drivers/gpu/drm/i915/intel_sideband.c SB_CRRDDA_NP, reg, &val); reg 227 drivers/gpu/drm/i915/intel_sideband.c void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val) reg 230 drivers/gpu/drm/i915/intel_sideband.c SB_CRWRDA_NP, reg, &val); reg 233 drivers/gpu/drm/i915/intel_sideband.c u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg) reg 238 drivers/gpu/drm/i915/intel_sideband.c vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MRD_NP, reg, &val); reg 245 drivers/gpu/drm/i915/intel_sideband.c pipe_name(pipe), reg, val); reg 251 drivers/gpu/drm/i915/intel_sideband.c enum pipe pipe, int reg, u32 val) reg 255 drivers/gpu/drm/i915/intel_sideband.c vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MWR_NP, reg, &val); reg 258 drivers/gpu/drm/i915/intel_sideband.c u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg) reg 263 drivers/gpu/drm/i915/intel_sideband.c reg, &val); reg 267 drivers/gpu/drm/i915/intel_sideband.c void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val) reg 270 drivers/gpu/drm/i915/intel_sideband.c reg, &val); reg 274 drivers/gpu/drm/i915/intel_sideband.c static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg, reg 290 drivers/gpu/drm/i915/intel_sideband.c intel_uncore_write_fw(uncore, SBI_ADDR, (u32)reg << 16); reg 309 drivers/gpu/drm/i915/intel_sideband.c DRM_ERROR("error during SBI read of reg %x\n", reg); reg 319 drivers/gpu/drm/i915/intel_sideband.c u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg, reg 324 drivers/gpu/drm/i915/intel_sideband.c intel_sbi_rw(i915, reg, destination, &result, true); reg 329 drivers/gpu/drm/i915/intel_sideband.c void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value, reg 332 drivers/gpu/drm/i915/intel_sideband.c intel_sbi_rw(i915, reg, destination, &value, false); reg 29 drivers/gpu/drm/i915/intel_sideband.h u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg); reg 31 drivers/gpu/drm/i915/intel_sideband.h u8 port, u32 reg, u32 val); reg 39 drivers/gpu/drm/i915/intel_sideband.h u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg); reg 40 drivers/gpu/drm/i915/intel_sideband.h void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val); reg 52 drivers/gpu/drm/i915/intel_sideband.h u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg); reg 53 drivers/gpu/drm/i915/intel_sideband.h void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val); reg 65 drivers/gpu/drm/i915/intel_sideband.h u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg); reg 66 drivers/gpu/drm/i915/intel_sideband.h void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val); reg 78 drivers/gpu/drm/i915/intel_sideband.h u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg); reg 80 drivers/gpu/drm/i915/intel_sideband.h enum pipe pipe, int reg, u32 val); reg 92 drivers/gpu/drm/i915/intel_sideband.h u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg); reg 93 drivers/gpu/drm/i915/intel_sideband.h void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val); reg 125 drivers/gpu/drm/i915/intel_sideband.h u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg, reg 127 drivers/gpu/drm/i915/intel_sideband.h void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value, reg 806 drivers/gpu/drm/i915/intel_uncore.c #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000) reg 808 drivers/gpu/drm/i915/intel_uncore.c #define GEN11_NEEDS_FORCE_WAKE(reg) \ reg 809 drivers/gpu/drm/i915/intel_uncore.c ((reg) < 0x40000 || ((reg) >= 0x1c0000 && (reg) < 0x1dc000)) reg 938 drivers/gpu/drm/i915/intel_uncore.c static int mmio_reg_cmp(u32 key, const i915_reg_t *reg) reg 940 drivers/gpu/drm/i915/intel_uncore.c u32 offset = i915_mmio_reg_offset(*reg); reg 962 drivers/gpu/drm/i915/intel_uncore.c gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) reg 1094 drivers/gpu/drm/i915/intel_uncore.c const i915_reg_t reg, reg 1101 drivers/gpu/drm/i915/intel_uncore.c i915_mmio_reg_offset(reg))) reg 1108 drivers/gpu/drm/i915/intel_uncore.c const i915_reg_t reg, reg 1121 drivers/gpu/drm/i915/intel_uncore.c __unclaimed_reg_debug(uncore, reg, read, before); reg 1132 drivers/gpu/drm/i915/intel_uncore.c trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ reg 1137 drivers/gpu/drm/i915/intel_uncore.c gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ reg 1139 drivers/gpu/drm/i915/intel_uncore.c val = __raw_uncore_read##x(uncore, reg); \ reg 1145 drivers/gpu/drm/i915/intel_uncore.c gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ reg 1148 drivers/gpu/drm/i915/intel_uncore.c val = __raw_uncore_read##x(uncore, reg); \ reg 1168 drivers/gpu/drm/i915/intel_uncore.c u32 offset = i915_mmio_reg_offset(reg); \ reg 1173 drivers/gpu/drm/i915/intel_uncore.c unclaimed_reg_debug(uncore, reg, true, true) reg 1176 drivers/gpu/drm/i915/intel_uncore.c unclaimed_reg_debug(uncore, reg, true, false); \ reg 1178 drivers/gpu/drm/i915/intel_uncore.c trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ reg 1210 drivers/gpu/drm/i915/intel_uncore.c func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ reg 1216 drivers/gpu/drm/i915/intel_uncore.c val = __raw_uncore_read##x(uncore, reg); \ reg 1222 drivers/gpu/drm/i915/intel_uncore.c func##_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \ reg 1223 drivers/gpu/drm/i915/intel_uncore.c return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \ reg 1240 drivers/gpu/drm/i915/intel_uncore.c trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ reg 1247 drivers/gpu/drm/i915/intel_uncore.c gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ reg 1249 drivers/gpu/drm/i915/intel_uncore.c __raw_uncore_write##x(uncore, reg, val); \ reg 1255 drivers/gpu/drm/i915/intel_uncore.c gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ reg 1258 drivers/gpu/drm/i915/intel_uncore.c __raw_uncore_write##x(uncore, reg, val); \ reg 1276 drivers/gpu/drm/i915/intel_uncore.c u32 offset = i915_mmio_reg_offset(reg); \ reg 1278 drivers/gpu/drm/i915/intel_uncore.c trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ reg 1281 drivers/gpu/drm/i915/intel_uncore.c unclaimed_reg_debug(uncore, reg, false, true) reg 1284 drivers/gpu/drm/i915/intel_uncore.c unclaimed_reg_debug(uncore, reg, false, false); \ reg 1289 drivers/gpu/drm/i915/intel_uncore.c gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ reg 1293 drivers/gpu/drm/i915/intel_uncore.c __raw_uncore_write##x(uncore, reg, val); \ reg 1302 drivers/gpu/drm/i915/intel_uncore.c func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ reg 1308 drivers/gpu/drm/i915/intel_uncore.c __raw_uncore_write##x(uncore, reg, val); \ reg 1314 drivers/gpu/drm/i915/intel_uncore.c func##_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \ reg 1315 drivers/gpu/drm/i915/intel_uncore.c return __##func##_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); \ reg 1819 drivers/gpu/drm/i915/intel_uncore.c struct drm_i915_reg_read *reg = data; reg 1836 drivers/gpu/drm/i915/intel_uncore.c entry_offset == (reg->offset & -entry->size)) reg 1845 drivers/gpu/drm/i915/intel_uncore.c flags = reg->offset & (entry->size - 1); reg 1849 drivers/gpu/drm/i915/intel_uncore.c reg->val = intel_uncore_read64_2x32(uncore, reg 1853 drivers/gpu/drm/i915/intel_uncore.c reg->val = intel_uncore_read64(uncore, reg 1856 drivers/gpu/drm/i915/intel_uncore.c reg->val = intel_uncore_read(uncore, entry->offset_ldw); reg 1858 drivers/gpu/drm/i915/intel_uncore.c reg->val = intel_uncore_read16(uncore, reg 1861 drivers/gpu/drm/i915/intel_uncore.c reg->val = intel_uncore_read8(uncore, reg 1897 drivers/gpu/drm/i915/intel_uncore.c i915_reg_t reg, reg 1905 drivers/gpu/drm/i915/intel_uncore.c #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value) reg 1945 drivers/gpu/drm/i915/intel_uncore.c i915_reg_t reg, reg 1953 drivers/gpu/drm/i915/intel_uncore.c intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ); reg 1963 drivers/gpu/drm/i915/intel_uncore.c reg, mask, value, reg 1971 drivers/gpu/drm/i915/intel_uncore.c reg), reg 1976 drivers/gpu/drm/i915/intel_uncore.c trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true); reg 2038 drivers/gpu/drm/i915/intel_uncore.c i915_reg_t reg, unsigned int op) reg 2048 drivers/gpu/drm/i915/intel_uncore.c fw_domains = uncore->funcs.read_fw_domains(uncore, reg); reg 2051 drivers/gpu/drm/i915/intel_uncore.c fw_domains |= uncore->funcs.write_fw_domains(uncore, reg); reg 204 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, unsigned int op); reg 224 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, reg 232 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, reg 237 drivers/gpu/drm/i915/intel_uncore.h return __intel_wait_for_register(uncore, reg, mask, value, 2, reg 242 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, reg 250 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, reg 255 drivers/gpu/drm/i915/intel_uncore.h return __intel_wait_for_register_fw(uncore, reg, mask, value, reg 262 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg) \ reg 264 drivers/gpu/drm/i915/intel_uncore.h return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \ reg 269 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, u##x__ val) \ reg 271 drivers/gpu/drm/i915/intel_uncore.h write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \ reg 288 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg) \ reg 290 drivers/gpu/drm/i915/intel_uncore.h return uncore->funcs.mmio_read##s__(uncore, reg, (trace__)); \ reg 295 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, u##x__ val) \ reg 297 drivers/gpu/drm/i915/intel_uncore.h uncore->funcs.mmio_write##s__(uncore, reg, val, (trace__)); \ reg 379 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, u32 clear, u32 set) reg 383 drivers/gpu/drm/i915/intel_uncore.h val = intel_uncore_read(uncore, reg); reg 386 drivers/gpu/drm/i915/intel_uncore.h intel_uncore_write(uncore, reg, val); reg 390 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, u32 clear, u32 set) reg 394 drivers/gpu/drm/i915/intel_uncore.h val = intel_uncore_read_fw(uncore, reg); reg 397 drivers/gpu/drm/i915/intel_uncore.h intel_uncore_write_fw(uncore, reg, val); reg 401 drivers/gpu/drm/i915/intel_uncore.h i915_reg_t reg, u32 val, reg 406 drivers/gpu/drm/i915/intel_uncore.h intel_uncore_write(uncore, reg, val); reg 407 drivers/gpu/drm/i915/intel_uncore.h reg_val = intel_uncore_read(uncore, reg); reg 412 drivers/gpu/drm/i915/intel_uncore.h #define raw_reg_read(base, reg) \ reg 413 drivers/gpu/drm/i915/intel_uncore.h readl(base + i915_mmio_reg_offset(reg)) reg 414 drivers/gpu/drm/i915/intel_uncore.h #define raw_reg_write(base, reg, value) \ reg 415 drivers/gpu/drm/i915/intel_uncore.h writel(value, base + i915_mmio_reg_offset(reg)) reg 71 drivers/gpu/drm/i915/selftests/intel_uncore.c const i915_reg_t *reg; reg 76 drivers/gpu/drm/i915/selftests/intel_uncore.c reg = reg_lists[j].regs; reg 77 drivers/gpu/drm/i915/selftests/intel_uncore.c for (i = 0, prev = -1; i < reg_lists[j].size; i++, reg++) { reg 78 drivers/gpu/drm/i915/selftests/intel_uncore.c u32 offset = i915_mmio_reg_offset(*reg); reg 140 drivers/gpu/drm/i915/selftests/intel_uncore.c const struct reg *r; reg 191 drivers/gpu/drm/i915/selftests/intel_uncore.c u32 __iomem *reg = uncore->regs + engine->mmio_base + r->offset; reg 214 drivers/gpu/drm/i915/selftests/intel_uncore.c val = readl(reg); reg 241 drivers/gpu/drm/i915/selftests/intel_uncore.c if (wait_for(readl(reg) == 0, 100)) { reg 243 drivers/gpu/drm/i915/selftests/intel_uncore.c engine->name, r->name, readl(reg), fw_domains); reg 282 drivers/gpu/drm/i915/selftests/intel_uncore.c i915_reg_t reg = { offset }; reg 284 drivers/gpu/drm/i915/selftests/intel_uncore.c (void)I915_READ_FW(reg); reg 293 drivers/gpu/drm/i915/selftests/intel_uncore.c i915_reg_t reg = { offset }; reg 301 drivers/gpu/drm/i915/selftests/intel_uncore.c (void)I915_READ(reg); reg 29 drivers/gpu/drm/i915/selftests/mock_uncore.c nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { } reg 36 drivers/gpu/drm/i915/selftests/mock_uncore.c nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return 0; } reg 81 drivers/gpu/drm/imx/imx-ldb.c int reg; reg 235 drivers/gpu/drm/imx/imx-ldb.c regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask, reg 329 drivers/gpu/drm/imx/imx-ldb.c regmap_read(ldb->regmap, lvds_mux->reg, &mux); reg 521 drivers/gpu/drm/imx/imx-ldb.c .reg = IOMUXC_GPR3, reg 525 drivers/gpu/drm/imx/imx-ldb.c .reg = IOMUXC_GPR3, reg 497 drivers/gpu/drm/imx/imx-tve.c static bool imx_tve_readable_reg(struct device *dev, unsigned int reg) reg 499 drivers/gpu/drm/imx/imx-tve.c return (reg % 4 == 0) && (reg <= 0xdc); reg 179 drivers/gpu/drm/ingenic/ingenic-drm.c static bool ingenic_drm_writeable_reg(struct device *dev, unsigned int reg) reg 181 drivers/gpu/drm/ingenic/ingenic-drm.c switch (reg) { reg 11 drivers/gpu/drm/lima/lima_bcast.c #define bcast_write(reg, data) writel(data, ip->iomem + reg) reg 12 drivers/gpu/drm/lima/lima_bcast.c #define bcast_read(reg) readl(ip->iomem + reg) reg 12 drivers/gpu/drm/lima/lima_dlbu.c #define dlbu_write(reg, data) writel(data, ip->iomem + reg) reg 13 drivers/gpu/drm/lima/lima_dlbu.c #define dlbu_read(reg) readl(ip->iomem + reg) reg 37 drivers/gpu/drm/lima/lima_dlbu.c void lima_dlbu_set_reg(struct lima_ip *ip, u32 *reg) reg 39 drivers/gpu/drm/lima/lima_dlbu.c dlbu_write(LIMA_DLBU_TLLIST_VBASEADDR, reg[0]); reg 40 drivers/gpu/drm/lima/lima_dlbu.c dlbu_write(LIMA_DLBU_FB_DIM, reg[1]); reg 41 drivers/gpu/drm/lima/lima_dlbu.c dlbu_write(LIMA_DLBU_TLLIST_CONF, reg[2]); reg 42 drivers/gpu/drm/lima/lima_dlbu.c dlbu_write(LIMA_DLBU_START_TILE_POS, reg[3]); reg 13 drivers/gpu/drm/lima/lima_dlbu.h void lima_dlbu_set_reg(struct lima_ip *ip, u32 *reg); reg 15 drivers/gpu/drm/lima/lima_gp.c #define gp_write(reg, data) writel(data, ip->iomem + reg) reg 16 drivers/gpu/drm/lima/lima_gp.c #define gp_read(reg) readl(ip->iomem + reg) reg 11 drivers/gpu/drm/lima/lima_l2_cache.c #define l2_cache_write(reg, data) writel(data, ip->iomem + reg) reg 12 drivers/gpu/drm/lima/lima_l2_cache.c #define l2_cache_read(reg) readl(ip->iomem + reg) reg 14 drivers/gpu/drm/lima/lima_mmu.c #define mmu_write(reg, data) writel(data, ip->iomem + reg) reg 15 drivers/gpu/drm/lima/lima_mmu.c #define mmu_read(reg) readl(ip->iomem + reg) reg 11 drivers/gpu/drm/lima/lima_pmu.c #define pmu_write(reg, data) writel(data, ip->iomem + reg) reg 12 drivers/gpu/drm/lima/lima_pmu.c #define pmu_read(reg) readl(ip->iomem + reg) reg 18 drivers/gpu/drm/lima/lima_pp.c #define pp_write(reg, data) writel(data, ip->iomem + reg) reg 19 drivers/gpu/drm/lima/lima_pp.c #define pp_read(reg) readl(ip->iomem + reg) reg 62 drivers/gpu/drm/mediatek/mtk_cec.c void __iomem *reg = cec->regs + offset; reg 65 drivers/gpu/drm/mediatek/mtk_cec.c tmp = readl(reg); reg 67 drivers/gpu/drm/mediatek/mtk_cec.c writel(tmp, reg); reg 73 drivers/gpu/drm/mediatek/mtk_cec.c void __iomem *reg = cec->regs + offset; reg 76 drivers/gpu/drm/mediatek/mtk_cec.c tmp = readl(reg); reg 78 drivers/gpu/drm/mediatek/mtk_cec.c writel(tmp, reg); reg 134 drivers/gpu/drm/mediatek/mtk_disp_ovl.c unsigned int reg; reg 139 drivers/gpu/drm/mediatek/mtk_disp_ovl.c reg = readl(comp->regs + DISP_REG_OVL_SRC_CON); reg 140 drivers/gpu/drm/mediatek/mtk_disp_ovl.c reg = reg | BIT(idx); reg 141 drivers/gpu/drm/mediatek/mtk_disp_ovl.c writel(reg, comp->regs + DISP_REG_OVL_SRC_CON); reg 146 drivers/gpu/drm/mediatek/mtk_disp_ovl.c unsigned int reg; reg 148 drivers/gpu/drm/mediatek/mtk_disp_ovl.c reg = readl(comp->regs + DISP_REG_OVL_SRC_CON); reg 149 drivers/gpu/drm/mediatek/mtk_disp_ovl.c reg = reg & ~BIT(idx); reg 150 drivers/gpu/drm/mediatek/mtk_disp_ovl.c writel(reg, comp->regs + DISP_REG_OVL_SRC_CON); reg 88 drivers/gpu/drm/mediatek/mtk_disp_rdma.c static void rdma_update_bits(struct mtk_ddp_comp *comp, unsigned int reg, reg 91 drivers/gpu/drm/mediatek/mtk_disp_rdma.c unsigned int tmp = readl(comp->regs + reg); reg 94 drivers/gpu/drm/mediatek/mtk_disp_rdma.c writel(tmp, comp->regs + reg); reg 131 drivers/gpu/drm/mediatek/mtk_disp_rdma.c unsigned int reg; reg 144 drivers/gpu/drm/mediatek/mtk_disp_rdma.c reg = RDMA_FIFO_UNDERFLOW_EN | reg 147 drivers/gpu/drm/mediatek/mtk_disp_rdma.c writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON); reg 355 drivers/gpu/drm/mediatek/mtk_drm_ddp.c unsigned int addr, value, reg; reg 359 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg = readl_relaxed(config_regs + addr) | value; reg 360 drivers/gpu/drm/mediatek/mtk_drm_ddp.c writel_relaxed(reg, config_regs + addr); reg 367 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg = readl_relaxed(config_regs + addr) | value; reg 368 drivers/gpu/drm/mediatek/mtk_drm_ddp.c writel_relaxed(reg, config_regs + addr); reg 376 drivers/gpu/drm/mediatek/mtk_drm_ddp.c unsigned int addr, value, reg; reg 380 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg = readl_relaxed(config_regs + addr) & ~value; reg 381 drivers/gpu/drm/mediatek/mtk_drm_ddp.c writel_relaxed(reg, config_regs + addr); reg 386 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg = readl_relaxed(config_regs + addr) & ~value; reg 387 drivers/gpu/drm/mediatek/mtk_drm_ddp.c writel_relaxed(reg, config_regs + addr); reg 434 drivers/gpu/drm/mediatek/mtk_drm_ddp.c unsigned int reg; reg 441 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg = MUTEX_SOF_DSI0; reg 444 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg = MUTEX_SOF_DSI0; reg 447 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg = MUTEX_SOF_DSI2; reg 450 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg = MUTEX_SOF_DSI3; reg 453 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg = MUTEX_SOF_DPI0; reg 456 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg = MUTEX_SOF_DPI1; reg 461 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg = readl_relaxed(ddp->regs + offset); reg 462 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg |= 1 << ddp->mutex_mod[id]; reg 463 drivers/gpu/drm/mediatek/mtk_drm_ddp.c writel_relaxed(reg, ddp->regs + offset); reg 466 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg = readl_relaxed(ddp->regs + offset); reg 467 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg |= 1 << (ddp->mutex_mod[id] - 32); reg 468 drivers/gpu/drm/mediatek/mtk_drm_ddp.c writel_relaxed(reg, ddp->regs + offset); reg 473 drivers/gpu/drm/mediatek/mtk_drm_ddp.c writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_SOF(mutex->id)); reg 481 drivers/gpu/drm/mediatek/mtk_drm_ddp.c unsigned int reg; reg 499 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg = readl_relaxed(ddp->regs + offset); reg 500 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg &= ~(1 << ddp->mutex_mod[id]); reg 501 drivers/gpu/drm/mediatek/mtk_drm_ddp.c writel_relaxed(reg, ddp->regs + offset); reg 504 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg = readl_relaxed(ddp->regs + offset); reg 505 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg &= ~(1 << (ddp->mutex_mod[id] - 32)); reg 506 drivers/gpu/drm/mediatek/mtk_drm_ddp.c writel_relaxed(reg, ddp->regs + offset); reg 147 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c unsigned int i, reg; reg 153 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c reg = readl(comp->regs + DISP_GAMMA_CFG); reg 154 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c reg = reg | GAMMA_LUT_EN; reg 155 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c writel(reg, comp->regs + DISP_GAMMA_CFG); reg 195 drivers/gpu/drm/mediatek/mtk_hdmi.c void __iomem *reg = hdmi->regs + offset; reg 198 drivers/gpu/drm/mediatek/mtk_hdmi.c tmp = readl(reg); reg 200 drivers/gpu/drm/mediatek/mtk_hdmi.c writel(tmp, reg); reg 205 drivers/gpu/drm/mediatek/mtk_hdmi.c void __iomem *reg = hdmi->regs + offset; reg 208 drivers/gpu/drm/mediatek/mtk_hdmi.c tmp = readl(reg); reg 210 drivers/gpu/drm/mediatek/mtk_hdmi.c writel(tmp, reg); reg 215 drivers/gpu/drm/mediatek/mtk_hdmi.c void __iomem *reg = hdmi->regs + offset; reg 218 drivers/gpu/drm/mediatek/mtk_hdmi.c tmp = readl(reg); reg 220 drivers/gpu/drm/mediatek/mtk_hdmi.c writel(tmp, reg); reg 21 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c void __iomem *reg = hdmi_phy->regs + offset; reg 24 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c tmp = readl(reg); reg 26 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c writel(tmp, reg); reg 32 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c void __iomem *reg = hdmi_phy->regs + offset; reg 35 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c tmp = readl(reg); reg 37 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c writel(tmp, reg); reg 43 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c void __iomem *reg = hdmi_phy->regs + offset; reg 46 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c tmp = readl(reg); reg 48 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c writel(tmp, reg); reg 321 drivers/gpu/drm/mediatek/mtk_mipi_tx.c u32 reg; reg 323 drivers/gpu/drm/mediatek/mtk_mipi_tx.c for (reg = MIPITX_DSI_CLOCK_LANE; reg 324 drivers/gpu/drm/mediatek/mtk_mipi_tx.c reg <= MIPITX_DSI_DATA_LANE3; reg += 4) reg 325 drivers/gpu/drm/mediatek/mtk_mipi_tx.c mtk_mipi_tx_set_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN); reg 352 drivers/gpu/drm/mediatek/mtk_mipi_tx.c u32 reg; reg 357 drivers/gpu/drm/mediatek/mtk_mipi_tx.c for (reg = MIPITX_DSI_CLOCK_LANE; reg 358 drivers/gpu/drm/mediatek/mtk_mipi_tx.c reg <= MIPITX_DSI_DATA_LANE3; reg += 4) reg 359 drivers/gpu/drm/mediatek/mtk_mipi_tx.c mtk_mipi_tx_clear_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN); reg 739 drivers/gpu/drm/meson/meson_dw_hdmi.c static int meson_dw_hdmi_reg_read(void *context, unsigned int reg, reg 744 drivers/gpu/drm/meson/meson_dw_hdmi.c *result = dw_hdmi->data->dwc_read(dw_hdmi, reg); reg 750 drivers/gpu/drm/meson/meson_dw_hdmi.c static int meson_dw_hdmi_reg_write(void *context, unsigned int reg, reg 755 drivers/gpu/drm/meson/meson_dw_hdmi.c dw_hdmi->data->dwc_write(dw_hdmi, reg, val); reg 12 drivers/gpu/drm/meson/meson_registers.h #define _REG(reg) ((reg) << 2) reg 979 drivers/gpu/drm/meson/meson_venc.c u32 reg; reg 1519 drivers/gpu/drm/meson/meson_venc.c reg = VPU_HDMI_ENCI_DATA_TO_HDMI; reg 1521 drivers/gpu/drm/meson/meson_venc.c reg = VPU_HDMI_ENCP_DATA_TO_HDMI; reg 1525 drivers/gpu/drm/meson/meson_venc.c reg |= VPU_HDMI_INV_HSYNC; reg 1529 drivers/gpu/drm/meson/meson_venc.c reg |= VPU_HDMI_INV_VSYNC; reg 1532 drivers/gpu/drm/meson/meson_venc.c reg |= VPU_HDMI_OUTPUT_CBYCR; reg 1539 drivers/gpu/drm/meson/meson_venc.c reg |= VPU_HDMI_WR_RATE(2); reg 1546 drivers/gpu/drm/meson/meson_venc.c reg |= VPU_HDMI_RD_RATE(2); reg 1548 drivers/gpu/drm/meson/meson_venc.c writel_relaxed(reg, priv->io_base + _REG(VPU_HDMI_SETTING)); reg 1561 drivers/gpu/drm/meson/meson_venc.c u32 reg; reg 1668 drivers/gpu/drm/meson/meson_venc.c reg = VENC_UPSAMPLE_CTRL_F0_2_CLK_RATIO | VENC_UPSAMPLE_CTRL_F1_EN | reg 1675 drivers/gpu/drm/meson/meson_venc.c writel_relaxed(VENC_UPSAMPLE_CTRL_INTERLACE_HIGH_LUMA | reg, reg 1682 drivers/gpu/drm/meson/meson_venc.c writel_relaxed(VENC_UPSAMPLE_CTRL_INTERLACE_PB | reg, reg 1689 drivers/gpu/drm/meson/meson_venc.c writel_relaxed(VENC_UPSAMPLE_CTRL_INTERLACE_PR | reg, reg 347 drivers/gpu/drm/meson/meson_viu.c uint32_t reg; reg 364 drivers/gpu/drm/meson/meson_viu.c reg = VIU_OSD_DDR_PRIORITY_URGENT | reg 371 drivers/gpu/drm/meson/meson_viu.c reg |= meson_viu_osd_burst_length_reg(32); reg 373 drivers/gpu/drm/meson/meson_viu.c reg |= meson_viu_osd_burst_length_reg(64); reg 375 drivers/gpu/drm/meson/meson_viu.c writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); reg 376 drivers/gpu/drm/meson/meson_viu.c writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT)); reg 215 drivers/gpu/drm/mga/mga_drv.h #define MGA_READ8(reg) \ reg 216 drivers/gpu/drm/mga/mga_drv.h readb(((void __iomem *)dev_priv->mmio->handle) + (reg)) reg 217 drivers/gpu/drm/mga/mga_drv.h #define MGA_READ(reg) \ reg 218 drivers/gpu/drm/mga/mga_drv.h readl(((void __iomem *)dev_priv->mmio->handle) + (reg)) reg 219 drivers/gpu/drm/mga/mga_drv.h #define MGA_WRITE8(reg, val) \ reg 220 drivers/gpu/drm/mga/mga_drv.h writeb(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) reg 221 drivers/gpu/drm/mga/mga_drv.h #define MGA_WRITE(reg, val) \ reg 222 drivers/gpu/drm/mga/mga_drv.h writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) reg 38 drivers/gpu/drm/mgag200/mgag200_drv.h #define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg)) reg 39 drivers/gpu/drm/mgag200/mgag200_drv.h #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg)) reg 40 drivers/gpu/drm/mgag200/mgag200_drv.h #define RREG32(reg) ioread32(((void __iomem *)mdev->rmmio) + (reg)) reg 41 drivers/gpu/drm/mgag200/mgag200_drv.h #define WREG32(reg, v) iowrite32(v, ((void __iomem *)mdev->rmmio) + (reg)) reg 46 drivers/gpu/drm/mgag200/mgag200_drv.h #define WREG_ATTR(reg, v) \ reg 49 drivers/gpu/drm/mgag200/mgag200_drv.h WREG8(ATTR_INDEX, reg); \ reg 53 drivers/gpu/drm/mgag200/mgag200_drv.h #define WREG_SEQ(reg, v) \ reg 55 drivers/gpu/drm/mgag200/mgag200_drv.h WREG8(MGAREG_SEQ_INDEX, reg); \ reg 59 drivers/gpu/drm/mgag200/mgag200_drv.h #define WREG_CRT(reg, v) \ reg 61 drivers/gpu/drm/mgag200/mgag200_drv.h WREG8(MGAREG_CRTC_INDEX, reg); \ reg 66 drivers/gpu/drm/mgag200/mgag200_drv.h #define WREG_ECRT(reg, v) \ reg 68 drivers/gpu/drm/mgag200/mgag200_drv.h WREG8(MGAREG_CRTCEXT_INDEX, reg); \ reg 75 drivers/gpu/drm/mgag200/mgag200_drv.h #define WREG_GFX(reg, v) \ reg 77 drivers/gpu/drm/mgag200/mgag200_drv.h WREG8(GFX_INDEX, reg); \ reg 84 drivers/gpu/drm/mgag200/mgag200_drv.h #define WREG_DAC(reg, v) \ reg 86 drivers/gpu/drm/mgag200/mgag200_drv.h WREG8(DAC_INDEX, reg); \ reg 354 drivers/gpu/drm/msm/adreno/a4xx_gpu.c uint32_t reg = gpu_read(gpu, REG_A4XX_CP_PROTECT_STATUS); reg 356 drivers/gpu/drm/msm/adreno/a4xx_gpu.c reg & (1 << 24) ? "WRITE" : "READ", reg 357 drivers/gpu/drm/msm/adreno/a4xx_gpu.c (reg & 0xFFFFF) >> 2); reg 490 drivers/gpu/drm/msm/adreno/a4xx_gpu.c unsigned int reg; reg 495 drivers/gpu/drm/msm/adreno/a4xx_gpu.c reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS); reg 496 drivers/gpu/drm/msm/adreno/a4xx_gpu.c } while (!(reg & A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON)); reg 131 drivers/gpu/drm/msm/adreno/a5xx_gpu.h uint32_t reg, uint32_t mask, uint32_t value) reg 135 drivers/gpu/drm/msm/adreno/a5xx_gpu.h if ((gpu_read(gpu, reg) & mask) == value) reg 39 drivers/gpu/drm/msm/adreno/a5xx_power.c uint32_t reg; reg 130 drivers/gpu/drm/msm/adreno/a5xx_power.c gpu_write(gpu, a5xx_sequence_regs[i].reg, reg 768 drivers/gpu/drm/msm/adreno/a6xx_gmu.c u32 reg; reg 773 drivers/gpu/drm/msm/adreno/a6xx_gmu.c reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS); reg 775 drivers/gpu/drm/msm/adreno/a6xx_gmu.c if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB) reg 92 drivers/gpu/drm/msm/adreno/a6xx_gmu.h static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or) reg 94 drivers/gpu/drm/msm/adreno/a6xx_gmu.h u32 val = gmu_read(gmu, reg); reg 98 drivers/gpu/drm/msm/adreno/a6xx_gmu.h gmu_write(gmu, reg, val | or); reg 48 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static inline int CRASHDUMP_WRITE(u64 *in, u32 reg, u32 val) reg 51 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c in[1] = (((u64) reg) << 44 | (1 << 21) | 1); reg 56 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static inline int CRASHDUMP_READ(u64 *in, u32 reg, u32 dwords, u64 target) reg 59 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c in[1] = (((u64) reg) << 44 | dwords); reg 159 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c u32 reg = A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(offset) | reg 162 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_A, reg); reg 163 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_B, reg); reg 164 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_C, reg); reg 165 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_D, reg); reg 186 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c u32 reg = A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(offset) | reg 189 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A, reg); reg 190 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B, reg); reg 191 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C, reg); reg 192 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D, reg); reg 205 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c u32 reg, int count, u32 *data) reg 209 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c gpu_write(gpu, ctrl0, reg); reg 424 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c #define RANGE(reg, a) ((reg)[(a) + 1] - (reg)[(a)] + 1) reg 338 drivers/gpu/drm/msm/adreno/adreno_gpu.h u32 reg = gpu->reg_offsets[offset_name]; reg 341 drivers/gpu/drm/msm/adreno/adreno_gpu.h val = gpu_read(&gpu->base, reg - 1); reg 348 drivers/gpu/drm/msm/adreno/adreno_gpu.h u32 reg = gpu->reg_offsets[offset_name]; reg 350 drivers/gpu/drm/msm/adreno/adreno_gpu.h gpu_write(&gpu->base, reg - 1, data); reg 845 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c const struct dpu_intr_reg *reg; reg 860 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c reg = &dpu_intr_set[reg_idx]; reg 871 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask); reg 873 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); reg 891 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c const struct dpu_intr_reg *reg; reg 906 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c reg = &dpu_intr_set[reg_idx]; reg 916 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); reg 918 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask); reg 159 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c u32 reg, wd_load_value, wd_ctl, wd_ctl2, i; reg 166 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c reg = DPU_REG_READ(c, MDP_VSYNC_SEL); reg 173 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c reg &= ~(0xf << pp_offset[pp_idx]); reg 174 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c reg |= (cfg->vsync_source & 0xf) << pp_offset[pp_idx]; reg 176 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c DPU_REG_WRITE(c, MDP_VSYNC_SEL, reg); reg 213 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c reg = DPU_REG_READ(c, wd_ctl2); reg 214 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c reg |= BIT(8); /* enable heartbeat timer */ reg 215 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c reg |= BIT(0); /* enable WD timer */ reg 216 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c DPU_REG_WRITE(c, wd_ctl2, reg); reg 51 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data) reg 53 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h msm_writel(data, mdp4_kms->mmio + reg); reg 56 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg) reg 58 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h return msm_readl(mdp4_kms->mmio + reg); reg 433 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c struct regulator *reg; reg 459 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c reg = devm_regulator_get(dev->dev, "lvds-vccs-3p3v"); reg 460 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c if (IS_ERR(reg)) { reg 461 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c ret = PTR_ERR(reg); reg 465 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_lcdc_encoder->regs[0] = reg; reg 467 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c reg = devm_regulator_get(dev->dev, "lvds-pll-vdda"); reg 468 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c if (IS_ERR(reg)) { reg 469 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c ret = PTR_ERR(reg); reg 473 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_lcdc_encoder->regs[1] = reg; reg 475 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c reg = devm_regulator_get(dev->dev, "lvds-vdda"); reg 476 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c if (IS_ERR(reg)) { reg 477 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c ret = PTR_ERR(reg); reg 481 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c mdp4_lcdc_encoder->regs[2] = reg; reg 29 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c uint32_t reg; reg 71 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c for (i = 0; pll_rate->conf[i].reg; i++) reg 72 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate->conf[i].val); reg 83 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c void ctl_write(struct mdp5_ctl *ctl, u32 reg, u32 data) reg 88 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c mdp5_write(mdp5_kms, reg, data); reg 92 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c u32 ctl_read(struct mdp5_ctl *ctl, u32 reg) reg 97 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c return mdp5_read(mdp5_kms, reg); reg 170 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data) reg 173 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h msm_writel(data, mdp5_kms->mmio + reg); reg 176 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg) reg 179 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h return msm_readl(mdp5_kms->mmio + reg); reg 31 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c static inline void mdss_write(struct mdp5_mdss *mdp5_mdss, u32 reg, u32 data) reg 33 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c msm_writel(data, mdp5_mdss->mmio + reg); reg 36 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c static inline u32 mdss_read(struct mdp5_mdss *mdp5_mdss, u32 reg) reg 38 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c return msm_readl(mdp5_mdss->mmio + reg); reg 186 drivers/gpu/drm/msm/dsi/dsi_host.c static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) reg 188 drivers/gpu/drm/msm/dsi/dsi_host.c return msm_readl(msm_host->ctrl_base + reg); reg 190 drivers/gpu/drm/msm/dsi/dsi_host.c static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) reg 192 drivers/gpu/drm/msm/dsi/dsi_host.c msm_writel(data, msm_host->ctrl_base + reg); reg 1299 drivers/gpu/drm/msm/dsi/dsi_host.c u8 reg[16]; reg 1304 drivers/gpu/drm/msm/dsi/dsi_host.c temp = (u32 *)reg; reg 1338 drivers/gpu/drm/msm/dsi/dsi_host.c buf[j++] = reg[i]; reg 369 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg, reg 378 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c val = dsi_phy_read(phy->base + reg); reg 381 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c dsi_phy_write(phy->base + reg, val | bit_mask); reg 383 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c dsi_phy_write(phy->base + reg, val & (~bit_mask)); reg 103 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg, reg 42 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h static inline void pll_write(void __iomem *reg, u32 data) reg 44 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h msm_writel(data, reg); reg 47 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h static inline u32 pll_read(const void __iomem *reg) reg 49 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h return msm_readl(reg); reg 52 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h static inline void pll_write_udelay(void __iomem *reg, u32 data, u32 delay_us) reg 54 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h pll_write(reg, data); reg 58 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns) reg 60 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h pll_write((reg), data); reg 298 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_regs *reg = &pll->reg_setup; reg 302 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c reg->decimal_div_start); reg 304 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c reg->frac_div_start_low); reg 306 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c reg->frac_div_start_mid); reg 308 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c reg->frac_div_start_high); reg 313 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c reg->pll_clock_inverters); reg 60 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c void __iomem *reg; reg 224 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c div = pll_read(bytediv->reg) & 0xff; reg 270 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(bytediv->reg); reg 272 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(bytediv->reg, val); reg 446 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c bytediv->reg = pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_9; reg 36 drivers/gpu/drm/msm/edp/edp_aux.c u32 reg, len; reg 63 drivers/gpu/drm/msm/edp/edp_aux.c reg = (i < 4) ? data[i] : msgdata[i - 4]; reg 64 drivers/gpu/drm/msm/edp/edp_aux.c reg = EDP_AUX_DATA_DATA(reg); /* index = 0, write */ reg 66 drivers/gpu/drm/msm/edp/edp_aux.c reg |= EDP_AUX_DATA_INDEX_WRITE; reg 67 drivers/gpu/drm/msm/edp/edp_aux.c edp_write(aux->base + REG_EDP_AUX_DATA, reg); reg 70 drivers/gpu/drm/msm/edp/edp_aux.c reg = 0; /* Transaction number is always 1 */ reg 72 drivers/gpu/drm/msm/edp/edp_aux.c reg |= EDP_AUX_TRANS_CTRL_I2C; reg 74 drivers/gpu/drm/msm/edp/edp_aux.c reg |= EDP_AUX_TRANS_CTRL_GO; reg 75 drivers/gpu/drm/msm/edp/edp_aux.c edp_write(aux->base + REG_EDP_AUX_TRANS_CTRL, reg); reg 158 drivers/gpu/drm/msm/hdmi/hdmi.c struct regulator *reg; reg 160 drivers/gpu/drm/msm/hdmi/hdmi.c reg = devm_regulator_get(&pdev->dev, reg 162 drivers/gpu/drm/msm/hdmi/hdmi.c if (IS_ERR(reg)) { reg 163 drivers/gpu/drm/msm/hdmi/hdmi.c ret = PTR_ERR(reg); reg 169 drivers/gpu/drm/msm/hdmi/hdmi.c hdmi->hpd_regs[i] = reg; reg 181 drivers/gpu/drm/msm/hdmi/hdmi.c struct regulator *reg; reg 183 drivers/gpu/drm/msm/hdmi/hdmi.c reg = devm_regulator_get(&pdev->dev, reg 185 drivers/gpu/drm/msm/hdmi/hdmi.c if (IS_ERR(reg)) { reg 186 drivers/gpu/drm/msm/hdmi/hdmi.c ret = PTR_ERR(reg); reg 192 drivers/gpu/drm/msm/hdmi/hdmi.c hdmi->pwr_regs[i] = reg; reg 117 drivers/gpu/drm/msm/hdmi/hdmi.h static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data) reg 119 drivers/gpu/drm/msm/hdmi/hdmi.h msm_writel(data, hdmi->mmio + reg); reg 122 drivers/gpu/drm/msm/hdmi/hdmi.h static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg) reg 124 drivers/gpu/drm/msm/hdmi/hdmi.h return msm_readl(hdmi->mmio + reg); reg 127 drivers/gpu/drm/msm/hdmi/hdmi.h static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg) reg 129 drivers/gpu/drm/msm/hdmi/hdmi.h return msm_readl(hdmi->qfprom_mmio + reg); reg 168 drivers/gpu/drm/msm/hdmi/hdmi.h static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data) reg 170 drivers/gpu/drm/msm/hdmi/hdmi.h msm_writel(data, phy->mmio + reg); reg 173 drivers/gpu/drm/msm/hdmi/hdmi.h static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg) reg 175 drivers/gpu/drm/msm/hdmi/hdmi.h return msm_readl(phy->mmio + reg); reg 694 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c u32 reg[2], data[2]; reg 718 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg[0] = REG_HDMI_HDCP_RCVPORT_DATA0; reg 720 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg[1] = REG_HDMI_HDCP_RCVPORT_DATA1; reg 722 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, reg, data, 2); reg 731 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c u32 reg, data; reg 745 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg = REG_HDMI_HDCP_RCVPORT_DATA12; reg 747 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, ®, &data, 1); reg 935 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c u32 reg, data; reg 974 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg = REG_HDMI_HDCP_RCVPORT_DATA12; reg 976 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, ®, &data, 1); reg 1004 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c u32 reg[ARRAY_SIZE(reg_data)]; reg 1018 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg[i] = reg_data[i].reg_id; reg 1021 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, reg, data, size); reg 1045 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c u32 reg[2], data[2]; reg 1048 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg[0] = REG_HDMI_HDCP_SHA_CTRL; reg 1050 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg[1] = REG_HDMI_HDCP_SHA_CTRL; reg 1053 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, reg, data, 2); reg 1120 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c u32 reg_val, data, reg; reg 1161 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c reg = REG_HDMI_HDCP_SHA_DATA; reg 1163 drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, ®, &data, 1); reg 27 drivers/gpu/drm/msm/hdmi/hdmi_phy.c struct regulator *reg; reg 29 drivers/gpu/drm/msm/hdmi/hdmi_phy.c reg = devm_regulator_get(dev, cfg->reg_names[i]); reg 30 drivers/gpu/drm/msm/hdmi/hdmi_phy.c if (IS_ERR(reg)) { reg 31 drivers/gpu/drm/msm/hdmi/hdmi_phy.c ret = PTR_ERR(reg); reg 37 drivers/gpu/drm/msm/hdmi/hdmi_phy.c phy->regs[i] = reg; reg 35 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c u32 reg; reg 237 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c static inline void pll_write(struct hdmi_pll_8960 *pll, u32 reg, u32 data) reg 239 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c msm_writel(data, pll->mmio + reg); reg 242 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c static inline u32 pll_read(struct hdmi_pll_8960 *pll, u32 reg) reg 244 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c return msm_readl(pll->mmio + reg); reg 394 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, pll_rate->conf[i].reg, pll_rate->conf[i].val); reg 214 drivers/gpu/drm/msm/msm_gpu.h static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) reg 216 drivers/gpu/drm/msm/msm_gpu.h msm_writel(data, gpu->mmio + (reg << 2)); reg 219 drivers/gpu/drm/msm/msm_gpu.h static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) reg 221 drivers/gpu/drm/msm/msm_gpu.h return msm_readl(gpu->mmio + (reg << 2)); reg 224 drivers/gpu/drm/msm/msm_gpu.h static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or) reg 226 drivers/gpu/drm/msm/msm_gpu.h uint32_t val = gpu_read(gpu, reg); reg 229 drivers/gpu/drm/msm/msm_gpu.h gpu_write(gpu, reg, val | or); reg 94 drivers/gpu/drm/mxsfb/mxsfb_crtc.c u32 reg; reg 96 drivers/gpu/drm/mxsfb/mxsfb_crtc.c reg = readl(mxsfb->base + LCDC_CTRL); reg 101 drivers/gpu/drm/mxsfb/mxsfb_crtc.c reg &= ~CTRL_BUS_WIDTH_MASK; reg 104 drivers/gpu/drm/mxsfb/mxsfb_crtc.c reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_16BIT); reg 107 drivers/gpu/drm/mxsfb/mxsfb_crtc.c reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_18BIT); reg 110 drivers/gpu/drm/mxsfb/mxsfb_crtc.c reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_24BIT); reg 116 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(reg, mxsfb->base + LCDC_CTRL); reg 121 drivers/gpu/drm/mxsfb/mxsfb_crtc.c u32 reg; reg 131 drivers/gpu/drm/mxsfb/mxsfb_crtc.c reg = readl(mxsfb->base + LCDC_VDCTRL4); reg 132 drivers/gpu/drm/mxsfb/mxsfb_crtc.c reg |= VDCTRL4_SYNC_SIGNALS_ON; reg 133 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(reg, mxsfb->base + LCDC_VDCTRL4); reg 140 drivers/gpu/drm/mxsfb/mxsfb_crtc.c u32 reg; reg 148 drivers/gpu/drm/mxsfb/mxsfb_crtc.c readl_poll_timeout(mxsfb->base + LCDC_CTRL, reg, !(reg & CTRL_RUN), reg 151 drivers/gpu/drm/mxsfb/mxsfb_crtc.c reg = readl(mxsfb->base + LCDC_VDCTRL4); reg 152 drivers/gpu/drm/mxsfb/mxsfb_crtc.c reg &= ~VDCTRL4_SYNC_SIGNALS_ON; reg 153 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(reg, mxsfb->base + LCDC_VDCTRL4); reg 167 drivers/gpu/drm/mxsfb/mxsfb_crtc.c u32 reg; reg 170 drivers/gpu/drm/mxsfb/mxsfb_crtc.c return readl_poll_timeout(addr, reg, !(reg & mask), 0, RESET_TIMEOUT); reg 300 drivers/gpu/drm/mxsfb/mxsfb_drv.c u32 reg; reg 304 drivers/gpu/drm/mxsfb/mxsfb_drv.c reg = readl(mxsfb->base + LCDC_CTRL1); reg 306 drivers/gpu/drm/mxsfb/mxsfb_drv.c if (reg & CTRL1_CUR_FRAME_DONE_IRQ) reg 174 drivers/gpu/drm/nouveau/dispnv04/hw.c if (ret || !(reg1 = pll_lim.reg)) reg 281 drivers/gpu/drm/nouveau/dispnv04/hw.c clk->pll_prog(clk, pll_lim.reg, &pv); reg 60 drivers/gpu/drm/nouveau/dispnv04/hw.h int head, uint32_t reg) reg 65 drivers/gpu/drm/nouveau/dispnv04/hw.h reg += NV_PCRTC0_SIZE; reg 66 drivers/gpu/drm/nouveau/dispnv04/hw.h val = nvif_rd32(device, reg); reg 71 drivers/gpu/drm/nouveau/dispnv04/hw.h int head, uint32_t reg, uint32_t val) reg 75 drivers/gpu/drm/nouveau/dispnv04/hw.h reg += NV_PCRTC0_SIZE; reg 76 drivers/gpu/drm/nouveau/dispnv04/hw.h nvif_wr32(device, reg, val); reg 80 drivers/gpu/drm/nouveau/dispnv04/hw.h int head, uint32_t reg) reg 85 drivers/gpu/drm/nouveau/dispnv04/hw.h reg += NV_PRAMDAC0_SIZE; reg 86 drivers/gpu/drm/nouveau/dispnv04/hw.h val = nvif_rd32(device, reg); reg 91 drivers/gpu/drm/nouveau/dispnv04/hw.h int head, uint32_t reg, uint32_t val) reg 95 drivers/gpu/drm/nouveau/dispnv04/hw.h reg += NV_PRAMDAC0_SIZE; reg 96 drivers/gpu/drm/nouveau/dispnv04/hw.h nvif_wr32(device, reg, val); reg 165 drivers/gpu/drm/nouveau/dispnv04/hw.h int head, uint32_t reg) reg 174 drivers/gpu/drm/nouveau/dispnv04/hw.h reg += NV_PRMVIO_SIZE; reg 176 drivers/gpu/drm/nouveau/dispnv04/hw.h val = nvif_rd08(device, reg); reg 181 drivers/gpu/drm/nouveau/dispnv04/hw.h int head, uint32_t reg, uint8_t value) reg 189 drivers/gpu/drm/nouveau/dispnv04/hw.h reg += NV_PRMVIO_SIZE; reg 191 drivers/gpu/drm/nouveau/dispnv04/hw.h nvif_wr08(device, reg, value); reg 130 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h static inline void nv_write_ptv(struct drm_device *dev, uint32_t reg, reg 134 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h nvif_wr32(&device->object, reg, val); reg 137 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h static inline uint32_t nv_read_ptv(struct drm_device *dev, uint32_t reg) reg 140 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h return nvif_rd32(&device->object, reg); reg 143 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h static inline void nv_write_tv_enc(struct drm_device *dev, uint8_t reg, reg 146 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h nv_write_ptv(dev, NV_PTV_TV_INDEX, reg); reg 150 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h static inline uint8_t nv_read_tv_enc(struct drm_device *dev, uint8_t reg) reg 152 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h nv_write_ptv(dev, NV_PTV_TV_INDEX, reg); reg 156 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h #define nv_load_ptv(dev, state, reg) \ reg 157 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h nv_write_ptv(dev, NV_PTV_OFFSET + 0x##reg, state->ptv_##reg) reg 158 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h #define nv_save_ptv(dev, state, reg) \ reg 159 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h state->ptv_##reg = nv_read_ptv(dev, NV_PTV_OFFSET + 0x##reg) reg 160 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h #define nv_load_tv_enc(dev, state, reg) \ reg 161 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h nv_write_tv_enc(dev, 0x##reg, state->tv_enc[0x##reg]) reg 46 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pll.h u32 reg; reg 98 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h nvkm_rdi2cr(struct i2c_adapter *adap, u8 addr, u8 reg) reg 102 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h { .addr = addr, .flags = 0, .len = 1, .buf = ® }, reg 114 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h nv_rd16i2cr(struct i2c_adapter *adap, u8 addr, u8 reg) reg 118 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h { .addr = addr, .flags = 0, .len = 1, .buf = ® }, reg 130 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h nvkm_wri2cr(struct i2c_adapter *adap, u8 addr, u8 reg, u8 val) reg 132 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h u8 buf[2] = { reg, val }; reg 145 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h nv_wr16i2cr(struct i2c_adapter *adap, u8 addr, u8 reg, u16 val) reg 147 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h u8 buf[3] = { reg, val >> 8, val & 0xff}; reg 84 drivers/gpu/drm/nouveau/nouveau_backlight.c int reg = nvif_rd32(device, NV40_PMC_BACKLIGHT); reg 87 drivers/gpu/drm/nouveau/nouveau_backlight.c (val << 16) | (reg & ~NV40_PMC_BACKLIGHT_MASK)); reg 52 drivers/gpu/drm/nouveau/nouveau_bo.c nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, reg 56 drivers/gpu/drm/nouveau/nouveau_bo.c int i = reg - drm->tile.reg; reg 60 drivers/gpu/drm/nouveau/nouveau_bo.c nouveau_fence_unref(®->fence); reg 75 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_drm_tile *tile = &drm->tile.reg[i]; reg 1038 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_channel *chan, struct ttm_mem_reg *reg) reg 1040 drivers/gpu/drm/nouveau/nouveau_bo.c if (reg->mem_type == TTM_PL_TT) reg 1093 drivers/gpu/drm/nouveau/nouveau_bo.c struct ttm_mem_reg *reg) reg 1096 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_mem *new_mem = nouveau_mem(reg); reg 1438 drivers/gpu/drm/nouveau/nouveau_bo.c nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) reg 1440 drivers/gpu/drm/nouveau/nouveau_bo.c struct ttm_mem_type_manager *man = &bdev->man[reg->mem_type]; reg 1443 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_mem *mem = nouveau_mem(reg); reg 1445 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.addr = NULL; reg 1446 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.offset = 0; reg 1447 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.size = reg->num_pages << PAGE_SHIFT; reg 1448 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.base = 0; reg 1449 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.is_iomem = false; reg 1452 drivers/gpu/drm/nouveau/nouveau_bo.c switch (reg->mem_type) { reg 1459 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.offset = reg->start << PAGE_SHIFT; reg 1460 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.base = drm->agp.base; reg 1461 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.is_iomem = !drm->agp.cma; reg 1469 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.offset = reg->start << PAGE_SHIFT; reg 1470 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.base = device->func->resource_addr(device, 1); reg 1471 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.is_iomem = true; reg 1506 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.base = 0; reg 1507 drivers/gpu/drm/nouveau/nouveau_bo.c reg->bus.offset = handle; reg 1517 drivers/gpu/drm/nouveau/nouveau_bo.c nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) reg 1520 drivers/gpu/drm/nouveau/nouveau_bo.c struct nouveau_mem *mem = nouveau_mem(reg); reg 1523 drivers/gpu/drm/nouveau/nouveau_bo.c switch (reg->mem_type) { reg 190 drivers/gpu/drm/nouveau/nouveau_drv.h struct nouveau_drm_tile reg[15]; reg 95 drivers/gpu/drm/nouveau/nouveau_mem.c nouveau_mem_host(struct ttm_mem_reg *reg, struct ttm_dma_tt *tt) reg 97 drivers/gpu/drm/nouveau/nouveau_mem.c struct nouveau_mem *mem = nouveau_mem(reg); reg 125 drivers/gpu/drm/nouveau/nouveau_mem.c reg->num_pages << PAGE_SHIFT, reg 133 drivers/gpu/drm/nouveau/nouveau_mem.c nouveau_mem_vram(struct ttm_mem_reg *reg, bool contig, u8 page) reg 135 drivers/gpu/drm/nouveau/nouveau_mem.c struct nouveau_mem *mem = nouveau_mem(reg); reg 140 drivers/gpu/drm/nouveau/nouveau_mem.c u64 size = ALIGN(reg->num_pages << PAGE_SHIFT, 1 << page); reg 171 drivers/gpu/drm/nouveau/nouveau_mem.c reg->start = mem->mem.addr >> PAGE_SHIFT; reg 176 drivers/gpu/drm/nouveau/nouveau_mem.c nouveau_mem_del(struct ttm_mem_reg *reg) reg 178 drivers/gpu/drm/nouveau/nouveau_mem.c struct nouveau_mem *mem = nouveau_mem(reg); reg 180 drivers/gpu/drm/nouveau/nouveau_mem.c kfree(reg->mm_node); reg 181 drivers/gpu/drm/nouveau/nouveau_mem.c reg->mm_node = NULL; reg 186 drivers/gpu/drm/nouveau/nouveau_mem.c struct ttm_mem_reg *reg) reg 196 drivers/gpu/drm/nouveau/nouveau_mem.c reg->mm_node = mem; reg 10 drivers/gpu/drm/nouveau/nouveau_mem.h nouveau_mem(struct ttm_mem_reg *reg) reg 12 drivers/gpu/drm/nouveau/nouveau_mem.h return reg->mm_node; reg 29 drivers/gpu/drm/nouveau/nouveau_sgdma.c nv04_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *reg) reg 32 drivers/gpu/drm/nouveau/nouveau_sgdma.c struct nouveau_mem *mem = nouveau_mem(reg); reg 35 drivers/gpu/drm/nouveau/nouveau_sgdma.c ret = nouveau_mem_host(reg, &nvbe->ttm); reg 64 drivers/gpu/drm/nouveau/nouveau_sgdma.c nv50_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *reg) reg 67 drivers/gpu/drm/nouveau/nouveau_sgdma.c struct nouveau_mem *mem = nouveau_mem(reg); reg 70 drivers/gpu/drm/nouveau/nouveau_sgdma.c ret = nouveau_mem_host(reg, &nvbe->ttm); reg 47 drivers/gpu/drm/nouveau/nouveau_ttm.c nouveau_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *reg) reg 49 drivers/gpu/drm/nouveau/nouveau_ttm.c nouveau_mem_del(reg); reg 62 drivers/gpu/drm/nouveau/nouveau_ttm.c struct ttm_mem_reg *reg) reg 71 drivers/gpu/drm/nouveau/nouveau_ttm.c ret = nouveau_mem_new(&drm->master, nvbo->kind, nvbo->comp, reg); reg 75 drivers/gpu/drm/nouveau/nouveau_ttm.c ret = nouveau_mem_vram(reg, nvbo->contig, nvbo->page); reg 77 drivers/gpu/drm/nouveau/nouveau_ttm.c nouveau_mem_del(reg); reg 79 drivers/gpu/drm/nouveau/nouveau_ttm.c reg->mm_node = NULL; reg 100 drivers/gpu/drm/nouveau/nouveau_ttm.c struct ttm_mem_reg *reg) reg 106 drivers/gpu/drm/nouveau/nouveau_ttm.c ret = nouveau_mem_new(&drm->master, nvbo->kind, nvbo->comp, reg); reg 110 drivers/gpu/drm/nouveau/nouveau_ttm.c reg->start = 0; reg 126 drivers/gpu/drm/nouveau/nouveau_ttm.c struct ttm_mem_reg *reg) reg 133 drivers/gpu/drm/nouveau/nouveau_ttm.c ret = nouveau_mem_new(&drm->master, nvbo->kind, nvbo->comp, reg); reg 134 drivers/gpu/drm/nouveau/nouveau_ttm.c mem = nouveau_mem(reg); reg 139 drivers/gpu/drm/nouveau/nouveau_ttm.c reg->num_pages << PAGE_SHIFT, &mem->vma[0]); reg 141 drivers/gpu/drm/nouveau/nouveau_ttm.c nouveau_mem_del(reg); reg 143 drivers/gpu/drm/nouveau/nouveau_ttm.c reg->mm_node = NULL; reg 149 drivers/gpu/drm/nouveau/nouveau_ttm.c reg->start = mem->vma[0].addr >> PAGE_SHIFT; reg 79 drivers/gpu/drm/nouveau/nv17_fence.c struct ttm_mem_reg *reg = &priv->bo->bo.mem; reg 80 drivers/gpu/drm/nouveau/nv17_fence.c u32 start = reg->start * PAGE_SIZE; reg 81 drivers/gpu/drm/nouveau/nv17_fence.c u32 limit = start + reg->size - 1; reg 40 drivers/gpu/drm/nouveau/nv50_fence.c struct ttm_mem_reg *reg = &priv->bo->bo.mem; reg 41 drivers/gpu/drm/nouveau/nv50_fence.c u32 start = reg->start * PAGE_SIZE; reg 42 drivers/gpu/drm/nouveau/nv50_fence.c u32 limit = start + reg->size - 1; reg 36 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nv40_fifo_dma_engine(struct nvkm_engine *engine, u32 *reg, u32 *ctx) reg 43 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c *reg = 0x0032e0; reg 49 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c *reg = 0x00330c; reg 67 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c u32 reg, ctx; reg 70 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c if (!nv40_fifo_dma_engine(engine, ®, &ctx)) reg 78 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nvkm_wr32(device, reg, 0x00000000); reg 97 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c u32 inst, reg, ctx; reg 100 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c if (!nv40_fifo_dma_engine(engine, ®, &ctx)) reg 109 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nvkm_wr32(device, reg, inst); reg 134 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c u32 reg, ctx; reg 136 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c if (!nv40_fifo_dma_engine(engine, ®, &ctx)) reg 43 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h cp_ctx(struct nvkm_grctx *ctx, u32 reg, u32 length) reg 45 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h ctx->ctxprog_reg = (reg - 0x00400000) >> 2; reg 121 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h gr_def(struct nvkm_grctx *ctx, u32 reg, u32 val) reg 126 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h reg = (reg - 0x00400000) / 4; reg 127 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base; reg 129 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h nvkm_wo32(ctx->data, reg * 4, val); reg 1135 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c static u32 *ctx_reg(struct nv04_gr_chan *chan, u32 reg) reg 1140 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c if (nv04_gr_ctx_regs[i] == reg) reg 786 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv10_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg) reg 791 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c if (nv10_gr_ctx_regs[i] == reg) reg 794 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nvkm_error(subdev, "unknown offset nv10_ctx_regs %d\n", reg); reg 799 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv17_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg) reg 804 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c if (nv17_gr_ctx_regs[i] == reg) reg 807 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nvkm_error(subdev, "unknown offset nv17_ctx_regs %d\n", reg); reg 989 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c #define NV_WRITE_CTX(reg, val) do { \ reg 990 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c int offset = nv10_gr_ctx_regs_find_offset(gr, reg); \ reg 995 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c #define NV17_WRITE_CTX(reg, val) do { \ reg 996 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c int offset = nv17_gr_ctx_regs_find_offset(gr, reg); \ reg 174 drivers/gpu/drm/nouveau/nvkm/falcon/base.c u32 reg; reg 183 drivers/gpu/drm/nouveau/nvkm/falcon/base.c reg = nvkm_falcon_rd32(falcon, 0x12c); reg 184 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->version = reg & 0xf; reg 185 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->secret = (reg >> 4) & 0x3; reg 186 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->code.ports = (reg >> 8) & 0xf; reg 187 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->data.ports = (reg >> 12) & 0xf; reg 189 drivers/gpu/drm/nouveau/nvkm/falcon/base.c reg = nvkm_falcon_rd32(falcon, 0x108); reg 190 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->code.limit = (reg & 0x1ff) << 8; reg 191 drivers/gpu/drm/nouveau/nvkm/falcon/base.c falcon->data.limit = (reg & 0x3fe00) >> 1; reg 33 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c u32 reg; reg 38 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c reg = start | BIT(24) | (secure ? BIT(28) : 0); reg 39 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_wr32(falcon, 0x180 + (port * 16), reg); reg 283 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c u32 reg = nvkm_falcon_rd32(falcon, 0x100); reg 285 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c if (reg & BIT(6)) reg 144 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_nvreg(struct nvbios_init *init, u32 reg) reg 154 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c reg &= ~0x00000003; reg 160 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c if (reg & 0x80000000) { reg 161 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c reg += init_head(init) * 0x800; reg 162 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c reg &= ~0x80000000; reg 165 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c if (reg & 0x40000000) { reg 166 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c reg += init_or(init) * 0x800; reg 167 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c reg &= ~0x40000000; reg 168 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c if (reg & 0x20000000) { reg 169 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c reg += init_link(init) * 0x80; reg 170 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c reg &= ~0x20000000; reg 175 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c if (reg & ~0x00fffffc) reg 176 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c warn("unknown bits in register 0x%08x\n", reg); reg 178 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c return nvkm_devinit_mmio(devinit, reg); reg 182 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_rd32(struct nvbios_init *init, u32 reg) reg 185 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c reg = init_nvreg(init, reg); reg 186 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c if (reg != ~0 && init_exec(init)) reg 187 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c return nvkm_rd32(device, reg); reg 192 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wr32(struct nvbios_init *init, u32 reg, u32 val) reg 195 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c reg = init_nvreg(init, reg); reg 196 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c if (reg != ~0 && init_exec(init)) reg 197 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c nvkm_wr32(device, reg, val); reg 201 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val) reg 204 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c reg = init_nvreg(init, reg); reg 205 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c if (reg != ~0 && init_exec(init)) { reg 206 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 tmp = nvkm_rd32(device, reg); reg 207 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c nvkm_wr32(device, reg, (tmp & ~mask) | val); reg 285 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg) reg 289 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c return nvkm_rdi2cr(adap, addr, reg); reg 294 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val) reg 298 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c return nvkm_wri2cr(adap, addr, reg, val); reg 484 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 reg = nvbios_rd32(bios, table + (cond * 12) + 0); reg 488 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c cond, reg, msk, val); reg 489 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c return (init_rd32(init, reg) & msk) == val; reg 629 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 reg = nvbios_rd32(bios, init->offset + 7); reg 634 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c reg, port, index, mask, shift); reg 643 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wr32(init, reg, data); reg 693 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 reg = nvbios_rd32(bios, init->offset + 8); reg 698 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c reg, port, index, mask, shift, iofc); reg 709 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_prog_pll(init, reg, freq); reg 743 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 reg = nvbios_rd32(bios, init->offset + 1); reg 753 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c port, index, mask, reg, (shift & 0x80) ? "<<" : ">>", reg 758 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c data |= init_shift(init_rd32(init, reg), shift) & smask; reg 889 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 reg = nvbios_rd32(bios, init->offset + 1); reg 892 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask); reg 895 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_mask(init, reg, mask, 0); reg 906 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 reg = nvbios_rd32(bios, init->offset + 1); reg 909 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask); reg 912 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_mask(init, reg, 0, mask); reg 958 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 reg = nvbios_rd32(bios, init->offset + 7); reg 963 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c reg, port, index, mask, shift); reg 971 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_prog_pll(init, reg, freq); reg 988 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 reg = nvbios_rd32(bios, init->offset + 1); reg 991 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq); reg 994 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_prog_pll(init, reg, freq); reg 1013 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 reg = nvbios_rd08(bios, init->offset + 0); reg 1018 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data); reg 1021 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c val = init_rdi2cr(init, index, addr, reg); reg 1024 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wri2cr(init, index, addr, reg, (val & mask) | data); reg 1044 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 reg = nvbios_rd08(bios, init->offset + 0); reg 1047 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("\t[0x%02x] = 0x%02x\n", reg, data); reg 1050 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wri2cr(init, index, addr, reg, data); reg 1100 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 reg = init_tmds_reg(init, tmds); reg 1106 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c if (reg == 0) reg 1109 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wr32(init, reg + 0, addr | 0x00010000); reg 1110 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask)); reg 1111 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wr32(init, reg + 0, addr); reg 1124 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 reg = init_tmds_reg(init, tmds); reg 1136 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wr32(init, reg + 4, data); reg 1137 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wr32(init, reg + 0, addr); reg 1309 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 reg = nvbios_rd32(bios, init->offset + 1); reg 1314 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c reg, addr, freq); reg 1317 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_prog_pll(init, reg, freq); reg 1328 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 reg = nvbios_rd32(bios, init->offset + 1); reg 1333 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c reg, addr, data); reg 1393 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 reg = nvbios_rd08(bios, init->offset + 3); reg 1399 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c index, addr, reg, mask, data); reg 1403 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c value = init_rdi2cr(init, index, addr, reg); reg 1480 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 reg = nvbios_rd32(bios, init->offset + 1); reg 1485 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2); reg 1490 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wr32(init, reg, data1); reg 1492 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wr32(init, reg, data2); reg 1712 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 reg = nvbios_rd32(bios, init->offset + 1); reg 1716 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data); reg 1719 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_mask(init, reg, ~mask, data); reg 1878 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 reg = nvbios_rd32(bios, init->offset + 1); reg 1881 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq); reg 1884 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_prog_pll(init, reg, freq); reg 33 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c u32 reg; reg 144 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c pll_map_reg(struct nvkm_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len) reg 154 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c if (nvbios_rd32(bios, data + 3) == reg) { reg 164 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c while (map && map->reg) { reg 165 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c if (map->reg == reg && *ver >= 0x20) { reg 169 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c if (nvbios_rd32(bios, data) == map->reg) reg 175 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c if (map->reg == reg) { reg 186 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c pll_map_type(struct nvkm_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len) reg 198 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c *reg = nvbios_rd32(bios, data + 3); reg 200 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c *reg = 0; reg 209 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c while (map && map->reg) { reg 212 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c *reg = map->reg; reg 214 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c if (nvbios_rd32(bios, data) == map->reg) reg 221 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c *reg = map->reg; reg 236 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c u32 reg = type; reg 240 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c reg = type; reg 241 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c data = pll_map_reg(bios, reg, &type, &ver, &len); reg 243 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c data = pll_map_type(bios, type, ®, &ver, &len); reg 251 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c info->reg = reg; reg 391 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c if ((info->reg == 0x680508 && sel_clk & 0x20) || reg 392 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c (info->reg == 0x680520 && sel_clk & 0x80)) { reg 86 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_rd32(struct hwsq *ram, struct hwsq_reg *reg) reg 89 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h if (reg->sequence != ram->sequence) reg 90 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h reg->data = nvkm_rd32(device, reg->addr); reg 91 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h return reg->data; reg 95 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_wr32(struct hwsq *ram, struct hwsq_reg *reg, u32 data) reg 99 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h reg->sequence = ram->sequence; reg 100 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h reg->data = data; reg 102 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h for (mask = reg->mask; mask > 0; mask = (mask & ~1) >> 1) { reg 104 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h nvkm_hwsq_wr32(ram->hwsq, reg->addr+off, reg->data); reg 106 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h off += reg->stride; reg 111 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_nuke(struct hwsq *ram, struct hwsq_reg *reg) reg 113 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h reg->force = true; reg 117 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_mask(struct hwsq *ram, struct hwsq_reg *reg, u32 mask, u32 data) reg 119 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h u32 temp = hwsq_rd32(ram, reg); reg 120 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h if (temp != ((temp & ~mask) | data) || reg->force) reg 121 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_wr32(ram, reg, (temp & ~mask) | data); reg 165 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c calc_pll(struct mcp77_clk *clk, u32 reg, reg 172 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c ret = nvbios_pll_parse(subdev->device->bios, reg, &pll); reg 40 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c read_pll_1(struct nv40_clk *clk, u32 reg) reg 43 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c u32 ctrl = nvkm_rd32(device, reg + 0x00); reg 56 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c read_pll_2(struct nv40_clk *clk, u32 reg) reg 59 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c u32 ctrl = nvkm_rd32(device, reg + 0x00); reg 60 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c u32 coef = nvkm_rd32(device, reg + 0x04); reg 124 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c nv40_clk_calc_pll(struct nv40_clk *clk, u32 reg, u32 khz, reg 131 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c ret = nvbios_pll_parse(subdev->device->bios, reg, &pll); reg 325 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c calc_pll(struct nv50_clk *clk, u32 reg, u32 idx, int *N, int *M, int *P) reg 331 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c ret = nvbios_pll_parse(subdev->device->bios, reg, &pll); reg 336 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c pll.refclk = read_pll_ref(clk, reg); reg 53 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c nvkm_mask(device, info.reg + 0x0c, 0x00000000, 0x00000100); reg 54 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c nvkm_wr32(device, info.reg + 0x04, (P << 16) | (N << 8) | M); reg 55 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c nvkm_wr32(device, info.reg + 0x10, fN << 16); reg 51 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c nvkm_wr32(device, info.reg + 0, 0x50000610); reg 52 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c nvkm_mask(device, info.reg + 4, 0x003fffff, reg 54 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c nvkm_wr32(device, info.reg + 8, fN); reg 113 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c powerctrl_1_shift(int chip_version, int reg) reg 120 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c switch (reg) { reg 143 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c setPLL_single(struct nvkm_devinit *init, u32 reg, reg 148 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t oldpll = nvkm_rd32(device, reg); reg 152 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg); reg 166 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c nvkm_wr32(device, reg, pv->log2P << 16 | (oldpll & 0xffff)); reg 169 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c nvkm_wr32(device, reg, (oldpll & 0xffff0000) | pv->NM1); reg 175 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c nvkm_rd32(device, reg); reg 178 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c nvkm_wr32(device, reg, pll); reg 59 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c nvkm_wr32(device, info.reg + 0, 0x10000611); reg 60 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c nvkm_mask(device, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1); reg 61 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c nvkm_mask(device, info.reg + 8, 0x7fff00ff, (P << 28) | reg 65 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c nvkm_mask(device, info.reg + 0, 0x01ff0000, reg 69 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1); reg 72 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c nvkm_mask(device, info.reg + 0, 0x00070000, (P << 16)); reg 73 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1); reg 82 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h ramfuc_rd32(struct ramfuc *ram, struct ramfuc_reg *reg) reg 85 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h if (reg->sequence != ram->sequence) reg 86 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h reg->data = nvkm_rd32(device, reg->addr); reg 87 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h return reg->data; reg 91 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h ramfuc_wr32(struct ramfuc *ram, struct ramfuc_reg *reg, u32 data) reg 95 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h reg->sequence = ram->sequence; reg 96 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h reg->data = data; reg 98 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h for (mask = reg->mask; mask > 0; mask = (mask & ~1) >> 1) { reg 100 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h nvkm_memx_wr32(ram->memx, reg->addr+off, reg->data); reg 101 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h off += reg->stride; reg 106 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h ramfuc_nuke(struct ramfuc *ram, struct ramfuc_reg *reg) reg 108 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h reg->force = true; reg 112 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h ramfuc_mask(struct ramfuc *ram, struct ramfuc_reg *reg, u32 mask, u32 data) reg 114 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h u32 temp = ramfuc_rd32(ram, reg); reg 115 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h if (temp != ((temp & ~mask) | data) || reg->force) { reg 116 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h ramfuc_wr32(ram, reg, (temp & ~mask) | data); reg 117 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h reg->force = false; reg 229 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg, reg 235 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c u32 addr = 0x110000 + (reg->addr & 0xfff); reg 237 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c u32 data = (_data & _mask) | (reg->data & _copy); reg 470 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c u32 reg, sh, gpio_val; reg 478 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c reg = func.line >> 3; reg 480 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c gpio_val = ram_rd32(fuc, gpio[reg]); reg 486 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram_mask(fuc, gpio[reg], (0x3 << sh), ((val | 0x2) << sh)); reg 196 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c u32 reg, sh, gpio_val; reg 204 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c reg = func.line >> 3; reg 206 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c gpio_val = ram_rd32(hwsq, gpio[reg]); reg 213 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c ram_mask(hwsq, gpio[reg], (0x3 << sh), ((val | 0x2) << sh)); reg 55 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c u32 reg, mask, data; reg 59 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c reg = 0x600818; reg 65 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c reg = 0x60081c; reg 71 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c reg = 0x600850; reg 78 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c nvkm_mask(device, reg, mask << line, data << line); reg 44 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c u32 reg = regs[line >> 4]; reg 53 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c nvkm_mask(device, reg, 0x00010001 << lsh, val << lsh); reg 58 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c nv50_gpio_location(int line, u32 *reg, u32 *shift) reg 65 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c *reg = nv50_gpio_reg[line >> 3]; reg 74 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c u32 reg, shift; reg 76 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c if (nv50_gpio_location(line, ®, &shift)) reg 79 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c nvkm_mask(device, reg, 3 << shift, (((dir ^ 1) << 1) | out) << shift); reg 87 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c u32 reg, shift; reg 89 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c if (nv50_gpio_location(line, ®, &shift)) reg 92 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c return !!(nvkm_rd32(device, reg) & (4 << shift)); reg 38 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c u32 reg; reg 41 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c reg = nvkm_rd32(device, 0x100cd0); reg 43 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c return (reg & BIT(4)); reg 126 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c u32 reg = nvkm_rd32(device, 0x0010f0); reg 127 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c if (reg & 0x80000000) { reg 128 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c *duty = (reg & 0x7fff0000) >> 16; reg 129 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c *divs = (reg & 0x00007fff); reg 134 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c u32 reg = nvkm_rd32(device, 0x0015f4); reg 135 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c if (reg & 0x80000000) { reg 137 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c *duty = (reg & 0x7fffffff); reg 230 drivers/gpu/drm/omapdrm/dss/dispc.c u16 reg; reg 238 drivers/gpu/drm/omapdrm/dss/dispc.c u16 reg; reg 258 drivers/gpu/drm/omapdrm/dss/dispc.c .reg = DISPC_GAMMA_TABLE0, reg 281 drivers/gpu/drm/omapdrm/dss/dispc.c .reg = DISPC_GAMMA_TABLE2, reg 304 drivers/gpu/drm/omapdrm/dss/dispc.c .reg = DISPC_GAMMA_TABLE1, reg 327 drivers/gpu/drm/omapdrm/dss/dispc.c .reg = DISPC_GAMMA_TABLE3, reg 373 drivers/gpu/drm/omapdrm/dss/dispc.c return REG_GET(dispc, rfld.reg, rfld.high, rfld.low); reg 380 drivers/gpu/drm/omapdrm/dss/dispc.c const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG; reg 385 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low); reg 388 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low); reg 426 drivers/gpu/drm/omapdrm/dss/dispc.c #define SR(dispc, reg) \ reg 427 drivers/gpu/drm/omapdrm/dss/dispc.c dispc->ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(dispc, DISPC_##reg) reg 428 drivers/gpu/drm/omapdrm/dss/dispc.c #define RR(dispc, reg) \ reg 429 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_##reg, dispc->ctx[DISPC_##reg / sizeof(u32)]) reg 762 drivers/gpu/drm/omapdrm/dss/dispc.c enum omap_plane_id plane, int reg, reg 765 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H(plane, reg), value); reg 769 drivers/gpu/drm/omapdrm/dss/dispc.c enum omap_plane_id plane, int reg, reg 772 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV(plane, reg), value); reg 776 drivers/gpu/drm/omapdrm/dss/dispc.c enum omap_plane_id plane, int reg, reg 779 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V(plane, reg), value); reg 783 drivers/gpu/drm/omapdrm/dss/dispc.c enum omap_plane_id plane, int reg, reg 788 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H2(plane, reg), value); reg 792 drivers/gpu/drm/omapdrm/dss/dispc.c enum omap_plane_id plane, int reg, reg 797 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV2(plane, reg), value); reg 801 drivers/gpu/drm/omapdrm/dss/dispc.c enum omap_plane_id plane, int reg, reg 806 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V2(plane, reg), value); reg 3816 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, gdesc->reg, v); reg 105 drivers/gpu/drm/omapdrm/dss/dss.c #define SR(dss, reg) \ reg 106 drivers/gpu/drm/omapdrm/dss/dss.c dss->ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(dss, DSS_##reg) reg 107 drivers/gpu/drm/omapdrm/dss/dss.c #define RR(dss, reg) \ reg 108 drivers/gpu/drm/omapdrm/dss/dss.c dss_write_reg(dss, DSS_##reg, dss->ctx[(DSS_##reg).idx / sizeof(u32)]) reg 88 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c unsigned int reg = HDMI_CEC_RX_OPERAND + i * 4; reg 91 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c hdmi_read_reg(core->base, reg); reg 323 drivers/gpu/drm/omapdrm/dss/pll.c static int wait_for_bit_change(void __iomem *reg, int bitnum, int value) reg 332 drivers/gpu/drm/omapdrm/dss/pll.c if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value) reg 339 drivers/gpu/drm/omapdrm/dss/pll.c if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value) reg 25 drivers/gpu/drm/omapdrm/dss/video-pll.c #define REG_MOD(reg, val, start, end) \ reg 26 drivers/gpu/drm/omapdrm/dss/video-pll.c writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg) reg 76 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c static const u32 reg[][4] = { reg 111 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c static u32 dmm_read_wa(struct dmm *dmm, u32 reg) reg 116 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c src = dmm->phys_base + reg; reg 122 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c return readl(dmm->base + reg); reg 134 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c static void dmm_write_wa(struct dmm *dmm, u32 val, u32 reg) reg 149 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c dst = dmm->phys_base + reg; reg 154 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c writel(val, dmm->base + reg); reg 158 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c static u32 dmm_read(struct dmm *dmm, u32 reg) reg 165 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c v = dmm_read_wa(dmm, reg); reg 170 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c return readl(dmm->base + reg); reg 174 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c static void dmm_write(struct dmm *dmm, u32 val, u32 reg) reg 180 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c dmm_write_wa(dmm, val, reg); reg 183 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c writel(val, dmm->base + reg); reg 246 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c r = dmm_read(dmm, reg[PAT_STATUS][engine->id]); reg 426 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c dmm_write(dmm, 0x0, reg[PAT_DESCR][engine->id]); reg 442 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c dmm_write(dmm, engine->refill_pa, reg[PAT_DESCR][engine->id]); reg 305 drivers/gpu/drm/panel/panel-ilitek-ili9322.c static int ili9322_regmap_spi_read(void *context, const void *reg, reg 313 drivers/gpu/drm/panel/panel-ilitek-ili9322.c memcpy(buf, reg, 1); reg 328 drivers/gpu/drm/panel/panel-ilitek-ili9322.c static bool ili9322_volatile_reg(struct device *dev, unsigned int reg) reg 333 drivers/gpu/drm/panel/panel-ilitek-ili9322.c static bool ili9322_writeable_reg(struct device *dev, unsigned int reg) reg 336 drivers/gpu/drm/panel/panel-ilitek-ili9322.c if (reg == 0x00) reg 352 drivers/gpu/drm/panel/panel-ilitek-ili9322.c u8 reg; reg 409 drivers/gpu/drm/panel/panel-ilitek-ili9322.c reg = 0; reg 411 drivers/gpu/drm/panel/panel-ilitek-ili9322.c reg = ILI9322_POL_DCLK; reg 413 drivers/gpu/drm/panel/panel-ilitek-ili9322.c reg |= ILI9322_POL_DE; reg 415 drivers/gpu/drm/panel/panel-ilitek-ili9322.c reg |= ILI9322_POL_HSYNC; reg 417 drivers/gpu/drm/panel/panel-ilitek-ili9322.c reg |= ILI9322_POL_VSYNC; reg 418 drivers/gpu/drm/panel/panel-ilitek-ili9322.c ret = regmap_write(ili->regmap, ILI9322_POL, reg); reg 428 drivers/gpu/drm/panel/panel-ilitek-ili9322.c reg = ili->conf->syncmode; reg 429 drivers/gpu/drm/panel/panel-ilitek-ili9322.c reg |= ILI9322_IF_CTRL_LINE_INVERSION; reg 430 drivers/gpu/drm/panel/panel-ilitek-ili9322.c ret = regmap_write(ili->regmap, ILI9322_IF_CTRL, reg); reg 437 drivers/gpu/drm/panel/panel-ilitek-ili9322.c reg = (ili->input << 4); reg 440 drivers/gpu/drm/panel/panel-ilitek-ili9322.c reg |= ILI9322_ENTRY_HDIR; reg 442 drivers/gpu/drm/panel/panel-ilitek-ili9322.c reg |= ILI9322_ENTRY_VDIR; reg 443 drivers/gpu/drm/panel/panel-ilitek-ili9322.c reg |= ILI9322_ENTRY_AUTODETECT; reg 444 drivers/gpu/drm/panel/panel-ilitek-ili9322.c ret = regmap_write(ili->regmap, ILI9322_ENTRY, reg); reg 32 drivers/gpu/drm/panel/panel-lg-lb035q02.c static int lb035q02_write(struct lb035q02_device *lcd, u16 reg, u16 val) reg 49 drivers/gpu/drm/panel/panel-lg-lb035q02.c buffer[2] = reg & 0x7f; reg 74 drivers/gpu/drm/panel/panel-novatek-nt39016.c #define RV(REG, VAL) { .reg = (REG), .def = (VAL), .delay_us = 2 } reg 223 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c static int rpi_touchscreen_i2c_read(struct rpi_touchscreen *ts, u8 reg) reg 225 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c return i2c_smbus_read_byte_data(ts->i2c, reg); reg 229 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c u8 reg, u8 val) reg 233 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c ret = i2c_smbus_write_byte_data(ts->i2c, reg, val); reg 238 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c static int rpi_touchscreen_write(struct rpi_touchscreen *ts, u16 reg, u32 val) reg 241 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c reg, reg 242 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c reg >> 8, reg 129 drivers/gpu/drm/panel/panel-sony-acx565akm.c int reg, const u8 *buf, int len) reg 131 drivers/gpu/drm/panel/panel-sony-acx565akm.c acx565akm_transfer(lcd, reg, buf, len, NULL, 0); reg 135 drivers/gpu/drm/panel/panel-sony-acx565akm.c int reg, u8 *buf, int len) reg 137 drivers/gpu/drm/panel/panel-sony-acx565akm.c acx565akm_transfer(lcd, reg, NULL, 0, buf, len); reg 91 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c static int jbt_ret_write_0(struct td028ttec1_panel *lcd, u8 reg, int *err) reg 94 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c u16 tx_buf = JBT_COMMAND | reg; reg 111 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c u8 reg, u8 data, int *err) reg 120 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c tx_buf[0] = JBT_COMMAND | reg; reg 134 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c u8 reg, u16 data, int *err) reg 143 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c tx_buf[0] = JBT_COMMAND | reg; reg 23 drivers/gpu/drm/panfrost/panfrost_job.c #define job_write(dev, reg, data) writel(data, dev->iomem + (reg)) reg 24 drivers/gpu/drm/panfrost/panfrost_job.c #define job_read(dev, reg) readl(dev->iomem + (reg)) reg 23 drivers/gpu/drm/panfrost/panfrost_mmu.c #define mmu_write(dev, reg, data) writel(data, dev->iomem + reg) reg 24 drivers/gpu/drm/panfrost/panfrost_mmu.c #define mmu_read(dev, reg) readl(dev->iomem + reg) reg 317 drivers/gpu/drm/panfrost/panfrost_regs.h #define gpu_write(dev, reg, data) writel(data, dev->iomem + reg) reg 318 drivers/gpu/drm/panfrost/panfrost_regs.h #define gpu_read(dev, reg) readl(dev->iomem + reg) reg 14 drivers/gpu/drm/pl111/pl111_debugfs.c #define REGDEF(reg) { reg, #reg } reg 16 drivers/gpu/drm/pl111/pl111_debugfs.c u32 reg; reg 43 drivers/gpu/drm/pl111/pl111_debugfs.c pl111_reg_defs[i].name, pl111_reg_defs[i].reg, reg 44 drivers/gpu/drm/pl111/pl111_debugfs.c readl(priv->regs + pl111_reg_defs[i].reg)); reg 406 drivers/gpu/drm/r128/r128_drv.h #define R128_READ(reg) readl(((void __iomem *)dev_priv->mmio->handle) + (reg)) reg 407 drivers/gpu/drm/r128/r128_drv.h #define R128_WRITE(reg, val) writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) reg 408 drivers/gpu/drm/r128/r128_drv.h #define R128_READ8(reg) readb(((void __iomem *)dev_priv->mmio->handle) + (reg)) reg 409 drivers/gpu/drm/r128/r128_drv.h #define R128_WRITE8(reg, val) writeb(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) reg 418 drivers/gpu/drm/r128/r128_drv.h #define CCE_PACKET0(reg, n) (R128_CCE_PACKET0 | \ reg 419 drivers/gpu/drm/r128/r128_drv.h ((n) << 16) | ((reg) >> 2)) reg 1549 drivers/gpu/drm/radeon/atombios_encoders.c uint32_t temp, reg; reg 1554 drivers/gpu/drm/radeon/atombios_encoders.c reg = R600_BIOS_3_SCRATCH; reg 1556 drivers/gpu/drm/radeon/atombios_encoders.c reg = RADEON_BIOS_3_SCRATCH; reg 1559 drivers/gpu/drm/radeon/atombios_encoders.c temp = RREG32(reg); reg 1561 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(reg, (ATOM_S3_TV1_ACTIVE | reg 1564 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); reg 1566 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(reg, 0); reg 1574 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(reg, temp); reg 1634 drivers/gpu/drm/radeon/atombios_encoders.c u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); reg 1635 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); reg 1637 drivers/gpu/drm/radeon/atombios_encoders.c WREG32(RADEON_BIOS_3_SCRATCH, reg); reg 163 drivers/gpu/drm/radeon/cik.c u32 reg, u32 *val) reg 165 drivers/gpu/drm/radeon/cik.c switch (reg) { reg 178 drivers/gpu/drm/radeon/cik.c *val = RREG32(reg); reg 188 drivers/gpu/drm/radeon/cik.c u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) reg 194 drivers/gpu/drm/radeon/cik.c WREG32(CIK_DIDT_IND_INDEX, (reg)); reg 200 drivers/gpu/drm/radeon/cik.c void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) reg 205 drivers/gpu/drm/radeon/cik.c WREG32(CIK_DIDT_IND_INDEX, (reg)); reg 250 drivers/gpu/drm/radeon/cik.c u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg) reg 256 drivers/gpu/drm/radeon/cik.c WREG32(PCIE_INDEX, reg); reg 263 drivers/gpu/drm/radeon/cik.c void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) reg 268 drivers/gpu/drm/radeon/cik.c WREG32(PCIE_INDEX, reg); reg 3444 drivers/gpu/drm/radeon/cik.c rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); reg 5555 drivers/gpu/drm/radeon/cik.c uint32_t reg; reg 5557 drivers/gpu/drm/radeon/cik.c reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2); reg 5559 drivers/gpu/drm/radeon/cik.c reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2); reg 5560 drivers/gpu/drm/radeon/cik.c rdev->vm_manager.saved_table_addr[i] = RREG32(reg); reg 66 drivers/gpu/drm/radeon/cik_sdma.c u32 rptr, reg; reg 72 drivers/gpu/drm/radeon/cik_sdma.c reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET; reg 74 drivers/gpu/drm/radeon/cik_sdma.c reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET; reg 76 drivers/gpu/drm/radeon/cik_sdma.c rptr = RREG32(reg); reg 93 drivers/gpu/drm/radeon/cik_sdma.c u32 reg; reg 96 drivers/gpu/drm/radeon/cik_sdma.c reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; reg 98 drivers/gpu/drm/radeon/cik_sdma.c reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; reg 100 drivers/gpu/drm/radeon/cik_sdma.c return (RREG32(reg) & 0x3fffc) >> 2; reg 114 drivers/gpu/drm/radeon/cik_sdma.c u32 reg; reg 117 drivers/gpu/drm/radeon/cik_sdma.c reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; reg 119 drivers/gpu/drm/radeon/cik_sdma.c reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; reg 121 drivers/gpu/drm/radeon/cik_sdma.c WREG32(reg, (ring->wptr << 2) & 0x3fffc); reg 122 drivers/gpu/drm/radeon/cik_sdma.c (void)RREG32(reg); reg 1682 drivers/gpu/drm/radeon/cikd.h #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ reg 1683 drivers/gpu/drm/radeon/cikd.h (((reg) >> 2) & 0xFFFF) | \ reg 33 drivers/gpu/drm/radeon/dce6_afmt.c u32 block_offset, u32 reg) reg 39 drivers/gpu/drm/radeon/dce6_afmt.c WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); reg 47 drivers/gpu/drm/radeon/dce6_afmt.c u32 block_offset, u32 reg, u32 v) reg 53 drivers/gpu/drm/radeon/dce6_afmt.c WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); reg 56 drivers/gpu/drm/radeon/dce6_afmt.c AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg)); reg 49 drivers/gpu/drm/radeon/evergreen.c u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) reg 55 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); reg 61 drivers/gpu/drm/radeon/evergreen.c void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) reg 66 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); reg 71 drivers/gpu/drm/radeon/evergreen.c u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) reg 77 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); reg 83 drivers/gpu/drm/radeon/evergreen.c void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) reg 88 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); reg 93 drivers/gpu/drm/radeon/evergreen.c u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) reg 99 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); reg 105 drivers/gpu/drm/radeon/evergreen.c void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) reg 110 drivers/gpu/drm/radeon/evergreen.c WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); reg 1097 drivers/gpu/drm/radeon/evergreen.c u32 reg, u32 *val) reg 1099 drivers/gpu/drm/radeon/evergreen.c switch (reg) { reg 1107 drivers/gpu/drm/radeon/evergreen.c *val = RREG32(reg); reg 1050 drivers/gpu/drm/radeon/evergreen_cs.c unsigned idx, unsigned reg) reg 1054 drivers/gpu/drm/radeon/evergreen_cs.c switch (reg) { reg 1059 drivers/gpu/drm/radeon/evergreen_cs.c idx, reg); reg 1064 drivers/gpu/drm/radeon/evergreen_cs.c pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx); reg 1073 drivers/gpu/drm/radeon/evergreen_cs.c unsigned reg, i; reg 1078 drivers/gpu/drm/radeon/evergreen_cs.c reg = pkt->reg; reg 1079 drivers/gpu/drm/radeon/evergreen_cs.c for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { reg 1080 drivers/gpu/drm/radeon/evergreen_cs.c r = evergreen_packet0_check(p, pkt, idx, reg); reg 1094 drivers/gpu/drm/radeon/evergreen_cs.c static int evergreen_cs_handle_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) reg 1102 drivers/gpu/drm/radeon/evergreen_cs.c switch (reg) { reg 1146 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1158 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1165 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1175 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1217 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1229 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1241 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1253 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1276 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1279 drivers/gpu/drm/radeon/evergreen_cs.c tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; reg 1289 drivers/gpu/drm/radeon/evergreen_cs.c tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16; reg 1298 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1314 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1323 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1337 drivers/gpu/drm/radeon/evergreen_cs.c tmp = (reg - CB_COLOR0_VIEW) / 0x3c; reg 1345 drivers/gpu/drm/radeon/evergreen_cs.c tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8; reg 1357 drivers/gpu/drm/radeon/evergreen_cs.c tmp = (reg - CB_COLOR0_INFO) / 0x3c; reg 1363 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1375 drivers/gpu/drm/radeon/evergreen_cs.c tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8; reg 1381 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1397 drivers/gpu/drm/radeon/evergreen_cs.c tmp = (reg - CB_COLOR0_PITCH) / 0x3c; reg 1405 drivers/gpu/drm/radeon/evergreen_cs.c tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8; reg 1417 drivers/gpu/drm/radeon/evergreen_cs.c tmp = (reg - CB_COLOR0_SLICE) / 0x3c; reg 1426 drivers/gpu/drm/radeon/evergreen_cs.c tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8; reg 1442 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1459 drivers/gpu/drm/radeon/evergreen_cs.c tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c); reg 1470 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1487 drivers/gpu/drm/radeon/evergreen_cs.c tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8; reg 1499 drivers/gpu/drm/radeon/evergreen_cs.c tmp = (reg - CB_COLOR0_FMASK) / 0x3c; reg 1502 drivers/gpu/drm/radeon/evergreen_cs.c dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); reg 1516 drivers/gpu/drm/radeon/evergreen_cs.c tmp = (reg - CB_COLOR0_CMASK) / 0x3c; reg 1519 drivers/gpu/drm/radeon/evergreen_cs.c dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); reg 1533 drivers/gpu/drm/radeon/evergreen_cs.c tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c; reg 1544 drivers/gpu/drm/radeon/evergreen_cs.c tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c; reg 1558 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1561 drivers/gpu/drm/radeon/evergreen_cs.c tmp = (reg - CB_COLOR0_BASE) / 0x3c; reg 1574 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1577 drivers/gpu/drm/radeon/evergreen_cs.c tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8; reg 1587 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1705 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1713 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1719 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1727 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1733 drivers/gpu/drm/radeon/evergreen_cs.c "0x%04X\n", reg); reg 1742 drivers/gpu/drm/radeon/evergreen_cs.c dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); reg 1756 drivers/gpu/drm/radeon/evergreen_cs.c static inline bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg) reg 1761 drivers/gpu/drm/radeon/evergreen_cs.c i = (reg >> 7); reg 1765 drivers/gpu/drm/radeon/evergreen_cs.c m = 1 << ((reg >> 2) & 31); reg 1780 drivers/gpu/drm/radeon/evergreen_cs.c unsigned start_reg, end_reg, reg; reg 2309 drivers/gpu/drm/radeon/evergreen_cs.c for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) { reg 2310 drivers/gpu/drm/radeon/evergreen_cs.c if (evergreen_is_safe_reg(p, reg)) reg 2312 drivers/gpu/drm/radeon/evergreen_cs.c r = evergreen_cs_handle_reg(p, reg, idx); reg 2326 drivers/gpu/drm/radeon/evergreen_cs.c for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) { reg 2327 drivers/gpu/drm/radeon/evergreen_cs.c if (evergreen_is_safe_reg(p, reg)) reg 2329 drivers/gpu/drm/radeon/evergreen_cs.c r = evergreen_cs_handle_reg(p, reg, idx); reg 2583 drivers/gpu/drm/radeon/evergreen_cs.c reg = radeon_get_ib_value(p, idx+1) << 2; reg 2584 drivers/gpu/drm/radeon/evergreen_cs.c if (!evergreen_is_safe_reg(p, reg)) { reg 2586 drivers/gpu/drm/radeon/evergreen_cs.c reg, idx + 1); reg 2610 drivers/gpu/drm/radeon/evergreen_cs.c reg = radeon_get_ib_value(p, idx+3) << 2; reg 2611 drivers/gpu/drm/radeon/evergreen_cs.c if (!evergreen_is_safe_reg(p, reg)) { reg 2613 drivers/gpu/drm/radeon/evergreen_cs.c reg, idx + 3); reg 3226 drivers/gpu/drm/radeon/evergreen_cs.c static bool evergreen_vm_reg_valid(u32 reg) reg 3229 drivers/gpu/drm/radeon/evergreen_cs.c if (reg >= 0x28000) reg 3233 drivers/gpu/drm/radeon/evergreen_cs.c switch (reg) { reg 3343 drivers/gpu/drm/radeon/evergreen_cs.c DRM_ERROR("Invalid register 0x%x in CS\n", reg); reg 3353 drivers/gpu/drm/radeon/evergreen_cs.c u32 start_reg, end_reg, reg, i; reg 3409 drivers/gpu/drm/radeon/evergreen_cs.c reg = ib[idx + 5] * 4; reg 3410 drivers/gpu/drm/radeon/evergreen_cs.c if (!evergreen_vm_reg_valid(reg)) reg 3416 drivers/gpu/drm/radeon/evergreen_cs.c reg = ib[idx + 3] * 4; reg 3417 drivers/gpu/drm/radeon/evergreen_cs.c if (!evergreen_vm_reg_valid(reg)) reg 3431 drivers/gpu/drm/radeon/evergreen_cs.c reg = start_reg + (4 * i); reg 3432 drivers/gpu/drm/radeon/evergreen_cs.c if (!evergreen_vm_reg_valid(reg)) reg 3456 drivers/gpu/drm/radeon/evergreen_cs.c reg = start_reg; reg 3457 drivers/gpu/drm/radeon/evergreen_cs.c if (!evergreen_vm_reg_valid(reg)) { reg 3463 drivers/gpu/drm/radeon/evergreen_cs.c reg = start_reg + (4 * i); reg 3464 drivers/gpu/drm/radeon/evergreen_cs.c if (!evergreen_vm_reg_valid(reg)) { reg 3477 drivers/gpu/drm/radeon/evergreen_cs.c reg = start_reg; reg 3478 drivers/gpu/drm/radeon/evergreen_cs.c if (!evergreen_vm_reg_valid(reg)) { reg 3484 drivers/gpu/drm/radeon/evergreen_cs.c reg = start_reg + (4 * i); reg 3485 drivers/gpu/drm/radeon/evergreen_cs.c if (!evergreen_vm_reg_valid(reg)) { reg 1534 drivers/gpu/drm/radeon/evergreend.h #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ reg 1535 drivers/gpu/drm/radeon/evergreend.h (((reg) >> 2) & 0xFFFF) | \ reg 45 drivers/gpu/drm/radeon/ni.c u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) reg 51 drivers/gpu/drm/radeon/ni.c WREG32(TN_SMC_IND_INDEX_0, (reg)); reg 57 drivers/gpu/drm/radeon/ni.c void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) reg 62 drivers/gpu/drm/radeon/ni.c WREG32(TN_SMC_IND_INDEX_0, (reg)); reg 862 drivers/gpu/drm/radeon/ni.c u32 reg, u32 *val) reg 864 drivers/gpu/drm/radeon/ni.c switch (reg) { reg 873 drivers/gpu/drm/radeon/ni.c *val = RREG32(reg); reg 56 drivers/gpu/drm/radeon/ni_dma.c u32 rptr, reg; reg 62 drivers/gpu/drm/radeon/ni_dma.c reg = DMA_RB_RPTR + DMA0_REGISTER_OFFSET; reg 64 drivers/gpu/drm/radeon/ni_dma.c reg = DMA_RB_RPTR + DMA1_REGISTER_OFFSET; reg 66 drivers/gpu/drm/radeon/ni_dma.c rptr = RREG32(reg); reg 83 drivers/gpu/drm/radeon/ni_dma.c u32 reg; reg 86 drivers/gpu/drm/radeon/ni_dma.c reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET; reg 88 drivers/gpu/drm/radeon/ni_dma.c reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET; reg 90 drivers/gpu/drm/radeon/ni_dma.c return (RREG32(reg) & 0x3fffc) >> 2; reg 104 drivers/gpu/drm/radeon/ni_dma.c u32 reg; reg 107 drivers/gpu/drm/radeon/ni_dma.c reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET; reg 109 drivers/gpu/drm/radeon/ni_dma.c reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET; reg 111 drivers/gpu/drm/radeon/ni_dma.c WREG32(reg, (ring->wptr << 2) & 0x3fffc); reg 1689 drivers/gpu/drm/radeon/ni_dpm.c u32 reg; reg 1753 drivers/gpu/drm/radeon/ni_dpm.c reg = CG_R(0xffff) | CG_L(0); reg 1754 drivers/gpu/drm/radeon/ni_dpm.c table->initialState.levels[0].aT = cpu_to_be32(reg); reg 1783 drivers/gpu/drm/radeon/ni_dpm.c reg = MIN_POWER_MASK | MAX_POWER_MASK; reg 1784 drivers/gpu/drm/radeon/ni_dpm.c table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); reg 1786 drivers/gpu/drm/radeon/ni_dpm.c reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; reg 1787 drivers/gpu/drm/radeon/ni_dpm.c table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); reg 1808 drivers/gpu/drm/radeon/ni_dpm.c u32 reg; reg 1931 drivers/gpu/drm/radeon/ni_dpm.c reg = MIN_POWER_MASK | MAX_POWER_MASK; reg 1932 drivers/gpu/drm/radeon/ni_dpm.c table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); reg 1934 drivers/gpu/drm/radeon/ni_dpm.c reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; reg 1935 drivers/gpu/drm/radeon/ni_dpm.c table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); reg 3145 drivers/gpu/drm/radeon/ni_dpm.c u32 reg; reg 3154 drivers/gpu/drm/radeon/ni_dpm.c reg = RREG32(CG_CAC_CTRL) & ~(TID_CNT_MASK | TID_UNIT_MASK); reg 3155 drivers/gpu/drm/radeon/ni_dpm.c reg |= (TID_CNT(ni_pi->cac_weights->tid_cnt) | reg 3157 drivers/gpu/drm/radeon/ni_dpm.c WREG32(CG_CAC_CTRL, reg); reg 3211 drivers/gpu/drm/radeon/ni_dpm.c u32 reg; reg 3220 drivers/gpu/drm/radeon/ni_dpm.c reg = RREG32_CG(CG_CAC_REGION_1_WEIGHT_0) & ~(WEIGHT_TCP_SIG0_MASK | reg 3223 drivers/gpu/drm/radeon/ni_dpm.c reg |= (WEIGHT_TCP_SIG0(ni_pi->cac_weights->weight_tcp_sig0) | reg 3226 drivers/gpu/drm/radeon/ni_dpm.c WREG32_CG(CG_CAC_REGION_1_WEIGHT_0, reg); reg 3228 drivers/gpu/drm/radeon/ni_dpm.c reg = RREG32_CG(CG_CAC_REGION_1_WEIGHT_1) & ~(WEIGHT_TCC_EN0_MASK | reg 3231 drivers/gpu/drm/radeon/ni_dpm.c reg |= (WEIGHT_TCC_EN0(ni_pi->cac_weights->weight_tcc_en0) | reg 3234 drivers/gpu/drm/radeon/ni_dpm.c WREG32_CG(CG_CAC_REGION_1_WEIGHT_1, reg); reg 3236 drivers/gpu/drm/radeon/ni_dpm.c reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_0) & ~(WEIGHT_CB_EN0_MASK | reg 3240 drivers/gpu/drm/radeon/ni_dpm.c reg |= (WEIGHT_CB_EN0(ni_pi->cac_weights->weight_cb_en0) | reg 3244 drivers/gpu/drm/radeon/ni_dpm.c WREG32_CG(CG_CAC_REGION_2_WEIGHT_0, reg); reg 3246 drivers/gpu/drm/radeon/ni_dpm.c reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_1) & ~(WEIGHT_DB_SIG0_MASK | reg 3250 drivers/gpu/drm/radeon/ni_dpm.c reg |= (WEIGHT_DB_SIG0(ni_pi->cac_weights->weight_db_sig0) | reg 3254 drivers/gpu/drm/radeon/ni_dpm.c WREG32_CG(CG_CAC_REGION_2_WEIGHT_1, reg); reg 3256 drivers/gpu/drm/radeon/ni_dpm.c reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_2) & ~(WEIGHT_SXM_SIG0_MASK | reg 3261 drivers/gpu/drm/radeon/ni_dpm.c reg |= (WEIGHT_SXM_SIG0(ni_pi->cac_weights->weight_sxm_sig0) | reg 3266 drivers/gpu/drm/radeon/ni_dpm.c WREG32_CG(CG_CAC_REGION_2_WEIGHT_2, reg); reg 3268 drivers/gpu/drm/radeon/ni_dpm.c reg = RREG32_CG(CG_CAC_REGION_3_WEIGHT_0) & ~(WEIGHT_XBR_0_MASK | reg 3272 drivers/gpu/drm/radeon/ni_dpm.c reg |= (WEIGHT_XBR_0(ni_pi->cac_weights->weight_xbr_0) | reg 3276 drivers/gpu/drm/radeon/ni_dpm.c WREG32_CG(CG_CAC_REGION_3_WEIGHT_0, reg); reg 3278 drivers/gpu/drm/radeon/ni_dpm.c reg = RREG32_CG(CG_CAC_REGION_3_WEIGHT_1) & ~(WEIGHT_SPI_SIG1_MASK | reg 3283 drivers/gpu/drm/radeon/ni_dpm.c reg |= (WEIGHT_SPI_SIG1(ni_pi->cac_weights->weight_spi_sig1) | reg 3288 drivers/gpu/drm/radeon/ni_dpm.c WREG32_CG(CG_CAC_REGION_3_WEIGHT_1, reg); reg 3290 drivers/gpu/drm/radeon/ni_dpm.c reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_0) & ~(WEIGHT_LDS_SIG0_MASK | reg 3293 drivers/gpu/drm/radeon/ni_dpm.c reg |= (WEIGHT_LDS_SIG0(ni_pi->cac_weights->weight_lds_sig0) | reg 3296 drivers/gpu/drm/radeon/ni_dpm.c WREG32_CG(CG_CAC_REGION_4_WEIGHT_0, reg); reg 3298 drivers/gpu/drm/radeon/ni_dpm.c reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_1) & ~(WEIGHT_BIF_MASK | reg 3303 drivers/gpu/drm/radeon/ni_dpm.c reg |= (WEIGHT_BIF(ni_pi->cac_weights->weight_bif) | reg 3308 drivers/gpu/drm/radeon/ni_dpm.c WREG32_CG(CG_CAC_REGION_4_WEIGHT_1, reg); reg 3310 drivers/gpu/drm/radeon/ni_dpm.c reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_2) & ~(WEIGHT_VGT_SIG1_MASK | reg 3315 drivers/gpu/drm/radeon/ni_dpm.c reg |= (WEIGHT_VGT_SIG1(ni_pi->cac_weights->weight_vgt_sig1) | reg 3320 drivers/gpu/drm/radeon/ni_dpm.c WREG32_CG(CG_CAC_REGION_4_WEIGHT_2, reg); reg 3322 drivers/gpu/drm/radeon/ni_dpm.c reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_3) & ~(WEIGHT_DC_SIG3_MASK | reg 3327 drivers/gpu/drm/radeon/ni_dpm.c reg |= (WEIGHT_DC_SIG3(ni_pi->cac_weights->weight_dc_sig3) | reg 3332 drivers/gpu/drm/radeon/ni_dpm.c WREG32_CG(CG_CAC_REGION_4_WEIGHT_3, reg); reg 3334 drivers/gpu/drm/radeon/ni_dpm.c reg = RREG32_CG(CG_CAC_REGION_5_WEIGHT_0) & ~(WEIGHT_SQ_VSP_MASK | reg 3336 drivers/gpu/drm/radeon/ni_dpm.c reg |= (WEIGHT_SQ_VSP(ni_pi->cac_weights->weight_sq_vsp) | reg 3338 drivers/gpu/drm/radeon/ni_dpm.c WREG32_CG(CG_CAC_REGION_5_WEIGHT_0, reg); reg 3340 drivers/gpu/drm/radeon/ni_dpm.c reg = RREG32_CG(CG_CAC_REGION_5_WEIGHT_1) & ~(WEIGHT_SQ_GPR_MASK); reg 3341 drivers/gpu/drm/radeon/ni_dpm.c reg |= WEIGHT_SQ_GPR(ni_pi->cac_weights->weight_sq_gpr); reg 3342 drivers/gpu/drm/radeon/ni_dpm.c WREG32_CG(CG_CAC_REGION_5_WEIGHT_1, reg); reg 3344 drivers/gpu/drm/radeon/ni_dpm.c reg = RREG32_CG(CG_CAC_REGION_4_OVERRIDE_4) & ~(OVR_MODE_SPARE_0_MASK | reg 3348 drivers/gpu/drm/radeon/ni_dpm.c reg |= (OVR_MODE_SPARE_0(ni_pi->cac_weights->ovr_mode_spare_0) | reg 3352 drivers/gpu/drm/radeon/ni_dpm.c WREG32_CG(CG_CAC_REGION_4_OVERRIDE_4, reg); reg 3354 drivers/gpu/drm/radeon/ni_dpm.c reg = RREG32(SQ_CAC_THRESHOLD) & ~(VSP_MASK | reg 3357 drivers/gpu/drm/radeon/ni_dpm.c reg |= (VSP(ni_pi->cac_weights->vsp) | reg 3360 drivers/gpu/drm/radeon/ni_dpm.c WREG32(SQ_CAC_THRESHOLD, reg); reg 3362 drivers/gpu/drm/radeon/ni_dpm.c reg = (MCDW_WR_ENABLE | reg 3367 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_CG_CONFIG, reg); reg 3369 drivers/gpu/drm/radeon/ni_dpm.c reg = (READ_WEIGHT(ni_pi->cac_weights->mc_read_weight) | reg 3372 drivers/gpu/drm/radeon/ni_dpm.c WREG32(MC_CG_DATAPORT, reg); reg 1148 drivers/gpu/drm/radeon/nid.h #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ reg 1149 drivers/gpu/drm/radeon/nid.h (((reg) >> 2) & 0xFFFF) | \ reg 360 drivers/gpu/drm/radeon/r100.c tmp = RREG32(voltage->gpio.reg); reg 365 drivers/gpu/drm/radeon/r100.c WREG32(voltage->gpio.reg, tmp); reg 369 drivers/gpu/drm/radeon/r100.c tmp = RREG32(voltage->gpio.reg); reg 374 drivers/gpu/drm/radeon/r100.c WREG32(voltage->gpio.reg, tmp); reg 1262 drivers/gpu/drm/radeon/r100.c unsigned reg) reg 1273 drivers/gpu/drm/radeon/r100.c idx, reg); reg 1286 drivers/gpu/drm/radeon/r100.c if (reg == RADEON_SRC_PITCH_OFFSET) { reg 1370 drivers/gpu/drm/radeon/r100.c unsigned reg; reg 1376 drivers/gpu/drm/radeon/r100.c reg = pkt->reg; reg 1382 drivers/gpu/drm/radeon/r100.c if ((reg >> 7) > n) { reg 1386 drivers/gpu/drm/radeon/r100.c if (((reg + (pkt->count << 2)) >> 7) > n) { reg 1391 drivers/gpu/drm/radeon/r100.c j = (reg >> 7); reg 1392 drivers/gpu/drm/radeon/r100.c m = 1 << ((reg >> 2) & 31); reg 1394 drivers/gpu/drm/radeon/r100.c r = check(p, pkt, idx, reg); reg 1404 drivers/gpu/drm/radeon/r100.c reg += 4; reg 1431 drivers/gpu/drm/radeon/r100.c uint32_t header, h_idx, reg; reg 1442 drivers/gpu/drm/radeon/r100.c if (waitreloc.reg != RADEON_WAIT_UNTIL || reg 1464 drivers/gpu/drm/radeon/r100.c reg = R100_CP_PACKET0_GET_REG(header); reg 1478 drivers/gpu/drm/radeon/r100.c switch (reg) { reg 1553 drivers/gpu/drm/radeon/r100.c unsigned idx, unsigned reg) reg 1569 drivers/gpu/drm/radeon/r100.c switch (reg) { reg 1574 drivers/gpu/drm/radeon/r100.c idx, reg); reg 1583 drivers/gpu/drm/radeon/r100.c r = r100_reloc_pitch_offset(p, pkt, idx, reg); reg 1591 drivers/gpu/drm/radeon/r100.c idx, reg); reg 1604 drivers/gpu/drm/radeon/r100.c idx, reg); reg 1616 drivers/gpu/drm/radeon/r100.c i = (reg - RADEON_PP_TXOFFSET_0) / 24; reg 1620 drivers/gpu/drm/radeon/r100.c idx, reg); reg 1643 drivers/gpu/drm/radeon/r100.c i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; reg 1647 drivers/gpu/drm/radeon/r100.c idx, reg); reg 1661 drivers/gpu/drm/radeon/r100.c i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; reg 1665 drivers/gpu/drm/radeon/r100.c idx, reg); reg 1679 drivers/gpu/drm/radeon/r100.c i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; reg 1683 drivers/gpu/drm/radeon/r100.c idx, reg); reg 1701 drivers/gpu/drm/radeon/r100.c idx, reg); reg 1772 drivers/gpu/drm/radeon/r100.c idx, reg); reg 1795 drivers/gpu/drm/radeon/r100.c i = (reg - RADEON_PP_TEX_SIZE_0) / 8; reg 1803 drivers/gpu/drm/radeon/r100.c i = (reg - RADEON_PP_TEX_PITCH_0) / 8; reg 1810 drivers/gpu/drm/radeon/r100.c i = (reg - RADEON_PP_TXFILTER_0) / 24; reg 1824 drivers/gpu/drm/radeon/r100.c i = (reg - RADEON_PP_TXFORMAT_0) / 24; reg 1878 drivers/gpu/drm/radeon/r100.c i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; reg 1886 drivers/gpu/drm/radeon/r100.c pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx); reg 2880 drivers/gpu/drm/radeon/r100.c uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) reg 2886 drivers/gpu/drm/radeon/r100.c WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); reg 2894 drivers/gpu/drm/radeon/r100.c void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) reg 2899 drivers/gpu/drm/radeon/r100.c WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); reg 2928 drivers/gpu/drm/radeon/r100.c uint32_t reg, value; reg 2936 drivers/gpu/drm/radeon/r100.c reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; reg 2939 drivers/gpu/drm/radeon/r100.c seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); reg 3093 drivers/gpu/drm/radeon/r100.c int r100_set_surface_reg(struct radeon_device *rdev, int reg, reg 3097 drivers/gpu/drm/radeon/r100.c int surf_index = reg * 16; reg 3134 drivers/gpu/drm/radeon/r100.c DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); reg 3141 drivers/gpu/drm/radeon/r100.c void r100_clear_surface_reg(struct radeon_device *rdev, int reg) reg 3143 drivers/gpu/drm/radeon/r100.c int surf_index = reg * 16; reg 4114 drivers/gpu/drm/radeon/r100.c uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg) reg 4120 drivers/gpu/drm/radeon/r100.c writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); reg 4126 drivers/gpu/drm/radeon/r100.c void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v) reg 4131 drivers/gpu/drm/radeon/r100.c writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); reg 4136 drivers/gpu/drm/radeon/r100.c u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) reg 4138 drivers/gpu/drm/radeon/r100.c if (reg < rdev->rio_mem_size) reg 4139 drivers/gpu/drm/radeon/r100.c return ioread32(rdev->rio_mem + reg); reg 4141 drivers/gpu/drm/radeon/r100.c iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); reg 4146 drivers/gpu/drm/radeon/r100.c void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) reg 4148 drivers/gpu/drm/radeon/r100.c if (reg < rdev->rio_mem_size) reg 4149 drivers/gpu/drm/radeon/r100.c iowrite32(v, rdev->rio_mem + reg); reg 4151 drivers/gpu/drm/radeon/r100.c iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); reg 92 drivers/gpu/drm/radeon/r100_track.h unsigned idx, unsigned reg); reg 97 drivers/gpu/drm/radeon/r100_track.h unsigned reg); reg 59 drivers/gpu/drm/radeon/r100d.h #define PACKET0(reg, n) (CP_PACKET0 | \ reg 60 drivers/gpu/drm/radeon/r100d.h REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ reg 147 drivers/gpu/drm/radeon/r200.c unsigned idx, unsigned reg) reg 162 drivers/gpu/drm/radeon/r200.c switch (reg) { reg 167 drivers/gpu/drm/radeon/r200.c idx, reg); reg 176 drivers/gpu/drm/radeon/r200.c r = r100_reloc_pitch_offset(p, pkt, idx, reg); reg 184 drivers/gpu/drm/radeon/r200.c idx, reg); reg 197 drivers/gpu/drm/radeon/r200.c idx, reg); reg 212 drivers/gpu/drm/radeon/r200.c i = (reg - R200_PP_TXOFFSET_0) / 24; reg 216 drivers/gpu/drm/radeon/r200.c idx, reg); reg 264 drivers/gpu/drm/radeon/r200.c i = (reg - R200_PP_TXOFFSET_0) / 24; reg 265 drivers/gpu/drm/radeon/r200.c face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4; reg 269 drivers/gpu/drm/radeon/r200.c idx, reg); reg 287 drivers/gpu/drm/radeon/r200.c idx, reg); reg 364 drivers/gpu/drm/radeon/r200.c idx, reg); reg 397 drivers/gpu/drm/radeon/r200.c i = (reg - R200_PP_TXSIZE_0) / 32; reg 408 drivers/gpu/drm/radeon/r200.c i = (reg - R200_PP_TXPITCH_0) / 32; reg 418 drivers/gpu/drm/radeon/r200.c i = (reg - R200_PP_TXFILTER_0) / 32; reg 435 drivers/gpu/drm/radeon/r200.c i = (reg - R200_PP_TXMULTI_CTL_0) / 32; reg 443 drivers/gpu/drm/radeon/r200.c i = (reg - R200_PP_TXFORMAT_X_0) / 32; reg 474 drivers/gpu/drm/radeon/r200.c i = (reg - R200_PP_TXFORMAT_0) / 32; reg 532 drivers/gpu/drm/radeon/r200.c i = (reg - R200_PP_CUBIC_FACES_0) / 32; reg 540 drivers/gpu/drm/radeon/r200.c pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx); reg 61 drivers/gpu/drm/radeon/r300.c uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) reg 67 drivers/gpu/drm/radeon/r300.c WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); reg 73 drivers/gpu/drm/radeon/r300.c void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) reg 78 drivers/gpu/drm/radeon/r300.c WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); reg 633 drivers/gpu/drm/radeon/r300.c unsigned idx, unsigned reg) reg 647 drivers/gpu/drm/radeon/r300.c switch(reg) { reg 653 drivers/gpu/drm/radeon/r300.c idx, reg); reg 660 drivers/gpu/drm/radeon/r300.c r = r100_reloc_pitch_offset(p, pkt, idx, reg); reg 668 drivers/gpu/drm/radeon/r300.c i = (reg - R300_RB3D_COLOROFFSET0) >> 2; reg 672 drivers/gpu/drm/radeon/r300.c idx, reg); reg 685 drivers/gpu/drm/radeon/r300.c idx, reg); reg 710 drivers/gpu/drm/radeon/r300.c i = (reg - R300_TX_OFFSET_0) >> 2; reg 714 drivers/gpu/drm/radeon/r300.c idx, reg); reg 787 drivers/gpu/drm/radeon/r300.c idx, reg); reg 803 drivers/gpu/drm/radeon/r300.c i = (reg - 0x4E38) >> 2; reg 872 drivers/gpu/drm/radeon/r300.c idx, reg); reg 918 drivers/gpu/drm/radeon/r300.c i = (reg - 0x44C0) >> 2; reg 1004 drivers/gpu/drm/radeon/r300.c i = (reg - 0x4400) >> 2; reg 1032 drivers/gpu/drm/radeon/r300.c i = (reg - 0x4500) >> 2; reg 1070 drivers/gpu/drm/radeon/r300.c i = (reg - 0x4480) >> 2; reg 1087 drivers/gpu/drm/radeon/r300.c idx, reg); reg 1129 drivers/gpu/drm/radeon/r300.c idx, reg); reg 1172 drivers/gpu/drm/radeon/r300.c reg, idx, idx_value); reg 60 drivers/gpu/drm/radeon/r300d.h #define PACKET0(reg, n) (CP_PACKET0 | \ reg 61 drivers/gpu/drm/radeon/r300d.h REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ reg 165 drivers/gpu/drm/radeon/r420.c u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) reg 171 drivers/gpu/drm/radeon/r420.c WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); reg 177 drivers/gpu/drm/radeon/r420.c void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) reg 182 drivers/gpu/drm/radeon/r420.c WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | reg 120 drivers/gpu/drm/radeon/r600.c u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) reg 126 drivers/gpu/drm/radeon/r600.c WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); reg 132 drivers/gpu/drm/radeon/r600.c void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) reg 137 drivers/gpu/drm/radeon/r600.c WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); reg 142 drivers/gpu/drm/radeon/r600.c u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) reg 148 drivers/gpu/drm/radeon/r600.c WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); reg 154 drivers/gpu/drm/radeon/r600.c void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) reg 159 drivers/gpu/drm/radeon/r600.c WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); reg 175 drivers/gpu/drm/radeon/r600.c u32 reg, u32 *val) reg 177 drivers/gpu/drm/radeon/r600.c switch (reg) { reg 183 drivers/gpu/drm/radeon/r600.c *val = RREG32(reg); reg 1278 drivers/gpu/drm/radeon/r600.c uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) reg 1284 drivers/gpu/drm/radeon/r600.c WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); reg 1291 drivers/gpu/drm/radeon/r600.c void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) reg 1296 drivers/gpu/drm/radeon/r600.c WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | reg 2396 drivers/gpu/drm/radeon/r600.c u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) reg 2402 drivers/gpu/drm/radeon/r600.c WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); reg 2409 drivers/gpu/drm/radeon/r600.c void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) reg 2414 drivers/gpu/drm/radeon/r600.c WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); reg 2818 drivers/gpu/drm/radeon/r600.c rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); reg 3027 drivers/gpu/drm/radeon/r600.c int r600_set_surface_reg(struct radeon_device *rdev, int reg, reg 3035 drivers/gpu/drm/radeon/r600.c void r600_clear_surface_reg(struct radeon_device *rdev, int reg) reg 834 drivers/gpu/drm/radeon/r600_cs.c uint32_t header, h_idx, reg, wait_reg_mem_info; reg 888 drivers/gpu/drm/radeon/r600_cs.c reg = R600_CP_PACKET0_GET_REG(header); reg 907 drivers/gpu/drm/radeon/r600_cs.c } else if (reg == vline_start_end[0]) { reg 921 drivers/gpu/drm/radeon/r600_cs.c unsigned idx, unsigned reg) reg 925 drivers/gpu/drm/radeon/r600_cs.c switch (reg) { reg 930 drivers/gpu/drm/radeon/r600_cs.c idx, reg); reg 935 drivers/gpu/drm/radeon/r600_cs.c pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx); reg 944 drivers/gpu/drm/radeon/r600_cs.c unsigned reg, i; reg 949 drivers/gpu/drm/radeon/r600_cs.c reg = pkt->reg; reg 950 drivers/gpu/drm/radeon/r600_cs.c for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { reg 951 drivers/gpu/drm/radeon/r600_cs.c r = r600_packet0_check(p, pkt, idx, reg); reg 969 drivers/gpu/drm/radeon/r600_cs.c static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) reg 976 drivers/gpu/drm/radeon/r600_cs.c i = (reg >> 7); reg 978 drivers/gpu/drm/radeon/r600_cs.c dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); reg 981 drivers/gpu/drm/radeon/r600_cs.c m = 1 << ((reg >> 2) & 31); reg 985 drivers/gpu/drm/radeon/r600_cs.c switch (reg) { reg 1020 drivers/gpu/drm/radeon/r600_cs.c "0x%04X\n", reg); reg 1038 drivers/gpu/drm/radeon/r600_cs.c "0x%04X\n", reg); reg 1080 drivers/gpu/drm/radeon/r600_cs.c "0x%04X\n", reg); reg 1083 drivers/gpu/drm/radeon/r600_cs.c tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; reg 1094 drivers/gpu/drm/radeon/r600_cs.c tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16; reg 1103 drivers/gpu/drm/radeon/r600_cs.c "0x%04X\n", reg); reg 1138 drivers/gpu/drm/radeon/r600_cs.c dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); reg 1141 drivers/gpu/drm/radeon/r600_cs.c tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; reg 1151 drivers/gpu/drm/radeon/r600_cs.c tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; reg 1164 drivers/gpu/drm/radeon/r600_cs.c tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4; reg 1176 drivers/gpu/drm/radeon/r600_cs.c tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4; reg 1198 drivers/gpu/drm/radeon/r600_cs.c tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4; reg 1201 drivers/gpu/drm/radeon/r600_cs.c dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); reg 1210 drivers/gpu/drm/radeon/r600_cs.c dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); reg 1229 drivers/gpu/drm/radeon/r600_cs.c tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4; reg 1232 drivers/gpu/drm/radeon/r600_cs.c dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); reg 1241 drivers/gpu/drm/radeon/r600_cs.c dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); reg 1260 drivers/gpu/drm/radeon/r600_cs.c tmp = (reg - R_028100_CB_COLOR0_MASK) / 4; reg 1277 drivers/gpu/drm/radeon/r600_cs.c "0x%04X\n", reg); reg 1280 drivers/gpu/drm/radeon/r600_cs.c tmp = (reg - CB_COLOR0_BASE) / 4; reg 1292 drivers/gpu/drm/radeon/r600_cs.c "0x%04X\n", reg); reg 1305 drivers/gpu/drm/radeon/r600_cs.c "0x%04X\n", reg); reg 1375 drivers/gpu/drm/radeon/r600_cs.c "0x%04X\n", reg); reg 1384 drivers/gpu/drm/radeon/r600_cs.c "0x%04X\n", reg); reg 1393 drivers/gpu/drm/radeon/r600_cs.c dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); reg 1610 drivers/gpu/drm/radeon/r600_cs.c static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) reg 1614 drivers/gpu/drm/radeon/r600_cs.c i = (reg >> 7); reg 1616 drivers/gpu/drm/radeon/r600_cs.c dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); reg 1619 drivers/gpu/drm/radeon/r600_cs.c m = 1 << ((reg >> 2) & 31); reg 1622 drivers/gpu/drm/radeon/r600_cs.c dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); reg 1634 drivers/gpu/drm/radeon/r600_cs.c unsigned start_reg, end_reg, reg; reg 1918 drivers/gpu/drm/radeon/r600_cs.c reg = start_reg + (4 * i); reg 1919 drivers/gpu/drm/radeon/r600_cs.c r = r600_cs_check_reg(p, reg, idx+1+i); reg 1934 drivers/gpu/drm/radeon/r600_cs.c reg = start_reg + (4 * i); reg 1935 drivers/gpu/drm/radeon/r600_cs.c r = r600_cs_check_reg(p, reg, idx+1+i); reg 2230 drivers/gpu/drm/radeon/r600_cs.c reg = radeon_get_ib_value(p, idx+1) << 2; reg 2231 drivers/gpu/drm/radeon/r600_cs.c if (!r600_is_safe_reg(p, reg, idx+1)) reg 2254 drivers/gpu/drm/radeon/r600_cs.c reg = radeon_get_ib_value(p, idx+3) << 2; reg 2255 drivers/gpu/drm/radeon/r600_cs.c if (!r600_is_safe_reg(p, reg, idx+3)) reg 1584 drivers/gpu/drm/radeon/r600d.h #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ reg 1585 drivers/gpu/drm/radeon/r600d.h (((reg) >> 2) & 0xFFFF) | \ reg 708 drivers/gpu/drm/radeon/radeon.h uint32_t reg[32]; reg 711 drivers/gpu/drm/radeon/radeon.h int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); reg 712 drivers/gpu/drm/radeon/radeon.h void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); reg 1102 drivers/gpu/drm/radeon/radeon.h unsigned reg; reg 1110 drivers/gpu/drm/radeon/radeon.h unsigned idx, unsigned reg); reg 1859 drivers/gpu/drm/radeon/radeon.h int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); reg 1934 drivers/gpu/drm/radeon/radeon.h int (*set_reg)(struct radeon_device *rdev, int reg, reg 1937 drivers/gpu/drm/radeon/radeon.h void (*clear_reg)(struct radeon_device *rdev, int reg); reg 2464 drivers/gpu/drm/radeon/radeon.h uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); reg 2465 drivers/gpu/drm/radeon/radeon.h void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); reg 2466 drivers/gpu/drm/radeon/radeon.h static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, reg 2470 drivers/gpu/drm/radeon/radeon.h if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) reg 2471 drivers/gpu/drm/radeon/radeon.h return readl(((void __iomem *)rdev->rmmio) + reg); reg 2473 drivers/gpu/drm/radeon/radeon.h return r100_mm_rreg_slow(rdev, reg); reg 2475 drivers/gpu/drm/radeon/radeon.h static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, reg 2478 drivers/gpu/drm/radeon/radeon.h if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) reg 2479 drivers/gpu/drm/radeon/radeon.h writel(v, ((void __iomem *)rdev->rmmio) + reg); reg 2481 drivers/gpu/drm/radeon/radeon.h r100_mm_wreg_slow(rdev, reg, v); reg 2484 drivers/gpu/drm/radeon/radeon.h u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); reg 2485 drivers/gpu/drm/radeon/radeon.h void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); reg 2508 drivers/gpu/drm/radeon/radeon.h #define RREG8(reg) readb((rdev->rmmio) + (reg)) reg 2509 drivers/gpu/drm/radeon/radeon.h #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) reg 2510 drivers/gpu/drm/radeon/radeon.h #define RREG16(reg) readw((rdev->rmmio) + (reg)) reg 2511 drivers/gpu/drm/radeon/radeon.h #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) reg 2512 drivers/gpu/drm/radeon/radeon.h #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) reg 2513 drivers/gpu/drm/radeon/radeon.h #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) reg 2514 drivers/gpu/drm/radeon/radeon.h #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \ reg 2515 drivers/gpu/drm/radeon/radeon.h r100_mm_rreg(rdev, (reg), false)) reg 2516 drivers/gpu/drm/radeon/radeon.h #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) reg 2517 drivers/gpu/drm/radeon/radeon.h #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) reg 2520 drivers/gpu/drm/radeon/radeon.h #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) reg 2521 drivers/gpu/drm/radeon/radeon.h #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) reg 2522 drivers/gpu/drm/radeon/radeon.h #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) reg 2523 drivers/gpu/drm/radeon/radeon.h #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) reg 2524 drivers/gpu/drm/radeon/radeon.h #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) reg 2525 drivers/gpu/drm/radeon/radeon.h #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) reg 2526 drivers/gpu/drm/radeon/radeon.h #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) reg 2527 drivers/gpu/drm/radeon/radeon.h #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) reg 2528 drivers/gpu/drm/radeon/radeon.h #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) reg 2529 drivers/gpu/drm/radeon/radeon.h #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) reg 2530 drivers/gpu/drm/radeon/radeon.h #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) reg 2531 drivers/gpu/drm/radeon/radeon.h #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) reg 2532 drivers/gpu/drm/radeon/radeon.h #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) reg 2533 drivers/gpu/drm/radeon/radeon.h #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) reg 2534 drivers/gpu/drm/radeon/radeon.h #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) reg 2535 drivers/gpu/drm/radeon/radeon.h #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) reg 2536 drivers/gpu/drm/radeon/radeon.h #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) reg 2537 drivers/gpu/drm/radeon/radeon.h #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) reg 2538 drivers/gpu/drm/radeon/radeon.h #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) reg 2539 drivers/gpu/drm/radeon/radeon.h #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) reg 2540 drivers/gpu/drm/radeon/radeon.h #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) reg 2541 drivers/gpu/drm/radeon/radeon.h #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) reg 2542 drivers/gpu/drm/radeon/radeon.h #define WREG32_P(reg, val, mask) \ reg 2544 drivers/gpu/drm/radeon/radeon.h uint32_t tmp_ = RREG32(reg); \ reg 2547 drivers/gpu/drm/radeon/radeon.h WREG32(reg, tmp_); \ reg 2549 drivers/gpu/drm/radeon/radeon.h #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) reg 2550 drivers/gpu/drm/radeon/radeon.h #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) reg 2551 drivers/gpu/drm/radeon/radeon.h #define WREG32_PLL_P(reg, val, mask) \ reg 2553 drivers/gpu/drm/radeon/radeon.h uint32_t tmp_ = RREG32_PLL(reg); \ reg 2556 drivers/gpu/drm/radeon/radeon.h WREG32_PLL(reg, tmp_); \ reg 2558 drivers/gpu/drm/radeon/radeon.h #define WREG32_SMC_P(reg, val, mask) \ reg 2560 drivers/gpu/drm/radeon/radeon.h uint32_t tmp_ = RREG32_SMC(reg); \ reg 2563 drivers/gpu/drm/radeon/radeon.h WREG32_SMC(reg, tmp_); \ reg 2565 drivers/gpu/drm/radeon/radeon.h #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) reg 2566 drivers/gpu/drm/radeon/radeon.h #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) reg 2567 drivers/gpu/drm/radeon/radeon.h #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) reg 2580 drivers/gpu/drm/radeon/radeon.h uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); reg 2581 drivers/gpu/drm/radeon/radeon.h void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); reg 2582 drivers/gpu/drm/radeon/radeon.h u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); reg 2583 drivers/gpu/drm/radeon/radeon.h void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); reg 2584 drivers/gpu/drm/radeon/radeon.h u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); reg 2585 drivers/gpu/drm/radeon/radeon.h void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); reg 2586 drivers/gpu/drm/radeon/radeon.h u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); reg 2587 drivers/gpu/drm/radeon/radeon.h void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); reg 2588 drivers/gpu/drm/radeon/radeon.h u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); reg 2589 drivers/gpu/drm/radeon/radeon.h void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); reg 2590 drivers/gpu/drm/radeon/radeon.h u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); reg 2591 drivers/gpu/drm/radeon/radeon.h void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); reg 2592 drivers/gpu/drm/radeon/radeon.h u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); reg 2593 drivers/gpu/drm/radeon/radeon.h void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); reg 2594 drivers/gpu/drm/radeon/radeon.h u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); reg 2595 drivers/gpu/drm/radeon/radeon.h void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); reg 2956 drivers/gpu/drm/radeon/radeon.h u32 reg, u32 mask, reg 54 drivers/gpu/drm/radeon/radeon_asic.c static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) reg 56 drivers/gpu/drm/radeon/radeon_asic.c DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); reg 71 drivers/gpu/drm/radeon/radeon_asic.c static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) reg 74 drivers/gpu/drm/radeon/radeon_asic.c reg, v); reg 141 drivers/gpu/drm/radeon/radeon_asic.c u32 reg, u32 *val) reg 83 drivers/gpu/drm/radeon/radeon_asic.h void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); reg 84 drivers/gpu/drm/radeon/radeon_asic.h uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); reg 90 drivers/gpu/drm/radeon/radeon_asic.h int r100_set_surface_reg(struct radeon_device *rdev, int reg, reg 93 drivers/gpu/drm/radeon/radeon_asic.h void r100_clear_surface_reg(struct radeon_device *rdev, int reg); reg 200 drivers/gpu/drm/radeon/radeon_asic.h extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); reg 201 drivers/gpu/drm/radeon/radeon_asic.h extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); reg 216 drivers/gpu/drm/radeon/radeon_asic.h uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); reg 217 drivers/gpu/drm/radeon/radeon_asic.h void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); reg 241 drivers/gpu/drm/radeon/radeon_asic.h uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); reg 242 drivers/gpu/drm/radeon/radeon_asic.h void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); reg 266 drivers/gpu/drm/radeon/radeon_asic.h uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); reg 267 drivers/gpu/drm/radeon/radeon_asic.h void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); reg 285 drivers/gpu/drm/radeon/radeon_asic.h uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); reg 286 drivers/gpu/drm/radeon/radeon_asic.h void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); reg 318 drivers/gpu/drm/radeon/radeon_asic.h uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); reg 319 drivers/gpu/drm/radeon/radeon_asic.h void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); reg 338 drivers/gpu/drm/radeon/radeon_asic.h int r600_set_surface_reg(struct radeon_device *rdev, int reg, reg 341 drivers/gpu/drm/radeon/radeon_asic.h void r600_clear_surface_reg(struct radeon_device *rdev, int reg); reg 365 drivers/gpu/drm/radeon/radeon_asic.h extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg); reg 366 drivers/gpu/drm/radeon/radeon_asic.h extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); reg 388 drivers/gpu/drm/radeon/radeon_asic.h u32 reg, u32 *val); reg 553 drivers/gpu/drm/radeon/radeon_asic.h u32 reg, u32 *val); reg 656 drivers/gpu/drm/radeon/radeon_asic.h u32 reg, u32 *val); reg 753 drivers/gpu/drm/radeon/radeon_asic.h u32 reg, u32 *val); reg 785 drivers/gpu/drm/radeon/radeon_asic.h uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg); reg 786 drivers/gpu/drm/radeon/radeon_asic.h void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); reg 872 drivers/gpu/drm/radeon/radeon_asic.h u32 reg, u32 *val); reg 227 drivers/gpu/drm/radeon/radeon_atombios.c gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4; reg 245 drivers/gpu/drm/radeon/radeon_atombios.c u32 reg; reg 250 drivers/gpu/drm/radeon/radeon_atombios.c reg = SI_DC_GPIO_HPD_A; reg 252 drivers/gpu/drm/radeon/radeon_atombios.c reg = EVERGREEN_DC_GPIO_HPD_A; reg 254 drivers/gpu/drm/radeon/radeon_atombios.c reg = AVIVO_DC_GPIO_HPD_A; reg 257 drivers/gpu/drm/radeon/radeon_atombios.c if (gpio->reg == reg) { reg 38 drivers/gpu/drm/radeon/radeon_audio.c u32 dce6_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg); reg 40 drivers/gpu/drm/radeon/radeon_audio.c u32 offset, u32 reg, u32 v); reg 117 drivers/gpu/drm/radeon/radeon_audio.c static u32 radeon_audio_rreg(struct radeon_device *rdev, u32 offset, u32 reg) reg 119 drivers/gpu/drm/radeon/radeon_audio.c return RREG32(reg); reg 123 drivers/gpu/drm/radeon/radeon_audio.c u32 reg, u32 v) reg 125 drivers/gpu/drm/radeon/radeon_audio.c WREG32(reg, v); reg 344 drivers/gpu/drm/radeon/radeon_audio.c u32 radeon_audio_endpoint_rreg(struct radeon_device *rdev, u32 offset, u32 reg) reg 347 drivers/gpu/drm/radeon/radeon_audio.c return rdev->audio.funcs->endpoint_rreg(rdev, offset, reg); reg 353 drivers/gpu/drm/radeon/radeon_audio.c u32 reg, u32 v) reg 356 drivers/gpu/drm/radeon/radeon_audio.c rdev->audio.funcs->endpoint_wreg(rdev, offset, reg, v); reg 30 drivers/gpu/drm/radeon/radeon_audio.h #define RREG32_ENDPOINT(block, reg) \ reg 31 drivers/gpu/drm/radeon/radeon_audio.h radeon_audio_endpoint_rreg(rdev, (block), (reg)) reg 32 drivers/gpu/drm/radeon/radeon_audio.h #define WREG32_ENDPOINT(block, reg, v) \ reg 33 drivers/gpu/drm/radeon/radeon_audio.h radeon_audio_endpoint_wreg(rdev, (block), (reg), (v)) reg 37 drivers/gpu/drm/radeon/radeon_audio.h u32 (*endpoint_rreg)(struct radeon_device *rdev, u32 offset, u32 reg); reg 39 drivers/gpu/drm/radeon/radeon_audio.h u32 offset, u32 reg, u32 v); reg 74 drivers/gpu/drm/radeon/radeon_audio.h u32 offset, u32 reg); reg 76 drivers/gpu/drm/radeon/radeon_audio.h u32 offset, u32 reg, u32 v); reg 2759 drivers/gpu/drm/radeon/radeon_combios.c rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = reg 2767 drivers/gpu/drm/radeon/radeon_combios.c rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = reg 2892 drivers/gpu/drm/radeon/radeon_combios.c uint32_t reg, val, and_mask, or_mask; reg 2911 drivers/gpu/drm/radeon/radeon_combios.c reg = (id & 0x1fff) * 4; reg 2914 drivers/gpu/drm/radeon/radeon_combios.c WREG32(reg, val); reg 2917 drivers/gpu/drm/radeon/radeon_combios.c reg = (id & 0x1fff) * 4; reg 2922 drivers/gpu/drm/radeon/radeon_combios.c val = RREG32(reg); reg 2924 drivers/gpu/drm/radeon/radeon_combios.c WREG32(reg, val); reg 2940 drivers/gpu/drm/radeon/radeon_combios.c reg = RBIOS8(index); reg 2946 drivers/gpu/drm/radeon/radeon_combios.c reg, val); reg 2966 drivers/gpu/drm/radeon/radeon_combios.c reg = (id & 0x1fff) * 4; reg 2968 drivers/gpu/drm/radeon/radeon_combios.c WREG32(reg, val); reg 2971 drivers/gpu/drm/radeon/radeon_combios.c reg = (id & 0x1fff) * 4; reg 2976 drivers/gpu/drm/radeon/radeon_combios.c val = RREG32(reg); reg 2978 drivers/gpu/drm/radeon/radeon_combios.c WREG32(reg, val); reg 2986 drivers/gpu/drm/radeon/radeon_combios.c reg = id & 0x1fff; reg 2991 drivers/gpu/drm/radeon/radeon_combios.c val = RREG32_PLL(reg); reg 2993 drivers/gpu/drm/radeon/radeon_combios.c WREG32_PLL(reg, val); reg 2996 drivers/gpu/drm/radeon/radeon_combios.c reg = id & 0x1fff; reg 3001 drivers/gpu/drm/radeon/radeon_combios.c reg, val); reg 754 drivers/gpu/drm/radeon/radeon_cs.c pkt->reg = R100_CP_PACKET0_GET_REG(header); reg 758 drivers/gpu/drm/radeon/radeon_cs.c pkt->reg = R600_CP_PACKET0_GET_REG(header); reg 75 drivers/gpu/drm/radeon/radeon_cursor.c u32 reg; reg 78 drivers/gpu/drm/radeon/radeon_cursor.c reg = RADEON_CRTC_GEN_CNTL; reg 81 drivers/gpu/drm/radeon/radeon_cursor.c reg = RADEON_CRTC2_GEN_CNTL; reg 86 drivers/gpu/drm/radeon/radeon_cursor.c WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN); reg 205 drivers/gpu/drm/radeon/radeon_device.c u32 tmp, reg, and_mask, or_mask; reg 212 drivers/gpu/drm/radeon/radeon_device.c reg = registers[i + 0]; reg 219 drivers/gpu/drm/radeon/radeon_device.c tmp = RREG32(reg); reg 223 drivers/gpu/drm/radeon/radeon_device.c WREG32(reg, tmp); reg 279 drivers/gpu/drm/radeon/radeon_device.c rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); reg 292 drivers/gpu/drm/radeon/radeon_device.c int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) reg 299 drivers/gpu/drm/radeon/radeon_device.c *reg = rdev->scratch.reg[i]; reg 314 drivers/gpu/drm/radeon/radeon_device.c void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) reg 319 drivers/gpu/drm/radeon/radeon_device.c if (rdev->scratch.reg[i] == reg) { reg 657 drivers/gpu/drm/radeon/radeon_device.c uint32_t reg; reg 675 drivers/gpu/drm/radeon/radeon_device.c reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | reg 678 drivers/gpu/drm/radeon/radeon_device.c reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | reg 682 drivers/gpu/drm/radeon/radeon_device.c reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | reg 685 drivers/gpu/drm/radeon/radeon_device.c if (reg & EVERGREEN_CRTC_MASTER_EN) reg 688 drivers/gpu/drm/radeon/radeon_device.c reg = RREG32(AVIVO_D1CRTC_CONTROL) | reg 690 drivers/gpu/drm/radeon/radeon_device.c if (reg & AVIVO_CRTC_EN) { reg 694 drivers/gpu/drm/radeon/radeon_device.c reg = RREG32(RADEON_CRTC_GEN_CNTL) | reg 696 drivers/gpu/drm/radeon/radeon_device.c if (reg & RADEON_CRTC_EN) { reg 704 drivers/gpu/drm/radeon/radeon_device.c reg = RREG32(R600_CONFIG_MEMSIZE); reg 706 drivers/gpu/drm/radeon/radeon_device.c reg = RREG32(RADEON_CONFIG_MEMSIZE); reg 708 drivers/gpu/drm/radeon/radeon_device.c if (reg) reg 836 drivers/gpu/drm/radeon/radeon_device.c static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) reg 841 drivers/gpu/drm/radeon/radeon_device.c r = rdev->pll_rreg(rdev, reg); reg 854 drivers/gpu/drm/radeon/radeon_device.c static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) reg 858 drivers/gpu/drm/radeon/radeon_device.c rdev->pll_wreg(rdev, reg, val); reg 870 drivers/gpu/drm/radeon/radeon_device.c static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) reg 875 drivers/gpu/drm/radeon/radeon_device.c r = rdev->mc_rreg(rdev, reg); reg 888 drivers/gpu/drm/radeon/radeon_device.c static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) reg 892 drivers/gpu/drm/radeon/radeon_device.c rdev->mc_wreg(rdev, reg, val); reg 904 drivers/gpu/drm/radeon/radeon_device.c static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) reg 908 drivers/gpu/drm/radeon/radeon_device.c WREG32(reg*4, val); reg 920 drivers/gpu/drm/radeon/radeon_device.c static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) reg 925 drivers/gpu/drm/radeon/radeon_device.c r = RREG32(reg*4); reg 938 drivers/gpu/drm/radeon/radeon_device.c static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) reg 942 drivers/gpu/drm/radeon/radeon_device.c WREG32_IO(reg*4, val); reg 954 drivers/gpu/drm/radeon/radeon_device.c static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) reg 959 drivers/gpu/drm/radeon/radeon_device.c r = RREG32_IO(reg*4); reg 34 drivers/gpu/drm/radeon/radeon_dp_mst.c uint32_t reg; reg 38 drivers/gpu/drm/radeon/radeon_dp_mst.c reg = RREG32(NI_DIG_BE_CNTL + primary->offset); reg 41 drivers/gpu/drm/radeon/radeon_dp_mst.c reg &= ~NI_DIG_FE_DIG_MODE(7); reg 42 drivers/gpu/drm/radeon/radeon_dp_mst.c reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST); reg 45 drivers/gpu/drm/radeon/radeon_dp_mst.c reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe); reg 47 drivers/gpu/drm/radeon/radeon_dp_mst.c reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe); reg 49 drivers/gpu/drm/radeon/radeon_dp_mst.c reg |= NI_DIG_HPD_SELECT(hpd); reg 50 drivers/gpu/drm/radeon/radeon_dp_mst.c DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg); reg 51 drivers/gpu/drm/radeon/radeon_dp_mst.c WREG32(NI_DIG_BE_CNTL + primary->offset, reg); reg 108 drivers/gpu/drm/radeon/radeon_i2c.c u32 reg; reg 111 drivers/gpu/drm/radeon/radeon_i2c.c reg = RADEON_GPIO_MONID; reg 114 drivers/gpu/drm/radeon/radeon_i2c.c reg = RADEON_GPIO_DVI_DDC; reg 116 drivers/gpu/drm/radeon/radeon_i2c.c reg = RADEON_GPIO_CRT2_DDC; reg 119 drivers/gpu/drm/radeon/radeon_i2c.c if (rec->a_clk_reg == reg) { reg 339 drivers/gpu/drm/radeon/radeon_i2c.c u32 tmp, reg; reg 347 drivers/gpu/drm/radeon/radeon_i2c.c reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | reg 388 drivers/gpu/drm/radeon/radeon_i2c.c reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); reg 391 drivers/gpu/drm/radeon/radeon_i2c.c reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); reg 404 drivers/gpu/drm/radeon/radeon_i2c.c reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); reg 407 drivers/gpu/drm/radeon/radeon_i2c.c reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); reg 410 drivers/gpu/drm/radeon/radeon_i2c.c reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); reg 423 drivers/gpu/drm/radeon/radeon_i2c.c reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); reg 426 drivers/gpu/drm/radeon/radeon_i2c.c reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); reg 444 drivers/gpu/drm/radeon/radeon_i2c.c reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); reg 447 drivers/gpu/drm/radeon/radeon_i2c.c reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); reg 450 drivers/gpu/drm/radeon/radeon_i2c.c reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); reg 479 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_cntl_0, reg); reg 511 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); reg 539 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(i2c_cntl_0, reg); reg 591 drivers/gpu/drm/radeon/radeon_i2c.c u32 tmp, reg; reg 652 drivers/gpu/drm/radeon/radeon_i2c.c reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; reg 655 drivers/gpu/drm/radeon/radeon_i2c.c reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); reg 658 drivers/gpu/drm/radeon/radeon_i2c.c reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); reg 661 drivers/gpu/drm/radeon/radeon_i2c.c reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); reg 686 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_CONTROL1, reg); reg 728 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); reg 771 drivers/gpu/drm/radeon/radeon_i2c.c WREG32(AVIVO_DC_I2C_CONTROL1, reg); reg 569 drivers/gpu/drm/radeon/radeon_irq_kms.c u32 reg, u32 mask, reg 572 drivers/gpu/drm/radeon/radeon_irq_kms.c u32 tmp = RREG32(reg); reg 580 drivers/gpu/drm/radeon/radeon_irq_kms.c WREG32(reg, tmp |= mask); reg 583 drivers/gpu/drm/radeon/radeon_irq_kms.c WREG32(reg, tmp & ~mask); reg 501 drivers/gpu/drm/radeon/radeon_mode.h u32 reg; reg 608 drivers/gpu/drm/radeon/radeon_object.c struct radeon_surface_reg *reg; reg 619 drivers/gpu/drm/radeon/radeon_object.c reg = &rdev->surface_regs[bo->surface_reg]; reg 627 drivers/gpu/drm/radeon/radeon_object.c reg = &rdev->surface_regs[i]; reg 628 drivers/gpu/drm/radeon/radeon_object.c if (!reg->bo) reg 631 drivers/gpu/drm/radeon/radeon_object.c old_object = reg->bo; reg 641 drivers/gpu/drm/radeon/radeon_object.c reg = &rdev->surface_regs[steal]; reg 642 drivers/gpu/drm/radeon/radeon_object.c old_object = reg->bo; reg 651 drivers/gpu/drm/radeon/radeon_object.c reg->bo = bo; reg 663 drivers/gpu/drm/radeon/radeon_object.c struct radeon_surface_reg *reg; reg 668 drivers/gpu/drm/radeon/radeon_object.c reg = &rdev->surface_regs[bo->surface_reg]; reg 671 drivers/gpu/drm/radeon/radeon_object.c reg->bo = NULL; reg 658 drivers/gpu/drm/radeon/radeon_uvd.c switch (pkt->reg + i*4) { reg 676 drivers/gpu/drm/radeon/radeon_uvd.c pkt->reg + i*4); reg 285 drivers/gpu/drm/radeon/rs400.c uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) reg 291 drivers/gpu/drm/radeon/rs400.c WREG32(RS480_NB_MC_INDEX, reg & 0xff); reg 298 drivers/gpu/drm/radeon/rs400.c void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) reg 303 drivers/gpu/drm/radeon/rs400.c WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); reg 232 drivers/gpu/drm/radeon/rs600.c tmp = RREG32(voltage->gpio.reg); reg 237 drivers/gpu/drm/radeon/rs600.c WREG32(voltage->gpio.reg, tmp); reg 241 drivers/gpu/drm/radeon/rs600.c tmp = RREG32(voltage->gpio.reg); reg 246 drivers/gpu/drm/radeon/rs600.c WREG32(voltage->gpio.reg, tmp); reg 924 drivers/gpu/drm/radeon/rs600.c uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) reg 930 drivers/gpu/drm/radeon/rs600.c WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | reg 937 drivers/gpu/drm/radeon/rs600.c void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) reg 942 drivers/gpu/drm/radeon/rs600.c WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | reg 651 drivers/gpu/drm/radeon/rs690.c uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) reg 657 drivers/gpu/drm/radeon/rs690.c WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg)); reg 664 drivers/gpu/drm/radeon/rs690.c void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) reg 669 drivers/gpu/drm/radeon/rs690.c WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) | reg 212 drivers/gpu/drm/radeon/rv515.c uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) reg 218 drivers/gpu/drm/radeon/rv515.c WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); reg 226 drivers/gpu/drm/radeon/rv515.c void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) reg 231 drivers/gpu/drm/radeon/rv515.c WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); reg 200 drivers/gpu/drm/radeon/rv515d.h #define PACKET0(reg, n) (CP_PACKET0 | \ reg 201 drivers/gpu/drm/radeon/rv515d.h REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ reg 985 drivers/gpu/drm/radeon/rv770d.h #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ reg 986 drivers/gpu/drm/radeon/rv770d.h (((reg) >> 2) & 0xFFFF) | \ reg 1313 drivers/gpu/drm/radeon/si.c u32 reg, u32 *val) reg 1315 drivers/gpu/drm/radeon/si.c switch (reg) { reg 1325 drivers/gpu/drm/radeon/si.c *val = RREG32(reg); reg 3370 drivers/gpu/drm/radeon/si.c rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); reg 4378 drivers/gpu/drm/radeon/si.c uint32_t reg; reg 4380 drivers/gpu/drm/radeon/si.c reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2); reg 4382 drivers/gpu/drm/radeon/si.c reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2); reg 4383 drivers/gpu/drm/radeon/si.c rdev->vm_manager.saved_table_addr[i] = RREG32(reg); reg 4411 drivers/gpu/drm/radeon/si.c static bool si_vm_reg_valid(u32 reg) reg 4414 drivers/gpu/drm/radeon/si.c if (reg >= 0x28000) reg 4418 drivers/gpu/drm/radeon/si.c if (reg >= 0xB000 && reg < 0xC000) reg 4422 drivers/gpu/drm/radeon/si.c switch (reg) { reg 4452 drivers/gpu/drm/radeon/si.c DRM_ERROR("Invalid register 0x%x in CS\n", reg); reg 4481 drivers/gpu/drm/radeon/si.c u32 start_reg, reg, i; reg 4490 drivers/gpu/drm/radeon/si.c reg = start_reg; reg 4491 drivers/gpu/drm/radeon/si.c if (!si_vm_reg_valid(reg)) { reg 4497 drivers/gpu/drm/radeon/si.c reg = start_reg + (4 * i); reg 4498 drivers/gpu/drm/radeon/si.c if (!si_vm_reg_valid(reg)) { reg 4511 drivers/gpu/drm/radeon/si.c reg = start_reg; reg 4512 drivers/gpu/drm/radeon/si.c if (!si_vm_reg_valid(reg)) { reg 4518 drivers/gpu/drm/radeon/si.c reg = start_reg + (4 * i); reg 4519 drivers/gpu/drm/radeon/si.c if (!si_vm_reg_valid(reg)) { reg 4536 drivers/gpu/drm/radeon/si.c u32 start_reg, end_reg, reg, i; reg 4587 drivers/gpu/drm/radeon/si.c reg = ib[idx + 3] * 4; reg 4588 drivers/gpu/drm/radeon/si.c if (!si_vm_reg_valid(reg)) reg 4600 drivers/gpu/drm/radeon/si.c reg = start_reg + (4 * i); reg 4601 drivers/gpu/drm/radeon/si.c if (!si_vm_reg_valid(reg)) reg 4609 drivers/gpu/drm/radeon/si.c reg = ib[idx + 5] * 4; reg 4610 drivers/gpu/drm/radeon/si.c if (!si_vm_reg_valid(reg)) reg 4616 drivers/gpu/drm/radeon/si.c reg = ib[idx + 3] * 4; reg 4617 drivers/gpu/drm/radeon/si.c if (!si_vm_reg_valid(reg)) reg 4631 drivers/gpu/drm/radeon/si.c reg = start_reg + (4 * i); reg 4632 drivers/gpu/drm/radeon/si.c if (!si_vm_reg_valid(reg)) reg 4654 drivers/gpu/drm/radeon/si.c u32 start_reg, reg, i; reg 4690 drivers/gpu/drm/radeon/si.c reg = ib[idx + 3] * 4; reg 4691 drivers/gpu/drm/radeon/si.c if (!si_vm_reg_valid(reg)) reg 4703 drivers/gpu/drm/radeon/si.c reg = start_reg + (4 * i); reg 4704 drivers/gpu/drm/radeon/si.c if (!si_vm_reg_valid(reg)) reg 4712 drivers/gpu/drm/radeon/si.c reg = ib[idx + 5] * 4; reg 4713 drivers/gpu/drm/radeon/si.c if (!si_vm_reg_valid(reg)) reg 4719 drivers/gpu/drm/radeon/si.c reg = ib[idx + 3] * 4; reg 4720 drivers/gpu/drm/radeon/si.c if (!si_vm_reg_valid(reg)) reg 2661 drivers/gpu/drm/radeon/si_dpm.c u32 load_line_slope, reg; reg 2672 drivers/gpu/drm/radeon/si_dpm.c reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; reg 2673 drivers/gpu/drm/radeon/si_dpm.c reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); reg 2674 drivers/gpu/drm/radeon/si_dpm.c WREG32(CG_CAC_CTRL, reg); reg 4374 drivers/gpu/drm/radeon/si_dpm.c u32 reg; reg 4452 drivers/gpu/drm/radeon/si_dpm.c reg = CG_R(0xffff) | CG_L(0); reg 4453 drivers/gpu/drm/radeon/si_dpm.c table->initialState.levels[0].aT = cpu_to_be32(reg); reg 4480 drivers/gpu/drm/radeon/si_dpm.c reg = MIN_POWER_MASK | MAX_POWER_MASK; reg 4481 drivers/gpu/drm/radeon/si_dpm.c table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); reg 4483 drivers/gpu/drm/radeon/si_dpm.c reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; reg 4484 drivers/gpu/drm/radeon/si_dpm.c table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); reg 4506 drivers/gpu/drm/radeon/si_dpm.c u32 reg; reg 4621 drivers/gpu/drm/radeon/si_dpm.c reg = MIN_POWER_MASK | MAX_POWER_MASK; reg 4622 drivers/gpu/drm/radeon/si_dpm.c table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); reg 4624 drivers/gpu/drm/radeon/si_dpm.c reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; reg 4625 drivers/gpu/drm/radeon/si_dpm.c table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); reg 1586 drivers/gpu/drm/radeon/sid.h #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ reg 1587 drivers/gpu/drm/radeon/sid.h (((reg) >> 2) & 0xFFFF) | \ reg 33 drivers/gpu/drm/rcar-du/rcar_du_crtc.c static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg) reg 37 drivers/gpu/drm/rcar-du/rcar_du_crtc.c return rcar_du_read(rcdu, rcrtc->mmio_offset + reg); reg 40 drivers/gpu/drm/rcar-du/rcar_du_crtc.c static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data) reg 44 drivers/gpu/drm/rcar-du/rcar_du_crtc.c rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data); reg 47 drivers/gpu/drm/rcar-du/rcar_du_crtc.c static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr) reg 51 drivers/gpu/drm/rcar-du/rcar_du_crtc.c rcar_du_write(rcdu, rcrtc->mmio_offset + reg, reg 52 drivers/gpu/drm/rcar-du/rcar_du_crtc.c rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr); reg 55 drivers/gpu/drm/rcar-du/rcar_du_crtc.c static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set) reg 59 drivers/gpu/drm/rcar-du/rcar_du_crtc.c rcar_du_write(rcdu, rcrtc->mmio_offset + reg, reg 60 drivers/gpu/drm/rcar-du/rcar_du_crtc.c rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set); reg 111 drivers/gpu/drm/rcar-du/rcar_du_drv.h static inline u32 rcar_du_read(struct rcar_du_device *rcdu, u32 reg) reg 113 drivers/gpu/drm/rcar-du/rcar_du_drv.h return ioread32(rcdu->mmio + reg); reg 116 drivers/gpu/drm/rcar-du/rcar_du_drv.h static inline void rcar_du_write(struct rcar_du_device *rcdu, u32 reg, u32 data) reg 118 drivers/gpu/drm/rcar-du/rcar_du_drv.h iowrite32(data, rcdu->mmio + reg); reg 33 drivers/gpu/drm/rcar-du/rcar_du_group.c u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg) reg 35 drivers/gpu/drm/rcar-du/rcar_du_group.c return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg); reg 38 drivers/gpu/drm/rcar-du/rcar_du_group.c void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data) reg 40 drivers/gpu/drm/rcar-du/rcar_du_group.c rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data); reg 52 drivers/gpu/drm/rcar-du/rcar_du_group.h u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg); reg 53 drivers/gpu/drm/rcar-du/rcar_du_group.h void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data); reg 322 drivers/gpu/drm/rcar-du/rcar_du_plane.c unsigned int index, u32 reg, u32 data) reg 324 drivers/gpu/drm/rcar-du/rcar_du_plane.c rcar_du_write(rgrp->dev, rgrp->mmio_offset + index * PLANE_OFF + reg, reg 81 drivers/gpu/drm/rcar-du/rcar_lvds.c static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data) reg 83 drivers/gpu/drm/rcar-du/rcar_lvds.c iowrite32(data, lvds->mmio + reg); reg 62 drivers/gpu/drm/rockchip/cdn-dp-core.c unsigned int reg, unsigned int val) reg 72 drivers/gpu/drm/rockchip/cdn-dp-core.c ret = regmap_write(dp->grf, reg, val); reg 218 drivers/gpu/drm/rockchip/cdn-dp-reg.c u8 msg[5], reg[5]; reg 233 drivers/gpu/drm/rockchip/cdn-dp-reg.c sizeof(reg) + len); reg 237 drivers/gpu/drm/rockchip/cdn-dp-reg.c ret = cdn_dp_mailbox_read_receive(dp, reg, sizeof(reg)); reg 249 drivers/gpu/drm/rockchip/cdn-dp-reg.c u8 msg[6], reg[5]; reg 264 drivers/gpu/drm/rockchip/cdn-dp-reg.c DPTX_WRITE_DPCD, sizeof(reg)); reg 268 drivers/gpu/drm/rockchip/cdn-dp-reg.c ret = cdn_dp_mailbox_read_receive(dp, reg, sizeof(reg)); reg 272 drivers/gpu/drm/rockchip/cdn-dp-reg.c if (addr != (reg[2] << 16 | reg[3] << 8 | reg[4])) reg 284 drivers/gpu/drm/rockchip/cdn-dp-reg.c u32 reg; reg 302 drivers/gpu/drm/rockchip/cdn-dp-reg.c reg, reg, 2000, FW_ALIVE_TIMEOUT_US); reg 305 drivers/gpu/drm/rockchip/cdn-dp-reg.c reg); reg 309 drivers/gpu/drm/rockchip/cdn-dp-reg.c reg = readl(dp->regs + VER_L) & 0xff; reg 310 drivers/gpu/drm/rockchip/cdn-dp-reg.c dp->fw_version = reg; reg 311 drivers/gpu/drm/rockchip/cdn-dp-reg.c reg = readl(dp->regs + VER_H) & 0xff; reg 312 drivers/gpu/drm/rockchip/cdn-dp-reg.c dp->fw_version |= reg << 8; reg 313 drivers/gpu/drm/rockchip/cdn-dp-reg.c reg = readl(dp->regs + VER_LIB_L_ADDR) & 0xff; reg 314 drivers/gpu/drm/rockchip/cdn-dp-reg.c dp->fw_version |= reg << 16; reg 315 drivers/gpu/drm/rockchip/cdn-dp-reg.c reg = readl(dp->regs + VER_LIB_H_ADDR) & 0xff; reg 316 drivers/gpu/drm/rockchip/cdn-dp-reg.c dp->fw_version |= reg << 24; reg 438 drivers/gpu/drm/rockchip/cdn-dp-reg.c u8 msg[2], reg[2], i; reg 452 drivers/gpu/drm/rockchip/cdn-dp-reg.c sizeof(reg) + length); reg 456 drivers/gpu/drm/rockchip/cdn-dp-reg.c ret = cdn_dp_mailbox_read_receive(dp, reg, sizeof(reg)); reg 464 drivers/gpu/drm/rockchip/cdn-dp-reg.c if (reg[0] == length && reg[1] == block / 2) reg 194 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c u32 reg; reg 298 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) reg 300 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c writel(val, dsi->base + reg); reg 303 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg) reg 305 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c return readl(dsi->base + reg); reg 308 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c static inline void dsi_set(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 mask) reg 310 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c dsi_write(dsi, reg, dsi_read(dsi, reg) | mask); reg 313 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg, reg 316 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); reg 909 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c while (cdata[i].reg) { reg 910 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c if (cdata[i].reg == res->start) { reg 994 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c .reg = 0xff960000, reg 1002 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c .reg = 0xff964000, reg 1014 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c .reg = 0xff960000, reg 1030 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c .reg = 0xff968000, reg 70 drivers/gpu/drm/rockchip/rockchip_drm_vop.c int i, reg = 0, mask = 0; \ reg 73 drivers/gpu/drm/rockchip/rockchip_drm_vop.c reg |= (v) << i; \ reg 77 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_INTR_SET_MASK(vop, name, mask, reg); \ reg 183 drivers/gpu/drm/rockchip/rockchip_drm_vop.c const struct vop_reg *reg) reg 185 drivers/gpu/drm/rockchip/rockchip_drm_vop.c return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; reg 188 drivers/gpu/drm/rockchip/rockchip_drm_vop.c static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, reg 194 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (!reg || !reg->mask) { reg 199 drivers/gpu/drm/rockchip/rockchip_drm_vop.c offset = reg->offset + _offset; reg 200 drivers/gpu/drm/rockchip/rockchip_drm_vop.c mask = reg->mask & _mask; reg 201 drivers/gpu/drm/rockchip/rockchip_drm_vop.c shift = reg->shift; reg 203 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (reg->write_mask) { reg 212 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (reg->relaxed) reg 219 drivers/gpu/drm/rockchip/rockchip_drm_vop.c const struct vop_reg *reg, int type) reg 222 drivers/gpu/drm/rockchip/rockchip_drm_vop.c uint32_t regs = vop_read_reg(vop, 0, reg); reg 491 drivers/gpu/drm/savage/savage_drv.h #define SAVAGE_READ(reg) \ reg 492 drivers/gpu/drm/savage/savage_drv.h readl(((void __iomem *)dev_priv->mmio->handle) + (reg)) reg 493 drivers/gpu/drm/savage/savage_drv.h #define SAVAGE_WRITE(reg) \ reg 494 drivers/gpu/drm/savage/savage_drv.h writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) reg 123 drivers/gpu/drm/savage/savage_state.c #define SAVE_STATE(reg,where) \ reg 124 drivers/gpu/drm/savage/savage_state.c if(start <= reg && start+count > reg) \ reg 125 drivers/gpu/drm/savage/savage_state.c dev_priv->state.where = regs[reg - start] reg 126 drivers/gpu/drm/savage/savage_state.c #define SAVE_STATE_MASK(reg,where,mask) do { \ reg 127 drivers/gpu/drm/savage/savage_state.c if(start <= reg && start+count > reg) { \ reg 129 drivers/gpu/drm/savage/savage_state.c tmp = regs[reg - start]; \ reg 112 drivers/gpu/drm/shmobile/shmob_drm_plane.c #define plane_reg_dump(sdev, splane, reg) \ reg 114 drivers/gpu/drm/shmobile/shmob_drm_plane.c splane->index, #reg, \ reg 115 drivers/gpu/drm/shmobile/shmob_drm_plane.c lcdc_read(sdev, reg(splane->index)), \ reg 116 drivers/gpu/drm/shmobile/shmob_drm_plane.c lcdc_read(sdev, reg(splane->index) + LCDC_SIDE_B_OFFSET)) reg 251 drivers/gpu/drm/shmobile/shmob_drm_regs.h static inline bool lcdc_is_banked(u32 reg) reg 253 drivers/gpu/drm/shmobile/shmob_drm_regs.h switch (reg) { reg 274 drivers/gpu/drm/shmobile/shmob_drm_regs.h return reg >= LDBnBBGCL(0) && reg <= LDBnBPPCR(3); reg 278 drivers/gpu/drm/shmobile/shmob_drm_regs.h static inline void lcdc_write_mirror(struct shmob_drm_device *sdev, u32 reg, reg 281 drivers/gpu/drm/shmobile/shmob_drm_regs.h iowrite32(data, sdev->mmio + reg + LCDC_MIRROR_OFFSET); reg 284 drivers/gpu/drm/shmobile/shmob_drm_regs.h static inline void lcdc_write(struct shmob_drm_device *sdev, u32 reg, u32 data) reg 286 drivers/gpu/drm/shmobile/shmob_drm_regs.h iowrite32(data, sdev->mmio + reg); reg 287 drivers/gpu/drm/shmobile/shmob_drm_regs.h if (lcdc_is_banked(reg)) reg 288 drivers/gpu/drm/shmobile/shmob_drm_regs.h iowrite32(data, sdev->mmio + reg + LCDC_SIDE_B_OFFSET); reg 291 drivers/gpu/drm/shmobile/shmob_drm_regs.h static inline u32 lcdc_read(struct shmob_drm_device *sdev, u32 reg) reg 293 drivers/gpu/drm/shmobile/shmob_drm_regs.h return ioread32(sdev->mmio + reg); reg 296 drivers/gpu/drm/shmobile/shmob_drm_regs.h static inline int lcdc_wait_bit(struct shmob_drm_device *sdev, u32 reg, reg 301 drivers/gpu/drm/shmobile/shmob_drm_regs.h while ((lcdc_read(sdev, reg) & mask) != until) { reg 51 drivers/gpu/drm/sis/sis_drv.h #define SIS_READ(reg) readl(((void __iomem *)dev_priv->mmio->handle) + (reg)) reg 52 drivers/gpu/drm/sis/sis_drv.h #define SIS_WRITE(reg, val) writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) reg 79 drivers/gpu/drm/sti/sti_cursor.c #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ reg 80 drivers/gpu/drm/sti/sti_cursor.c readl(cursor->regs + reg)) reg 162 drivers/gpu/drm/sti/sti_dvo.c #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ reg 163 drivers/gpu/drm/sti/sti_dvo.c readl(dvo->regs + reg)) reg 165 drivers/gpu/drm/sti/sti_dvo.c static void dvo_dbg_awg_microcode(struct seq_file *s, void __iomem *reg) reg 174 drivers/gpu/drm/sti/sti_dvo.c seq_printf(s, " %04X", readl(reg + i * 4)); reg 146 drivers/gpu/drm/sti/sti_gdp.c #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ reg 147 drivers/gpu/drm/sti/sti_gdp.c readl(gdp->regs + reg ## _OFFSET)) reg 314 drivers/gpu/drm/sti/sti_hda.c #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ reg 315 drivers/gpu/drm/sti/sti_hda.c readl(hda->regs + reg)) reg 323 drivers/gpu/drm/sti/sti_hda.c static void hda_dbg_awg_microcode(struct seq_file *s, void __iomem *reg) reg 331 drivers/gpu/drm/sti/sti_hda.c seq_printf(s, " %04X", readl(reg + i * 4)); reg 335 drivers/gpu/drm/sti/sti_hda.c static void hda_dbg_video_dacs_ctrl(struct seq_file *s, void __iomem *reg) reg 337 drivers/gpu/drm/sti/sti_hda.c u32 val = readl(reg); reg 593 drivers/gpu/drm/sti/sti_hdmi.c #define DBGFS_DUMP(str, reg) seq_printf(s, "%s %-25s 0x%08X", str, #reg, \ reg 594 drivers/gpu/drm/sti/sti_hdmi.c hdmi_read(hdmi, reg)) reg 595 drivers/gpu/drm/sti/sti_hdmi.c #define DBGFS_DUMP_DI(reg, slot) DBGFS_DUMP("\n", reg(slot)) reg 450 drivers/gpu/drm/sti/sti_hqvdp.c #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ reg 451 drivers/gpu/drm/sti/sti_hqvdp.c readl(hqvdp->regs + reg)) reg 77 drivers/gpu/drm/sti/sti_mixer.c #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ reg 78 drivers/gpu/drm/sti/sti_mixer.c sti_mixer_reg_read(mixer, reg)) reg 164 drivers/gpu/drm/sti/sti_tvout.c static void tvout_vip_set_color_order(struct sti_tvout *tvout, int reg, reg 167 drivers/gpu/drm/sti/sti_tvout.c u32 val = tvout_read(tvout, reg); reg 176 drivers/gpu/drm/sti/sti_tvout.c tvout_write(tvout, val, reg); reg 186 drivers/gpu/drm/sti/sti_tvout.c static void tvout_vip_set_clip_mode(struct sti_tvout *tvout, int reg, u32 range) reg 188 drivers/gpu/drm/sti/sti_tvout.c u32 val = tvout_read(tvout, reg); reg 192 drivers/gpu/drm/sti/sti_tvout.c tvout_write(tvout, val, reg); reg 202 drivers/gpu/drm/sti/sti_tvout.c static void tvout_vip_set_rnd(struct sti_tvout *tvout, int reg, u32 rnd) reg 204 drivers/gpu/drm/sti/sti_tvout.c u32 val = tvout_read(tvout, reg); reg 208 drivers/gpu/drm/sti/sti_tvout.c tvout_write(tvout, val, reg); reg 220 drivers/gpu/drm/sti/sti_tvout.c int reg, reg 225 drivers/gpu/drm/sti/sti_tvout.c u32 val = tvout_read(tvout, reg); reg 246 drivers/gpu/drm/sti/sti_tvout.c tvout_write(tvout, val, reg); reg 257 drivers/gpu/drm/sti/sti_tvout.c int reg, u32 in_vid_fmt) reg 259 drivers/gpu/drm/sti/sti_tvout.c u32 val = tvout_read(tvout, reg); reg 263 drivers/gpu/drm/sti/sti_tvout.c tvout_write(tvout, val, reg); reg 449 drivers/gpu/drm/sti/sti_tvout.c #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ reg 450 drivers/gpu/drm/sti/sti_tvout.c readl(tvout->regs + reg)) reg 60 drivers/gpu/drm/sti/sti_vid.c #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ reg 61 drivers/gpu/drm/sti/sti_vid.c readl(vid->regs + reg)) reg 87 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val) reg 89 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c writel(val, dsi->base + reg); reg 92 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c static inline u32 dsi_read(struct dw_mipi_dsi_stm *dsi, u32 reg) reg 94 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c return readl(dsi->base + reg); reg 97 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c static inline void dsi_set(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask) reg 99 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c dsi_write(dsi, reg, dsi_read(dsi, reg) | mask); reg 102 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c static inline void dsi_clear(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask) reg 104 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask); reg 107 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c static inline void dsi_update_bits(struct dw_mipi_dsi_stm *dsi, u32 reg, reg 110 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); reg 242 drivers/gpu/drm/stm/ltdc.c static inline u32 reg_read(void __iomem *base, u32 reg) reg 244 drivers/gpu/drm/stm/ltdc.c return readl_relaxed(base + reg); reg 247 drivers/gpu/drm/stm/ltdc.c static inline void reg_write(void __iomem *base, u32 reg, u32 val) reg 249 drivers/gpu/drm/stm/ltdc.c writel_relaxed(val, base + reg); reg 252 drivers/gpu/drm/stm/ltdc.c static inline void reg_set(void __iomem *base, u32 reg, u32 mask) reg 254 drivers/gpu/drm/stm/ltdc.c reg_write(base, reg, reg_read(base, reg) | mask); reg 257 drivers/gpu/drm/stm/ltdc.c static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) reg 259 drivers/gpu/drm/stm/ltdc.c reg_write(base, reg, reg_read(base, reg) & ~mask); reg 262 drivers/gpu/drm/stm/ltdc.c static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, reg 265 drivers/gpu/drm/stm/ltdc.c reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); reg 17 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c struct regmap_field *reg; reg 75 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c unsigned int reg; reg 78 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c regmap_field_read(ddc->reg, ®); reg 79 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c m = (reg >> 3) & 0xf; reg 80 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c n = reg & 0x7; reg 95 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c regmap_field_write(ddc->reg, reg 122 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c ddc->reg = devm_regmap_field_alloc(hdmi->dev, hdmi->regmap, reg 124 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c if (IS_ERR(ddc->reg)) reg 125 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c return PTR_ERR(ddc->reg); reg 263 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c unsigned long reg; reg 265 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_HPD_REG, reg, reg 266 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c reg & SUN4I_HDMI_HPD_HIGH, reg 496 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c u32 reg; reg 591 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); reg 592 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK; reg 593 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c reg |= hdmi->variant->pll_ctrl_init_val; reg 594 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); reg 35 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c u32 reg; reg 50 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg, reg 51 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c reg & mask, len * byte_time_ns, reg 55 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c if (reg & SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK) reg 73 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c u32 reg; reg 77 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); reg 78 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c reg &= ~SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK; reg 79 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c reg |= (msg->flags & I2C_M_RD) ? reg 82 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c writel(reg, hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); reg 102 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c reg, !reg, 100, 2000)) reg 133 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c reg, !reg, 100, 100000)) reg 137 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c regmap_field_read(hdmi->field_ddc_int_status, ®); reg 138 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c if ((reg & SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK) || reg 139 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c !(reg & SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE)) { reg 150 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c u32 reg; reg 168 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c reg, !reg, 100, 2000)) { reg 129 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c u32 reg; reg 131 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); reg 132 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c if (reg & SUN4I_HDMI_PAD_CTRL1_HALVE_CLK) reg 135 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); reg 136 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg = ((reg >> 4) & 0xf) + tmds->div_offset; reg 137 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c if (!reg) reg 138 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg = 1; reg 140 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c return parent_rate / reg; reg 148 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c u32 reg; reg 154 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); reg 155 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg &= ~SUN4I_HDMI_PAD_CTRL1_HALVE_CLK; reg 157 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg |= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK; reg 158 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c writel(reg, tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); reg 160 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); reg 161 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg &= ~SUN4I_HDMI_PLL_CTRL_DIV_MASK; reg 162 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c writel(reg | SUN4I_HDMI_PLL_CTRL_DIV(div - tmds->div_offset), reg 171 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c u32 reg; reg 173 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG); reg 174 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c return ((reg & SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK) >> reg 181 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c u32 reg; reg 186 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG); reg 187 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c reg &= ~SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK; reg 188 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c writel(reg | SUN4I_HDMI_PLL_DBG0_TMDS_PARENT(index), reg 408 drivers/gpu/drm/sun4i/sun4i_tcon.c u32 reg, val = 0; reg 451 drivers/gpu/drm/sun4i/sun4i_tcon.c reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 | reg 455 drivers/gpu/drm/sun4i/sun4i_tcon.c reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS; reg 457 drivers/gpu/drm/sun4i/sun4i_tcon.c reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS; reg 459 drivers/gpu/drm/sun4i/sun4i_tcon.c regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg); reg 864 drivers/gpu/drm/sun4i/sun4i_tcon.c u32 reg = 0; reg 906 drivers/gpu/drm/sun4i/sun4i_tcon.c if (!of_property_read_u32(port, "reg", ®) && reg > 0) reg 907 drivers/gpu/drm/sun4i/sun4i_tcon.c reg -= 1; reg 910 drivers/gpu/drm/sun4i/sun4i_tcon.c engine = sun4i_tcon_find_engine_traverse(drv, remote, reg); reg 940 drivers/gpu/drm/sun4i/sun4i_tcon.c u32 reg; reg 946 drivers/gpu/drm/sun4i/sun4i_tcon.c ret = of_property_read_u32(remote, "reg", ®); reg 950 drivers/gpu/drm/sun4i/sun4i_tcon.c ret = reg; reg 72 drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c u32 reg; reg 74 drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c regmap_read(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG, ®); reg 75 drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c reg = ((reg >> SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_SHIFT) & reg 78 drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c return parent_rate / reg; reg 111 drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c u32 reg; reg 113 drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c regmap_read(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, ®); reg 114 drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c reg = (reg & SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK) >> reg 117 drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c return reg; reg 61 drivers/gpu/drm/sun4i/sun8i_tcon_top.c u32 reg; reg 80 drivers/gpu/drm/sun4i/sun8i_tcon_top.c reg = readl(tcon_top->regs + TCON_TOP_PORT_SEL_REG); reg 82 drivers/gpu/drm/sun4i/sun8i_tcon_top.c reg &= ~TCON_TOP_PORT_DE0_MSK; reg 83 drivers/gpu/drm/sun4i/sun8i_tcon_top.c reg |= FIELD_PREP(TCON_TOP_PORT_DE0_MSK, tcon); reg 85 drivers/gpu/drm/sun4i/sun8i_tcon_top.c reg &= ~TCON_TOP_PORT_DE1_MSK; reg 86 drivers/gpu/drm/sun4i/sun8i_tcon_top.c reg |= FIELD_PREP(TCON_TOP_PORT_DE1_MSK, tcon); reg 88 drivers/gpu/drm/sun4i/sun8i_tcon_top.c writel(reg, tcon_top->regs + TCON_TOP_PORT_SEL_REG); reg 280 drivers/gpu/drm/tilcdc/tilcdc_crtc.c uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; reg 291 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770; reg 294 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1); reg 297 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2); reg 300 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4); reg 303 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8); reg 306 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16); reg 312 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg |= (info->fifo_th << 8); reg 313 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg); reg 327 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00; reg 328 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) | reg 337 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg &= ~0x78000033; reg 338 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg |= ((hfp-1) & 0x300) >> 8; reg 339 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg |= ((hbp-1) & 0x300) >> 4; reg 340 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg |= ((hsw-1) & 0x3c0) << 21; reg 342 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg); reg 344 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg = (((mode->hdisplay >> 4) - 1) << 4) | reg 349 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3; reg 350 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg); reg 352 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg = ((mode->vdisplay - 1) & 0x3ff) | reg 356 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg); reg 374 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & reg 378 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg |= LCDC_TFT_MODE; /* no monochrome/passive support */ reg 380 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg |= LCDC_TFT_ALT_ENABLE; reg 388 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg |= LCDC_V2_TFT_24BPP_UNPACK; reg 392 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg |= LCDC_V2_TFT_24BPP_MODE; reg 399 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg |= info->fdd < 12; reg 400 drivers/gpu/drm/tilcdc/tilcdc_crtc.c tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg); reg 870 drivers/gpu/drm/tilcdc/tilcdc_crtc.c uint32_t stat, reg; reg 934 drivers/gpu/drm/tilcdc/tilcdc_crtc.c reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG); reg 935 drivers/gpu/drm/tilcdc/tilcdc_crtc.c if (reg & LCDC_RASTER_ENABLE) { reg 424 drivers/gpu/drm/tilcdc/tilcdc_drv.c uint32_t reg; reg 426 drivers/gpu/drm/tilcdc/tilcdc_drv.c #define REG(rev, save, reg) { #reg, rev, save, reg } reg 467 drivers/gpu/drm/tilcdc/tilcdc_drv.c tilcdc_read(dev, registers[i].reg)); reg 114 drivers/gpu/drm/tilcdc/tilcdc_regs.h static inline void tilcdc_write(struct drm_device *dev, u32 reg, u32 data) reg 117 drivers/gpu/drm/tilcdc/tilcdc_regs.h iowrite32(data, priv->mmio + reg); reg 120 drivers/gpu/drm/tilcdc/tilcdc_regs.h static inline void tilcdc_write64(struct drm_device *dev, u32 reg, u64 data) reg 123 drivers/gpu/drm/tilcdc/tilcdc_regs.h volatile void __iomem *addr = priv->mmio + reg; reg 134 drivers/gpu/drm/tilcdc/tilcdc_regs.h static inline u32 tilcdc_read(struct drm_device *dev, u32 reg) reg 137 drivers/gpu/drm/tilcdc/tilcdc_regs.h return ioread32(priv->mmio + reg); reg 140 drivers/gpu/drm/tilcdc/tilcdc_regs.h static inline void tilcdc_write_mask(struct drm_device *dev, u32 reg, reg 143 drivers/gpu/drm/tilcdc/tilcdc_regs.h tilcdc_write(dev, reg, (tilcdc_read(dev, reg) & ~mask) | (val & mask)); reg 146 drivers/gpu/drm/tilcdc/tilcdc_regs.h static inline void tilcdc_set(struct drm_device *dev, u32 reg, u32 mask) reg 148 drivers/gpu/drm/tilcdc/tilcdc_regs.h tilcdc_write(dev, reg, tilcdc_read(dev, reg) | mask); reg 151 drivers/gpu/drm/tilcdc/tilcdc_regs.h static inline void tilcdc_clear(struct drm_device *dev, u32 reg, u32 mask) reg 153 drivers/gpu/drm/tilcdc/tilcdc_regs.h tilcdc_write(dev, reg, tilcdc_read(dev, reg) & ~mask); reg 150 drivers/gpu/drm/tiny/repaper.c static int repaper_write_buf(struct spi_device *spi, u8 reg, reg 155 drivers/gpu/drm/tiny/repaper.c ret = repaper_spi_transfer(spi, 0x70, ®, NULL, 1); reg 162 drivers/gpu/drm/tiny/repaper.c static int repaper_write_val(struct spi_device *spi, u8 reg, u8 val) reg 164 drivers/gpu/drm/tiny/repaper.c return repaper_write_buf(spi, reg, &val, 1); reg 167 drivers/gpu/drm/tiny/repaper.c static int repaper_read_val(struct spi_device *spi, u8 reg) reg 172 drivers/gpu/drm/tiny/repaper.c ret = repaper_spi_transfer(spi, 0x70, ®, NULL, 1); reg 22 drivers/gpu/drm/udl/udl_modeset.c static char *udl_set_register(char *buf, u8 reg, u8 val) reg 26 drivers/gpu/drm/udl/udl_modeset.c *buf++ = reg; reg 49 drivers/gpu/drm/udl/udl_modeset.c u8 reg; reg 52 drivers/gpu/drm/udl/udl_modeset.c reg = 0x07; reg 55 drivers/gpu/drm/udl/udl_modeset.c reg = 0x05; reg 58 drivers/gpu/drm/udl/udl_modeset.c reg = 0x01; reg 61 drivers/gpu/drm/udl/udl_modeset.c reg = 0x00; reg 65 drivers/gpu/drm/udl/udl_modeset.c return udl_set_register(buf, 0x1f, reg); reg 92 drivers/gpu/drm/udl/udl_modeset.c static char *udl_set_register_16(char *wrptr, u8 reg, u16 value) reg 94 drivers/gpu/drm/udl/udl_modeset.c wrptr = udl_set_register(wrptr, reg, value >> 8); reg 95 drivers/gpu/drm/udl/udl_modeset.c return udl_set_register(wrptr, reg+1, value); reg 102 drivers/gpu/drm/udl/udl_modeset.c static char *udl_set_register_16be(char *wrptr, u8 reg, u16 value) reg 104 drivers/gpu/drm/udl/udl_modeset.c wrptr = udl_set_register(wrptr, reg, value); reg 105 drivers/gpu/drm/udl/udl_modeset.c return udl_set_register(wrptr, reg+1, value >> 8); reg 134 drivers/gpu/drm/udl/udl_modeset.c static char *udl_set_register_lfsr16(char *wrptr, u8 reg, u16 value) reg 136 drivers/gpu/drm/udl/udl_modeset.c return udl_set_register_16(wrptr, reg, udl_lfsr16(value)); reg 15 drivers/gpu/drm/v3d/v3d_debugfs.c #define REGDEF(reg) { reg, #reg } reg 17 drivers/gpu/drm/v3d/v3d_debugfs.c u32 reg; reg 89 drivers/gpu/drm/v3d/v3d_debugfs.c v3d_hub_reg_defs[i].name, v3d_hub_reg_defs[i].reg, reg 90 drivers/gpu/drm/v3d/v3d_debugfs.c V3D_READ(v3d_hub_reg_defs[i].reg)); reg 97 drivers/gpu/drm/v3d/v3d_debugfs.c v3d_gca_reg_defs[i].reg, reg 98 drivers/gpu/drm/v3d/v3d_debugfs.c V3D_GCA_READ(v3d_gca_reg_defs[i].reg)); reg 107 drivers/gpu/drm/v3d/v3d_debugfs.c v3d_core_reg_defs[i].reg, reg 109 drivers/gpu/drm/v3d/v3d_debugfs.c v3d_core_reg_defs[i].reg)); reg 117 drivers/gpu/drm/v3d/v3d_debugfs.c v3d_csd_reg_defs[i].reg, reg 119 drivers/gpu/drm/v3d/v3d_debugfs.c v3d_csd_reg_defs[i].reg)); reg 483 drivers/gpu/drm/vc4/vc4_drv.h #define VC4_REG32(reg) { .name = #reg, .offset = reg } reg 124 drivers/gpu/drm/via/via_drv.h static inline u32 via_read(struct drm_via_private *dev_priv, u32 reg) reg 126 drivers/gpu/drm/via/via_drv.h return readl((void __iomem *)(dev_priv->mmio->handle + reg)); reg 129 drivers/gpu/drm/via/via_drv.h static inline void via_write(struct drm_via_private *dev_priv, u32 reg, reg 132 drivers/gpu/drm/via/via_drv.h writel(val, (void __iomem *)(dev_priv->mmio->handle + reg)); reg 135 drivers/gpu/drm/via/via_drv.h static inline void via_write8(struct drm_via_private *dev_priv, u32 reg, reg 138 drivers/gpu/drm/via/via_drv.h writeb(val, (void __iomem *)(dev_priv->mmio->handle + reg)); reg 142 drivers/gpu/drm/via/via_drv.h u32 reg, u32 mask, u32 val) reg 146 drivers/gpu/drm/via/via_drv.h tmp = readb((void __iomem *)(dev_priv->mmio->handle + reg)); reg 148 drivers/gpu/drm/via/via_drv.h writeb(tmp, (void __iomem *)(dev_priv->mmio->handle + reg)); reg 1036 drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h uint32 reg; /* register number */ reg 15 drivers/gpu/drm/zte/zx_drm_drv.h static inline u32 zx_readl(void __iomem *reg) reg 17 drivers/gpu/drm/zte/zx_drm_drv.h return readl_relaxed(reg); reg 20 drivers/gpu/drm/zte/zx_drm_drv.h static inline void zx_writel(void __iomem *reg, u32 val) reg 22 drivers/gpu/drm/zte/zx_drm_drv.h writel_relaxed(val, reg); reg 25 drivers/gpu/drm/zte/zx_drm_drv.h static inline void zx_writel_mask(void __iomem *reg, u32 mask, u32 val) reg 29 drivers/gpu/drm/zte/zx_drm_drv.h tmp = zx_readl(reg); reg 31 drivers/gpu/drm/zte/zx_drm_drv.h zx_writel(reg, tmp); reg 24 drivers/gpu/drm/zte/zx_tvenc.c u32 reg; reg 194 drivers/gpu/drm/zte/zx_tvenc.c regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask, reg 212 drivers/gpu/drm/zte/zx_tvenc.c regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask, 0); reg 323 drivers/gpu/drm/zte/zx_tvenc.c pwrctrl->reg = out_args.args[0]; reg 24 drivers/gpu/drm/zte/zx_vga.c u32 reg; reg 53 drivers/gpu/drm/zte/zx_vga.c regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask, reg 67 drivers/gpu/drm/zte/zx_vga.c regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask, 0); reg 212 drivers/gpu/drm/zte/zx_vga.c pwrctrl->reg = out_args.args[0]; reg 302 drivers/gpu/drm/zte/zx_vou.c u32 reg, shift; reg 306 drivers/gpu/drm/zte/zx_vou.c reg = VOU_CLK_SEL; reg 310 drivers/gpu/drm/zte/zx_vou.c reg = VOU_CLK_SEL; reg 314 drivers/gpu/drm/zte/zx_vou.c reg = VOU_DIV_PARA; reg 318 drivers/gpu/drm/zte/zx_vou.c reg = VOU_DIV_PARA; reg 322 drivers/gpu/drm/zte/zx_vou.c reg = VOU_DIV_PARA; reg 326 drivers/gpu/drm/zte/zx_vou.c reg = VOU_DIV_PARA; reg 330 drivers/gpu/drm/zte/zx_vou.c reg = VOU_DIV_PARA; reg 338 drivers/gpu/drm/zte/zx_vou.c zx_writel_mask(vou->vouctl + reg, 0x7 << shift, reg 36 drivers/gpu/host1x/hw/intr_hw.c unsigned long reg; reg 40 drivers/gpu/host1x/hw/intr_hw.c reg = host1x_sync_readl(host, reg 42 drivers/gpu/host1x/hw/intr_hw.c for_each_set_bit(id, ®, 32) { reg 265 drivers/gpu/host1x/job.c u32 reg; reg 305 drivers/gpu/host1x/job.c u32 reg = fw->reg; reg 313 drivers/gpu/host1x/job.c ret = check_register(fw, reg); reg 321 drivers/gpu/host1x/job.c reg++; reg 330 drivers/gpu/host1x/job.c u32 reg = fw->reg; reg 337 drivers/gpu/host1x/job.c ret = check_register(fw, reg); reg 341 drivers/gpu/host1x/job.c reg++; reg 359 drivers/gpu/host1x/job.c ret = check_register(fw, fw->reg); reg 387 drivers/gpu/host1x/job.c fw->reg = 0; reg 396 drivers/gpu/host1x/job.c fw->reg = word >> 16 & 0xfff; reg 404 drivers/gpu/host1x/job.c fw->reg = word >> 16 & 0xfff; reg 412 drivers/gpu/host1x/job.c fw->reg = word >> 16 & 0xfff; reg 421 drivers/gpu/host1x/job.c fw->reg = word >> 16 & 0xfff; reg 341 drivers/gpu/ipu-v3/ipu-common.c u32 reg; reg 345 drivers/gpu/ipu-v3/ipu-common.c reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); reg 347 drivers/gpu/ipu-v3/ipu-common.c reg |= idma_mask(channel->num); reg 349 drivers/gpu/ipu-v3/ipu-common.c reg &= ~idma_mask(channel->num); reg 350 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num)); reg 360 drivers/gpu/ipu-v3/ipu-common.c u32 reg; reg 363 drivers/gpu/ipu-v3/ipu-common.c { .chnum = 5, .reg = IDMAC_CH_LOCK_EN_1, .shift = 0, }, reg 364 drivers/gpu/ipu-v3/ipu-common.c { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift = 2, }, reg 365 drivers/gpu/ipu-v3/ipu-common.c { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift = 4, }, reg 366 drivers/gpu/ipu-v3/ipu-common.c { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift = 6, }, reg 367 drivers/gpu/ipu-v3/ipu-common.c { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift = 8, }, reg 368 drivers/gpu/ipu-v3/ipu-common.c { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, }, reg 369 drivers/gpu/ipu-v3/ipu-common.c { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, }, reg 370 drivers/gpu/ipu-v3/ipu-common.c { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, }, reg 371 drivers/gpu/ipu-v3/ipu-common.c { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, }, reg 372 drivers/gpu/ipu-v3/ipu-common.c { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, }, reg 373 drivers/gpu/ipu-v3/ipu-common.c { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, }, reg 374 drivers/gpu/ipu-v3/ipu-common.c { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift = 0, }, reg 375 drivers/gpu/ipu-v3/ipu-common.c { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift = 2, }, reg 376 drivers/gpu/ipu-v3/ipu-common.c { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift = 4, }, reg 377 drivers/gpu/ipu-v3/ipu-common.c { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift = 6, }, reg 378 drivers/gpu/ipu-v3/ipu-common.c { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift = 8, }, reg 379 drivers/gpu/ipu-v3/ipu-common.c { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, }, reg 424 drivers/gpu/ipu-v3/ipu-common.c regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg); reg 427 drivers/gpu/ipu-v3/ipu-common.c ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg); reg 500 drivers/gpu/ipu-v3/ipu-common.c u32 reg = 0; reg 505 drivers/gpu/ipu-v3/ipu-common.c reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)); reg 508 drivers/gpu/ipu-v3/ipu-common.c reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)); reg 511 drivers/gpu/ipu-v3/ipu-common.c reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num)); reg 516 drivers/gpu/ipu-v3/ipu-common.c return ((reg & idma_mask(channel->num)) != 0); reg 748 drivers/gpu/ipu-v3/ipu-common.c u32 reg; reg 810 drivers/gpu/ipu-v3/ipu-common.c src_reg = ipu_cm_read(ipu, link->src.reg); reg 813 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, src_reg, link->src.reg); reg 817 drivers/gpu/ipu-v3/ipu-common.c sink_reg = ipu_cm_read(ipu, link->sink.reg); reg 820 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, sink_reg, link->sink.reg); reg 844 drivers/gpu/ipu-v3/ipu-common.c src_reg = ipu_cm_read(ipu, link->src.reg); reg 846 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, src_reg, link->src.reg); reg 850 drivers/gpu/ipu-v3/ipu-common.c sink_reg = ipu_cm_read(ipu, link->sink.reg); reg 852 drivers/gpu/ipu-v3/ipu-common.c ipu_cm_write(ipu, sink_reg, link->sink.reg); reg 1219 drivers/gpu/ipu-v3/ipu-common.c struct ipu_platform_reg *reg = &client_reg[i]; reg 1233 drivers/gpu/ipu-v3/ipu-common.c pdev = platform_device_alloc(reg->name, id++); reg 1241 drivers/gpu/ipu-v3/ipu-common.c reg->pdata.of_node = of_node; reg 1242 drivers/gpu/ipu-v3/ipu-common.c ret = platform_device_add_data(pdev, ®->pdata, reg 1243 drivers/gpu/ipu-v3/ipu-common.c sizeof(reg->pdata)); reg 554 drivers/gpu/ipu-v3/ipu-csi.c u32 reg; reg 558 drivers/gpu/ipu-v3/ipu-csi.c reg = ipu_csi_read(csi, CSI_ACT_FRM_SIZE); reg 559 drivers/gpu/ipu-v3/ipu-csi.c w->width = (reg & 0xFFFF) + 1; reg 560 drivers/gpu/ipu-v3/ipu-csi.c w->height = (reg >> 16 & 0xFFFF) + 1; reg 562 drivers/gpu/ipu-v3/ipu-csi.c reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL); reg 563 drivers/gpu/ipu-v3/ipu-csi.c w->left = (reg & CSI_HSC_MASK) >> CSI_HSC_SHIFT; reg 564 drivers/gpu/ipu-v3/ipu-csi.c w->top = (reg & CSI_VSC_MASK) >> CSI_VSC_SHIFT; reg 573 drivers/gpu/ipu-v3/ipu-csi.c u32 reg; reg 580 drivers/gpu/ipu-v3/ipu-csi.c reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL); reg 581 drivers/gpu/ipu-v3/ipu-csi.c reg &= ~(CSI_HSC_MASK | CSI_VSC_MASK); reg 582 drivers/gpu/ipu-v3/ipu-csi.c reg |= ((w->top << CSI_VSC_SHIFT) | (w->left << CSI_HSC_SHIFT)); reg 583 drivers/gpu/ipu-v3/ipu-csi.c ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL); reg 592 drivers/gpu/ipu-v3/ipu-csi.c u32 reg; reg 596 drivers/gpu/ipu-v3/ipu-csi.c reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL); reg 597 drivers/gpu/ipu-v3/ipu-csi.c reg &= ~(CSI_HORI_DOWNSIZE_EN | CSI_VERT_DOWNSIZE_EN); reg 598 drivers/gpu/ipu-v3/ipu-csi.c reg |= (horiz ? CSI_HORI_DOWNSIZE_EN : 0) | reg 600 drivers/gpu/ipu-v3/ipu-csi.c ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL); reg 111 drivers/gpu/ipu-v3/ipu-dc.c u32 reg; reg 113 drivers/gpu/ipu-v3/ipu-dc.c reg = readl(dc->base + DC_RL_CH(event)); reg 114 drivers/gpu/ipu-v3/ipu-dc.c reg &= ~(0xffff << (16 * (event & 0x1))); reg 115 drivers/gpu/ipu-v3/ipu-dc.c reg |= ((addr << 8) | priority) << (16 * (event & 0x1)); reg 116 drivers/gpu/ipu-v3/ipu-dc.c writel(reg, dc->base + DC_RL_CH(event)); reg 165 drivers/gpu/ipu-v3/ipu-dc.c u32 reg = 0; reg 212 drivers/gpu/ipu-v3/ipu-dc.c reg = readl(dc->base + DC_WR_CH_CONF); reg 214 drivers/gpu/ipu-v3/ipu-dc.c reg |= DC_WR_CH_CONF_FIELD_MODE; reg 216 drivers/gpu/ipu-v3/ipu-dc.c reg &= ~DC_WR_CH_CONF_FIELD_MODE; reg 217 drivers/gpu/ipu-v3/ipu-dc.c writel(reg, dc->base + DC_WR_CH_CONF); reg 243 drivers/gpu/ipu-v3/ipu-dc.c u32 reg; reg 245 drivers/gpu/ipu-v3/ipu-dc.c reg = readl(dc->base + DC_WR_CH_CONF); reg 246 drivers/gpu/ipu-v3/ipu-dc.c reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL; reg 247 drivers/gpu/ipu-v3/ipu-dc.c writel(reg, dc->base + DC_WR_CH_CONF); reg 282 drivers/gpu/ipu-v3/ipu-dc.c u32 reg; reg 284 drivers/gpu/ipu-v3/ipu-dc.c reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr)); reg 285 drivers/gpu/ipu-v3/ipu-dc.c reg &= ~(0xffff << (16 * (ptr & 0x1))); reg 286 drivers/gpu/ipu-v3/ipu-dc.c reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1)); reg 287 drivers/gpu/ipu-v3/ipu-dc.c writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr)); reg 289 drivers/gpu/ipu-v3/ipu-dc.c reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map)); reg 290 drivers/gpu/ipu-v3/ipu-dc.c reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num))); reg 291 drivers/gpu/ipu-v3/ipu-dc.c reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num)); reg 292 drivers/gpu/ipu-v3/ipu-dc.c writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map)); reg 297 drivers/gpu/ipu-v3/ipu-dc.c u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map)); reg 299 drivers/gpu/ipu-v3/ipu-dc.c writel(reg & ~(0xffff << (16 * (map & 0x1))), reg 137 drivers/gpu/ipu-v3/ipu-di.c u32 reg; reg 138 drivers/gpu/ipu-v3/ipu-di.c reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) | reg 140 drivers/gpu/ipu-v3/ipu-di.c ipu_di_write(di, reg, DI_DW_GEN(wave_gen)); reg 146 drivers/gpu/ipu-v3/ipu-di.c u32 reg; reg 148 drivers/gpu/ipu-v3/ipu-di.c reg = ipu_di_read(di, DI_DW_GEN(wave_gen)); reg 149 drivers/gpu/ipu-v3/ipu-di.c reg &= ~(0x3 << (di_pin * 2)); reg 150 drivers/gpu/ipu-v3/ipu-di.c reg |= set << (di_pin * 2); reg 151 drivers/gpu/ipu-v3/ipu-di.c ipu_di_write(di, reg, DI_DW_GEN(wave_gen)); reg 159 drivers/gpu/ipu-v3/ipu-di.c u32 reg; reg 175 drivers/gpu/ipu-v3/ipu-di.c reg = DI_SW_GEN0_RUN_COUNT(c->run_count) | reg 179 drivers/gpu/ipu-v3/ipu-di.c ipu_di_write(di, reg, DI_SW_GEN0(wave_gen)); reg 181 drivers/gpu/ipu-v3/ipu-di.c reg = DI_SW_GEN1_CNT_POL_GEN_EN(c->cnt_polarity_gen_en) | reg 191 drivers/gpu/ipu-v3/ipu-di.c reg |= DI_SW_GEN1_AUTO_RELOAD; reg 193 drivers/gpu/ipu-v3/ipu-di.c ipu_di_write(di, reg, DI_SW_GEN1(wave_gen)); reg 195 drivers/gpu/ipu-v3/ipu-di.c reg = ipu_di_read(di, DI_STP_REP(wave_gen)); reg 196 drivers/gpu/ipu-v3/ipu-di.c reg &= ~(0xffff << (16 * ((wave_gen - 1) & 0x1))); reg 197 drivers/gpu/ipu-v3/ipu-di.c reg |= c->repeat_count << (16 * ((wave_gen - 1) & 0x1)); reg 198 drivers/gpu/ipu-v3/ipu-di.c ipu_di_write(di, reg, DI_STP_REP(wave_gen)); reg 559 drivers/gpu/ipu-v3/ipu-di.c u32 reg; reg 621 drivers/gpu/ipu-v3/ipu-di.c reg = ipu_di_read(di, DI_POL); reg 622 drivers/gpu/ipu-v3/ipu-di.c reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15); reg 625 drivers/gpu/ipu-v3/ipu-di.c reg |= DI_POL_DRDY_POLARITY_15; reg 627 drivers/gpu/ipu-v3/ipu-di.c reg |= DI_POL_DRDY_DATA_POLARITY; reg 629 drivers/gpu/ipu-v3/ipu-di.c ipu_di_write(di, reg, DI_POL); reg 83 drivers/gpu/ipu-v3/ipu-dp.c u32 reg; reg 87 drivers/gpu/ipu-v3/ipu-dp.c reg = readl(flow->base + DP_COM_CONF); reg 89 drivers/gpu/ipu-v3/ipu-dp.c reg &= ~DP_COM_CONF_GWSEL; reg 91 drivers/gpu/ipu-v3/ipu-dp.c reg |= DP_COM_CONF_GWSEL; reg 92 drivers/gpu/ipu-v3/ipu-dp.c writel(reg, flow->base + DP_COM_CONF); reg 95 drivers/gpu/ipu-v3/ipu-dp.c reg = readl(flow->base + DP_GRAPH_WIND_CTRL) & 0x00FFFFFFL; reg 96 drivers/gpu/ipu-v3/ipu-dp.c writel(reg | ((u32) alpha << 24), reg 99 drivers/gpu/ipu-v3/ipu-dp.c reg = readl(flow->base + DP_COM_CONF); reg 100 drivers/gpu/ipu-v3/ipu-dp.c writel(reg | DP_COM_CONF_GWAM, flow->base + DP_COM_CONF); reg 102 drivers/gpu/ipu-v3/ipu-dp.c reg = readl(flow->base + DP_COM_CONF); reg 103 drivers/gpu/ipu-v3/ipu-dp.c writel(reg & ~DP_COM_CONF_GWAM, flow->base + DP_COM_CONF); reg 132 drivers/gpu/ipu-v3/ipu-dp.c u32 reg; reg 134 drivers/gpu/ipu-v3/ipu-dp.c reg = readl(flow->base + DP_COM_CONF); reg 135 drivers/gpu/ipu-v3/ipu-dp.c reg &= ~DP_COM_CONF_CSC_DEF_MASK; reg 138 drivers/gpu/ipu-v3/ipu-dp.c writel(reg, flow->base + DP_COM_CONF); reg 162 drivers/gpu/ipu-v3/ipu-dp.c reg |= place; reg 164 drivers/gpu/ipu-v3/ipu-dp.c writel(reg, flow->base + DP_COM_CONF); reg 231 drivers/gpu/ipu-v3/ipu-dp.c u32 reg; reg 238 drivers/gpu/ipu-v3/ipu-dp.c reg = readl(flow->base + DP_COM_CONF); reg 239 drivers/gpu/ipu-v3/ipu-dp.c reg |= DP_COM_CONF_FG_EN; reg 240 drivers/gpu/ipu-v3/ipu-dp.c writel(reg, flow->base + DP_COM_CONF); reg 254 drivers/gpu/ipu-v3/ipu-dp.c u32 reg, csc; reg 263 drivers/gpu/ipu-v3/ipu-dp.c reg = readl(flow->base + DP_COM_CONF); reg 264 drivers/gpu/ipu-v3/ipu-dp.c csc = reg & DP_COM_CONF_CSC_DEF_MASK; reg 265 drivers/gpu/ipu-v3/ipu-dp.c reg &= ~DP_COM_CONF_CSC_DEF_MASK; reg 267 drivers/gpu/ipu-v3/ipu-dp.c reg |= DP_COM_CONF_CSC_DEF_BG; reg 269 drivers/gpu/ipu-v3/ipu-dp.c reg &= ~DP_COM_CONF_FG_EN; reg 270 drivers/gpu/ipu-v3/ipu-dp.c writel(reg, flow->base + DP_COM_CONF); reg 140 drivers/gpu/ipu-v3/ipu-ic.c const struct ic_task_regoffs *reg; reg 185 drivers/gpu/ipu-v3/ipu-ic.c (priv->tpmem_base + ic->reg->tpmem_csc[csc_index]); reg 332 drivers/gpu/ipu-v3/ipu-ic.c u32 reg, ic_conf; reg 375 drivers/gpu/ipu-v3/ipu-ic.c reg = ipu_ic_read(ic, IC_CMBP_1); reg 376 drivers/gpu/ipu-v3/ipu-ic.c reg &= ~(0xff << ic->bit->ic_cmb_galpha_bit); reg 377 drivers/gpu/ipu-v3/ipu-ic.c reg |= (galpha << ic->bit->ic_cmb_galpha_bit); reg 378 drivers/gpu/ipu-v3/ipu-ic.c ipu_ic_write(ic, reg, IC_CMBP_1); reg 429 drivers/gpu/ipu-v3/ipu-ic.c ipu_ic_write(ic, rsc, ic->reg->rsc); reg 724 drivers/gpu/ipu-v3/ipu-ic.c priv->task[i].reg = &ic_task_reg[i]; reg 60 drivers/gpu/ipu-v3/ipu-vdi.c u32 reg; reg 80 drivers/gpu/ipu-v3/ipu-vdi.c reg = ipu_vdi_read(vdi, VDI_C); reg 82 drivers/gpu/ipu-v3/ipu-vdi.c reg &= ~(VDI_C_TOP_FIELD_MAN_1 | VDI_C_TOP_FIELD_AUTO_1); reg 84 drivers/gpu/ipu-v3/ipu-vdi.c reg |= VDI_C_TOP_FIELD_MAN_1 | VDI_C_TOP_FIELD_AUTO_1; reg 85 drivers/gpu/ipu-v3/ipu-vdi.c ipu_vdi_write(vdi, reg, VDI_C); reg 94 drivers/gpu/ipu-v3/ipu-vdi.c u32 reg; reg 98 drivers/gpu/ipu-v3/ipu-vdi.c reg = ipu_vdi_read(vdi, VDI_C); reg 100 drivers/gpu/ipu-v3/ipu-vdi.c reg &= ~VDI_C_MOT_SEL_MASK; reg 104 drivers/gpu/ipu-v3/ipu-vdi.c reg |= VDI_C_MOT_SEL_MED; reg 107 drivers/gpu/ipu-v3/ipu-vdi.c reg |= VDI_C_MOT_SEL_FULL; reg 110 drivers/gpu/ipu-v3/ipu-vdi.c reg |= VDI_C_MOT_SEL_LOW; reg 114 drivers/gpu/ipu-v3/ipu-vdi.c ipu_vdi_write(vdi, reg, VDI_C); reg 123 drivers/gpu/ipu-v3/ipu-vdi.c u32 pixel_fmt, reg; reg 127 drivers/gpu/ipu-v3/ipu-vdi.c reg = ((yres - 1) << 16) | (xres - 1); reg 128 drivers/gpu/ipu-v3/ipu-vdi.c ipu_vdi_write(vdi, reg, VDI_FSIZE); reg 142 drivers/gpu/ipu-v3/ipu-vdi.c reg = ipu_vdi_read(vdi, VDI_C); reg 143 drivers/gpu/ipu-v3/ipu-vdi.c reg |= pixel_fmt; reg 144 drivers/gpu/ipu-v3/ipu-vdi.c reg |= VDI_C_BURST_SIZE2_4; reg 145 drivers/gpu/ipu-v3/ipu-vdi.c reg |= VDI_C_BURST_SIZE1_4 | VDI_C_VWM1_CLR_2; reg 146 drivers/gpu/ipu-v3/ipu-vdi.c reg |= VDI_C_BURST_SIZE3_4 | VDI_C_VWM3_CLR_2; reg 147 drivers/gpu/ipu-v3/ipu-vdi.c ipu_vdi_write(vdi, reg, VDI_C); reg 209 drivers/hid/hid-steam.c u8 reg; reg 216 drivers/hid/hid-steam.c reg = va_arg(args, int); reg 217 drivers/hid/hid-steam.c if (reg == 0) reg 220 drivers/hid/hid-steam.c cmd[cmd[1] + 2] = reg; reg 101 drivers/hid/i2c-hid/i2c-hid-core.c __le16 reg; reg 227 drivers/hid/i2c-hid/i2c-hid-core.c cmd->c.reg = ihid->wHIDDescRegister; reg 307 drivers/hid/intel-ish-hid/ipc/ipc.c uint32_t reg = 0; reg 309 drivers/hid/intel-ish-hid/ipc/ipc.c memcpy(®, &r_buf[length >> 2], rem); reg 310 drivers/hid/intel-ish-hid/ipc/ipc.c ish_reg_write(dev, reg_addr, reg); reg 900 drivers/hsi/controllers/omap_ssi_port.c u32 reg; reg 942 drivers/hsi/controllers/omap_ssi_port.c reg = readl(omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); reg 948 drivers/hsi/controllers/omap_ssi_port.c reg &= ~val; reg 949 drivers/hsi/controllers/omap_ssi_port.c writel_relaxed(reg, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0)); reg 47 drivers/hwmon/ad7414.c static inline int ad7414_temp_from_reg(s16 reg) reg 53 drivers/hwmon/ad7414.c return ((int)reg / 64) * 250; reg 56 drivers/hwmon/ad7414.c static inline int ad7414_read(struct i2c_client *client, u8 reg) reg 58 drivers/hwmon/ad7414.c if (reg == AD7414_REG_TEMP) reg 59 drivers/hwmon/ad7414.c return i2c_smbus_read_word_swapped(client, reg); reg 61 drivers/hwmon/ad7414.c return i2c_smbus_read_byte_data(client, reg); reg 64 drivers/hwmon/ad7414.c static inline int ad7414_write(struct i2c_client *client, u8 reg, u8 value) reg 66 drivers/hwmon/ad7414.c return i2c_smbus_write_byte_data(client, reg, value); reg 129 drivers/hwmon/ad7414.c u8 reg = AD7414_REG_LIMIT[index]; reg 141 drivers/hwmon/ad7414.c ad7414_write(client, reg, temp); reg 220 drivers/hwmon/ad7418.c int reg = i2c_smbus_read_byte_data(client, AD7418_REG_CONF); reg 221 drivers/hwmon/ad7418.c if (reg < 0) { reg 225 drivers/hwmon/ad7418.c i2c_smbus_write_byte_data(client, AD7418_REG_CONF, reg & 0xfe); reg 169 drivers/hwmon/adc128d818.c u8 reg, regval; reg 181 drivers/hwmon/adc128d818.c reg = index == 1 ? ADC128_REG_IN_MIN(nr) : ADC128_REG_IN_MAX(nr); reg 182 drivers/hwmon/adc128d818.c i2c_smbus_write_byte_data(data->client, reg, regval); reg 81 drivers/hwmon/adm1025.c #define IN_FROM_REG(reg, scale) (((reg) * (scale) + 96) / 192) reg 86 drivers/hwmon/adm1025.c #define TEMP_FROM_REG(reg) ((reg) * 1000) reg 480 drivers/hwmon/adm1025.c u8 reg; reg 495 drivers/hwmon/adm1025.c reg = i2c_smbus_read_byte_data(client, reg 497 drivers/hwmon/adm1025.c if (reg == 0) reg 503 drivers/hwmon/adm1025.c reg = i2c_smbus_read_byte_data(client, reg 505 drivers/hwmon/adm1025.c if (reg == 0) reg 514 drivers/hwmon/adm1025.c reg = i2c_smbus_read_byte_data(client, ADM1025_REG_CONFIG); reg 515 drivers/hwmon/adm1025.c if (!(reg & 0x01)) reg 517 drivers/hwmon/adm1025.c (reg&0x7E)|0x01); reg 291 drivers/hwmon/adm1026.c static int adm1026_read_value(struct i2c_client *client, u8 reg) reg 295 drivers/hwmon/adm1026.c if (reg < 0x80) { reg 297 drivers/hwmon/adm1026.c res = i2c_smbus_read_byte_data(client, reg) & 0xff; reg 305 drivers/hwmon/adm1026.c static int adm1026_write_value(struct i2c_client *client, u8 reg, int value) reg 309 drivers/hwmon/adm1026.c if (reg < 0x80) { reg 311 drivers/hwmon/adm1026.c res = i2c_smbus_write_byte_data(client, reg, value); reg 203 drivers/hwmon/adm1029.c u8 reg; reg 213 drivers/hwmon/adm1029.c reg = i2c_smbus_read_byte_data(client, reg 234 drivers/hwmon/adm1029.c reg = (reg & 0x3F) | (val << 6); reg 237 drivers/hwmon/adm1029.c data->fan_div[attr->index] = reg; reg 241 drivers/hwmon/adm1029.c ADM1029_REG_FAN_DIV[attr->index], reg); reg 96 drivers/hwmon/adm1031.c static inline u8 adm1031_read_value(struct i2c_client *client, u8 reg) reg 98 drivers/hwmon/adm1031.c return i2c_smbus_read_byte_data(client, reg); reg 102 drivers/hwmon/adm1031.c adm1031_write_value(struct i2c_client *client, u8 reg, unsigned int value) reg 104 drivers/hwmon/adm1031.c return i2c_smbus_write_byte_data(client, reg, value); reg 209 drivers/hwmon/adm1031.c #define FAN_FROM_REG(reg, div) ((reg) ? \ reg 210 drivers/hwmon/adm1031.c (11250 * 60) / ((reg) * (div)) : 0) reg 212 drivers/hwmon/adm1031.c static int FAN_TO_REG(int reg, int div) reg 215 drivers/hwmon/adm1031.c tmp = FAN_FROM_REG(clamp_val(reg, 0, 65535), div); reg 219 drivers/hwmon/adm1031.c #define FAN_DIV_FROM_REG(reg) (1<<(((reg)&0xc0)>>6)) reg 224 drivers/hwmon/adm1031.c #define FAN_CHAN_FROM_REG(reg) (((reg) >> 5) & 7) reg 225 drivers/hwmon/adm1031.c #define FAN_CHAN_TO_REG(val, reg) \ reg 226 drivers/hwmon/adm1031.c (((reg) & 0x1F) | (((val) << 5) & 0xe0)) reg 228 drivers/hwmon/adm1031.c #define AUTO_TEMP_MIN_TO_REG(val, reg) \ reg 229 drivers/hwmon/adm1031.c ((((val) / 500) & 0xf8) | ((reg) & 0x7)) reg 230 drivers/hwmon/adm1031.c #define AUTO_TEMP_RANGE_FROM_REG(reg) (5000 * (1 << ((reg) & 0x7))) reg 231 drivers/hwmon/adm1031.c #define AUTO_TEMP_MIN_FROM_REG(reg) (1000 * ((((reg) >> 3) & 0x1f) << 2)) reg 233 drivers/hwmon/adm1031.c #define AUTO_TEMP_MIN_FROM_REG_DEG(reg) ((((reg) >> 3) & 0x1f) << 2) reg 235 drivers/hwmon/adm1031.c #define AUTO_TEMP_OFF_FROM_REG(reg) \ reg 236 drivers/hwmon/adm1031.c (AUTO_TEMP_MIN_FROM_REG(reg) - 5000) reg 238 drivers/hwmon/adm1031.c #define AUTO_TEMP_MAX_FROM_REG(reg) \ reg 239 drivers/hwmon/adm1031.c (AUTO_TEMP_RANGE_FROM_REG(reg) + \ reg 240 drivers/hwmon/adm1031.c AUTO_TEMP_MIN_FROM_REG(reg)) reg 242 drivers/hwmon/adm1031.c static int AUTO_TEMP_MAX_TO_REG(int val, int reg, int pwm) reg 245 drivers/hwmon/adm1031.c int range = val - AUTO_TEMP_MIN_FROM_REG(reg); reg 247 drivers/hwmon/adm1031.c range = ((val - AUTO_TEMP_MIN_FROM_REG(reg))*10)/(16 - pwm); reg 248 drivers/hwmon/adm1031.c ret = ((reg & 0xf8) | reg 286 drivers/hwmon/adm1031.c get_fan_auto_nearest(struct adm1031_data *data, int chan, u8 val, u8 reg) reg 291 drivers/hwmon/adm1031.c (*data->chan_select_table)[FAN_CHAN_FROM_REG(reg)][chan ? 0 : 1]; reg 337 drivers/hwmon/adm1031.c u8 reg; reg 354 drivers/hwmon/adm1031.c reg = ret; reg 355 drivers/hwmon/adm1031.c data->conf1 = FAN_CHAN_TO_REG(reg, data->conf1); reg 376 drivers/hwmon/adm1031.c data->conf1 = FAN_CHAN_TO_REG(reg, data->conf1); reg 481 drivers/hwmon/adm1031.c int ret, reg; reg 495 drivers/hwmon/adm1031.c reg = adm1031_read_value(client, ADM1031_REG_PWM); reg 497 drivers/hwmon/adm1031.c nr ? ((data->pwm[nr] << 4) & 0xf0) | (reg & 0xf) reg 498 drivers/hwmon/adm1031.c : (data->pwm[nr] & 0xf) | (reg & 0xf0)); reg 866 drivers/hwmon/adm1031.c u8 reg; reg 883 drivers/hwmon/adm1031.c reg = adm1031_read_value(client, ADM1031_REG_FAN_FILTER); reg 884 drivers/hwmon/adm1031.c reg &= ~ADM1031_UPDATE_RATE_MASK; reg 885 drivers/hwmon/adm1031.c reg |= i << ADM1031_UPDATE_RATE_SHIFT; reg 886 drivers/hwmon/adm1031.c adm1031_write_value(client, ADM1031_REG_FAN_FILTER, reg); reg 81 drivers/hwmon/adm9240.c static inline unsigned int IN_FROM_REG(u8 reg, int n) reg 83 drivers/hwmon/adm9240.c return SCALE(reg, nom_mv[n], 192); reg 100 drivers/hwmon/adm9240.c static inline unsigned int FAN_FROM_REG(u8 reg, u8 div) reg 102 drivers/hwmon/adm9240.c if (!reg) /* error */ reg 105 drivers/hwmon/adm9240.c if (reg == 255) reg 108 drivers/hwmon/adm9240.c return SCALE(1350000, 1, reg * div); reg 118 drivers/hwmon/adm9240.c static inline unsigned int AOUT_FROM_REG(u8 reg) reg 120 drivers/hwmon/adm9240.c return SCALE(reg, 1250, 255); reg 149 drivers/hwmon/adm9240.c u8 reg, old, shift = (nr + 2) * 2; reg 151 drivers/hwmon/adm9240.c reg = i2c_smbus_read_byte_data(client, ADM9240_REG_VID_FAN_DIV); reg 152 drivers/hwmon/adm9240.c old = (reg >> shift) & 3; reg 153 drivers/hwmon/adm9240.c reg &= ~(3 << shift); reg 154 drivers/hwmon/adm9240.c reg |= (fan_div << shift); reg 155 drivers/hwmon/adm9240.c i2c_smbus_write_byte_data(client, ADM9240_REG_VID_FAN_DIV, reg); reg 115 drivers/hwmon/ads7828.c struct regulator *reg; reg 129 drivers/hwmon/ads7828.c reg = devm_regulator_get_optional(dev, "vref"); reg 130 drivers/hwmon/ads7828.c if (!IS_ERR(reg)) { reg 131 drivers/hwmon/ads7828.c vref_uv = regulator_get_voltage(reg); reg 69 drivers/hwmon/ads7871.c static int ads7871_read_reg8(struct spi_device *spi, int reg) reg 72 drivers/hwmon/ads7871.c reg = reg | INST_READ_BM; reg 73 drivers/hwmon/ads7871.c ret = spi_w8r8(spi, reg); reg 77 drivers/hwmon/ads7871.c static int ads7871_read_reg16(struct spi_device *spi, int reg) reg 80 drivers/hwmon/ads7871.c reg = reg | INST_READ_BM | INST_16BIT_BM; reg 81 drivers/hwmon/ads7871.c ret = spi_w8r16(spi, reg); reg 85 drivers/hwmon/ads7871.c static int ads7871_write_reg8(struct spi_device *spi, int reg, u8 val) reg 87 drivers/hwmon/ads7871.c u8 tmp[2] = {reg, val}; reg 39 drivers/hwmon/adt7310.c #define AD7310_COMMAND(reg) (adt7310_reg_table[(reg)] << ADT7310_CMD_REG_OFFSET) reg 41 drivers/hwmon/adt7310.c static int adt7310_spi_read_word(struct device *dev, u8 reg) reg 45 drivers/hwmon/adt7310.c return spi_w8r16be(spi, AD7310_COMMAND(reg) | ADT7310_CMD_READ); reg 48 drivers/hwmon/adt7310.c static int adt7310_spi_write_word(struct device *dev, u8 reg, u16 data) reg 53 drivers/hwmon/adt7310.c buf[0] = AD7310_COMMAND(reg); reg 59 drivers/hwmon/adt7310.c static int adt7310_spi_read_byte(struct device *dev, u8 reg) reg 63 drivers/hwmon/adt7310.c return spi_w8r8(spi, AD7310_COMMAND(reg) | ADT7310_CMD_READ); reg 66 drivers/hwmon/adt7310.c static int adt7310_spi_write_byte(struct device *dev, u8 reg, reg 72 drivers/hwmon/adt7310.c buf[0] = AD7310_COMMAND(reg); reg 15 drivers/hwmon/adt7410.c static int adt7410_i2c_read_word(struct device *dev, u8 reg) reg 17 drivers/hwmon/adt7410.c return i2c_smbus_read_word_swapped(to_i2c_client(dev), reg); reg 20 drivers/hwmon/adt7410.c static int adt7410_i2c_write_word(struct device *dev, u8 reg, u16 data) reg 22 drivers/hwmon/adt7410.c return i2c_smbus_write_word_swapped(to_i2c_client(dev), reg, data); reg 25 drivers/hwmon/adt7410.c static int adt7410_i2c_read_byte(struct device *dev, u8 reg) reg 27 drivers/hwmon/adt7410.c return i2c_smbus_read_byte_data(to_i2c_client(dev), reg); reg 30 drivers/hwmon/adt7410.c static int adt7410_i2c_write_byte(struct device *dev, u8 reg, u8 data) reg 32 drivers/hwmon/adt7410.c return i2c_smbus_write_byte_data(to_i2c_client(dev), reg, data); reg 140 drivers/hwmon/adt7411.c static int adt7411_modify_bit(struct i2c_client *client, u8 reg, u8 bit, reg 148 drivers/hwmon/adt7411.c ret = i2c_smbus_read_byte_data(client, reg); reg 157 drivers/hwmon/adt7411.c ret = i2c_smbus_write_byte_data(client, reg, val); reg 294 drivers/hwmon/adt7411.c int reg, lsb_reg, lsb_shift; reg 316 drivers/hwmon/adt7411.c reg = (attr == hwmon_in_min) reg 319 drivers/hwmon/adt7411.c ret = i2c_smbus_read_byte_data(client, reg); reg 383 drivers/hwmon/adt7411.c int ret, reg, regl, regh; reg 399 drivers/hwmon/adt7411.c reg = (attr == hwmon_temp_min) reg 402 drivers/hwmon/adt7411.c ret = i2c_smbus_read_byte_data(client, reg); reg 434 drivers/hwmon/adt7411.c int reg; reg 441 drivers/hwmon/adt7411.c reg = ADT7411_REG_VDD_LOW; reg 444 drivers/hwmon/adt7411.c reg = ADT7411_REG_VDD_HIGH; reg 450 drivers/hwmon/adt7411.c return i2c_smbus_write_byte_data(client, reg, val); reg 458 drivers/hwmon/adt7411.c int ret, reg; reg 469 drivers/hwmon/adt7411.c reg = ADT7411_REG_IN_LOW(channel); reg 472 drivers/hwmon/adt7411.c reg = ADT7411_REG_IN_HIGH(channel); reg 479 drivers/hwmon/adt7411.c ret = i2c_smbus_write_byte_data(client, reg, val); reg 499 drivers/hwmon/adt7411.c int reg; reg 506 drivers/hwmon/adt7411.c reg = ADT7411_REG_TEMP_LOW(channel); reg 509 drivers/hwmon/adt7411.c reg = ADT7411_REG_TEMP_HIGH(channel); reg 515 drivers/hwmon/adt7411.c return i2c_smbus_write_byte_data(client, reg, val); reg 225 drivers/hwmon/adt7462.c static inline int adt7462_read_word_data(struct i2c_client *client, u8 reg) reg 228 drivers/hwmon/adt7462.c foo = i2c_smbus_read_byte_data(client, reg); reg 229 drivers/hwmon/adt7462.c foo |= ((u16)i2c_smbus_read_byte_data(client, reg + 1) << 8); reg 712 drivers/hwmon/adt7462.c int reg = ADT7462_REG_VOLT(data, i); reg 713 drivers/hwmon/adt7462.c if (!reg) reg 717 drivers/hwmon/adt7462.c reg); reg 746 drivers/hwmon/adt7462.c int reg = ADT7462_REG_VOLT_MAX(data, i); reg 748 drivers/hwmon/adt7462.c (reg ? i2c_smbus_read_byte_data(client, reg) : 0); reg 750 drivers/hwmon/adt7462.c reg = ADT7462_REG_VOLT_MIN(data, i); reg 752 drivers/hwmon/adt7462.c (reg ? i2c_smbus_read_byte_data(client, reg) : 0); reg 980 drivers/hwmon/adt7462.c int reg = attr->index >> ADT7462_ALARM_REG_SHIFT; reg 983 drivers/hwmon/adt7462.c if (data->alarms[reg] & mask) reg 1066 drivers/hwmon/adt7462.c u8 reg; reg 1072 drivers/hwmon/adt7462.c reg = i2c_smbus_read_byte_data(client, ADT7462_REG_CFG2); reg 1074 drivers/hwmon/adt7462.c reg |= ADT7462_FSPD_MASK; reg 1076 drivers/hwmon/adt7462.c reg &= ~ADT7462_FSPD_MASK; reg 1077 drivers/hwmon/adt7462.c data->cfg2 = reg; reg 1078 drivers/hwmon/adt7462.c i2c_smbus_write_byte_data(client, ADT7462_REG_CFG2, reg); reg 174 drivers/hwmon/adt7470.c static inline int adt7470_read_word_data(struct i2c_client *client, u8 reg) reg 177 drivers/hwmon/adt7470.c foo = i2c_smbus_read_byte_data(client, reg); reg 178 drivers/hwmon/adt7470.c foo |= ((u16)i2c_smbus_read_byte_data(client, reg + 1) << 8); reg 182 drivers/hwmon/adt7470.c static inline int adt7470_write_word_data(struct i2c_client *client, u8 reg, reg 185 drivers/hwmon/adt7470.c return i2c_smbus_write_byte_data(client, reg, value & 0xFF) reg 186 drivers/hwmon/adt7470.c || i2c_smbus_write_byte_data(client, reg + 1, value >> 8); reg 317 drivers/hwmon/adt7470.c int reg; reg 328 drivers/hwmon/adt7470.c reg = ADT7470_REG_PWM_CFG(i); reg 329 drivers/hwmon/adt7470.c if (i2c_smbus_read_byte_data(client, reg) & reg_mask) reg 334 drivers/hwmon/adt7470.c reg = ADT7470_REG_PWM_AUTO_TEMP(i); reg 335 drivers/hwmon/adt7470.c cfg = i2c_smbus_read_byte_data(client, reg); reg 650 drivers/hwmon/adt7470.c u8 reg; reg 657 drivers/hwmon/adt7470.c reg = i2c_smbus_read_byte_data(client, ADT7470_REG_CFG); reg 659 drivers/hwmon/adt7470.c reg |= ADT7470_FSPD_MASK; reg 661 drivers/hwmon/adt7470.c reg &= ~ADT7470_FSPD_MASK; reg 662 drivers/hwmon/adt7470.c i2c_smbus_write_byte_data(client, ADT7470_REG_CFG, reg); reg 882 drivers/hwmon/adt7470.c u8 reg; reg 898 drivers/hwmon/adt7470.c reg = i2c_smbus_read_byte_data(client, pwm_auto_reg); reg 900 drivers/hwmon/adt7470.c reg |= pwm_auto_reg_mask; reg 902 drivers/hwmon/adt7470.c reg &= ~pwm_auto_reg_mask; reg 903 drivers/hwmon/adt7470.c i2c_smbus_write_byte_data(client, pwm_auto_reg, reg); reg 940 drivers/hwmon/adt7470.c u8 reg; reg 951 drivers/hwmon/adt7470.c reg = i2c_smbus_read_byte_data(client, pwm_auto_reg); reg 954 drivers/hwmon/adt7470.c reg &= 0xF; reg 955 drivers/hwmon/adt7470.c reg |= (temp << 4) & 0xF0; reg 957 drivers/hwmon/adt7470.c reg &= 0xF0; reg 958 drivers/hwmon/adt7470.c reg |= temp & 0xF; reg 961 drivers/hwmon/adt7470.c i2c_smbus_write_byte_data(client, pwm_auto_reg, reg); reg 1210 drivers/hwmon/adt7470.c int reg = i2c_smbus_read_byte_data(client, ADT7470_REG_CFG); reg 1212 drivers/hwmon/adt7470.c if (reg < 0) { reg 1216 drivers/hwmon/adt7470.c i2c_smbus_write_byte_data(client, ADT7470_REG_CFG, reg | 3); reg 131 drivers/hwmon/adt7475.c #define adt7475_read(reg) i2c_smbus_read_byte_data(client, (reg)) reg 245 drivers/hwmon/adt7475.c static inline int reg2temp(struct adt7475_data *data, u16 reg) reg 248 drivers/hwmon/adt7475.c if (reg >= 512) reg 249 drivers/hwmon/adt7475.c return (reg - 1024) * 250; reg 251 drivers/hwmon/adt7475.c return reg * 250; reg 253 drivers/hwmon/adt7475.c return (reg - 256) * 250; reg 282 drivers/hwmon/adt7475.c static inline int reg2volt(int channel, u16 reg, u8 bypass_attn) reg 287 drivers/hwmon/adt7475.c return DIV_ROUND_CLOSEST(reg * 2250, 1024); reg 288 drivers/hwmon/adt7475.c return DIV_ROUND_CLOSEST(reg * (r[0] + r[1]) * 2250, r[1] * 1024); reg 294 drivers/hwmon/adt7475.c long reg; reg 297 drivers/hwmon/adt7475.c reg = DIV_ROUND_CLOSEST(volt * 1024, 2250); reg 299 drivers/hwmon/adt7475.c reg = DIV_ROUND_CLOSEST(volt * r[1] * 1024, reg 301 drivers/hwmon/adt7475.c return clamp_val(reg, 0, 1023) & (0xff << 2); reg 304 drivers/hwmon/adt7475.c static int adt7475_read_word(struct i2c_client *client, int reg) reg 308 drivers/hwmon/adt7475.c val1 = i2c_smbus_read_byte_data(client, reg); reg 311 drivers/hwmon/adt7475.c val2 = i2c_smbus_read_byte_data(client, reg + 1); reg 318 drivers/hwmon/adt7475.c static void adt7475_write_word(struct i2c_client *client, int reg, u16 val) reg 320 drivers/hwmon/adt7475.c i2c_smbus_write_byte_data(client, reg + 1, val >> 8); reg 321 drivers/hwmon/adt7475.c i2c_smbus_write_byte_data(client, reg, val & 0xFF); reg 353 drivers/hwmon/adt7475.c unsigned char reg; reg 366 drivers/hwmon/adt7475.c reg = VOLTAGE_MIN_REG(sattr->index); reg 368 drivers/hwmon/adt7475.c reg = VOLTAGE_MAX_REG(sattr->index); reg 371 drivers/hwmon/adt7475.c reg = REG_VTT_MIN; reg 373 drivers/hwmon/adt7475.c reg = REG_VTT_MAX; reg 376 drivers/hwmon/adt7475.c i2c_smbus_write_byte_data(client, reg, reg 447 drivers/hwmon/adt7475.c unsigned char reg = 0; reg 509 drivers/hwmon/adt7475.c reg = TEMP_MIN_REG(sattr->index); reg 512 drivers/hwmon/adt7475.c reg = TEMP_MAX_REG(sattr->index); reg 515 drivers/hwmon/adt7475.c reg = TEMP_OFFSET_REG(sattr->index); reg 518 drivers/hwmon/adt7475.c reg = TEMP_TMIN_REG(sattr->index); reg 521 drivers/hwmon/adt7475.c reg = TEMP_THERM_REG(sattr->index); reg 525 drivers/hwmon/adt7475.c reg = REG_REMOTE1_HYSTERSIS; reg 527 drivers/hwmon/adt7475.c reg = REG_REMOTE2_HYSTERSIS; reg 532 drivers/hwmon/adt7475.c i2c_smbus_write_byte_data(client, reg, out); reg 576 drivers/hwmon/adt7475.c unsigned char reg; reg 585 drivers/hwmon/adt7475.c reg = REG_ENHANCE_ACOUSTICS1; reg 590 drivers/hwmon/adt7475.c reg = REG_ENHANCE_ACOUSTICS2; reg 596 drivers/hwmon/adt7475.c reg = REG_ENHANCE_ACOUSTICS2; reg 613 drivers/hwmon/adt7475.c i2c_smbus_write_byte_data(client, reg, data->enh_acoustics[idx]); reg 775 drivers/hwmon/adt7475.c unsigned char reg = 0; reg 798 drivers/hwmon/adt7475.c reg = PWM_REG(sattr->index); reg 802 drivers/hwmon/adt7475.c reg = PWM_MIN_REG(sattr->index); reg 806 drivers/hwmon/adt7475.c reg = PWM_MAX_REG(sattr->index); reg 811 drivers/hwmon/adt7475.c i2c_smbus_write_byte_data(client, reg, reg 72 drivers/hwmon/adt7x10.c static int adt7x10_read_byte(struct device *dev, u8 reg) reg 75 drivers/hwmon/adt7x10.c return d->ops->read_byte(dev, reg); reg 78 drivers/hwmon/adt7x10.c static int adt7x10_write_byte(struct device *dev, u8 reg, u8 data) reg 81 drivers/hwmon/adt7x10.c return d->ops->write_byte(dev, reg, data); reg 84 drivers/hwmon/adt7x10.c static int adt7x10_read_word(struct device *dev, u8 reg) reg 87 drivers/hwmon/adt7x10.c return d->ops->read_word(dev, reg); reg 90 drivers/hwmon/adt7x10.c static int adt7x10_write_word(struct device *dev, u8 reg, u16 data) reg 93 drivers/hwmon/adt7x10.c return d->ops->write_word(dev, reg, data); reg 204 drivers/hwmon/adt7x10.c static int ADT7X10_REG_TO_TEMP(struct adt7x10_data *data, s16 reg) reg 208 drivers/hwmon/adt7x10.c reg &= ADT7X10_T13_VALUE_MASK; reg 213 drivers/hwmon/adt7x10.c return DIV_ROUND_CLOSEST(reg * 1000, 128); reg 21 drivers/hwmon/adt7x10.h int (*read_byte)(struct device *, u8 reg); reg 22 drivers/hwmon/adt7x10.h int (*write_byte)(struct device *, u8 reg, u8 data); reg 23 drivers/hwmon/adt7x10.h int (*read_word)(struct device *, u8 reg); reg 24 drivers/hwmon/adt7x10.h int (*write_word)(struct device *, u8 reg, u16 data); reg 169 drivers/hwmon/amc6821.c u8 reg; reg 210 drivers/hwmon/amc6821.c reg = i2c_smbus_read_byte_data(client, reg 212 drivers/hwmon/amc6821.c data->temp1_auto_point_temp[1] = (reg & 0xF8) >> 1; reg 213 drivers/hwmon/amc6821.c reg &= 0x07; reg 214 drivers/hwmon/amc6821.c reg = 0x20 >> reg; reg 215 drivers/hwmon/amc6821.c if (reg > 0) reg 219 drivers/hwmon/amc6821.c data->pwm1_auto_point_pwm[1]) / reg; reg 223 drivers/hwmon/amc6821.c reg = i2c_smbus_read_byte_data(client, reg 225 drivers/hwmon/amc6821.c data->temp2_auto_point_temp[1] = (reg & 0xF8) >> 1; reg 226 drivers/hwmon/amc6821.c reg &= 0x07; reg 227 drivers/hwmon/amc6821.c reg = 0x20 >> reg; reg 228 drivers/hwmon/amc6821.c if (reg > 0) reg 232 drivers/hwmon/amc6821.c data->pwm1_auto_point_pwm[1]) / reg; reg 236 drivers/hwmon/amc6821.c reg = i2c_smbus_read_byte_data(client, AMC6821_REG_CONF1); reg 237 drivers/hwmon/amc6821.c reg = (reg >> 5) & 0x3; reg 238 drivers/hwmon/amc6821.c switch (reg) { reg 462 drivers/hwmon/amc6821.c u8 reg, reg 476 drivers/hwmon/amc6821.c reg, tmp)) { reg 492 drivers/hwmon/amc6821.c u8 reg; reg 502 drivers/hwmon/amc6821.c reg = AMC6821_REG_LTEMP_FAN_CTRL; reg 506 drivers/hwmon/amc6821.c reg = AMC6821_REG_RTEMP_FAN_CTRL; reg 546 drivers/hwmon/amc6821.c if (set_slope_register(client, reg, dpwm, ptemp)) reg 108 drivers/hwmon/asb100.c static unsigned IN_FROM_REG(u8 reg) reg 110 drivers/hwmon/asb100.c return reg * 16; reg 143 drivers/hwmon/asb100.c static int TEMP_FROM_REG(u8 reg) reg 145 drivers/hwmon/asb100.c return (s8)reg * 1000; reg 158 drivers/hwmon/asb100.c static int ASB100_PWM_FROM_REG(u8 reg) reg 160 drivers/hwmon/asb100.c return reg * 16; reg 205 drivers/hwmon/asb100.c static int asb100_read_value(struct i2c_client *client, u16 reg); reg 206 drivers/hwmon/asb100.c static void asb100_write_value(struct i2c_client *client, u16 reg, u16 val); reg 235 drivers/hwmon/asb100.c #define show_in_reg(reg) \ reg 236 drivers/hwmon/asb100.c static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ reg 241 drivers/hwmon/asb100.c return sprintf(buf, "%d\n", IN_FROM_REG(data->reg[nr])); \ reg 248 drivers/hwmon/asb100.c #define set_in_reg(REG, reg) \ reg 249 drivers/hwmon/asb100.c static ssize_t set_in_##reg(struct device *dev, struct device_attribute *attr, \ reg 260 drivers/hwmon/asb100.c data->in_##reg[nr] = IN_TO_REG(val); \ reg 262 drivers/hwmon/asb100.c data->in_##reg[nr]); \ reg 346 drivers/hwmon/asb100.c int reg; reg 362 drivers/hwmon/asb100.c reg = asb100_read_value(client, ASB100_REG_VID_FANDIV); reg 363 drivers/hwmon/asb100.c reg = (reg & 0xcf) | (data->fan_div[0] << 4); reg 364 drivers/hwmon/asb100.c asb100_write_value(client, ASB100_REG_VID_FANDIV, reg); reg 368 drivers/hwmon/asb100.c reg = asb100_read_value(client, ASB100_REG_VID_FANDIV); reg 369 drivers/hwmon/asb100.c reg = (reg & 0x3f) | (data->fan_div[1] << 6); reg 370 drivers/hwmon/asb100.c asb100_write_value(client, ASB100_REG_VID_FANDIV, reg); reg 374 drivers/hwmon/asb100.c reg = asb100_read_value(client, ASB100_REG_PIN); reg 375 drivers/hwmon/asb100.c reg = (reg & 0x3f) | (data->fan_div[2] << 6); reg 376 drivers/hwmon/asb100.c asb100_write_value(client, ASB100_REG_PIN, reg); reg 402 drivers/hwmon/asb100.c static int sprintf_temp_from_reg(u16 reg, char *buf, int nr) reg 408 drivers/hwmon/asb100.c ret = sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(reg)); reg 411 drivers/hwmon/asb100.c ret = sprintf(buf, "%d\n", TEMP_FROM_REG(reg)); reg 417 drivers/hwmon/asb100.c #define show_temp_reg(reg) \ reg 418 drivers/hwmon/asb100.c static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ reg 423 drivers/hwmon/asb100.c return sprintf_temp_from_reg(data->reg[nr], buf, nr); \ reg 430 drivers/hwmon/asb100.c #define set_temp_reg(REG, reg) \ reg 431 drivers/hwmon/asb100.c static ssize_t set_##reg(struct device *dev, struct device_attribute *attr, \ reg 444 drivers/hwmon/asb100.c data->reg[nr] = LM75_TEMP_TO_REG(val); \ reg 447 drivers/hwmon/asb100.c data->reg[nr] = TEMP_TO_REG(val); \ reg 451 drivers/hwmon/asb100.c data->reg[nr]); \ reg 844 drivers/hwmon/asb100.c static int asb100_read_value(struct i2c_client *client, u16 reg) reg 852 drivers/hwmon/asb100.c bank = (reg >> 8) & 0x0f; reg 858 drivers/hwmon/asb100.c res = i2c_smbus_read_byte_data(client, reg & 0xff); reg 864 drivers/hwmon/asb100.c switch (reg & 0xff) { reg 889 drivers/hwmon/asb100.c static void asb100_write_value(struct i2c_client *client, u16 reg, u16 value) reg 897 drivers/hwmon/asb100.c bank = (reg >> 8) & 0x0f; reg 903 drivers/hwmon/asb100.c i2c_smbus_write_byte_data(client, reg & 0xff, value & 0xff); reg 909 drivers/hwmon/asb100.c switch (reg & 0xff) { reg 88 drivers/hwmon/asc7621.c u8 reg[LAST_REGISTER + 1]; reg 121 drivers/hwmon/asc7621.c static inline u8 read_byte(struct i2c_client *client, u8 reg) reg 123 drivers/hwmon/asc7621.c int res = i2c_smbus_read_byte_data(client, reg); reg 126 drivers/hwmon/asc7621.c "Unable to read from register 0x%02x.\n", reg); reg 132 drivers/hwmon/asc7621.c static inline int write_byte(struct i2c_client *client, u8 reg, u8 data) reg 134 drivers/hwmon/asc7621.c int res = i2c_smbus_write_byte_data(client, reg, data); reg 138 drivers/hwmon/asc7621.c data, reg); reg 169 drivers/hwmon/asc7621.c return sprintf(buf, "%u\n", data->reg[param->msb[0]]); reg 184 drivers/hwmon/asc7621.c data->reg[param->msb[0]] = reqval; reg 199 drivers/hwmon/asc7621.c (data->reg[param->msb[0]] >> param-> reg 221 drivers/hwmon/asc7621.c data->reg[param->msb[0]] = reqval; reg 240 drivers/hwmon/asc7621.c regval = (data->reg[param->msb[0]] << 8) | data->reg[param->lsb[0]]; reg 267 drivers/hwmon/asc7621.c data->reg[param->msb[0]] = (reqval >> 8) & 0xff; reg 268 drivers/hwmon/asc7621.c data->reg[param->lsb[0]] = reqval & 0xff; reg 269 drivers/hwmon/asc7621.c write_byte(client, param->msb[0], data->reg[param->msb[0]]); reg 270 drivers/hwmon/asc7621.c write_byte(client, param->lsb[0], data->reg[param->lsb[0]]); reg 302 drivers/hwmon/asc7621.c regval = (data->reg[param->msb[0]] << 8) | (data->reg[param->lsb[0]]); reg 319 drivers/hwmon/asc7621.c ((data->reg[param->msb[0]] * reg 340 drivers/hwmon/asc7621.c data->reg[param->msb[0]] = reqval; reg 352 drivers/hwmon/asc7621.c return sprintf(buf, "%d\n", ((s8) data->reg[param->msb[0]]) * 1000); reg 371 drivers/hwmon/asc7621.c data->reg[param->msb[0]] = temp; reg 392 drivers/hwmon/asc7621.c msb = data->reg[param->msb[0]]; reg 393 drivers/hwmon/asc7621.c lsb = (data->reg[param->lsb[0]] >> 6) & 0x03; reg 405 drivers/hwmon/asc7621.c u8 regval = data->reg[param->msb[0]]; reg 429 drivers/hwmon/asc7621.c data->reg[param->msb[0]] = temp; reg 455 drivers/hwmon/asc7621.c auto_point1 = ((s8) data->reg[param->msb[1]]) * 1000; reg 457 drivers/hwmon/asc7621.c ((data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]); reg 478 drivers/hwmon/asc7621.c auto_point1 = data->reg[param->msb[1]] * 1000; reg 491 drivers/hwmon/asc7621.c data->reg[param->msb[0]] = newval; reg 508 drivers/hwmon/asc7621.c config = (data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]; reg 509 drivers/hwmon/asc7621.c altbit = (data->reg[param->msb[1]] >> param->shift[1]) & param->mask[1]; reg 550 drivers/hwmon/asc7621.c data->reg[param->msb[0]] = newval; reg 563 drivers/hwmon/asc7621.c config = (data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]; reg 564 drivers/hwmon/asc7621.c altbit = (data->reg[param->msb[1]] >> param->shift[1]) & param->mask[1]; reg 565 drivers/hwmon/asc7621.c minoff = (data->reg[param->msb[2]] >> param->shift[2]) & param->mask[2]; reg 626 drivers/hwmon/asc7621.c data->reg[param->msb[0]] = newval; reg 633 drivers/hwmon/asc7621.c data->reg[param->msb[2]] = newval; reg 650 drivers/hwmon/asc7621.c (data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]; reg 683 drivers/hwmon/asc7621.c data->reg[param->msb[0]] = newval; reg 698 drivers/hwmon/asc7621.c (data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]; reg 732 drivers/hwmon/asc7621.c data->reg[param->msb[0]] = newval; reg 747 drivers/hwmon/asc7621.c (data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]; reg 780 drivers/hwmon/asc7621.c data->reg[param->msb[0]] = newval; reg 1014 drivers/hwmon/asc7621.c data->reg[i] = reg 1028 drivers/hwmon/asc7621.c data->reg[i] = reg 346 drivers/hwmon/aspeed-pwm-tacho.c static int regmap_aspeed_pwm_tacho_reg_write(void *context, unsigned int reg, reg 351 drivers/hwmon/aspeed-pwm-tacho.c writel(val, regs + reg); reg 355 drivers/hwmon/aspeed-pwm-tacho.c static int regmap_aspeed_pwm_tacho_reg_read(void *context, unsigned int reg, reg 360 drivers/hwmon/aspeed-pwm-tacho.c *val = readl(regs + reg); reg 46 drivers/hwmon/atxp1.c } reg; reg 60 drivers/hwmon/atxp1.c data->reg.vid = i2c_smbus_read_byte_data(client, ATXP1_VID); reg 61 drivers/hwmon/atxp1.c data->reg.cpu_vid = i2c_smbus_read_byte_data(client, reg 63 drivers/hwmon/atxp1.c data->reg.gpio1 = i2c_smbus_read_byte_data(client, ATXP1_GPIO1); reg 64 drivers/hwmon/atxp1.c data->reg.gpio2 = i2c_smbus_read_byte_data(client, ATXP1_GPIO2); reg 83 drivers/hwmon/atxp1.c size = sprintf(buf, "%d\n", vid_from_reg(data->reg.vid & ATXP1_VIDMASK, reg 117 drivers/hwmon/atxp1.c if (data->reg.vid & ATXP1_VIDENA) reg 118 drivers/hwmon/atxp1.c cvid = data->reg.vid & ATXP1_VIDMASK; reg 120 drivers/hwmon/atxp1.c cvid = data->reg.cpu_vid; reg 159 drivers/hwmon/atxp1.c size = sprintf(buf, "0x%02x\n", data->reg.gpio1 & ATXP1_GPIO1MASK); reg 178 drivers/hwmon/atxp1.c if (value != (data->reg.gpio1 & ATXP1_GPIO1MASK)) { reg 204 drivers/hwmon/atxp1.c size = sprintf(buf, "0x%02x\n", data->reg.gpio2); reg 222 drivers/hwmon/atxp1.c if (value != data->reg.gpio2) { reg 262 drivers/hwmon/dme1737.c static inline int IN_FROM_REG(int reg, int nominal, int res) reg 264 drivers/hwmon/dme1737.c return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2)); reg 279 drivers/hwmon/dme1737.c static inline int TEMP_FROM_REG(int reg, int res) reg 281 drivers/hwmon/dme1737.c return (reg * 1000) >> (res - 8); reg 295 drivers/hwmon/dme1737.c static inline int TEMP_RANGE_FROM_REG(int reg) reg 297 drivers/hwmon/dme1737.c return TEMP_RANGE[(reg >> 4) & 0x0f]; reg 300 drivers/hwmon/dme1737.c static int TEMP_RANGE_TO_REG(long val, int reg) reg 309 drivers/hwmon/dme1737.c return (reg & 0x0f) | (i << 4); reg 318 drivers/hwmon/dme1737.c static inline int TEMP_HYST_FROM_REG(int reg, int ix) reg 320 drivers/hwmon/dme1737.c return (((ix == 1) ? reg : reg >> 4) & 0x0f) * 1000; reg 323 drivers/hwmon/dme1737.c static inline int TEMP_HYST_TO_REG(int temp, long hyst, int ix, int reg) reg 328 drivers/hwmon/dme1737.c return (ix == 1) ? (reg & 0xf0) | hyst : (reg & 0x0f) | (hyst << 4); reg 332 drivers/hwmon/dme1737.c static inline int FAN_FROM_REG(int reg, int tpc) reg 335 drivers/hwmon/dme1737.c return tpc * reg; reg 337 drivers/hwmon/dme1737.c return (reg == 0 || reg == 0xffff) ? 0 : 90000 * 60 / reg; reg 355 drivers/hwmon/dme1737.c static inline int FAN_TPC_FROM_REG(int reg) reg 357 drivers/hwmon/dme1737.c return (reg & 0x20) ? 0 : 60 >> (reg & 0x03); reg 365 drivers/hwmon/dme1737.c static inline int FAN_TYPE_FROM_REG(int reg) reg 367 drivers/hwmon/dme1737.c int edge = (reg >> 1) & 0x03; reg 372 drivers/hwmon/dme1737.c static inline int FAN_TYPE_TO_REG(long val, int reg) reg 376 drivers/hwmon/dme1737.c return (reg & 0xf9) | (edge << 1); reg 383 drivers/hwmon/dme1737.c static int FAN_MAX_FROM_REG(int reg) reg 388 drivers/hwmon/dme1737.c if (reg == FAN_MAX[i]) reg 419 drivers/hwmon/dme1737.c static inline int PWM_EN_FROM_REG(int reg) reg 423 drivers/hwmon/dme1737.c return en[(reg >> 5) & 0x07]; reg 426 drivers/hwmon/dme1737.c static inline int PWM_EN_TO_REG(int val, int reg) reg 430 drivers/hwmon/dme1737.c return (reg & 0x1f) | ((en & 0x07) << 5); reg 446 drivers/hwmon/dme1737.c static inline int PWM_ACZ_FROM_REG(int reg) reg 450 drivers/hwmon/dme1737.c return acz[(reg >> 5) & 0x07]; reg 453 drivers/hwmon/dme1737.c static inline int PWM_ACZ_TO_REG(long val, int reg) reg 457 drivers/hwmon/dme1737.c return (reg & 0x1f) | ((acz & 0x07) << 5); reg 464 drivers/hwmon/dme1737.c static inline int PWM_FREQ_FROM_REG(int reg) reg 466 drivers/hwmon/dme1737.c return PWM_FREQ[reg & 0x0f]; reg 469 drivers/hwmon/dme1737.c static int PWM_FREQ_TO_REG(long val, int reg) reg 485 drivers/hwmon/dme1737.c return (reg & 0xf0) | i; reg 496 drivers/hwmon/dme1737.c static inline int PWM_RR_FROM_REG(int reg, int ix) reg 498 drivers/hwmon/dme1737.c int rr = (ix == 1) ? reg >> 4 : reg; reg 503 drivers/hwmon/dme1737.c static int PWM_RR_TO_REG(long val, int ix, int reg) reg 512 drivers/hwmon/dme1737.c return (ix == 1) ? (reg & 0x8f) | (i << 4) : (reg & 0xf8) | i; reg 516 drivers/hwmon/dme1737.c static inline int PWM_RR_EN_FROM_REG(int reg, int ix) reg 518 drivers/hwmon/dme1737.c return PWM_RR_FROM_REG(reg, ix) ? 1 : 0; reg 521 drivers/hwmon/dme1737.c static inline int PWM_RR_EN_TO_REG(long val, int ix, int reg) reg 525 drivers/hwmon/dme1737.c return val ? reg | en : reg & ~en; reg 533 drivers/hwmon/dme1737.c static inline int PWM_OFF_FROM_REG(int reg, int ix) reg 535 drivers/hwmon/dme1737.c return (reg >> (ix + 5)) & 0x01; reg 538 drivers/hwmon/dme1737.c static inline int PWM_OFF_TO_REG(int val, int ix, int reg) reg 540 drivers/hwmon/dme1737.c return (reg & ~(1 << (ix + 5))) | ((val & 0x01) << (ix + 5)); reg 552 drivers/hwmon/dme1737.c static u8 dme1737_read(const struct dme1737_data *data, u8 reg) reg 558 drivers/hwmon/dme1737.c val = i2c_smbus_read_byte_data(client, reg); reg 563 drivers/hwmon/dme1737.c reg, DO_REPORT); reg 566 drivers/hwmon/dme1737.c outb(reg, data->addr); reg 573 drivers/hwmon/dme1737.c static s32 dme1737_write(const struct dme1737_data *data, u8 reg, u8 val) reg 579 drivers/hwmon/dme1737.c res = i2c_smbus_write_byte_data(client, reg, val); reg 584 drivers/hwmon/dme1737.c reg, DO_REPORT); reg 587 drivers/hwmon/dme1737.c outb(reg, data->addr); reg 1017 drivers/hwmon/dme1737.c u8 reg; reg 1031 drivers/hwmon/dme1737.c reg = dme1737_read(data, DME1737_REG_ZONE_HYST(ix == 2)); reg 1032 drivers/hwmon/dme1737.c data->zone_hyst[ix == 2] = TEMP_HYST_TO_REG(temp, val, ix, reg); reg 1051 drivers/hwmon/dme1737.c reg = dme1737_read(data, DME1737_REG_PWM_FREQ(ix)); reg 1052 drivers/hwmon/dme1737.c data->pwm_freq[ix] = TEMP_RANGE_TO_REG(val - temp, reg); reg 2025 drivers/hwmon/dme1737.c static inline int dme1737_sio_inb(int sio_cip, int reg) reg 2027 drivers/hwmon/dme1737.c outb(reg, sio_cip); reg 2031 drivers/hwmon/dme1737.c static inline void dme1737_sio_outb(int sio_cip, int reg, int val) reg 2033 drivers/hwmon/dme1737.c outb(reg, sio_cip); reg 2237 drivers/hwmon/dme1737.c u8 reg; reg 2325 drivers/hwmon/dme1737.c reg = dme1737_read(data, DME1737_REG_TACH_PWM); reg 2327 drivers/hwmon/dme1737.c if (client && reg != 0xa4) { /* I2C chip */ reg 2330 drivers/hwmon/dme1737.c (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1, reg 2331 drivers/hwmon/dme1737.c ((reg >> 4) & 0x03) + 1, ((reg >> 6) & 0x03) + 1, reg 2333 drivers/hwmon/dme1737.c } else if (!client && reg != 0x24) { /* ISA chip */ reg 2336 drivers/hwmon/dme1737.c (reg & 0x03) + 1, ((reg >> 2) & 0x03) + 1, reg 2337 drivers/hwmon/dme1737.c ((reg >> 4) & 0x03) + 1, DO_REPORT); reg 2384 drivers/hwmon/dme1737.c int err = 0, reg; reg 2393 drivers/hwmon/dme1737.c reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20); reg 2394 drivers/hwmon/dme1737.c if (!(reg == DME1737_ID_1 || reg == DME1737_ID_2 || reg 2395 drivers/hwmon/dme1737.c reg == SCH5027_ID)) { reg 2545 drivers/hwmon/dme1737.c int err = 0, reg; reg 2554 drivers/hwmon/dme1737.c reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20); reg 2555 drivers/hwmon/dme1737.c if (!(reg == SCH3112_ID || reg == SCH3114_ID || reg == SCH3116_ID || reg 2556 drivers/hwmon/dme1737.c reg == SCH5127_ID)) { reg 123 drivers/hwmon/ds1621.c static inline int DS1621_TEMP_FROM_REG(u16 reg) reg 125 drivers/hwmon/ds1621.c return DIV_ROUND_CLOSEST(((s16)reg / 16) * 625, 10); reg 360 drivers/hwmon/emc1403.c static bool emc1403_regmap_is_volatile(struct device *dev, unsigned int reg) reg 362 drivers/hwmon/emc1403.c switch (reg) { reg 61 drivers/hwmon/emc6w201.c static u16 emc6w201_read16(struct i2c_client *client, u8 reg) reg 65 drivers/hwmon/emc6w201.c lsb = i2c_smbus_read_byte_data(client, reg); reg 66 drivers/hwmon/emc6w201.c msb = i2c_smbus_read_byte_data(client, reg + 1); reg 69 drivers/hwmon/emc6w201.c 16, "read", reg); reg 80 drivers/hwmon/emc6w201.c static int emc6w201_write16(struct i2c_client *client, u8 reg, u16 val) reg 84 drivers/hwmon/emc6w201.c err = i2c_smbus_write_byte_data(client, reg, val & 0xff); reg 86 drivers/hwmon/emc6w201.c err = i2c_smbus_write_byte_data(client, reg + 1, val >> 8); reg 89 drivers/hwmon/emc6w201.c 16, "write", reg); reg 95 drivers/hwmon/emc6w201.c static u8 emc6w201_read8(struct i2c_client *client, u8 reg) reg 99 drivers/hwmon/emc6w201.c val = i2c_smbus_read_byte_data(client, reg); reg 102 drivers/hwmon/emc6w201.c 8, "read", reg); reg 110 drivers/hwmon/emc6w201.c static int emc6w201_write8(struct i2c_client *client, u8 reg, u8 val) reg 114 drivers/hwmon/emc6w201.c err = i2c_smbus_write_byte_data(client, reg, val); reg 117 drivers/hwmon/emc6w201.c 8, "write", reg); reg 199 drivers/hwmon/emc6w201.c u8 reg; reg 207 drivers/hwmon/emc6w201.c reg = (sf == min) ? EMC6W201_REG_IN_LOW(nr) reg 212 drivers/hwmon/emc6w201.c err = emc6w201_write8(client, reg, data->in[sf][nr]); reg 238 drivers/hwmon/emc6w201.c u8 reg; reg 246 drivers/hwmon/emc6w201.c reg = (sf == min) ? EMC6W201_REG_TEMP_LOW(nr) reg 251 drivers/hwmon/emc6w201.c err = emc6w201_write8(client, reg, data->temp[sf][nr]); reg 62 drivers/hwmon/f71805f.c superio_inb(int base, int reg) reg 64 drivers/hwmon/f71805f.c outb(reg, base); reg 69 drivers/hwmon/f71805f.c superio_inw(int base, int reg) reg 72 drivers/hwmon/f71805f.c outb(reg++, base); reg 74 drivers/hwmon/f71805f.c outb(reg, base); reg 196 drivers/hwmon/f71805f.c static inline long in_from_reg(u8 reg) reg 198 drivers/hwmon/f71805f.c return reg * 8; reg 212 drivers/hwmon/f71805f.c static inline long in0_from_reg(u8 reg) reg 214 drivers/hwmon/f71805f.c return reg * 16; reg 227 drivers/hwmon/f71805f.c static inline long fan_from_reg(u16 reg) reg 229 drivers/hwmon/f71805f.c reg &= 0xfff; reg 230 drivers/hwmon/f71805f.c if (!reg || reg == 0xfff) reg 232 drivers/hwmon/f71805f.c return 1500000 / reg; reg 247 drivers/hwmon/f71805f.c static inline unsigned long pwm_freq_from_reg(u8 reg) reg 249 drivers/hwmon/f71805f.c unsigned long clock = (reg & 0x80) ? 48000000UL : 1000000UL; reg 251 drivers/hwmon/f71805f.c reg &= 0x7f; reg 252 drivers/hwmon/f71805f.c if (reg == 0) reg 253 drivers/hwmon/f71805f.c reg++; reg 254 drivers/hwmon/f71805f.c return clock / (reg << 8); reg 269 drivers/hwmon/f71805f.c static inline int pwm_mode_from_reg(u8 reg) reg 271 drivers/hwmon/f71805f.c return !(reg & FAN_CTRL_DC_MODE); reg 274 drivers/hwmon/f71805f.c static inline long temp_from_reg(u8 reg) reg 276 drivers/hwmon/f71805f.c return reg * 1000; reg 293 drivers/hwmon/f71805f.c static u8 f71805f_read8(struct f71805f_data *data, u8 reg) reg 295 drivers/hwmon/f71805f.c outb(reg, data->addr + ADDR_REG_OFFSET); reg 300 drivers/hwmon/f71805f.c static void f71805f_write8(struct f71805f_data *data, u8 reg, u8 val) reg 302 drivers/hwmon/f71805f.c outb(reg, data->addr + ADDR_REG_OFFSET); reg 311 drivers/hwmon/f71805f.c static u16 f71805f_read16(struct f71805f_data *data, u8 reg) reg 315 drivers/hwmon/f71805f.c outb(reg, data->addr + ADDR_REG_OFFSET); reg 317 drivers/hwmon/f71805f.c outb(++reg, data->addr + ADDR_REG_OFFSET); reg 324 drivers/hwmon/f71805f.c static void f71805f_write16(struct f71805f_data *data, u8 reg, u16 val) reg 326 drivers/hwmon/f71805f.c outb(reg, data->addr + ADDR_REG_OFFSET); reg 328 drivers/hwmon/f71805f.c outb(++reg, data->addr + ADDR_REG_OFFSET); reg 720 drivers/hwmon/f71805f.c u8 reg; reg 738 drivers/hwmon/f71805f.c reg = f71805f_read8(data, F71805F_REG_FAN_CTRL(nr)) reg 742 drivers/hwmon/f71805f.c reg |= FAN_CTRL_MODE_MANUAL; reg 745 drivers/hwmon/f71805f.c reg |= FAN_CTRL_MODE_TEMPERATURE; reg 748 drivers/hwmon/f71805f.c reg |= FAN_CTRL_MODE_SPEED; reg 751 drivers/hwmon/f71805f.c data->fan_ctrl[nr] = reg; reg 752 drivers/hwmon/f71805f.c f71805f_write8(data, F71805F_REG_FAN_CTRL(nr), reg); reg 1341 drivers/hwmon/f71805f.c u8 reg; reg 1344 drivers/hwmon/f71805f.c reg = f71805f_read8(data, F71805F_REG_START); reg 1345 drivers/hwmon/f71805f.c if ((reg & 0x41) != 0x01) { reg 1347 drivers/hwmon/f71805f.c f71805f_write8(data, F71805F_REG_START, (reg | 0x01) & ~0x40); reg 239 drivers/hwmon/f71882fg.c static inline int superio_inb(int base, int reg); reg 240 drivers/hwmon/f71882fg.c static inline int superio_inw(int base, int reg); reg 1104 drivers/hwmon/f71882fg.c static inline int superio_inb(int base, int reg) reg 1106 drivers/hwmon/f71882fg.c outb(reg, base); reg 1110 drivers/hwmon/f71882fg.c static int superio_inw(int base, int reg) reg 1113 drivers/hwmon/f71882fg.c val = superio_inb(base, reg) << 8; reg 1114 drivers/hwmon/f71882fg.c val |= superio_inb(base, reg + 1); reg 1145 drivers/hwmon/f71882fg.c static inline int fan_from_reg(u16 reg) reg 1147 drivers/hwmon/f71882fg.c return reg ? (1500000 / reg) : 0; reg 1155 drivers/hwmon/f71882fg.c static u8 f71882fg_read8(struct f71882fg_data *data, u8 reg) reg 1159 drivers/hwmon/f71882fg.c outb(reg, data->addr + ADDR_REG_OFFSET); reg 1165 drivers/hwmon/f71882fg.c static u16 f71882fg_read16(struct f71882fg_data *data, u8 reg) reg 1169 drivers/hwmon/f71882fg.c val = f71882fg_read8(data, reg) << 8; reg 1170 drivers/hwmon/f71882fg.c val |= f71882fg_read8(data, reg + 1); reg 1175 drivers/hwmon/f71882fg.c static void f71882fg_write8(struct f71882fg_data *data, u8 reg, u8 val) reg 1177 drivers/hwmon/f71882fg.c outb(reg, data->addr + ADDR_REG_OFFSET); reg 1181 drivers/hwmon/f71882fg.c static void f71882fg_write16(struct f71882fg_data *data, u8 reg, u16 val) reg 1183 drivers/hwmon/f71882fg.c f71882fg_write8(data, reg, val >> 8); reg 1184 drivers/hwmon/f71882fg.c f71882fg_write8(data, reg + 1, val & 0xff); reg 1200 drivers/hwmon/f71882fg.c int nr, reg, point; reg 1242 drivers/hwmon/f71882fg.c reg = f71882fg_read8(data, F71882FG_REG_TEMP_TYPE); reg 1243 drivers/hwmon/f71882fg.c data->temp_type[1] = (reg & 0x02) ? 2 : 4; reg 1244 drivers/hwmon/f71882fg.c data->temp_type[2] = (reg & 0x04) ? 2 : 4; reg 1245 drivers/hwmon/f71882fg.c data->temp_type[3] = (reg & 0x08) ? 2 : 4; reg 1641 drivers/hwmon/f71882fg.c u8 reg; reg 1658 drivers/hwmon/f71882fg.c reg = f71882fg_read8(data, F71882FG_REG_TEMP_HYST(nr / 2)); reg 1660 drivers/hwmon/f71882fg.c reg = (reg & 0x0f) | (val << 4); reg 1662 drivers/hwmon/f71882fg.c reg = (reg & 0xf0) | val; reg 1663 drivers/hwmon/f71882fg.c f71882fg_write8(data, F71882FG_REG_TEMP_HYST(nr / 2), reg); reg 1664 drivers/hwmon/f71882fg.c data->temp_hyst[nr / 2] = reg; reg 2043 drivers/hwmon/f71882fg.c u8 reg; reg 2059 drivers/hwmon/f71882fg.c reg = f71882fg_read8(data, F71882FG_REG_FAN_HYST(nr / 2)); reg 2061 drivers/hwmon/f71882fg.c reg = (reg & 0x0f) | (val << 4); reg 2063 drivers/hwmon/f71882fg.c reg = (reg & 0xf0) | val; reg 2065 drivers/hwmon/f71882fg.c f71882fg_write8(data, F71882FG_REG_FAN_HYST(nr / 2), reg); reg 2066 drivers/hwmon/f71882fg.c data->pwm_auto_point_hyst[nr / 2] = reg; reg 2337 drivers/hwmon/f71882fg.c u8 start_reg, reg; reg 2449 drivers/hwmon/f71882fg.c reg = f71882fg_read8(data, F71882FG_REG_FAN_FAULT_T); reg 2450 drivers/hwmon/f71882fg.c if (reg & F71882FG_FAN_NEG_TEMP_EN) reg 2453 drivers/hwmon/f71882fg.c reg &= ~F71882FG_FAN_PROG_SEL; reg 2454 drivers/hwmon/f71882fg.c f71882fg_write8(data, F71882FG_REG_FAN_FAULT_T, reg); reg 140 drivers/hwmon/f75375s.c static inline int f75375_read8(struct i2c_client *client, u8 reg) reg 142 drivers/hwmon/f75375s.c return i2c_smbus_read_byte_data(client, reg); reg 146 drivers/hwmon/f75375s.c static inline u16 f75375_read16(struct i2c_client *client, u8 reg) reg 148 drivers/hwmon/f75375s.c return (i2c_smbus_read_byte_data(client, reg) << 8) reg 149 drivers/hwmon/f75375s.c | i2c_smbus_read_byte_data(client, reg + 1); reg 152 drivers/hwmon/f75375s.c static inline void f75375_write8(struct i2c_client *client, u8 reg, reg 155 drivers/hwmon/f75375s.c i2c_smbus_write_byte_data(client, reg, value); reg 158 drivers/hwmon/f75375s.c static inline void f75375_write16(struct i2c_client *client, u8 reg, reg 161 drivers/hwmon/f75375s.c int err = i2c_smbus_write_byte_data(client, reg, (value >> 8)); reg 164 drivers/hwmon/f75375s.c i2c_smbus_write_byte_data(client, reg + 1, (value & 0xFF)); reg 239 drivers/hwmon/f75375s.c static inline u16 rpm_from_reg(u16 reg) reg 241 drivers/hwmon/f75375s.c if (reg == 0 || reg == 0xffff) reg 243 drivers/hwmon/f75375s.c return 1500000 / reg; reg 454 drivers/hwmon/f75375s.c char reg, ctrl; reg 469 drivers/hwmon/f75375s.c reg = F75375_REG_FAN_TIMER; reg 472 drivers/hwmon/f75375s.c reg = F75375_REG_CONFIG1; reg 477 drivers/hwmon/f75375s.c conf = f75375_read8(client, reg); reg 483 drivers/hwmon/f75375s.c f75375_write8(client, reg, conf); reg 575 drivers/hwmon/f75375s.c #define TEMP11_FROM_REG(reg) ((reg) / 32 * 125) reg 433 drivers/hwmon/fschmd.c u8 reg; reg 463 drivers/hwmon/fschmd.c reg = i2c_smbus_read_byte_data(to_i2c_client(dev), reg 467 drivers/hwmon/fschmd.c reg &= ~0x03; reg 468 drivers/hwmon/fschmd.c reg |= v; reg 471 drivers/hwmon/fschmd.c FSCHMD_REG_FAN_RIPPLE[data->kind][index], reg); reg 473 drivers/hwmon/fschmd.c data->fan_ripple[index] = reg; reg 569 drivers/hwmon/fschmd.c u8 reg; reg 580 drivers/hwmon/fschmd.c reg = i2c_smbus_read_byte_data(to_i2c_client(dev), FSCHMD_REG_CONTROL); reg 583 drivers/hwmon/fschmd.c reg |= FSCHMD_CONTROL_ALERT_LED; reg 585 drivers/hwmon/fschmd.c reg &= ~FSCHMD_CONTROL_ALERT_LED; reg 587 drivers/hwmon/fschmd.c i2c_smbus_write_byte_data(to_i2c_client(dev), FSCHMD_REG_CONTROL, reg); reg 589 drivers/hwmon/fschmd.c data->global_control = reg; reg 98 drivers/hwmon/ftsteutates.c static int fts_read_byte(struct i2c_client *client, unsigned short reg) reg 101 drivers/hwmon/ftsteutates.c unsigned char page = reg >> 8; reg 111 drivers/hwmon/ftsteutates.c reg &= 0xFF; reg 112 drivers/hwmon/ftsteutates.c ret = i2c_smbus_read_byte_data(client, reg); reg 113 drivers/hwmon/ftsteutates.c dev_dbg(&client->dev, "read - reg: 0x%.02x: val: 0x%.02x\n", reg, ret); reg 120 drivers/hwmon/ftsteutates.c static int fts_write_byte(struct i2c_client *client, unsigned short reg, reg 124 drivers/hwmon/ftsteutates.c unsigned char page = reg >> 8; reg 134 drivers/hwmon/ftsteutates.c reg &= 0xFF; reg 136 drivers/hwmon/ftsteutates.c "write - reg: 0x%.02x: val: 0x%.02x\n", reg, value); reg 137 drivers/hwmon/ftsteutates.c ret = i2c_smbus_write_byte_data(client, reg, value); reg 67 drivers/hwmon/g760a.c static int g760a_read_value(struct i2c_client *client, enum g760a_regs reg) reg 69 drivers/hwmon/g760a.c return i2c_smbus_read_byte_data(client, reg); reg 72 drivers/hwmon/g760a.c static int g760a_write_value(struct i2c_client *client, enum g760a_regs reg, reg 75 drivers/hwmon/g760a.c return i2c_smbus_write_byte_data(client, reg, value); reg 98 drivers/hwmon/g762.c #define G762_PULSE_FROM_REG(reg) \ reg 99 drivers/hwmon/g762.c ((((reg) & G762_REG_FAN_CMD1_PULSE_PER_REV) + 1) << 1) reg 105 drivers/hwmon/g762.c #define G762_CLKDIV_FROM_REG(reg) \ reg 106 drivers/hwmon/g762.c (1 << (((reg) & (G762_REG_FAN_CMD1_CLK_DIV_ID0 | \ reg 113 drivers/hwmon/g762.c #define G762_GEARMULT_FROM_REG(reg) \ reg 114 drivers/hwmon/g762.c (1 << (((reg) & (G762_REG_FAN_CMD2_GEAR_MODE_0 | \ reg 134 drivers/hwmon/gl518sm.c static int gl518_read_value(struct i2c_client *client, u8 reg) reg 136 drivers/hwmon/gl518sm.c if ((reg >= 0x07) && (reg <= 0x0c)) reg 137 drivers/hwmon/gl518sm.c return i2c_smbus_read_word_swapped(client, reg); reg 139 drivers/hwmon/gl518sm.c return i2c_smbus_read_byte_data(client, reg); reg 142 drivers/hwmon/gl518sm.c static int gl518_write_value(struct i2c_client *client, u8 reg, u16 value) reg 144 drivers/hwmon/gl518sm.c if ((reg >= 0x07) && (reg <= 0x0c)) reg 145 drivers/hwmon/gl518sm.c return i2c_smbus_write_word_swapped(client, reg, value); reg 147 drivers/hwmon/gl518sm.c return i2c_smbus_write_byte_data(client, reg, value); reg 280 drivers/hwmon/gl518sm.c #define set(type, suffix, value, reg) \ reg 294 drivers/hwmon/gl518sm.c gl518_write_value(client, reg, data->value); \ reg 299 drivers/hwmon/gl518sm.c #define set_bits(type, suffix, value, reg, mask, shift) \ reg 313 drivers/hwmon/gl518sm.c regvalue = gl518_read_value(client, reg); \ reg 316 drivers/hwmon/gl518sm.c gl518_write_value(client, reg, regvalue); \ reg 321 drivers/hwmon/gl518sm.c #define set_low(type, suffix, value, reg) \ reg 322 drivers/hwmon/gl518sm.c set_bits(type, suffix, value, reg, 0x00ff, 0) reg 323 drivers/hwmon/gl518sm.c #define set_high(type, suffix, value, reg) \ reg 324 drivers/hwmon/gl518sm.c set_bits(type, suffix, value, reg, 0xff00, 8) reg 93 drivers/hwmon/gl520sm.c static int gl520_read_value(struct i2c_client *client, u8 reg) reg 95 drivers/hwmon/gl520sm.c if ((reg >= 0x07) && (reg <= 0x0c)) reg 96 drivers/hwmon/gl520sm.c return i2c_smbus_read_word_swapped(client, reg); reg 98 drivers/hwmon/gl520sm.c return i2c_smbus_read_byte_data(client, reg); reg 101 drivers/hwmon/gl520sm.c static int gl520_write_value(struct i2c_client *client, u8 reg, u16 value) reg 103 drivers/hwmon/gl520sm.c if ((reg >= 0x07) && (reg <= 0x0c)) reg 104 drivers/hwmon/gl520sm.c return i2c_smbus_write_word_swapped(client, reg, value); reg 106 drivers/hwmon/gl520sm.c return i2c_smbus_write_byte_data(client, reg, value); reg 56 drivers/hwmon/i5500_temp.c int reg = to_sensor_dev_attr(devattr)->index; reg 60 drivers/hwmon/i5500_temp.c pci_read_config_word(pdev, reg, &tsthr); reg 216 drivers/hwmon/ibmaem.c u8 reg; reg 349 drivers/hwmon/ibmaem.c static int aem_read_sensor(struct aem_data *data, u8 elt, u8 reg, reg 373 drivers/hwmon/ibmaem.c rs_req.reg = reg; reg 108 drivers/hwmon/ina209.c static long ina209_from_reg(const u8 reg, const u16 val) reg 110 drivers/hwmon/ina209.c switch (reg) { reg 158 drivers/hwmon/ina209.c static int ina209_to_reg(u8 reg, u16 old, long val) reg 160 drivers/hwmon/ina209.c switch (reg) { reg 208 drivers/hwmon/ina209.c static int ina209_interval_from_reg(u16 reg) reg 210 drivers/hwmon/ina209.c return 68 >> (15 - ((reg >> 3) & 0x0f)); reg 311 drivers/hwmon/ina209.c int reg = attr->index; reg 323 drivers/hwmon/ina209.c ret = ina209_to_reg(reg, data->regs[reg], val); reg 328 drivers/hwmon/ina209.c i2c_smbus_write_word_swapped(data->client, reg, ret); reg 329 drivers/hwmon/ina209.c data->regs[reg] = ret; reg 492 drivers/hwmon/ina209.c int reg; reg 494 drivers/hwmon/ina209.c reg = i2c_smbus_read_word_swapped(client, INA209_CALIBRATION); reg 495 drivers/hwmon/ina209.c if (reg < 0) reg 496 drivers/hwmon/ina209.c return reg; reg 497 drivers/hwmon/ina209.c data->calibration_orig = reg; reg 499 drivers/hwmon/ina209.c reg = i2c_smbus_read_word_swapped(client, INA209_CONFIGURATION); reg 500 drivers/hwmon/ina209.c if (reg < 0) reg 501 drivers/hwmon/ina209.c return reg; reg 502 drivers/hwmon/ina209.c data->config_orig = reg; reg 74 drivers/hwmon/ina2xx.c #define INA226_READ_AVG(reg) (((reg) & INA226_AVG_RD_MASK) >> 9) reg 196 drivers/hwmon/ina2xx.c static int ina2xx_read_reg(struct device *dev, int reg, unsigned int *regval) reg 201 drivers/hwmon/ina2xx.c dev_dbg(dev, "Starting register %d read\n", reg); reg 205 drivers/hwmon/ina2xx.c ret = regmap_read(data->regmap, reg, regval); reg 209 drivers/hwmon/ina2xx.c dev_dbg(dev, "read %d, val = 0x%04x\n", reg, *regval); reg 254 drivers/hwmon/ina2xx.c static int ina2xx_get_value(struct ina2xx_data *data, u8 reg, reg 259 drivers/hwmon/ina2xx.c switch (reg) { reg 176 drivers/hwmon/ina3221.c static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg, reg 182 drivers/hwmon/ina3221.c ret = regmap_read(ina->regmap, reg, ®val); reg 224 drivers/hwmon/ina3221.c u8 reg = ina3221_in_reg[channel]; reg 244 drivers/hwmon/ina3221.c ret = ina3221_read_value(ina, reg, ®val); reg 276 drivers/hwmon/ina3221.c u8 reg = ina3221_curr_reg[attr][channel]; reg 296 drivers/hwmon/ina3221.c ret = ina3221_read_value(ina, reg, ®val); reg 313 drivers/hwmon/ina3221.c ret = regmap_field_read(ina->fields[reg], ®val); reg 371 drivers/hwmon/ina3221.c u8 reg = ina3221_curr_reg[attr][channel]; reg 387 drivers/hwmon/ina3221.c return regmap_write(ina->regmap, reg, regval); reg 86 drivers/hwmon/it87.c static inline int superio_inb(int ioreg, int reg) reg 88 drivers/hwmon/it87.c outb(reg, ioreg); reg 92 drivers/hwmon/it87.c static inline void superio_outb(int ioreg, int reg, int val) reg 94 drivers/hwmon/it87.c outb(reg, ioreg); reg 98 drivers/hwmon/it87.c static int superio_inw(int ioreg, int reg) reg 102 drivers/hwmon/it87.c outb(reg++, ioreg); reg 104 drivers/hwmon/it87.c outb(reg, ioreg); reg 625 drivers/hwmon/it87.c static int pwm_from_reg(const struct it87_data *data, u8 reg) reg 628 drivers/hwmon/it87.c return reg; reg 630 drivers/hwmon/it87.c return (reg & 0x7f) << 1; reg 670 drivers/hwmon/it87.c static int it87_read_value(struct it87_data *data, u8 reg) reg 672 drivers/hwmon/it87.c outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); reg 681 drivers/hwmon/it87.c static void it87_write_value(struct it87_data *data, u8 reg, u8 value) reg 683 drivers/hwmon/it87.c outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); reg 962 drivers/hwmon/it87.c u8 reg, regval; reg 972 drivers/hwmon/it87.c reg = IT87_REG_TEMP_LOW(nr); reg 975 drivers/hwmon/it87.c reg = IT87_REG_TEMP_HIGH(nr); reg 984 drivers/hwmon/it87.c reg = IT87_REG_TEMP_OFFSET[nr]; reg 989 drivers/hwmon/it87.c it87_write_value(data, reg, data->temp[nr][index]); reg 1025 drivers/hwmon/it87.c u8 reg = data->sensor; /* In case value is updated while used */ reg 1028 drivers/hwmon/it87.c if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1)) || reg 1031 drivers/hwmon/it87.c if (reg & (1 << nr)) reg 1033 drivers/hwmon/it87.c if (reg & (8 << nr)) reg 1046 drivers/hwmon/it87.c u8 reg, extra; reg 1051 drivers/hwmon/it87.c reg = it87_read_value(data, IT87_REG_TEMP_ENABLE); reg 1052 drivers/hwmon/it87.c reg &= ~(1 << nr); reg 1053 drivers/hwmon/it87.c reg &= ~(8 << nr); reg 1054 drivers/hwmon/it87.c if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6)) reg 1055 drivers/hwmon/it87.c reg &= 0x3f; reg 1066 drivers/hwmon/it87.c reg |= 1 << nr; reg 1068 drivers/hwmon/it87.c reg |= 8 << nr; reg 1070 drivers/hwmon/it87.c reg |= (nr + 1) << 6; reg 1077 drivers/hwmon/it87.c data->sensor = reg; reg 1184 drivers/hwmon/it87.c u8 reg; reg 1198 drivers/hwmon/it87.c reg = it87_read_value(data, IT87_REG_FAN_DIV); reg 1201 drivers/hwmon/it87.c data->fan_div[nr] = reg & 0x07; reg 1204 drivers/hwmon/it87.c data->fan_div[nr] = (reg >> 3) & 0x07; reg 1207 drivers/hwmon/it87.c data->fan_div[nr] = (reg & 0x40) ? 3 : 1; reg 1469 drivers/hwmon/it87.c u8 reg; reg 1479 drivers/hwmon/it87.c reg = 0x00; reg 1482 drivers/hwmon/it87.c reg = 0x01; reg 1485 drivers/hwmon/it87.c reg = 0x02; reg 1493 drivers/hwmon/it87.c data->pwm_temp_map[nr] = reg; reg 1583 drivers/hwmon/it87.c int reg; reg 1586 drivers/hwmon/it87.c reg = data->auto_temp[nr][point]; reg 1588 drivers/hwmon/it87.c reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f); reg 1590 drivers/hwmon/it87.c return sprintf(buf, "%d\n", TEMP_FROM_REG(reg)); reg 1602 drivers/hwmon/it87.c int reg; reg 1609 drivers/hwmon/it87.c reg = data->auto_temp[nr][1] - TEMP_TO_REG(val); reg 1610 drivers/hwmon/it87.c reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0); reg 1611 drivers/hwmon/it87.c data->auto_temp[nr][0] = reg; reg 1612 drivers/hwmon/it87.c it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg); reg 1614 drivers/hwmon/it87.c reg = TEMP_TO_REG(val); reg 1615 drivers/hwmon/it87.c data->auto_temp[nr][point] = reg; reg 1618 drivers/hwmon/it87.c it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg); reg 2614 drivers/hwmon/it87.c int reg; reg 2619 drivers/hwmon/it87.c reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); reg 2620 drivers/hwmon/it87.c if (reg & BIT(6)) reg 2624 drivers/hwmon/it87.c reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); reg 2625 drivers/hwmon/it87.c if (!(reg & BIT(5))) reg 2627 drivers/hwmon/it87.c if (!(reg & BIT(4))) reg 2631 drivers/hwmon/it87.c reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); reg 2632 drivers/hwmon/it87.c if (reg & BIT(6)) reg 2634 drivers/hwmon/it87.c if (reg & BIT(7)) reg 2638 drivers/hwmon/it87.c reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG); reg 2639 drivers/hwmon/it87.c if (reg & BIT(2)) reg 2643 drivers/hwmon/it87.c reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); reg 2644 drivers/hwmon/it87.c if (reg & BIT(1)) reg 2646 drivers/hwmon/it87.c if (reg & BIT(2)) reg 2649 drivers/hwmon/it87.c if (!(reg & BIT(7))) { reg 2655 drivers/hwmon/it87.c reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); reg 2656 drivers/hwmon/it87.c if (reg & BIT(0)) reg 2664 drivers/hwmon/it87.c int reg; reg 2669 drivers/hwmon/it87.c reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); reg 2670 drivers/hwmon/it87.c if (reg & BIT(6)) reg 2672 drivers/hwmon/it87.c if (reg & BIT(5)) reg 2676 drivers/hwmon/it87.c reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); reg 2677 drivers/hwmon/it87.c if (reg & BIT(6)) reg 2679 drivers/hwmon/it87.c if (reg & BIT(7)) reg 2681 drivers/hwmon/it87.c if (reg & BIT(3)) reg 2683 drivers/hwmon/it87.c if (reg & BIT(1)) reg 2687 drivers/hwmon/it87.c reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); reg 2688 drivers/hwmon/it87.c if (reg & BIT(1)) reg 2690 drivers/hwmon/it87.c if (reg & BIT(2)) reg 2694 drivers/hwmon/it87.c reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); reg 2695 drivers/hwmon/it87.c if (!(reg & BIT(0))) reg 2701 drivers/hwmon/it87.c int reg; reg 2708 drivers/hwmon/it87.c reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); reg 2711 drivers/hwmon/it87.c if (reg & BIT(5)) reg 2713 drivers/hwmon/it87.c if (reg & BIT(4)) reg 2719 drivers/hwmon/it87.c if (!(reg & BIT(5))) reg 2721 drivers/hwmon/it87.c if (!(reg & BIT(4))) reg 2729 drivers/hwmon/it87.c reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); reg 2732 drivers/hwmon/it87.c if (reg & 0x0f) { reg 2739 drivers/hwmon/it87.c if (reg & BIT(6)) reg 2741 drivers/hwmon/it87.c if (reg & BIT(7)) reg 2745 drivers/hwmon/it87.c reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); reg 2746 drivers/hwmon/it87.c if (reg & BIT(1)) reg 2748 drivers/hwmon/it87.c if (reg & BIT(2)) reg 2756 drivers/hwmon/it87.c reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); reg 2758 drivers/hwmon/it87.c uart6 = sio_data->type == it8782 && (reg & BIT(2)); reg 2774 drivers/hwmon/it87.c if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) { reg 2775 drivers/hwmon/it87.c reg |= BIT(1); reg 2776 drivers/hwmon/it87.c superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg); reg 2780 drivers/hwmon/it87.c if (reg & BIT(0)) reg 2782 drivers/hwmon/it87.c if (reg & BIT(1)) reg 2838 drivers/hwmon/it87.c int i, reg; reg 2841 drivers/hwmon/it87.c reg = it87_read_value(data, IT87_REG_VIN_MIN(i)); reg 2842 drivers/hwmon/it87.c if (reg == 0xff) reg 2846 drivers/hwmon/it87.c reg = it87_read_value(data, IT87_REG_TEMP_HIGH(i)); reg 2847 drivers/hwmon/it87.c if (reg == 0xff) reg 2855 drivers/hwmon/it87.c int reg; reg 2857 drivers/hwmon/it87.c reg = it87_read_value(data, IT87_REG_VIN_ENABLE); reg 2858 drivers/hwmon/it87.c if ((reg & 0xff) == 0) { reg 2885 drivers/hwmon/it87.c int reg; reg 2890 drivers/hwmon/it87.c reg = it87_read_value(data, IT87_REG_FAN_16BIT); reg 2891 drivers/hwmon/it87.c if (~reg & 0x07 & data->has_fan) { reg 2895 drivers/hwmon/it87.c reg | 0x07); reg 3130 drivers/hwmon/it87.c u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE); reg 3133 drivers/hwmon/it87.c if ((reg & 0x03) >= 0x02) reg 3135 drivers/hwmon/it87.c if (((reg >> 2) & 0x03) >= 0x02) reg 3137 drivers/hwmon/it87.c if (((reg >> 4) & 0x03) >= 0x02) reg 3141 drivers/hwmon/it87.c if ((reg & 0x03) == 0x01) reg 3143 drivers/hwmon/it87.c if (((reg >> 2) & 0x03) == 0x01) reg 3145 drivers/hwmon/it87.c if (((reg >> 4) & 0x03) == 0x01) reg 233 drivers/hwmon/jc42.c static int jc42_temp_from_reg(s16 reg) reg 235 drivers/hwmon/jc42.c reg = sign_extend32(reg, 12); reg 238 drivers/hwmon/jc42.c return reg * 125 / 2; reg 206 drivers/hwmon/k10temp.c u32 reg; reg 217 drivers/hwmon/k10temp.c ®); reg 218 drivers/hwmon/k10temp.c if (!(reg & NB_CAP_HTC)) reg 221 drivers/hwmon/k10temp.c data->read_htcreg(data->pdev, ®); reg 222 drivers/hwmon/k10temp.c if (!(reg & HTC_ENABLE)) reg 112 drivers/hwmon/lm63.c #define FAN_FROM_REG(reg) ((reg) == 0xFFFC || (reg) == 0 ? 0 : \ reg 113 drivers/hwmon/lm63.c 5400000 / (reg)) reg 116 drivers/hwmon/lm63.c #define TEMP8_FROM_REG(reg) ((reg) * 1000) reg 121 drivers/hwmon/lm63.c #define TEMP11_FROM_REG(reg) ((reg) / 32 * 125) reg 388 drivers/hwmon/lm63.c u8 reg; reg 397 drivers/hwmon/lm63.c reg = nr ? LM63_REG_LUT_PWM(nr - 1) : LM63_REG_PWM_VALUE; reg 403 drivers/hwmon/lm63.c i2c_smbus_write_byte_data(client, reg, data->pwm1[nr]); reg 495 drivers/hwmon/lm63.c u8 reg; reg 504 drivers/hwmon/lm63.c reg = LM63_REG_REMOTE_TCRIT; reg 511 drivers/hwmon/lm63.c reg = LM63_REG_LOCAL_HIGH; reg 515 drivers/hwmon/lm63.c reg = LM63_REG_LUT_TEMP(nr - 3); reg 519 drivers/hwmon/lm63.c i2c_smbus_write_byte_data(client, reg, temp); reg 553 drivers/hwmon/lm63.c static const u8 reg[6] = { reg 579 drivers/hwmon/lm63.c i2c_smbus_write_byte_data(client, reg[(nr - 1) * 2], reg 581 drivers/hwmon/lm63.c i2c_smbus_write_byte_data(client, reg[(nr - 1) * 2 + 1], reg 704 drivers/hwmon/lm63.c u8 reg; reg 714 drivers/hwmon/lm63.c reg = i2c_smbus_read_byte_data(client, LM96163_REG_TRUTHERM) & ~0x02; reg 716 drivers/hwmon/lm63.c reg | (data->trutherm ? 0x02 : 0x00)); reg 328 drivers/hwmon/lm75.c int err, reg; reg 343 drivers/hwmon/lm75.c reg = LM75_REG_TEMP; reg 346 drivers/hwmon/lm75.c reg = LM75_REG_MAX; reg 349 drivers/hwmon/lm75.c reg = LM75_REG_HYST; reg 354 drivers/hwmon/lm75.c err = regmap_read(data->regmap, reg, ®val); reg 370 drivers/hwmon/lm75.c int reg; reg 374 drivers/hwmon/lm75.c reg = LM75_REG_MAX; reg 377 drivers/hwmon/lm75.c reg = LM75_REG_HYST; reg 396 drivers/hwmon/lm75.c return regmap_write(data->regmap, reg, (u16)temp); reg 402 drivers/hwmon/lm75.c unsigned int reg; reg 421 drivers/hwmon/lm75.c err = regmap_read(data->regmap, LM75_REG_CONF, ®); reg 424 drivers/hwmon/lm75.c reg &= ~0x00c0; reg 425 drivers/hwmon/lm75.c reg |= (3 - index) << 6; reg 426 drivers/hwmon/lm75.c err = regmap_write(data->regmap, LM75_REG_CONF, reg); reg 515 drivers/hwmon/lm75.c static bool lm75_is_writeable_reg(struct device *dev, unsigned int reg) reg 517 drivers/hwmon/lm75.c return reg != LM75_REG_TEMP; reg 520 drivers/hwmon/lm75.c static bool lm75_is_volatile_reg(struct device *dev, unsigned int reg) reg 522 drivers/hwmon/lm75.c return reg == LM75_REG_TEMP || reg == LM75_REG_CONF; reg 32 drivers/hwmon/lm75.h static inline int LM75_TEMP_FROM_REG(u16 reg) reg 36 drivers/hwmon/lm75.h return ((s16)reg / 128) * 500; reg 77 drivers/hwmon/lm77.c static inline int LM77_TEMP_FROM_REG(s16 reg) reg 79 drivers/hwmon/lm77.c return (reg / 8) * 500; reg 86 drivers/hwmon/lm77.c static u16 lm77_read_value(struct i2c_client *client, u8 reg) reg 88 drivers/hwmon/lm77.c if (reg == LM77_REG_CONF) reg 89 drivers/hwmon/lm77.c return i2c_smbus_read_byte_data(client, reg); reg 91 drivers/hwmon/lm77.c return i2c_smbus_read_word_swapped(client, reg); reg 94 drivers/hwmon/lm77.c static int lm77_write_value(struct i2c_client *client, u8 reg, u16 value) reg 96 drivers/hwmon/lm77.c if (reg == LM77_REG_CONF) reg 97 drivers/hwmon/lm77.c return i2c_smbus_write_byte_data(client, reg, value); reg 99 drivers/hwmon/lm77.c return i2c_smbus_write_word_swapped(client, reg, value); reg 136 drivers/hwmon/lm78.c static int lm78_read_value(struct lm78_data *data, u8 reg); reg 137 drivers/hwmon/lm78.c static int lm78_write_value(struct lm78_data *data, u8 reg, u8 value); reg 354 drivers/hwmon/lm78.c u8 reg; reg 387 drivers/hwmon/lm78.c reg = lm78_read_value(data, LM78_REG_VID_FANDIV); reg 390 drivers/hwmon/lm78.c reg = (reg & 0xcf) | (data->fan_div[nr] << 4); reg 393 drivers/hwmon/lm78.c reg = (reg & 0x3f) | (data->fan_div[nr] << 6); reg 396 drivers/hwmon/lm78.c lm78_write_value(data, LM78_REG_VID_FANDIV, reg); reg 677 drivers/hwmon/lm78.c static int lm78_read_value(struct lm78_data *data, u8 reg) reg 685 drivers/hwmon/lm78.c outb_p(reg, data->isa_addr + LM78_ADDR_REG_OFFSET); reg 691 drivers/hwmon/lm78.c return i2c_smbus_read_byte_data(client, reg); reg 694 drivers/hwmon/lm78.c static int lm78_write_value(struct lm78_data *data, u8 reg, u8 value) reg 701 drivers/hwmon/lm78.c outb_p(reg, data->isa_addr + LM78_ADDR_REG_OFFSET); reg 707 drivers/hwmon/lm78.c return i2c_smbus_write_byte_data(client, reg, value); reg 76 drivers/hwmon/lm80.c #define TEMP_FROM_REG(reg) ((reg) * 125 / 32) reg 130 drivers/hwmon/lm80.c static int lm80_read_value(struct i2c_client *client, u8 reg) reg 132 drivers/hwmon/lm80.c return i2c_smbus_read_byte_data(client, reg); reg 135 drivers/hwmon/lm80.c static int lm80_write_value(struct i2c_client *client, u8 reg, u8 value) reg 137 drivers/hwmon/lm80.c return i2c_smbus_write_byte_data(client, reg, value); reg 279 drivers/hwmon/lm80.c u8 reg; reg 284 drivers/hwmon/lm80.c reg = nr == i_min ? LM80_REG_IN_MIN(index) : LM80_REG_IN_MAX(index); reg 288 drivers/hwmon/lm80.c lm80_write_value(client, reg, data->in[nr][index]); reg 350 drivers/hwmon/lm80.c u8 reg; reg 388 drivers/hwmon/lm80.c reg = (rv & ~(3 << (2 * (nr + 1)))) reg 390 drivers/hwmon/lm80.c lm80_write_value(client, LM80_REG_FANDIV, reg); reg 206 drivers/hwmon/lm85.c static int FREQ_FROM_REG(const int *map, unsigned int map_size, u8 reg) reg 208 drivers/hwmon/lm85.c return map[reg % map_size]; reg 321 drivers/hwmon/lm85.c static int lm85_read_value(struct i2c_client *client, u8 reg) reg 326 drivers/hwmon/lm85.c switch (reg) { reg 336 drivers/hwmon/lm85.c res = i2c_smbus_read_byte_data(client, reg) & 0xff; reg 337 drivers/hwmon/lm85.c res |= i2c_smbus_read_byte_data(client, reg + 1) << 8; reg 340 drivers/hwmon/lm85.c res = i2c_smbus_read_byte_data(client, reg); reg 347 drivers/hwmon/lm85.c static void lm85_write_value(struct i2c_client *client, u8 reg, int value) reg 349 drivers/hwmon/lm85.c switch (reg) { reg 359 drivers/hwmon/lm85.c i2c_smbus_write_byte_data(client, reg, value & 0xff); reg 360 drivers/hwmon/lm85.c i2c_smbus_write_byte_data(client, reg + 1, value >> 8); reg 363 drivers/hwmon/lm85.c i2c_smbus_write_byte_data(client, reg, value); reg 108 drivers/hwmon/lm87.c #define IN_FROM_REG(reg, scale) (((reg) * (scale) + 96) / 192) reg 113 drivers/hwmon/lm87.c #define TEMP_FROM_REG(reg) ((reg) * 1000) reg 119 drivers/hwmon/lm87.c #define FAN_FROM_REG(reg, div) ((reg) == 255 || (reg) == 0 ? 0 : \ reg 120 drivers/hwmon/lm87.c (1350000 + (reg)*(div) / 2) / ((reg) * (div))) reg 124 drivers/hwmon/lm87.c #define FAN_DIV_FROM_REG(reg) (1 << (reg)) reg 127 drivers/hwmon/lm87.c #define AOUT_FROM_REG(reg) (((reg) * 98 + 5) / 10) reg 173 drivers/hwmon/lm87.c static inline int lm87_read_value(struct i2c_client *client, u8 reg) reg 175 drivers/hwmon/lm87.c return i2c_smbus_read_byte_data(client, reg); reg 178 drivers/hwmon/lm87.c static inline int lm87_write_value(struct i2c_client *client, u8 reg, u8 value) reg 180 drivers/hwmon/lm87.c return i2c_smbus_write_byte_data(client, reg, value); reg 530 drivers/hwmon/lm87.c u8 reg; reg 558 drivers/hwmon/lm87.c reg = lm87_read_value(client, LM87_REG_VID_FAN_DIV); reg 561 drivers/hwmon/lm87.c reg = (reg & 0xCF) | (data->fan_div[0] << 4); reg 564 drivers/hwmon/lm87.c reg = (reg & 0x3F) | (data->fan_div[1] << 6); reg 567 drivers/hwmon/lm87.c lm87_write_value(client, LM87_REG_VID_FAN_DIV, reg); reg 498 drivers/hwmon/lm90.c static int lm90_read_reg(struct i2c_client *client, u8 reg) reg 503 drivers/hwmon/lm90.c err = adm1032_write_byte(client, reg); reg 507 drivers/hwmon/lm90.c err = i2c_smbus_read_byte_data(client, reg); reg 1001 drivers/hwmon/lm90.c } reg[] = { reg 1009 drivers/hwmon/lm90.c struct reg *regp = ®[index]; reg 1059 drivers/hwmon/lm90.c static const u8 reg[TEMP8_REG_NUM] = { reg 1084 drivers/hwmon/lm90.c err = i2c_smbus_write_byte_data(client, reg[index], data->temp8[index]); reg 64 drivers/hwmon/lm92.c static inline int TEMP_FROM_REG(s16 reg) reg 66 drivers/hwmon/lm92.c return reg / 8 * 625 / 10; reg 76 drivers/hwmon/lm92.c static inline u8 ALARMS_FROM_REG(s16 reg) reg 78 drivers/hwmon/lm92.c return reg & 0x0007; reg 74 drivers/hwmon/lm93.c #define LM93_REG_PWM_CTL(nr, reg) (0xc8 + (reg) + (nr) * 4) reg 302 drivers/hwmon/lm93.c static int LM93_VID_FROM_REG(u8 reg) reg 304 drivers/hwmon/lm93.c return vid_from_reg((reg & 0x3f), 100); reg 342 drivers/hwmon/lm93.c static unsigned LM93_IN_FROM_REG(int nr, u8 reg) reg 351 drivers/hwmon/lm93.c return (slope * reg + intercept + 500) / 1000; reg 381 drivers/hwmon/lm93.c static unsigned LM93_IN_REL_FROM_REG(u8 reg, int upper, int vid) reg 383 drivers/hwmon/lm93.c const long uv_offset = upper ? (((reg >> 4 & 0x0f) + 1) * 12500) : reg 384 drivers/hwmon/lm93.c (((reg >> 0 & 0x0f) + 1) * -25000); reg 389 drivers/hwmon/lm93.c #define LM93_IN_MIN_FROM_REG(reg, vid) LM93_IN_REL_FROM_REG((reg), 0, (vid)) reg 390 drivers/hwmon/lm93.c #define LM93_IN_MAX_FROM_REG(reg, vid) LM93_IN_REL_FROM_REG((reg), 1, (vid)) reg 413 drivers/hwmon/lm93.c static int LM93_TEMP_FROM_REG(u8 reg) reg 415 drivers/hwmon/lm93.c return (s8)reg * 1000; reg 444 drivers/hwmon/lm93.c static int LM93_TEMP_OFFSET_FROM_REG(u8 reg, int mode) reg 446 drivers/hwmon/lm93.c return (reg & 0x0f) * (mode ? 5 : 10); reg 468 drivers/hwmon/lm93.c static int LM93_TEMP_AUTO_OFFSET_FROM_REG(u8 reg, int nr, int mode) reg 472 drivers/hwmon/lm93.c return LM93_TEMP_OFFSET_FROM_REG(reg & 0x0f, mode); reg 476 drivers/hwmon/lm93.c return LM93_TEMP_OFFSET_FROM_REG(reg >> 4 & 0x0f, mode); reg 500 drivers/hwmon/lm93.c u8 reg; reg 504 drivers/hwmon/lm93.c reg = data->boost_hyst[0] & 0x0f; reg 507 drivers/hwmon/lm93.c reg = data->boost_hyst[0] >> 4 & 0x0f; reg 510 drivers/hwmon/lm93.c reg = data->boost_hyst[1] & 0x0f; reg 514 drivers/hwmon/lm93.c reg = data->boost_hyst[1] >> 4 & 0x0f; reg 519 drivers/hwmon/lm93.c LM93_TEMP_OFFSET_FROM_REG(reg, mode); reg 525 drivers/hwmon/lm93.c u8 reg = LM93_TEMP_OFFSET_TO_REG( reg 530 drivers/hwmon/lm93.c reg = (data->boost_hyst[0] & 0xf0) | (reg & 0x0f); reg 533 drivers/hwmon/lm93.c reg = (reg << 4 & 0xf0) | (data->boost_hyst[0] & 0x0f); reg 536 drivers/hwmon/lm93.c reg = (data->boost_hyst[1] & 0xf0) | (reg & 0x0f); reg 540 drivers/hwmon/lm93.c reg = (reg << 4 & 0xf0) | (data->boost_hyst[1] & 0x0f); reg 544 drivers/hwmon/lm93.c return reg; reg 576 drivers/hwmon/lm93.c static int LM93_PWM_FROM_REG(u8 reg, enum pwm_freq freq) reg 578 drivers/hwmon/lm93.c return lm93_pwm_map[freq][reg & 0x0f]; reg 626 drivers/hwmon/lm93.c static int LM93_PWM_FREQ_FROM_REG(u8 reg) reg 628 drivers/hwmon/lm93.c return lm93_pwm_freq_map[reg & 0x07]; reg 651 drivers/hwmon/lm93.c static int LM93_SPINUP_TIME_FROM_REG(u8 reg) reg 653 drivers/hwmon/lm93.c return lm93_spinup_time_map[reg >> 5 & 0x07]; reg 671 drivers/hwmon/lm93.c static int LM93_RAMP_FROM_REG(u8 reg) reg 673 drivers/hwmon/lm93.c return (reg & 0x0f) * 5; reg 704 drivers/hwmon/lm93.c static int LM93_INTERVAL_FROM_REG(u8 reg) reg 706 drivers/hwmon/lm93.c return lm93_interval_map[reg & 0x0f]; reg 725 drivers/hwmon/lm93.c static unsigned LM93_GPI_FROM_REG(u8 reg) reg 727 drivers/hwmon/lm93.c return ~reg & 0xff; reg 798 drivers/hwmon/lm93.c static u8 lm93_read_byte(struct i2c_client *client, u8 reg) reg 804 drivers/hwmon/lm93.c value = i2c_smbus_read_byte_data(client, reg); reg 810 drivers/hwmon/lm93.c reg); reg 821 drivers/hwmon/lm93.c static int lm93_write_byte(struct i2c_client *client, u8 reg, u8 value) reg 826 drivers/hwmon/lm93.c result = i2c_smbus_write_byte_data(client, reg, value); reg 831 drivers/hwmon/lm93.c value, reg); reg 836 drivers/hwmon/lm93.c static u16 lm93_read_word(struct i2c_client *client, u8 reg) reg 842 drivers/hwmon/lm93.c value = i2c_smbus_read_word_data(client, reg); reg 848 drivers/hwmon/lm93.c reg); reg 859 drivers/hwmon/lm93.c static int lm93_write_word(struct i2c_client *client, u8 reg, u16 value) reg 864 drivers/hwmon/lm93.c result = i2c_smbus_write_word_data(client, reg, value); reg 869 drivers/hwmon/lm93.c value, reg); reg 1526 drivers/hwmon/lm93.c u8 reg, ctl4; reg 1528 drivers/hwmon/lm93.c reg = data->auto_pwm_min_hyst[nr/2] >> 4 & 0x0f; reg 1530 drivers/hwmon/lm93.c return sprintf(buf, "%d\n", LM93_PWM_FROM_REG(reg, (ctl4 & 0x07) ? reg 1541 drivers/hwmon/lm93.c u8 reg, ctl4; reg 1550 drivers/hwmon/lm93.c reg = lm93_read_byte(client, LM93_REG_PWM_MIN_HYST(nr)); reg 1552 drivers/hwmon/lm93.c reg = (reg & 0x0f) | reg 1556 drivers/hwmon/lm93.c data->auto_pwm_min_hyst[nr/2] = reg; reg 1557 drivers/hwmon/lm93.c lm93_write_byte(client, LM93_REG_PWM_MIN_HYST(nr), reg); reg 1584 drivers/hwmon/lm93.c u8 reg; reg 1597 drivers/hwmon/lm93.c reg = data->auto_pwm_min_hyst[nr/2]; reg 1598 drivers/hwmon/lm93.c reg = (reg & 0xf0) | (LM93_TEMP_OFFSET_TO_REG(val, 1) & 0x0f); reg 1599 drivers/hwmon/lm93.c data->auto_pwm_min_hyst[nr/2] = reg; reg 1600 drivers/hwmon/lm93.c lm93_write_byte(client, LM93_REG_PWM_MIN_HYST(nr), reg); reg 2501 drivers/hwmon/lm93.c u8 reg; reg 2504 drivers/hwmon/lm93.c reg = lm93_read_byte(client, LM93_REG_GPI_VID_CTL); reg 2506 drivers/hwmon/lm93.c reg | (vid_agtl ? 0x03 : 0x00)); reg 2510 drivers/hwmon/lm93.c reg = lm93_read_byte(client, LM93_REG_CONFIG); reg 2511 drivers/hwmon/lm93.c lm93_write_byte(client, LM93_REG_CONFIG, reg | 0x08); reg 2514 drivers/hwmon/lm93.c reg = lm93_read_byte(client, LM93_REG_STATUS_CONTROL); reg 2515 drivers/hwmon/lm93.c lm93_write_byte(client, LM93_REG_STATUS_CONTROL, reg | 0x02); reg 2521 drivers/hwmon/lm93.c reg = lm93_read_byte(client, LM93_REG_MISC_ERR_MASK); reg 2522 drivers/hwmon/lm93.c reg &= ~0x03; reg 2523 drivers/hwmon/lm93.c reg &= ~(vccp_limit_type[0] ? 0x10 : 0); reg 2524 drivers/hwmon/lm93.c reg &= ~(vccp_limit_type[1] ? 0x20 : 0); reg 2525 drivers/hwmon/lm93.c lm93_write_byte(client, LM93_REG_MISC_ERR_MASK, reg); reg 2529 drivers/hwmon/lm93.c reg = lm93_read_byte(client, LM93_REG_CONFIG); reg 2530 drivers/hwmon/lm93.c lm93_write_byte(client, LM93_REG_CONFIG, reg | 0x01); reg 282 drivers/hwmon/lm95245.c int ret, reg; reg 290 drivers/hwmon/lm95245.c reg = channel ? LM95245_REG_RW_REMOTE_TCRIT_LIMIT : reg 293 drivers/hwmon/lm95245.c ret = regmap_write(regmap, reg, val); reg 480 drivers/hwmon/lm95245.c static bool lm95245_is_writeable_reg(struct device *dev, unsigned int reg) reg 482 drivers/hwmon/lm95245.c switch (reg) { reg 499 drivers/hwmon/lm95245.c static bool lm95245_is_volatile_reg(struct device *dev, unsigned int reg) reg 501 drivers/hwmon/lm95245.c switch (reg) { reg 61 drivers/hwmon/ltc2945.c static inline bool is_power_reg(u8 reg) reg 63 drivers/hwmon/ltc2945.c return reg < LTC2945_SENSE_H; reg 67 drivers/hwmon/ltc2945.c static long long ltc2945_reg_to_val(struct device *dev, u8 reg) reg 75 drivers/hwmon/ltc2945.c ret = regmap_bulk_read(regmap, reg, buf, reg 76 drivers/hwmon/ltc2945.c is_power_reg(reg) ? 3 : 2); reg 80 drivers/hwmon/ltc2945.c if (is_power_reg(reg)) { reg 88 drivers/hwmon/ltc2945.c switch (reg) { reg 148 drivers/hwmon/ltc2945.c static int ltc2945_val_to_reg(struct device *dev, u8 reg, reg 155 drivers/hwmon/ltc2945.c switch (reg) { reg 238 drivers/hwmon/ltc2945.c u8 reg = attr->index; reg 250 drivers/hwmon/ltc2945.c regval = ltc2945_val_to_reg(dev, reg, val); reg 251 drivers/hwmon/ltc2945.c if (is_power_reg(reg)) { reg 263 drivers/hwmon/ltc2945.c ret = regmap_bulk_write(regmap, reg, regbuf, num_regs); reg 273 drivers/hwmon/ltc2945.c u8 reg = attr->index; reg 274 drivers/hwmon/ltc2945.c int num_regs = is_power_reg(reg) ? 3 : 2; reg 290 drivers/hwmon/ltc2945.c ret = regmap_bulk_write(regmap, reg, buf_min, num_regs); reg 294 drivers/hwmon/ltc2945.c switch (reg) { reg 296 drivers/hwmon/ltc2945.c reg = LTC2945_MAX_POWER_H; reg 299 drivers/hwmon/ltc2945.c reg = LTC2945_MAX_SENSE_H; reg 302 drivers/hwmon/ltc2945.c reg = LTC2945_MAX_VIN_H; reg 305 drivers/hwmon/ltc2945.c reg = LTC2945_MAX_ADIN_H; reg 308 drivers/hwmon/ltc2945.c WARN_ONCE(1, "Bad register: 0x%x\n", reg); reg 312 drivers/hwmon/ltc2945.c ret = regmap_bulk_write(regmap, reg, buf_max, num_regs); reg 75 drivers/hwmon/ltc2990.c u8 reg; reg 79 drivers/hwmon/ltc2990.c reg = LTC2990_VCC_MSB; reg 84 drivers/hwmon/ltc2990.c reg = LTC2990_V1_MSB; reg 87 drivers/hwmon/ltc2990.c reg = LTC2990_V2_MSB; reg 92 drivers/hwmon/ltc2990.c reg = LTC2990_V3_MSB; reg 95 drivers/hwmon/ltc2990.c reg = LTC2990_V4_MSB; reg 98 drivers/hwmon/ltc2990.c reg = LTC2990_TINT_MSB; reg 104 drivers/hwmon/ltc2990.c val = i2c_smbus_read_word_swapped(i2c, reg); reg 88 drivers/hwmon/ltc4151.c static int ltc4151_get_value(struct ltc4151_data *data, u8 reg) reg 92 drivers/hwmon/ltc4151.c val = (data->regs[reg] << 4) + (data->regs[reg + 1] >> 4); reg 94 drivers/hwmon/ltc4151.c switch (reg) { reg 76 drivers/hwmon/ltc4215.c static int ltc4215_get_voltage(struct device *dev, u8 reg) reg 79 drivers/hwmon/ltc4215.c const u8 regval = data->regs[reg]; reg 82 drivers/hwmon/ltc4215.c switch (reg) { reg 170 drivers/hwmon/ltc4215.c const u8 reg = data->regs[LTC4215_STATUS]; reg 173 drivers/hwmon/ltc4215.c return snprintf(buf, PAGE_SIZE, "%u\n", !!(reg & mask)); reg 47 drivers/hwmon/ltc4222.c static int ltc4222_get_value(struct device *dev, u8 reg) reg 54 drivers/hwmon/ltc4222.c ret = regmap_bulk_read(regmap, reg, buf, 2); reg 60 drivers/hwmon/ltc4222.c switch (reg) { reg 170 drivers/hwmon/ltc4245.c static int ltc4245_get_voltage(struct device *dev, u8 reg) reg 173 drivers/hwmon/ltc4245.c const u8 regval = data->vregs[reg - 0x10]; reg 176 drivers/hwmon/ltc4245.c switch (reg) { reg 206 drivers/hwmon/ltc4245.c static unsigned int ltc4245_get_current(struct device *dev, u8 reg) reg 209 drivers/hwmon/ltc4245.c const u8 regval = data->vregs[reg - 0x10]; reg 228 drivers/hwmon/ltc4245.c switch (reg) { reg 37 drivers/hwmon/ltc4260.c static int ltc4260_get_value(struct device *dev, u8 reg) reg 43 drivers/hwmon/ltc4260.c ret = regmap_read(regmap, reg, &val); reg 47 drivers/hwmon/ltc4260.c switch (reg) { reg 90 drivers/hwmon/ltc4261.c static int ltc4261_get_value(struct ltc4261_data *data, u8 reg) reg 94 drivers/hwmon/ltc4261.c val = (data->regs[reg] << 2) + (data->regs[reg + 1] >> 6); reg 96 drivers/hwmon/ltc4261.c switch (reg) { reg 133 drivers/hwmon/max16065.c static int max16065_read_adc(struct i2c_client *client, int reg) reg 137 drivers/hwmon/max16065.c rv = i2c_smbus_read_word_swapped(client, reg); reg 36 drivers/hwmon/max31790.c #define SR_FROM_REG(reg) (((reg) & MAX31790_FAN_DYN_SR_MASK) \ reg 42 drivers/hwmon/max31790.c #define RPM_FROM_REG(reg, sr) (((reg) >> 4) ? \ reg 43 drivers/hwmon/max31790.c ((60 * (sr) * 8192) / ((reg) >> 4)) : \ reg 206 drivers/hwmon/max6621.c int reg; reg 214 drivers/hwmon/max6621.c reg = data->input_chan2reg[channel]; reg 215 drivers/hwmon/max6621.c ret = regmap_read(data->regmap, reg, ®val); reg 248 drivers/hwmon/max6621.c reg = max6621_temp_alert_chan2reg[channel]; reg 249 drivers/hwmon/max6621.c ret = regmap_read(data->regmap, reg, ®val); reg 314 drivers/hwmon/max6621.c u32 reg; reg 329 drivers/hwmon/max6621.c reg = max6621_temp_alert_chan2reg[channel]; reg 335 drivers/hwmon/max6621.c return regmap_write(data->regmap, reg, val); reg 369 drivers/hwmon/max6621.c static bool max6621_writeable_reg(struct device *dev, unsigned int reg) reg 371 drivers/hwmon/max6621.c switch (reg) { reg 386 drivers/hwmon/max6621.c static bool max6621_readable_reg(struct device *dev, unsigned int reg) reg 388 drivers/hwmon/max6621.c switch (reg) { reg 412 drivers/hwmon/max6621.c static bool max6621_volatile_reg(struct device *dev, unsigned int reg) reg 414 drivers/hwmon/max6621.c switch (reg) { reg 95 drivers/hwmon/max6650.c #define DIV_FROM_REG(reg) (1 << ((reg) & 7)) reg 160 drivers/hwmon/max6650.c int reg, err = 0; reg 167 drivers/hwmon/max6650.c reg = i2c_smbus_read_byte_data(client, tach_reg[i]); reg 168 drivers/hwmon/max6650.c if (reg < 0) { reg 169 drivers/hwmon/max6650.c err = reg; reg 172 drivers/hwmon/max6650.c data->tach[i] = reg; reg 180 drivers/hwmon/max6650.c reg = i2c_smbus_read_byte_data(client, MAX6650_REG_ALARM); reg 181 drivers/hwmon/max6650.c if (reg < 0) { reg 182 drivers/hwmon/max6650.c err = reg; reg 185 drivers/hwmon/max6650.c data->alarm |= reg; reg 362 drivers/hwmon/max6650.c int reg; reg 377 drivers/hwmon/max6650.c reg = i2c_smbus_read_byte_data(client, MAX6650_REG_CONFIG); reg 378 drivers/hwmon/max6650.c if (reg < 0) { reg 380 drivers/hwmon/max6650.c return reg; reg 387 drivers/hwmon/max6650.c reg &= ~MAX6650_CFG_V12; reg 390 drivers/hwmon/max6650.c reg |= MAX6650_CFG_V12; reg 400 drivers/hwmon/max6650.c reg &= ~MAX6650_CFG_PRESCALER_MASK; reg 403 drivers/hwmon/max6650.c reg = (reg & ~MAX6650_CFG_PRESCALER_MASK) reg 407 drivers/hwmon/max6650.c reg = (reg & ~MAX6650_CFG_PRESCALER_MASK) reg 411 drivers/hwmon/max6650.c reg = (reg & ~MAX6650_CFG_PRESCALER_MASK) reg 415 drivers/hwmon/max6650.c reg = (reg & ~MAX6650_CFG_PRESCALER_MASK) reg 423 drivers/hwmon/max6650.c (reg & MAX6650_CFG_V12) ? 12 : 5, reg 424 drivers/hwmon/max6650.c 1 << (reg & MAX6650_CFG_PRESCALER_MASK)); reg 426 drivers/hwmon/max6650.c err = i2c_smbus_write_byte_data(client, MAX6650_REG_CONFIG, reg); reg 431 drivers/hwmon/max6650.c data->config = reg; reg 433 drivers/hwmon/max6650.c reg = i2c_smbus_read_byte_data(client, MAX6650_REG_SPEED); reg 434 drivers/hwmon/max6650.c if (reg < 0) { reg 436 drivers/hwmon/max6650.c return reg; reg 438 drivers/hwmon/max6650.c data->speed = reg; reg 440 drivers/hwmon/max6650.c reg = i2c_smbus_read_byte_data(client, MAX6650_REG_DAC); reg 441 drivers/hwmon/max6650.c if (reg < 0) { reg 443 drivers/hwmon/max6650.c return reg; reg 445 drivers/hwmon/max6650.c data->dac = reg; reg 447 drivers/hwmon/max6650.c reg = i2c_smbus_read_byte_data(client, MAX6650_REG_COUNT); reg 448 drivers/hwmon/max6650.c if (reg < 0) { reg 450 drivers/hwmon/max6650.c return reg; reg 452 drivers/hwmon/max6650.c data->count = reg; reg 454 drivers/hwmon/max6650.c reg = i2c_smbus_read_byte_data(client, MAX6650_REG_ALARM_EN); reg 455 drivers/hwmon/max6650.c if (reg < 0) { reg 457 drivers/hwmon/max6650.c return reg; reg 459 drivers/hwmon/max6650.c data->alarm_en = reg; reg 615 drivers/hwmon/max6650.c u8 reg; reg 623 drivers/hwmon/max6650.c reg = pwm_to_dac(clamp_val(val, 0, 255), reg 626 drivers/hwmon/max6650.c MAX6650_REG_DAC, reg); reg 629 drivers/hwmon/max6650.c data->dac = reg; reg 649 drivers/hwmon/max6650.c reg = 0; reg 652 drivers/hwmon/max6650.c reg = 1; reg 655 drivers/hwmon/max6650.c reg = 2; reg 658 drivers/hwmon/max6650.c reg = 3; reg 665 drivers/hwmon/max6650.c MAX6650_REG_COUNT, reg); reg 668 drivers/hwmon/max6650.c data->count = reg; reg 41 drivers/hwmon/max6697.c #define MAX6697_MAP_BITS(reg) ((((reg) & 0x7e) >> 1) | \ reg 42 drivers/hwmon/max6697.c (((reg) & 0x01) << 6) | ((reg) & 0x80)) reg 508 drivers/hwmon/max6697.c int ret, reg; reg 516 drivers/hwmon/max6697.c reg = i2c_smbus_read_byte_data(client, MAX6697_REG_CONFIG); reg 517 drivers/hwmon/max6697.c if (reg < 0) reg 518 drivers/hwmon/max6697.c return reg; reg 520 drivers/hwmon/max6697.c if (reg & MAX6581_CONF_EXTENDED) reg 522 drivers/hwmon/max6697.c reg = i2c_smbus_read_byte_data(client, reg 524 drivers/hwmon/max6697.c if (reg < 0) reg 525 drivers/hwmon/max6697.c return reg; reg 526 drivers/hwmon/max6697.c factor += hweight8(reg); reg 528 drivers/hwmon/max6697.c if (reg & MAX6697_CONF_RESISTANCE) reg 540 drivers/hwmon/max6697.c reg = 0; reg 543 drivers/hwmon/max6697.c reg |= MAX6697_CONF_TIMEOUT; reg 547 drivers/hwmon/max6697.c reg |= MAX6581_CONF_EXTENDED; reg 552 drivers/hwmon/max6697.c reg |= MAX6697_CONF_RESISTANCE; reg 557 drivers/hwmon/max6697.c reg |= MAX6693_CONF_BETA; reg 560 drivers/hwmon/max6697.c ret = i2c_smbus_write_byte_data(client, MAX6697_REG_CONFIG, reg); reg 59 drivers/hwmon/mcp3021.c u16 reg; reg 69 drivers/hwmon/mcp3021.c reg = be16_to_cpu(buf); reg 75 drivers/hwmon/mcp3021.c reg = (reg >> data->sar_shift) & data->sar_mask; reg 77 drivers/hwmon/mcp3021.c return reg; reg 90 drivers/hwmon/mcp3021.c int reg, in_input; reg 92 drivers/hwmon/mcp3021.c reg = mcp3021_read16(client); reg 93 drivers/hwmon/mcp3021.c if (reg < 0) reg 94 drivers/hwmon/mcp3021.c return reg; reg 96 drivers/hwmon/mcp3021.c in_input = volts_from_reg(data, reg); reg 73 drivers/hwmon/mlxreg-fan.c u32 reg; reg 85 drivers/hwmon/mlxreg-fan.c u32 reg; reg 126 drivers/hwmon/mlxreg-fan.c err = regmap_read(fan->regmap, tacho->reg, ®val); reg 135 drivers/hwmon/mlxreg-fan.c err = regmap_read(fan->regmap, tacho->reg, ®val); reg 150 drivers/hwmon/mlxreg-fan.c err = regmap_read(fan->regmap, fan->pwm.reg, ®val); reg 182 drivers/hwmon/mlxreg-fan.c return regmap_write(fan->regmap, fan->pwm.reg, val); reg 277 drivers/hwmon/mlxreg-fan.c err = regmap_read(fan->regmap, fan->pwm.reg, ®val); reg 314 drivers/hwmon/mlxreg-fan.c err = regmap_read(fan->regmap, fan->pwm.reg, ®val); reg 332 drivers/hwmon/mlxreg-fan.c err = regmap_write(fan->regmap, fan->pwm.reg, reg 416 drivers/hwmon/mlxreg-fan.c fan->tacho[tacho_num].reg = data->reg; reg 425 drivers/hwmon/mlxreg-fan.c fan->pwm.reg = data->reg; reg 69 drivers/hwmon/nct6683.c superio_outb(int ioreg, int reg, int val) reg 71 drivers/hwmon/nct6683.c outb(reg, ioreg); reg 76 drivers/hwmon/nct6683.c superio_inb(int ioreg, int reg) reg 78 drivers/hwmon/nct6683.c outb(reg, ioreg); reg 475 drivers/hwmon/nct6683.c static inline long in_from_reg(u16 reg, u8 src) reg 482 drivers/hwmon/nct6683.c return reg * scale; reg 496 drivers/hwmon/nct6683.c static u16 nct6683_read(struct nct6683_data *data, u16 reg) reg 501 drivers/hwmon/nct6683.c outb_p(reg >> 8, data->addr + EC_PAGE_REG); reg 502 drivers/hwmon/nct6683.c outb_p(reg & 0xff, data->addr + EC_INDEX_REG); reg 507 drivers/hwmon/nct6683.c static u16 nct6683_read16(struct nct6683_data *data, u16 reg) reg 509 drivers/hwmon/nct6683.c return (nct6683_read(data, reg) << 8) | nct6683_read(data, reg + 1); reg 512 drivers/hwmon/nct6683.c static void nct6683_write(struct nct6683_data *data, u16 reg, u16 value) reg 515 drivers/hwmon/nct6683.c outb_p(reg >> 8, data->addr + EC_PAGE_REG); reg 516 drivers/hwmon/nct6683.c outb_p(reg & 0xff, data->addr + EC_INDEX_REG); reg 523 drivers/hwmon/nct6683.c int reg = -EINVAL; reg 527 drivers/hwmon/nct6683.c reg = NCT6683_REG_MON(ch); reg 531 drivers/hwmon/nct6683.c reg = NCT6683_REG_MON_LOW(ch); reg 535 drivers/hwmon/nct6683.c reg = NCT6683_REG_MON_HIGH(ch); reg 540 drivers/hwmon/nct6683.c return reg; reg 546 drivers/hwmon/nct6683.c int reg = -EINVAL; reg 553 drivers/hwmon/nct6683.c reg = NCT6683_REG_INTEL_TEMP_MAX(ch); reg 556 drivers/hwmon/nct6683.c reg = NCT6683_REG_INTEL_TEMP_CRIT(ch); reg 565 drivers/hwmon/nct6683.c reg = NCT6683_REG_MON_LOW(ch); reg 568 drivers/hwmon/nct6683.c reg = NCT6683_REG_TEMP_MAX(ch); reg 571 drivers/hwmon/nct6683.c reg = NCT6683_REG_TEMP_HYST(ch); reg 574 drivers/hwmon/nct6683.c reg = NCT6683_REG_MON_HIGH(ch); reg 579 drivers/hwmon/nct6683.c return reg; reg 605 drivers/hwmon/nct6683.c int reg = get_in_reg(data, j, i); reg 607 drivers/hwmon/nct6683.c if (reg >= 0) reg 609 drivers/hwmon/nct6683.c nct6683_read(data, reg); reg 620 drivers/hwmon/nct6683.c int reg = get_temp_reg(data, j, i); reg 622 drivers/hwmon/nct6683.c if (reg >= 0) reg 624 drivers/hwmon/nct6683.c nct6683_read(data, reg); reg 977 drivers/hwmon/nct6683.c u8 reg; reg 985 drivers/hwmon/nct6683.c reg = superio_inb(data->sioreg, NCT6683_REG_CR_BEEP); reg 990 drivers/hwmon/nct6683.c return sprintf(buf, "%u\n", !!(reg & NCT6683_CR_BEEP_MASK)); reg 1003 drivers/hwmon/nct6683.c u8 reg; reg 1018 drivers/hwmon/nct6683.c reg = superio_inb(data->sioreg, NCT6683_REG_CR_BEEP); reg 1020 drivers/hwmon/nct6683.c reg |= NCT6683_CR_BEEP_MASK; reg 1022 drivers/hwmon/nct6683.c reg &= ~NCT6683_CR_BEEP_MASK; reg 1023 drivers/hwmon/nct6683.c superio_outb(data->sioreg, NCT6683_REG_CR_BEEP, reg); reg 1038 drivers/hwmon/nct6683.c u8 reg; reg 1046 drivers/hwmon/nct6683.c reg = superio_inb(data->sioreg, NCT6683_REG_CR_CASEOPEN); reg 1051 drivers/hwmon/nct6683.c return sprintf(buf, "%u\n", !(reg & NCT6683_CR_CASEOPEN_MASK)); reg 1064 drivers/hwmon/nct6683.c u8 reg; reg 1084 drivers/hwmon/nct6683.c reg = superio_inb(data->sioreg, NCT6683_REG_CR_CASEOPEN); reg 1085 drivers/hwmon/nct6683.c reg |= NCT6683_CR_CASEOPEN_MASK; reg 1086 drivers/hwmon/nct6683.c superio_outb(data->sioreg, NCT6683_REG_CR_CASEOPEN, reg); reg 1087 drivers/hwmon/nct6683.c reg &= ~NCT6683_CR_CASEOPEN_MASK; reg 1088 drivers/hwmon/nct6683.c superio_outb(data->sioreg, NCT6683_REG_CR_CASEOPEN, reg); reg 1129 drivers/hwmon/nct6683.c u8 reg; reg 1132 drivers/hwmon/nct6683.c reg = nct6683_read(data, NCT6683_REG_FANIN_CFG(i)); reg 1133 drivers/hwmon/nct6683.c if (reg & 0x80) reg 1135 drivers/hwmon/nct6683.c data->fanin_cfg[i] = reg; reg 1138 drivers/hwmon/nct6683.c reg = nct6683_read(data, NCT6683_REG_FANOUT_CFG(i)); reg 1139 drivers/hwmon/nct6683.c if (reg & 0x80) reg 1141 drivers/hwmon/nct6683.c data->fanout_cfg[i] = reg; reg 1163 drivers/hwmon/nct6683.c u8 reg; reg 1169 drivers/hwmon/nct6683.c reg = nct6683_read(data, NCT6683_REG_MON_CFG(i)) & 0x7f; reg 1171 drivers/hwmon/nct6683.c if (reg >= NUM_MON_LABELS) reg 1174 drivers/hwmon/nct6683.c if (nct6683_mon_label[reg] == NULL) reg 1176 drivers/hwmon/nct6683.c if (reg < MON_VOLTAGE_START) { reg 1178 drivers/hwmon/nct6683.c data->temp_src[data->temp_num] = reg; reg 1182 drivers/hwmon/nct6683.c data->in_src[data->in_num] = reg; reg 137 drivers/hwmon/nct6775.c superio_outb(int ioreg, int reg, int val) reg 139 drivers/hwmon/nct6775.c outb(reg, ioreg); reg 144 drivers/hwmon/nct6775.c superio_inb(int ioreg, int reg) reg 146 drivers/hwmon/nct6775.c outb(reg, ioreg); reg 984 drivers/hwmon/nct6775.c static unsigned int step_time_from_reg(u8 reg, u8 mode) reg 986 drivers/hwmon/nct6775.c return mode ? 400 * reg : 100 * reg; reg 995 drivers/hwmon/nct6775.c static unsigned int fan_from_reg8(u16 reg, unsigned int divreg) reg 997 drivers/hwmon/nct6775.c if (reg == 0 || reg == 255) reg 999 drivers/hwmon/nct6775.c return 1350000U / (reg << divreg); reg 1002 drivers/hwmon/nct6775.c static unsigned int fan_from_reg13(u16 reg, unsigned int divreg) reg 1004 drivers/hwmon/nct6775.c if ((reg & 0xff1f) == 0xff1f) reg 1007 drivers/hwmon/nct6775.c reg = (reg & 0x1f) | ((reg & 0xff00) >> 3); reg 1009 drivers/hwmon/nct6775.c if (reg == 0) reg 1012 drivers/hwmon/nct6775.c return 1350000U / reg; reg 1015 drivers/hwmon/nct6775.c static unsigned int fan_from_reg16(u16 reg, unsigned int divreg) reg 1017 drivers/hwmon/nct6775.c if (reg == 0 || reg == 0xffff) reg 1024 drivers/hwmon/nct6775.c return 1350000U / (reg << divreg); reg 1027 drivers/hwmon/nct6775.c static unsigned int fan_from_reg_rpm(u16 reg, unsigned int divreg) reg 1029 drivers/hwmon/nct6775.c return reg; reg 1041 drivers/hwmon/nct6775.c div_from_reg(u8 reg) reg 1043 drivers/hwmon/nct6775.c return BIT(reg); reg 1055 drivers/hwmon/nct6775.c static inline long in_from_reg(u8 reg, u8 nr) reg 1057 drivers/hwmon/nct6775.c return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100); reg 1136 drivers/hwmon/nct6775.c unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg); reg 1137 drivers/hwmon/nct6775.c unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg); reg 1356 drivers/hwmon/nct6775.c static bool is_word_sized(struct nct6775_data *data, u16 reg) reg 1360 drivers/hwmon/nct6775.c return reg == 0x20 || reg == 0x22 || reg == 0x24 || reg 1361 drivers/hwmon/nct6775.c reg == 0xe0 || reg == 0xe2 || reg == 0xe4 || reg 1362 drivers/hwmon/nct6775.c reg == 0x111 || reg == 0x121 || reg == 0x131; reg 1364 drivers/hwmon/nct6775.c return reg == 0x20 || reg == 0x22 || reg == 0x24 || reg 1365 drivers/hwmon/nct6775.c reg == 0x26 || reg == 0x28 || reg == 0xe0 || reg == 0xe2 || reg 1366 drivers/hwmon/nct6775.c reg == 0xe4 || reg == 0xe6 || reg == 0xe8 || reg == 0x111 || reg 1367 drivers/hwmon/nct6775.c reg == 0x121 || reg == 0x131 || reg == 0x191 || reg == 0x1a1; reg 1369 drivers/hwmon/nct6775.c return (((reg & 0xff00) == 0x100 || reg 1370 drivers/hwmon/nct6775.c (reg & 0xff00) == 0x200) && reg 1371 drivers/hwmon/nct6775.c ((reg & 0x00ff) == 0x50 || reg 1372 drivers/hwmon/nct6775.c (reg & 0x00ff) == 0x53 || reg 1373 drivers/hwmon/nct6775.c (reg & 0x00ff) == 0x55)) || reg 1374 drivers/hwmon/nct6775.c (reg & 0xfff0) == 0x630 || reg 1375 drivers/hwmon/nct6775.c reg == 0x640 || reg == 0x642 || reg 1376 drivers/hwmon/nct6775.c reg == 0x662 || reg 1377 drivers/hwmon/nct6775.c ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) || reg 1378 drivers/hwmon/nct6775.c reg == 0x73 || reg == 0x75 || reg == 0x77; reg 1380 drivers/hwmon/nct6775.c return (((reg & 0xff00) == 0x100 || reg 1381 drivers/hwmon/nct6775.c (reg & 0xff00) == 0x200) && reg 1382 drivers/hwmon/nct6775.c ((reg & 0x00ff) == 0x50 || reg 1383 drivers/hwmon/nct6775.c (reg & 0x00ff) == 0x53 || reg 1384 drivers/hwmon/nct6775.c (reg & 0x00ff) == 0x55)) || reg 1385 drivers/hwmon/nct6775.c (reg & 0xfff0) == 0x630 || reg 1386 drivers/hwmon/nct6775.c reg == 0x402 || reg 1387 drivers/hwmon/nct6775.c reg == 0x640 || reg == 0x642 || reg 1388 drivers/hwmon/nct6775.c ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) || reg 1389 drivers/hwmon/nct6775.c reg == 0x73 || reg == 0x75 || reg == 0x77; reg 1398 drivers/hwmon/nct6775.c return reg == 0x150 || reg == 0x153 || reg == 0x155 || reg 1399 drivers/hwmon/nct6775.c (reg & 0xfff0) == 0x4c0 || reg 1400 drivers/hwmon/nct6775.c reg == 0x402 || reg 1401 drivers/hwmon/nct6775.c reg == 0x63a || reg == 0x63c || reg == 0x63e || reg 1402 drivers/hwmon/nct6775.c reg == 0x640 || reg == 0x642 || reg == 0x64a || reg 1403 drivers/hwmon/nct6775.c reg == 0x64c || reg 1404 drivers/hwmon/nct6775.c reg == 0x73 || reg == 0x75 || reg == 0x77 || reg == 0x79 || reg 1405 drivers/hwmon/nct6775.c reg == 0x7b || reg == 0x7d; reg 1416 drivers/hwmon/nct6775.c static inline void nct6775_set_bank(struct nct6775_data *data, u16 reg) reg 1418 drivers/hwmon/nct6775.c u8 bank = reg >> 8; reg 1427 drivers/hwmon/nct6775.c static u16 nct6775_read_value(struct nct6775_data *data, u16 reg) reg 1429 drivers/hwmon/nct6775.c int res, word_sized = is_word_sized(data, reg); reg 1431 drivers/hwmon/nct6775.c nct6775_set_bank(data, reg); reg 1432 drivers/hwmon/nct6775.c outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET); reg 1435 drivers/hwmon/nct6775.c outb_p((reg & 0xff) + 1, reg 1442 drivers/hwmon/nct6775.c static int nct6775_write_value(struct nct6775_data *data, u16 reg, u16 value) reg 1444 drivers/hwmon/nct6775.c int word_sized = is_word_sized(data, reg); reg 1446 drivers/hwmon/nct6775.c nct6775_set_bank(data, reg); reg 1447 drivers/hwmon/nct6775.c outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET); reg 1450 drivers/hwmon/nct6775.c outb_p((reg & 0xff) + 1, reg 1458 drivers/hwmon/nct6775.c static u16 nct6775_read_temp(struct nct6775_data *data, u16 reg) reg 1462 drivers/hwmon/nct6775.c res = nct6775_read_value(data, reg); reg 1463 drivers/hwmon/nct6775.c if (!is_word_sized(data, reg)) reg 1469 drivers/hwmon/nct6775.c static int nct6775_write_temp(struct nct6775_data *data, u16 reg, u16 value) reg 1471 drivers/hwmon/nct6775.c if (!is_word_sized(data, reg)) reg 1473 drivers/hwmon/nct6775.c return nct6775_write_value(data, reg, value); reg 1479 drivers/hwmon/nct6775.c u8 reg; reg 1483 drivers/hwmon/nct6775.c reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x70) reg 1485 drivers/hwmon/nct6775.c nct6775_write_value(data, NCT6775_REG_FANDIV1, reg); reg 1488 drivers/hwmon/nct6775.c reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x7) reg 1490 drivers/hwmon/nct6775.c nct6775_write_value(data, NCT6775_REG_FANDIV1, reg); reg 1493 drivers/hwmon/nct6775.c reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x70) reg 1495 drivers/hwmon/nct6775.c nct6775_write_value(data, NCT6775_REG_FANDIV2, reg); reg 1498 drivers/hwmon/nct6775.c reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x7) reg 1500 drivers/hwmon/nct6775.c nct6775_write_value(data, NCT6775_REG_FANDIV2, reg); reg 1555 drivers/hwmon/nct6775.c u8 reg; reg 1566 drivers/hwmon/nct6775.c reg = nct6775_read_value(data, data->REG_FAN_MIN[i]); reg 1567 drivers/hwmon/nct6775.c if (!reg) reg 1576 drivers/hwmon/nct6775.c struct nct6775_data *data, int nr, u16 reg) reg 1589 drivers/hwmon/nct6775.c if (reg == 0x00 && fan_div < 0x07) reg 1591 drivers/hwmon/nct6775.c else if (reg != 0x00 && reg < 0x30 && fan_div > 0) reg 1627 drivers/hwmon/nct6775.c int fanmodecfg, reg; reg 1669 drivers/hwmon/nct6775.c reg = nct6775_read_value(data, data->REG_TEMP_SEL[i]); reg 1670 drivers/hwmon/nct6775.c data->pwm_temp_sel[i] = reg & 0x1f; reg 1672 drivers/hwmon/nct6775.c if (reg & 0x80) reg 1678 drivers/hwmon/nct6775.c reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[i]); reg 1679 drivers/hwmon/nct6775.c data->pwm_weight_temp_sel[i] = reg & 0x1f; reg 1681 drivers/hwmon/nct6775.c if (!(reg & 0x80)) reg 1697 drivers/hwmon/nct6775.c u8 reg; reg 1738 drivers/hwmon/nct6775.c reg = nct6775_read_value(data, reg 1741 drivers/hwmon/nct6775.c (reg & 0x02) ? 0xff : 0x00; reg 1756 drivers/hwmon/nct6775.c reg = nct6775_read_value(data, reg 1758 drivers/hwmon/nct6775.c if (reg & data->CRITICAL_PWM_ENABLE_MASK) reg 1759 drivers/hwmon/nct6775.c reg = nct6775_read_value(data, reg 1762 drivers/hwmon/nct6775.c reg = 0xff; reg 1763 drivers/hwmon/nct6775.c data->auto_pwm[i][data->auto_pwm_num] = reg; reg 1796 drivers/hwmon/nct6775.c u16 reg; reg 1801 drivers/hwmon/nct6775.c reg = nct6775_read_value(data, data->REG_FAN[i]); reg 1802 drivers/hwmon/nct6775.c data->rpm[i] = data->fan_from_reg(reg, reg 1816 drivers/hwmon/nct6775.c nct6775_select_fan_div(dev, data, i, reg); reg 2128 drivers/hwmon/nct6775.c unsigned int reg; reg 2157 drivers/hwmon/nct6775.c reg = 1350000U / val; reg 2158 drivers/hwmon/nct6775.c if (reg >= 128 * 255) { reg 2168 drivers/hwmon/nct6775.c } else if (!reg) { reg 2185 drivers/hwmon/nct6775.c while (reg > 192 && new_div < 7) { reg 2186 drivers/hwmon/nct6775.c reg >>= 1; reg 2189 drivers/hwmon/nct6775.c data->fan_min[nr] = reg; reg 2233 drivers/hwmon/nct6775.c u8 reg; reg 2244 drivers/hwmon/nct6775.c reg = nct6775_read_value(data, data->REG_FAN_PULSES[nr]); reg 2245 drivers/hwmon/nct6775.c reg &= ~(0x03 << data->FAN_PULSE_SHIFT[nr]); reg 2246 drivers/hwmon/nct6775.c reg |= (val & 3) << data->FAN_PULSE_SHIFT[nr]; reg 2247 drivers/hwmon/nct6775.c nct6775_write_value(data, data->REG_FAN_PULSES[nr], reg); reg 2540 drivers/hwmon/nct6775.c u8 reg; reg 2558 drivers/hwmon/nct6775.c reg = nct6775_read_value(data, data->REG_PWM_MODE[nr]); reg 2559 drivers/hwmon/nct6775.c reg &= ~data->PWM_MODE_MASK[nr]; reg 2561 drivers/hwmon/nct6775.c reg |= data->PWM_MODE_MASK[nr]; reg 2562 drivers/hwmon/nct6775.c nct6775_write_value(data, data->REG_PWM_MODE[nr], reg); reg 2601 drivers/hwmon/nct6775.c u8 reg; reg 2612 drivers/hwmon/nct6775.c reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]); reg 2613 drivers/hwmon/nct6775.c reg &= 0x7f; reg 2615 drivers/hwmon/nct6775.c reg |= 0x80; reg 2616 drivers/hwmon/nct6775.c nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg); reg 2648 drivers/hwmon/nct6775.c u8 reg; reg 2655 drivers/hwmon/nct6775.c reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]); reg 2656 drivers/hwmon/nct6775.c reg = (reg & ~data->tolerance_mask) | reg 2658 drivers/hwmon/nct6775.c nct6775_write_value(data, data->REG_FAN_MODE[nr], reg); reg 2662 drivers/hwmon/nct6775.c reg = (data->target_speed[nr] >> 8) & 0x0f; reg 2663 drivers/hwmon/nct6775.c reg |= (data->target_speed_tolerance[nr] & 0x38) << 1; reg 2666 drivers/hwmon/nct6775.c reg); reg 2674 drivers/hwmon/nct6775.c reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]); reg 2675 drivers/hwmon/nct6775.c reg = (reg & ~data->tolerance_mask) | reg 2677 drivers/hwmon/nct6775.c nct6775_write_value(data, data->REG_FAN_MODE[nr], reg); reg 2700 drivers/hwmon/nct6775.c u16 reg; reg 2728 drivers/hwmon/nct6775.c reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]); reg 2729 drivers/hwmon/nct6775.c reg &= 0x0f; reg 2730 drivers/hwmon/nct6775.c reg |= pwm_enable_to_reg(val) << 4; reg 2731 drivers/hwmon/nct6775.c nct6775_write_value(data, data->REG_FAN_MODE[nr], reg); reg 2771 drivers/hwmon/nct6775.c int err, reg, src; reg 2784 drivers/hwmon/nct6775.c reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]); reg 2785 drivers/hwmon/nct6775.c reg &= 0xe0; reg 2786 drivers/hwmon/nct6775.c reg |= src; reg 2787 drivers/hwmon/nct6775.c nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg); reg 2813 drivers/hwmon/nct6775.c int err, reg, src; reg 2829 drivers/hwmon/nct6775.c reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]); reg 2830 drivers/hwmon/nct6775.c reg &= 0xe0; reg 2831 drivers/hwmon/nct6775.c reg |= (src | 0x80); reg 2832 drivers/hwmon/nct6775.c nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg); reg 2835 drivers/hwmon/nct6775.c reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]); reg 2836 drivers/hwmon/nct6775.c reg &= 0x7f; reg 2837 drivers/hwmon/nct6775.c nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg); reg 3147 drivers/hwmon/nct6775.c u8 reg; reg 3172 drivers/hwmon/nct6775.c reg = nct6775_read_value(data, reg 3175 drivers/hwmon/nct6775.c reg |= 0x02; reg 3177 drivers/hwmon/nct6775.c reg &= ~0x02; reg 3179 drivers/hwmon/nct6775.c reg); reg 3195 drivers/hwmon/nct6775.c reg = nct6775_read_value(data, reg 3198 drivers/hwmon/nct6775.c reg &= ~data->CRITICAL_PWM_ENABLE_MASK; reg 3200 drivers/hwmon/nct6775.c reg |= data->CRITICAL_PWM_ENABLE_MASK; reg 3203 drivers/hwmon/nct6775.c reg); reg 3415 drivers/hwmon/nct6775.c u8 reg; reg 3435 drivers/hwmon/nct6775.c reg = superio_inb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr]); reg 3436 drivers/hwmon/nct6775.c reg |= NCT6775_CR_CASEOPEN_CLR_MASK[nr]; reg 3437 drivers/hwmon/nct6775.c superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg); reg 3438 drivers/hwmon/nct6775.c reg &= ~NCT6775_CR_CASEOPEN_CLR_MASK[nr]; reg 3439 drivers/hwmon/nct6775.c superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg); reg 4648 drivers/hwmon/nct6775.c u8 reg; reg 4658 drivers/hwmon/nct6775.c reg = superio_inb(sioreg, SIO_REG_ENABLE); reg 4659 drivers/hwmon/nct6775.c if (reg != data->sio_reg_enable) reg 158 drivers/hwmon/nct7802.c unsigned int reg, enabled; reg 161 drivers/hwmon/nct7802.c ret = regmap_read(data->regmap, REG_SMARTFAN_EN(sattr->index), ®); reg 164 drivers/hwmon/nct7802.c enabled = reg >> SMARTFAN_EN_SHIFT(sattr->index) & 1; reg 684 drivers/hwmon/nct7802.c unsigned int reg; reg 687 drivers/hwmon/nct7802.c err = regmap_read(data->regmap, REG_MODE, ®); reg 692 drivers/hwmon/nct7802.c (reg & 03) != 0x01 && (reg & 0x03) != 0x02) /* RD1 */ reg 696 drivers/hwmon/nct7802.c (reg & 0x0c) != 0x04 && (reg & 0x0c) != 0x08) /* RD2 */ reg 698 drivers/hwmon/nct7802.c if (index >= 20 && index < 30 && (reg & 0x30) != 0x20) /* RD3 */ reg 704 drivers/hwmon/nct7802.c err = regmap_read(data->regmap, REG_PECI_ENABLE, ®); reg 708 drivers/hwmon/nct7802.c if (index >= 38 && index < 46 && !(reg & 0x01)) /* PECI 0 */ reg 711 drivers/hwmon/nct7802.c if (index >= 0x46 && (!(reg & 0x02))) /* PECI 1 */ reg 783 drivers/hwmon/nct7802.c unsigned int reg; reg 789 drivers/hwmon/nct7802.c err = regmap_read(data->regmap, REG_MODE, ®); reg 793 drivers/hwmon/nct7802.c if (index >= 6 && index < 11 && (reg & 0x03) != 0x03) /* VSEN1 */ reg 795 drivers/hwmon/nct7802.c if (index >= 11 && index < 16 && (reg & 0x0c) != 0x0c) /* VSEN2 */ reg 797 drivers/hwmon/nct7802.c if (index >= 16 && (reg & 0x30) != 0x30) /* VSEN3 */ reg 859 drivers/hwmon/nct7802.c unsigned int reg; reg 862 drivers/hwmon/nct7802.c err = regmap_read(data->regmap, REG_FAN_ENABLE, ®); reg 863 drivers/hwmon/nct7802.c if (err < 0 || !(reg & (1 << fan))) reg 989 drivers/hwmon/nct7802.c int reg; reg 995 drivers/hwmon/nct7802.c reg = i2c_smbus_read_byte_data(client, REG_BANK); reg 996 drivers/hwmon/nct7802.c if (reg != 0x00) reg 999 drivers/hwmon/nct7802.c reg = i2c_smbus_read_byte_data(client, REG_VENDOR_ID); reg 1000 drivers/hwmon/nct7802.c if (reg != 0x50) reg 1003 drivers/hwmon/nct7802.c reg = i2c_smbus_read_byte_data(client, REG_CHIP_ID); reg 1004 drivers/hwmon/nct7802.c if (reg != 0xc3) reg 1007 drivers/hwmon/nct7802.c reg = i2c_smbus_read_byte_data(client, REG_VERSION_ID); reg 1008 drivers/hwmon/nct7802.c if (reg < 0 || (reg & 0xf0) != 0x20) reg 1012 drivers/hwmon/nct7802.c reg = i2c_smbus_read_byte_data(client, REG_TEMP_LSB); reg 1013 drivers/hwmon/nct7802.c if (reg < 0 || (reg & 0x1f)) reg 1016 drivers/hwmon/nct7802.c reg = i2c_smbus_read_byte_data(client, REG_TEMP_PECI_LSB); reg 1017 drivers/hwmon/nct7802.c if (reg < 0 || (reg & 0x3f)) reg 1020 drivers/hwmon/nct7802.c reg = i2c_smbus_read_byte_data(client, REG_VOLTAGE_LOW); reg 1021 drivers/hwmon/nct7802.c if (reg < 0 || (reg & 0x3f)) reg 1028 drivers/hwmon/nct7802.c static bool nct7802_regmap_is_volatile(struct device *dev, unsigned int reg) reg 1030 drivers/hwmon/nct7802.c return (reg != REG_BANK && reg <= 0x20) || reg 1031 drivers/hwmon/nct7802.c (reg >= REG_PWM(0) && reg <= REG_PWM(2)); reg 133 drivers/hwmon/nct7904.c unsigned int bank, unsigned int reg) reg 140 drivers/hwmon/nct7904.c ret = i2c_smbus_read_byte_data(client, reg); reg 151 drivers/hwmon/nct7904.c unsigned int bank, unsigned int reg) reg 158 drivers/hwmon/nct7904.c ret = i2c_smbus_read_byte_data(client, reg); reg 161 drivers/hwmon/nct7904.c ret = i2c_smbus_read_byte_data(client, reg + 1); reg 173 drivers/hwmon/nct7904.c unsigned int bank, unsigned int reg, u8 val) reg 180 drivers/hwmon/nct7904.c ret = i2c_smbus_write_byte_data(client, reg, val); reg 75 drivers/hwmon/pc87360.c static inline void superio_outb(int sioaddr, int reg, int val) reg 77 drivers/hwmon/pc87360.c outb(reg, sioaddr); reg 81 drivers/hwmon/pc87360.c static inline int superio_inb(int sioaddr, int reg) reg 83 drivers/hwmon/pc87360.c outb(reg, sioaddr); reg 221 drivers/hwmon/pc87360.c u8 reg); reg 223 drivers/hwmon/pc87360.c u8 reg, u8 value); reg 1362 drivers/hwmon/pc87360.c u8 reg) reg 1369 drivers/hwmon/pc87360.c res = inb_p(data->address[ldi] + reg); reg 1376 drivers/hwmon/pc87360.c u8 reg, u8 value) reg 1381 drivers/hwmon/pc87360.c outb_p(value, data->address[ldi] + reg); reg 1402 drivers/hwmon/pc87360.c u8 reg; reg 1405 drivers/hwmon/pc87360.c reg = pc87360_read_value(data, LD_IN, NO_BANK, reg 1411 drivers/hwmon/pc87360.c (reg & 0xC0) | 0x11); reg 1416 drivers/hwmon/pc87360.c reg = pc87360_read_value(data, LD_IN, i, reg 1418 drivers/hwmon/pc87360.c dev_dbg(&pdev->dev, "bios in%d status:0x%02x\n", i, reg); reg 1421 drivers/hwmon/pc87360.c if (!(reg & CHAN_ENA)) { reg 1426 drivers/hwmon/pc87360.c (reg & 0x68) | 0x87); reg 1437 drivers/hwmon/pc87360.c reg = pc87360_read_value(data, LD_IN, i, reg 1439 drivers/hwmon/pc87360.c use_thermistors = use_thermistors || (reg & CHAN_ENA); reg 1441 drivers/hwmon/pc87360.c dev_dbg(&pdev->dev, "bios temp%d_status:0x%02x\n", i-7, reg); reg 1447 drivers/hwmon/pc87360.c reg = pc87360_read_value(data, LD_TEMP, i, reg 1449 drivers/hwmon/pc87360.c dev_dbg(&pdev->dev, "bios temp%d_status:0x%02x\n", i + 1, reg); reg 1452 drivers/hwmon/pc87360.c if (!(reg & CHAN_ENA)) { reg 1469 drivers/hwmon/pc87360.c reg = pc87360_read_value(data, LD_TEMP, reg 1471 drivers/hwmon/pc87360.c if (reg & CHAN_ENA) { reg 1479 drivers/hwmon/pc87360.c reg = pc87360_read_value(data, LD_IN, i, reg 1481 drivers/hwmon/pc87360.c if (!(reg & CHAN_ENA)) { reg 1487 drivers/hwmon/pc87360.c (reg & 0x60) | 0x8F); reg 1494 drivers/hwmon/pc87360.c reg = pc87360_read_value(data, LD_IN, NO_BANK, reg 1496 drivers/hwmon/pc87360.c dev_dbg(&pdev->dev, "bios vin-cfg:0x%02x\n", reg); reg 1497 drivers/hwmon/pc87360.c if (reg & CHAN_ENA) { reg 1502 drivers/hwmon/pc87360.c reg & 0xFE); reg 1507 drivers/hwmon/pc87360.c reg = pc87360_read_value(data, LD_TEMP, NO_BANK, reg 1509 drivers/hwmon/pc87360.c dev_dbg(&pdev->dev, "bios temp-cfg:0x%02x\n", reg); reg 1510 drivers/hwmon/pc87360.c if (reg & CHAN_ENA) { reg 1515 drivers/hwmon/pc87360.c reg & 0xFE); reg 108 drivers/hwmon/pc87427.c static inline void superio_outb(int sioaddr, int reg, int val) reg 110 drivers/hwmon/pc87427.c outb(reg, sioaddr); reg 114 drivers/hwmon/pc87427.c static inline int superio_inb(int sioaddr, int reg) reg 116 drivers/hwmon/pc87427.c outb(reg, sioaddr); reg 144 drivers/hwmon/pc87427.c static inline int pc87427_read8(struct pc87427_data *data, u8 ldi, u8 reg) reg 146 drivers/hwmon/pc87427.c return inb(data->address[ldi] + reg); reg 151 drivers/hwmon/pc87427.c u8 bank, u8 reg) reg 154 drivers/hwmon/pc87427.c return inb(data->address[ldi] + reg); reg 159 drivers/hwmon/pc87427.c u8 bank, u8 reg, u8 value) reg 162 drivers/hwmon/pc87427.c outb(value, data->address[ldi] + reg); reg 200 drivers/hwmon/pc87427.c static inline unsigned long fan_from_reg(u16 reg) reg 202 drivers/hwmon/pc87427.c reg &= 0xfffc; reg 203 drivers/hwmon/pc87427.c if (reg == 0x0000 || reg == 0xfffc) reg 205 drivers/hwmon/pc87427.c return 5400000UL / reg; reg 248 drivers/hwmon/pc87427.c static inline int pwm_enable_from_reg(u8 reg) reg 250 drivers/hwmon/pc87427.c switch (reg & PWM_ENABLE_MODE_MASK) { reg 318 drivers/hwmon/pc87427.c static inline unsigned int temp_type_from_reg(u8 reg) reg 320 drivers/hwmon/pc87427.c switch (reg & TEMP_TYPE_MASK) { reg 335 drivers/hwmon/pc87427.c static inline long temp_from_reg(s16 reg) reg 337 drivers/hwmon/pc87427.c return reg * 1000 / 256; reg 340 drivers/hwmon/pc87427.c static inline long temp_from_reg8(s8 reg) reg 342 drivers/hwmon/pc87427.c return reg * 1000; reg 964 drivers/hwmon/pc87427.c u8 reg; reg 967 drivers/hwmon/pc87427.c reg = pc87427_read8(data, LD_FAN, PC87427_REG_BANK); reg 968 drivers/hwmon/pc87427.c if (!(reg & 0x80)) reg 975 drivers/hwmon/pc87427.c reg = pc87427_read8_bank(data, LD_FAN, BANK_FM(i), reg 977 drivers/hwmon/pc87427.c if (reg & FAN_STATUS_MONEN) reg 997 drivers/hwmon/pc87427.c reg = pc87427_read8_bank(data, LD_FAN, BANK_FC(i), reg 999 drivers/hwmon/pc87427.c if (reg & PWM_ENABLE_CTLEN) reg 1007 drivers/hwmon/pc87427.c if ((reg & PWM_ENABLE_MODE_MASK) == PWM_MODE_AUTO) { reg 1015 drivers/hwmon/pc87427.c reg = pc87427_read8(data, LD_TEMP, PC87427_REG_BANK); reg 1016 drivers/hwmon/pc87427.c if (!(reg & 0x80)) reg 1021 drivers/hwmon/pc87427.c reg = pc87427_read8_bank(data, LD_TEMP, BANK_TM(i), reg 1023 drivers/hwmon/pc87427.c if (reg & TEMP_STATUS_CHANEN) reg 64 drivers/hwmon/pcf8591.c #define REG_TO_SIGNED(reg) (((reg) & 0x80) ? ((reg) - 256) : (reg)) reg 229 drivers/hwmon/pmbus/adm1275.c static int adm1275_read_word_data(struct i2c_client *client, int page, int reg) reg 238 drivers/hwmon/pmbus/adm1275.c switch (reg) { reg 329 drivers/hwmon/pmbus/adm1275.c static int adm1275_write_word_data(struct i2c_client *client, int page, int reg, reg 339 drivers/hwmon/pmbus/adm1275.c switch (reg) { reg 386 drivers/hwmon/pmbus/adm1275.c static int adm1275_read_byte_data(struct i2c_client *client, int page, int reg) reg 395 drivers/hwmon/pmbus/adm1275.c switch (reg) { reg 219 drivers/hwmon/pmbus/ibm-cffps.c int reg) reg 223 drivers/hwmon/pmbus/ibm-cffps.c switch (reg) { reg 228 drivers/hwmon/pmbus/ibm-cffps.c rc = pmbus_read_byte_data(client, page, reg); reg 242 drivers/hwmon/pmbus/ibm-cffps.c if (reg == PMBUS_STATUS_FAN_12) { reg 245 drivers/hwmon/pmbus/ibm-cffps.c } else if (reg == PMBUS_STATUS_TEMPERATURE) { reg 248 drivers/hwmon/pmbus/ibm-cffps.c } else if (reg == PMBUS_STATUS_VOUT) { reg 253 drivers/hwmon/pmbus/ibm-cffps.c } else if (reg == PMBUS_STATUS_IOUT) { reg 269 drivers/hwmon/pmbus/ibm-cffps.c int reg) reg 273 drivers/hwmon/pmbus/ibm-cffps.c switch (reg) { reg 275 drivers/hwmon/pmbus/ibm-cffps.c rc = pmbus_read_word_data(client, page, reg); reg 57 drivers/hwmon/pmbus/inspur-ipsps.c u8 reg; reg 64 drivers/hwmon/pmbus/inspur-ipsps.c reg = ipsps_regs[attr->index]; reg 65 drivers/hwmon/pmbus/inspur-ipsps.c rc = i2c_smbus_read_block_data(client, reg, data); reg 80 drivers/hwmon/pmbus/inspur-ipsps.c u8 reg; reg 86 drivers/hwmon/pmbus/inspur-ipsps.c reg = ipsps_regs[attr->index]; reg 87 drivers/hwmon/pmbus/inspur-ipsps.c rc = i2c_smbus_read_block_data(client, reg, data); reg 102 drivers/hwmon/pmbus/inspur-ipsps.c u8 reg; reg 107 drivers/hwmon/pmbus/inspur-ipsps.c reg = ipsps_regs[attr->index]; reg 108 drivers/hwmon/pmbus/inspur-ipsps.c rc = i2c_smbus_read_byte_data(client, reg); reg 134 drivers/hwmon/pmbus/inspur-ipsps.c u8 reg; reg 139 drivers/hwmon/pmbus/inspur-ipsps.c reg = ipsps_regs[attr->index]; reg 141 drivers/hwmon/pmbus/inspur-ipsps.c rc = i2c_smbus_write_byte_data(client, reg, reg 147 drivers/hwmon/pmbus/inspur-ipsps.c rc = i2c_smbus_write_byte_data(client, reg, reg 24 drivers/hwmon/pmbus/ir35221.c static int ir35221_read_word_data(struct i2c_client *client, int page, int reg) reg 28 drivers/hwmon/pmbus/ir35221.c switch (reg) { reg 214 drivers/hwmon/pmbus/lm25066.c static int lm25066_read_word_data(struct i2c_client *client, int page, int reg) reg 220 drivers/hwmon/pmbus/lm25066.c switch (reg) { reg 291 drivers/hwmon/pmbus/lm25066.c static int lm25056_read_word_data(struct i2c_client *client, int page, int reg) reg 295 drivers/hwmon/pmbus/lm25066.c switch (reg) { reg 313 drivers/hwmon/pmbus/lm25066.c ret = lm25066_read_word_data(client, page, reg); reg 319 drivers/hwmon/pmbus/lm25066.c static int lm25056_read_byte_data(struct i2c_client *client, int page, int reg) reg 323 drivers/hwmon/pmbus/lm25066.c switch (reg) { reg 343 drivers/hwmon/pmbus/lm25066.c static int lm25066_write_word_data(struct i2c_client *client, int page, int reg, reg 350 drivers/hwmon/pmbus/lm25066.c switch (reg) { reg 362 drivers/hwmon/pmbus/lm25066.c ret = pmbus_write_word_data(client, 0, reg, word); reg 154 drivers/hwmon/pmbus/ltc2978.c static int ltc_read_word_data(struct i2c_client *client, int page, int reg) reg 162 drivers/hwmon/pmbus/ltc2978.c return pmbus_read_word_data(client, page, reg); reg 165 drivers/hwmon/pmbus/ltc2978.c static int ltc_read_byte_data(struct i2c_client *client, int page, int reg) reg 173 drivers/hwmon/pmbus/ltc2978.c return pmbus_read_byte_data(client, page, reg); reg 201 drivers/hwmon/pmbus/ltc2978.c int page, int reg, u16 *pmax) reg 205 drivers/hwmon/pmbus/ltc2978.c ret = ltc_read_word_data(client, page, reg); reg 215 drivers/hwmon/pmbus/ltc2978.c int page, int reg, u16 *pmin) reg 219 drivers/hwmon/pmbus/ltc2978.c ret = ltc_read_word_data(client, page, reg); reg 229 drivers/hwmon/pmbus/ltc2978.c int reg) reg 235 drivers/hwmon/pmbus/ltc2978.c switch (reg) { reg 272 drivers/hwmon/pmbus/ltc2978.c static int ltc2978_read_word_data(struct i2c_client *client, int page, int reg) reg 278 drivers/hwmon/pmbus/ltc2978.c switch (reg) { reg 311 drivers/hwmon/pmbus/ltc2978.c ret = ltc2978_read_word_data_common(client, page, reg); reg 317 drivers/hwmon/pmbus/ltc2978.c static int ltc2974_read_word_data(struct i2c_client *client, int page, int reg) reg 323 drivers/hwmon/pmbus/ltc2978.c switch (reg) { reg 336 drivers/hwmon/pmbus/ltc2978.c ret = ltc2978_read_word_data(client, page, reg); reg 342 drivers/hwmon/pmbus/ltc2978.c static int ltc2975_read_word_data(struct i2c_client *client, int page, int reg) reg 348 drivers/hwmon/pmbus/ltc2978.c switch (reg) { reg 370 drivers/hwmon/pmbus/ltc2978.c ret = ltc2978_read_word_data(client, page, reg); reg 376 drivers/hwmon/pmbus/ltc2978.c static int ltc3880_read_word_data(struct i2c_client *client, int page, int reg) reg 382 drivers/hwmon/pmbus/ltc2978.c switch (reg) { reg 402 drivers/hwmon/pmbus/ltc2978.c ret = ltc2978_read_word_data_common(client, page, reg); reg 408 drivers/hwmon/pmbus/ltc2978.c static int ltc3883_read_word_data(struct i2c_client *client, int page, int reg) reg 414 drivers/hwmon/pmbus/ltc2978.c switch (reg) { reg 423 drivers/hwmon/pmbus/ltc2978.c ret = ltc3880_read_word_data(client, page, reg); reg 443 drivers/hwmon/pmbus/ltc2978.c int reg, u16 word) reg 449 drivers/hwmon/pmbus/ltc2978.c switch (reg) { reg 27 drivers/hwmon/pmbus/ltc3815.c static int ltc3815_read_byte_data(struct i2c_client *client, int page, int reg) reg 31 drivers/hwmon/pmbus/ltc3815.c switch (reg) { reg 48 drivers/hwmon/pmbus/ltc3815.c static int ltc3815_write_byte(struct i2c_client *client, int page, u8 reg) reg 52 drivers/hwmon/pmbus/ltc3815.c switch (reg) { reg 72 drivers/hwmon/pmbus/ltc3815.c static int ltc3815_read_word_data(struct i2c_client *client, int page, int reg) reg 76 drivers/hwmon/pmbus/ltc3815.c switch (reg) { reg 107 drivers/hwmon/pmbus/ltc3815.c int reg, u16 word) reg 111 drivers/hwmon/pmbus/ltc3815.c switch (reg) { reg 18 drivers/hwmon/pmbus/max16064.c static int max16064_read_word_data(struct i2c_client *client, int page, int reg) reg 22 drivers/hwmon/pmbus/max16064.c switch (reg) { reg 43 drivers/hwmon/pmbus/max16064.c int reg, u16 word) reg 47 drivers/hwmon/pmbus/max16064.c switch (reg) { reg 27 drivers/hwmon/pmbus/max31785.c int reg) reg 32 drivers/hwmon/pmbus/max31785.c switch (reg) { reg 37 drivers/hwmon/pmbus/max31785.c reg); reg 52 drivers/hwmon/pmbus/max31785.c int reg, u32 *data) reg 73 drivers/hwmon/pmbus/max31785.c cmdbuf[0] = reg; reg 129 drivers/hwmon/pmbus/max31785.c int reg) reg 134 drivers/hwmon/pmbus/max31785.c switch (reg) { reg 140 drivers/hwmon/pmbus/max31785.c reg, &val); reg 223 drivers/hwmon/pmbus/max31785.c int reg, u16 word) reg 225 drivers/hwmon/pmbus/max31785.c switch (reg) { reg 44 drivers/hwmon/pmbus/max34440.c static int max34440_read_word_data(struct i2c_client *client, int page, int reg) reg 50 drivers/hwmon/pmbus/max34440.c switch (reg) { reg 110 drivers/hwmon/pmbus/max34440.c int reg, u16 word) reg 116 drivers/hwmon/pmbus/max34440.c switch (reg) { reg 156 drivers/hwmon/pmbus/max34440.c static int max34440_read_byte_data(struct i2c_client *client, int page, int reg) reg 167 drivers/hwmon/pmbus/max34440.c switch (reg) { reg 31 drivers/hwmon/pmbus/max8688.c static int max8688_read_word_data(struct i2c_client *client, int page, int reg) reg 38 drivers/hwmon/pmbus/max8688.c switch (reg) { reg 61 drivers/hwmon/pmbus/max8688.c static int max8688_write_word_data(struct i2c_client *client, int page, int reg, reg 66 drivers/hwmon/pmbus/max8688.c switch (reg) { reg 87 drivers/hwmon/pmbus/max8688.c static int max8688_read_byte_data(struct i2c_client *client, int page, int reg) reg 95 drivers/hwmon/pmbus/max8688.c switch (reg) { reg 406 drivers/hwmon/pmbus/pmbus.h int (*read_byte_data)(struct i2c_client *client, int page, int reg); reg 407 drivers/hwmon/pmbus/pmbus.h int (*read_word_data)(struct i2c_client *client, int page, int reg); reg 408 drivers/hwmon/pmbus/pmbus.h int (*write_word_data)(struct i2c_client *client, int page, int reg, reg 447 drivers/hwmon/pmbus/pmbus.h int pmbus_read_word_data(struct i2c_client *client, int page, u8 reg); reg 448 drivers/hwmon/pmbus/pmbus.h int pmbus_write_word_data(struct i2c_client *client, int page, u8 reg, u16 word); reg 449 drivers/hwmon/pmbus/pmbus.h int pmbus_read_byte_data(struct i2c_client *client, int page, u8 reg); reg 451 drivers/hwmon/pmbus/pmbus.h int pmbus_write_byte_data(struct i2c_client *client, int page, u8 reg, reg 453 drivers/hwmon/pmbus/pmbus.h int pmbus_update_byte_data(struct i2c_client *client, int page, u8 reg, reg 456 drivers/hwmon/pmbus/pmbus.h bool pmbus_check_byte_register(struct i2c_client *client, int page, int reg); reg 457 drivers/hwmon/pmbus/pmbus.h bool pmbus_check_word_register(struct i2c_client *client, int page, int reg); reg 52 drivers/hwmon/pmbus/pmbus_core.c u16 reg; /* register */ reg 117 drivers/hwmon/pmbus/pmbus_core.c u8 reg; reg 206 drivers/hwmon/pmbus/pmbus_core.c int pmbus_write_word_data(struct i2c_client *client, int page, u8 reg, reg 215 drivers/hwmon/pmbus/pmbus_core.c return i2c_smbus_write_word_data(client, reg, word); reg 220 drivers/hwmon/pmbus/pmbus_core.c static int pmbus_write_virt_reg(struct i2c_client *client, int page, int reg, reg 227 drivers/hwmon/pmbus/pmbus_core.c switch (reg) { reg 229 drivers/hwmon/pmbus/pmbus_core.c id = reg - PMBUS_VIRT_FAN_TARGET_1; reg 245 drivers/hwmon/pmbus/pmbus_core.c static int _pmbus_write_word_data(struct i2c_client *client, int page, int reg, reg 253 drivers/hwmon/pmbus/pmbus_core.c status = info->write_word_data(client, page, reg, word); reg 258 drivers/hwmon/pmbus/pmbus_core.c if (reg >= PMBUS_VIRT_BASE) reg 259 drivers/hwmon/pmbus/pmbus_core.c return pmbus_write_virt_reg(client, page, reg, word); reg 261 drivers/hwmon/pmbus/pmbus_core.c return pmbus_write_word_data(client, page, reg, word); reg 289 drivers/hwmon/pmbus/pmbus_core.c int pmbus_read_word_data(struct i2c_client *client, int page, u8 reg) reg 297 drivers/hwmon/pmbus/pmbus_core.c return i2c_smbus_read_word_data(client, reg); reg 301 drivers/hwmon/pmbus/pmbus_core.c static int pmbus_read_virt_reg(struct i2c_client *client, int page, int reg) reg 306 drivers/hwmon/pmbus/pmbus_core.c switch (reg) { reg 308 drivers/hwmon/pmbus/pmbus_core.c id = reg - PMBUS_VIRT_FAN_TARGET_1; reg 323 drivers/hwmon/pmbus/pmbus_core.c static int _pmbus_read_word_data(struct i2c_client *client, int page, int reg) reg 330 drivers/hwmon/pmbus/pmbus_core.c status = info->read_word_data(client, page, reg); reg 335 drivers/hwmon/pmbus/pmbus_core.c if (reg >= PMBUS_VIRT_BASE) reg 336 drivers/hwmon/pmbus/pmbus_core.c return pmbus_read_virt_reg(client, page, reg); reg 338 drivers/hwmon/pmbus/pmbus_core.c return pmbus_read_word_data(client, page, reg); reg 341 drivers/hwmon/pmbus/pmbus_core.c int pmbus_read_byte_data(struct i2c_client *client, int page, u8 reg) reg 349 drivers/hwmon/pmbus/pmbus_core.c return i2c_smbus_read_byte_data(client, reg); reg 353 drivers/hwmon/pmbus/pmbus_core.c int pmbus_write_byte_data(struct i2c_client *client, int page, u8 reg, u8 value) reg 361 drivers/hwmon/pmbus/pmbus_core.c return i2c_smbus_write_byte_data(client, reg, value); reg 365 drivers/hwmon/pmbus/pmbus_core.c int pmbus_update_byte_data(struct i2c_client *client, int page, u8 reg, reg 371 drivers/hwmon/pmbus/pmbus_core.c rv = pmbus_read_byte_data(client, page, reg); reg 378 drivers/hwmon/pmbus/pmbus_core.c rv = pmbus_write_byte_data(client, page, reg, tmp); reg 388 drivers/hwmon/pmbus/pmbus_core.c static int _pmbus_read_byte_data(struct i2c_client *client, int page, int reg) reg 395 drivers/hwmon/pmbus/pmbus_core.c status = info->read_byte_data(client, page, reg); reg 399 drivers/hwmon/pmbus/pmbus_core.c return pmbus_read_byte_data(client, page, reg); reg 403 drivers/hwmon/pmbus/pmbus_core.c int reg) reg 408 drivers/hwmon/pmbus/pmbus_core.c if (sensor->page == page && sensor->reg == reg) reg 423 drivers/hwmon/pmbus/pmbus_core.c int reg; reg 428 drivers/hwmon/pmbus/pmbus_core.c reg = want_rpm ? PMBUS_VIRT_FAN_TARGET_1 : PMBUS_VIRT_PWM_1; reg 429 drivers/hwmon/pmbus/pmbus_core.c s = pmbus_find_sensor(data, page, reg + id); reg 495 drivers/hwmon/pmbus/pmbus_core.c int page, int reg), reg 496 drivers/hwmon/pmbus/pmbus_core.c int page, int reg) reg 501 drivers/hwmon/pmbus/pmbus_core.c rv = func(client, page, reg); reg 525 drivers/hwmon/pmbus/pmbus_core.c bool pmbus_check_byte_register(struct i2c_client *client, int page, int reg) reg 527 drivers/hwmon/pmbus/pmbus_core.c return pmbus_check_register(client, _pmbus_read_byte_data, page, reg); reg 531 drivers/hwmon/pmbus/pmbus_core.c bool pmbus_check_word_register(struct i2c_client *client, int page, int reg) reg 533 drivers/hwmon/pmbus/pmbus_core.c return pmbus_check_register(client, _pmbus_read_word_data, page, reg); reg 548 drivers/hwmon/pmbus/pmbus_core.c u16 reg; reg 579 drivers/hwmon/pmbus/pmbus_core.c s->reg); reg 598 drivers/hwmon/pmbus/pmbus_core.c sensor->reg); reg 904 drivers/hwmon/pmbus/pmbus_core.c u16 reg = (index >> 16) & 0xffff; reg 909 drivers/hwmon/pmbus/pmbus_core.c status = data->status[reg]; reg 977 drivers/hwmon/pmbus/pmbus_core.c ret = _pmbus_write_word_data(client, sensor->page, sensor->reg, regval); reg 1048 drivers/hwmon/pmbus/pmbus_core.c u16 reg, u16 mask) reg 1064 drivers/hwmon/pmbus/pmbus_core.c (reg << 16) | mask); reg 1071 drivers/hwmon/pmbus/pmbus_core.c int seq, int page, int reg, reg 1092 drivers/hwmon/pmbus/pmbus_core.c sensor->reg = reg; reg 1142 drivers/hwmon/pmbus/pmbus_core.c u16 reg; /* Limit register */ reg 1156 drivers/hwmon/pmbus/pmbus_core.c u16 reg; /* sensor register */ reg 1190 drivers/hwmon/pmbus/pmbus_core.c if (pmbus_check_word_register(client, page, l->reg)) { reg 1192 drivers/hwmon/pmbus/pmbus_core.c page, l->reg, attr->class, reg 1233 drivers/hwmon/pmbus/pmbus_core.c base = pmbus_add_sensor(data, name, "input", index, page, attr->reg, reg 1319 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIN_UV_WARN_LIMIT, reg 1324 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIN_UV_FAULT_LIMIT, reg 1329 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIN_OV_WARN_LIMIT, reg 1334 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIN_OV_FAULT_LIMIT, reg 1339 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_VIN_AVG, reg 1343 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_VIN_MIN, reg 1347 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_VIN_MAX, reg 1351 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_RESET_VIN_HISTORY, reg 1358 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_VMON_UV_WARN_LIMIT, reg 1363 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_VMON_UV_FAULT_LIMIT, reg 1368 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_VMON_OV_WARN_LIMIT, reg 1373 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_VMON_OV_FAULT_LIMIT, reg 1382 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VOUT_UV_WARN_LIMIT, reg 1387 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VOUT_UV_FAULT_LIMIT, reg 1392 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VOUT_OV_WARN_LIMIT, reg 1397 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VOUT_OV_FAULT_LIMIT, reg 1402 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_VOUT_AVG, reg 1406 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_VOUT_MIN, reg 1410 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_VOUT_MAX, reg 1414 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_RESET_VOUT_HISTORY, reg 1421 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_READ_VIN, reg 1431 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_VMON, reg 1440 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_READ_VCAP, reg 1445 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_READ_VOUT, reg 1462 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_IIN_OC_WARN_LIMIT, reg 1467 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_IIN_OC_FAULT_LIMIT, reg 1472 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_IIN_AVG, reg 1476 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_IIN_MIN, reg 1480 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_IIN_MAX, reg 1484 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_RESET_IIN_HISTORY, reg 1491 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_IOUT_OC_WARN_LIMIT, reg 1496 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_IOUT_UC_FAULT_LIMIT, reg 1501 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_IOUT_OC_FAULT_LIMIT, reg 1506 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_IOUT_AVG, reg 1510 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_IOUT_MIN, reg 1514 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_IOUT_MAX, reg 1518 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_RESET_IOUT_HISTORY, reg 1525 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_READ_IIN, reg 1535 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_READ_IOUT, reg 1552 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_PIN_OP_WARN_LIMIT, reg 1557 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_PIN_AVG, reg 1561 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_PIN_MIN, reg 1565 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_PIN_MAX, reg 1569 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_RESET_PIN_HISTORY, reg 1576 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_POUT_MAX, reg 1581 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_POUT_OP_WARN_LIMIT, reg 1586 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_POUT_OP_FAULT_LIMIT, reg 1591 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_POUT_AVG, reg 1595 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_POUT_MIN, reg 1599 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_POUT_MAX, reg 1603 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_RESET_POUT_HISTORY, reg 1610 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_READ_PIN, reg 1620 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_READ_POUT, reg 1636 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_UT_WARN_LIMIT, reg 1642 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_UT_FAULT_LIMIT, reg 1648 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_OT_WARN_LIMIT, reg 1653 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_OT_FAULT_LIMIT, reg 1658 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_TEMP_MIN, reg 1661 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_TEMP_AVG, reg 1664 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_TEMP_MAX, reg 1667 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_RESET_TEMP_HISTORY, reg 1674 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_UT_WARN_LIMIT, reg 1680 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_UT_FAULT_LIMIT, reg 1686 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_OT_WARN_LIMIT, reg 1691 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_OT_FAULT_LIMIT, reg 1696 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_TEMP2_MIN, reg 1699 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_TEMP2_AVG, reg 1702 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_READ_TEMP2_MAX, reg 1705 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_RESET_TEMP2_HISTORY, reg 1712 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_UT_WARN_LIMIT, reg 1718 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_UT_FAULT_LIMIT, reg 1724 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_OT_WARN_LIMIT, reg 1729 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_OT_FAULT_LIMIT, reg 1738 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_READ_TEMPERATURE_1, reg 1750 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_READ_TEMPERATURE_2, reg 1762 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_READ_TEMPERATURE_3, reg 1918 drivers/hwmon/pmbus/pmbus_core.c int reg; reg 1930 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_SAMPLES, reg 1933 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_IN_SAMPLES, reg 1936 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_CURR_SAMPLES, reg 1939 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_POWER_SAMPLES, reg 1942 drivers/hwmon/pmbus/pmbus_core.c .reg = PMBUS_VIRT_TEMP_SAMPLES, reg 1954 drivers/hwmon/pmbus/pmbus_core.c struct pmbus_samples_reg *reg = to_samples_reg(devattr); reg 1956 drivers/hwmon/pmbus/pmbus_core.c val = _pmbus_read_word_data(client, reg->page, reg->attr->reg); reg 1970 drivers/hwmon/pmbus/pmbus_core.c struct pmbus_samples_reg *reg = to_samples_reg(devattr); reg 1977 drivers/hwmon/pmbus/pmbus_core.c ret = _pmbus_write_word_data(client, reg->page, reg->attr->reg, val); reg 1986 drivers/hwmon/pmbus/pmbus_core.c struct pmbus_samples_reg *reg; reg 1988 drivers/hwmon/pmbus/pmbus_core.c reg = devm_kzalloc(data->dev, sizeof(*reg), GFP_KERNEL); reg 1989 drivers/hwmon/pmbus/pmbus_core.c if (!reg) reg 1992 drivers/hwmon/pmbus/pmbus_core.c reg->attr = attr; reg 1993 drivers/hwmon/pmbus/pmbus_core.c reg->page = page; reg 1995 drivers/hwmon/pmbus/pmbus_core.c pmbus_dev_attr_init(®->dev_attr, attr->name, 0644, reg 1998 drivers/hwmon/pmbus/pmbus_core.c return pmbus_add_attribute(data, ®->dev_attr.attr); reg 2015 drivers/hwmon/pmbus/pmbus_core.c if (!pmbus_check_word_register(client, 0, attr->reg)) reg 2258 drivers/hwmon/pmbus/pmbus_core.c rc = _pmbus_read_byte_data(entry->client, entry->page, entry->reg); reg 2329 drivers/hwmon/pmbus/pmbus_core.c entries[idx].reg = PMBUS_STATUS_VOUT; reg 2339 drivers/hwmon/pmbus/pmbus_core.c entries[idx].reg = PMBUS_STATUS_IOUT; reg 2349 drivers/hwmon/pmbus/pmbus_core.c entries[idx].reg = PMBUS_STATUS_INPUT; reg 2359 drivers/hwmon/pmbus/pmbus_core.c entries[idx].reg = PMBUS_STATUS_TEMPERATURE; reg 2369 drivers/hwmon/pmbus/pmbus_core.c entries[idx].reg = PMBUS_STATUS_CML; reg 2379 drivers/hwmon/pmbus/pmbus_core.c entries[idx].reg = PMBUS_STATUS_OTHER; reg 2390 drivers/hwmon/pmbus/pmbus_core.c entries[idx].reg = PMBUS_STATUS_MFR_SPECIFIC; reg 2400 drivers/hwmon/pmbus/pmbus_core.c entries[idx].reg = PMBUS_STATUS_FAN_12; reg 2410 drivers/hwmon/pmbus/pmbus_core.c entries[idx].reg = PMBUS_STATUS_FAN_34; reg 88 drivers/hwmon/pmbus/ucd9000.c static int ucd9000_read_byte_data(struct i2c_client *client, int page, int reg) reg 93 drivers/hwmon/pmbus/ucd9000.c switch (reg) { reg 128 drivers/hwmon/pmbus/zl6100.c static int zl6100_read_word_data(struct i2c_client *client, int page, int reg) reg 142 drivers/hwmon/pmbus/zl6100.c switch (reg) { reg 150 drivers/hwmon/pmbus/zl6100.c switch (reg) { reg 163 drivers/hwmon/pmbus/zl6100.c if (reg >= PMBUS_VIRT_BASE) reg 165 drivers/hwmon/pmbus/zl6100.c vreg = reg; reg 175 drivers/hwmon/pmbus/zl6100.c switch (reg) { reg 187 drivers/hwmon/pmbus/zl6100.c static int zl6100_read_byte_data(struct i2c_client *client, int page, int reg) reg 198 drivers/hwmon/pmbus/zl6100.c switch (reg) { reg 217 drivers/hwmon/pmbus/zl6100.c ret = pmbus_read_byte_data(client, page, reg); reg 225 drivers/hwmon/pmbus/zl6100.c static int zl6100_write_word_data(struct i2c_client *client, int page, int reg, reg 235 drivers/hwmon/pmbus/zl6100.c switch (reg) { reg 255 drivers/hwmon/pmbus/zl6100.c if (reg >= PMBUS_VIRT_BASE) reg 257 drivers/hwmon/pmbus/zl6100.c vreg = reg; reg 175 drivers/hwmon/sch5627.c static int reg_to_temp(u16 reg) reg 177 drivers/hwmon/sch5627.c return (reg * 625) / 10 - 64000; reg 180 drivers/hwmon/sch5627.c static int reg_to_temp_limit(u8 reg) reg 182 drivers/hwmon/sch5627.c return (reg - 64) * 1000; reg 185 drivers/hwmon/sch5627.c static int reg_to_rpm(u16 reg) reg 187 drivers/hwmon/sch5627.c if (reg == 0) reg 189 drivers/hwmon/sch5627.c if (reg == 0xffff) reg 192 drivers/hwmon/sch5627.c return 5400540 / reg; reg 150 drivers/hwmon/sch5636.c static int reg_to_rpm(u16 reg) reg 152 drivers/hwmon/sch5636.c if (reg == 0) reg 154 drivers/hwmon/sch5636.c if (reg == 0xffff) reg 157 drivers/hwmon/sch5636.c return 5400540 / reg; reg 65 drivers/hwmon/sch56xx-common.c static inline int superio_inb(int base, int reg) reg 67 drivers/hwmon/sch56xx-common.c outb(reg, base); reg 96 drivers/hwmon/sch56xx-common.c static int sch56xx_send_cmd(u16 addr, u8 cmd, u16 reg, u8 v) reg 128 drivers/hwmon/sch56xx-common.c outb(reg & 0xff, addr + 6); reg 129 drivers/hwmon/sch56xx-common.c outb(reg >> 8, addr + 7); reg 149 drivers/hwmon/sch56xx-common.c reg, 1); reg 166 drivers/hwmon/sch56xx-common.c (unsigned int)val, reg); reg 170 drivers/hwmon/sch56xx-common.c reg, 2); reg 191 drivers/hwmon/sch56xx-common.c int sch56xx_read_virtual_reg(u16 addr, u16 reg) reg 193 drivers/hwmon/sch56xx-common.c return sch56xx_send_cmd(addr, SCH56XX_CMD_READ, reg, 0); reg 197 drivers/hwmon/sch56xx-common.c int sch56xx_write_virtual_reg(u16 addr, u16 reg, u8 val) reg 199 drivers/hwmon/sch56xx-common.c return sch56xx_send_cmd(addr, SCH56XX_CMD_WRITE, reg, val); reg 203 drivers/hwmon/sch56xx-common.c int sch56xx_read_virtual_reg16(u16 addr, u16 reg) reg 208 drivers/hwmon/sch56xx-common.c lsb = sch56xx_read_virtual_reg(addr, reg); reg 212 drivers/hwmon/sch56xx-common.c msb = sch56xx_read_virtual_reg(addr, reg + 1); reg 11 drivers/hwmon/sch56xx-common.h int sch56xx_read_virtual_reg(u16 addr, u16 reg); reg 12 drivers/hwmon/sch56xx-common.h int sch56xx_write_virtual_reg(u16 addr, u16 reg, u8 val); reg 13 drivers/hwmon/sch56xx-common.h int sch56xx_read_virtual_reg16(u16 addr, u16 reg); reg 167 drivers/hwmon/sht15.c struct regulator *reg; reg 883 drivers/hwmon/sht15.c data->supply_uv = regulator_get_voltage(data->reg); reg 936 drivers/hwmon/sht15.c data->reg = devm_regulator_get_optional(data->dev, "vcc"); reg 937 drivers/hwmon/sht15.c if (!IS_ERR(data->reg)) { reg 940 drivers/hwmon/sht15.c voltage = regulator_get_voltage(data->reg); reg 944 drivers/hwmon/sht15.c ret = regulator_enable(data->reg); reg 956 drivers/hwmon/sht15.c ret = regulator_register_notifier(data->reg, &data->nb); reg 960 drivers/hwmon/sht15.c regulator_disable(data->reg); reg 1013 drivers/hwmon/sht15.c if (!IS_ERR(data->reg)) { reg 1014 drivers/hwmon/sht15.c regulator_unregister_notifier(data->reg, &data->nb); reg 1015 drivers/hwmon/sht15.c regulator_disable(data->reg); reg 1035 drivers/hwmon/sht15.c if (!IS_ERR(data->reg)) { reg 1036 drivers/hwmon/sht15.c regulator_unregister_notifier(data->reg, &data->nb); reg 1037 drivers/hwmon/sht15.c regulator_disable(data->reg); reg 197 drivers/hwmon/sis5595.c static int sis5595_read_value(struct sis5595_data *data, u8 reg); reg 198 drivers/hwmon/sis5595.c static void sis5595_write_value(struct sis5595_data *data, u8 reg, u8 value); reg 421 drivers/hwmon/sis5595.c int reg; reg 432 drivers/hwmon/sis5595.c reg = sis5595_read_value(data, SIS5595_REG_FANDIV); reg 457 drivers/hwmon/sis5595.c reg = (reg & 0xcf) | (data->fan_div[nr] << 4); reg 460 drivers/hwmon/sis5595.c reg = (reg & 0x3f) | (data->fan_div[nr] << 6); reg 463 drivers/hwmon/sis5595.c sis5595_write_value(data, SIS5595_REG_FANDIV, reg); reg 661 drivers/hwmon/sis5595.c static int sis5595_read_value(struct sis5595_data *data, u8 reg) reg 666 drivers/hwmon/sis5595.c outb_p(reg, data->addr + SIS5595_ADDR_REG_OFFSET); reg 672 drivers/hwmon/sis5595.c static void sis5595_write_value(struct sis5595_data *data, u8 reg, u8 value) reg 675 drivers/hwmon/sis5595.c outb_p(reg, data->addr + SIS5595_ADDR_REG_OFFSET); reg 159 drivers/hwmon/smm665.c static int smm665_read16(struct i2c_client *client, int reg) reg 163 drivers/hwmon/smm665.c rv = i2c_smbus_read_byte_data(client, reg); reg 167 drivers/hwmon/smm665.c rv = i2c_smbus_read_byte_data(client, reg + 1); reg 44 drivers/hwmon/smsc47b397.c static inline void superio_outb(int reg, int val) reg 46 drivers/hwmon/smsc47b397.c outb(reg, REG); reg 50 drivers/hwmon/smsc47b397.c static inline int superio_inb(int reg) reg 52 drivers/hwmon/smsc47b397.c outb(reg, REG); reg 106 drivers/hwmon/smsc47b397.c static int smsc47b397_read_value(struct smsc47b397_data *data, u8 reg) reg 111 drivers/hwmon/smsc47b397.c outb(reg, data->addr); reg 154 drivers/hwmon/smsc47b397.c static int temp_from_reg(u8 reg) reg 156 drivers/hwmon/smsc47b397.c return (s8)reg * 1000; reg 176 drivers/hwmon/smsc47b397.c static int fan_from_reg(u16 reg) reg 178 drivers/hwmon/smsc47b397.c if (reg == 0 || reg == 0xffff) reg 180 drivers/hwmon/smsc47b397.c return 90000 * 60 / reg; reg 47 drivers/hwmon/smsc47m1.c superio_outb(int reg, int val) reg 49 drivers/hwmon/smsc47m1.c outb(reg, REG); reg 54 drivers/hwmon/smsc47m1.c superio_inb(int reg) reg 56 drivers/hwmon/smsc47m1.c outb(reg, REG); reg 106 drivers/hwmon/smsc47m1.c #define MIN_FROM_REG(reg, div) ((reg) >= 192 ? 0 : \ reg 107 drivers/hwmon/smsc47m1.c 983040 / ((192 - (reg)) * (div))) reg 108 drivers/hwmon/smsc47m1.c #define FAN_FROM_REG(reg, div, preload) ((reg) <= (preload) || (reg) == 255 ? \ reg 110 drivers/hwmon/smsc47m1.c 983040 / (((reg) - (preload)) * (div))) reg 111 drivers/hwmon/smsc47m1.c #define DIV_FROM_REG(reg) (1 << (reg)) reg 112 drivers/hwmon/smsc47m1.c #define PWM_FROM_REG(reg) (((reg) & 0x7E) << 1) reg 113 drivers/hwmon/smsc47m1.c #define PWM_EN_FROM_REG(reg) ((~(reg)) & 0x01) reg 114 drivers/hwmon/smsc47m1.c #define PWM_TO_REG(reg) (((reg) >> 1) & 0x7E) reg 137 drivers/hwmon/smsc47m1.c static inline int smsc47m1_read_value(struct smsc47m1_data *data, u8 reg) reg 139 drivers/hwmon/smsc47m1.c return inb_p(data->addr + reg); reg 142 drivers/hwmon/smsc47m1.c static inline void smsc47m1_write_value(struct smsc47m1_data *data, u8 reg, reg 145 drivers/hwmon/smsc47m1.c outb_p(value, data->addr + reg); reg 60 drivers/hwmon/smsc47m192.c static inline unsigned int IN_FROM_REG(u8 reg, int n) reg 62 drivers/hwmon/smsc47m192.c return SCALE(reg, nom_mv[n], 192); reg 215 drivers/hwmon/stts751.c static int stts751_set_temp_reg8(struct stts751_priv *priv, int temp, u8 reg) reg 220 drivers/hwmon/stts751.c return i2c_smbus_write_byte_data(priv->client, reg, hwval >> 8); reg 241 drivers/hwmon/stts751.c static int stts751_read_reg8(struct stts751_priv *priv, int *temp, u8 reg) reg 245 drivers/hwmon/stts751.c integer = i2c_smbus_read_byte_data(priv->client, reg); reg 77 drivers/hwmon/tmp102.c int err, reg; reg 86 drivers/hwmon/tmp102.c reg = TMP102_TEMP_REG; reg 89 drivers/hwmon/tmp102.c reg = TMP102_TLOW_REG; reg 92 drivers/hwmon/tmp102.c reg = TMP102_THIGH_REG; reg 98 drivers/hwmon/tmp102.c err = regmap_read(tmp102->regmap, reg, ®val); reg 110 drivers/hwmon/tmp102.c int reg; reg 114 drivers/hwmon/tmp102.c reg = TMP102_TLOW_REG; reg 117 drivers/hwmon/tmp102.c reg = TMP102_THIGH_REG; reg 124 drivers/hwmon/tmp102.c return regmap_write(tmp102->regmap, reg, tmp102_mC_to_reg(temp)); reg 170 drivers/hwmon/tmp102.c static bool tmp102_is_writeable_reg(struct device *dev, unsigned int reg) reg 172 drivers/hwmon/tmp102.c return reg != TMP102_TEMP_REG; reg 175 drivers/hwmon/tmp102.c static bool tmp102_is_volatile_reg(struct device *dev, unsigned int reg) reg 177 drivers/hwmon/tmp102.c return reg == TMP102_TEMP_REG; reg 100 drivers/hwmon/tmp103.c static bool tmp103_regmap_is_volatile(struct device *dev, unsigned int reg) reg 102 drivers/hwmon/tmp103.c return reg == TMP103_TEMP_REG; reg 303 drivers/hwmon/tmp108.c static bool tmp108_is_writeable_reg(struct device *dev, unsigned int reg) reg 305 drivers/hwmon/tmp108.c return reg != TMP108_REG_TEMP; reg 308 drivers/hwmon/tmp108.c static bool tmp108_is_volatile_reg(struct device *dev, unsigned int reg) reg 311 drivers/hwmon/tmp108.c return reg == TMP108_REG_TEMP || reg == TMP108_REG_CONF; reg 156 drivers/hwmon/tmp401.c static int tmp401_register_to_temp(u16 reg, u8 config) reg 158 drivers/hwmon/tmp401.c int temp = reg; reg 332 drivers/hwmon/tmp401.c u16 reg; reg 338 drivers/hwmon/tmp401.c reg = tmp401_temp_to_register(val, data->config, nr == 3 ? 8 : 4); reg 345 drivers/hwmon/tmp401.c i2c_smbus_write_byte_data(client, regaddr, reg >> 8); reg 348 drivers/hwmon/tmp401.c i2c_smbus_write_word_swapped(client, regaddr, reg); reg 350 drivers/hwmon/tmp401.c data->temp[nr][index] = reg; reg 364 drivers/hwmon/tmp401.c u8 reg; reg 380 drivers/hwmon/tmp401.c reg = ((temp - val) + 500) / 1000; reg 383 drivers/hwmon/tmp401.c reg); reg 385 drivers/hwmon/tmp401.c data->temp_crit_hyst = reg; reg 622 drivers/hwmon/tmp401.c u8 reg; reg 628 drivers/hwmon/tmp401.c reg = i2c_smbus_read_byte_data(client, TMP401_MANUFACTURER_ID_REG); reg 629 drivers/hwmon/tmp401.c if (reg != TMP401_MANUFACTURER_ID) reg 632 drivers/hwmon/tmp401.c reg = i2c_smbus_read_byte_data(client, TMP401_DEVICE_ID_REG); reg 634 drivers/hwmon/tmp401.c switch (reg) { reg 672 drivers/hwmon/tmp401.c reg = i2c_smbus_read_byte_data(client, TMP401_CONFIG_READ); reg 673 drivers/hwmon/tmp401.c if (reg & 0x1b) reg 676 drivers/hwmon/tmp401.c reg = i2c_smbus_read_byte_data(client, TMP401_CONVERSION_RATE_READ); reg 678 drivers/hwmon/tmp401.c if (reg > 15) reg 103 drivers/hwmon/tmp421.c static int temp_from_s16(s16 reg) reg 106 drivers/hwmon/tmp421.c int temp = reg & ~0xf; reg 111 drivers/hwmon/tmp421.c static int temp_from_u16(u16 reg) reg 114 drivers/hwmon/tmp421.c int temp = reg & ~0xf; reg 225 drivers/hwmon/tmp421.c u8 reg; reg 230 drivers/hwmon/tmp421.c reg = i2c_smbus_read_byte_data(client, TMP421_MANUFACTURER_ID_REG); reg 231 drivers/hwmon/tmp421.c if (reg != TMP421_MANUFACTURER_ID) reg 234 drivers/hwmon/tmp421.c reg = i2c_smbus_read_byte_data(client, TMP421_CONVERSION_RATE_REG); reg 235 drivers/hwmon/tmp421.c if (reg & 0xf8) reg 238 drivers/hwmon/tmp421.c reg = i2c_smbus_read_byte_data(client, TMP421_STATUS_REG); reg 239 drivers/hwmon/tmp421.c if (reg & 0x7f) reg 242 drivers/hwmon/tmp421.c reg = i2c_smbus_read_byte_data(client, TMP421_DEVICE_ID_REG); reg 243 drivers/hwmon/tmp421.c switch (reg) { reg 22 drivers/hwmon/vexpress-hwmon.c struct regmap *reg; reg 40 drivers/hwmon/vexpress-hwmon.c err = regmap_read(data->reg, 0, &value); reg 55 drivers/hwmon/vexpress-hwmon.c err = regmap_read(data->reg, 0, &value_lo); reg 59 drivers/hwmon/vexpress-hwmon.c err = regmap_read(data->reg, 1, &value_hi); reg 224 drivers/hwmon/vexpress-hwmon.c data->reg = devm_regmap_init_vexpress_config(&pdev->dev); reg 225 drivers/hwmon/vexpress-hwmon.c if (IS_ERR(data->reg)) reg 226 drivers/hwmon/vexpress-hwmon.c return PTR_ERR(data->reg); reg 327 drivers/hwmon/via686a.c static inline int via686a_read_value(struct via686a_data *data, u8 reg) reg 329 drivers/hwmon/via686a.c return inb_p(data->addr + reg); reg 332 drivers/hwmon/via686a.c static inline void via686a_write_value(struct via686a_data *data, u8 reg, reg 335 drivers/hwmon/via686a.c outb_p(value, data->addr + reg); reg 724 drivers/hwmon/via686a.c int reg = via686a_read_value(data, VIA686A_REG_FANDIV); reg 725 drivers/hwmon/via686a.c data->fan_div[0] = (reg >> 4) & 0x03; reg 726 drivers/hwmon/via686a.c data->fan_div[1] = reg >> 6; reg 731 drivers/hwmon/via686a.c u8 reg; reg 734 drivers/hwmon/via686a.c reg = via686a_read_value(data, VIA686A_REG_CONFIG); reg 735 drivers/hwmon/via686a.c via686a_write_value(data, VIA686A_REG_CONFIG, (reg | 0x01) & 0x7F); reg 738 drivers/hwmon/via686a.c reg = via686a_read_value(data, VIA686A_REG_TEMP_MODE); reg 740 drivers/hwmon/via686a.c (reg & ~VIA686A_TEMP_MODE_MASK) reg 145 drivers/hwmon/vt1211.c #define IN_FROM_REG(ix, reg) ((reg) < 3 ? 0 : (ix) == 5 ? \ reg 146 drivers/hwmon/vt1211.c (((reg) - 3) * 15882 + 479) / 958 : \ reg 147 drivers/hwmon/vt1211.c (((reg) - 3) * 10000 + 479) / 958) reg 159 drivers/hwmon/vt1211.c #define TEMP_FROM_REG(ix, reg) ((ix) == 0 ? (reg) * 1000 : \ reg 160 drivers/hwmon/vt1211.c (ix) == 1 ? (reg) < 51 ? 0 : \ reg 161 drivers/hwmon/vt1211.c ((reg) - 51) * 1000 : \ reg 162 drivers/hwmon/vt1211.c ((253 - (reg)) * 2200 + 105) / 210) reg 168 drivers/hwmon/vt1211.c #define DIV_FROM_REG(reg) (1 << (reg)) reg 170 drivers/hwmon/vt1211.c #define RPM_FROM_REG(reg, div) (((reg) == 0) || ((reg) == 255) ? 0 : \ reg 171 drivers/hwmon/vt1211.c 1310720 / (reg) / DIV_FROM_REG(div)) reg 198 drivers/hwmon/vt1211.c static inline void superio_outb(int sio_cip, int reg, int val) reg 200 drivers/hwmon/vt1211.c outb(reg, sio_cip); reg 204 drivers/hwmon/vt1211.c static inline int superio_inb(int sio_cip, int reg) reg 206 drivers/hwmon/vt1211.c outb(reg, sio_cip); reg 237 drivers/hwmon/vt1211.c static inline u8 vt1211_read8(struct vt1211_data *data, u8 reg) reg 239 drivers/hwmon/vt1211.c return inb(data->addr + reg); reg 242 drivers/hwmon/vt1211.c static inline void vt1211_write8(struct vt1211_data *data, u8 reg, u8 val) reg 244 drivers/hwmon/vt1211.c outb(val, data->addr + reg); reg 529 drivers/hwmon/vt1211.c int reg; reg 540 drivers/hwmon/vt1211.c reg = vt1211_read8(data, VT1211_REG_FAN_DIV); reg 541 drivers/hwmon/vt1211.c data->fan_div[0] = (reg >> 4) & 3; reg 542 drivers/hwmon/vt1211.c data->fan_div[1] = (reg >> 6) & 3; reg 543 drivers/hwmon/vt1211.c data->fan_ctl = reg & 0xf; reg 635 drivers/hwmon/vt1211.c int tmp, reg; reg 648 drivers/hwmon/vt1211.c reg = vt1211_read8(data, VT1211_REG_FAN_DIV); reg 649 drivers/hwmon/vt1211.c data->fan_div[0] = (reg >> 4) & 3; reg 650 drivers/hwmon/vt1211.c data->fan_div[1] = (reg >> 6) & 3; reg 651 drivers/hwmon/vt1211.c data->fan_ctl = reg & 0xf; reg 652 drivers/hwmon/vt1211.c reg = vt1211_read8(data, VT1211_REG_PWM_CTL); reg 653 drivers/hwmon/vt1211.c data->pwm_ctl[0] = reg & 0xf; reg 654 drivers/hwmon/vt1211.c data->pwm_ctl[1] = (reg >> 4) & 0xf; reg 691 drivers/hwmon/vt1211.c reg = vt1211_read8(data, VT1211_REG_PWM_CLK); reg 692 drivers/hwmon/vt1211.c data->pwm_clk = (reg & 0xf8) | tmp; reg 710 drivers/hwmon/vt1211.c reg = vt1211_read8(data, VT1211_REG_PWM_CTL); reg 711 drivers/hwmon/vt1211.c data->pwm_ctl[0] = reg & 0xf; reg 712 drivers/hwmon/vt1211.c data->pwm_ctl[1] = (reg >> 4) & 0xf; reg 773 drivers/hwmon/vt1211.c int reg; reg 785 drivers/hwmon/vt1211.c reg = vt1211_read8(data, VT1211_REG_PWM_CTL); reg 786 drivers/hwmon/vt1211.c data->pwm_ctl[0] = reg & 0xf; reg 787 drivers/hwmon/vt1211.c data->pwm_ctl[1] = (reg >> 4) & 0xf; reg 89 drivers/hwmon/vt8231.c #define TEMP_FROM_REG(reg) (((253 * 4 - (reg)) * 550 + 105) / 210) reg 90 drivers/hwmon/vt8231.c #define TEMP_MAXMIN_FROM_REG(reg) (((253 - (reg)) * 2200 + 105) / 210) reg 170 drivers/hwmon/vt8231.c static inline int vt8231_read_value(struct vt8231_data *data, u8 reg) reg 172 drivers/hwmon/vt8231.c return inb_p(data->addr + reg); reg 175 drivers/hwmon/vt8231.c static inline void vt8231_write_value(struct vt8231_data *data, u8 reg, reg 178 drivers/hwmon/vt8231.c outb_p(value, data->addr + reg); reg 105 drivers/hwmon/w83627ehf.c superio_outb(int ioreg, int reg, int val) reg 107 drivers/hwmon/w83627ehf.c outb(reg, ioreg); reg 112 drivers/hwmon/w83627ehf.c superio_inb(int ioreg, int reg) reg 114 drivers/hwmon/w83627ehf.c outb(reg, ioreg); reg 323 drivers/hwmon/w83627ehf.c static int is_word_sized(u16 reg) reg 325 drivers/hwmon/w83627ehf.c return ((((reg & 0xff00) == 0x100 reg 326 drivers/hwmon/w83627ehf.c || (reg & 0xff00) == 0x200) reg 327 drivers/hwmon/w83627ehf.c && ((reg & 0x00ff) == 0x50 reg 328 drivers/hwmon/w83627ehf.c || (reg & 0x00ff) == 0x53 reg 329 drivers/hwmon/w83627ehf.c || (reg & 0x00ff) == 0x55)) reg 330 drivers/hwmon/w83627ehf.c || (reg & 0xfff0) == 0x630 reg 331 drivers/hwmon/w83627ehf.c || reg == 0x640 || reg == 0x642 reg 332 drivers/hwmon/w83627ehf.c || ((reg & 0xfff0) == 0x650 reg 333 drivers/hwmon/w83627ehf.c && (reg & 0x000f) >= 0x06) reg 334 drivers/hwmon/w83627ehf.c || reg == 0x73 || reg == 0x75 || reg == 0x77 reg 343 drivers/hwmon/w83627ehf.c static inline unsigned int step_time_from_reg(u8 reg, u8 mode) reg 345 drivers/hwmon/w83627ehf.c return mode ? 100 * reg : 400 * reg; reg 354 drivers/hwmon/w83627ehf.c static unsigned int fan_from_reg8(u16 reg, unsigned int divreg) reg 356 drivers/hwmon/w83627ehf.c if (reg == 0 || reg == 255) reg 358 drivers/hwmon/w83627ehf.c return 1350000U / (reg << divreg); reg 361 drivers/hwmon/w83627ehf.c static unsigned int fan_from_reg13(u16 reg, unsigned int divreg) reg 363 drivers/hwmon/w83627ehf.c if ((reg & 0xff1f) == 0xff1f) reg 366 drivers/hwmon/w83627ehf.c reg = (reg & 0x1f) | ((reg & 0xff00) >> 3); reg 368 drivers/hwmon/w83627ehf.c if (reg == 0) reg 371 drivers/hwmon/w83627ehf.c return 1350000U / reg; reg 374 drivers/hwmon/w83627ehf.c static unsigned int fan_from_reg16(u16 reg, unsigned int divreg) reg 376 drivers/hwmon/w83627ehf.c if (reg == 0 || reg == 0xffff) reg 383 drivers/hwmon/w83627ehf.c return 1350000U / (reg << divreg); reg 387 drivers/hwmon/w83627ehf.c div_from_reg(u8 reg) reg 389 drivers/hwmon/w83627ehf.c return 1 << reg; reg 403 drivers/hwmon/w83627ehf.c static inline long in_from_reg(u8 reg, u8 nr, const u16 *scale_in) reg 405 drivers/hwmon/w83627ehf.c return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100); reg 442 drivers/hwmon/w83627ehf.c unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg); reg 443 drivers/hwmon/w83627ehf.c unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg); reg 517 drivers/hwmon/w83627ehf.c static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg) reg 519 drivers/hwmon/w83627ehf.c u8 bank = reg >> 8; reg 527 drivers/hwmon/w83627ehf.c static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg) reg 529 drivers/hwmon/w83627ehf.c int res, word_sized = is_word_sized(reg); reg 533 drivers/hwmon/w83627ehf.c w83627ehf_set_bank(data, reg); reg 534 drivers/hwmon/w83627ehf.c outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET); reg 537 drivers/hwmon/w83627ehf.c outb_p((reg & 0xff) + 1, reg 546 drivers/hwmon/w83627ehf.c static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg, reg 549 drivers/hwmon/w83627ehf.c int word_sized = is_word_sized(reg); reg 553 drivers/hwmon/w83627ehf.c w83627ehf_set_bank(data, reg); reg 554 drivers/hwmon/w83627ehf.c outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET); reg 557 drivers/hwmon/w83627ehf.c outb_p((reg & 0xff) + 1, reg 567 drivers/hwmon/w83627ehf.c static u16 w83627ehf_read_temp(struct w83627ehf_data *data, u16 reg) reg 571 drivers/hwmon/w83627ehf.c res = w83627ehf_read_value(data, reg); reg 572 drivers/hwmon/w83627ehf.c if (!is_word_sized(reg)) reg 578 drivers/hwmon/w83627ehf.c static int w83627ehf_write_temp(struct w83627ehf_data *data, u16 reg, reg 581 drivers/hwmon/w83627ehf.c if (!is_word_sized(reg)) reg 583 drivers/hwmon/w83627ehf.c return w83627ehf_write_value(data, reg, value); reg 589 drivers/hwmon/w83627ehf.c u8 reg; reg 593 drivers/hwmon/w83627ehf.c reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x70) reg 595 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg); reg 598 drivers/hwmon/w83627ehf.c reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x7) reg 600 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg); reg 603 drivers/hwmon/w83627ehf.c reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x70) reg 605 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg); reg 608 drivers/hwmon/w83627ehf.c reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x7) reg 610 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg); reg 618 drivers/hwmon/w83627ehf.c u8 reg; reg 622 drivers/hwmon/w83627ehf.c reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf) reg 625 drivers/hwmon/w83627ehf.c reg |= (data->has_fan & (1 << 4)) ? 1 : 0; reg 626 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg); reg 627 drivers/hwmon/w83627ehf.c reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf) reg 629 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg); reg 632 drivers/hwmon/w83627ehf.c reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f) reg 635 drivers/hwmon/w83627ehf.c reg |= (data->has_fan & (1 << 4)) ? 1 : 0; reg 636 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg); reg 637 drivers/hwmon/w83627ehf.c reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf) reg 639 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg); reg 642 drivers/hwmon/w83627ehf.c reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f) reg 644 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg); reg 645 drivers/hwmon/w83627ehf.c reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f) reg 647 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg); reg 650 drivers/hwmon/w83627ehf.c reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc) reg 652 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg); reg 653 drivers/hwmon/w83627ehf.c reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f) reg 655 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg); reg 658 drivers/hwmon/w83627ehf.c reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73) reg 661 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg); reg 814 drivers/hwmon/w83627ehf.c u16 reg; reg 819 drivers/hwmon/w83627ehf.c reg = w83627ehf_read_value(data, data->REG_FAN[i]); reg 820 drivers/hwmon/w83627ehf.c data->rpm[i] = data->fan_from_reg(reg, reg 833 drivers/hwmon/w83627ehf.c && (reg >= 0xff || (sio_data->kind == nct6775 reg 834 drivers/hwmon/w83627ehf.c && reg == 0x00)) reg 929 drivers/hwmon/w83627ehf.c #define show_in_reg(reg) \ reg 931 drivers/hwmon/w83627ehf.c show_##reg(struct device *dev, struct device_attribute *attr, \ reg 938 drivers/hwmon/w83627ehf.c return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr, \ reg 945 drivers/hwmon/w83627ehf.c #define store_in_reg(REG, reg) \ reg 947 drivers/hwmon/w83627ehf.c store_in_##reg(struct device *dev, struct device_attribute *attr, \ reg 960 drivers/hwmon/w83627ehf.c data->in_##reg[nr] = in_to_reg(val, nr, data->scale_in); \ reg 962 drivers/hwmon/w83627ehf.c data->in_##reg[nr]); \ reg 1070 drivers/hwmon/w83627ehf.c unsigned int reg; reg 1099 drivers/hwmon/w83627ehf.c } else if ((reg = 1350000U / val) >= 128 * 255) { reg 1109 drivers/hwmon/w83627ehf.c } else if (!reg) { reg 1126 drivers/hwmon/w83627ehf.c while (reg > 192 && new_div < 7) { reg 1127 drivers/hwmon/w83627ehf.c reg >>= 1; reg 1130 drivers/hwmon/w83627ehf.c data->fan_min[nr] = reg; reg 1200 drivers/hwmon/w83627ehf.c #define show_temp_reg(addr, reg) \ reg 1202 drivers/hwmon/w83627ehf.c show_##reg(struct device *dev, struct device_attribute *attr, \ reg 1209 drivers/hwmon/w83627ehf.c return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->reg[nr])); \ reg 1215 drivers/hwmon/w83627ehf.c #define store_temp_reg(addr, reg) \ reg 1217 drivers/hwmon/w83627ehf.c store_##reg(struct device *dev, struct device_attribute *attr, \ reg 1230 drivers/hwmon/w83627ehf.c data->reg[nr] = LM75_TEMP_TO_REG(val); \ reg 1231 drivers/hwmon/w83627ehf.c w83627ehf_write_temp(data, data->addr[nr], data->reg[nr]); \ reg 1367 drivers/hwmon/w83627ehf.c #define show_pwm_reg(reg) \ reg 1368 drivers/hwmon/w83627ehf.c static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ reg 1375 drivers/hwmon/w83627ehf.c return sprintf(buf, "%d\n", data->reg[nr]); \ reg 1392 drivers/hwmon/w83627ehf.c u16 reg; reg 1406 drivers/hwmon/w83627ehf.c reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]); reg 1408 drivers/hwmon/w83627ehf.c reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]); reg 1410 drivers/hwmon/w83627ehf.c reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr]; reg 1411 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg); reg 1449 drivers/hwmon/w83627ehf.c u16 reg; reg 1464 drivers/hwmon/w83627ehf.c reg = w83627ehf_read_value(data, reg 1466 drivers/hwmon/w83627ehf.c reg &= 0x0f; reg 1467 drivers/hwmon/w83627ehf.c reg |= (val - 1) << 4; reg 1469 drivers/hwmon/w83627ehf.c NCT6775_REG_FAN_MODE[nr], reg); reg 1471 drivers/hwmon/w83627ehf.c reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]); reg 1472 drivers/hwmon/w83627ehf.c reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]); reg 1473 drivers/hwmon/w83627ehf.c reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr]; reg 1474 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg); reg 1481 drivers/hwmon/w83627ehf.c #define show_tol_temp(reg) \ reg 1482 drivers/hwmon/w83627ehf.c static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ reg 1489 drivers/hwmon/w83627ehf.c return sprintf(buf, "%d\n", data->reg[nr] * 1000); \ reg 1526 drivers/hwmon/w83627ehf.c u16 reg; reg 1542 drivers/hwmon/w83627ehf.c reg = w83627ehf_read_value(data, NCT6775_REG_FAN_MODE[nr]); reg 1543 drivers/hwmon/w83627ehf.c reg = (reg & 0xf0) | val; reg 1544 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, NCT6775_REG_FAN_MODE[nr], reg); reg 1546 drivers/hwmon/w83627ehf.c reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]); reg 1548 drivers/hwmon/w83627ehf.c reg = (reg & 0x0f) | (val << 4); reg 1550 drivers/hwmon/w83627ehf.c reg = (reg & 0xf0) | val; reg 1551 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg); reg 1611 drivers/hwmon/w83627ehf.c #define fan_functions(reg, REG) \ reg 1612 drivers/hwmon/w83627ehf.c static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ reg 1619 drivers/hwmon/w83627ehf.c return sprintf(buf, "%d\n", data->reg[nr]); \ reg 1622 drivers/hwmon/w83627ehf.c store_##reg(struct device *dev, struct device_attribute *attr, \ reg 1636 drivers/hwmon/w83627ehf.c data->reg[nr] = val; \ reg 1647 drivers/hwmon/w83627ehf.c #define fan_time_functions(reg, REG) \ reg 1648 drivers/hwmon/w83627ehf.c static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ reg 1656 drivers/hwmon/w83627ehf.c step_time_from_reg(data->reg[nr], \ reg 1661 drivers/hwmon/w83627ehf.c store_##reg(struct device *dev, struct device_attribute *attr, \ reg 1675 drivers/hwmon/w83627ehf.c data->reg[nr] = val; \ reg 1775 drivers/hwmon/w83627ehf.c u16 reg, mask; reg 1783 drivers/hwmon/w83627ehf.c reg = w83627ehf_read_value(data, W83627EHF_REG_CASEOPEN_CLR); reg 1784 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask); reg 1785 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask); reg 2146 drivers/hwmon/w83627ehf.c u8 reg; reg 2149 drivers/hwmon/w83627ehf.c reg = w83627ehf_read_value(data, reg 2152 drivers/hwmon/w83627ehf.c reg = 0; /* Assume AUXTIN is used */ reg 2154 drivers/hwmon/w83627ehf.c if (reg & 0x01) reg 2169 drivers/hwmon/w83627ehf.c u8 reg; reg 2177 drivers/hwmon/w83627ehf.c reg = w83627ehf_read_value(data, 0x4a); reg 2178 drivers/hwmon/w83627ehf.c data->temp_src[0] = reg >> 5; reg 2179 drivers/hwmon/w83627ehf.c reg = w83627ehf_read_value(data, 0x49); reg 2180 drivers/hwmon/w83627ehf.c data->temp_src[1] = reg & 0x07; reg 2181 drivers/hwmon/w83627ehf.c data->temp_src[2] = (reg >> 4) & 0x07; reg 2189 drivers/hwmon/w83627ehf.c reg = w83627ehf_read_value(data, 0x7d); reg 2190 drivers/hwmon/w83627ehf.c reg &= 0x07; reg 2191 drivers/hwmon/w83627ehf.c if (reg != data->temp_src[0] && reg != data->temp_src[1] reg 2192 drivers/hwmon/w83627ehf.c && reg != data->temp_src[2]) { reg 2193 drivers/hwmon/w83627ehf.c data->temp_src[3] = reg; reg 2201 drivers/hwmon/w83627ehf.c reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]); reg 2202 drivers/hwmon/w83627ehf.c if (data->temp_src[2] == 2 && (reg & 0x01)) reg 2216 drivers/hwmon/w83627ehf.c u8 reg; reg 2225 drivers/hwmon/w83627ehf.c reg = w83627ehf_read_value(data, 0x49) & 0x07; reg 2227 drivers/hwmon/w83627ehf.c if (reg == 0) reg 2229 drivers/hwmon/w83627ehf.c else if (reg >= 2 && reg <= 5) reg 2230 drivers/hwmon/w83627ehf.c data->temp_src[1] = reg + 2; reg 2233 drivers/hwmon/w83627ehf.c reg = w83627ehf_read_value(data, 0x4a); reg 2234 drivers/hwmon/w83627ehf.c data->temp_src[2] = reg >> 5; reg 2262 drivers/hwmon/w83627ehf.c u8 reg; reg 2268 drivers/hwmon/w83627ehf.c reg = w83627ehf_read_value(data, reg 2270 drivers/hwmon/w83627ehf.c if (reg & 0x01) reg 100 drivers/hwmon/w83627hf.c superio_outb(struct w83627hf_sio_data *sio, int reg, int val) reg 102 drivers/hwmon/w83627hf.c outb(reg, sio->sioaddr); reg 107 drivers/hwmon/w83627hf.c superio_inb(struct w83627hf_sio_data *sio, int reg) reg 109 drivers/hwmon/w83627hf.c outb(reg, sio->sioaddr); reg 275 drivers/hwmon/w83627hf.c static int TEMP_FROM_REG(u8 reg) reg 277 drivers/hwmon/w83627hf.c return (s8)reg * 1000; reg 284 drivers/hwmon/w83627hf.c static inline unsigned long pwm_freq_from_reg_627hf(u8 reg) reg 287 drivers/hwmon/w83627hf.c freq = W83627HF_BASE_PWM_FREQ >> reg; reg 305 drivers/hwmon/w83627hf.c static inline unsigned long pwm_freq_from_reg(u8 reg) reg 308 drivers/hwmon/w83627hf.c unsigned long clock = (reg & 0x80) ? 180000UL : 24000000UL; reg 310 drivers/hwmon/w83627hf.c reg &= 0x7f; reg 312 drivers/hwmon/w83627hf.c if (reg == 0) reg 313 drivers/hwmon/w83627hf.c reg++; reg 314 drivers/hwmon/w83627hf.c return clock / (reg << 8); reg 395 drivers/hwmon/w83627hf.c static int w83627hf_read_value(struct w83627hf_data *data, u16 reg); reg 396 drivers/hwmon/w83627hf.c static int w83627hf_write_value(struct w83627hf_data *data, u16 reg, u16 value); reg 562 drivers/hwmon/w83627hf.c static ssize_t show_in_0(struct w83627hf_data *data, char *buf, u8 reg) reg 571 drivers/hwmon/w83627hf.c in0 = (long)((reg * 488 + 70000 + 50) / 100); reg 574 drivers/hwmon/w83627hf.c in0 = (long)IN_FROM_REG(reg); reg 915 drivers/hwmon/w83627hf.c u8 reg; reg 933 drivers/hwmon/w83627hf.c reg = w83627hf_read_value(data, W83781D_REG_BEEP_INTS1); reg 935 drivers/hwmon/w83627hf.c reg |= (1 << bitnr); reg 937 drivers/hwmon/w83627hf.c reg &= ~(1 << bitnr); reg 938 drivers/hwmon/w83627hf.c w83627hf_write_value(data, W83781D_REG_BEEP_INTS1, reg); reg 940 drivers/hwmon/w83627hf.c reg = w83627hf_read_value(data, W83781D_REG_BEEP_INTS2); reg 942 drivers/hwmon/w83627hf.c reg |= (1 << (bitnr - 8)); reg 944 drivers/hwmon/w83627hf.c reg &= ~(1 << (bitnr - 8)); reg 945 drivers/hwmon/w83627hf.c w83627hf_write_value(data, W83781D_REG_BEEP_INTS2, reg); reg 947 drivers/hwmon/w83627hf.c reg = w83627hf_read_value(data, W83781D_REG_BEEP_INTS3); reg 949 drivers/hwmon/w83627hf.c reg |= (1 << (bitnr - 16)); reg 951 drivers/hwmon/w83627hf.c reg &= ~(1 << (bitnr - 16)); reg 952 drivers/hwmon/w83627hf.c w83627hf_write_value(data, W83781D_REG_BEEP_INTS3, reg); reg 997 drivers/hwmon/w83627hf.c u8 reg; reg 1013 drivers/hwmon/w83627hf.c reg = (w83627hf_read_value(data, nr==2 ? W83781D_REG_PIN : W83781D_REG_VID_FANDIV) reg 1016 drivers/hwmon/w83627hf.c w83627hf_write_value(data, nr==2 ? W83781D_REG_PIN : W83781D_REG_VID_FANDIV, reg); reg 1018 drivers/hwmon/w83627hf.c reg = (w83627hf_read_value(data, W83781D_REG_VBAT) reg 1021 drivers/hwmon/w83627hf.c w83627hf_write_value(data, W83781D_REG_VBAT, reg); reg 1096 drivers/hwmon/w83627hf.c u8 reg; reg 1108 drivers/hwmon/w83627hf.c reg = w83627hf_read_value(data, W83627THF_REG_PWM_ENABLE[nr]); reg 1109 drivers/hwmon/w83627hf.c reg &= ~(0x03 << W83627THF_PWM_ENABLE_SHIFT[nr]); reg 1110 drivers/hwmon/w83627hf.c reg |= (val - 1) << W83627THF_PWM_ENABLE_SHIFT[nr]; reg 1111 drivers/hwmon/w83627hf.c w83627hf_write_value(data, W83627THF_REG_PWM_ENABLE[nr], reg); reg 1572 drivers/hwmon/w83627hf.c static inline void w83627hf_set_bank(struct w83627hf_data *data, u16 reg) reg 1574 drivers/hwmon/w83627hf.c if ((reg & 0x00f0) == 0x50) { reg 1576 drivers/hwmon/w83627hf.c outb_p(reg >> 8, data->addr + W83781D_DATA_REG_OFFSET); reg 1581 drivers/hwmon/w83627hf.c static inline void w83627hf_reset_bank(struct w83627hf_data *data, u16 reg) reg 1583 drivers/hwmon/w83627hf.c if (reg & 0xff00) { reg 1589 drivers/hwmon/w83627hf.c static int w83627hf_read_value(struct w83627hf_data *data, u16 reg) reg 1594 drivers/hwmon/w83627hf.c word_sized = (((reg & 0xff00) == 0x100) reg 1595 drivers/hwmon/w83627hf.c || ((reg & 0xff00) == 0x200)) reg 1596 drivers/hwmon/w83627hf.c && (((reg & 0x00ff) == 0x50) reg 1597 drivers/hwmon/w83627hf.c || ((reg & 0x00ff) == 0x53) reg 1598 drivers/hwmon/w83627hf.c || ((reg & 0x00ff) == 0x55)); reg 1599 drivers/hwmon/w83627hf.c w83627hf_set_bank(data, reg); reg 1600 drivers/hwmon/w83627hf.c outb_p(reg & 0xff, data->addr + W83781D_ADDR_REG_OFFSET); reg 1603 drivers/hwmon/w83627hf.c outb_p((reg & 0xff) + 1, reg 1609 drivers/hwmon/w83627hf.c w83627hf_reset_bank(data, reg); reg 1697 drivers/hwmon/w83627hf.c static int w83627hf_write_value(struct w83627hf_data *data, u16 reg, u16 value) reg 1702 drivers/hwmon/w83627hf.c word_sized = (((reg & 0xff00) == 0x100) reg 1703 drivers/hwmon/w83627hf.c || ((reg & 0xff00) == 0x200)) reg 1704 drivers/hwmon/w83627hf.c && (((reg & 0x00ff) == 0x53) reg 1705 drivers/hwmon/w83627hf.c || ((reg & 0x00ff) == 0x55)); reg 1706 drivers/hwmon/w83627hf.c w83627hf_set_bank(data, reg); reg 1707 drivers/hwmon/w83627hf.c outb_p(reg & 0xff, data->addr + W83781D_ADDR_REG_OFFSET); reg 1711 drivers/hwmon/w83627hf.c outb_p((reg & 0xff) + 1, reg 1716 drivers/hwmon/w83627hf.c w83627hf_reset_bank(data, reg); reg 1806 drivers/hwmon/w83627hf.c int reg; reg 1808 drivers/hwmon/w83627hf.c reg = w83627hf_read_value(data, W83781D_REG_VID_FANDIV); reg 1809 drivers/hwmon/w83627hf.c data->fan_div[0] = (reg >> 4) & 0x03; reg 1810 drivers/hwmon/w83627hf.c data->fan_div[1] = (reg >> 6) & 0x03; reg 1815 drivers/hwmon/w83627hf.c reg = w83627hf_read_value(data, W83781D_REG_VBAT); reg 1816 drivers/hwmon/w83627hf.c data->fan_div[0] |= (reg >> 3) & 0x04; reg 1817 drivers/hwmon/w83627hf.c data->fan_div[1] |= (reg >> 4) & 0x04; reg 1819 drivers/hwmon/w83627hf.c data->fan_div[2] |= (reg >> 5) & 0x04; reg 51 drivers/hwmon/w83773g.c static inline long temp_of_local(s8 reg) reg 53 drivers/hwmon/w83773g.c return reg * 1000; reg 240 drivers/hwmon/w83781d.c static int w83781d_read_value(struct w83781d_data *data, u16 reg); reg 241 drivers/hwmon/w83781d.c static int w83781d_write_value(struct w83781d_data *data, u16 reg, u16 value); reg 246 drivers/hwmon/w83781d.c #define show_in_reg(reg) \ reg 247 drivers/hwmon/w83781d.c static ssize_t show_##reg(struct device *dev, struct device_attribute *da, \ reg 253 drivers/hwmon/w83781d.c (long)IN_FROM_REG(data->reg[attr->index])); \ reg 259 drivers/hwmon/w83781d.c #define store_in_reg(REG, reg) \ reg 260 drivers/hwmon/w83781d.c static ssize_t store_in_##reg(struct device *dev, struct device_attribute \ reg 271 drivers/hwmon/w83781d.c data->in_##reg[nr] = IN_TO_REG(val); \ reg 273 drivers/hwmon/w83781d.c data->in_##reg[nr]); \ reg 299 drivers/hwmon/w83781d.c #define show_fan_reg(reg) \ reg 300 drivers/hwmon/w83781d.c static ssize_t show_##reg(struct device *dev, struct device_attribute *da, \ reg 306 drivers/hwmon/w83781d.c FAN_FROM_REG(data->reg[attr->index], \ reg 346 drivers/hwmon/w83781d.c #define show_temp_reg(reg) \ reg 347 drivers/hwmon/w83781d.c static ssize_t show_##reg(struct device *dev, struct device_attribute *da, \ reg 355 drivers/hwmon/w83781d.c LM75_TEMP_FROM_REG(data->reg##_add[nr-2])); \ reg 357 drivers/hwmon/w83781d.c return sprintf(buf, "%ld\n", (long)TEMP_FROM_REG(data->reg)); \ reg 364 drivers/hwmon/w83781d.c #define store_temp_reg(REG, reg) \ reg 365 drivers/hwmon/w83781d.c static ssize_t store_temp_##reg(struct device *dev, \ reg 378 drivers/hwmon/w83781d.c data->temp_##reg##_add[nr-2] = LM75_TEMP_TO_REG(val); \ reg 380 drivers/hwmon/w83781d.c data->temp_##reg##_add[nr-2]); \ reg 382 drivers/hwmon/w83781d.c data->temp_##reg = TEMP_TO_REG(val); \ reg 384 drivers/hwmon/w83781d.c data->temp_##reg); \ reg 533 drivers/hwmon/w83781d.c u8 reg; reg 551 drivers/hwmon/w83781d.c reg = w83781d_read_value(data, W83781D_REG_BEEP_INTS1); reg 553 drivers/hwmon/w83781d.c reg |= (1 << bitnr); reg 555 drivers/hwmon/w83781d.c reg &= ~(1 << bitnr); reg 556 drivers/hwmon/w83781d.c w83781d_write_value(data, W83781D_REG_BEEP_INTS1, reg); reg 558 drivers/hwmon/w83781d.c reg = w83781d_read_value(data, W83781D_REG_BEEP_INTS2); reg 560 drivers/hwmon/w83781d.c reg |= (1 << (bitnr - 8)); reg 562 drivers/hwmon/w83781d.c reg &= ~(1 << (bitnr - 8)); reg 563 drivers/hwmon/w83781d.c w83781d_write_value(data, W83781D_REG_BEEP_INTS2, reg); reg 565 drivers/hwmon/w83781d.c reg = w83781d_read_value(data, W83781D_REG_BEEP_INTS3); reg 567 drivers/hwmon/w83781d.c reg |= (1 << (bitnr - 16)); reg 569 drivers/hwmon/w83781d.c reg &= ~(1 << (bitnr - 16)); reg 570 drivers/hwmon/w83781d.c w83781d_write_value(data, W83781D_REG_BEEP_INTS3, reg); reg 642 drivers/hwmon/w83781d.c u8 reg; reg 658 drivers/hwmon/w83781d.c reg = (w83781d_read_value(data, nr == 2 ? reg 663 drivers/hwmon/w83781d.c W83781D_REG_PIN : W83781D_REG_VID_FANDIV, reg); reg 667 drivers/hwmon/w83781d.c reg = (w83781d_read_value(data, W83781D_REG_VBAT) reg 670 drivers/hwmon/w83781d.c w83781d_write_value(data, W83781D_REG_VBAT, reg); reg 730 drivers/hwmon/w83781d.c u32 reg; reg 742 drivers/hwmon/w83781d.c reg = w83781d_read_value(data, W83781D_REG_PWMCLK12); reg 744 drivers/hwmon/w83781d.c (reg & 0xf7) | (val << 3)); reg 746 drivers/hwmon/w83781d.c reg = w83781d_read_value(data, W83781D_REG_BEEP_CONFIG); reg 748 drivers/hwmon/w83781d.c (reg & 0xef) | (!val << 4)); reg 1257 drivers/hwmon/w83781d.c w83781d_read_value_i2c(struct w83781d_data *data, u16 reg) reg 1263 drivers/hwmon/w83781d.c bank = (reg >> 8) & 0x0f; reg 1269 drivers/hwmon/w83781d.c res = i2c_smbus_read_byte_data(client, reg & 0xff); reg 1274 drivers/hwmon/w83781d.c switch (reg & 0xff) { reg 1297 drivers/hwmon/w83781d.c w83781d_write_value_i2c(struct w83781d_data *data, u16 reg, u16 value) reg 1303 drivers/hwmon/w83781d.c bank = (reg >> 8) & 0x0f; reg 1309 drivers/hwmon/w83781d.c i2c_smbus_write_byte_data(client, reg & 0xff, reg 1315 drivers/hwmon/w83781d.c switch (reg & 0xff) { reg 1650 drivers/hwmon/w83781d.c w83781d_read_value_isa(struct w83781d_data *data, u16 reg) reg 1654 drivers/hwmon/w83781d.c word_sized = (((reg & 0xff00) == 0x100) reg 1655 drivers/hwmon/w83781d.c || ((reg & 0xff00) == 0x200)) reg 1656 drivers/hwmon/w83781d.c && (((reg & 0x00ff) == 0x50) reg 1657 drivers/hwmon/w83781d.c || ((reg & 0x00ff) == 0x53) reg 1658 drivers/hwmon/w83781d.c || ((reg & 0x00ff) == 0x55)); reg 1659 drivers/hwmon/w83781d.c if (reg & 0xff00) { reg 1662 drivers/hwmon/w83781d.c outb_p(reg >> 8, reg 1665 drivers/hwmon/w83781d.c outb_p(reg & 0xff, data->isa_addr + W83781D_ADDR_REG_OFFSET); reg 1668 drivers/hwmon/w83781d.c outb_p((reg & 0xff) + 1, reg 1674 drivers/hwmon/w83781d.c if (reg & 0xff00) { reg 1683 drivers/hwmon/w83781d.c w83781d_write_value_isa(struct w83781d_data *data, u16 reg, u16 value) reg 1687 drivers/hwmon/w83781d.c word_sized = (((reg & 0xff00) == 0x100) reg 1688 drivers/hwmon/w83781d.c || ((reg & 0xff00) == 0x200)) reg 1689 drivers/hwmon/w83781d.c && (((reg & 0x00ff) == 0x53) reg 1690 drivers/hwmon/w83781d.c || ((reg & 0x00ff) == 0x55)); reg 1691 drivers/hwmon/w83781d.c if (reg & 0xff00) { reg 1694 drivers/hwmon/w83781d.c outb_p(reg >> 8, reg 1697 drivers/hwmon/w83781d.c outb_p(reg & 0xff, data->isa_addr + W83781D_ADDR_REG_OFFSET); reg 1701 drivers/hwmon/w83781d.c outb_p((reg & 0xff) + 1, reg 1705 drivers/hwmon/w83781d.c if (reg & 0xff00) { reg 1721 drivers/hwmon/w83781d.c w83781d_read_value(struct w83781d_data *data, u16 reg) reg 1728 drivers/hwmon/w83781d.c res = w83781d_read_value_i2c(data, reg); reg 1730 drivers/hwmon/w83781d.c res = w83781d_read_value_isa(data, reg); reg 1736 drivers/hwmon/w83781d.c w83781d_write_value(struct w83781d_data *data, u16 reg, u16 value) reg 1742 drivers/hwmon/w83781d.c w83781d_write_value_i2c(data, reg, value); reg 1744 drivers/hwmon/w83781d.c w83781d_write_value_isa(data, reg, value); reg 1752 drivers/hwmon/w83781d.c int err, reg; reg 1772 drivers/hwmon/w83781d.c reg = w83781d_read_value(data, W83781D_REG_WCHIPID); reg 1773 drivers/hwmon/w83781d.c switch (reg) { reg 2013 drivers/hwmon/w83781d.c w83781d_read_value(struct w83781d_data *data, u16 reg) reg 2018 drivers/hwmon/w83781d.c res = w83781d_read_value_i2c(data, reg); reg 2025 drivers/hwmon/w83781d.c w83781d_write_value(struct w83781d_data *data, u16 reg, u16 value) reg 2028 drivers/hwmon/w83781d.c w83781d_write_value_i2c(data, reg, value); reg 195 drivers/hwmon/w83791d.c static inline int w83791d_read(struct i2c_client *client, u8 reg) reg 197 drivers/hwmon/w83791d.c return i2c_smbus_read_byte_data(client, reg); reg 200 drivers/hwmon/w83791d.c static inline int w83791d_write(struct i2c_client *client, u8 reg, u8 value) reg 202 drivers/hwmon/w83791d.c return i2c_smbus_write_byte_data(client, reg, value); reg 324 drivers/hwmon/w83791d.c static int w83791d_read(struct i2c_client *client, u8 reg); reg 325 drivers/hwmon/w83791d.c static int w83791d_write(struct i2c_client *client, u8 reg, u8 value); reg 353 drivers/hwmon/w83791d.c #define show_in_reg(reg) \ reg 354 drivers/hwmon/w83791d.c static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ reg 361 drivers/hwmon/w83791d.c return sprintf(buf, "%d\n", IN_FROM_REG(data->reg[nr])); \ reg 368 drivers/hwmon/w83791d.c #define store_in_reg(REG, reg) \ reg 369 drivers/hwmon/w83791d.c static ssize_t store_in_##reg(struct device *dev, \ reg 383 drivers/hwmon/w83791d.c data->in_##reg[nr] = IN_TO_REG(val); \ reg 384 drivers/hwmon/w83791d.c w83791d_write(client, W83791D_REG_IN_##REG[nr], data->in_##reg[nr]); \ reg 519 drivers/hwmon/w83791d.c #define show_fan_reg(reg) \ reg 520 drivers/hwmon/w83791d.c static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ reg 528 drivers/hwmon/w83791d.c FAN_FROM_REG(data->reg[nr], DIV_FROM_REG(data->fan_div[nr]))); \ reg 331 drivers/hwmon/w83792d.c static inline int w83792d_read_value(struct i2c_client *client, u8 reg) reg 333 drivers/hwmon/w83792d.c return i2c_smbus_read_byte_data(client, reg); reg 337 drivers/hwmon/w83792d.c w83792d_write_value(struct i2c_client *client, u8 reg, u8 value) reg 339 drivers/hwmon/w83792d.c return i2c_smbus_write_byte_data(client, reg, value); reg 353 drivers/hwmon/w83792d.c #define show_in_reg(reg) \ reg 354 drivers/hwmon/w83792d.c static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ reg 362 drivers/hwmon/w83792d.c (long)(IN_FROM_REG(nr, data->reg[nr]) * 4)); \ reg 368 drivers/hwmon/w83792d.c #define store_in_reg(REG, reg) \ reg 369 drivers/hwmon/w83792d.c static ssize_t store_in_##reg(struct device *dev, \ reg 383 drivers/hwmon/w83792d.c data->in_##reg[nr] = clamp_val(IN_TO_REG(nr, val) / 4, 0, 255); \ reg 385 drivers/hwmon/w83792d.c data->in_##reg[nr]); \ reg 393 drivers/hwmon/w83792d.c #define show_fan_reg(reg) \ reg 394 drivers/hwmon/w83792d.c static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ reg 402 drivers/hwmon/w83792d.c FAN_FROM_REG(data->reg[nr], DIV_FROM_REG(data->fan_div[nr]))); \ reg 739 drivers/hwmon/w83792d.c u8 reg; reg 745 drivers/hwmon/w83792d.c reg = w83792d_read_value(client, W83792D_REG_CHASSIS_CLR); reg 746 drivers/hwmon/w83792d.c w83792d_write_value(client, W83792D_REG_CHASSIS_CLR, reg | 0x80); reg 184 drivers/hwmon/w83793.c static inline unsigned long TIME_FROM_REG(u8 reg) reg 186 drivers/hwmon/w83793.c return reg * 100; reg 194 drivers/hwmon/w83793.c static inline long TEMP_FROM_REG(s8 reg) reg 196 drivers/hwmon/w83793.c return reg * 1000; reg 284 drivers/hwmon/w83793.c static u8 w83793_read_value(struct i2c_client *client, u16 reg); reg 285 drivers/hwmon/w83793.c static int w83793_write_value(struct i2c_client *client, u16 reg, u8 value); reg 445 drivers/hwmon/w83793.c u8 reg; reg 455 drivers/hwmon/w83793.c reg = w83793_read_value(client, W83793_REG_CLR_CHASSIS); reg 456 drivers/hwmon/w83793.c w83793_write_value(client, W83793_REG_CLR_CHASSIS, reg | 0x80); reg 2096 drivers/hwmon/w83793.c static u8 w83793_read_value(struct i2c_client *client, u16 reg) reg 2100 drivers/hwmon/w83793.c u8 new_bank = reg >> 8; reg 2111 drivers/hwmon/w83793.c new_bank, data->bank, reg); reg 2116 drivers/hwmon/w83793.c res = i2c_smbus_read_byte_data(client, reg & 0xff); reg 2122 drivers/hwmon/w83793.c static int w83793_write_value(struct i2c_client *client, u16 reg, u8 value) reg 2126 drivers/hwmon/w83793.c u8 new_bank = reg >> 8; reg 2136 drivers/hwmon/w83793.c new_bank, data->bank, reg); reg 2142 drivers/hwmon/w83793.c res = i2c_smbus_write_byte_data(client, reg & 0xff, value); reg 256 drivers/hwmon/w83795.c static inline unsigned long time_from_reg(u8 reg) reg 258 drivers/hwmon/w83795.c return reg * 100; reg 266 drivers/hwmon/w83795.c static inline long temp_from_reg(s8 reg) reg 268 drivers/hwmon/w83795.c return reg * 1000; reg 281 drivers/hwmon/w83795.c static unsigned int pwm_freq_from_reg(u8 reg, u16 clkin) reg 285 drivers/hwmon/w83795.c if (reg & 0x80) { reg 287 drivers/hwmon/w83795.c return base_clock / ((reg & 0x7f) + 1); reg 289 drivers/hwmon/w83795.c return pwm_freq_cksel0[reg & 0x0f]; reg 417 drivers/hwmon/w83795.c static u8 w83795_read(struct i2c_client *client, u16 reg) reg 421 drivers/hwmon/w83795.c err = w83795_set_bank(client, reg >> 8); reg 425 drivers/hwmon/w83795.c err = i2c_smbus_read_byte_data(client, reg & 0xff); reg 429 drivers/hwmon/w83795.c (int)reg, err); reg 436 drivers/hwmon/w83795.c static int w83795_write(struct i2c_client *client, u16 reg, u8 value) reg 440 drivers/hwmon/w83795.c err = w83795_set_bank(client, reg >> 8); reg 444 drivers/hwmon/w83795.c err = i2c_smbus_write_byte_data(client, reg & 0xff, value); reg 448 drivers/hwmon/w83795.c (int)reg, err); reg 70 drivers/hwmon/w83l785ts.c static u8 w83l785ts_read_value(struct i2c_client *client, u8 reg, u8 defval); reg 221 drivers/hwmon/w83l785ts.c static u8 w83l785ts_read_value(struct i2c_client *client, u8 reg, u8 defval) reg 245 drivers/hwmon/w83l785ts.c value = i2c_smbus_read_byte_data(client, reg); reg 248 drivers/hwmon/w83l785ts.c prefix, value, reg); reg 256 drivers/hwmon/w83l785ts.c reg); reg 139 drivers/hwmon/w83l786ng.c w83l786ng_read_value(struct i2c_client *client, u8 reg) reg 141 drivers/hwmon/w83l786ng.c return i2c_smbus_read_byte_data(client, reg); reg 145 drivers/hwmon/w83l786ng.c w83l786ng_write_value(struct i2c_client *client, u8 reg, u8 value) reg 147 drivers/hwmon/w83l786ng.c return i2c_smbus_write_byte_data(client, reg, value); reg 222 drivers/hwmon/w83l786ng.c #define show_in_reg(reg) \ reg 224 drivers/hwmon/w83l786ng.c show_##reg(struct device *dev, struct device_attribute *attr, \ reg 229 drivers/hwmon/w83l786ng.c return sprintf(buf, "%d\n", IN_FROM_REG(data->reg[nr])); \ reg 236 drivers/hwmon/w83l786ng.c #define store_in_reg(REG, reg) \ reg 238 drivers/hwmon/w83l786ng.c store_in_##reg(struct device *dev, struct device_attribute *attr, \ reg 249 drivers/hwmon/w83l786ng.c data->in_##reg[nr] = IN_TO_REG(val); \ reg 251 drivers/hwmon/w83l786ng.c data->in_##reg[nr]); \ reg 277 drivers/hwmon/w83l786ng.c #define show_fan_reg(reg) \ reg 278 drivers/hwmon/w83l786ng.c static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ reg 284 drivers/hwmon/w83l786ng.c FAN_FROM_REG(data->reg[nr], DIV_FROM_REG(data->fan_div[nr]))); \ reg 461 drivers/hwmon/w83l786ng.c #define show_pwm_reg(reg) \ reg 462 drivers/hwmon/w83l786ng.c static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \ reg 467 drivers/hwmon/w83l786ng.c return sprintf(buf, "%d\n", data->reg[nr]); \ reg 481 drivers/hwmon/w83l786ng.c u8 reg; reg 493 drivers/hwmon/w83l786ng.c reg = w83l786ng_read_value(client, W83L786NG_REG_FAN_CFG); reg 494 drivers/hwmon/w83l786ng.c reg &= ~(1 << W83L786NG_PWM_MODE_SHIFT[nr]); reg 496 drivers/hwmon/w83l786ng.c reg |= 1 << W83L786NG_PWM_MODE_SHIFT[nr]; reg 497 drivers/hwmon/w83l786ng.c w83l786ng_write_value(client, W83L786NG_REG_FAN_CFG, reg); reg 533 drivers/hwmon/w83l786ng.c u8 reg; reg 545 drivers/hwmon/w83l786ng.c reg = w83l786ng_read_value(client, W83L786NG_REG_FAN_CFG); reg 547 drivers/hwmon/w83l786ng.c reg &= ~(0x03 << W83L786NG_PWM_ENABLE_SHIFT[nr]); reg 548 drivers/hwmon/w83l786ng.c reg |= (val - 1) << W83L786NG_PWM_ENABLE_SHIFT[nr]; reg 549 drivers/hwmon/w83l786ng.c w83l786ng_write_value(client, W83L786NG_REG_FAN_CFG, reg); reg 117 drivers/hwspinlock/qcom_hwspinlock.c field.reg = base + i * stride; reg 15 drivers/hwtracing/coresight/coresight-etm-cp14.c int etm_readl_cp14(u32 reg, unsigned int *val) reg 17 drivers/hwtracing/coresight/coresight-etm-cp14.c switch (reg) { reg 306 drivers/hwtracing/coresight/coresight-etm-cp14.c int etm_writel_cp14(u32 reg, u32 val) reg 308 drivers/hwtracing/coresight/coresight-etm-cp14.c switch (reg) { reg 2068 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c struct etmv4_reg *reg = data; reg 2070 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c reg->data = readl_relaxed(reg->addr); reg 2076 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c struct etmv4_reg reg; reg 2078 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c reg.addr = drvdata->base + offset; reg 2083 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c smp_call_function_single(drvdata->cpu, do_smp_cross_read, ®, 1); reg 2084 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c return reg.data; reg 69 drivers/hwtracing/coresight/coresight-replicator.c u32 reg; reg 73 drivers/hwtracing/coresight/coresight-replicator.c reg = REPLICATOR_IDFILTER0; reg 76 drivers/hwtracing/coresight/coresight-replicator.c reg = REPLICATOR_IDFILTER1; reg 91 drivers/hwtracing/coresight/coresight-replicator.c writel_relaxed(0x00, drvdata->base + reg); reg 125 drivers/hwtracing/coresight/coresight-replicator.c u32 reg; reg 129 drivers/hwtracing/coresight/coresight-replicator.c reg = REPLICATOR_IDFILTER0; reg 132 drivers/hwtracing/coresight/coresight-replicator.c reg = REPLICATOR_IDFILTER1; reg 142 drivers/hwtracing/coresight/coresight-replicator.c writel_relaxed(0xff, drvdata->base + reg); reg 64 drivers/hwtracing/intel_th/gth.c unsigned long reg = port & 4 ? REG_GTH_GTHOPT1 : REG_GTH_GTHOPT0; reg 68 drivers/hwtracing/intel_th/gth.c val = ioread32(gth->base + reg); reg 71 drivers/hwtracing/intel_th/gth.c iowrite32(val, gth->base + reg); reg 76 drivers/hwtracing/intel_th/gth.c unsigned long reg = port & 4 ? REG_GTH_GTHOPT1 : REG_GTH_GTHOPT0; reg 80 drivers/hwtracing/intel_th/gth.c val = ioread32(gth->base + reg); reg 90 drivers/hwtracing/intel_th/gth.c unsigned long reg = REG_GTH_SMCR0 + ((port / 2) * 4); reg 94 drivers/hwtracing/intel_th/gth.c val = ioread32(gth->base + reg); reg 97 drivers/hwtracing/intel_th/gth.c iowrite32(val, gth->base + reg); reg 102 drivers/hwtracing/intel_th/gth.c unsigned long reg = REG_GTH_SMCR0 + ((port / 2) * 4); reg 106 drivers/hwtracing/intel_th/gth.c val = ioread32(gth->base + reg); reg 126 drivers/hwtracing/intel_th/gth.c unsigned int reg = REG_GTH_SWDEST0 + ((master >> 1) & ~3u); reg 131 drivers/hwtracing/intel_th/gth.c reg = REG_GTH_GSWTDEST; reg 135 drivers/hwtracing/intel_th/gth.c val = ioread32(gth->base + reg); reg 139 drivers/hwtracing/intel_th/gth.c iowrite32(val, gth->base + reg); reg 280 drivers/hwtracing/intel_th/gth.c u32 reg; reg 283 drivers/hwtracing/intel_th/gth.c reg = ioread32(gth->base + REG_GTH_SCRPD0); reg 284 drivers/hwtracing/intel_th/gth.c if (reg & SCRPD_DEBUGGER_IN_USE) reg 288 drivers/hwtracing/intel_th/gth.c reg |= SCRPD_STH_IS_ENABLED | SCRPD_TRIGGER_IS_ENABLED; reg 289 drivers/hwtracing/intel_th/gth.c iowrite32(reg, gth->base + REG_GTH_SCRPD0); reg 482 drivers/hwtracing/intel_th/gth.c u32 reg; reg 489 drivers/hwtracing/intel_th/gth.c for (reg = 0, count = GTH_PLE_WAITLOOP_DEPTH; reg 490 drivers/hwtracing/intel_th/gth.c count && !(reg & BIT(output->port)); count--) { reg 491 drivers/hwtracing/intel_th/gth.c reg = ioread32(gth->base + REG_GTH_STAT); reg 540 drivers/hwtracing/intel_th/gth.c u32 reg; reg 553 drivers/hwtracing/intel_th/gth.c reg = ioread32(gth->base + REG_GTH_SCRPD0); reg 554 drivers/hwtracing/intel_th/gth.c reg &= ~output->scratchpad; reg 555 drivers/hwtracing/intel_th/gth.c iowrite32(reg, gth->base + REG_GTH_SCRPD0); reg 560 drivers/hwtracing/intel_th/gth.c u32 reg; reg 562 drivers/hwtracing/intel_th/gth.c reg = ioread32(gth->base + REG_TSCU_TSUCTRL); reg 563 drivers/hwtracing/intel_th/gth.c reg &= ~TSUCTRL_CTCRESYNC; reg 564 drivers/hwtracing/intel_th/gth.c iowrite32(reg, gth->base + REG_TSCU_TSUCTRL); reg 615 drivers/hwtracing/intel_th/gth.c u32 reg; reg 621 drivers/hwtracing/intel_th/gth.c for (reg = 0, count = CTS_TRIG_WAITLOOP_DEPTH; reg 622 drivers/hwtracing/intel_th/gth.c count && !(reg & BIT(4)); count--) { reg 623 drivers/hwtracing/intel_th/gth.c reg = ioread32(gth->base + REG_CTS_STAT); reg 759 drivers/hwtracing/intel_th/msu.c u32 reg; reg 776 drivers/hwtracing/intel_th/msu.c reg = msc->base_addr >> PAGE_SHIFT; reg 777 drivers/hwtracing/intel_th/msu.c iowrite32(reg, msc->reg_base + REG_MSU_MSC0BAR); reg 780 drivers/hwtracing/intel_th/msu.c reg = msc->nr_pages; reg 781 drivers/hwtracing/intel_th/msu.c iowrite32(reg, msc->reg_base + REG_MSU_MSC0SIZE); reg 784 drivers/hwtracing/intel_th/msu.c reg = ioread32(msc->reg_base + REG_MSU_MSC0CTL); reg 785 drivers/hwtracing/intel_th/msu.c reg &= ~(MSC_MODE | MSC_WRAPEN | MSC_EN | MSC_RD_HDR_OVRD); reg 787 drivers/hwtracing/intel_th/msu.c reg |= MSC_EN; reg 788 drivers/hwtracing/intel_th/msu.c reg |= msc->mode << __ffs(MSC_MODE); reg 789 drivers/hwtracing/intel_th/msu.c reg |= msc->burst_len << __ffs(MSC_LEN); reg 792 drivers/hwtracing/intel_th/msu.c reg |= MSC_WRAPEN; reg 794 drivers/hwtracing/intel_th/msu.c iowrite32(reg, msc->reg_base + REG_MSU_MSC0CTL); reg 818 drivers/hwtracing/intel_th/msu.c u32 reg; reg 831 drivers/hwtracing/intel_th/msu.c reg = ioread32(msc->reg_base + REG_MSU_MSC0STS); reg 832 drivers/hwtracing/intel_th/msu.c msc->single_wrap = !!(reg & MSCSTS_WRAPSTAT); reg 834 drivers/hwtracing/intel_th/msu.c reg = ioread32(msc->reg_base + REG_MSU_MSC0MWP); reg 835 drivers/hwtracing/intel_th/msu.c msc->single_sz = reg & ((msc->nr_pages << PAGE_SHIFT) - 1); reg 837 drivers/hwtracing/intel_th/msu.c reg, msc->single_sz, msc->single_wrap); reg 840 drivers/hwtracing/intel_th/msu.c reg = ioread32(msc->reg_base + REG_MSU_MSC0CTL); reg 841 drivers/hwtracing/intel_th/msu.c reg &= ~MSC_EN; reg 842 drivers/hwtracing/intel_th/msu.c iowrite32(reg, msc->reg_base + REG_MSU_MSC0CTL); reg 856 drivers/hwtracing/intel_th/msu.c reg = ioread32(msc->reg_base + REG_MSU_MSC0STS); reg 857 drivers/hwtracing/intel_th/msu.c dev_dbg(msc_dev(msc), "MSCnSTS: %08x\n", reg); reg 859 drivers/hwtracing/intel_th/msu.c reg = ioread32(msc->reg_base + REG_MSU_MSUSTS); reg 860 drivers/hwtracing/intel_th/msu.c reg &= msc->index ? MSUSTS_MSC1BLAST : MSUSTS_MSC0BLAST; reg 861 drivers/hwtracing/intel_th/msu.c iowrite32(reg, msc->reg_base + REG_MSU_MSUSTS); reg 1652 drivers/hwtracing/intel_th/msu.c u32 reg; reg 1654 drivers/hwtracing/intel_th/msu.c for (reg = 0, count = MSC_PLE_WAITLOOP_DEPTH; reg 1655 drivers/hwtracing/intel_th/msu.c count && !(reg & MSCSTS_PLE); count--) { reg 1656 drivers/hwtracing/intel_th/msu.c reg = __raw_readl(msc->reg_base + REG_MSU_MSC0STS); reg 74 drivers/hwtracing/intel_th/sth.c unsigned long reg = REG_STH_TRIG; reg 86 drivers/hwtracing/intel_th/sth.c reg += 4; reg 90 drivers/hwtracing/intel_th/sth.c reg += 8; reg 95 drivers/hwtracing/intel_th/sth.c reg += 4; reg 96 drivers/hwtracing/intel_th/sth.c writeb_relaxed(*payload, sth->base + reg); reg 171 drivers/hwtracing/intel_th/sth.c u32 reg; reg 173 drivers/hwtracing/intel_th/sth.c reg = ioread32(sth->base + REG_STH_STHCAP1); reg 174 drivers/hwtracing/intel_th/sth.c sth->stm.sw_nchannels = reg & 0xff; reg 176 drivers/hwtracing/intel_th/sth.c reg = ioread32(sth->base + REG_STH_STHCAP0); reg 177 drivers/hwtracing/intel_th/sth.c sth->stm.sw_start = reg & 0xffff; reg 178 drivers/hwtracing/intel_th/sth.c sth->stm.sw_end = reg >> 16; reg 26 drivers/i2c/algos/i2c-algo-pca.c #define pca_outw(adap, reg, val) adap->write_byte(adap->data, reg, val) reg 27 drivers/i2c/algos/i2c-algo-pca.c #define pca_inw(adap, reg) adap->read_byte(adap->data, reg) reg 239 drivers/i2c/busses/i2c-ali1563.c u32 reg; reg 242 drivers/i2c/busses/i2c-ali1563.c reg = inb_p(SMB_HST_STS); reg 243 drivers/i2c/busses/i2c-ali1563.c if (!(reg & HST_STS_BUSY)) reg 247 drivers/i2c/busses/i2c-ali1563.c dev_warn(&a->dev, "SMBus not idle. HST_STS = %02x\n", reg); reg 46 drivers/i2c/busses/i2c-amd-mp2-pci.c void __iomem *reg; reg 50 drivers/i2c/busses/i2c-amd-mp2-pci.c reg = privdata->mmio + ((i2c_cmd_base.s.bus_id == 1) ? reg 52 drivers/i2c/busses/i2c-amd-mp2-pci.c writel(i2c_cmd_base.ul, reg); reg 214 drivers/i2c/busses/i2c-amd-mp2-pci.c void __iomem *reg; reg 222 drivers/i2c/busses/i2c-amd-mp2-pci.c reg = privdata->mmio + ((bus_id == 0) ? reg 224 drivers/i2c/busses/i2c-amd-mp2-pci.c val = readl(reg); reg 226 drivers/i2c/busses/i2c-amd-mp2-pci.c writel(0, reg); reg 286 drivers/i2c/busses/i2c-amd-mp2-pci.c int reg; reg 288 drivers/i2c/busses/i2c-amd-mp2-pci.c for (reg = AMD_C2P_MSG0; reg <= AMD_C2P_MSG9; reg += 4) reg 289 drivers/i2c/busses/i2c-amd-mp2-pci.c writel(0, privdata->mmio + reg); reg 291 drivers/i2c/busses/i2c-amd-mp2-pci.c for (reg = AMD_P2C_MSG1; reg <= AMD_P2C_MSG2; reg += 4) reg 292 drivers/i2c/busses/i2c-amd-mp2-pci.c writel(0, privdata->mmio + reg); reg 29 drivers/i2c/busses/i2c-at91-core.c unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg) reg 31 drivers/i2c/busses/i2c-at91-core.c return readl_relaxed(dev->base + reg); reg 34 drivers/i2c/busses/i2c-at91-core.c void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val) reg 36 drivers/i2c/busses/i2c-at91-core.c writel_relaxed(val, dev->base + reg); reg 150 drivers/i2c/busses/i2c-at91.h unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg); reg 151 drivers/i2c/busses/i2c-at91.h void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val); reg 69 drivers/i2c/busses/i2c-bcm2835.c u32 reg, u32 val) reg 71 drivers/i2c/busses/i2c-bcm2835.c writel(val, i2c_dev->regs + reg); reg 74 drivers/i2c/busses/i2c-bcm2835.c static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg) reg 76 drivers/i2c/busses/i2c-bcm2835.c return readl(i2c_dev->regs + reg); reg 178 drivers/i2c/busses/i2c-cadence.c u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); reg 179 drivers/i2c/busses/i2c-cadence.c if (reg & CDNS_I2C_CR_HOLD) reg 180 drivers/i2c/busses/i2c-cadence.c cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET); reg 515 drivers/i2c/busses/i2c-cadence.c u32 reg; reg 522 drivers/i2c/busses/i2c-cadence.c reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); reg 524 drivers/i2c/busses/i2c-cadence.c if (reg & CDNS_I2C_CR_NEA) reg 525 drivers/i2c/busses/i2c-cadence.c cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA, reg 528 drivers/i2c/busses/i2c-cadence.c if (!(reg & CDNS_I2C_CR_NEA)) reg 529 drivers/i2c/busses/i2c-cadence.c cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA, reg 572 drivers/i2c/busses/i2c-cadence.c u32 reg; reg 607 drivers/i2c/busses/i2c-cadence.c reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); reg 608 drivers/i2c/busses/i2c-cadence.c reg |= CDNS_I2C_CR_HOLD; reg 609 drivers/i2c/busses/i2c-cadence.c cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET); reg 115 drivers/i2c/busses/i2c-cbus-gpio.c unsigned reg, unsigned data) reg 136 drivers/i2c/busses/i2c-cbus-gpio.c cbus_send_data(host, reg, CBUS_REG_BITS); reg 59 drivers/i2c/busses/i2c-cht-wc.c int ret, reg; reg 64 drivers/i2c/busses/i2c-cht-wc.c ret = regmap_read(adap->regmap, CHT_WC_EXTCHGRIRQ, ®); reg 71 drivers/i2c/busses/i2c-cht-wc.c reg &= ~adap->irq_mask; reg 82 drivers/i2c/busses/i2c-cht-wc.c ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ, reg); reg 86 drivers/i2c/busses/i2c-cht-wc.c if (reg & CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK) { reg 87 drivers/i2c/busses/i2c-cht-wc.c adap->io_error |= !!(reg & CHT_WC_EXTCHGRIRQ_NACK_IRQ); reg 93 drivers/i2c/busses/i2c-cht-wc.c if (reg & CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK) reg 102 drivers/i2c/busses/i2c-cht-wc.c if (reg & CHT_WC_EXTCHGRIRQ_CLIENT_IRQ) { reg 314 drivers/i2c/busses/i2c-cht-wc.c int ret, reg, irq; reg 342 drivers/i2c/busses/i2c-cht-wc.c ret = regmap_read(adap->regmap, CHT_WC_I2C_RDDATA, ®); reg 145 drivers/i2c/busses/i2c-davinci.c int reg, u16 val) reg 147 drivers/i2c/busses/i2c-davinci.c writew_relaxed(val, i2c_dev->base + reg); reg 150 drivers/i2c/busses/i2c-davinci.c static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg) reg 152 drivers/i2c/busses/i2c-davinci.c return readw_relaxed(i2c_dev->base + reg); reg 94 drivers/i2c/busses/i2c-designware-common.c u32 reg; reg 101 drivers/i2c/busses/i2c-designware-common.c reg = dw_readl(dev, DW_IC_COMP_TYPE); reg 104 drivers/i2c/busses/i2c-designware-common.c if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) { reg 107 drivers/i2c/busses/i2c-designware-common.c } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) { reg 110 drivers/i2c/busses/i2c-designware-common.c } else if (reg != DW_IC_COMP_TYPE_VALUE) { reg 112 drivers/i2c/busses/i2c-designware-common.c "Unknown Synopsys component type: 0x%08x\n", reg); reg 176 drivers/i2c/busses/i2c-designware-common.c u32 reg; reg 184 drivers/i2c/busses/i2c-designware-common.c reg = dw_readl(dev, DW_IC_COMP_VERSION); reg 185 drivers/i2c/busses/i2c-designware-common.c if (reg >= DW_IC_SDA_HOLD_MIN_VERS) { reg 299 drivers/i2c/busses/i2c-efm32.c u32 reg = efm32_i2c_read32(ddata, REG_ROUTE); reg 301 drivers/i2c/busses/i2c-efm32.c return (reg & REG_ROUTE_LOCATION__MASK) >> reg 75 drivers/i2c/busses/i2c-emev2.c static inline void em_clear_set_bit(struct em_i2c_device *priv, u8 clear, u8 set, u8 reg) reg 77 drivers/i2c/busses/i2c-emev2.c writeb((readb(priv->base + reg) & ~clear) | set, priv->base + reg); reg 163 drivers/i2c/busses/i2c-fsi.c static int fsi_i2c_read_reg(struct fsi_device *fsi, unsigned int reg, reg 169 drivers/i2c/busses/i2c-fsi.c rc = fsi_device_read(fsi, reg, &data_be, sizeof(data_be)); reg 178 drivers/i2c/busses/i2c-fsi.c static int fsi_i2c_write_reg(struct fsi_device *fsi, unsigned int reg, reg 183 drivers/i2c/busses/i2c-fsi.c return fsi_device_write(fsi, reg, &data_be, sizeof(data_be)); reg 306 drivers/i2c/busses/i2c-gpio.c u32 reg; reg 310 drivers/i2c/busses/i2c-gpio.c if (!of_property_read_u32(np, "i2c-gpio,timeout-ms", ®)) reg 311 drivers/i2c/busses/i2c-gpio.c pdata->timeout = msecs_to_jiffies(reg); reg 271 drivers/i2c/busses/i2c-imx.c struct imx_i2c_struct *i2c_imx, unsigned int reg) reg 273 drivers/i2c/busses/i2c-imx.c writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); reg 277 drivers/i2c/busses/i2c-imx.c unsigned int reg) reg 279 drivers/i2c/busses/i2c-imx.c return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); reg 102 drivers/i2c/busses/i2c-meson.c static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask, reg 107 drivers/i2c/busses/i2c-meson.c data = readl(i2c->regs + reg); reg 110 drivers/i2c/busses/i2c-meson.c writel(data, i2c->regs + reg); reg 324 drivers/i2c/busses/i2c-mpc.c u32 __iomem *reg; reg 339 drivers/i2c/busses/i2c-mpc.c reg = ioremap(get_immrbase() + *prop + 0x14, 0x4); reg 340 drivers/i2c/busses/i2c-mpc.c if (!reg) reg 344 drivers/i2c/busses/i2c-mpc.c val = in_be32(reg) & 0x00000020; /* sec-cfg */ reg 345 drivers/i2c/busses/i2c-mpc.c iounmap(reg); reg 328 drivers/i2c/busses/i2c-mt65xx.c static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg) reg 330 drivers/i2c/busses/i2c-mt65xx.c return readw(i2c->base + i2c->dev_comp->regs[reg]); reg 334 drivers/i2c/busses/i2c-mt65xx.c enum I2C_REGS_OFFSET reg) reg 336 drivers/i2c/busses/i2c-mt65xx.c writew(val, i2c->base + i2c->dev_comp->regs[reg]); reg 335 drivers/i2c/busses/i2c-mxs.c u32 reg; reg 340 drivers/i2c/busses/i2c-mxs.c reg = readl(i2c->regs + MXS_I2C_CTRL0); reg 341 drivers/i2c/busses/i2c-mxs.c reg |= MXS_I2C_CTRL0_RUN; reg 342 drivers/i2c/busses/i2c-mxs.c writel(reg, i2c->regs + MXS_I2C_CTRL0); reg 197 drivers/i2c/busses/i2c-nomadik.c static inline void i2c_set_bit(void __iomem *reg, u32 mask) reg 199 drivers/i2c/busses/i2c-nomadik.c writel(readl(reg) | mask, reg); reg 202 drivers/i2c/busses/i2c-nomadik.c static inline void i2c_clr_bit(void __iomem *reg, u32 mask) reg 204 drivers/i2c/busses/i2c-nomadik.c writel(readl(reg) & ~mask, reg); reg 49 drivers/i2c/busses/i2c-ocores.c void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value); reg 50 drivers/i2c/busses/i2c-ocores.c u8 (*getreg)(struct ocores_i2c *i2c, int reg); reg 90 drivers/i2c/busses/i2c-ocores.c static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value) reg 92 drivers/i2c/busses/i2c-ocores.c iowrite8(value, i2c->base + (reg << i2c->reg_shift)); reg 95 drivers/i2c/busses/i2c-ocores.c static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value) reg 97 drivers/i2c/busses/i2c-ocores.c iowrite16(value, i2c->base + (reg << i2c->reg_shift)); reg 100 drivers/i2c/busses/i2c-ocores.c static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value) reg 102 drivers/i2c/busses/i2c-ocores.c iowrite32(value, i2c->base + (reg << i2c->reg_shift)); reg 105 drivers/i2c/busses/i2c-ocores.c static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value) reg 107 drivers/i2c/busses/i2c-ocores.c iowrite16be(value, i2c->base + (reg << i2c->reg_shift)); reg 110 drivers/i2c/busses/i2c-ocores.c static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value) reg 112 drivers/i2c/busses/i2c-ocores.c iowrite32be(value, i2c->base + (reg << i2c->reg_shift)); reg 115 drivers/i2c/busses/i2c-ocores.c static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg) reg 117 drivers/i2c/busses/i2c-ocores.c return ioread8(i2c->base + (reg << i2c->reg_shift)); reg 120 drivers/i2c/busses/i2c-ocores.c static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg) reg 122 drivers/i2c/busses/i2c-ocores.c return ioread16(i2c->base + (reg << i2c->reg_shift)); reg 125 drivers/i2c/busses/i2c-ocores.c static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg) reg 127 drivers/i2c/busses/i2c-ocores.c return ioread32(i2c->base + (reg << i2c->reg_shift)); reg 130 drivers/i2c/busses/i2c-ocores.c static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg) reg 132 drivers/i2c/busses/i2c-ocores.c return ioread16be(i2c->base + (reg << i2c->reg_shift)); reg 135 drivers/i2c/busses/i2c-ocores.c static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg) reg 137 drivers/i2c/busses/i2c-ocores.c return ioread32be(i2c->base + (reg << i2c->reg_shift)); reg 140 drivers/i2c/busses/i2c-ocores.c static void oc_setreg_io_8(struct ocores_i2c *i2c, int reg, u8 value) reg 142 drivers/i2c/busses/i2c-ocores.c outb(value, i2c->iobase + reg); reg 145 drivers/i2c/busses/i2c-ocores.c static inline u8 oc_getreg_io_8(struct ocores_i2c *i2c, int reg) reg 147 drivers/i2c/busses/i2c-ocores.c return inb(i2c->iobase + reg); reg 150 drivers/i2c/busses/i2c-ocores.c static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value) reg 152 drivers/i2c/busses/i2c-ocores.c i2c->setreg(i2c, reg, value); reg 155 drivers/i2c/busses/i2c-ocores.c static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg) reg 157 drivers/i2c/busses/i2c-ocores.c return i2c->getreg(i2c, reg); reg 281 drivers/i2c/busses/i2c-ocores.c int reg, u8 mask, u8 val, reg 288 drivers/i2c/busses/i2c-ocores.c u8 status = oc_getreg(i2c, reg); reg 495 drivers/i2c/busses/i2c-ocores.c static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg) reg 498 drivers/i2c/busses/i2c-ocores.c int rreg = reg; reg 500 drivers/i2c/busses/i2c-ocores.c if (reg != OCI2C_PRELOW) reg 503 drivers/i2c/busses/i2c-ocores.c if (reg == OCI2C_PREHIGH) reg 509 drivers/i2c/busses/i2c-ocores.c static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value) reg 512 drivers/i2c/busses/i2c-ocores.c int rreg = reg; reg 514 drivers/i2c/busses/i2c-ocores.c if (reg != OCI2C_PRELOW) reg 516 drivers/i2c/busses/i2c-ocores.c if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) { reg 518 drivers/i2c/busses/i2c-ocores.c if (reg == OCI2C_PRELOW) reg 266 drivers/i2c/busses/i2c-omap.c int reg, u16 val) reg 269 drivers/i2c/busses/i2c-omap.c (omap->regs[reg] << omap->reg_shift)); reg 272 drivers/i2c/busses/i2c-omap.c static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *omap, int reg) reg 275 drivers/i2c/busses/i2c-omap.c (omap->regs[reg] << omap->reg_shift)); reg 1283 drivers/i2c/busses/i2c-omap.c u32 reg; reg 1285 drivers/i2c/busses/i2c-omap.c reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); reg 1287 drivers/i2c/busses/i2c-omap.c return reg & OMAP_I2C_SYSTEST_SCL_I_FUNC; reg 1293 drivers/i2c/busses/i2c-omap.c u32 reg; reg 1295 drivers/i2c/busses/i2c-omap.c reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); reg 1297 drivers/i2c/busses/i2c-omap.c return reg & OMAP_I2C_SYSTEST_SDA_I_FUNC; reg 1303 drivers/i2c/busses/i2c-omap.c u32 reg; reg 1305 drivers/i2c/busses/i2c-omap.c reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); reg 1307 drivers/i2c/busses/i2c-omap.c reg |= OMAP_I2C_SYSTEST_SCL_O; reg 1309 drivers/i2c/busses/i2c-omap.c reg &= ~OMAP_I2C_SYSTEST_SCL_O; reg 1310 drivers/i2c/busses/i2c-omap.c omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg); reg 1316 drivers/i2c/busses/i2c-omap.c u32 reg; reg 1318 drivers/i2c/busses/i2c-omap.c reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); reg 1320 drivers/i2c/busses/i2c-omap.c reg |= OMAP_I2C_SYSTEST_ST_EN; reg 1322 drivers/i2c/busses/i2c-omap.c reg |= 3 << OMAP_I2C_SYSTEST_TMODE_SHIFT; reg 1324 drivers/i2c/busses/i2c-omap.c reg |= OMAP_I2C_SYSTEST_SCL_O; reg 1326 drivers/i2c/busses/i2c-omap.c reg |= OMAP_I2C_SYSTEST_SDA_O; reg 1327 drivers/i2c/busses/i2c-omap.c omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg); reg 1333 drivers/i2c/busses/i2c-omap.c u32 reg; reg 1335 drivers/i2c/busses/i2c-omap.c reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG); reg 1337 drivers/i2c/busses/i2c-omap.c reg &= ~OMAP_I2C_SYSTEST_ST_EN; reg 1338 drivers/i2c/busses/i2c-omap.c reg &= ~OMAP_I2C_SYSTEST_TMODE_MASK; reg 1339 drivers/i2c/busses/i2c-omap.c reg &= ~OMAP_I2C_SYSTEST_SCL_O; reg 1340 drivers/i2c/busses/i2c-omap.c reg &= ~OMAP_I2C_SYSTEST_SDA_O; reg 1341 drivers/i2c/busses/i2c-omap.c omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg); reg 106 drivers/i2c/busses/i2c-owl.c static void owl_i2c_update_reg(void __iomem *reg, unsigned int val, bool state) reg 110 drivers/i2c/busses/i2c-owl.c regval = readl(reg); reg 117 drivers/i2c/busses/i2c-owl.c writel(regval, reg); reg 52 drivers/i2c/busses/i2c-pasemi.c static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val) reg 55 drivers/i2c/busses/i2c-pasemi.c smbus->base + reg, val); reg 56 drivers/i2c/busses/i2c-pasemi.c outl(val, smbus->base + reg); reg 59 drivers/i2c/busses/i2c-pasemi.c static inline int reg_read(struct pasemi_smbus *smbus, int reg) reg 62 drivers/i2c/busses/i2c-pasemi.c ret = inl(smbus->base + reg); reg 64 drivers/i2c/busses/i2c-pasemi.c smbus->base + reg, ret); reg 68 drivers/i2c/busses/i2c-pasemi.c #define TXFIFO_WR(smbus, reg) reg_write((smbus), REG_MTXFIFO, (reg)) reg 37 drivers/i2c/busses/i2c-pca-isa.c static void pca_isa_writebyte(void *pd, int reg, int val) reg 41 drivers/i2c/busses/i2c-pca-isa.c printk(KERN_DEBUG "*** write %s at %#lx <= %#04x\n", names[reg], reg 42 drivers/i2c/busses/i2c-pca-isa.c base+reg, val); reg 44 drivers/i2c/busses/i2c-pca-isa.c outb(val, base+reg); reg 47 drivers/i2c/busses/i2c-pca-isa.c static int pca_isa_readbyte(void *pd, int reg) reg 49 drivers/i2c/busses/i2c-pca-isa.c int res = inb(base+reg); reg 53 drivers/i2c/busses/i2c-pca-isa.c printk(KERN_DEBUG "*** read %s => %#04x\n", names[reg], res); reg 42 drivers/i2c/busses/i2c-pca-platform.c static int i2c_pca_pf_readbyte8(void *pd, int reg) reg 45 drivers/i2c/busses/i2c-pca-platform.c return ioread8(i2c->reg_base + reg); reg 48 drivers/i2c/busses/i2c-pca-platform.c static int i2c_pca_pf_readbyte16(void *pd, int reg) reg 51 drivers/i2c/busses/i2c-pca-platform.c return ioread8(i2c->reg_base + reg * 2); reg 54 drivers/i2c/busses/i2c-pca-platform.c static int i2c_pca_pf_readbyte32(void *pd, int reg) reg 57 drivers/i2c/busses/i2c-pca-platform.c return ioread8(i2c->reg_base + reg * 4); reg 60 drivers/i2c/busses/i2c-pca-platform.c static void i2c_pca_pf_writebyte8(void *pd, int reg, int val) reg 63 drivers/i2c/busses/i2c-pca-platform.c iowrite8(val, i2c->reg_base + reg); reg 66 drivers/i2c/busses/i2c-pca-platform.c static void i2c_pca_pf_writebyte16(void *pd, int reg, int val) reg 69 drivers/i2c/busses/i2c-pca-platform.c iowrite8(val, i2c->reg_base + reg * 2); reg 72 drivers/i2c/busses/i2c-pca-platform.c static void i2c_pca_pf_writebyte32(void *pd, int reg, int val) reg 75 drivers/i2c/busses/i2c-pca-platform.c iowrite8(val, i2c->reg_base + reg * 4); reg 161 drivers/i2c/busses/i2c-pmcmsp.c static inline void pmcmsptwi_reg_to_cfg(u32 reg, struct pmcmsptwi_cfg *cfg) reg 163 drivers/i2c/busses/i2c-pmcmsp.c cfg->arbf = (reg >> 12) & 0xf; reg 164 drivers/i2c/busses/i2c-pmcmsp.c cfg->nak = (reg >> 8) & 0xf; reg 165 drivers/i2c/busses/i2c-pmcmsp.c cfg->add10 = (reg >> 7) & 0x1; reg 166 drivers/i2c/busses/i2c-pmcmsp.c cfg->mst_code = (reg >> 4) & 0x7; reg 167 drivers/i2c/busses/i2c-pmcmsp.c cfg->arb = (reg >> 1) & 0x1; reg 168 drivers/i2c/busses/i2c-pmcmsp.c cfg->highspeed = reg & 0x1; reg 212 drivers/i2c/busses/i2c-pmcmsp.c static enum pmcmsptwi_xfer_result pmcmsptwi_get_result(u32 reg) reg 214 drivers/i2c/busses/i2c-pmcmsp.c if (reg & MSP_TWI_INT_STS_LOST_ARBITRATION) { reg 218 drivers/i2c/busses/i2c-pmcmsp.c } else if (reg & MSP_TWI_INT_STS_NO_RESPONSE) { reg 222 drivers/i2c/busses/i2c-pmcmsp.c } else if (reg & MSP_TWI_INT_STS_DATA_COLLISION) { reg 226 drivers/i2c/busses/i2c-pmcmsp.c } else if (reg & MSP_TWI_INT_STS_BUSY) { reg 409 drivers/i2c/busses/i2c-pmcmsp.c u32 reg, struct pmcmsptwi_data *data) reg 411 drivers/i2c/busses/i2c-pmcmsp.c dev_dbg(&pmcmsptwi_adapter.dev, "Writing cmd reg 0x%08x\n", reg); reg 412 drivers/i2c/busses/i2c-pmcmsp.c pmcmsptwi_writel(reg, data->iobase + MSP_TWI_CMD_REG_OFFSET); reg 151 drivers/i2c/busses/i2c-rcar.c static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) reg 153 drivers/i2c/busses/i2c-rcar.c writel(val, priv->io + reg); reg 156 drivers/i2c/busses/i2c-rcar.c static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) reg 158 drivers/i2c/busses/i2c-rcar.c return readl(priv->io + reg); reg 107 drivers/i2c/busses/i2c-riic.c static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg) reg 109 drivers/i2c/busses/i2c-riic.c writeb((readb(riic->base + reg) & ~clear) | set, riic->base + reg); reg 102 drivers/i2c/busses/i2c-sh7760.c static inline void OUT32(struct cami2c *cam, int reg, unsigned long val) reg 104 drivers/i2c/busses/i2c-sh7760.c __raw_writel(val, (unsigned long)cam->iobase + reg); reg 107 drivers/i2c/busses/i2c-sh7760.c static inline unsigned long IN32(struct cami2c *cam, int reg) reg 109 drivers/i2c/busses/i2c-sh7760.c return __raw_readl((unsigned long)cam->iobase + reg); reg 115 drivers/i2c/busses/i2c-sh_mobile.c void __iomem *reg; reg 192 drivers/i2c/busses/i2c-sh_mobile.c iowrite8(data, pd->reg + offs); reg 197 drivers/i2c/busses/i2c-sh_mobile.c return ioread8(pd->reg + offs); reg 849 drivers/i2c/busses/i2c-sh_mobile.c pd->reg = devm_ioremap_resource(&dev->dev, res); reg 850 drivers/i2c/busses/i2c-sh_mobile.c if (IS_ERR(pd->reg)) reg 851 drivers/i2c/busses/i2c-sh_mobile.c return PTR_ERR(pd->reg); reg 21 drivers/i2c/busses/i2c-simtec.c void __iomem *reg; reg 37 drivers/i2c/busses/i2c-simtec.c writeb(CMD_SET_SDA | (state ? STATE_SDA : 0), pd->reg); reg 43 drivers/i2c/busses/i2c-simtec.c writeb(CMD_SET_SCL | (state ? STATE_SCL : 0), pd->reg); reg 49 drivers/i2c/busses/i2c-simtec.c return readb(pd->reg) & STATE_SDA ? 1 : 0; reg 55 drivers/i2c/busses/i2c-simtec.c return readb(pd->reg) & STATE_SCL ? 1 : 0; reg 89 drivers/i2c/busses/i2c-simtec.c pd->reg = ioremap(res->start, size); reg 90 drivers/i2c/busses/i2c-simtec.c if (pd->reg == NULL) { reg 119 drivers/i2c/busses/i2c-simtec.c iounmap(pd->reg); reg 135 drivers/i2c/busses/i2c-simtec.c iounmap(pd->reg); reg 121 drivers/i2c/busses/i2c-sis5595.c static u8 sis5595_read(u8 reg) reg 123 drivers/i2c/busses/i2c-sis5595.c outb(reg, sis5595_base + SMB_INDEX); reg 127 drivers/i2c/busses/i2c-sis5595.c static void sis5595_write(u8 reg, u8 data) reg 129 drivers/i2c/busses/i2c-sis5595.c outb(reg, sis5595_base + SMB_INDEX); reg 111 drivers/i2c/busses/i2c-sis630.c static inline u8 sis630_read(u8 reg) reg 113 drivers/i2c/busses/i2c-sis630.c return inb(smbus_base + reg); reg 116 drivers/i2c/busses/i2c-sis630.c static inline void sis630_write(u8 reg, u8 data) reg 118 drivers/i2c/busses/i2c-sis630.c outb(data, smbus_base + reg); reg 66 drivers/i2c/busses/i2c-sis96x.c static inline u8 sis96x_read(u8 reg) reg 68 drivers/i2c/busses/i2c-sis96x.c return inb(sis96x_smbus_base + reg) ; reg 71 drivers/i2c/busses/i2c-sis96x.c static inline void sis96x_write(u8 reg, u8 data) reg 73 drivers/i2c/busses/i2c-sis96x.c outb(data, sis96x_smbus_base + reg) ; reg 197 drivers/i2c/busses/i2c-st.c static inline void st_i2c_set_bits(void __iomem *reg, u32 mask) reg 199 drivers/i2c/busses/i2c-st.c writel_relaxed(readl_relaxed(reg) | mask, reg); reg 202 drivers/i2c/busses/i2c-st.c static inline void st_i2c_clr_bits(void __iomem *reg, u32 mask) reg 204 drivers/i2c/busses/i2c-st.c writel_relaxed(readl_relaxed(reg) & ~mask, reg); reg 134 drivers/i2c/busses/i2c-stm32f4.c static inline void stm32f4_i2c_set_bits(void __iomem *reg, u32 mask) reg 136 drivers/i2c/busses/i2c-stm32f4.c writel_relaxed(readl_relaxed(reg) | mask, reg); reg 139 drivers/i2c/busses/i2c-stm32f4.c static inline void stm32f4_i2c_clr_bits(void __iomem *reg, u32 mask) reg 141 drivers/i2c/busses/i2c-stm32f4.c writel_relaxed(readl_relaxed(reg) & ~mask, reg); reg 146 drivers/i2c/busses/i2c-stm32f4.c void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; reg 148 drivers/i2c/busses/i2c-stm32f4.c stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_IRQ_MASK); reg 352 drivers/i2c/busses/i2c-stm32f4.c void __iomem *reg; reg 356 drivers/i2c/busses/i2c-stm32f4.c reg = i2c_dev->base + STM32F4_I2C_CR1; reg 358 drivers/i2c/busses/i2c-stm32f4.c stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP); reg 360 drivers/i2c/busses/i2c-stm32f4.c stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START); reg 372 drivers/i2c/busses/i2c-stm32f4.c void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; reg 381 drivers/i2c/busses/i2c-stm32f4.c stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN); reg 397 drivers/i2c/busses/i2c-stm32f4.c void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; reg 415 drivers/i2c/busses/i2c-stm32f4.c stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN); reg 437 drivers/i2c/busses/i2c-stm32f4.c void __iomem *reg; reg 451 drivers/i2c/busses/i2c-stm32f4.c reg = i2c_dev->base + STM32F4_I2C_CR1; reg 453 drivers/i2c/busses/i2c-stm32f4.c stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP); reg 455 drivers/i2c/busses/i2c-stm32f4.c stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START); reg 460 drivers/i2c/busses/i2c-stm32f4.c reg = i2c_dev->base + STM32F4_I2C_CR2; reg 462 drivers/i2c/busses/i2c-stm32f4.c stm32f4_i2c_clr_bits(reg, mask); reg 472 drivers/i2c/busses/i2c-stm32f4.c reg = i2c_dev->base + STM32F4_I2C_CR1; reg 473 drivers/i2c/busses/i2c-stm32f4.c stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR1_ACK); reg 632 drivers/i2c/busses/i2c-stm32f4.c void __iomem *reg; reg 650 drivers/i2c/busses/i2c-stm32f4.c reg = i2c_dev->base + STM32F4_I2C_CR1; reg 651 drivers/i2c/busses/i2c-stm32f4.c stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP); reg 683 drivers/i2c/busses/i2c-stm32f4.c void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR1; reg 706 drivers/i2c/busses/i2c-stm32f4.c stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START); reg 361 drivers/i2c/busses/i2c-stm32f7.c static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask) reg 363 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(readl_relaxed(reg) | mask, reg); reg 366 drivers/i2c/busses/i2c-stm32f7.c static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask) reg 368 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(readl_relaxed(reg) & ~mask, reg); reg 1788 drivers/i2c/busses/i2c-stm32f7.c u32 reg, mask; reg 1796 drivers/i2c/busses/i2c-stm32f7.c ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, ®); reg 1804 drivers/i2c/busses/i2c-stm32f7.c return regmap_update_bits(i2c_dev->regmap, reg, mask, mask); reg 285 drivers/i2c/busses/i2c-tegra.c unsigned long reg) reg 287 drivers/i2c/busses/i2c-tegra.c writel(val, i2c_dev->base + reg); reg 290 drivers/i2c/busses/i2c-tegra.c static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) reg 292 drivers/i2c/busses/i2c-tegra.c return readl(i2c_dev->base + reg); reg 300 drivers/i2c/busses/i2c-tegra.c unsigned long reg) reg 303 drivers/i2c/busses/i2c-tegra.c reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; reg 304 drivers/i2c/busses/i2c-tegra.c return reg; reg 308 drivers/i2c/busses/i2c-tegra.c unsigned long reg) reg 310 drivers/i2c/busses/i2c-tegra.c writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); reg 313 drivers/i2c/busses/i2c-tegra.c if (reg != I2C_TX_FIFO) reg 314 drivers/i2c/busses/i2c-tegra.c readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); reg 317 drivers/i2c/busses/i2c-tegra.c static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) reg 319 drivers/i2c/busses/i2c-tegra.c return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); reg 323 drivers/i2c/busses/i2c-tegra.c unsigned long reg, int len) reg 325 drivers/i2c/busses/i2c-tegra.c writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); reg 329 drivers/i2c/busses/i2c-tegra.c unsigned long reg, int len) reg 331 drivers/i2c/busses/i2c-tegra.c readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); reg 935 drivers/i2c/busses/i2c-tegra.c u32 val, reg; reg 943 drivers/i2c/busses/i2c-tegra.c reg = I2C_MST_FIFO_CONTROL; reg 945 drivers/i2c/busses/i2c-tegra.c reg = I2C_FIFO_CONTROL; reg 999 drivers/i2c/busses/i2c-tegra.c i2c_writel(i2c_dev, val, reg); reg 1007 drivers/i2c/busses/i2c-tegra.c u32 reg; reg 1010 drivers/i2c/busses/i2c-tegra.c reg = (I2C_BC_SCLK_THRESHOLD << I2C_BC_SCLK_THRESHOLD_SHIFT) | reg 1012 drivers/i2c/busses/i2c-tegra.c i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG); reg 1019 drivers/i2c/busses/i2c-tegra.c reg |= I2C_BC_ENABLE; reg 1020 drivers/i2c/busses/i2c-tegra.c i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG); reg 1030 drivers/i2c/busses/i2c-tegra.c reg = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS); reg 1031 drivers/i2c/busses/i2c-tegra.c if (!(reg & I2C_BC_STATUS)) { reg 178 drivers/i2c/busses/i2c-xiic.c static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) reg 181 drivers/i2c/busses/i2c-xiic.c iowrite8(value, i2c->base + reg); reg 183 drivers/i2c/busses/i2c-xiic.c iowrite8(value, i2c->base + reg + 3); reg 186 drivers/i2c/busses/i2c-xiic.c static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) reg 191 drivers/i2c/busses/i2c-xiic.c ret = ioread8(i2c->base + reg); reg 193 drivers/i2c/busses/i2c-xiic.c ret = ioread8(i2c->base + reg + 3); reg 197 drivers/i2c/busses/i2c-xiic.c static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) reg 200 drivers/i2c/busses/i2c-xiic.c iowrite16(value, i2c->base + reg); reg 202 drivers/i2c/busses/i2c-xiic.c iowrite16be(value, i2c->base + reg + 2); reg 205 drivers/i2c/busses/i2c-xiic.c static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) reg 208 drivers/i2c/busses/i2c-xiic.c iowrite32(value, i2c->base + reg); reg 210 drivers/i2c/busses/i2c-xiic.c iowrite32be(value, i2c->base + reg); reg 213 drivers/i2c/busses/i2c-xiic.c static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) reg 218 drivers/i2c/busses/i2c-xiic.c ret = ioread32(i2c->base + reg); reg 220 drivers/i2c/busses/i2c-xiic.c ret = ioread32be(i2c->base + reg); reg 104 drivers/i2c/busses/i2c-xlp9xx.c unsigned long reg, u32 val) reg 106 drivers/i2c/busses/i2c-xlp9xx.c writel(val, priv->base + reg); reg 110 drivers/i2c/busses/i2c-xlp9xx.c unsigned long reg) reg 112 drivers/i2c/busses/i2c-xlp9xx.c return readl(priv->base + reg); reg 64 drivers/i2c/busses/i2c-xlr.c static inline void xlr_i2c_wreg(u32 __iomem *base, unsigned int reg, u32 val) reg 66 drivers/i2c/busses/i2c-xlr.c __raw_writel(val, base + reg); reg 69 drivers/i2c/busses/i2c-xlr.c static inline u32 xlr_i2c_rdreg(u32 __iomem *base, unsigned int reg) reg 71 drivers/i2c/busses/i2c-xlr.c return __raw_readl(base + reg); reg 70 drivers/i2c/busses/i2c-zx2967.c u32 val, unsigned long reg) reg 72 drivers/i2c/busses/i2c-zx2967.c writel_relaxed(val, i2c->reg_base + reg); reg 75 drivers/i2c/busses/i2c-zx2967.c static u32 zx2967_i2c_readl(struct zx2967_i2c *i2c, unsigned long reg) reg 77 drivers/i2c/busses/i2c-zx2967.c return readl_relaxed(i2c->reg_base + reg); reg 81 drivers/i2c/busses/i2c-zx2967.c void *data, unsigned long reg, int len) reg 83 drivers/i2c/busses/i2c-zx2967.c writesb(i2c->reg_base + reg, data, len); reg 87 drivers/i2c/busses/i2c-zx2967.c void *data, unsigned long reg, int len) reg 89 drivers/i2c/busses/i2c-zx2967.c readsb(i2c->reg_base + reg, data, len); reg 97 drivers/i2c/i2c-core-slave.c u32 reg; reg 100 drivers/i2c/i2c-core-slave.c of_property_read_u32(child, "reg", ®); reg 101 drivers/i2c/i2c-core-slave.c if (reg & I2C_OWN_SLAVE_ADDRESS) { reg 357 drivers/i2c/i2c-mux.c u32 reg; reg 368 drivers/i2c/i2c-mux.c if (!of_property_read_u32(mux_node, "reg", ®)) { reg 381 drivers/i2c/i2c-mux.c ret = of_property_read_u32(child, "reg", ®); reg 384 drivers/i2c/i2c-mux.c if (chan_id == reg) reg 63 drivers/i2c/muxes/i2c-mux-ltc4306.c static bool ltc4306_is_volatile_reg(struct device *dev, unsigned int reg) reg 65 drivers/i2c/muxes/i2c-mux-ltc4306.c return (reg == LTC_REG_CONFIG) ? true : false; reg 132 drivers/i2c/muxes/i2c-mux-pca9541.c int reg; reg 134 drivers/i2c/muxes/i2c-mux-pca9541.c reg = pca9541_reg_read(client, PCA9541_CONTROL); reg 135 drivers/i2c/muxes/i2c-mux-pca9541.c if (reg >= 0 && !busoff(reg) && mybus(reg)) reg 137 drivers/i2c/muxes/i2c-mux-pca9541.c (reg & PCA9541_CTL_NBUSON) >> 1); reg 181 drivers/i2c/muxes/i2c-mux-pca9541.c int reg; reg 183 drivers/i2c/muxes/i2c-mux-pca9541.c reg = pca9541_reg_read(client, PCA9541_CONTROL); reg 184 drivers/i2c/muxes/i2c-mux-pca9541.c if (reg < 0) reg 185 drivers/i2c/muxes/i2c-mux-pca9541.c return reg; reg 187 drivers/i2c/muxes/i2c-mux-pca9541.c if (busoff(reg)) { reg 202 drivers/i2c/muxes/i2c-mux-pca9541.c pca9541_control[reg & 0x0f] reg 212 drivers/i2c/muxes/i2c-mux-pca9541.c } else if (mybus(reg)) { reg 217 drivers/i2c/muxes/i2c-mux-pca9541.c if (reg & (PCA9541_CTL_NTESTON | PCA9541_CTL_BUSINIT)) reg 220 drivers/i2c/muxes/i2c-mux-pca9541.c reg & ~(PCA9541_CTL_NTESTON reg 234 drivers/i2c/muxes/i2c-mux-pca9541.c pca9541_control[reg & 0x0f] reg 239 drivers/i2c/muxes/i2c-mux-pca9541.c if (!(reg & PCA9541_CTL_NTESTON)) reg 242 drivers/i2c/muxes/i2c-mux-pca9541.c reg | PCA9541_CTL_NTESTON); reg 25 drivers/i2c/muxes/i2c-mux-reg.c if (!mux->data.reg) reg 37 drivers/i2c/muxes/i2c-mux-reg.c iowrite32(chan_id, mux->data.reg); reg 39 drivers/i2c/muxes/i2c-mux-reg.c iowrite32be(chan_id, mux->data.reg); reg 41 drivers/i2c/muxes/i2c-mux-reg.c ioread32(mux->data.reg); reg 45 drivers/i2c/muxes/i2c-mux-reg.c iowrite16(chan_id, mux->data.reg); reg 47 drivers/i2c/muxes/i2c-mux-reg.c iowrite16be(chan_id, mux->data.reg); reg 49 drivers/i2c/muxes/i2c-mux-reg.c ioread16(mux->data.reg); reg 52 drivers/i2c/muxes/i2c-mux-reg.c iowrite8(chan_id, mux->data.reg); reg 54 drivers/i2c/muxes/i2c-mux-reg.c ioread8(mux->data.reg); reg 141 drivers/i2c/muxes/i2c-mux-reg.c mux->data.reg = devm_ioremap_resource(&pdev->dev, &res); reg 142 drivers/i2c/muxes/i2c-mux-reg.c if (IS_ERR(mux->data.reg)) reg 143 drivers/i2c/muxes/i2c-mux-reg.c return PTR_ERR(mux->data.reg); reg 187 drivers/i2c/muxes/i2c-mux-reg.c if (!mux->data.reg) { reg 192 drivers/i2c/muxes/i2c-mux-reg.c mux->data.reg = devm_ioremap_resource(&pdev->dev, res); reg 193 drivers/i2c/muxes/i2c-mux-reg.c if (IS_ERR(mux->data.reg)) { reg 194 drivers/i2c/muxes/i2c-mux-reg.c ret = PTR_ERR(mux->data.reg); reg 1936 drivers/i3c/master.c struct device_node *node, u32 *reg) reg 1961 drivers/i3c/master.c boardinfo->lvr = reg[2]; reg 1971 drivers/i3c/master.c struct device_node *node, u32 *reg) reg 1982 drivers/i3c/master.c if (reg[0]) { reg 1983 drivers/i3c/master.c if (reg[0] > I3C_MAX_ADDR) reg 1987 drivers/i3c/master.c reg[0]); reg 1992 drivers/i3c/master.c boardinfo->static_addr = reg[0]; reg 2004 drivers/i3c/master.c boardinfo->pid = ((u64)reg[1] << 32) | reg[2]; reg 2020 drivers/i3c/master.c u32 reg[3]; reg 2026 drivers/i3c/master.c ret = of_property_read_u32_array(node, "reg", reg, ARRAY_SIZE(reg)); reg 2034 drivers/i3c/master.c if (!reg[1]) reg 2035 drivers/i3c/master.c ret = of_i3c_master_add_i2c_boardinfo(master, node, reg); reg 2037 drivers/i3c/master.c ret = of_i3c_master_add_i3c_boardinfo(master, node, reg); reg 60 drivers/ide/ali14xx.c typedef struct { u8 reg, data; } RegInitializer; reg 91 drivers/ide/ali14xx.c static inline u8 inReg(u8 reg) reg 93 drivers/ide/ali14xx.c outb_p(reg, regPort); reg 100 drivers/ide/ali14xx.c static void outReg(u8 data, u8 reg) reg 102 drivers/ide/ali14xx.c outb_p(reg, regPort); reg 190 drivers/ide/ali14xx.c for (p = initData; p->reg != 0; ++p) reg 191 drivers/ide/ali14xx.c outReg(p->data, p->reg); reg 189 drivers/ide/cmd640.c static void (*__put_cmd640_reg)(u16 reg, u8 val); reg 190 drivers/ide/cmd640.c static u8 (*__get_cmd640_reg)(u16 reg); reg 205 drivers/ide/cmd640.c static void put_cmd640_reg_pci1(u16 reg, u8 val) reg 207 drivers/ide/cmd640.c outl_p((reg & 0xfc) | cmd640_key, 0xcf8); reg 208 drivers/ide/cmd640.c outb_p(val, (reg & 3) | 0xcfc); reg 211 drivers/ide/cmd640.c static u8 get_cmd640_reg_pci1(u16 reg) reg 213 drivers/ide/cmd640.c outl_p((reg & 0xfc) | cmd640_key, 0xcf8); reg 214 drivers/ide/cmd640.c return inb_p((reg & 3) | 0xcfc); reg 219 drivers/ide/cmd640.c static void put_cmd640_reg_pci2(u16 reg, u8 val) reg 222 drivers/ide/cmd640.c outb_p(val, cmd640_key + reg); reg 226 drivers/ide/cmd640.c static u8 get_cmd640_reg_pci2(u16 reg) reg 231 drivers/ide/cmd640.c b = inb_p(cmd640_key + reg); reg 238 drivers/ide/cmd640.c static void put_cmd640_reg_vlb(u16 reg, u8 val) reg 240 drivers/ide/cmd640.c outb_p(reg, cmd640_key); reg 244 drivers/ide/cmd640.c static u8 get_cmd640_reg_vlb(u16 reg) reg 246 drivers/ide/cmd640.c outb_p(reg, cmd640_key); reg 250 drivers/ide/cmd640.c static u8 get_cmd640_reg(u16 reg) reg 256 drivers/ide/cmd640.c b = __get_cmd640_reg(reg); reg 261 drivers/ide/cmd640.c static void put_cmd640_reg(u16 reg, u8 val) reg 266 drivers/ide/cmd640.c __put_cmd640_reg(reg, val); reg 367 drivers/ide/cmd640.c unsigned int reg = cmd640_vlb ? 0x50 : 0x00; reg 371 drivers/ide/cmd640.c for (; reg <= 0x59; reg++) { reg 372 drivers/ide/cmd640.c if (!(reg & 0x0f)) reg 373 drivers/ide/cmd640.c printk("\n%04x:", reg); reg 374 drivers/ide/cmd640.c printk(" %02x", get_cmd640_reg(reg)); reg 414 drivers/ide/cmd640.c int reg = prefetch_regs[index]; reg 418 drivers/ide/cmd640.c b = __get_cmd640_reg(reg); reg 424 drivers/ide/cmd640.c __put_cmd640_reg(reg, b); reg 408 drivers/ide/cmd64x.c d.enablebits[0].reg = 0; reg 106 drivers/ide/cs5530.c unsigned int reg, timings = 0; reg 117 drivers/ide/cs5530.c reg = inl(basereg + 4); /* get drive0 config register */ reg 118 drivers/ide/cs5530.c timings |= reg & 0x80000000; /* preserve PIO format bit */ reg 123 drivers/ide/cs5530.c reg |= 0x00100000; /* enable UDMA timings for both drives */ reg 125 drivers/ide/cs5530.c reg &= ~0x00100000; /* disable UDMA timings for both drives */ reg 126 drivers/ide/cs5530.c outl(reg, basereg + 4); /* write drive0 config register */ reg 75 drivers/ide/cs5535.c u32 reg = 0, dummy; reg 93 drivers/ide/cs5535.c reg = (cs5535_pio_cmd_timings[cmd] << 16) | reg 95 drivers/ide/cs5535.c wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0); reg 98 drivers/ide/cs5535.c rdmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy); reg 100 drivers/ide/cs5535.c if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) != reg 102 drivers/ide/cs5535.c reg &= 0x0000FFFF; reg 103 drivers/ide/cs5535.c reg |= cs5535_pio_cmd_timings[cmd] << 16; reg 104 drivers/ide/cs5535.c wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0); reg 108 drivers/ide/cs5535.c rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy); reg 110 drivers/ide/cs5535.c reg | 0x80000000UL, 0); reg 112 drivers/ide/cs5535.c rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy); reg 114 drivers/ide/cs5535.c reg &= 0x80000000UL; /* Preserve the PIO format bit */ reg 117 drivers/ide/cs5535.c reg |= cs5535_udma_timings[speed - XFER_UDMA_0]; reg 119 drivers/ide/cs5535.c reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0]; reg 123 drivers/ide/cs5535.c wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0); reg 58 drivers/ide/cs5536.c static int cs5536_read(struct pci_dev *pdev, int reg, u32 *val) reg 63 drivers/ide/cs5536.c rdmsr(MSR_IDE_CFG + reg, *val, dummy); reg 67 drivers/ide/cs5536.c return pci_read_config_dword(pdev, PCI_IDE_CFG + reg * 4, val); reg 70 drivers/ide/cs5536.c static int cs5536_write(struct pci_dev *pdev, int reg, int val) reg 73 drivers/ide/cs5536.c wrmsr(MSR_IDE_CFG + reg, val, 0); reg 77 drivers/ide/cs5536.c return pci_write_config_dword(pdev, PCI_IDE_CFG + reg * 4, val); reg 39 drivers/ide/opti621.c static void write_reg(u8 value, int reg) reg 44 drivers/ide/opti621.c outb(value, reg_base + reg); reg 53 drivers/ide/opti621.c static u8 read_reg(int reg) reg 60 drivers/ide/opti621.c ret = inb(reg_base + reg); reg 28 drivers/ide/rz1000.c u16 reg; reg 30 drivers/ide/rz1000.c if (!pci_read_config_word (dev, 0x40, ®) && reg 31 drivers/ide/rz1000.c !pci_write_config_word(dev, 0x40, reg & 0xdfff)) { reg 129 drivers/ide/sc1200.c unsigned int reg, timings; reg 159 drivers/ide/sc1200.c pci_read_config_dword(dev, basereg + 4, ®); reg 160 drivers/ide/sc1200.c timings |= reg & 0x80000000; /* preserve PIO format bit */ reg 170 drivers/ide/serverworks.c unsigned int reg; reg 182 drivers/ide/serverworks.c pci_read_config_dword(isa_dev, 0x64, ®); reg 183 drivers/ide/serverworks.c reg &= ~0x00002000; /* disable 600ns interrupt mask */ reg 184 drivers/ide/serverworks.c if(!(reg & 0x00004000)) reg 187 drivers/ide/serverworks.c reg |= 0x00004000; /* enable UDMA/33 support */ reg 188 drivers/ide/serverworks.c pci_write_config_dword(isa_dev, 0x64, reg); reg 469 drivers/ide/setup-pci.c if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || reg 321 drivers/ide/sis5513.c u8 drive_pci = 0x40 + drive->dn * 2, reg = 0, i = chipset_family; reg 323 drivers/ide/sis5513.c pci_read_config_byte(dev, drive_pci + 1, ®); reg 326 drivers/ide/sis5513.c reg |= 0x80; reg 328 drivers/ide/sis5513.c reg &= ~((0xff >> (8 - cycle_time_range[i])) << cycle_time_offset[i]); reg 330 drivers/ide/sis5513.c reg |= cycle_time_value[i][mode - XFER_UDMA_0] << cycle_time_offset[i]; reg 332 drivers/ide/sis5513.c pci_write_config_byte(dev, drive_pci + 1, reg); reg 460 drivers/ide/sis5513.c u8 reg; reg 478 drivers/ide/sis5513.c pci_read_config_byte(dev, 0x49, ®); reg 479 drivers/ide/sis5513.c if (!(reg & 0x01)) reg 480 drivers/ide/sis5513.c pci_write_config_byte(dev, 0x49, reg|0x01); reg 488 drivers/ide/sis5513.c pci_read_config_byte(dev, 0x52, ®); reg 489 drivers/ide/sis5513.c if (!(reg & 0x04)) reg 490 drivers/ide/sis5513.c pci_write_config_byte(dev, 0x52, reg|0x04); reg 494 drivers/ide/sis5513.c pci_read_config_byte(dev, 0x09, ®); reg 495 drivers/ide/sis5513.c if ((reg & 0x0f) != 0x00) reg 496 drivers/ide/sis5513.c pci_write_config_byte(dev, 0x09, reg&0xf0); reg 501 drivers/ide/sis5513.c pci_read_config_byte(dev, 0x52, ®); reg 502 drivers/ide/sis5513.c if (!(reg & 0x08)) reg 503 drivers/ide/sis5513.c pci_write_config_byte(dev, 0x52, reg|0x08); reg 71 drivers/ide/sl82c105.c int reg = 0x44 + drive->dn * 4; reg 85 drivers/ide/sl82c105.c pci_write_config_word(dev, reg, drv_ctrl); reg 86 drivers/ide/sl82c105.c pci_read_config_word (dev, reg, &drv_ctrl); reg 190 drivers/ide/sl82c105.c int reg = 0x44 + drive->dn * 4; reg 192 drivers/ide/sl82c105.c pci_write_config_word(dev, reg, reg 209 drivers/ide/sl82c105.c int reg = 0x44 + drive->dn * 4; reg 212 drivers/ide/sl82c105.c pci_write_config_word(dev, reg, reg 148 drivers/ide/trm290.c u16 reg = 0; reg 152 drivers/ide/trm290.c reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82); reg 156 drivers/ide/trm290.c if (reg != hwif->select_data) { reg 157 drivers/ide/trm290.c hwif->select_data = reg; reg 160 drivers/ide/trm290.c outw(reg & 0xff, hwif->config_data); reg 165 drivers/ide/trm290.c reg = inw(hwif->config_data + 3); reg 166 drivers/ide/trm290.c reg &= 0x13; reg 167 drivers/ide/trm290.c reg &= ~(1 << hwif->channel); reg 168 drivers/ide/trm290.c outw(reg, hwif->config_data + 3); reg 239 drivers/ide/trm290.c u8 reg = 0; reg 264 drivers/ide/trm290.c reg = inb(hwif->config_data + 3); reg 266 drivers/ide/trm290.c reg = (reg & 0x10) | 0x03; reg 267 drivers/ide/trm290.c outb(reg, hwif->config_data + 3); reg 270 drivers/ide/trm290.c if (reg & 0x10) reg 84 drivers/ide/tx4939ide.c static u16 tx4939ide_readw(void __iomem *base, u32 reg) reg 86 drivers/ide/tx4939ide.c return __raw_readw(base + tx4939ide_swizzlew(reg)); reg 88 drivers/ide/tx4939ide.c static u8 tx4939ide_readb(void __iomem *base, u32 reg) reg 90 drivers/ide/tx4939ide.c return __raw_readb(base + tx4939ide_swizzleb(reg)); reg 92 drivers/ide/tx4939ide.c static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg) reg 94 drivers/ide/tx4939ide.c __raw_writel(val, base + tx4939ide_swizzlel(reg)); reg 96 drivers/ide/tx4939ide.c static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg) reg 98 drivers/ide/tx4939ide.c __raw_writew(val, base + tx4939ide_swizzlew(reg)); reg 100 drivers/ide/tx4939ide.c static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg) reg 102 drivers/ide/tx4939ide.c __raw_writeb(val, base + tx4939ide_swizzleb(reg)); reg 460 drivers/ide/via82cxxx.c d.enablebits[1].reg = d.enablebits[0].reg = 0; reg 225 drivers/iio/accel/adxl372.c #define ADXL372_ACCEL_CHANNEL(index, reg, axis) { \ reg 227 drivers/iio/accel/adxl372.c .address = reg, \ reg 631 drivers/iio/accel/adxl372.c unsigned int reg, reg 638 drivers/iio/accel/adxl372.c return regmap_read(st->regmap, reg, readval); reg 640 drivers/iio/accel/adxl372.c return regmap_write(st->regmap, reg, writeval); reg 914 drivers/iio/accel/adxl372.c bool adxl372_readable_noinc_reg(struct device *dev, unsigned int reg) reg 916 drivers/iio/accel/adxl372.c return (reg == ADXL372_FIFO_DATA); reg 15 drivers/iio/accel/adxl372.h bool adxl372_readable_noinc_reg(struct device *dev, unsigned int reg); reg 164 drivers/iio/accel/bma180.c static int bma180_set_bits(struct bma180_data *data, u8 reg, u8 mask, u8 val) reg 166 drivers/iio/accel/bma180.c int ret = i2c_smbus_read_byte_data(data->client, reg); reg 172 drivers/iio/accel/bma180.c return i2c_smbus_write_byte_data(data->client, reg, reg_val); reg 35 drivers/iio/accel/bma220_spi.c #define BMA220_ACCEL_CHANNEL(index, reg, axis) { \ reg 37 drivers/iio/accel/bma220_spi.c .address = reg, \ reg 87 drivers/iio/accel/bma220_spi.c static inline int bma220_read_reg(struct spi_device *spi, u8 reg) reg 89 drivers/iio/accel/bma220_spi.c return spi_w8r8(spi, reg | BMA220_READ_MASK); reg 1381 drivers/iio/accel/bmc150-accel-core.c u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1; reg 1384 drivers/iio/accel/bmc150-accel-core.c ret = regmap_write(data->regmap, reg, data->fifo_mode); reg 35 drivers/iio/accel/da280.c #define DA280_CHANNEL(reg, axis) { \ reg 37 drivers/iio/accel/da280.c .address = reg, \ reg 80 drivers/iio/accel/da311.c #define DA311_CHANNEL(reg, axis) { \ reg 82 drivers/iio/accel/da311.c .address = reg, \ reg 54 drivers/iio/accel/dmard10.c #define DMARD10_CHANNEL(reg, axis) { \ reg 56 drivers/iio/accel/dmard10.c .address = reg, \ reg 701 drivers/iio/accel/kxcjk-1013.c u8 reg = KXCJK1013_REG_XOUT_L + axis * 2; reg 704 drivers/iio/accel/kxcjk-1013.c ret = i2c_smbus_read_word_data(data->client, reg); reg 40 drivers/iio/accel/mc3230.c #define MC3230_CHANNEL(reg, axis) { \ reg 42 drivers/iio/accel/mc3230.c .address = reg, \ reg 60 drivers/iio/accel/mma7455_core.c unsigned int reg; reg 65 drivers/iio/accel/mma7455_core.c ret = regmap_read(mma7455->regmap, MMA7455_REG_STATUS, ®); reg 69 drivers/iio/accel/mma7455_core.c if (reg & MMA7455_STATUS_DRDY) reg 111 drivers/iio/accel/mma7455_core.c unsigned int reg; reg 140 drivers/iio/accel/mma7455_core.c ret = regmap_read(mma7455->regmap, MMA7455_REG_CTL1, ®); reg 144 drivers/iio/accel/mma7455_core.c if (reg & MMA7455_CTL1_DFBW_MASK) reg 239 drivers/iio/accel/mma7455_core.c unsigned int reg; reg 242 drivers/iio/accel/mma7455_core.c ret = regmap_read(regmap, MMA7455_REG_WHOAMI, ®); reg 248 drivers/iio/accel/mma7455_core.c if (reg != MMA7455_WHOAMI_ID) { reg 41 drivers/iio/accel/mma7660.c #define MMA7660_CHANNEL(reg, axis) { \ reg 43 drivers/iio/accel/mma7660.c .address = reg, \ reg 355 drivers/iio/accel/mma8452.c int reg; reg 357 drivers/iio/accel/mma8452.c reg = i2c_smbus_read_byte_data(data->client, reg 359 drivers/iio/accel/mma8452.c if (reg < 0) reg 360 drivers/iio/accel/mma8452.c return reg; reg 362 drivers/iio/accel/mma8452.c return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >> reg 582 drivers/iio/accel/mma8452.c int reg; reg 584 drivers/iio/accel/mma8452.c reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1); reg 585 drivers/iio/accel/mma8452.c if (reg < 0) reg 586 drivers/iio/accel/mma8452.c return reg; reg 588 drivers/iio/accel/mma8452.c return reg & MMA8452_CTRL_ACTIVE; reg 591 drivers/iio/accel/mma8452.c static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val) reg 611 drivers/iio/accel/mma8452.c ret = i2c_smbus_write_byte_data(data->client, reg, val); reg 630 drivers/iio/accel/mma8452.c int reg; reg 632 drivers/iio/accel/mma8452.c reg = i2c_smbus_read_byte_data(data->client, reg 634 drivers/iio/accel/mma8452.c if (reg < 0) reg 635 drivers/iio/accel/mma8452.c return reg; reg 637 drivers/iio/accel/mma8452.c reg &= ~MMA8452_CTRL_REG2_MODS_MASK; reg 638 drivers/iio/accel/mma8452.c reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT; reg 640 drivers/iio/accel/mma8452.c return mma8452_change_config(data, MMA8452_CTRL_REG2, reg); reg 685 drivers/iio/accel/mma8452.c int i, reg; reg 691 drivers/iio/accel/mma8452.c reg = i2c_smbus_read_byte_data(data->client, reg 693 drivers/iio/accel/mma8452.c if (reg < 0) reg 694 drivers/iio/accel/mma8452.c return reg; reg 696 drivers/iio/accel/mma8452.c reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK; reg 697 drivers/iio/accel/mma8452.c reg |= i; reg 699 drivers/iio/accel/mma8452.c return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg); reg 886 drivers/iio/accel/mma8452.c int ret, reg, steps; reg 915 drivers/iio/accel/mma8452.c reg = i2c_smbus_read_byte_data(data->client, reg 917 drivers/iio/accel/mma8452.c if (reg < 0) reg 918 drivers/iio/accel/mma8452.c return reg; reg 921 drivers/iio/accel/mma8452.c reg |= MMA8452_TRANSIENT_CFG_HPF_BYP; reg 923 drivers/iio/accel/mma8452.c reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP; reg 929 drivers/iio/accel/mma8452.c return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg); reg 1111 drivers/iio/accel/mma8452.c unsigned int reg, unsigned int writeval, reg 1117 drivers/iio/accel/mma8452.c if (reg > MMA8452_MAX_REG) reg 1121 drivers/iio/accel/mma8452.c return mma8452_change_config(data, reg, writeval); reg 1123 drivers/iio/accel/mma8452.c ret = i2c_smbus_read_byte_data(data->client, reg); reg 1428 drivers/iio/accel/mma8452.c int reg, ret; reg 1434 drivers/iio/accel/mma8452.c reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4); reg 1435 drivers/iio/accel/mma8452.c if (reg < 0) reg 1436 drivers/iio/accel/mma8452.c return reg; reg 1439 drivers/iio/accel/mma8452.c reg |= MMA8452_INT_DRDY; reg 1441 drivers/iio/accel/mma8452.c reg &= ~MMA8452_INT_DRDY; reg 1443 drivers/iio/accel/mma8452.c return mma8452_change_config(data, MMA8452_CTRL_REG4, reg); reg 339 drivers/iio/accel/mma9551.c u16 reg; reg 359 drivers/iio/accel/mma9551.c reg = MMA9551_TILT_YZ_ANG_REG; reg 362 drivers/iio/accel/mma9551.c reg = MMA9551_TILT_XZ_ANG_REG; reg 365 drivers/iio/accel/mma9551.c reg = MMA9551_TILT_XY_ANG_REG; reg 374 drivers/iio/accel/mma9551.c reg, &val); reg 217 drivers/iio/accel/mma9551_core.c u16 reg, u8 *val) reg 220 drivers/iio/accel/mma9551_core.c reg, NULL, 0, val, 1); reg 242 drivers/iio/accel/mma9551_core.c u16 reg, u8 val) reg 244 drivers/iio/accel/mma9551_core.c return mma9551_transfer(client, app_id, MMA9551_CMD_WRITE_CONFIG, reg, reg 267 drivers/iio/accel/mma9551_core.c u16 reg, u8 *val) reg 270 drivers/iio/accel/mma9551_core.c reg, NULL, 0, val, 1); reg 292 drivers/iio/accel/mma9551_core.c u16 reg, u16 *val) reg 298 drivers/iio/accel/mma9551_core.c reg, NULL, 0, (u8 *)&v, 2); reg 323 drivers/iio/accel/mma9551_core.c u16 reg, u16 val) reg 327 drivers/iio/accel/mma9551_core.c return mma9551_transfer(client, app_id, MMA9551_CMD_WRITE_CONFIG, reg, reg 350 drivers/iio/accel/mma9551_core.c u16 reg, u16 *val) reg 356 drivers/iio/accel/mma9551_core.c reg, NULL, 0, (u8 *)&v, 2); reg 380 drivers/iio/accel/mma9551_core.c u16 reg, u8 len, u16 *buf) reg 391 drivers/iio/accel/mma9551_core.c reg, NULL, 0, (u8 *)be_buf, len * sizeof(u16)); reg 419 drivers/iio/accel/mma9551_core.c u16 reg, u8 len, u16 *buf) reg 430 drivers/iio/accel/mma9551_core.c reg, NULL, 0, (u8 *)be_buf, len * sizeof(u16)); reg 458 drivers/iio/accel/mma9551_core.c u16 reg, u8 len, u16 *buf) reg 472 drivers/iio/accel/mma9551_core.c reg, (u8 *)be_buf, len * sizeof(u16), NULL, 0); reg 493 drivers/iio/accel/mma9551_core.c u16 reg, u8 mask, u8 val) reg 498 drivers/iio/accel/mma9551_core.c ret = mma9551_read_config_byte(client, app_id, reg, &orig); reg 508 drivers/iio/accel/mma9551_core.c return mma9551_write_config_byte(client, app_id, reg, tmp); reg 534 drivers/iio/accel/mma9551_core.c u8 reg, pol_mask, pol_val; reg 546 drivers/iio/accel/mma9551_core.c reg = pin * 2; reg 549 drivers/iio/accel/mma9551_core.c reg, app_id); reg 556 drivers/iio/accel/mma9551_core.c reg + 1, bitnum); reg 564 drivers/iio/accel/mma9551_core.c reg = MMA9551_GPIO_POL_LSB; reg 568 drivers/iio/accel/mma9551_core.c reg = MMA9551_GPIO_POL_LSB; reg 572 drivers/iio/accel/mma9551_core.c reg = MMA9551_GPIO_POL_MSB; reg 576 drivers/iio/accel/mma9551_core.c reg = MMA9551_GPIO_POL_MSB; reg 582 drivers/iio/accel/mma9551_core.c ret = mma9551_update_config_bits(client, MMA9551_APPID_GPIO, reg, reg 42 drivers/iio/accel/mma9551_core.h u16 reg, u8 *val); reg 44 drivers/iio/accel/mma9551_core.h u16 reg, u8 val); reg 46 drivers/iio/accel/mma9551_core.h u16 reg, u8 *val); reg 48 drivers/iio/accel/mma9551_core.h u16 reg, u16 *val); reg 50 drivers/iio/accel/mma9551_core.h u16 reg, u16 val); reg 52 drivers/iio/accel/mma9551_core.h u16 reg, u16 *val); reg 54 drivers/iio/accel/mma9551_core.h u16 reg, u8 len, u16 *buf); reg 56 drivers/iio/accel/mma9551_core.h u16 reg, u8 len, u16 *buf); reg 58 drivers/iio/accel/mma9551_core.h u16 reg, u8 len, u16 *buf); reg 60 drivers/iio/accel/mma9551_core.h u16 reg, u8 mask, u8 val); reg 263 drivers/iio/accel/mma9553.c static int mma9553_set_config(struct mma9553_data *data, u16 reg, reg 275 drivers/iio/accel/mma9553.c reg, reg_val); reg 278 drivers/iio/accel/mma9553.c "error writing config register 0x%x\n", reg); reg 436 drivers/iio/accel/mma9553.c static int mma9553_read_status_word(struct mma9553_data *data, u16 reg, reg 457 drivers/iio/accel/mma9553.c reg, tmp); reg 92 drivers/iio/accel/mxc4005.c static bool mxc4005_is_readable_reg(struct device *dev, unsigned int reg) reg 94 drivers/iio/accel/mxc4005.c switch (reg) { reg 109 drivers/iio/accel/mxc4005.c static bool mxc4005_is_writeable_reg(struct device *dev, unsigned int reg) reg 111 drivers/iio/accel/mxc4005.c switch (reg) { reg 150 drivers/iio/accel/mxc4005.c __be16 reg; reg 153 drivers/iio/accel/mxc4005.c ret = regmap_bulk_read(data->regmap, addr, (u8 *) ®, sizeof(reg)); reg 159 drivers/iio/accel/mxc4005.c return be16_to_cpu(reg); reg 164 drivers/iio/accel/mxc4005.c unsigned int reg; reg 168 drivers/iio/accel/mxc4005.c ret = regmap_read(data->regmap, MXC4005_REG_CONTROL, ®); reg 174 drivers/iio/accel/mxc4005.c i = reg >> MXC4005_CONTROL_FSR_SHIFT; reg 184 drivers/iio/accel/mxc4005.c unsigned int reg; reg 190 drivers/iio/accel/mxc4005.c reg = i << MXC4005_CONTROL_FSR_SHIFT; reg 194 drivers/iio/accel/mxc4005.c reg); reg 375 drivers/iio/accel/mxc4005.c unsigned int reg; reg 377 drivers/iio/accel/mxc4005.c ret = regmap_read(data->regmap, MXC4005_REG_DEVICE_ID, ®); reg 383 drivers/iio/accel/mxc4005.c dev_dbg(data->dev, "MXC4005 chip id %02x\n", reg); reg 54 drivers/iio/accel/mxc6255.c unsigned int reg; reg 59 drivers/iio/accel/mxc6255.c ret = regmap_read(data->regmap, chan->address, ®); reg 66 drivers/iio/accel/mxc6255.c *val = sign_extend32(reg, 7); reg 81 drivers/iio/accel/mxc6255.c #define MXC6255_CHANNEL(_axis, reg) { \ reg 85 drivers/iio/accel/mxc6255.c .address = reg, \ reg 95 drivers/iio/accel/mxc6255.c static bool mxc6255_is_readable_reg(struct device *dev, unsigned int reg) reg 97 drivers/iio/accel/mxc6255.c switch (reg) { reg 74 drivers/iio/accel/stk8312.c #define STK8312_ACCEL_CHANNEL(index, reg, axis) { \ reg 76 drivers/iio/accel/stk8312.c .address = reg, \ reg 102 drivers/iio/accel/stk8ba50.c #define STK8BA50_ACCEL_CHANNEL(index, reg, axis) { \ reg 104 drivers/iio/accel/stk8ba50.c .address = reg, \ reg 141 drivers/iio/accel/stk8ba50.c static int stk8ba50_read_accel(struct stk8ba50_data *data, u8 reg) reg 146 drivers/iio/accel/stk8ba50.c ret = i2c_smbus_read_word_data(client, reg); reg 28 drivers/iio/adc/ad7266.c struct regulator *reg; reg 396 drivers/iio/adc/ad7266.c st->reg = devm_regulator_get_optional(&spi->dev, "vref"); reg 397 drivers/iio/adc/ad7266.c if (!IS_ERR(st->reg)) { reg 398 drivers/iio/adc/ad7266.c ret = regulator_enable(st->reg); reg 402 drivers/iio/adc/ad7266.c ret = regulator_get_voltage(st->reg); reg 409 drivers/iio/adc/ad7266.c if (PTR_ERR(st->reg) != -ENODEV) reg 410 drivers/iio/adc/ad7266.c return PTR_ERR(st->reg); reg 482 drivers/iio/adc/ad7266.c if (!IS_ERR(st->reg)) reg 483 drivers/iio/adc/ad7266.c regulator_disable(st->reg); reg 497 drivers/iio/adc/ad7266.c if (!IS_ERR(st->reg)) reg 498 drivers/iio/adc/ad7266.c regulator_disable(st->reg); reg 83 drivers/iio/adc/ad7291.c struct regulator *reg; reg 89 drivers/iio/adc/ad7291.c static int ad7291_i2c_read(struct ad7291_chip_info *chip, u8 reg, u16 *data) reg 94 drivers/iio/adc/ad7291.c ret = i2c_smbus_read_word_swapped(client, reg); reg 105 drivers/iio/adc/ad7291.c static int ad7291_i2c_write(struct ad7291_chip_info *chip, u8 reg, u16 data) reg 107 drivers/iio/adc/ad7291.c return i2c_smbus_write_word_swapped(chip->client, reg, data); reg 379 drivers/iio/adc/ad7291.c if (chip->reg) { reg 382 drivers/iio/adc/ad7291.c vref = regulator_get_voltage(chip->reg); reg 479 drivers/iio/adc/ad7291.c chip->reg = devm_regulator_get(&client->dev, "vref"); reg 480 drivers/iio/adc/ad7291.c if (IS_ERR(chip->reg)) reg 481 drivers/iio/adc/ad7291.c return PTR_ERR(chip->reg); reg 483 drivers/iio/adc/ad7291.c ret = regulator_enable(chip->reg); reg 543 drivers/iio/adc/ad7291.c if (chip->reg) reg 544 drivers/iio/adc/ad7291.c regulator_disable(chip->reg); reg 559 drivers/iio/adc/ad7291.c if (chip->reg) reg 560 drivers/iio/adc/ad7291.c regulator_disable(chip->reg); reg 43 drivers/iio/adc/ad7298.c struct regulator *reg; reg 220 drivers/iio/adc/ad7298.c vref = regulator_get_voltage(st->reg); reg 301 drivers/iio/adc/ad7298.c st->reg = devm_regulator_get(&spi->dev, "vref"); reg 302 drivers/iio/adc/ad7298.c if (IS_ERR(st->reg)) reg 303 drivers/iio/adc/ad7298.c return PTR_ERR(st->reg); reg 305 drivers/iio/adc/ad7298.c ret = regulator_enable(st->reg); reg 353 drivers/iio/adc/ad7298.c regulator_disable(st->reg); reg 366 drivers/iio/adc/ad7298.c regulator_disable(st->reg); reg 36 drivers/iio/adc/ad7476.c struct regulator *reg; reg 128 drivers/iio/adc/ad7476.c scale_uv = regulator_get_voltage(st->reg); reg 249 drivers/iio/adc/ad7476.c st->reg = devm_regulator_get(&spi->dev, "vcc"); reg 250 drivers/iio/adc/ad7476.c if (IS_ERR(st->reg)) reg 251 drivers/iio/adc/ad7476.c return PTR_ERR(st->reg); reg 253 drivers/iio/adc/ad7476.c ret = regulator_enable(st->reg); reg 293 drivers/iio/adc/ad7476.c regulator_disable(st->reg); reg 305 drivers/iio/adc/ad7476.c regulator_disable(st->reg); reg 64 drivers/iio/adc/ad7606.c unsigned int reg, reg 73 drivers/iio/adc/ad7606.c ret = st->bops->reg_read(st, reg); reg 79 drivers/iio/adc/ad7606.c ret = st->bops->reg_write(st, reg, writeval); reg 564 drivers/iio/adc/ad7606.c regulator_disable(st->reg); reg 592 drivers/iio/adc/ad7606.c st->reg = devm_regulator_get(dev, "avcc"); reg 593 drivers/iio/adc/ad7606.c if (IS_ERR(st->reg)) reg 594 drivers/iio/adc/ad7606.c return PTR_ERR(st->reg); reg 596 drivers/iio/adc/ad7606.c ret = regulator_enable(st->reg); reg 95 drivers/iio/adc/ad7606.h struct regulator *reg; reg 40 drivers/iio/adc/ad7766.c struct regulator_bulk_data reg[AD7766_NUM_SUPPLIES]; reg 91 drivers/iio/adc/ad7766.c ret = regulator_bulk_enable(ARRAY_SIZE(ad7766->reg), ad7766->reg); reg 101 drivers/iio/adc/ad7766.c regulator_bulk_disable(ARRAY_SIZE(ad7766->reg), ad7766->reg); reg 123 drivers/iio/adc/ad7766.c regulator_bulk_disable(ARRAY_SIZE(ad7766->reg), ad7766->reg); reg 132 drivers/iio/adc/ad7766.c struct regulator *vref = ad7766->reg[AD7766_SUPPLY_VREF].consumer; reg 231 drivers/iio/adc/ad7766.c ad7766->reg[AD7766_SUPPLY_AVDD].supply = "avdd"; reg 232 drivers/iio/adc/ad7766.c ad7766->reg[AD7766_SUPPLY_DVDD].supply = "dvdd"; reg 233 drivers/iio/adc/ad7766.c ad7766->reg[AD7766_SUPPLY_VREF].supply = "vref"; reg 235 drivers/iio/adc/ad7766.c ret = devm_regulator_bulk_get(&spi->dev, ARRAY_SIZE(ad7766->reg), reg 236 drivers/iio/adc/ad7766.c ad7766->reg); reg 247 drivers/iio/adc/ad7768-1.c unsigned int reg, reg 256 drivers/iio/adc/ad7768-1.c ret = ad7768_spi_reg_read(st, reg, 1); reg 262 drivers/iio/adc/ad7768-1.c ret = ad7768_spi_reg_write(st, reg, writeval); reg 61 drivers/iio/adc/ad7780.c struct regulator *reg; reg 118 drivers/iio/adc/ad7780.c voltage_uv = regulator_get_voltage(st->reg); reg 314 drivers/iio/adc/ad7780.c st->reg = devm_regulator_get(&spi->dev, "avdd"); reg 315 drivers/iio/adc/ad7780.c if (IS_ERR(st->reg)) reg 316 drivers/iio/adc/ad7780.c return PTR_ERR(st->reg); reg 318 drivers/iio/adc/ad7780.c ret = regulator_enable(st->reg); reg 337 drivers/iio/adc/ad7780.c regulator_disable(st->reg); reg 350 drivers/iio/adc/ad7780.c regulator_disable(st->reg); reg 151 drivers/iio/adc/ad7791.c struct regulator *reg; reg 241 drivers/iio/adc/ad7791.c voltage_uv = regulator_get_voltage(st->reg); reg 366 drivers/iio/adc/ad7791.c st->reg = devm_regulator_get(&spi->dev, "refin"); reg 367 drivers/iio/adc/ad7791.c if (IS_ERR(st->reg)) reg 368 drivers/iio/adc/ad7791.c return PTR_ERR(st->reg); reg 370 drivers/iio/adc/ad7791.c ret = regulator_enable(st->reg); reg 407 drivers/iio/adc/ad7791.c regulator_disable(st->reg); reg 420 drivers/iio/adc/ad7791.c regulator_disable(st->reg); reg 155 drivers/iio/adc/ad7793.c struct regulator *reg; reg 730 drivers/iio/adc/ad7793.c st->reg = devm_regulator_get(&spi->dev, "refin"); reg 731 drivers/iio/adc/ad7793.c if (IS_ERR(st->reg)) reg 732 drivers/iio/adc/ad7793.c return PTR_ERR(st->reg); reg 734 drivers/iio/adc/ad7793.c ret = regulator_enable(st->reg); reg 738 drivers/iio/adc/ad7793.c vref_mv = regulator_get_voltage(st->reg); reg 780 drivers/iio/adc/ad7793.c regulator_disable(st->reg); reg 795 drivers/iio/adc/ad7793.c regulator_disable(st->reg); reg 56 drivers/iio/adc/ad7887.c struct regulator *reg; reg 170 drivers/iio/adc/ad7887.c if (st->reg) { reg 171 drivers/iio/adc/ad7887.c *val = regulator_get_voltage(st->reg); reg 248 drivers/iio/adc/ad7887.c st->reg = devm_regulator_get(&spi->dev, "vref"); reg 249 drivers/iio/adc/ad7887.c if (IS_ERR(st->reg)) reg 250 drivers/iio/adc/ad7887.c return PTR_ERR(st->reg); reg 252 drivers/iio/adc/ad7887.c ret = regulator_enable(st->reg); reg 329 drivers/iio/adc/ad7887.c if (st->reg) reg 330 drivers/iio/adc/ad7887.c regulator_disable(st->reg); reg 342 drivers/iio/adc/ad7887.c if (st->reg) reg 343 drivers/iio/adc/ad7887.c regulator_disable(st->reg); reg 60 drivers/iio/adc/ad7923.c struct regulator *reg; reg 212 drivers/iio/adc/ad7923.c vref = regulator_get_voltage(st->reg); reg 307 drivers/iio/adc/ad7923.c st->reg = devm_regulator_get(&spi->dev, "refin"); reg 308 drivers/iio/adc/ad7923.c if (IS_ERR(st->reg)) reg 309 drivers/iio/adc/ad7923.c return PTR_ERR(st->reg); reg 311 drivers/iio/adc/ad7923.c ret = regulator_enable(st->reg); reg 329 drivers/iio/adc/ad7923.c regulator_disable(st->reg); reg 341 drivers/iio/adc/ad7923.c regulator_disable(st->reg); reg 193 drivers/iio/adc/ad7949.c unsigned int reg, unsigned int writeval, reg 126 drivers/iio/adc/ad799x.c struct regulator *reg; reg 785 drivers/iio/adc/ad799x.c st->reg = devm_regulator_get(&client->dev, "vcc"); reg 786 drivers/iio/adc/ad799x.c if (IS_ERR(st->reg)) reg 787 drivers/iio/adc/ad799x.c return PTR_ERR(st->reg); reg 788 drivers/iio/adc/ad799x.c ret = regulator_enable(st->reg); reg 847 drivers/iio/adc/ad799x.c regulator_disable(st->reg); reg 861 drivers/iio/adc/ad799x.c regulator_disable(st->reg); reg 57 drivers/iio/adc/ad_sigma_delta.c int ad_sd_write_reg(struct ad_sigma_delta *sigma_delta, unsigned int reg, reg 69 drivers/iio/adc/ad_sigma_delta.c data[0] = (reg << sigma_delta->info->addr_shift) | sigma_delta->comm; reg 102 drivers/iio/adc/ad_sigma_delta.c unsigned int reg, unsigned int size, uint8_t *val) reg 121 drivers/iio/adc/ad_sigma_delta.c data[0] = reg << sigma_delta->info->addr_shift; reg 147 drivers/iio/adc/ad_sigma_delta.c unsigned int reg, unsigned int size, unsigned int *val) reg 151 drivers/iio/adc/ad_sigma_delta.c ret = ad_sd_read_reg_raw(sigma_delta, reg, size, sigma_delta->data); reg 152 drivers/iio/adc/aspeed_adc.c unsigned int reg, unsigned int writeval, reg 157 drivers/iio/adc/aspeed_adc.c if (!readval || reg % 4 || reg > ASPEED_REG_MAX) reg 160 drivers/iio/adc/aspeed_adc.c *readval = readl(data->base + reg); reg 330 drivers/iio/adc/at91-sama5d2_adc.c #define at91_adc_readl(st, reg) readl_relaxed(st->base + reg) reg 331 drivers/iio/adc/at91-sama5d2_adc.c #define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg) reg 388 drivers/iio/adc/at91-sama5d2_adc.c struct regulator *reg; reg 614 drivers/iio/adc/at91-sama5d2_adc.c static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg) reg 625 drivers/iio/adc/at91-sama5d2_adc.c val = at91_adc_readl(st, reg); reg 1754 drivers/iio/adc/at91-sama5d2_adc.c st->reg = devm_regulator_get(&pdev->dev, "vddana"); reg 1755 drivers/iio/adc/at91-sama5d2_adc.c if (IS_ERR(st->reg)) reg 1756 drivers/iio/adc/at91-sama5d2_adc.c return PTR_ERR(st->reg); reg 1767 drivers/iio/adc/at91-sama5d2_adc.c ret = regulator_enable(st->reg); reg 1834 drivers/iio/adc/at91-sama5d2_adc.c regulator_disable(st->reg); reg 1850 drivers/iio/adc/at91-sama5d2_adc.c regulator_disable(st->reg); reg 1870 drivers/iio/adc/at91-sama5d2_adc.c regulator_disable(st->reg); reg 1885 drivers/iio/adc/at91-sama5d2_adc.c ret = regulator_enable(st->reg); reg 1919 drivers/iio/adc/at91-sama5d2_adc.c regulator_disable(st->reg); reg 140 drivers/iio/adc/at91_adc.c #define at91_adc_readl(st, reg) \ reg 141 drivers/iio/adc/at91_adc.c (readl_relaxed(st->reg_base + reg)) reg 142 drivers/iio/adc/at91_adc.c #define at91_adc_writel(st, reg, val) \ reg 143 drivers/iio/adc/at91_adc.c (writel_relaxed(val, st->reg_base + reg)) reg 292 drivers/iio/adc/at91_adc.c unsigned int xscale, yscale, reg, z1, z2; reg 303 drivers/iio/adc/at91_adc.c reg = at91_adc_readl(st, AT91_ADC_TSXPOSR); reg 304 drivers/iio/adc/at91_adc.c xpos = reg & xyz_mask; reg 306 drivers/iio/adc/at91_adc.c xscale = (reg >> 16) & xyz_mask; reg 314 drivers/iio/adc/at91_adc.c reg = at91_adc_readl(st, AT91_ADC_TSYPOSR); reg 315 drivers/iio/adc/at91_adc.c ypos = reg & xyz_mask; reg 317 drivers/iio/adc/at91_adc.c yscale = (reg >> 16) & xyz_mask; reg 325 drivers/iio/adc/at91_adc.c reg = at91_adc_readl(st, AT91_ADC_TSPRESSR); reg 326 drivers/iio/adc/at91_adc.c z1 = reg & xyz_mask; reg 327 drivers/iio/adc/at91_adc.c z2 = (reg >> 16) & xyz_mask; reg 358 drivers/iio/adc/at91_adc.c unsigned int reg; reg 366 drivers/iio/adc/at91_adc.c reg = at91_adc_readl(st, AT91_ADC_MR); reg 367 drivers/iio/adc/at91_adc.c reg &= ~AT91_ADC_PENDBC; reg 368 drivers/iio/adc/at91_adc.c at91_adc_writel(st, AT91_ADC_MR, reg); reg 378 drivers/iio/adc/at91_adc.c reg = at91_adc_readl(st, AT91_ADC_MR); reg 379 drivers/iio/adc/at91_adc.c reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC; reg 380 drivers/iio/adc/at91_adc.c at91_adc_writel(st, AT91_ADC_MR, reg); reg 553 drivers/iio/adc/at91_adc.c struct at91_adc_reg_desc *reg = st->registers; reg 554 drivers/iio/adc/at91_adc.c u32 status = at91_adc_readl(st, reg->trigger_register); reg 569 drivers/iio/adc/at91_adc.c at91_adc_writel(st, reg->trigger_register, reg 579 drivers/iio/adc/at91_adc.c at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask); reg 582 drivers/iio/adc/at91_adc.c at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask); reg 584 drivers/iio/adc/at91_adc.c at91_adc_writel(st, reg->trigger_register, reg 1016 drivers/iio/adc/at91_adc.c u32 reg = 0; reg 1035 drivers/iio/adc/at91_adc.c reg = at91_adc_readl(st, AT91_ADC_MR); reg 1036 drivers/iio/adc/at91_adc.c reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET; reg 1038 drivers/iio/adc/at91_adc.c reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC; reg 1039 drivers/iio/adc/at91_adc.c at91_adc_writel(st, AT91_ADC_MR, reg); reg 1041 drivers/iio/adc/at91_adc.c reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM; reg 1042 drivers/iio/adc/at91_adc.c at91_adc_writel(st, AT91_ADC_TSR, reg); reg 1059 drivers/iio/adc/at91_adc.c reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS; reg 1061 drivers/iio/adc/at91_adc.c reg = AT91_ADC_TSMR_TSMODE_5WIRE; reg 1063 drivers/iio/adc/at91_adc.c reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM; reg 1064 drivers/iio/adc/at91_adc.c reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average) reg 1066 drivers/iio/adc/at91_adc.c reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC; reg 1067 drivers/iio/adc/at91_adc.c reg |= AT91_ADC_TSMR_NOTSDMA; reg 1068 drivers/iio/adc/at91_adc.c reg |= AT91_ADC_TSMR_PENDET_ENA; reg 1069 drivers/iio/adc/at91_adc.c reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */ reg 1071 drivers/iio/adc/at91_adc.c at91_adc_writel(st, AT91_ADC_TSMR, reg); reg 1156 drivers/iio/adc/at91_adc.c u32 reg; reg 1269 drivers/iio/adc/at91_adc.c reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask; reg 1270 drivers/iio/adc/at91_adc.c reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask; reg 1272 drivers/iio/adc/at91_adc.c reg |= AT91_ADC_LOWRES; reg 1274 drivers/iio/adc/at91_adc.c reg |= AT91_ADC_SLEEP; reg 1275 drivers/iio/adc/at91_adc.c reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM; reg 1276 drivers/iio/adc/at91_adc.c at91_adc_writel(st, AT91_ADC_MR, reg); reg 530 drivers/iio/adc/axp20x_adc.c unsigned int reg, regval; reg 546 drivers/iio/adc/axp20x_adc.c reg = AXP20X_GPIO10_IN_RANGE_GPIO0; reg 551 drivers/iio/adc/axp20x_adc.c reg = AXP20X_GPIO10_IN_RANGE_GPIO1; reg 559 drivers/iio/adc/axp20x_adc.c return regmap_update_bits(info->regmap, AXP20X_GPIO10_IN_RANGE, reg, reg 101 drivers/iio/adc/bcm_iproc_adc.c #define iproc_adc_dbg_reg(dev, priv, reg) \ reg 104 drivers/iio/adc/bcm_iproc_adc.c regmap_read(priv->regmap, reg, &val); \ reg 105 drivers/iio/adc/bcm_iproc_adc.c dev_dbg(dev, "%20s= 0x%08x\n", #reg, val); \ reg 58 drivers/iio/adc/cc10001_adc.c struct regulator *reg; reg 68 drivers/iio/adc/cc10001_adc.c u32 reg, u32 val) reg 70 drivers/iio/adc/cc10001_adc.c writel(val, adc_dev->reg_base + reg); reg 74 drivers/iio/adc/cc10001_adc.c u32 reg) reg 76 drivers/iio/adc/cc10001_adc.c return readl(adc_dev->reg_base + reg); reg 234 drivers/iio/adc/cc10001_adc.c ret = regulator_get_voltage(adc_dev->reg); reg 330 drivers/iio/adc/cc10001_adc.c adc_dev->reg = devm_regulator_get(&pdev->dev, "vref"); reg 331 drivers/iio/adc/cc10001_adc.c if (IS_ERR(adc_dev->reg)) reg 332 drivers/iio/adc/cc10001_adc.c return PTR_ERR(adc_dev->reg); reg 334 drivers/iio/adc/cc10001_adc.c ret = regulator_enable(adc_dev->reg); reg 406 drivers/iio/adc/cc10001_adc.c regulator_disable(adc_dev->reg); reg 419 drivers/iio/adc/cc10001_adc.c regulator_disable(adc_dev->reg); reg 114 drivers/iio/adc/cpcap-adc.c struct regmap *reg; reg 388 drivers/iio/adc/cpcap-adc.c error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, reg 416 drivers/iio/adc/cpcap-adc.c error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1, reg 427 drivers/iio/adc/cpcap-adc.c error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, reg 435 drivers/iio/adc/cpcap-adc.c error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, reg 441 drivers/iio/adc/cpcap-adc.c error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, reg 449 drivers/iio/adc/cpcap-adc.c error = regmap_read(ddata->reg, CPCAP_REG_ADCC2, &value); reg 458 drivers/iio/adc/cpcap-adc.c error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1, reg 479 drivers/iio/adc/cpcap-adc.c error = regmap_read(ddata->reg, calibration_register, reg 484 drivers/iio/adc/cpcap-adc.c error = regmap_read(ddata->reg, calibration_register, reg 548 drivers/iio/adc/cpcap-adc.c error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, reg 583 drivers/iio/adc/cpcap-adc.c error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1, reg 594 drivers/iio/adc/cpcap-adc.c error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, reg 604 drivers/iio/adc/cpcap-adc.c error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, reg 610 drivers/iio/adc/cpcap-adc.c error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, reg 616 drivers/iio/adc/cpcap-adc.c error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, reg 622 drivers/iio/adc/cpcap-adc.c error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, reg 661 drivers/iio/adc/cpcap-adc.c error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1, reg 667 drivers/iio/adc/cpcap-adc.c return regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, reg 792 drivers/iio/adc/cpcap-adc.c error = regmap_read(ddata->reg, CPCAP_REG_ADCAL1, reg 799 drivers/iio/adc/cpcap-adc.c error = regmap_read(ddata->reg, CPCAP_REG_ADCAL2, reg 809 drivers/iio/adc/cpcap-adc.c error = regmap_read(ddata->reg, addr, &req->result); reg 852 drivers/iio/adc/cpcap-adc.c error = regmap_read(ddata->reg, addr, val); reg 881 drivers/iio/adc/cpcap-adc.c error = regmap_read(ddata->reg, chan->address, val); reg 995 drivers/iio/adc/cpcap-adc.c ddata->reg = dev_get_regmap(pdev->dev.parent, NULL); reg 996 drivers/iio/adc/cpcap-adc.c if (!ddata->reg) reg 999 drivers/iio/adc/cpcap-adc.c error = cpcap_get_vendor(ddata->dev, ddata->reg, &ddata->vendor); reg 662 drivers/iio/adc/exynos_adc.c unsigned reg, unsigned writeval, reg 670 drivers/iio/adc/exynos_adc.c *readval = readl(info->regs + reg); reg 202 drivers/iio/adc/fsl-imx25-gcq.c u32 reg; reg 206 drivers/iio/adc/fsl-imx25-gcq.c ret = of_property_read_u32(child, "reg", ®); reg 213 drivers/iio/adc/fsl-imx25-gcq.c if (reg >= MX25_NUM_CFGS) { reg 233 drivers/iio/adc/fsl-imx25-gcq.c priv->channel_vref_mv[reg] = reg 236 drivers/iio/adc/fsl-imx25-gcq.c priv->channel_vref_mv[reg] /= 1000; reg 239 drivers/iio/adc/fsl-imx25-gcq.c priv->channel_vref_mv[reg] = 2500; reg 267 drivers/iio/adc/fsl-imx25-gcq.c regmap_update_bits(priv->regs, MX25_ADCQ_CFG(reg), reg 57 drivers/iio/adc/hi8435.c static int hi8435_readb(struct hi8435_priv *priv, u8 reg, u8 *val) reg 59 drivers/iio/adc/hi8435.c reg |= HI8435_READ_OPCODE; reg 60 drivers/iio/adc/hi8435.c return spi_write_then_read(priv->spi, ®, 1, val, 1); reg 63 drivers/iio/adc/hi8435.c static int hi8435_readw(struct hi8435_priv *priv, u8 reg, u16 *val) reg 68 drivers/iio/adc/hi8435.c reg |= HI8435_READ_OPCODE; reg 69 drivers/iio/adc/hi8435.c ret = spi_write_then_read(priv->spi, ®, 1, &be_val, 2); reg 75 drivers/iio/adc/hi8435.c static int hi8435_readl(struct hi8435_priv *priv, u8 reg, u32 *val) reg 80 drivers/iio/adc/hi8435.c reg |= HI8435_READ_OPCODE; reg 81 drivers/iio/adc/hi8435.c ret = spi_write_then_read(priv->spi, ®, 1, &be_val, 4); reg 87 drivers/iio/adc/hi8435.c static int hi8435_writeb(struct hi8435_priv *priv, u8 reg, u8 val) reg 89 drivers/iio/adc/hi8435.c priv->reg_buffer[0] = reg | HI8435_WRITE_OPCODE; reg 95 drivers/iio/adc/hi8435.c static int hi8435_writew(struct hi8435_priv *priv, u8 reg, u16 val) reg 97 drivers/iio/adc/hi8435.c priv->reg_buffer[0] = reg | HI8435_WRITE_OPCODE; reg 169 drivers/iio/adc/hi8435.c u16 reg; reg 179 drivers/iio/adc/hi8435.c HI8435_GOCENHYS_REG, ®); reg 184 drivers/iio/adc/hi8435.c *val = ((reg & 0xff) - (reg >> 8)) / 2; reg 186 drivers/iio/adc/hi8435.c *val = ((reg & 0xff) + (reg >> 8)) / 2; reg 201 drivers/iio/adc/hi8435.c u16 reg; reg 211 drivers/iio/adc/hi8435.c HI8435_GOCENHYS_REG, ®); reg 247 drivers/iio/adc/hi8435.c HI8435_GOCENHYS_REG, ®); reg 254 drivers/iio/adc/hi8435.c reg = priv->threshold_hi[mode] - priv->threshold_lo[mode]; reg 255 drivers/iio/adc/hi8435.c reg <<= 8; reg 257 drivers/iio/adc/hi8435.c reg |= (priv->threshold_hi[mode] + priv->threshold_lo[mode]); reg 260 drivers/iio/adc/hi8435.c HI8435_GOCENHYS_REG, reg); reg 268 drivers/iio/adc/hi8435.c unsigned reg, unsigned writeval, reg 276 drivers/iio/adc/hi8435.c ret = hi8435_readb(priv, reg, &val); reg 280 drivers/iio/adc/hi8435.c ret = hi8435_writeb(priv, reg, val); reg 307 drivers/iio/adc/hi8435.c u8 reg; reg 309 drivers/iio/adc/hi8435.c ret = hi8435_readb(priv, HI8435_PSEN_REG, ®); reg 313 drivers/iio/adc/hi8435.c return !!(reg & BIT(chan->channel / 8)); reg 322 drivers/iio/adc/hi8435.c u8 reg; reg 326 drivers/iio/adc/hi8435.c ret = hi8435_readb(priv, HI8435_PSEN_REG, ®); reg 332 drivers/iio/adc/hi8435.c reg &= ~BIT(chan->channel / 8); reg 334 drivers/iio/adc/hi8435.c reg |= BIT(chan->channel / 8); reg 336 drivers/iio/adc/hi8435.c ret = hi8435_writeb(priv, HI8435_PSEN_REG, reg); reg 393 drivers/iio/adc/imx7d_adc.c unsigned reg, unsigned writeval, reg 398 drivers/iio/adc/imx7d_adc.c if (!readval || reg % 4 || reg > IMX7D_REG_ADC_ADC_CFG) reg 401 drivers/iio/adc/imx7d_adc.c *readval = readl(info->regs + reg); reg 101 drivers/iio/adc/ina2xx-adc.c static bool ina2xx_is_writeable_reg(struct device *dev, unsigned int reg) reg 103 drivers/iio/adc/ina2xx-adc.c return (reg == INA2XX_CONFIG) || (reg > INA2XX_CURRENT); reg 106 drivers/iio/adc/ina2xx-adc.c static bool ina2xx_is_volatile_reg(struct device *dev, unsigned int reg) reg 108 drivers/iio/adc/ina2xx-adc.c return (reg != INA2XX_CONFIG); reg 111 drivers/iio/adc/ina2xx-adc.c static inline bool is_signed_reg(unsigned int reg) reg 113 drivers/iio/adc/ina2xx-adc.c return (reg == INA2XX_SHUNT_VOLTAGE) || (reg == INA2XX_CURRENT); reg 874 drivers/iio/adc/ina2xx-adc.c unsigned reg, unsigned writeval, unsigned *readval) reg 879 drivers/iio/adc/ina2xx-adc.c return regmap_write(chip->regmap, reg, writeval); reg 881 drivers/iio/adc/ina2xx-adc.c return regmap_read(chip->regmap, reg, readval); reg 73 drivers/iio/adc/lpc18xx_adc.c u32 reg; reg 75 drivers/iio/adc/lpc18xx_adc.c reg = adc->cr_reg | BIT(ch) | LPC18XX_ADC_CR_START_NOW; reg 76 drivers/iio/adc/lpc18xx_adc.c writel(reg, adc->base + LPC18XX_ADC_CR); reg 78 drivers/iio/adc/lpc18xx_adc.c ret = readl_poll_timeout(adc->base + LPC18XX_ADC_GDR, reg, reg 79 drivers/iio/adc/lpc18xx_adc.c reg & LPC18XX_ADC_CONV_DONE, 3, 9); reg 85 drivers/iio/adc/lpc18xx_adc.c return (reg >> LPC18XX_ADC_SAMPLE_SHIFT) & LPC18XX_ADC_SAMPLE_MASK; reg 212 drivers/iio/adc/max1027.c u8 reg ____cacheline_aligned; reg 228 drivers/iio/adc/max1027.c st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2 | MAX1027_CKS_MODE2; reg 229 drivers/iio/adc/max1027.c ret = spi_write(st->spi, &st->reg, 1); reg 237 drivers/iio/adc/max1027.c st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) | reg 240 drivers/iio/adc/max1027.c st->reg |= MAX1027_TEMP; reg 241 drivers/iio/adc/max1027.c ret = spi_write(st->spi, &st->reg, 1); reg 306 drivers/iio/adc/max1027.c unsigned reg, unsigned writeval, reg 338 drivers/iio/adc/max1027.c st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE0 | reg 340 drivers/iio/adc/max1027.c ret = spi_write(st->spi, &st->reg, 1); reg 345 drivers/iio/adc/max1027.c st->reg = MAX1027_CONV_REG | MAX1027_CHAN(0) | reg 347 drivers/iio/adc/max1027.c ret = spi_write(st->spi, &st->reg, 1); reg 352 drivers/iio/adc/max1027.c st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE2 | reg 354 drivers/iio/adc/max1027.c ret = spi_write(st->spi, &st->reg, 1); reg 462 drivers/iio/adc/max1027.c st->reg = MAX1027_RST_REG; reg 463 drivers/iio/adc/max1027.c ret = spi_write(st->spi, &st->reg, 1); reg 470 drivers/iio/adc/max1027.c st->reg = MAX1027_AVG_REG; reg 471 drivers/iio/adc/max1027.c ret = spi_write(st->spi, &st->reg, 1); reg 37 drivers/iio/adc/max1118.c struct regulator *reg; reg 117 drivers/iio/adc/max1118.c vref_uV = regulator_get_voltage(adc->reg); reg 209 drivers/iio/adc/max1118.c adc->reg = devm_regulator_get(&spi->dev, "vref"); reg 210 drivers/iio/adc/max1118.c if (IS_ERR(adc->reg)) { reg 212 drivers/iio/adc/max1118.c return PTR_ERR(adc->reg); reg 214 drivers/iio/adc/max1118.c ret = regulator_enable(adc->reg); reg 251 drivers/iio/adc/max1118.c regulator_disable(adc->reg); reg 265 drivers/iio/adc/max1118.c return regulator_disable(adc->reg); reg 171 drivers/iio/adc/max1363.c struct regulator *reg; reg 1590 drivers/iio/adc/max1363.c st->reg = devm_regulator_get(&client->dev, "vcc"); reg 1591 drivers/iio/adc/max1363.c if (IS_ERR(st->reg)) { reg 1592 drivers/iio/adc/max1363.c ret = PTR_ERR(st->reg); reg 1596 drivers/iio/adc/max1363.c ret = regulator_enable(st->reg); reg 1681 drivers/iio/adc/max1363.c regulator_disable(st->reg); reg 1696 drivers/iio/adc/max1363.c regulator_disable(st->reg); reg 90 drivers/iio/adc/mcp320x.c struct regulator *reg; reg 216 drivers/iio/adc/mcp320x.c ret = regulator_get_voltage(adc->reg); reg 440 drivers/iio/adc/mcp320x.c adc->reg = devm_regulator_get(&spi->dev, "vref"); reg 441 drivers/iio/adc/mcp320x.c if (IS_ERR(adc->reg)) reg 442 drivers/iio/adc/mcp320x.c return PTR_ERR(adc->reg); reg 444 drivers/iio/adc/mcp320x.c ret = regulator_enable(adc->reg); reg 457 drivers/iio/adc/mcp320x.c regulator_disable(adc->reg); reg 468 drivers/iio/adc/mcp320x.c regulator_disable(adc->reg); reg 44 drivers/iio/adc/mcp3911.c #define MCP3911_REG_READ(reg, id) ((((reg) << 1) | ((id) << 5) | (1 << 0)) & 0xff) reg 45 drivers/iio/adc/mcp3911.c #define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 5) | (0 << 0)) & 0xff) reg 57 drivers/iio/adc/mcp3911.c static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len) reg 61 drivers/iio/adc/mcp3911.c reg = MCP3911_REG_READ(reg, adc->dev_addr); reg 62 drivers/iio/adc/mcp3911.c ret = spi_write_then_read(adc->spi, ®, 1, val, len); reg 69 drivers/iio/adc/mcp3911.c reg >> 1); reg 73 drivers/iio/adc/mcp3911.c static int mcp3911_write(struct mcp3911 *adc, u8 reg, u32 val, u8 len) reg 75 drivers/iio/adc/mcp3911.c dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n", val, reg); reg 79 drivers/iio/adc/mcp3911.c val |= MCP3911_REG_WRITE(reg, adc->dev_addr); reg 84 drivers/iio/adc/mcp3911.c static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask, reg 90 drivers/iio/adc/mcp3911.c ret = mcp3911_read(adc, reg, &tmp, len); reg 96 drivers/iio/adc/mcp3911.c return mcp3911_write(adc, reg, val, len); reg 669 drivers/iio/adc/meson_saradc.c priv->clk_div.reg = base + MESON_SAR_ADC_REG3; reg 691 drivers/iio/adc/meson_saradc.c priv->clk_gate.reg = base + MESON_SAR_ADC_REG3; reg 90 drivers/iio/adc/mt6577_auxadc.c static inline void mt6577_auxadc_mod_reg(void __iomem *reg, reg 95 drivers/iio/adc/mt6577_auxadc.c val = readl(reg); reg 98 drivers/iio/adc/mt6577_auxadc.c writel(val, reg); reg 388 drivers/iio/adc/mxs-lradc-adc.c unsigned long reg = readl(adc->base + LRADC_CTRL1); reg 391 drivers/iio/adc/mxs-lradc-adc.c if (!(reg & mxs_lradc_irq_mask(lradc))) reg 395 drivers/iio/adc/mxs-lradc-adc.c if (reg & lradc->buffer_vchans) { reg 400 drivers/iio/adc/mxs-lradc-adc.c } else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) { reg 404 drivers/iio/adc/mxs-lradc-adc.c writel(reg & mxs_lradc_irq_mask(lradc), reg 737 drivers/iio/adc/qcom-spmi-adc5.c u32 reg; reg 743 drivers/iio/adc/qcom-spmi-adc5.c ret = of_property_read_u32(node, "reg", ®); reg 754 drivers/iio/adc/qcom-spmi-adc5.c adc->base = reg; reg 858 drivers/iio/adc/qcom-spmi-vadc.c u32 reg; reg 864 drivers/iio/adc/qcom-spmi-vadc.c ret = of_property_read_u32(node, "reg", ®); reg 875 drivers/iio/adc/qcom-spmi-vadc.c vadc->base = reg; reg 246 drivers/iio/adc/rcar-gyroadc.c unsigned int reg, unsigned int writeval, reg 255 drivers/iio/adc/rcar-gyroadc.c if (reg % 4) reg 262 drivers/iio/adc/rcar-gyroadc.c if (reg > maxreg) reg 265 drivers/iio/adc/rcar-gyroadc.c *readval = readl(priv->regs + reg); reg 328 drivers/iio/adc/rcar-gyroadc.c unsigned int reg; reg 370 drivers/iio/adc/rcar-gyroadc.c reg = 0; reg 372 drivers/iio/adc/rcar-gyroadc.c ret = of_property_read_u32(child, "reg", ®); reg 381 drivers/iio/adc/rcar-gyroadc.c if (reg >= num_channels) { reg 384 drivers/iio/adc/rcar-gyroadc.c num_channels, child, reg); reg 393 drivers/iio/adc/rcar-gyroadc.c reg); reg 403 drivers/iio/adc/rcar-gyroadc.c reg); reg 407 drivers/iio/adc/rcar-gyroadc.c priv->vref[reg] = vref; reg 111 drivers/iio/adc/stm32-adc.c int reg; reg 450 drivers/iio/adc/stm32-adc.c static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg) reg 452 drivers/iio/adc/stm32-adc.c return readl_relaxed(adc->common->base + adc->offset + reg); reg 457 drivers/iio/adc/stm32-adc.c #define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \ reg 458 drivers/iio/adc/stm32-adc.c readx_poll_timeout(stm32_adc_readl_addr, reg, val, \ reg 461 drivers/iio/adc/stm32-adc.c static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg) reg 463 drivers/iio/adc/stm32-adc.c return readw_relaxed(adc->common->base + adc->offset + reg); reg 466 drivers/iio/adc/stm32-adc.c static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val) reg 468 drivers/iio/adc/stm32-adc.c writel_relaxed(val, adc->common->base + adc->offset + reg); reg 471 drivers/iio/adc/stm32-adc.c static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits) reg 476 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits); reg 480 drivers/iio/adc/stm32-adc.c static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits) reg 485 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits); reg 495 drivers/iio/adc/stm32-adc.c stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg, reg 505 drivers/iio/adc/stm32-adc.c stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg, reg 514 drivers/iio/adc/stm32-adc.c val = stm32_adc_readl(adc, res->reg); reg 516 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, res->reg, val); reg 977 drivers/iio/adc/stm32-adc.c val = stm32_adc_readl(adc, sqr[i].reg); reg 980 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, sqr[i].reg, val); reg 987 drivers/iio/adc/stm32-adc.c val = stm32_adc_readl(adc, sqr[0].reg); reg 990 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, sqr[0].reg, val); reg 1051 drivers/iio/adc/stm32-adc.c val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg); reg 1055 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val); reg 1129 drivers/iio/adc/stm32-adc.c val = stm32_adc_readl(adc, regs->sqr[1].reg); reg 1132 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, regs->sqr[1].reg, val); reg 1135 drivers/iio/adc/stm32-adc.c stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask); reg 1138 drivers/iio/adc/stm32-adc.c stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask); reg 1212 drivers/iio/adc/stm32-adc.c u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); reg 1309 drivers/iio/adc/stm32-adc.c unsigned reg, unsigned writeval, reg 1323 drivers/iio/adc/stm32-adc.c stm32_adc_writel(adc, reg, writeval); reg 1325 drivers/iio/adc/stm32-adc.c *readval = stm32_adc_readl(adc, reg); reg 1605 drivers/iio/adc/stm32-adc.c unsigned int smp, r = smpr->reg; reg 33 drivers/iio/adc/stm32-dfsdm-core.c static bool stm32_dfsdm_volatile_reg(struct device *dev, unsigned int reg) reg 35 drivers/iio/adc/stm32-dfsdm-core.c if (reg < DFSDM_FILTER_BASE_ADR) reg 42 drivers/iio/adc/stm32-dfsdm-core.c switch (reg & DFSDM_FILTER_REG_MASK) { reg 169 drivers/iio/adc/sun4i-gpadc-iio.c u32 reg; reg 181 drivers/iio/adc/sun4i-gpadc-iio.c ret = regmap_read(info->regmap, SUN4I_GPADC_CTRL1, ®); reg 194 drivers/iio/adc/sun4i-gpadc-iio.c if ((reg & info->data->adc_chan_mask) != reg 214 drivers/iio/adc/sun4i-gpadc-iio.c if ((reg & info->data->tp_adc_select) != info->data->tp_adc_select) reg 28 drivers/iio/adc/ti-adc0832.c struct regulator *reg; reg 179 drivers/iio/adc/ti-adc0832.c *value = regulator_get_voltage(adc->reg); reg 278 drivers/iio/adc/ti-adc0832.c adc->reg = devm_regulator_get(&spi->dev, "vref"); reg 279 drivers/iio/adc/ti-adc0832.c if (IS_ERR(adc->reg)) reg 280 drivers/iio/adc/ti-adc0832.c return PTR_ERR(adc->reg); reg 282 drivers/iio/adc/ti-adc0832.c ret = regulator_enable(adc->reg); reg 301 drivers/iio/adc/ti-adc0832.c regulator_disable(adc->reg); reg 313 drivers/iio/adc/ti-adc0832.c regulator_disable(adc->reg); reg 26 drivers/iio/adc/ti-adc084s021.c struct regulator *reg; reg 97 drivers/iio/adc/ti-adc084s021.c ret = regulator_enable(adc->reg); reg 106 drivers/iio/adc/ti-adc084s021.c regulator_disable(adc->reg); reg 115 drivers/iio/adc/ti-adc084s021.c ret = regulator_enable(adc->reg); reg 119 drivers/iio/adc/ti-adc084s021.c ret = regulator_get_voltage(adc->reg); reg 120 drivers/iio/adc/ti-adc084s021.c regulator_disable(adc->reg); reg 172 drivers/iio/adc/ti-adc084s021.c return regulator_enable(adc->reg); reg 181 drivers/iio/adc/ti-adc084s021.c return regulator_disable(adc->reg); reg 228 drivers/iio/adc/ti-adc084s021.c adc->reg = devm_regulator_get(&spi->dev, "vref"); reg 229 drivers/iio/adc/ti-adc084s021.c if (IS_ERR(adc->reg)) reg 230 drivers/iio/adc/ti-adc084s021.c return PTR_ERR(adc->reg); reg 60 drivers/iio/adc/ti-adc108s102.c struct regulator *reg; reg 232 drivers/iio/adc/ti-adc108s102.c st->reg = devm_regulator_get(&spi->dev, "vref"); reg 233 drivers/iio/adc/ti-adc108s102.c if (IS_ERR(st->reg)) reg 234 drivers/iio/adc/ti-adc108s102.c return PTR_ERR(st->reg); reg 236 drivers/iio/adc/ti-adc108s102.c ret = regulator_enable(st->reg); reg 242 drivers/iio/adc/ti-adc108s102.c ret = regulator_get_voltage(st->reg); reg 285 drivers/iio/adc/ti-adc108s102.c regulator_disable(st->reg); reg 298 drivers/iio/adc/ti-adc108s102.c regulator_disable(st->reg); reg 28 drivers/iio/adc/ti-adc128s052.c struct regulator *reg; reg 78 drivers/iio/adc/ti-adc128s052.c ret = regulator_get_voltage(adc->reg); reg 164 drivers/iio/adc/ti-adc128s052.c adc->reg = devm_regulator_get(&spi->dev, "vref"); reg 165 drivers/iio/adc/ti-adc128s052.c if (IS_ERR(adc->reg)) reg 166 drivers/iio/adc/ti-adc128s052.c return PTR_ERR(adc->reg); reg 168 drivers/iio/adc/ti-adc128s052.c ret = regulator_enable(adc->reg); reg 185 drivers/iio/adc/ti-adc128s052.c regulator_disable(adc->reg); reg 269 drivers/iio/adc/ti-ads1015.c static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg) reg 271 drivers/iio/adc/ti-ads1015.c switch (reg) { reg 161 drivers/iio/adc/ti-ads124s08.c static int ads124s_write_reg(struct iio_dev *indio_dev, u8 reg, u8 data) reg 165 drivers/iio/adc/ti-ads124s08.c priv->data[0] = ADS124S08_CMD_WREG | reg; reg 77 drivers/iio/adc/ti-ads7950.c struct regulator *reg; reg 354 drivers/iio/adc/ti-ads7950.c vref = regulator_get_voltage(st->reg); reg 603 drivers/iio/adc/ti-ads7950.c st->reg = devm_regulator_get(&spi->dev, "vref"); reg 604 drivers/iio/adc/ti-ads7950.c if (IS_ERR(st->reg)) { reg 606 drivers/iio/adc/ti-ads7950.c ret = PTR_ERR(st->reg); reg 610 drivers/iio/adc/ti-ads7950.c ret = regulator_enable(st->reg); reg 660 drivers/iio/adc/ti-ads7950.c regulator_disable(st->reg); reg 675 drivers/iio/adc/ti-ads7950.c regulator_disable(st->reg); reg 24 drivers/iio/adc/ti-ads8344.c struct regulator *reg; reg 118 drivers/iio/adc/ti-ads8344.c *value = regulator_get_voltage(adc->reg); reg 158 drivers/iio/adc/ti-ads8344.c adc->reg = devm_regulator_get(&spi->dev, "vref"); reg 159 drivers/iio/adc/ti-ads8344.c if (IS_ERR(adc->reg)) reg 160 drivers/iio/adc/ti-ads8344.c return PTR_ERR(adc->reg); reg 162 drivers/iio/adc/ti-ads8344.c ret = regulator_enable(adc->reg); reg 170 drivers/iio/adc/ti-ads8344.c regulator_disable(adc->reg); reg 183 drivers/iio/adc/ti-ads8344.c regulator_disable(adc->reg); reg 68 drivers/iio/adc/ti-ads8688.c struct regulator *reg; reg 86 drivers/iio/adc/ti-ads8688.c u8 reg; reg 94 drivers/iio/adc/ti-ads8688.c .reg = ADS8688_REG_PLUSMINUS25VREF, reg 99 drivers/iio/adc/ti-ads8688.c .reg = ADS8688_REG_PLUSMINUS125VREF, reg 104 drivers/iio/adc/ti-ads8688.c .reg = ADS8688_REG_PLUSMINUS0625VREF, reg 109 drivers/iio/adc/ti-ads8688.c .reg = ADS8688_REG_PLUS25VREF, reg 114 drivers/iio/adc/ti-ads8688.c .reg = ADS8688_REG_PLUS125VREF, reg 315 drivers/iio/adc/ti-ads8688.c ads8688_range_def[i].reg); reg 347 drivers/iio/adc/ti-ads8688.c ads8688_range_def[i].reg); reg 427 drivers/iio/adc/ti-ads8688.c st->reg = devm_regulator_get_optional(&spi->dev, "vref"); reg 428 drivers/iio/adc/ti-ads8688.c if (!IS_ERR(st->reg)) { reg 429 drivers/iio/adc/ti-ads8688.c ret = regulator_enable(st->reg); reg 433 drivers/iio/adc/ti-ads8688.c ret = regulator_get_voltage(st->reg); reg 479 drivers/iio/adc/ti-ads8688.c if (!IS_ERR(st->reg)) reg 480 drivers/iio/adc/ti-ads8688.c regulator_disable(st->reg); reg 493 drivers/iio/adc/ti-ads8688.c if (!IS_ERR(st->reg)) reg 494 drivers/iio/adc/ti-ads8688.c regulator_disable(st->reg); reg 34 drivers/iio/adc/ti-tlc4541.c struct regulator *reg; reg 113 drivers/iio/adc/ti-tlc4541.c vref = regulator_get_voltage(st->reg); reg 199 drivers/iio/adc/ti-tlc4541.c st->reg = devm_regulator_get(&spi->dev, "vref"); reg 200 drivers/iio/adc/ti-tlc4541.c if (IS_ERR(st->reg)) reg 201 drivers/iio/adc/ti-tlc4541.c return PTR_ERR(st->reg); reg 203 drivers/iio/adc/ti-tlc4541.c ret = regulator_enable(st->reg); reg 221 drivers/iio/adc/ti-tlc4541.c regulator_disable(st->reg); reg 233 drivers/iio/adc/ti-tlc4541.c regulator_disable(st->reg); reg 62 drivers/iio/adc/ti_am335x_adc.c static unsigned int tiadc_readl(struct tiadc_device *adc, unsigned int reg) reg 64 drivers/iio/adc/ti_am335x_adc.c return readl(adc->mfd_tscadc->tscadc_base + reg); reg 67 drivers/iio/adc/ti_am335x_adc.c static void tiadc_writel(struct tiadc_device *adc, unsigned int reg, reg 70 drivers/iio/adc/ti_am335x_adc.c writel(val, adc->mfd_tscadc->tscadc_base + reg); reg 308 drivers/iio/adc/twl4030-madc.c static int twl4030_madc_channel_raw_read(struct twl4030_madc_data *madc, u8 reg) reg 316 drivers/iio/adc/twl4030-madc.c ret = twl_i2c_read_u16(TWL4030_MODULE_MADC, &val, reg); reg 318 drivers/iio/adc/twl4030-madc.c dev_err(madc->dev, "unable to read register 0x%X\n", reg); reg 386 drivers/iio/adc/twl4030-madc.c u8 reg; reg 389 drivers/iio/adc/twl4030-madc.c reg = reg_base + (2 * i); reg 390 drivers/iio/adc/twl4030-madc.c buf[i] = twl4030_madc_channel_raw_read(madc, reg); reg 393 drivers/iio/adc/twl4030-madc.c reg); reg 584 drivers/iio/adc/twl4030-madc.c u8 reg; reg 586 drivers/iio/adc/twl4030-madc.c ret = twl_i2c_read_u8(TWL4030_MODULE_MADC, ®, status_reg); reg 593 drivers/iio/adc/twl4030-madc.c if (!(reg & TWL4030_MADC_BUSY) && (reg & TWL4030_MADC_EOC_SW)) reg 340 drivers/iio/adc/twl6030-gpadc.c static inline int twl6030_gpadc_write(u8 reg, u8 val) reg 342 drivers/iio/adc/twl6030-gpadc.c return twl_i2c_write_u8(TWL6030_MODULE_GPADC, val, reg); reg 345 drivers/iio/adc/twl6030-gpadc.c static inline int twl6030_gpadc_read(u8 reg, u8 *val) reg 348 drivers/iio/adc/twl6030-gpadc.c return twl_i2c_read(TWL6030_MODULE_GPADC, val, reg, 2); reg 453 drivers/iio/adc/twl6030-gpadc.c u8 reg = gpadc->pdata->channel_to_reg(channel); reg 458 drivers/iio/adc/twl6030-gpadc.c ret = twl6030_gpadc_read(reg, (u8 *)&val); reg 460 drivers/iio/adc/twl6030-gpadc.c dev_dbg(gpadc->dev, "unable to read register 0x%X\n", reg); reg 774 drivers/iio/adc/vf610_adc.c unsigned reg, unsigned writeval, reg 780 drivers/iio/adc/vf610_adc.c ((reg % 4) || (reg > VF610_REG_ADC_PCTL))) reg 783 drivers/iio/adc/vf610_adc.c *readval = readl(info->regs + reg); reg 115 drivers/iio/adc/xilinx-xadc-core.c static void xadc_write_reg(struct xadc *xadc, unsigned int reg, reg 118 drivers/iio/adc/xilinx-xadc-core.c writel(val, xadc->base + reg); reg 121 drivers/iio/adc/xilinx-xadc-core.c static void xadc_read_reg(struct xadc *xadc, unsigned int reg, reg 124 drivers/iio/adc/xilinx-xadc-core.c *val = readl(xadc->base + reg); reg 168 drivers/iio/adc/xilinx-xadc-core.c static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg, reg 181 drivers/iio/adc/xilinx-xadc-core.c cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val); reg 202 drivers/iio/adc/xilinx-xadc-core.c static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg, reg 209 drivers/iio/adc/xilinx-xadc-core.c cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_READ, reg, 0); reg 452 drivers/iio/adc/xilinx-xadc-core.c static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg, reg 457 drivers/iio/adc/xilinx-xadc-core.c xadc_read_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, &val32); reg 463 drivers/iio/adc/xilinx-xadc-core.c static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg, reg 466 drivers/iio/adc/xilinx-xadc-core.c xadc_write_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, val); reg 554 drivers/iio/adc/xilinx-xadc-core.c static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg, reg 560 drivers/iio/adc/xilinx-xadc-core.c ret = _xadc_read_adc_reg(xadc, reg, &tmp); reg 564 drivers/iio/adc/xilinx-xadc-core.c return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val); reg 567 drivers/iio/adc/xilinx-xadc-core.c static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg, reg 573 drivers/iio/adc/xilinx-xadc-core.c ret = _xadc_update_adc_reg(xadc, reg, mask, val); reg 1103 drivers/iio/adc/xilinx-xadc-core.c u32 reg; reg 1156 drivers/iio/adc/xilinx-xadc-core.c ret = of_property_read_u32(child, "reg", ®); reg 1157 drivers/iio/adc/xilinx-xadc-core.c if (ret || reg > 16) reg 1163 drivers/iio/adc/xilinx-xadc-core.c if (reg == 0) { reg 1167 drivers/iio/adc/xilinx-xadc-core.c chan->scan_index = 15 + reg; reg 1168 drivers/iio/adc/xilinx-xadc-core.c chan->address = XADC_REG_VAUX(reg - 1); reg 74 drivers/iio/adc/xilinx-xadc.h int (*read)(struct xadc *xadc, unsigned int reg, uint16_t *val); reg 75 drivers/iio/adc/xilinx-xadc.h int (*write)(struct xadc *xadc, unsigned int reg, uint16_t val); reg 85 drivers/iio/adc/xilinx-xadc.h static inline int _xadc_read_adc_reg(struct xadc *xadc, unsigned int reg, reg 89 drivers/iio/adc/xilinx-xadc.h return xadc->ops->read(xadc, reg, val); reg 92 drivers/iio/adc/xilinx-xadc.h static inline int _xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, reg 96 drivers/iio/adc/xilinx-xadc.h return xadc->ops->write(xadc, reg, val); reg 99 drivers/iio/adc/xilinx-xadc.h static inline int xadc_read_adc_reg(struct xadc *xadc, unsigned int reg, reg 105 drivers/iio/adc/xilinx-xadc.h ret = _xadc_read_adc_reg(xadc, reg, val); reg 110 drivers/iio/adc/xilinx-xadc.h static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg, reg 116 drivers/iio/adc/xilinx-xadc.h ret = _xadc_write_adc_reg(xadc, reg, val); reg 39 drivers/iio/amplifiers/ad8366.c struct regulator *reg; reg 217 drivers/iio/amplifiers/ad8366.c st->reg = devm_regulator_get(&spi->dev, "vcc"); reg 218 drivers/iio/amplifiers/ad8366.c if (!IS_ERR(st->reg)) { reg 219 drivers/iio/amplifiers/ad8366.c ret = regulator_enable(st->reg); reg 264 drivers/iio/amplifiers/ad8366.c if (!IS_ERR(st->reg)) reg 265 drivers/iio/amplifiers/ad8366.c regulator_disable(st->reg); reg 274 drivers/iio/amplifiers/ad8366.c struct regulator *reg = st->reg; reg 278 drivers/iio/amplifiers/ad8366.c if (!IS_ERR(reg)) reg 279 drivers/iio/amplifiers/ad8366.c regulator_disable(reg); reg 383 drivers/iio/chemical/atlas-ph-sensor.c static int atlas_read_measurement(struct atlas_data *data, int reg, __be32 *val) reg 398 drivers/iio/chemical/atlas-ph-sensor.c ret = regmap_bulk_read(data->regmap, reg, (u8 *) val, sizeof(*val)); reg 415 drivers/iio/chemical/atlas-ph-sensor.c __be32 reg; reg 420 drivers/iio/chemical/atlas-ph-sensor.c (u8 *) ®, sizeof(reg)); reg 430 drivers/iio/chemical/atlas-ph-sensor.c ret = atlas_read_measurement(data, chan->address, ®); reg 439 drivers/iio/chemical/atlas-ph-sensor.c *val = be32_to_cpu(reg); reg 479 drivers/iio/chemical/atlas-ph-sensor.c __be32 reg = cpu_to_be32(val / 10); reg 488 drivers/iio/chemical/atlas-ph-sensor.c ®, sizeof(reg)); reg 26 drivers/iio/chemical/bme680_spi.c struct bme680_spi_bus_context *ctx, u8 reg) reg 31 drivers/iio/chemical/bme680_spi.c u8 page = (reg & 0x80) ? 0 : 1; /* Page "1" is low range */ reg 87 drivers/iio/chemical/bme680_spi.c static int bme680_regmap_spi_read(void *context, const void *reg, reg 93 drivers/iio/chemical/bme680_spi.c u8 addr = *(const u8 *)reg; reg 39 drivers/iio/common/st_sensors/st_sensors_core.c unsigned reg, unsigned writeval, reg 46 drivers/iio/common/st_sensors/st_sensors_core.c return regmap_write(sdata->regmap, reg, writeval); reg 48 drivers/iio/common/st_sensors/st_sensors_core.c err = regmap_read(sdata->regmap, reg, readval); reg 460 drivers/iio/dac/ad5380.c static bool ad5380_reg_false(struct device *dev, unsigned int reg) reg 133 drivers/iio/dac/ad5421.c unsigned int reg, unsigned int val) reg 137 drivers/iio/dac/ad5421.c st->data[0].d32 = cpu_to_be32((reg << 16) | val); reg 142 drivers/iio/dac/ad5421.c static int ad5421_write(struct iio_dev *indio_dev, unsigned int reg, reg 148 drivers/iio/dac/ad5421.c ret = ad5421_write_unlocked(indio_dev, reg, val); reg 154 drivers/iio/dac/ad5421.c static int ad5421_read(struct iio_dev *indio_dev, unsigned int reg) reg 171 drivers/iio/dac/ad5421.c st->data[0].d32 = cpu_to_be32((1 << 23) | (reg << 16)); reg 39 drivers/iio/dac/ad5446.c struct regulator *reg; reg 221 drivers/iio/dac/ad5446.c struct regulator *reg; reg 224 drivers/iio/dac/ad5446.c reg = devm_regulator_get(dev, "vcc"); reg 225 drivers/iio/dac/ad5446.c if (!IS_ERR(reg)) { reg 226 drivers/iio/dac/ad5446.c ret = regulator_enable(reg); reg 230 drivers/iio/dac/ad5446.c ret = regulator_get_voltage(reg); reg 246 drivers/iio/dac/ad5446.c st->reg = reg; reg 273 drivers/iio/dac/ad5446.c if (!IS_ERR(reg)) reg 274 drivers/iio/dac/ad5446.c regulator_disable(reg); reg 284 drivers/iio/dac/ad5446.c if (!IS_ERR(st->reg)) reg 285 drivers/iio/dac/ad5446.c regulator_disable(st->reg); reg 134 drivers/iio/dac/ad5449.c struct regulator_bulk_data *reg; reg 152 drivers/iio/dac/ad5449.c reg = &st->vref_reg[chan->channel]; reg 153 drivers/iio/dac/ad5449.c scale_uv = regulator_get_voltage(reg->consumer); reg 52 drivers/iio/dac/ad5504.c struct regulator *reg; reg 277 drivers/iio/dac/ad5504.c struct regulator *reg; reg 283 drivers/iio/dac/ad5504.c reg = devm_regulator_get(&spi->dev, "vcc"); reg 284 drivers/iio/dac/ad5504.c if (!IS_ERR(reg)) { reg 285 drivers/iio/dac/ad5504.c ret = regulator_enable(reg); reg 289 drivers/iio/dac/ad5504.c ret = regulator_get_voltage(reg); reg 305 drivers/iio/dac/ad5504.c st->reg = reg; reg 335 drivers/iio/dac/ad5504.c if (!IS_ERR(reg)) reg 336 drivers/iio/dac/ad5504.c regulator_disable(reg); reg 348 drivers/iio/dac/ad5504.c if (!IS_ERR(st->reg)) reg 349 drivers/iio/dac/ad5504.c regulator_disable(st->reg); reg 185 drivers/iio/dac/ad5592r-base.c if (st->reg) { reg 186 drivers/iio/dac/ad5592r-base.c ret = regulator_get_voltage(st->reg); reg 521 drivers/iio/dac/ad5592r-base.c u32 reg, tmp; reg 525 drivers/iio/dac/ad5592r-base.c ret = fwnode_property_read_u32(child, "reg", ®); reg 526 drivers/iio/dac/ad5592r-base.c if (ret || reg >= ARRAY_SIZE(st->channel_modes)) reg 531 drivers/iio/dac/ad5592r-base.c st->channel_modes[reg] = tmp; reg 535 drivers/iio/dac/ad5592r-base.c st->channel_offstate[reg] = tmp; reg 612 drivers/iio/dac/ad5592r-base.c st->reg = devm_regulator_get_optional(dev, "vref"); reg 613 drivers/iio/dac/ad5592r-base.c if (IS_ERR(st->reg)) { reg 614 drivers/iio/dac/ad5592r-base.c if ((PTR_ERR(st->reg) != -ENODEV) && dev->of_node) reg 615 drivers/iio/dac/ad5592r-base.c return PTR_ERR(st->reg); reg 617 drivers/iio/dac/ad5592r-base.c st->reg = NULL; reg 619 drivers/iio/dac/ad5592r-base.c ret = regulator_enable(st->reg); reg 636 drivers/iio/dac/ad5592r-base.c (st->reg == NULL) ? AD5592R_REG_PD_EN_REF : 0); reg 665 drivers/iio/dac/ad5592r-base.c if (st->reg) reg 666 drivers/iio/dac/ad5592r-base.c regulator_disable(st->reg); reg 681 drivers/iio/dac/ad5592r-base.c if (st->reg) reg 682 drivers/iio/dac/ad5592r-base.c regulator_disable(st->reg); reg 45 drivers/iio/dac/ad5592r-base.h int (*reg_write)(struct ad5592r_state *st, u8 reg, u16 value); reg 46 drivers/iio/dac/ad5592r-base.h int (*reg_read)(struct ad5592r_state *st, u8 reg, u16 *value); reg 52 drivers/iio/dac/ad5592r-base.h struct regulator *reg; reg 71 drivers/iio/dac/ad5592r.c static int ad5592r_reg_write(struct ad5592r_state *st, u8 reg, u16 value) reg 75 drivers/iio/dac/ad5592r.c st->spi_msg = cpu_to_be16((reg << 11) | value); reg 80 drivers/iio/dac/ad5592r.c static int ad5592r_reg_read(struct ad5592r_state *st, u8 reg, u16 *value) reg 86 drivers/iio/dac/ad5592r.c AD5592R_LDAC_READBACK_EN | (reg << 2)); reg 51 drivers/iio/dac/ad5593r.c static int ad5593r_reg_write(struct ad5592r_state *st, u8 reg, u16 value) reg 56 drivers/iio/dac/ad5593r.c AD5593R_MODE_CONF | reg, value); reg 59 drivers/iio/dac/ad5593r.c static int ad5593r_reg_read(struct ad5592r_state *st, u8 reg, u16 *value) reg 64 drivers/iio/dac/ad5593r.c val = i2c_smbus_read_word_swapped(i2c, AD5593R_MODE_REG_READBACK | reg); reg 57 drivers/iio/dac/ad5624r.h struct regulator *reg; reg 232 drivers/iio/dac/ad5624r_spi.c st->reg = devm_regulator_get(&spi->dev, "vcc"); reg 233 drivers/iio/dac/ad5624r_spi.c if (!IS_ERR(st->reg)) { reg 234 drivers/iio/dac/ad5624r_spi.c ret = regulator_enable(st->reg); reg 238 drivers/iio/dac/ad5624r_spi.c ret = regulator_get_voltage(st->reg); reg 275 drivers/iio/dac/ad5624r_spi.c if (!IS_ERR(st->reg)) reg 276 drivers/iio/dac/ad5624r_spi.c regulator_disable(st->reg); reg 287 drivers/iio/dac/ad5624r_spi.c if (!IS_ERR(st->reg)) reg 288 drivers/iio/dac/ad5624r_spi.c regulator_disable(st->reg); reg 440 drivers/iio/dac/ad5686.c st->reg = devm_regulator_get_optional(dev, "vcc"); reg 441 drivers/iio/dac/ad5686.c if (!IS_ERR(st->reg)) { reg 442 drivers/iio/dac/ad5686.c ret = regulator_enable(st->reg); reg 446 drivers/iio/dac/ad5686.c ret = regulator_get_voltage(st->reg); reg 509 drivers/iio/dac/ad5686.c if (!IS_ERR(st->reg)) reg 510 drivers/iio/dac/ad5686.c regulator_disable(st->reg); reg 521 drivers/iio/dac/ad5686.c if (!IS_ERR(st->reg)) reg 522 drivers/iio/dac/ad5686.c regulator_disable(st->reg); reg 126 drivers/iio/dac/ad5686.h struct regulator *reg; reg 158 drivers/iio/dac/ad5755.c unsigned int reg, unsigned int val) reg 162 drivers/iio/dac/ad5755.c st->data[0].d32 = cpu_to_be32((reg << 16) | val); reg 168 drivers/iio/dac/ad5755.c unsigned int channel, unsigned int reg, unsigned int val) reg 171 drivers/iio/dac/ad5755.c AD5755_WRITE_REG_CTRL(channel), (reg << 13) | val); reg 174 drivers/iio/dac/ad5755.c static int ad5755_write(struct iio_dev *indio_dev, unsigned int reg, reg 180 drivers/iio/dac/ad5755.c ret = ad5755_write_unlocked(indio_dev, reg, val); reg 187 drivers/iio/dac/ad5755.c unsigned int reg, unsigned int val) reg 192 drivers/iio/dac/ad5755.c ret = ad5755_write_ctrl_unlocked(indio_dev, channel, reg, val); reg 303 drivers/iio/dac/ad5755.c unsigned int *reg, unsigned int *shift, unsigned int *offset) reg 308 drivers/iio/dac/ad5755.c *reg = AD5755_WRITE_REG_DATA(chan->address); reg 310 drivers/iio/dac/ad5755.c *reg = AD5755_READ_REG_DATA(chan->address); reg 316 drivers/iio/dac/ad5755.c *reg = AD5755_WRITE_REG_OFFSET(chan->address); reg 318 drivers/iio/dac/ad5755.c *reg = AD5755_READ_REG_OFFSET(chan->address); reg 324 drivers/iio/dac/ad5755.c *reg = AD5755_WRITE_REG_GAIN(chan->address); reg 326 drivers/iio/dac/ad5755.c *reg = AD5755_READ_REG_GAIN(chan->address); reg 341 drivers/iio/dac/ad5755.c unsigned int reg, shift, offset; reg 356 drivers/iio/dac/ad5755.c ®, &shift, &offset); reg 360 drivers/iio/dac/ad5755.c ret = ad5755_read(indio_dev, reg); reg 376 drivers/iio/dac/ad5755.c unsigned int shift, reg, offset; reg 380 drivers/iio/dac/ad5755.c ®, &shift, &offset); reg 390 drivers/iio/dac/ad5755.c return ad5755_write(indio_dev, reg, val); reg 108 drivers/iio/dac/ad5758.c int reg; reg 260 drivers/iio/dac/ad5758.c unsigned int reg, reg 268 drivers/iio/dac/ad5758.c ret = ad5758_spi_reg_read(st, reg); reg 279 drivers/iio/dac/ad5758.c "Error reading bit 0x%x in 0x%x register\n", mask, reg); reg 494 drivers/iio/dac/ad5758.c unsigned int reg, reg 503 drivers/iio/dac/ad5758.c ret = ad5758_spi_reg_read(st, reg); reg 512 drivers/iio/dac/ad5758.c ret = ad5758_spi_reg_write(st, reg, writeval); reg 685 drivers/iio/dac/ad5758.c st->out_range.reg = range[i].reg; reg 818 drivers/iio/dac/ad5758.c ret = ad5758_set_out_range(st, st->out_range.reg); reg 123 drivers/iio/dac/ad5764.c static int ad5764_write(struct iio_dev *indio_dev, unsigned int reg, reg 130 drivers/iio/dac/ad5764.c st->data[0].d32 = cpu_to_be32((reg << 16) | val); reg 138 drivers/iio/dac/ad5764.c static int ad5764_read(struct iio_dev *indio_dev, unsigned int reg, reg 156 drivers/iio/dac/ad5764.c st->data[0].d32 = cpu_to_be32((1 << 23) | (reg << 16)); reg 187 drivers/iio/dac/ad5764.c unsigned int reg; reg 207 drivers/iio/dac/ad5764.c reg = ad5764_chan_info_to_reg(chan, info); reg 208 drivers/iio/dac/ad5764.c return ad5764_write(indio_dev, reg, (u16)val); reg 224 drivers/iio/dac/ad5764.c unsigned int reg; reg 230 drivers/iio/dac/ad5764.c reg = AD5764_REG_DATA(chan->address); reg 231 drivers/iio/dac/ad5764.c ret = ad5764_read(indio_dev, reg, val); reg 237 drivers/iio/dac/ad5764.c reg = AD5764_REG_OFFSET(chan->address); reg 238 drivers/iio/dac/ad5764.c ret = ad5764_read(indio_dev, reg, val); reg 244 drivers/iio/dac/ad5764.c reg = AD5764_REG_FINE_GAIN(chan->address); reg 245 drivers/iio/dac/ad5764.c ret = ad5764_read(indio_dev, reg, val); reg 54 drivers/iio/dac/lpc18xx_dac.c u32 reg; reg 58 drivers/iio/dac/lpc18xx_dac.c reg = readl(dac->base + LPC18XX_DAC_CR); reg 59 drivers/iio/dac/lpc18xx_dac.c *val = reg >> LPC18XX_DAC_CR_VALUE_SHIFT; reg 79 drivers/iio/dac/lpc18xx_dac.c u32 reg; reg 86 drivers/iio/dac/lpc18xx_dac.c reg = LPC18XX_DAC_CR_BIAS; reg 87 drivers/iio/dac/lpc18xx_dac.c reg |= val << LPC18XX_DAC_CR_VALUE_SHIFT; reg 90 drivers/iio/dac/lpc18xx_dac.c writel(reg, dac->base + LPC18XX_DAC_CR); reg 131 drivers/iio/dac/stm32-dac.c unsigned reg, unsigned writeval, reg 137 drivers/iio/dac/stm32-dac.c return regmap_write(dac->common->regmap, reg, writeval); reg 139 drivers/iio/dac/stm32-dac.c return regmap_read(dac->common->regmap, reg, readval); reg 268 drivers/iio/frequency/ad9523.c struct regulator *reg; reg 673 drivers/iio/frequency/ad9523.c unsigned int reg; reg 681 drivers/iio/frequency/ad9523.c reg = ret; reg 686 drivers/iio/frequency/ad9523.c reg &= ~AD9523_CLK_DIST_PWR_DOWN_EN; reg 688 drivers/iio/frequency/ad9523.c reg |= AD9523_CLK_DIST_PWR_DOWN_EN; reg 700 drivers/iio/frequency/ad9523.c reg &= ~(0x3FF << 8); reg 701 drivers/iio/frequency/ad9523.c reg |= AD9523_CLK_DIST_DIV(tmp); reg 707 drivers/iio/frequency/ad9523.c reg &= ~AD9523_CLK_DIST_DIV_PHASE(~0); reg 708 drivers/iio/frequency/ad9523.c reg |= AD9523_CLK_DIST_DIV_PHASE(tmp); reg 716 drivers/iio/frequency/ad9523.c reg); reg 727 drivers/iio/frequency/ad9523.c unsigned int reg, unsigned int writeval, reg 735 drivers/iio/frequency/ad9523.c ret = ad9523_write(indio_dev, reg | AD9523_R1B, writeval); reg 738 drivers/iio/frequency/ad9523.c ret = ad9523_read(indio_dev, reg | AD9523_R1B); reg 992 drivers/iio/frequency/ad9523.c st->reg = devm_regulator_get(&spi->dev, "vcc"); reg 993 drivers/iio/frequency/ad9523.c if (!IS_ERR(st->reg)) { reg 994 drivers/iio/frequency/ad9523.c ret = regulator_enable(st->reg); reg 1050 drivers/iio/frequency/ad9523.c if (!IS_ERR(st->reg)) reg 1051 drivers/iio/frequency/ad9523.c regulator_disable(st->reg); reg 1063 drivers/iio/frequency/ad9523.c if (!IS_ERR(st->reg)) reg 1064 drivers/iio/frequency/ad9523.c regulator_disable(st->reg); reg 36 drivers/iio/frequency/adf4350.c struct regulator *reg; reg 94 drivers/iio/frequency/adf4350.c unsigned reg, unsigned writeval, reg 100 drivers/iio/frequency/adf4350.c if (reg > ADF4350_REG5) reg 105 drivers/iio/frequency/adf4350.c st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2)); reg 108 drivers/iio/frequency/adf4350.c *readval = st->regs_hw[reg]; reg 531 drivers/iio/frequency/adf4350.c st->reg = devm_regulator_get(&spi->dev, "vcc"); reg 532 drivers/iio/frequency/adf4350.c if (!IS_ERR(st->reg)) { reg 533 drivers/iio/frequency/adf4350.c ret = regulator_enable(st->reg); reg 588 drivers/iio/frequency/adf4350.c if (!IS_ERR(st->reg)) reg 589 drivers/iio/frequency/adf4350.c regulator_disable(st->reg); reg 601 drivers/iio/frequency/adf4350.c struct regulator *reg = st->reg; reg 611 drivers/iio/frequency/adf4350.c if (!IS_ERR(reg)) reg 612 drivers/iio/frequency/adf4350.c regulator_disable(reg); reg 100 drivers/iio/frequency/adf4371.c unsigned int reg; reg 331 drivers/iio/frequency/adf4371.c unsigned int readval, reg, bit; reg 347 drivers/iio/frequency/adf4371.c reg = adf4371_pwrdown_ch[chan->channel].reg; reg 350 drivers/iio/frequency/adf4371.c ret = regmap_read(st->regmap, reg, &readval); reg 375 drivers/iio/frequency/adf4371.c unsigned int bit, readval, reg; reg 392 drivers/iio/frequency/adf4371.c reg = adf4371_pwrdown_ch[chan->channel].reg; reg 394 drivers/iio/frequency/adf4371.c ret = regmap_read(st->regmap, reg, &readval); reg 401 drivers/iio/frequency/adf4371.c ret = regmap_write(st->regmap, reg, readval); reg 459 drivers/iio/frequency/adf4371.c unsigned int reg, reg 466 drivers/iio/frequency/adf4371.c return regmap_read(st->regmap, reg, readval); reg 468 drivers/iio/frequency/adf4371.c return regmap_write(st->regmap, reg, writeval); reg 89 drivers/iio/gyro/itg3200_core.c u8 reg; reg 94 drivers/iio/gyro/itg3200_core.c reg = (u8)chan->address; reg 95 drivers/iio/gyro/itg3200_core.c ret = itg3200_read_reg_s16(indio_dev, reg, val); reg 212 drivers/iio/health/afe4403.c static int afe4403_read(struct afe4403_data *afe, unsigned int reg, u32 *val) reg 223 drivers/iio/health/afe4403.c ret = spi_write_then_read(afe->spi, ®, 1, rx, 3); reg 245 drivers/iio/health/afe4403.c unsigned int reg = afe4403_channel_values[chan->address]; reg 253 drivers/iio/health/afe4403.c ret = afe4403_read(afe, reg, val); reg 79 drivers/iio/health/max30100.c static bool max30100_is_volatile_reg(struct device *dev, unsigned int reg) reg 81 drivers/iio/health/max30100.c switch (reg) { reg 247 drivers/iio/health/max30100.c static int max30100_get_current_idx(unsigned int val, int *reg) reg 253 drivers/iio/health/max30100.c *reg = 0; reg 259 drivers/iio/health/max30100.c *reg = idx + 1; reg 272 drivers/iio/health/max30100.c int reg, ret; reg 278 drivers/iio/health/max30100.c reg = (MAX30100_REG_LED_CONFIG_24MA << reg 283 drivers/iio/health/max30100.c return regmap_write(data->regmap, MAX30100_REG_LED_CONFIG, reg); reg 287 drivers/iio/health/max30100.c ret = max30100_get_current_idx(val[0], ®); reg 296 drivers/iio/health/max30100.c reg << MAX30100_REG_LED_CONFIG_RED_LED_SHIFT); reg 301 drivers/iio/health/max30100.c ret = max30100_get_current_idx(val[1], ®); reg 308 drivers/iio/health/max30100.c MAX30100_REG_LED_CONFIG_LED_MASK, reg); reg 345 drivers/iio/health/max30100.c unsigned int reg; reg 347 drivers/iio/health/max30100.c ret = regmap_read(data->regmap, MAX30100_REG_TEMP_INTEGER, ®); reg 350 drivers/iio/health/max30100.c *val = reg << 4; reg 352 drivers/iio/health/max30100.c ret = regmap_read(data->regmap, MAX30100_REG_TEMP_FRACTION, ®); reg 356 drivers/iio/health/max30100.c *val |= reg & 0xf; reg 179 drivers/iio/health/max30102.c u8 reg = mode; reg 182 drivers/iio/health/max30102.c reg |= MAX30102_REG_MODE_CONFIG_PWR; reg 186 drivers/iio/health/max30102.c MAX30102_REG_MODE_CONFIG_MODE_MASK, reg); reg 196 drivers/iio/health/max30102.c u8 reg; reg 200 drivers/iio/health/max30102.c reg = MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2; reg 218 drivers/iio/health/max30102.c reg = MAX30102_REG_MODE_CONFIG_MODE_MULTI; reg 224 drivers/iio/health/max30102.c return max30102_set_powermode(data, reg, true); reg 315 drivers/iio/health/max30102.c static int max30102_get_current_idx(unsigned int val, int *reg) reg 318 drivers/iio/health/max30102.c *reg = val / 200; reg 320 drivers/iio/health/max30102.c return *reg > 0xff ? -EINVAL : 0; reg 328 drivers/iio/health/max30102.c int reg, ret; reg 338 drivers/iio/health/max30102.c ret = max30102_get_current_idx(val, ®); reg 344 drivers/iio/health/max30102.c ret = regmap_write(data->regmap, MAX30102_REG_RED_LED_CONFIG, reg); reg 358 drivers/iio/health/max30102.c ret = max30102_get_current_idx(val, ®); reg 366 drivers/iio/health/max30102.c reg); reg 379 drivers/iio/health/max30102.c ret = max30102_get_current_idx(val, ®); reg 385 drivers/iio/health/max30102.c return regmap_write(data->regmap, MAX30102_REG_IR_LED_CONFIG, reg); reg 424 drivers/iio/health/max30102.c unsigned int reg; reg 426 drivers/iio/health/max30102.c ret = regmap_read(data->regmap, MAX30102_REG_TEMP_INTEGER, ®); reg 429 drivers/iio/health/max30102.c *val = reg << 4; reg 431 drivers/iio/health/max30102.c ret = regmap_read(data->regmap, MAX30102_REG_TEMP_FRACTION, ®); reg 435 drivers/iio/health/max30102.c *val |= reg & 0xf; reg 513 drivers/iio/health/max30102.c unsigned int reg; reg 561 drivers/iio/health/max30102.c ret = regmap_read(data->regmap, MAX30102_REG_PART_ID, ®); reg 564 drivers/iio/health/max30102.c if (reg != MAX30102_PART_NUMBER) reg 568 drivers/iio/health/max30102.c ret = regmap_read(data->regmap, MAX30102_REG_REV_ID, ®); reg 571 drivers/iio/health/max30102.c dev_dbg(&client->dev, "max3010x revision %02x\n", reg); reg 29 drivers/iio/imu/adis.c int adis_write_reg(struct adis *adis, unsigned int reg, reg 32 drivers/iio/imu/adis.c unsigned int page = reg / ADIS_PAGE_SIZE; reg 85 drivers/iio/imu/adis.c adis->tx[8] = ADIS_WRITE_REG(reg + 3); reg 87 drivers/iio/imu/adis.c adis->tx[6] = ADIS_WRITE_REG(reg + 2); reg 91 drivers/iio/imu/adis.c adis->tx[4] = ADIS_WRITE_REG(reg + 1); reg 95 drivers/iio/imu/adis.c adis->tx[2] = ADIS_WRITE_REG(reg); reg 111 drivers/iio/imu/adis.c reg, ret); reg 129 drivers/iio/imu/adis.c int adis_read_reg(struct adis *adis, unsigned int reg, reg 132 drivers/iio/imu/adis.c unsigned int page = reg / ADIS_PAGE_SIZE; reg 180 drivers/iio/imu/adis.c adis->tx[2] = ADIS_READ_REG(reg + 2); reg 185 drivers/iio/imu/adis.c adis->tx[4] = ADIS_READ_REG(reg); reg 198 drivers/iio/imu/adis.c reg, ret); reg 223 drivers/iio/imu/adis.c unsigned int reg, unsigned int writeval, unsigned int *readval) reg 231 drivers/iio/imu/adis.c ret = adis_read_reg_16(adis, reg, &val16); reg 236 drivers/iio/imu/adis.c return adis_write_reg_16(adis, reg, writeval); reg 30 drivers/iio/imu/adis16480.c #define ADIS16480_REG(page, reg) ((page) * ADIS16480_PAGE_SIZE + (reg)) reg 318 drivers/iio/imu/adis16480.c unsigned int t, reg; reg 336 drivers/iio/imu/adis16480.c reg = ADIS16495_REG_SYNC_SCALE; reg 339 drivers/iio/imu/adis16480.c reg = ADIS16480_REG_DEC_RATE; reg 348 drivers/iio/imu/adis16480.c return adis_write_reg_16(&st->adis, reg, t); reg 357 drivers/iio/imu/adis16480.c unsigned int reg; reg 360 drivers/iio/imu/adis16480.c reg = ADIS16495_REG_SYNC_SCALE; reg 362 drivers/iio/imu/adis16480.c reg = ADIS16480_REG_DEC_RATE; reg 364 drivers/iio/imu/adis16480.c ret = adis_read_reg_16(&st->adis, reg, &t); reg 425 drivers/iio/imu/adis16480.c unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; reg 433 drivers/iio/imu/adis16480.c return adis_write_reg_16(&st->adis, reg, bias); reg 436 drivers/iio/imu/adis16480.c return adis_write_reg_32(&st->adis, reg, bias); reg 447 drivers/iio/imu/adis16480.c unsigned int reg = adis16480_calibbias_regs[chan->scan_index]; reg 456 drivers/iio/imu/adis16480.c ret = adis_read_reg_16(&st->adis, reg, &val16); reg 462 drivers/iio/imu/adis16480.c ret = adis_read_reg_32(&st->adis, reg, &val32); reg 479 drivers/iio/imu/adis16480.c unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; reg 485 drivers/iio/imu/adis16480.c return adis_write_reg_16(&st->adis, reg, scale); reg 491 drivers/iio/imu/adis16480.c unsigned int reg = adis16480_calibscale_regs[chan->scan_index]; reg 496 drivers/iio/imu/adis16480.c ret = adis_read_reg_16(&st->adis, reg, &val16); reg 534 drivers/iio/imu/adis16480.c unsigned int enable_mask, offset, reg; reg 538 drivers/iio/imu/adis16480.c reg = ad16480_filter_data[chan->scan_index][0]; reg 542 drivers/iio/imu/adis16480.c ret = adis_read_reg_16(&st->adis, reg, &val); reg 558 drivers/iio/imu/adis16480.c unsigned int enable_mask, offset, reg; reg 564 drivers/iio/imu/adis16480.c reg = ad16480_filter_data[chan->scan_index][0]; reg 568 drivers/iio/imu/adis16480.c ret = adis_read_reg_16(&st->adis, reg, &val); reg 592 drivers/iio/imu/adis16480.c return adis_write_reg_16(&st->adis, reg, val); reg 349 drivers/iio/imu/bmi160/bmi160_core.c u8 reg; reg 354 drivers/iio/imu/bmi160/bmi160_core.c reg = bmi160_regs[t].data + (axis - IIO_MOD_X) * sizeof(sample); reg 356 drivers/iio/imu/bmi160/bmi160_core.c ret = regmap_bulk_read(data->regmap, reg, &sample, sizeof(sample)); reg 526 drivers/iio/imu/bmi160/bmi160_core.c static int bmi160_write_conf_reg(struct regmap *regmap, unsigned int reg, reg 533 drivers/iio/imu/bmi160/bmi160_core.c ret = regmap_read(regmap, reg, &val); reg 539 drivers/iio/imu/bmi160/bmi160_core.c ret = regmap_write(regmap, reg, val); reg 115 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c .reg = ®_set_6050, reg 123 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c .reg = ®_set_6500, reg 131 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c .reg = ®_set_6500, reg 139 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c .reg = ®_set_6050, reg 147 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c .reg = ®_set_6050, reg 155 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c .reg = ®_set_6500, reg 163 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c .reg = ®_set_6500, reg 171 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c .reg = ®_set_6500, reg 179 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c .reg = ®_set_icm20602, reg 196 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_read(st->map, st->reg->pwr_mgmt_1, &mgmt_1); reg 209 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_write(st->map, st->reg->pwr_mgmt_1, mgmt_1); reg 214 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_read(st->map, st->reg->pwr_mgmt_2, &d); reg 221 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_write(st->map, st->reg->pwr_mgmt_2, d); reg 232 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c st->reg->pwr_mgmt_1, mgmt_1); reg 247 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_write(st->map, st->reg->pwr_mgmt_1, 0); reg 256 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_write(st->map, st->reg->pwr_mgmt_1, reg 282 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_write(st->map, st->reg->lpf, val); reg 295 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_write(st->map, st->reg->accel_lpf, val); reg 321 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_write(st->map, st->reg->gyro_config, d); reg 330 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_write(st->map, st->reg->sample_rate_div, d); reg 335 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_write(st->map, st->reg->accl_config, d); reg 339 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_write(st->map, st->reg->int_pin_cfg, st->irq_mask); reg 360 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c static int inv_mpu6050_sensor_set(struct inv_mpu6050_state *st, int reg, reg 367 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_bulk_write(st->map, reg + ind, (u8 *)&d, 2); reg 374 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c static int inv_mpu6050_sensor_show(struct inv_mpu6050_state *st, int reg, reg 381 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_bulk_read(st->map, reg + ind, (u8 *)&d, 2); reg 407 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c ret = inv_mpu6050_sensor_show(st, st->reg->raw_gyro, reg 419 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c ret = inv_mpu6050_sensor_show(st, st->reg->raw_accl, reg 429 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c ret = inv_mpu6050_sensor_show(st, st->reg->temperature, reg 501 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c ret = inv_mpu6050_sensor_show(st, st->reg->gyro_offset, reg 507 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c ret = inv_mpu6050_sensor_show(st, st->reg->accl_offset, reg 528 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_write(st->map, st->reg->gyro_config, d); reg 566 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_write(st->map, st->reg->accl_config, d); reg 616 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c st->reg->gyro_offset, reg 621 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c st->reg->accl_offset, reg 714 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_write(st->map, st->reg->sample_rate_div, d); reg 979 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c st->reg = hw_info[st->chip_type].reg; reg 1006 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c result = regmap_write(st->map, st->reg->pwr_mgmt_1, reg 32 drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c ret = regmap_write(st->map, st->reg->int_pin_cfg, reg 49 drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c regmap_write(st->map, st->reg->int_pin_cfg, st->irq_mask); reg 109 drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h const struct inv_mpu6050_reg_map *reg; reg 140 drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h const struct inv_mpu6050_reg_map *reg; reg 348 drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val); reg 103 drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c result = regmap_write(st->map, st->reg->int_enable, 0); reg 110 drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c result = regmap_write(st->map, st->reg->fifo_en, 0); reg 114 drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c result = regmap_write(st->map, st->reg->user_ctrl, reg 121 drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c result = regmap_write(st->map, st->reg->user_ctrl, d); reg 128 drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c result = regmap_write(st->map, st->reg->int_enable, reg 135 drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c result = regmap_write(st->map, st->reg->user_ctrl, d); reg 144 drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c result = regmap_write(st->map, st->reg->fifo_en, d); reg 152 drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c result = regmap_write(st->map, st->reg->int_enable, reg 177 drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c result = regmap_read(st->map, st->reg->int_status, &int_status); reg 206 drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c result = regmap_bulk_read(st->map, st->reg->fifo_count_h, data, reg 227 drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c result = regmap_bulk_read(st->map, st->reg->fifo_r_w, reg 26 drivers/iio/imu/inv_mpu6050/inv_mpu_spi.c if (st->reg->i2c_if) { reg 27 drivers/iio/imu/inv_mpu6050/inv_mpu_spi.c ret = regmap_write(st->map, st->reg->i2c_if, reg 31 drivers/iio/imu/inv_mpu6050/inv_mpu_spi.c ret = regmap_write(st->map, st->reg->user_ctrl, reg 63 drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c result = regmap_write(st->map, st->reg->fifo_en, 0); reg 67 drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c result = regmap_write(st->map, st->reg->int_enable, 0); reg 71 drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c result = regmap_write(st->map, st->reg->user_ctrl, reg 774 drivers/iio/imu/kmx61.c u8 reg = base + offset * 2; reg 776 drivers/iio/imu/kmx61.c ret = i2c_smbus_read_word_data(data->client, reg); reg 778 drivers/iio/imu/kmx61.c dev_err(&data->client->dev, "failed to read reg at %x\n", reg); reg 90 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h struct st_lsm6dsx_reg reg; reg 101 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h struct st_lsm6dsx_reg reg; reg 195 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h struct st_lsm6dsx_reg reg; reg 114 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 126 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 140 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 151 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 187 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 199 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 213 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 224 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 301 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 313 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 327 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 338 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 424 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 436 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 450 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 461 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 541 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 553 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 567 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 578 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 673 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 685 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 699 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 710 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 782 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 794 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 808 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 819 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .reg = { reg 961 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c fs_table->reg.mask); reg 962 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c err = st_lsm6dsx_update_bits_locked(sensor->hw, fs_table->reg.addr, reg 963 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c fs_table->reg.mask, data); reg 1012 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c const struct st_lsm6dsx_reg *reg; reg 1053 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c reg = &hw->settings->odr_table[ref_sensor->id].reg; reg 1054 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask); reg 1055 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c return st_lsm6dsx_update_bits_locked(hw, reg->addr, reg->mask, data); reg 50 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c .reg = { reg 71 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c .reg = { reg 350 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c settings->odr_table.reg.addr, reg 351 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c settings->odr_table.reg.mask, reg 410 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c settings->odr_table.reg.addr, reg 411 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c settings->odr_table.reg.mask, 0); reg 416 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c if (settings->pwr_table.reg.addr) { reg 422 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c settings->pwr_table.reg.addr, reg 423 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c settings->pwr_table.reg.mask, val); reg 325 drivers/iio/industrialio-core.c unsigned reg, val; reg 335 drivers/iio/industrialio-core.c ret = sscanf(buf, "%i %i", ®, &val); reg 339 drivers/iio/industrialio-core.c indio_dev->cached_reg_addr = reg; reg 342 drivers/iio/industrialio-core.c indio_dev->cached_reg_addr = reg; reg 343 drivers/iio/industrialio-core.c ret = indio_dev->info->debugfs_reg_access(indio_dev, reg, reg 96 drivers/iio/light/adjd_s311.c static int adjd_s311_read_data(struct iio_dev *indio_dev, u8 reg, int *val) reg 104 drivers/iio/light/adjd_s311.c ret = i2c_smbus_read_word_data(data->client, reg); reg 573 drivers/iio/light/apds9960.c u8 *reg) reg 579 drivers/iio/light/apds9960.c *reg = APDS9960_REG_PIHT; reg 582 drivers/iio/light/apds9960.c *reg = APDS9960_REG_AIHTL; reg 591 drivers/iio/light/apds9960.c *reg = APDS9960_REG_PILT; reg 594 drivers/iio/light/apds9960.c *reg = APDS9960_REG_AILTL; reg 614 drivers/iio/light/apds9960.c u8 reg; reg 622 drivers/iio/light/apds9960.c ret = apds9960_get_thres_reg(chan, dir, ®); reg 627 drivers/iio/light/apds9960.c ret = regmap_read(data->regmap, reg, val); reg 631 drivers/iio/light/apds9960.c ret = regmap_bulk_read(data->regmap, reg, &buf, 2); reg 650 drivers/iio/light/apds9960.c u8 reg; reg 658 drivers/iio/light/apds9960.c ret = apds9960_get_thres_reg(chan, dir, ®); reg 665 drivers/iio/light/apds9960.c ret = regmap_write(data->regmap, reg, val); reg 672 drivers/iio/light/apds9960.c ret = regmap_bulk_write(data->regmap, reg, &buf, 2); reg 43 drivers/iio/light/bh1780.c static int bh1780_write(struct bh1780_data *bh1780, u8 reg, u8 val) reg 46 drivers/iio/light/bh1780.c BH1780_CMD_BIT | reg, reg 52 drivers/iio/light/bh1780.c ret, reg); reg 56 drivers/iio/light/bh1780.c static int bh1780_read(struct bh1780_data *bh1780, u8 reg) reg 59 drivers/iio/light/bh1780.c BH1780_CMD_BIT | reg); reg 64 drivers/iio/light/bh1780.c ret, reg); reg 68 drivers/iio/light/bh1780.c static int bh1780_read_word(struct bh1780_data *bh1780, u8 reg) reg 71 drivers/iio/light/bh1780.c BH1780_CMD_BIT | reg); reg 76 drivers/iio/light/bh1780.c ret, reg); reg 81 drivers/iio/light/bh1780.c unsigned int reg, unsigned int writeval, reg 88 drivers/iio/light/bh1780.c return bh1780_write(bh1780, (u8)reg, (u8)writeval); reg 90 drivers/iio/light/bh1780.c ret = bh1780_read(bh1780, (u8)reg); reg 275 drivers/iio/light/gp2ap020a00f.c static bool gp2ap020a00f_is_volatile_reg(struct device *dev, unsigned int reg) reg 277 drivers/iio/light/gp2ap020a00f.c switch (reg) { reg 630 drivers/iio/light/isl29018.c static bool isl29018_is_volatile_reg(struct device *dev, unsigned int reg) reg 632 drivers/iio/light/isl29018.c switch (reg) { reg 548 drivers/iio/light/isl29028.c static bool isl29028_is_volatile_reg(struct device *dev, unsigned int reg) reg 550 drivers/iio/light/isl29028.c switch (reg) { reg 289 drivers/iio/light/jsa1212.c static bool jsa1212_is_volatile_reg(struct device *dev, unsigned int reg) reg 291 drivers/iio/light/jsa1212.c switch (reg) { reg 66 drivers/iio/light/lm3533-als.c u8 reg; reg 71 drivers/iio/light/lm3533-als.c reg = LM3533_REG_ALS_READ_ADC_AVERAGE; reg 73 drivers/iio/light/lm3533-als.c reg = LM3533_REG_ALS_READ_ADC_RAW; reg 75 drivers/iio/light/lm3533-als.c ret = lm3533_read(als->lm3533, reg, &val); reg 133 drivers/iio/light/lm3533-als.c u8 reg; reg 142 drivers/iio/light/lm3533-als.c reg = lm3533_als_get_target_reg(channel, zone); reg 143 drivers/iio/light/lm3533-als.c ret = lm3533_read(als->lm3533, reg, val); reg 154 drivers/iio/light/lm3533-als.c u8 reg; reg 163 drivers/iio/light/lm3533-als.c reg = lm3533_als_get_target_reg(channel, zone); reg 164 drivers/iio/light/lm3533-als.c ret = lm3533_write(als->lm3533, reg, val); reg 322 drivers/iio/light/lm3533-als.c u8 reg; reg 328 drivers/iio/light/lm3533-als.c reg = lm3533_als_get_threshold_reg(nr, raising); reg 329 drivers/iio/light/lm3533-als.c ret = lm3533_read(als->lm3533, reg, val); reg 341 drivers/iio/light/lm3533-als.c u8 reg, reg2; reg 347 drivers/iio/light/lm3533-als.c reg = lm3533_als_get_threshold_reg(nr, raising); reg 366 drivers/iio/light/lm3533-als.c ret = lm3533_write(als->lm3533, reg, val); reg 1349 drivers/iio/light/ltr501.c static bool ltr501_is_volatile_reg(struct device *dev, unsigned int reg) reg 1351 drivers/iio/light/ltr501.c switch (reg) { reg 407 drivers/iio/light/max44000.c static bool max44000_readable_reg(struct device *dev, unsigned int reg) reg 409 drivers/iio/light/max44000.c switch (reg) { reg 432 drivers/iio/light/max44000.c static bool max44000_writeable_reg(struct device *dev, unsigned int reg) reg 434 drivers/iio/light/max44000.c switch (reg) { reg 453 drivers/iio/light/max44000.c static bool max44000_volatile_reg(struct device *dev, unsigned int reg) reg 455 drivers/iio/light/max44000.c switch (reg) { reg 466 drivers/iio/light/max44000.c static bool max44000_precious_reg(struct device *dev, unsigned int reg) reg 468 drivers/iio/light/max44000.c return reg == MAX44000_REG_STATUS; reg 527 drivers/iio/light/max44000.c int ret, reg; reg 575 drivers/iio/light/max44000.c reg = MAX44000_CFG_TRIM | MAX44000_CFG_MODE_ALS_PRX; reg 576 drivers/iio/light/max44000.c ret = regmap_write(data->regmap, MAX44000_REG_CFG_MAIN, reg); reg 583 drivers/iio/light/max44000.c ret = regmap_read(data->regmap, MAX44000_REG_STATUS, ®); reg 346 drivers/iio/light/max44009.c int reg, threshold; reg 355 drivers/iio/light/max44009.c reg = max44009_get_thr_reg(dir); reg 356 drivers/iio/light/max44009.c if (reg < 0) reg 357 drivers/iio/light/max44009.c return reg; reg 359 drivers/iio/light/max44009.c return i2c_smbus_write_byte_data(data->client, reg, threshold); reg 366 drivers/iio/light/max44009.c int byte, reg; reg 369 drivers/iio/light/max44009.c reg = max44009_get_thr_reg(dir); reg 370 drivers/iio/light/max44009.c if (reg < 0) reg 371 drivers/iio/light/max44009.c return reg; reg 373 drivers/iio/light/max44009.c byte = i2c_smbus_read_byte_data(data->client, reg); reg 167 drivers/iio/light/noa1305.c static bool noa1305_writable_reg(struct device *dev, unsigned int reg) reg 169 drivers/iio/light/noa1305.c switch (reg) { reg 179 drivers/iio/light/opt3001.c static void opt3001_set_mode(struct opt3001 *opt, u16 *reg, u16 mode) reg 181 drivers/iio/light/opt3001.c *reg &= ~OPT3001_CONFIGURATION_M_MASK; reg 182 drivers/iio/light/opt3001.c *reg |= mode; reg 227 drivers/iio/light/opt3001.c u16 reg; reg 262 drivers/iio/light/opt3001.c reg = ret; reg 263 drivers/iio/light/opt3001.c opt3001_set_mode(opt, ®, OPT3001_CONFIGURATION_M_SINGLE); reg 266 drivers/iio/light/opt3001.c reg); reg 357 drivers/iio/light/opt3001.c u16 reg; reg 366 drivers/iio/light/opt3001.c reg = ret; reg 370 drivers/iio/light/opt3001.c reg &= ~OPT3001_CONFIGURATION_CT; reg 374 drivers/iio/light/opt3001.c reg |= OPT3001_CONFIGURATION_CT; reg 382 drivers/iio/light/opt3001.c reg); reg 480 drivers/iio/light/opt3001.c u16 reg; reg 500 drivers/iio/light/opt3001.c reg = OPT3001_HIGH_LIMIT; reg 505 drivers/iio/light/opt3001.c reg = OPT3001_LOW_LIMIT; reg 514 drivers/iio/light/opt3001.c ret = i2c_smbus_write_word_swapped(opt->client, reg, value); reg 516 drivers/iio/light/opt3001.c dev_err(opt->dev, "failed to write register %02x\n", reg); reg 542 drivers/iio/light/opt3001.c u16 reg; reg 562 drivers/iio/light/opt3001.c reg = ret; reg 563 drivers/iio/light/opt3001.c opt3001_set_mode(opt, ®, mode); reg 566 drivers/iio/light/opt3001.c reg); reg 623 drivers/iio/light/opt3001.c u16 reg; reg 632 drivers/iio/light/opt3001.c reg = ret; reg 635 drivers/iio/light/opt3001.c reg &= ~OPT3001_CONFIGURATION_RN_MASK; reg 636 drivers/iio/light/opt3001.c reg |= OPT3001_CONFIGURATION_RN_AUTO; reg 639 drivers/iio/light/opt3001.c if (reg & OPT3001_CONFIGURATION_CT) reg 645 drivers/iio/light/opt3001.c opt3001_set_mode(opt, ®, OPT3001_CONFIGURATION_M_SHUTDOWN); reg 648 drivers/iio/light/opt3001.c reg |= OPT3001_CONFIGURATION_L; reg 649 drivers/iio/light/opt3001.c reg &= ~OPT3001_CONFIGURATION_POL; reg 650 drivers/iio/light/opt3001.c reg &= ~OPT3001_CONFIGURATION_ME; reg 651 drivers/iio/light/opt3001.c reg &= ~OPT3001_CONFIGURATION_FC_MASK; reg 654 drivers/iio/light/opt3001.c reg); reg 802 drivers/iio/light/opt3001.c u16 reg; reg 814 drivers/iio/light/opt3001.c reg = ret; reg 815 drivers/iio/light/opt3001.c opt3001_set_mode(opt, ®, OPT3001_CONFIGURATION_M_SHUTDOWN); reg 818 drivers/iio/light/opt3001.c reg); reg 77 drivers/iio/light/pa12203001.c u8 reg; reg 318 drivers/iio/light/pa12203001.c ret = regmap_write(data->map, regvals[i].reg, regvals[i].val); reg 124 drivers/iio/light/rpr0521.c u8 reg; reg 131 drivers/iio/light/rpr0521.c .reg = RPR0521_REG_PXS_CTRL, reg 138 drivers/iio/light/rpr0521.c .reg = RPR0521_REG_ALS_CTRL, reg 145 drivers/iio/light/rpr0521.c .reg = RPR0521_REG_ALS_CTRL, reg 391 drivers/iio/light/rpr0521.c int reg; reg 393 drivers/iio/light/rpr0521.c ret = regmap_read(data->regmap, RPR0521_REG_INTERRUPT, ®); reg 396 drivers/iio/light/rpr0521.c if (reg & reg 581 drivers/iio/light/rpr0521.c int ret, reg, idx; reg 583 drivers/iio/light/rpr0521.c ret = regmap_read(data->regmap, rpr0521_gain[chan].reg, ®); reg 587 drivers/iio/light/rpr0521.c idx = (rpr0521_gain[chan].mask & reg) >> rpr0521_gain[chan].shift; reg 610 drivers/iio/light/rpr0521.c return regmap_update_bits(data->regmap, rpr0521_gain[chan].reg, reg 619 drivers/iio/light/rpr0521.c int reg, ret; reg 621 drivers/iio/light/rpr0521.c ret = regmap_read(data->regmap, RPR0521_REG_MODE_CTRL, ®); reg 625 drivers/iio/light/rpr0521.c reg &= RPR0521_MODE_MEAS_TIME_MASK; reg 626 drivers/iio/light/rpr0521.c if (reg >= ARRAY_SIZE(rpr0521_samp_freq_i)) reg 631 drivers/iio/light/rpr0521.c *val = rpr0521_samp_freq_i[reg].als_hz; reg 632 drivers/iio/light/rpr0521.c *val2 = rpr0521_samp_freq_i[reg].als_uhz; reg 636 drivers/iio/light/rpr0521.c *val = rpr0521_samp_freq_i[reg].pxs_hz; reg 637 drivers/iio/light/rpr0521.c *val2 = rpr0521_samp_freq_i[reg].pxs_uhz; reg 903 drivers/iio/light/rpr0521.c static bool rpr0521_is_volatile_reg(struct device *dev, unsigned int reg) reg 905 drivers/iio/light/rpr0521.c switch (reg) { reg 508 drivers/iio/light/si1145.c u8 reg = 0, mux; reg 519 drivers/iio/light/si1145.c reg |= SI1145_CHLIST_EN_ALSVIS; reg 522 drivers/iio/light/si1145.c reg |= SI1145_CHLIST_EN_ALSIR; reg 525 drivers/iio/light/si1145.c reg |= SI1145_CHLIST_EN_PS1; reg 528 drivers/iio/light/si1145.c reg |= SI1145_CHLIST_EN_PS2; reg 531 drivers/iio/light/si1145.c reg |= SI1145_CHLIST_EN_PS3; reg 536 drivers/iio/light/si1145.c reg |= SI1145_CHLIST_EN_UV; reg 539 drivers/iio/light/si1145.c reg |= SI1145_CHLIST_EN_AUX; reg 555 drivers/iio/light/si1145.c ret = si1145_param_set(data, SI1145_PARAM_CHLIST, reg); reg 626 drivers/iio/light/si1145.c u8 reg; reg 664 drivers/iio/light/si1145.c reg = SI1145_PARAM_PS_ADC_GAIN; reg 668 drivers/iio/light/si1145.c reg = SI1145_PARAM_ALSIR_ADC_GAIN; reg 670 drivers/iio/light/si1145.c reg = SI1145_PARAM_ALSVIS_ADC_GAIN; reg 684 drivers/iio/light/si1145.c ret = si1145_param_query(data, reg); reg 198 drivers/iio/light/stk3310.c u8 reg; reg 208 drivers/iio/light/stk3310.c reg = STK3310_REG_THDH_PS; reg 210 drivers/iio/light/stk3310.c reg = STK3310_REG_THDL_PS; reg 215 drivers/iio/light/stk3310.c ret = regmap_bulk_read(data->regmap, reg, &buf, 2); reg 233 drivers/iio/light/stk3310.c u8 reg; reg 248 drivers/iio/light/stk3310.c reg = STK3310_REG_THDH_PS; reg 250 drivers/iio/light/stk3310.c reg = STK3310_REG_THDL_PS; reg 255 drivers/iio/light/stk3310.c ret = regmap_bulk_write(data->regmap, reg, &buf, 2); reg 305 drivers/iio/light/stk3310.c u8 reg; reg 318 drivers/iio/light/stk3310.c reg = STK3310_REG_ALS_DATA_MSB; reg 320 drivers/iio/light/stk3310.c reg = STK3310_REG_PS_DATA_MSB; reg 323 drivers/iio/light/stk3310.c ret = regmap_bulk_read(data->regmap, reg, &buf, 2); reg 476 drivers/iio/light/stk3310.c static bool stk3310_is_volatile_reg(struct device *dev, unsigned int reg) reg 478 drivers/iio/light/stk3310.c switch (reg) { reg 190 drivers/iio/light/tsl2583.c int reg = TSL2583_CMD_REG | (TSL2583_ALS_CHAN0LO + i); reg 192 drivers/iio/light/tsl2583.c ret = i2c_smbus_read_byte_data(chip->client, reg); reg 195 drivers/iio/light/tsl2583.c __func__, reg); reg 779 drivers/iio/light/tsl2772.c int reg = TSL2772_CMD_REG + i; reg 781 drivers/iio/light/tsl2772.c ret = i2c_smbus_write_byte_data(chip->client, reg, reg 786 drivers/iio/light/tsl2772.c __func__, reg, ret); reg 157 drivers/iio/light/us5182d.c u8 reg; reg 742 drivers/iio/light/us5182d.c us5182d_regvals[i].reg, reg 68 drivers/iio/light/vcnl4000.c u8 reg; reg 166 drivers/iio/light/vcnl4000.c data->vcnl4200_al.reg = VCNL4200_AL_DATA; reg 167 drivers/iio/light/vcnl4000.c data->vcnl4200_ps.reg = VCNL4200_PS_DATA; reg 254 drivers/iio/light/vcnl4000.c ret = i2c_smbus_read_word_data(data->client, chan->reg); reg 71 drivers/iio/light/vcnl4035.c int reg; reg 73 drivers/iio/light/vcnl4035.c ret = regmap_read(data->regmap, VCNL4035_INT_FLAG, ®); reg 77 drivers/iio/light/vcnl4035.c return !!(reg & reg 178 drivers/iio/light/vcnl4035.c unsigned int reg; reg 189 drivers/iio/light/vcnl4035.c reg = VCNL4035_ALS_DATA; reg 191 drivers/iio/light/vcnl4035.c reg = VCNL4035_WHITE_DATA; reg 192 drivers/iio/light/vcnl4035.c ret = regmap_read(data->regmap, reg, &raw_data); reg 482 drivers/iio/light/vcnl4035.c static bool vcnl4035_is_volatile_reg(struct device *dev, unsigned int reg) reg 484 drivers/iio/light/vcnl4035.c switch (reg) { reg 182 drivers/iio/light/zopt2201.c static int zopt2201_read(struct zopt2201_data *data, u8 reg) reg 190 drivers/iio/light/zopt2201.c ret = zopt2201_enable_mode(data, reg == ZOPT2201_UVB_DATA); reg 213 drivers/iio/light/zopt2201.c ret = i2c_smbus_read_i2c_block_data(client, reg, sizeof(buf), buf); reg 193 drivers/iio/magnetometer/ak8974.c static int ak8974_get_u16_val(struct ak8974 *ak8974, u8 reg, u16 *val) reg 198 drivers/iio/magnetometer/ak8974.c ret = regmap_bulk_read(ak8974->map, reg, &bulk, 2); reg 206 drivers/iio/magnetometer/ak8974.c static int ak8974_set_u16_val(struct ak8974 *ak8974, u8 reg, u16 val) reg 210 drivers/iio/magnetometer/ak8974.c return regmap_bulk_write(ak8974->map, reg, &bulk, 2); reg 449 drivers/iio/magnetometer/ak8974.c static void ak8974_read_calib_data(struct ak8974 *ak8974, unsigned int reg, reg 452 drivers/iio/magnetometer/ak8974.c int ret = regmap_bulk_read(ak8974->map, reg, tab, tab_size); reg 457 drivers/iio/magnetometer/ak8974.c reg, reg + tab_size - 1, ret); reg 664 drivers/iio/magnetometer/ak8974.c static bool ak8974_writeable_reg(struct device *dev, unsigned int reg) reg 670 drivers/iio/magnetometer/ak8974.c switch (reg) { reg 705 drivers/iio/magnetometer/ak8974.c static bool ak8974_precious_reg(struct device *dev, unsigned int reg) reg 707 drivers/iio/magnetometer/ak8974.c return reg == AK8974_INT_CLEAR; reg 179 drivers/iio/magnetometer/bmc150_magn.c static bool bmc150_magn_is_writeable_reg(struct device *dev, unsigned int reg) reg 181 drivers/iio/magnetometer/bmc150_magn.c switch (reg) { reg 196 drivers/iio/magnetometer/bmc150_magn.c static bool bmc150_magn_is_volatile_reg(struct device *dev, unsigned int reg) reg 198 drivers/iio/magnetometer/bmc150_magn.c switch (reg) { reg 214 drivers/iio/magnetometer/mag3110.c int reg; reg 216 drivers/iio/magnetometer/mag3110.c reg = i2c_smbus_read_byte_data(data->client, MAG3110_CTRL_REG1); reg 217 drivers/iio/magnetometer/mag3110.c if (reg < 0) reg 218 drivers/iio/magnetometer/mag3110.c return reg; reg 220 drivers/iio/magnetometer/mag3110.c return reg & MAG3110_CTRL_AC; reg 223 drivers/iio/magnetometer/mag3110.c static int mag3110_change_config(struct mag3110_data *data, u8 reg, u8 val) reg 251 drivers/iio/magnetometer/mag3110.c ret = i2c_smbus_write_byte_data(data->client, reg, val); reg 357 drivers/iio/magnetometer/mmc35240.c unsigned int reg; reg 377 drivers/iio/magnetometer/mmc35240.c ret = regmap_read(data->regmap, MMC35240_REG_CTRL1, ®); reg 382 drivers/iio/magnetometer/mmc35240.c i = (reg & MMC35240_CTRL1_BW_MASK) >> MMC35240_CTRL1_BW_SHIFT; reg 423 drivers/iio/magnetometer/mmc35240.c static bool mmc35240_is_writeable_reg(struct device *dev, unsigned int reg) reg 425 drivers/iio/magnetometer/mmc35240.c switch (reg) { reg 434 drivers/iio/magnetometer/mmc35240.c static bool mmc35240_is_readable_reg(struct device *dev, unsigned int reg) reg 436 drivers/iio/magnetometer/mmc35240.c switch (reg) { reg 451 drivers/iio/magnetometer/mmc35240.c static bool mmc35240_is_volatile_reg(struct device *dev, unsigned int reg) reg 453 drivers/iio/magnetometer/mmc35240.c switch (reg) { reg 62 drivers/iio/potentiometer/ad5272.c static int ad5272_write(struct ad5272_data *data, int reg, int val) reg 66 drivers/iio/potentiometer/ad5272.c data->buf[0] = (reg << 2) | ((val >> 8) & 0x3); reg 75 drivers/iio/potentiometer/ad5272.c static int ad5272_read(struct ad5272_data *data, int reg, int *val) reg 79 drivers/iio/potentiometer/ad5272.c data->buf[0] = reg << 2; reg 209 drivers/iio/potentiostat/lmp91000.c unsigned int reg, val; reg 224 drivers/iio/potentiostat/lmp91000.c reg = i << LMP91000_REG_TIACN_GAIN_SHIFT; reg 244 drivers/iio/potentiostat/lmp91000.c reg |= i; reg 256 drivers/iio/potentiostat/lmp91000.c regmap_write(data->regmap, LMP91000_REG_TIACN, reg); reg 8 drivers/iio/pressure/bmp280-regmap.c static bool bmp180_is_writeable_reg(struct device *dev, unsigned int reg) reg 10 drivers/iio/pressure/bmp280-regmap.c switch (reg) { reg 19 drivers/iio/pressure/bmp280-regmap.c static bool bmp180_is_volatile_reg(struct device *dev, unsigned int reg) reg 21 drivers/iio/pressure/bmp280-regmap.c switch (reg) { reg 44 drivers/iio/pressure/bmp280-regmap.c static bool bmp280_is_writeable_reg(struct device *dev, unsigned int reg) reg 46 drivers/iio/pressure/bmp280-regmap.c switch (reg) { reg 57 drivers/iio/pressure/bmp280-regmap.c static bool bmp280_is_volatile_reg(struct device *dev, unsigned int reg) reg 59 drivers/iio/pressure/bmp280-regmap.c switch (reg) { reg 31 drivers/iio/pressure/bmp280-spi.c static int bmp280_regmap_spi_read(void *context, const void *reg, reg 37 drivers/iio/pressure/bmp280-spi.c return spi_write_then_read(spi, reg, reg_size, val, val_size); reg 378 drivers/iio/pressure/dps310.c static bool dps310_is_writeable_reg(struct device *dev, unsigned int reg) reg 380 drivers/iio/pressure/dps310.c switch (reg) { reg 396 drivers/iio/pressure/dps310.c static bool dps310_is_volatile_reg(struct device *dev, unsigned int reg) reg 398 drivers/iio/pressure/dps310.c switch (reg) { reg 688 drivers/iio/pressure/dps310.c int reg; reg 690 drivers/iio/pressure/dps310.c rc = regmap_read(data->regmap, 0x32, ®); reg 698 drivers/iio/pressure/dps310.c if (reg & BIT(1)) reg 60 drivers/iio/pressure/hp03.c static bool hp03_is_writeable_reg(struct device *dev, unsigned int reg) reg 65 drivers/iio/pressure/hp03.c static bool hp03_is_volatile_reg(struct device *dev, unsigned int reg) reg 81 drivers/iio/pressure/hp03.c static int hp03_get_temp_pressure(struct hp03_priv *priv, const u8 reg) reg 85 drivers/iio/pressure/hp03.c ret = i2c_smbus_write_byte_data(priv->client, HP03_ADC_WRITE_REG, reg); reg 80 drivers/iio/pressure/hp206c.c static inline int hp206c_read_reg(struct i2c_client *client, u8 reg) reg 82 drivers/iio/pressure/hp206c.c return i2c_smbus_read_byte_data(client, HP206C_CMD_READ_REG | reg); reg 85 drivers/iio/pressure/hp206c.c static inline int hp206c_write_reg(struct i2c_client *client, u8 reg, u8 val) reg 88 drivers/iio/pressure/hp206c.c HP206C_CMD_WRITE_REG | reg, val); reg 145 drivers/iio/pressure/zpa2326.c bool zpa2326_isreg_writeable(struct device *dev, unsigned int reg) reg 147 drivers/iio/pressure/zpa2326.c switch (reg) { reg 166 drivers/iio/pressure/zpa2326.c bool zpa2326_isreg_readable(struct device *dev, unsigned int reg) reg 168 drivers/iio/pressure/zpa2326.c switch (reg) { reg 195 drivers/iio/pressure/zpa2326.c bool zpa2326_isreg_precious(struct device *dev, unsigned int reg) reg 197 drivers/iio/pressure/zpa2326.c switch (reg) { reg 47 drivers/iio/pressure/zpa2326.h bool zpa2326_isreg_writeable(struct device *dev, unsigned int reg); reg 48 drivers/iio/pressure/zpa2326.h bool zpa2326_isreg_readable(struct device *dev, unsigned int reg); reg 49 drivers/iio/pressure/zpa2326.h bool zpa2326_isreg_precious(struct device *dev, unsigned int reg); reg 85 drivers/iio/proximity/as3935.c static int as3935_read(struct as3935_state *st, unsigned int reg, int *val) reg 90 drivers/iio/proximity/as3935.c cmd = (AS3935_READ_DATA | AS3935_ADDRESS(reg)) >> 8; reg 100 drivers/iio/proximity/as3935.c unsigned int reg, reg 105 drivers/iio/proximity/as3935.c buf[0] = AS3935_ADDRESS(reg) >> 8; reg 201 drivers/iio/proximity/isl29501.c const struct isl29501_register_desc *reg = &isl29501_registers[name]; reg 206 drivers/iio/proximity/isl29501.c if (reg->msb) { reg 207 drivers/iio/proximity/isl29501.c ret = i2c_smbus_read_byte_data(isl29501->client, reg->msb); reg 213 drivers/iio/proximity/isl29501.c if (reg->lsb) { reg 214 drivers/iio/proximity/isl29501.c ret = i2c_smbus_read_byte_data(isl29501->client, reg->lsb); reg 234 drivers/iio/proximity/isl29501.c const struct isl29501_register_desc *reg = &isl29501_registers[name]; reg 237 drivers/iio/proximity/isl29501.c if (!reg->msb && value > U8_MAX) reg 244 drivers/iio/proximity/isl29501.c if (reg->msb) { reg 246 drivers/iio/proximity/isl29501.c reg->msb, value >> 8); reg 251 drivers/iio/proximity/isl29501.c ret = i2c_smbus_write_byte_data(isl29501->client, reg->lsb, value); reg 264 drivers/iio/proximity/isl29501.c enum isl29501_register_name reg = private; reg 268 drivers/iio/proximity/isl29501.c switch (reg) { reg 271 drivers/iio/proximity/isl29501.c ret = isl29501_register_read(isl29501, reg, &gain); reg 285 drivers/iio/proximity/isl29501.c ret = isl29501_register_read(isl29501, reg, &coeff); reg 299 drivers/iio/proximity/isl29501.c enum isl29501_register_name reg, reg 304 drivers/iio/proximity/isl29501.c switch (reg) { reg 329 drivers/iio/proximity/isl29501.c enum isl29501_register_name reg; reg 333 drivers/iio/proximity/isl29501.c reg = REG_CALIB_PHASE_TEMP_A; reg 336 drivers/iio/proximity/isl29501.c reg = REG_CALIB_PHASE_TEMP_B; reg 339 drivers/iio/proximity/isl29501.c reg = REG_CALIB_PHASE_LIGHT_A; reg 342 drivers/iio/proximity/isl29501.c reg = REG_CALIB_PHASE_LIGHT_B; reg 348 drivers/iio/proximity/isl29501.c return isl29501_register_write(isl29501, reg, val); reg 386 drivers/iio/proximity/isl29501.c enum isl29501_register_name reg = private; reg 396 drivers/iio/proximity/isl29501.c switch (reg) { reg 401 drivers/iio/proximity/isl29501.c ret = isl29501_register_write(isl29501, reg, val); reg 415 drivers/iio/proximity/isl29501.c ret = isl29501_set_shadow_coeff(isl29501, reg, val); reg 43 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c int (*xfer)(struct lidar_data *data, u8 reg, u8 *val, int len); reg 64 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c static int lidar_i2c_xfer(struct lidar_data *data, u8 reg, u8 *val, int len) reg 73 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c msg[0].buf = (char *) ® reg 85 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c static int lidar_smbus_xfer(struct lidar_data *data, u8 reg, u8 *val, int len) reg 96 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c ret = i2c_smbus_write_byte(client, reg++); reg 114 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c static int lidar_read_byte(struct lidar_data *data, u8 reg) reg 119 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c ret = data->xfer(data, reg, &val, 1); reg 137 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c static int lidar_read_measurement(struct lidar_data *data, u16 *reg) reg 141 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c (u8 *) reg, 2); reg 144 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c *reg = be16_to_cpu(*reg); reg 149 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c static int lidar_get_measurement(struct lidar_data *data, u16 *reg) reg 173 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c *reg = 0; reg 180 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c ret = lidar_read_measurement(data, reg); reg 200 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c u16 reg; reg 205 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c ret = lidar_get_measurement(data, ®); reg 207 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c *val = reg; reg 68 drivers/iio/proximity/rfd77402.c u8 reg; reg 237 drivers/iio/proximity/rfd77402.c rf77402_tof_config[i].reg, reg 205 drivers/iio/proximity/sx9500.c unsigned int reg, unsigned int bitmask) reg 212 drivers/iio/proximity/sx9500.c return regmap_update_bits(data->regmap, reg, bitmask, bitmask); reg 216 drivers/iio/proximity/sx9500.c unsigned int reg, unsigned int bitmask) reg 223 drivers/iio/proximity/sx9500.c return regmap_update_bits(data->regmap, reg, bitmask, 0); reg 735 drivers/iio/proximity/sx9500.c u8 reg; reg 741 drivers/iio/proximity/sx9500.c .reg = SX9500_REG_PROX_CTRL1, reg 746 drivers/iio/proximity/sx9500.c .reg = SX9500_REG_PROX_CTRL2, reg 751 drivers/iio/proximity/sx9500.c .reg = SX9500_REG_PROX_CTRL3, reg 756 drivers/iio/proximity/sx9500.c .reg = SX9500_REG_PROX_CTRL4, reg 761 drivers/iio/proximity/sx9500.c .reg = SX9500_REG_PROX_CTRL5, reg 769 drivers/iio/proximity/sx9500.c .reg = SX9500_REG_PROX_CTRL6, reg 774 drivers/iio/proximity/sx9500.c .reg = SX9500_REG_PROX_CTRL7, reg 783 drivers/iio/proximity/sx9500.c .reg = SX9500_REG_PROX_CTRL8, reg 788 drivers/iio/proximity/sx9500.c .reg = SX9500_REG_PROX_CTRL0, reg 854 drivers/iio/proximity/sx9500.c sx9500_default_regs[i].reg, reg 68 drivers/iio/temperature/max31856.c static int max31856_read(struct max31856_data *data, u8 reg, reg 71 drivers/iio/temperature/max31856.c return spi_write_then_read(data->spi, ®, 1, val, read_size); reg 74 drivers/iio/temperature/max31856.c static int max31856_write(struct max31856_data *data, u8 reg, reg 79 drivers/iio/temperature/max31856.c buf[0] = reg | (MAX31856_RD_WR_BIT); reg 49 drivers/iio/temperature/tmp006.c static int tmp006_read_measurement(struct tmp006_data *data, u8 reg) reg 67 drivers/iio/temperature/tmp006.c return i2c_smbus_read_word_swapped(data->client, reg); reg 73 drivers/iio/temperature/tmp007.c static int tmp007_read_temperature(struct tmp007_data *data, u8 reg) reg 92 drivers/iio/temperature/tmp007.c return i2c_smbus_read_word_swapped(data->client, reg); reg 291 drivers/iio/temperature/tmp007.c u8 reg; reg 296 drivers/iio/temperature/tmp007.c reg = TMP007_TDIE_HIGH_LIMIT; reg 298 drivers/iio/temperature/tmp007.c reg = TMP007_TDIE_LOW_LIMIT; reg 302 drivers/iio/temperature/tmp007.c reg = TMP007_TOBJ_HIGH_LIMIT; reg 304 drivers/iio/temperature/tmp007.c reg = TMP007_TOBJ_LOW_LIMIT; reg 310 drivers/iio/temperature/tmp007.c ret = i2c_smbus_read_word_swapped(data->client, reg); reg 326 drivers/iio/temperature/tmp007.c u8 reg; reg 331 drivers/iio/temperature/tmp007.c reg = TMP007_TDIE_HIGH_LIMIT; reg 333 drivers/iio/temperature/tmp007.c reg = TMP007_TDIE_LOW_LIMIT; reg 337 drivers/iio/temperature/tmp007.c reg = TMP007_TOBJ_HIGH_LIMIT; reg 339 drivers/iio/temperature/tmp007.c reg = TMP007_TOBJ_LOW_LIMIT; reg 350 drivers/iio/temperature/tmp007.c return i2c_smbus_write_word_swapped(data->client, reg, (val << 7)); reg 440 drivers/infiniband/core/iwpm_util.c void iwpm_set_registration(u8 nl_client, u32 reg) reg 442 drivers/infiniband/core/iwpm_util.c iwpm_admin.reg_list[nl_client] = reg; reg 446 drivers/infiniband/core/iwpm_util.c u32 iwpm_check_registration(u8 nl_client, u32 reg) reg 448 drivers/infiniband/core/iwpm_util.c return (iwpm_get_registration(nl_client) & reg); reg 176 drivers/infiniband/core/iwpm_util.h u32 iwpm_check_registration(u8 nl_client, u32 reg); reg 183 drivers/infiniband/core/iwpm_util.h void iwpm_set_registration(u8 nl_client, u32 reg); reg 68 drivers/infiniband/core/rw.c static inline int rdma_rw_inv_key(struct rdma_rw_reg_ctx *reg) reg 72 drivers/infiniband/core/rw.c if (reg->mr->need_inval) { reg 73 drivers/infiniband/core/rw.c reg->inv_wr.opcode = IB_WR_LOCAL_INV; reg 74 drivers/infiniband/core/rw.c reg->inv_wr.ex.invalidate_rkey = reg->mr->lkey; reg 75 drivers/infiniband/core/rw.c reg->inv_wr.next = ®->reg_wr.wr; reg 78 drivers/infiniband/core/rw.c reg->inv_wr.next = NULL; reg 86 drivers/infiniband/core/rw.c struct rdma_rw_reg_ctx *reg, struct scatterlist *sg, reg 94 drivers/infiniband/core/rw.c reg->mr = ib_mr_pool_get(qp, &qp->rdma_mrs); reg 95 drivers/infiniband/core/rw.c if (!reg->mr) reg 98 drivers/infiniband/core/rw.c count += rdma_rw_inv_key(reg); reg 100 drivers/infiniband/core/rw.c ret = ib_map_mr_sg(reg->mr, sg, nents, &offset, PAGE_SIZE); reg 102 drivers/infiniband/core/rw.c ib_mr_pool_put(qp, &qp->rdma_mrs, reg->mr); reg 106 drivers/infiniband/core/rw.c reg->reg_wr.wr.opcode = IB_WR_REG_MR; reg 107 drivers/infiniband/core/rw.c reg->reg_wr.mr = reg->mr; reg 108 drivers/infiniband/core/rw.c reg->reg_wr.access = IB_ACCESS_LOCAL_WRITE; reg 110 drivers/infiniband/core/rw.c reg->reg_wr.access |= IB_ACCESS_REMOTE_WRITE; reg 113 drivers/infiniband/core/rw.c reg->sge.addr = reg->mr->iova; reg 114 drivers/infiniband/core/rw.c reg->sge.length = reg->mr->length; reg 128 drivers/infiniband/core/rw.c ctx->reg = kcalloc(ctx->nr_ops, sizeof(*ctx->reg), GFP_KERNEL); reg 129 drivers/infiniband/core/rw.c if (!ctx->reg) { reg 135 drivers/infiniband/core/rw.c struct rdma_rw_reg_ctx *reg = &ctx->reg[i]; reg 138 drivers/infiniband/core/rw.c ret = rdma_rw_init_one_mr(qp, port_num, reg, sg, sg_cnt, reg 145 drivers/infiniband/core/rw.c if (reg->mr->need_inval) reg 146 drivers/infiniband/core/rw.c prev->wr.wr.next = ®->inv_wr; reg 148 drivers/infiniband/core/rw.c prev->wr.wr.next = ®->reg_wr.wr; reg 151 drivers/infiniband/core/rw.c reg->reg_wr.wr.next = ®->wr.wr; reg 153 drivers/infiniband/core/rw.c reg->wr.wr.sg_list = ®->sge; reg 154 drivers/infiniband/core/rw.c reg->wr.wr.num_sge = 1; reg 155 drivers/infiniband/core/rw.c reg->wr.remote_addr = remote_addr; reg 156 drivers/infiniband/core/rw.c reg->wr.rkey = rkey; reg 158 drivers/infiniband/core/rw.c reg->wr.wr.opcode = IB_WR_RDMA_WRITE; reg 160 drivers/infiniband/core/rw.c reg->wr.wr.opcode = IB_WR_RDMA_READ; reg 162 drivers/infiniband/core/rw.c reg->wr.wr.opcode = IB_WR_RDMA_READ_WITH_INV; reg 163 drivers/infiniband/core/rw.c reg->wr.wr.ex.invalidate_rkey = reg->mr->lkey; reg 167 drivers/infiniband/core/rw.c remote_addr += reg->sge.length; reg 171 drivers/infiniband/core/rw.c prev = reg; reg 183 drivers/infiniband/core/rw.c ib_mr_pool_put(qp, &qp->rdma_mrs, ctx->reg[i].mr); reg 184 drivers/infiniband/core/rw.c kfree(ctx->reg); reg 405 drivers/infiniband/core/rw.c ctx->reg = kcalloc(1, sizeof(*ctx->reg), GFP_KERNEL); reg 406 drivers/infiniband/core/rw.c if (!ctx->reg) { reg 411 drivers/infiniband/core/rw.c ctx->reg->mr = ib_mr_pool_get(qp, &qp->sig_mrs); reg 412 drivers/infiniband/core/rw.c if (!ctx->reg->mr) { reg 417 drivers/infiniband/core/rw.c count += rdma_rw_inv_key(ctx->reg); reg 419 drivers/infiniband/core/rw.c memcpy(ctx->reg->mr->sig_attrs, sig_attrs, sizeof(struct ib_sig_attrs)); reg 421 drivers/infiniband/core/rw.c ret = ib_map_mr_sg_pi(ctx->reg->mr, sg, sg_cnt, NULL, prot_sg, reg 428 drivers/infiniband/core/rw.c ctx->reg->reg_wr.wr.opcode = IB_WR_REG_MR_INTEGRITY; reg 429 drivers/infiniband/core/rw.c ctx->reg->reg_wr.wr.wr_cqe = NULL; reg 430 drivers/infiniband/core/rw.c ctx->reg->reg_wr.wr.num_sge = 0; reg 431 drivers/infiniband/core/rw.c ctx->reg->reg_wr.wr.send_flags = 0; reg 432 drivers/infiniband/core/rw.c ctx->reg->reg_wr.access = IB_ACCESS_LOCAL_WRITE; reg 434 drivers/infiniband/core/rw.c ctx->reg->reg_wr.access |= IB_ACCESS_REMOTE_WRITE; reg 435 drivers/infiniband/core/rw.c ctx->reg->reg_wr.mr = ctx->reg->mr; reg 436 drivers/infiniband/core/rw.c ctx->reg->reg_wr.key = ctx->reg->mr->lkey; reg 439 drivers/infiniband/core/rw.c ctx->reg->sge.addr = ctx->reg->mr->iova; reg 440 drivers/infiniband/core/rw.c ctx->reg->sge.length = ctx->reg->mr->length; reg 442 drivers/infiniband/core/rw.c ctx->reg->sge.length -= ctx->reg->mr->sig_attrs->meta_length; reg 444 drivers/infiniband/core/rw.c rdma_wr = &ctx->reg->wr; reg 445 drivers/infiniband/core/rw.c rdma_wr->wr.sg_list = &ctx->reg->sge; reg 453 drivers/infiniband/core/rw.c ctx->reg->reg_wr.wr.next = &rdma_wr->wr; reg 459 drivers/infiniband/core/rw.c ib_mr_pool_put(qp, &qp->sig_mrs, ctx->reg->mr); reg 461 drivers/infiniband/core/rw.c kfree(ctx->reg); reg 477 drivers/infiniband/core/rw.c static void rdma_rw_update_lkey(struct rdma_rw_reg_ctx *reg, bool need_inval) reg 479 drivers/infiniband/core/rw.c reg->mr->need_inval = need_inval; reg 480 drivers/infiniband/core/rw.c ib_update_fast_reg_key(reg->mr, ib_inc_rkey(reg->mr->lkey)); reg 481 drivers/infiniband/core/rw.c reg->reg_wr.key = reg->mr->lkey; reg 482 drivers/infiniband/core/rw.c reg->sge.lkey = reg->mr->lkey; reg 510 drivers/infiniband/core/rw.c rdma_rw_update_lkey(&ctx->reg[i], reg 511 drivers/infiniband/core/rw.c ctx->reg[i].wr.wr.opcode != reg 515 drivers/infiniband/core/rw.c if (ctx->reg[0].inv_wr.next) reg 516 drivers/infiniband/core/rw.c first_wr = &ctx->reg[0].inv_wr; reg 518 drivers/infiniband/core/rw.c first_wr = &ctx->reg[0].reg_wr.wr; reg 519 drivers/infiniband/core/rw.c last_wr = &ctx->reg[ctx->nr_ops - 1].wr.wr; reg 585 drivers/infiniband/core/rw.c ib_mr_pool_put(qp, &qp->rdma_mrs, ctx->reg[i].mr); reg 586 drivers/infiniband/core/rw.c kfree(ctx->reg); reg 623 drivers/infiniband/core/rw.c ib_mr_pool_put(qp, &qp->sig_mrs, ctx->reg->mr); reg 624 drivers/infiniband/core/rw.c kfree(ctx->reg); reg 16 drivers/infiniband/hw/hfi1/aspm.c #define ASPM_L1_SUPPORTED(reg) \ reg 17 drivers/infiniband/hw/hfi1/aspm.c ((((reg) & PCI_EXP_LNKCAP_ASPMS) >> 10) & 0x2) reg 1044 drivers/infiniband/hw/hfi1/chip.c static void handle_qsfp_int(struct hfi1_devdata *dd, u32 source, u64 reg); reg 1049 drivers/infiniband/hw/hfi1/chip.c static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg); reg 1050 drivers/infiniband/hw/hfi1/chip.c static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg); reg 1051 drivers/infiniband/hw/hfi1/chip.c static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg); reg 1052 drivers/infiniband/hw/hfi1/chip.c static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg); reg 1053 drivers/infiniband/hw/hfi1/chip.c static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg); reg 1054 drivers/infiniband/hw/hfi1/chip.c static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg); reg 1055 drivers/infiniband/hw/hfi1/chip.c static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg); reg 1056 drivers/infiniband/hw/hfi1/chip.c static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg); reg 1099 drivers/infiniband/hw/hfi1/chip.c void (*handler)(struct hfi1_devdata *dd, u32 source, u64 reg); reg 1111 drivers/infiniband/hw/hfi1/chip.c #define EE(reg, handler, desc) \ reg 1112 drivers/infiniband/hw/hfi1/chip.c { reg##_STATUS, reg##_CLEAR, reg##_MASK, \ reg 1114 drivers/infiniband/hw/hfi1/chip.c #define DC_EE1(reg, handler, desc) \ reg 1115 drivers/infiniband/hw/hfi1/chip.c { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc } reg 1116 drivers/infiniband/hw/hfi1/chip.c #define DC_EE2(reg, handler, desc) \ reg 1117 drivers/infiniband/hw/hfi1/chip.c { reg##_FLG, reg##_CLR, reg##_EN, handler, desc } reg 5538 drivers/infiniband/hw/hfi1/chip.c static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg) reg 5548 drivers/infiniband/hw/hfi1/chip.c cce_err_status_string(buf, sizeof(buf), reg)); reg 5550 drivers/infiniband/hw/hfi1/chip.c if ((reg & CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK) && reg 5558 drivers/infiniband/hw/hfi1/chip.c if (reg & (1ull << i)) { reg 5604 drivers/infiniband/hw/hfi1/chip.c static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg) reg 5610 drivers/infiniband/hw/hfi1/chip.c rxe_err_status_string(buf, sizeof(buf), reg)); reg 5612 drivers/infiniband/hw/hfi1/chip.c if (reg & ALL_RXE_FREEZE_ERR) { reg 5619 drivers/infiniband/hw/hfi1/chip.c if (is_ax(dd) && (reg & RXE_FREEZE_ABORT_MASK)) reg 5626 drivers/infiniband/hw/hfi1/chip.c if (reg & (1ull << i)) reg 5631 drivers/infiniband/hw/hfi1/chip.c static void handle_misc_err(struct hfi1_devdata *dd, u32 unused, u64 reg) reg 5637 drivers/infiniband/hw/hfi1/chip.c misc_err_status_string(buf, sizeof(buf), reg)); reg 5639 drivers/infiniband/hw/hfi1/chip.c if (reg & (1ull << i)) reg 5644 drivers/infiniband/hw/hfi1/chip.c static void handle_pio_err(struct hfi1_devdata *dd, u32 unused, u64 reg) reg 5650 drivers/infiniband/hw/hfi1/chip.c pio_err_status_string(buf, sizeof(buf), reg)); reg 5652 drivers/infiniband/hw/hfi1/chip.c if (reg & ALL_PIO_FREEZE_ERR) reg 5656 drivers/infiniband/hw/hfi1/chip.c if (reg & (1ull << i)) reg 5661 drivers/infiniband/hw/hfi1/chip.c static void handle_sdma_err(struct hfi1_devdata *dd, u32 unused, u64 reg) reg 5667 drivers/infiniband/hw/hfi1/chip.c sdma_err_status_string(buf, sizeof(buf), reg)); reg 5669 drivers/infiniband/hw/hfi1/chip.c if (reg & ALL_SDMA_FREEZE_ERR) reg 5673 drivers/infiniband/hw/hfi1/chip.c if (reg & (1ull << i)) reg 5829 drivers/infiniband/hw/hfi1/chip.c static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg) reg 5831 drivers/infiniband/hw/hfi1/chip.c u64 reg_copy = reg, handled = 0; reg 5835 drivers/infiniband/hw/hfi1/chip.c if (reg & ALL_TXE_EGRESS_FREEZE_ERR) reg 5838 drivers/infiniband/hw/hfi1/chip.c (reg & SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK) && reg 5860 drivers/infiniband/hw/hfi1/chip.c reg &= ~handled; reg 5862 drivers/infiniband/hw/hfi1/chip.c if (reg) reg 5864 drivers/infiniband/hw/hfi1/chip.c egress_err_status_string(buf, sizeof(buf), reg)); reg 5867 drivers/infiniband/hw/hfi1/chip.c if (reg & (1ull << i)) reg 5872 drivers/infiniband/hw/hfi1/chip.c static void handle_txe_err(struct hfi1_devdata *dd, u32 unused, u64 reg) reg 5878 drivers/infiniband/hw/hfi1/chip.c send_err_status_string(buf, sizeof(buf), reg)); reg 5881 drivers/infiniband/hw/hfi1/chip.c if (reg & (1ull << i)) reg 5907 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 5913 drivers/infiniband/hw/hfi1/chip.c reg = read_kctxt_csr(dd, context, eri->status); reg 5914 drivers/infiniband/hw/hfi1/chip.c if (reg == 0) reg 5916 drivers/infiniband/hw/hfi1/chip.c write_kctxt_csr(dd, context, eri->clear, reg); reg 5918 drivers/infiniband/hw/hfi1/chip.c eri->handler(dd, context, reg); reg 5924 drivers/infiniband/hw/hfi1/chip.c eri->desc, reg); reg 5930 drivers/infiniband/hw/hfi1/chip.c mask &= ~reg; reg 6093 drivers/infiniband/hw/hfi1/chip.c static void handle_qsfp_int(struct hfi1_devdata *dd, u32 src_ctx, u64 reg) reg 6100 drivers/infiniband/hw/hfi1/chip.c if (reg & QSFP_HFI0_MODPRST_N) { reg 6166 drivers/infiniband/hw/hfi1/chip.c if (reg & QSFP_HFI0_INT_N) { reg 6360 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 6364 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1); reg 6365 drivers/infiniband/hw/hfi1/chip.c if ((reg & DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK) == 0) reg 6372 drivers/infiniband/hw/hfi1/chip.c type = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT) reg 6374 drivers/infiniband/hw/hfi1/chip.c data = (reg >> DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT) reg 6419 drivers/infiniband/hw/hfi1/chip.c u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); reg 6422 drivers/infiniband/hw/hfi1/chip.c reg &= ~SEND_CM_GLOBAL_CREDIT_AU_SMASK; reg 6423 drivers/infiniband/hw/hfi1/chip.c reg |= (u64)vau << SEND_CM_GLOBAL_CREDIT_AU_SHIFT; reg 6424 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); reg 6434 drivers/infiniband/hw/hfi1/chip.c u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); reg 6437 drivers/infiniband/hw/hfi1/chip.c reg &= ~(SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK | reg 6444 drivers/infiniband/hw/hfi1/chip.c reg |= (u64)vl15buf << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT; reg 6445 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); reg 6499 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 6508 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DCC_CFG_RESET); reg 6509 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DCC_CFG_RESET, reg | reg 6514 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DCC_CFG_RESET, reg); reg 6807 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 6811 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, CCE_STATUS); reg 6814 drivers/infiniband/hw/hfi1/chip.c if ((reg & ALL_FROZE) == ALL_FROZE) reg 6818 drivers/infiniband/hw/hfi1/chip.c if ((reg & ALL_FROZE) == 0) reg 6825 drivers/infiniband/hw/hfi1/chip.c freeze ? "" : "un", reg & ALL_FROZE, reg 7446 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 7524 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, SEND_CM_CTRL); reg 7527 drivers/infiniband/hw/hfi1/chip.c reg | SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK); reg 7530 drivers/infiniband/hw/hfi1/chip.c reg & ~SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK); reg 7587 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN); reg 7588 drivers/infiniband/hw/hfi1/chip.c reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK reg 7590 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_LCB_CFG_LINK_KILL_EN, reg); reg 7750 drivers/infiniband/hw/hfi1/chip.c static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg) reg 7758 drivers/infiniband/hw/hfi1/chip.c if (reg & DC_DC8051_ERR_FLG_SET_BY_8051_SMASK) { reg 7856 drivers/infiniband/hw/hfi1/chip.c reg &= ~DC_DC8051_ERR_FLG_SET_BY_8051_SMASK; reg 7858 drivers/infiniband/hw/hfi1/chip.c if (reg & DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK) { reg 7869 drivers/infiniband/hw/hfi1/chip.c reg &= ~DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK; reg 7871 drivers/infiniband/hw/hfi1/chip.c if (reg) { reg 7874 drivers/infiniband/hw/hfi1/chip.c dc8051_err_string(buf, sizeof(buf), reg)); reg 7945 drivers/infiniband/hw/hfi1/chip.c static void handle_dcc_err(struct hfi1_devdata *dd, u32 unused, u64 reg) reg 7954 drivers/infiniband/hw/hfi1/chip.c if (reg & DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK) { reg 7961 drivers/infiniband/hw/hfi1/chip.c reg &= ~DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK; reg 7964 drivers/infiniband/hw/hfi1/chip.c if (reg & DCC_ERR_FLG_LINK_ERR_SMASK) { reg 7969 drivers/infiniband/hw/hfi1/chip.c reg &= ~DCC_ERR_FLG_LINK_ERR_SMASK; reg 7972 drivers/infiniband/hw/hfi1/chip.c if (reg & DCC_ERR_FLG_FMCONFIG_ERR_SMASK) { reg 8020 drivers/infiniband/hw/hfi1/chip.c reg &= ~DCC_ERR_FLG_FMCONFIG_ERR_SMASK; reg 8023 drivers/infiniband/hw/hfi1/chip.c if (reg & DCC_ERR_FLG_RCVPORT_ERR_SMASK) { reg 8074 drivers/infiniband/hw/hfi1/chip.c reg &= ~DCC_ERR_FLG_RCVPORT_ERR_SMASK; reg 8077 drivers/infiniband/hw/hfi1/chip.c if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK) { reg 8080 drivers/infiniband/hw/hfi1/chip.c reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK; reg 8082 drivers/infiniband/hw/hfi1/chip.c if (reg & DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK) { reg 8085 drivers/infiniband/hw/hfi1/chip.c reg &= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK; reg 8089 drivers/infiniband/hw/hfi1/chip.c reg &= ~DCC_ERR_FLG_LATE_EBP_ERR_SMASK; reg 8092 drivers/infiniband/hw/hfi1/chip.c if (reg) reg 8094 drivers/infiniband/hw/hfi1/chip.c dcc_err_string(buf, sizeof(buf), reg)); reg 8107 drivers/infiniband/hw/hfi1/chip.c static void handle_lcb_err(struct hfi1_devdata *dd, u32 unused, u64 reg) reg 8112 drivers/infiniband/hw/hfi1/chip.c lcb_err_string(buf, sizeof(buf), reg)); reg 8501 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 8503 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DC_DC8051_STS_CUR_STATE); reg 8504 drivers/infiniband/hw/hfi1/chip.c return (reg >> DC_DC8051_STS_CUR_STATE_PORT_SHIFT) reg 8510 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 8512 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DCC_CFG_PORT_CONFIG); reg 8513 drivers/infiniband/hw/hfi1/chip.c return (reg >> DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT) reg 8519 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 8521 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DCC_CFG_PORT_CONFIG); reg 8523 drivers/infiniband/hw/hfi1/chip.c reg &= ~DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK; reg 8524 drivers/infiniband/hw/hfi1/chip.c reg |= (u64)chip_lstate << DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT; reg 8525 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DCC_CFG_PORT_CONFIG, reg); reg 8675 drivers/infiniband/hw/hfi1/chip.c u64 reg, completed; reg 8730 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_0); reg 8731 drivers/infiniband/hw/hfi1/chip.c reg &= DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK; reg 8732 drivers/infiniband/hw/hfi1/chip.c reg |= ((((*out_data) >> 40) & 0xff) << reg 8736 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, reg); reg 8743 drivers/infiniband/hw/hfi1/chip.c reg = ((u64)type & DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK) reg 8747 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); reg 8748 drivers/infiniband/hw/hfi1/chip.c reg |= DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK; reg 8749 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, DC_DC8051_CFG_HOST_CMD_0, reg); reg 8754 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1); reg 8755 drivers/infiniband/hw/hfi1/chip.c completed = reg & DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK; reg 8770 drivers/infiniband/hw/hfi1/chip.c *out_data = (reg >> DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT) reg 8780 drivers/infiniband/hw/hfi1/chip.c return_code = (reg >> DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT) reg 9896 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 9913 drivers/infiniband/hw/hfi1/chip.c reg = RCV_ARRAY_RT_WRITE_ENABLE_SMASK reg 9917 drivers/infiniband/hw/hfi1/chip.c trace_hfi1_write_rcvarray(dd->rcvarray_wc + (index * 8), reg); reg 9918 drivers/infiniband/hw/hfi1/chip.c writeq(reg, dd->rcvarray_wc + (index * 8)); reg 10302 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 10308 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE); reg 10309 drivers/infiniband/hw/hfi1/chip.c if (reg) reg 10605 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 10611 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(ppd->dd, SEND_CM_CREDIT_VL + (8 * i)); reg 10612 drivers/infiniband/hw/hfi1/chip.c if ((reg && !ppd->dd->vld[i].mtu) || reg 10613 drivers/infiniband/hw/hfi1/chip.c (!reg && ppd->dd->vld[i].mtu)) reg 10931 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 10944 drivers/infiniband/hw/hfi1/chip.c reg = ((u64)val & SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK) reg 10946 drivers/infiniband/hw/hfi1/chip.c write_csr(ppd->dd, SEND_HIGH_PRIORITY_LIMIT, reg); reg 11080 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 11113 drivers/infiniband/hw/hfi1/chip.c reg = (((u64)vl->vl & SEND_LOW_PRIORITY_LIST_VL_MASK) reg 11118 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, target + (i * 8), reg); reg 11137 drivers/infiniband/hw/hfi1/chip.c u64 reg = read_csr(dd, csr); reg 11140 drivers/infiniband/hw/hfi1/chip.c (reg >> SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT) reg 11143 drivers/infiniband/hw/hfi1/chip.c (reg >> SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT) reg 11153 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 11166 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); reg 11168 drivers/infiniband/hw/hfi1/chip.c (reg >> SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT) reg 11171 drivers/infiniband/hw/hfi1/chip.c *overall_limit = (reg reg 11179 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 11183 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0); reg 11185 drivers/infiniband/hw/hfi1/chip.c u8 byte = *(((u8 *)®) + i); reg 11191 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16); reg 11193 drivers/infiniband/hw/hfi1/chip.c u8 byte = *(((u8 *)®) + i); reg 11263 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 11265 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); reg 11266 drivers/infiniband/hw/hfi1/chip.c reg &= ~SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK; reg 11267 drivers/infiniband/hw/hfi1/chip.c reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT; reg 11268 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); reg 11274 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 11276 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); reg 11277 drivers/infiniband/hw/hfi1/chip.c reg &= ~SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK; reg 11278 drivers/infiniband/hw/hfi1/chip.c reg |= (u64)limit << SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT; reg 11279 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, SEND_CM_GLOBAL_CREDIT, reg); reg 11285 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 11293 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, addr); reg 11294 drivers/infiniband/hw/hfi1/chip.c reg &= ~SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK; reg 11295 drivers/infiniband/hw/hfi1/chip.c reg |= (u64)limit << SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT; reg 11296 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, addr, reg); reg 11302 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 11310 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, addr); reg 11311 drivers/infiniband/hw/hfi1/chip.c reg &= ~SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK; reg 11312 drivers/infiniband/hw/hfi1/chip.c reg |= (u64)limit << SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT; reg 11313 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, addr, reg); reg 11321 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 11325 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask; reg 11327 drivers/infiniband/hw/hfi1/chip.c if (reg == 0) reg 11336 drivers/infiniband/hw/hfi1/chip.c which, VL_STATUS_CLEAR_TIMEOUT, mask, reg); reg 11808 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 11818 drivers/infiniband/hw/hfi1/chip.c reg = (egrhd & RCV_EGR_INDEX_HEAD_HEAD_MASK) reg 11820 drivers/infiniband/hw/hfi1/chip.c write_uctxt_csr(dd, ctxt, RCV_EGR_INDEX_HEAD, reg); reg 11822 drivers/infiniband/hw/hfi1/chip.c reg = ((u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT) | reg 11825 drivers/infiniband/hw/hfi1/chip.c write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg); reg 11882 drivers/infiniband/hw/hfi1/chip.c u64 rcvctrl, reg; reg 11936 drivers/infiniband/hw/hfi1/chip.c reg = (((u64)(rcd->egrbufs.alloced >> RCV_SHIFT) reg 11942 drivers/infiniband/hw/hfi1/chip.c write_kctxt_csr(dd, ctxt, RCV_EGR_CTRL, reg); reg 11950 drivers/infiniband/hw/hfi1/chip.c reg = (((rcd->expected_count >> RCV_SHIFT) reg 11956 drivers/infiniband/hw/hfi1/chip.c write_kctxt_csr(dd, ctxt, RCV_TID_CTRL, reg); reg 12028 drivers/infiniband/hw/hfi1/chip.c reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS); reg 12029 drivers/infiniband/hw/hfi1/chip.c if (reg != 0) { reg 12031 drivers/infiniband/hw/hfi1/chip.c ctxt, reg); reg 12036 drivers/infiniband/hw/hfi1/chip.c reg = read_kctxt_csr(dd, ctxt, RCV_CTXT_STATUS); reg 12038 drivers/infiniband/hw/hfi1/chip.c ctxt, reg, reg == 0 ? "not" : "still"); reg 12053 drivers/infiniband/hw/hfi1/chip.c reg = (u64)rcv_intr_count << RCV_HDR_HEAD_COUNTER_SHIFT; reg 12054 drivers/infiniband/hw/hfi1/chip.c write_uctxt_csr(dd, ctxt, RCV_HDR_HEAD, reg); reg 13013 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 13017 drivers/infiniband/hw/hfi1/chip.c reg = read_kctxt_csr(dd, sc->hw_context, reg 13020 drivers/infiniband/hw/hfi1/chip.c CLEAR_STATIC_RATE_CONTROL_SMASK(reg); reg 13022 drivers/infiniband/hw/hfi1/chip.c SET_STATIC_RATE_CONTROL_SMASK(reg); reg 13024 drivers/infiniband/hw/hfi1/chip.c SEND_CTXT_CHECK_ENABLE, reg); reg 13031 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 13039 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, ASIC_STS_THERM); reg 13040 drivers/infiniband/hw/hfi1/chip.c temp->curr = ((reg >> ASIC_STS_THERM_CURR_TEMP_SHIFT) & reg 13042 drivers/infiniband/hw/hfi1/chip.c temp->lo_lim = ((reg >> ASIC_STS_THERM_LO_TEMP_SHIFT) & reg 13044 drivers/infiniband/hw/hfi1/chip.c temp->hi_lim = ((reg >> ASIC_STS_THERM_HI_TEMP_SHIFT) & reg 13046 drivers/infiniband/hw/hfi1/chip.c temp->crit_lim = ((reg >> ASIC_STS_THERM_CRIT_TEMP_SHIFT) & reg 13049 drivers/infiniband/hw/hfi1/chip.c temp->triggers = (u8)((reg >> ASIC_STS_THERM_LOW_SHIFT) & 0x7); reg 13067 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 13071 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, CCE_INT_MASK + (8 * idx)); reg 13073 drivers/infiniband/hw/hfi1/chip.c reg |= bits; reg 13075 drivers/infiniband/hw/hfi1/chip.c reg &= ~bits; reg 13076 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_MASK + (8 * idx), reg); reg 13148 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 13164 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, CCE_INT_MAP + (8 * m)); reg 13165 drivers/infiniband/hw/hfi1/chip.c reg &= ~((u64)0xff << (8 * n)); reg 13166 drivers/infiniband/hw/hfi1/chip.c reg |= ((u64)msix_intr & 0xff) << (8 * n); reg 13167 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_MAP + (8 * m), reg); reg 13410 drivers/infiniband/hw/hfi1/chip.c u64 reg = 0; reg 13415 drivers/infiniband/hw/hfi1/chip.c reg |= (ppd->pkeys[i] & reg 13422 drivers/infiniband/hw/hfi1/chip.c ((i - 3) * 2), reg); reg 13423 drivers/infiniband/hw/hfi1/chip.c reg = 0; reg 13484 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 13487 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, CCE_STATUS); reg 13488 drivers/infiniband/hw/hfi1/chip.c if ((reg & status_bits) == 0) reg 13497 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, CCE_STATUS); reg 13498 drivers/infiniband/hw/hfi1/chip.c if ((reg & status_bits) == 0) reg 13503 drivers/infiniband/hw/hfi1/chip.c status_bits, reg & status_bits); reg 13706 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 13715 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, RCV_STATUS); reg 13716 drivers/infiniband/hw/hfi1/chip.c if ((reg & (RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK reg 13729 drivers/infiniband/hw/hfi1/chip.c __func__, reg); reg 13751 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, RCV_STATUS); reg 13752 drivers/infiniband/hw/hfi1/chip.c if (reg & (RCV_STATUS_RX_RBUF_INIT_DONE_SMASK)) reg 14054 drivers/infiniband/hw/hfi1/chip.c u64 reg = read_csr(dd, RCV_QP_MAP_TABLE + (idx / 8) * 8); reg 14056 drivers/infiniband/hw/hfi1/chip.c reg >>= (idx % 8) * 8; reg 14057 drivers/infiniband/hw/hfi1/chip.c return reg; reg 14081 drivers/infiniband/hw/hfi1/chip.c u64 reg = 0; reg 14087 drivers/infiniband/hw/hfi1/chip.c reg |= ctxt << (8 * (i % 8)); reg 14092 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, regno, reg); reg 14093 drivers/infiniband/hw/hfi1/chip.c reg = 0; reg 14256 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 14283 drivers/infiniband/hw/hfi1/chip.c reg = rmt->map[regidx]; reg 14284 drivers/infiniband/hw/hfi1/chip.c reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK reg 14286 drivers/infiniband/hw/hfi1/chip.c reg |= (u64)(tctxt++) << regoff; reg 14287 drivers/infiniband/hw/hfi1/chip.c rmt->map[regidx] = reg; reg 14325 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 14361 drivers/infiniband/hw/hfi1/chip.c reg = rmt->map[regidx]; reg 14362 drivers/infiniband/hw/hfi1/chip.c reg &= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK << regoff); reg 14363 drivers/infiniband/hw/hfi1/chip.c reg |= (u64)i << regoff; reg 14364 drivers/infiniband/hw/hfi1/chip.c rmt->map[regidx] = reg; reg 14400 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 14416 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, regoff); reg 14420 drivers/infiniband/hw/hfi1/chip.c reg &= ~(0xffllu << (j * 8)); reg 14421 drivers/infiniband/hw/hfi1/chip.c reg |= (u64)dd->vnic.ctxt[ctx_id++]->ctxt << (j * 8); reg 14428 drivers/infiniband/hw/hfi1/chip.c regoff - RCV_RSM_MAP_TABLE, reg); reg 14430 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, regoff, reg); reg 14433 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, regoff); reg 14592 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 14598 drivers/infiniband/hw/hfi1/chip.c reg = SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK | /* mask is always 1's */ reg 14603 drivers/infiniband/hw/hfi1/chip.c reg |= SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK; reg 14604 drivers/infiniband/hw/hfi1/chip.c write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_JOB_KEY, reg); reg 14609 drivers/infiniband/hw/hfi1/chip.c reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); reg 14610 drivers/infiniband/hw/hfi1/chip.c reg |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; reg 14611 drivers/infiniband/hw/hfi1/chip.c write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); reg 14615 drivers/infiniband/hw/hfi1/chip.c reg = RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK | reg 14618 drivers/infiniband/hw/hfi1/chip.c write_kctxt_csr(dd, rcd->ctxt, RCV_KEY_CTRL, reg); reg 14626 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 14639 drivers/infiniband/hw/hfi1/chip.c reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); reg 14640 drivers/infiniband/hw/hfi1/chip.c reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK; reg 14641 drivers/infiniband/hw/hfi1/chip.c write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); reg 14653 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 14659 drivers/infiniband/hw/hfi1/chip.c reg = ((u64)pkey & SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK) << reg 14661 drivers/infiniband/hw/hfi1/chip.c write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_PARTITION_KEY, reg); reg 14662 drivers/infiniband/hw/hfi1/chip.c reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); reg 14663 drivers/infiniband/hw/hfi1/chip.c reg |= SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK; reg 14664 drivers/infiniband/hw/hfi1/chip.c reg &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK; reg 14665 drivers/infiniband/hw/hfi1/chip.c write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); reg 14673 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 14679 drivers/infiniband/hw/hfi1/chip.c reg = read_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE); reg 14680 drivers/infiniband/hw/hfi1/chip.c reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK; reg 14681 drivers/infiniband/hw/hfi1/chip.c write_kctxt_csr(dd, hw_ctxt, SEND_CTXT_CHECK_ENABLE, reg); reg 14781 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 14788 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, CCE_INT_MASK); reg 14789 drivers/infiniband/hw/hfi1/chip.c if (reg) reg 14794 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, CCE_INT_STATUS); reg 14795 drivers/infiniband/hw/hfi1/chip.c if (reg) reg 14800 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, CCE_INT_STATUS); reg 14801 drivers/infiniband/hw/hfi1/chip.c if (reg != all_bits) reg 14827 drivers/infiniband/hw/hfi1/chip.c u64 reg; reg 14918 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, CCE_REVISION2); reg 14919 drivers/infiniband/hw/hfi1/chip.c dd->hfi1_id = (reg >> CCE_REVISION2_HFI_ID_SHIFT) reg 14922 drivers/infiniband/hw/hfi1/chip.c dd->icode = reg >> CCE_REVISION2_IMPL_CODE_SHIFT; reg 14923 drivers/infiniband/hw/hfi1/chip.c dd->irev = reg >> CCE_REVISION2_IMPL_REVISION_SHIFT; reg 89 drivers/infiniband/hw/hfi1/firmware.c #define SBUS_COUNTER(reg, name) \ reg 90 drivers/infiniband/hw/hfi1/firmware.c (((reg) >> ASIC_STS_SBUS_COUNTERS_##name##_CNT_SHIFT) & \ reg 274 drivers/infiniband/hw/hfi1/firmware.c u64 reg; reg 278 drivers/infiniband/hw/hfi1/firmware.c reg = (addr & DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK) reg 280 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg); reg 283 drivers/infiniband/hw/hfi1/firmware.c reg | DC_DC8051_CFG_RAM_ACCESS_CTRL_READ_ENA_SMASK); reg 339 drivers/infiniband/hw/hfi1/firmware.c u64 reg; reg 347 drivers/infiniband/hw/hfi1/firmware.c reg = (code ? DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK : 0ull) reg 349 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, reg); reg 351 drivers/infiniband/hw/hfi1/firmware.c reg = ((start & DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK) reg 354 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg); reg 361 drivers/infiniband/hw/hfi1/firmware.c reg = 0; reg 362 drivers/infiniband/hw/hfi1/firmware.c memcpy(®, &data[offset], bytes); reg 364 drivers/infiniband/hw/hfi1/firmware.c reg = *(u64 *)&data[offset]; reg 366 drivers/infiniband/hw/hfi1/firmware.c memcpy(®, &data[offset], 8); reg 368 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_WR_DATA, reg); reg 822 drivers/infiniband/hw/hfi1/firmware.c u64 reg; reg 919 drivers/infiniband/hw/hfi1/firmware.c reg = read_csr(dd, MISC_ERR_STATUS); reg 921 drivers/infiniband/hw/hfi1/firmware.c if (reg & MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK) reg 924 drivers/infiniband/hw/hfi1/firmware.c if (reg & MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK) reg 949 drivers/infiniband/hw/hfi1/firmware.c u64 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE); reg 951 drivers/infiniband/hw/hfi1/firmware.c return (reg >> DC_DC8051_STS_CUR_STATE_FIRMWARE_SHIFT) reg 983 drivers/infiniband/hw/hfi1/firmware.c u64 reg; reg 996 drivers/infiniband/hw/hfi1/firmware.c reg = DC_DC8051_CFG_RST_M8051W_SMASK reg 1001 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, DC_DC8051_CFG_RST, reg); reg 1012 drivers/infiniband/hw/hfi1/firmware.c reg = DC_DC8051_CFG_RST_M8051W_SMASK; reg 1013 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, DC_DC8051_CFG_RST, reg); reg 1095 drivers/infiniband/hw/hfi1/firmware.c u64 reg; reg 1105 drivers/infiniband/hw/hfi1/firmware.c reg = read_csr(dd, ASIC_STS_SBUS_RESULT); reg 1106 drivers/infiniband/hw/hfi1/firmware.c result_code = (reg >> ASIC_STS_SBUS_RESULT_RESULT_CODE_SHIFT) reg 1112 drivers/infiniband/hw/hfi1/firmware.c result = (reg >> ASIC_STS_SBUS_RESULT_DATA_OUT_SHIFT) reg 1217 drivers/infiniband/hw/hfi1/firmware.c u64 reg, count = 0; reg 1226 drivers/infiniband/hw/hfi1/firmware.c reg = read_csr(dd, ASIC_STS_SBUS_RESULT); reg 1227 drivers/infiniband/hw/hfi1/firmware.c while (!((reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) && reg 1228 drivers/infiniband/hw/hfi1/firmware.c (reg & ASIC_STS_SBUS_RESULT_RCV_DATA_VALID_SMASK))) { reg 1236 drivers/infiniband/hw/hfi1/firmware.c if ((reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) && reg 1243 drivers/infiniband/hw/hfi1/firmware.c reg = read_csr(dd, ASIC_STS_SBUS_RESULT); reg 1248 drivers/infiniband/hw/hfi1/firmware.c reg = read_csr(dd, ASIC_STS_SBUS_RESULT); reg 1249 drivers/infiniband/hw/hfi1/firmware.c while (reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) { reg 1253 drivers/infiniband/hw/hfi1/firmware.c reg = read_csr(dd, ASIC_STS_SBUS_RESULT); reg 1651 drivers/infiniband/hw/hfi1/firmware.c u64 reg, count = 0; reg 1653 drivers/infiniband/hw/hfi1/firmware.c reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS); reg 1654 drivers/infiniband/hw/hfi1/firmware.c while (SBUS_COUNTER(reg, EXECUTE) != reg 1655 drivers/infiniband/hw/hfi1/firmware.c SBUS_COUNTER(reg, RCV_DATA_VALID)) { reg 1659 drivers/infiniband/hw/hfi1/firmware.c reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS); reg 1845 drivers/infiniband/hw/hfi1/init.c u64 reg; reg 1883 drivers/infiniband/hw/hfi1/init.c reg = ((u64)(rcd->rcvhdrq_cnt >> HDRQ_SIZE_SHIFT) reg 1886 drivers/infiniband/hw/hfi1/init.c write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_CNT, reg); reg 1887 drivers/infiniband/hw/hfi1/init.c reg = (encode_rcv_header_entry_size(rcd->rcvhdrqentsize) reg 1890 drivers/infiniband/hw/hfi1/init.c write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_ENT_SIZE, reg); reg 1891 drivers/infiniband/hw/hfi1/init.c reg = ((u64)DEFAULT_RCVHDRSIZE & RCV_HDR_SIZE_HDR_SIZE_MASK) reg 1893 drivers/infiniband/hw/hfi1/init.c write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_SIZE, reg); reg 788 drivers/infiniband/hw/hfi1/mad.c u64 reg; reg 790 drivers/infiniband/hw/hfi1/mad.c if (read_lcb_csr(dd, DC_LCB_STS_ROUND_TRIP_LTP_CNT, ®)) reg 793 drivers/infiniband/hw/hfi1/mad.c write_lcb_cache(DC_LCB_STS_ROUND_TRIP_LTP_CNT, reg); reg 3383 drivers/infiniband/hw/hfi1/mad.c u64 reg; reg 3429 drivers/infiniband/hw/hfi1/mad.c reg = read_csr(dd, RCV_ERR_INFO); reg 3430 drivers/infiniband/hw/hfi1/mad.c if (reg & RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK) { reg 3435 drivers/infiniband/hw/hfi1/mad.c u8 tmp = (u8)reg; reg 889 drivers/infiniband/hw/hfi1/pcie.c u64 reg; reg 891 drivers/infiniband/hw/hfi1/pcie.c reg = (((u64)1 << dd->hfi1_id) << reg 898 drivers/infiniband/hw/hfi1/pcie.c write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg); reg 987 drivers/infiniband/hw/hfi1/pcie.c u64 reg, therm; reg 1363 drivers/infiniband/hw/hfi1/pcie.c reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); reg 1364 drivers/infiniband/hw/hfi1/pcie.c dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg); reg 1365 drivers/infiniband/hw/hfi1/pcie.c if (reg == ~0ull) { /* PCIe read failed/timeout */ reg 1389 drivers/infiniband/hw/hfi1/pcie.c status = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT) reg 1400 drivers/infiniband/hw/hfi1/pcie.c err = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT) reg 77 drivers/infiniband/hw/hfi1/pio.c u64 reg, mask; reg 85 drivers/infiniband/hw/hfi1/pio.c reg = read_csr(dd, SEND_CTRL); reg 88 drivers/infiniband/hw/hfi1/pio.c reg |= SEND_CTRL_SEND_ENABLE_SMASK; reg 98 drivers/infiniband/hw/hfi1/pio.c reg = (reg & ~SEND_CTRL_UNSUPPORTED_VL_SMASK) | mask; reg 101 drivers/infiniband/hw/hfi1/pio.c reg &= ~SEND_CTRL_SEND_ENABLE_SMASK; reg 104 drivers/infiniband/hw/hfi1/pio.c reg |= SEND_CTRL_VL_ARBITER_ENABLE_SMASK; reg 107 drivers/infiniband/hw/hfi1/pio.c reg &= ~SEND_CTRL_VL_ARBITER_ENABLE_SMASK; reg 110 drivers/infiniband/hw/hfi1/pio.c __cm_reset(dd, reg); reg 114 drivers/infiniband/hw/hfi1/pio.c reg |= SEND_CTRL_UNSUPPORTED_VL_SMASK; reg 123 drivers/infiniband/hw/hfi1/pio.c write_csr(dd, SEND_CTRL, reg); reg 703 drivers/infiniband/hw/hfi1/pio.c u64 reg; reg 766 drivers/infiniband/hw/hfi1/pio.c reg = ((sci->credits & SC(CTRL_CTXT_DEPTH_MASK)) reg 770 drivers/infiniband/hw/hfi1/pio.c write_kctxt_csr(dd, hw_context, SC(CTRL), reg); reg 798 drivers/infiniband/hw/hfi1/pio.c reg = dma & SC(CREDIT_RETURN_ADDR_ADDRESS_SMASK); reg 799 drivers/infiniband/hw/hfi1/pio.c write_kctxt_csr(dd, hw_context, SC(CREDIT_RETURN_ADDR), reg); reg 822 drivers/infiniband/hw/hfi1/pio.c reg = thresh << SC(CREDIT_CTRL_THRESHOLD_SHIFT); reg 825 drivers/infiniband/hw/hfi1/pio.c reg |= SC(CREDIT_CTRL_EARLY_RETURN_SMASK); reg 827 drivers/infiniband/hw/hfi1/pio.c reg |= SC(CREDIT_CTRL_EARLY_RETURN_SMASK); reg 830 drivers/infiniband/hw/hfi1/pio.c sc->credit_ctrl = reg; reg 831 drivers/infiniband/hw/hfi1/pio.c write_kctxt_csr(dd, hw_context, SC(CREDIT_CTRL), reg); reg 835 drivers/infiniband/hw/hfi1/pio.c reg = 1ULL << 15; reg 836 drivers/infiniband/hw/hfi1/pio.c write_kctxt_csr(dd, hw_context, SC(CHECK_VL), reg); reg 921 drivers/infiniband/hw/hfi1/pio.c u64 reg; reg 929 drivers/infiniband/hw/hfi1/pio.c reg = read_kctxt_csr(sc->dd, sc->hw_context, SC(CTRL)); reg 930 drivers/infiniband/hw/hfi1/pio.c reg &= ~SC(CTRL_CTXT_ENABLE_SMASK); reg 933 drivers/infiniband/hw/hfi1/pio.c write_kctxt_csr(sc->dd, sc->hw_context, SC(CTRL), reg); reg 975 drivers/infiniband/hw/hfi1/pio.c static u64 packet_occupancy(u64 reg) reg 977 drivers/infiniband/hw/hfi1/pio.c return (reg & reg 983 drivers/infiniband/hw/hfi1/pio.c static bool egress_halted(u64 reg) reg 985 drivers/infiniband/hw/hfi1/pio.c return !!(reg & SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_HALT_STATUS_SMASK); reg 1012 drivers/infiniband/hw/hfi1/pio.c u64 reg = 0; reg 1017 drivers/infiniband/hw/hfi1/pio.c reg_prev = reg; reg 1018 drivers/infiniband/hw/hfi1/pio.c reg = read_csr(dd, sc->hw_context * 8 + reg 1022 drivers/infiniband/hw/hfi1/pio.c is_sc_halted(dd, sc->hw_context) || egress_halted(reg)) reg 1024 drivers/infiniband/hw/hfi1/pio.c reg = packet_occupancy(reg); reg 1025 drivers/infiniband/hw/hfi1/pio.c if (reg == 0) reg 1028 drivers/infiniband/hw/hfi1/pio.c if (reg != reg_prev) reg 1035 drivers/infiniband/hw/hfi1/pio.c sc->hw_context, (u32)reg); reg 1074 drivers/infiniband/hw/hfi1/pio.c u64 reg; reg 1093 drivers/infiniband/hw/hfi1/pio.c reg = read_kctxt_csr(dd, sc->hw_context, SC(STATUS)); reg 1094 drivers/infiniband/hw/hfi1/pio.c if (reg & SC(STATUS_CTXT_HALTED_SMASK)) reg 1235 drivers/infiniband/hw/hfi1/pio.c u64 reg; reg 1241 drivers/infiniband/hw/hfi1/pio.c reg = read_csr(dd, SEND_PIO_INIT_CTXT); reg 1242 drivers/infiniband/hw/hfi1/pio.c if (!(reg & SEND_PIO_INIT_CTXT_PIO_INIT_IN_PROGRESS_SMASK)) reg 1250 drivers/infiniband/hw/hfi1/pio.c return reg & SEND_PIO_INIT_CTXT_PIO_INIT_ERR_SMASK ? -EIO : 0; reg 1285 drivers/infiniband/hw/hfi1/pio.c u64 sc_ctrl, reg, pio; reg 1325 drivers/infiniband/hw/hfi1/pio.c reg = read_kctxt_csr(dd, sc->hw_context, SC(ERR_STATUS)); reg 1326 drivers/infiniband/hw/hfi1/pio.c if (reg) reg 1327 drivers/infiniband/hw/hfi1/pio.c write_kctxt_csr(dd, sc->hw_context, SC(ERR_CLEAR), reg); reg 2165 drivers/infiniband/hw/hfi1/pio.c u64 reg; reg 2177 drivers/infiniband/hw/hfi1/pio.c reg = read_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_STATUS)); reg 2181 drivers/infiniband/hw/hfi1/pio.c (reg >> SC(CREDIT_STATUS_CURRENT_FREE_COUNTER_SHIFT)) & reg 2183 drivers/infiniband/hw/hfi1/pio.c reg & SC(CREDIT_STATUS_LAST_RETURNED_COUNTER_SMASK)); reg 70 drivers/infiniband/hw/hfi1/qsfp.c u64 reg; reg 74 drivers/infiniband/hw/hfi1/qsfp.c reg = read_csr(dd, target_oe); reg 82 drivers/infiniband/hw/hfi1/qsfp.c reg &= ~QSFP_HFI0_I2CDAT; reg 84 drivers/infiniband/hw/hfi1/qsfp.c reg |= QSFP_HFI0_I2CDAT; reg 85 drivers/infiniband/hw/hfi1/qsfp.c write_csr(dd, target_oe, reg); reg 94 drivers/infiniband/hw/hfi1/qsfp.c u64 reg; reg 98 drivers/infiniband/hw/hfi1/qsfp.c reg = read_csr(dd, target_oe); reg 106 drivers/infiniband/hw/hfi1/qsfp.c reg &= ~QSFP_HFI0_I2CCLK; reg 108 drivers/infiniband/hw/hfi1/qsfp.c reg |= QSFP_HFI0_I2CCLK; reg 109 drivers/infiniband/hw/hfi1/qsfp.c write_csr(dd, target_oe, reg); reg 117 drivers/infiniband/hw/hfi1/qsfp.c u64 reg; reg 124 drivers/infiniband/hw/hfi1/qsfp.c reg = read_csr(bus->controlling_dd, target_in); reg 125 drivers/infiniband/hw/hfi1/qsfp.c return !!(reg & QSFP_HFI0_I2CDAT); reg 131 drivers/infiniband/hw/hfi1/qsfp.c u64 reg; reg 138 drivers/infiniband/hw/hfi1/qsfp.c reg = read_csr(bus->controlling_dd, target_in); reg 139 drivers/infiniband/hw/hfi1/qsfp.c return !!(reg & QSFP_HFI0_I2CCLK); reg 686 drivers/infiniband/hw/hfi1/qsfp.c u64 reg; reg 688 drivers/infiniband/hw/hfi1/qsfp.c reg = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_IN : ASIC_QSFP1_IN); reg 689 drivers/infiniband/hw/hfi1/qsfp.c return !(reg & QSFP_HFI0_MODPRST_N); reg 312 drivers/infiniband/hw/hfi1/sdma.c u64 reg = 0; reg 315 drivers/infiniband/hw/hfi1/sdma.c reg_prev = reg; reg 316 drivers/infiniband/hw/hfi1/sdma.c reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS); reg 318 drivers/infiniband/hw/hfi1/sdma.c reg &= SDMA_EGRESS_PACKET_OCCUPANCY_SMASK; reg 319 drivers/infiniband/hw/hfi1/sdma.c reg >>= SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT; reg 320 drivers/infiniband/hw/hfi1/sdma.c if (reg == 0) reg 323 drivers/infiniband/hw/hfi1/sdma.c if (reg != reg_prev) reg 328 drivers/infiniband/hw/hfi1/sdma.c __func__, sde->this_idx, (u32)reg); reg 354 drivers/infiniband/hw/hfi1/sdma.c u64 reg; reg 358 drivers/infiniband/hw/hfi1/sdma.c reg = cnt; reg 359 drivers/infiniband/hw/hfi1/sdma.c reg &= SD(DESC_CNT_CNT_MASK); reg 360 drivers/infiniband/hw/hfi1/sdma.c reg <<= SD(DESC_CNT_CNT_SHIFT); reg 361 drivers/infiniband/hw/hfi1/sdma.c write_sde_csr(sde, SD(DESC_CNT), reg); reg 2022 drivers/infiniband/hw/hfi1/sdma.c u64 reg; reg 2033 drivers/infiniband/hw/hfi1/sdma.c reg = SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_MASK) << reg 2035 drivers/infiniband/hw/hfi1/sdma.c write_sde_csr(sde, SD(ENG_ERR_CLEAR), reg); reg 2085 drivers/infiniband/hw/hfi1/sdma.c #define sdma_dumpstate_helper0(reg) do { \ reg 2086 drivers/infiniband/hw/hfi1/sdma.c csr = read_csr(sde->dd, reg); \ reg 2087 drivers/infiniband/hw/hfi1/sdma.c dd_dev_err(sde->dd, "%36s 0x%016llx\n", #reg, csr); \ reg 2090 drivers/infiniband/hw/hfi1/sdma.c #define sdma_dumpstate_helper(reg) do { \ reg 2091 drivers/infiniband/hw/hfi1/sdma.c csr = read_sde_csr(sde, reg); \ reg 2093 drivers/infiniband/hw/hfi1/sdma.c #reg, sde->this_idx, csr); \ reg 2096 drivers/infiniband/hw/hfi1/sdma.c #define sdma_dumpstate_helper2(reg) do { \ reg 2097 drivers/infiniband/hw/hfi1/sdma.c csr = read_csr(sde->dd, reg + (8 * i)); \ reg 2099 drivers/infiniband/hw/hfi1/sdma.c #reg, i, csr); \ reg 733 drivers/infiniband/hw/hfi1/tid_rdma.c u64 reg; reg 735 drivers/infiniband/hw/hfi1/tid_rdma.c reg = ((u64)generation << HFI1_KDETH_BTH_SEQ_SHIFT) | reg 743 drivers/infiniband/hw/hfi1/tid_rdma.c reg |= RCV_TID_FLOW_TABLE_CTRL_HDR_SUPP_EN_SMASK; reg 746 drivers/infiniband/hw/hfi1/tid_rdma.c RCV_TID_FLOW_TABLE + 8 * flow_idx, reg); reg 5475 drivers/infiniband/hw/hfi1/tid_rdma.c u64 reg; reg 5481 drivers/infiniband/hw/hfi1/tid_rdma.c reg = read_uctxt_csr(dd, ctxt, RCV_TID_FLOW_TABLE + (8 * fidx)); reg 5482 drivers/infiniband/hw/hfi1/tid_rdma.c return mask_psn(reg); reg 40 drivers/infiniband/hw/hns/hns_roce_common.h #define roce_write(dev, reg, val) writel((val), (dev)->reg_base + (reg)) reg 41 drivers/infiniband/hw/hns/hns_roce_common.h #define roce_read(dev, reg) readl((dev)->reg_base + (reg)) reg 215 drivers/infiniband/hw/i40iw/i40iw_osdep.h void i40iw_wr32(struct i40iw_hw *hw, u32 reg, u32 value); reg 216 drivers/infiniband/hw/i40iw/i40iw_osdep.h u32 i40iw_rd32(struct i40iw_hw *hw, u32 reg); reg 122 drivers/infiniband/hw/i40iw/i40iw_utils.c inline void i40iw_wr32(struct i40iw_hw *hw, u32 reg, u32 value) reg 124 drivers/infiniband/hw/i40iw/i40iw_utils.c writel(value, hw->hw_addr + reg); reg 134 drivers/infiniband/hw/i40iw/i40iw_utils.c inline u32 i40iw_rd32(struct i40iw_hw *hw, u32 reg) reg 136 drivers/infiniband/hw/i40iw/i40iw_utils.c return readl(hw->hw_addr + reg); reg 2277 drivers/infiniband/hw/qib/qib_iba6120.c static u64 qib_portcntr_6120(struct qib_pportdata *ppd, u32 reg) reg 2320 drivers/infiniband/hw/qib/qib_iba6120.c if (reg >= ARRAY_SIZE(xlator)) { reg 2322 drivers/infiniband/hw/qib/qib_iba6120.c "Unimplemented portcounter %u\n", reg); reg 2325 drivers/infiniband/hw/qib/qib_iba6120.c creg = xlator[reg]; reg 2328 drivers/infiniband/hw/qib/qib_iba6120.c if (reg == QIBPORTCNTR_LLI) reg 2330 drivers/infiniband/hw/qib/qib_iba6120.c else if (reg == QIBPORTCNTR_EXCESSBUFOVFL) reg 2332 drivers/infiniband/hw/qib/qib_iba6120.c else if (reg == QIBPORTCNTR_KHDROVFL) { reg 2338 drivers/infiniband/hw/qib/qib_iba6120.c } else if (reg == QIBPORTCNTR_PSSTAT) reg 2361 drivers/infiniband/hw/qib/qib_iba6120.c if (reg == QIBPORTCNTR_RXDROPPKT) /* add special cased count */ reg 2902 drivers/infiniband/hw/qib/qib_iba7220.c static u64 qib_portcntr_7220(struct qib_pportdata *ppd, u32 reg) reg 2945 drivers/infiniband/hw/qib/qib_iba7220.c if (reg >= ARRAY_SIZE(xlator)) { reg 2947 drivers/infiniband/hw/qib/qib_iba7220.c "Unimplemented portcounter %u\n", reg); reg 2950 drivers/infiniband/hw/qib/qib_iba7220.c creg = xlator[reg]; reg 2952 drivers/infiniband/hw/qib/qib_iba7220.c if (reg == QIBPORTCNTR_KHDROVFL) { reg 3444 drivers/infiniband/hw/qib/qib_iba7322.c int lsb, reg, sh; reg 3508 drivers/infiniband/hw/qib/qib_iba7322.c reg = lsb / IBA7322_REDIRECT_VEC_PER_REG; reg 3512 drivers/infiniband/hw/qib/qib_iba7322.c redirect[reg] |= ((u64) msixnum) << sh; reg 4731 drivers/infiniband/hw/qib/qib_iba7322.c static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg) reg 4780 drivers/infiniband/hw/qib/qib_iba7322.c if (reg >= ARRAY_SIZE(xlator)) { reg 4782 drivers/infiniband/hw/qib/qib_iba7322.c "Unimplemented portcounter %u\n", reg); reg 4785 drivers/infiniband/hw/qib/qib_iba7322.c creg = xlator[reg] & _PORT_CNTR_IDXMASK; reg 4788 drivers/infiniband/hw/qib/qib_iba7322.c if (reg == QIBPORTCNTR_KHDROVFL) { reg 4800 drivers/infiniband/hw/qib/qib_iba7322.c } else if (reg == QIBPORTCNTR_RXDROPPKT) { reg 4807 drivers/infiniband/hw/qib/qib_iba7322.c } else if (reg == QIBPORTCNTR_PSINTERVAL || reg 4808 drivers/infiniband/hw/qib/qib_iba7322.c reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) { reg 4818 drivers/infiniband/hw/qib/qib_iba7322.c if (xlator[reg] & _PORT_64BIT_FLAG) reg 6746 drivers/infiniband/hw/qib/qib_iba7322.c u64 reg, reg1, reg2; reg 6748 drivers/infiniband/hw/qib/qib_iba7322.c reg = qib_read_kreg_port(ppd, krp_senddmastatus); reg 6750 drivers/infiniband/hw/qib/qib_iba7322.c "SDMA senddmastatus: 0x%016llx\n", reg); reg 6752 drivers/infiniband/hw/qib/qib_iba7322.c reg = qib_read_kreg_port(ppd, krp_sendctrl); reg 6754 drivers/infiniband/hw/qib/qib_iba7322.c "SDMA sendctrl: 0x%016llx\n", reg); reg 6756 drivers/infiniband/hw/qib/qib_iba7322.c reg = qib_read_kreg_port(ppd, krp_senddmabase); reg 6758 drivers/infiniband/hw/qib/qib_iba7322.c "SDMA senddmabase: 0x%016llx\n", reg); reg 6760 drivers/infiniband/hw/qib/qib_iba7322.c reg = qib_read_kreg_port(ppd, krp_senddmabufmask0); reg 6765 drivers/infiniband/hw/qib/qib_iba7322.c reg, reg1, reg2); reg 6768 drivers/infiniband/hw/qib/qib_iba7322.c reg = qib_read_kreg_port(ppd, krp_senddmabuf_use0); reg 6769 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg); reg 6777 drivers/infiniband/hw/qib/qib_iba7322.c reg, reg1, reg2); reg 6778 drivers/infiniband/hw/qib/qib_iba7322.c reg = qib_read_kreg_port(ppd, krp_senddmabuf_use0); reg 6784 drivers/infiniband/hw/qib/qib_iba7322.c reg, reg1, reg2); reg 6786 drivers/infiniband/hw/qib/qib_iba7322.c reg = qib_read_kreg_port(ppd, krp_senddmatail); reg 6788 drivers/infiniband/hw/qib/qib_iba7322.c "SDMA senddmatail: 0x%016llx\n", reg); reg 6790 drivers/infiniband/hw/qib/qib_iba7322.c reg = qib_read_kreg_port(ppd, krp_senddmahead); reg 6792 drivers/infiniband/hw/qib/qib_iba7322.c "SDMA senddmahead: 0x%016llx\n", reg); reg 6794 drivers/infiniband/hw/qib/qib_iba7322.c reg = qib_read_kreg_port(ppd, krp_senddmaheadaddr); reg 6796 drivers/infiniband/hw/qib/qib_iba7322.c "SDMA senddmaheadaddr: 0x%016llx\n", reg); reg 6798 drivers/infiniband/hw/qib/qib_iba7322.c reg = qib_read_kreg_port(ppd, krp_senddmalengen); reg 6800 drivers/infiniband/hw/qib/qib_iba7322.c "SDMA senddmalengen: 0x%016llx\n", reg); reg 6802 drivers/infiniband/hw/qib/qib_iba7322.c reg = qib_read_kreg_port(ppd, krp_senddmadesccnt); reg 6804 drivers/infiniband/hw/qib/qib_iba7322.c "SDMA senddmadesccnt: 0x%016llx\n", reg); reg 6806 drivers/infiniband/hw/qib/qib_iba7322.c reg = qib_read_kreg_port(ppd, krp_senddmaidlecnt); reg 6808 drivers/infiniband/hw/qib/qib_iba7322.c "SDMA senddmaidlecnt: 0x%016llx\n", reg); reg 6810 drivers/infiniband/hw/qib/qib_iba7322.c reg = qib_read_kreg_port(ppd, krp_senddmaprioritythld); reg 6812 drivers/infiniband/hw/qib/qib_iba7322.c "SDMA senddmapriorityhld: 0x%016llx\n", reg); reg 6814 drivers/infiniband/hw/qib/qib_iba7322.c reg = qib_read_kreg_port(ppd, krp_senddmareloadcnt); reg 6816 drivers/infiniband/hw/qib/qib_iba7322.c "SDMA senddmareloadcnt: 0x%016llx\n", reg); reg 88 drivers/infiniband/hw/qib/qib_sd7220.c #define EPB_LOC(chn, elt, reg) \ reg 89 drivers/infiniband/hw/qib/qib_sd7220.c (((elt & 0xf) | ((chn & 7) << 4) | ((reg & 0x3f) << 9)) << \ reg 621 drivers/infiniband/hw/qib/qib_sd7220.c static int epb_trans(struct qib_devdata *dd, u16 reg, u64 i_val, u64 *o_vp) reg 626 drivers/infiniband/hw/qib/qib_sd7220.c qib_write_kreg(dd, reg, i_val); reg 628 drivers/infiniband/hw/qib/qib_sd7220.c transval = qib_read_kreg64(dd, reg); reg 631 drivers/infiniband/hw/qib/qib_sd7220.c transval = qib_read_kreg32(dd, reg); reg 1194 drivers/infiniband/hw/qib/qib_sd7220.c int idx, reg, data; reg 1199 drivers/infiniband/hw/qib/qib_sd7220.c reg = (regmap & 0xF); reg 1203 drivers/infiniband/hw/qib/qib_sd7220.c ret = ibsd_mod_allchnls(dd, EPB_LOC(0, 9, reg), data, 0xFF); reg 1221 drivers/infiniband/hw/qib/qib_sd7220.c int elt, reg, val, loc; reg 1224 drivers/infiniband/hw/qib/qib_sd7220.c reg = rxeq_init_vals[ridx].rdesc >> 4; reg 1225 drivers/infiniband/hw/qib/qib_sd7220.c loc = EPB_LOC(0, elt, reg); reg 299 drivers/infiniband/hw/vmw_pvrdma/pvrdma.h static inline void pvrdma_write_reg(struct pvrdma_dev *dev, u32 reg, u32 val) reg 301 drivers/infiniband/hw/vmw_pvrdma/pvrdma.h writel(cpu_to_le32(val), dev->regs + reg); reg 304 drivers/infiniband/hw/vmw_pvrdma/pvrdma.h static inline u32 pvrdma_read_reg(struct pvrdma_dev *dev, u32 reg) reg 306 drivers/infiniband/hw/vmw_pvrdma/pvrdma.h return le32_to_cpu(readl(dev->regs + reg)); reg 646 drivers/infiniband/sw/rxe/rxe_req.c struct rxe_mem *rmr = to_rmr(wqe->wr.wr.reg.mr); reg 649 drivers/infiniband/sw/rxe/rxe_req.c rmr->access = wqe->wr.wr.reg.access; reg 650 drivers/infiniband/sw/rxe/rxe_req.c rmr->lkey = wqe->wr.wr.reg.key; reg 651 drivers/infiniband/sw/rxe/rxe_req.c rmr->rkey = wqe->wr.wr.reg.key; reg 652 drivers/infiniband/sw/rxe/rxe_req.c rmr->iova = wqe->wr.wr.reg.mr->iova; reg 576 drivers/infiniband/sw/rxe/rxe_verbs.c wr->wr.reg.mr = reg_wr(ibwr)->mr; reg 577 drivers/infiniband/sw/rxe/rxe_verbs.c wr->wr.reg.key = reg_wr(ibwr)->key; reg 578 drivers/infiniband/sw/rxe/rxe_verbs.c wr->wr.reg.access = reg_wr(ibwr)->access; reg 336 drivers/infiniband/ulp/iser/iscsi_iser.h struct iser_mem_reg *reg); reg 192 drivers/infiniband/ulp/iser/iser_memory.c struct iser_mem_reg *reg) reg 196 drivers/infiniband/ulp/iser/iser_memory.c reg->sge.lkey = device->pd->local_dma_lkey; reg 203 drivers/infiniband/ulp/iser/iser_memory.c reg->rkey = device->pd->unsafe_global_rkey; reg 205 drivers/infiniband/ulp/iser/iser_memory.c reg->rkey = 0; reg 206 drivers/infiniband/ulp/iser/iser_memory.c reg->sge.addr = sg_dma_address(&sg[0]); reg 207 drivers/infiniband/ulp/iser/iser_memory.c reg->sge.length = sg_dma_len(&sg[0]); reg 210 drivers/infiniband/ulp/iser/iser_memory.c " length=0x%x\n", reg->sge.lkey, reg->rkey, reg 211 drivers/infiniband/ulp/iser/iser_memory.c reg->sge.addr, reg->sge.length); reg 230 drivers/infiniband/ulp/iser/iser_memory.c struct iser_mem_reg *reg) reg 258 drivers/infiniband/ulp/iser/iser_memory.c reg->sge.lkey = fmr->fmr->lkey; reg 259 drivers/infiniband/ulp/iser/iser_memory.c reg->rkey = fmr->fmr->rkey; reg 260 drivers/infiniband/ulp/iser/iser_memory.c reg->sge.addr = page_vec->fake_mr.iova; reg 261 drivers/infiniband/ulp/iser/iser_memory.c reg->sge.length = page_vec->fake_mr.length; reg 262 drivers/infiniband/ulp/iser/iser_memory.c reg->mem_h = fmr; reg 265 drivers/infiniband/ulp/iser/iser_memory.c " length=0x%x\n", reg->sge.lkey, reg->rkey, reg 266 drivers/infiniband/ulp/iser/iser_memory.c reg->sge.addr, reg->sge.length); reg 278 drivers/infiniband/ulp/iser/iser_memory.c struct iser_mem_reg *reg = &iser_task->rdma_reg[cmd_dir]; reg 280 drivers/infiniband/ulp/iser/iser_memory.c if (!reg->mem_h) reg 283 drivers/infiniband/ulp/iser/iser_memory.c iser_dbg("PHYSICAL Mem.Unregister mem_h %p\n", reg->mem_h); reg 285 drivers/infiniband/ulp/iser/iser_memory.c ib_fmr_pool_unmap((struct ib_pool_fmr *)reg->mem_h); reg 287 drivers/infiniband/ulp/iser/iser_memory.c reg->mem_h = NULL; reg 294 drivers/infiniband/ulp/iser/iser_memory.c struct iser_mem_reg *reg = &iser_task->rdma_reg[cmd_dir]; reg 296 drivers/infiniband/ulp/iser/iser_memory.c if (!reg->mem_h) reg 300 drivers/infiniband/ulp/iser/iser_memory.c reg->mem_h); reg 301 drivers/infiniband/ulp/iser/iser_memory.c reg->mem_h = NULL; reg 441 drivers/infiniband/ulp/iser/iser_memory.c struct iser_mem_reg *reg) reg 474 drivers/infiniband/ulp/iser/iser_memory.c reg->sge.lkey = mr->lkey; reg 475 drivers/infiniband/ulp/iser/iser_memory.c reg->rkey = mr->rkey; reg 476 drivers/infiniband/ulp/iser/iser_memory.c reg->sge.addr = mr->iova; reg 477 drivers/infiniband/ulp/iser/iser_memory.c reg->sge.length = mr->length; reg 480 drivers/infiniband/ulp/iser/iser_memory.c reg->sge.lkey, reg->rkey, reg->sge.addr, reg->sge.length); reg 490 drivers/infiniband/ulp/iser/iser_memory.c struct iser_mem_reg *reg) reg 495 drivers/infiniband/ulp/iser/iser_memory.c return iser_reg_dma(device, mem, reg); reg 497 drivers/infiniband/ulp/iser/iser_memory.c return device->reg_ops->reg_mem(task, mem, &desc->rsc, reg); reg 507 drivers/infiniband/ulp/iser/iser_memory.c struct iser_mem_reg *reg = &task->rdma_reg[dir]; reg 517 drivers/infiniband/ulp/iser/iser_memory.c reg->mem_h = desc; reg 521 drivers/infiniband/ulp/iser/iser_memory.c err = iser_reg_data_sg(task, mem, desc, use_dma_key, reg); reg 526 drivers/infiniband/ulp/iser/iser_memory.c &desc->rsc, reg); reg 1073 drivers/infiniband/ulp/iser/iser_verbs.c struct iser_mem_reg *reg = &iser_task->rdma_reg[cmd_dir]; reg 1074 drivers/infiniband/ulp/iser/iser_verbs.c struct iser_fr_desc *desc = reg->mem_h; reg 1672 drivers/infiniband/ulp/isert/ib_isert.c ret = isert_check_pi_status(cmd, isert_cmd->rw.reg->mr); reg 1718 drivers/infiniband/ulp/isert/ib_isert.c ret = isert_check_pi_status(se_cmd, isert_cmd->rw.reg->mr); reg 58 drivers/input/keyboard/adp5588-keys.c static int adp5588_read(struct i2c_client *client, u8 reg) reg 60 drivers/input/keyboard/adp5588-keys.c int ret = i2c_smbus_read_byte_data(client, reg); reg 68 drivers/input/keyboard/adp5588-keys.c static int adp5588_write(struct i2c_client *client, u8 reg, u8 val) reg 70 drivers/input/keyboard/adp5588-keys.c return i2c_smbus_write_byte_data(client, reg, val); reg 226 drivers/input/keyboard/adp5589-keys.c u8 (*reg) (u8 reg); reg 266 drivers/input/keyboard/adp5589-keys.c static unsigned char adp5589_reg(unsigned char reg) reg 268 drivers/input/keyboard/adp5589-keys.c return reg; reg 288 drivers/input/keyboard/adp5589-keys.c .reg = adp5589_reg, reg 347 drivers/input/keyboard/adp5589-keys.c static unsigned char adp5585_reg(unsigned char reg) reg 349 drivers/input/keyboard/adp5589-keys.c return adp5585_reg_lut[reg]; reg 369 drivers/input/keyboard/adp5589-keys.c .reg = adp5585_reg, reg 372 drivers/input/keyboard/adp5589-keys.c static int adp5589_read(struct i2c_client *client, u8 reg) reg 374 drivers/input/keyboard/adp5589-keys.c int ret = i2c_smbus_read_byte_data(client, reg); reg 382 drivers/input/keyboard/adp5589-keys.c static int adp5589_write(struct i2c_client *client, u8 reg, u8 val) reg 384 drivers/input/keyboard/adp5589-keys.c return i2c_smbus_write_byte_data(client, reg, val); reg 395 drivers/input/keyboard/adp5589-keys.c kpad->var->reg(ADP5589_GPI_STATUS_A) + bank) & reg 413 drivers/input/keyboard/adp5589-keys.c adp5589_write(kpad->client, kpad->var->reg(ADP5589_GPO_DATA_OUT_A) + reg 430 drivers/input/keyboard/adp5589-keys.c kpad->var->reg(ADP5589_GPIO_DIRECTION_A) + bank, reg 455 drivers/input/keyboard/adp5589-keys.c ret = adp5589_write(kpad->client, kpad->var->reg(ADP5589_GPO_DATA_OUT_A) reg 458 drivers/input/keyboard/adp5589-keys.c kpad->var->reg(ADP5589_GPIO_DIRECTION_A) + bank, reg 536 drivers/input/keyboard/adp5589-keys.c kpad->dat_out[i] = adp5589_read(kpad->client, kpad->var->reg( reg 538 drivers/input/keyboard/adp5589-keys.c kpad->dir[i] = adp5589_read(kpad->client, kpad->var->reg( reg 660 drivers/input/keyboard/adp5589-keys.c u8 (*reg) (u8) = kpad->var->reg; reg 665 drivers/input/keyboard/adp5589-keys.c ret = adp5589_write(client, reg(ADP5589_PIN_CONFIG_A), reg 667 drivers/input/keyboard/adp5589-keys.c ret |= adp5589_write(client, reg(ADP5589_PIN_CONFIG_B), reg 703 drivers/input/keyboard/adp5589-keys.c ret |= adp5589_write(client, reg(ADP5589_GPI_EVENT_EN_A), reg 705 drivers/input/keyboard/adp5589-keys.c ret |= adp5589_write(client, reg(ADP5589_GPI_EVENT_EN_B), reg 709 drivers/input/keyboard/adp5589-keys.c reg(ADP5589_GPI_EVENT_EN_C), reg 731 drivers/input/keyboard/adp5589-keys.c ret |= adp5589_write(client, reg(ADP5585_RPULL_CONFIG_A) reg 752 drivers/input/keyboard/adp5589-keys.c reg(ADP5585_RPULL_CONFIG_C) + reg 759 drivers/input/keyboard/adp5589-keys.c ret |= adp5589_write(client, reg(ADP5589_RESET1_EVENT_A), reg 762 drivers/input/keyboard/adp5589-keys.c ret |= adp5589_write(client, reg(ADP5589_RESET1_EVENT_B), reg 765 drivers/input/keyboard/adp5589-keys.c ret |= adp5589_write(client, reg(ADP5589_RESET1_EVENT_C), reg 772 drivers/input/keyboard/adp5589-keys.c ret |= adp5589_write(client, reg(ADP5589_RESET2_EVENT_A), reg 775 drivers/input/keyboard/adp5589-keys.c ret |= adp5589_write(client, reg(ADP5589_RESET2_EVENT_B), reg 782 drivers/input/keyboard/adp5589-keys.c ret |= adp5589_write(client, reg(ADP5589_RESET_CFG), reg 784 drivers/input/keyboard/adp5589-keys.c ret |= adp5589_write(client, reg(ADP5589_PIN_CONFIG_D), reg 788 drivers/input/keyboard/adp5589-keys.c ret |= adp5589_write(client, reg(ADP5589_DEBOUNCE_DIS_A), reg 791 drivers/input/keyboard/adp5589-keys.c ret |= adp5589_write(client, reg(ADP5589_DEBOUNCE_DIS_B), reg 796 drivers/input/keyboard/adp5589-keys.c ret |= adp5589_write(client, reg(ADP5589_DEBOUNCE_DIS_C), reg 799 drivers/input/keyboard/adp5589-keys.c ret |= adp5589_write(client, reg(ADP5589_POLL_PTIME_CFG), reg 807 drivers/input/keyboard/adp5589-keys.c ret |= adp5589_write(client, reg(ADP5589_GENERAL_CFG), reg 809 drivers/input/keyboard/adp5589-keys.c ret |= adp5589_write(client, reg(ADP5589_INT_EN), reg 825 drivers/input/keyboard/adp5589-keys.c kpad->var->reg(ADP5589_GPI_STATUS_A)); reg 827 drivers/input/keyboard/adp5589-keys.c kpad->var->reg(ADP5589_GPI_STATUS_B)); reg 1052 drivers/input/keyboard/adp5589-keys.c adp5589_write(client, kpad->var->reg(ADP5589_GENERAL_CFG), 0); reg 75 drivers/input/keyboard/cap11xx.c u32 reg; reg 143 drivers/input/keyboard/cap11xx.c static bool cap11xx_volatile_reg(struct device *dev, unsigned int reg) reg 145 drivers/input/keyboard/cap11xx.c switch (reg) { reg 244 drivers/input/keyboard/cap11xx.c BIT(led->reg), reg 245 drivers/input/keyboard/cap11xx.c value ? BIT(led->reg) : 0); reg 281 drivers/input/keyboard/cap11xx.c u32 reg; reg 292 drivers/input/keyboard/cap11xx.c error = of_property_read_u32(child, "reg", ®); reg 293 drivers/input/keyboard/cap11xx.c if (error != 0 || reg >= num_leds) { reg 298 drivers/input/keyboard/cap11xx.c led->reg = reg; reg 64 drivers/input/keyboard/max7359_keypad.c static int max7359_write_reg(struct i2c_client *client, u8 reg, u8 val) reg 66 drivers/input/keyboard/max7359_keypad.c int ret = i2c_smbus_write_byte_data(client, reg, val); reg 70 drivers/input/keyboard/max7359_keypad.c __func__, reg, val, ret); reg 74 drivers/input/keyboard/max7359_keypad.c static int max7359_read_reg(struct i2c_client *client, int reg) reg 76 drivers/input/keyboard/max7359_keypad.c int ret = i2c_smbus_read_byte_data(client, reg); reg 80 drivers/input/keyboard/max7359_keypad.c __func__, reg, ret); reg 125 drivers/input/keyboard/mpr121_touchkey.c int reg; reg 127 drivers/input/keyboard/mpr121_touchkey.c reg = i2c_smbus_read_byte_data(client, ELE_TOUCH_STATUS_1_ADDR); reg 128 drivers/input/keyboard/mpr121_touchkey.c if (reg < 0) { reg 129 drivers/input/keyboard/mpr121_touchkey.c dev_err(&client->dev, "i2c read error [%d]\n", reg); reg 133 drivers/input/keyboard/mpr121_touchkey.c reg <<= 8; reg 134 drivers/input/keyboard/mpr121_touchkey.c reg |= i2c_smbus_read_byte_data(client, ELE_TOUCH_STATUS_0_ADDR); reg 135 drivers/input/keyboard/mpr121_touchkey.c if (reg < 0) { reg 136 drivers/input/keyboard/mpr121_touchkey.c dev_err(&client->dev, "i2c read error [%d]\n", reg); reg 140 drivers/input/keyboard/mpr121_touchkey.c reg &= TOUCH_STATUS_MASK; reg 142 drivers/input/keyboard/mpr121_touchkey.c bit_changed = reg ^ mpr121->statusbits; reg 143 drivers/input/keyboard/mpr121_touchkey.c mpr121->statusbits = reg; reg 147 drivers/input/keyboard/mpr121_touchkey.c pressed = reg & BIT(key_num); reg 166 drivers/input/keyboard/mpr121_touchkey.c const struct mpr121_init_register *reg; reg 184 drivers/input/keyboard/mpr121_touchkey.c reg = &init_reg_table[i]; reg 185 drivers/input/keyboard/mpr121_touchkey.c ret = i2c_smbus_write_byte_data(client, reg->addr, reg->val); reg 153 drivers/input/keyboard/qt1050.c static bool qt1050_volatile_reg(struct device *dev, unsigned int reg) reg 155 drivers/input/keyboard/qt1050.c switch (reg) { reg 56 drivers/input/keyboard/qt1070.c static int qt1070_read(struct i2c_client *client, u8 reg) reg 60 drivers/input/keyboard/qt1070.c ret = i2c_smbus_read_byte_data(client, reg); reg 68 drivers/input/keyboard/qt1070.c static int qt1070_write(struct i2c_client *client, u8 reg, u8 data) reg 72 drivers/input/keyboard/qt1070.c ret = i2c_smbus_write_byte_data(client, reg, data); reg 65 drivers/input/keyboard/qt2160.c static int qt2160_read(struct i2c_client *client, u8 reg); reg 66 drivers/input/keyboard/qt2160.c static int qt2160_write(struct i2c_client *client, u8 reg, u8 data); reg 225 drivers/input/keyboard/qt2160.c static int qt2160_read(struct i2c_client *client, u8 reg) reg 229 drivers/input/keyboard/qt2160.c ret = i2c_smbus_write_byte(client, reg); reg 246 drivers/input/keyboard/qt2160.c static int qt2160_write(struct i2c_client *client, u8 reg, u8 data) reg 250 drivers/input/keyboard/qt2160.c ret = i2c_smbus_write_byte_data(client, reg, data); reg 54 drivers/input/keyboard/tca6416-keypad.c static int tca6416_write_reg(struct tca6416_keypad_chip *chip, int reg, u16 val) reg 59 drivers/input/keyboard/tca6416-keypad.c i2c_smbus_write_word_data(chip->client, reg << 1, val) : reg 60 drivers/input/keyboard/tca6416-keypad.c i2c_smbus_write_byte_data(chip->client, reg, val); reg 64 drivers/input/keyboard/tca6416-keypad.c __func__, reg, val, error); reg 71 drivers/input/keyboard/tca6416-keypad.c static int tca6416_read_reg(struct tca6416_keypad_chip *chip, int reg, u16 *val) reg 76 drivers/input/keyboard/tca6416-keypad.c i2c_smbus_read_word_data(chip->client, reg << 1) : reg 77 drivers/input/keyboard/tca6416-keypad.c i2c_smbus_read_byte_data(chip->client, reg); reg 80 drivers/input/keyboard/tca6416-keypad.c __func__, reg, retval); reg 123 drivers/input/keyboard/tca8418_keypad.c int reg, u8 val) reg 127 drivers/input/keyboard/tca8418_keypad.c error = i2c_smbus_write_byte_data(keypad_data->client, reg, val); reg 131 drivers/input/keyboard/tca8418_keypad.c __func__, reg, val, error); reg 142 drivers/input/keyboard/tca8418_keypad.c int reg, u8 *val) reg 146 drivers/input/keyboard/tca8418_keypad.c error = i2c_smbus_read_byte_data(keypad_data->client, reg); reg 150 drivers/input/keyboard/tca8418_keypad.c __func__, reg, error); reg 164 drivers/input/keyboard/tca8418_keypad.c u8 reg, state, code; reg 167 drivers/input/keyboard/tca8418_keypad.c error = tca8418_read_byte(keypad_data, REG_KEY_EVENT_A, ®); reg 175 drivers/input/keyboard/tca8418_keypad.c if (reg <= 0) reg 178 drivers/input/keyboard/tca8418_keypad.c state = reg & KEY_EVENT_VALUE; reg 179 drivers/input/keyboard/tca8418_keypad.c code = reg & KEY_EVENT_CODE; reg 202 drivers/input/keyboard/tca8418_keypad.c u8 reg; reg 205 drivers/input/keyboard/tca8418_keypad.c error = tca8418_read_byte(keypad_data, REG_INT_STAT, ®); reg 212 drivers/input/keyboard/tca8418_keypad.c if (!reg) reg 215 drivers/input/keyboard/tca8418_keypad.c if (reg & INT_STAT_OVR_FLOW_INT) reg 218 drivers/input/keyboard/tca8418_keypad.c if (reg & INT_STAT_K_INT) reg 222 drivers/input/keyboard/tca8418_keypad.c reg = 0xff; reg 223 drivers/input/keyboard/tca8418_keypad.c error = tca8418_write_byte(keypad_data, REG_INT_STAT, reg); reg 237 drivers/input/keyboard/tca8418_keypad.c int reg, error = 0; reg 240 drivers/input/keyboard/tca8418_keypad.c reg = ~(~0 << rows); reg 241 drivers/input/keyboard/tca8418_keypad.c reg += (~(~0 << cols)) << 8; reg 244 drivers/input/keyboard/tca8418_keypad.c error |= tca8418_write_byte(keypad_data, REG_KP_GPIO1, reg); reg 245 drivers/input/keyboard/tca8418_keypad.c error |= tca8418_write_byte(keypad_data, REG_KP_GPIO2, reg >> 8); reg 246 drivers/input/keyboard/tca8418_keypad.c error |= tca8418_write_byte(keypad_data, REG_KP_GPIO3, reg >> 16); reg 249 drivers/input/keyboard/tca8418_keypad.c error |= tca8418_write_byte(keypad_data, REG_DEBOUNCE_DIS1, reg); reg 250 drivers/input/keyboard/tca8418_keypad.c error |= tca8418_write_byte(keypad_data, REG_DEBOUNCE_DIS2, reg >> 8); reg 251 drivers/input/keyboard/tca8418_keypad.c error |= tca8418_write_byte(keypad_data, REG_DEBOUNCE_DIS3, reg >> 16); reg 270 drivers/input/keyboard/tca8418_keypad.c u8 reg; reg 304 drivers/input/keyboard/tca8418_keypad.c error = tca8418_read_byte(keypad_data, REG_KEY_LCK_EC, ®); reg 126 drivers/input/keyboard/twl4030_keypad.c u8 *data, u32 reg, u8 num_bytes) reg 128 drivers/input/keyboard/twl4030_keypad.c int ret = twl_i2c_read(TWL4030_MODULE_KEYPAD, data, reg, num_bytes); reg 133 drivers/input/keyboard/twl4030_keypad.c reg, ret, ret); reg 138 drivers/input/keyboard/twl4030_keypad.c static int twl4030_kpwrite_u8(struct twl4030_keypad *kp, u8 data, u32 reg) reg 140 drivers/input/keyboard/twl4030_keypad.c int ret = twl_i2c_write_u8(TWL4030_MODULE_KEYPAD, data, reg); reg 145 drivers/input/keyboard/twl4030_keypad.c reg, ret, ret); reg 247 drivers/input/keyboard/twl4030_keypad.c u8 reg; reg 251 drivers/input/keyboard/twl4030_keypad.c ret = twl4030_kpread(kp, ®, KEYP_ISR1, 1); reg 257 drivers/input/keyboard/twl4030_keypad.c if (ret >= 0 && (reg & KEYP_IMR1_KP)) reg 267 drivers/input/keyboard/twl4030_keypad.c u8 reg; reg 271 drivers/input/keyboard/twl4030_keypad.c reg = KEYP_CTRL_SOFT_NRST | KEYP_CTRL_SOFTMODEN reg 273 drivers/input/keyboard/twl4030_keypad.c if (twl4030_kpwrite_u8(kp, reg, KEYP_CTRL) < 0) reg 282 drivers/input/keyboard/twl4030_keypad.c reg = KEYP_EDR_KP_BOTH | KEYP_EDR_TO_RISING; reg 283 drivers/input/keyboard/twl4030_keypad.c if (twl4030_kpwrite_u8(kp, reg, KEYP_EDR) < 0) reg 287 drivers/input/keyboard/twl4030_keypad.c reg = (PTV_PRESCALER << KEYP_LK_PTV_PTV_SHIFT); reg 288 drivers/input/keyboard/twl4030_keypad.c if (twl4030_kpwrite_u8(kp, reg, KEYP_LK_PTV) < 0) reg 308 drivers/input/keyboard/twl4030_keypad.c reg = TWL4030_SIH_CTRL_COR_MASK | TWL4030_SIH_CTRL_PENDDIS_MASK; reg 309 drivers/input/keyboard/twl4030_keypad.c if (twl4030_kpwrite_u8(kp, reg, KEYP_SIH_CTRL) < 0) reg 329 drivers/input/keyboard/twl4030_keypad.c u8 reg; reg 424 drivers/input/keyboard/twl4030_keypad.c reg = (u8) ~(KEYP_IMR1_KP | KEYP_IMR1_TO); reg 425 drivers/input/keyboard/twl4030_keypad.c if (twl4030_kpwrite_u8(kp, reg, KEYP_IMR1)) { reg 28 drivers/input/misc/ad714x-i2c.c unsigned short reg, unsigned short data) reg 33 drivers/input/misc/ad714x-i2c.c chip->xfer_buf[0] = cpu_to_be16(reg); reg 47 drivers/input/misc/ad714x-i2c.c unsigned short reg, unsigned short *data, size_t len) reg 53 drivers/input/misc/ad714x-i2c.c chip->xfer_buf[0] = cpu_to_be16(reg); reg 31 drivers/input/misc/ad714x-spi.c unsigned short reg, unsigned short *data, size_t len) reg 43 drivers/input/misc/ad714x-spi.c AD714x_SPI_READ | reg); reg 65 drivers/input/misc/ad714x-spi.c unsigned short reg, unsigned short data) reg 70 drivers/input/misc/ad714x-spi.c chip->xfer_buf[0] = cpu_to_be16(AD714x_SPI_CMD_PREFIX | reg); reg 18 drivers/input/misc/adxl34x-i2c.c static int adxl34x_smbus_read(struct device *dev, unsigned char reg) reg 22 drivers/input/misc/adxl34x-i2c.c return i2c_smbus_read_byte_data(client, reg); reg 26 drivers/input/misc/adxl34x-i2c.c unsigned char reg, unsigned char val) reg 30 drivers/input/misc/adxl34x-i2c.c return i2c_smbus_write_byte_data(client, reg, val); reg 34 drivers/input/misc/adxl34x-i2c.c unsigned char reg, int count, reg 39 drivers/input/misc/adxl34x-i2c.c return i2c_smbus_read_i2c_block_data(client, reg, count, buf); reg 43 drivers/input/misc/adxl34x-i2c.c unsigned char reg, int count, reg 49 drivers/input/misc/adxl34x-i2c.c ret = i2c_master_send(client, ®, 1); reg 21 drivers/input/misc/adxl34x-spi.c #define ADXL34X_WRITECMD(reg) (reg & 0x3F) reg 22 drivers/input/misc/adxl34x-spi.c #define ADXL34X_READCMD(reg) (ADXL34X_CMD_READ | (reg & 0x3F)) reg 23 drivers/input/misc/adxl34x-spi.c #define ADXL34X_READMB_CMD(reg) (ADXL34X_CMD_READ | ADXL34X_CMD_MULTB \ reg 24 drivers/input/misc/adxl34x-spi.c | (reg & 0x3F)) reg 26 drivers/input/misc/adxl34x-spi.c static int adxl34x_spi_read(struct device *dev, unsigned char reg) reg 31 drivers/input/misc/adxl34x-spi.c cmd = ADXL34X_READCMD(reg); reg 37 drivers/input/misc/adxl34x-spi.c unsigned char reg, unsigned char val) reg 42 drivers/input/misc/adxl34x-spi.c buf[0] = ADXL34X_WRITECMD(reg); reg 49 drivers/input/misc/adxl34x-spi.c unsigned char reg, int count, reg 55 drivers/input/misc/adxl34x-spi.c reg = ADXL34X_READMB_CMD(reg); reg 56 drivers/input/misc/adxl34x-spi.c status = spi_write_then_read(spi, ®, 1, buf, count); reg 181 drivers/input/misc/adxl34x.c #define AC_READ(ac, reg) ((ac)->bops->read((ac)->dev, reg)) reg 182 drivers/input/misc/adxl34x.c #define AC_WRITE(ac, reg, val) ((ac)->bops->write((ac)->dev, reg, val)) reg 84 drivers/input/misc/atmel_captouch.c u8 reg, u8 *data, size_t len) reg 94 drivers/input/misc/atmel_captouch.c capdev->xfer_buf[0] = reg; reg 111 drivers/input/misc/atmel_captouch.c if (capdev->xfer_buf[0] != reg) { reg 114 drivers/input/misc/atmel_captouch.c capdev->xfer_buf[0], reg); reg 152 drivers/input/misc/bma150.c static int bma150_write_byte(struct i2c_client *client, u8 reg, u8 val) reg 160 drivers/input/misc/bma150.c ret = i2c_smbus_write_byte_data(client, reg, val); reg 169 drivers/input/misc/bma150.c int val, int shift, u8 mask, u8 reg) reg 173 drivers/input/misc/bma150.c data = i2c_smbus_read_byte_data(client, reg); reg 178 drivers/input/misc/bma150.c return bma150_write_byte(client, reg, data); reg 73 drivers/input/misc/cma3000_d0x.c #define CMA3000_READ(data, reg, msg) \ reg 74 drivers/input/misc/cma3000_d0x.c (data->bus_ops->read(data->dev, reg, msg)) reg 75 drivers/input/misc/cma3000_d0x.c #define CMA3000_SET(data, reg, val, msg) \ reg 76 drivers/input/misc/cma3000_d0x.c ((data)->bus_ops->write(data->dev, reg, val, msg)) reg 15 drivers/input/misc/cma3000_d0x_i2c.c u8 reg, u8 val, char *msg) reg 20 drivers/input/misc/cma3000_d0x_i2c.c ret = i2c_smbus_write_byte_data(client, reg, val); reg 27 drivers/input/misc/cma3000_d0x_i2c.c static int cma3000_i2c_read(struct device *dev, u8 reg, char *msg) reg 32 drivers/input/misc/cma3000_d0x_i2c.c ret = i2c_smbus_read_byte_data(client, reg); reg 32 drivers/input/misc/cobalt_btns.c void __iomem *reg; reg 42 drivers/input/misc/cobalt_btns.c status = ~readl(bdev->reg) >> 24; reg 106 drivers/input/misc/cobalt_btns.c bdev->reg = ioremap(res->start, resource_size(res)); reg 116 drivers/input/misc/cobalt_btns.c iounmap(bdev->reg); reg 130 drivers/input/misc/cobalt_btns.c iounmap(bdev->reg); reg 98 drivers/input/misc/mc13783-pwrbutton.c int reg = 0; reg 119 drivers/input/misc/mc13783-pwrbutton.c reg |= (pdata->b1on_flags & 0x3) << MC13783_POWER_CONTROL_2_ON1BDBNC; reg 120 drivers/input/misc/mc13783-pwrbutton.c reg |= (pdata->b2on_flags & 0x3) << MC13783_POWER_CONTROL_2_ON2BDBNC; reg 121 drivers/input/misc/mc13783-pwrbutton.c reg |= (pdata->b3on_flags & 0x3) << MC13783_POWER_CONTROL_2_ON3BDBNC; reg 137 drivers/input/misc/mc13783-pwrbutton.c reg |= MC13783_POWER_CONTROL_2_ON1BRSTEN; reg 156 drivers/input/misc/mc13783-pwrbutton.c reg |= MC13783_POWER_CONTROL_2_ON2BRSTEN; reg 175 drivers/input/misc/mc13783-pwrbutton.c reg |= MC13783_POWER_CONTROL_2_ON3BRSTEN; reg 185 drivers/input/misc/mc13783-pwrbutton.c mc13xxx_reg_rmw(mc13783, MC13783_REG_POWER_CONTROL_2, 0x3FE, reg); reg 66 drivers/input/misc/palmas-pwrbutton.c unsigned int reg; reg 70 drivers/input/misc/palmas-pwrbutton.c PALMAS_INT1_LINE_STATE, ®); reg 74 drivers/input/misc/palmas-pwrbutton.c } else if (reg & BIT(1)) { reg 165 drivers/input/misc/pmic8xxx-pwrkey.c unsigned int reg; reg 172 drivers/input/misc/pmic8xxx-pwrkey.c error = regmap_read(regmap, test2_addr, ®); reg 176 drivers/input/misc/pmic8xxx-pwrkey.c reg &= PM8058_SMPS_ADVANCED_MODE_MASK; reg 178 drivers/input/misc/pmic8xxx-pwrkey.c if (reg == PM8058_SMPS_ADVANCED_MODE) { reg 180 drivers/input/misc/pmic8xxx-pwrkey.c error = regmap_read(regmap, ctrl_addr, ®); reg 184 drivers/input/misc/pmic8xxx-pwrkey.c band = reg & PM8058_SMPS_ADVANCED_BAND_MASK; reg 203 drivers/input/misc/pmic8xxx-pwrkey.c vprog = reg & PM8058_SMPS_ADVANCED_VPROG_MASK; reg 56 drivers/input/misc/stpmic1_onkey.c unsigned int val, reg = 0; reg 74 drivers/input/misc/stpmic1_onkey.c reg |= PONKEY_PWR_OFF; reg 75 drivers/input/misc/stpmic1_onkey.c reg |= ((16 - val) & PONKEY_TURNOFF_TIMER_MASK); reg 83 drivers/input/misc/stpmic1_onkey.c reg |= PONKEY_CC_FLAG_CLEAR; reg 86 drivers/input/misc/stpmic1_onkey.c PONKEY_TURNOFF_MASK, reg); reg 67 drivers/input/misc/tps65218-pwrbutton.c unsigned int reg; reg 70 drivers/input/misc/tps65218-pwrbutton.c error = regmap_read(pwr->regmap, tps_data->reg_status, ®); reg 76 drivers/input/misc/tps65218-pwrbutton.c if (reg & tps_data->pb_mask) { reg 43 drivers/input/misc/twl4030-vibra.c u8 reg; reg 46 drivers/input/misc/twl4030-vibra.c twl_i2c_read_u8(TWL4030_MODULE_LED, ®, LEDEN); reg 47 drivers/input/misc/twl4030-vibra.c reg &= ~0x03; reg 48 drivers/input/misc/twl4030-vibra.c twl_i2c_write_u8(TWL4030_MODULE_LED, LEDEN, reg); reg 54 drivers/input/misc/twl4030-vibra.c u8 reg; reg 60 drivers/input/misc/twl4030-vibra.c ®, TWL4030_REG_VIBRA_CTL); reg 62 drivers/input/misc/twl4030-vibra.c (reg | TWL4030_VIBRA_EN), TWL4030_REG_VIBRA_CTL); reg 71 drivers/input/misc/twl4030-vibra.c u8 reg; reg 75 drivers/input/misc/twl4030-vibra.c ®, TWL4030_REG_VIBRA_CTL); reg 77 drivers/input/misc/twl4030-vibra.c (reg & ~TWL4030_VIBRA_EN), TWL4030_REG_VIBRA_CTL); reg 91 drivers/input/misc/twl4030-vibra.c u8 reg; reg 97 drivers/input/misc/twl4030-vibra.c ®, TWL4030_REG_VIBRA_CTL); reg 98 drivers/input/misc/twl4030-vibra.c if (pwm && (!info->coexist || !(reg & TWL4030_VIBRA_SEL))) { reg 105 drivers/input/misc/twl4030-vibra.c ®, TWL4030_REG_VIBRA_CTL); reg 106 drivers/input/misc/twl4030-vibra.c reg = (dir) ? (reg | TWL4030_VIBRA_DIR) : reg 107 drivers/input/misc/twl4030-vibra.c (reg & ~TWL4030_VIBRA_DIR); reg 109 drivers/input/misc/twl4030-vibra.c reg, TWL4030_REG_VIBRA_CTL); reg 2290 drivers/input/mouse/alps.c int reg, x_pitch, y_pitch, x_electrode, y_electrode, x_phys, y_phys; reg 2293 drivers/input/mouse/alps.c reg = alps_command_mode_read_reg(psmouse, reg_pitch); reg 2294 drivers/input/mouse/alps.c if (reg < 0) reg 2295 drivers/input/mouse/alps.c return reg; reg 2297 drivers/input/mouse/alps.c x_pitch = (char)(reg << 4) >> 4; /* sign extend lower 4 bits */ reg 2300 drivers/input/mouse/alps.c y_pitch = (char)reg >> 4; /* sign extend upper 4 bits */ reg 2303 drivers/input/mouse/alps.c reg = alps_command_mode_read_reg(psmouse, reg_pitch + 1); reg 2304 drivers/input/mouse/alps.c if (reg < 0) reg 2305 drivers/input/mouse/alps.c return reg; reg 2307 drivers/input/mouse/alps.c x_electrode = (char)(reg << 4) >> 4; /* sign extend lower 4 bits */ reg 2310 drivers/input/mouse/alps.c y_electrode = (char)reg >> 4; /* sign extend upper 4 bits */ reg 91 drivers/input/mouse/cyapa.c static ssize_t cyapa_i2c_read(struct cyapa *cyapa, u8 reg, size_t len, reg 100 drivers/input/mouse/cyapa.c .buf = ®, reg 128 drivers/input/mouse/cyapa.c static int cyapa_i2c_write(struct cyapa *cyapa, u8 reg, reg 138 drivers/input/mouse/cyapa.c buf[0] = reg; reg 225 drivers/input/mouse/cyapa.h #define GET_PIP_CMD_CODE(reg) ((reg) & 0x7f) reg 387 drivers/input/mouse/cyapa.h ssize_t cyapa_i2c_reg_read_block(struct cyapa *cyapa, u8 reg, size_t len, reg 303 drivers/input/mouse/cyapa_gen3.c ssize_t cyapa_i2c_reg_read_block(struct cyapa *cyapa, u8 reg, size_t len, reg 306 drivers/input/mouse/cyapa_gen3.c return i2c_smbus_read_i2c_block_data(cyapa->client, reg, len, values); reg 309 drivers/input/mouse/cyapa_gen3.c static ssize_t cyapa_i2c_reg_write_block(struct cyapa *cyapa, u8 reg, reg 312 drivers/input/mouse/cyapa_gen3.c return i2c_smbus_write_i2c_block_data(cyapa->client, reg, len, values); reg 72 drivers/input/mouse/cyapa_gen5.c #define PIP_GET_EVENT_ID(reg) (((reg) >> 5) & 0x03) reg 73 drivers/input/mouse/cyapa_gen5.c #define PIP_GET_TOUCH_ID(reg) ((reg) & 0x1f) reg 77 drivers/input/mouse/cyapa_gen5.c #define PIP_GET_TOUCH_TYPE(reg) ((reg) & 0x07) reg 68 drivers/input/mouse/elan_i2c_i2c.c u16 reg, u8 *val, u16 len) reg 71 drivers/input/mouse/elan_i2c_i2c.c cpu_to_le16(reg), reg 93 drivers/input/mouse/elan_i2c_i2c.c static int elan_i2c_read_cmd(struct i2c_client *client, u16 reg, u8 *val) reg 97 drivers/input/mouse/elan_i2c_i2c.c retval = elan_i2c_read_block(client, reg, val, ETP_I2C_INF_LENGTH); reg 99 drivers/input/mouse/elan_i2c_i2c.c dev_err(&client->dev, "reading cmd (0x%04x) fail.\n", reg); reg 106 drivers/input/mouse/elan_i2c_i2c.c static int elan_i2c_write_cmd(struct i2c_client *client, u16 reg, u16 cmd) reg 109 drivers/input/mouse/elan_i2c_i2c.c cpu_to_le16(reg), reg 125 drivers/input/mouse/elan_i2c_i2c.c reg, ret); reg 180 drivers/input/mouse/elan_i2c_i2c.c u16 reg; reg 191 drivers/input/mouse/elan_i2c_i2c.c reg = le16_to_cpup((__le16 *)val); reg 193 drivers/input/mouse/elan_i2c_i2c.c reg &= ~ETP_DISABLE_POWER; reg 195 drivers/input/mouse/elan_i2c_i2c.c reg |= ETP_DISABLE_POWER; reg 197 drivers/input/mouse/elan_i2c_i2c.c error = elan_i2c_write_cmd(client, ETP_I2C_POWER_CMD, reg); reg 95 drivers/input/mouse/elantech.c static int elantech_read_reg(struct psmouse *psmouse, unsigned char reg, reg 102 drivers/input/mouse/elantech.c if (reg < 0x07 || reg > 0x26) reg 105 drivers/input/mouse/elantech.c if (reg > 0x11 && reg < 0x20) reg 111 drivers/input/mouse/elantech.c ps2_sliced_command(&psmouse->ps2dev, reg) || reg 121 drivers/input/mouse/elantech.c elantech_ps2_command(psmouse, NULL, reg) || reg 131 drivers/input/mouse/elantech.c elantech_ps2_command(psmouse, NULL, reg) || reg 139 drivers/input/mouse/elantech.c psmouse_err(psmouse, "failed to read register 0x%02x.\n", reg); reg 151 drivers/input/mouse/elantech.c static int elantech_write_reg(struct psmouse *psmouse, unsigned char reg, reg 157 drivers/input/mouse/elantech.c if (reg < 0x07 || reg > 0x26) reg 160 drivers/input/mouse/elantech.c if (reg > 0x11 && reg < 0x20) reg 166 drivers/input/mouse/elantech.c ps2_sliced_command(&psmouse->ps2dev, reg) || reg 177 drivers/input/mouse/elantech.c elantech_ps2_command(psmouse, NULL, reg) || reg 189 drivers/input/mouse/elantech.c elantech_ps2_command(psmouse, NULL, reg) || reg 201 drivers/input/mouse/elantech.c elantech_ps2_command(psmouse, NULL, reg) || reg 215 drivers/input/mouse/elantech.c reg, val); reg 1210 drivers/input/mouse/elantech.c unsigned char reg; reg 1221 drivers/input/mouse/elantech.c unsigned char *reg = (unsigned char *) etd + attr->field_offset; reg 1224 drivers/input/mouse/elantech.c if (attr->reg) reg 1225 drivers/input/mouse/elantech.c rc = elantech_read_reg(psmouse, attr->reg, reg); reg 1227 drivers/input/mouse/elantech.c return sprintf(buf, "0x%02x\n", (attr->reg && rc) ? -1 : *reg); reg 1238 drivers/input/mouse/elantech.c unsigned char *reg = (unsigned char *) etd + attr->field_offset; reg 1248 drivers/input/mouse/elantech.c if (attr->reg == 0x10) reg 1251 drivers/input/mouse/elantech.c else if (attr->reg == 0x11) reg 1256 drivers/input/mouse/elantech.c if (!attr->reg || elantech_write_reg(psmouse, attr->reg, value) == 0) reg 1257 drivers/input/mouse/elantech.c *reg = value; reg 1265 drivers/input/mouse/elantech.c .reg = _register, \ reg 1276 drivers/input/mouse/elantech.c .reg = 0, \ reg 347 drivers/input/mouse/focaltech.c static int focaltech_read_register(struct ps2dev *ps2dev, int reg, reg 363 drivers/input/mouse/focaltech.c param[0] = reg; reg 422 drivers/input/mouse/sentelic.c unsigned int reg, val; reg 426 drivers/input/mouse/sentelic.c reg = simple_strtoul(buf, &rest, 16); reg 427 drivers/input/mouse/sentelic.c if (rest == buf || *rest != ' ' || reg > 0xff) reg 440 drivers/input/mouse/sentelic.c retval = fsp_reg_write(psmouse, reg, val) < 0 ? -EIO : count; reg 466 drivers/input/mouse/sentelic.c unsigned int reg, val; reg 469 drivers/input/mouse/sentelic.c err = kstrtouint(buf, 16, ®); reg 473 drivers/input/mouse/sentelic.c if (reg > 0xff) reg 476 drivers/input/mouse/sentelic.c if (fsp_reg_read(psmouse, reg, &val)) reg 479 drivers/input/mouse/sentelic.c pad->last_reg = reg; reg 241 drivers/input/mouse/synaptics_i2c.c static s32 synaptics_i2c_reg_get(struct i2c_client *client, u16 reg) reg 245 drivers/input/mouse/synaptics_i2c.c ret = i2c_smbus_write_byte_data(client, PAGE_SEL_REG, reg >> 8); reg 247 drivers/input/mouse/synaptics_i2c.c ret = i2c_smbus_read_byte_data(client, reg & 0xff); reg 252 drivers/input/mouse/synaptics_i2c.c static s32 synaptics_i2c_reg_set(struct i2c_client *client, u16 reg, u8 val) reg 256 drivers/input/mouse/synaptics_i2c.c ret = i2c_smbus_write_byte_data(client, PAGE_SEL_REG, reg >> 8); reg 258 drivers/input/mouse/synaptics_i2c.c ret = i2c_smbus_write_byte_data(client, reg & 0xff, val); reg 263 drivers/input/mouse/synaptics_i2c.c static s32 synaptics_i2c_word_get(struct i2c_client *client, u16 reg) reg 267 drivers/input/mouse/synaptics_i2c.c ret = i2c_smbus_write_byte_data(client, PAGE_SEL_REG, reg >> 8); reg 269 drivers/input/mouse/synaptics_i2c.c ret = i2c_smbus_read_word_data(client, reg & 0xff); reg 568 drivers/input/rmi4/rmi_driver.c int reg; reg 642 drivers/input/rmi4/rmi_driver.c reg = find_first_bit(rdesc->presense_map, RMI_REG_DESC_PRESENSE_BITS); reg 662 drivers/input/rmi4/rmi_driver.c item->reg = reg; reg 681 drivers/input/rmi4/rmi_driver.c item->reg, item->reg_size, item->num_subpackets); reg 683 drivers/input/rmi4/rmi_driver.c reg = find_next_bit(rdesc->presense_map, reg 684 drivers/input/rmi4/rmi_driver.c RMI_REG_DESC_PRESENSE_BITS, reg + 1); reg 693 drivers/input/rmi4/rmi_driver.c struct rmi_register_descriptor *rdesc, u16 reg) reg 700 drivers/input/rmi4/rmi_driver.c if (item->reg == reg) reg 722 drivers/input/rmi4/rmi_driver.c struct rmi_register_descriptor *rdesc, u16 reg) reg 730 drivers/input/rmi4/rmi_driver.c if (item->reg == reg) reg 54 drivers/input/rmi4/rmi_driver.h u16 reg; reg 75 drivers/input/rmi4/rmi_driver.h struct rmi_register_descriptor *rdesc, u16 reg); reg 83 drivers/input/rmi4/rmi_driver.h struct rmi_register_descriptor *rdesc, u16 reg); reg 201 drivers/input/rmi4/rmi_f30.c int *ctrl_addr, int len, u8 **reg) reg 205 drivers/input/rmi4/rmi_f30.c ctrl->regs = *reg; reg 207 drivers/input/rmi4/rmi_f30.c *reg += len; reg 199 drivers/input/touchscreen/ad7877.c static int ad7877_read(struct spi_device *spi, u16 reg) reg 211 drivers/input/touchscreen/ad7877.c AD7877_READADD(reg)); reg 230 drivers/input/touchscreen/ad7877.c static int ad7877_write(struct spi_device *spi, u16 reg, u16 val) reg 241 drivers/input/touchscreen/ad7877.c req->command = (u16) (AD7877_WRITEADD(reg) | (val & MAX_12BIT)); reg 135 drivers/input/touchscreen/ad7879.c static int ad7879_read(struct ad7879 *ts, u8 reg) reg 140 drivers/input/touchscreen/ad7879.c error = regmap_read(ts->regmap, reg, &val); reg 143 drivers/input/touchscreen/ad7879.c reg, error); reg 150 drivers/input/touchscreen/ad7879.c static int ad7879_write(struct ad7879 *ts, u8 reg, u16 val) reg 154 drivers/input/touchscreen/ad7879.c error = regmap_write(ts->regmap, reg, val); reg 158 drivers/input/touchscreen/ad7879.c val, reg, error); reg 272 drivers/input/touchscreen/ad7879.c u16 reg = (ts->cmd_crtl2 & ~AD7879_PM(-1)) | reg 279 drivers/input/touchscreen/ad7879.c ad7879_write(ts, AD7879_REG_CTRL2, reg); reg 99 drivers/input/touchscreen/ads7846.c struct regulator *reg; reg 229 drivers/input/touchscreen/ads7846.c regulator_disable(ts->reg); reg 242 drivers/input/touchscreen/ads7846.c error = regulator_enable(ts->reg); reg 1391 drivers/input/touchscreen/ads7846.c ts->reg = regulator_get(&spi->dev, "vcc"); reg 1392 drivers/input/touchscreen/ads7846.c if (IS_ERR(ts->reg)) { reg 1393 drivers/input/touchscreen/ads7846.c err = PTR_ERR(ts->reg); reg 1398 drivers/input/touchscreen/ads7846.c err = regulator_enable(ts->reg); reg 1464 drivers/input/touchscreen/ads7846.c regulator_disable(ts->reg); reg 1466 drivers/input/touchscreen/ads7846.c regulator_put(ts->reg); reg 1493 drivers/input/touchscreen/ads7846.c regulator_put(ts->reg); reg 624 drivers/input/touchscreen/atmel_mxt_ts.c u16 reg, u16 len, void *val) reg 630 drivers/input/touchscreen/atmel_mxt_ts.c buf[0] = reg & 0xff; reg 631 drivers/input/touchscreen/atmel_mxt_ts.c buf[1] = (reg >> 8) & 0xff; reg 658 drivers/input/touchscreen/atmel_mxt_ts.c static int __mxt_write_reg(struct i2c_client *client, u16 reg, u16 len, reg 670 drivers/input/touchscreen/atmel_mxt_ts.c buf[0] = reg & 0xff; reg 671 drivers/input/touchscreen/atmel_mxt_ts.c buf[1] = (reg >> 8) & 0xff; reg 688 drivers/input/touchscreen/atmel_mxt_ts.c static int mxt_write_reg(struct i2c_client *client, u16 reg, u8 val) reg 690 drivers/input/touchscreen/atmel_mxt_ts.c return __mxt_write_reg(client, reg, 1, &val); reg 746 drivers/input/touchscreen/atmel_mxt_ts.c u16 reg; reg 752 drivers/input/touchscreen/atmel_mxt_ts.c reg = object->start_address; reg 753 drivers/input/touchscreen/atmel_mxt_ts.c return mxt_write_reg(data->client, reg + offset, val); reg 1159 drivers/input/touchscreen/atmel_mxt_ts.c u16 reg; reg 1164 drivers/input/touchscreen/atmel_mxt_ts.c reg = data->T6_address + cmd_offset; reg 1166 drivers/input/touchscreen/atmel_mxt_ts.c ret = mxt_write_reg(data->client, reg, value); reg 1175 drivers/input/touchscreen/atmel_mxt_ts.c ret = __mxt_read_reg(data->client, reg, 1, &command_register); reg 1294 drivers/input/touchscreen/atmel_mxt_ts.c u16 reg; reg 1353 drivers/input/touchscreen/atmel_mxt_ts.c reg = object->start_address + mxt_obj_size(object) * instance; reg 1369 drivers/input/touchscreen/atmel_mxt_ts.c byte_offset = reg + i - cfg->start_ofs; reg 1375 drivers/input/touchscreen/atmel_mxt_ts.c reg, object->type, byte_offset); reg 92 drivers/input/touchscreen/bcm_iproc_tsc.c #define dbg_reg(dev, priv, reg) \ reg 95 drivers/input/touchscreen/bcm_iproc_tsc.c regmap_read(priv->regmap, reg, &val); \ reg 96 drivers/input/touchscreen/bcm_iproc_tsc.c dev_dbg(dev, "%20s= 0x%08x\n", #reg, val); \ reg 257 drivers/input/touchscreen/bu21029_ts.c u8 reg; reg 297 drivers/input/touchscreen/bu21029_ts.c init_table[i].reg, reg 302 drivers/input/touchscreen/bu21029_ts.c init_table[i].value, init_table[i].reg, reg 58 drivers/input/touchscreen/chipone_icn8318.c u8 reg = ICN8318_REG_TOUCHDATA; reg 63 drivers/input/touchscreen/chipone_icn8318.c .buf = ® reg 147 drivers/input/touchscreen/chipone_icn8505.c static int icn8505_read_data(struct icn8505_data *icn8505, int reg, reg 150 drivers/input/touchscreen/chipone_icn8505.c return icn8505_read_xfer(icn8505->client, icn8505->client->addr, reg, reg 154 drivers/input/touchscreen/chipone_icn8505.c static int icn8505_read_reg_silent(struct icn8505_data *icn8505, int reg) reg 159 drivers/input/touchscreen/chipone_icn8505.c error = icn8505_read_xfer(icn8505->client, icn8505->client->addr, reg, reg 167 drivers/input/touchscreen/chipone_icn8505.c static int icn8505_write_reg(struct icn8505_data *icn8505, int reg, u8 val) reg 169 drivers/input/touchscreen/chipone_icn8505.c return icn8505_write_xfer(icn8505->client, icn8505->client->addr, reg, reg 173 drivers/input/touchscreen/chipone_icn8505.c static int icn8505_read_prog_data(struct icn8505_data *icn8505, int reg, reg 176 drivers/input/touchscreen/chipone_icn8505.c return icn8505_read_xfer(icn8505->client, ICN8505_PROG_I2C_ADDR, reg, reg 180 drivers/input/touchscreen/chipone_icn8505.c static int icn8505_write_prog_data(struct icn8505_data *icn8505, int reg, reg 183 drivers/input/touchscreen/chipone_icn8505.c return icn8505_write_xfer(icn8505->client, ICN8505_PROG_I2C_ADDR, reg, reg 187 drivers/input/touchscreen/chipone_icn8505.c static int icn8505_write_prog_reg(struct icn8505_data *icn8505, int reg, u8 val) reg 189 drivers/input/touchscreen/chipone_icn8505.c return icn8505_write_xfer(icn8505->client, ICN8505_PROG_I2C_ADDR, reg, reg 62 drivers/input/touchscreen/cy8ctmg110_ts.c static int cy8ctmg110_write_regs(struct cy8ctmg110 *tsc, unsigned char reg, reg 71 drivers/input/touchscreen/cy8ctmg110_ts.c i2c_data[0] = reg; reg 37 drivers/input/touchscreen/cyttsp4_spi.c u8 op, u16 reg, u8 *buf, int length) reg 56 drivers/input/touchscreen/cyttsp4_spi.c wr_buf[0] = op + (((reg >> 8) & 0x1) ? CY_SPI_A8_BIT : 0); reg 58 drivers/input/touchscreen/cyttsp4_spi.c wr_buf[1] = reg & 0xFF; reg 37 drivers/input/touchscreen/cyttsp_core.c #define GET_HSTMODE(reg) (((reg) & 0x70) >> 4) reg 38 drivers/input/touchscreen/cyttsp_core.c #define GET_BOOTLOADERMODE(reg) (((reg) & 0x10) >> 4) reg 34 drivers/input/touchscreen/cyttsp_spi.c u8 op, u16 reg, u8 *buf, int length) reg 55 drivers/input/touchscreen/cyttsp_spi.c wr_buf[2] = reg; /* reg index */ reg 180 drivers/input/touchscreen/goodix.c u16 reg, u8 *buf, int len) reg 183 drivers/input/touchscreen/goodix.c __be16 wbuf = cpu_to_be16(reg); reg 208 drivers/input/touchscreen/goodix.c static int goodix_i2c_write(struct i2c_client *client, u16 reg, const u8 *buf, reg 219 drivers/input/touchscreen/goodix.c addr_buf[0] = reg >> 8; reg 220 drivers/input/touchscreen/goodix.c addr_buf[1] = reg & 0xFF; reg 233 drivers/input/touchscreen/goodix.c static int goodix_i2c_write_u8(struct i2c_client *client, u16 reg, u8 value) reg 235 drivers/input/touchscreen/goodix.c return goodix_i2c_write(client, reg, &value, sizeof(value)); reg 147 drivers/input/touchscreen/hideep.c struct regmap *reg; reg 313 drivers/input/touchscreen/hideep.c error = regmap_bulk_write(ts->reg, p1, &p2, 1); reg 668 drivers/input/touchscreen/hideep.c error = regmap_write(ts->reg, HIDEEP_RESET_CMD, 0x01); reg 748 drivers/input/touchscreen/hideep.c error = regmap_bulk_read(ts->reg, HIDEEP_EVENT_ADDR, reg 766 drivers/input/touchscreen/hideep.c error = regmap_bulk_read(ts->reg, 0x28, val, ARRAY_SIZE(val)); reg 1018 drivers/input/touchscreen/hideep.c ts->reg = devm_regmap_init_i2c(client, &hideep_regmap_config); reg 1019 drivers/input/touchscreen/hideep.c if (IS_ERR(ts->reg)) { reg 1020 drivers/input/touchscreen/hideep.c error = PTR_ERR(ts->reg); reg 47 drivers/input/touchscreen/ili210x.c static int ili210x_read_reg(struct i2c_client *client, u8 reg, void *buf, reg 56 drivers/input/touchscreen/ili210x.c .buf = ®, reg 130 drivers/input/touchscreen/iqs5xx.c u16 reg, void *val, u16 len) reg 132 drivers/input/touchscreen/iqs5xx.c __be16 reg_buf = cpu_to_be16(reg); reg 166 drivers/input/touchscreen/iqs5xx.c reg, ret); reg 171 drivers/input/touchscreen/iqs5xx.c static int iqs5xx_read_word(struct i2c_client *client, u16 reg, u16 *val) reg 176 drivers/input/touchscreen/iqs5xx.c error = iqs5xx_read_burst(client, reg, &val_buf, sizeof(val_buf)); reg 185 drivers/input/touchscreen/iqs5xx.c static int iqs5xx_read_byte(struct i2c_client *client, u16 reg, u8 *val) reg 187 drivers/input/touchscreen/iqs5xx.c return iqs5xx_read_burst(client, reg, val, sizeof(*val)); reg 191 drivers/input/touchscreen/iqs5xx.c u16 reg, const void *val, u16 len) reg 194 drivers/input/touchscreen/iqs5xx.c u16 mlen = sizeof(reg) + len; reg 195 drivers/input/touchscreen/iqs5xx.c u8 mbuf[sizeof(reg) + IQS5XX_WR_BYTES_MAX]; reg 200 drivers/input/touchscreen/iqs5xx.c put_unaligned_be16(reg, mbuf); reg 201 drivers/input/touchscreen/iqs5xx.c memcpy(mbuf + sizeof(reg), val, len); reg 220 drivers/input/touchscreen/iqs5xx.c reg, ret); reg 225 drivers/input/touchscreen/iqs5xx.c static int iqs5xx_write_word(struct i2c_client *client, u16 reg, u16 val) reg 229 drivers/input/touchscreen/iqs5xx.c return iqs5xx_write_burst(client, reg, &val_buf, sizeof(val_buf)); reg 232 drivers/input/touchscreen/iqs5xx.c static int iqs5xx_write_byte(struct i2c_client *client, u16 reg, u8 val) reg 234 drivers/input/touchscreen/iqs5xx.c return iqs5xx_write_burst(client, reg, &val, sizeof(val)); reg 59 drivers/input/touchscreen/lpc32xx_ts.c #define tsc_readl(dev, reg) \ reg 60 drivers/input/touchscreen/lpc32xx_ts.c __raw_readl((dev)->tsc_base + (reg)) reg 61 drivers/input/touchscreen/lpc32xx_ts.c #define tsc_writel(dev, reg, val) \ reg 62 drivers/input/touchscreen/lpc32xx_ts.c __raw_writel((val), (dev)->tsc_base + (reg)) reg 83 drivers/input/touchscreen/mms114.c static int __mms114_read_reg(struct mms114_data *data, unsigned int reg, reg 88 drivers/input/touchscreen/mms114.c u8 buf = reg & 0xff; reg 91 drivers/input/touchscreen/mms114.c if (reg <= MMS114_MODE_CONTROL && reg + len > MMS114_MODE_CONTROL) reg 117 drivers/input/touchscreen/mms114.c static int mms114_read_reg(struct mms114_data *data, unsigned int reg) reg 122 drivers/input/touchscreen/mms114.c if (reg == MMS114_MODE_CONTROL) reg 125 drivers/input/touchscreen/mms114.c error = __mms114_read_reg(data, reg, 1, &val); reg 129 drivers/input/touchscreen/mms114.c static int mms114_write_reg(struct mms114_data *data, unsigned int reg, reg 136 drivers/input/touchscreen/mms114.c buf[0] = reg & 0xff; reg 147 drivers/input/touchscreen/mms114.c if (reg == MMS114_MODE_CONTROL) reg 163 drivers/input/touchscreen/mxs-lradc-ts.c u32 reg; reg 173 drivers/input/touchscreen/mxs-lradc-ts.c reg = LRADC_CH_ACCUMULATE | reg 175 drivers/input/touchscreen/mxs-lradc-ts.c writel(reg, ts->base + LRADC_CH(ch1)); reg 176 drivers/input/touchscreen/mxs-lradc-ts.c writel(reg, ts->base + LRADC_CH(ch2)); reg 211 drivers/input/touchscreen/mxs-lradc-ts.c u32 reg; reg 214 drivers/input/touchscreen/mxs-lradc-ts.c reg = readl(ts->base + LRADC_CH(channel)); reg 215 drivers/input/touchscreen/mxs-lradc-ts.c if (reg & LRADC_CH_ACCUMULATE) reg 220 drivers/input/touchscreen/mxs-lradc-ts.c val = (reg & LRADC_CH_VALUE_MASK) >> LRADC_CH_VALUE_OFFSET; reg 227 drivers/input/touchscreen/mxs-lradc-ts.c u32 reg, mask; reg 231 drivers/input/touchscreen/mxs-lradc-ts.c reg = readl(ts->base + LRADC_CTRL1) & mask; reg 233 drivers/input/touchscreen/mxs-lradc-ts.c while (reg != mask) { reg 234 drivers/input/touchscreen/mxs-lradc-ts.c reg = readl(ts->base + LRADC_CTRL1) & mask; reg 235 drivers/input/touchscreen/mxs-lradc-ts.c dev_dbg(ts->dev, "One channel is still busy: %X\n", reg); reg 497 drivers/input/touchscreen/mxs-lradc-ts.c unsigned long reg = readl(ts->base + LRADC_CTRL1); reg 505 drivers/input/touchscreen/mxs-lradc-ts.c if (!(reg & mxs_lradc_irq_mask(lradc))) reg 508 drivers/input/touchscreen/mxs-lradc-ts.c if (reg & ts_irq_mask) { reg 515 drivers/input/touchscreen/mxs-lradc-ts.c writel(reg & clr_irq, reg 362 drivers/input/touchscreen/rohm_bu21023.c #define READ_CALIB_BUF(reg) buf[((reg) - PRM1_X_H)] reg 548 drivers/input/touchscreen/rohm_bu21023.c #define READ_POS_BUF(reg) buf[((reg) - POS_X1_H)] reg 526 drivers/input/touchscreen/stmfts.c u8 reg[8]; reg 540 drivers/input/touchscreen/stmfts.c sizeof(reg), reg); reg 543 drivers/input/touchscreen/stmfts.c if (err != sizeof(reg)) reg 546 drivers/input/touchscreen/stmfts.c sdata->chip_id = be16_to_cpup((__be16 *)®[6]); reg 547 drivers/input/touchscreen/stmfts.c sdata->chip_ver = reg[0]; reg 548 drivers/input/touchscreen/stmfts.c sdata->fw_ver = be16_to_cpup((__be16 *)®[2]); reg 549 drivers/input/touchscreen/stmfts.c sdata->config_id = reg[4]; reg 550 drivers/input/touchscreen/stmfts.c sdata->config_ver = reg[5]; reg 242 drivers/input/touchscreen/sun4i-ts.c u32 reg; reg 343 drivers/input/touchscreen/sun4i-ts.c reg = STYLUS_UP_DEBOUN(5) | STYLUS_UP_DEBOUN_EN(1); reg 345 drivers/input/touchscreen/sun4i-ts.c reg |= SUN6I_TP_MODE_EN(1); reg 347 drivers/input/touchscreen/sun4i-ts.c reg |= TP_MODE_EN(1); reg 348 drivers/input/touchscreen/sun4i-ts.c writel(reg, ts->base + TP_CTRL1); reg 63 drivers/input/touchscreen/ti_am335x_tsc.c static unsigned int titsc_readl(struct titsc *ts, unsigned int reg) reg 65 drivers/input/touchscreen/ti_am335x_tsc.c return readl(ts->mfd_tscadc->tscadc_base + reg); reg 68 drivers/input/touchscreen/ti_am335x_tsc.c static void titsc_writel(struct titsc *tsc, unsigned int reg, reg 71 drivers/input/touchscreen/ti_am335x_tsc.c writel(val, tsc->mfd_tscadc->tscadc_base + reg); reg 51 drivers/input/touchscreen/tps6507x-ts.c static int tps6507x_read_u8(struct tps6507x_ts *tsc, u8 reg, u8 *data) reg 53 drivers/input/touchscreen/tps6507x-ts.c return tsc->mfd->read_dev(tsc->mfd, reg, 1, data); reg 56 drivers/input/touchscreen/tps6507x-ts.c static int tps6507x_write_u8(struct tps6507x_ts *tsc, u8 reg, u8 data) reg 58 drivers/input/touchscreen/tps6507x-ts.c return tsc->mfd->write_dev(tsc->mfd, reg, 1, &data); reg 42 drivers/input/touchscreen/ts4800-ts.c unsigned int reg; reg 57 drivers/input/touchscreen/ts4800-ts.c ret = regmap_update_bits(ts->regmap, ts->reg, ts->bit, ts->bit); reg 67 drivers/input/touchscreen/ts4800-ts.c ret = regmap_update_bits(ts->regmap, ts->reg, ts->bit, 0); reg 112 drivers/input/touchscreen/ts4800-ts.c u32 reg, bit; reg 128 drivers/input/touchscreen/ts4800-ts.c error = of_property_read_u32_index(np, "syscon", 1, ®); reg 134 drivers/input/touchscreen/ts4800-ts.c ts->reg = reg; reg 200 drivers/input/touchscreen/wm9712.c u16 reg; reg 202 drivers/input/touchscreen/wm9712.c reg = wm97xx_reg_read(wm, AC97_MISC_AFE); reg 203 drivers/input/touchscreen/wm9712.c wm97xx_reg_write(wm, AC97_MISC_AFE, reg | WM97XX_GPIO_4); reg 204 drivers/input/touchscreen/wm9712.c reg = wm97xx_reg_read(wm, AC97_GPIO_CFG); reg 205 drivers/input/touchscreen/wm9712.c wm97xx_reg_write(wm, AC97_GPIO_CFG, reg | WM97XX_GPIO_4); reg 84 drivers/input/touchscreen/wm97xx-core.c int wm97xx_reg_read(struct wm97xx *wm, u16 reg) reg 87 drivers/input/touchscreen/wm97xx-core.c return wm->ac97->bus->ops->read(wm->ac97, reg); reg 93 drivers/input/touchscreen/wm97xx-core.c void wm97xx_reg_write(struct wm97xx *wm, u16 reg, u16 val) reg 96 drivers/input/touchscreen/wm97xx-core.c if (reg >= AC97_WM9713_DIG1 && reg <= AC97_WM9713_DIG3) reg 97 drivers/input/touchscreen/wm97xx-core.c wm->dig[(reg - AC97_WM9713_DIG1) >> 1] = val; reg 100 drivers/input/touchscreen/wm97xx-core.c if (reg >= AC97_GPIO_CFG && reg <= AC97_MISC_AFE) reg 101 drivers/input/touchscreen/wm97xx-core.c wm->gpio[(reg - AC97_GPIO_CFG) >> 1] = val; reg 104 drivers/input/touchscreen/wm97xx-core.c if (reg == 0x5a) reg 108 drivers/input/touchscreen/wm97xx-core.c wm->ac97->bus->ops->write(wm->ac97, reg, val); reg 205 drivers/input/touchscreen/wm97xx-core.c u16 reg; reg 208 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_GPIO_STATUS); reg 211 drivers/input/touchscreen/wm97xx-core.c reg |= gpio; reg 213 drivers/input/touchscreen/wm97xx-core.c reg &= ~gpio; reg 216 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_STATUS, reg << 1); reg 218 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_STATUS, reg); reg 231 drivers/input/touchscreen/wm97xx-core.c u16 reg; reg 234 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_GPIO_POLARITY); reg 237 drivers/input/touchscreen/wm97xx-core.c reg |= gpio; reg 239 drivers/input/touchscreen/wm97xx-core.c reg &= ~gpio; reg 241 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_POLARITY, reg); reg 242 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_GPIO_STICKY); reg 245 drivers/input/touchscreen/wm97xx-core.c reg |= gpio; reg 247 drivers/input/touchscreen/wm97xx-core.c reg &= ~gpio; reg 249 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_STICKY, reg); reg 250 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_GPIO_WAKEUP); reg 253 drivers/input/touchscreen/wm97xx-core.c reg |= gpio; reg 255 drivers/input/touchscreen/wm97xx-core.c reg &= ~gpio; reg 257 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_WAKEUP, reg); reg 258 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_GPIO_CFG); reg 261 drivers/input/touchscreen/wm97xx-core.c reg |= gpio; reg 263 drivers/input/touchscreen/wm97xx-core.c reg &= ~gpio; reg 265 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_CFG, reg); reg 375 drivers/input/touchscreen/wm97xx-core.c u16 reg; reg 392 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_MISC_AFE); reg 394 drivers/input/touchscreen/wm97xx-core.c reg & ~(wm->mach_ops->irq_gpio)); reg 395 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, 0x5a); reg 396 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, 0x5a, reg & ~0x0001); reg 547 drivers/input/touchscreen/wm97xx-core.c u16 reg; reg 553 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_MISC_AFE); reg 555 drivers/input/touchscreen/wm97xx-core.c reg | wm->mach_ops->irq_gpio); reg 801 drivers/input/touchscreen/wm97xx-core.c u16 reg; reg 813 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER2); reg 814 drivers/input/touchscreen/wm97xx-core.c reg &= ~WM97XX_PRP_DET_DIG; reg 816 drivers/input/touchscreen/wm97xx-core.c reg |= suspend_mode; reg 817 drivers/input/touchscreen/wm97xx-core.c wm->ac97->bus->ops->write(wm->ac97, AC97_WM97XX_DIGITISER2, reg); reg 823 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_EXTENDED_MID) | 0x8000; reg 824 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_EXTENDED_MID, reg); reg 839 drivers/input/touchscreen/wm97xx-core.c u16 reg; reg 840 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_EXTENDED_MID) & 0x7fff; reg 841 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_EXTENDED_MID, reg); reg 114 drivers/iommu/arm-smmu-impl.c u32 reg, major; reg 121 drivers/iommu/arm-smmu-impl.c reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID7); reg 122 drivers/iommu/arm-smmu-impl.c major = FIELD_GET(ID7_MAJOR, reg); reg 123 drivers/iommu/arm-smmu-impl.c reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sACR); reg 125 drivers/iommu/arm-smmu-impl.c reg &= ~ARM_MMU500_ACR_CACHE_LOCK; reg 130 drivers/iommu/arm-smmu-impl.c reg |= ARM_MMU500_ACR_SMTNMB_TLBEN | ARM_MMU500_ACR_S2CRB_TLBEN; reg 131 drivers/iommu/arm-smmu-impl.c arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sACR, reg); reg 138 drivers/iommu/arm-smmu-impl.c reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR); reg 139 drivers/iommu/arm-smmu-impl.c reg &= ~ARM_MMU500_ACTLR_CPRE; reg 140 drivers/iommu/arm-smmu-impl.c arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg); reg 2871 drivers/iommu/arm-smmu-v3.c u64 reg; reg 2898 drivers/iommu/arm-smmu-v3.c reg = FIELD_PREP(STRTAB_BASE_CFG_FMT, STRTAB_BASE_CFG_FMT_2LVL); reg 2899 drivers/iommu/arm-smmu-v3.c reg |= FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, size); reg 2900 drivers/iommu/arm-smmu-v3.c reg |= FIELD_PREP(STRTAB_BASE_CFG_SPLIT, STRTAB_SPLIT); reg 2901 drivers/iommu/arm-smmu-v3.c cfg->strtab_base_cfg = reg; reg 2909 drivers/iommu/arm-smmu-v3.c u64 reg; reg 2926 drivers/iommu/arm-smmu-v3.c reg = FIELD_PREP(STRTAB_BASE_CFG_FMT, STRTAB_BASE_CFG_FMT_LINEAR); reg 2927 drivers/iommu/arm-smmu-v3.c reg |= FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, smmu->sid_bits); reg 2928 drivers/iommu/arm-smmu-v3.c cfg->strtab_base_cfg = reg; reg 2936 drivers/iommu/arm-smmu-v3.c u64 reg; reg 2948 drivers/iommu/arm-smmu-v3.c reg = smmu->strtab_cfg.strtab_dma & STRTAB_BASE_ADDR_MASK; reg 2949 drivers/iommu/arm-smmu-v3.c reg |= STRTAB_BASE_RA; reg 2950 drivers/iommu/arm-smmu-v3.c smmu->strtab_cfg.strtab_base = reg; reg 2971 drivers/iommu/arm-smmu-v3.c u32 reg; reg 2974 drivers/iommu/arm-smmu-v3.c return readl_relaxed_poll_timeout(smmu->base + ack_off, reg, reg == val, reg 2982 drivers/iommu/arm-smmu-v3.c u32 reg, __iomem *gbpa = smmu->base + ARM_SMMU_GBPA; reg 2984 drivers/iommu/arm-smmu-v3.c ret = readl_relaxed_poll_timeout(gbpa, reg, !(reg & GBPA_UPDATE), reg 2989 drivers/iommu/arm-smmu-v3.c reg &= ~clr; reg 2990 drivers/iommu/arm-smmu-v3.c reg |= set; reg 2991 drivers/iommu/arm-smmu-v3.c writel_relaxed(reg | GBPA_UPDATE, gbpa); reg 2992 drivers/iommu/arm-smmu-v3.c ret = readl_relaxed_poll_timeout(gbpa, reg, !(reg & GBPA_UPDATE), reg 3172 drivers/iommu/arm-smmu-v3.c u32 reg, enables; reg 3176 drivers/iommu/arm-smmu-v3.c reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); reg 3177 drivers/iommu/arm-smmu-v3.c if (reg & CR0_SMMUEN) { reg 3188 drivers/iommu/arm-smmu-v3.c reg = FIELD_PREP(CR1_TABLE_SH, ARM_SMMU_SH_ISH) | reg 3194 drivers/iommu/arm-smmu-v3.c writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); reg 3197 drivers/iommu/arm-smmu-v3.c reg = CR2_PTM | CR2_RECINVSID | CR2_E2H; reg 3198 drivers/iommu/arm-smmu-v3.c writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); reg 3306 drivers/iommu/arm-smmu-v3.c u32 reg; reg 3310 drivers/iommu/arm-smmu-v3.c reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0); reg 3313 drivers/iommu/arm-smmu-v3.c if (FIELD_GET(IDR0_ST_LVL, reg) == IDR0_ST_LVL_2LVL) reg 3316 drivers/iommu/arm-smmu-v3.c if (reg & IDR0_CD2L) reg 3324 drivers/iommu/arm-smmu-v3.c switch (FIELD_GET(IDR0_TTENDIAN, reg)) { reg 3343 drivers/iommu/arm-smmu-v3.c if (IS_ENABLED(CONFIG_PCI_PRI) && reg & IDR0_PRI) reg 3346 drivers/iommu/arm-smmu-v3.c if (IS_ENABLED(CONFIG_PCI_ATS) && reg & IDR0_ATS) reg 3349 drivers/iommu/arm-smmu-v3.c if (reg & IDR0_SEV) reg 3352 drivers/iommu/arm-smmu-v3.c if (reg & IDR0_MSI) reg 3355 drivers/iommu/arm-smmu-v3.c if (reg & IDR0_HYP) reg 3362 drivers/iommu/arm-smmu-v3.c if (!!(reg & IDR0_COHACC) != coherent) reg 3366 drivers/iommu/arm-smmu-v3.c switch (FIELD_GET(IDR0_STALL_MODEL, reg)) { reg 3374 drivers/iommu/arm-smmu-v3.c if (reg & IDR0_S1P) reg 3377 drivers/iommu/arm-smmu-v3.c if (reg & IDR0_S2P) reg 3380 drivers/iommu/arm-smmu-v3.c if (!(reg & (IDR0_S1P | IDR0_S2P))) { reg 3386 drivers/iommu/arm-smmu-v3.c switch (FIELD_GET(IDR0_TTF, reg)) { reg 3398 drivers/iommu/arm-smmu-v3.c smmu->asid_bits = reg & IDR0_ASID16 ? 16 : 8; reg 3399 drivers/iommu/arm-smmu-v3.c smmu->vmid_bits = reg & IDR0_VMID16 ? 16 : 8; reg 3402 drivers/iommu/arm-smmu-v3.c reg = readl_relaxed(smmu->base + ARM_SMMU_IDR1); reg 3403 drivers/iommu/arm-smmu-v3.c if (reg & (IDR1_TABLES_PRESET | IDR1_QUEUES_PRESET | IDR1_REL)) { reg 3410 drivers/iommu/arm-smmu-v3.c FIELD_GET(IDR1_CMDQS, reg)); reg 3424 drivers/iommu/arm-smmu-v3.c FIELD_GET(IDR1_EVTQS, reg)); reg 3426 drivers/iommu/arm-smmu-v3.c FIELD_GET(IDR1_PRIQS, reg)); reg 3429 drivers/iommu/arm-smmu-v3.c smmu->ssid_bits = FIELD_GET(IDR1_SSIDSIZE, reg); reg 3430 drivers/iommu/arm-smmu-v3.c smmu->sid_bits = FIELD_GET(IDR1_SIDSIZE, reg); reg 3440 drivers/iommu/arm-smmu-v3.c reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5); reg 3443 drivers/iommu/arm-smmu-v3.c smmu->evtq.max_stalls = FIELD_GET(IDR5_STALL_MAX, reg); reg 3446 drivers/iommu/arm-smmu-v3.c if (reg & IDR5_GRAN64K) reg 3448 drivers/iommu/arm-smmu-v3.c if (reg & IDR5_GRAN16K) reg 3450 drivers/iommu/arm-smmu-v3.c if (reg & IDR5_GRAN4K) reg 3454 drivers/iommu/arm-smmu-v3.c if (FIELD_GET(IDR5_VAX, reg) == IDR5_VAX_52_BIT) reg 3458 drivers/iommu/arm-smmu-v3.c switch (FIELD_GET(IDR5_OAS, reg)) { reg 245 drivers/iommu/arm-smmu.c u32 reg; reg 250 drivers/iommu/arm-smmu.c reg = arm_smmu_readl(smmu, page, status); reg 251 drivers/iommu/arm-smmu.c if (!(reg & sTLBGSTATUS_GSACTIVE)) reg 320 drivers/iommu/arm-smmu.c int reg, idx = cfg->cbndx; reg 325 drivers/iommu/arm-smmu.c reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA; reg 331 drivers/iommu/arm-smmu.c arm_smmu_cb_write(smmu, idx, reg, iova); reg 338 drivers/iommu/arm-smmu.c arm_smmu_cb_writeq(smmu, idx, reg, iova); reg 349 drivers/iommu/arm-smmu.c int reg, idx = smmu_domain->cfg.cbndx; reg 354 drivers/iommu/arm-smmu.c reg = leaf ? ARM_SMMU_CB_S2_TLBIIPAS2L : ARM_SMMU_CB_S2_TLBIIPAS2; reg 358 drivers/iommu/arm-smmu.c arm_smmu_cb_writeq(smmu, idx, reg, iova); reg 360 drivers/iommu/arm-smmu.c arm_smmu_cb_write(smmu, idx, reg, iova); reg 547 drivers/iommu/arm-smmu.c u32 reg; reg 563 drivers/iommu/arm-smmu.c reg = CBA2R_VA64; reg 565 drivers/iommu/arm-smmu.c reg = 0; reg 568 drivers/iommu/arm-smmu.c reg |= FIELD_PREP(CBA2R_VMID16, cfg->vmid); reg 570 drivers/iommu/arm-smmu.c arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBA2R(idx), reg); reg 574 drivers/iommu/arm-smmu.c reg = FIELD_PREP(CBAR_TYPE, cfg->cbar); reg 576 drivers/iommu/arm-smmu.c reg |= FIELD_PREP(CBAR_IRPTNDX, cfg->irptndx); reg 583 drivers/iommu/arm-smmu.c reg |= FIELD_PREP(CBAR_S1_BPSHCFG, CBAR_S1_BPSHCFG_NSH) | reg 587 drivers/iommu/arm-smmu.c reg |= FIELD_PREP(CBAR_VMID, cfg->vmid); reg 589 drivers/iommu/arm-smmu.c arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(idx), reg); reg 619 drivers/iommu/arm-smmu.c reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE | SCTLR_M; reg 621 drivers/iommu/arm-smmu.c reg |= SCTLR_S1_ASIDPNE; reg 623 drivers/iommu/arm-smmu.c reg |= SCTLR_E; reg 625 drivers/iommu/arm-smmu.c arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); reg 899 drivers/iommu/arm-smmu.c u32 reg = FIELD_PREP(SMR_ID, smr->id) | FIELD_PREP(SMR_MASK, smr->mask); reg 902 drivers/iommu/arm-smmu.c reg |= SMR_VALID; reg 903 drivers/iommu/arm-smmu.c arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(idx), reg); reg 909 drivers/iommu/arm-smmu.c u32 reg = FIELD_PREP(S2CR_TYPE, s2cr->type) | reg 915 drivers/iommu/arm-smmu.c reg |= S2CR_EXIDVALID; reg 916 drivers/iommu/arm-smmu.c arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg); reg 1229 drivers/iommu/arm-smmu.c void __iomem *reg; reg 1246 drivers/iommu/arm-smmu.c reg = arm_smmu_page(smmu, ARM_SMMU_CB(smmu, idx)) + ARM_SMMU_CB_ATSR; reg 1247 drivers/iommu/arm-smmu.c if (readl_poll_timeout_atomic(reg, tmp, !(tmp & ATSR_ACTIVE), 5, 50)) { reg 1579 drivers/iommu/arm-smmu.c u32 reg; reg 1582 drivers/iommu/arm-smmu.c reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); reg 1583 drivers/iommu/arm-smmu.c arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, reg); reg 1602 drivers/iommu/arm-smmu.c reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sCR0); reg 1605 drivers/iommu/arm-smmu.c reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE); reg 1608 drivers/iommu/arm-smmu.c reg |= (sCR0_VMIDPNE | sCR0_PTM); reg 1611 drivers/iommu/arm-smmu.c reg &= ~sCR0_CLIENTPD; reg 1613 drivers/iommu/arm-smmu.c reg |= sCR0_USFCFG; reg 1615 drivers/iommu/arm-smmu.c reg &= ~sCR0_USFCFG; reg 1618 drivers/iommu/arm-smmu.c reg &= ~sCR0_FB; reg 1621 drivers/iommu/arm-smmu.c reg &= ~(sCR0_BSU); reg 1624 drivers/iommu/arm-smmu.c reg |= sCR0_VMID16EN; reg 1627 drivers/iommu/arm-smmu.c reg |= sCR0_EXIDENABLE; reg 1634 drivers/iommu/arm-smmu.c arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, reg); reg 923 drivers/iommu/dmar.c iounmap(iommu->reg); reg 948 drivers/iommu/dmar.c iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); reg 949 drivers/iommu/dmar.c if (!iommu->reg) { reg 955 drivers/iommu/dmar.c iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG); reg 956 drivers/iommu/dmar.c iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG); reg 969 drivers/iommu/dmar.c iounmap(iommu->reg); reg 978 drivers/iommu/dmar.c iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); reg 979 drivers/iommu/dmar.c if (!iommu->reg) { reg 989 drivers/iommu/dmar.c iounmap(iommu->reg); reg 1066 drivers/iommu/dmar.c ver = readl(iommu->reg + DMAR_VER_REG); reg 1075 drivers/iommu/dmar.c sts = readl(iommu->reg + DMAR_GSTS_REG); reg 1136 drivers/iommu/dmar.c if (iommu->reg) reg 1167 drivers/iommu/dmar.c fault = readl(iommu->reg + DMAR_FSTS_REG); reg 1175 drivers/iommu/dmar.c head = readl(iommu->reg + DMAR_IQH_REG); reg 1189 drivers/iommu/dmar.c writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG); reg 1199 drivers/iommu/dmar.c head = readl(iommu->reg + DMAR_IQH_REG); reg 1202 drivers/iommu/dmar.c tail = readl(iommu->reg + DMAR_IQT_REG); reg 1205 drivers/iommu/dmar.c writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG); reg 1218 drivers/iommu/dmar.c writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG); reg 1274 drivers/iommu/dmar.c writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG); reg 1394 drivers/iommu/dmar.c sts = readl(iommu->reg + DMAR_GSTS_REG); reg 1401 drivers/iommu/dmar.c while ((readl(iommu->reg + DMAR_IQT_REG) != reg 1402 drivers/iommu/dmar.c readl(iommu->reg + DMAR_IQH_REG)) && reg 1407 drivers/iommu/dmar.c writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); reg 1438 drivers/iommu/dmar.c writel(0, iommu->reg + DMAR_IQT_REG); reg 1440 drivers/iommu/dmar.c dmar_writeq(iommu->reg + DMAR_IQA_REG, val); reg 1443 drivers/iommu/dmar.c writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); reg 1633 drivers/iommu/dmar.c int reg = dmar_msi_reg(iommu, data->irq); reg 1638 drivers/iommu/dmar.c writel(0, iommu->reg + reg); reg 1640 drivers/iommu/dmar.c readl(iommu->reg + reg); reg 1647 drivers/iommu/dmar.c int reg = dmar_msi_reg(iommu, data->irq); reg 1652 drivers/iommu/dmar.c writel(DMA_FECTL_IM, iommu->reg + reg); reg 1654 drivers/iommu/dmar.c readl(iommu->reg + reg); reg 1661 drivers/iommu/dmar.c int reg = dmar_msi_reg(iommu, irq); reg 1665 drivers/iommu/dmar.c writel(msg->data, iommu->reg + reg + 4); reg 1666 drivers/iommu/dmar.c writel(msg->address_lo, iommu->reg + reg + 8); reg 1667 drivers/iommu/dmar.c writel(msg->address_hi, iommu->reg + reg + 12); reg 1674 drivers/iommu/dmar.c int reg = dmar_msi_reg(iommu, irq); reg 1678 drivers/iommu/dmar.c msg->data = readl(iommu->reg + reg + 4); reg 1679 drivers/iommu/dmar.c msg->address_lo = readl(iommu->reg + reg + 8); reg 1680 drivers/iommu/dmar.c msg->address_hi = readl(iommu->reg + reg + 12); reg 1711 drivers/iommu/dmar.c int reg, fault_index; reg 1719 drivers/iommu/dmar.c fault_status = readl(iommu->reg + DMAR_FSTS_REG); reg 1728 drivers/iommu/dmar.c reg = cap_fault_reg_offset(iommu->cap); reg 1740 drivers/iommu/dmar.c data = readl(iommu->reg + reg + reg 1750 drivers/iommu/dmar.c data = readl(iommu->reg + reg + reg 1755 drivers/iommu/dmar.c guest_addr = dmar_readq(iommu->reg + reg + reg 1761 drivers/iommu/dmar.c writel(DMA_FRCD_F, iommu->reg + reg + reg 1779 drivers/iommu/dmar.c iommu->reg + DMAR_FSTS_REG); reg 1832 drivers/iommu/dmar.c fault_status = readl(iommu->reg + DMAR_FSTS_REG); reg 1833 drivers/iommu/dmar.c writel(fault_status, iommu->reg + DMAR_FSTS_REG); reg 148 drivers/iommu/exynos-iommu.c #define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */ reg 134 drivers/iommu/intel-iommu-debugfs.c value = dmar_readl(iommu->reg + iommu_regs_32[i].offset); reg 140 drivers/iommu/intel-iommu-debugfs.c value = dmar_readq(iommu->reg + iommu_regs_64[i].offset); reg 248 drivers/iommu/intel-iommu-debugfs.c if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) { reg 288 drivers/iommu/intel-iommu-debugfs.c sts = dmar_readl(iommu->reg + DMAR_GSTS_REG); reg 373 drivers/iommu/intel-iommu-debugfs.c sts = dmar_readl(iommu->reg + DMAR_GSTS_REG); reg 426 drivers/iommu/intel-iommu.c gsts = readl(iommu->reg + DMAR_GSTS_REG); reg 1222 drivers/iommu/intel-iommu.c dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr); reg 1224 drivers/iommu/intel-iommu.c writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); reg 1242 drivers/iommu/intel-iommu.c writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); reg 1276 drivers/iommu/intel-iommu.c dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); reg 1324 drivers/iommu/intel-iommu.c dmar_writeq(iommu->reg + tlb_offset, val_iva); reg 1325 drivers/iommu/intel-iommu.c dmar_writeq(iommu->reg + tlb_offset + 8, val); reg 1560 drivers/iommu/intel-iommu.c pmen = readl(iommu->reg + DMAR_PMEN_REG); reg 1562 drivers/iommu/intel-iommu.c writel(pmen, iommu->reg + DMAR_PMEN_REG); reg 1578 drivers/iommu/intel-iommu.c writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); reg 1594 drivers/iommu/intel-iommu.c writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); reg 3103 drivers/iommu/intel-iommu.c rtaddr_reg = dmar_readq(iommu->reg + DMAR_RTADDR_REG); reg 4237 drivers/iommu/intel-iommu.c readl(iommu->reg + DMAR_FECTL_REG); reg 4239 drivers/iommu/intel-iommu.c readl(iommu->reg + DMAR_FEDATA_REG); reg 4241 drivers/iommu/intel-iommu.c readl(iommu->reg + DMAR_FEADDR_REG); reg 4243 drivers/iommu/intel-iommu.c readl(iommu->reg + DMAR_FEUADDR_REG); reg 4275 drivers/iommu/intel-iommu.c iommu->reg + DMAR_FECTL_REG); reg 4277 drivers/iommu/intel-iommu.c iommu->reg + DMAR_FEDATA_REG); reg 4279 drivers/iommu/intel-iommu.c iommu->reg + DMAR_FEADDR_REG); reg 4281 drivers/iommu/intel-iommu.c iommu->reg + DMAR_FEUADDR_REG); reg 4766 drivers/iommu/intel-iommu.c u32 ver = readl(iommu->reg + DMAR_VER_REG); reg 5670 drivers/iommu/intel-iommu.c struct iommu_resv_region *reg; reg 5707 drivers/iommu/intel-iommu.c reg = iommu_alloc_resv_region(0, 1UL << 24, prot, reg 5709 drivers/iommu/intel-iommu.c if (reg) reg 5710 drivers/iommu/intel-iommu.c list_add_tail(®->list, head); reg 5715 drivers/iommu/intel-iommu.c reg = iommu_alloc_resv_region(IOAPIC_RANGE_START, reg 5718 drivers/iommu/intel-iommu.c if (!reg) reg 5720 drivers/iommu/intel-iommu.c list_add_tail(®->list, head); reg 77 drivers/iommu/intel-svm.c dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); reg 78 drivers/iommu/intel-svm.c dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); reg 79 drivers/iommu/intel-svm.c dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER); reg 86 drivers/iommu/intel-svm.c dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); reg 87 drivers/iommu/intel-svm.c dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); reg 88 drivers/iommu/intel-svm.c dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL); reg 539 drivers/iommu/intel-svm.c writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG); reg 541 drivers/iommu/intel-svm.c tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK; reg 542 drivers/iommu/intel-svm.c head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK; reg 665 drivers/iommu/intel-svm.c dmar_writeq(iommu->reg + DMAR_PQH_REG, tail); reg 99 drivers/iommu/intel_irq_remapping.c gsts = readl(iommu->reg + DMAR_GSTS_REG); reg 441 drivers/iommu/intel_irq_remapping.c irta = dmar_readq(iommu->reg + DMAR_IRTA_REG); reg 484 drivers/iommu/intel_irq_remapping.c dmar_writeq(iommu->reg + DMAR_IRTA_REG, reg 488 drivers/iommu/intel_irq_remapping.c writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG); reg 511 drivers/iommu/intel_irq_remapping.c writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); reg 667 drivers/iommu/intel_irq_remapping.c sts = readl(iommu->reg + DMAR_GSTS_REG); reg 672 drivers/iommu/intel_irq_remapping.c writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); reg 791 drivers/iommu/io-pgtable-arm.c u64 reg; reg 804 drivers/iommu/io-pgtable-arm.c reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) | reg 808 drivers/iommu/io-pgtable-arm.c reg = (ARM_LPAE_TCR_SH_OS << ARM_LPAE_TCR_SH0_SHIFT) | reg 815 drivers/iommu/io-pgtable-arm.c reg |= ARM_LPAE_TCR_TG0_4K; reg 818 drivers/iommu/io-pgtable-arm.c reg |= ARM_LPAE_TCR_TG0_16K; reg 821 drivers/iommu/io-pgtable-arm.c reg |= ARM_LPAE_TCR_TG0_64K; reg 827 drivers/iommu/io-pgtable-arm.c reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_IPS_SHIFT); reg 830 drivers/iommu/io-pgtable-arm.c reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_IPS_SHIFT); reg 833 drivers/iommu/io-pgtable-arm.c reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_IPS_SHIFT); reg 836 drivers/iommu/io-pgtable-arm.c reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_IPS_SHIFT); reg 839 drivers/iommu/io-pgtable-arm.c reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_IPS_SHIFT); reg 842 drivers/iommu/io-pgtable-arm.c reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_IPS_SHIFT); reg 845 drivers/iommu/io-pgtable-arm.c reg |= (ARM_LPAE_TCR_PS_52_BIT << ARM_LPAE_TCR_IPS_SHIFT); reg 851 drivers/iommu/io-pgtable-arm.c reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT; reg 854 drivers/iommu/io-pgtable-arm.c reg |= ARM_LPAE_TCR_EPD1; reg 855 drivers/iommu/io-pgtable-arm.c cfg->arm_lpae_s1_cfg.tcr = reg; reg 858 drivers/iommu/io-pgtable-arm.c reg = (ARM_LPAE_MAIR_ATTR_NC reg 867 drivers/iommu/io-pgtable-arm.c cfg->arm_lpae_s1_cfg.mair[0] = reg; reg 891 drivers/iommu/io-pgtable-arm.c u64 reg, sl; reg 917 drivers/iommu/io-pgtable-arm.c reg = ARM_64_LPAE_S2_TCR_RES1 | reg 926 drivers/iommu/io-pgtable-arm.c reg |= ARM_LPAE_TCR_TG0_4K; reg 930 drivers/iommu/io-pgtable-arm.c reg |= ARM_LPAE_TCR_TG0_16K; reg 933 drivers/iommu/io-pgtable-arm.c reg |= ARM_LPAE_TCR_TG0_64K; reg 939 drivers/iommu/io-pgtable-arm.c reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_PS_SHIFT); reg 942 drivers/iommu/io-pgtable-arm.c reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_PS_SHIFT); reg 945 drivers/iommu/io-pgtable-arm.c reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_PS_SHIFT); reg 948 drivers/iommu/io-pgtable-arm.c reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_PS_SHIFT); reg 951 drivers/iommu/io-pgtable-arm.c reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_PS_SHIFT); reg 954 drivers/iommu/io-pgtable-arm.c reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_PS_SHIFT); reg 957 drivers/iommu/io-pgtable-arm.c reg |= (ARM_LPAE_TCR_PS_52_BIT << ARM_LPAE_TCR_PS_SHIFT); reg 963 drivers/iommu/io-pgtable-arm.c reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT; reg 964 drivers/iommu/io-pgtable-arm.c reg |= (~sl & ARM_LPAE_TCR_SL0_MASK) << ARM_LPAE_TCR_SL0_SHIFT; reg 965 drivers/iommu/io-pgtable-arm.c cfg->arm_lpae_s2_cfg.vtcr = reg; reg 268 drivers/iommu/ipmmu-vmsa.c unsigned int reg) reg 271 drivers/iommu/ipmmu-vmsa.c domain->context_id * IM_CTX_SIZE + reg); reg 275 drivers/iommu/ipmmu-vmsa.c unsigned int reg, u32 data) reg 278 drivers/iommu/ipmmu-vmsa.c domain->context_id * IM_CTX_SIZE + reg, data); reg 282 drivers/iommu/ipmmu-vmsa.c unsigned int reg, u32 data) reg 286 drivers/iommu/ipmmu-vmsa.c domain->context_id * IM_CTX_SIZE + reg, data); reg 289 drivers/iommu/ipmmu-vmsa.c domain->context_id * IM_CTX_SIZE + reg, data); reg 314 drivers/iommu/ipmmu-vmsa.c u32 reg; reg 316 drivers/iommu/ipmmu-vmsa.c reg = ipmmu_ctx_read_root(domain, IMCTR); reg 317 drivers/iommu/ipmmu-vmsa.c reg |= IMCTR_FLUSH; reg 318 drivers/iommu/ipmmu-vmsa.c ipmmu_ctx_write_all(domain, IMCTR, reg); reg 29 drivers/iommu/msm_iommu.c #define MRC(reg, processor, op1, crn, crm, op2) \ reg 32 drivers/iommu/msm_iommu.c : "=r" (reg)) reg 10 drivers/iommu/msm_iommu_hw-8xxx.h #define GET_GLOBAL_REG(reg, base) (readl((base) + (reg))) reg 11 drivers/iommu/msm_iommu_hw-8xxx.h #define GET_CTX_REG(reg, base, ctx) \ reg 12 drivers/iommu/msm_iommu_hw-8xxx.h (readl((base) + (reg) + ((ctx) << CTX_SHIFT))) reg 14 drivers/iommu/msm_iommu_hw-8xxx.h #define SET_GLOBAL_REG(reg, base, val) writel((val), ((base) + (reg))) reg 16 drivers/iommu/msm_iommu_hw-8xxx.h #define SET_CTX_REG(reg, base, ctx, val) \ reg 17 drivers/iommu/msm_iommu_hw-8xxx.h writel((val), ((base) + (reg) + ((ctx) << CTX_SHIFT))) reg 784 drivers/iommu/mtk_iommu.c struct mtk_iommu_suspend_reg *reg = &data->reg; reg 787 drivers/iommu/mtk_iommu.c reg->standard_axi_mode = readl_relaxed(base + reg 789 drivers/iommu/mtk_iommu.c reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); reg 790 drivers/iommu/mtk_iommu.c reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); reg 791 drivers/iommu/mtk_iommu.c reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); reg 792 drivers/iommu/mtk_iommu.c reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); reg 793 drivers/iommu/mtk_iommu.c reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR); reg 794 drivers/iommu/mtk_iommu.c reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); reg 802 drivers/iommu/mtk_iommu.c struct mtk_iommu_suspend_reg *reg = &data->reg; reg 812 drivers/iommu/mtk_iommu.c writel_relaxed(reg->standard_axi_mode, reg 814 drivers/iommu/mtk_iommu.c writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); reg 815 drivers/iommu/mtk_iommu.c writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); reg 816 drivers/iommu/mtk_iommu.c writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); reg 817 drivers/iommu/mtk_iommu.c writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); reg 818 drivers/iommu/mtk_iommu.c writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); reg 819 drivers/iommu/mtk_iommu.c writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); reg 56 drivers/iommu/mtk_iommu.h struct mtk_iommu_suspend_reg reg; reg 662 drivers/iommu/mtk_iommu_v1.c struct mtk_iommu_suspend_reg *reg = &data->reg; reg 665 drivers/iommu/mtk_iommu_v1.c reg->standard_axi_mode = readl_relaxed(base + reg 667 drivers/iommu/mtk_iommu_v1.c reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM); reg 668 drivers/iommu/mtk_iommu_v1.c reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); reg 669 drivers/iommu/mtk_iommu_v1.c reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL); reg 676 drivers/iommu/mtk_iommu_v1.c struct mtk_iommu_suspend_reg *reg = &data->reg; reg 680 drivers/iommu/mtk_iommu_v1.c writel_relaxed(reg->standard_axi_mode, reg 682 drivers/iommu/mtk_iommu_v1.c writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM); reg 683 drivers/iommu/mtk_iommu_v1.c writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); reg 684 drivers/iommu/mtk_iommu_v1.c writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL); reg 93 drivers/iommu/qcom_iommu.c iommu_writel(struct qcom_iommu_ctx *ctx, unsigned reg, u32 val) reg 95 drivers/iommu/qcom_iommu.c writel_relaxed(val, ctx->base + reg); reg 99 drivers/iommu/qcom_iommu.c iommu_writeq(struct qcom_iommu_ctx *ctx, unsigned reg, u64 val) reg 101 drivers/iommu/qcom_iommu.c writeq_relaxed(val, ctx->base + reg); reg 105 drivers/iommu/qcom_iommu.c iommu_readl(struct qcom_iommu_ctx *ctx, unsigned reg) reg 107 drivers/iommu/qcom_iommu.c return readl_relaxed(ctx->base + reg); reg 111 drivers/iommu/qcom_iommu.c iommu_readq(struct qcom_iommu_ctx *ctx, unsigned reg) reg 113 drivers/iommu/qcom_iommu.c return readq_relaxed(ctx->base + reg); reg 151 drivers/iommu/qcom_iommu.c unsigned i, reg; reg 153 drivers/iommu/qcom_iommu.c reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA; reg 162 drivers/iommu/qcom_iommu.c iommu_writel(ctx, reg, iova); reg 231 drivers/iommu/qcom_iommu.c u32 reg; reg 292 drivers/iommu/qcom_iommu.c reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE | reg 296 drivers/iommu/qcom_iommu.c reg |= SCTLR_E; reg 298 drivers/iommu/qcom_iommu.c iommu_writel(ctx, ARM_SMMU_CB_SCTLR, reg); reg 692 drivers/iommu/qcom_iommu.c u32 reg; reg 697 drivers/iommu/qcom_iommu.c if (of_property_read_u32_index(np, "reg", 0, ®)) reg 700 drivers/iommu/qcom_iommu.c return reg / 0x1000; /* context banks are 0x1000 apart */ reg 360 drivers/iommu/tegra-smmu.c value = smmu_readl(smmu, client->smmu.reg); reg 362 drivers/iommu/tegra-smmu.c smmu_writel(smmu, value, client->smmu.reg); reg 367 drivers/iommu/tegra-smmu.c value = smmu_readl(smmu, group->reg); reg 371 drivers/iommu/tegra-smmu.c smmu_writel(smmu, value, group->reg); reg 384 drivers/iommu/tegra-smmu.c value = smmu_readl(smmu, group->reg); reg 388 drivers/iommu/tegra-smmu.c smmu_writel(smmu, value, group->reg); reg 397 drivers/iommu/tegra-smmu.c value = smmu_readl(smmu, client->smmu.reg); reg 399 drivers/iommu/tegra-smmu.c smmu_writel(smmu, value, client->smmu.reg); reg 932 drivers/iommu/tegra-smmu.c value = smmu_readl(smmu, group->reg); reg 963 drivers/iommu/tegra-smmu.c value = smmu_readl(smmu, client->smmu.reg); reg 274 drivers/irqchip/irq-armada-370-xp.c u32 reg; reg 294 drivers/irqchip/irq-armada-370-xp.c reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS) reg 297 drivers/irqchip/irq-armada-370-xp.c writel(reg, per_cpu_int_base + reg 320 drivers/irqchip/irq-armada-370-xp.c unsigned long reg, mask; reg 328 drivers/irqchip/irq-armada-370-xp.c reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); reg 329 drivers/irqchip/irq-armada-370-xp.c reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask; reg 330 drivers/irqchip/irq-armada-370-xp.c writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); reg 28 drivers/irqchip/irq-bcm2836.c void __iomem *reg = intc.base + reg_offset + 4 * cpu; reg 30 drivers/irqchip/irq-bcm2836.c writel(readl(reg) & ~BIT(bit), reg); reg 37 drivers/irqchip/irq-bcm2836.c void __iomem *reg = intc.base + reg_offset + 4 * cpu; reg 39 drivers/irqchip/irq-bcm2836.c writel(readl(reg) | BIT(bit), reg); reg 98 drivers/irqchip/irq-bcm7038-l1.c static inline u32 l1_readl(void __iomem *reg) reg 101 drivers/irqchip/irq-bcm7038-l1.c return ioread32be(reg); reg 103 drivers/irqchip/irq-bcm7038-l1.c return readl(reg); reg 106 drivers/irqchip/irq-bcm7038-l1.c static inline void l1_writel(u32 val, void __iomem *reg) reg 109 drivers/irqchip/irq-bcm7038-l1.c iowrite32be(val, reg); reg 111 drivers/irqchip/irq-bcm7038-l1.c writel(val, reg); reg 87 drivers/irqchip/irq-davinci-aintc.c req = request_mem_region(config->reg.start, reg 88 drivers/irqchip/irq-davinci-aintc.c resource_size(&config->reg), reg 95 drivers/irqchip/irq-davinci-aintc.c davinci_aintc_base = ioremap(config->reg.start, reg 96 drivers/irqchip/irq-davinci-aintc.c resource_size(&config->reg)); reg 76 drivers/irqchip/irq-davinci-cp-intc.c unsigned int reg, mask, polarity, type; reg 78 drivers/irqchip/irq-davinci-cp-intc.c reg = BIT_WORD(d->hwirq); reg 80 drivers/irqchip/irq-davinci-cp-intc.c polarity = davinci_cp_intc_read(DAVINCI_CP_INTC_SYS_POLARITY(reg)); reg 81 drivers/irqchip/irq-davinci-cp-intc.c type = davinci_cp_intc_read(DAVINCI_CP_INTC_SYS_TYPE(reg)); reg 104 drivers/irqchip/irq-davinci-cp-intc.c davinci_cp_intc_write(polarity, DAVINCI_CP_INTC_SYS_POLARITY(reg)); reg 105 drivers/irqchip/irq-davinci-cp-intc.c davinci_cp_intc_write(type, DAVINCI_CP_INTC_SYS_TYPE(reg)); reg 166 drivers/irqchip/irq-davinci-cp-intc.c req = request_mem_region(config->reg.start, reg 167 drivers/irqchip/irq-davinci-cp-intc.c resource_size(&config->reg), reg 174 drivers/irqchip/irq-davinci-cp-intc.c davinci_cp_intc_base = ioremap(config->reg.start, reg 175 drivers/irqchip/irq-davinci-cp-intc.c resource_size(&config->reg)); reg 244 drivers/irqchip/irq-davinci-cp-intc.c ret = of_address_to_resource(node, 0, &config.reg); reg 77 drivers/irqchip/irq-dw-apb-ictl.c u32 reg; reg 117 drivers/irqchip/irq-dw-apb-ictl.c reg = readl_relaxed(iobase + APB_INT_ENABLE_H); reg 118 drivers/irqchip/irq-dw-apb-ictl.c if (reg) reg 119 drivers/irqchip/irq-dw-apb-ictl.c nrirqs = 32 + fls(reg); reg 266 drivers/irqchip/irq-gic-v3-mbi.c const __be32 *reg; reg 303 drivers/irqchip/irq-gic-v3-mbi.c reg = of_get_property(np, "mbi-alias", NULL); reg 304 drivers/irqchip/irq-gic-v3-mbi.c if (reg) { reg 305 drivers/irqchip/irq-gic-v3-mbi.c mbi_phys_base = of_translate_address(np, reg); reg 363 drivers/irqchip/irq-gic-v3.c u32 reg; reg 370 drivers/irqchip/irq-gic-v3.c reg = val ? GICD_ISPENDR : GICD_ICPENDR; reg 374 drivers/irqchip/irq-gic-v3.c reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; reg 378 drivers/irqchip/irq-gic-v3.c reg = val ? GICD_ICENABLER : GICD_ISENABLER; reg 385 drivers/irqchip/irq-gic-v3.c gic_poke_irq(d, reg); reg 773 drivers/irqchip/irq-gic-v3.c u32 reg; reg 775 drivers/irqchip/irq-gic-v3.c reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; reg 776 drivers/irqchip/irq-gic-v3.c if (reg != GIC_PIDR2_ARCH_GICv3 && reg 777 drivers/irqchip/irq-gic-v3.c reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ reg 1133 drivers/irqchip/irq-gic-v3.c void __iomem *reg; reg 1154 drivers/irqchip/irq-gic-v3.c reg = gic_dist_base(d) + offset + (index * 8); reg 1157 drivers/irqchip/irq-gic-v3.c gic_write_irouter(val, reg); reg 1597 drivers/irqchip/irq-gic-v3.c u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; reg 1599 drivers/irqchip/irq-gic-v3.c if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) reg 1845 drivers/irqchip/irq-gic-v3.c u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; reg 1846 drivers/irqchip/irq-gic-v3.c u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; reg 244 drivers/irqchip/irq-gic.c u32 reg; reg 248 drivers/irqchip/irq-gic.c reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; reg 252 drivers/irqchip/irq-gic.c reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; reg 256 drivers/irqchip/irq-gic.c reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; reg 263 drivers/irqchip/irq-gic.c gic_poke_irq(d, reg); reg 332 drivers/irqchip/irq-gic.c void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); reg 348 drivers/irqchip/irq-gic.c val = readl_relaxed(reg) & ~mask; reg 349 drivers/irqchip/irq-gic.c writel_relaxed(val | bit, reg); reg 150 drivers/irqchip/irq-hip04.c void __iomem *reg; reg 163 drivers/irqchip/irq-hip04.c reg = hip04_dist_base(d) + GIC_DIST_TARGET + ((hip04_irq(d) * 2) & ~3); reg 166 drivers/irqchip/irq-hip04.c val = readl_relaxed(reg) & ~mask; reg 167 drivers/irqchip/irq-hip04.c writel_relaxed(val | bit, reg); reg 39 drivers/irqchip/irq-imx-gpcv2.c void __iomem *reg; reg 47 drivers/irqchip/irq-imx-gpcv2.c reg = gpcv2_idx_to_reg(cd, i); reg 48 drivers/irqchip/irq-imx-gpcv2.c cd->saved_irq_mask[i] = readl_relaxed(reg); reg 49 drivers/irqchip/irq-imx-gpcv2.c writel_relaxed(cd->wakeup_sources[i], reg); reg 98 drivers/irqchip/irq-imx-gpcv2.c void __iomem *reg; reg 102 drivers/irqchip/irq-imx-gpcv2.c reg = gpcv2_idx_to_reg(cd, d->hwirq / 32); reg 103 drivers/irqchip/irq-imx-gpcv2.c val = readl_relaxed(reg); reg 105 drivers/irqchip/irq-imx-gpcv2.c writel_relaxed(val, reg); reg 114 drivers/irqchip/irq-imx-gpcv2.c void __iomem *reg; reg 118 drivers/irqchip/irq-imx-gpcv2.c reg = gpcv2_idx_to_reg(cd, d->hwirq / 32); reg 119 drivers/irqchip/irq-imx-gpcv2.c val = readl_relaxed(reg); reg 121 drivers/irqchip/irq-imx-gpcv2.c writel_relaxed(val, reg); reg 256 drivers/irqchip/irq-imx-gpcv2.c void __iomem *reg = cd->gpc_base + i * 4; reg 260 drivers/irqchip/irq-imx-gpcv2.c writel_relaxed(~0, reg + GPC_IMR1_CORE2); reg 261 drivers/irqchip/irq-imx-gpcv2.c writel_relaxed(~0, reg + GPC_IMR1_CORE3); reg 264 drivers/irqchip/irq-imx-gpcv2.c writel_relaxed(~0, reg + GPC_IMR1_CORE0); reg 265 drivers/irqchip/irq-imx-gpcv2.c writel_relaxed(~0, reg + GPC_IMR1_CORE1); reg 34 drivers/irqchip/irq-lpc32xx.c static inline u32 lpc32xx_ic_read(struct lpc32xx_irq_chip *ic, u32 reg) reg 36 drivers/irqchip/irq-lpc32xx.c return readl_relaxed(ic->base + reg); reg 40 drivers/irqchip/irq-lpc32xx.c u32 reg, u32 val) reg 42 drivers/irqchip/irq-lpc32xx.c writel_relaxed(val, ic->base + reg); reg 179 drivers/irqchip/irq-lpc32xx.c const __be32 *reg = of_get_property(node, "reg", NULL); reg 180 drivers/irqchip/irq-lpc32xx.c u32 parent_irq, i, addr = reg ? be32_to_cpu(*reg) : 0; reg 42 drivers/irqchip/irq-ls-scfg-msi.c void __iomem *reg; reg 201 drivers/irqchip/irq-ls-scfg-msi.c val = ioread32be(msir->reg); reg 255 drivers/irqchip/irq-ls-scfg-msi.c msir->reg = msi_data->regs + msi_data->cfg->msir_base + 4 * index; reg 93 drivers/irqchip/irq-meson-gpio.c unsigned int reg, u32 mask, u32 val) reg 97 drivers/irqchip/irq-meson-gpio.c tmp = readl_relaxed(ctl->base + reg); reg 100 drivers/irqchip/irq-meson-gpio.c writel_relaxed(tmp, ctl->base + reg); reg 113 drivers/irqchip/irq-meson-gpio.c unsigned int reg, idx; reg 132 drivers/irqchip/irq-meson-gpio.c reg = meson_gpio_irq_channel_to_reg(idx); reg 133 drivers/irqchip/irq-meson-gpio.c meson_gpio_irq_update_bits(ctl, reg, reg 487 drivers/irqchip/irq-mmp.c u32 reg[4]; reg 506 drivers/irqchip/irq-mmp.c ret = of_property_read_variable_u32_array(node, "reg", reg, reg 507 drivers/irqchip/irq-mmp.c ARRAY_SIZE(reg), reg 508 drivers/irqchip/irq-mmp.c ARRAY_SIZE(reg)); reg 513 drivers/irqchip/irq-mmp.c icu_data[i].reg_status = mmp_icu_base + reg[0]; reg 514 drivers/irqchip/irq-mmp.c icu_data[i].reg_mask = mmp_icu_base + reg[2]; reg 47 drivers/irqchip/irq-mscc-ocelot.c u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(0)); reg 51 drivers/irqchip/irq-mscc-ocelot.c while (reg) { reg 52 drivers/irqchip/irq-mscc-ocelot.c u32 hwirq = __fls(reg); reg 55 drivers/irqchip/irq-mscc-ocelot.c reg &= ~(BIT(hwirq)); reg 52 drivers/irqchip/irq-mvebu-pic.c u32 reg; reg 54 drivers/irqchip/irq-mvebu-pic.c reg = readl(pic->base + PIC_MASK); reg 55 drivers/irqchip/irq-mvebu-pic.c reg |= (1 << d->hwirq); reg 56 drivers/irqchip/irq-mvebu-pic.c writel(reg, pic->base + PIC_MASK); reg 62 drivers/irqchip/irq-mvebu-pic.c u32 reg; reg 64 drivers/irqchip/irq-mvebu-pic.c reg = readl(pic->base + PIC_MASK); reg 65 drivers/irqchip/irq-mvebu-pic.c reg &= ~(1 << d->hwirq); reg 66 drivers/irqchip/irq-mvebu-pic.c writel(reg, pic->base + PIC_MASK); reg 68 drivers/irqchip/irq-mvebu-sei.c u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); reg 73 drivers/irqchip/irq-mvebu-sei.c reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx)); reg 74 drivers/irqchip/irq-mvebu-sei.c reg |= BIT(SEI_IRQ_REG_BIT(d->hwirq)); reg 75 drivers/irqchip/irq-mvebu-sei.c writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx)); reg 82 drivers/irqchip/irq-mvebu-sei.c u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); reg 87 drivers/irqchip/irq-mvebu-sei.c reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx)); reg 88 drivers/irqchip/irq-mvebu-sei.c reg &= ~BIT(SEI_IRQ_REG_BIT(d->hwirq)); reg 89 drivers/irqchip/irq-mvebu-sei.c writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx)); reg 72 drivers/irqchip/irq-omap-intc.c static void intc_writel(u32 reg, u32 val) reg 74 drivers/irqchip/irq-omap-intc.c writel_relaxed(val, omap_irq_base + reg); reg 77 drivers/irqchip/irq-omap-intc.c static u32 intc_readl(u32 reg) reg 79 drivers/irqchip/irq-omap-intc.c return readl_relaxed(omap_irq_base + reg); reg 290 drivers/irqchip/irq-omap-intc.c u32 reg; reg 292 drivers/irqchip/irq-omap-intc.c reg = intc_readl(INTC_PROTECTION); reg 293 drivers/irqchip/irq-omap-intc.c reg |= INTC_PROTECTION_ENABLE; reg 294 drivers/irqchip/irq-omap-intc.c intc_writel(INTC_PROTECTION, reg); reg 108 drivers/irqchip/irq-pic32-evic.c u32 reg, shift; reg 110 drivers/irqchip/irq-pic32-evic.c reg = irq / 4; reg 114 drivers/irqchip/irq-pic32-evic.c evic_base + PIC32_CLR(REG_IPC_OFFSET + reg * 0x10)); reg 116 drivers/irqchip/irq-pic32-evic.c evic_base + PIC32_SET(REG_IPC_OFFSET + reg * 0x10)); reg 132 drivers/irqchip/irq-pic32-evic.c u32 reg, mask; reg 150 drivers/irqchip/irq-pic32-evic.c IRQ_REG_MASK(hw, reg, mask); reg 152 drivers/irqchip/irq-pic32-evic.c iecclr = PIC32_CLR(REG_IEC_OFFSET + reg * 0x10); reg 153 drivers/irqchip/irq-pic32-evic.c ifsclr = PIC32_CLR(REG_IFS_OFFSET + reg * 0x10); reg 99 drivers/irqchip/irq-renesas-intc-irqpin.c int reg) reg 101 drivers/irqchip/irq-renesas-intc-irqpin.c struct intc_irqpin_iomem *i = &p->iomem[reg]; reg 107 drivers/irqchip/irq-renesas-intc-irqpin.c int reg, unsigned long data) reg 109 drivers/irqchip/irq-renesas-intc-irqpin.c struct intc_irqpin_iomem *i = &p->iomem[reg]; reg 115 drivers/irqchip/irq-renesas-intc-irqpin.c int reg, int hw_irq) reg 117 drivers/irqchip/irq-renesas-intc-irqpin.c return BIT((p->iomem[reg].width - 1) - hw_irq); reg 121 drivers/irqchip/irq-renesas-intc-irqpin.c int reg, int hw_irq) reg 123 drivers/irqchip/irq-renesas-intc-irqpin.c intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq)); reg 129 drivers/irqchip/irq-renesas-intc-irqpin.c int reg, int shift, reg 137 drivers/irqchip/irq-renesas-intc-irqpin.c tmp = intc_irqpin_read(p, reg); reg 140 drivers/irqchip/irq-renesas-intc-irqpin.c intc_irqpin_write(p, reg, tmp); reg 36 drivers/irqchip/irq-sa11x0.c u32 reg; reg 38 drivers/irqchip/irq-sa11x0.c reg = readl_relaxed(iobase + ICMR); reg 39 drivers/irqchip/irq-sa11x0.c reg &= ~BIT(d->hwirq); reg 40 drivers/irqchip/irq-sa11x0.c writel_relaxed(reg, iobase + ICMR); reg 45 drivers/irqchip/irq-sa11x0.c u32 reg; reg 47 drivers/irqchip/irq-sa11x0.c reg = readl_relaxed(iobase + ICMR); reg 48 drivers/irqchip/irq-sa11x0.c reg |= BIT(d->hwirq); reg 49 drivers/irqchip/irq-sa11x0.c writel_relaxed(reg, iobase + ICMR); reg 75 drivers/irqchip/irq-sifive-plic.c u32 __iomem *reg = handler->enable_base + (hwirq / 32) * sizeof(u32); reg 80 drivers/irqchip/irq-sifive-plic.c writel(readl(reg) | hwirq_mask, reg); reg 82 drivers/irqchip/irq-sifive-plic.c writel(readl(reg) & ~hwirq_mask, reg); reg 434 drivers/irqchip/irq-stm32-exti.c static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg) reg 440 drivers/irqchip/irq-stm32-exti.c val = readl_relaxed(base + reg); reg 442 drivers/irqchip/irq-stm32-exti.c writel_relaxed(val, base + reg); reg 447 drivers/irqchip/irq-stm32-exti.c static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg) reg 453 drivers/irqchip/irq-stm32-exti.c val = readl_relaxed(base + reg); reg 455 drivers/irqchip/irq-stm32-exti.c writel_relaxed(val, base + reg); reg 63 drivers/irqchip/irq-sun4i.c int reg = irq / 32; reg 67 drivers/irqchip/irq-sun4i.c SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); reg 69 drivers/irqchip/irq-sun4i.c irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); reg 76 drivers/irqchip/irq-sun4i.c int reg = irq / 32; reg 80 drivers/irqchip/irq-sun4i.c SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); reg 82 drivers/irqchip/irq-sun4i.c irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); reg 45 drivers/irqchip/irq-tango.c static inline u32 intc_readl(struct tangox_irq_chip *chip, int reg) reg 47 drivers/irqchip/irq-tango.c return readl_relaxed(chip->base + reg); reg 50 drivers/irqchip/irq-tango.c static inline void intc_writel(struct tangox_irq_chip *chip, int reg, u32 val) reg 52 drivers/irqchip/irq-tango.c writel_relaxed(val, chip->base + reg); reg 31 drivers/irqchip/irq-tb10x.c static inline void ab_irqctl_writereg(struct irq_chip_generic *gc, u32 reg, reg 34 drivers/irqchip/irq-tb10x.c irq_reg_writel(gc, val, reg); reg 37 drivers/irqchip/irq-tb10x.c static inline u32 ab_irqctl_readreg(struct irq_chip_generic *gc, u32 reg) reg 39 drivers/irqchip/irq-tb10x.c return irq_reg_readl(gc, reg); reg 82 drivers/irqchip/irq-tegra.c static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long reg) reg 88 drivers/irqchip/irq-tegra.c writel_relaxed(mask, base + reg); reg 35 drivers/irqchip/irq-ts4800.c u16 reg = readw(data->base + IRQ_MASK); reg 38 drivers/irqchip/irq-ts4800.c writew(reg | mask, data->base + IRQ_MASK); reg 44 drivers/irqchip/irq-ts4800.c u16 reg = readw(data->base + IRQ_MASK); reg 47 drivers/irqchip/irq-ts4800.c writew(reg & ~mask, data->base + IRQ_MASK); reg 32 drivers/irqchip/irq-uniphier-aidet.c unsigned int reg, u32 mask, u32 val) reg 38 drivers/irqchip/irq-uniphier-aidet.c tmp = readl_relaxed(priv->reg_base + reg); reg 41 drivers/irqchip/irq-uniphier-aidet.c writel_relaxed(tmp, priv->reg_base + reg); reg 48 drivers/irqchip/irq-uniphier-aidet.c unsigned int reg; reg 51 drivers/irqchip/irq-uniphier-aidet.c reg = UNIPHIER_AIDET_DETCONF + index / 32 * 4; reg 54 drivers/irqchip/irq-uniphier-aidet.c uniphier_aidet_reg_update(priv, reg, mask, val ? mask : 0); reg 91 drivers/irqchip/irq-vic.c void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); reg 92 drivers/irqchip/irq-vic.c writel(VIC_VECT_CNTL_ENABLE | i, reg); reg 421 drivers/irqchip/irq-vic.c void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); reg 422 drivers/irqchip/irq-vic.c writel(0, reg); reg 45 drivers/irqchip/irq-xilinx-intc.c static void xintc_write(int reg, u32 data) reg 48 drivers/irqchip/irq-xilinx-intc.c iowrite32be(data, xintc_irqc->base + reg); reg 50 drivers/irqchip/irq-xilinx-intc.c iowrite32(data, xintc_irqc->base + reg); reg 53 drivers/irqchip/irq-xilinx-intc.c static unsigned int xintc_read(int reg) reg 56 drivers/irqchip/irq-xilinx-intc.c return ioread32be(xintc_irqc->base + reg); reg 58 drivers/irqchip/irq-xilinx-intc.c return ioread32(xintc_irqc->base + reg); reg 39 drivers/irqchip/qcom-irq-combiner.c static inline int irq_nr(u32 reg, u32 bit) reg 41 drivers/irqchip/qcom-irq-combiner.c return reg * REG_SIZE + bit; reg 51 drivers/irqchip/qcom-irq-combiner.c u32 reg; reg 55 drivers/irqchip/qcom-irq-combiner.c for (reg = 0; reg < combiner->nregs; reg++) { reg 61 drivers/irqchip/qcom-irq-combiner.c bit = readl_relaxed(combiner->regs[reg].addr); reg 62 drivers/irqchip/qcom-irq-combiner.c status = bit & combiner->regs[reg].enabled; reg 66 drivers/irqchip/qcom-irq-combiner.c combiner->regs[reg].enabled, reg 67 drivers/irqchip/qcom-irq-combiner.c combiner->regs[reg].addr); reg 72 drivers/irqchip/qcom-irq-combiner.c hwirq = irq_nr(reg, bit); reg 86 drivers/irqchip/qcom-irq-combiner.c struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE; reg 88 drivers/irqchip/qcom-irq-combiner.c clear_bit(data->hwirq % REG_SIZE, ®->enabled); reg 94 drivers/irqchip/qcom-irq-combiner.c struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE; reg 96 drivers/irqchip/qcom-irq-combiner.c set_bit(data->hwirq % REG_SIZE, ®->enabled); reg 179 drivers/irqchip/qcom-irq-combiner.c struct acpi_resource_generic_register *reg; reg 186 drivers/irqchip/qcom-irq-combiner.c reg = &ares->data.generic_reg; reg 187 drivers/irqchip/qcom-irq-combiner.c paddr = reg->address; reg 188 drivers/irqchip/qcom-irq-combiner.c if ((reg->space_id != ACPI_SPACE_MEM) || reg 189 drivers/irqchip/qcom-irq-combiner.c (reg->bit_offset != 0) || reg 190 drivers/irqchip/qcom-irq-combiner.c (reg->bit_width > REG_SIZE)) { reg 196 drivers/irqchip/qcom-irq-combiner.c vaddr = devm_ioremap(ctx->dev, reg->address, REG_SIZE); reg 204 drivers/irqchip/qcom-irq-combiner.c ctx->combiner->nirqs += reg->bit_width; reg 23 drivers/irqchip/qcom-pdc.c #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr)) reg 24 drivers/irqchip/qcom-pdc.c #define ENABLE_INTR(reg, intr) (reg | (1 << intr)) reg 40 drivers/irqchip/qcom-pdc.c static void pdc_reg_write(int reg, u32 i, u32 val) reg 42 drivers/irqchip/qcom-pdc.c writel_relaxed(val, pdc_base + reg + i * sizeof(u32)); reg 45 drivers/irqchip/qcom-pdc.c static u32 pdc_reg_read(int reg, u32 i) reg 47 drivers/irqchip/qcom-pdc.c return readl_relaxed(pdc_base + reg + i * sizeof(u32)); reg 62 drivers/irqchip/spear-shirq.c u32 __iomem *reg = shirq->base + shirq->mask_reg; reg 65 drivers/irqchip/spear-shirq.c val = readl(reg) & ~(0x1 << shift); reg 66 drivers/irqchip/spear-shirq.c writel(val, reg); reg 74 drivers/irqchip/spear-shirq.c u32 __iomem *reg = shirq->base + shirq->mask_reg; reg 77 drivers/irqchip/spear-shirq.c val = readl(reg) | (0x1 << shift); reg 78 drivers/irqchip/spear-shirq.c writel(val, reg); reg 151 drivers/isdn/hardware/mISDN/hfc_multi.h void (*HFC_outb)(struct hfc_multi *hc, u_char reg, reg 153 drivers/isdn/hardware/mISDN/hfc_multi.h void (*HFC_outb_nodebug)(struct hfc_multi *hc, u_char reg, reg 155 drivers/isdn/hardware/mISDN/hfc_multi.h u_char (*HFC_inb)(struct hfc_multi *hc, u_char reg, reg 157 drivers/isdn/hardware/mISDN/hfc_multi.h u_char (*HFC_inb_nodebug)(struct hfc_multi *hc, u_char reg, reg 159 drivers/isdn/hardware/mISDN/hfc_multi.h u_short (*HFC_inw)(struct hfc_multi *hc, u_char reg, reg 161 drivers/isdn/hardware/mISDN/hfc_multi.h u_short (*HFC_inw_nodebug)(struct hfc_multi *hc, u_char reg, reg 168 drivers/isdn/hardware/mISDN/hfc_multi.h void (*HFC_outb)(struct hfc_multi *hc, u_char reg, reg 170 drivers/isdn/hardware/mISDN/hfc_multi.h void (*HFC_outb_nodebug)(struct hfc_multi *hc, u_char reg, reg 172 drivers/isdn/hardware/mISDN/hfc_multi.h u_char (*HFC_inb)(struct hfc_multi *hc, u_char reg); reg 173 drivers/isdn/hardware/mISDN/hfc_multi.h u_char (*HFC_inb_nodebug)(struct hfc_multi *hc, u_char reg); reg 174 drivers/isdn/hardware/mISDN/hfc_multi.h u_short (*HFC_inw)(struct hfc_multi *hc, u_char reg); reg 175 drivers/isdn/hardware/mISDN/hfc_multi.h u_short (*HFC_inw_nodebug)(struct hfc_multi *hc, u_char reg); reg 1092 drivers/isdn/hardware/mISDN/hfc_multi.h u_char reg; reg 19 drivers/isdn/hardware/mISDN/hfc_multi_8xx.h HFC_outb_embsd(struct hfc_multi *hc, u_char reg, u_char val, reg 22 drivers/isdn/hardware/mISDN/hfc_multi_8xx.h HFC_outb_embsd(struct hfc_multi *hc, u_char reg, u_char val) reg 26 drivers/isdn/hardware/mISDN/hfc_multi_8xx.h writeb(reg, hc->xhfc_memaddr); reg 32 drivers/isdn/hardware/mISDN/hfc_multi_8xx.h HFC_inb_embsd(struct hfc_multi *hc, u_char reg, const char *function, int line) reg 34 drivers/isdn/hardware/mISDN/hfc_multi_8xx.h HFC_inb_embsd(struct hfc_multi *hc, u_char reg) reg 38 drivers/isdn/hardware/mISDN/hfc_multi_8xx.h writeb(reg, hc->xhfc_memaddr); reg 44 drivers/isdn/hardware/mISDN/hfc_multi_8xx.h HFC_inw_embsd(struct hfc_multi *hc, u_char reg, const char *function, int line) reg 46 drivers/isdn/hardware/mISDN/hfc_multi_8xx.h HFC_inw_embsd(struct hfc_multi *hc, u_char reg) reg 50 drivers/isdn/hardware/mISDN/hfc_multi_8xx.h writeb(reg, hc->xhfc_memaddr); reg 241 drivers/isdn/hardware/mISDN/hfcmulti.c #define HFC_outb(hc, reg, val) \ reg 242 drivers/isdn/hardware/mISDN/hfcmulti.c (hc->HFC_outb(hc, reg, val, __func__, __LINE__)) reg 243 drivers/isdn/hardware/mISDN/hfcmulti.c #define HFC_outb_nodebug(hc, reg, val) \ reg 244 drivers/isdn/hardware/mISDN/hfcmulti.c (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__)) reg 245 drivers/isdn/hardware/mISDN/hfcmulti.c #define HFC_inb(hc, reg) \ reg 246 drivers/isdn/hardware/mISDN/hfcmulti.c (hc->HFC_inb(hc, reg, __func__, __LINE__)) reg 247 drivers/isdn/hardware/mISDN/hfcmulti.c #define HFC_inb_nodebug(hc, reg) \ reg 248 drivers/isdn/hardware/mISDN/hfcmulti.c (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__)) reg 249 drivers/isdn/hardware/mISDN/hfcmulti.c #define HFC_inw(hc, reg) \ reg 250 drivers/isdn/hardware/mISDN/hfcmulti.c (hc->HFC_inw(hc, reg, __func__, __LINE__)) reg 251 drivers/isdn/hardware/mISDN/hfcmulti.c #define HFC_inw_nodebug(hc, reg) \ reg 252 drivers/isdn/hardware/mISDN/hfcmulti.c (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__)) reg 258 drivers/isdn/hardware/mISDN/hfcmulti.c #define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val)) reg 259 drivers/isdn/hardware/mISDN/hfcmulti.c #define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val)) reg 260 drivers/isdn/hardware/mISDN/hfcmulti.c #define HFC_inb(hc, reg) (hc->HFC_inb(hc, reg)) reg 261 drivers/isdn/hardware/mISDN/hfcmulti.c #define HFC_inb_nodebug(hc, reg) (hc->HFC_inb_nodebug(hc, reg)) reg 262 drivers/isdn/hardware/mISDN/hfcmulti.c #define HFC_inw(hc, reg) (hc->HFC_inw(hc, reg)) reg 263 drivers/isdn/hardware/mISDN/hfcmulti.c #define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg)) reg 275 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val, reg 278 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val) reg 281 drivers/isdn/hardware/mISDN/hfcmulti.c writeb(val, hc->pci_membase + reg); reg 285 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line) reg 287 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_inb_pcimem(struct hfc_multi *hc, u_char reg) reg 290 drivers/isdn/hardware/mISDN/hfcmulti.c return readb(hc->pci_membase + reg); reg 294 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line) reg 296 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_inw_pcimem(struct hfc_multi *hc, u_char reg) reg 299 drivers/isdn/hardware/mISDN/hfcmulti.c return readw(hc->pci_membase + reg); reg 315 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val, reg 318 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val) reg 321 drivers/isdn/hardware/mISDN/hfcmulti.c outb(reg, hc->pci_iobase + 4); reg 326 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line) reg 328 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_inb_regio(struct hfc_multi *hc, u_char reg) reg 331 drivers/isdn/hardware/mISDN/hfcmulti.c outb(reg, hc->pci_iobase + 4); reg 336 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line) reg 338 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_inw_regio(struct hfc_multi *hc, u_char reg) reg 341 drivers/isdn/hardware/mISDN/hfcmulti.c outb(reg, hc->pci_iobase + 4); reg 358 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val, reg 366 drivers/isdn/hardware/mISDN/hfcmulti.c if (hfc_register_names[i].reg == reg) reg 382 drivers/isdn/hardware/mISDN/hfcmulti.c hc->id, reg, regname, val, bits, function, line); reg 383 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_outb_nodebug(hc, reg, val); reg 386 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line) reg 389 drivers/isdn/hardware/mISDN/hfcmulti.c u_char val = HFC_inb_nodebug(hc, reg); reg 396 drivers/isdn/hardware/mISDN/hfcmulti.c if (hfc_register_names[i].reg == reg) reg 412 drivers/isdn/hardware/mISDN/hfcmulti.c hc->id, reg, regname, val, bits, function, line); reg 416 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line) reg 419 drivers/isdn/hardware/mISDN/hfcmulti.c u_short val = HFC_inw_nodebug(hc, reg); reg 426 drivers/isdn/hardware/mISDN/hfcmulti.c if (hfc_register_names[i].reg == reg) reg 434 drivers/isdn/hardware/mISDN/hfcmulti.c hc->id, reg, regname, val, function, line); reg 624 drivers/isdn/hardware/mISDN/hfcmulti.c cpld_set_reg(struct hfc_multi *hc, unsigned char reg) reg 627 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_outb(hc, R_GPIO_OUT1, reg); reg 631 drivers/isdn/hardware/mISDN/hfcmulti.c cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val) reg 633 drivers/isdn/hardware/mISDN/hfcmulti.c cpld_set_reg(hc, reg); reg 643 drivers/isdn/hardware/mISDN/hfcmulti.c cpld_read_reg(struct hfc_multi *hc, unsigned char reg) reg 647 drivers/isdn/hardware/mISDN/hfcmulti.c cpld_set_reg(hc, reg); reg 650 drivers/isdn/hardware/mISDN/hfcmulti.c HFC_outb(hc, R_GPIO_OUT1, reg); reg 734 drivers/isdn/hardware/mISDN/hfcmulti.c unsigned char reg; reg 753 drivers/isdn/hardware/mISDN/hfcmulti.c reg = vpm_in(wc, x, 0x1a3); /* misc_con */ reg 754 drivers/isdn/hardware/mISDN/hfcmulti.c vpm_out(wc, x, 0x1a3, reg & ~2); reg 770 drivers/isdn/hardware/mISDN/hfcmulti.c reg = 0x00 | 0x10 | 0x01; reg 771 drivers/isdn/hardware/mISDN/hfcmulti.c vpm_out(wc, x, 0x20, reg); reg 772 drivers/isdn/hardware/mISDN/hfcmulti.c printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg); reg 776 drivers/isdn/hardware/mISDN/hfcmulti.c reg = vpm_in(wc, x, 0x24); reg 777 drivers/isdn/hardware/mISDN/hfcmulti.c printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg); reg 76 drivers/isdn/hardware/mISDN/hfcsusb.c static int write_reg(struct hfcsusb *hw, __u8 reg, __u8 val) reg 82 drivers/isdn/hardware/mISDN/hfcsusb.c hw->name, __func__, reg, val); reg 90 drivers/isdn/hardware/mISDN/hfcsusb.c buf->hfcs_reg = reg; reg 236 drivers/leds/leds-as3645a.c u8 reg; reg 239 drivers/leds/leds-as3645a.c reg = (flash->cfg.peak << AS_CONTROL_COIL_PEAK_SHIFT) reg 245 drivers/leds/leds-as3645a.c reg |= AS_CONTROL_STROBE_TYPE_LEVEL reg 248 drivers/leds/leds-as3645a.c return as3645a_write(flash, AS_CONTROL_REG, reg); reg 73 drivers/leds/leds-bcm6328.c static void bcm6328_led_write(void __iomem *reg, unsigned long data) reg 76 drivers/leds/leds-bcm6328.c iowrite32be(data, reg); reg 78 drivers/leds/leds-bcm6328.c writel(data, reg); reg 82 drivers/leds/leds-bcm6328.c static unsigned long bcm6328_led_read(void __iomem *reg) reg 85 drivers/leds/leds-bcm6328.c return ioread32be(reg); reg 87 drivers/leds/leds-bcm6328.c return readl(reg); reg 204 drivers/leds/leds-bcm6328.c static int bcm6328_hwled(struct device *dev, struct device_node *nc, u32 reg, reg 212 drivers/leds/leds-bcm6328.c val &= ~BIT(reg); reg 217 drivers/leds/leds-bcm6328.c if (reg >= 8) reg 226 drivers/leds/leds-bcm6328.c if (reg < 4) reg 234 drivers/leds/leds-bcm6328.c if (reg / 4 != sel / 4) { reg 241 drivers/leds/leds-bcm6328.c val |= (BIT(reg % 4) << (((sel % 4) * 4) + 16)); reg 253 drivers/leds/leds-bcm6328.c if (reg < 4) reg 261 drivers/leds/leds-bcm6328.c if (reg / 4 != sel / 4) { reg 268 drivers/leds/leds-bcm6328.c val |= (BIT(reg % 4) << ((sel % 4) * 4)); reg 276 drivers/leds/leds-bcm6328.c static int bcm6328_led(struct device *dev, struct device_node *nc, u32 reg, reg 288 drivers/leds/leds-bcm6328.c led->pin = reg; reg 396 drivers/leds/leds-bcm6328.c u32 reg; reg 398 drivers/leds/leds-bcm6328.c if (of_property_read_u32(child, "reg", ®)) reg 401 drivers/leds/leds-bcm6328.c if (reg >= BCM6328_LED_MAX_COUNT) { reg 402 drivers/leds/leds-bcm6328.c dev_err(dev, "invalid LED (%u >= %d)\n", reg, reg 408 drivers/leds/leds-bcm6328.c rc = bcm6328_hwled(dev, child, reg, mem, lock); reg 410 drivers/leds/leds-bcm6328.c rc = bcm6328_led(dev, child, reg, mem, lock, reg 46 drivers/leds/leds-bcm6358.c static void bcm6358_led_write(void __iomem *reg, unsigned long data) reg 49 drivers/leds/leds-bcm6358.c iowrite32be(data, reg); reg 51 drivers/leds/leds-bcm6358.c writel(data, reg); reg 55 drivers/leds/leds-bcm6358.c static unsigned long bcm6358_led_read(void __iomem *reg) reg 58 drivers/leds/leds-bcm6358.c return ioread32be(reg); reg 60 drivers/leds/leds-bcm6358.c return readl(reg); reg 94 drivers/leds/leds-bcm6358.c static int bcm6358_led(struct device *dev, struct device_node *nc, u32 reg, reg 105 drivers/leds/leds-bcm6358.c led->pin = reg; reg 197 drivers/leds/leds-bcm6358.c u32 reg; reg 199 drivers/leds/leds-bcm6358.c if (of_property_read_u32(child, "reg", ®)) reg 202 drivers/leds/leds-bcm6358.c if (reg >= BCM6358_SLED_MAX_COUNT) { reg 203 drivers/leds/leds-bcm6358.c dev_err(dev, "invalid LED (%u >= %d)\n", reg, reg 208 drivers/leds/leds-bcm6358.c rc = bcm6358_led(dev, child, reg, mem, lock); reg 158 drivers/leds/leds-bd2802.c static int bd2802_write_byte(struct i2c_client *client, u8 reg, u8 val) reg 160 drivers/leds/leds-bd2802.c int ret = i2c_smbus_write_byte_data(client, reg, val); reg 165 drivers/leds/leds-bd2802.c __func__, reg, val, ret); reg 218 drivers/leds/leds-bd2802.c u8 reg; reg 220 drivers/leds/leds-bd2802.c reg = bd2802_get_reg_addr(LED1, RED, BD2802_REG_HOURSETUP); reg 221 drivers/leds/leds-bd2802.c bd2802_write_byte(led->client, reg, pdata->rgb_time); reg 223 drivers/leds/leds-bd2802.c reg = bd2802_get_reg_addr(LED2, RED, BD2802_REG_HOURSETUP); reg 224 drivers/leds/leds-bd2802.c bd2802_write_byte(led->client, reg, pdata->rgb_time); reg 251 drivers/leds/leds-bd2802.c u8 reg; reg 256 drivers/leds/leds-bd2802.c reg = bd2802_get_reg_addr(id, color, BD2802_REG_CURRENT1SETUP); reg 257 drivers/leds/leds-bd2802.c bd2802_write_byte(led->client, reg, led->rgb_current); reg 258 drivers/leds/leds-bd2802.c reg = bd2802_get_reg_addr(id, color, BD2802_REG_CURRENT2SETUP); reg 259 drivers/leds/leds-bd2802.c bd2802_write_byte(led->client, reg, BD2802_CURRENT_000); reg 260 drivers/leds/leds-bd2802.c reg = bd2802_get_reg_addr(id, color, BD2802_REG_WAVEPATTERN); reg 261 drivers/leds/leds-bd2802.c bd2802_write_byte(led->client, reg, BD2802_PATTERN_FULL); reg 270 drivers/leds/leds-bd2802.c u8 reg; reg 275 drivers/leds/leds-bd2802.c reg = bd2802_get_reg_addr(id, color, BD2802_REG_CURRENT1SETUP); reg 276 drivers/leds/leds-bd2802.c bd2802_write_byte(led->client, reg, BD2802_CURRENT_000); reg 277 drivers/leds/leds-bd2802.c reg = bd2802_get_reg_addr(id, color, BD2802_REG_CURRENT2SETUP); reg 278 drivers/leds/leds-bd2802.c bd2802_write_byte(led->client, reg, led->rgb_current); reg 279 drivers/leds/leds-bd2802.c reg = bd2802_get_reg_addr(id, color, BD2802_REG_WAVEPATTERN); reg 280 drivers/leds/leds-bd2802.c bd2802_write_byte(led->client, reg, led->wave_pattern); reg 304 drivers/leds/leds-bd2802.c u8 reg; reg 309 drivers/leds/leds-bd2802.c reg = bd2802_get_reg_addr(id, color, BD2802_REG_CURRENT1SETUP); reg 310 drivers/leds/leds-bd2802.c bd2802_write_byte(led->client, reg, BD2802_CURRENT_000); reg 311 drivers/leds/leds-bd2802.c reg = bd2802_get_reg_addr(id, color, BD2802_REG_CURRENT2SETUP); reg 312 drivers/leds/leds-bd2802.c bd2802_write_byte(led->client, reg, BD2802_CURRENT_000); reg 18 drivers/leds/leds-cpcap.c u16 reg; reg 26 drivers/leds/leds-cpcap.c .reg = CPCAP_REG_REDC, reg 32 drivers/leds/leds-cpcap.c .reg = CPCAP_REG_GREENC, reg 38 drivers/leds/leds-cpcap.c .reg = CPCAP_REG_BLUEC, reg 45 drivers/leds/leds-cpcap.c .reg = CPCAP_REG_ADLC, reg 54 drivers/leds/leds-cpcap.c .reg = CPCAP_REG_CLEDC, reg 120 drivers/leds/leds-cpcap.c led->info->reg, led->info->mask, CPCAP_LED_NO_CURRENT); reg 131 drivers/leds/leds-cpcap.c err = regmap_update_bits(led->regmap, led->info->reg, led->info->mask, reg 176 drivers/leds/leds-cpcap.c if (led->info->reg == 0x0000) { reg 199 drivers/leds/leds-cpcap.c err = regmap_update_bits(led->regmap, led->info->reg, reg 231 drivers/leds/leds-is31fl319x.c u32 reg; reg 233 drivers/leds/leds-is31fl319x.c ret = of_property_read_u32(child, "reg", ®); reg 239 drivers/leds/leds-is31fl319x.c if (reg < 1 || reg > is31->cdef->num_leds) { reg 240 drivers/leds/leds-is31fl319x.c dev_err(dev, "invalid led reg %u\n", reg); reg 245 drivers/leds/leds-is31fl319x.c led = &is31->leds[reg - 1]; reg 248 drivers/leds/leds-is31fl319x.c dev_err(dev, "led %u is already configured\n", reg); reg 255 drivers/leds/leds-is31fl319x.c dev_err(dev, "led %u DT parsing failed\n", reg); reg 275 drivers/leds/leds-is31fl319x.c static bool is31fl319x_readable_reg(struct device *dev, unsigned int reg) reg 280 drivers/leds/leds-is31fl319x.c static bool is31fl319x_volatile_reg(struct device *dev, unsigned int reg) reg 282 drivers/leds/leds-is31fl319x.c switch (reg) { reg 137 drivers/leds/leds-is31fl32xx.c static int is31fl32xx_write(struct is31fl32xx_priv *priv, u8 reg, u8 val) reg 141 drivers/leds/leds-is31fl32xx.c dev_dbg(&priv->client->dev, "writing register 0x%02X=0x%02X", reg, val); reg 143 drivers/leds/leds-is31fl32xx.c ret = i2c_smbus_write_byte_data(priv->client, reg, val); reg 147 drivers/leds/leds-is31fl32xx.c reg, ret); reg 333 drivers/leds/leds-is31fl32xx.c u32 reg; reg 338 drivers/leds/leds-is31fl32xx.c ret = of_property_read_u32(child, "reg", ®); reg 339 drivers/leds/leds-is31fl32xx.c if (ret || reg < 1 || reg > led_data->priv->cdef->channels) { reg 345 drivers/leds/leds-is31fl32xx.c led_data->channel = reg; reg 248 drivers/leds/leds-lm3533.c u8 reg; reg 261 drivers/leds/leds-lm3533.c reg = lm3533_led_get_pattern_reg(led, base); reg 262 drivers/leds/leds-lm3533.c ret = lm3533_write(led->lm3533, reg, val); reg 264 drivers/leds/leds-lm3533.c dev_err(led->cdev.dev, "failed to set delay (%02x)\n", reg); reg 339 drivers/leds/leds-lm3533.c u8 reg; reg 342 drivers/leds/leds-lm3533.c reg = lm3533_led_get_pattern_reg(led, base); reg 343 drivers/leds/leds-lm3533.c ret = lm3533_read(led->lm3533, reg, &val); reg 371 drivers/leds/leds-lm3533.c u8 reg; reg 377 drivers/leds/leds-lm3533.c reg = lm3533_led_get_pattern_reg(led, base); reg 378 drivers/leds/leds-lm3533.c ret = lm3533_write(led->lm3533, reg, val); reg 407 drivers/leds/leds-lm3533.c u8 reg; reg 411 drivers/leds/leds-lm3533.c reg = lm3533_led_get_lv_reg(led, LM3533_REG_CTRLBANK_BCONF_BASE); reg 412 drivers/leds/leds-lm3533.c ret = lm3533_read(led->lm3533, reg, &val); reg 428 drivers/leds/leds-lm3533.c u8 reg; reg 440 drivers/leds/leds-lm3533.c reg = lm3533_led_get_lv_reg(led, LM3533_REG_CTRLBANK_BCONF_BASE); reg 444 drivers/leds/leds-lm3533.c ret = lm3533_update(led->lm3533, reg, val, mask); reg 457 drivers/leds/leds-lm3533.c u8 reg; reg 461 drivers/leds/leds-lm3533.c reg = lm3533_led_get_lv_reg(led, LM3533_REG_CTRLBANK_BCONF_BASE); reg 462 drivers/leds/leds-lm3533.c ret = lm3533_read(led->lm3533, reg, &val); reg 478 drivers/leds/leds-lm3533.c u8 reg; reg 486 drivers/leds/leds-lm3533.c reg = lm3533_led_get_lv_reg(led, LM3533_REG_CTRLBANK_BCONF_BASE); reg 494 drivers/leds/leds-lm3533.c ret = lm3533_update(led->lm3533, reg, val, mask); reg 506 drivers/leds/leds-lm3533.c u8 reg; reg 511 drivers/leds/leds-lm3533.c reg = lm3533_led_get_lv_reg(led, LM3533_REG_CTRLBANK_BCONF_BASE); reg 512 drivers/leds/leds-lm3533.c ret = lm3533_read(led->lm3533, reg, &val); reg 531 drivers/leds/leds-lm3533.c u8 reg; reg 539 drivers/leds/leds-lm3533.c reg = lm3533_led_get_lv_reg(led, LM3533_REG_CTRLBANK_BCONF_BASE); reg 547 drivers/leds/leds-lm3533.c ret = lm3533_update(led->lm3533, reg, val, mask); reg 109 drivers/leds/leds-lm3601x.c static bool lm3601x_volatile_reg(struct device *dev, unsigned int reg) reg 111 drivers/leds/leds-lm3601x.c switch (reg) { reg 76 drivers/leds/leds-lp3944.c static int lp3944_reg_read(struct i2c_client *client, u8 reg, u8 *value) reg 80 drivers/leds/leds-lp3944.c tmp = i2c_smbus_read_byte_data(client, reg); reg 89 drivers/leds/leds-lp3944.c static int lp3944_reg_write(struct i2c_client *client, u8 reg, u8 value) reg 91 drivers/leds/leds-lp3944.c return i2c_smbus_write_byte_data(client, reg, value); reg 170 drivers/leds/leds-lp3944.c u8 reg; reg 182 drivers/leds/leds-lp3944.c reg = LP3944_REG_LS0; reg 189 drivers/leds/leds-lp3944.c reg = LP3944_REG_LS1; reg 208 drivers/leds/leds-lp3944.c lp3944_reg_read(led->client, reg, &val); reg 214 drivers/leds/leds-lp3944.c __func__, led->ldev.name, reg, id, status, val); reg 217 drivers/leds/leds-lp3944.c err = lp3944_reg_write(led->client, reg, val); reg 23 drivers/leds/leds-lp3952.c static int lp3952_register_write(struct i2c_client *client, u8 reg, u8 val) reg 28 drivers/leds/leds-lp3952.c ret = regmap_write(priv->regmap, reg, val); reg 32 drivers/leds/leds-lp3952.c __func__, reg, val, ret); reg 61 drivers/leds/leds-lp3952.c unsigned int reg, shift_val; reg 81 drivers/leds/leds-lp3952.c reg = LP3952_REG_RGB1_MAX_I_CTRL; reg 84 drivers/leds/leds-lp3952.c reg = LP3952_REG_RGB2_MAX_I_CTRL; reg 91 drivers/leds/leds-lp3952.c return regmap_update_bits(priv->regmap, reg, 3 << shift_val, reg 319 drivers/leds/leds-lp55xx-common.c int lp55xx_write(struct lp55xx_chip *chip, u8 reg, u8 val) reg 321 drivers/leds/leds-lp55xx-common.c return i2c_smbus_write_byte_data(chip->cl, reg, val); reg 325 drivers/leds/leds-lp55xx-common.c int lp55xx_read(struct lp55xx_chip *chip, u8 reg, u8 *val) reg 329 drivers/leds/leds-lp55xx-common.c ret = i2c_smbus_read_byte_data(chip->cl, reg); reg 338 drivers/leds/leds-lp55xx-common.c int lp55xx_update_bits(struct lp55xx_chip *chip, u8 reg, u8 mask, u8 val) reg 343 drivers/leds/leds-lp55xx-common.c ret = lp55xx_read(chip, reg, &tmp); reg 350 drivers/leds/leds-lp55xx-common.c return lp55xx_write(chip, reg, tmp); reg 177 drivers/leds/leds-lp55xx-common.h extern int lp55xx_write(struct lp55xx_chip *chip, u8 reg, u8 val); reg 178 drivers/leds/leds-lp55xx-common.h extern int lp55xx_read(struct lp55xx_chip *chip, u8 reg, u8 *val); reg 179 drivers/leds/leds-lp55xx-common.h extern int lp55xx_update_bits(struct lp55xx_chip *chip, u8 reg, reg 108 drivers/leds/leds-lp8860.c uint8_t reg; reg 273 drivers/leds/leds-lp8860.c lp8860_eeprom_disp_regs[i].reg, reg 71 drivers/leds/leds-max77650.c u32 reg; reg 89 drivers/leds/leds-max77650.c rv = fwnode_property_read_u32(child, "reg", ®); reg 90 drivers/leds/leds-max77650.c if (rv || reg >= MAX77650_LED_NUM_LEDS) { reg 95 drivers/leds/leds-max77650.c led = &leds[reg]; reg 97 drivers/leds/leds-max77650.c led->regA = MAX77650_LED_A_BASE + reg; reg 98 drivers/leds/leds-max77650.c led->regB = MAX77650_LED_B_BASE + reg; reg 121 drivers/leds/leds-max8997.c u8 val = 0, mask = 0, reg = 0; reg 128 drivers/leds/leds-max8997.c reg = led->id ? MAX8997_REG_FLASH2_CUR : MAX8997_REG_FLASH1_CUR; reg 134 drivers/leds/leds-max8997.c reg = MAX8997_REG_MOVIE_CUR; reg 141 drivers/leds/leds-max8997.c ret = max8997_update_reg(client, reg, val, mask); reg 58 drivers/leds/leds-mc13783.c unsigned int reg, bank, off, shift; reg 64 drivers/leds/leds-mc13783.c reg = 2; reg 78 drivers/leds/leds-mc13783.c reg = 3 + bank; reg 85 drivers/leds/leds-mc13783.c reg = off / 2; reg 86 drivers/leds/leds-mc13783.c shift = 3 + (off - reg * 2) * 12; reg 93 drivers/leds/leds-mc13783.c reg = 2 + bank; reg 98 drivers/leds/leds-mc13783.c reg = 0; reg 105 drivers/leds/leds-mc13783.c return mc13xxx_reg_rmw(leds->master, leds->devtype->ledctrl_base + reg, reg 81 drivers/leds/leds-mlxreg.c ret = regmap_read(led_pdata->regmap, data->reg, ®val); reg 89 drivers/leds/leds-mlxreg.c ret = regmap_write(led_pdata->regmap, data->reg, regval); reg 116 drivers/leds/leds-mlxreg.c err = regmap_read(led_pdata->regmap, data->reg, ®val); reg 250 drivers/leds/leds-mlxreg.c data->label, data->mask, data->reg); reg 379 drivers/leds/leds-mt6323.c u32 reg; reg 405 drivers/leds/leds-mt6323.c ret = of_property_read_u32(child, "reg", ®); reg 411 drivers/leds/leds-mt6323.c if (reg >= MT6323_MAX_LEDS || leds->led[reg]) { reg 412 drivers/leds/leds-mt6323.c dev_err(dev, "Invalid led reg %u\n", reg); reg 423 drivers/leds/leds-mt6323.c leds->led[reg] = led; reg 424 drivers/leds/leds-mt6323.c leds->led[reg]->id = reg; reg 425 drivers/leds/leds-mt6323.c leds->led[reg]->cdev.max_brightness = MT6323_MAX_BRIGHTNESS; reg 426 drivers/leds/leds-mt6323.c leds->led[reg]->cdev.brightness_set_blocking = reg 428 drivers/leds/leds-mt6323.c leds->led[reg]->cdev.blink_set = mt6323_led_set_blink; reg 429 drivers/leds/leds-mt6323.c leds->led[reg]->cdev.brightness_get = reg 431 drivers/leds/leds-mt6323.c leds->led[reg]->parent = leds; reg 433 drivers/leds/leds-mt6323.c ret = mt6323_led_set_dt_default(&leds->led[reg]->cdev, child); reg 440 drivers/leds/leds-mt6323.c ret = devm_led_classdev_register(dev, &leds->led[reg]->cdev); reg 446 drivers/leds/leds-mt6323.c leds->led[reg]->cdev.dev->of_node = child; reg 160 drivers/leds/leds-pca9532.c char reg; reg 163 drivers/leds/leds-pca9532.c reg = i2c_smbus_read_byte_data(client, LED_REG(maxleds, led->id)); reg 165 drivers/leds/leds-pca9532.c reg = reg & ~(0x3<<LED_NUM(led->id)*2); reg 167 drivers/leds/leds-pca9532.c reg = reg | (led->state << LED_NUM(led->id)*2); reg 168 drivers/leds/leds-pca9532.c i2c_smbus_write_byte_data(client, LED_REG(maxleds, led->id), reg); reg 258 drivers/leds/leds-pca9532.c char reg; reg 262 drivers/leds/leds-pca9532.c reg = i2c_smbus_read_byte_data(client, LED_REG(maxleds, led->id)); reg 263 drivers/leds/leds-pca9532.c ret = reg >> LED_NUM(led->id)/2; reg 296 drivers/leds/leds-pca9532.c unsigned char reg; reg 298 drivers/leds/leds-pca9532.c reg = i2c_smbus_read_byte_data(data->client, PCA9532_REG_INPUT(offset)); reg 300 drivers/leds/leds-pca9532.c return !!(reg & (1 << (offset % 8))); reg 338 drivers/leds/leds-pca955x.c u8 reg = 0; reg 341 drivers/leds/leds-pca955x.c pca955x_read_input(pca955x->client, led->led_num / 8, ®); reg 343 drivers/leds/leds-pca955x.c return !!(reg & (1 << (led->led_num % 8))); reg 386 drivers/leds/leds-pca955x.c u32 reg; reg 389 drivers/leds/leds-pca955x.c res = fwnode_property_read_u32(child, "reg", ®); reg 390 drivers/leds/leds-pca955x.c if ((res != 0) || (reg >= chip->bits)) reg 397 drivers/leds/leds-pca955x.c snprintf(pdata->leds[reg].name, sizeof(pdata->leds[reg].name), reg 400 drivers/leds/leds-pca955x.c pdata->leds[reg].type = PCA955X_TYPE_LED; reg 401 drivers/leds/leds-pca955x.c fwnode_property_read_u32(child, "type", &pdata->leds[reg].type); reg 403 drivers/leds/leds-pca955x.c &pdata->leds[reg].default_trigger); reg 299 drivers/leds/leds-pca963x.c u32 reg; reg 302 drivers/leds/leds-pca963x.c res = fwnode_property_read_u32(child, "reg", ®); reg 303 drivers/leds/leds-pca963x.c if ((res != 0) || (reg >= chip->n_leds)) reg 313 drivers/leds/leds-pca963x.c pca963x_leds[reg] = led; reg 23 drivers/leds/leds-pm8058.c u32 reg; reg 51 drivers/leds/leds-pm8058.c ret = regmap_update_bits(led->map, led->reg, mask, val); reg 64 drivers/leds/leds-pm8058.c ret = regmap_read(led->map, led->reg, &val); reg 110 drivers/leds/leds-pm8058.c ret = of_property_read_u32(np, "reg", &led->reg); reg 281 drivers/leds/leds-sc27xx-bltc.c u32 base, count, reg; reg 309 drivers/leds/leds-sc27xx-bltc.c err = of_property_read_u32(child, "reg", ®); reg 316 drivers/leds/leds-sc27xx-bltc.c if (reg >= SC27XX_LEDS_MAX || priv->leds[reg].active) { reg 322 drivers/leds/leds-sc27xx-bltc.c priv->leds[reg].fwnode = of_fwnode_handle(child); reg 323 drivers/leds/leds-sc27xx-bltc.c priv->leds[reg].active = true; reg 26 drivers/leds/leds-sunfire.c void __iomem *reg; reg 34 drivers/leds/leds-sunfire.c u8 reg = upa_readb(p->reg); reg 39 drivers/leds/leds-sunfire.c reg &= ~bit; reg 41 drivers/leds/leds-sunfire.c reg |= bit; reg 46 drivers/leds/leds-sunfire.c reg |= bit; reg 48 drivers/leds/leds-sunfire.c reg &= ~bit; reg 51 drivers/leds/leds-sunfire.c upa_writeb(reg, p->reg); reg 76 drivers/leds/leds-sunfire.c u32 reg = upa_readl(p->reg); reg 81 drivers/leds/leds-sunfire.c reg &= ~bit; reg 83 drivers/leds/leds-sunfire.c reg |= bit; reg 88 drivers/leds/leds-sunfire.c reg |= bit; reg 90 drivers/leds/leds-sunfire.c reg &= ~bit; reg 93 drivers/leds/leds-sunfire.c upa_writel(reg, p->reg); reg 145 drivers/leds/leds-sunfire.c p->leds[i].reg = (void __iomem *) pdev->resource[0].start; reg 293 drivers/leds/leds-tca6507.c static void set_code(struct tca6507_chip *tca, int reg, int bank, int new) reg 301 drivers/leds/leds-tca6507.c n = tca->reg_file[reg] & ~mask; reg 303 drivers/leds/leds-tca6507.c if (tca->reg_file[reg] != n) { reg 304 drivers/leds/leds-tca6507.c tca->reg_file[reg] = n; reg 305 drivers/leds/leds-tca6507.c tca->reg_set |= 1 << reg; reg 708 drivers/leds/leds-tca6507.c u32 reg; reg 718 drivers/leds/leds-tca6507.c ret = of_property_read_u32(child, "reg", ®); reg 719 drivers/leds/leds-tca6507.c if (ret != 0 || reg >= NUM_LEDS) reg 722 drivers/leds/leds-tca6507.c tca_leds[reg] = led; reg 23 drivers/leds/leds-ti-lmu-common.c u8 reg, val; reg 34 drivers/leds/leds-ti-lmu-common.c reg = lmu_bank->lsb_brightness_reg; reg 35 drivers/leds/leds-ti-lmu-common.c ret = regmap_update_bits(regmap, reg, reg 46 drivers/leds/leds-ti-lmu-common.c reg = lmu_bank->msb_brightness_reg; reg 48 drivers/leds/leds-ti-lmu-common.c return regmap_write(regmap, reg, val); reg 201 drivers/leds/leds-tlc591xx.c int err, count, reg; reg 230 drivers/leds/leds-tlc591xx.c err = of_property_read_u32(child, "reg", ®); reg 235 drivers/leds/leds-tlc591xx.c if (reg < 0 || reg >= tlc591xx->max_leds || reg 236 drivers/leds/leds-tlc591xx.c priv->leds[reg].active) { reg 240 drivers/leds/leds-tlc591xx.c priv->leds[reg].active = true; reg 241 drivers/leds/leds-tlc591xx.c priv->leds[reg].ldev.name = reg 243 drivers/leds/leds-tlc591xx.c priv->leds[reg].ldev.default_trigger = reg 25 drivers/leds/leds-wm831x-status.c int reg; /* Control register */ reg 61 drivers/leds/leds-wm831x-status.c wm831x_reg_write(led->wm831x, led->reg, led->reg_val); reg 230 drivers/leds/leds-wm831x-status.c drvdata->reg = res->start; reg 248 drivers/leds/leds-wm831x-status.c drvdata->reg_val = wm831x_reg_read(wm831x, drvdata->reg); reg 957 drivers/macintosh/adbhid.c u16 reg = 0; reg 983 drivers/macintosh/adbhid.c reg |= adbhid_input_reregister(id, default_id, org_handler_id, reg 991 drivers/macintosh/adbhid.c reg |= adbhid_input_reregister(id, default_id, org_handler_id, reg 1081 drivers/macintosh/adbhid.c reg |= adbhid_input_reregister(id, default_id, org_handler_id, reg 1084 drivers/macintosh/adbhid.c adbhid_input_devcleanup(reg); reg 78 drivers/macintosh/ams/ams-i2c.c static s32 ams_i2c_read(u8 reg) reg 80 drivers/macintosh/ams/ams-i2c.c return i2c_smbus_read_byte_data(ams_info.i2c_client, reg); reg 83 drivers/macintosh/ams/ams-i2c.c static int ams_i2c_write(u8 reg, u8 value) reg 85 drivers/macintosh/ams/ams-i2c.c return i2c_smbus_write_byte_data(ams_info.i2c_client, reg, value); reg 107 drivers/macintosh/ams/ams-i2c.c static void ams_i2c_set_irq(enum ams_irq reg, char enable) reg 109 drivers/macintosh/ams/ams-i2c.c if (reg & AMS_IRQ_FREEFALL) { reg 118 drivers/macintosh/ams/ams-i2c.c if (reg & AMS_IRQ_SHOCK) { reg 127 drivers/macintosh/ams/ams-i2c.c if (reg & AMS_IRQ_GLOBAL) { reg 137 drivers/macintosh/ams/ams-i2c.c static void ams_i2c_clear_irq(enum ams_irq reg) reg 139 drivers/macintosh/ams/ams-i2c.c if (reg & AMS_IRQ_FREEFALL) reg 142 drivers/macintosh/ams/ams-i2c.c if (reg & AMS_IRQ_SHOCK) reg 48 drivers/macintosh/ams/ams-pmu.c static void ams_pmu_set_register(u8 reg, u8 value) reg 54 drivers/macintosh/ams/ams-pmu.c if (pmu_request(&req, ams_pmu_req_complete, 4, ams_pmu_cmd, 0x00, reg, value)) reg 61 drivers/macintosh/ams/ams-pmu.c static u8 ams_pmu_get_register(u8 reg) reg 67 drivers/macintosh/ams/ams-pmu.c if (pmu_request(&req, ams_pmu_req_complete, 3, ams_pmu_cmd, 0x01, reg)) reg 79 drivers/macintosh/ams/ams-pmu.c static void ams_pmu_set_irq(enum ams_irq reg, char enable) reg 81 drivers/macintosh/ams/ams-pmu.c if (reg & AMS_IRQ_FREEFALL) { reg 90 drivers/macintosh/ams/ams-pmu.c if (reg & AMS_IRQ_SHOCK) { reg 99 drivers/macintosh/ams/ams-pmu.c if (reg & AMS_IRQ_GLOBAL) { reg 109 drivers/macintosh/ams/ams-pmu.c static void ams_pmu_clear_irq(enum ams_irq reg) reg 111 drivers/macintosh/ams/ams-pmu.c if (reg & AMS_IRQ_FREEFALL) reg 114 drivers/macintosh/ams/ams-pmu.c if (reg & AMS_IRQ_SHOCK) reg 46 drivers/macintosh/ams/ams.h void (*clear_irq)(enum ams_irq reg); reg 361 drivers/macintosh/macio_asic.c const u32 *reg; reg 413 drivers/macintosh/macio_asic.c reg = of_get_property(np, "reg", NULL); reg 416 drivers/macintosh/macio_asic.c reg ? *reg : 0, MAX_NODE_NAME_SIZE, name); reg 95 drivers/macintosh/therm_adt746x.c write_reg(struct thermostat* th, int reg, u8 data) reg 100 drivers/macintosh/therm_adt746x.c tmp[0] = reg; reg 111 drivers/macintosh/therm_adt746x.c read_reg(struct thermostat* th, int reg) reg 116 drivers/macintosh/therm_adt746x.c reg_addr = (u8)reg; reg 120 drivers/macintosh/therm_windtunnel.c write_reg( struct i2c_client *cl, int reg, int data, int len ) reg 127 drivers/macintosh/therm_windtunnel.c tmp[0] = reg; reg 138 drivers/macintosh/therm_windtunnel.c read_reg( struct i2c_client *cl, int reg, int len ) reg 144 drivers/macintosh/therm_windtunnel.c buf[0] = reg; reg 236 drivers/macintosh/via-cuda.c const u32 *reg; reg 245 drivers/macintosh/via-cuda.c reg = of_get_property(vias, "reg", NULL); reg 246 drivers/macintosh/via-cuda.c if (reg == NULL) { reg 250 drivers/macintosh/via-cuda.c taddr = of_translate_address(vias, reg); reg 293 drivers/macintosh/via-pmu.c const u32 *reg; reg 301 drivers/macintosh/via-pmu.c reg = of_get_property(vias, "reg", NULL); reg 302 drivers/macintosh/via-pmu.c if (reg == NULL) { reg 306 drivers/macintosh/via-pmu.c taddr = of_translate_address(vias, reg); reg 346 drivers/macintosh/via-pmu.c reg = of_get_property(gpiop, "reg", NULL); reg 347 drivers/macintosh/via-pmu.c if (reg) reg 348 drivers/macintosh/via-pmu.c gaddr = of_translate_address(gpiop, reg); reg 86 drivers/macintosh/windfarm_fcu_controls.c static int wf_fcu_read_reg(struct wf_fcu_priv *pv, int reg, reg 93 drivers/macintosh/windfarm_fcu_controls.c buf[0] = reg; reg 122 drivers/macintosh/windfarm_fcu_controls.c static int wf_fcu_write_reg(struct wf_fcu_priv *pv, int reg, reg 128 drivers/macintosh/windfarm_fcu_controls.c buf[0] = reg; reg 436 drivers/macintosh/windfarm_fcu_controls.c const u32 *reg; reg 453 drivers/macintosh/windfarm_fcu_controls.c reg = of_get_property(np, "reg", NULL); reg 454 drivers/macintosh/windfarm_fcu_controls.c if (loc == NULL || reg == NULL) reg 456 drivers/macintosh/windfarm_fcu_controls.c DBG(" matching location: %s, reg: 0x%08x\n", loc, *reg); reg 467 drivers/macintosh/windfarm_fcu_controls.c id = ((*reg) - 0x10) / 2; reg 469 drivers/macintosh/windfarm_fcu_controls.c id = ((*reg) - 0x30) / 2; reg 41 drivers/macintosh/windfarm_lm87_sensor.c static int wf_lm87_read_reg(struct i2c_client *chip, int reg) reg 48 drivers/macintosh/windfarm_lm87_sensor.c buf = (u8)reg; reg 46 drivers/macintosh/windfarm_smu_controls.c u32 reg; /* index in SMU */ reg 125 drivers/macintosh/windfarm_smu_controls.c return smu_set_fan(fct->fan_type, fct->reg, value); reg 161 drivers/macintosh/windfarm_smu_controls.c const u32 *reg; reg 241 drivers/macintosh/windfarm_smu_controls.c reg = of_get_property(node, "reg", NULL); reg 242 drivers/macintosh/windfarm_smu_controls.c if (reg == NULL) reg 244 drivers/macintosh/windfarm_smu_controls.c fct->reg = *reg; reg 198 drivers/macintosh/windfarm_smu_sat.c const u32 *reg; reg 221 drivers/macintosh/windfarm_smu_sat.c reg = of_get_property(child, "reg", NULL); reg 223 drivers/macintosh/windfarm_smu_sat.c if (reg == NULL || loc == NULL) reg 227 drivers/macintosh/windfarm_smu_sat.c if (*reg < 0x30 || *reg > 0x37) reg 229 drivers/macintosh/windfarm_smu_sat.c index = *reg - 0x30; reg 53 drivers/macintosh/windfarm_smu_sensors.c u32 reg; /* index in SMU */ reg 94 drivers/macintosh/windfarm_smu_sensors.c rc = smu_read_adc(ads->reg, &val); reg 116 drivers/macintosh/windfarm_smu_sensors.c rc = smu_read_adc(ads->reg, &val); reg 137 drivers/macintosh/windfarm_smu_sensors.c rc = smu_read_adc(ads->reg, &val); reg 158 drivers/macintosh/windfarm_smu_sensors.c rc = smu_read_adc(ads->reg, &val); reg 258 drivers/macintosh/windfarm_smu_sensors.c ads->reg = *v; reg 60 drivers/mailbox/armada-37xx-rwtm-mailbox.c u32 reg; reg 62 drivers/mailbox/armada-37xx-rwtm-mailbox.c reg = readl(mbox->base + RWTM_HOST_INT_RESET); reg 64 drivers/mailbox/armada-37xx-rwtm-mailbox.c if (reg & SP_CMD_COMPLETE) reg 67 drivers/mailbox/armada-37xx-rwtm-mailbox.c if (reg & (SP_CMD_QUEUE_FULL_ACCESS | SP_CMD_QUEUE_FULL)) reg 70 drivers/mailbox/armada-37xx-rwtm-mailbox.c writel(reg, mbox->base + RWTM_HOST_INT_RESET); reg 71 drivers/mailbox/armada-37xx-rwtm-mailbox.c if (reg) reg 74 drivers/mailbox/armada-37xx-rwtm-mailbox.c return reg ? IRQ_HANDLED : IRQ_NONE; reg 82 drivers/mailbox/armada-37xx-rwtm-mailbox.c u32 reg; reg 87 drivers/mailbox/armada-37xx-rwtm-mailbox.c reg = readl(mbox->base + RWTM_MBOX_FIFO_STATUS); reg 88 drivers/mailbox/armada-37xx-rwtm-mailbox.c if (!(reg & FIFO_STS_RDY)) reg 91 drivers/mailbox/armada-37xx-rwtm-mailbox.c if ((reg & FIFO_STS_CNTR_MASK) >= FIFO_STS_CNTR_MAX) { reg 106 drivers/mailbox/armada-37xx-rwtm-mailbox.c u32 reg; reg 117 drivers/mailbox/armada-37xx-rwtm-mailbox.c reg = readl(mbox->base + RWTM_HOST_INT_MASK); reg 118 drivers/mailbox/armada-37xx-rwtm-mailbox.c reg &= ~(SP_CMD_COMPLETE | SP_CMD_QUEUE_FULL_ACCESS | SP_CMD_QUEUE_FULL); reg 119 drivers/mailbox/armada-37xx-rwtm-mailbox.c writel(reg, mbox->base + RWTM_HOST_INT_MASK); reg 126 drivers/mailbox/armada-37xx-rwtm-mailbox.c u32 reg; reg 130 drivers/mailbox/armada-37xx-rwtm-mailbox.c reg = readl(mbox->base + RWTM_HOST_INT_MASK); reg 131 drivers/mailbox/armada-37xx-rwtm-mailbox.c reg |= SP_CMD_COMPLETE | SP_CMD_QUEUE_FULL_ACCESS | SP_CMD_QUEUE_FULL; reg 132 drivers/mailbox/armada-37xx-rwtm-mailbox.c writel(reg, mbox->base + RWTM_HOST_INT_MASK); reg 102 drivers/mailbox/mailbox-altera.c u32 reg; reg 108 drivers/mailbox/mailbox-altera.c reg = readl_relaxed(mbox->mbox_base + MAILBOX_PTR_REG); reg 109 drivers/mailbox/mailbox-altera.c if (reg == MBOX_MAGIC) { reg 46 drivers/mailbox/mailbox-xgene-slimpro.c void __iomem *reg; reg 70 drivers/mailbox/mailbox-xgene-slimpro.c writel(msg[1], mb_chan->reg + REG_DB_DOUT0); reg 71 drivers/mailbox/mailbox-xgene-slimpro.c writel(msg[2], mb_chan->reg + REG_DB_DOUT1); reg 72 drivers/mailbox/mailbox-xgene-slimpro.c writel(msg[0], mb_chan->reg + REG_DB_OUT); reg 77 drivers/mailbox/mailbox-xgene-slimpro.c mb_chan->rx_msg[1] = readl(mb_chan->reg + REG_DB_DIN0); reg 78 drivers/mailbox/mailbox-xgene-slimpro.c mb_chan->rx_msg[2] = readl(mb_chan->reg + REG_DB_DIN1); reg 79 drivers/mailbox/mailbox-xgene-slimpro.c mb_chan->rx_msg[0] = readl(mb_chan->reg + REG_DB_IN); reg 84 drivers/mailbox/mailbox-xgene-slimpro.c u32 val = readl(mb_chan->reg + REG_DB_STAT); reg 87 drivers/mailbox/mailbox-xgene-slimpro.c writel(MBOX_STATUS_ACK_MASK, mb_chan->reg + REG_DB_STAT); reg 95 drivers/mailbox/mailbox-xgene-slimpro.c u32 val = readl(mb_chan->reg + REG_DB_STAT); reg 99 drivers/mailbox/mailbox-xgene-slimpro.c writel(MBOX_STATUS_AVAIL_MASK, mb_chan->reg + REG_DB_STAT); reg 142 drivers/mailbox/mailbox-xgene-slimpro.c mb_chan->reg + REG_DB_STAT); reg 144 drivers/mailbox/mailbox-xgene-slimpro.c val = readl(mb_chan->reg + REG_DB_STATMASK); reg 146 drivers/mailbox/mailbox-xgene-slimpro.c writel(val, mb_chan->reg + REG_DB_STATMASK); reg 157 drivers/mailbox/mailbox-xgene-slimpro.c val = readl(mb_chan->reg + REG_DB_STATMASK); reg 159 drivers/mailbox/mailbox-xgene-slimpro.c writel(val, mb_chan->reg + REG_DB_STATMASK); reg 202 drivers/mailbox/mailbox-xgene-slimpro.c ctx->mc[i].reg = mb_base + i * MBOX_REG_SET_OFFSET; reg 604 drivers/mailbox/omap-mailbox.c u32 usr, fifo, reg; reg 618 drivers/mailbox/omap-mailbox.c reg = MAILBOX_IRQENABLE(mdev->intr_type, usr); reg 619 drivers/mailbox/omap-mailbox.c mdev->irq_ctx[usr] = mbox_read_reg(mdev, reg); reg 628 drivers/mailbox/omap-mailbox.c u32 usr, reg; reg 634 drivers/mailbox/omap-mailbox.c reg = MAILBOX_IRQENABLE(mdev->intr_type, usr); reg 635 drivers/mailbox/omap-mailbox.c mbox_write_reg(mdev, mdev->irq_ctx[usr], reg); reg 62 drivers/mailbox/stm32-ipcc.c static inline void stm32_ipcc_set_bits(spinlock_t *lock, void __iomem *reg, reg 68 drivers/mailbox/stm32-ipcc.c writel_relaxed(readl_relaxed(reg) | mask, reg); reg 72 drivers/mailbox/stm32-ipcc.c static inline void stm32_ipcc_clr_bits(spinlock_t *lock, void __iomem *reg, reg 78 drivers/mailbox/stm32-ipcc.c writel_relaxed(readl_relaxed(reg) & ~mask, reg); reg 23 drivers/mailbox/ti-msgmgr.c #define Q_DATA_OFFSET(proxy, queue, reg) \ reg 24 drivers/mailbox/ti-msgmgr.c ((0x10000 * (proxy)) + (0x80 * (queue)) + ((reg) * 4)) reg 29 drivers/mailbox/ti-msgmgr.c #define SPROXY_THREAD_DATA_OFFSET(tid, reg) \ reg 30 drivers/mailbox/ti-msgmgr.c (SPROXY_THREAD_OFFSET(tid) + ((reg) * 0x4) + 0x4) reg 138 drivers/mcb/mcb-parse.c __le32 reg; reg 150 drivers/mcb/mcb-parse.c reg = readl(*base); reg 152 drivers/mcb/mcb-parse.c bar_count = BAR_CNT(reg); reg 299 drivers/md/dm-raid1.c struct dm_region *reg = context; reg 300 drivers/md/dm-raid1.c struct mirror_set *ms = dm_rh_region_context(reg); reg 326 drivers/md/dm-raid1.c dm_rh_recovery_end(reg, !(read_err || write_err)); reg 329 drivers/md/dm-raid1.c static void recover(struct mirror_set *ms, struct dm_region *reg) reg 335 drivers/md/dm-raid1.c region_t key = dm_rh_get_region_key(reg); reg 370 drivers/md/dm-raid1.c flags, recovery_complete, reg); reg 386 drivers/md/dm-raid1.c struct dm_region *reg; reg 397 drivers/md/dm-raid1.c while ((reg = dm_rh_recovery_start(ms->rh))) reg 398 drivers/md/dm-raid1.c recover(ms, reg); reg 135 drivers/md/dm-region-hash.c void *dm_rh_region_context(struct dm_region *reg) reg 137 drivers/md/dm-region-hash.c return reg->rh->context; reg 141 drivers/md/dm-region-hash.c region_t dm_rh_get_region_key(struct dm_region *reg) reg 143 drivers/md/dm-region-hash.c return reg->key; reg 240 drivers/md/dm-region-hash.c struct dm_region *reg, *nreg; reg 244 drivers/md/dm-region-hash.c list_for_each_entry_safe(reg, nreg, rh->buckets + h, reg 246 drivers/md/dm-region-hash.c BUG_ON(atomic_read(®->pending)); reg 247 drivers/md/dm-region-hash.c mempool_free(reg, &rh->region_pool); reg 273 drivers/md/dm-region-hash.c struct dm_region *reg; reg 276 drivers/md/dm-region-hash.c list_for_each_entry(reg, bucket, hash_list) reg 277 drivers/md/dm-region-hash.c if (reg->key == region) reg 278 drivers/md/dm-region-hash.c return reg; reg 283 drivers/md/dm-region-hash.c static void __rh_insert(struct dm_region_hash *rh, struct dm_region *reg) reg 285 drivers/md/dm-region-hash.c list_add(®->hash_list, rh->buckets + rh_hash(rh, reg->key)); reg 290 drivers/md/dm-region-hash.c struct dm_region *reg, *nreg; reg 305 drivers/md/dm-region-hash.c reg = __rh_lookup(rh, region); reg 306 drivers/md/dm-region-hash.c if (reg) reg 317 drivers/md/dm-region-hash.c reg = nreg; reg 321 drivers/md/dm-region-hash.c return reg; reg 326 drivers/md/dm-region-hash.c struct dm_region *reg; reg 328 drivers/md/dm-region-hash.c reg = __rh_lookup(rh, region); reg 329 drivers/md/dm-region-hash.c if (!reg) { reg 331 drivers/md/dm-region-hash.c reg = __rh_alloc(rh, region); reg 335 drivers/md/dm-region-hash.c return reg; reg 341 drivers/md/dm-region-hash.c struct dm_region *reg; reg 344 drivers/md/dm-region-hash.c reg = __rh_lookup(rh, region); reg 347 drivers/md/dm-region-hash.c if (reg) reg 348 drivers/md/dm-region-hash.c return reg->state; reg 364 drivers/md/dm-region-hash.c static void complete_resync_work(struct dm_region *reg, int success) reg 366 drivers/md/dm-region-hash.c struct dm_region_hash *rh = reg->rh; reg 368 drivers/md/dm-region-hash.c rh->log->type->set_region_sync(rh->log, reg->key, success); reg 379 drivers/md/dm-region-hash.c rh->dispatch_bios(rh->context, ®->delayed_bios); reg 399 drivers/md/dm-region-hash.c struct dm_region *reg; reg 415 drivers/md/dm-region-hash.c reg = __rh_find(rh, region); reg 419 drivers/md/dm-region-hash.c BUG_ON(!reg); reg 420 drivers/md/dm-region-hash.c BUG_ON(!list_empty(®->list)); reg 430 drivers/md/dm-region-hash.c recovering = (reg->state == DM_RH_RECOVERING); reg 431 drivers/md/dm-region-hash.c reg->state = DM_RH_NOSYNC; reg 432 drivers/md/dm-region-hash.c BUG_ON(!list_empty(®->list)); reg 436 drivers/md/dm-region-hash.c complete_resync_work(reg, 0); reg 442 drivers/md/dm-region-hash.c struct dm_region *reg, *next; reg 456 drivers/md/dm-region-hash.c list_for_each_entry(reg, &clean, list) reg 457 drivers/md/dm-region-hash.c list_del(®->hash_list); reg 463 drivers/md/dm-region-hash.c list_for_each_entry(reg, &recovered, list) reg 464 drivers/md/dm-region-hash.c list_del(®->hash_list); reg 471 drivers/md/dm-region-hash.c list_for_each_entry(reg, &failed_recovered, list) reg 472 drivers/md/dm-region-hash.c list_del(®->hash_list); reg 483 drivers/md/dm-region-hash.c list_for_each_entry_safe(reg, next, &recovered, list) { reg 484 drivers/md/dm-region-hash.c rh->log->type->clear_region(rh->log, reg->key); reg 485 drivers/md/dm-region-hash.c complete_resync_work(reg, 1); reg 486 drivers/md/dm-region-hash.c mempool_free(reg, &rh->region_pool); reg 489 drivers/md/dm-region-hash.c list_for_each_entry_safe(reg, next, &failed_recovered, list) { reg 490 drivers/md/dm-region-hash.c complete_resync_work(reg, errors_handled ? 0 : 1); reg 491 drivers/md/dm-region-hash.c mempool_free(reg, &rh->region_pool); reg 494 drivers/md/dm-region-hash.c list_for_each_entry_safe(reg, next, &clean, list) { reg 495 drivers/md/dm-region-hash.c rh->log->type->clear_region(rh->log, reg->key); reg 496 drivers/md/dm-region-hash.c mempool_free(reg, &rh->region_pool); reg 505 drivers/md/dm-region-hash.c struct dm_region *reg; reg 508 drivers/md/dm-region-hash.c reg = __rh_find(rh, region); reg 511 drivers/md/dm-region-hash.c atomic_inc(®->pending); reg 513 drivers/md/dm-region-hash.c if (reg->state == DM_RH_CLEAN) { reg 514 drivers/md/dm-region-hash.c reg->state = DM_RH_DIRTY; reg 515 drivers/md/dm-region-hash.c list_del_init(®->list); /* take off the clean list */ reg 518 drivers/md/dm-region-hash.c rh->log->type->mark_region(rh->log, reg->key); reg 541 drivers/md/dm-region-hash.c struct dm_region *reg; reg 545 drivers/md/dm-region-hash.c reg = __rh_lookup(rh, region); reg 549 drivers/md/dm-region-hash.c if (atomic_dec_and_test(®->pending)) { reg 568 drivers/md/dm-region-hash.c reg->state = DM_RH_NOSYNC; reg 569 drivers/md/dm-region-hash.c } else if (reg->state == DM_RH_RECOVERING) { reg 570 drivers/md/dm-region-hash.c list_add_tail(®->list, &rh->quiesced_regions); reg 571 drivers/md/dm-region-hash.c } else if (reg->state == DM_RH_DIRTY) { reg 572 drivers/md/dm-region-hash.c reg->state = DM_RH_CLEAN; reg 573 drivers/md/dm-region-hash.c list_add(®->list, &rh->clean_regions); reg 591 drivers/md/dm-region-hash.c struct dm_region *reg; reg 605 drivers/md/dm-region-hash.c reg = __rh_find(rh, region); reg 609 drivers/md/dm-region-hash.c reg->state = DM_RH_RECOVERING; reg 612 drivers/md/dm-region-hash.c if (atomic_read(®->pending)) reg 613 drivers/md/dm-region-hash.c list_del_init(®->list); reg 615 drivers/md/dm-region-hash.c list_move(®->list, &rh->quiesced_regions); reg 647 drivers/md/dm-region-hash.c struct dm_region *reg = NULL; reg 651 drivers/md/dm-region-hash.c reg = list_entry(rh->quiesced_regions.next, reg 653 drivers/md/dm-region-hash.c list_del_init(®->list); /* remove from the quiesced list */ reg 657 drivers/md/dm-region-hash.c return reg; reg 661 drivers/md/dm-region-hash.c void dm_rh_recovery_end(struct dm_region *reg, int success) reg 663 drivers/md/dm-region-hash.c struct dm_region_hash *rh = reg->rh; reg 667 drivers/md/dm-region-hash.c list_add(®->list, ®->rh->recovered_regions); reg 669 drivers/md/dm-region-hash.c list_add(®->list, ®->rh->failed_recovered_regions); reg 692 drivers/md/dm-region-hash.c struct dm_region *reg; reg 695 drivers/md/dm-region-hash.c reg = __rh_find(rh, dm_rh_bio_to_region(rh, bio)); reg 696 drivers/md/dm-region-hash.c bio_list_add(®->delayed_bios, bio); reg 174 drivers/media/common/b2c2/flexcop-common.h flexcop_ibi_register reg, int num); reg 75 drivers/media/common/b2c2/flexcop-misc.c flexcop_ibi_register reg, int num) reg 80 drivers/media/common/b2c2/flexcop-misc.c v = fc->read_ibi_reg(fc, reg+4*i); reg 81 drivers/media/common/b2c2/flexcop-misc.c deb_rdump("0x%03x: %08x, ", reg+4*i, v.raw); reg 162 drivers/media/common/b2c2/flexcop-reg.h #define flexcop_set_ibi_value(reg,attr,val) { \ reg 163 drivers/media/common/b2c2/flexcop-reg.h flexcop_ibi_value v = fc->read_ibi_reg(fc,reg); \ reg 164 drivers/media/common/b2c2/flexcop-reg.h v.reg.attr = val; \ reg 165 drivers/media/common/b2c2/flexcop-reg.h fc->write_ibi_reg(fc,reg,v); \ reg 12 drivers/media/dvb-frontends/a8293.c u8 reg[2]; reg 42 drivers/media/dvb-frontends/a8293.c if (reg0 != dev->reg[0]) { reg 46 drivers/media/dvb-frontends/a8293.c dev->reg[0] = reg0; reg 51 drivers/media/dvb-frontends/a8293.c if (reg1 != dev->reg[1]) { reg 55 drivers/media/dvb-frontends/a8293.c dev->reg[1] = reg1; reg 896 drivers/media/dvb-frontends/af9013.c ret = regmap_update_bits(state->regmap, tab[i].reg, tab[i].mask, reg 949 drivers/media/dvb-frontends/af9013.c ret = regmap_update_bits(state->regmap, tab[i].reg, tab[i].mask, reg 1279 drivers/media/dvb-frontends/af9013.c static int af9013_wregs(struct i2c_client *client, u8 cmd, u16 reg, reg 1298 drivers/media/dvb-frontends/af9013.c buf[0] = (reg >> 8) & 0xff; reg 1299 drivers/media/dvb-frontends/af9013.c buf[1] = (reg >> 0) & 0xff; reg 1321 drivers/media/dvb-frontends/af9013.c static int af9013_rregs(struct i2c_client *client, u8 cmd, u16 reg, reg 1340 drivers/media/dvb-frontends/af9013.c buf[0] = (reg >> 8) & 0xff; reg 1341 drivers/media/dvb-frontends/af9013.c buf[1] = (reg >> 0) & 0xff; reg 1369 drivers/media/dvb-frontends/af9013.c u16 reg = ((u8 *)data)[1] << 8 | ((u8 *)data)[2] << 0; reg 1373 drivers/media/dvb-frontends/af9013.c if (state->ts_mode == AF9013_TS_MODE_USB && (reg & 0xff00) != 0xae00) { reg 1375 drivers/media/dvb-frontends/af9013.c ret = af9013_wregs(client, cmd, reg, val, len, lock); reg 1378 drivers/media/dvb-frontends/af9013.c } else if (reg >= 0x5100 && reg < 0x8fff) { reg 1381 drivers/media/dvb-frontends/af9013.c ret = af9013_wregs(client, cmd, reg, val, len, lock); reg 1387 drivers/media/dvb-frontends/af9013.c ret = af9013_wregs(client, cmd, reg + i, val + i, 1, reg 1408 drivers/media/dvb-frontends/af9013.c u16 reg = ((u8 *)reg_buf)[1] << 8 | ((u8 *)reg_buf)[2] << 0; reg 1412 drivers/media/dvb-frontends/af9013.c if (state->ts_mode == AF9013_TS_MODE_USB && (reg & 0xff00) != 0xae00) { reg 1414 drivers/media/dvb-frontends/af9013.c ret = af9013_rregs(client, cmd, reg, val_buf, len, lock); reg 1420 drivers/media/dvb-frontends/af9013.c ret = af9013_rregs(client, cmd, reg + i, val + i, 1, reg 25 drivers/media/dvb-frontends/af9013_priv.h u16 reg; reg 50 drivers/media/dvb-frontends/af9033.c if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1) { reg 51 drivers/media/dvb-frontends/af9033.c ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, reg 144 drivers/media/dvb-frontends/af9033.c ret = regmap_update_bits(dev->regmap, tab[i].reg, tab[i].mask, reg 1057 drivers/media/dvb-frontends/af9033.c u32 reg; reg 1110 drivers/media/dvb-frontends/af9033.c reg = 0x004bfc; reg 1114 drivers/media/dvb-frontends/af9033.c reg = 0x0083e9; reg 1118 drivers/media/dvb-frontends/af9033.c ret = regmap_bulk_read(dev->regmap, reg, &buf[0], 4); reg 20 drivers/media/dvb-frontends/af9033_priv.h u32 reg; reg 25 drivers/media/dvb-frontends/af9033_priv.h u32 reg; reg 104 drivers/media/dvb-frontends/ascot2e.c u8 reg, u8 write, const u8 *data, u32 len) reg 107 drivers/media/dvb-frontends/ascot2e.c (write == 0 ? "read" : "write"), reg, len); reg 113 drivers/media/dvb-frontends/ascot2e.c u8 reg, const u8 *data, u32 len) reg 128 drivers/media/dvb-frontends/ascot2e.c reg, len + 1); reg 132 drivers/media/dvb-frontends/ascot2e.c ascot2e_i2c_debug(priv, reg, 1, data, len); reg 133 drivers/media/dvb-frontends/ascot2e.c buf[0] = reg; reg 141 drivers/media/dvb-frontends/ascot2e.c KBUILD_MODNAME, ret, reg, len); reg 147 drivers/media/dvb-frontends/ascot2e.c static int ascot2e_write_reg(struct ascot2e_priv *priv, u8 reg, u8 val) reg 151 drivers/media/dvb-frontends/ascot2e.c return ascot2e_write_regs(priv, reg, &tmp, 1); reg 155 drivers/media/dvb-frontends/ascot2e.c u8 reg, u8 *val, u32 len) reg 163 drivers/media/dvb-frontends/ascot2e.c .buf = ®, reg 178 drivers/media/dvb-frontends/ascot2e.c KBUILD_MODNAME, ret, priv->i2c_address, reg); reg 187 drivers/media/dvb-frontends/ascot2e.c KBUILD_MODNAME, ret, priv->i2c_address, reg); reg 190 drivers/media/dvb-frontends/ascot2e.c ascot2e_i2c_debug(priv, reg, 0, val, len); reg 194 drivers/media/dvb-frontends/ascot2e.c static int ascot2e_read_reg(struct ascot2e_priv *priv, u8 reg, u8 *val) reg 196 drivers/media/dvb-frontends/ascot2e.c return ascot2e_read_regs(priv, reg, val, 1); reg 200 drivers/media/dvb-frontends/ascot2e.c u8 reg, u8 data, u8 mask) reg 206 drivers/media/dvb-frontends/ascot2e.c res = ascot2e_read_reg(priv, reg, &rdata); reg 211 drivers/media/dvb-frontends/ascot2e.c return ascot2e_write_reg(priv, reg, data); reg 26 drivers/media/dvb-frontends/atbm8830.c static int atbm8830_write_reg(struct atbm_state *priv, u16 reg, u8 data) reg 30 drivers/media/dvb-frontends/atbm8830.c u8 buf1[] = { reg >> 8, reg & 0xFF }; reg 40 drivers/media/dvb-frontends/atbm8830.c dprintk("%s: reg=0x%04X, data=0x%02X\n", __func__, reg, data); reg 50 drivers/media/dvb-frontends/atbm8830.c static int atbm8830_read_reg(struct atbm_state *priv, u16 reg, u8 *p_data) reg 55 drivers/media/dvb-frontends/atbm8830.c u8 buf1[] = { reg >> 8, reg & 0xFF }; reg 66 drivers/media/dvb-frontends/atbm8830.c dprintk("%s: error reg=0x%04x, ret=%i\n", __func__, reg, ret); reg 77 drivers/media/dvb-frontends/atbm8830.c __func__, reg, buf2[0]); reg 30 drivers/media/dvb-frontends/au8522_common.c int au8522_writereg(struct au8522_state *state, u16 reg, u8 data) reg 33 drivers/media/dvb-frontends/au8522_common.c u8 buf[] = { (reg >> 8) | 0x80, reg & 0xff, data }; reg 42 drivers/media/dvb-frontends/au8522_common.c __func__, reg, data, ret); reg 48 drivers/media/dvb-frontends/au8522_common.c u8 au8522_readreg(struct au8522_state *state, u16 reg) reg 51 drivers/media/dvb-frontends/au8522_common.c u8 b0[] = { (reg >> 8) | 0x40, reg & 0xff }; reg 473 drivers/media/dvb-frontends/au8522_decoder.c struct v4l2_dbg_register *reg) reg 477 drivers/media/dvb-frontends/au8522_decoder.c reg->val = au8522_readreg(state, reg->reg & 0xffff); reg 482 drivers/media/dvb-frontends/au8522_decoder.c const struct v4l2_dbg_register *reg) reg 486 drivers/media/dvb-frontends/au8522_decoder.c au8522_writereg(state, reg->reg, reg->val & 0xff); reg 271 drivers/media/dvb-frontends/au8522_dig.c u16 reg; reg 304 drivers/media/dvb-frontends/au8522_dig.c u16 reg; reg 383 drivers/media/dvb-frontends/au8522_dig.c u16 reg; reg 461 drivers/media/dvb-frontends/au8522_dig.c u16 reg; reg 554 drivers/media/dvb-frontends/au8522_dig.c VSB_mod_tab[i].reg, reg 562 drivers/media/dvb-frontends/au8522_dig.c QAM64_mod_tab[i].reg, reg 571 drivers/media/dvb-frontends/au8522_dig.c QAM256_mod_tab_zv_mode[i].reg, reg 580 drivers/media/dvb-frontends/au8522_dig.c QAM256_mod_tab[i].reg, reg 637 drivers/media/dvb-frontends/au8522_dig.c u8 reg; reg 644 drivers/media/dvb-frontends/au8522_dig.c reg = au8522_readreg(state, 0x0088); reg 645 drivers/media/dvb-frontends/au8522_dig.c if ((reg & 0x03) == 0x03) reg 649 drivers/media/dvb-frontends/au8522_dig.c reg = au8522_readreg(state, 0x0541); reg 650 drivers/media/dvb-frontends/au8522_dig.c if (reg & 0x80) reg 652 drivers/media/dvb-frontends/au8522_dig.c if (reg & 0x20) reg 75 drivers/media/dvb-frontends/au8522_priv.h int au8522_writereg(struct au8522_state *state, u16 reg, u8 data); reg 76 drivers/media/dvb-frontends/au8522_priv.h u8 au8522_readreg(struct au8522_state *state, u16 reg); reg 81 drivers/media/dvb-frontends/bcm3510.c static int bcm3510_writebytes (struct bcm3510_state *state, u8 reg, u8 *buf, u8 len) reg 87 drivers/media/dvb-frontends/bcm3510.c b[0] = reg; reg 90 drivers/media/dvb-frontends/bcm3510.c deb_i2c("i2c wr %02x: ",reg); reg 97 drivers/media/dvb-frontends/bcm3510.c __func__, state->config->demod_address, reg, err); reg 104 drivers/media/dvb-frontends/bcm3510.c static int bcm3510_readbytes (struct bcm3510_state *state, u8 reg, u8 *buf, u8 len) reg 107 drivers/media/dvb-frontends/bcm3510.c { .addr = state->config->demod_address, .flags = 0, .buf = ®, .len = 1 }, reg 116 drivers/media/dvb-frontends/bcm3510.c __func__, state->config->demod_address, reg, err); reg 119 drivers/media/dvb-frontends/bcm3510.c deb_i2c("i2c rd %02x: ",reg); reg 126 drivers/media/dvb-frontends/bcm3510.c static int bcm3510_writeB(struct bcm3510_state *state, u8 reg, bcm3510_register_value v) reg 128 drivers/media/dvb-frontends/bcm3510.c return bcm3510_writebytes(state,reg,&v.raw,1); reg 131 drivers/media/dvb-frontends/bcm3510.c static int bcm3510_readB(struct bcm3510_state *state, u8 reg, bcm3510_register_value *v) reg 133 drivers/media/dvb-frontends/bcm3510.c return bcm3510_readbytes(state,reg,&v->raw,1); reg 58 drivers/media/dvb-frontends/cx22700.c static int cx22700_writereg (struct cx22700_state* state, u8 reg, u8 data) reg 61 drivers/media/dvb-frontends/cx22700.c u8 buf [] = { reg, data }; reg 70 drivers/media/dvb-frontends/cx22700.c __func__, reg, data, ret); reg 75 drivers/media/dvb-frontends/cx22700.c static int cx22700_readreg (struct cx22700_state* state, u8 reg) reg 78 drivers/media/dvb-frontends/cx22700.c u8 b0 [] = { reg }; reg 73 drivers/media/dvb-frontends/cx22702.c static int cx22702_writereg(struct cx22702_state *state, u8 reg, u8 data) reg 76 drivers/media/dvb-frontends/cx22702.c u8 buf[] = { reg, data }; reg 86 drivers/media/dvb-frontends/cx22702.c __func__, reg, data, ret); reg 93 drivers/media/dvb-frontends/cx22702.c static u8 cx22702_readreg(struct cx22702_state *state, u8 reg) reg 100 drivers/media/dvb-frontends/cx22702.c .buf = ®, .len = 1 }, reg 108 drivers/media/dvb-frontends/cx22702.c __func__, reg, ret); reg 40 drivers/media/dvb-frontends/cx24110.c static struct {u8 reg; u8 data;} cx24110_regdata[]= reg 103 drivers/media/dvb-frontends/cx24110.c static int cx24110_writereg (struct cx24110_state* state, int reg, int data) reg 105 drivers/media/dvb-frontends/cx24110.c u8 buf [] = { reg, data }; reg 111 drivers/media/dvb-frontends/cx24110.c __func__, err, reg, data); reg 118 drivers/media/dvb-frontends/cx24110.c static int cx24110_readreg (struct cx24110_state* state, u8 reg) reg 121 drivers/media/dvb-frontends/cx24110.c u8 b0 [] = { reg }; reg 350 drivers/media/dvb-frontends/cx24110.c cx24110_writereg(state, cx24110_regdata[i].reg, cx24110_regdata[i].data); reg 90 drivers/media/dvb-frontends/cx24113.c static int cx24113_writereg(struct cx24113_state *state, int reg, int data) reg 92 drivers/media/dvb-frontends/cx24113.c u8 buf[] = { reg, data }; reg 98 drivers/media/dvb-frontends/cx24113.c __func__, err, reg, data); reg 105 drivers/media/dvb-frontends/cx24113.c static int cx24113_readreg(struct cx24113_state *state, u8 reg) reg 111 drivers/media/dvb-frontends/cx24113.c .flags = 0, .buf = ®, .len = 1 }, reg 120 drivers/media/dvb-frontends/cx24113.c __func__, reg, ret); reg 365 drivers/media/dvb-frontends/cx24113.c u8 reg; reg 368 drivers/media/dvb-frontends/cx24113.c reg = ((n & 0x1) << 7) | ((f >> 11) & 0x7f); reg 369 drivers/media/dvb-frontends/cx24113.c cx24113_writereg(state, 0x1a, reg); reg 373 drivers/media/dvb-frontends/cx24113.c reg = cx24113_readreg(state, 0x1c) & 0x1f; reg 374 drivers/media/dvb-frontends/cx24113.c cx24113_writereg(state, 0x1c, reg | ((f & 0x7) << 5)); reg 187 drivers/media/dvb-frontends/cx24116.c static int cx24116_writereg(struct cx24116_state *state, int reg, int data) reg 189 drivers/media/dvb-frontends/cx24116.c u8 buf[] = { reg, data }; reg 196 drivers/media/dvb-frontends/cx24116.c __func__, reg, data); reg 201 drivers/media/dvb-frontends/cx24116.c __func__, err, reg, data); reg 209 drivers/media/dvb-frontends/cx24116.c static int cx24116_writeregN(struct cx24116_state *state, int reg, reg 220 drivers/media/dvb-frontends/cx24116.c *(buf) = reg; reg 230 drivers/media/dvb-frontends/cx24116.c __func__, reg, len); reg 235 drivers/media/dvb-frontends/cx24116.c __func__, ret, reg); reg 244 drivers/media/dvb-frontends/cx24116.c static int cx24116_readreg(struct cx24116_state *state, u8 reg) reg 247 drivers/media/dvb-frontends/cx24116.c u8 b0[] = { reg }; reg 260 drivers/media/dvb-frontends/cx24116.c __func__, reg, ret); reg 266 drivers/media/dvb-frontends/cx24116.c reg, b1[0]); reg 257 drivers/media/dvb-frontends/cx24117.c static int cx24117_writereg(struct cx24117_state *state, u8 reg, u8 data) reg 259 drivers/media/dvb-frontends/cx24117.c u8 buf[] = { reg, data }; reg 266 drivers/media/dvb-frontends/cx24117.c __func__, state->demod, reg, data); reg 272 drivers/media/dvb-frontends/cx24117.c KBUILD_MODNAME, state->demod, ret, reg, data); reg 306 drivers/media/dvb-frontends/cx24117.c static int cx24117_readreg(struct cx24117_state *state, u8 reg) reg 312 drivers/media/dvb-frontends/cx24117.c .buf = ®, .len = 1 }, reg 321 drivers/media/dvb-frontends/cx24117.c KBUILD_MODNAME, state->demod, ret, reg); reg 326 drivers/media/dvb-frontends/cx24117.c __func__, state->demod, reg, recv); reg 332 drivers/media/dvb-frontends/cx24117.c u8 reg, u8 *buf, int len) reg 337 drivers/media/dvb-frontends/cx24117.c .buf = ®, .len = 1 }, reg 346 drivers/media/dvb-frontends/cx24117.c KBUILD_MODNAME, state->demod, ret, reg); reg 789 drivers/media/dvb-frontends/cx24117.c u8 reg = (state->demod == 0) ? reg 800 drivers/media/dvb-frontends/cx24117.c ret = cx24117_readregN(state, reg, buf, 2); reg 819 drivers/media/dvb-frontends/cx24117.c u8 reg = (state->demod == 0) ? reg 822 drivers/media/dvb-frontends/cx24117.c ret = cx24117_readregN(state, reg, buf, 2); reg 841 drivers/media/dvb-frontends/cx24117.c u8 reg = (state->demod == 0) ? reg 849 drivers/media/dvb-frontends/cx24117.c reg += (CX24117_REG_DVBS2_UCB2_0 - CX24117_REG_DVBS_UCB2_0); reg 855 drivers/media/dvb-frontends/cx24117.c ret = cx24117_readregN(state, reg, buf, 2); reg 878 drivers/media/dvb-frontends/cx24117.c u8 val, reg = (state->demod == 0) ? CX24117_REG_QSTATUS0 : reg 882 drivers/media/dvb-frontends/cx24117.c __func__, state->demod, cx24117_readreg(state, reg)); reg 886 drivers/media/dvb-frontends/cx24117.c val = cx24117_readreg(state, reg) & 0x01; reg 904 drivers/media/dvb-frontends/cx24117.c u8 reg = (state->demod == 0) ? 0x10 : 0x20; reg 914 drivers/media/dvb-frontends/cx24117.c cmd.args[2] = reg; /* mask */ reg 920 drivers/media/dvb-frontends/cx24117.c cmd.args[1] = reg; reg 1558 drivers/media/dvb-frontends/cx24117.c u8 reg, st, inv; reg 1574 drivers/media/dvb-frontends/cx24117.c reg = (state->demod == 0) ? CX24117_REG_FREQ3_0 : CX24117_REG_FREQ3_1; reg 1575 drivers/media/dvb-frontends/cx24117.c ret = cx24117_readregN(state, reg, buf, 0x1f-4); reg 162 drivers/media/dvb-frontends/cx24120.c static int cx24120_readreg(struct cx24120_state *state, u8 reg) reg 171 drivers/media/dvb-frontends/cx24120.c .buf = ® reg 182 drivers/media/dvb-frontends/cx24120.c err("Read error: reg=0x%02x, ret=%i)\n", reg, ret); reg 186 drivers/media/dvb-frontends/cx24120.c dev_dbg(&state->i2c->dev, "reg=0x%02x; data=0x%02x\n", reg, buf); reg 192 drivers/media/dvb-frontends/cx24120.c static int cx24120_writereg(struct cx24120_state *state, u8 reg, u8 data) reg 194 drivers/media/dvb-frontends/cx24120.c u8 buf[] = { reg, data }; reg 206 drivers/media/dvb-frontends/cx24120.c ret, reg, data); reg 210 drivers/media/dvb-frontends/cx24120.c dev_dbg(&state->i2c->dev, "reg=0x%02x; data=0x%02x\n", reg, data); reg 217 drivers/media/dvb-frontends/cx24120.c u8 reg, const u8 *values, u16 len, u8 incr) reg 234 drivers/media/dvb-frontends/cx24120.c msg.buf[0] = reg; reg 242 drivers/media/dvb-frontends/cx24120.c reg += msg.len; reg 247 drivers/media/dvb-frontends/cx24120.c err("i2c_write error(err == %i, 0x%02x)\n", ret, reg); reg 252 drivers/media/dvb-frontends/cx24120.c reg, msg.len - 1, msg.buf + 1); reg 1272 drivers/media/dvb-frontends/cx24120.c u8 reg; reg 1282 drivers/media/dvb-frontends/cx24120.c reg = cx24120_readreg(state, 0xfb) & 0xfe; reg 1283 drivers/media/dvb-frontends/cx24120.c cx24120_writereg(state, 0xfb, reg); reg 1284 drivers/media/dvb-frontends/cx24120.c reg = cx24120_readreg(state, 0xfc) & 0xfe; reg 1285 drivers/media/dvb-frontends/cx24120.c cx24120_writereg(state, 0xfc, reg); reg 1290 drivers/media/dvb-frontends/cx24120.c reg = cx24120_readreg(state, 0xea) & 0xfe; reg 1291 drivers/media/dvb-frontends/cx24120.c cx24120_writereg(state, 0xea, reg); reg 1305 drivers/media/dvb-frontends/cx24120.c cx24120_writereg(state, 0xea, (reg | 0x01)); reg 1333 drivers/media/dvb-frontends/cx24120.c reg = cx24120_readreg(state, 0xfb) & 0xfe; reg 1334 drivers/media/dvb-frontends/cx24120.c cx24120_writereg(state, 0xfb, reg); reg 1342 drivers/media/dvb-frontends/cx24120.c reg = (fw->size - 2) & 0x00ff; reg 1343 drivers/media/dvb-frontends/cx24120.c cx24120_writereg(state, 0xf8, reg); reg 1344 drivers/media/dvb-frontends/cx24120.c reg = ((fw->size - 2) >> 8) & 0x00ff; reg 1345 drivers/media/dvb-frontends/cx24120.c cx24120_writereg(state, 0xf9, reg); reg 1352 drivers/media/dvb-frontends/cx24120.c reg = cx24120_readreg(state, 0xe1); reg 1353 drivers/media/dvb-frontends/cx24120.c if (reg == fw->data[fw->size - 1]) { reg 1405 drivers/media/dvb-frontends/cx24120.c reg = cx24120_readreg(state, 0xba); reg 1406 drivers/media/dvb-frontends/cx24120.c if (reg > 3) { reg 185 drivers/media/dvb-frontends/cx24123.c u8 reg; reg 233 drivers/media/dvb-frontends/cx24123.c u8 i2c_addr, int reg, int data) reg 235 drivers/media/dvb-frontends/cx24123.c u8 buf[] = { reg, data }; reg 246 drivers/media/dvb-frontends/cx24123.c __func__, err, reg, data); reg 253 drivers/media/dvb-frontends/cx24123.c static int cx24123_i2c_readreg(struct cx24123_state *state, u8 i2c_addr, u8 reg) reg 258 drivers/media/dvb-frontends/cx24123.c { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 }, reg 265 drivers/media/dvb-frontends/cx24123.c err("%s: reg=0x%x (error=%d)\n", __func__, reg, ret); reg 274 drivers/media/dvb-frontends/cx24123.c #define cx24123_readreg(state, reg) \ reg 275 drivers/media/dvb-frontends/cx24123.c cx24123_i2c_readreg(state, state->config->demod_address, reg) reg 276 drivers/media/dvb-frontends/cx24123.c #define cx24123_writereg(state, reg, val) \ reg 277 drivers/media/dvb-frontends/cx24123.c cx24123_i2c_writereg(state, state->config->demod_address, reg, val) reg 695 drivers/media/dvb-frontends/cx24123.c cx24123_writereg(state, cx24123_regdata[i].reg, reg 86 drivers/media/dvb-frontends/cxd2099.c static int read_reg(struct cxd *ci, u8 reg, u8 *val) reg 88 drivers/media/dvb-frontends/cxd2099.c return read_block(ci, reg, val, 1); reg 139 drivers/media/dvb-frontends/cxd2099.c static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask) reg 144 drivers/media/dvb-frontends/cxd2099.c if (ci->lastaddress != reg) reg 145 drivers/media/dvb-frontends/cxd2099.c status = regmap_write(ci->regmap, 0, reg); reg 146 drivers/media/dvb-frontends/cxd2099.c if (!status && reg >= 6 && reg <= 8 && mask != 0xff) { reg 148 drivers/media/dvb-frontends/cxd2099.c ci->regs[reg] = regval; reg 150 drivers/media/dvb-frontends/cxd2099.c ci->lastaddress = reg; reg 151 drivers/media/dvb-frontends/cxd2099.c ci->regs[reg] = (ci->regs[reg] & (~mask)) | val; reg 153 drivers/media/dvb-frontends/cxd2099.c status = regmap_write(ci->regmap, 1, ci->regs[reg]); reg 154 drivers/media/dvb-frontends/cxd2099.c if (reg == 0x20) reg 155 drivers/media/dvb-frontends/cxd2099.c ci->regs[reg] &= 0x7f; reg 159 drivers/media/dvb-frontends/cxd2099.c static int write_reg(struct cxd *ci, u8 reg, u8 val) reg 161 drivers/media/dvb-frontends/cxd2099.c return write_regm(ci, reg, val, 0xff); reg 300 drivers/media/dvb-frontends/cxd2099.c u32 reg = ((ci->cfg.bitrate << 13) + 71999) / 72000; reg 314 drivers/media/dvb-frontends/cxd2099.c status = write_reg(ci, 0x21, (reg >> 8) & 0xff); reg 317 drivers/media/dvb-frontends/cxd2099.c status = write_reg(ci, 0x22, reg & 0xff); reg 17 drivers/media/dvb-frontends/cxd2820r_core.c unsigned int i, reg, mask, val; reg 23 drivers/media/dvb-frontends/cxd2820r_core.c if ((tab[i].reg >> 16) & 0x1) reg 28 drivers/media/dvb-frontends/cxd2820r_core.c reg = (tab[i].reg >> 0) & 0xffff; reg 33 drivers/media/dvb-frontends/cxd2820r_core.c ret = regmap_write(regmap, reg, val); reg 35 drivers/media/dvb-frontends/cxd2820r_core.c ret = regmap_write_bits(regmap, reg, mask, val); reg 21 drivers/media/dvb-frontends/cxd2820r_priv.h u32 reg; reg 62 drivers/media/dvb-frontends/cxd2820r_priv.h int cxd2820r_wr_reg_mask(struct cxd2820r_priv *priv, u32 reg, u8 val, reg 74 drivers/media/dvb-frontends/cxd2820r_priv.h int cxd2820r_wr_reg(struct cxd2820r_priv *priv, u32 reg, u8 val); reg 76 drivers/media/dvb-frontends/cxd2820r_priv.h int cxd2820r_rd_reg(struct cxd2820r_priv *priv, u32 reg, u8 *val); reg 203 drivers/media/dvb-frontends/cxd2841er.c u8 addr, u8 reg, u8 write, reg 208 drivers/media/dvb-frontends/cxd2841er.c (write == 0 ? "read" : "write"), addr, reg, len, len, data); reg 212 drivers/media/dvb-frontends/cxd2841er.c u8 addr, u8 reg, const u8 *data, u32 len) reg 229 drivers/media/dvb-frontends/cxd2841er.c reg, len + 1); reg 233 drivers/media/dvb-frontends/cxd2841er.c cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len); reg 234 drivers/media/dvb-frontends/cxd2841er.c buf[0] = reg; reg 243 drivers/media/dvb-frontends/cxd2841er.c KBUILD_MODNAME, ret, i2c_addr, reg, len); reg 250 drivers/media/dvb-frontends/cxd2841er.c u8 addr, u8 reg, u8 val) reg 254 drivers/media/dvb-frontends/cxd2841er.c return cxd2841er_write_regs(priv, addr, reg, &tmp, 1); reg 258 drivers/media/dvb-frontends/cxd2841er.c u8 addr, u8 reg, u8 *val, u32 len) reg 268 drivers/media/dvb-frontends/cxd2841er.c .buf = ®, reg 283 drivers/media/dvb-frontends/cxd2841er.c KBUILD_MODNAME, ret, i2c_addr, reg); reg 286 drivers/media/dvb-frontends/cxd2841er.c cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len); reg 291 drivers/media/dvb-frontends/cxd2841er.c u8 addr, u8 reg, u8 *val) reg 293 drivers/media/dvb-frontends/cxd2841er.c return cxd2841er_read_regs(priv, addr, reg, val, 1); reg 297 drivers/media/dvb-frontends/cxd2841er.c u8 addr, u8 reg, u8 data, u8 mask) reg 303 drivers/media/dvb-frontends/cxd2841er.c res = cxd2841er_read_reg(priv, addr, reg, &rdata); reg 308 drivers/media/dvb-frontends/cxd2841er.c return cxd2841er_write_reg(priv, addr, reg, data); reg 974 drivers/media/dvb-frontends/cxd2841er.c u8 reg = 0; reg 990 drivers/media/dvb-frontends/cxd2841er.c cxd2841er_read_reg(priv, I2C_SLVT, 0x11, ®); reg 991 drivers/media/dvb-frontends/cxd2841er.c if (reg & 0x04) { reg 1742 drivers/media/dvb-frontends/cxd2841er.c u32 reg; reg 1761 drivers/media/dvb-frontends/cxd2841er.c reg = ((u32)(data[0]&0x1f) << 8) | (u32)data[1]; reg 1762 drivers/media/dvb-frontends/cxd2841er.c if (reg == 0) { reg 1773 drivers/media/dvb-frontends/cxd2841er.c if (reg < 126) reg 1774 drivers/media/dvb-frontends/cxd2841er.c reg = 126; reg 1775 drivers/media/dvb-frontends/cxd2841er.c *snr = -95 * (int32_t)sony_log(reg) + 95941; reg 1780 drivers/media/dvb-frontends/cxd2841er.c if (reg < 69) reg 1781 drivers/media/dvb-frontends/cxd2841er.c reg = 69; reg 1782 drivers/media/dvb-frontends/cxd2841er.c *snr = -88 * (int32_t)sony_log(reg) + 86999; reg 1793 drivers/media/dvb-frontends/cxd2841er.c u32 reg; reg 1808 drivers/media/dvb-frontends/cxd2841er.c reg = ((u32)data[0] << 8) | (u32)data[1]; reg 1809 drivers/media/dvb-frontends/cxd2841er.c if (reg == 0) { reg 1814 drivers/media/dvb-frontends/cxd2841er.c if (reg > 4996) reg 1815 drivers/media/dvb-frontends/cxd2841er.c reg = 4996; reg 1816 drivers/media/dvb-frontends/cxd2841er.c *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(5350 - reg)) + 285); reg 1822 drivers/media/dvb-frontends/cxd2841er.c u32 reg; reg 1837 drivers/media/dvb-frontends/cxd2841er.c reg = ((u32)data[0] << 8) | (u32)data[1]; reg 1838 drivers/media/dvb-frontends/cxd2841er.c if (reg == 0) { reg 1843 drivers/media/dvb-frontends/cxd2841er.c if (reg > 10876) reg 1844 drivers/media/dvb-frontends/cxd2841er.c reg = 10876; reg 1845 drivers/media/dvb-frontends/cxd2841er.c *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(12600 - reg)) + 320); reg 1851 drivers/media/dvb-frontends/cxd2841er.c u32 reg; reg 1867 drivers/media/dvb-frontends/cxd2841er.c reg = ((u32)data[0] << 8) | (u32)data[1]; reg 1868 drivers/media/dvb-frontends/cxd2841er.c if (reg == 0) { reg 1873 drivers/media/dvb-frontends/cxd2841er.c *snr = 10000 * (intlog10(reg) >> 24) - 9031; reg 69 drivers/media/dvb-frontends/dib0070.c static u16 dib0070_read_reg(struct dib0070_state *state, u8 reg) reg 78 drivers/media/dvb-frontends/dib0070.c state->i2c_write_buffer[0] = reg; reg 101 drivers/media/dvb-frontends/dib0070.c static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val) reg 109 drivers/media/dvb-frontends/dib0070.c state->i2c_write_buffer[0] = reg; reg 200 drivers/media/dvb-frontends/dib0090.c static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg) reg 209 drivers/media/dvb-frontends/dib0090.c state->i2c_write_buffer[0] = reg; reg 232 drivers/media/dvb-frontends/dib0090.c static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val) reg 241 drivers/media/dvb-frontends/dib0090.c state->i2c_write_buffer[0] = reg & 0xff; reg 261 drivers/media/dvb-frontends/dib0090.c static u16 dib0090_fw_read_reg(struct dib0090_fw_state *state, u8 reg) reg 270 drivers/media/dvb-frontends/dib0090.c state->i2c_write_buffer[0] = reg; reg 273 drivers/media/dvb-frontends/dib0090.c state->msg.addr = reg; reg 288 drivers/media/dvb-frontends/dib0090.c static int dib0090_fw_write_reg(struct dib0090_fw_state *state, u8 reg, u16 val) reg 301 drivers/media/dvb-frontends/dib0090.c state->msg.addr = reg; reg 1673 drivers/media/dvb-frontends/dib0090.c u16 reg; reg 1684 drivers/media/dvb-frontends/dib0090.c reg = dib0090_read_reg(state, 0x24) & 0x0ffb; /* shutdown lna and lo */ reg 1685 drivers/media/dvb-frontends/dib0090.c dib0090_write_reg(state, 0x24, reg); reg 51 drivers/media/dvb-frontends/dib3000mb.c static int dib3000_read_reg(struct dib3000_state *state, u16 reg) reg 53 drivers/media/dvb-frontends/dib3000mb.c u8 wb[] = { ((reg >> 8) | 0x80) & 0xff, reg & 0xff }; reg 63 drivers/media/dvb-frontends/dib3000mb.c deb_i2c("reading i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg, reg 69 drivers/media/dvb-frontends/dib3000mb.c static int dib3000_write_reg(struct dib3000_state *state, u16 reg, u16 val) reg 72 drivers/media/dvb-frontends/dib3000mb.c (reg >> 8) & 0xff, reg & 0xff, reg 78 drivers/media/dvb-frontends/dib3000mb.c deb_i2c("writing i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,val,val); reg 14 drivers/media/dvb-frontends/dib3000mb_priv.h #define rd(reg) dib3000_read_reg(state,reg) reg 16 drivers/media/dvb-frontends/dib3000mb_priv.h #define wr(reg,val) if (dib3000_write_reg(state,reg,val)) \ reg 17 drivers/media/dvb-frontends/dib3000mb_priv.h { pr_err("while sending 0x%04x to 0x%04x.", val, reg); return -EREMOTEIO; } reg 26 drivers/media/dvb-frontends/dib3000mb_priv.h #define set_or(reg,val) wr(reg,rd(reg) | val) reg 28 drivers/media/dvb-frontends/dib3000mb_priv.h #define set_and(reg,val) wr(reg,rd(reg) & val) reg 53 drivers/media/dvb-frontends/dib3000mc.c static u16 dib3000mc_read_word(struct dib3000mc_state *state, u16 reg) reg 66 drivers/media/dvb-frontends/dib3000mc.c b[0] = (reg >> 8) | 0x80; reg 67 drivers/media/dvb-frontends/dib3000mc.c b[1] = reg; reg 75 drivers/media/dvb-frontends/dib3000mc.c dprintk("i2c read error on %d\n",reg); reg 83 drivers/media/dvb-frontends/dib3000mc.c static int dib3000mc_write_word(struct dib3000mc_state *state, u16 reg, u16 val) reg 95 drivers/media/dvb-frontends/dib3000mc.c b[0] = reg >> 8; reg 96 drivers/media/dvb-frontends/dib3000mc.c b[1] = reg; reg 249 drivers/media/dvb-frontends/dib3000mc.c u16 reg; reg 276 drivers/media/dvb-frontends/dib3000mc.c for (reg = 6; reg < 12; reg++) reg 277 drivers/media/dvb-frontends/dib3000mc.c dib3000mc_write_word(state, reg, bw_cfg[reg - 6]); reg 288 drivers/media/dvb-frontends/dib3000mc.c for (reg = 55; reg < 58; reg++) reg 289 drivers/media/dvb-frontends/dib3000mc.c dib3000mc_write_word(state, reg, imp_bw_cfg[reg - 55]); reg 456 drivers/media/dvb-frontends/dib3000mc.c u16 cfg[4] = { 0 },reg; reg 468 drivers/media/dvb-frontends/dib3000mc.c for (reg = 129; reg < 133; reg++) reg 469 drivers/media/dvb-frontends/dib3000mc.c dib3000mc_write_word(state, reg, cfg[reg - 129]); reg 588 drivers/media/dvb-frontends/dib3000mc.c u16 reg; reg 606 drivers/media/dvb-frontends/dib3000mc.c reg = dib3000mc_read_word(state, 0); reg 607 drivers/media/dvb-frontends/dib3000mc.c dib3000mc_write_word(state, 0, reg | (1 << 8)); reg 609 drivers/media/dvb-frontends/dib3000mc.c dib3000mc_write_word(state, 0, reg); reg 76 drivers/media/dvb-frontends/dib7000m.c static u16 dib7000m_read_word(struct dib7000m_state *state, u16 reg) reg 85 drivers/media/dvb-frontends/dib7000m.c state->i2c_write_buffer[0] = (reg >> 8) | 0x80; reg 86 drivers/media/dvb-frontends/dib7000m.c state->i2c_write_buffer[1] = reg & 0xff; reg 99 drivers/media/dvb-frontends/dib7000m.c dprintk("i2c read error on %d\n", reg); reg 107 drivers/media/dvb-frontends/dib7000m.c static int dib7000m_write_word(struct dib7000m_state *state, u16 reg, u16 val) reg 116 drivers/media/dvb-frontends/dib7000m.c state->i2c_write_buffer[0] = (reg >> 8) & 0xff; reg 117 drivers/media/dvb-frontends/dib7000m.c state->i2c_write_buffer[1] = reg & 0xff; reg 1015 drivers/media/dvb-frontends/dib7000m.c static int dib7000m_autosearch_irq(struct dib7000m_state *state, u16 reg) reg 1017 drivers/media/dvb-frontends/dib7000m.c u16 irq_pending = dib7000m_read_word(state, reg); reg 100 drivers/media/dvb-frontends/dib7000p.c static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg) reg 109 drivers/media/dvb-frontends/dib7000p.c state->i2c_write_buffer[0] = reg >> 8; reg 110 drivers/media/dvb-frontends/dib7000p.c state->i2c_write_buffer[1] = reg & 0xff; reg 123 drivers/media/dvb-frontends/dib7000p.c dprintk("i2c read error on %d\n", reg); reg 130 drivers/media/dvb-frontends/dib7000p.c static int dib7000p_write_word(struct dib7000p_state *state, u16 reg, u16 val) reg 139 drivers/media/dvb-frontends/dib7000p.c state->i2c_write_buffer[0] = (reg >> 8) & 0xff; reg 140 drivers/media/dvb-frontends/dib7000p.c state->i2c_write_buffer[1] = reg & 0xff; reg 305 drivers/media/dvb-frontends/dib7000p.c u16 reg; reg 315 drivers/media/dvb-frontends/dib7000p.c reg = dib7000p_read_word(state, 1925); reg 317 drivers/media/dvb-frontends/dib7000p.c dib7000p_write_word(state, 1925, reg | (1 << 4) | (1 << 2)); /* en_slowAdc = 1 & reset_sladc = 1 */ reg 319 drivers/media/dvb-frontends/dib7000p.c reg = dib7000p_read_word(state, 1925); /* read access to make it works... strange ... */ reg 321 drivers/media/dvb-frontends/dib7000p.c dib7000p_write_word(state, 1925, reg & ~(1 << 4)); /* en_slowAdc = 1 & reset_sladc = 0 */ reg 323 drivers/media/dvb-frontends/dib7000p.c reg = dib7000p_read_word(state, 72) & ~((0x3 << 14) | (0x3 << 12)); reg 324 drivers/media/dvb-frontends/dib7000p.c dib7000p_write_word(state, 72, reg | (1 << 14) | (3 << 12) | 524); /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ; (Vin2 = Vcm) */ reg 334 drivers/media/dvb-frontends/dib7000p.c reg = dib7000p_read_word(state, 1925); reg 335 drivers/media/dvb-frontends/dib7000p.c dib7000p_write_word(state, 1925, (reg & ~(1 << 2)) | (1 << 4)); /* reset_sladc = 1 en_slowAdc = 0 */ reg 844 drivers/media/dvb-frontends/dib7000p.c u16 reg; reg 852 drivers/media/dvb-frontends/dib7000p.c reg = dib7000p_read_word(state, 0x79b) & 0xff00; reg 854 drivers/media/dvb-frontends/dib7000p.c dib7000p_write_word(state, 0x79b, reg | (1 << 14) | ((upd_demod_gain_period >> 16) & 0xFF)); reg 857 drivers/media/dvb-frontends/dib7000p.c reg = dib7000p_read_word(state, 0x780); reg 858 drivers/media/dvb-frontends/dib7000p.c dib7000p_write_word(state, 0x780, (reg | (0x3)) & (~(1 << 7))); reg 2407 drivers/media/dvb-frontends/dib7000p.c u16 reg; reg 2410 drivers/media/dvb-frontends/dib7000p.c reg = dib7000p_read_word(state, 1798) & ~((0x7) | (0x7 << 6) | (0x7 << 12)); reg 2411 drivers/media/dvb-frontends/dib7000p.c reg |= (drive << 12) | (drive << 6) | drive; reg 2412 drivers/media/dvb-frontends/dib7000p.c dib7000p_write_word(state, 1798, reg); reg 2415 drivers/media/dvb-frontends/dib7000p.c reg = dib7000p_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8)); reg 2416 drivers/media/dvb-frontends/dib7000p.c reg |= (drive << 8) | (drive << 2); reg 2417 drivers/media/dvb-frontends/dib7000p.c dib7000p_write_word(state, 1799, reg); reg 2420 drivers/media/dvb-frontends/dib7000p.c reg = dib7000p_read_word(state, 1800) & ~((0x7) | (0x7 << 6) | (0x7 << 12)); reg 2421 drivers/media/dvb-frontends/dib7000p.c reg |= (drive << 12) | (drive << 6) | drive; reg 2422 drivers/media/dvb-frontends/dib7000p.c dib7000p_write_word(state, 1800, reg); reg 2425 drivers/media/dvb-frontends/dib7000p.c reg = dib7000p_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8)); reg 2426 drivers/media/dvb-frontends/dib7000p.c reg |= (drive << 8) | (drive << 2); reg 2427 drivers/media/dvb-frontends/dib7000p.c dib7000p_write_word(state, 1801, reg); reg 2430 drivers/media/dvb-frontends/dib7000p.c reg = dib7000p_read_word(state, 1802) & ~((0x7) | (0x7 << 6) | (0x7 << 12)); reg 2431 drivers/media/dvb-frontends/dib7000p.c reg |= (drive << 12) | (drive << 6) | drive; reg 2432 drivers/media/dvb-frontends/dib7000p.c dib7000p_write_word(state, 1802, reg); reg 2727 drivers/media/dvb-frontends/dib7000p.c u16 reg; reg 2729 drivers/media/dvb-frontends/dib7000p.c reg = dib7000p_read_word(state, 1794); reg 2730 drivers/media/dvb-frontends/dib7000p.c dib7000p_write_word(state, 1794, reg | (4 << 12)); reg 145 drivers/media/dvb-frontends/dib8000.c static u16 dib8000_i2c_read16(struct i2c_device *i2c, u16 reg) reg 159 drivers/media/dvb-frontends/dib8000.c msg[0].buf[0] = reg >> 8; reg 160 drivers/media/dvb-frontends/dib8000.c msg[0].buf[1] = reg & 0xff; reg 164 drivers/media/dvb-frontends/dib8000.c dprintk("i2c read error on %d\n", reg); reg 171 drivers/media/dvb-frontends/dib8000.c static u16 __dib8000_read_word(struct dib8000_state *state, u16 reg) reg 175 drivers/media/dvb-frontends/dib8000.c state->i2c_write_buffer[0] = reg >> 8; reg 176 drivers/media/dvb-frontends/dib8000.c state->i2c_write_buffer[1] = reg & 0xff; reg 189 drivers/media/dvb-frontends/dib8000.c dprintk("i2c read error on %d\n", reg); reg 196 drivers/media/dvb-frontends/dib8000.c static u16 dib8000_read_word(struct dib8000_state *state, u16 reg) reg 205 drivers/media/dvb-frontends/dib8000.c ret = __dib8000_read_word(state, reg); reg 212 drivers/media/dvb-frontends/dib8000.c static u32 dib8000_read32(struct dib8000_state *state, u16 reg) reg 221 drivers/media/dvb-frontends/dib8000.c rw[0] = __dib8000_read_word(state, reg + 0); reg 222 drivers/media/dvb-frontends/dib8000.c rw[1] = __dib8000_read_word(state, reg + 1); reg 229 drivers/media/dvb-frontends/dib8000.c static int dib8000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val) reg 240 drivers/media/dvb-frontends/dib8000.c msg.buf[0] = (reg >> 8) & 0xff; reg 241 drivers/media/dvb-frontends/dib8000.c msg.buf[1] = reg & 0xff; reg 251 drivers/media/dvb-frontends/dib8000.c static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val) reg 260 drivers/media/dvb-frontends/dib8000.c state->i2c_write_buffer[0] = (reg >> 8) & 0xff; reg 261 drivers/media/dvb-frontends/dib8000.c state->i2c_write_buffer[1] = reg & 0xff; reg 549 drivers/media/dvb-frontends/dib8000.c u16 reg, reg_907 = dib8000_read_word(state, 907); reg 559 drivers/media/dvb-frontends/dib8000.c reg = dib8000_read_word(state, 1925); reg 561 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 1925, reg | reg 565 drivers/media/dvb-frontends/dib8000.c reg = dib8000_read_word(state, 1925); reg 568 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 1925, reg & ~(1<<4)); reg 570 drivers/media/dvb-frontends/dib8000.c reg = dib8000_read_word(state, 921) & ~((0x3 << 14) reg 574 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 921, reg | (1 << 14) reg 581 drivers/media/dvb-frontends/dib8000.c reg = dib8000_read_word(state, 1925); reg 584 drivers/media/dvb-frontends/dib8000.c (reg & ~(1<<2)) | (1<<4)); reg 696 drivers/media/dvb-frontends/dib8000.c u16 clk_cfg1, reg; reg 733 drivers/media/dvb-frontends/dib8000.c reg = dib8000_read_word(state, 1857); reg 734 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15)); reg 736 drivers/media/dvb-frontends/dib8000.c reg = dib8000_read_word(state, 1858); /* Force clk out pll /2 */ reg 737 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 1858, reg | 1); reg 1170 drivers/media/dvb-frontends/dib8000.c u16 reg; reg 1209 drivers/media/dvb-frontends/dib8000.c reg = dib8000_read_word(state, 922) & (0x3 << 2); reg 1210 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2)); reg 1270 drivers/media/dvb-frontends/dib8000.c u16 reg; reg 1282 drivers/media/dvb-frontends/dib8000.c reg = dib8000_read_word(state, 1947)&0xff00; reg 1286 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 1947, reg | (1<<14) | reg 1290 drivers/media/dvb-frontends/dib8000.c reg = dib8000_read_word(state, 1920); reg 1291 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 1920, (reg | 0x3) & reg 1346 drivers/media/dvb-frontends/dib8000.c u16 reg; reg 1351 drivers/media/dvb-frontends/dib8000.c reg = dib8000_read_word(state, 1798) & reg 1353 drivers/media/dvb-frontends/dib8000.c reg |= (drive<<12) | (drive<<6) | drive; reg 1354 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 1798, reg); reg 1357 drivers/media/dvb-frontends/dib8000.c reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8)); reg 1358 drivers/media/dvb-frontends/dib8000.c reg |= (drive<<8) | (drive<<2); reg 1359 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 1799, reg); reg 1362 drivers/media/dvb-frontends/dib8000.c reg = dib8000_read_word(state, 1800) & reg 1364 drivers/media/dvb-frontends/dib8000.c reg |= (drive<<12) | (drive<<6) | drive; reg 1365 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 1800, reg); reg 1368 drivers/media/dvb-frontends/dib8000.c reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8)); reg 1369 drivers/media/dvb-frontends/dib8000.c reg |= (drive<<8) | (drive<<2); reg 1370 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 1801, reg); reg 1373 drivers/media/dvb-frontends/dib8000.c reg = dib8000_read_word(state, 1802) & reg 1375 drivers/media/dvb-frontends/dib8000.c reg |= (drive<<12) | (drive<<6) | drive; reg 1376 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 1802, reg); reg 2474 drivers/media/dvb-frontends/dib8000.c u16 reg = 11; /* P_search_end0 start addr */ reg 2476 drivers/media/dvb-frontends/dib8000.c for (reg = 11; reg < 16; reg += 2) { reg 2477 drivers/media/dvb-frontends/dib8000.c if (reg == 11) { reg 2482 drivers/media/dvb-frontends/dib8000.c } else if (reg == 13) reg 2484 drivers/media/dvb-frontends/dib8000.c else if (reg == 15) reg 2486 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, reg, (u16)((value >> 16) & 0xffff)); reg 2487 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, (reg + 1), (u16)(value & 0xffff)); reg 2896 drivers/media/dvb-frontends/dib8000.c u16 reg = 0; reg 2899 drivers/media/dvb-frontends/dib8000.c reg = dib8000_read_word(state, 274) & 0xfff0; reg 2900 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 274, reg | 0x7); /* P_dintlv_delay_ram = 7 because of MobileSdram */ reg 2904 drivers/media/dvb-frontends/dib8000.c reg = dib8000_read_word(state, 1280); reg 2905 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 1280, reg | (1 << 2)); /* force restart P_restart_sdram */ reg 2906 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 1280, reg); /* release restart P_restart_sdram */ reg 233 drivers/media/dvb-frontends/dib9000.c static int dib9000_read16_attr(struct dib9000_state *state, u16 reg, u8 *b, u32 len, u16 attribute) reg 239 drivers/media/dvb-frontends/dib9000.c if (state->platform.risc.fw_is_running && (reg < 1024)) reg 240 drivers/media/dvb-frontends/dib9000.c return dib9000_risc_apb_access_read(state, reg, attribute, NULL, 0, b, len); reg 252 drivers/media/dvb-frontends/dib9000.c state->i2c_write_buffer[0] = reg >> 8; reg 253 drivers/media/dvb-frontends/dib9000.c state->i2c_write_buffer[1] = reg & 0xff; reg 266 drivers/media/dvb-frontends/dib9000.c dprintk("i2c read error on %d\n", reg); reg 274 drivers/media/dvb-frontends/dib9000.c reg += l / 2; reg 280 drivers/media/dvb-frontends/dib9000.c static u16 dib9000_i2c_read16(struct i2c_device *i2c, u16 reg) reg 289 drivers/media/dvb-frontends/dib9000.c i2c->i2c_write_buffer[0] = reg >> 8; reg 290 drivers/media/dvb-frontends/dib9000.c i2c->i2c_write_buffer[1] = reg & 0xff; reg 293 drivers/media/dvb-frontends/dib9000.c dprintk("read register %x error\n", reg); reg 300 drivers/media/dvb-frontends/dib9000.c static inline u16 dib9000_read_word(struct dib9000_state *state, u16 reg) reg 302 drivers/media/dvb-frontends/dib9000.c if (dib9000_read16_attr(state, reg, state->i2c_read_buffer, 2, 0) != 0) reg 307 drivers/media/dvb-frontends/dib9000.c static inline u16 dib9000_read_word_attr(struct dib9000_state *state, u16 reg, u16 attribute) reg 309 drivers/media/dvb-frontends/dib9000.c if (dib9000_read16_attr(state, reg, state->i2c_read_buffer, 2, reg 315 drivers/media/dvb-frontends/dib9000.c #define dib9000_read16_noinc_attr(state, reg, b, len, attribute) dib9000_read16_attr(state, reg, b, len, (attribute) | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT) reg 317 drivers/media/dvb-frontends/dib9000.c static int dib9000_write16_attr(struct dib9000_state *state, u16 reg, const u8 *buf, u32 len, u16 attribute) reg 323 drivers/media/dvb-frontends/dib9000.c if (state->platform.risc.fw_is_running && (reg < 1024)) { reg 325 drivers/media/dvb-frontends/dib9000.c (state, reg, DATA_BUS_ACCESS_MODE_16BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | attribute, buf, len) != 0) reg 336 drivers/media/dvb-frontends/dib9000.c state->i2c_write_buffer[0] = (reg >> 8) & 0xff; reg 337 drivers/media/dvb-frontends/dib9000.c state->i2c_write_buffer[1] = (reg) & 0xff; reg 355 drivers/media/dvb-frontends/dib9000.c reg += l / 2; reg 361 drivers/media/dvb-frontends/dib9000.c static int dib9000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val) reg 368 drivers/media/dvb-frontends/dib9000.c i2c->i2c_write_buffer[0] = (reg >> 8) & 0xff; reg 369 drivers/media/dvb-frontends/dib9000.c i2c->i2c_write_buffer[1] = reg & 0xff; reg 376 drivers/media/dvb-frontends/dib9000.c static inline int dib9000_write_word(struct dib9000_state *state, u16 reg, u16 val) reg 379 drivers/media/dvb-frontends/dib9000.c return dib9000_write16_attr(state, reg, b, 2, 0); reg 382 drivers/media/dvb-frontends/dib9000.c static inline int dib9000_write_word_attr(struct dib9000_state *state, u16 reg, u16 val, u16 attribute) reg 385 drivers/media/dvb-frontends/dib9000.c return dib9000_write16_attr(state, reg, b, 2, attribute); reg 388 drivers/media/dvb-frontends/dib9000.c #define dib9000_write(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, 0) reg 389 drivers/media/dvb-frontends/dib9000.c #define dib9000_write16_noinc(state, reg, buf, len) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT) reg 390 drivers/media/dvb-frontends/dib9000.c #define dib9000_write16_noinc_attr(state, reg, buf, len, attribute) dib9000_write16_attr(state, reg, buf, len, DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | (attribute)) reg 20 drivers/media/dvb-frontends/dibx000_common.c static int dibx000_write_word(struct dibx000_i2c_master *mst, u16 reg, u16 val) reg 29 drivers/media/dvb-frontends/dibx000_common.c mst->i2c_write_buffer[0] = (reg >> 8) & 0xff; reg 30 drivers/media/dvb-frontends/dibx000_common.c mst->i2c_write_buffer[1] = reg & 0xff; reg 46 drivers/media/dvb-frontends/dibx000_common.c static u16 dibx000_read_word(struct dibx000_i2c_master *mst, u16 reg) reg 55 drivers/media/dvb-frontends/dibx000_common.c mst->i2c_write_buffer[0] = reg >> 8; reg 56 drivers/media/dvb-frontends/dibx000_common.c mst->i2c_write_buffer[1] = reg & 0xff; reg 69 drivers/media/dvb-frontends/dibx000_common.c dprintk("i2c read error on %d\n", reg); reg 225 drivers/media/dvb-frontends/drxd_hard.c static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags) reg 228 drivers/media/dvb-frontends/drxd_hard.c u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff, reg 229 drivers/media/dvb-frontends/drxd_hard.c flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff reg 239 drivers/media/dvb-frontends/drxd_hard.c static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags) reg 242 drivers/media/dvb-frontends/drxd_hard.c u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff, reg 243 drivers/media/dvb-frontends/drxd_hard.c flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff reg 255 drivers/media/dvb-frontends/drxd_hard.c static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags) reg 258 drivers/media/dvb-frontends/drxd_hard.c u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff, reg 259 drivers/media/dvb-frontends/drxd_hard.c flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff, reg 268 drivers/media/dvb-frontends/drxd_hard.c static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags) reg 271 drivers/media/dvb-frontends/drxd_hard.c u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff, reg 272 drivers/media/dvb-frontends/drxd_hard.c flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff, reg 283 drivers/media/dvb-frontends/drxd_hard.c u32 reg, u8 *data, u32 len, u8 flags) reg 286 drivers/media/dvb-frontends/drxd_hard.c u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff, reg 287 drivers/media/dvb-frontends/drxd_hard.c flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff reg 294 drivers/media/dvb-frontends/drxk_hard.c static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags) reg 302 drivers/media/dvb-frontends/drxk_hard.c if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { reg 303 drivers/media/dvb-frontends/drxk_hard.c mm1[0] = (((reg << 1) & 0xFF) | 0x01); reg 304 drivers/media/dvb-frontends/drxk_hard.c mm1[1] = ((reg >> 16) & 0xFF); reg 305 drivers/media/dvb-frontends/drxk_hard.c mm1[2] = ((reg >> 24) & 0xFF) | flags; reg 306 drivers/media/dvb-frontends/drxk_hard.c mm1[3] = ((reg >> 7) & 0xFF); reg 309 drivers/media/dvb-frontends/drxk_hard.c mm1[0] = ((reg << 1) & 0xFF); reg 310 drivers/media/dvb-frontends/drxk_hard.c mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); reg 313 drivers/media/dvb-frontends/drxk_hard.c dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags); reg 323 drivers/media/dvb-frontends/drxk_hard.c static int read16(struct drxk_state *state, u32 reg, u16 *data) reg 325 drivers/media/dvb-frontends/drxk_hard.c return read16_flags(state, reg, data, 0); reg 328 drivers/media/dvb-frontends/drxk_hard.c static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags) reg 336 drivers/media/dvb-frontends/drxk_hard.c if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { reg 337 drivers/media/dvb-frontends/drxk_hard.c mm1[0] = (((reg << 1) & 0xFF) | 0x01); reg 338 drivers/media/dvb-frontends/drxk_hard.c mm1[1] = ((reg >> 16) & 0xFF); reg 339 drivers/media/dvb-frontends/drxk_hard.c mm1[2] = ((reg >> 24) & 0xFF) | flags; reg 340 drivers/media/dvb-frontends/drxk_hard.c mm1[3] = ((reg >> 7) & 0xFF); reg 343 drivers/media/dvb-frontends/drxk_hard.c mm1[0] = ((reg << 1) & 0xFF); reg 344 drivers/media/dvb-frontends/drxk_hard.c mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); reg 347 drivers/media/dvb-frontends/drxk_hard.c dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags); reg 358 drivers/media/dvb-frontends/drxk_hard.c static int read32(struct drxk_state *state, u32 reg, u32 *data) reg 360 drivers/media/dvb-frontends/drxk_hard.c return read32_flags(state, reg, data, 0); reg 363 drivers/media/dvb-frontends/drxk_hard.c static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags) reg 369 drivers/media/dvb-frontends/drxk_hard.c if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { reg 370 drivers/media/dvb-frontends/drxk_hard.c mm[0] = (((reg << 1) & 0xFF) | 0x01); reg 371 drivers/media/dvb-frontends/drxk_hard.c mm[1] = ((reg >> 16) & 0xFF); reg 372 drivers/media/dvb-frontends/drxk_hard.c mm[2] = ((reg >> 24) & 0xFF) | flags; reg 373 drivers/media/dvb-frontends/drxk_hard.c mm[3] = ((reg >> 7) & 0xFF); reg 376 drivers/media/dvb-frontends/drxk_hard.c mm[0] = ((reg << 1) & 0xFF); reg 377 drivers/media/dvb-frontends/drxk_hard.c mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); reg 383 drivers/media/dvb-frontends/drxk_hard.c dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags); reg 387 drivers/media/dvb-frontends/drxk_hard.c static int write16(struct drxk_state *state, u32 reg, u16 data) reg 389 drivers/media/dvb-frontends/drxk_hard.c return write16_flags(state, reg, data, 0); reg 392 drivers/media/dvb-frontends/drxk_hard.c static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags) reg 398 drivers/media/dvb-frontends/drxk_hard.c if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) { reg 399 drivers/media/dvb-frontends/drxk_hard.c mm[0] = (((reg << 1) & 0xFF) | 0x01); reg 400 drivers/media/dvb-frontends/drxk_hard.c mm[1] = ((reg >> 16) & 0xFF); reg 401 drivers/media/dvb-frontends/drxk_hard.c mm[2] = ((reg >> 24) & 0xFF) | flags; reg 402 drivers/media/dvb-frontends/drxk_hard.c mm[3] = ((reg >> 7) & 0xFF); reg 405 drivers/media/dvb-frontends/drxk_hard.c mm[0] = ((reg << 1) & 0xFF); reg 406 drivers/media/dvb-frontends/drxk_hard.c mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0)); reg 413 drivers/media/dvb-frontends/drxk_hard.c dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags); reg 418 drivers/media/dvb-frontends/drxk_hard.c static int write32(struct drxk_state *state, u32 reg, u32 data) reg 420 drivers/media/dvb-frontends/drxk_hard.c return write32_flags(state, reg, data, 0); reg 228 drivers/media/dvb-frontends/ds3000.c static int ds3000_writereg(struct ds3000_state *state, int reg, int data) reg 230 drivers/media/dvb-frontends/ds3000.c u8 buf[] = { reg, data }; reg 235 drivers/media/dvb-frontends/ds3000.c dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data); reg 240 drivers/media/dvb-frontends/ds3000.c __func__, err, reg, data); reg 260 drivers/media/dvb-frontends/ds3000.c static int ds3000_writeFW(struct ds3000_state *state, int reg, reg 271 drivers/media/dvb-frontends/ds3000.c *(buf) = reg; reg 281 drivers/media/dvb-frontends/ds3000.c dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len); reg 286 drivers/media/dvb-frontends/ds3000.c __func__, ret, reg); reg 299 drivers/media/dvb-frontends/ds3000.c static int ds3000_readreg(struct ds3000_state *state, u8 reg) reg 302 drivers/media/dvb-frontends/ds3000.c u8 b0[] = { reg }; reg 321 drivers/media/dvb-frontends/ds3000.c printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret); reg 325 drivers/media/dvb-frontends/ds3000.c dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]); reg 20 drivers/media/dvb-frontends/ec100.c static int ec100_write_reg(struct ec100_state *state, u8 reg, u8 val) reg 23 drivers/media/dvb-frontends/ec100.c u8 buf[2] = {reg, val}; reg 38 drivers/media/dvb-frontends/ec100.c KBUILD_MODNAME, ret, reg); reg 46 drivers/media/dvb-frontends/ec100.c static int ec100_read_reg(struct ec100_state *state, u8 reg, u8 *val) reg 54 drivers/media/dvb-frontends/ec100.c .buf = ® reg 68 drivers/media/dvb-frontends/ec100.c KBUILD_MODNAME, ret, reg); reg 279 drivers/media/dvb-frontends/helene.c u8 reg, u8 write, const u8 *data, u32 len) reg 282 drivers/media/dvb-frontends/helene.c (write == 0 ? "read" : "write"), reg, len); reg 288 drivers/media/dvb-frontends/helene.c u8 reg, const u8 *data, u32 len) reg 304 drivers/media/dvb-frontends/helene.c reg, len + 1, sizeof(buf)); reg 308 drivers/media/dvb-frontends/helene.c helene_i2c_debug(priv, reg, 1, data, len); reg 309 drivers/media/dvb-frontends/helene.c buf[0] = reg; reg 317 drivers/media/dvb-frontends/helene.c KBUILD_MODNAME, ret, reg, len); reg 323 drivers/media/dvb-frontends/helene.c static int helene_write_reg(struct helene_priv *priv, u8 reg, u8 val) reg 327 drivers/media/dvb-frontends/helene.c return helene_write_regs(priv, reg, &tmp, 1); reg 331 drivers/media/dvb-frontends/helene.c u8 reg, u8 *val, u32 len) reg 339 drivers/media/dvb-frontends/helene.c .buf = ®, reg 354 drivers/media/dvb-frontends/helene.c KBUILD_MODNAME, ret, priv->i2c_address, reg); reg 363 drivers/media/dvb-frontends/helene.c KBUILD_MODNAME, ret, priv->i2c_address, reg); reg 366 drivers/media/dvb-frontends/helene.c helene_i2c_debug(priv, reg, 0, val, len); reg 370 drivers/media/dvb-frontends/helene.c static int helene_read_reg(struct helene_priv *priv, u8 reg, u8 *val) reg 372 drivers/media/dvb-frontends/helene.c return helene_read_regs(priv, reg, val, 1); reg 376 drivers/media/dvb-frontends/helene.c u8 reg, u8 data, u8 mask) reg 382 drivers/media/dvb-frontends/helene.c res = helene_read_reg(priv, reg, &rdata); reg 387 drivers/media/dvb-frontends/helene.c return helene_write_reg(priv, reg, data); reg 38 drivers/media/dvb-frontends/horus3a.c u8 reg, u8 write, const u8 *data, u32 len) reg 41 drivers/media/dvb-frontends/horus3a.c (write == 0 ? "read" : "write"), reg, len); reg 47 drivers/media/dvb-frontends/horus3a.c u8 reg, const u8 *data, u32 len) reg 62 drivers/media/dvb-frontends/horus3a.c reg, len + 1); reg 66 drivers/media/dvb-frontends/horus3a.c horus3a_i2c_debug(priv, reg, 1, data, len); reg 67 drivers/media/dvb-frontends/horus3a.c buf[0] = reg; reg 75 drivers/media/dvb-frontends/horus3a.c KBUILD_MODNAME, ret, reg, len); reg 81 drivers/media/dvb-frontends/horus3a.c static int horus3a_write_reg(struct horus3a_priv *priv, u8 reg, u8 val) reg 85 drivers/media/dvb-frontends/horus3a.c return horus3a_write_regs(priv, reg, &tmp, 1); reg 56 drivers/media/dvb-frontends/isl6423.c static int isl6423_write(struct isl6423_dev *isl6423, u8 reg) reg 62 drivers/media/dvb-frontends/isl6423.c struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = ®, .len = 1 }; reg 64 drivers/media/dvb-frontends/isl6423.c dprintk(FE_DEBUG, 1, "write reg %02X", reg); reg 42 drivers/media/dvb-frontends/itd1000.c static int itd1000_write_regs(struct itd1000_state *state, u8 reg, u8 v[], u8 len) reg 52 drivers/media/dvb-frontends/itd1000.c reg, len); reg 56 drivers/media/dvb-frontends/itd1000.c buf[0] = reg; reg 68 drivers/media/dvb-frontends/itd1000.c static int itd1000_read_reg(struct itd1000_state *state, u8 reg) reg 72 drivers/media/dvb-frontends/itd1000.c { .addr = state->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 }, reg 77 drivers/media/dvb-frontends/itd1000.c itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1); reg 40 drivers/media/dvb-frontends/l64781.c static int l64781_writereg (struct l64781_state* state, u8 reg, u8 data) reg 43 drivers/media/dvb-frontends/l64781.c u8 buf [] = { reg, data }; reg 48 drivers/media/dvb-frontends/l64781.c __func__, reg, ret); reg 53 drivers/media/dvb-frontends/l64781.c static int l64781_readreg (struct l64781_state* state, u8 reg) reg 56 drivers/media/dvb-frontends/l64781.c u8 b0 [] = { reg }; reg 53 drivers/media/dvb-frontends/lg2160.c static int lg216x_write_reg(struct lg216x_state *state, u16 reg, u8 val) reg 56 drivers/media/dvb-frontends/lg2160.c u8 buf[] = { reg >> 8, reg & 0xff, val }; reg 62 drivers/media/dvb-frontends/lg2160.c lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val); reg 77 drivers/media/dvb-frontends/lg2160.c static int lg216x_read_reg(struct lg216x_state *state, u16 reg, u8 *val) reg 80 drivers/media/dvb-frontends/lg2160.c u8 reg_buf[] = { reg >> 8, reg & 0xff }; reg 88 drivers/media/dvb-frontends/lg2160.c lg_reg("reg: 0x%04x\n", reg); reg 94 drivers/media/dvb-frontends/lg2160.c state->cfg->i2c_addr, reg, ret); reg 104 drivers/media/dvb-frontends/lg2160.c u16 reg; reg 116 drivers/media/dvb-frontends/lg2160.c ret = lg216x_write_reg(state, regs[i].reg, regs[i].val); reg 124 drivers/media/dvb-frontends/lg2160.c u16 reg, int bit, int onoff) reg 129 drivers/media/dvb-frontends/lg2160.c lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff); reg 131 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, reg, &val); reg 138 drivers/media/dvb-frontends/lg2160.c ret = lg216x_write_reg(state, reg, val); reg 189 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0015, .val = 0xe6 }, reg 191 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0015, .val = 0xf7 }, reg 192 drivers/media/dvb-frontends/lg2160.c { .reg = 0x001b, .val = 0x52 }, reg 193 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0208, .val = 0x00 }, reg 194 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0209, .val = 0x82 }, reg 195 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0210, .val = 0xf9 }, reg 196 drivers/media/dvb-frontends/lg2160.c { .reg = 0x020a, .val = 0x00 }, reg 197 drivers/media/dvb-frontends/lg2160.c { .reg = 0x020b, .val = 0x82 }, reg 198 drivers/media/dvb-frontends/lg2160.c { .reg = 0x020d, .val = 0x28 }, reg 199 drivers/media/dvb-frontends/lg2160.c { .reg = 0x020f, .val = 0x14 }, reg 204 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0000, .val = 0x41 }, reg 205 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0001, .val = 0xfb }, reg 206 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0216, .val = 0x00 }, reg 207 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0219, .val = 0x00 }, reg 208 drivers/media/dvb-frontends/lg2160.c { .reg = 0x021b, .val = 0x55 }, reg 209 drivers/media/dvb-frontends/lg2160.c { .reg = 0x0606, .val = 0x0a }, reg 394 drivers/media/dvb-frontends/lg2160.c u16 reg; reg 399 drivers/media/dvb-frontends/lg2160.c reg = 0x0400; reg 403 drivers/media/dvb-frontends/lg2160.c reg = 0x0500; reg 407 drivers/media/dvb-frontends/lg2160.c ret = lg216x_read_reg(state, reg, &val); reg 414 drivers/media/dvb-frontends/lg2160.c ret = lg216x_write_reg(state, reg, val); reg 101 drivers/media/dvb-frontends/lgdt3305.c static int lgdt3305_write_reg(struct lgdt3305_state *state, u16 reg, u8 val) reg 104 drivers/media/dvb-frontends/lgdt3305.c u8 buf[] = { reg >> 8, reg & 0xff, val }; reg 110 drivers/media/dvb-frontends/lgdt3305.c lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val); reg 125 drivers/media/dvb-frontends/lgdt3305.c static int lgdt3305_read_reg(struct lgdt3305_state *state, u16 reg, u8 *val) reg 128 drivers/media/dvb-frontends/lgdt3305.c u8 reg_buf[] = { reg >> 8, reg & 0xff }; reg 136 drivers/media/dvb-frontends/lgdt3305.c lg_reg("reg: 0x%04x\n", reg); reg 142 drivers/media/dvb-frontends/lgdt3305.c state->cfg->i2c_addr, reg, ret); reg 151 drivers/media/dvb-frontends/lgdt3305.c #define read_reg(state, reg) \ reg 154 drivers/media/dvb-frontends/lgdt3305.c int ret = lgdt3305_read_reg(state, reg, &__val); \ reg 161 drivers/media/dvb-frontends/lgdt3305.c u16 reg, int bit, int onoff) reg 166 drivers/media/dvb-frontends/lgdt3305.c lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff); reg 168 drivers/media/dvb-frontends/lgdt3305.c ret = lgdt3305_read_reg(state, reg, &val); reg 175 drivers/media/dvb-frontends/lgdt3305.c ret = lgdt3305_write_reg(state, reg, val); reg 181 drivers/media/dvb-frontends/lgdt3305.c u16 reg; reg 193 drivers/media/dvb-frontends/lgdt3305.c ret = lgdt3305_write_reg(state, regs[i].reg, regs[i].val); reg 589 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, }, reg 590 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x000d, .val = 0x02, }, reg 591 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x000e, .val = 0x02, }, reg 592 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, }, reg 593 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, }, reg 594 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, }, reg 595 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, }, reg 596 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, }, reg 597 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, }, reg 598 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTRL_7, .val = 0xf9, }, reg 599 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0112, .val = 0x17, }, reg 600 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0113, .val = 0x15, }, reg 601 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0114, .val = 0x18, }, reg 602 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0115, .val = 0xff, }, reg 603 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0116, .val = 0x3c, }, reg 604 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0214, .val = 0x67, }, reg 605 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0424, .val = 0x8d, }, reg 606 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0427, .val = 0x12, }, reg 607 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0428, .val = 0x4f, }, reg 608 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_IFBW_1, .val = 0x80, }, reg 609 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_IFBW_2, .val = 0x00, }, reg 610 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x030a, .val = 0x08, }, reg 611 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x030b, .val = 0x9b, }, reg 612 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x030d, .val = 0x00, }, reg 613 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x030e, .val = 0x1c, }, reg 614 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x0314, .val = 0xe1, }, reg 615 drivers/media/dvb-frontends/lgdt3305.c { .reg = 0x000d, .val = 0x82, }, reg 616 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, }, reg 617 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, }, reg 621 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, }, reg 622 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_GEN_CTRL_2, .val = 0xb0, }, reg 623 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_GEN_CTRL_3, .val = 0x01, }, reg 624 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_GEN_CONTROL, .val = 0x6f, }, reg 625 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_GEN_CTRL_4, .val = 0x03, }, reg 626 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, }, reg 627 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, }, reg 628 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, }, reg 629 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, }, reg 630 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, }, reg 631 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, }, reg 632 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_CR_CTRL_7, .val = 0x79, }, reg 633 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_AGC_POWER_REF_1, .val = 0x32, }, reg 634 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_AGC_POWER_REF_2, .val = 0xc4, }, reg 635 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_AGC_DELAY_PT_1, .val = 0x0d, }, reg 636 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_AGC_DELAY_PT_2, .val = 0x30, }, reg 637 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_1, .val = 0x80, }, reg 638 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_2, .val = 0x00, }, reg 639 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_IFBW_1, .val = 0x80, }, reg 640 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_IFBW_2, .val = 0x00, }, reg 641 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_AGC_CTRL_1, .val = 0x30, }, reg 642 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_AGC_CTRL_4, .val = 0x61, }, reg 643 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_FEC_BLOCK_CTRL, .val = 0xff, }, reg 644 drivers/media/dvb-frontends/lgdt3305.c { .reg = LGDT3305_TP_CTRL_1, .val = 0x1b, }, reg 123 drivers/media/dvb-frontends/lgdt3306a.c static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val) reg 126 drivers/media/dvb-frontends/lgdt3306a.c u8 buf[] = { reg >> 8, reg & 0xff, val }; reg 132 drivers/media/dvb-frontends/lgdt3306a.c dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val); reg 147 drivers/media/dvb-frontends/lgdt3306a.c static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val) reg 150 drivers/media/dvb-frontends/lgdt3306a.c u8 reg_buf[] = { reg >> 8, reg & 0xff }; reg 162 drivers/media/dvb-frontends/lgdt3306a.c state->cfg->i2c_addr, reg, ret); reg 168 drivers/media/dvb-frontends/lgdt3306a.c dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val); reg 173 drivers/media/dvb-frontends/lgdt3306a.c #define read_reg(state, reg) \ reg 176 drivers/media/dvb-frontends/lgdt3306a.c int ret = lgdt3306a_read_reg(state, reg, &__val); \ reg 183 drivers/media/dvb-frontends/lgdt3306a.c u16 reg, int bit, int onoff) reg 188 drivers/media/dvb-frontends/lgdt3306a.c dbg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff); reg 190 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_read_reg(state, reg, &val); reg 197 drivers/media/dvb-frontends/lgdt3306a.c ret = lgdt3306a_write_reg(state, reg, val); reg 93 drivers/media/dvb-frontends/lgdt330x.c enum I2C_REG reg, u8 *buf, int len) reg 95 drivers/media/dvb-frontends/lgdt330x.c u8 wr[] = { reg }; reg 115 drivers/media/dvb-frontends/lgdt330x.c __func__, state->client->addr, reg, ret); reg 60 drivers/media/dvb-frontends/lgs8gl5.c lgs8gl5_write_reg(struct lgs8gl5_state *state, u8 reg, u8 data) reg 63 drivers/media/dvb-frontends/lgs8gl5.c u8 buf[] = {reg, data}; reg 74 drivers/media/dvb-frontends/lgs8gl5.c __func__, reg, data, ret); reg 81 drivers/media/dvb-frontends/lgs8gl5.c lgs8gl5_read_reg(struct lgs8gl5_state *state, u8 reg) reg 84 drivers/media/dvb-frontends/lgs8gl5.c u8 b0[] = {reg}; reg 110 drivers/media/dvb-frontends/lgs8gl5.c lgs8gl5_update_reg(struct lgs8gl5_state *state, u8 reg, u8 data) reg 112 drivers/media/dvb-frontends/lgs8gl5.c lgs8gl5_read_reg(state, reg); reg 113 drivers/media/dvb-frontends/lgs8gl5.c lgs8gl5_write_reg(state, reg, data); reg 121 drivers/media/dvb-frontends/lgs8gl5.c lgs8gl5_update_alt_reg(struct lgs8gl5_state *state, u8 reg, u8 data) reg 124 drivers/media/dvb-frontends/lgs8gl5.c u8 b0[] = {reg}; reg 126 drivers/media/dvb-frontends/lgs8gl5.c u8 b2[] = {reg, data}; reg 40 drivers/media/dvb-frontends/lgs8gxx.c static int lgs8gxx_write_reg(struct lgs8gxx_state *priv, u8 reg, u8 data) reg 43 drivers/media/dvb-frontends/lgs8gxx.c u8 buf[] = { reg, data }; reg 47 drivers/media/dvb-frontends/lgs8gxx.c if (priv->config->prod != LGS8GXX_PROD_LGS8G75 && reg >= 0xC0) reg 51 drivers/media/dvb-frontends/lgs8gxx.c dprintk("%s: reg=0x%02X, data=0x%02X\n", __func__, reg, data); reg 57 drivers/media/dvb-frontends/lgs8gxx.c __func__, reg, data, ret); reg 62 drivers/media/dvb-frontends/lgs8gxx.c static int lgs8gxx_read_reg(struct lgs8gxx_state *priv, u8 reg, u8 *p_data) reg 67 drivers/media/dvb-frontends/lgs8gxx.c u8 b0[] = { reg }; reg 75 drivers/media/dvb-frontends/lgs8gxx.c if (priv->config->prod != LGS8GXX_PROD_LGS8G75 && reg >= 0xC0) reg 81 drivers/media/dvb-frontends/lgs8gxx.c dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg, ret); reg 87 drivers/media/dvb-frontends/lgs8gxx.c dprintk("%s: reg=0x%02X, data=0x%02X\n", __func__, reg, b1[0]); reg 101 drivers/media/dvb-frontends/lgs8gxx.c static int wait_reg_mask(struct lgs8gxx_state *priv, u8 reg, u8 mask, reg 108 drivers/media/dvb-frontends/lgs8gxx.c lgs8gxx_read_reg(priv, reg, &t); reg 318 drivers/media/dvb-frontends/lgs8gxx.c u8 reg, mask, val; reg 321 drivers/media/dvb-frontends/lgs8gxx.c reg = 0x13; reg 325 drivers/media/dvb-frontends/lgs8gxx.c reg = 0x4B; reg 330 drivers/media/dvb-frontends/lgs8gxx.c ret = wait_reg_mask(priv, reg, mask, val, 50, 40); reg 340 drivers/media/dvb-frontends/lgs8gxx.c u8 reg, mask, val; reg 343 drivers/media/dvb-frontends/lgs8gxx.c reg = 0x1f; reg 347 drivers/media/dvb-frontends/lgs8gxx.c reg = 0xA4; reg 352 drivers/media/dvb-frontends/lgs8gxx.c ret = wait_reg_mask(priv, reg, mask, val, 10, 20); reg 14 drivers/media/dvb-frontends/m88ds3103.c u8 reg, u8 mask, u8 val) reg 21 drivers/media/dvb-frontends/m88ds3103.c ret = regmap_bulk_read(dev->regmap, reg, &tmp, 1); reg 30 drivers/media/dvb-frontends/m88ds3103.c return regmap_bulk_write(dev->regmap, reg, &val, 1); reg 51 drivers/media/dvb-frontends/m88ds3103.c if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 || reg 53 drivers/media/dvb-frontends/m88ds3103.c ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, buf, j + 1); reg 45 drivers/media/dvb-frontends/m88ds3103_priv.h u8 reg; reg 52 drivers/media/dvb-frontends/m88rs2000.c u8 reg, u8 data) reg 55 drivers/media/dvb-frontends/m88rs2000.c u8 buf[] = { reg, data }; reg 67 drivers/media/dvb-frontends/m88rs2000.c __func__, reg, data, ret); reg 72 drivers/media/dvb-frontends/m88rs2000.c static u8 m88rs2000_readreg(struct m88rs2000_state *state, u8 reg) reg 75 drivers/media/dvb-frontends/m88rs2000.c u8 b0[] = { reg }; reg 96 drivers/media/dvb-frontends/m88rs2000.c __func__, reg, ret); reg 105 drivers/media/dvb-frontends/m88rs2000.c u8 reg; reg 107 drivers/media/dvb-frontends/m88rs2000.c reg = m88rs2000_readreg(state, 0x86); reg 108 drivers/media/dvb-frontends/m88rs2000.c if (!reg || reg == 0xff) reg 111 drivers/media/dvb-frontends/m88rs2000.c reg /= 2; reg 112 drivers/media/dvb-frontends/m88rs2000.c reg += 1; reg 114 drivers/media/dvb-frontends/m88rs2000.c mclk = (u32)(reg * RS2000_FE_CRYSTAL_KHZ + 28 / 2) / 28; reg 124 drivers/media/dvb-frontends/m88rs2000.c u8 reg; reg 138 drivers/media/dvb-frontends/m88rs2000.c reg = m88rs2000_readreg(state, 0x9d); reg 139 drivers/media/dvb-frontends/m88rs2000.c reg &= 0xf; reg 140 drivers/media/dvb-frontends/m88rs2000.c reg |= (u8)(tmp & 0xf) << 4; reg 142 drivers/media/dvb-frontends/m88rs2000.c ret |= m88rs2000_writereg(state, 0x9d, reg); reg 199 drivers/media/dvb-frontends/m88rs2000.c u8 reg; reg 202 drivers/media/dvb-frontends/m88rs2000.c reg = m88rs2000_readreg(state, 0xb2); reg 203 drivers/media/dvb-frontends/m88rs2000.c reg &= 0x3f; reg 204 drivers/media/dvb-frontends/m88rs2000.c m88rs2000_writereg(state, 0xb2, reg); reg 208 drivers/media/dvb-frontends/m88rs2000.c reg = m88rs2000_readreg(state, 0xb1); reg 209 drivers/media/dvb-frontends/m88rs2000.c reg &= 0x87; reg 210 drivers/media/dvb-frontends/m88rs2000.c reg |= ((m->msg_len - 1) << 3) | 0x07; reg 211 drivers/media/dvb-frontends/m88rs2000.c reg &= 0x7f; reg 212 drivers/media/dvb-frontends/m88rs2000.c m88rs2000_writereg(state, 0xb1, reg); reg 220 drivers/media/dvb-frontends/m88rs2000.c reg = m88rs2000_readreg(state, 0xb1); reg 221 drivers/media/dvb-frontends/m88rs2000.c if ((reg & 0x40) > 0x0) { reg 222 drivers/media/dvb-frontends/m88rs2000.c reg &= 0x7f; reg 223 drivers/media/dvb-frontends/m88rs2000.c reg |= 0x40; reg 224 drivers/media/dvb-frontends/m88rs2000.c m88rs2000_writereg(state, 0xb1, reg); reg 227 drivers/media/dvb-frontends/m88rs2000.c reg = m88rs2000_readreg(state, 0xb2); reg 228 drivers/media/dvb-frontends/m88rs2000.c reg &= 0x3f; reg 229 drivers/media/dvb-frontends/m88rs2000.c reg |= 0x80; reg 230 drivers/media/dvb-frontends/m88rs2000.c m88rs2000_writereg(state, 0xb2, reg); reg 285 drivers/media/dvb-frontends/m88rs2000.c u8 reg; reg 383 drivers/media/dvb-frontends/m88rs2000.c ret = m88rs2000_writereg(state, tab[i].reg, reg 387 drivers/media/dvb-frontends/m88rs2000.c if (tab[i].reg > 0) reg 388 drivers/media/dvb-frontends/m88rs2000.c mdelay(tab[i].reg); reg 391 drivers/media/dvb-frontends/m88rs2000.c if (tab[i].reg == 0xaa && tab[i].val == 0xff) reg 459 drivers/media/dvb-frontends/m88rs2000.c u8 reg = m88rs2000_readreg(state, 0x8c); reg 463 drivers/media/dvb-frontends/m88rs2000.c if ((reg & 0xee) == 0xee) { reg 535 drivers/media/dvb-frontends/m88rs2000.c u8 fec_set, reg; reg 559 drivers/media/dvb-frontends/m88rs2000.c reg = m88rs2000_readreg(state, 0x70); reg 560 drivers/media/dvb-frontends/m88rs2000.c reg &= 0x7; reg 561 drivers/media/dvb-frontends/m88rs2000.c ret = m88rs2000_writereg(state, 0x70, reg | fec_set); reg 570 drivers/media/dvb-frontends/m88rs2000.c u8 reg; reg 572 drivers/media/dvb-frontends/m88rs2000.c reg = m88rs2000_readreg(state, 0x76); reg 575 drivers/media/dvb-frontends/m88rs2000.c reg &= 0xf0; reg 576 drivers/media/dvb-frontends/m88rs2000.c reg >>= 5; reg 578 drivers/media/dvb-frontends/m88rs2000.c switch (reg) { reg 604 drivers/media/dvb-frontends/m88rs2000.c u8 reg; reg 675 drivers/media/dvb-frontends/m88rs2000.c reg = m88rs2000_readreg(state, 0x8c); reg 676 drivers/media/dvb-frontends/m88rs2000.c if ((reg & 0xee) == 0xee) { reg 682 drivers/media/dvb-frontends/m88rs2000.c reg = m88rs2000_readreg(state, 0x70); reg 683 drivers/media/dvb-frontends/m88rs2000.c reg ^= 0x4; reg 684 drivers/media/dvb-frontends/m88rs2000.c m88rs2000_writereg(state, 0x70, reg); reg 693 drivers/media/dvb-frontends/m88rs2000.c reg = m88rs2000_readreg(state, 0x65); reg 62 drivers/media/dvb-frontends/mb86a16.c static int mb86a16_write(struct mb86a16_state *state, u8 reg, u8 val) reg 65 drivers/media/dvb-frontends/mb86a16.c u8 buf[] = { reg, val }; reg 83 drivers/media/dvb-frontends/mb86a16.c static int mb86a16_read(struct mb86a16_state *state, u8 reg, u8 *val) reg 86 drivers/media/dvb-frontends/mb86a16.c u8 b0[] = { reg }; reg 105 drivers/media/dvb-frontends/mb86a16.c reg, ret); reg 48 drivers/media/dvb-frontends/mb86a20s.c u8 reg; reg 213 drivers/media/dvb-frontends/mb86a20s.c u8 i2c_addr, u8 reg, u8 data) reg 215 drivers/media/dvb-frontends/mb86a20s.c u8 buf[] = { reg, data }; reg 225 drivers/media/dvb-frontends/mb86a20s.c __func__, rc, reg, data); reg 238 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg, reg 247 drivers/media/dvb-frontends/mb86a20s.c u8 i2c_addr, u8 reg) reg 252 drivers/media/dvb-frontends/mb86a20s.c { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 }, reg 260 drivers/media/dvb-frontends/mb86a20s.c __func__, reg, rc); reg 267 drivers/media/dvb-frontends/mb86a20s.c #define mb86a20s_readreg(state, reg) \ reg 268 drivers/media/dvb-frontends/mb86a20s.c mb86a20s_i2c_readreg(state, state->config->demod_address, reg) reg 269 drivers/media/dvb-frontends/mb86a20s.c #define mb86a20s_writereg(state, reg, val) \ reg 270 drivers/media/dvb-frontends/mb86a20s.c mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val) reg 380 drivers/media/dvb-frontends/mb86a20s.c static unsigned char reg[] = { reg 386 drivers/media/dvb-frontends/mb86a20s.c if (layer >= ARRAY_SIZE(reg)) reg 388 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x6d, reg[layer]); reg 413 drivers/media/dvb-frontends/mb86a20s.c static unsigned char reg[] = { reg 419 drivers/media/dvb-frontends/mb86a20s.c if (layer >= ARRAY_SIZE(reg)) reg 421 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x6d, reg[layer]); reg 451 drivers/media/dvb-frontends/mb86a20s.c static unsigned char reg[] = { reg 457 drivers/media/dvb-frontends/mb86a20s.c if (layer >= ARRAY_SIZE(reg)) reg 459 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x6d, reg[layer]); reg 473 drivers/media/dvb-frontends/mb86a20s.c static unsigned char reg[] = { reg 481 drivers/media/dvb-frontends/mb86a20s.c if (layer >= ARRAY_SIZE(reg)) reg 484 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x6d, reg[layer]); reg 50 drivers/media/dvb-frontends/mt312.c static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg, reg 55 drivers/media/dvb-frontends/mt312.c u8 regbuf[1] = { reg }; reg 75 drivers/media/dvb-frontends/mt312.c dprintk("R(%d):", reg & 0x7f); reg 84 drivers/media/dvb-frontends/mt312.c static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg, reg 99 drivers/media/dvb-frontends/mt312.c dprintk("W(%d):", reg & 0x7f); reg 105 drivers/media/dvb-frontends/mt312.c buf[0] = reg; reg 124 drivers/media/dvb-frontends/mt312.c const enum mt312_reg_addr reg, u8 *val) reg 126 drivers/media/dvb-frontends/mt312.c return mt312_read(state, reg, val, 1); reg 130 drivers/media/dvb-frontends/mt312.c const enum mt312_reg_addr reg, const u8 val) reg 135 drivers/media/dvb-frontends/mt312.c return mt312_write(state, reg, &tmp, 1); reg 44 drivers/media/dvb-frontends/mt352.c static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val) reg 47 drivers/media/dvb-frontends/mt352.c u8 buf[2] = { reg, val }; reg 52 drivers/media/dvb-frontends/mt352.c printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err); reg 68 drivers/media/dvb-frontends/mt352.c static int mt352_read_register(struct mt352_state* state, u8 reg) reg 71 drivers/media/dvb-frontends/mt352.c u8 b0 [] = { reg }; reg 84 drivers/media/dvb-frontends/mt352.c __func__, reg, ret); reg 158 drivers/media/dvb-frontends/mxl5xx.c static int read_register_unlocked(struct mxl *state, u32 reg, u32 *val) reg 163 drivers/media/dvb-frontends/mxl5xx.c GET_BYTE(reg, 0), GET_BYTE(reg, 1), reg 164 drivers/media/dvb-frontends/mxl5xx.c GET_BYTE(reg, 2), GET_BYTE(reg, 3), reg 211 drivers/media/dvb-frontends/mxl5xx.c static int write_register(struct mxl *state, u32 reg, u32 val) reg 216 drivers/media/dvb-frontends/mxl5xx.c BYTE0(reg), BYTE1(reg), BYTE2(reg), BYTE3(reg), reg 228 drivers/media/dvb-frontends/mxl5xx.c u32 reg, u32 size, u8 *reg_data_ptr) reg 236 drivers/media/dvb-frontends/mxl5xx.c buf[2] = GET_BYTE(reg, 0); reg 237 drivers/media/dvb-frontends/mxl5xx.c buf[3] = GET_BYTE(reg, 1); reg 238 drivers/media/dvb-frontends/mxl5xx.c buf[4] = GET_BYTE(reg, 2); reg 239 drivers/media/dvb-frontends/mxl5xx.c buf[5] = GET_BYTE(reg, 3); reg 250 drivers/media/dvb-frontends/mxl5xx.c static int read_register(struct mxl *state, u32 reg, u32 *val) reg 255 drivers/media/dvb-frontends/mxl5xx.c GET_BYTE(reg, 0), GET_BYTE(reg, 1), reg 256 drivers/media/dvb-frontends/mxl5xx.c GET_BYTE(reg, 2), GET_BYTE(reg, 3), reg 274 drivers/media/dvb-frontends/mxl5xx.c static int read_register_block(struct mxl *state, u32 reg, u32 size, u8 *data) reg 283 drivers/media/dvb-frontends/mxl5xx.c buf[2] = GET_BYTE(reg, 0); reg 284 drivers/media/dvb-frontends/mxl5xx.c buf[3] = GET_BYTE(reg, 1); reg 285 drivers/media/dvb-frontends/mxl5xx.c buf[4] = GET_BYTE(reg, 2); reg 286 drivers/media/dvb-frontends/mxl5xx.c buf[5] = GET_BYTE(reg, 3); reg 298 drivers/media/dvb-frontends/mxl5xx.c u32 reg, u8 lsbloc, u8 numofbits, u32 *val) reg 303 drivers/media/dvb-frontends/mxl5xx.c stat = read_register(state, reg, &data); reg 315 drivers/media/dvb-frontends/mxl5xx.c u32 reg, u8 lsbloc, u8 numofbits, u32 val) reg 320 drivers/media/dvb-frontends/mxl5xx.c stat = read_register(state, reg, &data); reg 325 drivers/media/dvb-frontends/mxl5xx.c stat = write_register(state, reg, data); reg 547 drivers/media/dvb-frontends/mxl5xx.c u32 reg[8]; reg 555 drivers/media/dvb-frontends/mxl5xx.c (u8 *) ®[0]); reg 562 drivers/media/dvb-frontends/mxl5xx.c p->pre_bit_error.stat[0].uvalue = reg[2]; reg 564 drivers/media/dvb-frontends/mxl5xx.c p->pre_bit_count.stat[0].uvalue = reg[3]; reg 574 drivers/media/dvb-frontends/mxl5xx.c (u8 *) ®[0]); reg 580 drivers/media/dvb-frontends/mxl5xx.c p->post_bit_error.stat[0].uvalue = reg[5]; reg 582 drivers/media/dvb-frontends/mxl5xx.c p->post_bit_count.stat[0].uvalue = reg[6]; reg 586 drivers/media/dvb-frontends/mxl5xx.c p->post_bit_error.stat[0].uvalue = reg[1]; reg 588 drivers/media/dvb-frontends/mxl5xx.c p->post_bit_count.stat[0].uvalue = reg[2]; reg 84 drivers/media/dvb-frontends/nxt200x.c static int nxt200x_writebytes (struct nxt200x_state* state, u8 reg, reg 93 drivers/media/dvb-frontends/nxt200x.c __func__, reg, len); reg 97 drivers/media/dvb-frontends/nxt200x.c buf2[0] = reg; reg 108 drivers/media/dvb-frontends/nxt200x.c static int nxt200x_readbytes(struct nxt200x_state *state, u8 reg, u8 *buf, u8 len) reg 110 drivers/media/dvb-frontends/nxt200x.c u8 reg2 [] = { reg }; reg 141 drivers/media/dvb-frontends/nxt200x.c static int nxt200x_writereg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len) reg 147 drivers/media/dvb-frontends/nxt200x.c nxt200x_writebytes(state, 0x35, ®, 1); reg 160 drivers/media/dvb-frontends/nxt200x.c if (reg & 0x80) { reg 162 drivers/media/dvb-frontends/nxt200x.c if (reg & 0x04) reg 196 drivers/media/dvb-frontends/nxt200x.c pr_warn("Error writing multireg register 0x%02X\n", reg); reg 201 drivers/media/dvb-frontends/nxt200x.c static int nxt200x_readreg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len) reg 208 drivers/media/dvb-frontends/nxt200x.c nxt200x_writebytes(state, 0x35, ®, 1); reg 217 drivers/media/dvb-frontends/nxt200x.c nxt200x_readbytes(state, reg, data, len); reg 223 drivers/media/dvb-frontends/nxt200x.c if (reg & 0x80) { reg 225 drivers/media/dvb-frontends/nxt200x.c if (reg & 0x04) reg 38 drivers/media/dvb-frontends/nxt6000.c static int nxt6000_writereg(struct nxt6000_state* state, u8 reg, u8 data) reg 40 drivers/media/dvb-frontends/nxt6000.c u8 buf[] = { reg, data }; reg 45 drivers/media/dvb-frontends/nxt6000.c dprintk("nxt6000: nxt6000_write error (reg: 0x%02X, data: 0x%02X, ret: %d)\n", reg, data, ret); reg 50 drivers/media/dvb-frontends/nxt6000.c static u8 nxt6000_readreg(struct nxt6000_state* state, u8 reg) reg 53 drivers/media/dvb-frontends/nxt6000.c u8 b0[] = { reg }; reg 63 drivers/media/dvb-frontends/nxt6000.c dprintk("nxt6000: nxt6000_read error (reg: 0x%02X, ret: %d)\n", reg, ret); reg 99 drivers/media/dvb-frontends/or51132.c static int or51132_readreg(struct or51132_state *state, u8 reg) reg 101 drivers/media/dvb-frontends/or51132.c u8 buf[2] = { 0x04, reg }; reg 111 drivers/media/dvb-frontends/or51132.c reg, err); reg 404 drivers/media/dvb-frontends/or51132.c int reg; reg 407 drivers/media/dvb-frontends/or51132.c if ((reg = or51132_readreg(state, 0x00)) < 0) { reg 408 drivers/media/dvb-frontends/or51132.c printk(KERN_WARNING "or51132: read_status: error reading receiver status: %d\n", reg); reg 412 drivers/media/dvb-frontends/or51132.c dprintk("%s: read_status %04x\n", __func__, reg); reg 414 drivers/media/dvb-frontends/or51132.c if (reg & 0x0100) /* Receiver Lock */ reg 461 drivers/media/dvb-frontends/or51132.c int noise, reg; reg 476 drivers/media/dvb-frontends/or51132.c reg = or51132_readreg(state, 0x00); reg 477 drivers/media/dvb-frontends/or51132.c if (reg < 0) { reg 482 drivers/media/dvb-frontends/or51132.c switch (reg&0xff) { reg 484 drivers/media/dvb-frontends/or51132.c if (reg & 0x1000) usK = 3 << 24; reg 493 drivers/media/dvb-frontends/or51132.c printk(KERN_WARNING "or51132: unknown status 0x%02x\n", reg&0xff); reg 498 drivers/media/dvb-frontends/or51132.c reg&0xff, reg&0x1000?"n":"ff"); reg 58 drivers/media/dvb-frontends/or51211.c static int i2c_writebytes (struct or51211_state* state, u8 reg, const u8 *buf, reg 63 drivers/media/dvb-frontends/or51211.c msg.addr = reg; reg 69 drivers/media/dvb-frontends/or51211.c pr_warn("error (addr %02x, err == %i)\n", reg, err); reg 76 drivers/media/dvb-frontends/or51211.c static int i2c_readbytes(struct or51211_state *state, u8 reg, u8 *buf, int len) reg 80 drivers/media/dvb-frontends/or51211.c msg.addr = reg; reg 86 drivers/media/dvb-frontends/or51211.c pr_warn("error (addr %02x, err == %i)\n", reg, err); reg 11 drivers/media/dvb-frontends/rtl2830.c static int rtl2830_bulk_write(struct i2c_client *client, unsigned int reg, reg 18 drivers/media/dvb-frontends/rtl2830.c ret = regmap_bulk_write(dev->regmap, reg, val, val_count); reg 23 drivers/media/dvb-frontends/rtl2830.c static int rtl2830_update_bits(struct i2c_client *client, unsigned int reg, reg 30 drivers/media/dvb-frontends/rtl2830.c ret = regmap_update_bits(dev->regmap, reg, mask, val); reg 35 drivers/media/dvb-frontends/rtl2830.c static int rtl2830_bulk_read(struct i2c_client *client, unsigned int reg, reg 42 drivers/media/dvb-frontends/rtl2830.c ret = regmap_bulk_read(dev->regmap, reg, val, val_count); reg 93 drivers/media/dvb-frontends/rtl2830.c ret = rtl2830_update_bits(client, tab[i].reg, tab[i].mask, reg 742 drivers/media/dvb-frontends/rtl2830.c static int rtl2830_regmap_gather_write(void *context, const void *reg, reg 758 drivers/media/dvb-frontends/rtl2830.c buf[0] = *(u8 const *)reg; reg 34 drivers/media/dvb-frontends/rtl2830_priv.h u16 reg; reg 143 drivers/media/dvb-frontends/rtl2832.c static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val) reg 151 drivers/media/dvb-frontends/rtl2832.c reg_start_addr = registers[reg].start_address; reg 152 drivers/media/dvb-frontends/rtl2832.c msb = registers[reg].msb; reg 153 drivers/media/dvb-frontends/rtl2832.c lsb = registers[reg].lsb; reg 173 drivers/media/dvb-frontends/rtl2832.c static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val) reg 181 drivers/media/dvb-frontends/rtl2832.c reg_start_addr = registers[reg].start_address; reg 182 drivers/media/dvb-frontends/rtl2832.c msb = registers[reg].msb; reg 183 drivers/media/dvb-frontends/rtl2832.c lsb = registers[reg].lsb; reg 305 drivers/media/dvb-frontends/rtl2832.c ret = rtl2832_wr_demod_reg(dev, rtl2832_initial_regs[i].reg, reg 347 drivers/media/dvb-frontends/rtl2832.c ret = rtl2832_wr_demod_reg(dev, init[i].reg, init[i].value); reg 864 drivers/media/dvb-frontends/rtl2832.c static bool rtl2832_volatile_reg(struct device *dev, unsigned int reg) reg 866 drivers/media/dvb-frontends/rtl2832.c switch (reg) { reg 44 drivers/media/dvb-frontends/rtl2832_priv.h int reg; reg 54 drivers/media/dvb-frontends/s5h1409.c u8 reg; reg 301 drivers/media/dvb-frontends/s5h1409.c static int s5h1409_writereg(struct s5h1409_state *state, u8 reg, u16 data) reg 304 drivers/media/dvb-frontends/s5h1409.c u8 buf[] = { reg, data >> 8, data & 0xff }; reg 313 drivers/media/dvb-frontends/s5h1409.c __func__, reg, data, ret); reg 318 drivers/media/dvb-frontends/s5h1409.c static u16 s5h1409_readreg(struct s5h1409_state *state, u8 reg) reg 321 drivers/media/dvb-frontends/s5h1409.c u8 b0[] = { reg }; reg 471 drivers/media/dvb-frontends/s5h1409.c u16 reg; reg 486 drivers/media/dvb-frontends/s5h1409.c reg = s5h1409_readreg(state, 0xf0); reg 488 drivers/media/dvb-frontends/s5h1409.c if ((reg >> 13) & 0x1) { reg 489 drivers/media/dvb-frontends/s5h1409.c reg &= 0xff; reg 492 drivers/media/dvb-frontends/s5h1409.c if (reg < 0x68) { reg 524 drivers/media/dvb-frontends/s5h1409.c u16 reg; reg 530 drivers/media/dvb-frontends/s5h1409.c reg = s5h1409_readreg(state, 0xf0); reg 532 drivers/media/dvb-frontends/s5h1409.c if ((reg >> 13) & 0x1) { reg 535 drivers/media/dvb-frontends/s5h1409.c reg &= 0xff; reg 538 drivers/media/dvb-frontends/s5h1409.c if ((reg < 0x38) || (reg > 0x68)) { reg 556 drivers/media/dvb-frontends/s5h1409.c u16 reg, reg1, reg2; reg 563 drivers/media/dvb-frontends/s5h1409.c reg = s5h1409_readreg(state, 0xf1); reg 566 drivers/media/dvb-frontends/s5h1409.c if ((reg >> 15) & 0x1) { reg 594 drivers/media/dvb-frontends/s5h1409.c u16 reg, reg1, reg2; reg 596 drivers/media/dvb-frontends/s5h1409.c reg = s5h1409_readreg(state, 0xf1); reg 599 drivers/media/dvb-frontends/s5h1409.c if ((reg >> 15) & 0x1) { reg 707 drivers/media/dvb-frontends/s5h1409.c s5h1409_writereg(state, init_tab[i].reg, init_tab[i].data); reg 749 drivers/media/dvb-frontends/s5h1409.c u16 reg; reg 766 drivers/media/dvb-frontends/s5h1409.c reg = s5h1409_readreg(state, 0xf1); reg 767 drivers/media/dvb-frontends/s5h1409.c if (reg & 0x1000) reg 769 drivers/media/dvb-frontends/s5h1409.c if (reg & 0x8000) reg 847 drivers/media/dvb-frontends/s5h1409.c u16 reg; reg 852 drivers/media/dvb-frontends/s5h1409.c reg = s5h1409_readreg(state, 0xf0) & 0xff; reg 853 drivers/media/dvb-frontends/s5h1409.c return s5h1409_qam64_lookup_snr(fe, snr, reg); reg 855 drivers/media/dvb-frontends/s5h1409.c reg = s5h1409_readreg(state, 0xf0) & 0xff; reg 856 drivers/media/dvb-frontends/s5h1409.c return s5h1409_qam256_lookup_snr(fe, snr, reg); reg 858 drivers/media/dvb-frontends/s5h1409.c reg = s5h1409_readreg(state, 0xf1) & 0x3ff; reg 859 drivers/media/dvb-frontends/s5h1409.c return s5h1409_vsb_lookup_snr(fe, snr, reg); reg 946 drivers/media/dvb-frontends/s5h1409.c u16 reg; reg 960 drivers/media/dvb-frontends/s5h1409.c reg = s5h1409_readreg(state, 0x04); reg 961 drivers/media/dvb-frontends/s5h1409.c if ((reg != 0x0066) && (reg != 0x007f)) reg 47 drivers/media/dvb-frontends/s5h1411.c u8 reg; reg 331 drivers/media/dvb-frontends/s5h1411.c u8 addr, u8 reg, u16 data) reg 334 drivers/media/dvb-frontends/s5h1411.c u8 buf[] = { reg, data >> 8, data & 0xff }; reg 342 drivers/media/dvb-frontends/s5h1411.c __func__, addr, reg, data, ret); reg 347 drivers/media/dvb-frontends/s5h1411.c static u16 s5h1411_readreg(struct s5h1411_state *state, u8 addr, u8 reg) reg 350 drivers/media/dvb-frontends/s5h1411.c u8 b0[] = { reg }; reg 620 drivers/media/dvb-frontends/s5h1411.c init_tab[i].reg, reg 653 drivers/media/dvb-frontends/s5h1411.c u16 reg; reg 663 drivers/media/dvb-frontends/s5h1411.c reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf0); reg 664 drivers/media/dvb-frontends/s5h1411.c if (reg & 0x10) /* QAM FEC Lock */ reg 666 drivers/media/dvb-frontends/s5h1411.c if (reg & 0x100) /* QAM EQ Lock */ reg 671 drivers/media/dvb-frontends/s5h1411.c reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf2); reg 672 drivers/media/dvb-frontends/s5h1411.c if (reg & 0x1000) /* FEC Lock */ reg 674 drivers/media/dvb-frontends/s5h1411.c if (reg & 0x2000) /* EQ Lock */ reg 677 drivers/media/dvb-frontends/s5h1411.c reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x53); reg 678 drivers/media/dvb-frontends/s5h1411.c if (reg & 0x1) /* AFC Lock */ reg 761 drivers/media/dvb-frontends/s5h1411.c u16 reg; reg 766 drivers/media/dvb-frontends/s5h1411.c reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1); reg 767 drivers/media/dvb-frontends/s5h1411.c return s5h1411_qam64_lookup_snr(fe, snr, reg); reg 769 drivers/media/dvb-frontends/s5h1411.c reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1); reg 770 drivers/media/dvb-frontends/s5h1411.c return s5h1411_qam256_lookup_snr(fe, snr, reg); reg 772 drivers/media/dvb-frontends/s5h1411.c reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, reg 774 drivers/media/dvb-frontends/s5h1411.c return s5h1411_vsb_lookup_snr(fe, snr, reg); reg 861 drivers/media/dvb-frontends/s5h1411.c u16 reg; reg 875 drivers/media/dvb-frontends/s5h1411.c reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x05); reg 876 drivers/media/dvb-frontends/s5h1411.c if (reg != 0x0066) reg 65 drivers/media/dvb-frontends/s5h1420.c static u8 s5h1420_readreg(struct s5h1420_state *state, u8 reg) reg 71 drivers/media/dvb-frontends/s5h1420.c { .addr = state->config->demod_address, .flags = 0, .buf = ®, .len = 1 }, reg 75 drivers/media/dvb-frontends/s5h1420.c b[0] = (reg - 1) & 0xff; reg 76 drivers/media/dvb-frontends/s5h1420.c b[1] = state->shadow[(reg - 1) & 0xff]; reg 96 drivers/media/dvb-frontends/s5h1420.c static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data) reg 98 drivers/media/dvb-frontends/s5h1420.c u8 buf[] = { reg, data }; reg 105 drivers/media/dvb-frontends/s5h1420.c dprintk("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data); reg 108 drivers/media/dvb-frontends/s5h1420.c state->shadow[reg] = data; reg 43 drivers/media/dvb-frontends/s5h1432.c u8 addr, u8 reg, u8 data) reg 46 drivers/media/dvb-frontends/s5h1432.c u8 buf[] = { reg, data }; reg 54 drivers/media/dvb-frontends/s5h1432.c __func__, addr, reg, data, ret); reg 59 drivers/media/dvb-frontends/s5h1432.c static u8 s5h1432_readreg(struct s5h1432_state *state, u8 addr, u8 reg) reg 62 drivers/media/dvb-frontends/s5h1432.c u8 b0[] = { reg }; reg 88 drivers/media/dvb-frontends/s5h1432.c u8 reg = 0; reg 91 drivers/media/dvb-frontends/s5h1432.c reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E); reg 92 drivers/media/dvb-frontends/s5h1432.c reg &= ~(0x0C); reg 95 drivers/media/dvb-frontends/s5h1432.c reg |= 0x08; reg 98 drivers/media/dvb-frontends/s5h1432.c reg |= 0x04; reg 101 drivers/media/dvb-frontends/s5h1432.c reg |= 0x00; reg 106 drivers/media/dvb-frontends/s5h1432.c s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg); reg 239 drivers/media/dvb-frontends/s5h1432.c u8 reg = 0; reg 277 drivers/media/dvb-frontends/s5h1432.c reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42); reg 278 drivers/media/dvb-frontends/s5h1432.c reg |= 0x80; reg 279 drivers/media/dvb-frontends/s5h1432.c s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg); reg 69 drivers/media/dvb-frontends/s921.c u8 reg; reg 199 drivers/media/dvb-frontends/s921.c u8 i2c_addr, int reg, int data) reg 201 drivers/media/dvb-frontends/s921.c u8 buf[] = { reg, data }; reg 210 drivers/media/dvb-frontends/s921.c __func__, rc, reg, data); reg 223 drivers/media/dvb-frontends/s921.c rc = s921_i2c_writereg(state, i2c_addr, rd[i].reg, rd[i].data); reg 230 drivers/media/dvb-frontends/s921.c static int s921_i2c_readreg(struct s921_state *state, u8 i2c_addr, u8 reg) reg 235 drivers/media/dvb-frontends/s921.c { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 }, reg 242 drivers/media/dvb-frontends/s921.c rc("%s: reg=0x%x (rcor=%d)\n", __func__, reg, rc); reg 249 drivers/media/dvb-frontends/s921.c #define s921_readreg(state, reg) \ reg 250 drivers/media/dvb-frontends/s921.c s921_i2c_readreg(state, state->config->demod_address, reg) reg 251 drivers/media/dvb-frontends/s921.c #define s921_writereg(state, reg, val) \ reg 252 drivers/media/dvb-frontends/s921.c s921_i2c_writereg(state, state->config->demod_address, reg, val) reg 59 drivers/media/dvb-frontends/si2165.c static int si2165_write(struct si2165_state *state, const u16 reg, reg 65 drivers/media/dvb-frontends/si2165.c reg, count, src); reg 67 drivers/media/dvb-frontends/si2165.c ret = regmap_bulk_write(state->regmap, reg, src, count); reg 76 drivers/media/dvb-frontends/si2165.c const u16 reg, u8 *val, const int count) reg 78 drivers/media/dvb-frontends/si2165.c int ret = regmap_bulk_read(state->regmap, reg, val, count); reg 82 drivers/media/dvb-frontends/si2165.c __func__, state->config.i2c_addr, reg, ret); reg 87 drivers/media/dvb-frontends/si2165.c reg, count, val); reg 93 drivers/media/dvb-frontends/si2165.c const u16 reg, u8 *val) reg 96 drivers/media/dvb-frontends/si2165.c int ret = regmap_read(state->regmap, reg, &val_tmp); reg 98 drivers/media/dvb-frontends/si2165.c dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%02x\n", reg, *val); reg 103 drivers/media/dvb-frontends/si2165.c const u16 reg, u16 *val) reg 107 drivers/media/dvb-frontends/si2165.c int ret = si2165_read(state, reg, buf, 2); reg 109 drivers/media/dvb-frontends/si2165.c dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%04x\n", reg, *val); reg 114 drivers/media/dvb-frontends/si2165.c const u16 reg, u32 *val) reg 118 drivers/media/dvb-frontends/si2165.c int ret = si2165_read(state, reg, buf, 3); reg 120 drivers/media/dvb-frontends/si2165.c dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%06x\n", reg, *val); reg 124 drivers/media/dvb-frontends/si2165.c static int si2165_writereg8(struct si2165_state *state, const u16 reg, u8 val) reg 126 drivers/media/dvb-frontends/si2165.c return regmap_write(state->regmap, reg, val); reg 129 drivers/media/dvb-frontends/si2165.c static int si2165_writereg16(struct si2165_state *state, const u16 reg, u16 val) reg 133 drivers/media/dvb-frontends/si2165.c return si2165_write(state, reg, buf, 2); reg 136 drivers/media/dvb-frontends/si2165.c static int si2165_writereg24(struct si2165_state *state, const u16 reg, u32 val) reg 140 drivers/media/dvb-frontends/si2165.c return si2165_write(state, reg, buf, 3); reg 143 drivers/media/dvb-frontends/si2165.c static int si2165_writereg32(struct si2165_state *state, const u16 reg, u32 val) reg 151 drivers/media/dvb-frontends/si2165.c return si2165_write(state, reg, buf, 4); reg 154 drivers/media/dvb-frontends/si2165.c static int si2165_writereg_mask8(struct si2165_state *state, const u16 reg, reg 159 drivers/media/dvb-frontends/si2165.c int ret = si2165_readreg8(state, reg, &tmp); reg 168 drivers/media/dvb-frontends/si2165.c return si2165_writereg8(state, reg, val); reg 171 drivers/media/dvb-frontends/si2165.c #define REG16(reg, val) \ reg 172 drivers/media/dvb-frontends/si2165.c { (reg), (val) & 0xff }, \ reg 173 drivers/media/dvb-frontends/si2165.c { (reg) + 1, (val) >> 8 & 0xff } reg 175 drivers/media/dvb-frontends/si2165.c u16 reg; reg 187 drivers/media/dvb-frontends/si2165.c ret = si2165_writereg8(state, regs[i].reg, regs[i].val); reg 249 drivers/media/dvb-frontends/si21xx.c static int si21_writereg(struct si21xx_state *state, u8 reg, u8 data) reg 252 drivers/media/dvb-frontends/si21xx.c u8 buf[] = { reg, data }; reg 264 drivers/media/dvb-frontends/si21xx.c __func__, reg, data, ret); reg 279 drivers/media/dvb-frontends/si21xx.c static u8 si21_readreg(struct si21xx_state *state, u8 reg) reg 282 drivers/media/dvb-frontends/si21xx.c u8 b0[] = { reg }; reg 302 drivers/media/dvb-frontends/si21xx.c __func__, reg, ret); reg 651 drivers/media/dvb-frontends/si21xx.c u8 reg, regs[3]; reg 666 drivers/media/dvb-frontends/si21xx.c status |= si21_readregs(state, ACQ_CTRL_REG_2, ®, 0x01); reg 667 drivers/media/dvb-frontends/si21xx.c reg &= ~start_acq; reg 668 drivers/media/dvb-frontends/si21xx.c status |= si21_writeregs(state, ACQ_CTRL_REG_2, ®, 0x01); reg 678 drivers/media/dvb-frontends/si21xx.c reg = 0x56; reg 680 drivers/media/dvb-frontends/si21xx.c LSA_CTRL_REG_1, ®, 1); reg 681 drivers/media/dvb-frontends/si21xx.c reg = 0x05; reg 683 drivers/media/dvb-frontends/si21xx.c BLIND_SCAN_CTRL_REG, ®, 1); reg 28 drivers/media/dvb-frontends/si21xx.h static inline int si21xx_writeregister(struct dvb_frontend *fe, u8 reg, u8 val) reg 31 drivers/media/dvb-frontends/si21xx.h u8 buf[] = {reg, val}; reg 17 drivers/media/dvb-frontends/sp2.c static int sp2_read_i2c(struct sp2 *s, u8 reg, u8 *buf, int len) reg 26 drivers/media/dvb-frontends/sp2.c .buf = ®, reg 40 drivers/media/dvb-frontends/sp2.c reg, ret); reg 48 drivers/media/dvb-frontends/sp2.c client->addr, reg, buf[0]); reg 53 drivers/media/dvb-frontends/sp2.c static int sp2_write_i2c(struct sp2 *s, u8 reg, u8 *buf, int len) reg 68 drivers/media/dvb-frontends/sp2.c reg, len); reg 72 drivers/media/dvb-frontends/sp2.c buffer[0] = reg; reg 79 drivers/media/dvb-frontends/sp2.c reg, ret); reg 87 drivers/media/dvb-frontends/sp2.c client->addr, reg, len, buf); reg 53 drivers/media/dvb-frontends/sp8870.c static int sp8870_writereg (struct sp8870_state* state, u16 reg, u16 data) reg 55 drivers/media/dvb-frontends/sp8870.c u8 buf [] = { reg >> 8, reg & 0xff, data >> 8, data & 0xff }; reg 60 drivers/media/dvb-frontends/sp8870.c dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data); reg 67 drivers/media/dvb-frontends/sp8870.c static int sp8870_readreg (struct sp8870_state* state, u16 reg) reg 70 drivers/media/dvb-frontends/sp8870.c u8 b0 [] = { reg >> 8 , reg & 0xff }; reg 54 drivers/media/dvb-frontends/sp887x.c static int sp887x_writereg (struct sp887x_state* state, u16 reg, u16 data) reg 56 drivers/media/dvb-frontends/sp887x.c u8 b0 [] = { reg >> 8 , reg & 0xff, data >> 8, data & 0xff }; reg 64 drivers/media/dvb-frontends/sp887x.c if (!(reg == 0xf1a && data == 0x000 && reg 68 drivers/media/dvb-frontends/sp887x.c __func__, reg & 0xffff, data & 0xffff, ret); reg 76 drivers/media/dvb-frontends/sp887x.c static int sp887x_readreg (struct sp887x_state* state, u16 reg) reg 78 drivers/media/dvb-frontends/sp887x.c u8 b0 [] = { reg >> 8 , reg & 0xff }; reg 166 drivers/media/dvb-frontends/stb0899_algo.c u8 reg; reg 172 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_TLIR); reg 173 drivers/media/dvb-frontends/stb0899_algo.c lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg); reg 241 drivers/media/dvb-frontends/stb0899_algo.c u8 reg; reg 245 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_CFD); reg 246 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(CFD_ON, reg, 1); reg 247 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_reg(state, STB0899_CFD, reg); reg 249 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_DSTATUS); reg 250 drivers/media/dvb-frontends/stb0899_algo.c dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg); reg 251 drivers/media/dvb-frontends/stb0899_algo.c if (STB0899_GETFIELD(CARRIER_FOUND, reg)) { reg 273 drivers/media/dvb-frontends/stb0899_algo.c u8 reg; reg 279 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_CFD); reg 280 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(CFD_ON, reg, 1); reg 281 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_reg(state, STB0899_CFD, reg); reg 294 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_CFD); reg 295 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(CFD_ON, reg, 1); reg 296 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_reg(state, STB0899_CFD, reg); reg 328 drivers/media/dvb-frontends/stb0899_algo.c u8 reg; reg 333 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_TSTRES); reg 334 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(FRESACS, reg, 1); reg 335 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_reg(state, STB0899_TSTRES, reg); reg 337 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_TSTRES); reg 338 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(FRESACS, reg, 0); reg 339 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_reg(state, STB0899_TSTRES, reg); reg 356 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_VSTATUS); reg 357 drivers/media/dvb-frontends/stb0899_algo.c lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg); reg 358 drivers/media/dvb-frontends/stb0899_algo.c loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg); reg 381 drivers/media/dvb-frontends/stb0899_algo.c u8 reg; reg 400 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_CFD); reg 401 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(CFD_ON, reg, 1); reg 402 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_reg(state, STB0899_CFD, reg); reg 419 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_IQSWAP); reg 420 drivers/media/dvb-frontends/stb0899_algo.c if (STB0899_GETFIELD(SYM, reg)) reg 495 drivers/media/dvb-frontends/stb0899_algo.c u8 bclc, reg; reg 562 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_TSTRES); reg 563 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(FRESRS, reg, 1); reg 564 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_reg(state, STB0899_TSTRES, reg); reg 570 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_DEMAPVIT); reg 571 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60); reg 572 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_reg(state, STB0899_DEMAPVIT, reg); reg 584 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_CFD); reg 585 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(CFD_ON, reg, 1); reg 586 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_reg(state, STB0899_CFD, reg); reg 639 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_PLPARM); reg 640 drivers/media/dvb-frontends/stb0899_algo.c internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg); reg 670 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_BCLC); reg 674 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]); reg 675 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_reg(state, STB0899_BCLC, reg); reg 679 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]); reg 680 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_reg(state, STB0899_BCLC, reg); reg 684 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]); reg 685 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_reg(state, STB0899_BCLC, reg); reg 689 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]); reg 690 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_reg(state, STB0899_BCLC, reg); reg 699 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]); reg 700 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_reg(state, STB0899_BCLC, reg); reg 707 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_TSTRES); reg 708 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(FRESRS, reg, 0); reg 709 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_reg(state, STB0899_TSTRES, reg); reg 712 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_CFD); reg 713 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(CFD_ON, reg, 0); reg 714 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_reg(state, STB0899_CFD, reg); reg 730 drivers/media/dvb-frontends/stb0899_algo.c u32 uwp1, uwp2, uwp3, reg; reg 751 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO); reg 752 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout); reg 753 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg); reg 762 drivers/media/dvb-frontends/stb0899_algo.c u32 reg; reg 764 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1); reg 765 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1); reg 766 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg); reg 842 drivers/media/dvb-frontends/stb0899_algo.c u32 correction, freq_adj, band_lim, decim_cntrl, reg; reg 878 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL); reg 879 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction); reg 880 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg); reg 900 drivers/media/dvb-frontends/stb0899_algo.c u32 reg; reg 935 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN); reg 936 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft); reg 937 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0); reg 938 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft); reg 939 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1); reg 940 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft); reg 941 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg); reg 954 drivers/media/dvb-frontends/stb0899_algo.c u32 reg; reg 958 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ); reg 959 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq); reg 960 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg); reg 971 drivers/media/dvb-frontends/stb0899_algo.c u32 range, reg; reg 1002 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2); reg 1003 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(ZIGZAG, reg, 1); reg 1004 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps); reg 1005 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size); reg 1006 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg); reg 1015 drivers/media/dvb-frontends/stb0899_algo.c u32 reg; reg 1018 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL); reg 1019 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1); reg 1020 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1); reg 1021 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg); reg 1038 drivers/media/dvb-frontends/stb0899_algo.c u32 reg = 0; reg 1041 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1); reg 1042 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg); reg 1055 drivers/media/dvb-frontends/stb0899_algo.c reg = 0; reg 1056 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0); reg 1057 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg); reg 1069 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL); reg 1070 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0); reg 1071 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0); reg 1072 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05); reg 1073 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01); reg 1074 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg); reg 1087 drivers/media/dvb-frontends/stb0899_algo.c u32 reg; reg 1090 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS); reg 1091 drivers/media/dvb-frontends/stb0899_algo.c dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg); reg 1092 drivers/media/dvb-frontends/stb0899_algo.c if (STB0899_GETFIELD(IF_AGC_LOCK, reg)) reg 1094 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2); reg 1095 drivers/media/dvb-frontends/stb0899_algo.c dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg); reg 1096 drivers/media/dvb-frontends/stb0899_algo.c uwp = STB0899_GETFIELD(UWP_LOCK, reg); reg 1097 drivers/media/dvb-frontends/stb0899_algo.c csm = STB0899_GETFIELD(CSM_LOCK, reg); reg 1121 drivers/media/dvb-frontends/stb0899_algo.c u8 reg; reg 1124 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1); reg 1125 drivers/media/dvb-frontends/stb0899_algo.c dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg); reg 1126 drivers/media/dvb-frontends/stb0899_algo.c lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg); reg 1273 drivers/media/dvb-frontends/stb0899_algo.c u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg; reg 1281 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL); reg 1282 drivers/media/dvb-frontends/stb0899_algo.c decimRate = STB0899_GETFIELD(DECIM_RATE, reg); reg 1309 drivers/media/dvb-frontends/stb0899_algo.c u32 reg, csm1; reg 1335 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_TSTRES); reg 1336 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(FRESRS, reg, 1); reg 1337 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_reg(state, STB0899_TSTRES, reg); reg 1352 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL); reg 1353 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 4); reg 1354 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32); reg 1355 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg); reg 1357 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2); reg 1358 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0); reg 1359 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg); reg 1364 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2); reg 1367 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0); reg 1370 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1); reg 1373 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg); reg 1391 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ); reg 1392 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq); reg 1393 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg); reg 1401 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2); reg 1402 drivers/media/dvb-frontends/stb0899_algo.c iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg); reg 1404 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum); reg 1405 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg); reg 1421 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ); reg 1422 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq); reg 1423 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg); reg 1437 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2); reg 1438 drivers/media/dvb-frontends/stb0899_algo.c modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2; reg 1439 drivers/media/dvb-frontends/stb0899_algo.c pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01; reg 1468 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL); reg 1469 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1); reg 1470 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg); reg 1474 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL); reg 1475 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02); reg 1476 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg); reg 1487 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2); reg 1488 drivers/media/dvb-frontends/stb0899_algo.c if (STB0899_GETFIELD(SPECTRUM_INVERT, reg)) reg 1496 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2); reg 1497 drivers/media/dvb-frontends/stb0899_algo.c internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2; reg 1498 drivers/media/dvb-frontends/stb0899_algo.c internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01; reg 1499 drivers/media/dvb-frontends/stb0899_algo.c internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01; reg 1502 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL); reg 1503 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 3); reg 1507 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16); reg 1509 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg); reg 1511 drivers/media/dvb-frontends/stb0899_algo.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2); reg 1512 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7); reg 1513 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg); reg 1517 drivers/media/dvb-frontends/stb0899_algo.c reg = stb0899_read_reg(state, STB0899_TSTRES); reg 1518 drivers/media/dvb-frontends/stb0899_algo.c STB0899_SETFIELD_VAL(FRESRS, reg, 0); reg 1519 drivers/media/dvb-frontends/stb0899_algo.c stb0899_write_reg(state, STB0899_TSTRES, reg); reg 213 drivers/media/dvb-frontends/stb0899_drv.c static int _stb0899_read_reg(struct stb0899_state *state, unsigned int reg) reg 217 drivers/media/dvb-frontends/stb0899_drv.c u8 b0[] = { reg >> 8, reg & 0xff }; reg 239 drivers/media/dvb-frontends/stb0899_drv.c reg, ret); reg 245 drivers/media/dvb-frontends/stb0899_drv.c reg, buf); reg 250 drivers/media/dvb-frontends/stb0899_drv.c int stb0899_read_reg(struct stb0899_state *state, unsigned int reg) reg 254 drivers/media/dvb-frontends/stb0899_drv.c result = _stb0899_read_reg(state, reg); reg 260 drivers/media/dvb-frontends/stb0899_drv.c if ((reg != 0xf2ff) && (reg != 0xf6ff) && reg 261 drivers/media/dvb-frontends/stb0899_drv.c (((reg & 0xff00) == 0xf200) || ((reg & 0xff00) == 0xf600))) reg 262 drivers/media/dvb-frontends/stb0899_drv.c _stb0899_read_reg(state, (reg | 0x00ff)); reg 440 drivers/media/dvb-frontends/stb0899_drv.c int stb0899_read_regs(struct stb0899_state *state, unsigned int reg, u8 *buf, u32 count) reg 444 drivers/media/dvb-frontends/stb0899_drv.c u8 b0[] = { reg >> 8, reg & 0xff }; reg 464 drivers/media/dvb-frontends/stb0899_drv.c __func__, reg, count, status); reg 472 drivers/media/dvb-frontends/stb0899_drv.c if ((reg != 0xf2ff) && (reg != 0xf6ff) && reg 473 drivers/media/dvb-frontends/stb0899_drv.c (((reg & 0xff00) == 0xf200) || ((reg & 0xff00) == 0xf600))) reg 474 drivers/media/dvb-frontends/stb0899_drv.c _stb0899_read_reg(state, (reg | 0x00ff)); reg 477 drivers/media/dvb-frontends/stb0899_drv.c "%s [0x%04x]: %*ph", __func__, reg, count, buf); reg 484 drivers/media/dvb-frontends/stb0899_drv.c int stb0899_write_regs(struct stb0899_state *state, unsigned int reg, u8 *data, u32 count) reg 498 drivers/media/dvb-frontends/stb0899_drv.c KBUILD_MODNAME, reg, count); reg 502 drivers/media/dvb-frontends/stb0899_drv.c buf[0] = reg >> 8; reg 503 drivers/media/dvb-frontends/stb0899_drv.c buf[1] = reg & 0xff; reg 507 drivers/media/dvb-frontends/stb0899_drv.c "%s [0x%04x]: %*ph", __func__, reg, count, data); reg 515 drivers/media/dvb-frontends/stb0899_drv.c if ((((reg & 0xff00) == 0xf200) || ((reg & 0xff00) == 0xf600))) reg 516 drivers/media/dvb-frontends/stb0899_drv.c stb0899_read_reg(state, (reg | 0x00ff)); reg 521 drivers/media/dvb-frontends/stb0899_drv.c reg, data[0], count, ret); reg 528 drivers/media/dvb-frontends/stb0899_drv.c int stb0899_write_reg(struct stb0899_state *state, unsigned int reg, u8 data) reg 531 drivers/media/dvb-frontends/stb0899_drv.c return stb0899_write_regs(state, reg, &tmp, 1); reg 633 drivers/media/dvb-frontends/stb0899_drv.c u32 reg; reg 649 drivers/media/dvb-frontends/stb0899_drv.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL); reg 650 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(IF_GAIN_INIT, reg, internal->agc_gain); reg 651 drivers/media/dvb-frontends/stb0899_drv.c stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg); reg 653 drivers/media/dvb-frontends/stb0899_drv.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, RRC_ALPHA); reg 654 drivers/media/dvb-frontends/stb0899_drv.c internal->rrc_alpha = STB0899_GETFIELD(RRC_ALPHA, reg); reg 670 drivers/media/dvb-frontends/stb0899_drv.c u8 reg = 0; reg 674 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_DISSTATUS); reg 675 drivers/media/dvb-frontends/stb0899_drv.c if (!STB0899_GETFIELD(FIFOFULL, reg)) reg 689 drivers/media/dvb-frontends/stb0899_drv.c u8 reg, i; reg 695 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_DISCNTRL1); reg 696 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 1); reg 697 drivers/media/dvb-frontends/stb0899_drv.c stb0899_write_reg(state, STB0899_DISCNTRL1, reg); reg 705 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_DISCNTRL1); reg 706 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0); reg 707 drivers/media/dvb-frontends/stb0899_drv.c stb0899_write_reg(state, STB0899_DISCNTRL1, reg); reg 714 drivers/media/dvb-frontends/stb0899_drv.c u8 reg = 0; reg 717 drivers/media/dvb-frontends/stb0899_drv.c while (!STB0899_GETFIELD(RXEND, reg)) { reg 718 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_DISRX_ST0); reg 732 drivers/media/dvb-frontends/stb0899_drv.c u8 reg, length = 0, i; reg 738 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_DISRX_ST0); reg 739 drivers/media/dvb-frontends/stb0899_drv.c if (STB0899_GETFIELD(RXEND, reg)) { reg 741 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_DISRX_ST1); reg 742 drivers/media/dvb-frontends/stb0899_drv.c length = STB0899_GETFIELD(FIFOBYTENBR, reg); reg 763 drivers/media/dvb-frontends/stb0899_drv.c u8 reg = 0; reg 766 drivers/media/dvb-frontends/stb0899_drv.c while (!STB0899_GETFIELD(TXIDLE, reg)) { reg 767 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_DISSTATUS); reg 781 drivers/media/dvb-frontends/stb0899_drv.c u8 reg, old_state; reg 787 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_DISCNTRL1); reg 788 drivers/media/dvb-frontends/stb0899_drv.c old_state = reg; reg 790 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(DISEQCMODE, reg, 0x03); reg 791 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0x01); reg 792 drivers/media/dvb-frontends/stb0899_drv.c stb0899_write_reg(state, STB0899_DISCNTRL1, reg); reg 803 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_DISCNTRL1); reg 804 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0x00); reg 805 drivers/media/dvb-frontends/stb0899_drv.c stb0899_write_reg(state, STB0899_DISCNTRL1, reg); reg 821 drivers/media/dvb-frontends/stb0899_drv.c u8 f22_tx, reg; reg 824 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_DISCNTRL2); reg 825 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(ONECHIP_TRX, reg, 0); reg 826 drivers/media/dvb-frontends/stb0899_drv.c stb0899_write_reg(state, STB0899_DISCNTRL2, reg); reg 829 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_DISCNTRL1); reg 830 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(DISEQCRESET, reg, 1); reg 831 drivers/media/dvb-frontends/stb0899_drv.c stb0899_write_reg(state, STB0899_DISCNTRL1, reg); reg 833 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_DISCNTRL1); reg 834 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(DISEQCRESET, reg, 0); reg 835 drivers/media/dvb-frontends/stb0899_drv.c stb0899_write_reg(state, STB0899_DISCNTRL1, reg); reg 954 drivers/media/dvb-frontends/stb0899_drv.c u32 reg; reg 960 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_VSTATUS); reg 961 drivers/media/dvb-frontends/stb0899_drv.c if (STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg)) { reg 963 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_AGCIQIN); reg 964 drivers/media/dvb-frontends/stb0899_drv.c val = (s32)(s8)STB0899_GETFIELD(AGCIQVALUE, reg); reg 975 drivers/media/dvb-frontends/stb0899_drv.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_GAIN); reg 976 drivers/media/dvb-frontends/stb0899_drv.c val = STB0899_GETFIELD(IF_AGC_GAIN, reg); reg 999 drivers/media/dvb-frontends/stb0899_drv.c u32 reg; reg 1002 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_VSTATUS); reg 1007 drivers/media/dvb-frontends/stb0899_drv.c if (STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg)) { reg 1020 drivers/media/dvb-frontends/stb0899_drv.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1); reg 1021 drivers/media/dvb-frontends/stb0899_drv.c quant = STB0899_GETFIELD(UWP_ESN0_QUANT, reg); reg 1022 drivers/media/dvb-frontends/stb0899_drv.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2); reg 1023 drivers/media/dvb-frontends/stb0899_drv.c est = STB0899_GETFIELD(ESN0_EST, reg); reg 1053 drivers/media/dvb-frontends/stb0899_drv.c u8 reg; reg 1061 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_VSTATUS); reg 1062 drivers/media/dvb-frontends/stb0899_drv.c if (STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg)) { reg 1066 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_PLPARM); reg 1067 drivers/media/dvb-frontends/stb0899_drv.c if (STB0899_GETFIELD(VITCURPUN, reg)) { reg 1079 drivers/media/dvb-frontends/stb0899_drv.c reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2); reg 1080 drivers/media/dvb-frontends/stb0899_drv.c if (STB0899_GETFIELD(UWP_LOCK, reg) && STB0899_GETFIELD(CSM_LOCK, reg)) { reg 1085 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1); reg 1086 drivers/media/dvb-frontends/stb0899_drv.c if (STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg)) { reg 1092 drivers/media/dvb-frontends/stb0899_drv.c if (STB0899_GETFIELD(CONTINUOUS_STREAM, reg)) { reg 1097 drivers/media/dvb-frontends/stb0899_drv.c if (STB0899_GETFIELD(ACCEPTED_STREAM, reg)) { reg 1197 drivers/media/dvb-frontends/stb0899_drv.c u8 div, reg; reg 1208 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_ACRPRESC); reg 1209 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(ACRPRESC, reg, 0x03); reg 1210 drivers/media/dvb-frontends/stb0899_drv.c stb0899_write_reg(state, STB0899_ACRPRESC, reg); reg 1292 drivers/media/dvb-frontends/stb0899_drv.c u8 reg; reg 1302 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_FECM); reg 1303 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(FECM_RSVD0, reg, 0); reg 1304 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(FECM_VITERBI_ON, reg, 1); reg 1305 drivers/media/dvb-frontends/stb0899_drv.c stb0899_write_reg(state, STB0899_FECM, reg); reg 1312 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_TSTRES); reg 1313 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(FRESLDPC, reg, 1); reg 1314 drivers/media/dvb-frontends/stb0899_drv.c stb0899_write_reg(state, STB0899_TSTRES, reg); reg 1330 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_FECM); reg 1331 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(FECM_RSVD0, reg, 0); reg 1332 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(FECM_VITERBI_ON, reg, 0); reg 1333 drivers/media/dvb-frontends/stb0899_drv.c stb0899_write_reg(state, STB0899_FECM, reg); reg 1340 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_TSTRES); reg 1341 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(FRESLDPC, reg, 0); reg 1342 drivers/media/dvb-frontends/stb0899_drv.c stb0899_write_reg(state, STB0899_TSTRES, reg); reg 1358 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_FECM); reg 1359 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(FECM_RSVD0, reg, 1); reg 1360 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(FECM_VITERBI_ON, reg, 1); reg 1361 drivers/media/dvb-frontends/stb0899_drv.c stb0899_write_reg(state, STB0899_FECM, reg); reg 1367 drivers/media/dvb-frontends/stb0899_drv.c reg = stb0899_read_reg(state, STB0899_TSTRES); reg 1368 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(FRESLDPC, reg, 1); reg 1369 drivers/media/dvb-frontends/stb0899_drv.c stb0899_write_reg(state, STB0899_TSTRES, reg); reg 1400 drivers/media/dvb-frontends/stb0899_drv.c u32 reg; reg 1410 drivers/media/dvb-frontends/stb0899_drv.c reg = STB0899_READ_S2REG(STB0899_S2FEC, MAX_ITER); reg 1411 drivers/media/dvb-frontends/stb0899_drv.c STB0899_SETFIELD_VAL(MAX_ITERATIONS, reg, iter_scale); reg 1412 drivers/media/dvb-frontends/stb0899_drv.c stb0899_write_s2reg(state, STB0899_S2FEC, STB0899_BASE_MAX_ITER, STB0899_OFF0_MAX_ITER, reg); reg 215 drivers/media/dvb-frontends/stb0899_priv.h unsigned int reg); reg 223 drivers/media/dvb-frontends/stb0899_priv.h unsigned int reg, u8 *buf, reg 227 drivers/media/dvb-frontends/stb0899_priv.h unsigned int reg, u8 *data, reg 231 drivers/media/dvb-frontends/stb0899_priv.h unsigned int reg, reg 49 drivers/media/dvb-frontends/stb6100.c u8 reg; reg 148 drivers/media/dvb-frontends/stb6100.c static int stb6100_read_reg(struct stb6100_state *state, u8 reg) reg 153 drivers/media/dvb-frontends/stb6100.c .addr = state->config->tuner_address + reg, reg 161 drivers/media/dvb-frontends/stb6100.c if (unlikely(reg >= STB6100_NUMREGS)) { reg 162 drivers/media/dvb-frontends/stb6100.c dprintk(verbose, FE_ERROR, 1, "Invalid register offset 0x%x", reg); reg 167 drivers/media/dvb-frontends/stb6100.c dprintk(verbose, FE_DEBUG, 1, " %s: 0x%02x", stb6100_regnames[reg], regs[0]); reg 215 drivers/media/dvb-frontends/stb6100.c static int stb6100_write_reg(struct stb6100_state *state, u8 reg, u8 data) reg 219 drivers/media/dvb-frontends/stb6100.c if (unlikely(reg >= STB6100_NUMREGS)) { reg 220 drivers/media/dvb-frontends/stb6100.c dprintk(verbose, FE_ERROR, 1, "Invalid register offset 0x%x", reg); reg 223 drivers/media/dvb-frontends/stb6100.c tmp = (tmp & stb6100_template[reg].mask) | stb6100_template[reg].set; reg 224 drivers/media/dvb-frontends/stb6100.c return stb6100_write_reg_range(state, &tmp, reg, 1); reg 374 drivers/media/dvb-frontends/stb6100.c regs[STB6100_VCO] = (regs[STB6100_VCO] & ~STB6100_VCO_OSM) | ptr->reg; reg 437 drivers/media/dvb-frontends/stb6100.c ptr->reg, fvco, nint, nfrac); reg 51 drivers/media/dvb-frontends/stv0288.c static int stv0288_writeregI(struct stv0288_state *state, u8 reg, u8 data) reg 54 drivers/media/dvb-frontends/stv0288.c u8 buf[] = { reg, data }; reg 66 drivers/media/dvb-frontends/stv0288.c __func__, reg, data, ret); reg 81 drivers/media/dvb-frontends/stv0288.c static u8 stv0288_readreg(struct stv0288_state *state, u8 reg) reg 84 drivers/media/dvb-frontends/stv0288.c u8 b0[] = { reg }; reg 104 drivers/media/dvb-frontends/stv0288.c __func__, reg, ret); reg 328 drivers/media/dvb-frontends/stv0288.c u8 reg; reg 343 drivers/media/dvb-frontends/stv0288.c reg = state->config->inittab[i]; reg 345 drivers/media/dvb-frontends/stv0288.c if (reg == 0xff && val == 0xff) reg 347 drivers/media/dvb-frontends/stv0288.c stv0288_writeregI(state, reg, val); reg 445 drivers/media/dvb-frontends/stv0288.c u8 reg, time_out = 0; reg 473 drivers/media/dvb-frontends/stv0288.c reg = stv0288_readreg(state, 0x24); reg 474 drivers/media/dvb-frontends/stv0288.c if (reg & 0x8) reg 476 drivers/media/dvb-frontends/stv0288.c if (reg & 0x80) { reg 45 drivers/media/dvb-frontends/stv0288.h static inline int stv0288_writereg(struct dvb_frontend *fe, u8 reg, u8 val) reg 48 drivers/media/dvb-frontends/stv0288.h u8 buf[] = { reg, val }; reg 39 drivers/media/dvb-frontends/stv0297.c static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data) reg 42 drivers/media/dvb-frontends/stv0297.c u8 buf[] = { reg, data }; reg 49 drivers/media/dvb-frontends/stv0297.c __func__, reg, data, ret); reg 54 drivers/media/dvb-frontends/stv0297.c static int stv0297_readreg(struct stv0297_state *state, u8 reg) reg 57 drivers/media/dvb-frontends/stv0297.c u8 b0[] = { reg }; reg 66 drivers/media/dvb-frontends/stv0297.c dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret); reg 70 drivers/media/dvb-frontends/stv0297.c dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret); reg 75 drivers/media/dvb-frontends/stv0297.c dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg, ret); reg 83 drivers/media/dvb-frontends/stv0297.c static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data) reg 87 drivers/media/dvb-frontends/stv0297.c val = stv0297_readreg(state, reg); reg 90 drivers/media/dvb-frontends/stv0297.c stv0297_writereg(state, reg, val); reg 70 drivers/media/dvb-frontends/stv0299.c static int stv0299_writeregI (struct stv0299_state* state, u8 reg, u8 data) reg 73 drivers/media/dvb-frontends/stv0299.c u8 buf [] = { reg, data }; reg 80 drivers/media/dvb-frontends/stv0299.c __func__, reg, data, ret); reg 95 drivers/media/dvb-frontends/stv0299.c static u8 stv0299_readreg (struct stv0299_state* state, u8 reg) reg 98 drivers/media/dvb-frontends/stv0299.c u8 b0 [] = { reg }; reg 107 drivers/media/dvb-frontends/stv0299.c __func__, reg, ret); reg 449 drivers/media/dvb-frontends/stv0299.c u8 reg; reg 458 drivers/media/dvb-frontends/stv0299.c reg = state->config->inittab[i]; reg 460 drivers/media/dvb-frontends/stv0299.c if (reg == 0xff && val == 0xff) reg 462 drivers/media/dvb-frontends/stv0299.c if (reg == 0x0c && state->config->op0_off) reg 464 drivers/media/dvb-frontends/stv0299.c if (reg == 0x2) reg 466 drivers/media/dvb-frontends/stv0299.c stv0299_writeregI(state, reg, val); reg 98 drivers/media/dvb-frontends/stv0299.h static inline int stv0299_writereg(struct dvb_frontend *fe, u8 reg, u8 val) { reg 100 drivers/media/dvb-frontends/stv0299.h u8 buf[] = {reg, val}; reg 122 drivers/media/dvb-frontends/stv0367.c int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len) reg 136 drivers/media/dvb-frontends/stv0367.c KBUILD_MODNAME, reg, len); reg 141 drivers/media/dvb-frontends/stv0367.c buf[0] = MSB(reg); reg 142 drivers/media/dvb-frontends/stv0367.c buf[1] = LSB(reg); reg 147 drivers/media/dvb-frontends/stv0367.c state->config->demod_address, reg, buf[2]); reg 152 drivers/media/dvb-frontends/stv0367.c __func__, state->config->demod_address, reg, buf[2]); reg 157 drivers/media/dvb-frontends/stv0367.c static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data) reg 161 drivers/media/dvb-frontends/stv0367.c return stv0367_writeregs(state, reg, &tmp, 1); reg 164 drivers/media/dvb-frontends/stv0367.c static u8 stv0367_readreg(struct stv0367_state *state, u16 reg) reg 183 drivers/media/dvb-frontends/stv0367.c b0[0] = MSB(reg); reg 184 drivers/media/dvb-frontends/stv0367.c b0[1] = LSB(reg); reg 189 drivers/media/dvb-frontends/stv0367.c __func__, state->config->demod_address, reg, b1[0]); reg 193 drivers/media/dvb-frontends/stv0367.c state->config->demod_address, reg, b1[0]); reg 214 drivers/media/dvb-frontends/stv0367.c u8 reg, mask, pos; reg 216 drivers/media/dvb-frontends/stv0367.c reg = stv0367_readreg(state, (label >> 16) & 0xffff); reg 221 drivers/media/dvb-frontends/stv0367.c reg = (reg & (~mask)) | val; reg 222 drivers/media/dvb-frontends/stv0367.c stv0367_writereg(state, (label >> 16) & 0xffff, reg); reg 226 drivers/media/dvb-frontends/stv0367.c static void stv0367_setbits(u8 *reg, u32 label, u8 val) reg 234 drivers/media/dvb-frontends/stv0367.c (*reg) = ((*reg) & (~mask)) | val; reg 251 drivers/media/dvb-frontends/stv0367.c static u8 stv0367_getbits(u8 reg, u32 label) reg 257 drivers/media/dvb-frontends/stv0367.c return (reg & mask) >> pos; reg 139 drivers/media/dvb-frontends/stv0900_core.c u8 stv0900_read_reg(struct stv0900_internal *intp, u16 reg) reg 142 drivers/media/dvb-frontends/stv0900_core.c u8 b0[] = { MSB(reg), LSB(reg) }; reg 161 drivers/media/dvb-frontends/stv0900_core.c __func__, ret, reg); reg 182 drivers/media/dvb-frontends/stv0900_core.c u8 reg, mask, pos; reg 184 drivers/media/dvb-frontends/stv0900_core.c reg = stv0900_read_reg(intp, (label >> 16) & 0xffff); reg 189 drivers/media/dvb-frontends/stv0900_core.c reg = (reg & (~mask)) | val; reg 190 drivers/media/dvb-frontends/stv0900_core.c stv0900_write_reg(intp, (label >> 16) & 0xffff, reg); reg 683 drivers/media/dvb-frontends/stv090x.c static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg) reg 688 drivers/media/dvb-frontends/stv090x.c u8 b0[] = { reg >> 8, reg & 0xff }; reg 701 drivers/media/dvb-frontends/stv090x.c reg, ret); reg 707 drivers/media/dvb-frontends/stv090x.c reg, buf); reg 712 drivers/media/dvb-frontends/stv090x.c static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count) reg 722 drivers/media/dvb-frontends/stv090x.c KBUILD_MODNAME, reg, count); reg 726 drivers/media/dvb-frontends/stv090x.c buf[0] = reg >> 8; reg 727 drivers/media/dvb-frontends/stv090x.c buf[1] = reg & 0xff; reg 731 drivers/media/dvb-frontends/stv090x.c __func__, reg, count, data); reg 737 drivers/media/dvb-frontends/stv090x.c reg, data[0], count, ret); reg 744 drivers/media/dvb-frontends/stv090x.c static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data) reg 748 drivers/media/dvb-frontends/stv090x.c return stv090x_write_regs(state, reg, &tmp, 1); reg 753 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 771 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, I2CRPT); reg 774 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1); reg 775 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) reg 780 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0); reg 781 drivers/media/dvb-frontends/stv090x.c if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0) reg 1199 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 1204 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_STOPCLK2); reg 1205 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable); reg 1206 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) reg 1213 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_STOPCLK2); reg 1214 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable); reg 1215 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) reg 1267 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 1272 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDCFGMD); reg 1273 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); reg 1274 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); reg 1275 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) reg 1297 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDCFGMD); reg 1298 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); reg 1299 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); reg 1300 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) reg 1302 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); reg 1303 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); reg 1304 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) reg 1345 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDCFGMD); reg 1346 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); reg 1347 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); reg 1348 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) reg 1350 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); reg 1351 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); reg 1352 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) reg 1399 drivers/media/dvb-frontends/stv090x.c u32 reg, freq_abs; reg 1403 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDISTATE); reg 1404 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); reg 1405 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) reg 1509 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDCFGMD); reg 1510 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0); reg 1511 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); reg 1512 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) reg 1514 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDCFG2); reg 1515 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0); reg 1516 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0) reg 1587 drivers/media/dvb-frontends/stv090x.c u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg; reg 1592 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDCFGMD); reg 1593 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0); reg 1594 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); reg 1595 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) reg 1684 drivers/media/dvb-frontends/stv090x.c u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg; reg 1692 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDISTATE); reg 1693 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */ reg 1694 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0) reg 1704 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDCFGMD); reg 1705 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1); reg 1706 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0); reg 1707 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) reg 1774 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DSTATUS); reg 1775 drivers/media/dvb-frontends/stv090x.c if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2) reg 1816 drivers/media/dvb-frontends/stv090x.c if (state->config->tuner_get_status(fe, ®) < 0) reg 1820 drivers/media/dvb-frontends/stv090x.c if (reg) reg 1846 drivers/media/dvb-frontends/stv090x.c u32 srate_coarse, freq_coarse, sym, reg; reg 1866 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDCFGMD); reg 1867 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); reg 1868 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) reg 1945 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 1949 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDSTATE); reg 1950 drivers/media/dvb-frontends/stv090x.c stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); reg 1961 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DSTATUS); reg 1962 drivers/media/dvb-frontends/stv090x.c lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); reg 1978 drivers/media/dvb-frontends/stv090x.c u32 agc2, reg, srate_coarse; reg 2037 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DSTATUS2); reg 2038 drivers/media/dvb-frontends/stv090x.c if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) && reg 2039 drivers/media/dvb-frontends/stv090x.c (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01)) reg 2061 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 2074 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDCFGMD); reg 2075 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */ reg 2076 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) reg 2098 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DSTATUS); reg 2099 drivers/media/dvb-frontends/stv090x.c if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2) reg 2131 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 2206 drivers/media/dvb-frontends/stv090x.c if (state->config->tuner_get_status(fe, ®) < 0) reg 2208 drivers/media/dvb-frontends/stv090x.c if (reg) reg 2336 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 2360 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, PDELCTRL1); reg 2361 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */ reg 2362 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) reg 2385 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, PDELCTRL1); reg 2386 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0); reg 2387 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) reg 2399 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 2464 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDSTATE); reg 2465 drivers/media/dvb-frontends/stv090x.c if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) { reg 2468 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDFLYW); reg 2469 drivers/media/dvb-frontends/stv090x.c dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD); reg 2472 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDFLYW); reg 2473 drivers/media/dvb-frontends/stv090x.c dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD); reg 2500 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 2503 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDSTATE); reg 2504 drivers/media/dvb-frontends/stv090x.c if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2) reg 2506 drivers/media/dvb-frontends/stv090x.c else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) { reg 2507 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, FECM); reg 2508 drivers/media/dvb-frontends/stv090x.c if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1) reg 2545 drivers/media/dvb-frontends/stv090x.c u32 reg, rate; reg 2547 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, VITCURPUN); reg 2548 drivers/media/dvb-frontends/stv090x.c rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD); reg 2588 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 2621 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDMODCOD); reg 2622 drivers/media/dvb-frontends/stv090x.c state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD); reg 2623 drivers/media/dvb-frontends/stv090x.c state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01; reg 2624 drivers/media/dvb-frontends/stv090x.c state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1; reg 2625 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, TMGOBS); reg 2626 drivers/media/dvb-frontends/stv090x.c state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD); reg 2627 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, FECM); reg 2628 drivers/media/dvb-frontends/stv090x.c state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD); reg 2841 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 2850 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDCFGMD); reg 2851 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); reg 2852 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0); reg 2853 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) reg 2856 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DEMOD); reg 2857 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff); reg 2858 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01); reg 2859 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) reg 2884 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDCFGMD); reg 2885 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0); reg 2886 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); reg 2887 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) reg 2896 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDMODCOD); reg 2897 drivers/media/dvb-frontends/stv090x.c modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD); reg 2898 drivers/media/dvb-frontends/stv090x.c pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01; reg 2950 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDCFGMD); reg 2951 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1); reg 2952 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1); reg 2953 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) reg 2960 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, TMGOBS); reg 2964 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDCFGMD); reg 2965 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00); reg 2966 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); reg 2967 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0) reg 3083 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 3086 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDSTATE); reg 3087 drivers/media/dvb-frontends/stv090x.c stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); reg 3097 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, PDELSTATUS1); reg 3098 drivers/media/dvb-frontends/stv090x.c lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD); reg 3102 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, VSTATUSVIT); reg 3103 drivers/media/dvb-frontends/stv090x.c lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD); reg 3116 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 3128 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, TSSTATUS); reg 3129 drivers/media/dvb-frontends/stv090x.c lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD); reg 3140 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 3144 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DEMOD); reg 3145 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00); reg 3146 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) reg 3150 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DEMOD); reg 3151 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00); reg 3152 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) reg 3166 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 3170 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, TSCFGH); reg 3171 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */ reg 3172 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) reg 3254 drivers/media/dvb-frontends/stv090x.c reg = state->config->tuner_bbgain; reg 3255 drivers/media/dvb-frontends/stv090x.c if (reg == 0) reg 3256 drivers/media/dvb-frontends/stv090x.c reg = 10; /* default: 10dB */ reg 3257 drivers/media/dvb-frontends/stv090x.c if (state->config->tuner_set_bbgain(fe, reg) < 0) reg 3279 drivers/media/dvb-frontends/stv090x.c if (state->config->tuner_get_status(fe, ®) < 0) reg 3284 drivers/media/dvb-frontends/stv090x.c if (reg) reg 3312 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DEMOD); reg 3313 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion); reg 3317 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1); reg 3320 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1); reg 3322 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) reg 3363 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, TSCFGH); reg 3364 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */ reg 3365 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) reg 3370 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */ reg 3371 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) reg 3374 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */ reg 3375 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0) reg 3385 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, PDELCTRL2); reg 3386 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1); reg 3387 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0) reg 3390 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, PDELCTRL2); reg 3391 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0); reg 3392 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0) reg 3438 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 3442 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, PDELCTRL1); reg 3443 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x00); reg 3444 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) reg 3448 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, PDELCTRL1); reg 3449 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x01); reg 3450 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) reg 3515 drivers/media/dvb-frontends/stv090x.c u32 reg, dstatus; reg 3524 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DMDSTATE); reg 3525 drivers/media/dvb-frontends/stv090x.c search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD); reg 3537 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, PDELSTATUS1); reg 3538 drivers/media/dvb-frontends/stv090x.c if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) { reg 3540 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, TSSTATUS); reg 3541 drivers/media/dvb-frontends/stv090x.c if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) reg 3550 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, VSTATUSVIT); reg 3551 drivers/media/dvb-frontends/stv090x.c if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) { reg 3553 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, TSSTATUS); reg 3554 drivers/media/dvb-frontends/stv090x.c if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) reg 3569 drivers/media/dvb-frontends/stv090x.c u32 reg, h, m, l; reg 3577 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, ERRCNT22); reg 3578 drivers/media/dvb-frontends/stv090x.c h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD); reg 3580 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, ERRCNT21); reg 3581 drivers/media/dvb-frontends/stv090x.c m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD); reg 3583 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, ERRCNT20); reg 3584 drivers/media/dvb-frontends/stv090x.c l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD); reg 3654 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 3658 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, AGCIQIN1); reg 3659 drivers/media/dvb-frontends/stv090x.c agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD); reg 3660 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, AGCIQIN0); reg 3661 drivers/media/dvb-frontends/stv090x.c agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD); reg 3678 drivers/media/dvb-frontends/stv090x.c u32 reg_0, reg_1, reg, i; reg 3686 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DSTATUS); reg 3687 drivers/media/dvb-frontends/stv090x.c lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); reg 3711 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DSTATUS); reg 3712 drivers/media/dvb-frontends/stv090x.c lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD); reg 3741 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 3743 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DISTXCTL); reg 3746 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0); reg 3747 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); reg 3748 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) reg 3750 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); reg 3751 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) reg 3756 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0); reg 3757 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); reg 3758 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) reg 3780 drivers/media/dvb-frontends/stv090x.c u32 reg, idle = 0, fifo_full = 1; reg 3783 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DISTXCTL); reg 3785 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, reg 3787 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); reg 3788 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) reg 3790 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); reg 3791 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) reg 3794 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1); reg 3795 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) reg 3801 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DISTXSTATUS); reg 3802 drivers/media/dvb-frontends/stv090x.c fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD); reg 3808 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DISTXCTL); reg 3809 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0); reg 3810 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) reg 3816 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DISTXSTATUS); reg 3817 drivers/media/dvb-frontends/stv090x.c idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD); reg 3832 drivers/media/dvb-frontends/stv090x.c u32 reg, idle = 0, fifo_full = 1; reg 3836 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DISTXCTL); reg 3846 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode); reg 3847 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1); reg 3848 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) reg 3850 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0); reg 3851 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) reg 3854 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1); reg 3855 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) reg 3859 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DISTXSTATUS); reg 3860 drivers/media/dvb-frontends/stv090x.c fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD); reg 3866 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DISTXCTL); reg 3867 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0); reg 3868 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0) reg 3874 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DISTXSTATUS); reg 3875 drivers/media/dvb-frontends/stv090x.c idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD); reg 3889 drivers/media/dvb-frontends/stv090x.c u32 reg = 0, i = 0, rx_end = 0; reg 3894 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DISRX_ST0); reg 3895 drivers/media/dvb-frontends/stv090x.c rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD); reg 3899 drivers/media/dvb-frontends/stv090x.c reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD); reg 3910 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 3933 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_TSTTNR1); reg 3934 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0); reg 3935 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) reg 3938 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_TSTTNR2); reg 3939 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 0); reg 3940 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0) reg 3945 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_TSTTNR3); reg 3946 drivers/media/dvb-frontends/stv090x.c if (STV090x_GETFIELD(reg, ADC2_PON_FIELD) == 0) reg 3950 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_STOPCLK1); reg 3952 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 1); reg 3954 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 1); reg 3958 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1); reg 3959 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) reg 3961 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_STOPCLK2); reg 3963 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 1); reg 3965 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 1); reg 3969 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1); reg 3970 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) reg 3976 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_TSTTNR3); reg 3977 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, ADC2_PON_FIELD, 0); reg 3978 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) reg 3981 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_TSTTNR4); reg 3982 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 0); reg 3983 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0) reg 3988 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_TSTTNR1); reg 3989 drivers/media/dvb-frontends/stv090x.c if (STV090x_GETFIELD(reg, ADC1_PON_FIELD) == 0) reg 3993 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_STOPCLK1); reg 3995 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 1); reg 3997 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 1); reg 4001 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1); reg 4002 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) reg 4004 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_STOPCLK2); reg 4006 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 1); reg 4008 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 1); reg 4012 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1); reg 4013 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) reg 4024 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_SYNTCTRL); reg 4025 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01); reg 4026 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) reg 4046 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 4055 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_SYNTCTRL); reg 4056 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00); reg 4057 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0) reg 4063 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_TSTTNR1); reg 4064 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1); reg 4065 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) reg 4068 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_TSTTNR2); reg 4069 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 1); reg 4070 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0) reg 4074 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_STOPCLK1); reg 4076 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 0); reg 4078 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 0); reg 4080 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0); reg 4081 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) reg 4083 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_STOPCLK2); reg 4085 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 0); reg 4087 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 0); reg 4089 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0); reg 4090 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) reg 4096 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_TSTTNR3); reg 4097 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, ADC2_PON_FIELD, 1); reg 4098 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) reg 4101 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_TSTTNR4); reg 4102 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 1); reg 4103 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0) reg 4107 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_STOPCLK1); reg 4109 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 0); reg 4111 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 0); reg 4113 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0); reg 4114 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0) reg 4116 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_STOPCLK2); reg 4118 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 0); reg 4120 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 0); reg 4122 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0); reg 4123 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0) reg 4158 drivers/media/dvb-frontends/stv090x.c u32 reg = 0; reg 4160 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_GENCFG); reg 4165 drivers/media/dvb-frontends/stv090x.c if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) { reg 4172 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_TSTRES0); reg 4173 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1); reg 4174 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) reg 4176 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0); reg 4177 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) reg 4231 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_TSTRES0); reg 4232 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1); reg 4233 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) reg 4235 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0); reg 4236 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0) reg 4239 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, PDELCTRL1); reg 4240 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01); reg 4241 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) reg 4243 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00); reg 4244 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0) reg 4259 drivers/media/dvb-frontends/stv090x.c u32 div, reg; reg 4263 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_SYNTCTRL); reg 4264 drivers/media/dvb-frontends/stv090x.c ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6; reg 4272 drivers/media/dvb-frontends/stv090x.c u32 reg, div, clk_sel; reg 4274 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_SYNTCTRL); reg 4275 drivers/media/dvb-frontends/stv090x.c clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6); reg 4279 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_NCOARSE); reg 4280 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, M_DIV_FIELD, div); reg 4281 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0) reg 4301 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 4318 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); reg 4319 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); reg 4320 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) reg 4322 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P2_TSCFGM); reg 4323 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); reg 4324 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0) reg 4367 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); reg 4368 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); reg 4369 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) reg 4371 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); reg 4372 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0); reg 4373 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) reg 4404 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); reg 4405 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); reg 4406 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); reg 4407 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); reg 4408 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) reg 4413 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); reg 4414 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); reg 4415 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); reg 4416 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); reg 4417 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) reg 4422 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); reg 4423 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); reg 4424 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); reg 4425 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); reg 4426 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) reg 4431 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); reg 4432 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei); reg 4433 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); reg 4434 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); reg 4435 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) reg 4445 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); reg 4446 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); reg 4447 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); reg 4448 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); reg 4449 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) reg 4454 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); reg 4455 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); reg 4456 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); reg 4457 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); reg 4458 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) reg 4463 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); reg 4464 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); reg 4465 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); reg 4466 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); reg 4467 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) reg 4472 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); reg 4473 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei); reg 4474 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); reg 4475 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); reg 4476 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) reg 4508 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); reg 4509 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); reg 4510 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) reg 4540 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P2_TSCFGM); reg 4541 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); reg 4542 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0) reg 4548 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P2_TSCFGH); reg 4549 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); reg 4550 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) reg 4552 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); reg 4553 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0) reg 4556 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); reg 4557 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); reg 4558 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) reg 4560 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); reg 4561 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) reg 4572 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 4604 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); reg 4605 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); reg 4606 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); reg 4607 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) reg 4612 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); reg 4613 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00); reg 4614 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); reg 4615 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) reg 4620 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); reg 4621 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); reg 4622 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00); reg 4623 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) reg 4628 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); reg 4629 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01); reg 4630 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01); reg 4631 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) reg 4663 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); reg 4664 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); reg 4665 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) reg 4671 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_P1_TSCFGH); reg 4672 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01); reg 4673 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) reg 4675 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00); reg 4676 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0) reg 4689 drivers/media/dvb-frontends/stv090x.c u32 reg; reg 4722 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, TNRCFG2); reg 4723 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion); reg 4724 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0) reg 4726 drivers/media/dvb-frontends/stv090x.c reg = STV090x_READ_DEMOD(state, DEMOD); reg 4727 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff); reg 4728 drivers/media/dvb-frontends/stv090x.c if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0) reg 4771 drivers/media/dvb-frontends/stv090x.c u32 reg = 0; reg 4808 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level); reg 4809 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0) reg 4812 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0) reg 4855 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_TSTTNR1); reg 4856 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, ADC1_INMODE_FIELD, reg 4858 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0) reg 4862 drivers/media/dvb-frontends/stv090x.c reg = stv090x_read_reg(state, STV090x_TSTTNR3); reg 4863 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, ADC2_INMODE_FIELD, reg 4865 drivers/media/dvb-frontends/stv090x.c if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0) reg 4883 drivers/media/dvb-frontends/stv090x.c u8 reg = 0; reg 4885 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, GPIOx_OPD_FIELD, dir); reg 4886 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, GPIOx_CONFIG_FIELD, value); reg 4887 drivers/media/dvb-frontends/stv090x.c STV090x_SETFIELD(reg, GPIOx_XOR_FIELD, xor_value); reg 4889 drivers/media/dvb-frontends/stv090x.c return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg); reg 141 drivers/media/dvb-frontends/stv0910.c static int write_reg(struct stv *state, u16 reg, u8 val) reg 144 drivers/media/dvb-frontends/stv0910.c u8 data[3] = {reg >> 8, reg & 0xff, val}; reg 150 drivers/media/dvb-frontends/stv0910.c state->base->adr, reg, val); reg 157 drivers/media/dvb-frontends/stv0910.c u16 reg, u8 *val, int count) reg 159 drivers/media/dvb-frontends/stv0910.c u8 msg[2] = {reg >> 8, reg & 0xff}; reg 167 drivers/media/dvb-frontends/stv0910.c adr, reg); reg 173 drivers/media/dvb-frontends/stv0910.c static int read_reg(struct stv *state, u16 reg, u8 *val) reg 176 drivers/media/dvb-frontends/stv0910.c reg, val, 1); reg 179 drivers/media/dvb-frontends/stv0910.c static int read_regs(struct stv *state, u16 reg, u8 *val, int len) reg 182 drivers/media/dvb-frontends/stv0910.c reg, val, len); reg 185 drivers/media/dvb-frontends/stv0910.c static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val) reg 191 drivers/media/dvb-frontends/stv0910.c status = read_reg(state, reg, &tmp); reg 193 drivers/media/dvb-frontends/stv0910.c status = write_reg(state, reg, (tmp & ~mask) | (val & mask)); reg 1356 drivers/media/dvb-frontends/stv0910.c u8 reg[2]; reg 1361 drivers/media/dvb-frontends/stv0910.c read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, reg, 2); reg 1363 drivers/media/dvb-frontends/stv0910.c agc = (((u32)reg[0]) << 8) | reg[1]; reg 1366 drivers/media/dvb-frontends/stv0910.c read_regs(state, RSTV0910_P2_POWERI + state->regoff, reg, 2); reg 1367 drivers/media/dvb-frontends/stv0910.c power += (u32)reg[0] * (u32)reg[0] reg 1368 drivers/media/dvb-frontends/stv0910.c + (u32)reg[1] * (u32)reg[1]; reg 100 drivers/media/dvb-frontends/stv6110.c u8 reg[] = { start }; reg 105 drivers/media/dvb-frontends/stv6110.c .buf = reg, reg 140 drivers/media/dvb-frontends/stv6110.c u8 reg[] = { 0 }; reg 141 drivers/media/dvb-frontends/stv6110.c stv6110_write_regs(fe, reg, 0, 1); reg 30 drivers/media/dvb-frontends/stv6110x.c static int stv6110x_read_reg(struct stv6110x_state *stv6110x, u8 reg, u8 *data) reg 34 drivers/media/dvb-frontends/stv6110x.c u8 b0[] = { reg }; reg 86 drivers/media/dvb-frontends/stv6110x.c static int stv6110x_write_reg(struct stv6110x_state *stv6110x, u8 reg, u8 data) reg 90 drivers/media/dvb-frontends/stv6110x.c return stv6110x_write_regs(stv6110x, reg, &tmp, 1); reg 34 drivers/media/dvb-frontends/stv6111.c u8 reg[11]; reg 330 drivers/media/dvb-frontends/stv6111.c static int write_regs(struct stv *state, int reg, int len) reg 334 drivers/media/dvb-frontends/stv6111.c memcpy(&d[1], &state->reg[reg], len); reg 335 drivers/media/dvb-frontends/stv6111.c d[0] = reg; reg 339 drivers/media/dvb-frontends/stv6111.c static int write_reg(struct stv *state, u8 reg, u8 val) reg 341 drivers/media/dvb-frontends/stv6111.c u8 d[2] = {reg, val}; reg 346 drivers/media/dvb-frontends/stv6111.c static int read_reg(struct stv *state, u8 reg, u8 *val) reg 348 drivers/media/dvb-frontends/stv6111.c return i2c_read(state->i2c, state->adr, ®, 1, val, 1); reg 381 drivers/media/dvb-frontends/stv6111.c state->reg[0] = 0x08; reg 382 drivers/media/dvb-frontends/stv6111.c state->reg[1] = 0x41; reg 383 drivers/media/dvb-frontends/stv6111.c state->reg[2] = 0x8f; reg 384 drivers/media/dvb-frontends/stv6111.c state->reg[3] = 0x00; reg 385 drivers/media/dvb-frontends/stv6111.c state->reg[4] = 0xce; reg 386 drivers/media/dvb-frontends/stv6111.c state->reg[5] = 0x54; reg 387 drivers/media/dvb-frontends/stv6111.c state->reg[6] = 0x55; reg 388 drivers/media/dvb-frontends/stv6111.c state->reg[7] = 0x45; reg 389 drivers/media/dvb-frontends/stv6111.c state->reg[8] = 0x46; reg 390 drivers/media/dvb-frontends/stv6111.c state->reg[9] = 0xbd; reg 391 drivers/media/dvb-frontends/stv6111.c state->reg[10] = 0x11; reg 396 drivers/media/dvb-frontends/stv6111.c state->reg[0x00] |= (clkdiv & 0x03); reg 398 drivers/media/dvb-frontends/stv6111.c state->reg[0x03] |= (agcmode << 5); reg 400 drivers/media/dvb-frontends/stv6111.c state->reg[0x01] |= 0x30; reg 403 drivers/media/dvb-frontends/stv6111.c state->reg[0x01] = (state->reg[0x01] & ~0x30) | (bbmode << 4); reg 405 drivers/media/dvb-frontends/stv6111.c state->reg[0x03] |= agcref; reg 407 drivers/media/dvb-frontends/stv6111.c state->reg[0x02] = (state->reg[0x02] & ~0x1F) | agcset | 0x40; reg 433 drivers/media/dvb-frontends/stv6111.c if ((state->reg[0x08] & ~0xFC) == ((index - 6) << 2)) reg 436 drivers/media/dvb-frontends/stv6111.c state->reg[0x08] = (state->reg[0x08] & ~0xFC) | ((index - 6) << 2); reg 437 drivers/media/dvb-frontends/stv6111.c state->reg[0x09] = (state->reg[0x09] & ~0x0C) | 0x08; reg 489 drivers/media/dvb-frontends/stv6111.c state->reg[0x02] |= 0x80; /* LNA IIP3 Mode */ reg 491 drivers/media/dvb-frontends/stv6111.c state->reg[0x03] = (state->reg[0x03] & ~0x80) | (psel << 7); reg 492 drivers/media/dvb-frontends/stv6111.c state->reg[0x04] = (div & 0xFF); reg 493 drivers/media/dvb-frontends/stv6111.c state->reg[0x05] = (((div >> 8) & 0x01) | ((frac & 0x7F) << 1)) & 0xff; reg 494 drivers/media/dvb-frontends/stv6111.c state->reg[0x06] = ((frac >> 7) & 0xFF); reg 495 drivers/media/dvb-frontends/stv6111.c state->reg[0x07] = (state->reg[0x07] & ~0x07) | ((frac >> 15) & 0x07); reg 496 drivers/media/dvb-frontends/stv6111.c state->reg[0x07] = (state->reg[0x07] & ~0xE0) | (icp << 5); reg 498 drivers/media/dvb-frontends/stv6111.c state->reg[0x08] = (state->reg[0x08] & ~0xFC) | ((index - 6) << 2); reg 500 drivers/media/dvb-frontends/stv6111.c state->reg[0x09] = (state->reg[0x09] & ~0x0C) | 0x0C; reg 509 drivers/media/dvb-frontends/stv6111.c state->reg[0x02] &= ~0x80; /* LNA NF Mode */ reg 580 drivers/media/dvb-frontends/stv6111.c if ((state->reg[0x03] & 0x60) == 0) { reg 582 drivers/media/dvb-frontends/stv6111.c u8 reg = 0; reg 588 drivers/media/dvb-frontends/stv6111.c write_reg(state, 0x02, state->reg[0x02] | 0x20); reg 589 drivers/media/dvb-frontends/stv6111.c read_reg(state, 2, ®); reg 590 drivers/media/dvb-frontends/stv6111.c if (reg & 0x20) reg 591 drivers/media/dvb-frontends/stv6111.c read_reg(state, 2, ®); reg 596 drivers/media/dvb-frontends/stv6111.c if ((state->reg[0x02] & 0x80) == 0) reg 600 drivers/media/dvb-frontends/stv6111.c reg & 0x1F); reg 605 drivers/media/dvb-frontends/stv6111.c reg & 0x1F); reg 613 drivers/media/dvb-frontends/stv6111.c if ((state->reg[0x02] & 0x80) == 0) { reg 634 drivers/media/dvb-frontends/stv6111.c gain += (s32)((state->reg[0x01] & 0xC0) >> 6) * 600 - 1300; reg 41 drivers/media/dvb-frontends/tc90522.c u8 reg; reg 66 drivers/media/dvb-frontends/tc90522.c static int reg_read(struct tc90522_state *state, u8 reg, u8 *val, u8 len) reg 72 drivers/media/dvb-frontends/tc90522.c .buf = ®, reg 117 drivers/media/dvb-frontends/tc90522.c rv.reg = 0x71; reg 128 drivers/media/dvb-frontends/tc90522.c u8 reg; reg 131 drivers/media/dvb-frontends/tc90522.c ret = reg_read(state, 0xc3, ®, 1); reg 136 drivers/media/dvb-frontends/tc90522.c if (reg & 0x80) /* input level under min ? */ reg 140 drivers/media/dvb-frontends/tc90522.c if (reg & 0x60) /* carrier? */ reg 144 drivers/media/dvb-frontends/tc90522.c if (reg & 0x10) reg 146 drivers/media/dvb-frontends/tc90522.c if (reg_read(state, 0xc5, ®, 1) < 0 || !(reg & 0x03)) reg 156 drivers/media/dvb-frontends/tc90522.c u8 reg; reg 159 drivers/media/dvb-frontends/tc90522.c ret = reg_read(state, 0x96, ®, 1); reg 164 drivers/media/dvb-frontends/tc90522.c if (reg & 0xe0) { reg 170 drivers/media/dvb-frontends/tc90522.c ret = reg_read(state, 0x80, ®, 1); reg 174 drivers/media/dvb-frontends/tc90522.c if (reg & 0xf0) reg 178 drivers/media/dvb-frontends/tc90522.c if (reg & 0x0c) reg 182 drivers/media/dvb-frontends/tc90522.c if (reg & 0x02) reg 60 drivers/media/dvb-frontends/tda10021.c static int _tda10021_writereg (struct tda10021_state* state, u8 reg, u8 data) reg 62 drivers/media/dvb-frontends/tda10021.c u8 buf[] = { reg, data }; reg 69 drivers/media/dvb-frontends/tda10021.c state->frontend.dvb->num, __func__, reg, data, ret); reg 75 drivers/media/dvb-frontends/tda10021.c static u8 tda10021_readreg (struct tda10021_state* state, u8 reg) reg 77 drivers/media/dvb-frontends/tda10021.c u8 b0 [] = { reg }; reg 85 drivers/media/dvb-frontends/tda10021.c if (ret != 2 && reg != 0x1a) reg 52 drivers/media/dvb-frontends/tda10023.c static u8 tda10023_readreg (struct tda10023_state* state, u8 reg) reg 54 drivers/media/dvb-frontends/tda10023.c u8 b0 [] = { reg }; reg 64 drivers/media/dvb-frontends/tda10023.c num, __func__, reg, ret); reg 69 drivers/media/dvb-frontends/tda10023.c static int tda10023_writereg (struct tda10023_state* state, u8 reg, u8 data) reg 71 drivers/media/dvb-frontends/tda10023.c u8 buf[] = { reg, data }; reg 79 drivers/media/dvb-frontends/tda10023.c num, __func__, reg, data, ret); reg 85 drivers/media/dvb-frontends/tda10023.c static int tda10023_writebit (struct tda10023_state* state, u8 reg, u8 mask,u8 data) reg 88 drivers/media/dvb-frontends/tda10023.c return tda10023_writereg(state, reg, data); reg 91 drivers/media/dvb-frontends/tda10023.c val=tda10023_readreg(state,reg); reg 94 drivers/media/dvb-frontends/tda10023.c return tda10023_writereg(state, reg, val); reg 148 drivers/media/dvb-frontends/tda10048.c u8 reg; reg 209 drivers/media/dvb-frontends/tda10048.c static int tda10048_writereg(struct tda10048_state *state, u8 reg, u8 data) reg 213 drivers/media/dvb-frontends/tda10048.c u8 buf[] = { reg, data }; reg 218 drivers/media/dvb-frontends/tda10048.c dprintk(2, "%s(reg = 0x%02x, data = 0x%02x)\n", __func__, reg, data); reg 228 drivers/media/dvb-frontends/tda10048.c static u8 tda10048_readreg(struct tda10048_state *state, u8 reg) reg 232 drivers/media/dvb-frontends/tda10048.c u8 b0[] = { reg }; reg 240 drivers/media/dvb-frontends/tda10048.c dprintk(2, "%s(reg = 0x%02x)\n", __func__, reg); reg 251 drivers/media/dvb-frontends/tda10048.c static int tda10048_writeregbulk(struct tda10048_state *state, u8 reg, reg 259 drivers/media/dvb-frontends/tda10048.c dprintk(2, "%s(%d, ?, len = %d)\n", __func__, reg, len); reg 267 drivers/media/dvb-frontends/tda10048.c *buf = reg; reg 762 drivers/media/dvb-frontends/tda10048.c tda10048_writereg(state, init_tab[i].reg, init_tab[i].data); reg 786 drivers/media/dvb-frontends/tda10048.c u8 reg; reg 790 drivers/media/dvb-frontends/tda10048.c reg = tda10048_readreg(state, TDA10048_SYNC_STATUS); reg 792 drivers/media/dvb-frontends/tda10048.c dprintk(1, "%s() status =0x%02x\n", __func__, reg); reg 794 drivers/media/dvb-frontends/tda10048.c if (reg & 0x02) reg 797 drivers/media/dvb-frontends/tda10048.c if (reg & 0x04) reg 800 drivers/media/dvb-frontends/tda10048.c if (reg & 0x08) { reg 115 drivers/media/dvb-frontends/tda1004x.c static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data) reg 118 drivers/media/dvb-frontends/tda1004x.c u8 buf[] = { reg, data }; reg 121 drivers/media/dvb-frontends/tda1004x.c dprintk("%s: reg=0x%x, data=0x%x\n", __func__, reg, data); reg 128 drivers/media/dvb-frontends/tda1004x.c __func__, reg, data, ret); reg 131 drivers/media/dvb-frontends/tda1004x.c reg, data, ret); reg 135 drivers/media/dvb-frontends/tda1004x.c static int tda1004x_read_byte(struct tda1004x_state *state, int reg) reg 138 drivers/media/dvb-frontends/tda1004x.c u8 b0[] = { reg }; reg 143 drivers/media/dvb-frontends/tda1004x.c dprintk("%s: reg=0x%x\n", __func__, reg); reg 150 drivers/media/dvb-frontends/tda1004x.c dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg, reg 156 drivers/media/dvb-frontends/tda1004x.c reg, b1[0], ret); reg 160 drivers/media/dvb-frontends/tda1004x.c static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data) reg 163 drivers/media/dvb-frontends/tda1004x.c dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __func__, reg, reg 167 drivers/media/dvb-frontends/tda1004x.c val = tda1004x_read_byte(state, reg); reg 176 drivers/media/dvb-frontends/tda1004x.c return tda1004x_write_byteI(state, reg, val); reg 179 drivers/media/dvb-frontends/tda1004x.c static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len) reg 184 drivers/media/dvb-frontends/tda1004x.c dprintk("%s: reg=0x%x, len=0x%x\n", __func__, reg, len); reg 188 drivers/media/dvb-frontends/tda1004x.c result = tda1004x_write_byteI(state, reg + i, buf[i]); reg 1079 drivers/media/dvb-frontends/tda1004x.c int reg = 0; reg 1086 drivers/media/dvb-frontends/tda1004x.c reg = TDA10045H_S_AGC; reg 1090 drivers/media/dvb-frontends/tda1004x.c reg = TDA10046H_AGC_IF_LEVEL; reg 1095 drivers/media/dvb-frontends/tda1004x.c tmp = tda1004x_read_byte(state, reg); reg 128 drivers/media/dvb-frontends/tda1004x.h static inline int tda1004x_writereg(struct dvb_frontend *fe, u8 reg, u8 val) { reg 130 drivers/media/dvb-frontends/tda1004x.h u8 buf[] = {reg, val}; reg 19 drivers/media/dvb-frontends/tda10071.c u8 reg, u8 val, u8 mask) reg 26 drivers/media/dvb-frontends/tda10071.c ret = regmap_bulk_read(dev->regmap, reg, &tmp, 1); reg 35 drivers/media/dvb-frontends/tda10071.c return regmap_bulk_write(dev->regmap, reg, &val, 1); reg 430 drivers/media/dvb-frontends/tda10071.c u8 delivery_system, reg, len; reg 434 drivers/media/dvb-frontends/tda10071.c reg = 0x4c; reg 439 drivers/media/dvb-frontends/tda10071.c reg = 0x4d; reg 448 drivers/media/dvb-frontends/tda10071.c ret = regmap_read(dev->regmap, reg, &uitmp); reg 822 drivers/media/dvb-frontends/tda10071.c ret = tda10071_wr_reg_mask(dev, tab[i].reg, reg 849 drivers/media/dvb-frontends/tda10071.c ret = tda10071_wr_reg_mask(dev, tab2[i].reg, reg 1070 drivers/media/dvb-frontends/tda10071.c ret = tda10071_wr_reg_mask(dev, tab[i].reg, tab[i].val, reg 71 drivers/media/dvb-frontends/tda10071_priv.h u8 reg; reg 39 drivers/media/dvb-frontends/tda10086.c static int tda10086_write_byte(struct tda10086_state *state, int reg, int data) reg 42 drivers/media/dvb-frontends/tda10086.c u8 b0[] = { reg, data }; reg 50 drivers/media/dvb-frontends/tda10086.c __func__, reg, data, ret); reg 55 drivers/media/dvb-frontends/tda10086.c static int tda10086_read_byte(struct tda10086_state *state, int reg) reg 58 drivers/media/dvb-frontends/tda10086.c u8 b0[] = { reg }; reg 68 drivers/media/dvb-frontends/tda10086.c dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg, reg 76 drivers/media/dvb-frontends/tda10086.c static int tda10086_write_mask(struct tda10086_state *state, int reg, int mask, int data) reg 81 drivers/media/dvb-frontends/tda10086.c val = tda10086_read_byte(state, reg); reg 90 drivers/media/dvb-frontends/tda10086.c return tda10086_write_byte(state, reg, val); reg 49 drivers/media/dvb-frontends/tda8083.c static int tda8083_writereg (struct tda8083_state* state, u8 reg, u8 data) reg 52 drivers/media/dvb-frontends/tda8083.c u8 buf [] = { reg, data }; reg 59 drivers/media/dvb-frontends/tda8083.c __func__, reg, ret); reg 79 drivers/media/dvb-frontends/tda8083.c static inline u8 tda8083_readreg (struct tda8083_state* state, u8 reg) reg 83 drivers/media/dvb-frontends/tda8083.c tda8083_readregs (state, reg, &val, 1); reg 41 drivers/media/dvb-frontends/ts2020.c u8 reg; reg 138 drivers/media/dvb-frontends/ts2020.c regmap_write(priv->regmap, reg_vals[i].reg, reg 47 drivers/media/dvb-frontends/ves1820.c static int ves1820_writereg(struct ves1820_state *state, u8 reg, u8 data) reg 49 drivers/media/dvb-frontends/ves1820.c u8 buf[] = { 0x00, reg, data }; reg 57 drivers/media/dvb-frontends/ves1820.c __func__, reg, data, ret); reg 62 drivers/media/dvb-frontends/ves1820.c static u8 ves1820_readreg(struct ves1820_state *state, u8 reg) reg 64 drivers/media/dvb-frontends/ves1820.c u8 b0[] = { 0x00, reg }; reg 76 drivers/media/dvb-frontends/ves1820.c __func__, reg, ret); reg 82 drivers/media/dvb-frontends/ves1x93.c static int ves1x93_writereg (struct ves1x93_state* state, u8 reg, u8 data) reg 84 drivers/media/dvb-frontends/ves1x93.c u8 buf [] = { 0x00, reg, data }; reg 89 drivers/media/dvb-frontends/ves1x93.c dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data); reg 96 drivers/media/dvb-frontends/ves1x93.c static u8 ves1x93_readreg (struct ves1x93_state* state, u8 reg) reg 99 drivers/media/dvb-frontends/ves1x93.c u8 b0 [] = { 0x00, reg }; reg 21 drivers/media/dvb-frontends/zd1301_demod.c static int zd1301_demod_wreg(struct zd1301_demod_dev *dev, u16 reg, u8 val) reg 26 drivers/media/dvb-frontends/zd1301_demod.c return pdata->reg_write(pdata->reg_priv, reg, val); reg 29 drivers/media/dvb-frontends/zd1301_demod.c static int zd1301_demod_rreg(struct zd1301_demod_dev *dev, u16 reg, u8 *val) reg 34 drivers/media/dvb-frontends/zd1301_demod.c return pdata->reg_read(pdata->reg_priv, reg, val); reg 88 drivers/media/dvb-frontends/zl10036.c u8 reg = 0; reg 95 drivers/media/dvb-frontends/zl10036.c reg = 2; reg 97 drivers/media/dvb-frontends/zl10036.c reg = 4; reg 99 drivers/media/dvb-frontends/zl10036.c reg = 6; reg 101 drivers/media/dvb-frontends/zl10036.c reg = 8; reg 103 drivers/media/dvb-frontends/zl10036.c reg = 10; reg 105 drivers/media/dvb-frontends/zl10036.c reg = 12; reg 107 drivers/media/dvb-frontends/zl10036.c deb_i2c("W(%d):", reg); reg 58 drivers/media/dvb-frontends/zl10039.c const enum zl10039_reg_addr reg, u8 *buf, reg 61 drivers/media/dvb-frontends/zl10039.c u8 regbuf[] = { reg }; reg 87 drivers/media/dvb-frontends/zl10039.c const enum zl10039_reg_addr reg, const u8 *src, reg 101 drivers/media/dvb-frontends/zl10039.c KBUILD_MODNAME, reg, count); reg 107 drivers/media/dvb-frontends/zl10039.c buf[0] = reg; reg 118 drivers/media/dvb-frontends/zl10039.c const enum zl10039_reg_addr reg, u8 *val) reg 120 drivers/media/dvb-frontends/zl10039.c return zl10039_read(state, reg, val, 1); reg 124 drivers/media/dvb-frontends/zl10039.c const enum zl10039_reg_addr reg, reg 129 drivers/media/dvb-frontends/zl10039.c return zl10039_write(state, reg, &tmp, 1); reg 39 drivers/media/dvb-frontends/zl10353.c static int zl10353_single_write(struct dvb_frontend *fe, u8 reg, u8 val) reg 42 drivers/media/dvb-frontends/zl10353.c u8 buf[2] = { reg, val }; reg 47 drivers/media/dvb-frontends/zl10353.c printk("zl10353: write to reg %x failed (err = %d)!\n", reg, err); reg 63 drivers/media/dvb-frontends/zl10353.c static int zl10353_read_register(struct zl10353_state *state, u8 reg) reg 66 drivers/media/dvb-frontends/zl10353.c u8 b0[1] = { reg }; reg 79 drivers/media/dvb-frontends/zl10353.c __func__, reg, ret); reg 90 drivers/media/dvb-frontends/zl10353.c u8 reg; reg 93 drivers/media/dvb-frontends/zl10353.c for (reg = 0; ; reg++) { reg 94 drivers/media/dvb-frontends/zl10353.c if (reg % 16 == 0) { reg 95 drivers/media/dvb-frontends/zl10353.c if (reg) reg 97 drivers/media/dvb-frontends/zl10353.c printk(KERN_DEBUG "%02x:", reg); reg 99 drivers/media/dvb-frontends/zl10353.c ret = zl10353_read_register(state, reg); reg 104 drivers/media/dvb-frontends/zl10353.c if (reg == 0xff) reg 110 drivers/media/i2c/ad9389b.c static int ad9389b_rd(struct v4l2_subdev *sd, u8 reg) reg 114 drivers/media/i2c/ad9389b.c return i2c_smbus_read_byte_data(client, reg); reg 117 drivers/media/i2c/ad9389b.c static int ad9389b_wr(struct v4l2_subdev *sd, u8 reg, u8 val) reg 124 drivers/media/i2c/ad9389b.c ret = i2c_smbus_write_byte_data(client, reg, val); reg 128 drivers/media/i2c/ad9389b.c v4l2_err(sd, "%s: failed reg 0x%x, val 0x%x\n", __func__, reg, val); reg 134 drivers/media/i2c/ad9389b.c static inline void ad9389b_wr_and_or(struct v4l2_subdev *sd, u8 reg, reg 137 drivers/media/i2c/ad9389b.c ad9389b_wr(sd, reg, (ad9389b_rd(sd, reg) & clr_mask) | val_mask); reg 326 drivers/media/i2c/ad9389b.c static int ad9389b_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) reg 328 drivers/media/i2c/ad9389b.c reg->val = ad9389b_rd(sd, reg->reg & 0xff); reg 329 drivers/media/i2c/ad9389b.c reg->size = 1; reg 333 drivers/media/i2c/ad9389b.c static int ad9389b_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) reg 335 drivers/media/i2c/ad9389b.c ad9389b_wr(sd, reg->reg & 0xff, reg->val & 0xff); reg 40 drivers/media/i2c/adv7170.c unsigned char reg[128]; reg 60 drivers/media/i2c/adv7170.c static inline int adv7170_write(struct v4l2_subdev *sd, u8 reg, u8 value) reg 65 drivers/media/i2c/adv7170.c encoder->reg[reg] = value; reg 66 drivers/media/i2c/adv7170.c return i2c_smbus_write_byte_data(client, reg, value); reg 69 drivers/media/i2c/adv7170.c static inline int adv7170_read(struct v4l2_subdev *sd, u8 reg) reg 73 drivers/media/i2c/adv7170.c return i2c_smbus_read_byte_data(client, reg); reg 82 drivers/media/i2c/adv7170.c u8 reg; reg 93 drivers/media/i2c/adv7170.c block_data[block_len++] = reg = data[0]; reg 96 drivers/media/i2c/adv7170.c encoder->reg[reg++] = data[1]; reg 99 drivers/media/i2c/adv7170.c } while (len >= 2 && data[0] == reg && block_len < 32); reg 107 drivers/media/i2c/adv7170.c reg = *data++; reg 108 drivers/media/i2c/adv7170.c ret = adv7170_write(sd, reg, *data++); reg 57 drivers/media/i2c/adv7175.c static inline int adv7175_write(struct v4l2_subdev *sd, u8 reg, u8 value) reg 61 drivers/media/i2c/adv7175.c return i2c_smbus_write_byte_data(client, reg, value); reg 64 drivers/media/i2c/adv7175.c static inline int adv7175_read(struct v4l2_subdev *sd, u8 reg) reg 68 drivers/media/i2c/adv7175.c return i2c_smbus_read_byte_data(client, reg); reg 76 drivers/media/i2c/adv7175.c u8 reg; reg 87 drivers/media/i2c/adv7175.c block_data[block_len++] = reg = data[0]; reg 90 drivers/media/i2c/adv7175.c reg++; reg 93 drivers/media/i2c/adv7175.c } while (len >= 2 && data[0] == reg && block_len < 32); reg 101 drivers/media/i2c/adv7175.c reg = *data++; reg 102 drivers/media/i2c/adv7175.c ret = adv7175_write(sd, reg, *data++); reg 235 drivers/media/i2c/adv7180.c static int adv7180_write(struct adv7180_state *state, unsigned int reg, reg 239 drivers/media/i2c/adv7180.c adv7180_select_page(state, reg >> 8); reg 240 drivers/media/i2c/adv7180.c return i2c_smbus_write_byte_data(state->client, reg & 0xff, value); reg 243 drivers/media/i2c/adv7180.c static int adv7180_read(struct adv7180_state *state, unsigned int reg) reg 246 drivers/media/i2c/adv7180.c adv7180_select_page(state, reg >> 8); reg 247 drivers/media/i2c/adv7180.c return i2c_smbus_read_byte_data(state->client, reg & 0xff); reg 250 drivers/media/i2c/adv7180.c static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg, reg 253 drivers/media/i2c/adv7180.c return i2c_smbus_write_byte_data(state->csi_client, reg, value); reg 262 drivers/media/i2c/adv7180.c static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg, reg 265 drivers/media/i2c/adv7180.c return i2c_smbus_write_byte_data(state->vpp_client, reg, value); reg 72 drivers/media/i2c/adv7183.c static inline int adv7183_read(struct v4l2_subdev *sd, unsigned char reg) reg 76 drivers/media/i2c/adv7183.c return i2c_smbus_read_byte_data(client, reg); reg 79 drivers/media/i2c/adv7183.c static inline int adv7183_write(struct v4l2_subdev *sd, unsigned char reg, reg 84 drivers/media/i2c/adv7183.c return i2c_smbus_write_byte_data(client, reg, value); reg 90 drivers/media/i2c/adv7183.c unsigned char reg, data; reg 99 drivers/media/i2c/adv7183.c reg = *regs++; reg 103 drivers/media/i2c/adv7183.c adv7183_write(sd, reg, data); reg 200 drivers/media/i2c/adv7183.c int reg; reg 202 drivers/media/i2c/adv7183.c reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF; reg 204 drivers/media/i2c/adv7183.c reg |= 0x60; reg 206 drivers/media/i2c/adv7183.c reg |= 0x70; reg 208 drivers/media/i2c/adv7183.c reg |= 0x90; reg 210 drivers/media/i2c/adv7183.c reg |= 0xA0; reg 212 drivers/media/i2c/adv7183.c reg |= 0xC0; reg 214 drivers/media/i2c/adv7183.c reg |= 0x80; reg 216 drivers/media/i2c/adv7183.c reg |= 0x50; reg 218 drivers/media/i2c/adv7183.c reg |= 0xE0; reg 221 drivers/media/i2c/adv7183.c adv7183_write(sd, ADV7183_IN_CTRL, reg); reg 230 drivers/media/i2c/adv7183.c int reg; reg 232 drivers/media/i2c/adv7183.c reg = adv7183_read(sd, ADV7183_POW_MANAGE) | 0x80; reg 233 drivers/media/i2c/adv7183.c adv7183_write(sd, ADV7183_POW_MANAGE, reg); reg 243 drivers/media/i2c/adv7183.c int reg; reg 250 drivers/media/i2c/adv7183.c reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF0; reg 253 drivers/media/i2c/adv7183.c reg |= 0x1; reg 256 drivers/media/i2c/adv7183.c reg |= 0x2; reg 259 drivers/media/i2c/adv7183.c reg |= 0x3; reg 262 drivers/media/i2c/adv7183.c reg |= 0x4; reg 265 drivers/media/i2c/adv7183.c reg |= 0x5; reg 268 drivers/media/i2c/adv7183.c reg |= 0xB; reg 271 drivers/media/i2c/adv7183.c reg |= 0xC; reg 274 drivers/media/i2c/adv7183.c reg |= 0xD; reg 277 drivers/media/i2c/adv7183.c reg |= 0xE; reg 280 drivers/media/i2c/adv7183.c reg |= 0xF; reg 283 drivers/media/i2c/adv7183.c reg |= 0x6; reg 286 drivers/media/i2c/adv7183.c reg |= 0x7; reg 289 drivers/media/i2c/adv7183.c reg |= 0x8; reg 292 drivers/media/i2c/adv7183.c reg |= 0x9; reg 295 drivers/media/i2c/adv7183.c reg |= 0xA; reg 300 drivers/media/i2c/adv7183.c adv7183_write(sd, ADV7183_IN_CTRL, reg); reg 305 drivers/media/i2c/adv7183.c reg = adv7183_read(sd, ADV7183_OUT_CTRL) & 0xC0; reg 308 drivers/media/i2c/adv7183.c reg |= 0x9; reg 311 drivers/media/i2c/adv7183.c reg |= 0xC; reg 314 drivers/media/i2c/adv7183.c adv7183_write(sd, ADV7183_OUT_CTRL, reg); reg 352 drivers/media/i2c/adv7183.c int reg; reg 355 drivers/media/i2c/adv7183.c reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF; reg 356 drivers/media/i2c/adv7183.c adv7183_write(sd, ADV7183_IN_CTRL, reg); reg 362 drivers/media/i2c/adv7183.c reg = adv7183_read(sd, ADV7183_STATUS_1); reg 363 drivers/media/i2c/adv7183.c switch ((reg >> 0x4) & 0x7) { reg 400 drivers/media/i2c/adv7183.c int reg; reg 403 drivers/media/i2c/adv7183.c reg = adv7183_read(sd, ADV7183_STATUS_1); reg 404 drivers/media/i2c/adv7183.c if (reg < 0) reg 405 drivers/media/i2c/adv7183.c return reg; reg 406 drivers/media/i2c/adv7183.c if (reg & 0x1) reg 476 drivers/media/i2c/adv7183.c static int adv7183_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) reg 478 drivers/media/i2c/adv7183.c reg->val = adv7183_read(sd, reg->reg & 0xff); reg 479 drivers/media/i2c/adv7183.c reg->size = 1; reg 483 drivers/media/i2c/adv7183.c static int adv7183_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) reg 485 drivers/media/i2c/adv7183.c adv7183_write(sd, reg->reg & 0xff, reg->val & 0xff); reg 69 drivers/media/i2c/adv7343.c static inline int adv7343_write(struct v4l2_subdev *sd, u8 reg, u8 value) reg 73 drivers/media/i2c/adv7343.c return i2c_smbus_write_byte_data(client, reg, value); reg 138 drivers/media/i2c/adv7343.c u8 reg, val; reg 177 drivers/media/i2c/adv7343.c reg = ADV7343_FSC_REG0; reg 178 drivers/media/i2c/adv7343.c for (i = 0; i < 4; i++, reg++, fsc_ptr++) { reg 179 drivers/media/i2c/adv7343.c err = adv7343_write(sd, reg, *fsc_ptr); reg 70 drivers/media/i2c/adv7393.c static inline int adv7393_write(struct v4l2_subdev *sd, u8 reg, u8 value) reg 74 drivers/media/i2c/adv7393.c return i2c_smbus_write_byte_data(client, reg, value); reg 140 drivers/media/i2c/adv7393.c u8 reg; reg 181 drivers/media/i2c/adv7393.c for (reg = ADV7393_FSC_REG0; reg <= ADV7393_FSC_REG3; reg++) { reg 182 drivers/media/i2c/adv7393.c err = adv7393_write(sd, reg, val); reg 42 drivers/media/i2c/adv748x/adv748x-afe.c static int adv748x_afe_read_ro_map(struct adv748x_state *state, u8 reg) reg 52 drivers/media/i2c/adv748x/adv748x-afe.c return sdp_read(state, reg); reg 101 drivers/media/i2c/adv748x/adv748x-core.c int client_page, u8 reg) reg 107 drivers/media/i2c/adv748x/adv748x-core.c err = regmap_read(state->regmap[client_page], reg, &val); reg 111 drivers/media/i2c/adv748x/adv748x-core.c client->addr, reg); reg 118 drivers/media/i2c/adv748x/adv748x-core.c int adv748x_read(struct adv748x_state *state, u8 page, u8 reg) reg 120 drivers/media/i2c/adv748x/adv748x-core.c return adv748x_read_check(state, page, reg); reg 123 drivers/media/i2c/adv748x/adv748x-core.c int adv748x_write(struct adv748x_state *state, u8 page, u8 reg, u8 value) reg 125 drivers/media/i2c/adv748x/adv748x-core.c return regmap_write(state->regmap[page], reg, value); reg 128 drivers/media/i2c/adv748x/adv748x-core.c static int adv748x_write_check(struct adv748x_state *state, u8 page, u8 reg, reg 134 drivers/media/i2c/adv748x/adv748x-core.c *error = adv748x_write(state, page, reg, value); reg 212 drivers/media/i2c/adv748x/adv748x-core.c u8 reg; reg 222 drivers/media/i2c/adv748x/adv748x-core.c ret = adv748x_write(state, regs->page, regs->reg, regs->value); reg 225 drivers/media/i2c/adv748x/adv748x-core.c regs->page, regs->reg); reg 389 drivers/media/i2c/adv748x/adv748x.h int adv748x_read(struct adv748x_state *state, u8 addr, u8 reg); reg 390 drivers/media/i2c/adv748x/adv748x.h int adv748x_write(struct adv748x_state *state, u8 page, u8 reg, u8 value); reg 67 drivers/media/i2c/adv7511-v4l2.c unsigned char reg; reg 188 drivers/media/i2c/adv7511-v4l2.c static int adv7511_rd(struct v4l2_subdev *sd, u8 reg) reg 192 drivers/media/i2c/adv7511-v4l2.c return adv_smbus_read_byte_data(client, reg); reg 195 drivers/media/i2c/adv7511-v4l2.c static int adv7511_wr(struct v4l2_subdev *sd, u8 reg, u8 val) reg 202 drivers/media/i2c/adv7511-v4l2.c ret = i2c_smbus_write_byte_data(client, reg, val); reg 212 drivers/media/i2c/adv7511-v4l2.c static inline void adv7511_wr_and_or(struct v4l2_subdev *sd, u8 reg, u8 clr_mask, u8 val_mask) reg 214 drivers/media/i2c/adv7511-v4l2.c adv7511_wr(sd, reg, (adv7511_rd(sd, reg) & clr_mask) | val_mask); reg 249 drivers/media/i2c/adv7511-v4l2.c static inline int adv7511_cec_read(struct v4l2_subdev *sd, u8 reg) reg 253 drivers/media/i2c/adv7511-v4l2.c return i2c_smbus_read_byte_data(state->i2c_cec, reg); reg 256 drivers/media/i2c/adv7511-v4l2.c static int adv7511_cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 263 drivers/media/i2c/adv7511-v4l2.c ret = i2c_smbus_write_byte_data(state->i2c_cec, reg, val); reg 271 drivers/media/i2c/adv7511-v4l2.c static inline int adv7511_cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, reg 274 drivers/media/i2c/adv7511-v4l2.c return adv7511_cec_write(sd, reg, (adv7511_cec_read(sd, reg) & mask) | val); reg 277 drivers/media/i2c/adv7511-v4l2.c static int adv7511_pktmem_rd(struct v4l2_subdev *sd, u8 reg) reg 281 drivers/media/i2c/adv7511-v4l2.c return adv_smbus_read_byte_data(state->i2c_pktmem, reg); reg 284 drivers/media/i2c/adv7511-v4l2.c static int adv7511_pktmem_wr(struct v4l2_subdev *sd, u8 reg, u8 val) reg 291 drivers/media/i2c/adv7511-v4l2.c ret = i2c_smbus_write_byte_data(state->i2c_pktmem, reg, val); reg 301 drivers/media/i2c/adv7511-v4l2.c static inline void adv7511_pktmem_wr_and_or(struct v4l2_subdev *sd, u8 reg, u8 clr_mask, u8 val_mask) reg 303 drivers/media/i2c/adv7511-v4l2.c adv7511_pktmem_wr(sd, reg, (adv7511_pktmem_rd(sd, reg) & clr_mask) | val_mask); reg 459 drivers/media/i2c/adv7511-v4l2.c static int adv7511_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) reg 463 drivers/media/i2c/adv7511-v4l2.c reg->size = 1; reg 464 drivers/media/i2c/adv7511-v4l2.c switch (reg->reg >> 8) { reg 466 drivers/media/i2c/adv7511-v4l2.c reg->val = adv7511_rd(sd, reg->reg & 0xff); reg 470 drivers/media/i2c/adv7511-v4l2.c reg->val = adv7511_cec_read(sd, reg->reg & 0xff); reg 475 drivers/media/i2c/adv7511-v4l2.c v4l2_info(sd, "Register %03llx not supported\n", reg->reg); reg 482 drivers/media/i2c/adv7511-v4l2.c static int adv7511_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) reg 486 drivers/media/i2c/adv7511-v4l2.c switch (reg->reg >> 8) { reg 488 drivers/media/i2c/adv7511-v4l2.c adv7511_wr(sd, reg->reg & 0xff, reg->val & 0xff); reg 492 drivers/media/i2c/adv7511-v4l2.c adv7511_cec_write(sd, reg->reg & 0xff, reg->val & 0xff); reg 497 drivers/media/i2c/adv7511-v4l2.c v4l2_info(sd, "Register %03llx not supported\n", reg->reg); reg 83 drivers/media/i2c/adv7604.c unsigned int reg; reg 338 drivers/media/i2c/adv7604.c int client_page, u8 reg) reg 344 drivers/media/i2c/adv7604.c err = regmap_read(state->regmap[client_page], reg, &val); reg 348 drivers/media/i2c/adv7604.c client->addr, reg); reg 374 drivers/media/i2c/adv7604.c static inline int io_read(struct v4l2_subdev *sd, u8 reg) reg 378 drivers/media/i2c/adv7604.c return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg); reg 381 drivers/media/i2c/adv7604.c static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 385 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val); reg 388 drivers/media/i2c/adv7604.c static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, reg 391 drivers/media/i2c/adv7604.c return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); reg 394 drivers/media/i2c/adv7604.c static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) reg 398 drivers/media/i2c/adv7604.c return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg); reg 401 drivers/media/i2c/adv7604.c static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 405 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val); reg 408 drivers/media/i2c/adv7604.c static inline int cec_read(struct v4l2_subdev *sd, u8 reg) reg 412 drivers/media/i2c/adv7604.c return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg); reg 415 drivers/media/i2c/adv7604.c static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 419 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val); reg 422 drivers/media/i2c/adv7604.c static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, reg 425 drivers/media/i2c/adv7604.c return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); reg 428 drivers/media/i2c/adv7604.c static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) reg 432 drivers/media/i2c/adv7604.c return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg); reg 435 drivers/media/i2c/adv7604.c static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 439 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val); reg 442 drivers/media/i2c/adv7604.c static inline int afe_read(struct v4l2_subdev *sd, u8 reg) reg 446 drivers/media/i2c/adv7604.c return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg); reg 449 drivers/media/i2c/adv7604.c static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 453 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val); reg 456 drivers/media/i2c/adv7604.c static inline int rep_read(struct v4l2_subdev *sd, u8 reg) reg 460 drivers/media/i2c/adv7604.c return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg); reg 463 drivers/media/i2c/adv7604.c static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 467 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val); reg 470 drivers/media/i2c/adv7604.c static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) reg 472 drivers/media/i2c/adv7604.c return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val); reg 475 drivers/media/i2c/adv7604.c static inline int edid_read(struct v4l2_subdev *sd, u8 reg) reg 479 drivers/media/i2c/adv7604.c return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg); reg 482 drivers/media/i2c/adv7604.c static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 486 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val); reg 535 drivers/media/i2c/adv7604.c static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) reg 539 drivers/media/i2c/adv7604.c return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg); reg 542 drivers/media/i2c/adv7604.c static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) reg 544 drivers/media/i2c/adv7604.c return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; reg 547 drivers/media/i2c/adv7604.c static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 551 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val); reg 554 drivers/media/i2c/adv7604.c static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) reg 556 drivers/media/i2c/adv7604.c return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); reg 559 drivers/media/i2c/adv7604.c static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 563 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val); reg 566 drivers/media/i2c/adv7604.c static inline int cp_read(struct v4l2_subdev *sd, u8 reg) reg 570 drivers/media/i2c/adv7604.c return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg); reg 573 drivers/media/i2c/adv7604.c static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) reg 575 drivers/media/i2c/adv7604.c return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; reg 578 drivers/media/i2c/adv7604.c static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 582 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val); reg 585 drivers/media/i2c/adv7604.c static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) reg 587 drivers/media/i2c/adv7604.c return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val); reg 590 drivers/media/i2c/adv7604.c static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) reg 594 drivers/media/i2c/adv7604.c return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg); reg 597 drivers/media/i2c/adv7604.c static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 601 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val); reg 608 drivers/media/i2c/adv7604.c static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg) reg 611 drivers/media/i2c/adv7604.c unsigned int page = reg >> 8; reg 618 drivers/media/i2c/adv7604.c reg &= 0xff; reg 619 drivers/media/i2c/adv7604.c err = regmap_read(state->regmap[page], reg, &val); reg 625 drivers/media/i2c/adv7604.c static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) reg 628 drivers/media/i2c/adv7604.c unsigned int page = reg >> 8; reg 633 drivers/media/i2c/adv7604.c reg &= 0xff; reg 635 drivers/media/i2c/adv7604.c return regmap_write(state->regmap[page], reg, val); reg 643 drivers/media/i2c/adv7604.c for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++) reg 644 drivers/media/i2c/adv7604.c adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); reg 842 drivers/media/i2c/adv7604.c struct v4l2_dbg_register *reg) reg 846 drivers/media/i2c/adv7604.c ret = adv76xx_read_reg(sd, reg->reg); reg 848 drivers/media/i2c/adv7604.c v4l2_info(sd, "Register %03llx not supported\n", reg->reg); reg 853 drivers/media/i2c/adv7604.c reg->size = 1; reg 854 drivers/media/i2c/adv7604.c reg->val = ret; reg 860 drivers/media/i2c/adv7604.c const struct v4l2_dbg_register *reg) reg 864 drivers/media/i2c/adv7604.c ret = adv76xx_write_reg(sd, reg->reg, reg->val); reg 866 drivers/media/i2c/adv7604.c v4l2_info(sd, "Register %03llx not supported\n", reg->reg); reg 362 drivers/media/i2c/adv7842.c static inline int io_read(struct v4l2_subdev *sd, u8 reg) reg 366 drivers/media/i2c/adv7842.c return adv_smbus_read_byte_data(client, reg); reg 369 drivers/media/i2c/adv7842.c static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 373 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(client, reg, val); reg 376 drivers/media/i2c/adv7842.c static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) reg 378 drivers/media/i2c/adv7842.c return io_write(sd, reg, (io_read(sd, reg) & mask) | val); reg 382 drivers/media/i2c/adv7842.c u8 reg, u8 mask, u8 val) reg 384 drivers/media/i2c/adv7842.c return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); reg 387 drivers/media/i2c/adv7842.c static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) reg 391 drivers/media/i2c/adv7842.c return adv_smbus_read_byte_data(state->i2c_avlink, reg); reg 394 drivers/media/i2c/adv7842.c static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 398 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_avlink, reg, val); reg 401 drivers/media/i2c/adv7842.c static inline int cec_read(struct v4l2_subdev *sd, u8 reg) reg 405 drivers/media/i2c/adv7842.c return adv_smbus_read_byte_data(state->i2c_cec, reg); reg 408 drivers/media/i2c/adv7842.c static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 412 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_cec, reg, val); reg 415 drivers/media/i2c/adv7842.c static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) reg 417 drivers/media/i2c/adv7842.c return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); reg 420 drivers/media/i2c/adv7842.c static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) reg 424 drivers/media/i2c/adv7842.c return adv_smbus_read_byte_data(state->i2c_infoframe, reg); reg 427 drivers/media/i2c/adv7842.c static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 431 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val); reg 434 drivers/media/i2c/adv7842.c static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg) reg 438 drivers/media/i2c/adv7842.c return adv_smbus_read_byte_data(state->i2c_sdp_io, reg); reg 441 drivers/media/i2c/adv7842.c static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 445 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val); reg 448 drivers/media/i2c/adv7842.c static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) reg 450 drivers/media/i2c/adv7842.c return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val); reg 453 drivers/media/i2c/adv7842.c static inline int sdp_read(struct v4l2_subdev *sd, u8 reg) reg 457 drivers/media/i2c/adv7842.c return adv_smbus_read_byte_data(state->i2c_sdp, reg); reg 460 drivers/media/i2c/adv7842.c static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 464 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_sdp, reg, val); reg 467 drivers/media/i2c/adv7842.c static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) reg 469 drivers/media/i2c/adv7842.c return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val); reg 472 drivers/media/i2c/adv7842.c static inline int afe_read(struct v4l2_subdev *sd, u8 reg) reg 476 drivers/media/i2c/adv7842.c return adv_smbus_read_byte_data(state->i2c_afe, reg); reg 479 drivers/media/i2c/adv7842.c static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 483 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_afe, reg, val); reg 486 drivers/media/i2c/adv7842.c static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) reg 488 drivers/media/i2c/adv7842.c return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val); reg 491 drivers/media/i2c/adv7842.c static inline int rep_read(struct v4l2_subdev *sd, u8 reg) reg 495 drivers/media/i2c/adv7842.c return adv_smbus_read_byte_data(state->i2c_repeater, reg); reg 498 drivers/media/i2c/adv7842.c static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 502 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_repeater, reg, val); reg 505 drivers/media/i2c/adv7842.c static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) reg 507 drivers/media/i2c/adv7842.c return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val); reg 510 drivers/media/i2c/adv7842.c static inline int edid_read(struct v4l2_subdev *sd, u8 reg) reg 514 drivers/media/i2c/adv7842.c return adv_smbus_read_byte_data(state->i2c_edid, reg); reg 517 drivers/media/i2c/adv7842.c static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 521 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_edid, reg, val); reg 524 drivers/media/i2c/adv7842.c static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) reg 528 drivers/media/i2c/adv7842.c return adv_smbus_read_byte_data(state->i2c_hdmi, reg); reg 531 drivers/media/i2c/adv7842.c static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 535 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val); reg 538 drivers/media/i2c/adv7842.c static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) reg 540 drivers/media/i2c/adv7842.c return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val); reg 543 drivers/media/i2c/adv7842.c static inline int cp_read(struct v4l2_subdev *sd, u8 reg) reg 547 drivers/media/i2c/adv7842.c return adv_smbus_read_byte_data(state->i2c_cp, reg); reg 550 drivers/media/i2c/adv7842.c static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 554 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_cp, reg, val); reg 557 drivers/media/i2c/adv7842.c static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) reg 559 drivers/media/i2c/adv7842.c return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val); reg 562 drivers/media/i2c/adv7842.c static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) reg 566 drivers/media/i2c/adv7842.c return adv_smbus_read_byte_data(state->i2c_vdp, reg); reg 569 drivers/media/i2c/adv7842.c static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 573 drivers/media/i2c/adv7842.c return adv_smbus_write_byte_data(state->i2c_vdp, reg, val); reg 695 drivers/media/i2c/adv7842.c u8 reg = io_read(sd, 0x6f); reg 698 drivers/media/i2c/adv7842.c if (reg & 0x02) reg 700 drivers/media/i2c/adv7842.c if (reg & 0x01) reg 868 drivers/media/i2c/adv7842.c struct v4l2_dbg_register *reg) reg 870 drivers/media/i2c/adv7842.c reg->size = 1; reg 871 drivers/media/i2c/adv7842.c switch (reg->reg >> 8) { reg 873 drivers/media/i2c/adv7842.c reg->val = io_read(sd, reg->reg & 0xff); reg 876 drivers/media/i2c/adv7842.c reg->val = avlink_read(sd, reg->reg & 0xff); reg 879 drivers/media/i2c/adv7842.c reg->val = cec_read(sd, reg->reg & 0xff); reg 882 drivers/media/i2c/adv7842.c reg->val = infoframe_read(sd, reg->reg & 0xff); reg 885 drivers/media/i2c/adv7842.c reg->val = sdp_io_read(sd, reg->reg & 0xff); reg 888 drivers/media/i2c/adv7842.c reg->val = sdp_read(sd, reg->reg & 0xff); reg 891 drivers/media/i2c/adv7842.c reg->val = afe_read(sd, reg->reg & 0xff); reg 894 drivers/media/i2c/adv7842.c reg->val = rep_read(sd, reg->reg & 0xff); reg 897 drivers/media/i2c/adv7842.c reg->val = edid_read(sd, reg->reg & 0xff); reg 900 drivers/media/i2c/adv7842.c reg->val = hdmi_read(sd, reg->reg & 0xff); reg 903 drivers/media/i2c/adv7842.c reg->val = cp_read(sd, reg->reg & 0xff); reg 906 drivers/media/i2c/adv7842.c reg->val = vdp_read(sd, reg->reg & 0xff); reg 909 drivers/media/i2c/adv7842.c v4l2_info(sd, "Register %03llx not supported\n", reg->reg); reg 917 drivers/media/i2c/adv7842.c const struct v4l2_dbg_register *reg) reg 919 drivers/media/i2c/adv7842.c u8 val = reg->val & 0xff; reg 921 drivers/media/i2c/adv7842.c switch (reg->reg >> 8) { reg 923 drivers/media/i2c/adv7842.c io_write(sd, reg->reg & 0xff, val); reg 926 drivers/media/i2c/adv7842.c avlink_write(sd, reg->reg & 0xff, val); reg 929 drivers/media/i2c/adv7842.c cec_write(sd, reg->reg & 0xff, val); reg 932 drivers/media/i2c/adv7842.c infoframe_write(sd, reg->reg & 0xff, val); reg 935 drivers/media/i2c/adv7842.c sdp_io_write(sd, reg->reg & 0xff, val); reg 938 drivers/media/i2c/adv7842.c sdp_write(sd, reg->reg & 0xff, val); reg 941 drivers/media/i2c/adv7842.c afe_write(sd, reg->reg & 0xff, val); reg 944 drivers/media/i2c/adv7842.c rep_write(sd, reg->reg & 0xff, val); reg 947 drivers/media/i2c/adv7842.c edid_write(sd, reg->reg & 0xff, val); reg 950 drivers/media/i2c/adv7842.c hdmi_write(sd, reg->reg & 0xff, val); reg 953 drivers/media/i2c/adv7842.c cp_write(sd, reg->reg & 0xff, val); reg 956 drivers/media/i2c/adv7842.c vdp_write(sd, reg->reg & 0xff, val); reg 959 drivers/media/i2c/adv7842.c v4l2_info(sd, "Register %03llx not supported\n", reg->reg); reg 35 drivers/media/i2c/ak881x.c static int reg_read(struct i2c_client *client, const u8 reg) reg 37 drivers/media/i2c/ak881x.c return i2c_smbus_read_byte_data(client, reg); reg 40 drivers/media/i2c/ak881x.c static int reg_write(struct i2c_client *client, const u8 reg, reg 43 drivers/media/i2c/ak881x.c return i2c_smbus_write_byte_data(client, reg, data); reg 46 drivers/media/i2c/ak881x.c static int reg_set(struct i2c_client *client, const u8 reg, reg 49 drivers/media/i2c/ak881x.c int ret = reg_read(client, reg); reg 52 drivers/media/i2c/ak881x.c return reg_write(client, reg, (ret & ~mask) | (data & mask)); reg 62 drivers/media/i2c/ak881x.c struct v4l2_dbg_register *reg) reg 66 drivers/media/i2c/ak881x.c if (reg->reg > 0x26) reg 69 drivers/media/i2c/ak881x.c reg->size = 1; reg 70 drivers/media/i2c/ak881x.c reg->val = reg_read(client, reg->reg); reg 72 drivers/media/i2c/ak881x.c if (reg->val > 0xffff) reg 79 drivers/media/i2c/ak881x.c const struct v4l2_dbg_register *reg) reg 83 drivers/media/i2c/ak881x.c if (reg->reg > 0x26) reg 86 drivers/media/i2c/ak881x.c if (reg_write(client, reg->reg, reg->val) < 0) reg 43 drivers/media/i2c/bt819.c unsigned char reg[32]; reg 77 drivers/media/i2c/bt819.c static inline int bt819_write(struct bt819 *decoder, u8 reg, u8 value) reg 81 drivers/media/i2c/bt819.c decoder->reg[reg] = value; reg 82 drivers/media/i2c/bt819.c return i2c_smbus_write_byte_data(client, reg, value); reg 85 drivers/media/i2c/bt819.c static inline int bt819_setbit(struct bt819 *decoder, u8 reg, u8 bit, u8 value) reg 87 drivers/media/i2c/bt819.c return bt819_write(decoder, reg, reg 88 drivers/media/i2c/bt819.c (decoder->reg[reg] & ~(1 << bit)) | (value ? (1 << bit) : 0)); reg 95 drivers/media/i2c/bt819.c u8 reg; reg 106 drivers/media/i2c/bt819.c block_data[block_len++] = reg = data[0]; reg 109 drivers/media/i2c/bt819.c decoder->reg[reg++] = data[1]; reg 112 drivers/media/i2c/bt819.c } while (len >= 2 && data[0] == reg && block_len < 32); reg 120 drivers/media/i2c/bt819.c reg = *data++; reg 121 drivers/media/i2c/bt819.c ret = bt819_write(decoder, reg, *data++); reg 131 drivers/media/i2c/bt819.c static inline int bt819_read(struct bt819 *decoder, u8 reg) reg 135 drivers/media/i2c/bt819.c return i2c_smbus_read_byte_data(client, reg); reg 43 drivers/media/i2c/bt856.c unsigned char reg[BT856_NR_REG]; reg 55 drivers/media/i2c/bt856.c static inline int bt856_write(struct bt856 *encoder, u8 reg, u8 value) reg 59 drivers/media/i2c/bt856.c encoder->reg[reg - BT856_REG_OFFSET] = value; reg 60 drivers/media/i2c/bt856.c return i2c_smbus_write_byte_data(client, reg, value); reg 63 drivers/media/i2c/bt856.c static inline int bt856_setbit(struct bt856 *encoder, u8 reg, u8 bit, u8 value) reg 65 drivers/media/i2c/bt856.c return bt856_write(encoder, reg, reg 66 drivers/media/i2c/bt856.c (encoder->reg[reg - BT856_REG_OFFSET] & ~(1 << bit)) | reg 76 drivers/media/i2c/bt856.c printk(KERN_CONT " %02x", encoder->reg[i]); reg 41 drivers/media/i2c/bt866.c u8 reg[256]; reg 58 drivers/media/i2c/bt866.c encoder->reg[subaddr] = data; reg 125 drivers/media/i2c/bt866.c val = encoder->reg[0xdc]; reg 134 drivers/media/i2c/bt866.c val = encoder->reg[0xcc]; reg 157 drivers/media/i2c/bt866.c val = encoder->reg[0xdc]; reg 23 drivers/media/i2c/cs3308.c static inline int cs3308_write(struct v4l2_subdev *sd, u8 reg, u8 value) reg 27 drivers/media/i2c/cs3308.c return i2c_smbus_write_byte_data(client, reg, value); reg 30 drivers/media/i2c/cs3308.c static inline int cs3308_read(struct v4l2_subdev *sd, u8 reg) reg 34 drivers/media/i2c/cs3308.c return i2c_smbus_read_byte_data(client, reg); reg 38 drivers/media/i2c/cs3308.c static int cs3308_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) reg 40 drivers/media/i2c/cs3308.c reg->val = cs3308_read(sd, reg->reg & 0xffff); reg 41 drivers/media/i2c/cs3308.c reg->size = 1; reg 45 drivers/media/i2c/cs3308.c static int cs3308_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) reg 47 drivers/media/i2c/cs3308.c cs3308_write(sd, reg->reg & 0xffff, reg->val & 0xff); reg 43 drivers/media/i2c/cs5345.c static inline int cs5345_write(struct v4l2_subdev *sd, u8 reg, u8 value) reg 47 drivers/media/i2c/cs5345.c return i2c_smbus_write_byte_data(client, reg, value); reg 50 drivers/media/i2c/cs5345.c static inline int cs5345_read(struct v4l2_subdev *sd, u8 reg) reg 54 drivers/media/i2c/cs5345.c return i2c_smbus_read_byte_data(client, reg); reg 86 drivers/media/i2c/cs5345.c static int cs5345_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) reg 88 drivers/media/i2c/cs5345.c reg->size = 1; reg 89 drivers/media/i2c/cs5345.c reg->val = cs5345_read(sd, reg->reg & 0x1f); reg 93 drivers/media/i2c/cs5345.c static int cs5345_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) reg 95 drivers/media/i2c/cs5345.c cs5345_write(sd, reg->reg & 0x1f, reg->val & 0xff); reg 48 drivers/media/i2c/cs53l32a.c static int cs53l32a_write(struct v4l2_subdev *sd, u8 reg, u8 value) reg 52 drivers/media/i2c/cs53l32a.c return i2c_smbus_write_byte_data(client, reg, value); reg 55 drivers/media/i2c/cs53l32a.c static int cs53l32a_read(struct v4l2_subdev *sd, u8 reg) reg 59 drivers/media/i2c/cs53l32a.c return i2c_smbus_read_byte_data(client, reg); reg 1378 drivers/media/i2c/cx25840/cx25840-core.c u8 reg; reg 1388 drivers/media/i2c/cx25840/cx25840-core.c reg = vid_input & 0xff; reg 1393 drivers/media/i2c/cx25840/cx25840-core.c reg, is_composite); reg 1395 drivers/media/i2c/cx25840/cx25840-core.c reg = 0xf0 + (vid_input - CX25840_COMPOSITE1); reg 1406 drivers/media/i2c/cx25840/cx25840-core.c reg = 0xf0 + ((luma - CX25840_SVIDEO_LUMA1) >> 4); reg 1408 drivers/media/i2c/cx25840/cx25840-core.c reg &= 0x3f; reg 1409 drivers/media/i2c/cx25840/cx25840-core.c reg |= (chroma - CX25840_SVIDEO_CHROMA7) >> 2; reg 1411 drivers/media/i2c/cx25840/cx25840-core.c reg &= 0xcf; reg 1412 drivers/media/i2c/cx25840/cx25840-core.c reg |= (chroma - CX25840_SVIDEO_CHROMA4) >> 4; reg 1426 drivers/media/i2c/cx25840/cx25840-core.c reg &= ~0x30; reg 1429 drivers/media/i2c/cx25840/cx25840-core.c reg &= ~0x30; reg 1430 drivers/media/i2c/cx25840/cx25840-core.c reg |= 0x10; reg 1433 drivers/media/i2c/cx25840/cx25840-core.c reg &= ~0x30; reg 1434 drivers/media/i2c/cx25840/cx25840-core.c reg |= 0x20; reg 1437 drivers/media/i2c/cx25840/cx25840-core.c reg &= ~0xc0; reg 1440 drivers/media/i2c/cx25840/cx25840-core.c reg &= ~0xc0; reg 1441 drivers/media/i2c/cx25840/cx25840-core.c reg |= 0x40; reg 1450 drivers/media/i2c/cx25840/cx25840-core.c cx25840_write(client, 0x103, reg); reg 1525 drivers/media/i2c/cx25840/cx25840-core.c cx25840_and_or(client, 0x102, ~0x2, (reg & 0x80) == 0 ? 2 : 0); reg 1527 drivers/media/i2c/cx25840/cx25840-core.c if ((reg & 0xc0) != 0xc0 && (reg & 0x30) != 0x30) reg 2340 drivers/media/i2c/cx25840/cx25840-core.c struct v4l2_dbg_register *reg) reg 2344 drivers/media/i2c/cx25840/cx25840-core.c reg->size = 1; reg 2345 drivers/media/i2c/cx25840/cx25840-core.c reg->val = cx25840_read(client, reg->reg & 0x0fff); reg 2350 drivers/media/i2c/cx25840/cx25840-core.c const struct v4l2_dbg_register *reg) reg 2354 drivers/media/i2c/cx25840/cx25840-core.c cx25840_write(client, reg->reg & 0x0fff, reg->val & 0xff); reg 142 drivers/media/i2c/et8ek8/et8ek8_driver.c u16 reg, u32 *val) reg 159 drivers/media/i2c/et8ek8/et8ek8_driver.c data[0] = (u8) (reg >> 8); reg 160 drivers/media/i2c/et8ek8/et8ek8_driver.c data[1] = (u8) (reg & 0xff); reg 181 drivers/media/i2c/et8ek8/et8ek8_driver.c dev_err(&client->dev, "read from offset 0x%x error %d\n", reg, r); reg 186 drivers/media/i2c/et8ek8/et8ek8_driver.c static void et8ek8_i2c_create_msg(struct i2c_client *client, u16 len, u16 reg, reg 196 drivers/media/i2c/et8ek8/et8ek8_driver.c buf[0] = (u8) (reg >> 8); reg 197 drivers/media/i2c/et8ek8/et8ek8_driver.c buf[1] = (u8) (reg & 0xff); reg 225 drivers/media/i2c/et8ek8/et8ek8_driver.c u16 reg, data_length; reg 232 drivers/media/i2c/et8ek8/et8ek8_driver.c reg = wnext->reg; reg 236 drivers/media/i2c/et8ek8/et8ek8_driver.c et8ek8_i2c_create_msg(client, data_length, reg, reg 336 drivers/media/i2c/et8ek8/et8ek8_driver.c u16 reg, u32 val) reg 347 drivers/media/i2c/et8ek8/et8ek8_driver.c et8ek8_i2c_create_msg(client, data_length, reg, val, &msg, data); reg 352 drivers/media/i2c/et8ek8/et8ek8_driver.c "wrote 0x%x to offset 0x%x error %d\n", val, reg, r); reg 53 drivers/media/i2c/et8ek8/et8ek8_reg.h u16 reg; /* 16-bit offset */ reg 505 drivers/media/i2c/imx214.c const struct v4l2_dbg_register *reg) reg 509 drivers/media/i2c/imx214.c return regmap_write(imx214->regmap, reg->reg, reg->val); reg 513 drivers/media/i2c/imx214.c struct v4l2_dbg_register *reg) reg 519 drivers/media/i2c/imx214.c reg->size = 1; reg 520 drivers/media/i2c/imx214.c ret = regmap_read(imx214->regmap, reg->reg, &aux); reg 521 drivers/media/i2c/imx214.c reg->val = aux; reg 621 drivers/media/i2c/imx258.c static int imx258_read_reg(struct imx258 *imx258, u16 reg, u32 len, u32 *val) reg 625 drivers/media/i2c/imx258.c u8 addr_buf[2] = { reg >> 8, reg & 0xff }; reg 654 drivers/media/i2c/imx258.c static int imx258_write_reg(struct imx258 *imx258, u16 reg, u32 len, u32 val) reg 662 drivers/media/i2c/imx258.c put_unaligned_be16(reg, buf); reg 1787 drivers/media/i2c/imx319.c static int imx319_read_reg(struct imx319 *imx319, u16 reg, u32 len, u32 *val) reg 1798 drivers/media/i2c/imx319.c put_unaligned_be16(reg, addr_buf); reg 1821 drivers/media/i2c/imx319.c static int imx319_write_reg(struct imx319 *imx319, u16 reg, u32 len, u32 val) reg 1829 drivers/media/i2c/imx319.c put_unaligned_be16(reg, buf); reg 1087 drivers/media/i2c/imx355.c static int imx355_read_reg(struct imx355 *imx355, u16 reg, u32 len, u32 *val) reg 1098 drivers/media/i2c/imx355.c put_unaligned_be16(reg, addr_buf); reg 1121 drivers/media/i2c/imx355.c static int imx355_write_reg(struct imx355 *imx355, u16 reg, u32 len, u32 val) reg 1129 drivers/media/i2c/imx355.c put_unaligned_be16(reg, buf); reg 302 drivers/media/i2c/ks0127.c static u8 ks0127_read(struct v4l2_subdev *sd, u8 reg) reg 309 drivers/media/i2c/ks0127.c .len = sizeof(reg), reg 310 drivers/media/i2c/ks0127.c .buf = ® reg 329 drivers/media/i2c/ks0127.c static void ks0127_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 333 drivers/media/i2c/ks0127.c char msg[] = { reg, val }; reg 338 drivers/media/i2c/ks0127.c ks->regs[reg] = val; reg 343 drivers/media/i2c/ks0127.c static void ks0127_and_or(struct v4l2_subdev *sd, u8 reg, u8 and_v, u8 or_v) reg 347 drivers/media/i2c/ks0127.c u8 val = ks->regs[reg]; reg 349 drivers/media/i2c/ks0127.c ks0127_write(sd, reg, val); reg 69 drivers/media/i2c/m52790.c static int m52790_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) reg 73 drivers/media/i2c/m52790.c if (reg->reg != 0) reg 75 drivers/media/i2c/m52790.c reg->size = 1; reg 76 drivers/media/i2c/m52790.c reg->val = state->input | state->output; reg 80 drivers/media/i2c/m52790.c static int m52790_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) reg 84 drivers/media/i2c/m52790.c if (reg->reg != 0) reg 86 drivers/media/i2c/m52790.c state->input = reg->val & 0x0303; reg 87 drivers/media/i2c/m52790.c state->output = reg->val & ~0x0303; reg 42 drivers/media/i2c/m5mols/m5mols.h u8 reg; reg 277 drivers/media/i2c/m5mols/m5mols.h int m5mols_busy_wait(struct v4l2_subdev *sd, u32 reg, u32 value, u32 mask, reg 308 drivers/media/i2c/m5mols/m5mols.h int m5mols_enable_interrupt(struct v4l2_subdev *sd, u8 reg); reg 139 drivers/media/i2c/m5mols/m5mols_core.c static int m5mols_read(struct v4l2_subdev *sd, u32 size, u32 reg, u32 *val) reg 144 drivers/media/i2c/m5mols/m5mols_core.c u8 category = I2C_CATEGORY(reg); reg 145 drivers/media/i2c/m5mols/m5mols_core.c u8 cmd = I2C_COMMAND(reg); reg 185 drivers/media/i2c/m5mols/m5mols_core.c int m5mols_read_u8(struct v4l2_subdev *sd, u32 reg, u8 *val) reg 190 drivers/media/i2c/m5mols/m5mols_core.c if (I2C_SIZE(reg) != 1) { reg 195 drivers/media/i2c/m5mols/m5mols_core.c ret = m5mols_read(sd, I2C_SIZE(reg), reg, &val_32); reg 203 drivers/media/i2c/m5mols/m5mols_core.c int m5mols_read_u16(struct v4l2_subdev *sd, u32 reg, u16 *val) reg 208 drivers/media/i2c/m5mols/m5mols_core.c if (I2C_SIZE(reg) != 2) { reg 213 drivers/media/i2c/m5mols/m5mols_core.c ret = m5mols_read(sd, I2C_SIZE(reg), reg, &val_32); reg 221 drivers/media/i2c/m5mols/m5mols_core.c int m5mols_read_u32(struct v4l2_subdev *sd, u32 reg, u32 *val) reg 223 drivers/media/i2c/m5mols/m5mols_core.c if (I2C_SIZE(reg) != 4) { reg 228 drivers/media/i2c/m5mols/m5mols_core.c return m5mols_read(sd, I2C_SIZE(reg), reg, val); reg 239 drivers/media/i2c/m5mols/m5mols_core.c int m5mols_write(struct v4l2_subdev *sd, u32 reg, u32 val) reg 244 drivers/media/i2c/m5mols/m5mols_core.c u8 category = I2C_CATEGORY(reg); reg 245 drivers/media/i2c/m5mols/m5mols_core.c u8 cmd = I2C_COMMAND(reg); reg 246 drivers/media/i2c/m5mols/m5mols_core.c u8 size = I2C_SIZE(reg); reg 297 drivers/media/i2c/m5mols/m5mols_core.c int m5mols_busy_wait(struct v4l2_subdev *sd, u32 reg, u32 value, u32 mask, reg 305 drivers/media/i2c/m5mols/m5mols_core.c int ret = m5mols_read_u8(sd, reg, &status); reg 325 drivers/media/i2c/m5mols/m5mols_core.c int m5mols_enable_interrupt(struct v4l2_subdev *sd, u8 reg) reg 334 drivers/media/i2c/m5mols/m5mols_core.c ret = m5mols_write(sd, SYSTEM_INT_ENABLE, reg & ~mask); reg 382 drivers/media/i2c/m5mols/m5mols_core.c u8 reg; reg 387 drivers/media/i2c/m5mols/m5mols_core.c ret = m5mols_read_u8(sd, SYSTEM_SYSMODE, ®); reg 388 drivers/media/i2c/m5mols/m5mols_core.c if (ret || reg == mode) reg 391 drivers/media/i2c/m5mols/m5mols_core.c switch (reg) { reg 533 drivers/media/i2c/m5mols/m5mols_core.c *resolution = match->reg; reg 101 drivers/media/i2c/ml86v7667.c static int ml86v7667_mask_set(struct i2c_client *client, const u8 reg, reg 104 drivers/media/i2c/ml86v7667.c int val = i2c_smbus_read_byte_data(client, reg); reg 109 drivers/media/i2c/ml86v7667.c return i2c_smbus_write_byte_data(client, reg, val); reg 261 drivers/media/i2c/ml86v7667.c struct v4l2_dbg_register *reg) reg 266 drivers/media/i2c/ml86v7667.c ret = i2c_smbus_read_byte_data(client, (u8)reg->reg); reg 270 drivers/media/i2c/ml86v7667.c reg->val = ret; reg 271 drivers/media/i2c/ml86v7667.c reg->size = sizeof(u8); reg 277 drivers/media/i2c/ml86v7667.c const struct v4l2_dbg_register *reg) reg 281 drivers/media/i2c/ml86v7667.c return i2c_smbus_write_byte_data(client, (u8)reg->reg, (u8)reg->val); reg 479 drivers/media/i2c/msp3400-driver.c u16 val, reg; reg 498 drivers/media/i2c/msp3400-driver.c reg = (state->opmode == OPMODE_AUTOSELECT) ? 0x30 : 0xbb; reg 499 drivers/media/i2c/msp3400-driver.c val = msp_read_dem(client, reg); reg 500 drivers/media/i2c/msp3400-driver.c msp_write_dem(client, reg, (val & ~0x100) | (tuner << 8)); reg 878 drivers/media/i2c/msp3400-kthreads.c static void msp34xxg_set_source(struct i2c_client *client, u16 reg, int in) reg 917 drivers/media/i2c/msp3400-kthreads.c "set source to %d (0x%x) for output %02x\n", in, source, reg); reg 918 drivers/media/i2c/msp3400-kthreads.c msp_write_dsp(client, reg, source); reg 115 drivers/media/i2c/mt9m001.c static int reg_read(struct i2c_client *client, const u8 reg) reg 117 drivers/media/i2c/mt9m001.c return i2c_smbus_read_word_swapped(client, reg); reg 120 drivers/media/i2c/mt9m001.c static int reg_write(struct i2c_client *client, const u8 reg, reg 123 drivers/media/i2c/mt9m001.c return i2c_smbus_write_word_swapped(client, reg, data); reg 126 drivers/media/i2c/mt9m001.c static int reg_set(struct i2c_client *client, const u8 reg, reg 131 drivers/media/i2c/mt9m001.c ret = reg_read(client, reg); reg 134 drivers/media/i2c/mt9m001.c return reg_write(client, reg, ret | data); reg 137 drivers/media/i2c/mt9m001.c static int reg_clear(struct i2c_client *client, const u8 reg, reg 142 drivers/media/i2c/mt9m001.c ret = reg_read(client, reg); reg 145 drivers/media/i2c/mt9m001.c return reg_write(client, reg, ret & ~data); reg 149 drivers/media/i2c/mt9m001.c u8 reg; reg 159 drivers/media/i2c/mt9m001.c int ret = reg_write(client, regs[i].reg, regs[i].data); reg 419 drivers/media/i2c/mt9m001.c struct v4l2_dbg_register *reg) reg 423 drivers/media/i2c/mt9m001.c if (reg->reg > 0xff) reg 426 drivers/media/i2c/mt9m001.c reg->size = 2; reg 427 drivers/media/i2c/mt9m001.c reg->val = reg_read(client, reg->reg); reg 429 drivers/media/i2c/mt9m001.c if (reg->val > 0xffff) reg 436 drivers/media/i2c/mt9m001.c const struct v4l2_dbg_register *reg) reg 440 drivers/media/i2c/mt9m001.c if (reg->reg > 0xff) reg 443 drivers/media/i2c/mt9m001.c if (reg_write(client, reg->reg, reg->val) < 0) reg 158 drivers/media/i2c/mt9m032.c static int mt9m032_read(struct i2c_client *client, u8 reg) reg 160 drivers/media/i2c/mt9m032.c return i2c_smbus_read_word_swapped(client, reg); reg 163 drivers/media/i2c/mt9m032.c static int mt9m032_write(struct i2c_client *client, u8 reg, const u16 data) reg 165 drivers/media/i2c/mt9m032.c return i2c_smbus_write_word_swapped(client, reg, data); reg 546 drivers/media/i2c/mt9m032.c struct v4l2_dbg_register *reg) reg 552 drivers/media/i2c/mt9m032.c if (reg->reg > 0xff) reg 555 drivers/media/i2c/mt9m032.c val = mt9m032_read(client, reg->reg); reg 559 drivers/media/i2c/mt9m032.c reg->size = 2; reg 560 drivers/media/i2c/mt9m032.c reg->val = val; reg 566 drivers/media/i2c/mt9m032.c const struct v4l2_dbg_register *reg) reg 571 drivers/media/i2c/mt9m032.c if (reg->reg > 0xff) reg 574 drivers/media/i2c/mt9m032.c return mt9m032_write(client, reg->reg, reg->val); reg 139 drivers/media/i2c/mt9m111.c #define reg_read(reg) mt9m111_reg_read(client, MT9M111_##reg) reg 140 drivers/media/i2c/mt9m111.c #define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val)) reg 141 drivers/media/i2c/mt9m111.c #define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val)) reg 142 drivers/media/i2c/mt9m111.c #define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val)) reg 143 drivers/media/i2c/mt9m111.c #define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \ reg 301 drivers/media/i2c/mt9m111.c static int reg_page_map_set(struct i2c_client *client, const u16 reg) reg 307 drivers/media/i2c/mt9m111.c page = (reg >> 8); reg 319 drivers/media/i2c/mt9m111.c static int mt9m111_reg_read(struct i2c_client *client, const u16 reg) reg 323 drivers/media/i2c/mt9m111.c ret = reg_page_map_set(client, reg); reg 325 drivers/media/i2c/mt9m111.c ret = i2c_smbus_read_word_swapped(client, reg & 0xff); reg 327 drivers/media/i2c/mt9m111.c dev_dbg(&client->dev, "read reg.%03x -> %04x\n", reg, ret); reg 331 drivers/media/i2c/mt9m111.c static int mt9m111_reg_write(struct i2c_client *client, const u16 reg, reg 336 drivers/media/i2c/mt9m111.c ret = reg_page_map_set(client, reg); reg 338 drivers/media/i2c/mt9m111.c ret = i2c_smbus_write_word_swapped(client, reg & 0xff, data); reg 339 drivers/media/i2c/mt9m111.c dev_dbg(&client->dev, "write reg.%03x = %04x -> %d\n", reg, data, ret); reg 343 drivers/media/i2c/mt9m111.c static int mt9m111_reg_set(struct i2c_client *client, const u16 reg, reg 348 drivers/media/i2c/mt9m111.c ret = mt9m111_reg_read(client, reg); reg 350 drivers/media/i2c/mt9m111.c ret = mt9m111_reg_write(client, reg, ret | data); reg 354 drivers/media/i2c/mt9m111.c static int mt9m111_reg_clear(struct i2c_client *client, const u16 reg, reg 359 drivers/media/i2c/mt9m111.c ret = mt9m111_reg_read(client, reg); reg 361 drivers/media/i2c/mt9m111.c ret = mt9m111_reg_write(client, reg, ret & ~data); reg 365 drivers/media/i2c/mt9m111.c static int mt9m111_reg_mask(struct i2c_client *client, const u16 reg, reg 370 drivers/media/i2c/mt9m111.c ret = mt9m111_reg_read(client, reg); reg 372 drivers/media/i2c/mt9m111.c ret = mt9m111_reg_write(client, reg, (ret & ~mask) | data); reg 754 drivers/media/i2c/mt9m111.c struct v4l2_dbg_register *reg) reg 759 drivers/media/i2c/mt9m111.c if (reg->reg > 0x2ff) reg 762 drivers/media/i2c/mt9m111.c val = mt9m111_reg_read(client, reg->reg); reg 763 drivers/media/i2c/mt9m111.c reg->size = 2; reg 764 drivers/media/i2c/mt9m111.c reg->val = (u64)val; reg 766 drivers/media/i2c/mt9m111.c if (reg->val > 0xffff) reg 773 drivers/media/i2c/mt9m111.c const struct v4l2_dbg_register *reg) reg 777 drivers/media/i2c/mt9m111.c if (reg->reg > 0x2ff) reg 780 drivers/media/i2c/mt9m111.c if (mt9m111_reg_write(client, reg->reg, reg->val) < 0) reg 151 drivers/media/i2c/mt9p031.c static int mt9p031_read(struct i2c_client *client, u8 reg) reg 153 drivers/media/i2c/mt9p031.c return i2c_smbus_read_word_swapped(client, reg); reg 156 drivers/media/i2c/mt9p031.c static int mt9p031_write(struct i2c_client *client, u8 reg, u16 data) reg 158 drivers/media/i2c/mt9p031.c return i2c_smbus_write_word_swapped(client, reg, data); reg 140 drivers/media/i2c/mt9t001.c static int mt9t001_read(struct i2c_client *client, u8 reg) reg 142 drivers/media/i2c/mt9t001.c return i2c_smbus_read_word_swapped(client, reg); reg 145 drivers/media/i2c/mt9t001.c static int mt9t001_write(struct i2c_client *client, u8 reg, u16 data) reg 147 drivers/media/i2c/mt9t001.c return i2c_smbus_write_word_swapped(client, reg, data); reg 722 drivers/media/i2c/mt9t112.c struct v4l2_dbg_register *reg) reg 727 drivers/media/i2c/mt9t112.c reg->size = 2; reg 728 drivers/media/i2c/mt9t112.c mt9t112_reg_read(ret, client, reg->reg); reg 730 drivers/media/i2c/mt9t112.c reg->val = (__u64)ret; reg 736 drivers/media/i2c/mt9t112.c const struct v4l2_dbg_register *reg) reg 741 drivers/media/i2c/mt9t112.c mt9t112_reg_write(ret, client, reg->reg, reg->val); reg 116 drivers/media/i2c/mt9v011.c unsigned char reg; reg 319 drivers/media/i2c/mt9v011.c mt9v011_write(sd, mt9v011_init_default[i].reg, reg 396 drivers/media/i2c/mt9v011.c struct v4l2_dbg_register *reg) reg 398 drivers/media/i2c/mt9v011.c reg->val = mt9v011_read(sd, reg->reg & 0xff); reg 399 drivers/media/i2c/mt9v011.c reg->size = 2; reg 405 drivers/media/i2c/mt9v011.c const struct v4l2_dbg_register *reg) reg 407 drivers/media/i2c/mt9v011.c mt9v011_write(sd, reg->reg & 0xff, reg->val & 0xffff); reg 220 drivers/media/i2c/mt9v111.c static int __mt9v111_read(struct i2c_client *c, u8 reg, u16 *val) reg 229 drivers/media/i2c/mt9v111.c msg[0].buf = ® reg 244 drivers/media/i2c/mt9v111.c dev_dbg(&c->dev, "%s: %x=%x\n", __func__, reg, *val); reg 249 drivers/media/i2c/mt9v111.c static int __mt9v111_write(struct i2c_client *c, u8 reg, u16 val) reg 255 drivers/media/i2c/mt9v111.c buf[0] = reg; reg 264 drivers/media/i2c/mt9v111.c dev_dbg(&c->dev, "%s: %x = %x%x\n", __func__, reg, buf[1], buf[2]); reg 302 drivers/media/i2c/mt9v111.c static int mt9v111_read(struct i2c_client *c, u8 addr_space, u8 reg, u16 *val) reg 311 drivers/media/i2c/mt9v111.c ret = __mt9v111_read(c, reg, val); reg 318 drivers/media/i2c/mt9v111.c static int mt9v111_write(struct i2c_client *c, u8 addr_space, u8 reg, u16 val) reg 327 drivers/media/i2c/mt9v111.c ret = __mt9v111_write(c, reg, val); reg 334 drivers/media/i2c/mt9v111.c static int mt9v111_update(struct i2c_client *c, u8 addr_space, u8 reg, reg 346 drivers/media/i2c/mt9v111.c ret = __mt9v111_read(c, reg, ¤t_val); reg 352 drivers/media/i2c/mt9v111.c ret = __mt9v111_write(c, reg, current_val); reg 242 drivers/media/i2c/noon010pc30.c struct i2c_client *client, unsigned int reg) reg 244 drivers/media/i2c/noon010pc30.c u32 page = reg >> 8 & 0xFF; reg 247 drivers/media/i2c/noon010pc30.c if (info->i2c_reg_page != page && (reg & 0xFF) != 0x03) { reg 294 drivers/media/i2c/noon010pc30.c u8 reg = sleep ? 0xF1 : 0xF0; reg 298 drivers/media/i2c/noon010pc30.c ret = cam_i2c_write(sd, POWER_CTRL_REG, reg | 0x02); reg 302 drivers/media/i2c/noon010pc30.c ret = cam_i2c_write(sd, POWER_CTRL_REG, reg); reg 324 drivers/media/i2c/noon010pc30.c int reg, ret; reg 326 drivers/media/i2c/noon010pc30.c reg = cam_i2c_read(sd, VDO_CTL_REG(1)); reg 327 drivers/media/i2c/noon010pc30.c if (reg < 0) reg 328 drivers/media/i2c/noon010pc30.c return reg; reg 330 drivers/media/i2c/noon010pc30.c reg &= 0x7C; reg 332 drivers/media/i2c/noon010pc30.c reg |= 0x01; reg 334 drivers/media/i2c/noon010pc30.c reg |= 0x02; reg 336 drivers/media/i2c/noon010pc30.c ret = cam_i2c_write(sd, VDO_CTL_REG(1), reg | 0x80); reg 1053 drivers/media/i2c/ov13858.c static int ov13858_read_reg(struct ov13858 *ov13858, u16 reg, u32 len, reg 1061 drivers/media/i2c/ov13858.c __be16 reg_addr_be = cpu_to_be16(reg); reg 1089 drivers/media/i2c/ov13858.c static int ov13858_write_reg(struct ov13858 *ov13858, u16 reg, u32 len, reg 1100 drivers/media/i2c/ov13858.c buf[0] = reg >> 8; reg 1101 drivers/media/i2c/ov13858.c buf[1] = reg & 0xff; reg 673 drivers/media/i2c/ov2640.c u8 reg, u8 mask, u8 set) reg 675 drivers/media/i2c/ov2640.c s32 val = i2c_smbus_read_byte_data(client, reg); reg 682 drivers/media/i2c/ov2640.c dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val); reg 684 drivers/media/i2c/ov2640.c return i2c_smbus_write_byte_data(client, reg, val); reg 756 drivers/media/i2c/ov2640.c struct v4l2_dbg_register *reg) reg 761 drivers/media/i2c/ov2640.c reg->size = 1; reg 762 drivers/media/i2c/ov2640.c if (reg->reg > 0xff) reg 765 drivers/media/i2c/ov2640.c ret = i2c_smbus_read_byte_data(client, reg->reg); reg 769 drivers/media/i2c/ov2640.c reg->val = ret; reg 775 drivers/media/i2c/ov2640.c const struct v4l2_dbg_register *reg) reg 779 drivers/media/i2c/ov2640.c if (reg->reg > 0xff || reg 780 drivers/media/i2c/ov2640.c reg->val > 0xff) reg 783 drivers/media/i2c/ov2640.c return i2c_smbus_write_byte_data(client, reg->reg, reg->val); reg 218 drivers/media/i2c/ov2659.c unsigned char reg; reg 842 drivers/media/i2c/ov2659.c static int ov2659_write(struct i2c_client *client, u16 reg, u8 val) reg 848 drivers/media/i2c/ov2659.c buf[0] = reg >> 8; reg 849 drivers/media/i2c/ov2659.c buf[1] = reg & 0xFF; reg 862 drivers/media/i2c/ov2659.c "ov2659 write reg(0x%x val:0x%x) failed !\n", reg, val); reg 868 drivers/media/i2c/ov2659.c static int ov2659_read(struct i2c_client *client, u16 reg, u8 *val) reg 874 drivers/media/i2c/ov2659.c buf[0] = reg >> 8; reg 875 drivers/media/i2c/ov2659.c buf[1] = reg & 0xFF; reg 894 drivers/media/i2c/ov2659.c "ov2659 read reg(0x%x val:0x%x) failed !\n", reg, *val); reg 935 drivers/media/i2c/ov2659.c ctrl1_reg = ctrl1[i].reg; reg 937 drivers/media/i2c/ov2659.c ctrl3_reg = ctrl3[j].reg; reg 197 drivers/media/i2c/ov2680.c static int __ov2680_write_reg(struct ov2680_dev *sensor, u16 reg, reg 207 drivers/media/i2c/ov2680.c put_unaligned_be16(reg, buf); reg 211 drivers/media/i2c/ov2680.c dev_err(&client->dev, "write error: reg=0x%4x: %d\n", reg, ret); reg 227 drivers/media/i2c/ov2680.c static int __ov2680_read_reg(struct ov2680_dev *sensor, u16 reg, reg 232 drivers/media/i2c/ov2680.c u8 addr_buf[2] = { reg >> 8, reg & 0xff }; reg 251 drivers/media/i2c/ov2680.c dev_err(&client->dev, "read error: reg=0x%4x: %d\n", reg, ret); reg 269 drivers/media/i2c/ov2680.c static int ov2680_mod_reg(struct ov2680_dev *sensor, u16 reg, u8 mask, u8 val) reg 274 drivers/media/i2c/ov2680.c ret = ov2680_read_reg(sensor, reg, &readval); reg 282 drivers/media/i2c/ov2680.c return ov2680_write_reg(sensor, reg, val); reg 245 drivers/media/i2c/ov2685.c static int ov2685_write_reg(struct i2c_client *client, u16 reg, reg 256 drivers/media/i2c/ov2685.c buf[0] = reg >> 8; reg 257 drivers/media/i2c/ov2685.c buf[1] = reg & 0xff; reg 287 drivers/media/i2c/ov2685.c static int ov2685_read_reg(struct i2c_client *client, u16 reg, reg 293 drivers/media/i2c/ov2685.c __be16 reg_addr_be = cpu_to_be16(reg); reg 617 drivers/media/i2c/ov5640.c static int ov5640_write_reg(struct ov5640_dev *sensor, u16 reg, u8 val) reg 624 drivers/media/i2c/ov5640.c buf[0] = reg >> 8; reg 625 drivers/media/i2c/ov5640.c buf[1] = reg & 0xff; reg 636 drivers/media/i2c/ov5640.c __func__, reg, val); reg 643 drivers/media/i2c/ov5640.c static int ov5640_read_reg(struct ov5640_dev *sensor, u16 reg, u8 *val) reg 650 drivers/media/i2c/ov5640.c buf[0] = reg >> 8; reg 651 drivers/media/i2c/ov5640.c buf[1] = reg & 0xff; reg 666 drivers/media/i2c/ov5640.c __func__, reg); reg 674 drivers/media/i2c/ov5640.c static int ov5640_read_reg16(struct ov5640_dev *sensor, u16 reg, u16 *val) reg 679 drivers/media/i2c/ov5640.c ret = ov5640_read_reg(sensor, reg, &hi); reg 682 drivers/media/i2c/ov5640.c ret = ov5640_read_reg(sensor, reg + 1, &lo); reg 690 drivers/media/i2c/ov5640.c static int ov5640_write_reg16(struct ov5640_dev *sensor, u16 reg, u16 val) reg 694 drivers/media/i2c/ov5640.c ret = ov5640_write_reg(sensor, reg, val >> 8); reg 698 drivers/media/i2c/ov5640.c return ov5640_write_reg(sensor, reg + 1, val & 0xff); reg 701 drivers/media/i2c/ov5640.c static int ov5640_mod_reg(struct ov5640_dev *sensor, u16 reg, reg 707 drivers/media/i2c/ov5640.c ret = ov5640_read_reg(sensor, reg, &readval); reg 715 drivers/media/i2c/ov5640.c return ov5640_write_reg(sensor, reg, val); reg 74 drivers/media/i2c/ov5645.c u16 reg; reg 544 drivers/media/i2c/ov5645.c static int ov5645_write_reg(struct ov5645 *ov5645, u16 reg, u8 val) reg 549 drivers/media/i2c/ov5645.c regbuf[0] = reg >> 8; reg 550 drivers/media/i2c/ov5645.c regbuf[1] = reg & 0xff; reg 556 drivers/media/i2c/ov5645.c __func__, ret, reg, val); reg 563 drivers/media/i2c/ov5645.c static int ov5645_read_reg(struct ov5645 *ov5645, u16 reg, u8 *val) reg 568 drivers/media/i2c/ov5645.c regbuf[0] = reg >> 8; reg 569 drivers/media/i2c/ov5645.c regbuf[1] = reg & 0xff; reg 574 drivers/media/i2c/ov5645.c __func__, ret, reg); reg 581 drivers/media/i2c/ov5645.c __func__, ret, reg); reg 630 drivers/media/i2c/ov5645.c ret = ov5645_write_reg(ov5645, settings->reg, settings->val); reg 199 drivers/media/i2c/ov5647.c static int ov5647_write(struct v4l2_subdev *sd, u16 reg, u8 val) reg 202 drivers/media/i2c/ov5647.c unsigned char data[3] = { reg >> 8, reg & 0xff, val}; reg 208 drivers/media/i2c/ov5647.c __func__, reg); reg 213 drivers/media/i2c/ov5647.c static int ov5647_read(struct v4l2_subdev *sd, u16 reg, u8 *val) reg 216 drivers/media/i2c/ov5647.c unsigned char data_w[2] = { reg >> 8, reg & 0xff }; reg 222 drivers/media/i2c/ov5647.c __func__, reg); reg 229 drivers/media/i2c/ov5647.c __func__, reg); reg 409 drivers/media/i2c/ov5647.c struct v4l2_dbg_register *reg) reg 414 drivers/media/i2c/ov5647.c ret = ov5647_read(sd, reg->reg & 0xff, &val); reg 418 drivers/media/i2c/ov5647.c reg->val = val; reg 419 drivers/media/i2c/ov5647.c reg->size = 1; reg 425 drivers/media/i2c/ov5647.c const struct v4l2_dbg_register *reg) reg 427 drivers/media/i2c/ov5647.c return ov5647_write(sd, reg->reg & 0xff, reg->val & 0xff); reg 1839 drivers/media/i2c/ov5670.c static int ov5670_read_reg(struct ov5670 *ov5670, u16 reg, unsigned int len, reg 1846 drivers/media/i2c/ov5670.c __be16 reg_addr_be = cpu_to_be16(reg); reg 1875 drivers/media/i2c/ov5670.c static int ov5670_write_reg(struct ov5670 *ov5670, u16 reg, unsigned int len, reg 1888 drivers/media/i2c/ov5670.c buf[0] = reg >> 8; reg 1889 drivers/media/i2c/ov5670.c buf[1] = reg & 0xff; reg 512 drivers/media/i2c/ov5675.c static int ov5675_read_reg(struct ov5675 *ov5675, u16 reg, u16 len, u32 *val) reg 523 drivers/media/i2c/ov5675.c put_unaligned_be16(reg, addr_buf); reg 542 drivers/media/i2c/ov5675.c static int ov5675_write_reg(struct ov5675 *ov5675, u16 reg, u16 len, u32 val) reg 550 drivers/media/i2c/ov5675.c put_unaligned_be16(reg, buf); reg 705 drivers/media/i2c/ov5695.c static int ov5695_write_reg(struct i2c_client *client, u16 reg, reg 716 drivers/media/i2c/ov5695.c buf[0] = reg >> 8; reg 717 drivers/media/i2c/ov5695.c buf[1] = reg & 0xff; reg 747 drivers/media/i2c/ov5695.c static int ov5695_read_reg(struct i2c_client *client, u16 reg, unsigned int len, reg 753 drivers/media/i2c/ov5695.c __be16 reg_addr_be = cpu_to_be16(reg); reg 174 drivers/media/i2c/ov6650.c u8 reg; reg 228 drivers/media/i2c/ov6650.c static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val) reg 231 drivers/media/i2c/ov6650.c u8 data = reg; reg 252 drivers/media/i2c/ov6650.c dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg); reg 257 drivers/media/i2c/ov6650.c static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val) reg 260 drivers/media/i2c/ov6650.c unsigned char data[2] = { reg, val }; reg 272 drivers/media/i2c/ov6650.c dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg); reg 280 drivers/media/i2c/ov6650.c static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask) reg 285 drivers/media/i2c/ov6650.c ret = ov6650_reg_read(client, reg, &val); reg 289 drivers/media/i2c/ov6650.c reg); reg 296 drivers/media/i2c/ov6650.c ret = ov6650_reg_write(client, reg, val); reg 300 drivers/media/i2c/ov6650.c reg); reg 322 drivers/media/i2c/ov6650.c uint8_t reg, reg2; reg 327 drivers/media/i2c/ov6650.c ret = ov6650_reg_read(client, REG_GAIN, ®); reg 329 drivers/media/i2c/ov6650.c priv->gain->val = reg; reg 332 drivers/media/i2c/ov6650.c ret = ov6650_reg_read(client, REG_BLUE, ®); reg 336 drivers/media/i2c/ov6650.c priv->blue->val = reg; reg 341 drivers/media/i2c/ov6650.c ret = ov6650_reg_read(client, REG_AECH, ®); reg 343 drivers/media/i2c/ov6650.c priv->exposure->val = reg; reg 404 drivers/media/i2c/ov6650.c struct v4l2_dbg_register *reg) reg 410 drivers/media/i2c/ov6650.c if (reg->reg & ~0xff) reg 413 drivers/media/i2c/ov6650.c reg->size = 1; reg 415 drivers/media/i2c/ov6650.c ret = ov6650_reg_read(client, reg->reg, &val); reg 417 drivers/media/i2c/ov6650.c reg->val = (__u64)val; reg 423 drivers/media/i2c/ov6650.c const struct v4l2_dbg_register *reg) reg 427 drivers/media/i2c/ov6650.c if (reg->reg & ~0xff || reg->val & ~0xff) reg 430 drivers/media/i2c/ov6650.c return ov6650_reg_write(client, reg->reg, reg->val); reg 46 drivers/media/i2c/ov7251.c u16 reg; reg 624 drivers/media/i2c/ov7251.c static int ov7251_write_reg(struct ov7251 *ov7251, u16 reg, u8 val) reg 629 drivers/media/i2c/ov7251.c regbuf[0] = reg >> 8; reg 630 drivers/media/i2c/ov7251.c regbuf[1] = reg & 0xff; reg 636 drivers/media/i2c/ov7251.c __func__, ret, reg, val); reg 643 drivers/media/i2c/ov7251.c static int ov7251_write_seq_regs(struct ov7251 *ov7251, u16 reg, u8 *val, reg 647 drivers/media/i2c/ov7251.c u8 nregbuf = sizeof(reg) + num * sizeof(*val); reg 653 drivers/media/i2c/ov7251.c regbuf[0] = reg >> 8; reg 654 drivers/media/i2c/ov7251.c regbuf[1] = reg & 0xff; reg 662 drivers/media/i2c/ov7251.c __func__, ret, reg); reg 669 drivers/media/i2c/ov7251.c static int ov7251_read_reg(struct ov7251 *ov7251, u16 reg, u8 *val) reg 674 drivers/media/i2c/ov7251.c regbuf[0] = reg >> 8; reg 675 drivers/media/i2c/ov7251.c regbuf[1] = reg & 0xff; reg 680 drivers/media/i2c/ov7251.c __func__, ret, reg); reg 687 drivers/media/i2c/ov7251.c __func__, ret, reg); reg 696 drivers/media/i2c/ov7251.c u16 reg; reg 699 drivers/media/i2c/ov7251.c reg = OV7251_AEC_EXPO_0; reg 704 drivers/media/i2c/ov7251.c return ov7251_write_seq_regs(ov7251, reg, val, 3); reg 709 drivers/media/i2c/ov7251.c u16 reg; reg 712 drivers/media/i2c/ov7251.c reg = OV7251_AEC_AGC_ADJ_0; reg 716 drivers/media/i2c/ov7251.c return ov7251_write_seq_regs(ov7251, reg, val, 2); reg 727 drivers/media/i2c/ov7251.c ret = ov7251_write_reg(ov7251, settings->reg, settings->val); reg 478 drivers/media/i2c/ov7670.c static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg, reg 484 drivers/media/i2c/ov7670.c ret = i2c_smbus_read_byte_data(client, reg); reg 493 drivers/media/i2c/ov7670.c static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg, reg 497 drivers/media/i2c/ov7670.c int ret = i2c_smbus_write_byte_data(client, reg, value); reg 499 drivers/media/i2c/ov7670.c if (reg == REG_COM7 && (value & COM7_RESET)) reg 507 drivers/media/i2c/ov7670.c static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg, reg 511 drivers/media/i2c/ov7670.c u8 data = reg; reg 540 drivers/media/i2c/ov7670.c static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg, reg 545 drivers/media/i2c/ov7670.c unsigned char data[2] = { reg, value }; reg 555 drivers/media/i2c/ov7670.c if (reg == REG_COM7 && (value & COM7_RESET)) reg 560 drivers/media/i2c/ov7670.c static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg, reg 565 drivers/media/i2c/ov7670.c return ov7670_read_smbus(sd, reg, value); reg 567 drivers/media/i2c/ov7670.c return ov7670_read_i2c(sd, reg, value); reg 570 drivers/media/i2c/ov7670.c static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg, reg 575 drivers/media/i2c/ov7670.c return ov7670_write_smbus(sd, reg, value); reg 577 drivers/media/i2c/ov7670.c return ov7670_write_i2c(sd, reg, value); reg 580 drivers/media/i2c/ov7670.c static int ov7670_update_bits(struct v4l2_subdev *sd, unsigned char reg, reg 586 drivers/media/i2c/ov7670.c ret = ov7670_read(sd, reg, &orig); reg 590 drivers/media/i2c/ov7670.c return ov7670_write(sd, reg, (orig & ~mask) | (value & mask)); reg 1620 drivers/media/i2c/ov7670.c static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) reg 1625 drivers/media/i2c/ov7670.c ret = ov7670_read(sd, reg->reg & 0xff, &val); reg 1626 drivers/media/i2c/ov7670.c reg->val = val; reg 1627 drivers/media/i2c/ov7670.c reg->size = 1; reg 1631 drivers/media/i2c/ov7670.c static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) reg 1633 drivers/media/i2c/ov7670.c ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff); reg 810 drivers/media/i2c/ov772x.c struct v4l2_dbg_register *reg) reg 816 drivers/media/i2c/ov772x.c reg->size = 1; reg 817 drivers/media/i2c/ov772x.c if (reg->reg > 0xff) reg 820 drivers/media/i2c/ov772x.c ret = regmap_read(priv->regmap, reg->reg, &val); reg 824 drivers/media/i2c/ov772x.c reg->val = (__u64)val; reg 830 drivers/media/i2c/ov772x.c const struct v4l2_dbg_register *reg) reg 834 drivers/media/i2c/ov772x.c if (reg->reg > 0xff || reg 835 drivers/media/i2c/ov772x.c reg->val > 0xff) reg 838 drivers/media/i2c/ov772x.c return regmap_write(priv->regmap, reg->reg, reg->val); reg 271 drivers/media/i2c/ov7740.c struct v4l2_dbg_register *reg) reg 278 drivers/media/i2c/ov7740.c ret = regmap_read(regmap, reg->reg & 0xff, &val); reg 279 drivers/media/i2c/ov7740.c reg->val = val; reg 280 drivers/media/i2c/ov7740.c reg->size = 1; reg 286 drivers/media/i2c/ov7740.c const struct v4l2_dbg_register *reg) reg 291 drivers/media/i2c/ov7740.c regmap_write(regmap, reg->reg & 0xff, reg->val & 0xff); reg 395 drivers/media/i2c/ov7740.c unsigned int reg; reg 398 drivers/media/i2c/ov7740.c ret = regmap_read(regmap, REG_REG13, ®); reg 402 drivers/media/i2c/ov7740.c reg |= REG13_AGC_EN; reg 404 drivers/media/i2c/ov7740.c reg &= ~REG13_AGC_EN; reg 405 drivers/media/i2c/ov7740.c return regmap_write(regmap, REG_REG13, reg); reg 492 drivers/media/i2c/ov7740.c unsigned int reg; reg 495 drivers/media/i2c/ov7740.c ret = regmap_read(regmap, REG_REG13, ®); reg 498 drivers/media/i2c/ov7740.c reg |= (REG13_AEC_EN | REG13_AGC_EN); reg 500 drivers/media/i2c/ov7740.c reg &= ~(REG13_AEC_EN | REG13_AGC_EN); reg 501 drivers/media/i2c/ov7740.c ret = regmap_write(regmap, REG_REG13, reg); reg 604 drivers/media/i2c/ov8856.c static int ov8856_read_reg(struct ov8856 *ov8856, u16 reg, u16 len, u32 *val) reg 615 drivers/media/i2c/ov8856.c put_unaligned_be16(reg, addr_buf); reg 634 drivers/media/i2c/ov8856.c static int ov8856_write_reg(struct ov8856 *ov8856, u16 reg, u16 len, u32 val) reg 642 drivers/media/i2c/ov8856.c put_unaligned_be16(reg, buf); reg 171 drivers/media/i2c/ov9640.c static int ov9640_reg_read(struct i2c_client *client, u8 reg, u8 *val) reg 174 drivers/media/i2c/ov9640.c u8 data = reg; reg 195 drivers/media/i2c/ov9640.c dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg); reg 200 drivers/media/i2c/ov9640.c static int ov9640_reg_write(struct i2c_client *client, u8 reg, u8 val) reg 204 drivers/media/i2c/ov9640.c unsigned char data[2] = { reg, val }; reg 214 drivers/media/i2c/ov9640.c dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg); reg 219 drivers/media/i2c/ov9640.c ret = ov9640_reg_read(client, reg, &_val); reg 222 drivers/media/i2c/ov9640.c "Failed reading back register 0x%02x!\n", reg); reg 229 drivers/media/i2c/ov9640.c static int ov9640_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 unset) reg 234 drivers/media/i2c/ov9640.c ret = ov9640_reg_read(client, reg, &val); reg 237 drivers/media/i2c/ov9640.c "[Read]-Modify-Write of register %02x failed!\n", reg); reg 244 drivers/media/i2c/ov9640.c ret = ov9640_reg_write(client, reg, val); reg 247 drivers/media/i2c/ov9640.c "Read-Modify-[Write] of register %02x failed!\n", reg); reg 296 drivers/media/i2c/ov9640.c struct v4l2_dbg_register *reg) reg 302 drivers/media/i2c/ov9640.c if (reg->reg & ~0xff) reg 305 drivers/media/i2c/ov9640.c reg->size = 1; reg 307 drivers/media/i2c/ov9640.c ret = ov9640_reg_read(client, reg->reg, &val); reg 311 drivers/media/i2c/ov9640.c reg->val = (__u64)val; reg 317 drivers/media/i2c/ov9640.c const struct v4l2_dbg_register *reg) reg 321 drivers/media/i2c/ov9640.c if (reg->reg & ~0xff || reg->val & ~0xff) reg 324 drivers/media/i2c/ov9640.c return ov9640_reg_write(client, reg->reg, reg->val); reg 452 drivers/media/i2c/ov9640.c switch (ov9640_regs[i].reg) { reg 467 drivers/media/i2c/ov9640.c ret = ov9640_reg_write(client, ov9640_regs[i].reg, val); reg 474 drivers/media/i2c/ov9640.c ret = ov9640_reg_write(client, matrix_regs[i].reg, reg 490 drivers/media/i2c/ov9640.c ret = ov9640_reg_write(client, ov9640_regs_dflt[i].reg, reg 192 drivers/media/i2c/ov9640.h u8 reg; reg 598 drivers/media/i2c/ov9650.c u8 reg; reg 600 drivers/media/i2c/ov9650.c ret = ov965x_read(ov965x, REG_COM8, ®); reg 603 drivers/media/i2c/ov9650.c reg &= ~COM8_BFILT; reg 605 drivers/media/i2c/ov9650.c reg |= COM8_BFILT; reg 606 drivers/media/i2c/ov9650.c ret = ov965x_write(ov965x, REG_COM8, reg); reg 628 drivers/media/i2c/ov9650.c u8 reg; reg 630 drivers/media/i2c/ov9650.c ret = ov965x_read(ov965x, REG_COM8, ®); reg 632 drivers/media/i2c/ov9650.c reg = awb ? reg | REG_COM8 : reg & ~REG_COM8; reg 633 drivers/media/i2c/ov9650.c ret = ov965x_write(ov965x, REG_COM8, reg); reg 677 drivers/media/i2c/ov9650.c u8 reg; reg 683 drivers/media/i2c/ov9650.c ret = ov965x_read(ov965x, REG_COM8, ®); reg 687 drivers/media/i2c/ov9650.c reg |= COM8_AGC; reg 689 drivers/media/i2c/ov9650.c reg &= ~COM8_AGC; reg 690 drivers/media/i2c/ov9650.c ret = ov965x_write(ov965x, REG_COM8, reg); reg 717 drivers/media/i2c/ov9650.c ret = ov965x_read(ov965x, REG_VREF, ®); reg 720 drivers/media/i2c/ov9650.c reg &= ~VREF_GAIN_MASK; reg 721 drivers/media/i2c/ov9650.c reg |= (((rgain >> 8) & 0x3) << 6); reg 722 drivers/media/i2c/ov9650.c ret = ov965x_write(ov965x, REG_VREF, reg); reg 766 drivers/media/i2c/ov9650.c u8 reg; reg 769 drivers/media/i2c/ov9650.c ret = ov965x_read(ov965x, REG_COM8, ®); reg 773 drivers/media/i2c/ov9650.c reg |= (COM8_AEC | COM8_AGC); reg 775 drivers/media/i2c/ov9650.c reg &= ~(COM8_AEC | COM8_AGC); reg 776 drivers/media/i2c/ov9650.c ret = ov965x_write(ov965x, REG_COM8, reg); reg 848 drivers/media/i2c/ov9650.c u8 reg; reg 850 drivers/media/i2c/ov9650.c ret = ov965x_read(ov965x, REG_COM23, ®); reg 853 drivers/media/i2c/ov9650.c reg = value ? reg | COM23_TEST_MODE : reg & ~COM23_TEST_MODE; reg 854 drivers/media/i2c/ov9650.c return ov965x_write(ov965x, REG_COM23, reg); reg 1281 drivers/media/i2c/ov9650.c u8 reg; reg 1284 drivers/media/i2c/ov9650.c reg = DEF_CLKRC + ov965x->fiv->clkrc_div; reg 1285 drivers/media/i2c/ov9650.c ret = ov965x_write(ov965x, REG_CLKRC, reg); reg 1291 drivers/media/i2c/ov9650.c ret = ov965x_read(ov965x, REG_TSLB, ®); reg 1294 drivers/media/i2c/ov9650.c reg &= ~TSLB_YUYV_MASK; reg 1295 drivers/media/i2c/ov9650.c reg |= ov965x->tslb_reg; reg 1296 drivers/media/i2c/ov9650.c ret = ov965x_write(ov965x, REG_TSLB, reg); reg 1310 drivers/media/i2c/ov9650.c ret = ov965x_read(ov965x, REG_COM11, ®); reg 1312 drivers/media/i2c/ov9650.c reg |= COM11_BANDING; reg 1313 drivers/media/i2c/ov9650.c ret = ov965x_write(ov965x, REG_COM11, reg); reg 170 drivers/media/i2c/rj54n1cb0c.c u16 reg; reg 430 drivers/media/i2c/rj54n1cb0c.c static int reg_read(struct i2c_client *client, const u16 reg) reg 436 drivers/media/i2c/rj54n1cb0c.c if (rj54n1->bank != reg >> 8) { reg 437 drivers/media/i2c/rj54n1cb0c.c dev_dbg(&client->dev, "[0x%x] = 0x%x\n", 0xff, reg >> 8); reg 438 drivers/media/i2c/rj54n1cb0c.c ret = i2c_smbus_write_byte_data(client, 0xff, reg >> 8); reg 441 drivers/media/i2c/rj54n1cb0c.c rj54n1->bank = reg >> 8; reg 443 drivers/media/i2c/rj54n1cb0c.c return i2c_smbus_read_byte_data(client, reg & 0xff); reg 446 drivers/media/i2c/rj54n1cb0c.c static int reg_write(struct i2c_client *client, const u16 reg, reg 453 drivers/media/i2c/rj54n1cb0c.c if (rj54n1->bank != reg >> 8) { reg 454 drivers/media/i2c/rj54n1cb0c.c dev_dbg(&client->dev, "[0x%x] = 0x%x\n", 0xff, reg >> 8); reg 455 drivers/media/i2c/rj54n1cb0c.c ret = i2c_smbus_write_byte_data(client, 0xff, reg >> 8); reg 458 drivers/media/i2c/rj54n1cb0c.c rj54n1->bank = reg >> 8; reg 460 drivers/media/i2c/rj54n1cb0c.c dev_dbg(&client->dev, "[0x%x] = 0x%x\n", reg & 0xff, data); reg 461 drivers/media/i2c/rj54n1cb0c.c return i2c_smbus_write_byte_data(client, reg & 0xff, data); reg 464 drivers/media/i2c/rj54n1cb0c.c static int reg_set(struct i2c_client *client, const u16 reg, reg 469 drivers/media/i2c/rj54n1cb0c.c ret = reg_read(client, reg); reg 472 drivers/media/i2c/rj54n1cb0c.c return reg_write(client, reg, (ret & ~mask) | (data & mask)); reg 481 drivers/media/i2c/rj54n1cb0c.c ret = reg_write(client, rv->reg, rv->val); reg 1130 drivers/media/i2c/rj54n1cb0c.c struct v4l2_dbg_register *reg) reg 1134 drivers/media/i2c/rj54n1cb0c.c if (reg->reg < 0x400 || reg->reg > 0x1fff) reg 1138 drivers/media/i2c/rj54n1cb0c.c reg->size = 1; reg 1139 drivers/media/i2c/rj54n1cb0c.c reg->val = reg_read(client, reg->reg); reg 1141 drivers/media/i2c/rj54n1cb0c.c if (reg->val > 0xff) reg 1148 drivers/media/i2c/rj54n1cb0c.c const struct v4l2_dbg_register *reg) reg 1152 drivers/media/i2c/rj54n1cb0c.c if (reg->reg < 0x400 || reg->reg > 0x1fff) reg 1156 drivers/media/i2c/rj54n1cb0c.c if (reg_write(client, reg->reg, reg->val) < 0) reg 466 drivers/media/i2c/s5c73m3/s5c73m3-core.c u16 reg = 0; reg 469 drivers/media/i2c/s5c73m3/s5c73m3-core.c int ret = s5c73m3_read(state, 0x30100010, ®); reg 472 drivers/media/i2c/s5c73m3/s5c73m3-core.c if (reg == value) reg 33 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c u16 reg = REG_AF_STATUS_UNFOCUSED; reg 35 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c int ret = s5c73m3_read(state, REG_AF_STATUS, ®); reg 37 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c switch (reg) { reg 48 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c v4l2_info(&state->sensor_sd, "Unknown AF status %#x\n", reg); reg 238 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c u16 reg = (val < 0) ? -val + 2 : val; reg 239 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c return s5c73m3_isp_command(state, COMM_CONTRAST, reg); reg 244 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c u16 reg = (val < 0) ? -val + 2 : val; reg 245 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c return s5c73m3_isp_command(state, COMM_SATURATION, reg); reg 250 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c u16 reg = (val < 0) ? -val + 2 : val; reg 251 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c return s5c73m3_isp_command(state, COMM_SHARPNESS, reg); reg 278 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c int reg; reg 281 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c reg = COMM_IMAGE_QUALITY_NORMAL; reg 283 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c reg = COMM_IMAGE_QUALITY_FINE; reg 285 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c reg = COMM_IMAGE_QUALITY_SUPERFINE; reg 287 drivers/media/i2c/s5c73m3/s5c73m3-ctrls.c return s5c73m3_isp_command(state, COMM_IMAGE_QUALITY, reg); reg 543 drivers/media/i2c/s5k5baf.c u16 reg; reg 547 drivers/media/i2c/s5k5baf.c reg = s5k5baf_read(state, addr); reg 548 drivers/media/i2c/s5k5baf.c if (state->error || !reg) reg 480 drivers/media/i2c/s5k6aa.c u16 reg; reg 482 drivers/media/i2c/s5k6aa.c int ret = s5k6aa_read(c, REG_DBG_AUTOALG_EN, ®); reg 502 drivers/media/i2c/s5k6aa.c reg = awb ? reg | AALG_WB_EN_MASK : reg & ~AALG_WB_EN_MASK; reg 503 drivers/media/i2c/s5k6aa.c ret = s5k6aa_write(c, REG_DBG_AUTOALG_EN, reg); reg 703 drivers/media/i2c/s5k6aa.c u16 reg = 1; reg 715 drivers/media/i2c/s5k6aa.c ret = s5k6aa_read(client, REG_G_NEW_CFG_SYNC, ®); reg 716 drivers/media/i2c/s5k6aa.c if (!reg) reg 289 drivers/media/i2c/saa6752hs.c static inline void set_reg8(struct i2c_client *client, uint8_t reg, uint8_t val) reg 293 drivers/media/i2c/saa6752hs.c buf[0] = reg; reg 298 drivers/media/i2c/saa6752hs.c static inline void set_reg16(struct i2c_client *client, uint8_t reg, uint16_t val) reg 302 drivers/media/i2c/saa6752hs.c buf[0] = reg; reg 44 drivers/media/i2c/saa7110.c u8 reg[SAA7110_NR_REG]; reg 67 drivers/media/i2c/saa7110.c static int saa7110_write(struct v4l2_subdev *sd, u8 reg, u8 value) reg 72 drivers/media/i2c/saa7110.c decoder->reg[reg] = value; reg 73 drivers/media/i2c/saa7110.c return i2c_smbus_write_byte_data(client, reg, value); reg 81 drivers/media/i2c/saa7110.c u8 reg = *data; /* first register to write to */ reg 84 drivers/media/i2c/saa7110.c if (reg + (len - 1) > SAA7110_NR_REG) reg 93 drivers/media/i2c/saa7110.c memcpy(decoder->reg + reg, data + 1, len - 1); reg 96 drivers/media/i2c/saa7110.c ret = saa7110_write(sd, reg++, *data++); reg 109 drivers/media/i2c/saa7115.c static inline int saa711x_write(struct v4l2_subdev *sd, u8 reg, u8 value) reg 113 drivers/media/i2c/saa7115.c return i2c_smbus_write_byte_data(client, reg, value); reg 117 drivers/media/i2c/saa7115.c static int saa711x_has_reg(const int id, const u8 reg) reg 120 drivers/media/i2c/saa7115.c return reg < 0x20 && reg != 0x01 && reg != 0x0f && reg 121 drivers/media/i2c/saa7115.c (reg < 0x13 || reg > 0x19) && reg != 0x1d && reg != 0x1e; reg 123 drivers/media/i2c/saa7115.c return reg < 0x20 && reg != 0x01 && reg != 0x0f && reg 124 drivers/media/i2c/saa7115.c reg != 0x14 && reg != 0x18 && reg != 0x19 && reg 125 drivers/media/i2c/saa7115.c reg != 0x1d && reg != 0x1e; reg 128 drivers/media/i2c/saa7115.c if (unlikely((reg >= 0x3b && reg <= 0x3f) || reg == 0x5c || reg == 0x5f || reg 129 drivers/media/i2c/saa7115.c reg == 0xa3 || reg == 0xa7 || reg == 0xab || reg == 0xaf || (reg >= 0xb5 && reg <= 0xb7) || reg 130 drivers/media/i2c/saa7115.c reg == 0xd3 || reg == 0xd7 || reg == 0xdb || reg == 0xdf || (reg >= 0xe5 && reg <= 0xe7) || reg 131 drivers/media/i2c/saa7115.c reg == 0x82 || (reg >= 0x89 && reg <= 0x8e))) reg 136 drivers/media/i2c/saa7115.c return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && reg < 0x20; reg 138 drivers/media/i2c/saa7115.c return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && (reg < 0x20 || reg > 0x3f) && reg 139 drivers/media/i2c/saa7115.c reg != 0x5d && reg < 0x63; reg 141 drivers/media/i2c/saa7115.c return (reg < 0x1a || reg > 0x1e) && (reg < 0x20 || reg > 0x2f) && reg 142 drivers/media/i2c/saa7115.c (reg < 0x63 || reg > 0x7f) && reg != 0x33 && reg != 0x37 && reg 143 drivers/media/i2c/saa7115.c reg != 0x81 && reg < 0xf0; reg 145 drivers/media/i2c/saa7115.c return (reg < 0x20 || reg > 0x2f) && reg != 0x65 && (reg < 0xfc || reg > 0xfe); reg 147 drivers/media/i2c/saa7115.c return (reg < 0x1a || reg > 0x1d) && (reg < 0x20 || reg > 0x22) && reg 148 drivers/media/i2c/saa7115.c (reg < 0x26 || reg > 0x28) && reg != 0x33 && reg != 0x37 && reg 149 drivers/media/i2c/saa7115.c (reg < 0x63 || reg > 0x7f) && reg != 0x81 && reg < 0xf0; reg 157 drivers/media/i2c/saa7115.c unsigned char reg, data; reg 160 drivers/media/i2c/saa7115.c reg = *(regs++); reg 165 drivers/media/i2c/saa7115.c if (saa711x_has_reg(state->ident, reg)) { reg 166 drivers/media/i2c/saa7115.c if (saa711x_write(sd, reg, data) < 0) reg 169 drivers/media/i2c/saa7115.c v4l2_dbg(1, debug, sd, "tried to access reserved reg 0x%02x\n", reg); reg 175 drivers/media/i2c/saa7115.c static inline int saa711x_read(struct v4l2_subdev *sd, u8 reg) reg 179 drivers/media/i2c/saa7115.c return i2c_smbus_read_byte_data(client, reg); reg 990 drivers/media/i2c/saa7115.c u8 reg = saa711x_read(sd, R_08_SYNC_CNTL); reg 991 drivers/media/i2c/saa7115.c reg &= ~(SAA7113_R_08_FSEL | SAA7113_R_08_AUFD); reg 992 drivers/media/i2c/saa7115.c reg |= SAA7113_R_08_FSEL; reg 993 drivers/media/i2c/saa7115.c saa711x_write(sd, R_08_SYNC_CNTL, reg); reg 1001 drivers/media/i2c/saa7115.c u8 reg = saa711x_read(sd, R_08_SYNC_CNTL); reg 1002 drivers/media/i2c/saa7115.c reg &= ~(SAA7113_R_08_FSEL | SAA7113_R_08_AUFD); reg 1003 drivers/media/i2c/saa7115.c saa711x_write(sd, R_08_SYNC_CNTL, reg); reg 1021 drivers/media/i2c/saa7115.c u8 reg = saa711x_read(sd, R_0E_CHROMA_CNTL_1) & 0x8f; reg 1024 drivers/media/i2c/saa7115.c reg |= 0x30; reg 1026 drivers/media/i2c/saa7115.c reg |= 0x20; reg 1028 drivers/media/i2c/saa7115.c reg |= 0x10; reg 1030 drivers/media/i2c/saa7115.c reg |= 0x40; reg 1032 drivers/media/i2c/saa7115.c reg |= 0x50; reg 1034 drivers/media/i2c/saa7115.c saa711x_write(sd, R_0E_CHROMA_CNTL_1, reg); reg 1507 drivers/media/i2c/saa7115.c static int saa711x_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) reg 1509 drivers/media/i2c/saa7115.c reg->val = saa711x_read(sd, reg->reg & 0xff); reg 1510 drivers/media/i2c/saa7115.c reg->size = 1; reg 1514 drivers/media/i2c/saa7115.c static int saa711x_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) reg 1516 drivers/media/i2c/saa7115.c saa711x_write(sd, reg->reg & 0xff, reg->val & 0xff); reg 218 drivers/media/i2c/saa711x_regs.h u8 reg; reg 121 drivers/media/i2c/saa7127.c unsigned char reg; reg 302 drivers/media/i2c/saa7127.c static int saa7127_read(struct v4l2_subdev *sd, u8 reg) reg 306 drivers/media/i2c/saa7127.c return i2c_smbus_read_byte_data(client, reg); reg 311 drivers/media/i2c/saa7127.c static int saa7127_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 317 drivers/media/i2c/saa7127.c if (i2c_smbus_write_byte_data(client, reg, val) == 0) reg 329 drivers/media/i2c/saa7127.c while (regs->reg != 0) { reg 330 drivers/media/i2c/saa7127.c saa7127_write(sd, regs->reg, regs->value); reg 653 drivers/media/i2c/saa7127.c static int saa7127_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) reg 655 drivers/media/i2c/saa7127.c reg->val = saa7127_read(sd, reg->reg & 0xff); reg 656 drivers/media/i2c/saa7127.c reg->size = 1; reg 660 drivers/media/i2c/saa7127.c static int saa7127_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) reg 662 drivers/media/i2c/saa7127.c saa7127_write(sd, reg->reg & 0xff, reg->val & 0xff); reg 86 drivers/media/i2c/saa717x.c static int saa717x_write(struct v4l2_subdev *sd, u32 reg, u32 value) reg 90 drivers/media/i2c/saa717x.c int fw_addr = reg == 0x454 || (reg >= 0x464 && reg <= 0x478) || reg == 0x480 || reg == 0x488; reg 96 drivers/media/i2c/saa717x.c mm1[0] = (reg >> 8) & 0xff; reg 97 drivers/media/i2c/saa717x.c mm1[1] = reg & 0xff; reg 108 drivers/media/i2c/saa717x.c v4l2_dbg(2, debug, sd, "wrote: reg 0x%03x=%08x\n", reg, value); reg 120 drivers/media/i2c/saa717x.c static u32 saa717x_read(struct v4l2_subdev *sd, u32 reg) reg 124 drivers/media/i2c/saa717x.c int fw_addr = (reg >= 0x404 && reg <= 0x4b8) || reg == 0x528; reg 133 drivers/media/i2c/saa717x.c mm1[0] = (reg >> 8) & 0xff; reg 134 drivers/media/i2c/saa717x.c mm1[1] = reg & 0xff; reg 146 drivers/media/i2c/saa717x.c v4l2_dbg(2, debug, sd, "read: reg 0x%03x=0x%08x\n", reg, value); reg 965 drivers/media/i2c/saa717x.c static int saa717x_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) reg 967 drivers/media/i2c/saa717x.c reg->val = saa717x_read(sd, reg->reg); reg 968 drivers/media/i2c/saa717x.c reg->size = 1; reg 972 drivers/media/i2c/saa717x.c static int saa717x_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) reg 974 drivers/media/i2c/saa717x.c u16 addr = reg->reg & 0xffff; reg 975 drivers/media/i2c/saa717x.c u8 val = reg->val & 0xff; reg 36 drivers/media/i2c/saa7185.c unsigned char reg[128]; reg 55 drivers/media/i2c/saa7185.c static int saa7185_write(struct v4l2_subdev *sd, u8 reg, u8 value) reg 60 drivers/media/i2c/saa7185.c v4l2_dbg(1, debug, sd, "%02x set to %02x\n", reg, value); reg 61 drivers/media/i2c/saa7185.c encoder->reg[reg] = value; reg 62 drivers/media/i2c/saa7185.c return i2c_smbus_write_byte_data(client, reg, value); reg 71 drivers/media/i2c/saa7185.c u8 reg; reg 82 drivers/media/i2c/saa7185.c block_data[block_len++] = reg = data[0]; reg 85 drivers/media/i2c/saa7185.c encoder->reg[reg++] = data[1]; reg 88 drivers/media/i2c/saa7185.c } while (len >= 2 && data[0] == reg && block_len < 32); reg 96 drivers/media/i2c/saa7185.c reg = *data++; reg 97 drivers/media/i2c/saa7185.c ret = saa7185_write(sd, reg, *data++); reg 246 drivers/media/i2c/saa7185.c saa7185_write(sd, 0x61, (encoder->reg[0x61] & 0xf7) | 0x08); reg 254 drivers/media/i2c/saa7185.c saa7185_write(sd, 0x61, (encoder->reg[0x61] & 0xf7) | 0x00); reg 263 drivers/media/i2c/saa7185.c saa7185_write(sd, 0x61, (encoder->reg[0x61] & 0xf7) | 0x08); reg 332 drivers/media/i2c/saa7185.c saa7185_write(sd, 0x61, (encoder->reg[0x61]) | 0x40); reg 97 drivers/media/i2c/smiapp/smiapp-core.c u32 reg; reg 100 drivers/media/i2c/smiapp/smiapp-core.c reg = SMIAPP_REG_U16_FRAME_FORMAT_DESCRIPTOR_2(i); reg 101 drivers/media/i2c/smiapp/smiapp-core.c rval = smiapp_read(sensor, reg, &desc); reg 112 drivers/media/i2c/smiapp/smiapp-core.c reg = SMIAPP_REG_U32_FRAME_FORMAT_DESCRIPTOR_4(i); reg 113 drivers/media/i2c/smiapp/smiapp-core.c rval = smiapp_read(sensor, reg, &desc); reg 156 drivers/media/i2c/smiapp/smiapp-core.c "0x%8.8x %s pixels: %d %s (pixelcode %u)\n", reg, reg 15 drivers/media/i2c/smiapp/smiapp-quirk.c static int smiapp_write_8(struct smiapp_sensor *sensor, u16 reg, u8 val) reg 17 drivers/media/i2c/smiapp/smiapp-quirk.c return smiapp_write(sensor, SMIAPP_REG_MK_U8(reg), val); reg 27 drivers/media/i2c/smiapp/smiapp-quirk.c rval = smiapp_write_8(sensor, regs->reg, regs->val); reg 31 drivers/media/i2c/smiapp/smiapp-quirk.c rval, regs->reg, regs->val); reg 46 drivers/media/i2c/smiapp/smiapp-quirk.h int (*reg_access)(struct smiapp_sensor *sensor, bool write, u32 *reg, reg 54 drivers/media/i2c/smiapp/smiapp-quirk.h u16 reg; reg 63 drivers/media/i2c/smiapp/smiapp-quirk.h .reg = (u16)_reg, \ reg 67 drivers/media/i2c/smiapp/smiapp-regs.c static int ____smiapp_read(struct smiapp_sensor *sensor, u16 reg, reg 73 drivers/media/i2c/smiapp/smiapp-regs.c u16 offset = reg; reg 126 drivers/media/i2c/smiapp/smiapp-regs.c static int ____smiapp_read_8only(struct smiapp_sensor *sensor, u16 reg, reg 137 drivers/media/i2c/smiapp/smiapp-regs.c rval = ____smiapp_read(sensor, reg + i, 1, &val8); reg 150 drivers/media/i2c/smiapp/smiapp-regs.c static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val, reg 154 drivers/media/i2c/smiapp/smiapp-regs.c u8 len = SMIAPP_REG_WIDTH(reg); reg 162 drivers/media/i2c/smiapp/smiapp-regs.c rval = ____smiapp_read(sensor, SMIAPP_REG_ADDR(reg), len, val); reg 164 drivers/media/i2c/smiapp/smiapp-regs.c rval = ____smiapp_read_8only(sensor, SMIAPP_REG_ADDR(reg), len, reg 169 drivers/media/i2c/smiapp/smiapp-regs.c if (reg & SMIAPP_REG_FLAG_FLOAT) reg 175 drivers/media/i2c/smiapp/smiapp-regs.c int smiapp_read_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val) reg 178 drivers/media/i2c/smiapp/smiapp-regs.c sensor, reg, val, reg 183 drivers/media/i2c/smiapp/smiapp-regs.c static int smiapp_read_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val, reg 189 drivers/media/i2c/smiapp/smiapp-regs.c rval = smiapp_call_quirk(sensor, reg_access, false, ®, val); reg 196 drivers/media/i2c/smiapp/smiapp-regs.c return __smiapp_read(sensor, reg, val, true); reg 198 drivers/media/i2c/smiapp/smiapp-regs.c return smiapp_read_no_quirk(sensor, reg, val); reg 201 drivers/media/i2c/smiapp/smiapp-regs.c int smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val) reg 203 drivers/media/i2c/smiapp/smiapp-regs.c return smiapp_read_quirk(sensor, reg, val, false); reg 206 drivers/media/i2c/smiapp/smiapp-regs.c int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val) reg 208 drivers/media/i2c/smiapp/smiapp-regs.c return smiapp_read_quirk(sensor, reg, val, true); reg 211 drivers/media/i2c/smiapp/smiapp-regs.c int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val) reg 217 drivers/media/i2c/smiapp/smiapp-regs.c u8 flags = SMIAPP_REG_FLAGS(reg); reg 218 drivers/media/i2c/smiapp/smiapp-regs.c u8 len = SMIAPP_REG_WIDTH(reg); reg 219 drivers/media/i2c/smiapp/smiapp-regs.c u16 offset = SMIAPP_REG_ADDR(reg); reg 235 drivers/media/i2c/smiapp/smiapp-regs.c data[0] = (u8) (reg >> 8); reg 236 drivers/media/i2c/smiapp/smiapp-regs.c data[1] = (u8) (reg & 0xff); reg 284 drivers/media/i2c/smiapp/smiapp-regs.c int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val) reg 288 drivers/media/i2c/smiapp/smiapp-regs.c rval = smiapp_call_quirk(sensor, reg_access, true, ®, &val); reg 294 drivers/media/i2c/smiapp/smiapp-regs.c return smiapp_write_no_quirk(sensor, reg, val); reg 17 drivers/media/i2c/smiapp/smiapp-regs.h #define SMIAPP_REG_ADDR(reg) ((u16)reg) reg 18 drivers/media/i2c/smiapp/smiapp-regs.h #define SMIAPP_REG_WIDTH(reg) ((u8)(reg >> 16)) reg 19 drivers/media/i2c/smiapp/smiapp-regs.h #define SMIAPP_REG_FLAGS(reg) ((u8)(reg >> 24)) reg 30 drivers/media/i2c/smiapp/smiapp-regs.h int smiapp_read_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val); reg 31 drivers/media/i2c/smiapp/smiapp-regs.h int smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val); reg 32 drivers/media/i2c/smiapp/smiapp-regs.h int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val); reg 33 drivers/media/i2c/smiapp/smiapp-regs.h int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val); reg 34 drivers/media/i2c/smiapp/smiapp-regs.h int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val); reg 286 drivers/media/i2c/sr030pc30.c struct i2c_client *client, unsigned int reg) reg 289 drivers/media/i2c/sr030pc30.c u32 page = reg >> 8 & 0xFF; reg 291 drivers/media/i2c/sr030pc30.c if (info->i2c_reg_page != page && (reg & 0xFF) != 0x03) { reg 339 drivers/media/i2c/sr030pc30.c u8 reg = sleep ? 0xF1 : 0xF0; reg 343 drivers/media/i2c/sr030pc30.c ret = cam_i2c_write(sd, POWER_CTRL_REG, reg | 0x02); reg 345 drivers/media/i2c/sr030pc30.c ret = cam_i2c_write(sd, POWER_CTRL_REG, reg); reg 359 drivers/media/i2c/sr030pc30.c s32 reg = cam_i2c_read(sd, VDO_CTL2_REG); reg 360 drivers/media/i2c/sr030pc30.c if (reg < 0) reg 361 drivers/media/i2c/sr030pc30.c return reg; reg 363 drivers/media/i2c/sr030pc30.c reg &= 0x7C; reg 365 drivers/media/i2c/sr030pc30.c reg |= 0x01; reg 367 drivers/media/i2c/sr030pc30.c reg |= 0x02; reg 368 drivers/media/i2c/sr030pc30.c return cam_i2c_write(sd, VDO_CTL2_REG, reg | 0x80); reg 218 drivers/media/i2c/st-mipid02.c static int mipid02_read_reg(struct mipid02_dev *bridge, u16 reg, u8 *val) reg 225 drivers/media/i2c/st-mipid02.c buf[0] = reg >> 8; reg 226 drivers/media/i2c/st-mipid02.c buf[1] = reg & 0xff; reg 241 drivers/media/i2c/st-mipid02.c __func__, client->addr, reg, ret); reg 248 drivers/media/i2c/st-mipid02.c static int mipid02_write_reg(struct mipid02_dev *bridge, u16 reg, u8 val) reg 255 drivers/media/i2c/st-mipid02.c buf[0] = reg >> 8; reg 256 drivers/media/i2c/st-mipid02.c buf[1] = reg & 0xff; reg 267 drivers/media/i2c/st-mipid02.c __func__, reg, ret); reg 338 drivers/media/i2c/st-mipid02.c u8 reg; reg 344 drivers/media/i2c/st-mipid02.c return mipid02_read_reg(bridge, MIPID02_CLK_LANE_WR_REG1, ®); reg 113 drivers/media/i2c/tc358743.c static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) reg 118 drivers/media/i2c/tc358743.c u8 buf[2] = { reg >> 8, reg & 0xff }; reg 137 drivers/media/i2c/tc358743.c __func__, reg, client->addr); reg 141 drivers/media/i2c/tc358743.c static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n) reg 152 drivers/media/i2c/tc358743.c reg, 2 + n); reg 160 drivers/media/i2c/tc358743.c data[0] = reg >> 8; reg 161 drivers/media/i2c/tc358743.c data[1] = reg & 0xff; reg 169 drivers/media/i2c/tc358743.c __func__, reg, client->addr); reg 179 drivers/media/i2c/tc358743.c reg, data[2]); reg 183 drivers/media/i2c/tc358743.c reg, data[3], data[2]); reg 187 drivers/media/i2c/tc358743.c reg, data[5], data[4], data[3], data[2]); reg 191 drivers/media/i2c/tc358743.c n, reg); reg 195 drivers/media/i2c/tc358743.c static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n) reg 199 drivers/media/i2c/tc358743.c i2c_rd(sd, reg, (u8 __force *)&val, n); reg 204 drivers/media/i2c/tc358743.c static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n) reg 208 drivers/media/i2c/tc358743.c i2c_wr(sd, reg, (u8 __force *)&raw, n); reg 211 drivers/media/i2c/tc358743.c static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg) reg 213 drivers/media/i2c/tc358743.c return i2c_rdreg(sd, reg, 1); reg 216 drivers/media/i2c/tc358743.c static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val) reg 218 drivers/media/i2c/tc358743.c i2c_wrreg(sd, reg, val, 1); reg 221 drivers/media/i2c/tc358743.c static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg, reg 224 drivers/media/i2c/tc358743.c i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1); reg 227 drivers/media/i2c/tc358743.c static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg) reg 229 drivers/media/i2c/tc358743.c return i2c_rdreg(sd, reg, 2); reg 232 drivers/media/i2c/tc358743.c static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val) reg 234 drivers/media/i2c/tc358743.c i2c_wrreg(sd, reg, val, 2); reg 237 drivers/media/i2c/tc358743.c static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val) reg 239 drivers/media/i2c/tc358743.c i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2); reg 242 drivers/media/i2c/tc358743.c static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg) reg 244 drivers/media/i2c/tc358743.c return i2c_rdreg(sd, reg, 4); reg 247 drivers/media/i2c/tc358743.c static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val) reg 249 drivers/media/i2c/tc358743.c i2c_wrreg(sd, reg, val, 4); reg 873 drivers/media/i2c/tc358743.c u32 reg; reg 875 drivers/media/i2c/tc358743.c reg = i2c_rd32(sd, CECRCTL1); reg 877 drivers/media/i2c/tc358743.c reg |= MASK_CECOTH; reg 879 drivers/media/i2c/tc358743.c reg &= ~MASK_CECOTH; reg 880 drivers/media/i2c/tc358743.c i2c_wr32(sd, CECRCTL1, reg); reg 1366 drivers/media/i2c/tc358743.c struct v4l2_dbg_register *reg) reg 1368 drivers/media/i2c/tc358743.c if (reg->reg > 0xffff) { reg 1373 drivers/media/i2c/tc358743.c reg->size = tc358743_get_reg_size(reg->reg); reg 1375 drivers/media/i2c/tc358743.c reg->val = i2c_rdreg(sd, reg->reg, reg->size); reg 1381 drivers/media/i2c/tc358743.c const struct v4l2_dbg_register *reg) reg 1383 drivers/media/i2c/tc358743.c if (reg->reg > 0xffff) { reg 1394 drivers/media/i2c/tc358743.c if (reg->reg == HDCP_MODE || reg 1395 drivers/media/i2c/tc358743.c reg->reg == HDCP_REG1 || reg 1396 drivers/media/i2c/tc358743.c reg->reg == HDCP_REG2 || reg 1397 drivers/media/i2c/tc358743.c reg->reg == HDCP_REG3 || reg 1398 drivers/media/i2c/tc358743.c reg->reg == BCAPS) reg 1401 drivers/media/i2c/tc358743.c i2c_wrreg(sd, (u16)reg->reg, reg->val, reg 1402 drivers/media/i2c/tc358743.c tc358743_get_reg_size(reg->reg)); reg 306 drivers/media/i2c/tda1997x.c static int tda1997x_cec_read(struct v4l2_subdev *sd, u8 reg) reg 311 drivers/media/i2c/tda1997x.c val = i2c_smbus_read_byte_data(state->client_cec, reg); reg 313 drivers/media/i2c/tda1997x.c v4l_err(state->client, "read reg error: reg=%2x\n", reg); reg 320 drivers/media/i2c/tda1997x.c static int tda1997x_cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 325 drivers/media/i2c/tda1997x.c ret = i2c_smbus_write_byte_data(state->client_cec, reg, val); reg 328 drivers/media/i2c/tda1997x.c reg, val); reg 358 drivers/media/i2c/tda1997x.c static inline int io_read(struct v4l2_subdev *sd, u16 reg) reg 364 drivers/media/i2c/tda1997x.c if (tda1997x_setpage(sd, reg >> 8)) { reg 369 drivers/media/i2c/tda1997x.c val = i2c_smbus_read_byte_data(state->client, reg&0xff); reg 371 drivers/media/i2c/tda1997x.c v4l_err(state->client, "read reg error: reg=%2x\n", reg & 0xff); reg 381 drivers/media/i2c/tda1997x.c static inline long io_read16(struct v4l2_subdev *sd, u16 reg) reg 386 drivers/media/i2c/tda1997x.c val = io_read(sd, reg); reg 390 drivers/media/i2c/tda1997x.c val = io_read(sd, reg + 1); reg 398 drivers/media/i2c/tda1997x.c static inline long io_read24(struct v4l2_subdev *sd, u16 reg) reg 403 drivers/media/i2c/tda1997x.c val = io_read(sd, reg); reg 407 drivers/media/i2c/tda1997x.c val = io_read(sd, reg + 1); reg 411 drivers/media/i2c/tda1997x.c val = io_read(sd, reg + 2); reg 419 drivers/media/i2c/tda1997x.c static unsigned int io_readn(struct v4l2_subdev *sd, u16 reg, u8 len, u8 *data) reg 426 drivers/media/i2c/tda1997x.c val = io_read(sd, reg + i); reg 436 drivers/media/i2c/tda1997x.c static int io_write(struct v4l2_subdev *sd, u16 reg, u8 val) reg 442 drivers/media/i2c/tda1997x.c if (tda1997x_setpage(sd, reg >> 8)) { reg 447 drivers/media/i2c/tda1997x.c ret = i2c_smbus_write_byte_data(state->client, reg & 0xff, val); reg 450 drivers/media/i2c/tda1997x.c reg&0xff, val); reg 460 drivers/media/i2c/tda1997x.c static int io_write16(struct v4l2_subdev *sd, u16 reg, u16 val) reg 464 drivers/media/i2c/tda1997x.c ret = io_write(sd, reg, (val >> 8) & 0xff); reg 467 drivers/media/i2c/tda1997x.c ret = io_write(sd, reg + 1, val & 0xff); reg 473 drivers/media/i2c/tda1997x.c static int io_write24(struct v4l2_subdev *sd, u16 reg, u32 val) reg 477 drivers/media/i2c/tda1997x.c ret = io_write(sd, reg, (val >> 16) & 0xff); reg 480 drivers/media/i2c/tda1997x.c ret = io_write(sd, reg + 1, (val >> 8) & 0xff); reg 483 drivers/media/i2c/tda1997x.c ret = io_write(sd, reg + 2, val & 0xff); reg 659 drivers/media/i2c/tda1997x.c u8 reg; reg 705 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_VDP_CTRL); reg 706 drivers/media/i2c/tda1997x.c reg &= ~VDP_CTRL_MATRIX_BP; reg 707 drivers/media/i2c/tda1997x.c io_write(sd, REG_VDP_CTRL, reg); reg 728 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_VDP_CTRL); reg 729 drivers/media/i2c/tda1997x.c reg |= VDP_CTRL_MATRIX_BP; reg 730 drivers/media/i2c/tda1997x.c io_write(sd, REG_VDP_CTRL, reg); reg 753 drivers/media/i2c/tda1997x.c u8 reg; reg 799 drivers/media/i2c/tda1997x.c reg = VHREF_STD_DET_OFF << VHREF_STD_DET_SHIFT; reg 800 drivers/media/i2c/tda1997x.c io_write(sd, REG_VHREF_CTRL, reg); reg 819 drivers/media/i2c/tda1997x.c reg = fieldref_f1_start & MASK_VHREF; reg 820 drivers/media/i2c/tda1997x.c reg |= field_polarity << 8; reg 821 drivers/media/i2c/tda1997x.c io_write16(sd, REG_FREF_F1_S, reg); reg 822 drivers/media/i2c/tda1997x.c reg = fieldref_f2_start & MASK_VHREF; reg 823 drivers/media/i2c/tda1997x.c io_write16(sd, REG_FREF_F2_S, reg); reg 833 drivers/media/i2c/tda1997x.c u8 reg; reg 836 drivers/media/i2c/tda1997x.c reg = (state->vid_fmt == OF_FMT_422_CCIR) ? reg 838 drivers/media/i2c/tda1997x.c reg |= pdata->vidout_delay_pclk << PCLK_DELAY_SHIFT; reg 839 drivers/media/i2c/tda1997x.c reg |= pdata->vidout_inv_pclk << PCLK_INV_SHIFT; reg 840 drivers/media/i2c/tda1997x.c io_write(sd, REG_PCLK, reg); reg 854 drivers/media/i2c/tda1997x.c reg = state->vid_fmt & OF_FMT_MASK; reg 856 drivers/media/i2c/tda1997x.c reg |= (OF_BLK | OF_TRC); reg 857 drivers/media/i2c/tda1997x.c reg |= OF_VP_ENABLE; reg 858 drivers/media/i2c/tda1997x.c io_write(sd, REG_OF, reg); reg 861 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_VDP_CTRL); reg 864 drivers/media/i2c/tda1997x.c reg |= VDP_CTRL_PREFILTER_BP; reg 866 drivers/media/i2c/tda1997x.c reg &= ~VDP_CTRL_PREFILTER_BP; reg 869 drivers/media/i2c/tda1997x.c reg |= VDP_CTRL_FORMATTER_BP; reg 872 drivers/media/i2c/tda1997x.c reg &= ~(VDP_CTRL_FORMATTER_BP | VDP_CTRL_COMPDEL_BP); reg 875 drivers/media/i2c/tda1997x.c reg &= ~VDP_CTRL_COMPDEL_BP; reg 876 drivers/media/i2c/tda1997x.c io_write(sd, REG_VDP_CTRL, reg); reg 879 drivers/media/i2c/tda1997x.c reg = pdata->vidout_delay_de << DE_FREF_DELAY_SHIFT | reg 882 drivers/media/i2c/tda1997x.c io_write(sd, REG_DE_FREF, reg); reg 886 drivers/media/i2c/tda1997x.c reg = pdata->vidout_delay_hs << HS_HREF_DELAY_SHIFT | reg 890 drivers/media/i2c/tda1997x.c reg = HS_HREF_SEL_NONE << HS_HREF_SEL_SHIFT; reg 891 drivers/media/i2c/tda1997x.c io_write(sd, REG_HS_HREF, reg); reg 895 drivers/media/i2c/tda1997x.c reg = pdata->vidout_delay_vs << VS_VREF_DELAY_SHIFT | reg 899 drivers/media/i2c/tda1997x.c reg = VS_VREF_SEL_NONE << VS_VREF_SEL_SHIFT; reg 900 drivers/media/i2c/tda1997x.c io_write(sd, REG_VS_VREF, reg); reg 912 drivers/media/i2c/tda1997x.c u8 reg; reg 921 drivers/media/i2c/tda1997x.c reg = 0; reg 924 drivers/media/i2c/tda1997x.c reg |= AUDCFG_BUS_I2S << AUDCFG_BUS_SHIFT; reg 927 drivers/media/i2c/tda1997x.c reg |= AUDCFG_BUS_SPDIF << AUDCFG_BUS_SHIFT; reg 932 drivers/media/i2c/tda1997x.c reg |= AUDCFG_TYPE_PCM << AUDCFG_TYPE_SHIFT; reg 935 drivers/media/i2c/tda1997x.c reg |= AUDCFG_TYPE_OBA << AUDCFG_TYPE_SHIFT; reg 938 drivers/media/i2c/tda1997x.c reg |= AUDCFG_TYPE_DST << AUDCFG_TYPE_SHIFT; reg 942 drivers/media/i2c/tda1997x.c reg |= AUDCFG_TYPE_HBR << AUDCFG_TYPE_SHIFT; reg 945 drivers/media/i2c/tda1997x.c reg |= AUDCFG_HBR_DEMUX << AUDCFG_HBR_SHIFT; reg 950 drivers/media/i2c/tda1997x.c reg |= AUDCFG_HBR_STRAIGHT << AUDCFG_HBR_SHIFT; reg 955 drivers/media/i2c/tda1997x.c reg |= AUDCFG_I2SW_32 << AUDCFG_I2SW_SHIFT; reg 957 drivers/media/i2c/tda1997x.c reg |= AUDCFG_I2SW_16 << AUDCFG_I2SW_SHIFT; reg 961 drivers/media/i2c/tda1997x.c reg |= AUDCFG_AUTO_MUTE_EN; reg 964 drivers/media/i2c/tda1997x.c reg |= AUDCFG_CLK_INVERT; reg 965 drivers/media/i2c/tda1997x.c io_write(sd, REG_AUDCFG, reg); reg 968 drivers/media/i2c/tda1997x.c reg = (pdata->audout_layout) ? AUDIO_LAYOUT_LAYOUT1 : 0; reg 970 drivers/media/i2c/tda1997x.c reg |= AUDIO_LAYOUT_MANUAL; reg 972 drivers/media/i2c/tda1997x.c reg |= AUDIO_LAYOUT_SP_FLAG; reg 973 drivers/media/i2c/tda1997x.c io_write(sd, REG_AUDIO_LAYOUT, reg); reg 980 drivers/media/i2c/tda1997x.c reg = AUDIO_OUT_ENABLE_AP0; reg 982 drivers/media/i2c/tda1997x.c reg |= AUDIO_OUT_ENABLE_AP1; reg 984 drivers/media/i2c/tda1997x.c reg |= AUDIO_OUT_ENABLE_AP2; reg 986 drivers/media/i2c/tda1997x.c reg |= AUDIO_OUT_ENABLE_AP3; reg 995 drivers/media/i2c/tda1997x.c reg &= ~AUDIO_OUT_ENABLE_AP1; reg 999 drivers/media/i2c/tda1997x.c reg &= ~AUDIO_OUT_ENABLE_AP2; reg 1001 drivers/media/i2c/tda1997x.c reg = AUDIO_OUT_ENABLE_AP3 | reg 1007 drivers/media/i2c/tda1997x.c reg |= (AUDIO_OUT_ENABLE_ACLK | AUDIO_OUT_ENABLE_WS); reg 1008 drivers/media/i2c/tda1997x.c io_write(sd, REG_AUDIO_OUT_ENABLE, reg); reg 1020 drivers/media/i2c/tda1997x.c u8 reg; reg 1023 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_HDMI_INFO_RST); reg 1027 drivers/media/i2c/tda1997x.c if (reg & RESET_IF) { reg 1028 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_INT_FLG_CLR_MODE); reg 1029 drivers/media/i2c/tda1997x.c io_write(sd, REG_INT_FLG_CLR_MODE, reg); reg 1033 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_RATE_CTRL); reg 1034 drivers/media/i2c/tda1997x.c reg &= ~RATE_REFTIM_ENABLE; reg 1036 drivers/media/i2c/tda1997x.c reg |= RATE_REFTIM_ENABLE; reg 1037 drivers/media/i2c/tda1997x.c reg = io_write(sd, REG_RATE_CTRL, reg); reg 1046 drivers/media/i2c/tda1997x.c u8 reg; reg 1056 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_OF); reg 1057 drivers/media/i2c/tda1997x.c reg &= ~OF_VP_ENABLE; reg 1058 drivers/media/i2c/tda1997x.c io_write(sd, REG_OF, reg); reg 1062 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_OF); reg 1063 drivers/media/i2c/tda1997x.c reg |= OF_VP_ENABLE; reg 1064 drivers/media/i2c/tda1997x.c io_write(sd, REG_OF, reg); reg 1077 drivers/media/i2c/tda1997x.c u8 reg = io_read(sd, REG_DETECT_5V); reg 1079 drivers/media/i2c/tda1997x.c return ((reg & DETECT_5V_SEL) ? 1 : 0); reg 1085 drivers/media/i2c/tda1997x.c u8 reg = io_read(sd, REG_DETECT_5V); reg 1087 drivers/media/i2c/tda1997x.c return ((reg & DETECT_HPD) ? 1 : 0); reg 1161 drivers/media/i2c/tda1997x.c u8 reg; reg 1169 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_MODE_REC_CFG1); reg 1170 drivers/media/i2c/tda1997x.c reg &= ~0x06; reg 1171 drivers/media/i2c/tda1997x.c reg |= 0x02; reg 1172 drivers/media/i2c/tda1997x.c io_write(sd, REG_MODE_REC_CFG1, reg); reg 1175 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_MODE_REC_CFG1); reg 1176 drivers/media/i2c/tda1997x.c reg &= ~0x06; reg 1177 drivers/media/i2c/tda1997x.c io_write(sd, REG_MODE_REC_CFG1, reg); reg 1189 drivers/media/i2c/tda1997x.c u8 reg, status = 0; reg 1192 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_CLK_A_STATUS); reg 1194 drivers/media/i2c/tda1997x.c if ((reg & MASK_CLK_STABLE) && !(reg & MASK_CLK_ACTIVE)) reg 1195 drivers/media/i2c/tda1997x.c reg &= ~MASK_CLK_STABLE; reg 1196 drivers/media/i2c/tda1997x.c status |= ((reg & MASK_CLK_STABLE) >> 2); reg 1199 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_CLK_B_STATUS); reg 1201 drivers/media/i2c/tda1997x.c if ((reg & MASK_CLK_STABLE) && !(reg & MASK_CLK_ACTIVE)) reg 1202 drivers/media/i2c/tda1997x.c reg &= ~MASK_CLK_STABLE; reg 1203 drivers/media/i2c/tda1997x.c status |= ((reg & MASK_CLK_STABLE) >> 1); reg 1206 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_SUS_STATUS); reg 1209 drivers/media/i2c/tda1997x.c if ((reg & MASK_SUS_STATUS) == LAST_STATE_REACHED) reg 1251 drivers/media/i2c/tda1997x.c u8 reg; reg 1329 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_PIX_REPEAT); reg 1330 drivers/media/i2c/tda1997x.c reg &= ~PIX_REPEAT_MASK_UP_SEL; reg 1332 drivers/media/i2c/tda1997x.c reg |= (PIX_REPEAT_CHROMA << PIX_REPEAT_SHIFT); reg 1333 drivers/media/i2c/tda1997x.c io_write(sd, REG_PIX_REPEAT, reg); reg 1336 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_PIX_REPEAT); reg 1337 drivers/media/i2c/tda1997x.c reg &= ~PIX_REPEAT_MASK_REP; reg 1338 drivers/media/i2c/tda1997x.c reg |= frame.avi.pixel_repeat; reg 1339 drivers/media/i2c/tda1997x.c io_write(sd, REG_PIX_REPEAT, reg); reg 1353 drivers/media/i2c/tda1997x.c u8 reg, source; reg 1366 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_HDMI_INFO_RST); reg 1367 drivers/media/i2c/tda1997x.c reg |= MASK_SR_FIFO_FIFO_CTRL; reg 1368 drivers/media/i2c/tda1997x.c io_write(sd, REG_HDMI_INFO_RST, reg); reg 1369 drivers/media/i2c/tda1997x.c reg &= ~MASK_SR_FIFO_FIFO_CTRL; reg 1370 drivers/media/i2c/tda1997x.c io_write(sd, REG_HDMI_INFO_RST, reg); reg 1377 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_SUS_STATUS); reg 1378 drivers/media/i2c/tda1997x.c if (((reg & MASK_SUS_STATUS) != LAST_STATE_REACHED) reg 1384 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_SUS_STATUS); reg 1385 drivers/media/i2c/tda1997x.c if ((reg & MASK_SUS_STATUS) != LAST_STATE_REACHED) { reg 1419 drivers/media/i2c/tda1997x.c u8 reg, source; reg 1433 drivers/media/i2c/tda1997x.c reg = source; reg 1434 drivers/media/i2c/tda1997x.c while (reg != 0) { reg 1436 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_INT_FLG_CLR_RATE); reg 1437 drivers/media/i2c/tda1997x.c io_write(sd, REG_INT_FLG_CLR_RATE, reg); reg 1438 drivers/media/i2c/tda1997x.c source |= reg; reg 1455 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_PIX_REPEAT); reg 1456 drivers/media/i2c/tda1997x.c reg &= ~PIX_REPEAT_MASK_UP_SEL; reg 1457 drivers/media/i2c/tda1997x.c reg &= ~PIX_REPEAT_MASK_REP; reg 1458 drivers/media/i2c/tda1997x.c io_write(sd, REG_PIX_REPEAT, reg); reg 1511 drivers/media/i2c/tda1997x.c u8 reg, source; reg 1520 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_SUS_STATUS); reg 1521 drivers/media/i2c/tda1997x.c if ((reg & MASK_SUS_STATUS) == LAST_STATE_REACHED) { reg 1522 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_HDMI_INFO_RST); reg 1523 drivers/media/i2c/tda1997x.c reg |= MASK_SR_FIFO_FIFO_CTRL; reg 1524 drivers/media/i2c/tda1997x.c io_write(sd, REG_HDMI_INFO_RST, reg); reg 1525 drivers/media/i2c/tda1997x.c reg &= ~MASK_SR_FIFO_FIFO_CTRL; reg 1526 drivers/media/i2c/tda1997x.c io_write(sd, REG_HDMI_INFO_RST, reg); reg 1536 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_AUDIO_FREQ); reg 1537 drivers/media/i2c/tda1997x.c state->audio_samplerate = freq[reg & 7]; reg 1542 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_AUDIO_FLAGS); reg 1543 drivers/media/i2c/tda1997x.c if (reg & BIT(AUDCFG_TYPE_DST)) reg 1545 drivers/media/i2c/tda1997x.c if (reg & BIT(AUDCFG_TYPE_OBA)) reg 1547 drivers/media/i2c/tda1997x.c if (reg & BIT(AUDCFG_TYPE_HBR)) reg 1549 drivers/media/i2c/tda1997x.c if (reg & BIT(AUDCFG_TYPE_PCM)) reg 1559 drivers/media/i2c/tda1997x.c u8 reg, source; reg 1569 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_INT_MASK_TOP); reg 1570 drivers/media/i2c/tda1997x.c reg &= ~(INTERRUPT_AUDIO | INTERRUPT_INFO); reg 1571 drivers/media/i2c/tda1997x.c io_write(sd, REG_INT_MASK_TOP, reg); reg 2075 drivers/media/i2c/tda1997x.c u8 reg; reg 2100 drivers/media/i2c/tda1997x.c reg = tda1997x_cec_read(sd, REG_CONTROL & 0xff); reg 2101 drivers/media/i2c/tda1997x.c reg |= 0x20; reg 2102 drivers/media/i2c/tda1997x.c tda1997x_cec_write(sd, REG_CONTROL & 0xff, reg); reg 2106 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_VERSION); reg 2108 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_CMTP_REG10); reg 2176 drivers/media/i2c/tda1997x.c reg = HDMI_CTRL_MUTE_AUTO << HDMI_CTRL_MUTE_SHIFT; reg 2177 drivers/media/i2c/tda1997x.c reg |= HDMI_CTRL_HDCP_AUTO << HDMI_CTRL_HDCP_SHIFT; reg 2178 drivers/media/i2c/tda1997x.c io_write(sd, REG_HDMI_CTRL, reg); reg 2184 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_VDP_CTRL); reg 2185 drivers/media/i2c/tda1997x.c reg |= VDP_CTRL_MATRIX_BP; reg 2186 drivers/media/i2c/tda1997x.c io_write(sd, REG_VDP_CTRL, reg); reg 2204 drivers/media/i2c/tda1997x.c reg = AUDIO_CLOCK_SEL_512FS; reg 2207 drivers/media/i2c/tda1997x.c reg = AUDIO_CLOCK_SEL_256FS; reg 2210 drivers/media/i2c/tda1997x.c reg = AUDIO_CLOCK_SEL_128FS; reg 2213 drivers/media/i2c/tda1997x.c reg = AUDIO_CLOCK_SEL_64FS; reg 2216 drivers/media/i2c/tda1997x.c reg = AUDIO_CLOCK_SEL_32FS; reg 2219 drivers/media/i2c/tda1997x.c reg = AUDIO_CLOCK_SEL_16FS; reg 2222 drivers/media/i2c/tda1997x.c io_write(sd, REG_AUDIO_CLOCK, reg); reg 2317 drivers/media/i2c/tda1997x.c u32 reg, val, i; reg 2321 drivers/media/i2c/tda1997x.c i * 2, ®); reg 2324 drivers/media/i2c/tda1997x.c if (reg < 9) reg 2325 drivers/media/i2c/tda1997x.c pdata->vidout_port_cfg[reg] = val; reg 2406 drivers/media/i2c/tda1997x.c u8 reg; reg 2409 drivers/media/i2c/tda1997x.c reg = io_read(sd, REG_CMTP_REG10); reg 2410 drivers/media/i2c/tda1997x.c state->tmdsb_clk = (reg >> 6) & 0x01; /* use tmds clock B_inv for B */ reg 2411 drivers/media/i2c/tda1997x.c state->tmdsb_soc = (reg >> 5) & 0x01; /* tmds of input B */ reg 2412 drivers/media/i2c/tda1997x.c state->port_30bit = (reg >> 2) & 0x03; /* 30bit vs 24bit */ reg 2413 drivers/media/i2c/tda1997x.c state->output_2p5 = (reg >> 1) & 0x01; /* output supply 2.5v */ reg 2414 drivers/media/i2c/tda1997x.c switch ((reg >> 4) & 0x03) { reg 47 drivers/media/i2c/tda9840.c static void tda9840_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 51 drivers/media/i2c/tda9840.c if (i2c_smbus_write_byte_data(client, reg, val)) reg 53 drivers/media/i2c/tda9840.c val, reg); reg 60 drivers/media/i2c/ths7303.c static int ths7303_read(struct v4l2_subdev *sd, u8 reg) reg 64 drivers/media/i2c/ths7303.c return i2c_smbus_read_byte_data(client, reg); reg 67 drivers/media/i2c/ths7303.c static int ths7303_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 74 drivers/media/i2c/ths7303.c ret = i2c_smbus_write_byte_data(client, reg, val); reg 219 drivers/media/i2c/ths7303.c struct v4l2_dbg_register *reg) reg 221 drivers/media/i2c/ths7303.c reg->size = 1; reg 222 drivers/media/i2c/ths7303.c reg->val = ths7303_read(sd, reg->reg); reg 227 drivers/media/i2c/ths7303.c const struct v4l2_dbg_register *reg) reg 229 drivers/media/i2c/ths7303.c ths7303_write(sd, reg->reg, reg->val); reg 264 drivers/media/i2c/ths7303.c static void ths7303_log_channel_status(struct v4l2_subdev *sd, u8 reg) reg 266 drivers/media/i2c/ths7303.c u8 val = ths7303_read(sd, reg); reg 269 drivers/media/i2c/ths7303.c v4l2_info(sd, "Channel %d Off\n", reg); reg 273 drivers/media/i2c/ths7303.c v4l2_info(sd, "Channel %d On\n", reg); reg 71 drivers/media/i2c/ths8200.c static int ths8200_read(struct v4l2_subdev *sd, u8 reg) reg 75 drivers/media/i2c/ths8200.c return i2c_smbus_read_byte_data(client, reg); reg 78 drivers/media/i2c/ths8200.c static int ths8200_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 85 drivers/media/i2c/ths8200.c ret = i2c_smbus_write_byte_data(client, reg, val); reg 97 drivers/media/i2c/ths8200.c ths8200_write_and_or(struct v4l2_subdev *sd, u8 reg, reg 100 drivers/media/i2c/ths8200.c ths8200_write(sd, reg, (ths8200_read(sd, reg) & clr_mask) | val_mask); reg 106 drivers/media/i2c/ths8200.c struct v4l2_dbg_register *reg) reg 108 drivers/media/i2c/ths8200.c reg->val = ths8200_read(sd, reg->reg & 0xff); reg 109 drivers/media/i2c/ths8200.c reg->size = 1; reg 115 drivers/media/i2c/ths8200.c const struct v4l2_dbg_register *reg) reg 117 drivers/media/i2c/ths8200.c ths8200_write(sd, reg->reg & 0xff, reg->val & 0xff); reg 45 drivers/media/i2c/tlv320aic23b.c static int tlv320aic23b_write(struct v4l2_subdev *sd, int reg, u16 val) reg 50 drivers/media/i2c/tlv320aic23b.c if ((reg < 0 || reg > 9) && (reg != 15)) { reg 51 drivers/media/i2c/tlv320aic23b.c v4l2_err(sd, "Invalid register R%d\n", reg); reg 57 drivers/media/i2c/tlv320aic23b.c (reg << 1) | (val >> 8), val & 0xff) == 0) reg 59 drivers/media/i2c/tlv320aic23b.c v4l2_err(sd, "I2C: cannot write %03x to register R%d\n", val, reg); reg 279 drivers/media/i2c/tvp514x.c static int tvp514x_read_reg(struct v4l2_subdev *sd, u8 reg) reg 286 drivers/media/i2c/tvp514x.c err = i2c_smbus_read_byte_data(client, reg); reg 304 drivers/media/i2c/tvp514x.c static void dump_reg(struct v4l2_subdev *sd, u8 reg) reg 308 drivers/media/i2c/tvp514x.c val = tvp514x_read_reg(sd, reg); reg 309 drivers/media/i2c/tvp514x.c v4l2_info(sd, "Reg(0x%.2X): 0x%.2X\n", reg, val); reg 321 drivers/media/i2c/tvp514x.c static int tvp514x_write_reg(struct v4l2_subdev *sd, u8 reg, u8 val) reg 328 drivers/media/i2c/tvp514x.c err = i2c_smbus_write_byte_data(client, reg, val); reg 368 drivers/media/i2c/tvp514x.c err = tvp514x_write_reg(sd, next->reg, (u8) next->val); reg 270 drivers/media/i2c/tvp514x_regs.h u8 reg; reg 308 drivers/media/i2c/tvp5150.c unsigned char reg; reg 482 drivers/media/i2c/tvp5150.c u16 reg; reg 579 drivers/media/i2c/tvp5150.c while (regs->reg != 0xff) { reg 580 drivers/media/i2c/tvp5150.c regmap_write(decoder->regmap, regs->reg, regs->value); reg 607 drivers/media/i2c/tvp5150.c regmap_write(map, TVP5150_CONF_RAM_ADDR_HIGH, regs->reg >> 8); reg 608 drivers/media/i2c/tvp5150.c regmap_write(map, TVP5150_CONF_RAM_ADDR_LOW, regs->reg); reg 661 drivers/media/i2c/tvp5150.c u8 reg; reg 689 drivers/media/i2c/tvp5150.c reg = ((line - 6) << 1) + TVP5150_LINE_MODE_INI; reg 692 drivers/media/i2c/tvp5150.c regmap_write(decoder->regmap, reg, type); reg 695 drivers/media/i2c/tvp5150.c regmap_write(decoder->regmap, reg + 1, type); reg 704 drivers/media/i2c/tvp5150.c u8 reg; reg 719 drivers/media/i2c/tvp5150.c reg = ((line - 6) << 1) + TVP5150_LINE_MODE_INI; reg 722 drivers/media/i2c/tvp5150.c ret = tvp5150_read(sd, reg + i); reg 1322 drivers/media/i2c/tvp5150.c static int tvp5150_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) reg 1326 drivers/media/i2c/tvp5150.c res = tvp5150_read(sd, reg->reg & 0xff); reg 1332 drivers/media/i2c/tvp5150.c reg->val = res; reg 1333 drivers/media/i2c/tvp5150.c reg->size = 1; reg 1337 drivers/media/i2c/tvp5150.c static int tvp5150_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) reg 1341 drivers/media/i2c/tvp5150.c return regmap_write(decoder->regmap, reg->reg & 0xff, reg->val & 0xff); reg 1484 drivers/media/i2c/tvp5150.c static bool tvp5150_volatile_reg(struct device *dev, unsigned int reg) reg 1486 drivers/media/i2c/tvp5150.c switch (reg) { reg 61 drivers/media/i2c/tvp7002.c u8 reg; reg 472 drivers/media/i2c/tvp7002.c static inline void tvp7002_read_err(struct v4l2_subdev *sd, u8 reg, reg 476 drivers/media/i2c/tvp7002.c *err = tvp7002_read(sd, reg, dst); reg 519 drivers/media/i2c/tvp7002.c static inline void tvp7002_write_err(struct v4l2_subdev *sd, u8 reg, reg 523 drivers/media/i2c/tvp7002.c *err = tvp7002_write(sd, reg, val); reg 540 drivers/media/i2c/tvp7002.c while (TVP7002_EOR != regs->reg) { reg 542 drivers/media/i2c/tvp7002.c tvp7002_write_err(sd, regs->reg, regs->value, &error); reg 685 drivers/media/i2c/tvp7002.c struct v4l2_dbg_register *reg) reg 690 drivers/media/i2c/tvp7002.c ret = tvp7002_read(sd, reg->reg & 0xff, &val); reg 691 drivers/media/i2c/tvp7002.c reg->val = val; reg 692 drivers/media/i2c/tvp7002.c reg->size = 1; reg 705 drivers/media/i2c/tvp7002.c const struct v4l2_dbg_register *reg) reg 707 drivers/media/i2c/tvp7002.c return tvp7002_write(sd, reg->reg & 0xff, reg->val & 0xff); reg 106 drivers/media/i2c/tw2804.c static int write_reg(struct i2c_client *client, u8 reg, u8 value, u8 channel) reg 108 drivers/media/i2c/tw2804.c return i2c_smbus_write_byte_data(client, reg | (channel << 6), value); reg 125 drivers/media/i2c/tw2804.c static int read_reg(struct i2c_client *client, u8 reg, u8 channel) reg 127 drivers/media/i2c/tw2804.c return i2c_smbus_read_byte_data(client, (reg) | (channel << 6)); reg 194 drivers/media/i2c/tw2804.c int reg; reg 199 drivers/media/i2c/tw2804.c reg = read_reg(client, addr, state->channel); reg 200 drivers/media/i2c/tw2804.c if (reg < 0) reg 201 drivers/media/i2c/tw2804.c return reg; reg 203 drivers/media/i2c/tw2804.c reg &= ~(1 << 7); reg 205 drivers/media/i2c/tw2804.c reg |= 1 << 7; reg 206 drivers/media/i2c/tw2804.c return write_reg(client, addr, reg, state->channel); reg 210 drivers/media/i2c/tw2804.c reg = read_reg(client, addr, state->channel); reg 211 drivers/media/i2c/tw2804.c if (reg < 0) reg 212 drivers/media/i2c/tw2804.c return reg; reg 213 drivers/media/i2c/tw2804.c reg = (reg & ~(0x03)) | (ctrl->val == 0 ? 0x02 : 0x03); reg 214 drivers/media/i2c/tw2804.c return write_reg(client, addr, reg, state->channel); reg 279 drivers/media/i2c/tw2804.c int reg; reg 310 drivers/media/i2c/tw2804.c reg = read_reg(client, 0x22, dec->channel); reg 312 drivers/media/i2c/tw2804.c if (reg >= 0) { reg 314 drivers/media/i2c/tw2804.c reg &= ~(1 << 2); reg 316 drivers/media/i2c/tw2804.c reg |= 1 << 2; reg 317 drivers/media/i2c/tw2804.c reg = write_reg(client, 0x22, reg, dec->channel); reg 320 drivers/media/i2c/tw2804.c if (reg >= 0) reg 323 drivers/media/i2c/tw2804.c return reg; reg 90 drivers/media/i2c/tw9903.c static int write_reg(struct v4l2_subdev *sd, u8 reg, u8 value) reg 94 drivers/media/i2c/tw9903.c return i2c_smbus_write_byte_data(client, reg, value); reg 61 drivers/media/i2c/tw9906.c static int write_reg(struct v4l2_subdev *sd, u8 reg, u8 value) reg 65 drivers/media/i2c/tw9906.c return i2c_smbus_write_byte_data(client, reg, value); reg 552 drivers/media/i2c/tw9910.c struct v4l2_dbg_register *reg) reg 557 drivers/media/i2c/tw9910.c if (reg->reg > 0xff) reg 560 drivers/media/i2c/tw9910.c reg->size = 1; reg 561 drivers/media/i2c/tw9910.c ret = i2c_smbus_read_byte_data(client, reg->reg); reg 569 drivers/media/i2c/tw9910.c reg->val = (__u64)ret; reg 575 drivers/media/i2c/tw9910.c const struct v4l2_dbg_register *reg) reg 579 drivers/media/i2c/tw9910.c if (reg->reg > 0xff || reg 580 drivers/media/i2c/tw9910.c reg->val > 0xff) reg 583 drivers/media/i2c/tw9910.c return i2c_smbus_write_byte_data(client, reg->reg, reg->val); reg 14 drivers/media/i2c/uda1342.c static int write_reg(struct i2c_client *client, int reg, int value) reg 17 drivers/media/i2c/uda1342.c i2c_smbus_write_word_data(client, reg, swab16(value)); reg 72 drivers/media/i2c/upd64031a.c static u8 upd64031a_read(struct v4l2_subdev *sd, u8 reg) reg 77 drivers/media/i2c/upd64031a.c if (reg >= sizeof(buf)) reg 80 drivers/media/i2c/upd64031a.c return buf[reg]; reg 85 drivers/media/i2c/upd64031a.c static void upd64031a_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 90 drivers/media/i2c/upd64031a.c buf[0] = reg; reg 92 drivers/media/i2c/upd64031a.c v4l2_dbg(1, debug, sd, "write reg: %02X val: %02X\n", reg, val); reg 94 drivers/media/i2c/upd64031a.c v4l2_err(sd, "I/O error write 0x%02x/0x%02x\n", reg, val); reg 103 drivers/media/i2c/upd64031a.c u8 reg = state->regs[R00]; reg 106 drivers/media/i2c/upd64031a.c upd64031a_write(sd, R00, reg | 0x10); reg 107 drivers/media/i2c/upd64031a.c upd64031a_write(sd, R00, reg & ~0x10); reg 144 drivers/media/i2c/upd64031a.c static int upd64031a_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) reg 146 drivers/media/i2c/upd64031a.c reg->val = upd64031a_read(sd, reg->reg & 0xff); reg 147 drivers/media/i2c/upd64031a.c reg->size = 1; reg 151 drivers/media/i2c/upd64031a.c static int upd64031a_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) reg 153 drivers/media/i2c/upd64031a.c upd64031a_write(sd, reg->reg & 0xff, reg->val & 0xff); reg 61 drivers/media/i2c/upd64083.c static void upd64083_write(struct v4l2_subdev *sd, u8 reg, u8 val) reg 66 drivers/media/i2c/upd64083.c buf[0] = reg; reg 68 drivers/media/i2c/upd64083.c v4l2_dbg(1, debug, sd, "write reg: %02x val: %02x\n", reg, val); reg 70 drivers/media/i2c/upd64083.c v4l2_err(sd, "I/O error write 0x%02x/0x%02x\n", reg, val); reg 76 drivers/media/i2c/upd64083.c static u8 upd64083_read(struct v4l2_subdev *sd, u8 reg) reg 81 drivers/media/i2c/upd64083.c if (reg >= sizeof(buf)) reg 84 drivers/media/i2c/upd64083.c return buf[reg]; reg 108 drivers/media/i2c/upd64083.c static int upd64083_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) reg 110 drivers/media/i2c/upd64083.c reg->val = upd64083_read(sd, reg->reg & 0xff); reg 111 drivers/media/i2c/upd64083.c reg->size = 1; reg 115 drivers/media/i2c/upd64083.c static int upd64083_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) reg 117 drivers/media/i2c/upd64083.c upd64083_write(sd, reg->reg & 0xff, reg->val & 0xff); reg 35 drivers/media/i2c/vpx3220.c unsigned char reg[255]; reg 56 drivers/media/i2c/vpx3220.c static inline int vpx3220_write(struct v4l2_subdev *sd, u8 reg, u8 value) reg 61 drivers/media/i2c/vpx3220.c decoder->reg[reg] = value; reg 62 drivers/media/i2c/vpx3220.c return i2c_smbus_write_byte_data(client, reg, value); reg 65 drivers/media/i2c/vpx3220.c static inline int vpx3220_read(struct v4l2_subdev *sd, u8 reg) reg 69 drivers/media/i2c/vpx3220.c return i2c_smbus_read_byte_data(client, reg); reg 140 drivers/media/i2c/vpx3220.c u8 reg; reg 144 drivers/media/i2c/vpx3220.c reg = *data++; reg 145 drivers/media/i2c/vpx3220.c ret = vpx3220_write(sd, reg, *data++); reg 157 drivers/media/i2c/vpx3220.c u8 reg; reg 161 drivers/media/i2c/vpx3220.c reg = *data++; reg 162 drivers/media/i2c/vpx3220.c ret |= vpx3220_fp_write(sd, reg, *data++); reg 512 drivers/media/i2c/vs6624.c u16 reg; reg 516 drivers/media/i2c/vs6624.c reg = *regs++; reg 519 drivers/media/i2c/vs6624.c vs6624_write(sd, reg, data); reg 698 drivers/media/i2c/vs6624.c static int vs6624_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) reg 700 drivers/media/i2c/vs6624.c reg->val = vs6624_read(sd, reg->reg & 0xffff); reg 701 drivers/media/i2c/vs6624.c reg->size = 1; reg 705 drivers/media/i2c/vs6624.c static int vs6624_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) reg 707 drivers/media/i2c/vs6624.c vs6624_write(sd, reg->reg & 0xffff, reg->val & 0xff); reg 64 drivers/media/i2c/wm8739.c static int wm8739_write(struct v4l2_subdev *sd, int reg, u16 val) reg 69 drivers/media/i2c/wm8739.c if (reg < 0 || reg >= TOT_REGS) { reg 70 drivers/media/i2c/wm8739.c v4l2_err(sd, "Invalid register R%d\n", reg); reg 74 drivers/media/i2c/wm8739.c v4l2_dbg(1, debug, sd, "write: %02x %02x\n", reg, val); reg 78 drivers/media/i2c/wm8739.c (reg << 1) | (val >> 8), val & 0xff) == 0) reg 80 drivers/media/i2c/wm8739.c v4l2_err(sd, "I2C: cannot write %03x to register R%d\n", val, reg); reg 63 drivers/media/i2c/wm8775.c static int wm8775_write(struct v4l2_subdev *sd, int reg, u16 val) reg 68 drivers/media/i2c/wm8775.c if (reg < 0 || reg >= TOT_REGS) { reg 69 drivers/media/i2c/wm8775.c v4l2_err(sd, "Invalid register R%d\n", reg); reg 75 drivers/media/i2c/wm8775.c (reg << 1) | (val >> 8), val & 0xff) == 0) reg 77 drivers/media/i2c/wm8775.c v4l2_err(sd, "I2C: cannot write %03x to register R%d\n", val, reg); reg 1868 drivers/media/pci/bt8xx/bttv-driver.c struct v4l2_dbg_register *reg) reg 1874 drivers/media/pci/bt8xx/bttv-driver.c reg->reg &= 0xfff; reg 1875 drivers/media/pci/bt8xx/bttv-driver.c reg->val = btread(reg->reg); reg 1876 drivers/media/pci/bt8xx/bttv-driver.c reg->size = 1; reg 1882 drivers/media/pci/bt8xx/bttv-driver.c const struct v4l2_dbg_register *reg) reg 1888 drivers/media/pci/bt8xx/bttv-driver.c btwrite(reg->val, reg->reg & 0xfff); reg 295 drivers/media/pci/cobalt/cobalt-driver.h static inline void cobalt_write_bar0(struct cobalt *cobalt, u32 reg, u32 val) reg 297 drivers/media/pci/cobalt/cobalt-driver.h iowrite32(val, cobalt->bar0 + reg); reg 300 drivers/media/pci/cobalt/cobalt-driver.h static inline u32 cobalt_read_bar0(struct cobalt *cobalt, u32 reg) reg 302 drivers/media/pci/cobalt/cobalt-driver.h return ioread32(cobalt->bar0 + reg); reg 305 drivers/media/pci/cobalt/cobalt-driver.h static inline void cobalt_write_bar1(struct cobalt *cobalt, u32 reg, u32 val) reg 307 drivers/media/pci/cobalt/cobalt-driver.h iowrite32(val, cobalt->bar1 + reg); reg 310 drivers/media/pci/cobalt/cobalt-driver.h static inline u32 cobalt_read_bar1(struct cobalt *cobalt, u32 reg) reg 312 drivers/media/pci/cobalt/cobalt-driver.h return ioread32(cobalt->bar1 + reg); reg 441 drivers/media/pci/cobalt/cobalt-v4l2.c void __iomem *adrs = cobalt->bar1 + regs->reg; reg 457 drivers/media/pci/cobalt/cobalt-v4l2.c struct v4l2_dbg_register *reg) reg 462 drivers/media/pci/cobalt/cobalt-v4l2.c return cobalt_cobaltc(cobalt, VIDIOC_DBG_G_REGISTER, reg); reg 466 drivers/media/pci/cobalt/cobalt-v4l2.c const struct v4l2_dbg_register *reg) reg 472 drivers/media/pci/cobalt/cobalt-v4l2.c (struct v4l2_dbg_register *)reg); reg 17 drivers/media/pci/cx18/cx18-av-core.c u32 reg = 0xc40000 + (addr & ~3); reg 20 drivers/media/pci/cx18/cx18-av-core.c u32 x = cx18_read_reg(cx, reg); reg 23 drivers/media/pci/cx18/cx18-av-core.c cx18_write_reg(cx, x, reg); reg 29 drivers/media/pci/cx18/cx18-av-core.c u32 reg = 0xc40000 + (addr & ~3); reg 31 drivers/media/pci/cx18/cx18-av-core.c u32 x = cx18_read_reg(cx, reg); reg 34 drivers/media/pci/cx18/cx18-av-core.c cx18_write_reg_expect(cx, x, reg, reg 1224 drivers/media/pci/cx18/cx18-av-core.c struct v4l2_dbg_register *reg) reg 1228 drivers/media/pci/cx18/cx18-av-core.c if ((reg->reg & 0x3) != 0) reg 1230 drivers/media/pci/cx18/cx18-av-core.c reg->size = 4; reg 1231 drivers/media/pci/cx18/cx18-av-core.c reg->val = cx18_av_read4(cx, reg->reg & 0x00000ffc); reg 1236 drivers/media/pci/cx18/cx18-av-core.c const struct v4l2_dbg_register *reg) reg 1240 drivers/media/pci/cx18/cx18-av-core.c if ((reg->reg & 0x3) != 0) reg 1242 drivers/media/pci/cx18/cx18-av-core.c cx18_av_write4(cx, reg->reg & 0x00000ffc, reg->val); reg 137 drivers/media/pci/cx18/cx18-io.h static inline void cx18_write_reg_noretry(struct cx18 *cx, u32 val, u32 reg) reg 139 drivers/media/pci/cx18/cx18-io.h cx18_writel_noretry(cx, val, cx->reg_mem + reg); reg 142 drivers/media/pci/cx18/cx18-io.h static inline void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg) reg 144 drivers/media/pci/cx18/cx18-io.h cx18_writel(cx, val, cx->reg_mem + reg); reg 147 drivers/media/pci/cx18/cx18-io.h static inline void cx18_write_reg_expect(struct cx18 *cx, u32 val, u32 reg, reg 150 drivers/media/pci/cx18/cx18-io.h cx18_writel_expect(cx, val, cx->reg_mem + reg, eval, mask); reg 153 drivers/media/pci/cx18/cx18-io.h static inline u32 cx18_read_reg(struct cx18 *cx, u32 reg) reg 155 drivers/media/pci/cx18/cx18-io.h return cx18_readl(cx, cx->reg_mem + reg); reg 357 drivers/media/pci/cx18/cx18-ioctl.c struct v4l2_dbg_register *reg) reg 361 drivers/media/pci/cx18/cx18-ioctl.c if (reg->reg & 0x3) reg 363 drivers/media/pci/cx18/cx18-ioctl.c if (reg->reg >= CX18_MEM_OFFSET + CX18_MEM_SIZE) reg 365 drivers/media/pci/cx18/cx18-ioctl.c reg->size = 4; reg 366 drivers/media/pci/cx18/cx18-ioctl.c reg->val = cx18_read_enc(cx, reg->reg); reg 371 drivers/media/pci/cx18/cx18-ioctl.c const struct v4l2_dbg_register *reg) reg 375 drivers/media/pci/cx18/cx18-ioctl.c if (reg->reg & 0x3) reg 377 drivers/media/pci/cx18/cx18-ioctl.c if (reg->reg >= CX18_MEM_OFFSET + CX18_MEM_SIZE) reg 379 drivers/media/pci/cx18/cx18-ioctl.c cx18_write_enc(cx, reg->val, reg->reg); reg 82 drivers/media/pci/cx23885/cimax2.c static int netup_read_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg, reg 90 drivers/media/pci/cx23885/cimax2.c .buf = ®, reg 104 drivers/media/pci/cx23885/cimax2.c __func__, reg, ret); reg 110 drivers/media/pci/cx23885/cimax2.c __func__, addr, reg, buf[0]); reg 115 drivers/media/pci/cx23885/cimax2.c static int netup_write_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg, reg 130 drivers/media/pci/cx23885/cimax2.c KBUILD_MODNAME, reg, len); reg 134 drivers/media/pci/cx23885/cimax2.c buffer[0] = reg; reg 141 drivers/media/pci/cx23885/cimax2.c __func__, reg, ret); reg 1398 drivers/media/pci/cx23885/cx23885-core.c u32 reg; reg 1453 drivers/media/pci/cx23885/cx23885-core.c reg = cx_read(PAD_CTRL); reg 1454 drivers/media/pci/cx23885/cx23885-core.c reg &= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */ reg 1455 drivers/media/pci/cx23885/cx23885-core.c cx_write(PAD_CTRL, reg); reg 1460 drivers/media/pci/cx23885/cx23885-core.c reg = cx_read(PAD_CTRL); reg 1461 drivers/media/pci/cx23885/cx23885-core.c reg &= ~0x4; /* Clear TS2_SOP_OE */ reg 1462 drivers/media/pci/cx23885/cx23885-core.c cx_write(PAD_CTRL, reg); reg 1467 drivers/media/pci/cx23885/cx23885-core.c reg = cx_read(PAD_CTRL); reg 1468 drivers/media/pci/cx23885/cx23885-core.c reg = reg & ~0x1; /* Clear TS1_OE */ reg 1472 drivers/media/pci/cx23885/cx23885-core.c reg = reg | 0xa; reg 1473 drivers/media/pci/cx23885/cx23885-core.c cx_write(PAD_CTRL, reg); reg 1531 drivers/media/pci/cx23885/cx23885-core.c u32 reg; reg 1554 drivers/media/pci/cx23885/cx23885-core.c reg = cx_read(PAD_CTRL); reg 1557 drivers/media/pci/cx23885/cx23885-core.c reg = reg | 0x1; reg 1560 drivers/media/pci/cx23885/cx23885-core.c reg = reg & ~0xa; reg 1561 drivers/media/pci/cx23885/cx23885-core.c cx_write(PAD_CTRL, reg); reg 32 drivers/media/pci/cx23885/cx23885-ioctl.c struct v4l2_dbg_register *reg) reg 39 drivers/media/pci/cx23885/cx23885-ioctl.c if ((reg->reg & 0x3) != 0 || reg->reg >= 0x10000) reg 42 drivers/media/pci/cx23885/cx23885-ioctl.c if (mc417_register_read(dev, (u16) reg->reg, &value)) reg 45 drivers/media/pci/cx23885/cx23885-ioctl.c reg->size = 4; reg 46 drivers/media/pci/cx23885/cx23885-ioctl.c reg->val = value; reg 51 drivers/media/pci/cx23885/cx23885-ioctl.c struct v4l2_dbg_register *reg) reg 55 drivers/media/pci/cx23885/cx23885-ioctl.c if (reg->match.addr > 1) reg 57 drivers/media/pci/cx23885/cx23885-ioctl.c if (reg->match.addr) reg 58 drivers/media/pci/cx23885/cx23885-ioctl.c return cx23417_g_register(dev, reg); reg 60 drivers/media/pci/cx23885/cx23885-ioctl.c if ((reg->reg & 0x3) != 0 || reg->reg >= pci_resource_len(dev->pci, 0)) reg 63 drivers/media/pci/cx23885/cx23885-ioctl.c reg->size = 4; reg 64 drivers/media/pci/cx23885/cx23885-ioctl.c reg->val = cx_read(reg->reg); reg 69 drivers/media/pci/cx23885/cx23885-ioctl.c const struct v4l2_dbg_register *reg) reg 74 drivers/media/pci/cx23885/cx23885-ioctl.c if ((reg->reg & 0x3) != 0 || reg->reg >= 0x10000) reg 77 drivers/media/pci/cx23885/cx23885-ioctl.c if (mc417_register_write(dev, (u16) reg->reg, (u32) reg->val)) reg 83 drivers/media/pci/cx23885/cx23885-ioctl.c const struct v4l2_dbg_register *reg) reg 87 drivers/media/pci/cx23885/cx23885-ioctl.c if (reg->match.addr > 1) reg 89 drivers/media/pci/cx23885/cx23885-ioctl.c if (reg->match.addr) reg 90 drivers/media/pci/cx23885/cx23885-ioctl.c return cx23417_s_register(dev, reg); reg 92 drivers/media/pci/cx23885/cx23885-ioctl.c if ((reg->reg & 0x3) != 0 || reg->reg >= pci_resource_len(dev->pci, 0)) reg 95 drivers/media/pci/cx23885/cx23885-ioctl.c cx_write(reg->reg, reg->val); reg 18 drivers/media/pci/cx23885/cx23885-ioctl.h struct v4l2_dbg_register *reg); reg 22 drivers/media/pci/cx23885/cx23885-ioctl.h const struct v4l2_dbg_register *reg); reg 163 drivers/media/pci/cx23885/cx23885-video.c int cx23885_flatiron_write(struct cx23885_dev *dev, u8 reg, u8 data) reg 166 drivers/media/pci/cx23885/cx23885-video.c u8 buf[] = { reg, data }; reg 174 drivers/media/pci/cx23885/cx23885-video.c u8 cx23885_flatiron_read(struct cx23885_dev *dev, u8 reg) reg 178 drivers/media/pci/cx23885/cx23885-video.c u8 b0[] = { reg }; reg 10 drivers/media/pci/cx23885/cx23885-video.h int cx23885_flatiron_write(struct cx23885_dev *dev, u8 reg, u8 data); reg 11 drivers/media/pci/cx23885/cx23885-video.h u8 cx23885_flatiron_read(struct cx23885_dev *dev, u8 reg); reg 496 drivers/media/pci/cx23885/cx23885.h #define cx_read(reg) readl(dev->lmmio + ((reg)>>2)) reg 497 drivers/media/pci/cx23885/cx23885.h #define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2)) reg 499 drivers/media/pci/cx23885/cx23885.h #define cx_andor(reg, mask, value) \ reg 500 drivers/media/pci/cx23885/cx23885.h writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\ reg 501 drivers/media/pci/cx23885/cx23885.h ((value) & (mask)), dev->lmmio+((reg)>>2)) reg 503 drivers/media/pci/cx23885/cx23885.h #define cx_set(reg, bit) cx_andor((reg), (bit), (bit)) reg 504 drivers/media/pci/cx23885/cx23885.h #define cx_clear(reg, bit) cx_andor((reg), (bit), 0) reg 1071 drivers/media/pci/cx23885/cx23888-ir.c struct v4l2_dbg_register *reg) reg 1074 drivers/media/pci/cx23885/cx23888-ir.c u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg; reg 1080 drivers/media/pci/cx23885/cx23888-ir.c reg->size = 4; reg 1081 drivers/media/pci/cx23885/cx23888-ir.c reg->val = cx23888_ir_read4(state->dev, addr); reg 1086 drivers/media/pci/cx23885/cx23888-ir.c const struct v4l2_dbg_register *reg) reg 1089 drivers/media/pci/cx23885/cx23888-ir.c u32 addr = CX23888_IR_REG_BASE + (u32) reg->reg; reg 1095 drivers/media/pci/cx23885/cx23888-ir.c cx23888_ir_write4(state->dev, addr, reg->val); reg 15 drivers/media/pci/cx23885/netup-init.c static void i2c_av_write(struct i2c_adapter *i2c, u16 reg, u8 val) reg 26 drivers/media/pci/cx23885/netup-init.c buf[0] = reg >> 8; reg 27 drivers/media/pci/cx23885/netup-init.c buf[1] = reg & 0xff; reg 36 drivers/media/pci/cx23885/netup-init.c static void i2c_av_write4(struct i2c_adapter *i2c, u16 reg, u32 val) reg 47 drivers/media/pci/cx23885/netup-init.c buf[0] = reg >> 8; reg 48 drivers/media/pci/cx23885/netup-init.c buf[1] = reg & 0xff; reg 60 drivers/media/pci/cx23885/netup-init.c static u8 i2c_av_read(struct i2c_adapter *i2c, u16 reg) reg 71 drivers/media/pci/cx23885/netup-init.c buf[0] = reg >> 8; reg 72 drivers/media/pci/cx23885/netup-init.c buf[1] = reg & 0xff; reg 90 drivers/media/pci/cx23885/netup-init.c static void i2c_av_and_or(struct i2c_adapter *i2c, u16 reg, unsigned and_mask, reg 93 drivers/media/pci/cx23885/netup-init.c i2c_av_write(i2c, reg, (i2c_av_read(i2c, reg) & and_mask) | or_value); reg 351 drivers/media/pci/cx25821/cx25821.h #define cx_read(reg) readl(dev->lmmio + ((reg)>>2)) reg 352 drivers/media/pci/cx25821/cx25821.h #define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2)) reg 354 drivers/media/pci/cx25821/cx25821.h #define cx_andor(reg, mask, value) \ reg 355 drivers/media/pci/cx25821/cx25821.h writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\ reg 356 drivers/media/pci/cx25821/cx25821.h ((value) & (mask)), dev->lmmio+((reg)>>2)) reg 358 drivers/media/pci/cx25821/cx25821.h #define cx_set(reg, bit) cx_andor((reg), (bit), (bit)) reg 359 drivers/media/pci/cx25821/cx25821.h #define cx_clear(reg, bit) cx_andor((reg), (bit), 0) reg 610 drivers/media/pci/cx88/cx88-blackbird.c u32 reg; reg 617 drivers/media/pci/cx88/cx88-blackbird.c reg = cx_read(AUD_STATUS); reg 619 drivers/media/pci/cx88/cx88-blackbird.c dprintk(1, "AUD_STATUS:%dL: 0x%x\n", i, reg); reg 620 drivers/media/pci/cx88/cx88-blackbird.c if ((reg & 0x0F) != lastval) { reg 621 drivers/media/pci/cx88/cx88-blackbird.c lastval = reg & 0x0F; reg 980 drivers/media/pci/cx88/cx88-blackbird.c u32 reg; reg 993 drivers/media/pci/cx88/cx88-blackbird.c reg = cx_read(MO_DEVICE_STATUS); reg 994 drivers/media/pci/cx88/cx88-blackbird.c t->signal = (reg & (1 << 5)) ? 0xffff : 0x0000; reg 744 drivers/media/pci/cx88/cx88-core.c u32 reg; reg 754 drivers/media/pci/cx88/cx88-core.c reg = (pll & 0x3ffffff) | (pre[prescale] << 26); reg 755 drivers/media/pci/cx88/cx88-core.c if (((reg >> 20) & 0x3f) < 14) { reg 761 drivers/media/pci/cx88/cx88-core.c reg, cx_read(MO_PLL_REG), ofreq); reg 762 drivers/media/pci/cx88/cx88-core.c cx_write(MO_PLL_REG, reg); reg 764 drivers/media/pci/cx88/cx88-core.c reg = cx_read(MO_DEVICE_STATUS); reg 765 drivers/media/pci/cx88/cx88-core.c if (reg & (1 << 2)) { reg 88 drivers/media/pci/cx88/cx88-tvaudio.c u32 reg; reg 96 drivers/media/pci/cx88/cx88-tvaudio.c for (i = 0; l[i].reg; i++) { reg 97 drivers/media/pci/cx88/cx88-tvaudio.c switch (l[i].reg) { reg 104 drivers/media/pci/cx88/cx88-tvaudio.c cx_writeb(l[i].reg, l[i].val); reg 107 drivers/media/pci/cx88/cx88-tvaudio.c cx_write(l[i].reg, l[i].val); reg 814 drivers/media/pci/cx88/cx88-tvaudio.c u32 reg, mode, pilot; reg 816 drivers/media/pci/cx88/cx88-tvaudio.c reg = cx_read(AUD_STATUS); reg 817 drivers/media/pci/cx88/cx88-tvaudio.c mode = reg & 0x03; reg 818 drivers/media/pci/cx88/cx88-tvaudio.c pilot = (reg >> 2) & 0x03; reg 820 drivers/media/pci/cx88/cx88-tvaudio.c if (core->astat != reg) reg 822 drivers/media/pci/cx88/cx88-tvaudio.c reg, m[mode], p[pilot], reg 824 drivers/media/pci/cx88/cx88-tvaudio.c core->astat = reg; reg 147 drivers/media/pci/cx88/cx88-video.c u32 reg; reg 162 drivers/media/pci/cx88/cx88-video.c .reg = MO_CONTR_BRIGHT, reg 172 drivers/media/pci/cx88/cx88-video.c .reg = MO_CONTR_BRIGHT, reg 182 drivers/media/pci/cx88/cx88-video.c .reg = MO_HUE, reg 195 drivers/media/pci/cx88/cx88-video.c .reg = MO_UV_SATURATION, reg 209 drivers/media/pci/cx88/cx88-video.c .reg = MO_FILTER_ODD, reg 217 drivers/media/pci/cx88/cx88-video.c .reg = MO_INPUT_FORMAT, reg 225 drivers/media/pci/cx88/cx88-video.c .reg = MO_INPUT_FORMAT, reg 235 drivers/media/pci/cx88/cx88-video.c .reg = MO_HTOTAL, reg 248 drivers/media/pci/cx88/cx88-video.c .reg = AUD_VOL_CTL, reg 258 drivers/media/pci/cx88/cx88-video.c .reg = AUD_VOL_CTL, reg 268 drivers/media/pci/cx88/cx88-video.c .reg = AUD_BAL_CTL, reg 645 drivers/media/pci/cx88/cx88-video.c ctrl->id, ctrl->name, ctrl->val, cc->reg, value, reg 648 drivers/media/pci/cx88/cx88-video.c cx_sandor(cc->sreg, cc->reg, mask, value); reg 650 drivers/media/pci/cx88/cx88-video.c cx_andor(cc->reg, mask, value); reg 694 drivers/media/pci/cx88/cx88-video.c ctrl->id, ctrl->name, ctrl->val, cc->reg, value, reg 697 drivers/media/pci/cx88/cx88-video.c cx_sandor(cc->sreg, cc->reg, mask, value); reg 699 drivers/media/pci/cx88/cx88-video.c cx_andor(cc->reg, mask, value); reg 913 drivers/media/pci/cx88/cx88-video.c u32 reg; reg 926 drivers/media/pci/cx88/cx88-video.c reg = cx_read(MO_DEVICE_STATUS); reg 927 drivers/media/pci/cx88/cx88-video.c t->signal = (reg & (1 << 5)) ? 0xffff : 0x0000; reg 998 drivers/media/pci/cx88/cx88-video.c struct v4l2_dbg_register *reg) reg 1004 drivers/media/pci/cx88/cx88-video.c reg->val = cx_read(reg->reg & 0xfffffc); reg 1005 drivers/media/pci/cx88/cx88-video.c reg->size = 4; reg 1010 drivers/media/pci/cx88/cx88-video.c const struct v4l2_dbg_register *reg) reg 1015 drivers/media/pci/cx88/cx88-video.c cx_write(reg->reg & 0xfffffc, reg->val); reg 583 drivers/media/pci/cx88/cx88.h #define cx_read(reg) readl(core->lmmio + ((reg) >> 2)) reg 584 drivers/media/pci/cx88/cx88.h #define cx_write(reg, value) writel((value), core->lmmio + ((reg) >> 2)) reg 585 drivers/media/pci/cx88/cx88.h #define cx_writeb(reg, value) writeb((value), core->bmmio + (reg)) reg 587 drivers/media/pci/cx88/cx88.h #define cx_andor(reg, mask, value) \ reg 588 drivers/media/pci/cx88/cx88.h writel((readl(core->lmmio + ((reg) >> 2)) & ~(mask)) |\ reg 589 drivers/media/pci/cx88/cx88.h ((value) & (mask)), core->lmmio + ((reg) >> 2)) reg 590 drivers/media/pci/cx88/cx88.h #define cx_set(reg, bit) cx_andor((reg), (bit), (bit)) reg 591 drivers/media/pci/cx88/cx88.h #define cx_clear(reg, bit) cx_andor((reg), (bit), 0) reg 597 drivers/media/pci/cx88/cx88.h #define cx_swrite(sreg, reg, value) \ reg 599 drivers/media/pci/cx88/cx88.h writel(core->shadow[sreg], core->lmmio + ((reg) >> 2))) reg 600 drivers/media/pci/cx88/cx88.h #define cx_sandor(sreg, reg, mask, value) \ reg 604 drivers/media/pci/cx88/cx88.h core->lmmio + ((reg) >> 2))) reg 2580 drivers/media/pci/ddbridge/ddbridge-core.c static int reg_wait(struct ddb *dev, u32 reg, u32 bit) reg 2584 drivers/media/pci/ddbridge/ddbridge-core.c while (safe_ddbreadl(dev, reg) & bit) { reg 62 drivers/media/pci/ddbridge/ddbridge-i2c.h u8 adr, u8 reg, u8 *val, u8 len) reg 65 drivers/media/pci/ddbridge/ddbridge-i2c.h .buf = ®, .len = 1 }, reg 73 drivers/media/pci/ddbridge/ddbridge-i2c.h u8 adr, u16 reg, u8 *val, u8 len) reg 75 drivers/media/pci/ddbridge/ddbridge-i2c.h u8 msg[2] = { reg >> 8, reg & 0xff }; reg 85 drivers/media/pci/ddbridge/ddbridge-i2c.h u8 adr, u16 reg, u8 val) reg 87 drivers/media/pci/ddbridge/ddbridge-i2c.h u8 msg[3] = { reg >> 8, reg & 0xff, val }; reg 93 drivers/media/pci/ddbridge/ddbridge-i2c.h u8 adr, u8 reg, u8 val) reg 95 drivers/media/pci/ddbridge/ddbridge-i2c.h u8 msg[2] = { reg, val }; reg 101 drivers/media/pci/ddbridge/ddbridge-i2c.h u8 adr, u16 reg, u8 *val) reg 103 drivers/media/pci/ddbridge/ddbridge-i2c.h return i2c_read_regs16(adapter, adr, reg, val, 1); reg 107 drivers/media/pci/ddbridge/ddbridge-i2c.h u8 adr, u8 reg, u8 *val) reg 109 drivers/media/pci/ddbridge/ddbridge-i2c.h return i2c_read_regs(adapter, adr, reg, val, 1); reg 359 drivers/media/pci/dm1105/dm1105.c #define dm_io_mem(reg) ((unsigned long)(&dev->io_mem[reg])) reg 361 drivers/media/pci/dm1105/dm1105.c #define dm_readb(reg) inb(dm_io_mem(reg)) reg 362 drivers/media/pci/dm1105/dm1105.c #define dm_writeb(reg, value) outb((value), (dm_io_mem(reg))) reg 364 drivers/media/pci/dm1105/dm1105.c #define dm_readw(reg) inw(dm_io_mem(reg)) reg 365 drivers/media/pci/dm1105/dm1105.c #define dm_writew(reg, value) outw((value), (dm_io_mem(reg))) reg 367 drivers/media/pci/dm1105/dm1105.c #define dm_readl(reg) inl(dm_io_mem(reg)) reg 368 drivers/media/pci/dm1105/dm1105.c #define dm_writel(reg, value) outl((value), (dm_io_mem(reg))) reg 370 drivers/media/pci/dm1105/dm1105.c #define dm_andorl(reg, mask, value) \ reg 371 drivers/media/pci/dm1105/dm1105.c outl((inl(dm_io_mem(reg)) & ~(mask)) |\ reg 372 drivers/media/pci/dm1105/dm1105.c ((value) & (mask)), (dm_io_mem(reg))) reg 374 drivers/media/pci/dm1105/dm1105.c #define dm_setl(reg, bit) dm_andorl((reg), (bit), (bit)) reg 375 drivers/media/pci/dm1105/dm1105.c #define dm_clearl(reg, bit) dm_andorl((reg), (bit), 0) reg 811 drivers/media/pci/ivtv/ivtv-driver.h #define write_sync(val, reg) \ reg 812 drivers/media/pci/ivtv/ivtv-driver.h do { writel(val, reg); readl(reg); } while (0) reg 814 drivers/media/pci/ivtv/ivtv-driver.h #define read_reg(reg) readl(itv->reg_mem + (reg)) reg 815 drivers/media/pci/ivtv/ivtv-driver.h #define write_reg(val, reg) writel(val, itv->reg_mem + (reg)) reg 816 drivers/media/pci/ivtv/ivtv-driver.h #define write_reg_sync(val, reg) \ reg 817 drivers/media/pci/ivtv/ivtv-driver.h do { write_reg(val, reg); read_reg(reg); } while (0) reg 693 drivers/media/pci/ivtv/ivtv-ioctl.c static int ivtv_itvc(struct ivtv *itv, bool get, u64 reg, u64 *val) reg 697 drivers/media/pci/ivtv/ivtv-ioctl.c if (reg & 0x3) reg 699 drivers/media/pci/ivtv/ivtv-ioctl.c if (reg >= IVTV_REG_OFFSET && reg < IVTV_REG_OFFSET + IVTV_REG_SIZE) reg 701 drivers/media/pci/ivtv/ivtv-ioctl.c else if (itv->has_cx23415 && reg >= IVTV_DECODER_OFFSET && reg 702 drivers/media/pci/ivtv/ivtv-ioctl.c reg < IVTV_DECODER_OFFSET + IVTV_DECODER_SIZE) reg 704 drivers/media/pci/ivtv/ivtv-ioctl.c else if (reg < IVTV_ENCODER_SIZE) reg 710 drivers/media/pci/ivtv/ivtv-ioctl.c *val = readl(reg + reg_start); reg 712 drivers/media/pci/ivtv/ivtv-ioctl.c writel(*val, reg + reg_start); reg 716 drivers/media/pci/ivtv/ivtv-ioctl.c static int ivtv_g_register(struct file *file, void *fh, struct v4l2_dbg_register *reg) reg 720 drivers/media/pci/ivtv/ivtv-ioctl.c reg->size = 4; reg 721 drivers/media/pci/ivtv/ivtv-ioctl.c return ivtv_itvc(itv, true, reg->reg, ®->val); reg 724 drivers/media/pci/ivtv/ivtv-ioctl.c static int ivtv_s_register(struct file *file, void *fh, const struct v4l2_dbg_register *reg) reg 727 drivers/media/pci/ivtv/ivtv-ioctl.c u64 val = reg->val; reg 729 drivers/media/pci/ivtv/ivtv-ioctl.c return ivtv_itvc(itv, false, reg->reg, &val); reg 184 drivers/media/pci/mantis/mantis_core.c u32 reg; reg 186 drivers/media/pci/mantis/mantis_core.c reg = mmread(0x28); reg 190 drivers/media/pci/mantis/mantis_core.c reg |= 0x04; reg 191 drivers/media/pci/mantis/mantis_core.c mmwrite(reg, 0x28); reg 192 drivers/media/pci/mantis/mantis_core.c reg &= 0xff - 0x04; reg 193 drivers/media/pci/mantis/mantis_core.c mmwrite(reg, 0x28); reg 195 drivers/media/pci/mantis/mantis_core.c reg &= 0xff - 0x04; reg 196 drivers/media/pci/mantis/mantis_core.c mmwrite(reg, 0x28); reg 197 drivers/media/pci/mantis/mantis_core.c reg |= 0x04; reg 198 drivers/media/pci/mantis/mantis_core.c mmwrite(reg, 0x28); reg 27 drivers/media/pci/mantis/mantis_ioc.c static int read_eeprom_bytes(struct mantis_pci *mantis, u8 reg, u8 *data, u8 length) reg 31 drivers/media/pci/mantis/mantis_ioc.c u8 buf = reg; reg 86 drivers/media/pci/mantis/mantis_ioc.c u32 reg; reg 88 drivers/media/pci/mantis/mantis_ioc.c reg = mmread(MANTIS_CONTROL); reg 92 drivers/media/pci/mantis/mantis_ioc.c reg &= 0xff - MANTIS_BYPASS; reg 93 drivers/media/pci/mantis/mantis_ioc.c mmwrite(reg, MANTIS_CONTROL); reg 94 drivers/media/pci/mantis/mantis_ioc.c reg |= MANTIS_BYPASS; reg 95 drivers/media/pci/mantis/mantis_ioc.c mmwrite(reg, MANTIS_CONTROL); reg 100 drivers/media/pci/mantis/mantis_ioc.c reg |= MANTIS_BYPASS; reg 101 drivers/media/pci/mantis/mantis_ioc.c mmwrite(reg, MANTIS_CONTROL); reg 102 drivers/media/pci/mantis/mantis_ioc.c reg &= 0xff - MANTIS_BYPASS; reg 103 drivers/media/pci/mantis/mantis_ioc.c mmwrite(reg, MANTIS_CONTROL); reg 112 drivers/media/pci/mantis/mantis_uart.c u32 reg; reg 116 drivers/media/pci/mantis/mantis_uart.c reg = mmread(MANTIS_UART_BAUD); reg 120 drivers/media/pci/mantis/mantis_uart.c reg |= 0xd8; reg 123 drivers/media/pci/mantis/mantis_uart.c reg |= 0x6c; reg 126 drivers/media/pci/mantis/mantis_uart.c reg |= 0x36; reg 129 drivers/media/pci/mantis/mantis_uart.c reg |= 0x23; reg 132 drivers/media/pci/mantis/mantis_uart.c reg |= 0x11; reg 138 drivers/media/pci/mantis/mantis_uart.c mmwrite(reg, MANTIS_UART_BAUD); reg 400 drivers/media/pci/meye/meye.c static void mchip_sync(int reg) reg 405 drivers/media/pci/meye/meye.c if (reg == MCHIP_MM_FIFO_DATA) { reg 417 drivers/media/pci/meye/meye.c } else if (reg > 0x80) { reg 418 drivers/media/pci/meye/meye.c u32 mask = (reg < 0x100) ? MCHIP_HIC_STATUS_MCC_RDY reg 430 drivers/media/pci/meye/meye.c reg, status); reg 434 drivers/media/pci/meye/meye.c static inline void mchip_set(int reg, u32 v) reg 436 drivers/media/pci/meye/meye.c mchip_sync(reg); reg 437 drivers/media/pci/meye/meye.c writel(v, meye.mchip_mmregs + reg); reg 441 drivers/media/pci/meye/meye.c static inline u32 mchip_read(int reg) reg 443 drivers/media/pci/meye/meye.c mchip_sync(reg); reg 444 drivers/media/pci/meye/meye.c return readl(meye.mchip_mmregs + reg); reg 448 drivers/media/pci/meye/meye.c static inline int mchip_delay(u32 reg, u32 v) reg 451 drivers/media/pci/meye/meye.c while (--n && mchip_read(reg) != v) reg 144 drivers/media/pci/netup_unidvb/netup_unidvb_core.c u8 reg, mask; reg 153 drivers/media/pci/netup_unidvb/netup_unidvb_core.c reg = readb(ndev->bmmio0 + GPIO_REG_IO); reg 161 drivers/media/pci/netup_unidvb/netup_unidvb_core.c reg |= mask; reg 163 drivers/media/pci/netup_unidvb/netup_unidvb_core.c reg &= ~mask; reg 164 drivers/media/pci/netup_unidvb/netup_unidvb_core.c writeb(reg, ndev->bmmio0 + GPIO_REG_IO); reg 67 drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c u16 reg, tmp; reg 72 drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c reg = readw(&i2c->regs->twi_ctrl0_stat); reg 73 drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c writew(reg & ~TWI_IRQEN, &i2c->regs->twi_ctrl0_stat); reg 75 drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c "%s(): twi_ctrl0_state 0x%x\n", __func__, reg); reg 76 drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c if ((reg & TWI_IRQEN_COMPL) != 0 && (reg & TWI_IRQ_COMPL)) { reg 82 drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c if ((reg & TWI_IRQEN_ANACK) != 0 && (reg & TWI_IRQ_ANACK)) { reg 88 drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c if ((reg & TWI_IRQEN_DNACK) != 0 && (reg & TWI_IRQ_DNACK)) { reg 94 drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c if ((reg & TWI_IRQ_RX) != 0) { reg 102 drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c if ((reg & TWI_IRQ_TX) != 0) { reg 180 drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c u16 reg = readw(&i2c->regs->twi_ctrl0_stat); reg 182 drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c writew(TWI_IRQEN | reg, &i2c->regs->twi_ctrl0_stat); reg 206 drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c u16 reg; reg 257 drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c reg = readw( reg 259 drivers/media/pci/netup_unidvb/netup_unidvb_i2c.c writew(TWI_IRQEN | reg, reg 71 drivers/media/pci/netup_unidvb/netup_unidvb_spi.c u16 reg; reg 78 drivers/media/pci/netup_unidvb/netup_unidvb_spi.c reg = readw(&spi->regs->control_stat); reg 79 drivers/media/pci/netup_unidvb/netup_unidvb_spi.c if (!(reg & NETUP_SPI_CTRL_IRQ)) { reg 85 drivers/media/pci/netup_unidvb/netup_unidvb_spi.c writew(reg | NETUP_SPI_CTRL_IRQ, &spi->regs->control_stat); reg 86 drivers/media/pci/netup_unidvb/netup_unidvb_spi.c reg = readw(&spi->regs->control_stat); reg 87 drivers/media/pci/netup_unidvb/netup_unidvb_spi.c writew(reg & ~NETUP_SPI_CTRL_IMASK, &spi->regs->control_stat); reg 222 drivers/media/pci/netup_unidvb/netup_unidvb_spi.c u16 reg; reg 230 drivers/media/pci/netup_unidvb/netup_unidvb_spi.c reg = readw(&spi->regs->control_stat); reg 231 drivers/media/pci/netup_unidvb/netup_unidvb_spi.c writew(reg | NETUP_SPI_CTRL_IRQ, &spi->regs->control_stat); reg 232 drivers/media/pci/netup_unidvb/netup_unidvb_spi.c reg = readw(&spi->regs->control_stat); reg 233 drivers/media/pci/netup_unidvb/netup_unidvb_spi.c writew(reg & ~NETUP_SPI_CTRL_IMASK, &spi->regs->control_stat); reg 63 drivers/media/pci/ngene/ngene-cards.c u8 reg, u8 val) reg 65 drivers/media/pci/ngene/ngene-cards.c u8 msg[2] = {reg, val}; reg 78 drivers/media/pci/ngene/ngene-cards.c u16 reg, u8 *val) reg 80 drivers/media/pci/ngene/ngene-cards.c u8 msg[2] = {reg >> 8, reg & 0xff}; reg 89 drivers/media/pci/ngene/ngene-cards.c u8 adr, u8 reg, u8 *val, u8 len) reg 92 drivers/media/pci/ngene/ngene-cards.c .buf = ®, .len = 1}, reg 99 drivers/media/pci/ngene/ngene-cards.c static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val) reg 101 drivers/media/pci/ngene/ngene-cards.c return i2c_read_regs(adapter, adr, reg, val, 1); reg 788 drivers/media/pci/ngene/ngene-cards.c u8 adr, u16 reg, u8 data) reg 791 drivers/media/pci/ngene/ngene-cards.c u8 m[3] = {(reg >> 8), (reg & 0xff), data}; reg 803 drivers/media/pci/ngene/ngene-cards.c u8 adr, u16 reg, u8 *data, int len) reg 806 drivers/media/pci/ngene/ngene-cards.c u8 msg[2] = {(reg >> 8), (reg & 0xff)}; reg 125 drivers/media/pci/pluto2/pluto2.c static inline u32 pluto_readreg(struct pluto *pluto, u32 reg) reg 127 drivers/media/pci/pluto2/pluto2.c return readl(&pluto->io_mem[reg]); reg 130 drivers/media/pci/pluto2/pluto2.c static inline void pluto_writereg(struct pluto *pluto, u32 reg, u32 val) reg 132 drivers/media/pci/pluto2/pluto2.c writel(val, &pluto->io_mem[reg]); reg 135 drivers/media/pci/pluto2/pluto2.c static inline void pluto_rw(struct pluto *pluto, u32 reg, u32 mask, u32 bits) reg 137 drivers/media/pci/pluto2/pluto2.c u32 val = readl(&pluto->io_mem[reg]); reg 140 drivers/media/pci/pluto2/pluto2.c writel(val, &pluto->io_mem[reg]); reg 288 drivers/media/pci/pt1/pt1.c static void pt1_write_reg(struct pt1 *pt1, int reg, u32 data) reg 290 drivers/media/pci/pt1/pt1.c writel(data, pt1->regs + reg * 4); reg 293 drivers/media/pci/pt1/pt1.c static u32 pt1_read_reg(struct pt1 *pt1, int reg) reg 295 drivers/media/pci/pt1/pt1.c return readl(pt1->regs + reg * 4); reg 87 drivers/media/pci/pt3/pt3.c u8 reg; reg 126 drivers/media/pci/saa7134/saa7134-alsa.c int next_blk, reg = 0; reg 138 drivers/media/pci/saa7134/saa7134-alsa.c reg = SAA7134_RS_BA1(6); reg 142 drivers/media/pci/saa7134/saa7134-alsa.c reg = SAA7134_RS_BA2(6); reg 144 drivers/media/pci/saa7134/saa7134-alsa.c if (0 == reg) { reg 161 drivers/media/pci/saa7134/saa7134-alsa.c saa_writel(reg,next_blk * dev->dmasound.blksize); reg 171 drivers/media/pci/saa7134/saa7134-alsa.c dev->dmasound.recording_on = reg; reg 438 drivers/media/pci/saa7134/saa7134-tvaudio.c u32 reg; reg 450 drivers/media/pci/saa7134/saa7134-tvaudio.c reg = fm[ mode % ARRAY_SIZE(fm) ]; reg 451 drivers/media/pci/saa7134/saa7134-tvaudio.c saa_writeb(SAA7134_FM_DEMATRIX, reg); reg 682 drivers/media/pci/saa7134/saa7134-tvaudio.c int saa_dsp_writel(struct saa7134_dev *dev, int reg, u32 value) reg 686 drivers/media/pci/saa7134/saa7134-tvaudio.c audio_dbg(2, "dsp write reg 0x%x = 0x%06x\n", reg << 2, value); reg 690 drivers/media/pci/saa7134/saa7134-tvaudio.c saa_writel(reg,value); reg 712 drivers/media/pci/saa7134/saa7134-tvaudio.c u32 reg = 0; reg 720 drivers/media/pci/saa7134/saa7134-tvaudio.c reg = 0x02; reg 724 drivers/media/pci/saa7134/saa7134-tvaudio.c reg = 0x00; reg 728 drivers/media/pci/saa7134/saa7134-tvaudio.c reg = 0x09; reg 733 drivers/media/pci/saa7134/saa7134-tvaudio.c reg = 0x07; reg 739 drivers/media/pci/saa7134/saa7134-tvaudio.c saa_writel(0x594 >> 2, reg); reg 580 drivers/media/pci/saa7134/saa7134-video.c static void set_cliplist(struct saa7134_dev *dev, int reg, reg 591 drivers/media/pci/saa7134/saa7134-video.c saa_writeb(reg + 0, winbits); reg 592 drivers/media/pci/saa7134/saa7134-video.c saa_writeb(reg + 2, cl[i].position & 0xff); reg 593 drivers/media/pci/saa7134/saa7134-video.c saa_writeb(reg + 3, cl[i].position >> 8); reg 596 drivers/media/pci/saa7134/saa7134-video.c reg += 8; reg 598 drivers/media/pci/saa7134/saa7134-video.c for (; reg < 0x400; reg += 8) { reg 599 drivers/media/pci/saa7134/saa7134-video.c saa_writeb(reg+ 0, 0); reg 600 drivers/media/pci/saa7134/saa7134-video.c saa_writeb(reg + 1, 0); reg 601 drivers/media/pci/saa7134/saa7134-video.c saa_writeb(reg + 2, 0); reg 602 drivers/media/pci/saa7134/saa7134-video.c saa_writeb(reg + 3, 0); reg 1856 drivers/media/pci/saa7134/saa7134-video.c struct v4l2_dbg_register *reg) reg 1860 drivers/media/pci/saa7134/saa7134-video.c reg->val = saa_readb(reg->reg & 0xffffff); reg 1861 drivers/media/pci/saa7134/saa7134-video.c reg->size = 1; reg 1866 drivers/media/pci/saa7134/saa7134-video.c const struct v4l2_dbg_register *reg) reg 1870 drivers/media/pci/saa7134/saa7134-video.c saa_writeb(reg->reg & 0xffffff, reg->val); reg 690 drivers/media/pci/saa7134/saa7134.h #define saa_readl(reg) readl(dev->lmmio + (reg)) reg 691 drivers/media/pci/saa7134/saa7134.h #define saa_writel(reg,value) writel((value), dev->lmmio + (reg)); reg 692 drivers/media/pci/saa7134/saa7134.h #define saa_andorl(reg,mask,value) \ reg 693 drivers/media/pci/saa7134/saa7134.h writel((readl(dev->lmmio+(reg)) & ~(mask)) |\ reg 694 drivers/media/pci/saa7134/saa7134.h ((value) & (mask)), dev->lmmio+(reg)) reg 695 drivers/media/pci/saa7134/saa7134.h #define saa_setl(reg,bit) saa_andorl((reg),(bit),(bit)) reg 696 drivers/media/pci/saa7134/saa7134.h #define saa_clearl(reg,bit) saa_andorl((reg),(bit),0) reg 698 drivers/media/pci/saa7134/saa7134.h #define saa_readb(reg) readb(dev->bmmio + (reg)) reg 699 drivers/media/pci/saa7134/saa7134.h #define saa_writeb(reg,value) writeb((value), dev->bmmio + (reg)); reg 700 drivers/media/pci/saa7134/saa7134.h #define saa_andorb(reg,mask,value) \ reg 701 drivers/media/pci/saa7134/saa7134.h writeb((readb(dev->bmmio+(reg)) & ~(mask)) |\ reg 702 drivers/media/pci/saa7134/saa7134.h ((value) & (mask)), dev->bmmio+(reg)) reg 703 drivers/media/pci/saa7134/saa7134.h #define saa_setb(reg,bit) saa_andorb((reg),(bit),(bit)) reg 704 drivers/media/pci/saa7134/saa7134.h #define saa_clearb(reg,bit) saa_andorb((reg),(bit),0) reg 892 drivers/media/pci/saa7134/saa7134.h int saa_dsp_writel(struct saa7134_dev *dev, int reg, u32 value); reg 657 drivers/media/pci/saa7146/mxb.c static int vidioc_g_register(struct file *file, void *fh, struct v4l2_dbg_register *reg) reg 661 drivers/media/pci/saa7146/mxb.c if (reg->reg > pci_resource_len(dev->pci, 0) - 4) reg 663 drivers/media/pci/saa7146/mxb.c reg->val = saa7146_read(dev, reg->reg); reg 664 drivers/media/pci/saa7146/mxb.c reg->size = 4; reg 668 drivers/media/pci/saa7146/mxb.c static int vidioc_s_register(struct file *file, void *fh, const struct v4l2_dbg_register *reg) reg 672 drivers/media/pci/saa7146/mxb.c if (reg->reg > pci_resource_len(dev->pci, 0) - 4) reg 674 drivers/media/pci/saa7146/mxb.c saa7146_write(dev, reg->reg, reg->val); reg 608 drivers/media/pci/saa7164/saa7164-api.c static int saa7164_api_set_dif(struct saa7164_port *port, u8 reg, u8 val) reg 637 drivers/media/pci/saa7164/saa7164-api.c buf[0x08] = reg; reg 799 drivers/media/pci/saa7164/saa7164-api.c u8 reg[] = { 0x0f, 0x00 }; reg 806 drivers/media/pci/saa7164/saa7164-api.c return saa7164_api_i2c_read(&dev->i2c_bus[0], 0xa0 >> 1, sizeof(reg), reg 807 drivers/media/pci/saa7164/saa7164-api.c ®[0], 128, buf); reg 1353 drivers/media/pci/saa7164/saa7164-api.c int saa7164_api_i2c_read(struct saa7164_i2c *bus, u8 addr, u32 reglen, u8 *reg, reg 1374 drivers/media/pci/saa7164/saa7164-api.c memcpy((buf + 2 * sizeof(u32) + 0), reg, reglen); reg 736 drivers/media/pci/saa7164/saa7164-core.c u32 reg; reg 738 drivers/media/pci/saa7164/saa7164-core.c reg = saa7164_readl(SAA_DEVICE_VERSION); reg 740 drivers/media/pci/saa7164/saa7164-core.c (reg & 0x0000fc00) >> 10, reg 741 drivers/media/pci/saa7164/saa7164-core.c (reg & 0x000003e0) >> 5, reg 742 drivers/media/pci/saa7164/saa7164-core.c (reg & 0x0000001f), reg 743 drivers/media/pci/saa7164/saa7164-core.c (reg & 0xffff0000) >> 16, reg 744 drivers/media/pci/saa7164/saa7164-core.c reg); reg 746 drivers/media/pci/saa7164/saa7164-core.c return reg; reg 26 drivers/media/pci/saa7164/saa7164-fw.c static int saa7164_dl_wait_ack(struct saa7164_dev *dev, u32 reg) reg 29 drivers/media/pci/saa7164/saa7164-fw.c while ((saa7164_readl(reg) & 0x01) == 0) { reg 42 drivers/media/pci/saa7164/saa7164-fw.c static int saa7164_dl_wait_clr(struct saa7164_dev *dev, u32 reg) reg 45 drivers/media/pci/saa7164/saa7164-fw.c while (saa7164_readl(reg) & 0x01) { reg 63 drivers/media/pci/saa7164/saa7164-fw.c u32 reg, timeout, offset; reg 101 drivers/media/pci/saa7164/saa7164-fw.c reg = saa7164_readl(dlflag); reg 102 drivers/media/pci/saa7164/saa7164-fw.c dprintk(DBGLVL_FW, "%s() dlflag (0x%x)= 0x%x\n", __func__, dlflag, reg); reg 103 drivers/media/pci/saa7164/saa7164-fw.c if (reg == 1) reg 520 drivers/media/pci/saa7164/saa7164.h int saa7164_api_i2c_read(struct saa7164_i2c *bus, u8 addr, u32 reglen, u8 *reg, reg 618 drivers/media/pci/saa7164/saa7164.h #define saa7164_readl(reg) readl(dev->lmmio + ((reg) >> 2)) reg 619 drivers/media/pci/saa7164/saa7164.h #define saa7164_writel(reg, value) writel((value), dev->lmmio + ((reg) >> 2)) reg 621 drivers/media/pci/saa7164/saa7164.h #define saa7164_readb(reg) readl(dev->bmmio + (reg)) reg 622 drivers/media/pci/saa7164/saa7164.h #define saa7164_writeb(reg, value) writel((value), dev->bmmio + (reg)) reg 235 drivers/media/pci/smipcie/smipcie-main.c static int smi_read_eeprom(struct i2c_adapter *i2c, u16 reg, u8 *data, u16 size) reg 238 drivers/media/pci/smipcie/smipcie-main.c u8 b0[2] = { (reg >> 8) & 0xff, reg & 0xff }; reg 251 drivers/media/pci/smipcie/smipcie-main.c __func__, reg, ret); reg 295 drivers/media/pci/smipcie/smipcie.h #define smi_read(reg) readl(dev->lmmio + ((reg)>>2)) reg 296 drivers/media/pci/smipcie/smipcie.h #define smi_write(reg, value) writel((value), dev->lmmio + ((reg)>>2)) reg 298 drivers/media/pci/smipcie/smipcie.h #define smi_andor(reg, mask, value) \ reg 299 drivers/media/pci/smipcie/smipcie.h writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\ reg 300 drivers/media/pci/smipcie/smipcie.h ((value) & (mask)), dev->lmmio+((reg)>>2)) reg 302 drivers/media/pci/smipcie/smipcie.h #define smi_set(reg, bit) smi_andor((reg), (bit), (bit)) reg 303 drivers/media/pci/smipcie/smipcie.h #define smi_clear(reg, bit) smi_andor((reg), (bit), 0) reg 132 drivers/media/pci/solo6x10/solo6x10-enc.c u32 reg; reg 140 drivers/media/pci/solo6x10/solo6x10-enc.c reg = solo_reg_read(solo_dev, SOLO_VE_OSD_CH); reg 143 drivers/media/pci/solo6x10/solo6x10-enc.c reg &= ~(1 << solo_enc->ch); reg 162 drivers/media/pci/solo6x10/solo6x10-enc.c reg |= (1 << solo_enc->ch); reg 165 drivers/media/pci/solo6x10/solo6x10-enc.c solo_reg_write(solo_dev, SOLO_VE_OSD_CH, reg); reg 176 drivers/media/pci/solo6x10/solo6x10-enc.c unsigned int idx, reg; reg 186 drivers/media/pci/solo6x10/solo6x10-enc.c reg = SOLO_VE_JPEG_QP_CH_L; reg 190 drivers/media/pci/solo6x10/solo6x10-enc.c reg = SOLO_VE_JPEG_QP_CH_H; reg 199 drivers/media/pci/solo6x10/solo6x10-enc.c solo_reg_write(solo_dev, reg, solo_dev->jpeg_qp[idx]); reg 275 drivers/media/pci/solo6x10/solo6x10.h static inline u32 solo_reg_read(struct solo_dev *solo_dev, int reg) reg 277 drivers/media/pci/solo6x10/solo6x10.h return readl(solo_dev->reg_base + reg); reg 280 drivers/media/pci/solo6x10/solo6x10.h static inline void solo_reg_write(struct solo_dev *solo_dev, int reg, reg 285 drivers/media/pci/solo6x10/solo6x10.h writel(data, solo_dev->reg_base + reg); reg 203 drivers/media/pci/sta2x11/sta2x11_vip.c static inline void reg_write(struct sta2x11_vip *vip, unsigned int reg, u32 val) reg 205 drivers/media/pci/sta2x11/sta2x11_vip.c iowrite32((val), (vip->iomem)+(reg)); reg 208 drivers/media/pci/sta2x11/sta2x11_vip.c static inline u32 reg_read(struct sta2x11_vip *vip, unsigned int reg) reg 210 drivers/media/pci/sta2x11/sta2x11_vip.c return ioread32((vip->iomem)+(reg)); reg 1405 drivers/media/pci/ttpci/av7110.c int i2c_writereg(struct av7110 *av7110, u8 id, u8 reg, u8 val) reg 1407 drivers/media/pci/ttpci/av7110.c u8 msg[2] = { reg, val }; reg 1417 drivers/media/pci/ttpci/av7110.c u8 i2c_readreg(struct av7110 *av7110, u8 id, u8 reg) reg 1426 drivers/media/pci/ttpci/av7110.c mm1[0] = reg; reg 306 drivers/media/pci/ttpci/av7110.h extern int i2c_writereg(struct av7110 *av7110, u8 id, u8 reg, u8 val); reg 307 drivers/media/pci/ttpci/av7110.h extern u8 i2c_readreg(struct av7110 *av7110, u8 id, u8 reg); reg 308 drivers/media/pci/ttpci/av7110.h extern int msp_writereg(struct av7110 *av7110, u8 dev, u16 reg, u16 val); reg 27 drivers/media/pci/ttpci/av7110_v4l.c int msp_writereg(struct av7110 *av7110, u8 dev, u16 reg, u16 val) reg 29 drivers/media/pci/ttpci/av7110_v4l.c u8 msg[5] = { dev, reg >> 8, reg & 0xff, val >> 8 , val & 0xff }; reg 45 drivers/media/pci/ttpci/av7110_v4l.c av7110->dvb_adapter.num, reg, val); reg 51 drivers/media/pci/ttpci/av7110_v4l.c static int msp_readreg(struct av7110 *av7110, u8 dev, u16 reg, u16 *val) reg 53 drivers/media/pci/ttpci/av7110_v4l.c u8 msg1[3] = { dev, reg >> 8, reg & 0xff }; reg 75 drivers/media/pci/ttpci/av7110_v4l.c av7110->dvb_adapter.num, reg); reg 122 drivers/media/pci/ttpci/av7110_v4l.c static int ves1820_writereg(struct saa7146_dev *dev, u8 addr, u8 reg, u8 data) reg 125 drivers/media/pci/ttpci/av7110_v4l.c u8 buf[] = { 0x00, reg, data }; reg 77 drivers/media/pci/ttpci/budget-av.c static u8 i2c_readreg(struct i2c_adapter *i2c, u8 id, u8 reg) reg 86 drivers/media/pci/ttpci/budget-av.c mm1[0] = reg; reg 97 drivers/media/pci/ttpci/budget-av.c static int i2c_readregs(struct i2c_adapter *i2c, u8 id, u8 reg, u8 * buf, u8 len) reg 99 drivers/media/pci/ttpci/budget-av.c u8 mm1[] = { reg }; reg 111 drivers/media/pci/ttpci/budget-av.c static int i2c_writereg(struct i2c_adapter *i2c, u8 id, u8 reg, u8 val) reg 113 drivers/media/pci/ttpci/budget-av.c u8 msg[2] = { reg, val }; reg 414 drivers/media/pci/ttpci/budget.c static int i2c_readreg(struct i2c_adapter *i2c, u8 adr, u8 reg) reg 418 drivers/media/pci/ttpci/budget.c { .addr = adr, .flags = 0, .buf = ®, .len = 1 }, reg 842 drivers/media/pci/tw5864/tw5864-video.c struct v4l2_dbg_register *reg) reg 847 drivers/media/pci/tw5864/tw5864-video.c if (reg->reg < INDIR_SPACE_MAP_SHIFT) { reg 848 drivers/media/pci/tw5864/tw5864-video.c if (reg->reg > 0x87fff) reg 850 drivers/media/pci/tw5864/tw5864-video.c reg->size = 4; reg 851 drivers/media/pci/tw5864/tw5864-video.c reg->val = tw_readl(reg->reg); reg 853 drivers/media/pci/tw5864/tw5864-video.c __u64 indir_addr = reg->reg - INDIR_SPACE_MAP_SHIFT; reg 857 drivers/media/pci/tw5864/tw5864-video.c reg->size = 1; reg 858 drivers/media/pci/tw5864/tw5864-video.c reg->val = tw_indir_readb(reg->reg); reg 864 drivers/media/pci/tw5864/tw5864-video.c const struct v4l2_dbg_register *reg) reg 869 drivers/media/pci/tw5864/tw5864-video.c if (reg->reg < INDIR_SPACE_MAP_SHIFT) { reg 870 drivers/media/pci/tw5864/tw5864-video.c if (reg->reg > 0x87fff) reg 872 drivers/media/pci/tw5864/tw5864-video.c tw_writel(reg->reg, reg->val); reg 874 drivers/media/pci/tw5864/tw5864-video.c __u64 indir_addr = reg->reg - INDIR_SPACE_MAP_SHIFT; reg 878 drivers/media/pci/tw5864/tw5864-video.c tw_indir_writeb(reg->reg, reg->val); reg 166 drivers/media/pci/tw5864/tw5864.h #define tw_readl(reg) readl(dev->mmio + reg) reg 167 drivers/media/pci/tw5864/tw5864.h #define tw_mask_readl(reg, mask) \ reg 168 drivers/media/pci/tw5864/tw5864.h (tw_readl(reg) & (mask)) reg 169 drivers/media/pci/tw5864/tw5864.h #define tw_mask_shift_readl(reg, mask, shift) \ reg 170 drivers/media/pci/tw5864/tw5864.h (tw_mask_readl((reg), ((mask) << (shift))) >> (shift)) reg 172 drivers/media/pci/tw5864/tw5864.h #define tw_writel(reg, value) writel((value), dev->mmio + reg) reg 173 drivers/media/pci/tw5864/tw5864.h #define tw_mask_writel(reg, mask, value) \ reg 174 drivers/media/pci/tw5864/tw5864.h tw_writel(reg, (tw_readl(reg) & ~(mask)) | ((value) & (mask))) reg 175 drivers/media/pci/tw5864/tw5864.h #define tw_mask_shift_writel(reg, mask, shift, value) \ reg 176 drivers/media/pci/tw5864/tw5864.h tw_mask_writel((reg), ((mask) << (shift)), ((value) << (shift))) reg 178 drivers/media/pci/tw5864/tw5864.h #define tw_setl(reg, bit) tw_writel((reg), tw_readl(reg) | (bit)) reg 179 drivers/media/pci/tw5864/tw5864.h #define tw_clearl(reg, bit) tw_writel((reg), tw_readl(reg) & ~(bit)) reg 181 drivers/media/pci/tw68/tw68-risc.c #define RISC_OP(reg) (((reg) >> 28) & 7) reg 825 drivers/media/pci/tw68/tw68-video.c struct v4l2_dbg_register *reg) reg 829 drivers/media/pci/tw68/tw68-video.c if (reg->size == 1) reg 830 drivers/media/pci/tw68/tw68-video.c reg->val = tw_readb(reg->reg); reg 832 drivers/media/pci/tw68/tw68-video.c reg->val = tw_readl(reg->reg); reg 837 drivers/media/pci/tw68/tw68-video.c const struct v4l2_dbg_register *reg) reg 841 drivers/media/pci/tw68/tw68-video.c if (reg->size == 1) reg 842 drivers/media/pci/tw68/tw68-video.c tw_writeb(reg->reg, reg->val); reg 844 drivers/media/pci/tw68/tw68-video.c tw_writel(reg->reg & 0xffff, reg->val); reg 973 drivers/media/pci/tw68/tw68-video.c __u32 reg; reg 1012 drivers/media/pci/tw68/tw68-video.c reg = tw_readl(TW68_DMAC) & TW68_FIFO_EN; reg 1015 drivers/media/pci/tw68/tw68-video.c tw_setl(TW68_DMAC, reg); reg 167 drivers/media/pci/tw68/tw68.h #define tw_readl(reg) readl(dev->lmmio + ((reg) >> 2)) reg 168 drivers/media/pci/tw68/tw68.h #define tw_readb(reg) readb(dev->bmmio + (reg)) reg 169 drivers/media/pci/tw68/tw68.h #define tw_writel(reg, value) writel((value), dev->lmmio + ((reg) >> 2)) reg 170 drivers/media/pci/tw68/tw68.h #define tw_writeb(reg, value) writeb((value), dev->bmmio + (reg)) reg 172 drivers/media/pci/tw68/tw68.h #define tw_andorl(reg, mask, value) \ reg 173 drivers/media/pci/tw68/tw68.h writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\ reg 174 drivers/media/pci/tw68/tw68.h ((value) & (mask)), dev->lmmio+((reg)>>2)) reg 175 drivers/media/pci/tw68/tw68.h #define tw_andorb(reg, mask, value) \ reg 176 drivers/media/pci/tw68/tw68.h writeb((readb(dev->bmmio + (reg)) & ~(mask)) |\ reg 177 drivers/media/pci/tw68/tw68.h ((value) & (mask)), dev->bmmio+(reg)) reg 178 drivers/media/pci/tw68/tw68.h #define tw_setl(reg, bit) tw_andorl((reg), (bit), (bit)) reg 179 drivers/media/pci/tw68/tw68.h #define tw_setb(reg, bit) tw_andorb((reg), (bit), (bit)) reg 180 drivers/media/pci/tw68/tw68.h #define tw_clearl(reg, bit) \ reg 181 drivers/media/pci/tw68/tw68.h writel((readl(dev->lmmio + ((reg) >> 2)) & ~(bit)), \ reg 182 drivers/media/pci/tw68/tw68.h dev->lmmio + ((reg) >> 2)) reg 183 drivers/media/pci/tw68/tw68.h #define tw_clearb(reg, bit) \ reg 184 drivers/media/pci/tw68/tw68.h writeb((readb(dev->bmmio+(reg)) & ~(bit)), \ reg 185 drivers/media/pci/tw68/tw68.h dev->bmmio + (reg)) reg 73 drivers/media/pci/tw686x/tw686x-audio.c u32 reg = pb ? ADMA_B_ADDR[ch] : ADMA_P_ADDR[ch]; reg 74 drivers/media/pci/tw686x/tw686x-audio.c reg_write(dev, reg, next->dma); reg 164 drivers/media/pci/tw686x/tw686x-audio.c u32 reg; reg 167 drivers/media/pci/tw686x/tw686x-audio.c reg = ((125000000 / rt->rate) << 16) + reg 170 drivers/media/pci/tw686x/tw686x-audio.c reg_write(dev, AUDIO_CONTROL2, reg); reg 174 drivers/media/pci/tw686x/tw686x-audio.c u32 reg; reg 177 drivers/media/pci/tw686x/tw686x-audio.c reg = reg_read(dev, AUDIO_CONTROL1); reg 178 drivers/media/pci/tw686x/tw686x-audio.c reg &= ~(AUDIO_DMA_SIZE_MASK << AUDIO_DMA_SIZE_SHIFT); reg 179 drivers/media/pci/tw686x/tw686x-audio.c reg |= period_size << AUDIO_DMA_SIZE_SHIFT; reg 181 drivers/media/pci/tw686x/tw686x-audio.c reg_write(dev, AUDIO_CONTROL1, reg); reg 338 drivers/media/pci/tw686x/tw686x-audio.c u32 reg = pb ? ADMA_B_ADDR[ac->ch] : ADMA_P_ADDR[ac->ch]; reg 351 drivers/media/pci/tw686x/tw686x-audio.c reg_write(dev, reg, ac->dma_descs[pb].phys); reg 105 drivers/media/pci/tw686x/tw686x-video.c u32 reg = pb ? VDMA_B_ADDR[vc->ch] : VDMA_P_ADDR[vc->ch]; reg 123 drivers/media/pci/tw686x/tw686x-video.c reg_write(dev, reg, vc->dma_descs[pb].phys); reg 160 drivers/media/pci/tw686x/tw686x-video.c u32 reg = pb ? VDMA_B_ADDR[vc->ch] : VDMA_P_ADDR[vc->ch]; reg 168 drivers/media/pci/tw686x/tw686x-video.c reg_write(vc->dev, reg, phys); reg 274 drivers/media/pci/tw686x/tw686x-video.c u32 reg = pb ? DMA_PAGE_TABLE1_ADDR[vc->ch] : reg 289 drivers/media/pci/tw686x/tw686x-video.c reg_write(dev, reg, desc->phys); reg 145 drivers/media/pci/tw686x/tw686x.h static inline uint32_t reg_read(struct tw686x_dev *dev, unsigned int reg) reg 147 drivers/media/pci/tw686x/tw686x.h return readl(dev->mmio + reg); reg 150 drivers/media/pci/tw686x/tw686x.h static inline void reg_write(struct tw686x_dev *dev, unsigned int reg, reg 153 drivers/media/pci/tw686x/tw686x.h writel(value, dev->mmio + reg); reg 402 drivers/media/platform/aspeed-video.c static void aspeed_video_update(struct aspeed_video *video, u32 reg, u32 clear, reg 405 drivers/media/platform/aspeed-video.c u32 t = readl(video->base + reg); reg 410 drivers/media/platform/aspeed-video.c writel(t, video->base + reg); reg 411 drivers/media/platform/aspeed-video.c dev_dbg(video->dev, "update %03x[%08x -> %08x]\n", reg, before, reg 412 drivers/media/platform/aspeed-video.c readl(video->base + reg)); reg 415 drivers/media/platform/aspeed-video.c static u32 aspeed_video_read(struct aspeed_video *video, u32 reg) reg 417 drivers/media/platform/aspeed-video.c u32 t = readl(video->base + reg); reg 419 drivers/media/platform/aspeed-video.c dev_dbg(video->dev, "read %03x[%08x]\n", reg, t); reg 423 drivers/media/platform/aspeed-video.c static void aspeed_video_write(struct aspeed_video *video, u32 reg, u32 val) reg 425 drivers/media/platform/aspeed-video.c writel(val, video->base + reg); reg 426 drivers/media/platform/aspeed-video.c dev_dbg(video->dev, "write %03x[%08x]\n", reg, reg 427 drivers/media/platform/aspeed-video.c readl(video->base + reg)); reg 136 drivers/media/platform/atmel/atmel-isi.c static void isi_writel(struct atmel_isi *isi, u32 reg, u32 val) reg 138 drivers/media/platform/atmel/atmel-isi.c writel(val, isi->regs + reg); reg 140 drivers/media/platform/atmel/atmel-isi.c static u32 isi_readl(struct atmel_isi *isi, u32 reg) reg 142 drivers/media/platform/atmel/atmel-isi.c return readl(isi->regs + reg); reg 109 drivers/media/platform/cadence/cdns-csi2rx.c u32 reg; reg 118 drivers/media/platform/cadence/cdns-csi2rx.c reg = csi2rx->num_lanes << 8; reg 120 drivers/media/platform/cadence/cdns-csi2rx.c reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, csi2rx->lanes[i]); reg 134 drivers/media/platform/cadence/cdns-csi2rx.c reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, i + 1); reg 137 drivers/media/platform/cadence/cdns-csi2rx.c writel(reg, csi2rx->base + CSI2RX_STATIC_CFG_REG); reg 243 drivers/media/platform/cadence/cdns-csi2tx.c static void csi2tx_dphy_init_finish(struct csi2tx_priv *csi2tx, u32 reg) reg 250 drivers/media/platform/cadence/cdns-csi2tx.c reg |= CSI2TX_DPHY_CFG_CLK_ENABLE; reg 252 drivers/media/platform/cadence/cdns-csi2tx.c reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i] - 1); reg 253 drivers/media/platform/cadence/cdns-csi2tx.c writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG); reg 258 drivers/media/platform/cadence/cdns-csi2tx.c reg &= ~CSI2TX_DPHY_CFG_MODE_MASK; reg 259 drivers/media/platform/cadence/cdns-csi2tx.c writel(reg | CSI2TX_DPHY_CFG_MODE_HS, reg 266 drivers/media/platform/cadence/cdns-csi2tx.c u32 reg; reg 272 drivers/media/platform/cadence/cdns-csi2tx.c reg = CSI2TX_DPHY_CFG_CLK_RESET | CSI2TX_DPHY_CFG_MODE_LPDT; reg 274 drivers/media/platform/cadence/cdns-csi2tx.c reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i] - 1); reg 275 drivers/media/platform/cadence/cdns-csi2tx.c writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG); reg 277 drivers/media/platform/cadence/cdns-csi2tx.c csi2tx_dphy_init_finish(csi2tx, reg); reg 283 drivers/media/platform/cadence/cdns-csi2tx.c u32 reg; reg 288 drivers/media/platform/cadence/cdns-csi2tx.c reg = CSI2TX_V2_DPHY_CFG_RESET | CSI2TX_V2_DPHY_CFG_MODE_LPDT; reg 289 drivers/media/platform/cadence/cdns-csi2tx.c writel(reg, csi2tx->base + CSI2TX_V2_DPHY_CFG_REG); reg 291 drivers/media/platform/cadence/cdns-csi2tx.c csi2tx_dphy_init_finish(csi2tx, reg); reg 1475 drivers/media/platform/coda/coda-bit.c u32 reg; reg 1588 drivers/media/platform/coda/coda-bit.c reg = CODA9_CMD_ENC_PIC_SRC_ADDR_Y; reg 1590 drivers/media/platform/coda/coda-bit.c reg = CODA_CMD_ENC_PIC_SRC_ADDR_Y; reg 1592 drivers/media/platform/coda/coda-bit.c coda_write_base(ctx, q_data_src, src_buf, reg); reg 75 drivers/media/platform/coda/coda-common.c void coda_write(struct coda_dev *dev, u32 data, u32 reg) reg 78 drivers/media/platform/coda/coda-common.c "%s: data=0x%x, reg=0x%x\n", __func__, data, reg); reg 79 drivers/media/platform/coda/coda-common.c writel(data, dev->regs_base + reg); reg 82 drivers/media/platform/coda/coda-common.c unsigned int coda_read(struct coda_dev *dev, u32 reg) reg 86 drivers/media/platform/coda/coda-common.c data = readl(dev->regs_base + reg); reg 88 drivers/media/platform/coda/coda-common.c "%s: data=0x%x, reg=0x%x\n", __func__, data, reg); reg 286 drivers/media/platform/coda/coda.h void coda_write(struct coda_dev *dev, u32 data, u32 reg); reg 287 drivers/media/platform/coda/coda.h unsigned int coda_read(struct coda_dev *dev, u32 reg); reg 230 drivers/media/platform/davinci/vpif.c static inline void vpif_wr_bit(u32 reg, u32 bit, u32 val) reg 233 drivers/media/platform/davinci/vpif.c vpif_set_bit(reg, bit); reg 235 drivers/media/platform/davinci/vpif.c vpif_clr_bit(reg, bit); reg 322 drivers/media/platform/davinci/vpif.c u32 value, ch_nip, reg; reg 330 drivers/media/platform/davinci/vpif.c reg = vpifregs[i].ch_ctrl; reg 336 drivers/media/platform/davinci/vpif.c vpif_wr_bit(reg, ch_nip, config->frm_fmt); reg 337 drivers/media/platform/davinci/vpif.c vpif_wr_bit(reg, VPIF_CH_YC_MUX_BIT, config->ycmux_mode); reg 338 drivers/media/platform/davinci/vpif.c vpif_wr_bit(reg, VPIF_CH_INPUT_FIELD_FRAME_BIT, reg 342 drivers/media/platform/davinci/vpif.c vpif_clr_bit(reg, VPIF_CH_SDR_FMT_BIT); reg 343 drivers/media/platform/davinci/vpif.c vpif_wr_bit(reg, VPIF_CH_DATA_MODE_BIT, config->capture_format); reg 346 drivers/media/platform/davinci/vpif.c vpif_set_bit(reg, VPIF_DISPLAY_PIX_EN_BIT); reg 349 drivers/media/platform/davinci/vpif.c vpif_wr_bit(reg, VPIF_CH_FID_POLARITY_BIT, reg 351 drivers/media/platform/davinci/vpif.c vpif_wr_bit(reg, VPIF_CH_V_VALID_POLARITY_BIT, reg 353 drivers/media/platform/davinci/vpif.c vpif_wr_bit(reg, VPIF_CH_H_VALID_POLARITY_BIT, reg 356 drivers/media/platform/davinci/vpif.c value = regr(reg); reg 362 drivers/media/platform/davinci/vpif.c regw(value, reg); reg 32 drivers/media/platform/davinci/vpif.h #define regr(reg) readl((reg) + vpif_base) reg 33 drivers/media/platform/davinci/vpif.h #define regw(value, reg) writel(value, (reg + vpif_base)) reg 137 drivers/media/platform/davinci/vpif.h static inline void vpif_set_bit(u32 reg, u32 bit) reg 139 drivers/media/platform/davinci/vpif.h regw((regr(reg)) | (0x01 << bit), reg); reg 142 drivers/media/platform/davinci/vpif.h static inline void vpif_clr_bit(u32 reg, u32 bit) reg 144 drivers/media/platform/davinci/vpif.h regw(((regr(reg)) & ~(0x01 << bit)), reg); reg 761 drivers/media/platform/exynos4-is/fimc-reg.c s32 reg; reg 764 drivers/media/platform/exynos4-is/fimc-reg.c reg = readl(dev->regs + FIMC_REG_CISTATUS2) & 0x3f; reg 765 drivers/media/platform/exynos4-is/fimc-reg.c return reg - 1; reg 768 drivers/media/platform/exynos4-is/fimc-reg.c reg = readl(dev->regs + FIMC_REG_CISTATUS); reg 770 drivers/media/platform/exynos4-is/fimc-reg.c return (reg & FIMC_REG_CISTATUS_FRAMECNT_MASK) >> reg 777 drivers/media/platform/exynos4-is/fimc-reg.c s32 reg; reg 782 drivers/media/platform/exynos4-is/fimc-reg.c reg = readl(dev->regs + FIMC_REG_CISTATUS2); reg 783 drivers/media/platform/exynos4-is/fimc-reg.c return ((reg >> 7) & 0x3f) - 1; reg 540 drivers/media/platform/exynos4-is/media-dev.c u32 reg = 0; reg 545 drivers/media/platform/exynos4-is/media-dev.c of_property_read_u32(np, "reg", ®); reg 547 drivers/media/platform/exynos4-is/media-dev.c return reg - FIMC_INPUT_MIPI_CSI2_0; reg 1295 drivers/media/platform/fsl-viu.c static void viu_reset(struct viu_reg __iomem *reg) reg 1297 drivers/media/platform/fsl-viu.c out_be32(®->status_cfg, 0); reg 1298 drivers/media/platform/fsl-viu.c out_be32(®->luminance, 0x9512a254); reg 1299 drivers/media/platform/fsl-viu.c out_be32(®->chroma_r, 0x03310000); reg 1300 drivers/media/platform/fsl-viu.c out_be32(®->chroma_g, 0x06600f38); reg 1301 drivers/media/platform/fsl-viu.c out_be32(®->chroma_b, 0x00000409); reg 1302 drivers/media/platform/fsl-viu.c out_be32(®->field_base_addr, 0); reg 1303 drivers/media/platform/fsl-viu.c out_be32(®->dma_inc, 0); reg 1304 drivers/media/platform/fsl-viu.c out_be32(®->picture_count, 0x01e002d0); reg 1305 drivers/media/platform/fsl-viu.c out_be32(®->req_alarm, 0x00000090); reg 1306 drivers/media/platform/fsl-viu.c out_be32(®->alpha, 0x000000ff); reg 1567 drivers/media/platform/marvell-ccic/mcam-core.c struct v4l2_dbg_register *reg) reg 1571 drivers/media/platform/marvell-ccic/mcam-core.c if (reg->reg > cam->regs_size - 4) reg 1573 drivers/media/platform/marvell-ccic/mcam-core.c reg->val = mcam_reg_read(cam, reg->reg); reg 1574 drivers/media/platform/marvell-ccic/mcam-core.c reg->size = 4; reg 1579 drivers/media/platform/marvell-ccic/mcam-core.c const struct v4l2_dbg_register *reg) reg 1583 drivers/media/platform/marvell-ccic/mcam-core.c if (reg->reg > cam->regs_size - 4) reg 1585 drivers/media/platform/marvell-ccic/mcam-core.c mcam_reg_write(cam, reg->reg, reg->val); reg 199 drivers/media/platform/marvell-ccic/mcam-core.h static inline void mcam_reg_write(struct mcam_camera *cam, unsigned int reg, reg 202 drivers/media/platform/marvell-ccic/mcam-core.h iowrite32(val, cam->regs + reg); reg 206 drivers/media/platform/marvell-ccic/mcam-core.h unsigned int reg) reg 208 drivers/media/platform/marvell-ccic/mcam-core.h return ioread32(cam->regs + reg); reg 212 drivers/media/platform/marvell-ccic/mcam-core.h static inline void mcam_reg_write_mask(struct mcam_camera *cam, unsigned int reg, reg 215 drivers/media/platform/marvell-ccic/mcam-core.h unsigned int v = mcam_reg_read(cam, reg); reg 218 drivers/media/platform/marvell-ccic/mcam-core.h mcam_reg_write(cam, reg, v); reg 222 drivers/media/platform/marvell-ccic/mcam-core.h unsigned int reg, unsigned int val) reg 224 drivers/media/platform/marvell-ccic/mcam-core.h mcam_reg_write_mask(cam, reg, 0, val); reg 228 drivers/media/platform/marvell-ccic/mcam-core.h unsigned int reg, unsigned int val) reg 230 drivers/media/platform/marvell-ccic/mcam-core.h mcam_reg_write_mask(cam, reg, val, val); reg 376 drivers/media/platform/meson/ao-cec-g12a.c u32 reg = FIELD_PREP(CECB_RW_ADDR, addr); reg 379 drivers/media/platform/meson/ao-cec-g12a.c ret = regmap_write(ao_cec->regmap, CECB_RW_REG, reg); reg 383 drivers/media/platform/meson/ao-cec-g12a.c ret = regmap_read_poll_timeout(ao_cec->regmap, CECB_RW_REG, reg, reg 384 drivers/media/platform/meson/ao-cec-g12a.c !(reg & CECB_RW_BUS_BUSY), reg 389 drivers/media/platform/meson/ao-cec-g12a.c ret = regmap_read(ao_cec->regmap, CECB_RW_REG, ®); reg 391 drivers/media/platform/meson/ao-cec-g12a.c *data = FIELD_GET(CECB_RW_RD_DATA, reg); reg 400 drivers/media/platform/meson/ao-cec-g12a.c u32 reg = FIELD_PREP(CECB_RW_ADDR, addr) | reg 404 drivers/media/platform/meson/ao-cec-g12a.c return regmap_write(ao_cec->regmap, CECB_RW_REG, reg); reg 248 drivers/media/platform/meson/ao-cec.c u32 reg = FIELD_PREP(CEC_RW_ADDR, address); reg 260 drivers/media/platform/meson/ao-cec.c writel_relaxed(reg, ao_cec->base + CEC_RW_REG); reg 281 drivers/media/platform/meson/ao-cec.c u32 reg = FIELD_PREP(CEC_RW_ADDR, address) | reg 295 drivers/media/platform/meson/ao-cec.c writel_relaxed(reg, ao_cec->base + CEC_RW_REG); reg 429 drivers/media/platform/meson/ao-cec.c u8 reg; reg 431 drivers/media/platform/meson/ao-cec.c meson_ao_cec_read(ao_cec, CEC_RX_MSG_STATUS, ®, &ret); reg 432 drivers/media/platform/meson/ao-cec.c if (reg != RX_DONE) reg 435 drivers/media/platform/meson/ao-cec.c meson_ao_cec_read(ao_cec, CEC_RX_NUM_MSG, ®, &ret); reg 436 drivers/media/platform/meson/ao-cec.c if (reg != 1) reg 439 drivers/media/platform/meson/ao-cec.c meson_ao_cec_read(ao_cec, CEC_RX_MSG_LENGTH, ®, &ret); reg 441 drivers/media/platform/meson/ao-cec.c ao_cec->rx_msg.len = reg + 1; reg 520 drivers/media/platform/meson/ao-cec.c u8 reg; reg 522 drivers/media/platform/meson/ao-cec.c meson_ao_cec_read(ao_cec, CEC_TX_MSG_STATUS, ®, &ret); reg 526 drivers/media/platform/meson/ao-cec.c if (reg == TX_BUSY) { reg 26 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c static inline int mtk_jpeg_verify_align(u32 val, int align, u32 reg) reg 29 drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c pr_err("mtk-jpeg: write reg %x without %d align\n", reg, align); reg 202 drivers/media/platform/mtk-vpu/mtk_vpu.c struct vpu_regs reg; reg 220 drivers/media/platform/mtk-vpu/mtk_vpu.c writel(val, vpu->reg.cfg + offset); reg 225 drivers/media/platform/mtk-vpu/mtk_vpu.c return readl(vpu->reg.cfg + offset); reg 443 drivers/media/platform/mtk-vpu/mtk_vpu.c return (__force void *)(dtcm_dmem_addr + vpu->reg.tcm + reg 512 drivers/media/platform/mtk-vpu/mtk_vpu.c dest = (__force void *)vpu->reg.tcm; reg 725 drivers/media/platform/mtk-vpu/mtk_vpu.c vpu->recv_buf = (__force struct share_obj *)(vpu->reg.tcm + reg 784 drivers/media/platform/mtk-vpu/mtk_vpu.c vpu->reg.tcm = devm_ioremap_resource(dev, res); reg 785 drivers/media/platform/mtk-vpu/mtk_vpu.c if (IS_ERR((__force void *)vpu->reg.tcm)) reg 786 drivers/media/platform/mtk-vpu/mtk_vpu.c return PTR_ERR((__force void *)vpu->reg.tcm); reg 789 drivers/media/platform/mtk-vpu/mtk_vpu.c vpu->reg.cfg = devm_ioremap_resource(dev, res); reg 790 drivers/media/platform/mtk-vpu/mtk_vpu.c if (IS_ERR((__force void *)vpu->reg.cfg)) reg 791 drivers/media/platform/mtk-vpu/mtk_vpu.c return PTR_ERR((__force void *)vpu->reg.cfg); reg 881 drivers/media/platform/mtk-vpu/mtk_vpu.c vpu->reg.irq = platform_get_irq(pdev, 0); reg 882 drivers/media/platform/mtk-vpu/mtk_vpu.c ret = devm_request_irq(dev, vpu->reg.irq, vpu_irq_handler, 0, reg 1062 drivers/media/platform/omap3isp/isp.c for (; next->reg != ISP_TOK_TERM; next++) reg 1063 drivers/media/platform/omap3isp/isp.c next->val = isp_reg_readl(isp, next->mmio_range, next->reg); reg 1077 drivers/media/platform/omap3isp/isp.c for (; next->reg != ISP_TOK_TERM; next++) reg 1078 drivers/media/platform/omap3isp/isp.c isp_reg_writel(isp, next->val, next->mmio_range, next->reg); reg 116 drivers/media/platform/omap3isp/isp.h u32 reg; reg 306 drivers/media/platform/omap3isp/isp.h u32 reg, u32 clr_bits) reg 308 drivers/media/platform/omap3isp/isp.h u32 v = isp_reg_readl(isp, mmio_range, reg); reg 310 drivers/media/platform/omap3isp/isp.h isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg); reg 322 drivers/media/platform/omap3isp/isp.h u32 reg, u32 set_bits) reg 324 drivers/media/platform/omap3isp/isp.h u32 v = isp_reg_readl(isp, mmio_range, reg); reg 326 drivers/media/platform/omap3isp/isp.h isp_reg_writel(isp, v | set_bits, mmio_range, reg); reg 341 drivers/media/platform/omap3isp/isp.h u32 reg, u32 clr_bits, u32 set_bits) reg 343 drivers/media/platform/omap3isp/isp.h u32 v = isp_reg_readl(isp, mmio_range, reg); reg 345 drivers/media/platform/omap3isp/isp.h isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg); reg 210 drivers/media/platform/omap3isp/ispccdc.c int reg; reg 215 drivers/media/platform/omap3isp/ispccdc.c reg = 0; reg 216 drivers/media/platform/omap3isp/ispccdc.c reg |= cfg->gain_mode_n << ISPCCDC_LSC_GAIN_MODE_N_SHIFT; reg 217 drivers/media/platform/omap3isp/ispccdc.c reg |= cfg->gain_mode_m << ISPCCDC_LSC_GAIN_MODE_M_SHIFT; reg 218 drivers/media/platform/omap3isp/ispccdc.c reg |= cfg->gain_format << ISPCCDC_LSC_GAIN_FORMAT_SHIFT; reg 219 drivers/media/platform/omap3isp/ispccdc.c isp_reg_writel(isp, reg, OMAP3_ISP_IOMEM_CCDC, ISPCCDC_LSC_CONFIG); reg 221 drivers/media/platform/omap3isp/ispccdc.c reg = 0; reg 222 drivers/media/platform/omap3isp/ispccdc.c reg &= ~ISPCCDC_LSC_INITIAL_X_MASK; reg 223 drivers/media/platform/omap3isp/ispccdc.c reg |= cfg->initial_x << ISPCCDC_LSC_INITIAL_X_SHIFT; reg 224 drivers/media/platform/omap3isp/ispccdc.c reg &= ~ISPCCDC_LSC_INITIAL_Y_MASK; reg 225 drivers/media/platform/omap3isp/ispccdc.c reg |= cfg->initial_y << ISPCCDC_LSC_INITIAL_Y_SHIFT; reg 226 drivers/media/platform/omap3isp/ispccdc.c isp_reg_writel(isp, reg, OMAP3_ISP_IOMEM_CCDC, reg 47 drivers/media/platform/omap3isp/ispcsi2.c u32 reg; reg 49 drivers/media/platform/omap3isp/ispcsi2.c reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTRL); reg 52 drivers/media/platform/omap3isp/ispcsi2.c reg |= ISPCSI2_CTRL_FRAME; reg 54 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_CTRL_FRAME; reg 57 drivers/media/platform/omap3isp/ispcsi2.c reg |= ISPCSI2_CTRL_VP_CLK_EN; reg 59 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_CTRL_VP_CLK_EN; reg 62 drivers/media/platform/omap3isp/ispcsi2.c reg |= ISPCSI2_CTRL_VP_ONLY_EN; reg 64 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_CTRL_VP_ONLY_EN; reg 66 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_CTRL_VP_OUT_CTRL_MASK; reg 67 drivers/media/platform/omap3isp/ispcsi2.c reg |= currctrl->vp_out_ctrl << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT; reg 70 drivers/media/platform/omap3isp/ispcsi2.c reg |= ISPCSI2_CTRL_ECC_EN; reg 72 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_CTRL_ECC_EN; reg 74 drivers/media/platform/omap3isp/ispcsi2.c isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTRL); reg 252 drivers/media/platform/omap3isp/ispcsi2.c u32 reg; reg 254 drivers/media/platform/omap3isp/ispcsi2.c reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL1(ctxnum)); reg 262 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_CTX_CTRL1_COUNT_MASK; reg 263 drivers/media/platform/omap3isp/ispcsi2.c reg |= ISPCSI2_CTX_CTRL1_COUNT_UNLOCK reg 267 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_CTX_CTRL1_CTX_EN; reg 270 drivers/media/platform/omap3isp/ispcsi2.c isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL1(ctxnum)); reg 283 drivers/media/platform/omap3isp/ispcsi2.c u32 reg; reg 286 drivers/media/platform/omap3isp/ispcsi2.c reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL1(ctx->ctxnum)); reg 289 drivers/media/platform/omap3isp/ispcsi2.c reg |= ISPCSI2_CTX_CTRL1_EOF_EN; reg 291 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_CTX_CTRL1_EOF_EN; reg 294 drivers/media/platform/omap3isp/ispcsi2.c reg |= ISPCSI2_CTX_CTRL1_EOL_EN; reg 296 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_CTX_CTRL1_EOL_EN; reg 299 drivers/media/platform/omap3isp/ispcsi2.c reg |= ISPCSI2_CTX_CTRL1_CS_EN; reg 301 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_CTX_CTRL1_CS_EN; reg 303 drivers/media/platform/omap3isp/ispcsi2.c isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL1(ctx->ctxnum)); reg 306 drivers/media/platform/omap3isp/ispcsi2.c reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL2(ctx->ctxnum)); reg 308 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~(ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK); reg 309 drivers/media/platform/omap3isp/ispcsi2.c reg |= ctx->virtual_id << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT; reg 311 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~(ISPCSI2_CTX_CTRL2_FORMAT_MASK); reg 312 drivers/media/platform/omap3isp/ispcsi2.c reg |= ctx->format_id << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT; reg 316 drivers/media/platform/omap3isp/ispcsi2.c reg |= ISPCSI2_CTX_CTRL2_DPCM_PRED; reg 318 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_CTX_CTRL2_DPCM_PRED; reg 322 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_CTX_CTRL2_USER_DEF_MAP_MASK; reg 323 drivers/media/platform/omap3isp/ispcsi2.c reg |= 2 << ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT; reg 326 drivers/media/platform/omap3isp/ispcsi2.c isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL2(ctx->ctxnum)); reg 329 drivers/media/platform/omap3isp/ispcsi2.c reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL3(ctx->ctxnum)); reg 330 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~(ISPCSI2_CTX_CTRL3_ALPHA_MASK); reg 331 drivers/media/platform/omap3isp/ispcsi2.c reg |= (ctx->alpha << ISPCSI2_CTX_CTRL3_ALPHA_SHIFT); reg 333 drivers/media/platform/omap3isp/ispcsi2.c isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL3(ctx->ctxnum)); reg 336 drivers/media/platform/omap3isp/ispcsi2.c reg = isp_reg_readl(isp, csi2->regs1, reg 338 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_CTX_DAT_OFST_OFST_MASK; reg 339 drivers/media/platform/omap3isp/ispcsi2.c reg |= ctx->data_offset << ISPCSI2_CTX_DAT_OFST_OFST_SHIFT; reg 340 drivers/media/platform/omap3isp/ispcsi2.c isp_reg_writel(isp, reg, csi2->regs1, reg 358 drivers/media/platform/omap3isp/ispcsi2.c u32 reg; reg 360 drivers/media/platform/omap3isp/ispcsi2.c reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_TIMING); reg 363 drivers/media/platform/omap3isp/ispcsi2.c reg |= ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum); reg 365 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum); reg 368 drivers/media/platform/omap3isp/ispcsi2.c reg |= ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum); reg 370 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum); reg 373 drivers/media/platform/omap3isp/ispcsi2.c reg |= ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum); reg 375 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum); reg 377 drivers/media/platform/omap3isp/ispcsi2.c reg &= ~ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(timing->ionum); reg 378 drivers/media/platform/omap3isp/ispcsi2.c reg |= timing->stop_state_counter << reg 381 drivers/media/platform/omap3isp/ispcsi2.c isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_TIMING); reg 412 drivers/media/platform/omap3isp/ispcsi2.c u32 reg; reg 413 drivers/media/platform/omap3isp/ispcsi2.c reg = ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT | reg 440 drivers/media/platform/omap3isp/ispcsi2.c isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_PHY_IRQSTATUS); reg 442 drivers/media/platform/omap3isp/ispcsi2.c reg |= isp_reg_readl(isp, csi2->regs1, ISPCSI2_PHY_IRQENABLE); reg 444 drivers/media/platform/omap3isp/ispcsi2.c reg = 0; reg 445 drivers/media/platform/omap3isp/ispcsi2.c isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_PHY_IRQENABLE); reg 455 drivers/media/platform/omap3isp/ispcsi2.c u32 reg; reg 456 drivers/media/platform/omap3isp/ispcsi2.c reg = ISPCSI2_IRQSTATUS_OCP_ERR_IRQ | reg 464 drivers/media/platform/omap3isp/ispcsi2.c isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_IRQSTATUS); reg 466 drivers/media/platform/omap3isp/ispcsi2.c reg |= isp_reg_readl(isp, csi2->regs1, ISPCSI2_IRQENABLE); reg 468 drivers/media/platform/omap3isp/ispcsi2.c reg = 0; reg 470 drivers/media/platform/omap3isp/ispcsi2.c isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_IRQENABLE); reg 484 drivers/media/platform/omap3isp/ispcsi2.c u32 reg; reg 497 drivers/media/platform/omap3isp/ispcsi2.c reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_SYSSTATUS) & reg 499 drivers/media/platform/omap3isp/ispcsi2.c if (reg == ISPCSI2_SYSSTATUS_RESET_DONE) reg 517 drivers/media/platform/omap3isp/ispcsi2.c reg = isp_reg_readl(isp, csi2->phy->phy_regs, ISPCSIPHY_REG1) reg 519 drivers/media/platform/omap3isp/ispcsi2.c if (reg == ISPCSIPHY_REG1_RESET_DONE_CTRLCLK) reg 27 drivers/media/platform/omap3isp/ispcsiphy.c u32 reg; reg 30 drivers/media/platform/omap3isp/ispcsiphy.c regmap_read(phy->isp->syscon, phy->isp->syscon_offset, ®); reg 36 drivers/media/platform/omap3isp/ispcsiphy.c reg &= ~OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2; reg 44 drivers/media/platform/omap3isp/ispcsiphy.c reg |= OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2; reg 62 drivers/media/platform/omap3isp/ispcsiphy.c reg &= ~(OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_MASK << shift); reg 63 drivers/media/platform/omap3isp/ispcsiphy.c reg |= mode << shift; reg 65 drivers/media/platform/omap3isp/ispcsiphy.c regmap_write(phy->isp->syscon, phy->isp->syscon_offset, reg); reg 130 drivers/media/platform/omap3isp/ispcsiphy.c u32 reg; reg 139 drivers/media/platform/omap3isp/ispcsiphy.c reg = isp_reg_readl(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG) & reg 142 drivers/media/platform/omap3isp/ispcsiphy.c if (reg != power >> 2) reg 145 drivers/media/platform/omap3isp/ispcsiphy.c } while ((reg != power >> 2) && (retry_count < 100)); reg 170 drivers/media/platform/omap3isp/ispcsiphy.c u32 reg; reg 214 drivers/media/platform/omap3isp/ispcsiphy.c reg = isp_reg_readl(phy->isp, phy->phy_regs, ISPCSIPHY_REG0); reg 216 drivers/media/platform/omap3isp/ispcsiphy.c reg &= ~(ISPCSIPHY_REG0_THS_TERM_MASK | reg 219 drivers/media/platform/omap3isp/ispcsiphy.c reg |= (DIV_ROUND_UP(25 * csi2_ddrclk_khz, 2000000) - 1) reg 222 drivers/media/platform/omap3isp/ispcsiphy.c reg |= (DIV_ROUND_UP(90 * csi2_ddrclk_khz, 1000000) + 3) reg 225 drivers/media/platform/omap3isp/ispcsiphy.c isp_reg_writel(phy->isp, reg, phy->phy_regs, ISPCSIPHY_REG0); reg 227 drivers/media/platform/omap3isp/ispcsiphy.c reg = isp_reg_readl(phy->isp, phy->phy_regs, ISPCSIPHY_REG1); reg 229 drivers/media/platform/omap3isp/ispcsiphy.c reg &= ~(ISPCSIPHY_REG1_TCLK_TERM_MASK | reg 232 drivers/media/platform/omap3isp/ispcsiphy.c reg |= TCLK_TERM << ISPCSIPHY_REG1_TCLK_TERM_SHIFT; reg 233 drivers/media/platform/omap3isp/ispcsiphy.c reg |= TCLK_MISS << ISPCSIPHY_REG1_TCLK_MISS_SHIFT; reg 234 drivers/media/platform/omap3isp/ispcsiphy.c reg |= TCLK_SETTLE << ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT; reg 236 drivers/media/platform/omap3isp/ispcsiphy.c isp_reg_writel(phy->isp, reg, phy->phy_regs, ISPCSIPHY_REG1); reg 239 drivers/media/platform/omap3isp/ispcsiphy.c reg = isp_reg_readl(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG); reg 242 drivers/media/platform/omap3isp/ispcsiphy.c reg &= ~(ISPCSI2_PHY_CFG_DATA_POL_MASK(i + 1) | reg 244 drivers/media/platform/omap3isp/ispcsiphy.c reg |= (lanes->data[i].pol << reg 246 drivers/media/platform/omap3isp/ispcsiphy.c reg |= (lanes->data[i].pos << reg 250 drivers/media/platform/omap3isp/ispcsiphy.c reg &= ~(ISPCSI2_PHY_CFG_CLOCK_POL_MASK | reg 252 drivers/media/platform/omap3isp/ispcsiphy.c reg |= lanes->clk.pol << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT; reg 253 drivers/media/platform/omap3isp/ispcsiphy.c reg |= lanes->clk.pos << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT; reg 255 drivers/media/platform/omap3isp/ispcsiphy.c isp_reg_writel(phy->isp, reg, phy->cfg_regs, ISPCSI2_PHY_CFG); reg 1816 drivers/media/platform/pxa_camera.c struct v4l2_dbg_register *reg) reg 1820 drivers/media/platform/pxa_camera.c if (reg->reg > CIBR2) reg 1823 drivers/media/platform/pxa_camera.c reg->val = __raw_readl(pcdev->base + reg->reg); reg 1824 drivers/media/platform/pxa_camera.c reg->size = sizeof(__u32); reg 1829 drivers/media/platform/pxa_camera.c const struct v4l2_dbg_register *reg) reg 1833 drivers/media/platform/pxa_camera.c if (reg->reg > CIBR2) reg 1835 drivers/media/platform/pxa_camera.c if (reg->size != sizeof(__u32)) reg 1837 drivers/media/platform/pxa_camera.c __raw_writel(reg->val, pcdev->base + reg->reg); reg 1109 drivers/media/platform/qcom/camss/camss-csid.c r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[0]); reg 565 drivers/media/platform/qcom/camss/camss-csiphy.c r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[0]); reg 572 drivers/media/platform/qcom/camss/camss-csiphy.c r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[1]); reg 1104 drivers/media/platform/qcom/camss/camss-ispif.c r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[0]); reg 1111 drivers/media/platform/qcom/camss/camss-ispif.c r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[1]); reg 226 drivers/media/platform/qcom/camss/camss-vfe-4-1.c static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) reg 228 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 bits = readl_relaxed(vfe->base + reg); reg 230 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(bits & ~clr_bits, vfe->base + reg); reg 233 drivers/media/platform/qcom/camss/camss-vfe-4-1.c static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits) reg 235 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 bits = readl_relaxed(vfe->base + reg); reg 237 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(bits | set_bits, vfe->base + reg); reg 335 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 reg; reg 344 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = height - 1; reg 345 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg |= ((wpl + 1) / 2 - 1) << 16; reg 347 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + reg 352 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = 0x3; reg 353 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg |= (height - 1) << 4; reg 354 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg |= wpl << 16; reg 356 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + reg 368 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 reg; reg 370 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = readl_relaxed(vfe->base + reg 373 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg &= ~(VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK); reg 375 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg |= (per << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT) reg 378 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, reg 392 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 reg; reg 394 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = (offset << VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT) | reg 396 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); reg 420 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 reg; reg 422 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS); reg 424 drivers/media/platform/qcom/camss/camss-vfe-4-1.c return (reg >> wm) & 0x1; reg 438 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 reg; reg 440 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = VFE_0_RDI_CFG_x_MIPI_EN_BITS; reg 441 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg |= VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(id); reg 442 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), reg); reg 444 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; reg 445 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg |= ((3 * id) << VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT) & reg 447 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), reg); reg 452 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << reg 456 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << reg 460 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << reg 466 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg <<= 16; reg 468 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe_reg_set(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); reg 481 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 reg; reg 483 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(id); reg 484 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(0), reg); reg 486 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; reg 487 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), reg); reg 492 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << reg 496 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << reg 500 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << reg 506 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg <<= 16; reg 508 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe_reg_clr(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); reg 516 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 reg; reg 521 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA << reg 524 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN; reg 526 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA; reg 533 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg <<= 16; reg 538 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg); reg 542 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg); reg 685 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 reg; reg 694 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = (output << 16) | input; reg 695 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); reg 699 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = (interp_reso << 20) | phase_mult; reg 700 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); reg 704 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = (output << 16) | input; reg 705 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); reg 709 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = (interp_reso << 20) | phase_mult; reg 710 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); reg 716 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = (output << 16) | input; reg 717 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); reg 721 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = (interp_reso << 20) | phase_mult; reg 722 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); reg 728 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = (output << 16) | input; reg 729 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); reg 733 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = (interp_reso << 20) | phase_mult; reg 734 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); reg 740 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 reg; reg 745 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = (first << 16) | last; reg 746 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); reg 750 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = (first << 16) | last; reg 751 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); reg 755 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = (first << 16) | last; reg 756 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); reg 764 drivers/media/platform/qcom/camss/camss-vfe-4-1.c reg = (first << 16) | last; reg 765 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); reg 259 drivers/media/platform/qcom/camss/camss-vfe-4-7.c static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) reg 261 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 bits = readl_relaxed(vfe->base + reg); reg 263 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(bits & ~clr_bits, vfe->base + reg); reg 266 drivers/media/platform/qcom/camss/camss-vfe-4-7.c static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits) reg 268 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 bits = readl_relaxed(vfe->base + reg); reg 270 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(bits | set_bits, vfe->base + reg); reg 385 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 reg; reg 394 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = height - 1; reg 395 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg |= ((wpl + 3) / 4 - 1) << 16; reg 397 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + reg 402 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = 0x3; reg 403 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg |= (height - 1) << 2; reg 404 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg |= ((wpl + 1) / 2) << 16; reg 406 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + reg 418 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 reg; reg 420 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = readl_relaxed(vfe->base + reg 423 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg &= ~(VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK); reg 425 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg |= (per << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT) reg 428 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, reg 442 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 reg; reg 444 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = (offset << VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT) | reg 446 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); reg 470 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 reg; reg 472 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS); reg 474 drivers/media/platform/qcom/camss/camss-vfe-4-7.c return (reg >> wm) & 0x1; reg 488 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 reg; reg 490 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = VFE_0_RDI_CFG_x_MIPI_EN_BITS; reg 491 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), reg); reg 493 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; reg 494 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg |= ((3 * id) << VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT) & reg 496 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), reg); reg 501 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << reg 505 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << reg 509 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << reg 515 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg <<= 16; reg 517 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe_reg_set(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); reg 530 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 reg; reg 532 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; reg 533 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), reg); reg 538 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << reg 542 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << reg 546 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << reg 552 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg <<= 16; reg 554 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe_reg_clr(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); reg 562 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 reg; reg 569 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA << reg 573 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg <<= 16; reg 578 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg); reg 582 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg); reg 584 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN; reg 586 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA; reg 589 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg <<= 16; reg 594 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg); reg 598 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg); reg 604 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = VFE_0_BUS_XBAR_CFG_x_M_REALIGN_BUF_EN; reg 605 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN; reg 608 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA; reg 611 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg <<= 16; reg 616 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg); reg 620 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg); reg 788 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 reg; reg 797 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = (output << 16) | input; reg 798 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); reg 802 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = (interp_reso << 28) | phase_mult; reg 803 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); reg 807 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = (output << 16) | input; reg 808 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); reg 812 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = (interp_reso << 28) | phase_mult; reg 813 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); reg 819 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = (output << 16) | input; reg 820 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); reg 824 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = (interp_reso << 28) | phase_mult; reg 825 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); reg 831 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = (output << 16) | input; reg 832 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); reg 836 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = (interp_reso << 28) | phase_mult; reg 837 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); reg 843 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 reg; reg 848 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = (first << 16) | last; reg 849 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); reg 853 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = (first << 16) | last; reg 854 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); reg 858 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = (first << 16) | last; reg 859 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); reg 867 drivers/media/platform/qcom/camss/camss-vfe-4-7.c reg = (first << 16) | last; reg 868 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); reg 2005 drivers/media/platform/qcom/camss/camss-vfe.c r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[0]); reg 42 drivers/media/platform/qcom/camss/camss.c .reg = { "csiphy0", "csiphy0_clk_mux" }, reg 54 drivers/media/platform/qcom/camss/camss.c .reg = { "csiphy1", "csiphy1_clk_mux" }, reg 73 drivers/media/platform/qcom/camss/camss.c .reg = { "csid0" }, reg 90 drivers/media/platform/qcom/camss/camss.c .reg = { "csid1" }, reg 101 drivers/media/platform/qcom/camss/camss.c .reg = { "ispif", "csi_clk_mux" }, reg 123 drivers/media/platform/qcom/camss/camss.c .reg = { "vfe0" }, reg 137 drivers/media/platform/qcom/camss/camss.c .reg = { "csiphy0", "csiphy0_clk_mux" }, reg 149 drivers/media/platform/qcom/camss/camss.c .reg = { "csiphy1", "csiphy1_clk_mux" }, reg 161 drivers/media/platform/qcom/camss/camss.c .reg = { "csiphy2", "csiphy2_clk_mux" }, reg 180 drivers/media/platform/qcom/camss/camss.c .reg = { "csid0" }, reg 197 drivers/media/platform/qcom/camss/camss.c .reg = { "csid1" }, reg 214 drivers/media/platform/qcom/camss/camss.c .reg = { "csid2" }, reg 231 drivers/media/platform/qcom/camss/camss.c .reg = { "csid3" }, reg 244 drivers/media/platform/qcom/camss/camss.c .reg = { "ispif", "csi_clk_mux" }, reg 263 drivers/media/platform/qcom/camss/camss.c .reg = { "vfe0" }, reg 281 drivers/media/platform/qcom/camss/camss.c .reg = { "vfe1" }, reg 48 drivers/media/platform/qcom/camss/camss.h char *reg[CAMSS_RES_MAX]; reg 55 drivers/media/platform/qcom/camss/camss.h char *reg[CAMSS_RES_MAX]; reg 25 drivers/media/platform/qcom/venus/core.h u32 reg; reg 161 drivers/media/platform/qcom/venus/firmware.c u32 reg; reg 166 drivers/media/platform/qcom/venus/firmware.c reg = readl_relaxed(base + WRAPPER_A9SS_SW_RESET); reg 167 drivers/media/platform/qcom/venus/firmware.c reg |= WRAPPER_A9SS_SW_RESET_BIT; reg 168 drivers/media/platform/qcom/venus/firmware.c writel_relaxed(reg, base + WRAPPER_A9SS_SW_RESET); reg 348 drivers/media/platform/qcom/venus/hfi_venus.c static void venus_writel(struct venus_hfi_device *hdev, u32 reg, u32 value) reg 350 drivers/media/platform/qcom/venus/hfi_venus.c writel(value, hdev->core->base + reg); reg 353 drivers/media/platform/qcom/venus/hfi_venus.c static u32 venus_readl(struct venus_hfi_device *hdev, u32 reg) reg 355 drivers/media/platform/qcom/venus/hfi_venus.c return readl(hdev->core->base + reg); reg 366 drivers/media/platform/qcom/venus/hfi_venus.c venus_writel(hdev, tbl[i].reg, tbl[i].value); reg 136 drivers/media/platform/rcar-vin/rcar-csi2.c u16 reg; reg 140 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 80, .reg = 0x86 }, reg 141 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 90, .reg = 0x86 }, reg 142 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 100, .reg = 0x87 }, reg 143 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 110, .reg = 0x87 }, reg 144 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 120, .reg = 0x88 }, reg 145 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 130, .reg = 0x88 }, reg 146 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 140, .reg = 0x89 }, reg 147 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 150, .reg = 0x89 }, reg 148 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 160, .reg = 0x8a }, reg 149 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 170, .reg = 0x8a }, reg 150 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 180, .reg = 0x8b }, reg 151 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 190, .reg = 0x8b }, reg 152 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 205, .reg = 0x8c }, reg 153 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 220, .reg = 0x8d }, reg 154 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 235, .reg = 0x8e }, reg 155 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 250, .reg = 0x8e }, reg 160 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 80, .reg = 0x00 }, reg 161 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 90, .reg = 0x20 }, reg 162 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 100, .reg = 0x40 }, reg 163 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 110, .reg = 0x02 }, reg 164 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 130, .reg = 0x22 }, reg 165 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 140, .reg = 0x42 }, reg 166 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 150, .reg = 0x04 }, reg 167 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 170, .reg = 0x24 }, reg 168 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 180, .reg = 0x44 }, reg 169 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 200, .reg = 0x06 }, reg 170 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 220, .reg = 0x26 }, reg 171 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 240, .reg = 0x46 }, reg 172 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 250, .reg = 0x08 }, reg 173 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 270, .reg = 0x28 }, reg 174 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 300, .reg = 0x0a }, reg 175 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 330, .reg = 0x2a }, reg 176 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 360, .reg = 0x4a }, reg 177 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 400, .reg = 0x0c }, reg 178 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 450, .reg = 0x2c }, reg 179 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 500, .reg = 0x0e }, reg 180 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 550, .reg = 0x2e }, reg 181 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 600, .reg = 0x10 }, reg 182 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 650, .reg = 0x30 }, reg 183 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 700, .reg = 0x12 }, reg 184 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 750, .reg = 0x32 }, reg 185 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 800, .reg = 0x52 }, reg 186 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 850, .reg = 0x72 }, reg 187 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 900, .reg = 0x14 }, reg 188 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 950, .reg = 0x34 }, reg 189 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1000, .reg = 0x54 }, reg 190 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1050, .reg = 0x74 }, reg 191 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1125, .reg = 0x16 }, reg 204 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 80, .reg = 0x00 }, reg 205 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 90, .reg = 0x10 }, reg 206 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 100, .reg = 0x20 }, reg 207 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 110, .reg = 0x30 }, reg 208 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 120, .reg = 0x01 }, reg 209 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 130, .reg = 0x11 }, reg 210 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 140, .reg = 0x21 }, reg 211 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 150, .reg = 0x31 }, reg 212 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 160, .reg = 0x02 }, reg 213 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 170, .reg = 0x12 }, reg 214 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 180, .reg = 0x22 }, reg 215 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 190, .reg = 0x32 }, reg 216 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 205, .reg = 0x03 }, reg 217 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 220, .reg = 0x13 }, reg 218 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 235, .reg = 0x23 }, reg 219 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 250, .reg = 0x33 }, reg 220 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 275, .reg = 0x04 }, reg 221 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 300, .reg = 0x14 }, reg 222 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 325, .reg = 0x25 }, reg 223 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 350, .reg = 0x35 }, reg 224 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 400, .reg = 0x05 }, reg 225 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 450, .reg = 0x16 }, reg 226 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 500, .reg = 0x26 }, reg 227 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 550, .reg = 0x37 }, reg 228 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 600, .reg = 0x07 }, reg 229 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 650, .reg = 0x18 }, reg 230 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 700, .reg = 0x28 }, reg 231 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 750, .reg = 0x39 }, reg 232 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 800, .reg = 0x09 }, reg 233 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 850, .reg = 0x19 }, reg 234 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 900, .reg = 0x29 }, reg 235 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 950, .reg = 0x3a }, reg 236 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1000, .reg = 0x0a }, reg 237 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1050, .reg = 0x1a }, reg 238 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1100, .reg = 0x2a }, reg 239 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1150, .reg = 0x3b }, reg 240 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1200, .reg = 0x0b }, reg 241 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1250, .reg = 0x1b }, reg 242 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1300, .reg = 0x2b }, reg 243 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1350, .reg = 0x3c }, reg 244 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1400, .reg = 0x0c }, reg 245 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1450, .reg = 0x1c }, reg 246 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1500, .reg = 0x2c }, reg 251 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 80, .reg = 0x00 }, reg 252 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 90, .reg = 0x10 }, reg 253 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 100, .reg = 0x20 }, reg 254 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 110, .reg = 0x30 }, reg 255 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 120, .reg = 0x01 }, reg 256 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 130, .reg = 0x11 }, reg 257 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 140, .reg = 0x21 }, reg 258 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 150, .reg = 0x31 }, reg 259 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 160, .reg = 0x02 }, reg 260 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 170, .reg = 0x12 }, reg 261 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 180, .reg = 0x22 }, reg 262 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 190, .reg = 0x32 }, reg 263 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 205, .reg = 0x03 }, reg 264 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 220, .reg = 0x13 }, reg 265 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 235, .reg = 0x23 }, reg 266 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 250, .reg = 0x33 }, reg 267 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 275, .reg = 0x04 }, reg 268 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 300, .reg = 0x14 }, reg 269 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 325, .reg = 0x05 }, reg 270 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 350, .reg = 0x15 }, reg 271 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 400, .reg = 0x25 }, reg 272 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 450, .reg = 0x06 }, reg 273 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 500, .reg = 0x16 }, reg 274 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 550, .reg = 0x07 }, reg 275 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 600, .reg = 0x17 }, reg 276 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 650, .reg = 0x08 }, reg 277 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 700, .reg = 0x18 }, reg 278 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 750, .reg = 0x09 }, reg 279 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 800, .reg = 0x19 }, reg 280 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 850, .reg = 0x29 }, reg 281 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 900, .reg = 0x39 }, reg 282 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 950, .reg = 0x0a }, reg 283 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1000, .reg = 0x1a }, reg 284 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1050, .reg = 0x2a }, reg 285 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1100, .reg = 0x3a }, reg 286 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1150, .reg = 0x0b }, reg 287 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1200, .reg = 0x1b }, reg 288 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1250, .reg = 0x2b }, reg 289 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1300, .reg = 0x3b }, reg 290 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1350, .reg = 0x0c }, reg 291 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1400, .reg = 0x1c }, reg 292 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1450, .reg = 0x2c }, reg 293 drivers/media/platform/rcar-vin/rcar-csi2.c { .mbps = 1500, .reg = 0x3c }, reg 386 drivers/media/platform/rcar-vin/rcar-csi2.c static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg) reg 388 drivers/media/platform/rcar-vin/rcar-csi2.c return ioread32(priv->base + reg); reg 391 drivers/media/platform/rcar-vin/rcar-csi2.c static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data) reg 393 drivers/media/platform/rcar-vin/rcar-csi2.c iowrite32(data, priv->base + reg); reg 444 drivers/media/platform/rcar-vin/rcar-csi2.c rcsi2_write(priv, PHYPLL_REG, PHYPLL_HSFREQRANGE(hsfreq->reg)); reg 919 drivers/media/platform/rcar-vin/rcar-csi2.c return rcsi2_phtw_write(priv, value->reg, code); reg 776 drivers/media/platform/rcar_fdp1.c static u32 fdp1_read(struct fdp1_dev *fdp1, unsigned int reg) reg 778 drivers/media/platform/rcar_fdp1.c u32 value = ioread32(fdp1->regs + reg); reg 781 drivers/media/platform/rcar_fdp1.c dprintk(fdp1, "Read 0x%08x from 0x%04x\n", value, reg); reg 786 drivers/media/platform/rcar_fdp1.c static void fdp1_write(struct fdp1_dev *fdp1, u32 val, unsigned int reg) reg 789 drivers/media/platform/rcar_fdp1.c dprintk(fdp1, "Write 0x%08x to 0x%04x\n", val, reg); reg 791 drivers/media/platform/rcar_fdp1.c iowrite32(val, fdp1->regs + reg); reg 475 drivers/media/platform/rcar_jpu.c static u32 jpu_read(struct jpu *jpu, unsigned int reg) reg 477 drivers/media/platform/rcar_jpu.c return ioread32(jpu->regs + reg); reg 480 drivers/media/platform/rcar_jpu.c static void jpu_write(struct jpu *jpu, u32 val, unsigned int reg) reg 482 drivers/media/platform/rcar_jpu.c iowrite32(val, jpu->regs + reg); reg 495 drivers/media/platform/rcar_jpu.c static void jpu_set_tbl(struct jpu *jpu, u32 reg, const unsigned int *tbl, reg 500 drivers/media/platform/rcar_jpu.c jpu_write(jpu, tbl[i], reg + (i << 2)); reg 126 drivers/media/platform/rockchip/rga/rga-hw.c unsigned int reg; reg 128 drivers/media/platform/rockchip/rga/rga-hw.c reg = RGA_MMU_SRC_BASE - RGA_MODE_BASE_REG; reg 129 drivers/media/platform/rockchip/rga/rga-hw.c dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4; reg 131 drivers/media/platform/rockchip/rga/rga-hw.c reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG; reg 132 drivers/media/platform/rockchip/rga/rga-hw.c dest[reg >> 2] |= 0x7; reg 139 drivers/media/platform/rockchip/rga/rga-hw.c unsigned int reg; reg 141 drivers/media/platform/rockchip/rga/rga-hw.c reg = RGA_MMU_SRC1_BASE - RGA_MODE_BASE_REG; reg 142 drivers/media/platform/rockchip/rga/rga-hw.c dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4; reg 144 drivers/media/platform/rockchip/rga/rga-hw.c reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG; reg 145 drivers/media/platform/rockchip/rga/rga-hw.c dest[reg >> 2] |= 0x7 << 4; reg 152 drivers/media/platform/rockchip/rga/rga-hw.c unsigned int reg; reg 154 drivers/media/platform/rockchip/rga/rga-hw.c reg = RGA_MMU_DST_BASE - RGA_MODE_BASE_REG; reg 155 drivers/media/platform/rockchip/rga/rga-hw.c dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4; reg 157 drivers/media/platform/rockchip/rga/rga-hw.c reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG; reg 158 drivers/media/platform/rockchip/rga/rga-hw.c dest[reg >> 2] |= 0x7 << 8; reg 95 drivers/media/platform/rockchip/rga/rga.h static inline void rga_write(struct rockchip_rga *rga, u32 reg, u32 value) reg 97 drivers/media/platform/rockchip/rga/rga.h writel(value, rga->regs + reg); reg 100 drivers/media/platform/rockchip/rga/rga.h static inline u32 rga_read(struct rockchip_rga *rga, u32 reg) reg 102 drivers/media/platform/rockchip/rga/rga.h return readl(rga->regs + reg); reg 105 drivers/media/platform/rockchip/rga/rga.h static inline void rga_mod(struct rockchip_rga *rga, u32 reg, u32 val, u32 mask) reg 107 drivers/media/platform/rockchip/rga/rga.h u32 temp = rga_read(rga, reg) & ~(mask); reg 110 drivers/media/platform/rockchip/rga/rga.h rga_write(rga, reg, temp); reg 26 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c unsigned int reg; reg 30 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c if (regmap_read(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, ®)) { reg 35 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg = (reg & ~(0x3FF << 16)) | (div_ratio << 16); reg 37 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c if (regmap_write(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, reg)) { reg 44 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(0x0, cec->reg + S5P_CEC_DIVISOR_3); reg 45 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(0x0, cec->reg + S5P_CEC_DIVISOR_2); reg 46 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(0x0, cec->reg + S5P_CEC_DIVISOR_1); reg 47 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(div_val, cec->reg + S5P_CEC_DIVISOR_0); reg 52 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c u8 reg; reg 54 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg = readb(cec->reg + S5P_CEC_RX_CTRL); reg 55 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg |= S5P_CEC_RX_CTRL_ENABLE; reg 56 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(reg, cec->reg + S5P_CEC_RX_CTRL); reg 61 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c u8 reg; reg 63 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg = readb(cec->reg + S5P_CEC_IRQ_MASK); reg 64 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg |= S5P_CEC_IRQ_RX_DONE; reg 65 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg |= S5P_CEC_IRQ_RX_ERROR; reg 66 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(reg, cec->reg + S5P_CEC_IRQ_MASK); reg 71 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c u8 reg; reg 73 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg = readb(cec->reg + S5P_CEC_IRQ_MASK); reg 74 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg &= ~S5P_CEC_IRQ_RX_DONE; reg 75 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg &= ~S5P_CEC_IRQ_RX_ERROR; reg 76 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(reg, cec->reg + S5P_CEC_IRQ_MASK); reg 81 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c u8 reg; reg 83 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg = readb(cec->reg + S5P_CEC_IRQ_MASK); reg 84 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg |= S5P_CEC_IRQ_TX_DONE; reg 85 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg |= S5P_CEC_IRQ_TX_ERROR; reg 86 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(reg, cec->reg + S5P_CEC_IRQ_MASK); reg 91 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c u8 reg; reg 93 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg = readb(cec->reg + S5P_CEC_IRQ_MASK); reg 94 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg &= ~S5P_CEC_IRQ_TX_DONE; reg 95 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg &= ~S5P_CEC_IRQ_TX_ERROR; reg 96 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(reg, cec->reg + S5P_CEC_IRQ_MASK); reg 101 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c u8 reg; reg 103 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(S5P_CEC_RX_CTRL_RESET, cec->reg + S5P_CEC_RX_CTRL); reg 104 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(S5P_CEC_TX_CTRL_RESET, cec->reg + S5P_CEC_TX_CTRL); reg 106 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg = readb(cec->reg + 0xc4); reg 107 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg &= ~0x1; reg 108 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(reg, cec->reg + 0xc4); reg 113 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(S5P_CEC_TX_CTRL_RESET, cec->reg + S5P_CEC_TX_CTRL); reg 118 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c u8 reg; reg 120 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(S5P_CEC_RX_CTRL_RESET, cec->reg + S5P_CEC_RX_CTRL); reg 122 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg = readb(cec->reg + 0xc4); reg 123 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg &= ~0x1; reg 124 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(reg, cec->reg + 0xc4); reg 129 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(CEC_FILTER_THRESHOLD, cec->reg + S5P_CEC_RX_FILTER_TH); reg 130 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(0, cec->reg + S5P_CEC_RX_FILTER_CTRL); reg 137 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c u8 reg; reg 140 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(data[i], cec->reg + (S5P_CEC_TX_BUFF0 + (i * 4))); reg 144 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(count, cec->reg + S5P_CEC_TX_BYTES); reg 145 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg = readb(cec->reg + S5P_CEC_TX_CTRL); reg 146 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg |= S5P_CEC_TX_CTRL_START; reg 147 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg &= ~0x70; reg 148 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg |= retries << 4; reg 152 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg |= S5P_CEC_TX_CTRL_BCAST; reg 155 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c reg &= ~S5P_CEC_TX_CTRL_BCAST; reg 158 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(reg, cec->reg + S5P_CEC_TX_CTRL); reg 165 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c writeb(addr & 0x0F, cec->reg + S5P_CEC_LOGIC_ADDR); reg 172 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c status = readb(cec->reg + S5P_CEC_STATUS_0) & 0xf; reg 173 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c status |= (readb(cec->reg + S5P_CEC_TX_STAT1) & 0xf) << 4; reg 174 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c status |= readb(cec->reg + S5P_CEC_STATUS_1) << 8; reg 175 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c status |= readb(cec->reg + S5P_CEC_STATUS_2) << 16; reg 176 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c status |= readb(cec->reg + S5P_CEC_STATUS_3) << 24; reg 186 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c cec->reg + S5P_CEC_IRQ_CLEAR); reg 192 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c cec->reg + S5P_CEC_IRQ_CLEAR); reg 201 drivers/media/platform/s5p-cec/exynos_hdmi_cecctrl.c buffer[i] = readb(cec->reg + S5P_CEC_RX_BUFF0 + (i * 4)); reg 213 drivers/media/platform/s5p-cec/s5p_cec.c cec->reg = devm_ioremap_resource(dev, res); reg 214 drivers/media/platform/s5p-cec/s5p_cec.c if (IS_ERR(cec->reg)) reg 215 drivers/media/platform/s5p-cec/s5p_cec.c return PTR_ERR(cec->reg); reg 69 drivers/media/platform/s5p-cec/s5p_cec.h void __iomem *reg; reg 20 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c u32 reg = 1; reg 25 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c while (reg != 0 && --count > 0) { reg 28 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = readl(regs + EXYNOS3250_SW_RESET); reg 31 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = 0; reg 34 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c while (reg != 1 && --count > 0) { reg 38 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = readl(regs + EXYNOS3250_JPGDRI); reg 62 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c u32 reg; reg 64 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = readl(base + EXYNOS3250_JPGCMOD) & ~EXYNOS3250_HALF_EN_MASK; reg 66 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD); reg 71 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c u32 reg; reg 73 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = readl(regs + EXYNOS3250_JPGCMOD) & reg 78 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= EXYNOS3250_MODE_SEL_ARGB8888; reg 81 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= EXYNOS3250_MODE_SEL_ARGB8888 | EXYNOS3250_SRC_SWAP_RGB; reg 84 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= EXYNOS3250_MODE_SEL_RGB565; reg 87 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= EXYNOS3250_MODE_SEL_RGB565 | EXYNOS3250_SRC_SWAP_RGB; reg 90 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= EXYNOS3250_MODE_SEL_422_1P_LUM_CHR; reg 93 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= EXYNOS3250_MODE_SEL_422_1P_LUM_CHR | reg 97 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= EXYNOS3250_MODE_SEL_422_1P_CHR_LUM; reg 100 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= EXYNOS3250_MODE_SEL_422_1P_CHR_LUM | reg 104 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= EXYNOS3250_MODE_SEL_420_2P | EXYNOS3250_SRC_NV12; reg 107 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= EXYNOS3250_MODE_SEL_420_2P | EXYNOS3250_SRC_NV21; reg 110 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= EXYNOS3250_MODE_SEL_420_3P; reg 117 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c writel(reg, regs + EXYNOS3250_JPGCMOD); reg 122 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c u32 reg; reg 124 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = readl(regs + EXYNOS3250_JPGCMOD); reg 126 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= EXYNOS3250_MODE_Y16; reg 128 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg &= ~EXYNOS3250_MODE_Y16_MASK; reg 129 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c writel(reg, regs + EXYNOS3250_JPGCMOD); reg 134 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c u32 reg, m; reg 140 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = readl(regs + EXYNOS3250_JPGMOD); reg 141 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg &= ~EXYNOS3250_PROC_MODE_MASK; reg 142 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= m; reg 143 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c writel(reg, regs + EXYNOS3250_JPGMOD); reg 148 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c u32 reg, m = 0; reg 162 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = readl(regs + EXYNOS3250_JPGMOD); reg 163 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg &= ~EXYNOS3250_SUBSAMPLING_MODE_MASK; reg 164 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= m; reg 165 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c writel(reg, regs + EXYNOS3250_JPGMOD); reg 176 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c u32 reg; reg 178 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = dri & EXYNOS3250_JPGDRI_MASK; reg 179 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c writel(reg, regs + EXYNOS3250_JPGDRI); reg 184 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c unsigned long reg; reg 186 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = readl(regs + EXYNOS3250_QHTBL); reg 187 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg &= ~EXYNOS3250_QT_NUM_MASK(t); reg 188 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= (n << EXYNOS3250_QT_NUM_SHIFT(t)) & reg 190 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c writel(reg, regs + EXYNOS3250_QHTBL); reg 195 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c unsigned long reg; reg 197 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = readl(regs + EXYNOS3250_QHTBL); reg 198 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg &= ~EXYNOS3250_HT_NUM_AC_MASK(t); reg 200 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= (0 << EXYNOS3250_HT_NUM_AC_SHIFT(t)) & reg 202 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c writel(reg, regs + EXYNOS3250_QHTBL); reg 207 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c unsigned long reg; reg 209 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = readl(regs + EXYNOS3250_QHTBL); reg 210 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg &= ~EXYNOS3250_HT_NUM_DC_MASK(t); reg 212 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= (0 << EXYNOS3250_HT_NUM_DC_SHIFT(t)) & reg 214 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c writel(reg, regs + EXYNOS3250_QHTBL); reg 219 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c u32 reg; reg 221 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = y & EXYNOS3250_JPGY_MASK; reg 222 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c writel(reg, regs + EXYNOS3250_JPGY); reg 227 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c u32 reg; reg 229 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = x & EXYNOS3250_JPGX_MASK; reg 230 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c writel(reg, regs + EXYNOS3250_JPGX); reg 247 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c u32 reg; reg 249 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = readl(regs + EXYNOS3250_JPGINTSE); reg 250 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= (EXYNOS3250_JPEG_DONE_EN | reg 257 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c writel(reg, regs + EXYNOS3250_JPGINTSE); reg 262 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c u32 reg; reg 264 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = size & EXYNOS3250_ENC_STREAM_BOUND_MASK; reg 265 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c writel(reg, regs + EXYNOS3250_ENC_STREAM_BOUND); reg 270 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c u32 reg; reg 274 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = EXYNOS3250_OUT_FMT_ARGB8888; reg 277 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = EXYNOS3250_OUT_FMT_ARGB8888 | EXYNOS3250_OUT_SWAP_RGB; reg 280 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = EXYNOS3250_OUT_FMT_RGB565; reg 283 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = EXYNOS3250_OUT_FMT_RGB565 | EXYNOS3250_OUT_SWAP_RGB; reg 286 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = EXYNOS3250_OUT_FMT_422_1P_LUM_CHR; reg 289 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = EXYNOS3250_OUT_FMT_422_1P_LUM_CHR | reg 293 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = EXYNOS3250_OUT_FMT_422_1P_CHR_LUM; reg 296 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = EXYNOS3250_OUT_FMT_422_1P_CHR_LUM | reg 300 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = EXYNOS3250_OUT_FMT_420_2P | EXYNOS3250_OUT_NV12; reg 303 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = EXYNOS3250_OUT_FMT_420_2P | EXYNOS3250_OUT_NV21; reg 306 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = EXYNOS3250_OUT_FMT_420_3P; reg 309 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = 0; reg 313 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c writel(reg, regs + EXYNOS3250_OUTFORM); reg 366 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c u32 reg; reg 368 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = (y_offset << EXYNOS3250_LUMA_YY_OFFSET_SHIFT) & reg 370 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= (x_offset << EXYNOS3250_LUMA_YX_OFFSET_SHIFT) & reg 373 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c writel(reg, regs + EXYNOS3250_LUMA_XY_OFFSET); reg 375 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = (y_offset << EXYNOS3250_CHROMA_YY_OFFSET_SHIFT) & reg 377 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= (x_offset << EXYNOS3250_CHROMA_YX_OFFSET_SHIFT) & reg 380 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c writel(reg, regs + EXYNOS3250_CHROMA_XY_OFFSET); reg 382 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg = (y_offset << EXYNOS3250_CHROMA_CR_YY_OFFSET_SHIFT) & reg 384 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c reg |= (x_offset << EXYNOS3250_CHROMA_CR_YX_OFFSET_SHIFT) & reg 387 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos3250.c writel(reg, regs + EXYNOS3250_CHROMA_CR_XY_OFFSET); reg 18 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c unsigned int reg; reg 20 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_JPEG_CNTL_REG); reg 21 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg & ~(EXYNOS4_DEC_MODE | EXYNOS4_ENC_MODE), reg 24 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_JPEG_CNTL_REG); reg 25 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); reg 29 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); reg 34 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c unsigned int reg; reg 36 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_JPEG_CNTL_REG); reg 39 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | reg 43 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | reg 47 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg & EXYNOS4_ENC_DEC_MODE_MASK, reg 55 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c unsigned int reg; reg 67 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_IMG_FMT_REG) & reg 72 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = reg | EXYNOS4_ENC_GRAY_IMG | EXYNOS4_GRAY_IMG_IP; reg 75 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = reg | EXYNOS4_ENC_RGB_IMG | reg 79 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = reg | EXYNOS4_ENC_RGB_IMG | reg 83 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = reg | EXYNOS4_ENC_YUV_444_IMG | reg 88 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = reg | EXYNOS4_ENC_YUV_444_IMG | reg 93 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = reg | EXYNOS4_DEC_YUV_422_IMG | reg 99 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = reg | EXYNOS4_DEC_YUV_422_IMG | reg 104 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = reg | EXYNOS4_DEC_YUV_422_IMG | reg 109 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = reg | EXYNOS4_DEC_YUV_422_IMG | reg 114 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = reg | EXYNOS4_DEC_YUV_420_IMG | reg 119 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = reg | EXYNOS4_DEC_YUV_420_IMG | reg 124 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = reg | EXYNOS4_DEC_YUV_420_IMG | reg 133 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg, base + EXYNOS4_IMG_FMT_REG); reg 139 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c unsigned int reg; reg 141 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_IMG_FMT_REG) & reg 147 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = reg | EXYNOS4_ENC_FMT_GRAY; reg 151 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = reg | EXYNOS4_ENC_FMT_YUV_444; reg 155 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = reg | EXYNOS4_ENC_FMT_YUV_422; reg 159 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = reg | EXYNOS4_ENC_FMT_YUV_420; reg 166 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg, base + EXYNOS4_IMG_FMT_REG); reg 171 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c unsigned int reg; reg 174 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_INT_EN_REG) & ~EXYNOS4_INT_EN_MASK; reg 175 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg | EXYNOS4_INT_EN_ALL, base + EXYNOS4_INT_EN_REG); reg 177 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_INT_EN_REG) & reg 179 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg | EXYNOS5433_INT_EN_ALL, base + EXYNOS4_INT_EN_REG); reg 195 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c unsigned int reg; reg 197 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_JPEG_CNTL_REG) & ~EXYNOS4_HUF_TBL_EN; reg 200 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg | EXYNOS4_HUF_TBL_EN, reg 203 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg & ~EXYNOS4_HUF_TBL_EN, reg 209 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c unsigned int reg; reg 211 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_JPEG_CNTL_REG) & ~(EXYNOS4_SYS_INT_EN); reg 214 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg | EXYNOS4_SYS_INT_EN, base + EXYNOS4_JPEG_CNTL_REG); reg 216 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg & ~EXYNOS4_SYS_INT_EN, base + EXYNOS4_JPEG_CNTL_REG); reg 244 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c unsigned int reg; reg 246 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = EXYNOS4_Q_TBL_COMP1_0 | EXYNOS4_Q_TBL_COMP2_1 | reg 252 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg, base + EXYNOS4_TBL_SEL_REG); reg 257 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c unsigned int reg; reg 259 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_TBL_SEL_REG); reg 261 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg |= EXYNOS4_NF(n); reg 262 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg, base + EXYNOS4_TBL_SEL_REG); reg 267 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c unsigned int reg; reg 269 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_TBL_SEL_REG); reg 271 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg |= EXYNOS4_Q_TBL_COMP(c, x); reg 272 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg, base + EXYNOS4_TBL_SEL_REG); reg 277 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c unsigned int reg; reg 279 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg = readl(base + EXYNOS4_TBL_SEL_REG); reg 281 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c reg |= EXYNOS4_HUFF_TBL_COMP(c, x); reg 282 drivers/media/platform/s5p-jpeg/jpeg-hw-exynos4.c writel(reg, base + EXYNOS4_TBL_SEL_REG); reg 19 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c unsigned long reg; reg 22 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPG_SW_RESET); reg 24 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c while (reg != 0) { reg 26 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPG_SW_RESET); reg 37 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c unsigned long reg, m; reg 45 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPGCMOD); reg 46 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~S5P_MOD_SEL_MASK; reg 47 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= m; reg 48 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPGCMOD); reg 53 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c unsigned long reg, m; reg 60 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPGMOD); reg 61 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~S5P_PROC_MODE_MASK; reg 62 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= m; reg 63 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPGMOD); reg 68 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c unsigned long reg, m; reg 75 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPGMOD); reg 76 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~S5P_SUBSAMPLING_MODE_MASK; reg 77 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= m; reg 78 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPGMOD); reg 88 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c unsigned long reg; reg 90 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPGDRI_U); reg 91 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~0xff; reg 92 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= (dri >> 8) & 0xff; reg 93 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPGDRI_U); reg 95 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPGDRI_L); reg 96 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~0xff; reg 97 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= dri & 0xff; reg 98 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPGDRI_L); reg 103 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c unsigned long reg; reg 105 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPG_QTBL); reg 106 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~S5P_QT_NUMt_MASK(t); reg 107 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= (n << S5P_QT_NUMt_SHIFT(t)) & S5P_QT_NUMt_MASK(t); reg 108 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPG_QTBL); reg 113 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c unsigned long reg; reg 115 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPG_HTBL); reg 116 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~S5P_HT_NUMt_AC_MASK(t); reg 118 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= (0 << S5P_HT_NUMt_AC_SHIFT(t)) & S5P_HT_NUMt_AC_MASK(t); reg 119 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPG_HTBL); reg 124 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c unsigned long reg; reg 126 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPG_HTBL); reg 127 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~S5P_HT_NUMt_DC_MASK(t); reg 129 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= (0 << S5P_HT_NUMt_DC_SHIFT(t)) & S5P_HT_NUMt_DC_MASK(t); reg 130 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPG_HTBL); reg 135 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c unsigned long reg; reg 137 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPGY_U); reg 138 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~0xff; reg 139 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= (y >> 8) & 0xff; reg 140 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPGY_U); reg 142 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPGY_L); reg 143 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~0xff; reg 144 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= y & 0xff; reg 145 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPGY_L); reg 150 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c unsigned long reg; reg 152 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPGX_U); reg 153 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~0xff; reg 154 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= (x >> 8) & 0xff; reg 155 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPGX_U); reg 157 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPGX_L); reg 158 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~0xff; reg 159 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= x & 0xff; reg 160 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPGX_L); reg 165 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c unsigned long reg; reg 167 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPGINTSE); reg 168 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~S5P_RSTm_INT_EN_MASK; reg 170 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= S5P_RSTm_INT_EN; reg 171 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPGINTSE); reg 176 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c unsigned long reg; reg 178 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPGINTSE); reg 179 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~S5P_DATA_NUM_INT_EN_MASK; reg 181 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= S5P_DATA_NUM_INT_EN; reg 182 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPGINTSE); reg 187 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c unsigned long reg; reg 189 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPGINTSE); reg 190 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~S5P_FINAL_MCU_NUM_INT_EN_MASK; reg 192 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= S5P_FINAL_MCU_NUM_INT_EN; reg 193 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPGINTSE); reg 204 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c unsigned long reg; reg 206 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPG_TIMER_SE); reg 207 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~S5P_TIMER_INT_STAT_MASK; reg 208 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPG_TIMER_SE); reg 213 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c unsigned long reg; reg 215 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPG_ENC_STREAM_INTSE); reg 216 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~S5P_ENC_STREAM_BOUND_MASK; reg 217 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= S5P_ENC_STREAM_INT_EN; reg 218 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= size & S5P_ENC_STREAM_BOUND_MASK; reg 219 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPG_ENC_STREAM_INTSE); reg 230 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c unsigned long reg; reg 232 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPG_ENC_STREAM_INTSE); reg 233 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~S5P_ENC_STREAM_INT_MASK; reg 234 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPG_ENC_STREAM_INTSE); reg 239 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c unsigned long reg, f; reg 246 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPG_OUTFORM); reg 247 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~S5P_DEC_OUT_FORMAT_MASK; reg 248 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= f; reg 249 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPG_OUTFORM); reg 265 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c unsigned long reg; reg 267 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg = readl(regs + S5P_JPG_COEF(i)); reg 268 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg &= ~S5P_COEFn_MASK(j); reg 269 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c reg |= (coef << S5P_COEFn_SHIFT(j)) & S5P_COEFn_MASK(j); reg 270 drivers/media/platform/s5p-jpeg/jpeg-hw-s5p.c writel(reg, regs + S5P_JPG_COEF(i)); reg 678 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c unsigned int reg; reg 686 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL); reg 687 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (1 << 18); reg 688 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0xFFFF); reg 689 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= p->gop_size; reg 690 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL); reg 711 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = mfc_read(dev, S5P_FIMV_ENC_PADDING_CTRL); reg 714 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (1UL << 31); reg 716 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0xFF << 16); reg 717 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (p->pad_cr << 16); reg 719 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0xFF << 8); reg 720 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (p->pad_cb << 8); reg 722 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0xFF); reg 723 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (p->pad_luma); reg 726 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = 0; reg 728 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, reg, S5P_FIMV_ENC_PADDING_CTRL); reg 730 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); reg 732 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x1 << 9); reg 733 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (p->rc_frame << 9); reg 734 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); reg 762 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c unsigned int reg; reg 767 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL); reg 769 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x3 << 16); reg 770 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (p->num_b_frame << 16); reg 771 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL); reg 773 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = mfc_read(dev, S5P_FIMV_ENC_PROFILE); reg 775 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0xFF << 8); reg 776 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (p_264->level << 8); reg 778 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x3F); reg 779 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= p_264->profile; reg 780 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE); reg 790 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = 0x10; reg 791 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (0xFF - p_264->loop_filter_alpha) + 1; reg 793 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = 0x00; reg 794 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (p_264->loop_filter_alpha & 0xF); reg 796 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, reg, S5P_FIMV_ENC_ALPHA_OFF); reg 799 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = 0x10; reg 800 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (0xFF - p_264->loop_filter_beta) + 1; reg 802 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = 0x00; reg 803 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (p_264->loop_filter_beta & 0xF); reg 805 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, reg, S5P_FIMV_ENC_BETA_OFF); reg 812 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = mfc_read(dev, S5P_FIMV_ENC_H264_NUM_OF_REF); reg 814 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x3 << 5); reg 815 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (p_264->num_ref_pic_4p << 5); reg 817 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x1F); reg 818 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= p_264->max_ref_pic; reg 819 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, reg, S5P_FIMV_ENC_H264_NUM_OF_REF); reg 823 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); reg 825 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x1 << 8); reg 826 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (p->rc_mb << 8); reg 828 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x3F); reg 829 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= p_264->rc_frame_qp; reg 830 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); reg 838 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND); reg 840 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x3F << 8); reg 841 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (p_264->rc_max_qp << 8); reg 843 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x3F); reg 844 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= p_264->rc_min_qp; reg 845 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); reg 848 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = mfc_read(dev, S5P_FIMV_ENC_RC_MB_CTRL); reg 850 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x1 << 3); reg 851 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (p_264->rc_mb_dark << 3); reg 853 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x1 << 2); reg 854 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (p_264->rc_mb_smooth << 2); reg 856 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x1 << 1); reg 857 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (p_264->rc_mb_static << 1); reg 859 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x1); reg 860 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= p_264->rc_mb_activity; reg 861 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, reg, S5P_FIMV_ENC_RC_MB_CTRL); reg 919 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c unsigned int reg; reg 925 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL); reg 927 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x3 << 16); reg 928 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (p->num_b_frame << 16); reg 929 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL); reg 931 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = mfc_read(dev, S5P_FIMV_ENC_PROFILE); reg 933 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0xFF << 8); reg 934 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (p_mpeg4->level << 8); reg 936 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x3F); reg 937 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= p_mpeg4->profile; reg 938 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE); reg 967 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); reg 969 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x3F); reg 970 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= p_mpeg4->rc_frame_qp; reg 971 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); reg 973 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND); reg 975 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x3F << 8); reg 976 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (p_mpeg4->rc_max_qp << 8); reg 978 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x3F); reg 979 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= p_mpeg4->rc_min_qp; reg 980 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); reg 998 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c unsigned int reg; reg 1016 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); reg 1018 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x3F); reg 1019 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= p_h263->rc_frame_qp; reg 1020 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); reg 1022 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND); reg 1024 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x3F << 8); reg 1025 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= (p_h263->rc_max_qp << 8); reg 1027 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg &= ~(0x3F); reg 1028 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c reg |= p_h263->rc_min_qp; reg 1029 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v5.c mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); reg 754 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c unsigned int reg = 0; reg 771 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 772 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p->gop_size & 0xFFFF; reg 773 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_gop_config); reg 778 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 780 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (0x1 << 3); reg 781 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_enc_options); reg 784 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (0x1 << 3); reg 785 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_enc_options); reg 788 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 3); reg 789 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_enc_options); reg 796 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_enc_options); reg 798 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 4); reg 800 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (0x1 << 4); reg 801 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_enc_options); reg 804 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_enc_options); reg 805 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 9); reg 806 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_enc_options); reg 811 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_enc_options); reg 812 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 7); reg 813 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_enc_options); reg 818 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_enc_options); reg 819 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 7); reg 820 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_enc_options); reg 825 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_enc_options); reg 826 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (0x1 << 7); reg 827 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_enc_options); reg 834 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_enc_options); reg 835 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (0x1 << 8); reg 836 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_enc_options); reg 841 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 843 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (1UL << 31); reg 845 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p->pad_cr & 0xFF) << 16); reg 847 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p->pad_cb & 0xFF) << 8); reg 849 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p->pad_luma & 0xFF; reg 850 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_padding_ctrl); reg 854 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 856 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p->rc_frame & 0x1) << 9); reg 857 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_config); reg 875 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_enc_options); reg 876 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 2); reg 877 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p->seq_hdr_mode & 0x1) << 2); reg 880 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x3); reg 881 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p->frame_skip_mode & 0x3); reg 882 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_enc_options); reg 885 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_rc_config); reg 886 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 10); reg 887 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_config); reg 890 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = (p->mv_h_range & S5P_FIMV_E_MV_RANGE_V6_MASK); reg 891 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_mv_hor_range); reg 893 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = (p->mv_v_range & S5P_FIMV_E_MV_RANGE_V6_MASK); reg 894 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_mv_ver_range); reg 920 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c unsigned int reg = 0; reg 928 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_gop_config); reg 929 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x3 << 16); reg 930 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p->num_b_frame & 0x3) << 16); reg 931 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_gop_config); reg 934 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 936 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h264->level & 0xFF) << 8); reg 938 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_h264->profile & 0x3F; reg 939 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_picture_profile); reg 942 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_rc_config); reg 944 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 8); reg 945 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p->rc_mb & 0x1) << 8); reg 946 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_config); reg 949 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x3F); reg 950 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_h264->rc_frame_qp & 0x3F; reg 951 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_config); reg 954 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 956 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h264->rc_max_qp & 0x3F) << 8); reg 958 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_h264->rc_min_qp & 0x3F; reg 959 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_qp_bound); reg 964 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 965 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16); reg 966 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8); reg 967 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_h264->rc_frame_qp & 0x3F; reg 968 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_fixed_picture_qp); reg 973 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 974 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p->rc_framerate_num & 0xFFFF) << 16); reg 975 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p->rc_framerate_denom & 0xFFFF; reg 976 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_frame_rate); reg 990 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 991 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h264->interlace & 0x1) << 3); reg 992 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_h264_options); reg 1004 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_h264_options); reg 1005 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x3 << 1); reg 1006 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h264->loop_filter_mode & 0x3) << 1); reg 1007 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_h264_options); reg 1011 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0x10; reg 1012 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (0xFF - p_h264->loop_filter_alpha) + 1; reg 1014 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0x00; reg 1015 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_h264->loop_filter_alpha & 0xF); reg 1017 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_h264_lf_alpha_offset); reg 1021 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0x10; reg 1022 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (0xFF - p_h264->loop_filter_beta) + 1; reg 1024 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0x00; reg 1025 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_h264->loop_filter_beta & 0xF); reg 1027 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_h264_lf_beta_offset); reg 1030 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_h264_options); reg 1031 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1); reg 1032 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_h264->entropy_mode & 0x1; reg 1033 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_h264_options); reg 1036 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_h264_options); reg 1037 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 7); reg 1038 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7); reg 1039 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_h264_options); reg 1042 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_h264_options); reg 1043 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x3 << 12); reg 1044 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h264->_8x8_transform & 0x3) << 12); reg 1045 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_h264_options); reg 1050 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1052 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h264->rc_mb_dark & 0x1) << 3); reg 1054 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h264->rc_mb_smooth & 0x1) << 2); reg 1056 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h264->rc_mb_static & 0x1) << 1); reg 1058 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_h264->rc_mb_activity & 0x1; reg 1059 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_mb_rc_config); reg 1064 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 5); reg 1065 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h264->vui_sar & 0x1) << 5); reg 1066 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_h264_options); reg 1072 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1073 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_h264->vui_sar_idc & 0xFF; reg 1074 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_aspect_ratio); reg 1077 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1078 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16; reg 1079 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_h264->vui_ext_sar_height & 0xFFFF; reg 1080 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_extended_sar); reg 1087 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 4); reg 1088 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h264->open_gop & 0x1) << 4); reg 1089 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_h264_options); reg 1094 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1095 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_h264->open_gop_size & 0xFFFF; reg 1096 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_h264_i_period); reg 1101 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x3 << 9); reg 1102 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_h264_options); reg 1106 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 14); reg 1107 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_h264_options); reg 1111 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 6); reg 1112 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h264->aso & 0x1) << 6); reg 1113 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_h264_options); reg 1117 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 8); reg 1118 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h264->open_gop & 0x1) << 8); reg 1119 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_h264_options); reg 1120 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1122 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_h264->hier_qp_type & 0x1) << 0x3; reg 1123 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_h264->hier_qp_layer & 0x7; reg 1124 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_h264_num_t_layer); reg 1134 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_h264_num_t_layer); reg 1138 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 25); reg 1139 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h264->sei_frame_packing & 0x1) << 25); reg 1140 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_h264_options); reg 1142 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1144 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2); reg 1146 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_h264->sei_fp_arrangement_type & 0x3; reg 1147 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_h264_frame_packing_sei_info); reg 1201 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c unsigned int reg = 0; reg 1208 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_gop_config); reg 1209 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x3 << 16); reg 1210 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p->num_b_frame & 0x3) << 16); reg 1211 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_gop_config); reg 1214 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1216 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_mpeg4->level & 0xFF) << 8); reg 1218 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_mpeg4->profile & 0x3F; reg 1219 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_picture_profile); reg 1222 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_rc_config); reg 1224 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 8); reg 1225 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p->rc_mb & 0x1) << 8); reg 1226 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_config); reg 1229 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x3F); reg 1230 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_mpeg4->rc_frame_qp & 0x3F; reg 1231 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_config); reg 1234 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1236 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8); reg 1238 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_mpeg4->rc_min_qp & 0x3F; reg 1239 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_qp_bound); reg 1244 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1245 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16); reg 1246 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8); reg 1247 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_mpeg4->rc_frame_qp & 0x3F; reg 1248 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_fixed_picture_qp); reg 1253 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1254 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p->rc_framerate_num & 0xFFFF) << 16); reg 1255 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p->rc_framerate_denom & 0xFFFF; reg 1256 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_frame_rate); reg 1283 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c unsigned int reg = 0; reg 1290 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1292 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (0x1 << 4); reg 1293 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_picture_profile); reg 1296 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_rc_config); reg 1298 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 8); reg 1299 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p->rc_mb & 0x1) << 8); reg 1300 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_config); reg 1303 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x3F); reg 1304 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_h263->rc_frame_qp & 0x3F; reg 1305 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_config); reg 1308 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1310 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h263->rc_max_qp & 0x3F) << 8); reg 1312 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_h263->rc_min_qp & 0x3F; reg 1313 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_qp_bound); reg 1318 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1319 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16); reg 1320 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8); reg 1321 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_h263->rc_frame_qp & 0x3F; reg 1322 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_fixed_picture_qp); reg 1327 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1328 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p->rc_framerate_num & 0xFFFF) << 16); reg 1329 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p->rc_framerate_denom & 0xFFFF; reg 1330 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_frame_rate); reg 1353 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c unsigned int reg = 0; reg 1361 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_gop_config); reg 1362 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x3 << 16); reg 1363 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p->num_b_frame & 0x3) << 16); reg 1364 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_gop_config); reg 1367 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = p_vp8->profile & 0x3; reg 1368 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_picture_profile); reg 1371 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_rc_config); reg 1373 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 8); reg 1374 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p->rc_mb & 0x1) << 8); reg 1375 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_config); reg 1379 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1380 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p->rc_framerate_num & 0xFFFF) << 16); reg 1381 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p->rc_framerate_denom & 0xFFFF; reg 1382 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_frame_rate); reg 1386 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x7F); reg 1387 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_vp8->rc_frame_qp & 0x7F; reg 1388 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_config); reg 1393 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1394 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_vp8->rc_p_frame_qp & 0x7F) << 8); reg 1395 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_vp8->rc_frame_qp & 0x7F; reg 1396 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_fixed_picture_qp); reg 1400 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = ((p_vp8->rc_max_qp & 0x7F) << 8); reg 1402 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_vp8->rc_min_qp & 0x7F; reg 1403 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_qp_bound); reg 1415 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1416 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_vp8->imd_4x4 & 0x1) << 10; reg 1431 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (val & 0xF) << 3; reg 1432 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_vp8->num_ref & 0x2); reg 1433 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_vp8_options); reg 1446 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c unsigned int reg = 0; reg 1454 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_gop_config); reg 1456 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x3 << 16); reg 1457 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p->num_b_frame << 16); reg 1458 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_gop_config); reg 1468 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1470 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_hevc->profile & 0x3; reg 1472 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0xFF << 8); reg 1473 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->level << 8); reg 1475 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->tier << 16); reg 1476 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_picture_profile); reg 1493 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1494 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->max_partition_depth & 0x1); reg 1495 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->num_refs_for_p-1) << 2; reg 1496 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->refreshtype & 0x3) << 3; reg 1497 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->const_intra_period_enable & 0x1) << 5; reg 1498 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->lossless_cu_enable & 0x1) << 6; reg 1499 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->wavefront_enable & 0x1) << 7; reg 1500 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->loopfilter_disable & 0x1) << 8; reg 1501 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->loopfilter_across & 0x1) << 9; reg 1502 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->enable_ltr & 0x1) << 10; reg 1503 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->hier_qp_enable & 0x1) << 11; reg 1504 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->general_pb_enable & 0x1) << 13; reg 1505 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->temporal_id_enable & 0x1) << 14; reg 1506 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->strong_intra_smooth & 0x1) << 15; reg 1507 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->intra_pu_split_disable & 0x1) << 16; reg 1508 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->tmv_prediction_disable & 0x1) << 17; reg 1509 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->max_num_merge_mv & 0x7) << 18; reg 1510 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->encoding_nostartcode_enable & 0x1) << 23; reg 1511 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->prepend_sps_pps_to_idr << 26); reg 1513 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_hevc_options); reg 1516 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1517 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->refreshperiod & 0xFFFF); reg 1518 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_hevc_refresh_period); reg 1522 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1523 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->lf_beta_offset_div2); reg 1524 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_hevc_lf_beta_offset_div2); reg 1525 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1526 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->lf_tc_offset_div2); reg 1527 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_hevc_lf_tc_offset_div2); reg 1531 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1532 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->hier_qp_type & 0x1) << 0x3; reg 1533 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_hevc->num_hier_layer & 0x7; reg 1534 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_num_t_layer); reg 1550 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = readl(mfc_regs->e_rc_config); reg 1552 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0x1 << 8); reg 1553 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p->rc_mb << 8); reg 1554 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_config); reg 1556 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0xFF); reg 1557 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_hevc->rc_frame_qp; reg 1558 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_config); reg 1562 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1563 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0xFFFF << 16); reg 1564 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= ((p_hevc->rc_framerate) << 16); reg 1565 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0xFFFF); reg 1566 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= FRAME_DELTA_DEFAULT; reg 1567 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_frame_rate); reg 1571 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1573 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0xFF << 8); reg 1574 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->rc_max_qp << 8); reg 1576 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0xFF); reg 1577 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_hevc->rc_min_qp; reg 1578 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_rc_qp_bound); reg 1582 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1583 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0xFF << 16); reg 1584 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->rc_b_frame_qp << 16); reg 1585 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0xFF << 8); reg 1586 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (p_hevc->rc_p_frame_qp << 8); reg 1587 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg &= ~(0xFF); reg 1588 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= p_hevc->rc_frame_qp; reg 1589 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->e_fixed_picture_qp); reg 1601 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c unsigned int reg = 0; reg 1613 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6); reg 1616 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6); reg 1621 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->d_dec_options); reg 1622 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg = 0; reg 1629 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (ctx->loop_filter_mpeg4 << reg 1633 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6); reg 1636 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->d_init_buffer_options); reg 1638 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c writel(reg, mfc_regs->d_dec_options); reg 2233 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c #define S5P_MFC_REG_ADDR(dev, reg) ((dev)->regs_base + (reg)) reg 220 drivers/media/platform/sh_veu.c static u32 sh_veu_reg_read(struct sh_veu_dev *veu, unsigned int reg) reg 222 drivers/media/platform/sh_veu.c return ioread32(veu->base + reg); reg 225 drivers/media/platform/sh_veu.c static void sh_veu_reg_write(struct sh_veu_dev *veu, unsigned int reg, reg 228 drivers/media/platform/sh_veu.c iowrite32(value, veu->base + reg); reg 93 drivers/media/platform/sh_vou.c static void sh_vou_reg_a_write(struct sh_vou_device *vou_dev, unsigned int reg, reg 96 drivers/media/platform/sh_vou.c __raw_writel(value, vou_dev->base + reg); reg 99 drivers/media/platform/sh_vou.c static void sh_vou_reg_ab_write(struct sh_vou_device *vou_dev, unsigned int reg, reg 102 drivers/media/platform/sh_vou.c __raw_writel(value, vou_dev->base + reg); reg 103 drivers/media/platform/sh_vou.c __raw_writel(value, vou_dev->base + reg + 0x1000); reg 106 drivers/media/platform/sh_vou.c static void sh_vou_reg_m_write(struct sh_vou_device *vou_dev, unsigned int reg, reg 109 drivers/media/platform/sh_vou.c __raw_writel(value, vou_dev->base + reg + 0x2000); reg 112 drivers/media/platform/sh_vou.c static u32 sh_vou_reg_a_read(struct sh_vou_device *vou_dev, unsigned int reg) reg 114 drivers/media/platform/sh_vou.c return __raw_readl(vou_dev->base + reg); reg 117 drivers/media/platform/sh_vou.c static void sh_vou_reg_a_set(struct sh_vou_device *vou_dev, unsigned int reg, reg 120 drivers/media/platform/sh_vou.c u32 old = __raw_readl(vou_dev->base + reg); reg 123 drivers/media/platform/sh_vou.c __raw_writel(value, vou_dev->base + reg); reg 126 drivers/media/platform/sh_vou.c static void sh_vou_reg_b_set(struct sh_vou_device *vou_dev, unsigned int reg, reg 129 drivers/media/platform/sh_vou.c sh_vou_reg_a_set(vou_dev, reg + 0x1000, value, mask); reg 132 drivers/media/platform/sh_vou.c static void sh_vou_reg_ab_set(struct sh_vou_device *vou_dev, unsigned int reg, reg 135 drivers/media/platform/sh_vou.c sh_vou_reg_a_set(vou_dev, reg, value, mask); reg 136 drivers/media/platform/sh_vou.c sh_vou_reg_b_set(vou_dev, reg, value, mask); reg 475 drivers/media/platform/sti/bdisp/bdisp-debug.c #define DUMP(reg) seq_printf(s, #reg " \t0x%08X\n", readl(bdisp->regs + reg)) reg 191 drivers/media/platform/sti/cec/stih-cec.c u32 reg = readl(cec->regs + CEC_ADDR_TABLE); reg 193 drivers/media/platform/sti/cec/stih-cec.c reg |= 1 << logical_addr; reg 196 drivers/media/platform/sti/cec/stih-cec.c reg = 0; reg 198 drivers/media/platform/sti/cec/stih-cec.c writel(reg, cec->regs + CEC_ADDR_TABLE); reg 462 drivers/media/platform/sti/hva/hva-hw.c u32 reg = 0; reg 477 drivers/media/platform/sti/hva/hva-hw.c reg = readl_relaxed(hva->regs + HVA_HIF_REG_CLK_GATING); reg 480 drivers/media/platform/sti/hva/hva-hw.c reg |= CLK_GATING_HVC; reg 488 drivers/media/platform/sti/hva/hva-hw.c writel_relaxed(reg, hva->regs + HVA_HIF_REG_CLK_GATING); reg 531 drivers/media/platform/sti/hva/hva-hw.c reg &= ~CLK_GATING_HVC; reg 532 drivers/media/platform/sti/hva/hva-hw.c writel_relaxed(reg, hva->regs + HVA_HIF_REG_CLK_GATING); reg 545 drivers/media/platform/sti/hva/hva-hw.c #define DUMP(reg) seq_printf(s, "%-30s: 0x%08X\n",\ reg 546 drivers/media/platform/sti/hva/hva-hw.c #reg, readl_relaxed(hva->regs + reg)) reg 183 drivers/media/platform/stm32/stm32-dcmi.c static inline u32 reg_read(void __iomem *base, u32 reg) reg 185 drivers/media/platform/stm32/stm32-dcmi.c return readl_relaxed(base + reg); reg 188 drivers/media/platform/stm32/stm32-dcmi.c static inline void reg_write(void __iomem *base, u32 reg, u32 val) reg 190 drivers/media/platform/stm32/stm32-dcmi.c writel_relaxed(val, base + reg); reg 193 drivers/media/platform/stm32/stm32-dcmi.c static inline void reg_set(void __iomem *base, u32 reg, u32 mask) reg 195 drivers/media/platform/stm32/stm32-dcmi.c reg_write(base, reg, reg_read(base, reg) | mask); reg 198 drivers/media/platform/stm32/stm32-dcmi.c static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) reg 200 drivers/media/platform/stm32/stm32-dcmi.c reg_write(base, reg, reg_read(base, reg) & ~mask); reg 180 drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c u32 reg = readl(csi->regs + CSI_BUF_CTRL_REG); reg 184 drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c next = !(reg & CSI_BUF_CTRL_DBS); reg 381 drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c u32 reg; reg 383 drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c reg = readl(csi->regs + CSI_INT_STA_REG); reg 386 drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c writel(reg, csi->regs + CSI_INT_STA_REG); reg 388 drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c if (!(reg & CSI_INT_FRM_DONE)) reg 52 drivers/media/platform/tegra-cec/tegra_cec.c static inline u32 cec_read(struct tegra_cec *cec, u32 reg) reg 54 drivers/media/platform/tegra-cec/tegra_cec.c return readl(cec->cec_base + reg); reg 57 drivers/media/platform/tegra-cec/tegra_cec.c static inline void cec_write(struct tegra_cec *cec, u32 reg, u32 val) reg 59 drivers/media/platform/tegra-cec/tegra_cec.c writel(val, cec->cec_base + reg); reg 268 drivers/media/platform/tegra-cec/tegra_cec.c u32 reg = cec_read(cec, TEGRA_CEC_HW_CONTROL); reg 271 drivers/media/platform/tegra-cec/tegra_cec.c reg |= TEGRA_CEC_HWCTRL_RX_SNOOP; reg 273 drivers/media/platform/tegra-cec/tegra_cec.c reg &= ~TEGRA_CEC_HWCTRL_RX_SNOOP; reg 274 drivers/media/platform/tegra-cec/tegra_cec.c cec_write(cec, TEGRA_CEC_HW_CONTROL, reg); reg 507 drivers/media/platform/ti-vpe/vpe.c #define GET_OFFSET_TOP(ctx, obj, reg) \ reg 508 drivers/media/platform/ti-vpe/vpe.c ((obj)->res->start - ctx->dev->res->start + reg) reg 283 drivers/media/platform/via-camera.c int reg, int value) reg 285 drivers/media/platform/via-camera.c iowrite32(value, cam->mmio + reg); reg 288 drivers/media/platform/via-camera.c static inline int viacam_read_reg(struct via_camera *cam, int reg) reg 290 drivers/media/platform/via-camera.c return ioread32(cam->mmio + reg); reg 294 drivers/media/platform/via-camera.c int reg, int value, int mask) reg 296 drivers/media/platform/via-camera.c int tmp = viacam_read_reg(cam, reg); reg 299 drivers/media/platform/via-camera.c viacam_write_reg(cam, reg, tmp); reg 113 drivers/media/platform/vsp1/vsp1.h static inline u32 vsp1_read(struct vsp1_device *vsp1, u32 reg) reg 115 drivers/media/platform/vsp1/vsp1.h return ioread32(vsp1->mmio + reg); reg 118 drivers/media/platform/vsp1/vsp1.h static inline void vsp1_write(struct vsp1_device *vsp1, u32 reg, u32 data) reg 120 drivers/media/platform/vsp1/vsp1.h iowrite32(data, vsp1->mmio + reg); reg 30 drivers/media/platform/vsp1/vsp1_brx.c struct vsp1_dl_body *dlb, u32 reg, u32 data) reg 32 drivers/media/platform/vsp1/vsp1_brx.c vsp1_dl_body_write(dlb, brx->base + reg, data); reg 29 drivers/media/platform/vsp1/vsp1_clu.c struct vsp1_dl_body *dlb, u32 reg, u32 data) reg 31 drivers/media/platform/vsp1/vsp1_clu.c vsp1_dl_body_write(dlb, reg, data); reg 380 drivers/media/platform/vsp1/vsp1_dl.c void vsp1_dl_body_write(struct vsp1_dl_body *dlb, u32 reg, u32 data) reg 386 drivers/media/platform/vsp1/vsp1_dl.c dlb->entries[dlb->num_entries].addr = reg; reg 75 drivers/media/platform/vsp1/vsp1_dl.h void vsp1_dl_body_write(struct vsp1_dl_body *dlb, u32 reg, u32 data); reg 555 drivers/media/platform/vsp1/vsp1_drm.c vsp1_dl_body_write(dlb, entity->route->reg, reg 59 drivers/media/platform/vsp1/vsp1_entity.c if (source->route->reg == 0) reg 69 drivers/media/platform/vsp1/vsp1_entity.c vsp1_dl_body_write(dlb, source->route->reg, route); reg 61 drivers/media/platform/vsp1/vsp1_entity.h unsigned int reg; reg 26 drivers/media/platform/vsp1/vsp1_hgo.c static inline u32 vsp1_hgo_read(struct vsp1_hgo *hgo, u32 reg) reg 28 drivers/media/platform/vsp1/vsp1_hgo.c return vsp1_read(hgo->histo.entity.vsp1, reg); reg 32 drivers/media/platform/vsp1/vsp1_hgo.c struct vsp1_dl_body *dlb, u32 reg, u32 data) reg 34 drivers/media/platform/vsp1/vsp1_hgo.c vsp1_dl_body_write(dlb, reg, data); reg 26 drivers/media/platform/vsp1/vsp1_hgt.c static inline u32 vsp1_hgt_read(struct vsp1_hgt *hgt, u32 reg) reg 28 drivers/media/platform/vsp1/vsp1_hgt.c return vsp1_read(hgt->histo.entity.vsp1, reg); reg 32 drivers/media/platform/vsp1/vsp1_hgt.c struct vsp1_dl_body *dlb, u32 reg, u32 data) reg 34 drivers/media/platform/vsp1/vsp1_hgt.c vsp1_dl_body_write(dlb, reg, data); reg 27 drivers/media/platform/vsp1/vsp1_hsit.c struct vsp1_dl_body *dlb, u32 reg, u32 data) reg 29 drivers/media/platform/vsp1/vsp1_hsit.c vsp1_dl_body_write(dlb, reg, data); reg 27 drivers/media/platform/vsp1/vsp1_lif.c struct vsp1_dl_body *dlb, u32 reg, u32 data) reg 29 drivers/media/platform/vsp1/vsp1_lif.c vsp1_dl_body_write(dlb, reg + lif->entity.index * VI6_LIF_OFFSET, reg 29 drivers/media/platform/vsp1/vsp1_lut.c struct vsp1_dl_body *dlb, u32 reg, u32 data) reg 31 drivers/media/platform/vsp1/vsp1_lut.c vsp1_dl_body_write(dlb, reg, data); reg 343 drivers/media/platform/vsp1/vsp1_pipe.c if (entity->route && entity->route->reg) reg 344 drivers/media/platform/vsp1/vsp1_pipe.c vsp1_write(vsp1, entity->route->reg, reg 40 drivers/media/platform/vsp1/vsp1_rpf.c struct vsp1_dl_body *dlb, u32 reg, u32 data) reg 42 drivers/media/platform/vsp1/vsp1_rpf.c vsp1_dl_body_write(dlb, reg + rpf->entity.index * VI6_RPF_OFFSET, reg 28 drivers/media/platform/vsp1/vsp1_sru.c struct vsp1_dl_body *dlb, u32 reg, u32 data) reg 30 drivers/media/platform/vsp1/vsp1_sru.c vsp1_dl_body_write(dlb, reg, data); reg 31 drivers/media/platform/vsp1/vsp1_uds.c struct vsp1_dl_body *dlb, u32 reg, u32 data) reg 33 drivers/media/platform/vsp1/vsp1_uds.c vsp1_dl_body_write(dlb, reg + uds->entity.index * VI6_UDS_OFFSET, data); reg 29 drivers/media/platform/vsp1/vsp1_uif.c static inline u32 vsp1_uif_read(struct vsp1_uif *uif, u32 reg) reg 32 drivers/media/platform/vsp1/vsp1_uif.c uif->entity.index * VI6_UIF_OFFSET + reg); reg 36 drivers/media/platform/vsp1/vsp1_uif.c struct vsp1_dl_body *dlb, u32 reg, u32 data) reg 38 drivers/media/platform/vsp1/vsp1_uif.c vsp1_dl_body_write(dlb, reg + uif->entity.index * VI6_UIF_OFFSET, data); reg 30 drivers/media/platform/vsp1/vsp1_wpf.c struct vsp1_dl_body *dlb, u32 reg, u32 data) reg 32 drivers/media/platform/vsp1/vsp1_wpf.c vsp1_dl_body_write(dlb, reg + wpf->entity.index * VI6_WPF_OFFSET, data); reg 176 drivers/media/platform/xilinx/xilinx-vip.c u32 reg; reg 178 drivers/media/platform/xilinx/xilinx-vip.c reg = xvip_read(xvip, addr); reg 179 drivers/media/platform/xilinx/xilinx-vip.c reg = set ? reg | mask : reg & ~mask; reg 180 drivers/media/platform/xilinx/xilinx-vip.c xvip_write(xvip, addr, reg); reg 196 drivers/media/platform/xilinx/xilinx-vip.c u32 reg; reg 198 drivers/media/platform/xilinx/xilinx-vip.c reg = xvip_read(xvip, addr); reg 199 drivers/media/platform/xilinx/xilinx-vip.c reg &= ~clr; reg 200 drivers/media/platform/xilinx/xilinx-vip.c reg |= set; reg 201 drivers/media/platform/xilinx/xilinx-vip.c xvip_write(xvip, addr, reg); reg 200 drivers/media/platform/xilinx/xilinx-vip.h u32 reg; reg 202 drivers/media/platform/xilinx/xilinx-vip.h reg = xvip_read(xvip, XVIP_ACTIVE_SIZE); reg 203 drivers/media/platform/xilinx/xilinx-vip.h format->width = (reg & XVIP_ACTIVE_HSIZE_MASK) >> reg 205 drivers/media/platform/xilinx/xilinx-vip.h format->height = (reg & XVIP_ACTIVE_VSIZE_MASK) >> reg 127 drivers/media/radio/radio-sf16fmr2.c u32 reg; reg 130 drivers/media/radio/radio-sf16fmr2.c reg = TC9154A_ATT_MAJ(att / 10) | TC9154A_ATT_MIN((att % 10) / 2); reg 131 drivers/media/radio/radio-sf16fmr2.c reg |= channel; reg 134 drivers/media/radio/radio-sf16fmr2.c bit = reg & (1 << i) ? PT_DATA : 0; reg 75 drivers/media/radio/radio-shark2.c static int shark_write_reg(struct radio_tea5777 *tea, u64 reg) reg 83 drivers/media/radio/radio-shark2.c shark->transfer_buffer[i + 1] = (reg >> (40 - i * 8)) & 0xff; reg 104 drivers/media/radio/radio-shark2.c u32 reg = 0; reg 127 drivers/media/radio/radio-shark2.c reg |= shark->transfer_buffer[i] << (16 - i * 8); reg 132 drivers/media/radio/radio-shark2.c *reg_ret = reg; reg 1003 drivers/media/radio/radio-si476x.c struct v4l2_dbg_register *reg) reg 1010 drivers/media/radio/radio-si476x.c reg->size = 2; reg 1012 drivers/media/radio/radio-si476x.c (unsigned int)reg->reg, &value); reg 1013 drivers/media/radio/radio-si476x.c reg->val = value; reg 1019 drivers/media/radio/radio-si476x.c const struct v4l2_dbg_register *reg) reg 1027 drivers/media/radio/radio-si476x.c (unsigned int)reg->reg, reg 1028 drivers/media/radio/radio-si476x.c (unsigned int)reg->val); reg 144 drivers/media/radio/saa7706h.c static int saa7706h_set_reg24(struct v4l2_subdev *sd, u16 reg, u32 val) reg 150 drivers/media/radio/saa7706h.c buf[pos++] = reg >> 8; reg 151 drivers/media/radio/saa7706h.c buf[pos++] = reg; reg 159 drivers/media/radio/saa7706h.c static int saa7706h_set_reg24_err(struct v4l2_subdev *sd, u16 reg, u32 val, reg 162 drivers/media/radio/saa7706h.c return *err ? *err : saa7706h_set_reg24(sd, reg, val); reg 165 drivers/media/radio/saa7706h.c static int saa7706h_set_reg16(struct v4l2_subdev *sd, u16 reg, u16 val) reg 171 drivers/media/radio/saa7706h.c buf[pos++] = reg >> 8; reg 172 drivers/media/radio/saa7706h.c buf[pos++] = reg; reg 179 drivers/media/radio/saa7706h.c static int saa7706h_set_reg16_err(struct v4l2_subdev *sd, u16 reg, u16 val, reg 182 drivers/media/radio/saa7706h.c return *err ? *err : saa7706h_set_reg16(sd, reg, val); reg 185 drivers/media/radio/saa7706h.c static int saa7706h_get_reg16(struct v4l2_subdev *sd, u16 reg) reg 190 drivers/media/radio/saa7706h.c u8 regaddr[] = {reg >> 8, reg}; reg 88 drivers/media/radio/si470x/radio-si470x-usb.c #define REGISTER_REPORT(reg) ((reg) + 1) reg 35 drivers/media/rc/ene_ir.c static void ene_set_reg_addr(struct ene_device *dev, u16 reg) reg 37 drivers/media/rc/ene_ir.c outb(reg >> 8, dev->hw_io + ENE_ADDR_HI); reg 38 drivers/media/rc/ene_ir.c outb(reg & 0xFF, dev->hw_io + ENE_ADDR_LO); reg 42 drivers/media/rc/ene_ir.c static u8 ene_read_reg(struct ene_device *dev, u16 reg) reg 45 drivers/media/rc/ene_ir.c ene_set_reg_addr(dev, reg); reg 47 drivers/media/rc/ene_ir.c dbg_regs("reg %04x == %02x", reg, retval); reg 52 drivers/media/rc/ene_ir.c static void ene_write_reg(struct ene_device *dev, u16 reg, u8 value) reg 54 drivers/media/rc/ene_ir.c dbg_regs("reg %04x <- %02x", reg, value); reg 55 drivers/media/rc/ene_ir.c ene_set_reg_addr(dev, reg); reg 60 drivers/media/rc/ene_ir.c static void ene_set_reg_mask(struct ene_device *dev, u16 reg, u8 mask) reg 62 drivers/media/rc/ene_ir.c dbg_regs("reg %04x |= %02x", reg, mask); reg 63 drivers/media/rc/ene_ir.c ene_set_reg_addr(dev, reg); reg 68 drivers/media/rc/ene_ir.c static void ene_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask) reg 70 drivers/media/rc/ene_ir.c dbg_regs("reg %04x &= ~%02x ", reg, mask); reg 71 drivers/media/rc/ene_ir.c ene_set_reg_addr(dev, reg); reg 76 drivers/media/rc/ene_ir.c static void ene_set_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask, reg 80 drivers/media/rc/ene_ir.c ene_set_reg_mask(dev, reg, mask); reg 82 drivers/media/rc/ene_ir.c ene_clear_reg_mask(dev, reg, mask); reg 720 drivers/media/rc/ene_ir.c u16 hw_value, reg; reg 763 drivers/media/rc/ene_ir.c reg = ene_rx_get_sample_reg(dev); reg 765 drivers/media/rc/ene_ir.c dbg_verbose("next sample to read at: %04x", reg); reg 766 drivers/media/rc/ene_ir.c if (!reg) reg 769 drivers/media/rc/ene_ir.c hw_value = ene_read_reg(dev, reg); reg 776 drivers/media/rc/ene_ir.c hw_value |= ene_read_reg(dev, reg + offset) << 8; reg 26 drivers/media/rc/fintek-cir.c static inline void fintek_cr_write(struct fintek_dev *fintek, u8 val, u8 reg) reg 29 drivers/media/rc/fintek-cir.c __func__, reg, val, fintek->cr_ip, fintek->cr_dp); reg 30 drivers/media/rc/fintek-cir.c outb(reg, fintek->cr_ip); reg 35 drivers/media/rc/fintek-cir.c static inline u8 fintek_cr_read(struct fintek_dev *fintek, u8 reg) reg 39 drivers/media/rc/fintek-cir.c outb(reg, fintek->cr_ip); reg 43 drivers/media/rc/fintek-cir.c __func__, reg, val, fintek->cr_ip, fintek->cr_dp); reg 48 drivers/media/rc/fintek-cir.c static inline void fintek_set_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg) reg 50 drivers/media/rc/fintek-cir.c u8 tmp = fintek_cr_read(fintek, reg) | val; reg 51 drivers/media/rc/fintek-cir.c fintek_cr_write(fintek, tmp, reg); reg 55 drivers/media/rc/fintek-cir.c static inline void fintek_clear_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg) reg 57 drivers/media/rc/fintek-cir.c u8 tmp = fintek_cr_read(fintek, reg) & ~val; reg 58 drivers/media/rc/fintek-cir.c fintek_cr_write(fintek, tmp, reg); reg 63 drivers/media/rc/meson-ir.c void __iomem *reg; reg 68 drivers/media/rc/meson-ir.c static void meson_ir_set_mask(struct meson_ir *ir, unsigned int reg, reg 73 drivers/media/rc/meson-ir.c data = readl(ir->reg + reg); reg 76 drivers/media/rc/meson-ir.c writel(data, ir->reg + reg); reg 87 drivers/media/rc/meson-ir.c duration = readl_relaxed(ir->reg + IR_DEC_REG1); reg 91 drivers/media/rc/meson-ir.c status = readl_relaxed(ir->reg + IR_DEC_STATUS); reg 115 drivers/media/rc/meson-ir.c ir->reg = devm_ioremap_resource(dev, res); reg 116 drivers/media/rc/meson-ir.c if (IS_ERR(ir->reg)) reg 117 drivers/media/rc/meson-ir.c return PTR_ERR(ir->reg); reg 91 drivers/media/rc/mtk-cir.c u32 reg; reg 171 drivers/media/rc/mtk-cir.c static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg) reg 175 drivers/media/rc/mtk-cir.c tmp = __raw_readl(ir->base + reg); reg 177 drivers/media/rc/mtk-cir.c __raw_writel(tmp, ir->base + reg); reg 180 drivers/media/rc/mtk-cir.c static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg) reg 182 drivers/media/rc/mtk-cir.c __raw_writel(val, ir->base + reg); reg 185 drivers/media/rc/mtk-cir.c static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg) reg 187 drivers/media/rc/mtk-cir.c return __raw_readl(ir->base + reg); reg 393 drivers/media/rc/mtk-cir.c ir->data->fields[MTK_CHK_PERIOD].reg); reg 402 drivers/media/rc/mtk-cir.c ir->data->fields[MTK_HW_PERIOD].reg); reg 57 drivers/media/rc/nuvoton-cir.c static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg) reg 59 drivers/media/rc/nuvoton-cir.c outb(reg, nvt->cr_efir); reg 64 drivers/media/rc/nuvoton-cir.c static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg) reg 66 drivers/media/rc/nuvoton-cir.c outb(reg, nvt->cr_efir); reg 71 drivers/media/rc/nuvoton-cir.c static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) reg 73 drivers/media/rc/nuvoton-cir.c u8 tmp = nvt_cr_read(nvt, reg) | val; reg 74 drivers/media/rc/nuvoton-cir.c nvt_cr_write(nvt, tmp, reg); reg 78 drivers/media/rc/nuvoton-cir.c static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg) reg 80 drivers/media/rc/nuvoton-cir.c u8 tmp = nvt_cr_read(nvt, reg) & ~val; reg 81 drivers/media/rc/nuvoton-cir.c nvt_cr_write(nvt, tmp, reg); reg 37 drivers/media/rc/zx-irdec.c static void zx_irdec_set_mask(struct zx_irdec *irdec, unsigned int reg, reg 42 drivers/media/rc/zx-irdec.c data = readl(irdec->base + reg); reg 45 drivers/media/rc/zx-irdec.c writel(data, irdec->base + reg); reg 196 drivers/media/spi/gs1662.c struct v4l2_dbg_register *reg) reg 202 drivers/media/spi/gs1662.c ret = gs_read_register(spi, reg->reg & 0xFFFF, &val); reg 203 drivers/media/spi/gs1662.c reg->val = val; reg 204 drivers/media/spi/gs1662.c reg->size = 2; reg 209 drivers/media/spi/gs1662.c const struct v4l2_dbg_register *reg) reg 213 drivers/media/spi/gs1662.c return gs_write_register(spi, reg->reg & 0xFFFF, reg->val & 0xFFFF); reg 67 drivers/media/tuners/fc0011.c static int fc0011_writereg(struct fc0011_priv *priv, u8 reg, u8 val) reg 69 drivers/media/tuners/fc0011.c u8 buf[2] = { reg, val }; reg 76 drivers/media/tuners/fc0011.c reg, val); reg 83 drivers/media/tuners/fc0011.c static int fc0011_readreg(struct fc0011_priv *priv, u8 reg, u8 *val) reg 88 drivers/media/tuners/fc0011.c .flags = 0, .buf = ®, .len = 1 }, reg 95 drivers/media/tuners/fc0011.c "I2C read failed, reg: %02x\n", reg); reg 11 drivers/media/tuners/fc0012.c static int fc0012_writereg(struct fc0012_priv *priv, u8 reg, u8 val) reg 13 drivers/media/tuners/fc0012.c u8 buf[2] = {reg, val}; reg 21 drivers/media/tuners/fc0012.c KBUILD_MODNAME, reg, val); reg 27 drivers/media/tuners/fc0012.c static int fc0012_readreg(struct fc0012_priv *priv, u8 reg, u8 *val) reg 31 drivers/media/tuners/fc0012.c .buf = ®, .len = 1 }, reg 39 drivers/media/tuners/fc0012.c KBUILD_MODNAME, reg); reg 55 drivers/media/tuners/fc0012.c unsigned char reg[] = { reg 86 drivers/media/tuners/fc0012.c reg[0x07] |= 0x20; reg 94 drivers/media/tuners/fc0012.c reg[0x0c] |= 0x02; reg 97 drivers/media/tuners/fc0012.c reg[0x09] |= 0x01; reg 102 drivers/media/tuners/fc0012.c for (i = 1; i < sizeof(reg); i++) { reg 103 drivers/media/tuners/fc0012.c ret = fc0012_writereg(priv, i, reg[i]); reg 125 drivers/media/tuners/fc0012.c unsigned char reg[7], am, pm, multi, tmp; reg 153 drivers/media/tuners/fc0012.c reg[5] = 0x82; reg 154 drivers/media/tuners/fc0012.c reg[6] = 0x00; reg 157 drivers/media/tuners/fc0012.c reg[5] = 0x82; reg 158 drivers/media/tuners/fc0012.c reg[6] = 0x02; reg 161 drivers/media/tuners/fc0012.c reg[5] = 0x42; reg 162 drivers/media/tuners/fc0012.c reg[6] = 0x00; reg 165 drivers/media/tuners/fc0012.c reg[5] = 0x42; reg 166 drivers/media/tuners/fc0012.c reg[6] = 0x02; reg 169 drivers/media/tuners/fc0012.c reg[5] = 0x22; reg 170 drivers/media/tuners/fc0012.c reg[6] = 0x00; reg 173 drivers/media/tuners/fc0012.c reg[5] = 0x22; reg 174 drivers/media/tuners/fc0012.c reg[6] = 0x02; reg 177 drivers/media/tuners/fc0012.c reg[5] = 0x12; reg 178 drivers/media/tuners/fc0012.c reg[6] = 0x00; reg 181 drivers/media/tuners/fc0012.c reg[5] = 0x12; reg 182 drivers/media/tuners/fc0012.c reg[6] = 0x02; reg 185 drivers/media/tuners/fc0012.c reg[5] = 0x0a; reg 186 drivers/media/tuners/fc0012.c reg[6] = 0x00; reg 189 drivers/media/tuners/fc0012.c reg[5] = 0x0a; reg 190 drivers/media/tuners/fc0012.c reg[6] = 0x02; reg 196 drivers/media/tuners/fc0012.c reg[6] |= 0x08; reg 210 drivers/media/tuners/fc0012.c reg[1] = am + 8; reg 211 drivers/media/tuners/fc0012.c reg[2] = pm - 1; reg 213 drivers/media/tuners/fc0012.c reg[1] = am; reg 214 drivers/media/tuners/fc0012.c reg[2] = pm; reg 218 drivers/media/tuners/fc0012.c reg[1] = 0x06; reg 219 drivers/media/tuners/fc0012.c reg[2] = 0x11; reg 223 drivers/media/tuners/fc0012.c reg[6] |= 0x20; reg 232 drivers/media/tuners/fc0012.c reg[3] = xin >> 8; /* xin with 9 bit resolution */ reg 233 drivers/media/tuners/fc0012.c reg[4] = xin & 0xff; reg 236 drivers/media/tuners/fc0012.c reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */ reg 239 drivers/media/tuners/fc0012.c reg[6] |= 0x80; reg 242 drivers/media/tuners/fc0012.c reg[6] |= 0x40; reg 255 drivers/media/tuners/fc0012.c reg[5] |= 0x07; reg 261 drivers/media/tuners/fc0012.c ret = fc0012_writereg(priv, i, reg[i]); reg 287 drivers/media/tuners/fc0012.c reg[6] &= ~0x08; reg 288 drivers/media/tuners/fc0012.c ret = fc0012_writereg(priv, 0x06, reg[6]); reg 296 drivers/media/tuners/fc0012.c reg[6] |= 0x08; reg 297 drivers/media/tuners/fc0012.c ret = fc0012_writereg(priv, 0x06, reg[6]); reg 13 drivers/media/tuners/fc0013.c static int fc0013_writereg(struct fc0013_priv *priv, u8 reg, u8 val) reg 15 drivers/media/tuners/fc0013.c u8 buf[2] = {reg, val}; reg 21 drivers/media/tuners/fc0013.c err("I2C write reg failed, reg: %02x, val: %02x", reg, val); reg 27 drivers/media/tuners/fc0013.c static int fc0013_readreg(struct fc0013_priv *priv, u8 reg, u8 *val) reg 30 drivers/media/tuners/fc0013.c { .addr = priv->addr, .flags = 0, .buf = ®, .len = 1 }, reg 35 drivers/media/tuners/fc0013.c err("I2C read reg failed, reg: %02x", reg); reg 51 drivers/media/tuners/fc0013.c unsigned char reg[] = { reg 81 drivers/media/tuners/fc0013.c reg[0x07] |= 0x20; reg 89 drivers/media/tuners/fc0013.c reg[0x0c] |= 0x02; reg 94 drivers/media/tuners/fc0013.c for (i = 1; i < sizeof(reg); i++) { reg 95 drivers/media/tuners/fc0013.c ret = fc0013_writereg(priv, i, reg[i]); reg 216 drivers/media/tuners/fc0013.c unsigned char reg[7], am, pm, multi, tmp; reg 302 drivers/media/tuners/fc0013.c reg[5] = 0x82; reg 303 drivers/media/tuners/fc0013.c reg[6] = 0x00; reg 306 drivers/media/tuners/fc0013.c reg[5] = 0x02; reg 307 drivers/media/tuners/fc0013.c reg[6] = 0x02; reg 310 drivers/media/tuners/fc0013.c reg[5] = 0x42; reg 311 drivers/media/tuners/fc0013.c reg[6] = 0x00; reg 314 drivers/media/tuners/fc0013.c reg[5] = 0x82; reg 315 drivers/media/tuners/fc0013.c reg[6] = 0x02; reg 318 drivers/media/tuners/fc0013.c reg[5] = 0x22; reg 319 drivers/media/tuners/fc0013.c reg[6] = 0x00; reg 322 drivers/media/tuners/fc0013.c reg[5] = 0x42; reg 323 drivers/media/tuners/fc0013.c reg[6] = 0x02; reg 326 drivers/media/tuners/fc0013.c reg[5] = 0x12; reg 327 drivers/media/tuners/fc0013.c reg[6] = 0x00; reg 330 drivers/media/tuners/fc0013.c reg[5] = 0x22; reg 331 drivers/media/tuners/fc0013.c reg[6] = 0x02; reg 334 drivers/media/tuners/fc0013.c reg[5] = 0x0a; reg 335 drivers/media/tuners/fc0013.c reg[6] = 0x00; reg 338 drivers/media/tuners/fc0013.c reg[5] = 0x12; reg 339 drivers/media/tuners/fc0013.c reg[6] = 0x02; reg 342 drivers/media/tuners/fc0013.c reg[5] = 0x0a; reg 343 drivers/media/tuners/fc0013.c reg[6] = 0x02; reg 349 drivers/media/tuners/fc0013.c reg[6] |= 0x08; reg 363 drivers/media/tuners/fc0013.c reg[1] = am + 8; reg 364 drivers/media/tuners/fc0013.c reg[2] = pm - 1; reg 366 drivers/media/tuners/fc0013.c reg[1] = am; reg 367 drivers/media/tuners/fc0013.c reg[2] = pm; reg 371 drivers/media/tuners/fc0013.c reg[1] = 0x06; reg 372 drivers/media/tuners/fc0013.c reg[2] = 0x11; reg 376 drivers/media/tuners/fc0013.c reg[6] |= 0x20; reg 385 drivers/media/tuners/fc0013.c reg[3] = xin >> 8; reg 386 drivers/media/tuners/fc0013.c reg[4] = xin & 0xff; reg 389 drivers/media/tuners/fc0013.c reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */ reg 392 drivers/media/tuners/fc0013.c reg[6] |= 0x80; reg 395 drivers/media/tuners/fc0013.c reg[6] |= 0x40; reg 407 drivers/media/tuners/fc0013.c reg[5] |= 0x07; reg 410 drivers/media/tuners/fc0013.c ret = fc0013_writereg(priv, i, reg[i]); reg 446 drivers/media/tuners/fc0013.c reg[6] &= ~0x08; reg 447 drivers/media/tuners/fc0013.c ret = fc0013_writereg(priv, 0x06, reg[6]); reg 455 drivers/media/tuners/fc0013.c reg[6] |= 0x08; reg 456 drivers/media/tuners/fc0013.c ret = fc0013_writereg(priv, 0x06, reg[6]); reg 20 drivers/media/tuners/fc2580.c static int fc2580_wr_reg_ff(struct fc2580_dev *dev, u8 reg, u8 val) reg 25 drivers/media/tuners/fc2580.c return regmap_write(dev->regmap, reg, val); reg 283 drivers/media/tuners/fc2580.c ret = regmap_write(dev->regmap, fc2580_init_reg_vals[i].reg, reg 18 drivers/media/tuners/fc2580_priv.h u8 reg; reg 19 drivers/media/tuners/m88rs6000t.c u8 reg; reg 682 drivers/media/tuners/m88rs6000t.c reg_vals[i].reg, reg_vals[i].val); reg 32 drivers/media/tuners/max2165.c static int max2165_write_reg(struct max2165_priv *priv, u8 reg, u8 data) reg 35 drivers/media/tuners/max2165.c u8 buf[] = { reg, data }; reg 41 drivers/media/tuners/max2165.c dprintk("%s: reg=0x%02X, data=0x%02X\n", __func__, reg, data); reg 47 drivers/media/tuners/max2165.c __func__, reg, data, ret); reg 52 drivers/media/tuners/max2165.c static int max2165_read_reg(struct max2165_priv *priv, u8 reg, u8 *p_data) reg 57 drivers/media/tuners/max2165.c u8 b0[] = { reg }; reg 66 drivers/media/tuners/max2165.c dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg, ret); reg 73 drivers/media/tuners/max2165.c __func__, reg, b1[0]); reg 77 drivers/media/tuners/max2165.c static int max2165_mask_write_reg(struct max2165_priv *priv, u8 reg, reg 84 drivers/media/tuners/max2165.c ret = max2165_read_reg(priv, reg, &v); reg 89 drivers/media/tuners/max2165.c ret = max2165_write_reg(priv, reg, v); reg 42 drivers/media/tuners/mc44s803.c static int mc44s803_readreg(struct mc44s803_priv *priv, u8 reg, u32 *val) reg 53 drivers/media/tuners/mc44s803.c MC44S803_REG_SM(reg, MC44S803_D); reg 312 drivers/media/tuners/mc44s803.c u32 reg; reg 316 drivers/media/tuners/mc44s803.c reg = 0; reg 329 drivers/media/tuners/mc44s803.c ret = mc44s803_readreg(priv, MC44S803_REG_ID, ®); reg 333 drivers/media/tuners/mc44s803.c id = MC44S803_REG_MS(reg, MC44S803_ID); reg 61 drivers/media/tuners/msi001.c u32 reg; reg 66 drivers/media/tuners/msi001.c reg = 1 << 0; reg 67 drivers/media/tuners/msi001.c reg |= (59 - if_gain) << 4; reg 68 drivers/media/tuners/msi001.c reg |= 0 << 10; reg 69 drivers/media/tuners/msi001.c reg |= (1 - mixer_gain) << 12; reg 70 drivers/media/tuners/msi001.c reg |= (1 - lna_gain) << 13; reg 71 drivers/media/tuners/msi001.c reg |= 4 << 14; reg 72 drivers/media/tuners/msi001.c reg |= 0 << 17; reg 73 drivers/media/tuners/msi001.c ret = msi001_wreg(dev, reg); reg 88 drivers/media/tuners/msi001.c u32 reg; reg 242 drivers/media/tuners/msi001.c reg = 0 << 0; reg 243 drivers/media/tuners/msi001.c reg |= mode << 4; reg 244 drivers/media/tuners/msi001.c reg |= filter_mode << 12; reg 245 drivers/media/tuners/msi001.c reg |= bandwidth << 14; reg 246 drivers/media/tuners/msi001.c reg |= 0x02 << 17; reg 247 drivers/media/tuners/msi001.c reg |= 0x00 << 20; reg 248 drivers/media/tuners/msi001.c ret = msi001_wreg(dev, reg); reg 252 drivers/media/tuners/msi001.c reg = 5 << 0; reg 253 drivers/media/tuners/msi001.c reg |= k_thresh << 4; reg 254 drivers/media/tuners/msi001.c reg |= 1 << 19; reg 255 drivers/media/tuners/msi001.c reg |= 1 << 21; reg 256 drivers/media/tuners/msi001.c ret = msi001_wreg(dev, reg); reg 260 drivers/media/tuners/msi001.c reg = 2 << 0; reg 261 drivers/media/tuners/msi001.c reg |= k_frac << 4; reg 262 drivers/media/tuners/msi001.c reg |= div_n << 16; reg 263 drivers/media/tuners/msi001.c ret = msi001_wreg(dev, reg); reg 272 drivers/media/tuners/msi001.c reg = 6 << 0; reg 273 drivers/media/tuners/msi001.c reg |= 63 << 4; reg 274 drivers/media/tuners/msi001.c reg |= 4095 << 10; reg 275 drivers/media/tuners/msi001.c ret = msi001_wreg(dev, reg); reg 28 drivers/media/tuners/mt2060.c static int mt2060_readreg(struct mt2060_priv *priv, u8 reg, u8 *val) reg 41 drivers/media/tuners/mt2060.c b[0] = reg; reg 58 drivers/media/tuners/mt2060.c static int mt2060_writereg(struct mt2060_priv *priv, u8 reg, u8 val) reg 70 drivers/media/tuners/mt2060.c buf[0] = reg; reg 233 drivers/media/tuners/mt2063.c u8 reg[MT2063_REG_END_REGS]; reg 239 drivers/media/tuners/mt2063.c static int mt2063_write(struct mt2063_state *state, u8 reg, u8 *data, u32 len) reg 253 drivers/media/tuners/mt2063.c msg.buf[0] = reg; reg 271 drivers/media/tuners/mt2063.c static int mt2063_setreg(struct mt2063_state *state, u8 reg, u8 val) reg 277 drivers/media/tuners/mt2063.c if (reg >= MT2063_REG_END_REGS) reg 280 drivers/media/tuners/mt2063.c status = mt2063_write(state, reg, &val, 1); reg 284 drivers/media/tuners/mt2063.c state->reg[reg] = val; reg 926 drivers/media/tuners/mt2063.c &state->reg[MT2063_REG_LO_STATUS], 1); reg 931 drivers/media/tuners/mt2063.c if ((state->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) == reg 1022 drivers/media/tuners/mt2063.c if ((state->reg[MT2063_REG_DNC_GAIN] & 0x03) == 0x03) { /* if DNC1 is off */ reg 1023 drivers/media/tuners/mt2063.c if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */ reg 1028 drivers/media/tuners/mt2063.c if ((state->reg[MT2063_REG_VGA_GAIN] & 0x03) == 0x03) /* if DNC2 is off */ reg 1050 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */ reg 1051 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_DNC_GAIN] != reg 1058 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */ reg 1059 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_VGA_GAIN] != reg 1066 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */ reg 1067 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_RSVD_20] != reg 1076 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=x */ reg 1077 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_DNC_GAIN] != reg 1084 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | 0x03; /* Set DNC2GC=3 */ reg 1085 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_VGA_GAIN] != reg 1092 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_RSVD_20] & ~0x40); /* Set PD2MUX=0 */ reg 1093 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_RSVD_20] != reg 1102 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | 0x03; /* Set DNC1GC=3 */ reg 1103 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_DNC_GAIN] != reg 1110 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */ reg 1111 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_VGA_GAIN] != reg 1118 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */ reg 1119 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_RSVD_20] != reg 1128 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_DNC_GAIN] & 0xFC) | (DNC1GC[state->rcvr_mode] & 0x03); /* Set DNC1GC=x */ reg 1129 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_DNC_GAIN] != reg 1136 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_VGA_GAIN] & 0xFC) | (DNC2GC[state->rcvr_mode] & 0x03); /* Set DNC2GC=x */ reg 1137 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_VGA_GAIN] != reg 1144 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_RSVD_20] | 0x40); /* Set PD2MUX=1 */ reg 1145 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_RSVD_20] != reg 1189 drivers/media/tuners/mt2063.c reg[MT2063_REG_PD1_TGT] & ~0x40) | (RFAGCEN[Mode] reg 1192 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_PD1_TGT] != val) reg 1198 drivers/media/tuners/mt2063.c u8 val = (state->reg[MT2063_REG_CTRL_2C] & ~0x03) | reg 1200 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_CTRL_2C] != val) reg 1208 drivers/media/tuners/mt2063.c reg[MT2063_REG_FIFF_CTRL2] & ~0xF0) | reg 1210 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_FIFF_CTRL2] != val) { reg 1215 drivers/media/tuners/mt2063.c (state->reg[MT2063_REG_FIFF_CTRL] | 0x01); reg 1220 drivers/media/tuners/mt2063.c reg[MT2063_REG_FIFF_CTRL] & ~0x01); reg 1232 drivers/media/tuners/mt2063.c u8 val = (state->reg[MT2063_REG_LNA_OV] & ~0x1F) | reg 1234 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_LNA_OV] != val) reg 1240 drivers/media/tuners/mt2063.c u8 val = (state->reg[MT2063_REG_LNA_TGT] & ~0x3F) | reg 1242 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_LNA_TGT] != val) reg 1248 drivers/media/tuners/mt2063.c u8 val = (state->reg[MT2063_REG_RF_OV] & ~0x1F) | reg 1250 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_RF_OV] != val) reg 1256 drivers/media/tuners/mt2063.c u8 val = (state->reg[MT2063_REG_PD1_TGT] & ~0x3F) | reg 1258 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_PD1_TGT] != val) reg 1265 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_PART_REV] != MT2063_B3 && val > 5) reg 1267 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_FIF_OV] & ~0x1F) | reg 1269 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_FIF_OV] != val) reg 1275 drivers/media/tuners/mt2063.c u8 val = (state->reg[MT2063_REG_PD2_TGT] & ~0x3F) | reg 1277 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_PD2_TGT] != val) reg 1283 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_LNA_TGT] & ~0x80) | reg 1285 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_LNA_TGT] != val) reg 1291 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_PD1_TGT] & ~0x80) | reg 1293 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_PD1_TGT] != val) reg 1323 drivers/media/tuners/mt2063.c state->reg[MT2063_REG_PWR_2] &= ~(u8) (Bits >> 8); reg 1327 drivers/media/tuners/mt2063.c &state->reg[MT2063_REG_PWR_2], 1); reg 1330 drivers/media/tuners/mt2063.c state->reg[MT2063_REG_PWR_1] &= ~(u8) (Bits & 0xFF); reg 1334 drivers/media/tuners/mt2063.c &state->reg[MT2063_REG_PWR_1], 1); reg 1351 drivers/media/tuners/mt2063.c state->reg[MT2063_REG_PWR_1] |= 0x04; reg 1353 drivers/media/tuners/mt2063.c state->reg[MT2063_REG_PWR_1] &= ~0x04; reg 1357 drivers/media/tuners/mt2063.c &state->reg[MT2063_REG_PWR_1], 1); reg 1360 drivers/media/tuners/mt2063.c state->reg[MT2063_REG_BYP_CTRL] = reg 1361 drivers/media/tuners/mt2063.c (state->reg[MT2063_REG_BYP_CTRL] & 0x9F) | 0x40; reg 1365 drivers/media/tuners/mt2063.c &state->reg[MT2063_REG_BYP_CTRL], reg 1367 drivers/media/tuners/mt2063.c state->reg[MT2063_REG_BYP_CTRL] = reg 1368 drivers/media/tuners/mt2063.c (state->reg[MT2063_REG_BYP_CTRL] & 0x9F); reg 1372 drivers/media/tuners/mt2063.c &state->reg[MT2063_REG_BYP_CTRL], reg 1544 drivers/media/tuners/mt2063.c val = (state->reg[MT2063_REG_CTUNE_CTRL] | 0x08); reg 1545 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_CTUNE_CTRL] != val) { reg 1549 drivers/media/tuners/mt2063.c val = state->reg[MT2063_REG_CTUNE_OV]; reg 1551 drivers/media/tuners/mt2063.c state->reg[MT2063_REG_CTUNE_OV] = reg 1552 drivers/media/tuners/mt2063.c (u8) ((state->reg[MT2063_REG_CTUNE_OV] & ~0x1F) reg 1554 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_CTUNE_OV] != val) { reg 1567 drivers/media/tuners/mt2063.c &state->reg[MT2063_REG_FIFFC], 1); reg 1568 drivers/media/tuners/mt2063.c fiffc = state->reg[MT2063_REG_FIFFC]; reg 1635 drivers/media/tuners/mt2063.c || ((state->reg[MT2063_REG_LO_STATUS] & (LO1LK | LO2LK)) != reg 1656 drivers/media/tuners/mt2063.c state->reg[MT2063_REG_LO1CQ_1] = (u8) (LO1 & 0xFF); /* DIV1q */ reg 1657 drivers/media/tuners/mt2063.c state->reg[MT2063_REG_LO1CQ_2] = (u8) (Num1 & 0x3F); /* NUM1q */ reg 1658 drivers/media/tuners/mt2063.c state->reg[MT2063_REG_LO2CQ_1] = (u8) (((LO2 & 0x7F) << 1) /* DIV2q */ reg 1660 drivers/media/tuners/mt2063.c state->reg[MT2063_REG_LO2CQ_2] = (u8) ((Num2 & 0x0FF0) >> 4); /* NUM2q (mid) */ reg 1661 drivers/media/tuners/mt2063.c state->reg[MT2063_REG_LO2CQ_3] = (u8) (0xE0 | (Num2 & 0x000F)); /* NUM2q (lo) */ reg 1668 drivers/media/tuners/mt2063.c status |= mt2063_write(state, MT2063_REG_LO1CQ_1, &state->reg[MT2063_REG_LO1CQ_1], 5); /* 0x01 - 0x05 */ reg 1671 drivers/media/tuners/mt2063.c status |= mt2063_write(state, MT2063_REG_LO2CQ_3, &state->reg[MT2063_REG_LO2CQ_3], 1); /* 0x05 */ reg 1674 drivers/media/tuners/mt2063.c if (state->reg[MT2063_REG_FIFF_OFFSET] != reg 1676 drivers/media/tuners/mt2063.c state->reg[MT2063_REG_FIFF_OFFSET] = reg 1682 drivers/media/tuners/mt2063.c reg[MT2063_REG_FIFF_OFFSET], reg 1790 drivers/media/tuners/mt2063.c &state->reg[MT2063_REG_PART_REV], 1); reg 1797 drivers/media/tuners/mt2063.c switch (state->reg[MT2063_REG_PART_REV]) { reg 1812 drivers/media/tuners/mt2063.c state->reg[MT2063_REG_PART_REV]); reg 1818 drivers/media/tuners/mt2063.c &state->reg[MT2063_REG_RSVD_3B], 1); reg 1821 drivers/media/tuners/mt2063.c if (status < 0 || ((state->reg[MT2063_REG_RSVD_3B] & 0x80) != 0x00)) { reg 1823 drivers/media/tuners/mt2063.c state->reg[MT2063_REG_PART_REV], reg 1824 drivers/media/tuners/mt2063.c state->reg[MT2063_REG_RSVD_3B]); reg 1837 drivers/media/tuners/mt2063.c switch (state->reg[MT2063_REG_PART_REV]) { reg 1856 drivers/media/tuners/mt2063.c u8 reg = *def++; reg 1858 drivers/media/tuners/mt2063.c status = mt2063_write(state, reg, &val, 1); reg 1871 drivers/media/tuners/mt2063.c reg[MT2063_REG_XO_STATUS], 1); reg 1872 drivers/media/tuners/mt2063.c FCRUN = (state->reg[MT2063_REG_XO_STATUS] & 0x40) >> 6; reg 1880 drivers/media/tuners/mt2063.c &state->reg[MT2063_REG_FIFFC], 1); reg 1887 drivers/media/tuners/mt2063.c state->reg, MT2063_REG_END_REGS); reg 1892 drivers/media/tuners/mt2063.c state->tuner_id = state->reg[MT2063_REG_PART_REV]; reg 1895 drivers/media/tuners/mt2063.c ((u32) state->reg[MT2063_REG_FIFFC] + 640); reg 1953 drivers/media/tuners/mt2063.c state->reg[MT2063_REG_CTUNE_CTRL] = 0x0A; reg 1955 drivers/media/tuners/mt2063.c &state->reg[MT2063_REG_CTUNE_CTRL], 1); reg 1961 drivers/media/tuners/mt2063.c &state->reg[MT2063_REG_FIFFC], 1); reg 1965 drivers/media/tuners/mt2063.c fcu_osc = state->reg[MT2063_REG_FIFFC]; reg 1967 drivers/media/tuners/mt2063.c state->reg[MT2063_REG_CTUNE_CTRL] = 0x00; reg 1969 drivers/media/tuners/mt2063.c &state->reg[MT2063_REG_CTUNE_CTRL], 1); reg 39 drivers/media/tuners/mt2131.c static int mt2131_readreg(struct mt2131_priv *priv, u8 reg, u8 *val) reg 43 drivers/media/tuners/mt2131.c .buf = ®, .len = 1 }, reg 55 drivers/media/tuners/mt2131.c static int mt2131_writereg(struct mt2131_priv *priv, u8 reg, u8 val) reg 57 drivers/media/tuners/mt2131.c u8 buf[2] = { reg, val }; reg 48 drivers/media/tuners/mt2266.c static int mt2266_readreg(struct mt2266_priv *priv, u8 reg, u8 *val) reg 51 drivers/media/tuners/mt2266.c { .addr = priv->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 }, reg 62 drivers/media/tuners/mt2266.c static int mt2266_writereg(struct mt2266_priv *priv, u8 reg, u8 val) reg 64 drivers/media/tuners/mt2266.c u8 buf[2] = { reg, val }; reg 45 drivers/media/tuners/mxl301rf.c static int reg_write(struct mxl301rf_state *state, u8 reg, u8 val) reg 47 drivers/media/tuners/mxl301rf.c u8 buf[2] = { reg, val }; reg 52 drivers/media/tuners/mxl301rf.c static int reg_read(struct mxl301rf_state *state, u8 reg, u8 *val) reg 54 drivers/media/tuners/mxl301rf.c u8 wbuf[2] = { 0xfb, reg }; reg 138 drivers/media/tuners/mxl301rf.c u8 reg; reg 3875 drivers/media/tuners/mxl5005s.c static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) reg 3878 drivers/media/tuners/mxl5005s.c u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; reg 3885 drivers/media/tuners/mxl5005s.c dprintk(2, "%s(0x%x, 0x%x, 0x%x)\n", __func__, reg, val, msg.addr); reg 72 drivers/media/tuners/mxl5007t.c u8 reg; reg 163 drivers/media/tuners/mxl5007t.c static void set_reg_bits(struct reg_pair_t *reg_pair, u8 reg, u8 mask, u8 val) reg 167 drivers/media/tuners/mxl5007t.c while (reg_pair[i].reg || reg_pair[i].val) { reg 168 drivers/media/tuners/mxl5007t.c if (reg_pair[i].reg == reg) { reg 185 drivers/media/tuners/mxl5007t.c while (reg_pair1[i].reg || reg_pair1[i].val) { reg 186 drivers/media/tuners/mxl5007t.c while (reg_pair2[j].reg || reg_pair2[j].val) { reg 187 drivers/media/tuners/mxl5007t.c if (reg_pair1[i].reg != reg_pair2[j].reg) { reg 448 drivers/media/tuners/mxl5007t.c static int mxl5007t_write_reg(struct mxl5007t_state *state, u8 reg, u8 val) reg 450 drivers/media/tuners/mxl5007t.c u8 buf[] = { reg, val }; reg 469 drivers/media/tuners/mxl5007t.c while ((ret == 0) && (reg_pair[i].reg || reg_pair[i].val)) { reg 471 drivers/media/tuners/mxl5007t.c reg_pair[i].reg, reg_pair[i].val); reg 477 drivers/media/tuners/mxl5007t.c static int mxl5007t_read_reg(struct mxl5007t_state *state, u8 reg, u8 *val) reg 479 drivers/media/tuners/mxl5007t.c u8 buf[2] = { 0xfb, reg }; reg 64 drivers/media/tuners/qm1d1c0042.c static int reg_write(struct qm1d1c0042_state *state, u8 reg, u8 val) reg 66 drivers/media/tuners/qm1d1c0042.c u8 wbuf[2] = { reg, val }; reg 75 drivers/media/tuners/qm1d1c0042.c static int reg_read(struct qm1d1c0042_state *state, u8 reg, u8 *val) reg 81 drivers/media/tuners/qm1d1c0042.c .buf = ®, reg 12 drivers/media/tuners/qt1010.c static int qt1010_readreg(struct qt1010_priv *priv, u8 reg, u8 *val) reg 16 drivers/media/tuners/qt1010.c .flags = 0, .buf = ®, .len = 1 }, reg 23 drivers/media/tuners/qt1010.c KBUILD_MODNAME, reg); reg 30 drivers/media/tuners/qt1010.c static int qt1010_writereg(struct qt1010_priv *priv, u8 reg, u8 val) reg 32 drivers/media/tuners/qt1010.c u8 buf[2] = { reg, val }; reg 38 drivers/media/tuners/qt1010.c KBUILD_MODNAME, reg); reg 202 drivers/media/tuners/qt1010.c err = qt1010_writereg(priv, rd[i].reg, rd[i].val); reg 204 drivers/media/tuners/qt1010.c err = qt1010_readreg(priv, rd[i].reg, &tmpval); reg 216 drivers/media/tuners/qt1010.c u8 oper, u8 reg, u8 reg_init_val, u8 *retval) reg 222 drivers/media/tuners/qt1010.c { QT1010_WR, reg, reg_init_val }, reg 225 drivers/media/tuners/qt1010.c { QT1010_RD, reg, 0xff } reg 230 drivers/media/tuners/qt1010.c err = qt1010_writereg(priv, i2c_data[i].reg, reg 233 drivers/media/tuners/qt1010.c err = qt1010_readreg(priv, i2c_data[i].reg, &val2); reg 240 drivers/media/tuners/qt1010.c err = qt1010_readreg(priv, reg, &val2); reg 243 drivers/media/tuners/qt1010.c __func__, reg, val1, val2); reg 266 drivers/media/tuners/qt1010.c err = qt1010_writereg(priv, i2c_data[i].reg, reg 269 drivers/media/tuners/qt1010.c err = qt1010_readreg(priv, i2c_data[i].reg, &val); reg 327 drivers/media/tuners/qt1010.c err = qt1010_writereg(priv, i2c_data[i].reg, reg 335 drivers/media/tuners/qt1010.c err = qt1010_readreg(priv, i2c_data[i].reg, valptr); reg 347 drivers/media/tuners/qt1010.c err = qt1010_init_meas1(priv, i2c_data[i+1].reg, reg 348 drivers/media/tuners/qt1010.c i2c_data[i].reg, reg 79 drivers/media/tuners/qt1010_priv.h u8 oper, reg, val; reg 332 drivers/media/tuners/r820t.c static void shadow_store(struct r820t_priv *priv, u8 reg, const u8 *val, reg 335 drivers/media/tuners/r820t.c int r = reg - REG_SHADOW_START; reg 352 drivers/media/tuners/r820t.c static int r820t_write(struct r820t_priv *priv, u8 reg, const u8 *val, reg 358 drivers/media/tuners/r820t.c shadow_store(priv, reg, val, len); reg 367 drivers/media/tuners/r820t.c priv->buf[0] = reg; reg 373 drivers/media/tuners/r820t.c __func__, rc, reg, size, size, &priv->buf[1]); reg 379 drivers/media/tuners/r820t.c __func__, reg, size, size, &priv->buf[1]); reg 381 drivers/media/tuners/r820t.c reg += size; reg 389 drivers/media/tuners/r820t.c static inline int r820t_write_reg(struct r820t_priv *priv, u8 reg, u8 val) reg 393 drivers/media/tuners/r820t.c return r820t_write(priv, reg, &tmp, 1); reg 396 drivers/media/tuners/r820t.c static int r820t_read_cache_reg(struct r820t_priv *priv, int reg) reg 398 drivers/media/tuners/r820t.c reg -= REG_SHADOW_START; reg 400 drivers/media/tuners/r820t.c if (reg >= 0 && reg < NUM_REGS) reg 401 drivers/media/tuners/r820t.c return priv->regs[reg]; reg 406 drivers/media/tuners/r820t.c static inline int r820t_write_reg_mask(struct r820t_priv *priv, u8 reg, u8 val, reg 410 drivers/media/tuners/r820t.c int rc = r820t_read_cache_reg(priv, reg); reg 417 drivers/media/tuners/r820t.c return r820t_write(priv, reg, &tmp, 1); reg 420 drivers/media/tuners/r820t.c static int r820t_read(struct r820t_priv *priv, u8 reg, u8 *val, int len) reg 425 drivers/media/tuners/r820t.c priv->buf[0] = reg; reg 430 drivers/media/tuners/r820t.c __func__, rc, reg, len, len, p); reg 441 drivers/media/tuners/r820t.c __func__, reg, len, len, val); reg 1609 drivers/media/tuners/r820t.c struct r820t_sect_type iq[3], u8 reg) reg 1627 drivers/media/tuners/r820t.c if (reg == 0x08) reg 14 drivers/media/tuners/tda18218.c static int tda18218_wr_regs(struct tda18218_priv *priv, u8 reg, u8 *val, u8 len) reg 29 drivers/media/tuners/tda18218.c KBUILD_MODNAME, reg, len); reg 40 drivers/media/tuners/tda18218.c buf[0] = reg + len - remaining; reg 52 drivers/media/tuners/tda18218.c "len=%d\n", KBUILD_MODNAME, ret, reg, len); reg 60 drivers/media/tuners/tda18218.c static int tda18218_rd_regs(struct tda18218_priv *priv, u8 reg, u8 *val, u8 len) reg 73 drivers/media/tuners/tda18218.c .len = reg + len, reg 78 drivers/media/tuners/tda18218.c if (reg + len > sizeof(buf)) { reg 81 drivers/media/tuners/tda18218.c KBUILD_MODNAME, reg, len); reg 87 drivers/media/tuners/tda18218.c memcpy(val, &buf[reg], len); reg 91 drivers/media/tuners/tda18218.c "len=%d\n", KBUILD_MODNAME, ret, reg, len); reg 99 drivers/media/tuners/tda18218.c static int tda18218_wr_reg(struct tda18218_priv *priv, u8 reg, u8 val) reg 101 drivers/media/tuners/tda18218.c return tda18218_wr_regs(priv, reg, &val, 1); reg 106 drivers/media/tuners/tda18218.c static int tda18218_rd_reg(struct tda18218_priv *priv, u8 reg, u8 *val) reg 108 drivers/media/tuners/tda18218.c return tda18218_rd_regs(priv, reg, val, 1); reg 661 drivers/media/tuners/tda8290.c u8 reg = 0x1f, id; reg 663 drivers/media/tuners/tda8290.c { .addr = i2c_props->addr, .flags = 0, .len = 1, .buf = ® }, reg 670 drivers/media/tuners/tda8290.c __func__, reg); reg 688 drivers/media/tuners/tda8290.c u8 reg = 0x2f, id; reg 690 drivers/media/tuners/tda8290.c { .addr = i2c_props->addr, .flags = 0, .len = 1, .buf = ® }, reg 697 drivers/media/tuners/tda8290.c __func__, reg); reg 609 drivers/media/tuners/tda9887.c __u8 reg = 0; reg 613 drivers/media/tuners/tda9887.c if (1 == tuner_i2c_xfer_recv(&priv->i2c_props, ®, 1)) reg 614 drivers/media/tuners/tda9887.c *afc = AFC_BITS_2_kHz[(reg >> 1) & 0x0f]; reg 44 drivers/media/tuners/tua9001.c ret = regmap_write(dev->regmap, data[i].reg, data[i].val); reg 113 drivers/media/tuners/tua9001.c data[0].reg = 0x04; reg 115 drivers/media/tuners/tua9001.c data[1].reg = 0x1f; reg 127 drivers/media/tuners/tua9001.c ret = regmap_write(dev->regmap, data[i].reg, data[i].val); reg 16 drivers/media/tuners/tua9001_priv.h u8 reg; reg 158 drivers/media/tuners/tuner-xc2028.c static int xc2028_get_reg(struct xc2028_data *priv, u16 reg, u16 *val) reg 163 drivers/media/tuners/tuner-xc2028.c tuner_dbg("%s %04x called\n", __func__, reg); reg 165 drivers/media/tuners/tuner-xc2028.c buf[0] = reg >> 8; reg 166 drivers/media/tuners/tuner-xc2028.c buf[1] = (unsigned char) reg; reg 237 drivers/media/tuners/xc4000.c static int xc4000_readreg(struct xc4000_priv *priv, u16 reg, u16 *val); reg 531 drivers/media/tuners/xc4000.c static int xc4000_readreg(struct xc4000_priv *priv, u16 reg, u16 *val) reg 533 drivers/media/tuners/xc4000.c u8 buf[2] = { reg >> 8, reg & 0xff }; reg 241 drivers/media/tuners/xc5000.c static int xc5000_readreg(struct xc5000_priv *priv, u16 reg, u16 *val); reg 273 drivers/media/tuners/xc5000.c static int xc5000_readreg(struct xc5000_priv *priv, u16 reg, u16 *val) reg 275 drivers/media/tuners/xc5000.c u8 buf[2] = { reg >> 8, reg & 0xff }; reg 49 drivers/media/usb/au0828/au0828-core.c u32 au0828_readreg(struct au0828_dev *dev, u16 reg) reg 53 drivers/media/usb/au0828/au0828-core.c recv_control_msg(dev, CMD_REQUEST_IN, 0, reg, &result, 1); reg 54 drivers/media/usb/au0828/au0828-core.c dprintk(8, "%s(0x%04x) = 0x%02x\n", __func__, reg, result); reg 59 drivers/media/usb/au0828/au0828-core.c u32 au0828_writereg(struct au0828_dev *dev, u16 reg, u32 val) reg 61 drivers/media/usb/au0828/au0828-core.c dprintk(8, "%s(0x%04x, 0x%02x)\n", __func__, reg, val); reg 62 drivers/media/usb/au0828/au0828-core.c return send_control_msg(dev, CMD_REQUEST_OUT, val, reg); reg 43 drivers/media/usb/au0828/au0828-input.c static int au8522_rc_write(struct au0828_rc *ir, u16 reg, u8 data) reg 46 drivers/media/usb/au0828/au0828-input.c char buf[] = { (reg >> 8) | 0x80, reg & 0xff, data }; reg 58 drivers/media/usb/au0828/au0828-input.c static int au8522_rc_read(struct au0828_rc *ir, u16 reg, int val, reg 68 drivers/media/usb/au0828/au0828-input.c obuf[0] = 0x40 | reg >> 8; reg 69 drivers/media/usb/au0828/au0828-input.c obuf[1] = reg & 0xff; reg 83 drivers/media/usb/au0828/au0828-input.c static int au8522_rc_andor(struct au0828_rc *ir, u16 reg, u8 mask, u8 value) reg 88 drivers/media/usb/au0828/au0828-input.c rc = au8522_rc_read(ir, reg, -1, &buf, 1); reg 99 drivers/media/usb/au0828/au0828-input.c return au8522_rc_write(ir, reg, buf); reg 102 drivers/media/usb/au0828/au0828-input.c #define au8522_rc_set(ir, reg, bit) au8522_rc_andor(ir, (reg), (bit), (bit)) reg 103 drivers/media/usb/au0828/au0828-input.c #define au8522_rc_clear(ir, reg, bit) au8522_rc_andor(ir, (reg), (bit), 0) reg 1644 drivers/media/usb/au0828/au0828-video.c struct v4l2_dbg_register *reg) reg 1651 drivers/media/usb/au0828/au0828-video.c reg->val = au0828_read(dev, reg->reg); reg 1652 drivers/media/usb/au0828/au0828-video.c reg->size = 1; reg 1657 drivers/media/usb/au0828/au0828-video.c const struct v4l2_dbg_register *reg) reg 1664 drivers/media/usb/au0828/au0828-video.c return au0828_writereg(dev, reg->reg, reg->val); reg 288 drivers/media/usb/au0828/au0828.h #define au0828_read(dev, reg) au0828_readreg(dev, reg) reg 289 drivers/media/usb/au0828/au0828.h #define au0828_write(dev, reg, value) au0828_writereg(dev, reg, value) reg 290 drivers/media/usb/au0828/au0828.h #define au0828_andor(dev, reg, mask, value) \ reg 291 drivers/media/usb/au0828/au0828.h au0828_writereg(dev, reg, \ reg 292 drivers/media/usb/au0828/au0828.h (au0828_readreg(dev, reg) & ~(mask)) | ((value) & (mask))) reg 294 drivers/media/usb/au0828/au0828.h #define au0828_set(dev, reg, bit) au0828_andor(dev, (reg), (bit), (bit)) reg 295 drivers/media/usb/au0828/au0828.h #define au0828_clear(dev, reg, bit) au0828_andor(dev, (reg), (bit), 0) reg 299 drivers/media/usb/au0828/au0828.h extern u32 au0828_read(struct au0828_dev *dev, u16 reg); reg 300 drivers/media/usb/au0828/au0828.h extern u32 au0828_write(struct au0828_dev *dev, u16 reg, u32 val); reg 304 drivers/media/usb/b2c2/flexcop-usb.c flexcop_ibi_register reg) reg 308 drivers/media/usb/b2c2/flexcop-usb.c flexcop_usb_readwrite_dw(fc, reg, &val.raw, 1); reg 313 drivers/media/usb/b2c2/flexcop-usb.c flexcop_ibi_register reg, flexcop_ibi_value val) reg 315 drivers/media/usb/b2c2/flexcop-usb.c return flexcop_usb_readwrite_dw(fc, reg, &val.raw, 0); reg 384 drivers/media/usb/cpia2/cpia2_usb.c unsigned char reg; reg 411 drivers/media/usb/cpia2/cpia2_usb.c reg = cmd.buffer.block_data[0]; reg 414 drivers/media/usb/cpia2/cpia2_usb.c reg &= ~(CPIA2_VC_USB_STRM_BLK_ENABLE | reg 420 drivers/media/usb/cpia2/cpia2_usb.c reg |= CPIA2_VC_USB_STRM_BLK_ENABLE; /* Enable Bulk */ reg 424 drivers/media/usb/cpia2/cpia2_usb.c reg |= CPIA2_VC_USB_STRM_ISO_ENABLE; reg 428 drivers/media/usb/cpia2/cpia2_usb.c cmd.buffer.block_data[0] = reg; reg 282 drivers/media/usb/cx231xx/cx231xx-core.c int cx231xx_read_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg, reg 317 drivers/media/usb/cx231xx/cx231xx-core.c val, reg, buf, len, HZ); reg 400 drivers/media/usb/cx231xx/cx231xx-core.c int cx231xx_write_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg, char *buf, reg 439 drivers/media/usb/cx231xx/cx231xx-core.c req, 0, val, reg & 0xff, reg 440 drivers/media/usb/cx231xx/cx231xx-core.c reg >> 8, len & 0xff, len >> 8); reg 449 drivers/media/usb/cx231xx/cx231xx-core.c val, reg, buf, len, HZ); reg 85 drivers/media/usb/cx231xx/cx231xx-video.c .reg = 0, reg 1366 drivers/media/usb/cx231xx/cx231xx-video.c struct v4l2_dbg_register *reg) reg 1374 drivers/media/usb/cx231xx/cx231xx-video.c switch (reg->match.addr) { reg 1377 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, value, 4); reg 1378 drivers/media/usb/cx231xx/cx231xx-video.c reg->val = value[0] | value[1] << 8 | reg 1380 drivers/media/usb/cx231xx/cx231xx-video.c reg->size = 4; reg 1384 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, 2, &data, 1); reg 1385 drivers/media/usb/cx231xx/cx231xx-video.c reg->val = data; reg 1386 drivers/media/usb/cx231xx/cx231xx-video.c reg->size = 1; reg 1390 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, 2, &data, 1); reg 1391 drivers/media/usb/cx231xx/cx231xx-video.c reg->val = data; reg 1392 drivers/media/usb/cx231xx/cx231xx-video.c reg->size = 1; reg 1396 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, 1, &data, 1); reg 1397 drivers/media/usb/cx231xx/cx231xx-video.c reg->val = data; reg 1398 drivers/media/usb/cx231xx/cx231xx-video.c reg->size = 1; reg 1402 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, 2, &data, 4); reg 1403 drivers/media/usb/cx231xx/cx231xx-video.c reg->val = data; reg 1404 drivers/media/usb/cx231xx/cx231xx-video.c reg->size = 4; reg 1408 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, 2, &data, 4); reg 1409 drivers/media/usb/cx231xx/cx231xx-video.c reg->val = data; reg 1410 drivers/media/usb/cx231xx/cx231xx-video.c reg->size = 4; reg 1414 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, 1, &data, 4); reg 1415 drivers/media/usb/cx231xx/cx231xx-video.c reg->val = data; reg 1416 drivers/media/usb/cx231xx/cx231xx-video.c reg->size = 4; reg 1425 drivers/media/usb/cx231xx/cx231xx-video.c const struct v4l2_dbg_register *reg) reg 1432 drivers/media/usb/cx231xx/cx231xx-video.c switch (reg->match.addr) { reg 1434 drivers/media/usb/cx231xx/cx231xx-video.c data[0] = (u8) reg->val; reg 1435 drivers/media/usb/cx231xx/cx231xx-video.c data[1] = (u8) (reg->val >> 8); reg 1436 drivers/media/usb/cx231xx/cx231xx-video.c data[2] = (u8) (reg->val >> 16); reg 1437 drivers/media/usb/cx231xx/cx231xx-video.c data[3] = (u8) (reg->val >> 24); reg 1439 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, data, 4); reg 1443 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, 2, reg->val, 1); reg 1447 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, 2, reg->val, 1); reg 1451 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, 1, reg->val, 1); reg 1455 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, 2, reg->val, 4); reg 1459 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, 2, reg->val, 4); reg 1463 drivers/media/usb/cx231xx/cx231xx-video.c (u16)reg->reg, 1, reg->val, 4); reg 220 drivers/media/usb/cx231xx/cx231xx.h int reg; reg 673 drivers/media/usb/cx231xx/cx231xx.h int (*cx231xx_read_ctrl_reg) (struct cx231xx *dev, u8 req, u16 reg, reg 675 drivers/media/usb/cx231xx/cx231xx.h int (*cx231xx_write_ctrl_reg) (struct cx231xx *dev, u8 req, u16 reg, reg 836 drivers/media/usb/cx231xx/cx231xx.h int cx231xx_read_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg, reg 840 drivers/media/usb/cx231xx/cx231xx.h int cx231xx_write_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg, reg 954 drivers/media/usb/cx231xx/cx231xx.h struct v4l2_dbg_register *reg); reg 956 drivers/media/usb/cx231xx/cx231xx.h const struct v4l2_dbg_register *reg); reg 112 drivers/media/usb/dvb-usb-v2/af9015.c static int af9015_write_reg_i2c(struct dvb_usb_device *d, u8 addr, u16 reg, reg 116 drivers/media/usb/dvb-usb-v2/af9015.c struct req_t req = {WRITE_I2C, addr, reg, 1, 1, 1, &val}; reg 125 drivers/media/usb/dvb-usb-v2/af9015.c static int af9015_read_reg_i2c(struct dvb_usb_device *d, u8 addr, u16 reg, reg 129 drivers/media/usb/dvb-usb-v2/af9015.c struct req_t req = {READ_I2C, addr, reg, 0, 1, 1, val}; reg 1299 drivers/media/usb/dvb-usb-v2/af9015.c u16 reg = ((u8 *)data)[0] << 8 | ((u8 *)data)[1] << 0; reg 1302 drivers/media/usb/dvb-usb-v2/af9015.c struct req_t req = {WRITE_MEMORY, 0, reg, 0, 0, len, val}; reg 1320 drivers/media/usb/dvb-usb-v2/af9015.c u16 reg = ((u8 *)reg_buf)[0] << 8 | ((u8 *)reg_buf)[1] << 0; reg 1323 drivers/media/usb/dvb-usb-v2/af9015.c struct req_t req = {READ_MEMORY, 0, reg, 0, 0, len, val}; reg 114 drivers/media/usb/dvb-usb-v2/af9035.c static int af9035_wr_regs(struct dvb_usb_device *d, u32 reg, u8 *val, int len) reg 118 drivers/media/usb/dvb-usb-v2/af9035.c u8 mbox = (reg >> 16) & 0xff; reg 130 drivers/media/usb/dvb-usb-v2/af9035.c wbuf[4] = (reg >> 8) & 0xff; reg 131 drivers/media/usb/dvb-usb-v2/af9035.c wbuf[5] = (reg >> 0) & 0xff; reg 138 drivers/media/usb/dvb-usb-v2/af9035.c static int af9035_rd_regs(struct dvb_usb_device *d, u32 reg, u8 *val, int len) reg 140 drivers/media/usb/dvb-usb-v2/af9035.c u8 wbuf[] = { len, 2, 0, 0, (reg >> 8) & 0xff, reg & 0xff }; reg 141 drivers/media/usb/dvb-usb-v2/af9035.c u8 mbox = (reg >> 16) & 0xff; reg 148 drivers/media/usb/dvb-usb-v2/af9035.c static int af9035_wr_reg(struct dvb_usb_device *d, u32 reg, u8 val) reg 150 drivers/media/usb/dvb-usb-v2/af9035.c return af9035_wr_regs(d, reg, &val, 1); reg 154 drivers/media/usb/dvb-usb-v2/af9035.c static int af9035_rd_reg(struct dvb_usb_device *d, u32 reg, u8 *val) reg 156 drivers/media/usb/dvb-usb-v2/af9035.c return af9035_rd_regs(d, reg, val, 1); reg 160 drivers/media/usb/dvb-usb-v2/af9035.c static int af9035_wr_reg_mask(struct dvb_usb_device *d, u32 reg, u8 val, reg 168 drivers/media/usb/dvb-usb-v2/af9035.c ret = af9035_rd_regs(d, reg, &tmp, 1); reg 177 drivers/media/usb/dvb-usb-v2/af9035.c return af9035_wr_regs(d, reg, &val, 1); reg 325 drivers/media/usb/dvb-usb-v2/af9035.c u32 reg = msg[0].buf[0] << 16 | msg[0].buf[1] << 8 | reg 329 drivers/media/usb/dvb-usb-v2/af9035.c reg |= 0x100000; reg 331 drivers/media/usb/dvb-usb-v2/af9035.c ret = af9035_rd_regs(d, reg, &msg[1].buf[0], reg 384 drivers/media/usb/dvb-usb-v2/af9035.c u32 reg = msg[0].buf[0] << 16 | msg[0].buf[1] << 8 | reg 388 drivers/media/usb/dvb-usb-v2/af9035.c reg |= 0x100000; reg 390 drivers/media/usb/dvb-usb-v2/af9035.c ret = (msg[0].len >= 3) ? af9035_wr_regs(d, reg, reg 1722 drivers/media/usb/dvb-usb-v2/af9035.c ret = af9035_wr_reg_mask(d, tab[i].reg, tab[i].val, reg 1804 drivers/media/usb/dvb-usb-v2/af9035.c ret = af9035_wr_reg_mask(d, tab[i].reg, reg 26 drivers/media/usb/dvb-usb-v2/af9035.h u32 reg; reg 31 drivers/media/usb/dvb-usb-v2/af9035.h u32 reg; reg 104 drivers/media/usb/dvb-usb-v2/anysee.c static int anysee_read_reg(struct dvb_usb_device *d, u16 reg, u8 *val) reg 106 drivers/media/usb/dvb-usb-v2/anysee.c u8 buf[] = {CMD_REG_READ, reg >> 8, reg & 0xff, 0x01}; reg 109 drivers/media/usb/dvb-usb-v2/anysee.c dev_dbg(&d->udev->dev, "%s: reg=%04x val=%02x\n", __func__, reg, *val); reg 113 drivers/media/usb/dvb-usb-v2/anysee.c static int anysee_write_reg(struct dvb_usb_device *d, u16 reg, u8 val) reg 115 drivers/media/usb/dvb-usb-v2/anysee.c u8 buf[] = {CMD_REG_WRITE, reg >> 8, reg & 0xff, 0x01, val}; reg 116 drivers/media/usb/dvb-usb-v2/anysee.c dev_dbg(&d->udev->dev, "%s: reg=%04x val=%02x\n", __func__, reg, val); reg 121 drivers/media/usb/dvb-usb-v2/anysee.c static int anysee_wr_reg_mask(struct dvb_usb_device *d, u16 reg, u8 val, reg 129 drivers/media/usb/dvb-usb-v2/anysee.c ret = anysee_read_reg(d, reg, &tmp); reg 138 drivers/media/usb/dvb-usb-v2/anysee.c return anysee_write_reg(d, reg, val); reg 142 drivers/media/usb/dvb-usb-v2/anysee.c static int anysee_rd_reg_mask(struct dvb_usb_device *d, u16 reg, u8 *val, reg 148 drivers/media/usb/dvb-usb-v2/anysee.c ret = anysee_read_reg(d, reg, &tmp); reg 927 drivers/media/usb/dvb-usb-v2/mxl111sf.c u8 reg = 0; reg 929 drivers/media/usb/dvb-usb-v2/mxl111sf.c { .addr = 0xa0 >> 1, .len = 1, .buf = ® }, reg 63 drivers/media/usb/dvb-usb-v2/rtl28xxu.c static int rtl28xxu_wr_regs(struct dvb_usb_device *d, u16 reg, u8 *val, int len) reg 67 drivers/media/usb/dvb-usb-v2/rtl28xxu.c if (reg < 0x3000) reg 69 drivers/media/usb/dvb-usb-v2/rtl28xxu.c else if (reg < 0x4000) reg 74 drivers/media/usb/dvb-usb-v2/rtl28xxu.c req.value = reg; reg 81 drivers/media/usb/dvb-usb-v2/rtl28xxu.c static int rtl28xxu_rd_regs(struct dvb_usb_device *d, u16 reg, u8 *val, int len) reg 85 drivers/media/usb/dvb-usb-v2/rtl28xxu.c if (reg < 0x3000) reg 87 drivers/media/usb/dvb-usb-v2/rtl28xxu.c else if (reg < 0x4000) reg 92 drivers/media/usb/dvb-usb-v2/rtl28xxu.c req.value = reg; reg 99 drivers/media/usb/dvb-usb-v2/rtl28xxu.c static int rtl28xxu_wr_reg(struct dvb_usb_device *d, u16 reg, u8 val) reg 101 drivers/media/usb/dvb-usb-v2/rtl28xxu.c return rtl28xxu_wr_regs(d, reg, &val, 1); reg 104 drivers/media/usb/dvb-usb-v2/rtl28xxu.c static int rtl28xxu_rd_reg(struct dvb_usb_device *d, u16 reg, u8 *val) reg 106 drivers/media/usb/dvb-usb-v2/rtl28xxu.c return rtl28xxu_rd_regs(d, reg, val, 1); reg 109 drivers/media/usb/dvb-usb-v2/rtl28xxu.c static int rtl28xxu_wr_reg_mask(struct dvb_usb_device *d, u16 reg, u8 val, reg 117 drivers/media/usb/dvb-usb-v2/rtl28xxu.c ret = rtl28xxu_rd_reg(d, reg, &tmp); reg 126 drivers/media/usb/dvb-usb-v2/rtl28xxu.c return rtl28xxu_wr_reg(d, reg, val); reg 1644 drivers/media/usb/dvb-usb-v2/rtl28xxu.c ret = rtl28xxu_wr_reg(d, rc_nec_tab[i].reg, reg 1741 drivers/media/usb/dvb-usb-v2/rtl28xxu.c ret = rtl28xxu_wr_reg_mask(d, init_tab[i].reg, reg 1770 drivers/media/usb/dvb-usb-v2/rtl28xxu.c ret = rtl28xxu_wr_reg_mask(d, refresh_tab[i].reg, reg 123 drivers/media/usb/dvb-usb-v2/rtl28xxu.h u16 reg; reg 128 drivers/media/usb/dvb-usb-v2/rtl28xxu.h u16 reg; reg 85 drivers/media/usb/dvb-usb-v2/zd1301.c static int zd1301_demod_wreg(void *reg_priv, u16 reg, u8 val) reg 91 drivers/media/usb/dvb-usb-v2/zd1301.c (reg >> 0) & 0xff, (reg >> 8) & 0xff, val}; reg 103 drivers/media/usb/dvb-usb-v2/zd1301.c static int zd1301_demod_rreg(void *reg_priv, u16 reg, u8 *val) reg 109 drivers/media/usb/dvb-usb-v2/zd1301.c (reg >> 0) & 0xff, (reg >> 8) & 0xff, 0}; reg 964 drivers/media/usb/dvb-usb/af9005-fe.c af9005_write_register_bits(state->d, script[i].reg, reg 969 drivers/media/usb/dvb-usb/af9005-fe.c if (script[i].reg == 0xae18) reg 971 drivers/media/usb/dvb-usb/af9005-fe.c if (script[i].reg == 0xae19) reg 973 drivers/media/usb/dvb-usb/af9005-fe.c if (script[i].reg == 0xae1a) reg 977 drivers/media/usb/dvb-usb/af9005-fe.c if (script[i].reg == xd_p_reg_unplug_th) reg 979 drivers/media/usb/dvb-usb/af9005-fe.c if (script[i].reg == xd_p_reg_unplug_rf_gain_th) reg 981 drivers/media/usb/dvb-usb/af9005-fe.c if (script[i].reg == xd_p_reg_unplug_dtop_if_gain_th) reg 983 drivers/media/usb/dvb-usb/af9005-fe.c if (script[i].reg == xd_p_reg_unplug_dtop_rf_gain_th) reg 12 drivers/media/usb/dvb-usb/af9005-script.h u16 reg; reg 45 drivers/media/usb/dvb-usb/af9005.c static int af9005_generic_read_write(struct dvb_usb_device *d, u16 reg, reg 70 drivers/media/usb/dvb-usb/af9005.c st->data[5] = (u8) (reg >> 8); /* register address */ reg 71 drivers/media/usb/dvb-usb/af9005.c st->data[6] = (u8) (reg & 0xff); reg 134 drivers/media/usb/dvb-usb/af9005.c int af9005_read_ofdm_register(struct dvb_usb_device *d, u16 reg, u8 * value) reg 137 drivers/media/usb/dvb-usb/af9005.c deb_reg("read register %x ", reg); reg 138 drivers/media/usb/dvb-usb/af9005.c ret = af9005_generic_read_write(d, reg, reg 148 drivers/media/usb/dvb-usb/af9005.c int af9005_read_ofdm_registers(struct dvb_usb_device *d, u16 reg, reg 152 drivers/media/usb/dvb-usb/af9005.c deb_reg("read %d registers %x ", len, reg); reg 153 drivers/media/usb/dvb-usb/af9005.c ret = af9005_generic_read_write(d, reg, reg 163 drivers/media/usb/dvb-usb/af9005.c int af9005_write_ofdm_register(struct dvb_usb_device *d, u16 reg, u8 value) reg 167 drivers/media/usb/dvb-usb/af9005.c deb_reg("write register %x value %x ", reg, value); reg 168 drivers/media/usb/dvb-usb/af9005.c ret = af9005_generic_read_write(d, reg, reg 178 drivers/media/usb/dvb-usb/af9005.c int af9005_write_ofdm_registers(struct dvb_usb_device *d, u16 reg, reg 182 drivers/media/usb/dvb-usb/af9005.c deb_reg("write %d registers %x values ", len, reg); reg 185 drivers/media/usb/dvb-usb/af9005.c ret = af9005_generic_read_write(d, reg, reg 195 drivers/media/usb/dvb-usb/af9005.c int af9005_read_register_bits(struct dvb_usb_device *d, u16 reg, u8 pos, reg 200 drivers/media/usb/dvb-usb/af9005.c deb_reg("read bits %x %x %x", reg, pos, len); reg 201 drivers/media/usb/dvb-usb/af9005.c ret = af9005_read_ofdm_register(d, reg, &temp); reg 212 drivers/media/usb/dvb-usb/af9005.c int af9005_write_register_bits(struct dvb_usb_device *d, u16 reg, u8 pos, reg 217 drivers/media/usb/dvb-usb/af9005.c deb_reg("write bits %x %x %x value %x\n", reg, pos, len, value); reg 219 drivers/media/usb/dvb-usb/af9005.c return af9005_write_ofdm_register(d, reg, value); reg 220 drivers/media/usb/dvb-usb/af9005.c ret = af9005_read_ofdm_register(d, reg, &temp); reg 225 drivers/media/usb/dvb-usb/af9005.c return af9005_write_ofdm_register(d, reg, temp); reg 230 drivers/media/usb/dvb-usb/af9005.c u16 reg, u8 * values, int len) reg 232 drivers/media/usb/dvb-usb/af9005.c return af9005_generic_read_write(d, reg, reg 238 drivers/media/usb/dvb-usb/af9005.c u16 reg, u8 * values, int len) reg 240 drivers/media/usb/dvb-usb/af9005.c return af9005_generic_read_write(d, reg, reg 245 drivers/media/usb/dvb-usb/af9005.c int af9005_write_tuner_registers(struct dvb_usb_device *d, u16 reg, reg 253 drivers/media/usb/dvb-usb/af9005.c ret = af9005_usb_write_tuner_registers(d, reg, values, len); reg 256 drivers/media/usb/dvb-usb/af9005.c if (reg != 0xffff) { reg 298 drivers/media/usb/dvb-usb/af9005.c int af9005_read_tuner_registers(struct dvb_usb_device *d, u16 reg, u8 addr, reg 312 drivers/media/usb/dvb-usb/af9005.c if (reg == APO_REG_I2C_RW_SILICON_TUNER) { reg 320 drivers/media/usb/dvb-usb/af9005.c ret = af9005_usb_read_tuner_registers(d, reg, values, 1); reg 351 drivers/media/usb/dvb-usb/af9005.c static int af9005_i2c_write(struct dvb_usb_device *d, u8 i2caddr, u8 reg, reg 357 drivers/media/usb/dvb-usb/af9005.c reg, len); reg 362 drivers/media/usb/dvb-usb/af9005.c buf[1] = reg + (u8) i; reg 377 drivers/media/usb/dvb-usb/af9005.c static int af9005_i2c_read(struct dvb_usb_device *d, u8 i2caddr, u8 reg, reg 382 drivers/media/usb/dvb-usb/af9005.c deb_i2c("i2c_read i2caddr %x, reg %x, len %d\n ", i2caddr, reg, len); reg 384 drivers/media/usb/dvb-usb/af9005.c temp = reg + i; reg 407 drivers/media/usb/dvb-usb/af9005.c u8 reg, addr; reg 418 drivers/media/usb/dvb-usb/af9005.c reg = *msg[0].buf; reg 421 drivers/media/usb/dvb-usb/af9005.c ret = af9005_i2c_read(d, addr, reg, value, 1); reg 426 drivers/media/usb/dvb-usb/af9005.c reg = msg[0].buf[0]; reg 429 drivers/media/usb/dvb-usb/af9005.c ret = af9005_i2c_write(d, addr, reg, value, msg[0].len - 1); reg 3452 drivers/media/usb/dvb-usb/af9005.h extern int af9005_read_ofdm_register(struct dvb_usb_device *d, u16 reg, reg 3454 drivers/media/usb/dvb-usb/af9005.h extern int af9005_read_ofdm_registers(struct dvb_usb_device *d, u16 reg, reg 3456 drivers/media/usb/dvb-usb/af9005.h extern int af9005_write_ofdm_register(struct dvb_usb_device *d, u16 reg, reg 3458 drivers/media/usb/dvb-usb/af9005.h extern int af9005_write_ofdm_registers(struct dvb_usb_device *d, u16 reg, reg 3460 drivers/media/usb/dvb-usb/af9005.h extern int af9005_read_tuner_registers(struct dvb_usb_device *d, u16 reg, reg 3462 drivers/media/usb/dvb-usb/af9005.h extern int af9005_write_tuner_registers(struct dvb_usb_device *d, u16 reg, reg 3464 drivers/media/usb/dvb-usb/af9005.h extern int af9005_read_register_bits(struct dvb_usb_device *d, u16 reg, reg 3466 drivers/media/usb/dvb-usb/af9005.h extern int af9005_write_register_bits(struct dvb_usb_device *d, u16 reg, reg 390 drivers/media/usb/dvb-usb/technisat-usb2.c u8 reg; reg 396 drivers/media/usb/dvb-usb/technisat-usb2.c reg = j; reg 397 drivers/media/usb/dvb-usb/technisat-usb2.c if (technisat_usb2_i2c_access(d->udev, 0x50 + j / 256, ®, 1, b, 16) != 0) reg 400 drivers/media/usb/dvb-usb/technisat-usb2.c deb_eeprom("EEPROM: %01x%02x: ", j / 256, reg); reg 81 drivers/media/usb/dvb-usb/vp7045.c u8 vp7045_read_reg(struct dvb_usb_device *d, u8 reg) reg 84 drivers/media/usb/dvb-usb/vp7045.c obuf[1] = reg; reg 65 drivers/media/usb/dvb-usb/vp7045.h extern u8 vp7045_read_reg(struct dvb_usb_device *d, u8 reg); reg 181 drivers/media/usb/em28xx/em28xx-camera.c u8 reg; reg 193 drivers/media/usb/em28xx/em28xx-camera.c reg = 0x1c; reg 194 drivers/media/usb/em28xx/em28xx-camera.c ret = i2c_smbus_read_byte_data(client, reg); reg 203 drivers/media/usb/em28xx/em28xx-camera.c reg = 0x1d; reg 204 drivers/media/usb/em28xx/em28xx-camera.c ret = i2c_smbus_read_byte_data(client, reg); reg 216 drivers/media/usb/em28xx/em28xx-camera.c reg = 0x0a; reg 217 drivers/media/usb/em28xx/em28xx-camera.c ret = i2c_smbus_read_byte_data(client, reg); reg 225 drivers/media/usb/em28xx/em28xx-camera.c reg = 0x0b; reg 226 drivers/media/usb/em28xx/em28xx-camera.c ret = i2c_smbus_read_byte_data(client, reg); reg 76 drivers/media/usb/em28xx/em28xx-core.c int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg, reg 92 drivers/media/usb/em28xx/em28xx-core.c 0x0000, reg, dev->urb_buf, len, HZ); reg 98 drivers/media/usb/em28xx/em28xx-core.c reg & 0xff, reg >> 8, reg 112 drivers/media/usb/em28xx/em28xx-core.c reg & 0xff, reg >> 8, reg 122 drivers/media/usb/em28xx/em28xx-core.c int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg) reg 127 drivers/media/usb/em28xx/em28xx-core.c ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1); reg 134 drivers/media/usb/em28xx/em28xx-core.c int em28xx_read_reg(struct em28xx *dev, u16 reg) reg 136 drivers/media/usb/em28xx/em28xx-core.c return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg); reg 144 drivers/media/usb/em28xx/em28xx-core.c int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf, reg 161 drivers/media/usb/em28xx/em28xx-core.c 0x0000, reg, dev->urb_buf, len, HZ); reg 169 drivers/media/usb/em28xx/em28xx-core.c reg & 0xff, reg >> 8, reg 178 drivers/media/usb/em28xx/em28xx-core.c reg & 0xff, reg >> 8, reg 187 drivers/media/usb/em28xx/em28xx-core.c int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len) reg 189 drivers/media/usb/em28xx/em28xx-core.c return em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len); reg 194 drivers/media/usb/em28xx/em28xx-core.c int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val) reg 196 drivers/media/usb/em28xx/em28xx-core.c return em28xx_write_regs(dev, reg, &val, 1); reg 205 drivers/media/usb/em28xx/em28xx-core.c int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val, reg 211 drivers/media/usb/em28xx/em28xx-core.c oldval = em28xx_read_reg(dev, reg); reg 217 drivers/media/usb/em28xx/em28xx-core.c return em28xx_write_regs(dev, reg, &newval, 1); reg 225 drivers/media/usb/em28xx/em28xx-core.c int em28xx_toggle_reg_bits(struct em28xx *dev, u16 reg, u8 bitmask) reg 230 drivers/media/usb/em28xx/em28xx-core.c oldval = em28xx_read_reg(dev, reg); reg 236 drivers/media/usb/em28xx/em28xx-core.c return em28xx_write_reg(dev, reg, newval); reg 269 drivers/media/usb/em28xx/em28xx-core.c int em28xx_read_ac97(struct em28xx *dev, u8 reg) reg 272 drivers/media/usb/em28xx/em28xx-core.c u8 addr = (reg & 0x7f) | 0x80; reg 296 drivers/media/usb/em28xx/em28xx-core.c int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val) reg 299 drivers/media/usb/em28xx/em28xx-core.c u8 addr = reg & 0x7f; reg 322 drivers/media/usb/em28xx/em28xx-core.c u8 reg; reg 350 drivers/media/usb/em28xx/em28xx-core.c ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808); reg 352 drivers/media/usb/em28xx/em28xx-core.c ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000); reg 357 drivers/media/usb/em28xx/em28xx-core.c inputs[i].reg); reg 413 drivers/media/usb/em28xx/em28xx-core.c u8 reg; reg 439 drivers/media/usb/em28xx/em28xx-core.c ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000); reg 443 drivers/media/usb/em28xx/em28xx-core.c outputs[i].reg); reg 477 drivers/media/usb/em28xx/em28xx-core.c ret = em28xx_write_ac97(dev, outputs[i].reg, reg 482 drivers/media/usb/em28xx/em28xx-core.c outputs[i].reg); reg 731 drivers/media/usb/em28xx/em28xx-core.c if (gpio->reg >= 0) { reg 733 drivers/media/usb/em28xx/em28xx-core.c gpio->reg, reg 855 drivers/media/usb/em28xx/em28xx-dvb.c em28xx_write_reg_bits(dev, gpio[i].reg, gpio[i].val, reg 537 drivers/media/usb/em28xx/em28xx-i2c.c u8 reg; reg 554 drivers/media/usb/em28xx/em28xx-i2c.c reg = EM2874_I2C_SECONDARY_BUS_SELECT; reg 556 drivers/media/usb/em28xx/em28xx-i2c.c reg = 0; reg 557 drivers/media/usb/em28xx/em28xx-i2c.c em28xx_write_reg_bits(dev, EM28XX_R06_I2C_CLK, reg, reg 107 drivers/media/usb/em28xx/em28xx-video.c .reg = EM28XX_OUTFMT_YUV422_Y0UY1V, reg 111 drivers/media/usb/em28xx/em28xx-video.c .reg = EM28XX_OUTFMT_RGB_16_656, reg 115 drivers/media/usb/em28xx/em28xx-video.c .reg = EM28XX_OUTFMT_RGB_8_RGRG, reg 119 drivers/media/usb/em28xx/em28xx-video.c .reg = EM28XX_OUTFMT_RGB_8_BGBG, reg 123 drivers/media/usb/em28xx/em28xx-video.c .reg = EM28XX_OUTFMT_RGB_8_GRGR, reg 127 drivers/media/usb/em28xx/em28xx-video.c .reg = EM28XX_OUTFMT_RGB_8_GBGB, reg 131 drivers/media/usb/em28xx/em28xx-video.c .reg = EM28XX_OUTFMT_YUV411, reg 218 drivers/media/usb/em28xx/em28xx-video.c fmt = v4l2->format->reg; reg 1904 drivers/media/usb/em28xx/em28xx-video.c static int em28xx_reg_len(int reg) reg 1906 drivers/media/usb/em28xx/em28xx-video.c switch (reg) { reg 1917 drivers/media/usb/em28xx/em28xx-video.c struct v4l2_dbg_register *reg) reg 1922 drivers/media/usb/em28xx/em28xx-video.c if (reg->match.addr > 1) reg 1924 drivers/media/usb/em28xx/em28xx-video.c if (reg->match.addr) { reg 1925 drivers/media/usb/em28xx/em28xx-video.c ret = em28xx_read_ac97(dev, reg->reg); reg 1929 drivers/media/usb/em28xx/em28xx-video.c reg->val = ret; reg 1930 drivers/media/usb/em28xx/em28xx-video.c reg->size = 1; reg 1935 drivers/media/usb/em28xx/em28xx-video.c reg->size = em28xx_reg_len(reg->reg); reg 1936 drivers/media/usb/em28xx/em28xx-video.c if (reg->size == 1) { reg 1937 drivers/media/usb/em28xx/em28xx-video.c ret = em28xx_read_reg(dev, reg->reg); reg 1942 drivers/media/usb/em28xx/em28xx-video.c reg->val = ret; reg 1947 drivers/media/usb/em28xx/em28xx-video.c reg->reg, (char *)&val, 2); reg 1951 drivers/media/usb/em28xx/em28xx-video.c reg->val = le16_to_cpu(val); reg 1958 drivers/media/usb/em28xx/em28xx-video.c const struct v4l2_dbg_register *reg) reg 1963 drivers/media/usb/em28xx/em28xx-video.c if (reg->match.addr > 1) reg 1965 drivers/media/usb/em28xx/em28xx-video.c if (reg->match.addr) reg 1966 drivers/media/usb/em28xx/em28xx-video.c return em28xx_write_ac97(dev, reg->reg, reg->val); reg 1969 drivers/media/usb/em28xx/em28xx-video.c buf = cpu_to_le16(reg->val); reg 1971 drivers/media/usb/em28xx/em28xx-video.c return em28xx_write_regs(dev, reg->reg, (char *)&buf, reg 1972 drivers/media/usb/em28xx/em28xx-video.c em28xx_reg_len(reg->reg)); reg 261 drivers/media/usb/em28xx/em28xx.h int reg; reg 414 drivers/media/usb/em28xx/em28xx.h int reg; reg 753 drivers/media/usb/em28xx/em28xx.h int (*em28xx_write_regs)(struct em28xx *dev, u16 reg, reg 755 drivers/media/usb/em28xx/em28xx.h int (*em28xx_read_reg)(struct em28xx *dev, u16 reg); reg 756 drivers/media/usb/em28xx/em28xx.h int (*em28xx_read_reg_req_len)(struct em28xx *dev, u8 req, u16 reg, reg 758 drivers/media/usb/em28xx/em28xx.h int (*em28xx_write_regs_req)(struct em28xx *dev, u8 req, u16 reg, reg 760 drivers/media/usb/em28xx/em28xx.h int (*em28xx_read_reg_req)(struct em28xx *dev, u8 req, u16 reg); reg 803 drivers/media/usb/em28xx/em28xx.h int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg, reg 805 drivers/media/usb/em28xx/em28xx.h int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg); reg 806 drivers/media/usb/em28xx/em28xx.h int em28xx_read_reg(struct em28xx *dev, u16 reg); reg 807 drivers/media/usb/em28xx/em28xx.h int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf, reg 809 drivers/media/usb/em28xx/em28xx.h int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len); reg 810 drivers/media/usb/em28xx/em28xx.h int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val); reg 811 drivers/media/usb/em28xx/em28xx.h int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val, reg 813 drivers/media/usb/em28xx/em28xx.h int em28xx_toggle_reg_bits(struct em28xx *dev, u16 reg, u8 bitmask); reg 815 drivers/media/usb/em28xx/em28xx.h int em28xx_read_ac97(struct em28xx *dev, u8 reg); reg 816 drivers/media/usb/em28xx/em28xx.h int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val); reg 151 drivers/media/usb/go7007/s2250-board.c static int write_reg(struct i2c_client *client, u8 reg, u8 value) reg 176 drivers/media/usb/go7007/s2250-board.c (reg<<8 | value), reg 206 drivers/media/usb/gspca/etoms.c __u8 reg, reg 220 drivers/media/usb/gspca/etoms.c reg_w_val(gspca_dev, ET_I2C_REG, reg); reg 227 drivers/media/usb/gspca/etoms.c __u8 reg) reg 234 drivers/media/usb/gspca/etoms.c reg_w_val(gspca_dev, ET_I2C_REG, reg); /* set the register base */ reg 980 drivers/media/usb/gspca/gspca.c struct v4l2_dbg_register *reg) reg 985 drivers/media/usb/gspca/gspca.c return gspca_dev->sd_desc->get_register(gspca_dev, reg); reg 989 drivers/media/usb/gspca/gspca.c const struct v4l2_dbg_register *reg) reg 994 drivers/media/usb/gspca/gspca.c return gspca_dev->sd_desc->set_register(gspca_dev, reg); reg 103 drivers/media/usb/gspca/jl2005bcd.c static int jl2005c_read_reg(struct gspca_dev *gspca_dev, unsigned char reg) reg 109 drivers/media/usb/gspca/jl2005bcd.c instruction[1] = reg; reg 148 drivers/media/usb/gspca/jl2005bcd.c static int jl2005c_write_reg(struct gspca_dev *gspca_dev, unsigned char reg, reg 154 drivers/media/usb/gspca/jl2005bcd.c instruction[0] = reg; reg 198 drivers/media/usb/gspca/kinect.c static int write_register(struct gspca_dev *gspca_dev, uint16_t reg, reg 205 drivers/media/usb/gspca/kinect.c cmd[0] = cpu_to_le16(reg); reg 208 drivers/media/usb/gspca/kinect.c gspca_dbg(gspca_dev, D_USBO, "Write Reg 0x%04x <= 0x%02x\n", reg, data); reg 296 drivers/media/usb/gspca/m5602/m5602_s5k83a.c u8 reg, previous_rotation = 0; reg 304 drivers/media/usb/gspca/m5602/m5602_s5k83a.c s5k83a_get_rotation(sd, ®); reg 305 drivers/media/usb/gspca/m5602/m5602_s5k83a.c if (previous_rotation != reg) { reg 306 drivers/media/usb/gspca/m5602/m5602_s5k83a.c previous_rotation = reg; reg 312 drivers/media/usb/gspca/m5602/m5602_s5k83a.c if (reg) { reg 466 drivers/media/usb/gspca/m5602/m5602_s5k83a.c u8 reg; reg 471 drivers/media/usb/gspca/m5602/m5602_s5k83a.c err = s5k83a_get_rotation(sd, ®); reg 474 drivers/media/usb/gspca/m5602/m5602_s5k83a.c if (reg) { reg 86 drivers/media/usb/gspca/mr97310a.c u8 reg; reg 150 drivers/media/usb/gspca/mr97310a.c static int sensor_write_reg(struct gspca_dev *gspca_dev, u8 reg, u8 flags, reg 155 drivers/media/usb/gspca/mr97310a.c gspca_dev->usb_buf[2] = reg; reg 167 drivers/media/usb/gspca/mr97310a.c rc = sensor_write_reg(gspca_dev, data[i].reg, data[i].flags, reg 176 drivers/media/usb/gspca/mr97310a.c static int sensor_write1(struct gspca_dev *gspca_dev, u8 reg, u8 data) reg 184 drivers/media/usb/gspca/mr97310a.c rc = sensor_write_reg(gspca_dev, reg, 0x01, &buf, 1); reg 187 drivers/media/usb/gspca/mr97310a.c rc = sensor_write_reg(gspca_dev, reg, 0x00, &buf, 1); reg 201 drivers/media/usb/gspca/mr97310a.c static int cam_get_response16(struct gspca_dev *gspca_dev, u8 reg, int verbose) reg 205 drivers/media/usb/gspca/mr97310a.c gspca_dev->usb_buf[0] = reg; reg 216 drivers/media/usb/gspca/mr97310a.c reg, reg 1620 drivers/media/usb/gspca/nw80x.c u16 reg; reg 1624 drivers/media/usb/gspca/nw80x.c reg = *cmd++ << 8; reg 1625 drivers/media/usb/gspca/nw80x.c reg += *cmd++; reg 1630 drivers/media/usb/gspca/nw80x.c reg_w(gspca_dev, reg, cmd, len); reg 1632 drivers/media/usb/gspca/nw80x.c i2c_w(gspca_dev, reg, cmd, len); reg 582 drivers/media/usb/gspca/ov519.c u8 reg; reg 586 drivers/media/usb/gspca/ov519.c u8 reg; reg 2173 drivers/media/usb/gspca/ov519.c static void ov511_i2c_w(struct sd *sd, u8 reg, u8 value) reg 2178 drivers/media/usb/gspca/ov519.c gspca_dbg(gspca_dev, D_USBO, "ov511_i2c_w %02x %02x\n", reg, value); reg 2183 drivers/media/usb/gspca/ov519.c reg_w(sd, R51x_I2C_SADDR_3, reg); reg 2207 drivers/media/usb/gspca/ov519.c static int ov511_i2c_r(struct sd *sd, u8 reg) reg 2215 drivers/media/usb/gspca/ov519.c reg_w(sd, R51x_I2C_SADDR_2, reg); reg 2265 drivers/media/usb/gspca/ov519.c gspca_dbg(gspca_dev, D_USBI, "ov511_i2c_r %02x %02x\n", reg, value); reg 2279 drivers/media/usb/gspca/ov519.c u8 reg, reg 2284 drivers/media/usb/gspca/ov519.c gspca_dbg(gspca_dev, D_USBO, "ov518_i2c_w %02x %02x\n", reg, value); reg 2287 drivers/media/usb/gspca/ov519.c reg_w(sd, R51x_I2C_SADDR_3, reg); reg 2307 drivers/media/usb/gspca/ov519.c static int ov518_i2c_r(struct sd *sd, u8 reg) reg 2313 drivers/media/usb/gspca/ov519.c reg_w(sd, R51x_I2C_SADDR_2, reg); reg 2324 drivers/media/usb/gspca/ov519.c gspca_dbg(gspca_dev, D_USBI, "ov518_i2c_r %02x %02x\n", reg, value); reg 2328 drivers/media/usb/gspca/ov519.c static void ovfx2_i2c_w(struct sd *sd, u8 reg, u8 value) reg 2340 drivers/media/usb/gspca/ov519.c (u16) value, (u16) reg, NULL, 0, 500); reg 2343 drivers/media/usb/gspca/ov519.c gspca_err(gspca_dev, "ovfx2_i2c_w %02x failed %d\n", reg, ret); reg 2347 drivers/media/usb/gspca/ov519.c gspca_dbg(gspca_dev, D_USBO, "ovfx2_i2c_w %02x %02x\n", reg, value); reg 2350 drivers/media/usb/gspca/ov519.c static int ovfx2_i2c_r(struct sd *sd, u8 reg) reg 2362 drivers/media/usb/gspca/ov519.c 0, (u16) reg, sd->gspca_dev.usb_buf, 1, 500); reg 2367 drivers/media/usb/gspca/ov519.c reg, ret); reg 2369 drivers/media/usb/gspca/ov519.c gspca_err(gspca_dev, "ovfx2_i2c_r %02x failed %d\n", reg, ret); reg 2376 drivers/media/usb/gspca/ov519.c static void i2c_w(struct sd *sd, u8 reg, u8 value) reg 2378 drivers/media/usb/gspca/ov519.c if (sd->sensor_reg_cache[reg] == value) reg 2384 drivers/media/usb/gspca/ov519.c ov511_i2c_w(sd, reg, value); reg 2389 drivers/media/usb/gspca/ov519.c ov518_i2c_w(sd, reg, value); reg 2392 drivers/media/usb/gspca/ov519.c ovfx2_i2c_w(sd, reg, value); reg 2395 drivers/media/usb/gspca/ov519.c w9968cf_i2c_w(sd, reg, value); reg 2401 drivers/media/usb/gspca/ov519.c if (reg == 0x12 && (value & 0x80)) reg 2405 drivers/media/usb/gspca/ov519.c sd->sensor_reg_cache[reg] = value; reg 2409 drivers/media/usb/gspca/ov519.c static int i2c_r(struct sd *sd, u8 reg) reg 2413 drivers/media/usb/gspca/ov519.c if (sd->sensor_reg_cache[reg] != -1) reg 2414 drivers/media/usb/gspca/ov519.c return sd->sensor_reg_cache[reg]; reg 2419 drivers/media/usb/gspca/ov519.c ret = ov511_i2c_r(sd, reg); reg 2424 drivers/media/usb/gspca/ov519.c ret = ov518_i2c_r(sd, reg); reg 2427 drivers/media/usb/gspca/ov519.c ret = ovfx2_i2c_r(sd, reg); reg 2430 drivers/media/usb/gspca/ov519.c ret = w9968cf_i2c_r(sd, reg); reg 2435 drivers/media/usb/gspca/ov519.c sd->sensor_reg_cache[reg] = ret; reg 2446 drivers/media/usb/gspca/ov519.c u8 reg, reg 2454 drivers/media/usb/gspca/ov519.c rc = i2c_r(sd, reg); reg 2459 drivers/media/usb/gspca/ov519.c i2c_w(sd, reg, value); reg 2594 drivers/media/usb/gspca/ov519.c reg_w(sd, regvals->reg, regvals->val); reg 2604 drivers/media/usb/gspca/ov519.c i2c_w(sd, regvals->reg, regvals->val); reg 2915 drivers/media/usb/gspca/ov519.c int i, size, reg = R51x_COMP_LUT_BEGIN; reg 2935 drivers/media/usb/gspca/ov519.c reg_w(sd, reg, val0); reg 2942 drivers/media/usb/gspca/ov519.c reg_w(sd, reg + size, val0); reg 2944 drivers/media/usb/gspca/ov519.c reg++; reg 658 drivers/media/usb/gspca/ov534.c static void ov534_reg_write(struct gspca_dev *gspca_dev, u16 reg, u8 val) reg 666 drivers/media/usb/gspca/ov534.c gspca_dbg(gspca_dev, D_USBO, "SET 01 0000 %04x %02x\n", reg, val); reg 672 drivers/media/usb/gspca/ov534.c 0x00, reg, gspca_dev->usb_buf, 1, CTRL_TIMEOUT); reg 679 drivers/media/usb/gspca/ov534.c static u8 ov534_reg_read(struct gspca_dev *gspca_dev, u16 reg) reg 690 drivers/media/usb/gspca/ov534.c 0x00, reg, gspca_dev->usb_buf, 1, CTRL_TIMEOUT); reg 692 drivers/media/usb/gspca/ov534.c reg, gspca_dev->usb_buf[0]); reg 756 drivers/media/usb/gspca/ov534.c static void sccb_reg_write(struct gspca_dev *gspca_dev, u8 reg, u8 val) reg 758 drivers/media/usb/gspca/ov534.c gspca_dbg(gspca_dev, D_USBO, "sccb write: %02x %02x\n", reg, val); reg 759 drivers/media/usb/gspca/ov534.c ov534_reg_write(gspca_dev, OV534_REG_SUBADDR, reg); reg 769 drivers/media/usb/gspca/ov534.c static u8 sccb_reg_read(struct gspca_dev *gspca_dev, u16 reg) reg 771 drivers/media/usb/gspca/ov534.c ov534_reg_write(gspca_dev, OV534_REG_SUBADDR, reg); reg 1106 drivers/media/usb/gspca/ov534_9.c static void reg_w_i(struct gspca_dev *gspca_dev, u16 reg, u8 val) reg 1118 drivers/media/usb/gspca/ov534_9.c 0x00, reg, gspca_dev->usb_buf, 1, CTRL_TIMEOUT); reg 1125 drivers/media/usb/gspca/ov534_9.c static void reg_w(struct gspca_dev *gspca_dev, u16 reg, u8 val) reg 1127 drivers/media/usb/gspca/ov534_9.c gspca_dbg(gspca_dev, D_USBO, "reg_w [%04x] = %02x\n", reg, val); reg 1128 drivers/media/usb/gspca/ov534_9.c reg_w_i(gspca_dev, reg, val); reg 1131 drivers/media/usb/gspca/ov534_9.c static u8 reg_r(struct gspca_dev *gspca_dev, u16 reg) reg 1142 drivers/media/usb/gspca/ov534_9.c 0x00, reg, gspca_dev->usb_buf, 1, CTRL_TIMEOUT); reg 1144 drivers/media/usb/gspca/ov534_9.c reg, gspca_dev->usb_buf[0]); reg 1178 drivers/media/usb/gspca/ov534_9.c static void sccb_write(struct gspca_dev *gspca_dev, u8 reg, u8 val) reg 1180 drivers/media/usb/gspca/ov534_9.c gspca_dbg(gspca_dev, D_USBO, "sccb_write [%02x] = %02x\n", reg, val); reg 1181 drivers/media/usb/gspca/ov534_9.c reg_w_i(gspca_dev, OV534_REG_SUBADDR, reg); reg 1189 drivers/media/usb/gspca/ov534_9.c static u8 sccb_read(struct gspca_dev *gspca_dev, u16 reg) reg 1191 drivers/media/usb/gspca/ov534_9.c reg_w(gspca_dev, OV534_REG_SUBADDR, reg); reg 194 drivers/media/usb/gspca/pac207.c static void setcontrol(struct gspca_dev *gspca_dev, u16 reg, u16 val) reg 196 drivers/media/usb/gspca/pac207.c pac207_write_reg(gspca_dev, reg, val); reg 828 drivers/media/usb/gspca/pac7302.c const struct v4l2_dbg_register *reg) reg 837 drivers/media/usb/gspca/pac7302.c if (reg->match.addr == 0 && reg 838 drivers/media/usb/gspca/pac7302.c (reg->reg < 0x000000ff) && reg 839 drivers/media/usb/gspca/pac7302.c (reg->val <= 0x000000ff) reg 843 drivers/media/usb/gspca/pac7302.c index = reg->reg; reg 844 drivers/media/usb/gspca/pac7302.c value = reg->val; reg 108 drivers/media/usb/gspca/sn9c20x.c u8 reg; reg 113 drivers/media/usb/gspca/sn9c20x.c u8 reg; reg 901 drivers/media/usb/gspca/sn9c20x.c static void reg_r(struct gspca_dev *gspca_dev, u16 reg, u16 length) reg 911 drivers/media/usb/gspca/sn9c20x.c reg, reg 917 drivers/media/usb/gspca/sn9c20x.c pr_err("Read register %02x failed %d\n", reg, result); reg 927 drivers/media/usb/gspca/sn9c20x.c static void reg_w(struct gspca_dev *gspca_dev, u16 reg, reg 939 drivers/media/usb/gspca/sn9c20x.c reg, reg 945 drivers/media/usb/gspca/sn9c20x.c pr_err("Write register %02x failed %d\n", reg, result); reg 950 drivers/media/usb/gspca/sn9c20x.c static void reg_w1(struct gspca_dev *gspca_dev, u16 reg, const u8 value) reg 952 drivers/media/usb/gspca/sn9c20x.c reg_w(gspca_dev, reg, &value, 1); reg 977 drivers/media/usb/gspca/sn9c20x.c static void i2c_w1(struct gspca_dev *gspca_dev, u8 reg, u8 val) reg 988 drivers/media/usb/gspca/sn9c20x.c row[2] = reg; reg 1002 drivers/media/usb/gspca/sn9c20x.c i2c_w1(gspca_dev, buf->reg, buf->val); reg 1007 drivers/media/usb/gspca/sn9c20x.c static void i2c_w2(struct gspca_dev *gspca_dev, u8 reg, u16 val) reg 1018 drivers/media/usb/gspca/sn9c20x.c row[2] = reg; reg 1032 drivers/media/usb/gspca/sn9c20x.c i2c_w2(gspca_dev, buf->reg, buf->val); reg 1037 drivers/media/usb/gspca/sn9c20x.c static void i2c_r1(struct gspca_dev *gspca_dev, u8 reg, u8 *val) reg 1044 drivers/media/usb/gspca/sn9c20x.c row[2] = reg; reg 1058 drivers/media/usb/gspca/sn9c20x.c static void i2c_r2(struct gspca_dev *gspca_dev, u8 reg, u16 *val) reg 1065 drivers/media/usb/gspca/sn9c20x.c row[2] = reg; reg 1553 drivers/media/usb/gspca/sn9c20x.c struct v4l2_dbg_register *reg) reg 1557 drivers/media/usb/gspca/sn9c20x.c reg->size = 1; reg 1558 drivers/media/usb/gspca/sn9c20x.c switch (reg->match.addr) { reg 1560 drivers/media/usb/gspca/sn9c20x.c if (reg->reg < 0x1000 || reg->reg > 0x11ff) reg 1562 drivers/media/usb/gspca/sn9c20x.c reg_r(gspca_dev, reg->reg, 1); reg 1563 drivers/media/usb/gspca/sn9c20x.c reg->val = gspca_dev->usb_buf[0]; reg 1568 drivers/media/usb/gspca/sn9c20x.c i2c_r2(gspca_dev, reg->reg, (u16 *) ®->val); reg 1569 drivers/media/usb/gspca/sn9c20x.c reg->size = 2; reg 1571 drivers/media/usb/gspca/sn9c20x.c i2c_r1(gspca_dev, reg->reg, (u8 *) ®->val); reg 1579 drivers/media/usb/gspca/sn9c20x.c const struct v4l2_dbg_register *reg) reg 1583 drivers/media/usb/gspca/sn9c20x.c switch (reg->match.addr) { reg 1585 drivers/media/usb/gspca/sn9c20x.c if (reg->reg < 0x1000 || reg->reg > 0x11ff) reg 1587 drivers/media/usb/gspca/sn9c20x.c reg_w1(gspca_dev, reg->reg, reg->val); reg 1592 drivers/media/usb/gspca/sn9c20x.c i2c_w2(gspca_dev, reg->reg, reg->val); reg 1594 drivers/media/usb/gspca/sn9c20x.c i2c_w1(gspca_dev, reg->reg, reg->val); reg 687 drivers/media/usb/gspca/sonixb.c u16 reg = gspca_dev->exposure->val; reg 689 drivers/media/usb/gspca/sonixb.c i2c[3] = reg >> 8; reg 690 drivers/media/usb/gspca/sonixb.c i2c[4] = reg & 0xff; reg 699 drivers/media/usb/gspca/sonixb.c u8 reg = gspca_dev->exposure->val; reg 701 drivers/media/usb/gspca/sonixb.c reg = (reg << 4) | 0x0b; reg 702 drivers/media/usb/gspca/sonixb.c reg_w(gspca_dev, 0x19, ®, 1); reg 1228 drivers/media/usb/gspca/sonixj.c static void i2c_w1(struct gspca_dev *gspca_dev, u8 reg, u8 val) reg 1235 drivers/media/usb/gspca/sonixj.c gspca_dbg(gspca_dev, D_USBO, "i2c_w1 [%02x] = %02x\n", reg, val); reg 1247 drivers/media/usb/gspca/sonixj.c gspca_dev->usb_buf[2] = reg; reg 1294 drivers/media/usb/gspca/sonixj.c static void i2c_r(struct gspca_dev *gspca_dev, u8 reg, int len) reg 1310 drivers/media/usb/gspca/sonixj.c mode[2] = reg; reg 363 drivers/media/usb/gspca/spca500.c __u16 reg, __u16 index, __u16 value) reg 368 drivers/media/usb/gspca/spca500.c ret = reg_r_12(gspca_dev, reg, index, 1); reg 97 drivers/media/usb/gspca/spca506.c __u16 reg) reg 101 drivers/media/usb/gspca/spca506.c reg_w(gspca_dev->dev, 0x07, reg, 0x0001); reg 1274 drivers/media/usb/gspca/spca508.c u16 reg, u16 val) reg 1278 drivers/media/usb/gspca/spca508.c ret = reg_write(gspca_dev, 0x8802, reg >> 8); reg 1281 drivers/media/usb/gspca/spca508.c ret = reg_write(gspca_dev, 0x8801, reg & 0x00ff); reg 1284 drivers/media/usb/gspca/spca508.c if ((reg & 0xff00) == 0x1000) { /* if 2 bytes */ reg 326 drivers/media/usb/gspca/spca561.c static void i2c_write(struct gspca_dev *gspca_dev, __u16 value, __u16 reg) reg 330 drivers/media/usb/gspca/spca561.c reg_w_val(gspca_dev, 0x8801, reg); reg 341 drivers/media/usb/gspca/spca561.c static int i2c_read(struct gspca_dev *gspca_dev, __u16 reg, __u8 mode) reg 347 drivers/media/usb/gspca/spca561.c reg_w_val(gspca_dev, 0x8801, reg); reg 457 drivers/media/usb/gspca/spca561.c __u16 reg; reg 460 drivers/media/usb/gspca/spca561.c reg = 0x8610; reg 462 drivers/media/usb/gspca/spca561.c reg = 0x8611; reg 464 drivers/media/usb/gspca/spca561.c reg_w_val(gspca_dev, reg + 0, val); /* R */ reg 465 drivers/media/usb/gspca/spca561.c reg_w_val(gspca_dev, reg + 1, val); /* Gr */ reg 466 drivers/media/usb/gspca/spca561.c reg_w_val(gspca_dev, reg + 2, val); /* B */ reg 467 drivers/media/usb/gspca/spca561.c reg_w_val(gspca_dev, reg + 3, val); /* Gb */ reg 474 drivers/media/usb/gspca/spca561.c __u16 reg; reg 480 drivers/media/usb/gspca/spca561.c reg = 0x8614; reg 482 drivers/media/usb/gspca/spca561.c reg = 0x8651; reg 488 drivers/media/usb/gspca/spca561.c reg_w_val(gspca_dev, reg, red); reg 489 drivers/media/usb/gspca/spca561.c reg_w_val(gspca_dev, reg + 2, blue); reg 85 drivers/media/usb/gspca/sq930x.c u8 reg; reg 495 drivers/media/usb/gspca/sq930x.c idx = (cmd->val & 0xff00) | cmd->reg; reg 503 drivers/media/usb/gspca/sq930x.c *buf++ = cmd->reg; reg 177 drivers/media/usb/gspca/stk1135.c static u16 sensor_read(struct gspca_dev *gspca_dev, u16 reg) reg 179 drivers/media/usb/gspca/stk1135.c sensor_set_page(gspca_dev, reg >> 8); reg 180 drivers/media/usb/gspca/stk1135.c return sensor_read_16(gspca_dev, reg & 0xff); reg 183 drivers/media/usb/gspca/stk1135.c static void sensor_write(struct gspca_dev *gspca_dev, u16 reg, u16 val) reg 185 drivers/media/usb/gspca/stk1135.c sensor_set_page(gspca_dev, reg >> 8); reg 186 drivers/media/usb/gspca/stk1135.c sensor_write_16(gspca_dev, reg & 0xff, val); reg 190 drivers/media/usb/gspca/stk1135.c u16 reg, u16 val, u16 mask) reg 192 drivers/media/usb/gspca/stk1135.c val = (sensor_read(gspca_dev, reg) & ~mask) | (val & mask); reg 193 drivers/media/usb/gspca/stk1135.c sensor_write(gspca_dev, reg, val); reg 197 drivers/media/usb/gspca/stk1135.c u16 reg; reg 304 drivers/media/usb/gspca/stk1135.c sensor_write(gspca_dev, cfg[i].reg, cfg[i].val); reg 82 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c static int hdcs_reg_write_seq(struct sd *sd, u8 reg, u8 *vals, u8 len) reg 88 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c (reg + len > 0xff))) reg 92 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c regs[2 * i] = reg; reg 96 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c reg += 2; reg 522 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c u16 reg, val; reg 526 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c for (reg = HDCS_IDENT; reg <= HDCS_ROWEXPH; reg++) { reg 527 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c stv06xx_read_sensor(sd, reg, &val); reg 528 drivers/media/usb/gspca/stv06xx/stv06xx_hdcs.c pr_info("reg 0x%02x = 0x%02x\n", reg, val); reg 521 drivers/media/usb/gspca/sunplus.c u16 reg; reg 523 drivers/media/usb/gspca/sunplus.c reg = sd->bridge == BRIDGE_SPCA536 ? 0x20f0 : 0x21a7; reg 524 drivers/media/usb/gspca/sunplus.c reg_w_riv(gspca_dev, 0x00, reg, val); reg 530 drivers/media/usb/gspca/sunplus.c u16 reg; reg 532 drivers/media/usb/gspca/sunplus.c reg = sd->bridge == BRIDGE_SPCA536 ? 0x20f1 : 0x21a8; reg 533 drivers/media/usb/gspca/sunplus.c reg_w_riv(gspca_dev, 0x00, reg, val); reg 539 drivers/media/usb/gspca/sunplus.c u16 reg; reg 541 drivers/media/usb/gspca/sunplus.c reg = sd->bridge == BRIDGE_SPCA536 ? 0x20f6 : 0x21ae; reg 542 drivers/media/usb/gspca/sunplus.c reg_w_riv(gspca_dev, 0x00, reg, val); reg 348 drivers/media/usb/gspca/t613.c u8 reg, reg 365 drivers/media/usb/gspca/t613.c *p++ = reg++; reg 425 drivers/media/usb/gspca/topro.c u8 reg; reg 1014 drivers/media/usb/gspca/topro.c reg_w(gspca_dev, p->reg, p->val); reg 1041 drivers/media/usb/gspca/topro.c i2c_w(gspca_dev, p->reg, p->val); reg 3056 drivers/media/usb/gspca/vc032x.c u8 reg, const u8 *val, reg 3064 drivers/media/usb/gspca/vc032x.c gspca_dbg(gspca_dev, D_USBO, "i2c_w %02x %02x\n", reg, *val); reg 3067 drivers/media/usb/gspca/vc032x.c reg, *val, val[1]); reg 3071 drivers/media/usb/gspca/vc032x.c reg_w_i(gspca_dev, 0xa0, reg, 0xb33a); reg 249 drivers/media/usb/gspca/w996Xcf.c static void w9968cf_i2c_w(struct sd *sd, u8 reg, u8 value) reg 267 drivers/media/usb/gspca/w996Xcf.c data[0] = 0x8208 | ((reg & 0x80) ? 0x0015 : 0x0); reg 268 drivers/media/usb/gspca/w996Xcf.c data[0] |= (reg & 0x40) ? 0x0540 : 0x0; reg 269 drivers/media/usb/gspca/w996Xcf.c data[0] |= (reg & 0x20) ? 0x5000 : 0x0; reg 270 drivers/media/usb/gspca/w996Xcf.c data[1] = 0x0820 | ((reg & 0x20) ? 0x0001 : 0x0); reg 271 drivers/media/usb/gspca/w996Xcf.c data[1] |= (reg & 0x10) ? 0x0054 : 0x0; reg 272 drivers/media/usb/gspca/w996Xcf.c data[1] |= (reg & 0x08) ? 0x1500 : 0x0; reg 273 drivers/media/usb/gspca/w996Xcf.c data[1] |= (reg & 0x04) ? 0x4000 : 0x0; reg 274 drivers/media/usb/gspca/w996Xcf.c data[2] = 0x2082 | ((reg & 0x04) ? 0x0005 : 0x0); reg 275 drivers/media/usb/gspca/w996Xcf.c data[2] |= (reg & 0x02) ? 0x0150 : 0x0; reg 276 drivers/media/usb/gspca/w996Xcf.c data[2] |= (reg & 0x01) ? 0x5400 : 0x0; reg 295 drivers/media/usb/gspca/w996Xcf.c gspca_dbg(gspca_dev, D_USBO, "i2c 0x%02x -> [0x%02x]\n", value, reg); reg 299 drivers/media/usb/gspca/w996Xcf.c static int w9968cf_i2c_r(struct sd *sd, u8 reg) reg 311 drivers/media/usb/gspca/w996Xcf.c w9968cf_smbus_write_byte(sd, reg); reg 330 drivers/media/usb/gspca/w996Xcf.c reg, value); reg 332 drivers/media/usb/gspca/w996Xcf.c gspca_err(gspca_dev, "i2c read [0x%02x] failed\n", reg); reg 5572 drivers/media/usb/gspca/zc3xx.c u8 reg) reg 5579 drivers/media/usb/gspca/zc3xx.c reg_w(gspca_dev, reg, 0x0092); reg 5591 drivers/media/usb/gspca/zc3xx.c u8 reg, reg 5599 drivers/media/usb/gspca/zc3xx.c reg_w(gspca_dev, reg, 0x92); reg 3877 drivers/media/usb/pvrusb2/pvrusb2-hdw.c int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data) reg 3886 drivers/media/usb/pvrusb2/pvrusb2-hdw.c hdw->cmd_buffer[6] = (reg >> 8) & 0xff; reg 3887 drivers/media/usb/pvrusb2/pvrusb2-hdw.c hdw->cmd_buffer[7] = reg & 0xff; reg 3898 drivers/media/usb/pvrusb2/pvrusb2-hdw.c static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data) reg 3910 drivers/media/usb/pvrusb2/pvrusb2-hdw.c hdw->cmd_buffer[6] = (reg >> 8) & 0xff; reg 3911 drivers/media/usb/pvrusb2/pvrusb2-hdw.c hdw->cmd_buffer[7] = reg & 0xff; reg 40 drivers/media/usb/stk1160/stk1160-ac97.c static void stk1160_write_ac97(struct stk1160 *dev, u16 reg, u16 value) reg 43 drivers/media/usb/stk1160/stk1160-ac97.c stk1160_write_reg(dev, STK1160_AC97_ADDR, reg); reg 57 drivers/media/usb/stk1160/stk1160-ac97.c static u16 stk1160_read_ac97(struct stk1160 *dev, u16 reg) reg 63 drivers/media/usb/stk1160/stk1160-ac97.c stk1160_write_reg(dev, STK1160_AC97_ADDR, reg); reg 55 drivers/media/usb/stk1160/stk1160-core.c int stk1160_read_reg(struct stk1160 *dev, u16 reg, u8 *value) reg 68 drivers/media/usb/stk1160/stk1160-core.c 0x00, reg, buf, sizeof(u8), HZ); reg 71 drivers/media/usb/stk1160/stk1160-core.c reg, ret); reg 81 drivers/media/usb/stk1160/stk1160-core.c int stk1160_write_reg(struct stk1160 *dev, u16 reg, u16 value) reg 88 drivers/media/usb/stk1160/stk1160-core.c value, reg, NULL, 0, HZ); reg 91 drivers/media/usb/stk1160/stk1160-core.c reg, ret); reg 146 drivers/media/usb/stk1160/stk1160-core.c for (i = 0; ctl[i].reg != 0xffff; i++) reg 147 drivers/media/usb/stk1160/stk1160-core.c stk1160_write_reg(dev, ctl[i].reg, ctl[i].val); reg 54 drivers/media/usb/stk1160/stk1160-i2c.c u8 reg, u8 value) reg 64 drivers/media/usb/stk1160/stk1160-i2c.c rc = stk1160_write_reg(dev, STK1160_SBUSW_WA, reg); reg 86 drivers/media/usb/stk1160/stk1160-i2c.c u8 reg, u8 *value) reg 96 drivers/media/usb/stk1160/stk1160-i2c.c rc = stk1160_write_reg(dev, STK1160_SBUSR_RA, reg); reg 112 drivers/media/usb/stk1160/stk1160-v4l.c for (i = 0; std525[i].reg != 0xffff; i++) reg 113 drivers/media/usb/stk1160/stk1160-v4l.c stk1160_write_reg(dev, std525[i].reg, std525[i].val); reg 116 drivers/media/usb/stk1160/stk1160-v4l.c for (i = 0; std625[i].reg != 0xffff; i++) reg 117 drivers/media/usb/stk1160/stk1160-v4l.c stk1160_write_reg(dev, std625[i].reg, std625[i].val); reg 589 drivers/media/usb/stk1160/stk1160-v4l.c struct v4l2_dbg_register *reg) reg 596 drivers/media/usb/stk1160/stk1160-v4l.c rc = stk1160_read_reg(dev, reg->reg, &val); reg 597 drivers/media/usb/stk1160/stk1160-v4l.c reg->val = val; reg 598 drivers/media/usb/stk1160/stk1160-v4l.c reg->size = 1; reg 604 drivers/media/usb/stk1160/stk1160-v4l.c const struct v4l2_dbg_register *reg) reg 609 drivers/media/usb/stk1160/stk1160-v4l.c return stk1160_write_reg(dev, reg->reg, reg->val); reg 161 drivers/media/usb/stk1160/stk1160.h u16 reg; reg 182 drivers/media/usb/stk1160/stk1160.h int stk1160_read_reg(struct stk1160 *dev, u16 reg, u8 *value); reg 183 drivers/media/usb/stk1160/stk1160.h int stk1160_write_reg(struct stk1160 *dev, u16 reg, u16 value); reg 184 drivers/media/usb/stk1160/stk1160.h int stk1160_write_regs_req(struct stk1160 *dev, u8 req, u16 reg, reg 186 drivers/media/usb/stk1160/stk1160.h int stk1160_read_reg_req_len(struct stk1160 *dev, u8 req, u16 reg, reg 218 drivers/media/usb/stkwebcam/stk-sensor.c static int stk_sensor_outb(struct stk_camera *dev, u8 reg, u8 val) reg 223 drivers/media/usb/stkwebcam/stk-sensor.c if (stk_camera_write_reg(dev, STK_IIC_TX_INDEX, reg)) reg 243 drivers/media/usb/stkwebcam/stk-sensor.c static int stk_sensor_inb(struct stk_camera *dev, u8 reg, u8 *val) reg 248 drivers/media/usb/stkwebcam/stk-sensor.c if (stk_camera_write_reg(dev, STK_IIC_RX_INDEX, reg)) reg 277 drivers/media/usb/stkwebcam/stk-sensor.c while (rv->reg != 0xff || rv->val != 0xff) { reg 278 drivers/media/usb/stkwebcam/stk-sensor.c ret = stk_sensor_outb(dev, rv->reg, rv->val); reg 285 drivers/media/usb/stkwebcam/stk-webcam.c while (rv->reg != 0xffff) { reg 286 drivers/media/usb/stkwebcam/stk-webcam.c ret = stk_camera_write_reg(dev, rv->reg, rv->val); reg 71 drivers/media/usb/stkwebcam/stk-webcam.h unsigned reg; reg 397 drivers/media/usb/tm6000/tm6000-core.c u8 reg; reg 589 drivers/media/usb/tm6000/tm6000-core.c rc = tm6000_set_reg(dev, tab[i].req, tab[i].reg, tab[i].val); reg 593 drivers/media/usb/tm6000/tm6000-core.c tab[i].req, tab[i].reg, tab[i].val); reg 32 drivers/media/usb/tm6000/tm6000-i2c.c __u8 reg, char *buf, int len) reg 52 drivers/media/usb/tm6000/tm6000-i2c.c addr | reg << 8, 0, buf, len); reg 65 drivers/media/usb/tm6000/tm6000-i2c.c __u8 reg, char *buf, int len) reg 84 drivers/media/usb/tm6000/tm6000-i2c.c if ((dev->caps.has_zl10353) && (dev->demod_addr << 1 == addr) && (reg % 2 == 0)) { reg 88 drivers/media/usb/tm6000/tm6000-i2c.c reg -= 1; reg 92 drivers/media/usb/tm6000/tm6000-i2c.c REQ_16_SET_GET_I2C_WR1_RDN, addr | reg << 8, 0, b, len); reg 97 drivers/media/usb/tm6000/tm6000-i2c.c REQ_16_SET_GET_I2C_WR1_RDN, addr | reg << 8, 0, buf, len); reg 109 drivers/media/usb/tm6000/tm6000-i2c.c __u16 reg, char *buf, int len) reg 119 drivers/media/usb/tm6000/tm6000-i2c.c ureg = reg & 0xFF; reg 122 drivers/media/usb/tm6000/tm6000-i2c.c addr | (reg & 0xFF00), 0, &ureg, 1); reg 131 drivers/media/usb/tm6000/tm6000-i2c.c reg, 0, buf, len); reg 135 drivers/media/usb/tm6000/tm6000-i2c.c addr, reg, buf, len); reg 17 drivers/media/usb/tm6000/tm6000-stds.c unsigned char reg; reg 451 drivers/media/usb/tm6000/tm6000-stds.c rc = tm6000_set_reg(dev, set[i].req, set[i].reg, set[i].value); reg 454 drivers/media/usb/tm6000/tm6000-stds.c rc, set[i].req, set[i].reg, set[i].value); reg 1345 drivers/media/usb/usbvision/usbvision-core.c int usbvision_read_reg(struct usb_usbvision *usbvision, unsigned char reg) reg 1356 drivers/media/usb/usbvision/usbvision-core.c 0, (__u16) reg, buffer, 1, HZ); reg 1374 drivers/media/usb/usbvision/usbvision-core.c int usbvision_write_reg(struct usb_usbvision *usbvision, unsigned char reg, reg 1386 drivers/media/usb/usbvision/usbvision-core.c USB_RECIP_ENDPOINT, 0, (__u16) reg, reg 421 drivers/media/usb/usbvision/usbvision-video.c struct v4l2_dbg_register *reg) reg 427 drivers/media/usb/usbvision/usbvision-video.c err_code = usbvision_read_reg(usbvision, reg->reg&0xff); reg 434 drivers/media/usb/usbvision/usbvision-video.c reg->val = err_code; reg 435 drivers/media/usb/usbvision/usbvision-video.c reg->size = 1; reg 440 drivers/media/usb/usbvision/usbvision-video.c const struct v4l2_dbg_register *reg) reg 446 drivers/media/usb/usbvision/usbvision-video.c err_code = usbvision_write_reg(usbvision, reg->reg & 0xff, reg->val); reg 469 drivers/media/usb/usbvision/usbvision.h int usbvision_read_reg(struct usb_usbvision *usbvision, unsigned char reg); reg 470 drivers/media/usb/usbvision/usbvision.h int usbvision_write_reg(struct usb_usbvision *usbvision, unsigned char reg, reg 701 drivers/media/v4l2-core/v4l2-ioctl.c p->reg, p->val); reg 31 drivers/memory/da8xx-ddrctl.c u32 reg; reg 39 drivers/memory/da8xx-ddrctl.c .reg = 0x20, reg 109 drivers/memory/da8xx-ddrctl.c u32 reg; reg 135 drivers/memory/da8xx-ddrctl.c if (knob->reg + sizeof(u32) > resource_size(res)) { reg 142 drivers/memory/da8xx-ddrctl.c reg = readl(ddrctl + knob->reg); reg 143 drivers/memory/da8xx-ddrctl.c reg &= knob->mask; reg 144 drivers/memory/da8xx-ddrctl.c reg |= setting->val << knob->shift; reg 146 drivers/memory/da8xx-ddrctl.c dev_dbg(dev, "writing 0x%08x to %s\n", reg, setting->name); reg 148 drivers/memory/da8xx-ddrctl.c writel(reg, ddrctl + knob->reg); reg 162 drivers/memory/mtk-smi.c u32 reg; reg 169 drivers/memory/mtk-smi.c reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); reg 170 drivers/memory/mtk-smi.c reg |= F_MMU_EN; reg 171 drivers/memory/mtk-smi.c writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); reg 374 drivers/memory/omap-gpmc.c static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value) reg 378 drivers/memory/omap-gpmc.c l = gpmc_cs_read_reg(cs, reg); reg 383 drivers/memory/omap-gpmc.c gpmc_cs_write_reg(cs, reg, l); reg 430 drivers/memory/omap-gpmc.c int cs, int reg, int st_bit, int end_bit, int max, reg 442 drivers/memory/omap-gpmc.c l = gpmc_cs_read_reg(cs, reg); reg 476 drivers/memory/omap-gpmc.c #define GPMC_GET_RAW(reg, st, end, field) \ reg 477 drivers/memory/omap-gpmc.c get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0) reg 478 drivers/memory/omap-gpmc.c #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \ reg 479 drivers/memory/omap-gpmc.c get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0) reg 480 drivers/memory/omap-gpmc.c #define GPMC_GET_RAW_BOOL(reg, st, end, field) \ reg 481 drivers/memory/omap-gpmc.c get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1) reg 482 drivers/memory/omap-gpmc.c #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \ reg 483 drivers/memory/omap-gpmc.c get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1) reg 484 drivers/memory/omap-gpmc.c #define GPMC_GET_TICKS(reg, st, end, field) \ reg 485 drivers/memory/omap-gpmc.c get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0) reg 486 drivers/memory/omap-gpmc.c #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \ reg 487 drivers/memory/omap-gpmc.c get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0) reg 488 drivers/memory/omap-gpmc.c #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \ reg 489 drivers/memory/omap-gpmc.c get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0) reg 603 drivers/memory/omap-gpmc.c static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max, reg 626 drivers/memory/omap-gpmc.c l = gpmc_cs_read_reg(cs, reg); reg 635 drivers/memory/omap-gpmc.c gpmc_cs_write_reg(cs, reg, l); reg 640 drivers/memory/omap-gpmc.c #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd) \ reg 641 drivers/memory/omap-gpmc.c if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \ reg 645 drivers/memory/omap-gpmc.c #define GPMC_SET_ONE(reg, st, end, field) \ reg 646 drivers/memory/omap-gpmc.c GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK) reg 1096 drivers/memory/omap-gpmc.c struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs) reg 1103 drivers/memory/omap-gpmc.c reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + reg 1105 drivers/memory/omap-gpmc.c reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + reg 1107 drivers/memory/omap-gpmc.c reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + reg 1109 drivers/memory/omap-gpmc.c reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; reg 1110 drivers/memory/omap-gpmc.c reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; reg 1111 drivers/memory/omap-gpmc.c reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; reg 1112 drivers/memory/omap-gpmc.c reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; reg 1113 drivers/memory/omap-gpmc.c reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; reg 1114 drivers/memory/omap-gpmc.c reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; reg 1115 drivers/memory/omap-gpmc.c reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; reg 1116 drivers/memory/omap-gpmc.c reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; reg 1119 drivers/memory/omap-gpmc.c reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 + reg 1121 drivers/memory/omap-gpmc.c reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 + reg 1123 drivers/memory/omap-gpmc.c reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 + reg 1125 drivers/memory/omap-gpmc.c reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 + reg 1127 drivers/memory/omap-gpmc.c reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 + reg 1129 drivers/memory/omap-gpmc.c reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 + reg 1131 drivers/memory/omap-gpmc.c reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 + reg 2311 drivers/memory/omap-gpmc.c u32 reg; reg 2315 drivers/memory/omap-gpmc.c reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset); reg 2317 drivers/memory/omap-gpmc.c return !!reg; reg 168 drivers/memory/pl353-smc.c u32 addr, reg; reg 172 drivers/memory/pl353-smc.c reg = readl(pl353_smc_base + addr); reg 174 drivers/memory/pl353-smc.c return reg; reg 184 drivers/memory/pl353-smc.c u32 reg; reg 186 drivers/memory/pl353-smc.c reg = readl(pl353_smc_base + PL353_SMC_MEMC_STATUS_OFFS); reg 187 drivers/memory/pl353-smc.c reg >>= PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT; reg 188 drivers/memory/pl353-smc.c reg &= 1; reg 190 drivers/memory/pl353-smc.c return reg; reg 211 drivers/memory/pl353-smc.c u32 reg; reg 219 drivers/memory/pl353-smc.c reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS); reg 220 drivers/memory/pl353-smc.c reg &= ~PL353_SMC_ECC_MEMCFG_MODE_MASK; reg 221 drivers/memory/pl353-smc.c reg |= mode << PL353_SMC_ECC_MEMCFG_MODE_SHIFT; reg 222 drivers/memory/pl353-smc.c writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS); reg 240 drivers/memory/pl353-smc.c u32 reg, sz; reg 259 drivers/memory/pl353-smc.c reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS); reg 260 drivers/memory/pl353-smc.c reg &= ~PL353_SMC_ECC_MEMCFG_PGSIZE_MASK; reg 261 drivers/memory/pl353-smc.c reg |= sz; reg 262 drivers/memory/pl353-smc.c writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS); reg 298 drivers/memory/tegra/mc.c value = mc_readl(mc, la->reg); reg 301 drivers/memory/tegra/mc.c mc_writel(mc, value, la->reg); reg 567 drivers/memory/tegra/mc.c u32 value, reg; reg 572 drivers/memory/tegra/mc.c reg = MC_DECERR_EMEM_OTHERS_STATUS; reg 573 drivers/memory/tegra/mc.c value = mc_readl(mc, reg); reg 583 drivers/memory/tegra/mc.c reg = MC_GART_ERROR_REQ; reg 584 drivers/memory/tegra/mc.c value = mc_readl(mc, reg); reg 594 drivers/memory/tegra/mc.c reg = MC_SECURITY_VIOLATION_STATUS; reg 595 drivers/memory/tegra/mc.c value = mc_readl(mc, reg); reg 611 drivers/memory/tegra/mc.c addr = mc_readl(mc, reg + sizeof(u32)); reg 23 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 27 drivers/memory/tegra/tegra114.c .reg = 0x2e8, reg 37 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 41 drivers/memory/tegra/tegra114.c .reg = 0x2f4, reg 51 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 55 drivers/memory/tegra/tegra114.c .reg = 0x2e8, reg 65 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 69 drivers/memory/tegra/tegra114.c .reg = 0x2f4, reg 79 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 83 drivers/memory/tegra/tegra114.c .reg = 0x2ec, reg 93 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 97 drivers/memory/tegra/tegra114.c .reg = 0x2f8, reg 107 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 111 drivers/memory/tegra/tegra114.c .reg = 0x300, reg 121 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 125 drivers/memory/tegra/tegra114.c .reg = 0x308, reg 135 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 139 drivers/memory/tegra/tegra114.c .reg = 0x308, reg 149 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 153 drivers/memory/tegra/tegra114.c .reg = 0x2e4, reg 163 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 167 drivers/memory/tegra/tegra114.c .reg = 0x2f0, reg 177 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 181 drivers/memory/tegra/tegra114.c .reg = 0x2fc, reg 191 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 195 drivers/memory/tegra/tegra114.c .reg = 0x334, reg 205 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 209 drivers/memory/tegra/tegra114.c .reg = 0x33c, reg 219 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 223 drivers/memory/tegra/tegra114.c .reg = 0x30c, reg 233 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 237 drivers/memory/tegra/tegra114.c .reg = 0x318, reg 247 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 251 drivers/memory/tegra/tegra114.c .reg = 0x310, reg 261 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 265 drivers/memory/tegra/tegra114.c .reg = 0x310, reg 275 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 279 drivers/memory/tegra/tegra114.c .reg = 0x334, reg 289 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 293 drivers/memory/tegra/tegra114.c .reg = 0x328, reg 303 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 307 drivers/memory/tegra/tegra114.c .reg = 0x344, reg 317 drivers/memory/tegra/tegra114.c .reg = 0x228, reg 321 drivers/memory/tegra/tegra114.c .reg = 0x344, reg 331 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 335 drivers/memory/tegra/tegra114.c .reg = 0x338, reg 345 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 349 drivers/memory/tegra/tegra114.c .reg = 0x354, reg 359 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 363 drivers/memory/tegra/tegra114.c .reg = 0x354, reg 373 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 377 drivers/memory/tegra/tegra114.c .reg = 0x358, reg 387 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 391 drivers/memory/tegra/tegra114.c .reg = 0x358, reg 401 drivers/memory/tegra/tegra114.c .reg = 0x324, reg 411 drivers/memory/tegra/tegra114.c .reg = 0x320, reg 421 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 425 drivers/memory/tegra/tegra114.c .reg = 0x300, reg 435 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 439 drivers/memory/tegra/tegra114.c .reg = 0x304, reg 449 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 453 drivers/memory/tegra/tegra114.c .reg = 0x304, reg 463 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 467 drivers/memory/tegra/tegra114.c .reg = 0x328, reg 477 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 481 drivers/memory/tegra/tegra114.c .reg = 0x364, reg 491 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 495 drivers/memory/tegra/tegra114.c .reg = 0x368, reg 505 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 509 drivers/memory/tegra/tegra114.c .reg = 0x368, reg 519 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 523 drivers/memory/tegra/tegra114.c .reg = 0x36c, reg 533 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 537 drivers/memory/tegra/tegra114.c .reg = 0x30c, reg 547 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 551 drivers/memory/tegra/tegra114.c .reg = 0x2e4, reg 561 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 565 drivers/memory/tegra/tegra114.c .reg = 0x338, reg 575 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 579 drivers/memory/tegra/tegra114.c .reg = 0x340, reg 589 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 593 drivers/memory/tegra/tegra114.c .reg = 0x318, reg 603 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 607 drivers/memory/tegra/tegra114.c .reg = 0x314, reg 617 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 621 drivers/memory/tegra/tegra114.c .reg = 0x31c, reg 631 drivers/memory/tegra/tegra114.c .reg = 0x324, reg 641 drivers/memory/tegra/tegra114.c .reg = 0x320, reg 651 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 655 drivers/memory/tegra/tegra114.c .reg = 0x348, reg 665 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 669 drivers/memory/tegra/tegra114.c .reg = 0x348, reg 679 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 683 drivers/memory/tegra/tegra114.c .reg = 0x35c, reg 693 drivers/memory/tegra/tegra114.c .reg = 0x22c, reg 697 drivers/memory/tegra/tegra114.c .reg = 0x35c, reg 707 drivers/memory/tegra/tegra114.c .reg = 0x230, reg 711 drivers/memory/tegra/tegra114.c .reg = 0x360, reg 721 drivers/memory/tegra/tegra114.c .reg = 0x230, reg 725 drivers/memory/tegra/tegra114.c .reg = 0x360, reg 735 drivers/memory/tegra/tegra114.c .reg = 0x230, reg 739 drivers/memory/tegra/tegra114.c .reg = 0x37c, reg 749 drivers/memory/tegra/tegra114.c .reg = 0x230, reg 753 drivers/memory/tegra/tegra114.c .reg = 0x37c, reg 763 drivers/memory/tegra/tegra114.c .reg = 0x230, reg 767 drivers/memory/tegra/tegra114.c .reg = 0x380, reg 777 drivers/memory/tegra/tegra114.c .reg = 0x230, reg 781 drivers/memory/tegra/tegra114.c .reg = 0x380, reg 791 drivers/memory/tegra/tegra114.c .reg = 0x230, reg 795 drivers/memory/tegra/tegra114.c .reg = 0x388, reg 805 drivers/memory/tegra/tegra114.c .reg = 0x230, reg 809 drivers/memory/tegra/tegra114.c .reg = 0x384, reg 819 drivers/memory/tegra/tegra114.c .reg = 0x230, reg 823 drivers/memory/tegra/tegra114.c .reg = 0x388, reg 833 drivers/memory/tegra/tegra114.c .reg = 0x230, reg 837 drivers/memory/tegra/tegra114.c .reg = 0x384, reg 847 drivers/memory/tegra/tegra114.c .reg = 0x38c, reg 857 drivers/memory/tegra/tegra114.c .reg = 0x38c, reg 867 drivers/memory/tegra/tegra114.c .reg = 0x230, reg 871 drivers/memory/tegra/tegra114.c .reg = 0x390, reg 881 drivers/memory/tegra/tegra114.c .reg = 0x230, reg 885 drivers/memory/tegra/tegra114.c .reg = 0x390, reg 894 drivers/memory/tegra/tegra114.c { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 }, reg 895 drivers/memory/tegra/tegra114.c { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 }, reg 896 drivers/memory/tegra/tegra114.c { .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 }, reg 897 drivers/memory/tegra/tegra114.c { .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c }, reg 898 drivers/memory/tegra/tegra114.c { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c }, reg 899 drivers/memory/tegra/tegra114.c { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 }, reg 900 drivers/memory/tegra/tegra114.c { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 }, reg 901 drivers/memory/tegra/tegra114.c { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 }, reg 902 drivers/memory/tegra/tegra114.c { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 }, reg 903 drivers/memory/tegra/tegra114.c { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 }, reg 904 drivers/memory/tegra/tegra114.c { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c }, reg 905 drivers/memory/tegra/tegra114.c { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 }, reg 906 drivers/memory/tegra/tegra114.c { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 }, reg 907 drivers/memory/tegra/tegra114.c { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 }, reg 908 drivers/memory/tegra/tegra114.c { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c }, reg 909 drivers/memory/tegra/tegra114.c { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 }, reg 43 drivers/memory/tegra/tegra124.c .reg = 0x228, reg 47 drivers/memory/tegra/tegra124.c .reg = 0x2e8, reg 57 drivers/memory/tegra/tegra124.c .reg = 0x228, reg 61 drivers/memory/tegra/tegra124.c .reg = 0x2f4, reg 71 drivers/memory/tegra/tegra124.c .reg = 0x228, reg 75 drivers/memory/tegra/tegra124.c .reg = 0x2e8, reg 85 drivers/memory/tegra/tegra124.c .reg = 0x228, reg 89 drivers/memory/tegra/tegra124.c .reg = 0x2f4, reg 99 drivers/memory/tegra/tegra124.c .reg = 0x228, reg 103 drivers/memory/tegra/tegra124.c .reg = 0x2ec, reg 113 drivers/memory/tegra/tegra124.c .reg = 0x228, reg 117 drivers/memory/tegra/tegra124.c .reg = 0x2f8, reg 127 drivers/memory/tegra/tegra124.c .reg = 0x228, reg 131 drivers/memory/tegra/tegra124.c .reg = 0x2e0, reg 141 drivers/memory/tegra/tegra124.c .reg = 0x228, reg 145 drivers/memory/tegra/tegra124.c .reg = 0x2e4, reg 155 drivers/memory/tegra/tegra124.c .reg = 0x228, reg 159 drivers/memory/tegra/tegra124.c .reg = 0x2f0, reg 169 drivers/memory/tegra/tegra124.c .reg = 0x228, reg 173 drivers/memory/tegra/tegra124.c .reg = 0x2fc, reg 183 drivers/memory/tegra/tegra124.c .reg = 0x228, reg 187 drivers/memory/tegra/tegra124.c .reg = 0x318, reg 197 drivers/memory/tegra/tegra124.c .reg = 0x228, reg 201 drivers/memory/tegra/tegra124.c .reg = 0x310, reg 211 drivers/memory/tegra/tegra124.c .reg = 0x228, reg 215 drivers/memory/tegra/tegra124.c .reg = 0x310, reg 225 drivers/memory/tegra/tegra124.c .reg = 0x228, reg 229 drivers/memory/tegra/tegra124.c .reg = 0x328, reg 239 drivers/memory/tegra/tegra124.c .reg = 0x228, reg 243 drivers/memory/tegra/tegra124.c .reg = 0x344, reg 253 drivers/memory/tegra/tegra124.c .reg = 0x228, reg 257 drivers/memory/tegra/tegra124.c .reg = 0x344, reg 267 drivers/memory/tegra/tegra124.c .reg = 0x228, reg 271 drivers/memory/tegra/tegra124.c .reg = 0x350, reg 281 drivers/memory/tegra/tegra124.c .reg = 0x22c, reg 285 drivers/memory/tegra/tegra124.c .reg = 0x354, reg 295 drivers/memory/tegra/tegra124.c .reg = 0x22c, reg 299 drivers/memory/tegra/tegra124.c .reg = 0x354, reg 309 drivers/memory/tegra/tegra124.c .reg = 0x22c, reg 313 drivers/memory/tegra/tegra124.c .reg = 0x358, reg 323 drivers/memory/tegra/tegra124.c .reg = 0x22c, reg 327 drivers/memory/tegra/tegra124.c .reg = 0x358, reg 337 drivers/memory/tegra/tegra124.c .reg = 0x324, reg 347 drivers/memory/tegra/tegra124.c .reg = 0x320, reg 357 drivers/memory/tegra/tegra124.c .reg = 0x22c, reg 361 drivers/memory/tegra/tegra124.c .reg = 0x328, reg 371 drivers/memory/tegra/tegra124.c .reg = 0x22c, reg 375 drivers/memory/tegra/tegra124.c .reg = 0x2e0, reg 385 drivers/memory/tegra/tegra124.c .reg = 0x22c, reg 389 drivers/memory/tegra/tegra124.c .reg = 0x2e4, reg 399 drivers/memory/tegra/tegra124.c .reg = 0x22c, reg 403 drivers/memory/tegra/tegra124.c .reg = 0x318, reg 413 drivers/memory/tegra/tegra124.c .reg = 0x22c, reg 417 drivers/memory/tegra/tegra124.c .reg = 0x314, reg 427 drivers/memory/tegra/tegra124.c .reg = 0x324, reg 437 drivers/memory/tegra/tegra124.c .reg = 0x320, reg 447 drivers/memory/tegra/tegra124.c .reg = 0x22c, reg 451 drivers/memory/tegra/tegra124.c .reg = 0x348, reg 461 drivers/memory/tegra/tegra124.c .reg = 0x22c, reg 465 drivers/memory/tegra/tegra124.c .reg = 0x348, reg 475 drivers/memory/tegra/tegra124.c .reg = 0x22c, reg 479 drivers/memory/tegra/tegra124.c .reg = 0x350, reg 489 drivers/memory/tegra/tegra124.c .reg = 0x22c, reg 493 drivers/memory/tegra/tegra124.c .reg = 0x35c, reg 503 drivers/memory/tegra/tegra124.c .reg = 0x22c, reg 507 drivers/memory/tegra/tegra124.c .reg = 0x35c, reg 517 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 521 drivers/memory/tegra/tegra124.c .reg = 0x360, reg 531 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 535 drivers/memory/tegra/tegra124.c .reg = 0x360, reg 545 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 549 drivers/memory/tegra/tegra124.c .reg = 0x370, reg 559 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 563 drivers/memory/tegra/tegra124.c .reg = 0x374, reg 573 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 577 drivers/memory/tegra/tegra124.c .reg = 0x374, reg 587 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 591 drivers/memory/tegra/tegra124.c .reg = 0x37c, reg 601 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 605 drivers/memory/tegra/tegra124.c .reg = 0x37c, reg 615 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 619 drivers/memory/tegra/tegra124.c .reg = 0x380, reg 629 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 633 drivers/memory/tegra/tegra124.c .reg = 0x380, reg 643 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 647 drivers/memory/tegra/tegra124.c .reg = 0x384, reg 657 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 661 drivers/memory/tegra/tegra124.c .reg = 0x388, reg 671 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 675 drivers/memory/tegra/tegra124.c .reg = 0x388, reg 685 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 689 drivers/memory/tegra/tegra124.c .reg = 0x390, reg 699 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 703 drivers/memory/tegra/tegra124.c .reg = 0x390, reg 713 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 717 drivers/memory/tegra/tegra124.c .reg = 0x3a4, reg 727 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 731 drivers/memory/tegra/tegra124.c .reg = 0x3a4, reg 742 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 746 drivers/memory/tegra/tegra124.c .reg = 0x3c8, reg 757 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 761 drivers/memory/tegra/tegra124.c .reg = 0x3c8, reg 771 drivers/memory/tegra/tegra124.c .reg = 0x230, reg 775 drivers/memory/tegra/tegra124.c .reg = 0x2f0, reg 785 drivers/memory/tegra/tegra124.c .reg = 0x234, reg 789 drivers/memory/tegra/tegra124.c .reg = 0x3b8, reg 799 drivers/memory/tegra/tegra124.c .reg = 0x234, reg 803 drivers/memory/tegra/tegra124.c .reg = 0x3bc, reg 813 drivers/memory/tegra/tegra124.c .reg = 0x234, reg 817 drivers/memory/tegra/tegra124.c .reg = 0x3c0, reg 827 drivers/memory/tegra/tegra124.c .reg = 0x234, reg 831 drivers/memory/tegra/tegra124.c .reg = 0x3c4, reg 841 drivers/memory/tegra/tegra124.c .reg = 0x234, reg 845 drivers/memory/tegra/tegra124.c .reg = 0x3b8, reg 855 drivers/memory/tegra/tegra124.c .reg = 0x234, reg 859 drivers/memory/tegra/tegra124.c .reg = 0x3bc, reg 869 drivers/memory/tegra/tegra124.c .reg = 0x234, reg 873 drivers/memory/tegra/tegra124.c .reg = 0x3c0, reg 883 drivers/memory/tegra/tegra124.c .reg = 0x234, reg 887 drivers/memory/tegra/tegra124.c .reg = 0x3c4, reg 897 drivers/memory/tegra/tegra124.c .reg = 0x234, reg 901 drivers/memory/tegra/tegra124.c .reg = 0x394, reg 911 drivers/memory/tegra/tegra124.c .reg = 0x234, reg 915 drivers/memory/tegra/tegra124.c .reg = 0x394, reg 925 drivers/memory/tegra/tegra124.c .reg = 0x234, reg 929 drivers/memory/tegra/tegra124.c .reg = 0x398, reg 939 drivers/memory/tegra/tegra124.c .reg = 0x234, reg 943 drivers/memory/tegra/tegra124.c .reg = 0x3c8, reg 952 drivers/memory/tegra/tegra124.c { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 }, reg 953 drivers/memory/tegra/tegra124.c { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 }, reg 954 drivers/memory/tegra/tegra124.c { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 }, reg 955 drivers/memory/tegra/tegra124.c { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c }, reg 956 drivers/memory/tegra/tegra124.c { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 }, reg 957 drivers/memory/tegra/tegra124.c { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 }, reg 958 drivers/memory/tegra/tegra124.c { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 }, reg 959 drivers/memory/tegra/tegra124.c { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 }, reg 960 drivers/memory/tegra/tegra124.c { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 }, reg 961 drivers/memory/tegra/tegra124.c { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c }, reg 962 drivers/memory/tegra/tegra124.c { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 }, reg 963 drivers/memory/tegra/tegra124.c { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 }, reg 964 drivers/memory/tegra/tegra124.c { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c }, reg 965 drivers/memory/tegra/tegra124.c { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 }, reg 966 drivers/memory/tegra/tegra124.c { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 }, reg 967 drivers/memory/tegra/tegra124.c { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 }, reg 968 drivers/memory/tegra/tegra124.c { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac }, reg 969 drivers/memory/tegra/tegra124.c { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 }, reg 970 drivers/memory/tegra/tegra124.c { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 }, reg 971 drivers/memory/tegra/tegra124.c { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c }, reg 972 drivers/memory/tegra/tegra124.c { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 }, reg 973 drivers/memory/tegra/tegra124.c { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 }, reg 974 drivers/memory/tegra/tegra124.c { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 }, reg 20 drivers/memory/tegra/tegra210.c .reg = 0x228, reg 24 drivers/memory/tegra/tegra210.c .reg = 0x2e8, reg 34 drivers/memory/tegra/tegra210.c .reg = 0x228, reg 38 drivers/memory/tegra/tegra210.c .reg = 0x2f4, reg 48 drivers/memory/tegra/tegra210.c .reg = 0x228, reg 52 drivers/memory/tegra/tegra210.c .reg = 0x2e8, reg 62 drivers/memory/tegra/tegra210.c .reg = 0x228, reg 66 drivers/memory/tegra/tegra210.c .reg = 0x2f4, reg 76 drivers/memory/tegra/tegra210.c .reg = 0x228, reg 80 drivers/memory/tegra/tegra210.c .reg = 0x2ec, reg 90 drivers/memory/tegra/tegra210.c .reg = 0x228, reg 94 drivers/memory/tegra/tegra210.c .reg = 0x2f8, reg 104 drivers/memory/tegra/tegra210.c .reg = 0x228, reg 108 drivers/memory/tegra/tegra210.c .reg = 0x2e0, reg 118 drivers/memory/tegra/tegra210.c .reg = 0x228, reg 122 drivers/memory/tegra/tegra210.c .reg = 0x2e4, reg 132 drivers/memory/tegra/tegra210.c .reg = 0x228, reg 136 drivers/memory/tegra/tegra210.c .reg = 0x2f0, reg 146 drivers/memory/tegra/tegra210.c .reg = 0x228, reg 150 drivers/memory/tegra/tegra210.c .reg = 0x2fc, reg 160 drivers/memory/tegra/tegra210.c .reg = 0x228, reg 164 drivers/memory/tegra/tegra210.c .reg = 0x318, reg 174 drivers/memory/tegra/tegra210.c .reg = 0x228, reg 178 drivers/memory/tegra/tegra210.c .reg = 0x310, reg 188 drivers/memory/tegra/tegra210.c .reg = 0x228, reg 192 drivers/memory/tegra/tegra210.c .reg = 0x310, reg 202 drivers/memory/tegra/tegra210.c .reg = 0x228, reg 206 drivers/memory/tegra/tegra210.c .reg = 0x328, reg 216 drivers/memory/tegra/tegra210.c .reg = 0x228, reg 220 drivers/memory/tegra/tegra210.c .reg = 0x344, reg 230 drivers/memory/tegra/tegra210.c .reg = 0x228, reg 234 drivers/memory/tegra/tegra210.c .reg = 0x344, reg 244 drivers/memory/tegra/tegra210.c .reg = 0x228, reg 248 drivers/memory/tegra/tegra210.c .reg = 0x350, reg 258 drivers/memory/tegra/tegra210.c .reg = 0x320, reg 268 drivers/memory/tegra/tegra210.c .reg = 0x22c, reg 272 drivers/memory/tegra/tegra210.c .reg = 0x328, reg 282 drivers/memory/tegra/tegra210.c .reg = 0x22c, reg 286 drivers/memory/tegra/tegra210.c .reg = 0x2e0, reg 296 drivers/memory/tegra/tegra210.c .reg = 0x22c, reg 300 drivers/memory/tegra/tegra210.c .reg = 0x2e4, reg 310 drivers/memory/tegra/tegra210.c .reg = 0x22c, reg 314 drivers/memory/tegra/tegra210.c .reg = 0x318, reg 324 drivers/memory/tegra/tegra210.c .reg = 0x22c, reg 328 drivers/memory/tegra/tegra210.c .reg = 0x314, reg 338 drivers/memory/tegra/tegra210.c .reg = 0x320, reg 348 drivers/memory/tegra/tegra210.c .reg = 0x22c, reg 352 drivers/memory/tegra/tegra210.c .reg = 0x348, reg 362 drivers/memory/tegra/tegra210.c .reg = 0x22c, reg 366 drivers/memory/tegra/tegra210.c .reg = 0x348, reg 376 drivers/memory/tegra/tegra210.c .reg = 0x22c, reg 380 drivers/memory/tegra/tegra210.c .reg = 0x350, reg 390 drivers/memory/tegra/tegra210.c .reg = 0x230, reg 394 drivers/memory/tegra/tegra210.c .reg = 0x370, reg 404 drivers/memory/tegra/tegra210.c .reg = 0x230, reg 408 drivers/memory/tegra/tegra210.c .reg = 0x374, reg 418 drivers/memory/tegra/tegra210.c .reg = 0x230, reg 422 drivers/memory/tegra/tegra210.c .reg = 0x374, reg 432 drivers/memory/tegra/tegra210.c .reg = 0x230, reg 436 drivers/memory/tegra/tegra210.c .reg = 0x37c, reg 446 drivers/memory/tegra/tegra210.c .reg = 0x230, reg 450 drivers/memory/tegra/tegra210.c .reg = 0x37c, reg 460 drivers/memory/tegra/tegra210.c .reg = 0x230, reg 464 drivers/memory/tegra/tegra210.c .reg = 0x380, reg 474 drivers/memory/tegra/tegra210.c .reg = 0x230, reg 478 drivers/memory/tegra/tegra210.c .reg = 0x380, reg 488 drivers/memory/tegra/tegra210.c .reg = 0x230, reg 492 drivers/memory/tegra/tegra210.c .reg = 0x384, reg 502 drivers/memory/tegra/tegra210.c .reg = 0x230, reg 506 drivers/memory/tegra/tegra210.c .reg = 0x388, reg 516 drivers/memory/tegra/tegra210.c .reg = 0x230, reg 520 drivers/memory/tegra/tegra210.c .reg = 0x388, reg 530 drivers/memory/tegra/tegra210.c .reg = 0x230, reg 534 drivers/memory/tegra/tegra210.c .reg = 0x390, reg 544 drivers/memory/tegra/tegra210.c .reg = 0x230, reg 548 drivers/memory/tegra/tegra210.c .reg = 0x390, reg 558 drivers/memory/tegra/tegra210.c .reg = 0x230, reg 562 drivers/memory/tegra/tegra210.c .reg = 0x3a4, reg 572 drivers/memory/tegra/tegra210.c .reg = 0x230, reg 576 drivers/memory/tegra/tegra210.c .reg = 0x3a4, reg 587 drivers/memory/tegra/tegra210.c .reg = 0x230, reg 591 drivers/memory/tegra/tegra210.c .reg = 0x3c8, reg 602 drivers/memory/tegra/tegra210.c .reg = 0x230, reg 606 drivers/memory/tegra/tegra210.c .reg = 0x3c8, reg 616 drivers/memory/tegra/tegra210.c .reg = 0x230, reg 620 drivers/memory/tegra/tegra210.c .reg = 0x2f0, reg 630 drivers/memory/tegra/tegra210.c .reg = 0x234, reg 634 drivers/memory/tegra/tegra210.c .reg = 0x3b8, reg 644 drivers/memory/tegra/tegra210.c .reg = 0x234, reg 648 drivers/memory/tegra/tegra210.c .reg = 0x3bc, reg 658 drivers/memory/tegra/tegra210.c .reg = 0x234, reg 662 drivers/memory/tegra/tegra210.c .reg = 0x3c0, reg 672 drivers/memory/tegra/tegra210.c .reg = 0x234, reg 676 drivers/memory/tegra/tegra210.c .reg = 0x3c4, reg 686 drivers/memory/tegra/tegra210.c .reg = 0x234, reg 690 drivers/memory/tegra/tegra210.c .reg = 0x3b8, reg 700 drivers/memory/tegra/tegra210.c .reg = 0x234, reg 704 drivers/memory/tegra/tegra210.c .reg = 0x3bc, reg 714 drivers/memory/tegra/tegra210.c .reg = 0x234, reg 718 drivers/memory/tegra/tegra210.c .reg = 0x3c0, reg 728 drivers/memory/tegra/tegra210.c .reg = 0x234, reg 732 drivers/memory/tegra/tegra210.c .reg = 0x3c4, reg 742 drivers/memory/tegra/tegra210.c .reg = 0x234, reg 746 drivers/memory/tegra/tegra210.c .reg = 0x394, reg 756 drivers/memory/tegra/tegra210.c .reg = 0x234, reg 760 drivers/memory/tegra/tegra210.c .reg = 0x394, reg 770 drivers/memory/tegra/tegra210.c .reg = 0x234, reg 774 drivers/memory/tegra/tegra210.c .reg = 0x398, reg 784 drivers/memory/tegra/tegra210.c .reg = 0x234, reg 788 drivers/memory/tegra/tegra210.c .reg = 0x3c8, reg 798 drivers/memory/tegra/tegra210.c .reg = 0x234, reg 802 drivers/memory/tegra/tegra210.c .reg = 0x3d8, reg 812 drivers/memory/tegra/tegra210.c .reg = 0x234, reg 816 drivers/memory/tegra/tegra210.c .reg = 0x3d8, reg 826 drivers/memory/tegra/tegra210.c .reg = 0x234, reg 830 drivers/memory/tegra/tegra210.c .reg = 0x3dc, reg 840 drivers/memory/tegra/tegra210.c .reg = 0x234, reg 844 drivers/memory/tegra/tegra210.c .reg = 0x3dc, reg 854 drivers/memory/tegra/tegra210.c .reg = 0x234, reg 858 drivers/memory/tegra/tegra210.c .reg = 0x3e4, reg 868 drivers/memory/tegra/tegra210.c .reg = 0x234, reg 872 drivers/memory/tegra/tegra210.c .reg = 0x3e4, reg 882 drivers/memory/tegra/tegra210.c .reg = 0xb98, reg 886 drivers/memory/tegra/tegra210.c .reg = 0x3e0, reg 896 drivers/memory/tegra/tegra210.c .reg = 0xb98, reg 900 drivers/memory/tegra/tegra210.c .reg = 0xb98, reg 910 drivers/memory/tegra/tegra210.c .reg = 0xb98, reg 914 drivers/memory/tegra/tegra210.c .reg = 0x3a0, reg 924 drivers/memory/tegra/tegra210.c .reg = 0xb98, reg 928 drivers/memory/tegra/tegra210.c .reg = 0x3a0, reg 938 drivers/memory/tegra/tegra210.c .reg = 0xb98, reg 942 drivers/memory/tegra/tegra210.c .reg = 0x3ec, reg 952 drivers/memory/tegra/tegra210.c .reg = 0xb98, reg 956 drivers/memory/tegra/tegra210.c .reg = 0x3ec, reg 966 drivers/memory/tegra/tegra210.c .reg = 0xb98, reg 970 drivers/memory/tegra/tegra210.c .reg = 0x3f0, reg 980 drivers/memory/tegra/tegra210.c .reg = 0xb98, reg 984 drivers/memory/tegra/tegra210.c .reg = 0x3f0, reg 995 drivers/memory/tegra/tegra210.c .reg = 0xb98, reg 999 drivers/memory/tegra/tegra210.c .reg = 0x3e8, reg 1010 drivers/memory/tegra/tegra210.c .reg = 0xb98, reg 1014 drivers/memory/tegra/tegra210.c .reg = 0x3e8, reg 1023 drivers/memory/tegra/tegra210.c { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 }, reg 1024 drivers/memory/tegra/tegra210.c { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 }, reg 1025 drivers/memory/tegra/tegra210.c { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 }, reg 1026 drivers/memory/tegra/tegra210.c { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c }, reg 1027 drivers/memory/tegra/tegra210.c { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 }, reg 1028 drivers/memory/tegra/tegra210.c { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 }, reg 1029 drivers/memory/tegra/tegra210.c { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 }, reg 1030 drivers/memory/tegra/tegra210.c { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 }, reg 1031 drivers/memory/tegra/tegra210.c { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 }, reg 1032 drivers/memory/tegra/tegra210.c { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 }, reg 1033 drivers/memory/tegra/tegra210.c { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 }, reg 1034 drivers/memory/tegra/tegra210.c { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c }, reg 1035 drivers/memory/tegra/tegra210.c { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 }, reg 1036 drivers/memory/tegra/tegra210.c { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 }, reg 1037 drivers/memory/tegra/tegra210.c { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 }, reg 1038 drivers/memory/tegra/tegra210.c { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac }, reg 1039 drivers/memory/tegra/tegra210.c { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 }, reg 1040 drivers/memory/tegra/tegra210.c { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 }, reg 1041 drivers/memory/tegra/tegra210.c { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c }, reg 1042 drivers/memory/tegra/tegra210.c { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 }, reg 1043 drivers/memory/tegra/tegra210.c { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 }, reg 1044 drivers/memory/tegra/tegra210.c { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 }, reg 1045 drivers/memory/tegra/tegra210.c { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 }, reg 1046 drivers/memory/tegra/tegra210.c { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 }, reg 1047 drivers/memory/tegra/tegra210.c { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 }, reg 1048 drivers/memory/tegra/tegra210.c { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc }, reg 1049 drivers/memory/tegra/tegra210.c { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc }, reg 1050 drivers/memory/tegra/tegra210.c { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 }, reg 1051 drivers/memory/tegra/tegra210.c { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 }, reg 23 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 27 drivers/memory/tegra/tegra30.c .reg = 0x2e8, reg 37 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 41 drivers/memory/tegra/tegra30.c .reg = 0x2f4, reg 51 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 55 drivers/memory/tegra/tegra30.c .reg = 0x2e8, reg 65 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 69 drivers/memory/tegra/tegra30.c .reg = 0x2f4, reg 79 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 83 drivers/memory/tegra/tegra30.c .reg = 0x2ec, reg 93 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 97 drivers/memory/tegra/tegra30.c .reg = 0x2f8, reg 107 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 111 drivers/memory/tegra/tegra30.c .reg = 0x2ec, reg 121 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 125 drivers/memory/tegra/tegra30.c .reg = 0x2f8, reg 135 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 139 drivers/memory/tegra/tegra30.c .reg = 0x300, reg 149 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 153 drivers/memory/tegra/tegra30.c .reg = 0x308, reg 163 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 167 drivers/memory/tegra/tegra30.c .reg = 0x308, reg 177 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 181 drivers/memory/tegra/tegra30.c .reg = 0x328, reg 191 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 195 drivers/memory/tegra/tegra30.c .reg = 0x364, reg 205 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 209 drivers/memory/tegra/tegra30.c .reg = 0x2e0, reg 219 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 223 drivers/memory/tegra/tegra30.c .reg = 0x2e4, reg 233 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 237 drivers/memory/tegra/tegra30.c .reg = 0x2f0, reg 247 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 251 drivers/memory/tegra/tegra30.c .reg = 0x2fc, reg 261 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 265 drivers/memory/tegra/tegra30.c .reg = 0x334, reg 275 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 279 drivers/memory/tegra/tegra30.c .reg = 0x33c, reg 289 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 293 drivers/memory/tegra/tegra30.c .reg = 0x30c, reg 303 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 307 drivers/memory/tegra/tegra30.c .reg = 0x318, reg 317 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 321 drivers/memory/tegra/tegra30.c .reg = 0x310, reg 331 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 335 drivers/memory/tegra/tegra30.c .reg = 0x310, reg 345 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 349 drivers/memory/tegra/tegra30.c .reg = 0x334, reg 359 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 363 drivers/memory/tegra/tegra30.c .reg = 0x33c, reg 373 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 377 drivers/memory/tegra/tegra30.c .reg = 0x328, reg 387 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 391 drivers/memory/tegra/tegra30.c .reg = 0x32c, reg 401 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 405 drivers/memory/tegra/tegra30.c .reg = 0x32c, reg 415 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 419 drivers/memory/tegra/tegra30.c .reg = 0x344, reg 429 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 433 drivers/memory/tegra/tegra30.c .reg = 0x344, reg 443 drivers/memory/tegra/tegra30.c .reg = 0x228, reg 447 drivers/memory/tegra/tegra30.c .reg = 0x350, reg 457 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 461 drivers/memory/tegra/tegra30.c .reg = 0x338, reg 471 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 475 drivers/memory/tegra/tegra30.c .reg = 0x340, reg 485 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 489 drivers/memory/tegra/tegra30.c .reg = 0x354, reg 499 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 503 drivers/memory/tegra/tegra30.c .reg = 0x354, reg 513 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 517 drivers/memory/tegra/tegra30.c .reg = 0x358, reg 527 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 531 drivers/memory/tegra/tegra30.c .reg = 0x358, reg 541 drivers/memory/tegra/tegra30.c .reg = 0x324, reg 551 drivers/memory/tegra/tegra30.c .reg = 0x320, reg 561 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 565 drivers/memory/tegra/tegra30.c .reg = 0x300, reg 575 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 579 drivers/memory/tegra/tegra30.c .reg = 0x304, reg 589 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 593 drivers/memory/tegra/tegra30.c .reg = 0x304, reg 603 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 607 drivers/memory/tegra/tegra30.c .reg = 0x330, reg 617 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 621 drivers/memory/tegra/tegra30.c .reg = 0x364, reg 631 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 635 drivers/memory/tegra/tegra30.c .reg = 0x368, reg 645 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 649 drivers/memory/tegra/tegra30.c .reg = 0x368, reg 659 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 663 drivers/memory/tegra/tegra30.c .reg = 0x36c, reg 673 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 677 drivers/memory/tegra/tegra30.c .reg = 0x30c, reg 687 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 691 drivers/memory/tegra/tegra30.c .reg = 0x2e0, reg 701 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 705 drivers/memory/tegra/tegra30.c .reg = 0x2e4, reg 715 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 719 drivers/memory/tegra/tegra30.c .reg = 0x338, reg 729 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 733 drivers/memory/tegra/tegra30.c .reg = 0x340, reg 743 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 747 drivers/memory/tegra/tegra30.c .reg = 0x318, reg 757 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 761 drivers/memory/tegra/tegra30.c .reg = 0x314, reg 771 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 775 drivers/memory/tegra/tegra30.c .reg = 0x31c, reg 785 drivers/memory/tegra/tegra30.c .reg = 0x324, reg 795 drivers/memory/tegra/tegra30.c .reg = 0x320, reg 805 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 809 drivers/memory/tegra/tegra30.c .reg = 0x330, reg 819 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 823 drivers/memory/tegra/tegra30.c .reg = 0x348, reg 833 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 837 drivers/memory/tegra/tegra30.c .reg = 0x348, reg 847 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 851 drivers/memory/tegra/tegra30.c .reg = 0x350, reg 861 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 865 drivers/memory/tegra/tegra30.c .reg = 0x35c, reg 875 drivers/memory/tegra/tegra30.c .reg = 0x22c, reg 879 drivers/memory/tegra/tegra30.c .reg = 0x35c, reg 889 drivers/memory/tegra/tegra30.c .reg = 0x230, reg 893 drivers/memory/tegra/tegra30.c .reg = 0x360, reg 903 drivers/memory/tegra/tegra30.c .reg = 0x230, reg 907 drivers/memory/tegra/tegra30.c .reg = 0x360, reg 916 drivers/memory/tegra/tegra30.c { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 }, reg 917 drivers/memory/tegra/tegra30.c { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 }, reg 918 drivers/memory/tegra/tegra30.c { .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 }, reg 919 drivers/memory/tegra/tegra30.c { .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c }, reg 920 drivers/memory/tegra/tegra30.c { .name = "mpe", .swgroup = TEGRA_SWGROUP_MPE, .reg = 0x264 }, reg 921 drivers/memory/tegra/tegra30.c { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 }, reg 922 drivers/memory/tegra/tegra30.c { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 }, reg 923 drivers/memory/tegra/tegra30.c { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c }, reg 924 drivers/memory/tegra/tegra30.c { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 }, reg 925 drivers/memory/tegra/tegra30.c { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c }, reg 926 drivers/memory/tegra/tegra30.c { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 }, reg 927 drivers/memory/tegra/tegra30.c { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 }, reg 928 drivers/memory/tegra/tegra30.c { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 }, reg 929 drivers/memory/tegra/tegra30.c { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 }, reg 930 drivers/memory/tegra/tegra30.c { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c }, reg 931 drivers/memory/tegra/tegra30.c { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 }, reg 90 drivers/memstick/host/r592.c u32 reg = readl(dev->mmio + address); reg 91 drivers/memstick/host/r592.c dbg_reg("reg #%02d |= 0x%08x (old =0x%08x)", address, mask, reg); reg 92 drivers/memstick/host/r592.c writel(reg | mask , dev->mmio + address); reg 99 drivers/memstick/host/r592.c u32 reg = readl(dev->mmio + address); reg 101 drivers/memstick/host/r592.c address, ~mask, reg, mask); reg 102 drivers/memstick/host/r592.c writel(reg & ~mask, dev->mmio + address); reg 110 drivers/memstick/host/r592.c u32 reg = r592_read_reg(dev, R592_STATUS); reg 112 drivers/memstick/host/r592.c if ((reg & mask) == wanted_mask) reg 117 drivers/memstick/host/r592.c reg = r592_read_reg(dev, R592_STATUS); reg 119 drivers/memstick/host/r592.c if ((reg & mask) == wanted_mask) reg 122 drivers/memstick/host/r592.c if (reg & (R592_STATUS_SEND_ERR | R592_STATUS_RECV_ERR)) reg 228 drivers/memstick/host/r592.c u32 reg; reg 239 drivers/memstick/host/r592.c reg = r592_read_reg(dev, R592_FIFO_DMA_SETTINGS); reg 240 drivers/memstick/host/r592.c reg |= R592_FIFO_DMA_SETTINGS_EN; reg 243 drivers/memstick/host/r592.c reg |= R592_FIFO_DMA_SETTINGS_DIR; reg 245 drivers/memstick/host/r592.c reg &= ~R592_FIFO_DMA_SETTINGS_DIR; reg 246 drivers/memstick/host/r592.c r592_write_reg(dev, R592_FIFO_DMA_SETTINGS, reg); reg 457 drivers/memstick/host/r592.c u32 status, reg; reg 506 drivers/memstick/host/r592.c reg = (len << R592_TPC_EXEC_LEN_SHIFT) | reg 510 drivers/memstick/host/r592.c r592_write_reg(dev, R592_TPC_EXEC, reg); reg 599 drivers/memstick/host/r592.c u32 reg = r592_read_reg(dev, R592_REG_MSC); reg 600 drivers/memstick/host/r592.c bool card_detected = reg & R592_REG_MSC_PRSNT; reg 605 drivers/memstick/host/r592.c reg &= ~((R592_REG_MSC_IRQ_REMOVE | R592_REG_MSC_IRQ_INSERT) << 16); reg 608 drivers/memstick/host/r592.c reg |= (R592_REG_MSC_IRQ_REMOVE << 16); reg 610 drivers/memstick/host/r592.c reg |= (R592_REG_MSC_IRQ_INSERT << 16); reg 612 drivers/memstick/host/r592.c r592_write_reg(dev, R592_REG_MSC, reg); reg 628 drivers/memstick/host/r592.c u32 reg; reg 635 drivers/memstick/host/r592.c reg = r592_read_reg(dev, R592_REG_MSC); reg 636 drivers/memstick/host/r592.c irq_enable = reg >> 16; reg 637 drivers/memstick/host/r592.c irq_status = reg & 0xFFFF; reg 640 drivers/memstick/host/r592.c reg &= ~irq_status; reg 641 drivers/memstick/host/r592.c r592_write_reg(dev, R592_REG_MSC, reg); reg 343 drivers/mfd/88pm860x-core.c int reg; reg 351 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS1, reg 356 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS1, reg 361 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS1, reg 366 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS1, reg 371 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS1, reg 376 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS1, reg 381 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS2, reg 386 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS2, reg 391 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS2, reg 396 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS2, reg 401 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS2, reg 406 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS2, reg 411 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS2, reg 416 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS2, reg 421 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS3, reg 426 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS3, reg 431 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS3, reg 436 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS3, reg 441 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS3, reg 446 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS3, reg 451 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS3, reg 456 drivers/mfd/88pm860x-core.c .reg = PM8607_INT_STATUS3, reg 473 drivers/mfd/88pm860x-core.c if (read_reg != irq_data->reg) { reg 474 drivers/mfd/88pm860x-core.c read_reg = irq_data->reg; reg 475 drivers/mfd/88pm860x-core.c value = pm860x_reg_read(i2c, irq_data->reg); reg 15 drivers/mfd/88pm860x-i2c.c int pm860x_reg_read(struct i2c_client *i2c, int reg) reg 23 drivers/mfd/88pm860x-i2c.c ret = regmap_read(map, reg, &data); reg 31 drivers/mfd/88pm860x-i2c.c int pm860x_reg_write(struct i2c_client *i2c, int reg, reg 39 drivers/mfd/88pm860x-i2c.c ret = regmap_write(map, reg, data); reg 44 drivers/mfd/88pm860x-i2c.c int pm860x_bulk_read(struct i2c_client *i2c, int reg, reg 52 drivers/mfd/88pm860x-i2c.c ret = regmap_raw_read(map, reg, buf, count); reg 57 drivers/mfd/88pm860x-i2c.c int pm860x_bulk_write(struct i2c_client *i2c, int reg, reg 65 drivers/mfd/88pm860x-i2c.c ret = regmap_raw_write(map, reg, buf, count); reg 70 drivers/mfd/88pm860x-i2c.c int pm860x_set_bits(struct i2c_client *i2c, int reg, reg 78 drivers/mfd/88pm860x-i2c.c ret = regmap_update_bits(map, reg, mask, data); reg 83 drivers/mfd/88pm860x-i2c.c static int read_device(struct i2c_client *i2c, int reg, reg 106 drivers/mfd/88pm860x-i2c.c msgbuf0[0] = (unsigned char)reg; /* command */ reg 119 drivers/mfd/88pm860x-i2c.c static int write_device(struct i2c_client *i2c, int reg, reg 127 drivers/mfd/88pm860x-i2c.c buf[0] = (unsigned char)reg; reg 140 drivers/mfd/88pm860x-i2c.c int pm860x_page_reg_write(struct i2c_client *i2c, int reg, reg 150 drivers/mfd/88pm860x-i2c.c ret = write_device(i2c, reg, 1, &data); reg 158 drivers/mfd/88pm860x-i2c.c int pm860x_page_bulk_read(struct i2c_client *i2c, int reg, reg 168 drivers/mfd/88pm860x-i2c.c ret = read_device(i2c, reg, count, buf); reg 427 drivers/mfd/aat2870-core.c struct aat2870_register *reg = NULL; reg 434 drivers/mfd/aat2870-core.c reg = &aat2870->reg_cache[i]; reg 435 drivers/mfd/aat2870-core.c if (reg->writeable) reg 436 drivers/mfd/aat2870-core.c aat2870->write(aat2870, i, reg->value); reg 73 drivers/mfd/ab3100-core.c u8 reg, u8 regval) reg 75 drivers/mfd/ab3100-core.c u8 regandval[2] = {reg, regval}; reg 107 drivers/mfd/ab3100-core.c u8 bank, u8 reg, u8 value) reg 111 drivers/mfd/ab3100-core.c return ab3100_set_register_interruptible(ab3100, reg, value); reg 122 drivers/mfd/ab3100-core.c u8 reg, u8 regval) reg 124 drivers/mfd/ab3100-core.c u8 regandval[2] = {reg, regval}; reg 152 drivers/mfd/ab3100-core.c u8 reg, u8 *regval) reg 166 drivers/mfd/ab3100-core.c err = i2c_master_send(ab3100->i2c_client, ®, 1); reg 207 drivers/mfd/ab3100-core.c static int get_register_interruptible(struct device *dev, u8 bank, u8 reg, reg 212 drivers/mfd/ab3100-core.c return ab3100_get_register_interruptible(ab3100, reg, value); reg 280 drivers/mfd/ab3100-core.c u8 reg, u8 andmask, u8 ormask) reg 282 drivers/mfd/ab3100-core.c u8 regandval[2] = {reg, 0}; reg 290 drivers/mfd/ab3100-core.c err = i2c_master_send(ab3100->i2c_client, ®, 1); reg 349 drivers/mfd/ab3100-core.c u8 reg, u8 bitmask, u8 bitvalues) reg 354 drivers/mfd/ab3100-core.c reg, bitmask, (bitmask & bitvalues)); reg 458 drivers/mfd/ab3100-core.c u8 reg; reg 462 drivers/mfd/ab3100-core.c for (reg = 0; reg < 0xff; reg++) { reg 463 drivers/mfd/ab3100-core.c ab3100_get_register_interruptible(ab3100, reg, &value); reg 464 drivers/mfd/ab3100-core.c seq_printf(s, "[0x%x]: 0x%x\n", reg, value); reg 212 drivers/mfd/ab8500-core.c u8 reg, u8 data) reg 219 drivers/mfd/ab8500-core.c u16 addr = ((u16)bank) << 8 | reg; reg 235 drivers/mfd/ab8500-core.c u8 reg, u8 value) reg 241 drivers/mfd/ab8500-core.c ret = set_register_interruptible(ab8500, bank, reg, value); reg 247 drivers/mfd/ab8500-core.c u8 reg, u8 *value) reg 250 drivers/mfd/ab8500-core.c u16 addr = ((u16)bank) << 8 | reg; reg 268 drivers/mfd/ab8500-core.c u8 reg, u8 *value) reg 274 drivers/mfd/ab8500-core.c ret = get_register_interruptible(ab8500, bank, reg, value); reg 280 drivers/mfd/ab8500-core.c u8 reg, u8 bitmask, u8 bitvalues) reg 283 drivers/mfd/ab8500-core.c u16 addr = ((u16)bank) << 8 | reg; reg 319 drivers/mfd/ab8500-core.c u8 bank, u8 reg, u8 bitmask, u8 bitvalues) reg 325 drivers/mfd/ab8500-core.c ret = mask_and_set_register_interruptible(ab8500, bank, reg, reg 359 drivers/mfd/ab8500-core.c int reg; reg 377 drivers/mfd/ab8500-core.c reg = AB8500_IT_MASK1_REG + ab8500->irq_reg_offset[i]; reg 378 drivers/mfd/ab8500-core.c set_register_interruptible(ab8500, AB8500_INTERRUPT, reg, new); reg 1286 drivers/mfd/ab8500-debugfs.c u32 reg; reg 1288 drivers/mfd/ab8500-debugfs.c for (reg = debug_ranges[bank].range[i].first; reg 1289 drivers/mfd/ab8500-debugfs.c reg <= debug_ranges[bank].range[i].last; reg 1290 drivers/mfd/ab8500-debugfs.c reg++) { reg 1295 drivers/mfd/ab8500-debugfs.c (u8)bank, (u8)reg, &value); reg 1303 drivers/mfd/ab8500-debugfs.c bank, reg, value); reg 1312 drivers/mfd/ab8500-debugfs.c bank, reg, value); reg 1600 drivers/mfd/ab8500-debugfs.c u32 reg; reg 1623 drivers/mfd/ab8500-debugfs.c for (reg = AB8500_FIRST_SIM_REG; reg <= last_sim_reg; reg++) { reg 1625 drivers/mfd/ab8500-debugfs.c bank, reg, &value); reg 1629 drivers/mfd/ab8500-debugfs.c seq_printf(s, " [0x%02X/0x%02X]: 0x%02X\n", bank, reg, value); reg 99 drivers/mfd/ab8500-sysctrl.c int ab8500_sysctrl_read(u16 reg, u8 *value) reg 106 drivers/mfd/ab8500-sysctrl.c bank = (reg >> 8); reg 111 drivers/mfd/ab8500-sysctrl.c (u8)(reg & 0xFF), value); reg 115 drivers/mfd/ab8500-sysctrl.c int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value) reg 122 drivers/mfd/ab8500-sysctrl.c bank = (reg >> 8); reg 129 drivers/mfd/ab8500-sysctrl.c (u8)(reg & 0xFF), mask, value); reg 62 drivers/mfd/abx500-core.c int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg, reg 69 drivers/mfd/abx500-core.c return ops->set_register(dev, bank, reg, value); reg 75 drivers/mfd/abx500-core.c int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg, reg 82 drivers/mfd/abx500-core.c return ops->get_register(dev, bank, reg, value); reg 103 drivers/mfd/abx500-core.c u8 reg, u8 bitmask, u8 bitvalues) reg 110 drivers/mfd/abx500-core.c reg, bitmask, bitvalues); reg 43 drivers/mfd/adp5520.c int reg, uint8_t *val) reg 47 drivers/mfd/adp5520.c ret = i2c_smbus_read_byte_data(client, reg); reg 49 drivers/mfd/adp5520.c dev_err(&client->dev, "failed reading at 0x%02x\n", reg); reg 58 drivers/mfd/adp5520.c int reg, uint8_t val) reg 62 drivers/mfd/adp5520.c ret = i2c_smbus_write_byte_data(client, reg, val); reg 65 drivers/mfd/adp5520.c val, reg); reg 71 drivers/mfd/adp5520.c static int __adp5520_ack_bits(struct i2c_client *client, int reg, reg 80 drivers/mfd/adp5520.c ret = __adp5520_read(client, reg, ®_val); reg 84 drivers/mfd/adp5520.c ret = __adp5520_write(client, reg, reg_val); reg 91 drivers/mfd/adp5520.c int adp5520_write(struct device *dev, int reg, uint8_t val) reg 93 drivers/mfd/adp5520.c return __adp5520_write(to_i2c_client(dev), reg, val); reg 97 drivers/mfd/adp5520.c int adp5520_read(struct device *dev, int reg, uint8_t *val) reg 99 drivers/mfd/adp5520.c return __adp5520_read(to_i2c_client(dev), reg, val); reg 103 drivers/mfd/adp5520.c int adp5520_set_bits(struct device *dev, int reg, uint8_t bit_mask) reg 111 drivers/mfd/adp5520.c ret = __adp5520_read(chip->client, reg, ®_val); reg 115 drivers/mfd/adp5520.c ret = __adp5520_write(chip->client, reg, reg_val); reg 123 drivers/mfd/adp5520.c int adp5520_clr_bits(struct device *dev, int reg, uint8_t bit_mask) reg 131 drivers/mfd/adp5520.c ret = __adp5520_read(chip->client, reg, ®_val); reg 135 drivers/mfd/adp5520.c ret = __adp5520_write(chip->client, reg, reg_val); reg 31 drivers/mfd/altera-a10sr.c static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg) reg 33 drivers/mfd/altera-a10sr.c switch (reg) { reg 56 drivers/mfd/altera-a10sr.c static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg) reg 58 drivers/mfd/altera-a10sr.c switch (reg) { reg 75 drivers/mfd/altera-a10sr.c static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg) reg 77 drivers/mfd/altera-a10sr.c switch (reg) { reg 45 drivers/mfd/altera-sysmgr.c unsigned int reg, unsigned int val) reg 50 drivers/mfd/altera-sysmgr.c arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, sysmgr_base + reg, reg 67 drivers/mfd/altera-sysmgr.c unsigned int reg, unsigned int *val) reg 72 drivers/mfd/altera-sysmgr.c arm_smccc_smc(INTEL_SIP_SMC_REG_READ, sysmgr_base + reg, reg 248 drivers/mfd/arizona-core.c int timeout_ms, unsigned int reg, reg 256 drivers/mfd/arizona-core.c ret = regmap_read(arizona->regmap, reg, &val); reg 264 drivers/mfd/arizona-core.c reg, ret); reg 268 drivers/mfd/arizona-core.c dev_err(arizona->dev, "Polling reg 0x%x timed out: %x\n", reg, val); reg 993 drivers/mfd/arizona-core.c unsigned int reg, val; reg 1115 drivers/mfd/arizona-core.c ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, ®); reg 1121 drivers/mfd/arizona-core.c switch (reg) { reg 1129 drivers/mfd/arizona-core.c dev_err(arizona->dev, "Unknown device ID: %x\n", reg); reg 1171 drivers/mfd/arizona-core.c ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, ®); reg 1185 drivers/mfd/arizona-core.c switch (reg) { reg 1289 drivers/mfd/arizona-core.c dev_err(arizona->dev, "Unknown device ID %x\n", reg); reg 1296 drivers/mfd/arizona-core.c "No kernel support for device ID %x\n", reg); reg 34 drivers/mfd/as3711.c static bool as3711_volatile_reg(struct device *dev, unsigned int reg) reg 36 drivers/mfd/as3711.c switch (reg) { reg 49 drivers/mfd/as3711.c static bool as3711_precious_reg(struct device *dev, unsigned int reg) reg 51 drivers/mfd/as3711.c switch (reg) { reg 60 drivers/mfd/as3711.c static bool as3711_readable_reg(struct device *dev, unsigned int reg) reg 62 drivers/mfd/as3711.c switch (reg) { reg 90 drivers/mfd/asic3.c void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value) reg 93 drivers/mfd/asic3.c (reg >> asic->bus_shift)); reg 97 drivers/mfd/asic3.c u32 asic3_read_register(struct asic3 *asic, unsigned int reg) reg 100 drivers/mfd/asic3.c (reg >> asic->bus_shift)); reg 104 drivers/mfd/asic3.c static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set) reg 110 drivers/mfd/asic3.c val = asic3_read_register(asic, reg); reg 115 drivers/mfd/asic3.c asic3_write_register(asic, reg, val); reg 35 drivers/mfd/atmel-hlcdc.c static int regmap_atmel_hlcdc_reg_write(void *context, unsigned int reg, reg 40 drivers/mfd/atmel-hlcdc.c if (reg <= ATMEL_HLCDC_DIS) { reg 48 drivers/mfd/atmel-hlcdc.c writel(val, hregmap->regs + reg); reg 53 drivers/mfd/atmel-hlcdc.c static int regmap_atmel_hlcdc_reg_read(void *context, unsigned int reg, reg 58 drivers/mfd/atmel-hlcdc.c *val = readl(hregmap->regs + reg); reg 698 drivers/mfd/cs47l15-tables.c static bool cs47l15_is_adsp_memory(struct device *dev, unsigned int reg) reg 700 drivers/mfd/cs47l15-tables.c switch (reg) { reg 712 drivers/mfd/cs47l15-tables.c unsigned int reg) reg 714 drivers/mfd/cs47l15-tables.c switch (reg) { reg 1183 drivers/mfd/cs47l15-tables.c unsigned int reg) reg 1185 drivers/mfd/cs47l15-tables.c switch (reg) { reg 1216 drivers/mfd/cs47l15-tables.c unsigned int reg) reg 1218 drivers/mfd/cs47l15-tables.c switch (reg) { reg 1224 drivers/mfd/cs47l15-tables.c return cs47l15_is_adsp_memory(dev, reg); reg 1229 drivers/mfd/cs47l15-tables.c unsigned int reg) reg 1231 drivers/mfd/cs47l15-tables.c switch (reg) { reg 1237 drivers/mfd/cs47l15-tables.c return cs47l15_is_adsp_memory(dev, reg); reg 781 drivers/mfd/cs47l24-tables.c static bool cs47l24_is_adsp_memory(unsigned int reg) reg 783 drivers/mfd/cs47l24-tables.c switch (reg) { reg 798 drivers/mfd/cs47l24-tables.c static bool cs47l24_readable_register(struct device *dev, unsigned int reg) reg 800 drivers/mfd/cs47l24-tables.c switch (reg) { reg 1496 drivers/mfd/cs47l24-tables.c return cs47l24_is_adsp_memory(reg); reg 1500 drivers/mfd/cs47l24-tables.c static bool cs47l24_volatile_register(struct device *dev, unsigned int reg) reg 1502 drivers/mfd/cs47l24-tables.c switch (reg) { reg 1602 drivers/mfd/cs47l24-tables.c return cs47l24_is_adsp_memory(reg); reg 784 drivers/mfd/cs47l35-tables.c static bool cs47l35_is_adsp_memory(unsigned int reg) reg 786 drivers/mfd/cs47l35-tables.c switch (reg) { reg 808 drivers/mfd/cs47l35-tables.c unsigned int reg) reg 810 drivers/mfd/cs47l35-tables.c switch (reg) { reg 1421 drivers/mfd/cs47l35-tables.c unsigned int reg) reg 1423 drivers/mfd/cs47l35-tables.c switch (reg) { reg 1460 drivers/mfd/cs47l35-tables.c unsigned int reg) reg 1462 drivers/mfd/cs47l35-tables.c switch (reg) { reg 1470 drivers/mfd/cs47l35-tables.c return cs47l35_is_adsp_memory(reg); reg 1475 drivers/mfd/cs47l35-tables.c unsigned int reg) reg 1477 drivers/mfd/cs47l35-tables.c switch (reg) { reg 1485 drivers/mfd/cs47l35-tables.c return cs47l35_is_adsp_memory(reg); reg 1687 drivers/mfd/cs47l85-tables.c static bool cs47l85_is_adsp_memory(unsigned int reg) reg 1689 drivers/mfd/cs47l85-tables.c switch (reg) { reg 1727 drivers/mfd/cs47l85-tables.c unsigned int reg) reg 1729 drivers/mfd/cs47l85-tables.c switch (reg) { reg 2742 drivers/mfd/cs47l85-tables.c unsigned int reg) reg 2744 drivers/mfd/cs47l85-tables.c switch (reg) { reg 2790 drivers/mfd/cs47l85-tables.c unsigned int reg) reg 2792 drivers/mfd/cs47l85-tables.c switch (reg) { reg 2804 drivers/mfd/cs47l85-tables.c return cs47l85_is_adsp_memory(reg); reg 2809 drivers/mfd/cs47l85-tables.c unsigned int reg) reg 2811 drivers/mfd/cs47l85-tables.c switch (reg) { reg 2823 drivers/mfd/cs47l85-tables.c return cs47l85_is_adsp_memory(reg); reg 1394 drivers/mfd/cs47l90-tables.c static bool cs47l90_is_adsp_memory(unsigned int reg) reg 1396 drivers/mfd/cs47l90-tables.c switch (reg) { reg 1434 drivers/mfd/cs47l90-tables.c unsigned int reg) reg 1436 drivers/mfd/cs47l90-tables.c switch (reg) { reg 2444 drivers/mfd/cs47l90-tables.c unsigned int reg) reg 2446 drivers/mfd/cs47l90-tables.c switch (reg) { reg 2493 drivers/mfd/cs47l90-tables.c unsigned int reg) reg 2495 drivers/mfd/cs47l90-tables.c switch (reg) { reg 2507 drivers/mfd/cs47l90-tables.c return cs47l90_is_adsp_memory(reg); reg 2512 drivers/mfd/cs47l90-tables.c unsigned int reg) reg 2514 drivers/mfd/cs47l90-tables.c switch (reg) { reg 2526 drivers/mfd/cs47l90-tables.c return cs47l90_is_adsp_memory(reg); reg 1070 drivers/mfd/cs47l92-tables.c static bool cs47l92_is_adsp_memory(unsigned int reg) reg 1072 drivers/mfd/cs47l92-tables.c switch (reg) { reg 1084 drivers/mfd/cs47l92-tables.c unsigned int reg) reg 1086 drivers/mfd/cs47l92-tables.c switch (reg) { reg 1811 drivers/mfd/cs47l92-tables.c unsigned int reg) reg 1813 drivers/mfd/cs47l92-tables.c switch (reg) { reg 1856 drivers/mfd/cs47l92-tables.c unsigned int reg) reg 1858 drivers/mfd/cs47l92-tables.c switch (reg) { reg 1864 drivers/mfd/cs47l92-tables.c return cs47l92_is_adsp_memory(reg); reg 1869 drivers/mfd/cs47l92-tables.c unsigned int reg) reg 1871 drivers/mfd/cs47l92-tables.c switch (reg) { reg 1877 drivers/mfd/cs47l92-tables.c return cs47l92_is_adsp_memory(reg); reg 72 drivers/mfd/da903x.c int reg, uint8_t *val) reg 76 drivers/mfd/da903x.c ret = i2c_smbus_read_byte_data(client, reg); reg 78 drivers/mfd/da903x.c dev_err(&client->dev, "failed reading at 0x%02x\n", reg); reg 86 drivers/mfd/da903x.c static inline int __da903x_reads(struct i2c_client *client, int reg, reg 91 drivers/mfd/da903x.c ret = i2c_smbus_read_i2c_block_data(client, reg, len, val); reg 93 drivers/mfd/da903x.c dev_err(&client->dev, "failed reading from 0x%02x\n", reg); reg 100 drivers/mfd/da903x.c int reg, uint8_t val) reg 104 drivers/mfd/da903x.c ret = i2c_smbus_write_byte_data(client, reg, val); reg 107 drivers/mfd/da903x.c val, reg); reg 113 drivers/mfd/da903x.c static inline int __da903x_writes(struct i2c_client *client, int reg, reg 118 drivers/mfd/da903x.c ret = i2c_smbus_write_i2c_block_data(client, reg, len, val); reg 120 drivers/mfd/da903x.c dev_err(&client->dev, "failed writings to 0x%02x\n", reg); reg 146 drivers/mfd/da903x.c int da903x_write(struct device *dev, int reg, uint8_t val) reg 148 drivers/mfd/da903x.c return __da903x_write(to_i2c_client(dev), reg, val); reg 152 drivers/mfd/da903x.c int da903x_writes(struct device *dev, int reg, int len, uint8_t *val) reg 154 drivers/mfd/da903x.c return __da903x_writes(to_i2c_client(dev), reg, len, val); reg 158 drivers/mfd/da903x.c int da903x_read(struct device *dev, int reg, uint8_t *val) reg 160 drivers/mfd/da903x.c return __da903x_read(to_i2c_client(dev), reg, val); reg 164 drivers/mfd/da903x.c int da903x_reads(struct device *dev, int reg, int len, uint8_t *val) reg 166 drivers/mfd/da903x.c return __da903x_reads(to_i2c_client(dev), reg, len, val); reg 170 drivers/mfd/da903x.c int da903x_set_bits(struct device *dev, int reg, uint8_t bit_mask) reg 178 drivers/mfd/da903x.c ret = __da903x_read(chip->client, reg, ®_val); reg 184 drivers/mfd/da903x.c ret = __da903x_write(chip->client, reg, reg_val); reg 192 drivers/mfd/da903x.c int da903x_clr_bits(struct device *dev, int reg, uint8_t bit_mask) reg 200 drivers/mfd/da903x.c ret = __da903x_read(chip->client, reg, ®_val); reg 206 drivers/mfd/da903x.c ret = __da903x_write(chip->client, reg, reg_val); reg 214 drivers/mfd/da903x.c int da903x_update(struct device *dev, int reg, uint8_t val, uint8_t mask) reg 222 drivers/mfd/da903x.c ret = __da903x_read(chip->client, reg, ®_val); reg 228 drivers/mfd/da903x.c ret = __da903x_write(chip->client, reg, reg_val); reg 23 drivers/mfd/da9052-core.c static bool da9052_reg_readable(struct device *dev, unsigned int reg) reg 25 drivers/mfd/da9052-core.c switch (reg) { reg 159 drivers/mfd/da9052-core.c static bool da9052_reg_writeable(struct device *dev, unsigned int reg) reg 161 drivers/mfd/da9052-core.c switch (reg) { reg 275 drivers/mfd/da9052-core.c static bool da9052_reg_volatile(struct device *dev, unsigned int reg) reg 277 drivers/mfd/da9052-core.c switch (reg) { reg 26 drivers/mfd/da9052-i2c.c static inline bool i2c_safe_reg(unsigned char reg) reg 28 drivers/mfd/da9052-i2c.c switch (reg) { reg 58 drivers/mfd/da9052-i2c.c static int da9052_i2c_fix(struct da9052 *da9052, unsigned char reg) reg 68 drivers/mfd/da9052-i2c.c if (!i2c_safe_reg(reg)) reg 27 drivers/mfd/da9055-core.c static bool da9055_register_readable(struct device *dev, unsigned int reg) reg 29 drivers/mfd/da9055-core.c switch (reg) { reg 103 drivers/mfd/da9055-core.c static bool da9055_register_writeable(struct device *dev, unsigned int reg) reg 105 drivers/mfd/da9055-core.c switch (reg) { reg 179 drivers/mfd/da9055-core.c static bool da9055_register_volatile(struct device *dev, unsigned int reg) reg 181 drivers/mfd/da9055-core.c switch (reg) { reg 93 drivers/mfd/da9150-core.c static bool da9150_volatile_reg(struct device *dev, unsigned int reg) reg 95 drivers/mfd/da9150-core.c switch (reg) { reg 199 drivers/mfd/da9150-core.c u8 da9150_reg_read(struct da9150 *da9150, u16 reg) reg 203 drivers/mfd/da9150-core.c ret = regmap_read(da9150->regmap, reg, &val); reg 206 drivers/mfd/da9150-core.c reg, ret); reg 212 drivers/mfd/da9150-core.c void da9150_reg_write(struct da9150 *da9150, u16 reg, u8 val) reg 216 drivers/mfd/da9150-core.c ret = regmap_write(da9150->regmap, reg, val); reg 219 drivers/mfd/da9150-core.c reg, ret); reg 223 drivers/mfd/da9150-core.c void da9150_set_bits(struct da9150 *da9150, u16 reg, u8 mask, u8 val) reg 227 drivers/mfd/da9150-core.c ret = regmap_update_bits(da9150->regmap, reg, mask, val); reg 230 drivers/mfd/da9150-core.c reg, ret); reg 234 drivers/mfd/da9150-core.c void da9150_bulk_read(struct da9150 *da9150, u16 reg, int count, u8 *buf) reg 238 drivers/mfd/da9150-core.c ret = regmap_bulk_read(da9150->regmap, reg, buf, count); reg 241 drivers/mfd/da9150-core.c reg, ret); reg 245 drivers/mfd/da9150-core.c void da9150_bulk_write(struct da9150 *da9150, u16 reg, int count, const u8 *buf) reg 249 drivers/mfd/da9150-core.c ret = regmap_raw_write(da9150->regmap, reg, buf, count); reg 252 drivers/mfd/da9150-core.c reg, ret); reg 640 drivers/mfd/db8500-prcmu.c u32 db8500_prcmu_read(unsigned int reg) reg 642 drivers/mfd/db8500-prcmu.c return readl(prcmu_base + reg); reg 645 drivers/mfd/db8500-prcmu.c void db8500_prcmu_write(unsigned int reg, u32 value) reg 650 drivers/mfd/db8500-prcmu.c writel(value, (prcmu_base + reg)); reg 654 drivers/mfd/db8500-prcmu.c void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value) reg 660 drivers/mfd/db8500-prcmu.c val = readl(prcmu_base + reg); reg 662 drivers/mfd/db8500-prcmu.c writel(val, (prcmu_base + reg)); reg 1470 drivers/mfd/db8500-prcmu.c static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, reg 1478 drivers/mfd/db8500-prcmu.c val = readl(reg); reg 1496 drivers/mfd/db8500-prcmu.c ((reg == PRCM_PLLSOC0_FREQ) || reg 1497 drivers/mfd/db8500-prcmu.c (reg == PRCM_PLLARM_FREQ) || reg 1498 drivers/mfd/db8500-prcmu.c (reg == PRCM_PLLDDR_FREQ)))) reg 2172 drivers/mfd/db8500-prcmu.c int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) reg 2187 drivers/mfd/db8500-prcmu.c writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); reg 2222 drivers/mfd/db8500-prcmu.c int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size) reg 2237 drivers/mfd/db8500-prcmu.c writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); reg 2266 drivers/mfd/db8500-prcmu.c int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) reg 2270 drivers/mfd/db8500-prcmu.c return prcmu_abb_write_masked(slave, reg, value, &mask, size); reg 70 drivers/mfd/dm355evm_msp.c int dm355evm_msp_write(u8 value, u8 reg) reg 72 drivers/mfd/dm355evm_msp.c return i2c_smbus_write_byte_data(msp430, reg, value); reg 82 drivers/mfd/dm355evm_msp.c int dm355evm_msp_read(u8 reg) reg 84 drivers/mfd/dm355evm_msp.c return i2c_smbus_read_byte_data(msp430, reg); reg 94 drivers/mfd/dm355evm_msp.c #define MSP_GPIO(bit, reg) ((DM355EVM_MSP_ ## reg) << 3 | (bit)) reg 138 drivers/mfd/dm355evm_msp.c int reg, status; reg 140 drivers/mfd/dm355evm_msp.c reg = MSP_GPIO_REG(offset); reg 141 drivers/mfd/dm355evm_msp.c status = dm355evm_msp_read(reg); reg 144 drivers/mfd/dm355evm_msp.c if (reg == DM355EVM_MSP_LED) reg 34 drivers/mfd/htc-pasic3.c void pasic3_write_register(struct device *dev, u32 reg, u8 val) reg 41 drivers/mfd/htc-pasic3.c __raw_writeb(~READ_MODE & reg, addr); reg 49 drivers/mfd/htc-pasic3.c u8 pasic3_read_register(struct device *dev, u32 reg) reg 56 drivers/mfd/htc-pasic3.c __raw_writeb(READ_MODE | reg, addr); reg 172 drivers/mfd/intel_msic.c int intel_msic_reg_read(unsigned short reg, u8 *val) reg 174 drivers/mfd/intel_msic.c return intel_scu_ipc_ioread8(reg, val); reg 188 drivers/mfd/intel_msic.c int intel_msic_reg_write(unsigned short reg, u8 val) reg 190 drivers/mfd/intel_msic.c return intel_scu_ipc_iowrite8(reg, val); reg 207 drivers/mfd/intel_msic.c int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask) reg 209 drivers/mfd/intel_msic.c return intel_scu_ipc_update_register(reg, val, mask); reg 227 drivers/mfd/intel_msic.c int intel_msic_bulk_read(unsigned short *reg, u8 *buf, size_t count) reg 232 drivers/mfd/intel_msic.c return intel_scu_ipc_readv(reg, buf, count); reg 248 drivers/mfd/intel_msic.c int intel_msic_bulk_write(unsigned short *reg, u8 *buf, size_t count) reg 253 drivers/mfd/intel_msic.c return intel_scu_ipc_writev(reg, buf, count); reg 273 drivers/mfd/intel_msic.c int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg, u8 *val) reg 275 drivers/mfd/intel_msic.c if (WARN_ON(reg < INTEL_MSIC_IRQLVL1 || reg > INTEL_MSIC_RESETIRQ2)) reg 278 drivers/mfd/intel_msic.c *val = readb(msic->irq_base + (reg - INTEL_MSIC_IRQLVL1)); reg 270 drivers/mfd/intel_soc_pmic_bxtwc.c static int regmap_ipc_byte_reg_read(void *context, unsigned int reg, reg 282 drivers/mfd/intel_soc_pmic_bxtwc.c if (reg & REG_ADDR_MASK) reg 283 drivers/mfd/intel_soc_pmic_bxtwc.c i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT; reg 287 drivers/mfd/intel_soc_pmic_bxtwc.c reg &= REG_OFFSET_MASK; reg 289 drivers/mfd/intel_soc_pmic_bxtwc.c ipc_in[0] = reg; reg 303 drivers/mfd/intel_soc_pmic_bxtwc.c static int regmap_ipc_byte_reg_write(void *context, unsigned int reg, reg 314 drivers/mfd/intel_soc_pmic_bxtwc.c if (reg & REG_ADDR_MASK) reg 315 drivers/mfd/intel_soc_pmic_bxtwc.c i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT; reg 319 drivers/mfd/intel_soc_pmic_bxtwc.c reg &= REG_OFFSET_MASK; reg 321 drivers/mfd/intel_soc_pmic_bxtwc.c ipc_in[0] = reg; reg 71 drivers/mfd/intel_soc_pmic_chtwc.c static int cht_wc_byte_reg_read(void *context, unsigned int reg, reg 77 drivers/mfd/intel_soc_pmic_chtwc.c if (!(reg & REG_ADDR_MASK)) { reg 82 drivers/mfd/intel_soc_pmic_chtwc.c client->addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT; reg 83 drivers/mfd/intel_soc_pmic_chtwc.c ret = i2c_smbus_read_byte_data(client, reg & REG_OFFSET_MASK); reg 93 drivers/mfd/intel_soc_pmic_chtwc.c static int cht_wc_byte_reg_write(void *context, unsigned int reg, reg 99 drivers/mfd/intel_soc_pmic_chtwc.c if (!(reg & REG_ADDR_MASK)) { reg 104 drivers/mfd/intel_soc_pmic_chtwc.c client->addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT; reg 105 drivers/mfd/intel_soc_pmic_chtwc.c ret = i2c_smbus_write_byte_data(client, reg & REG_OFFSET_MASK, val); reg 74 drivers/mfd/intel_soc_pmic_mrfld.c static int bcove_ipc_byte_reg_read(void *context, unsigned int reg, reg 80 drivers/mfd/intel_soc_pmic_mrfld.c ret = intel_scu_ipc_ioread8(reg, &ipc_out); reg 88 drivers/mfd/intel_soc_pmic_mrfld.c static int bcove_ipc_byte_reg_write(void *context, unsigned int reg, reg 94 drivers/mfd/intel_soc_pmic_mrfld.c ret = intel_scu_ipc_iowrite8(reg, ipc_in); reg 83 drivers/mfd/lm3533-core.c int lm3533_read(struct lm3533 *lm3533, u8 reg, u8 *val) reg 88 drivers/mfd/lm3533-core.c ret = regmap_read(lm3533->regmap, reg, &tmp); reg 91 drivers/mfd/lm3533-core.c reg, ret); reg 97 drivers/mfd/lm3533-core.c dev_dbg(lm3533->dev, "read [%02x]: %02x\n", reg, *val); reg 103 drivers/mfd/lm3533-core.c int lm3533_write(struct lm3533 *lm3533, u8 reg, u8 val) reg 107 drivers/mfd/lm3533-core.c dev_dbg(lm3533->dev, "write [%02x]: %02x\n", reg, val); reg 109 drivers/mfd/lm3533-core.c ret = regmap_write(lm3533->regmap, reg, val); reg 112 drivers/mfd/lm3533-core.c reg, ret); reg 119 drivers/mfd/lm3533-core.c int lm3533_update(struct lm3533 *lm3533, u8 reg, u8 val, u8 mask) reg 123 drivers/mfd/lm3533-core.c dev_dbg(lm3533->dev, "update [%02x]: %02x/%02x\n", reg, val, mask); reg 125 drivers/mfd/lm3533-core.c ret = regmap_update_bits(lm3533->regmap, reg, mask, val); reg 128 drivers/mfd/lm3533-core.c reg, ret); reg 196 drivers/mfd/lm3533-core.c u8 reg; reg 209 drivers/mfd/lm3533-core.c reg = LM3533_REG_OUTPUT_CONF1; reg 212 drivers/mfd/lm3533-core.c reg = LM3533_REG_OUTPUT_CONF2; reg 219 drivers/mfd/lm3533-core.c ret = lm3533_update(lm3533, reg, val, mask); reg 262 drivers/mfd/lm3533-core.c u8 reg; reg 269 drivers/mfd/lm3533-core.c reg = LM3533_REG_OUTPUT_CONF1; reg 274 drivers/mfd/lm3533-core.c reg = LM3533_REG_OUTPUT_CONF1; reg 277 drivers/mfd/lm3533-core.c reg = LM3533_REG_OUTPUT_CONF2; reg 283 drivers/mfd/lm3533-core.c ret = lm3533_read(lm3533, reg, &val); reg 537 drivers/mfd/lm3533-core.c static bool lm3533_readable_register(struct device *dev, unsigned int reg) reg 539 drivers/mfd/lm3533-core.c switch (reg) { reg 556 drivers/mfd/lm3533-core.c static bool lm3533_volatile_register(struct device *dev, unsigned int reg) reg 558 drivers/mfd/lm3533-core.c switch (reg) { reg 568 drivers/mfd/lm3533-core.c static bool lm3533_precious_register(struct device *dev, unsigned int reg) reg 570 drivers/mfd/lm3533-core.c switch (reg) { reg 74 drivers/mfd/lm3533-ctrlbank.c u8 reg; reg 83 drivers/mfd/lm3533-ctrlbank.c reg = lm3533_ctrlbank_get_reg(cb, LM3533_REG_MAX_CURRENT_BASE); reg 84 drivers/mfd/lm3533-ctrlbank.c ret = lm3533_write(cb->lm3533, reg, val); reg 95 drivers/mfd/lm3533-ctrlbank.c u8 reg; \ reg 101 drivers/mfd/lm3533-ctrlbank.c reg = lm3533_ctrlbank_get_reg(cb, LM3533_REG_##_NAME##_BASE); \ reg 102 drivers/mfd/lm3533-ctrlbank.c ret = lm3533_write(cb->lm3533, reg, val); \ reg 113 drivers/mfd/lm3533-ctrlbank.c u8 reg; \ reg 116 drivers/mfd/lm3533-ctrlbank.c reg = lm3533_ctrlbank_get_reg(cb, LM3533_REG_##_NAME##_BASE); \ reg 117 drivers/mfd/lm3533-ctrlbank.c ret = lm3533_read(cb->lm3533, reg, val); \ reg 32 drivers/mfd/lochnagar-i2c.c static bool lochnagar1_readable_register(struct device *dev, unsigned int reg) reg 34 drivers/mfd/lochnagar-i2c.c switch (reg) { reg 82 drivers/mfd/lochnagar-i2c.c static bool lochnagar2_readable_register(struct device *dev, unsigned int reg) reg 84 drivers/mfd/lochnagar-i2c.c switch (reg) { reg 143 drivers/mfd/lochnagar-i2c.c static bool lochnagar2_volatile_register(struct device *dev, unsigned int reg) reg 145 drivers/mfd/lochnagar-i2c.c switch (reg) { reg 73 drivers/mfd/lp3943.c int lp3943_read_byte(struct lp3943 *lp3943, u8 reg, u8 *read) reg 78 drivers/mfd/lp3943.c ret = regmap_read(lp3943->regmap, reg, &val); reg 87 drivers/mfd/lp3943.c int lp3943_write_byte(struct lp3943 *lp3943, u8 reg, u8 data) reg 89 drivers/mfd/lp3943.c return regmap_write(lp3943->regmap, reg, data); reg 93 drivers/mfd/lp3943.c int lp3943_update_bits(struct lp3943 *lp3943, u8 reg, u8 mask, u8 data) reg 95 drivers/mfd/lp3943.c return regmap_update_bits(lp3943->regmap, reg, mask, data); reg 122 drivers/mfd/lp8788.c int lp8788_read_byte(struct lp8788 *lp, u8 reg, u8 *data) reg 127 drivers/mfd/lp8788.c ret = regmap_read(lp->regmap, reg, &val); reg 129 drivers/mfd/lp8788.c dev_err(lp->dev, "failed to read 0x%.2x\n", reg); reg 138 drivers/mfd/lp8788.c int lp8788_read_multi_bytes(struct lp8788 *lp, u8 reg, u8 *data, size_t count) reg 140 drivers/mfd/lp8788.c return regmap_bulk_read(lp->regmap, reg, data, count); reg 144 drivers/mfd/lp8788.c int lp8788_write_byte(struct lp8788 *lp, u8 reg, u8 data) reg 146 drivers/mfd/lp8788.c return regmap_write(lp->regmap, reg, data); reg 150 drivers/mfd/lp8788.c int lp8788_update_bits(struct lp8788 *lp, u8 reg, u8 mask, u8 data) reg 152 drivers/mfd/lp8788.c return regmap_update_bits(lp->regmap, reg, mask, data); reg 146 drivers/mfd/max14577.c static bool max14577_muic_volatile_reg(struct device *dev, unsigned int reg) reg 148 drivers/mfd/max14577.c switch (reg) { reg 157 drivers/mfd/max14577.c static bool max77836_muic_volatile_reg(struct device *dev, unsigned int reg) reg 160 drivers/mfd/max14577.c if (max14577_muic_volatile_reg(dev, reg)) reg 163 drivers/mfd/max14577.c switch (reg) { reg 38 drivers/mfd/max77686.c unsigned int reg) reg 40 drivers/mfd/max77686.c return reg < MAX77802_REG_PMIC_END; reg 44 drivers/mfd/max77686.c unsigned int reg) reg 46 drivers/mfd/max77686.c return (reg >= MAX77802_RTC_INT && reg < MAX77802_RTC_END); reg 49 drivers/mfd/max77686.c static bool max77802_is_accessible_reg(struct device *dev, unsigned int reg) reg 51 drivers/mfd/max77686.c return (max77802_pmic_is_accessible_reg(dev, reg) || reg 52 drivers/mfd/max77686.c max77802_rtc_is_accessible_reg(dev, reg)); reg 55 drivers/mfd/max77686.c static bool max77802_pmic_is_precious_reg(struct device *dev, unsigned int reg) reg 57 drivers/mfd/max77686.c return (reg == MAX77802_REG_INTSRC || reg == MAX77802_REG_INT1 || reg 58 drivers/mfd/max77686.c reg == MAX77802_REG_INT2); reg 61 drivers/mfd/max77686.c static bool max77802_rtc_is_precious_reg(struct device *dev, unsigned int reg) reg 63 drivers/mfd/max77686.c return (reg == MAX77802_RTC_INT || reg 64 drivers/mfd/max77686.c reg == MAX77802_RTC_UPDATE0 || reg 65 drivers/mfd/max77686.c reg == MAX77802_RTC_UPDATE1); reg 68 drivers/mfd/max77686.c static bool max77802_is_precious_reg(struct device *dev, unsigned int reg) reg 70 drivers/mfd/max77686.c return (max77802_pmic_is_precious_reg(dev, reg) || reg 71 drivers/mfd/max77686.c max77802_rtc_is_precious_reg(dev, reg)); reg 74 drivers/mfd/max77686.c static bool max77802_pmic_is_volatile_reg(struct device *dev, unsigned int reg) reg 76 drivers/mfd/max77686.c return (max77802_is_precious_reg(dev, reg) || reg 77 drivers/mfd/max77686.c reg == MAX77802_REG_STATUS1 || reg == MAX77802_REG_STATUS2 || reg 78 drivers/mfd/max77686.c reg == MAX77802_REG_PWRON); reg 81 drivers/mfd/max77686.c static bool max77802_rtc_is_volatile_reg(struct device *dev, unsigned int reg) reg 83 drivers/mfd/max77686.c return (max77802_rtc_is_precious_reg(dev, reg) || reg 84 drivers/mfd/max77686.c reg == MAX77802_RTC_SEC || reg 85 drivers/mfd/max77686.c reg == MAX77802_RTC_MIN || reg 86 drivers/mfd/max77686.c reg == MAX77802_RTC_HOUR || reg 87 drivers/mfd/max77686.c reg == MAX77802_RTC_WEEKDAY || reg 88 drivers/mfd/max77686.c reg == MAX77802_RTC_MONTH || reg 89 drivers/mfd/max77686.c reg == MAX77802_RTC_YEAR || reg 90 drivers/mfd/max77686.c reg == MAX77802_RTC_DATE); reg 93 drivers/mfd/max77686.c static bool max77802_is_volatile_reg(struct device *dev, unsigned int reg) reg 95 drivers/mfd/max77686.c return (max77802_pmic_is_volatile_reg(dev, reg) || reg 96 drivers/mfd/max77686.c max77802_rtc_is_volatile_reg(dev, reg)); reg 27 drivers/mfd/max8907.c static bool max8907_gen_is_volatile_reg(struct device *dev, unsigned int reg) reg 29 drivers/mfd/max8907.c switch (reg) { reg 42 drivers/mfd/max8907.c static bool max8907_gen_is_precious_reg(struct device *dev, unsigned int reg) reg 44 drivers/mfd/max8907.c switch (reg) { reg 55 drivers/mfd/max8907.c static bool max8907_gen_is_writeable_reg(struct device *dev, unsigned int reg) reg 57 drivers/mfd/max8907.c return !max8907_gen_is_volatile_reg(dev, reg); reg 70 drivers/mfd/max8907.c static bool max8907_rtc_is_volatile_reg(struct device *dev, unsigned int reg) reg 72 drivers/mfd/max8907.c if (reg <= MAX8907_REG_RTC_YEAR2) reg 75 drivers/mfd/max8907.c switch (reg) { reg 84 drivers/mfd/max8907.c static bool max8907_rtc_is_precious_reg(struct device *dev, unsigned int reg) reg 86 drivers/mfd/max8907.c switch (reg) { reg 94 drivers/mfd/max8907.c static bool max8907_rtc_is_writeable_reg(struct device *dev, unsigned int reg) reg 96 drivers/mfd/max8907.c switch (reg) { reg 330 drivers/mfd/max8925-core.c int reg; reg 340 drivers/mfd/max8925-core.c .reg = MAX8925_CHG_IRQ1, reg 345 drivers/mfd/max8925-core.c .reg = MAX8925_CHG_IRQ1, reg 350 drivers/mfd/max8925-core.c .reg = MAX8925_CHG_IRQ1, reg 355 drivers/mfd/max8925-core.c .reg = MAX8925_CHG_IRQ2, reg 360 drivers/mfd/max8925-core.c .reg = MAX8925_CHG_IRQ2, reg 365 drivers/mfd/max8925-core.c .reg = MAX8925_CHG_IRQ2, reg 370 drivers/mfd/max8925-core.c .reg = MAX8925_CHG_IRQ2, reg 375 drivers/mfd/max8925-core.c .reg = MAX8925_CHG_IRQ2, reg 380 drivers/mfd/max8925-core.c .reg = MAX8925_CHG_IRQ2, reg 385 drivers/mfd/max8925-core.c .reg = MAX8925_CHG_IRQ2, reg 390 drivers/mfd/max8925-core.c .reg = MAX8925_CHG_IRQ2, reg 395 drivers/mfd/max8925-core.c .reg = MAX8925_ON_OFF_IRQ1, reg 400 drivers/mfd/max8925-core.c .reg = MAX8925_ON_OFF_IRQ1, reg 405 drivers/mfd/max8925-core.c .reg = MAX8925_ON_OFF_IRQ1, reg 410 drivers/mfd/max8925-core.c .reg = MAX8925_ON_OFF_IRQ1, reg 415 drivers/mfd/max8925-core.c .reg = MAX8925_ON_OFF_IRQ1, reg 420 drivers/mfd/max8925-core.c .reg = MAX8925_ON_OFF_IRQ1, reg 425 drivers/mfd/max8925-core.c .reg = MAX8925_ON_OFF_IRQ1, reg 430 drivers/mfd/max8925-core.c .reg = MAX8925_ON_OFF_IRQ1, reg 435 drivers/mfd/max8925-core.c .reg = MAX8925_ON_OFF_IRQ2, reg 440 drivers/mfd/max8925-core.c .reg = MAX8925_ON_OFF_IRQ2, reg 445 drivers/mfd/max8925-core.c .reg = MAX8925_RTC_IRQ, reg 451 drivers/mfd/max8925-core.c .reg = MAX8925_RTC_IRQ, reg 457 drivers/mfd/max8925-core.c .reg = MAX8925_TSC_IRQ, reg 464 drivers/mfd/max8925-core.c .reg = MAX8925_TSC_IRQ, reg 497 drivers/mfd/max8925-core.c if (read_reg != irq_data->reg) { reg 498 drivers/mfd/max8925-core.c read_reg = irq_data->reg; reg 499 drivers/mfd/max8925-core.c value = max8925_reg_read(i2c, irq_data->reg); reg 526 drivers/mfd/max8925-core.c if (read_reg != irq_data->reg) { reg 527 drivers/mfd/max8925-core.c read_reg = irq_data->reg; reg 528 drivers/mfd/max8925-core.c value = max8925_reg_read(i2c, irq_data->reg); reg 19 drivers/mfd/max8925-i2c.c int reg, int bytes, void *dest) reg 24 drivers/mfd/max8925-i2c.c ret = i2c_smbus_read_i2c_block_data(i2c, reg, bytes, dest); reg 26 drivers/mfd/max8925-i2c.c ret = i2c_smbus_read_byte_data(i2c, reg); reg 35 drivers/mfd/max8925-i2c.c int reg, int bytes, void *src) reg 40 drivers/mfd/max8925-i2c.c buf[0] = (unsigned char)reg; reg 49 drivers/mfd/max8925-i2c.c int max8925_reg_read(struct i2c_client *i2c, int reg) reg 56 drivers/mfd/max8925-i2c.c ret = max8925_read_device(i2c, reg, 1, &data); reg 66 drivers/mfd/max8925-i2c.c int max8925_reg_write(struct i2c_client *i2c, int reg, reg 73 drivers/mfd/max8925-i2c.c ret = max8925_write_device(i2c, reg, 1, &data); reg 80 drivers/mfd/max8925-i2c.c int max8925_bulk_read(struct i2c_client *i2c, int reg, reg 87 drivers/mfd/max8925-i2c.c ret = max8925_read_device(i2c, reg, count, buf); reg 94 drivers/mfd/max8925-i2c.c int max8925_bulk_write(struct i2c_client *i2c, int reg, reg 101 drivers/mfd/max8925-i2c.c ret = max8925_write_device(i2c, reg, count, buf); reg 108 drivers/mfd/max8925-i2c.c int max8925_set_bits(struct i2c_client *i2c, int reg, reg 116 drivers/mfd/max8925-i2c.c ret = max8925_read_device(i2c, reg, 1, &value); reg 121 drivers/mfd/max8925-i2c.c ret = max8925_write_device(i2c, reg, 1, &value); reg 46 drivers/mfd/max8997.c int max8997_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest) reg 52 drivers/mfd/max8997.c ret = i2c_smbus_read_byte_data(i2c, reg); reg 63 drivers/mfd/max8997.c int max8997_bulk_read(struct i2c_client *i2c, u8 reg, int count, u8 *buf) reg 69 drivers/mfd/max8997.c ret = i2c_smbus_read_i2c_block_data(i2c, reg, count, buf); reg 78 drivers/mfd/max8997.c int max8997_write_reg(struct i2c_client *i2c, u8 reg, u8 value) reg 84 drivers/mfd/max8997.c ret = i2c_smbus_write_byte_data(i2c, reg, value); reg 90 drivers/mfd/max8997.c int max8997_bulk_write(struct i2c_client *i2c, u8 reg, int count, u8 *buf) reg 96 drivers/mfd/max8997.c ret = i2c_smbus_write_i2c_block_data(i2c, reg, count, buf); reg 105 drivers/mfd/max8997.c int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask) reg 111 drivers/mfd/max8997.c ret = i2c_smbus_read_byte_data(i2c, reg); reg 115 drivers/mfd/max8997.c ret = i2c_smbus_write_byte_data(i2c, reg, new_val); reg 15 drivers/mfd/max8998-irq.c int reg; reg 21 drivers/mfd/max8998-irq.c .reg = 1, reg 25 drivers/mfd/max8998-irq.c .reg = 1, reg 29 drivers/mfd/max8998-irq.c .reg = 1, reg 33 drivers/mfd/max8998-irq.c .reg = 1, reg 37 drivers/mfd/max8998-irq.c .reg = 1, reg 41 drivers/mfd/max8998-irq.c .reg = 1, reg 45 drivers/mfd/max8998-irq.c .reg = 2, reg 49 drivers/mfd/max8998-irq.c .reg = 2, reg 53 drivers/mfd/max8998-irq.c .reg = 2, reg 57 drivers/mfd/max8998-irq.c .reg = 2, reg 61 drivers/mfd/max8998-irq.c .reg = 3, reg 65 drivers/mfd/max8998-irq.c .reg = 3, reg 69 drivers/mfd/max8998-irq.c .reg = 3, reg 73 drivers/mfd/max8998-irq.c .reg = 3, reg 77 drivers/mfd/max8998-irq.c .reg = 3, reg 81 drivers/mfd/max8998-irq.c .reg = 3, reg 85 drivers/mfd/max8998-irq.c .reg = 4, reg 89 drivers/mfd/max8998-irq.c .reg = 4, reg 132 drivers/mfd/max8998-irq.c max8998->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask; reg 140 drivers/mfd/max8998-irq.c max8998->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask; reg 172 drivers/mfd/max8998-irq.c if (irq_reg[max8998_irqs[i].reg - 1] & max8998_irqs[i].mask) { reg 42 drivers/mfd/max8998.c int max8998_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest) reg 48 drivers/mfd/max8998.c ret = i2c_smbus_read_byte_data(i2c, reg); reg 59 drivers/mfd/max8998.c int max8998_bulk_read(struct i2c_client *i2c, u8 reg, int count, u8 *buf) reg 65 drivers/mfd/max8998.c ret = i2c_smbus_read_i2c_block_data(i2c, reg, count, buf); reg 74 drivers/mfd/max8998.c int max8998_write_reg(struct i2c_client *i2c, u8 reg, u8 value) reg 80 drivers/mfd/max8998.c ret = i2c_smbus_write_byte_data(i2c, reg, value); reg 86 drivers/mfd/max8998.c int max8998_bulk_write(struct i2c_client *i2c, u8 reg, int count, u8 *buf) reg 92 drivers/mfd/max8998.c ret = i2c_smbus_write_i2c_block_data(i2c, reg, count, buf); reg 101 drivers/mfd/max8998.c int max8998_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask) reg 107 drivers/mfd/max8998.c ret = i2c_smbus_read_byte_data(i2c, reg); reg 111 drivers/mfd/max8998.c ret = i2c_smbus_write_byte_data(i2c, reg, new_val); reg 177 drivers/mfd/mc13xxx-core.c #define maskval(reg, mask) (((reg) & (mask)) >> __ffs(mask)) reg 61 drivers/mfd/mc13xxx-spi.c static int mc13xxx_spi_read(void *context, const void *reg, size_t reg_size, reg 64 drivers/mfd/mc13xxx-spi.c unsigned char w[4] = { *((unsigned char *) reg), 0, 0, 0}; reg 94 drivers/mfd/mc13xxx-spi.c const char *reg = data; reg 100 drivers/mfd/mc13xxx-spi.c if (*reg == MC13783_AUDIO_CODEC || *reg == MC13783_AUDIO_DAC) reg 96 drivers/mfd/mcp-core.c void mcp_reg_write(struct mcp *mcp, unsigned int reg, unsigned int val) reg 101 drivers/mfd/mcp-core.c mcp->ops->reg_write(mcp, reg, val); reg 114 drivers/mfd/mcp-core.c unsigned int mcp_reg_read(struct mcp *mcp, unsigned int reg) reg 120 drivers/mfd/mcp-core.c val = mcp->ops->reg_read(mcp, reg); reg 75 drivers/mfd/mcp-sa11x0.c mcp_sa11x0_write(struct mcp *mcp, unsigned int reg, unsigned int val) reg 81 drivers/mfd/mcp-sa11x0.c writel_relaxed(reg << 17 | MCDR2_Wr | (val & 0xffff), MCDR2(m)); reg 102 drivers/mfd/mcp-sa11x0.c mcp_sa11x0_read(struct mcp *mcp, unsigned int reg) reg 108 drivers/mfd/mcp-sa11x0.c writel_relaxed(reg << 17 | MCDR2_Rd, MCDR2(m)); reg 171 drivers/mfd/menelaus.c static int menelaus_write_reg(int reg, u8 value) reg 173 drivers/mfd/menelaus.c int val = i2c_smbus_write_byte_data(the_menelaus->client, reg, value); reg 183 drivers/mfd/menelaus.c static int menelaus_read_reg(int reg) reg 185 drivers/mfd/menelaus.c int val = i2c_smbus_read_byte_data(the_menelaus->client, reg); reg 264 drivers/mfd/menelaus.c int reg; reg 267 drivers/mfd/menelaus.c reg = menelaus_read_reg(MENELAUS_MCT_PIN_ST); reg 268 drivers/mfd/menelaus.c if (reg < 0) reg 271 drivers/mfd/menelaus.c if (!(reg & 0x1)) reg 274 drivers/mfd/menelaus.c if (!(reg & 0x2)) reg 39 drivers/mfd/motorola-cpcap.c int reg = CPCAP_REG_INTS1 + (regnum * CPCAP_REGISTER_SIZE); reg 42 drivers/mfd/motorola-cpcap.c if (reg < CPCAP_REG_INTS1 || reg > CPCAP_REG_INTS4) reg 45 drivers/mfd/motorola-cpcap.c err = regmap_read(regmap, reg, &val); reg 40 drivers/mfd/mt6397-irq.c int reg = data->hwirq >> 4; reg 42 drivers/mfd/mt6397-irq.c mt6397->irq_masks_cur[reg] &= ~BIT(shift); reg 49 drivers/mfd/mt6397-irq.c int reg = data->hwirq >> 4; reg 51 drivers/mfd/mt6397-irq.c mt6397->irq_masks_cur[reg] |= BIT(shift); reg 59 drivers/mfd/mt6397-irq.c int reg = irq_data->hwirq >> 4; reg 62 drivers/mfd/mt6397-irq.c mt6397->wake_mask[reg] |= BIT(shift); reg 64 drivers/mfd/mt6397-irq.c mt6397->wake_mask[reg] &= ~BIT(shift); reg 81 drivers/mfd/mt6397-irq.c static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg, reg 87 drivers/mfd/mt6397-irq.c ret = regmap_read(mt6397->regmap, reg, &status); reg 101 drivers/mfd/mt6397-irq.c regmap_write(mt6397->regmap, reg, status); reg 111 drivers/mfd/omap-usb-host.c static inline void usbhs_write(void __iomem *base, u32 reg, u32 val) reg 113 drivers/mfd/omap-usb-host.c writel_relaxed(val, base + reg); reg 116 drivers/mfd/omap-usb-host.c static inline u32 usbhs_read(void __iomem *base, u32 reg) reg 118 drivers/mfd/omap-usb-host.c return readl_relaxed(base + reg); reg 367 drivers/mfd/omap-usb-host.c unsigned reg) reg 375 drivers/mfd/omap-usb-host.c reg &= ~(OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS << i); reg 382 drivers/mfd/omap-usb-host.c reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; reg 384 drivers/mfd/omap-usb-host.c reg &= ~(OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS reg 392 drivers/mfd/omap-usb-host.c reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; reg 394 drivers/mfd/omap-usb-host.c reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS reg 402 drivers/mfd/omap-usb-host.c reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; reg 406 drivers/mfd/omap-usb-host.c reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; reg 412 drivers/mfd/omap-usb-host.c return reg; reg 416 drivers/mfd/omap-usb-host.c unsigned reg) reg 423 drivers/mfd/omap-usb-host.c reg &= ~(OMAP4_P1_MODE_CLEAR << 2 * i); reg 427 drivers/mfd/omap-usb-host.c reg |= OMAP4_P1_MODE_TLL << 2 * i; reg 429 drivers/mfd/omap-usb-host.c reg |= OMAP4_P1_MODE_HSIC << 2 * i; reg 432 drivers/mfd/omap-usb-host.c return reg; reg 438 drivers/mfd/omap-usb-host.c unsigned reg; reg 444 drivers/mfd/omap-usb-host.c reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG); reg 446 drivers/mfd/omap-usb-host.c reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN reg 449 drivers/mfd/omap-usb-host.c reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK; reg 450 drivers/mfd/omap-usb-host.c reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; reg 454 drivers/mfd/omap-usb-host.c reg = omap_usbhs_rev1_hostconfig(omap, reg); reg 458 drivers/mfd/omap-usb-host.c reg = omap_usbhs_rev2_hostconfig(omap, reg); reg 462 drivers/mfd/omap-usb-host.c reg = omap_usbhs_rev2_hostconfig(omap, reg); reg 466 drivers/mfd/omap-usb-host.c usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); reg 467 drivers/mfd/omap-usb-host.c dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg); reg 113 drivers/mfd/omap-usb-tll.c static inline void usbtll_write(void __iomem *base, u32 reg, u32 val) reg 115 drivers/mfd/omap-usb-tll.c writel_relaxed(val, base + reg); reg 118 drivers/mfd/omap-usb-tll.c static inline u32 usbtll_read(void __iomem *base, u32 reg) reg 120 drivers/mfd/omap-usb-tll.c return readl_relaxed(base + reg); reg 123 drivers/mfd/omap-usb-tll.c static inline void usbtll_writeb(void __iomem *base, u32 reg, u8 val) reg 125 drivers/mfd/omap-usb-tll.c writeb_relaxed(val, base + reg); reg 128 drivers/mfd/omap-usb-tll.c static inline u8 usbtll_readb(void __iomem *base, u32 reg) reg 130 drivers/mfd/omap-usb-tll.c return readb_relaxed(base + reg); reg 318 drivers/mfd/omap-usb-tll.c unsigned reg; reg 336 drivers/mfd/omap-usb-tll.c reg = usbtll_read(base, OMAP_TLL_SHARED_CONF); reg 337 drivers/mfd/omap-usb-tll.c reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON reg 339 drivers/mfd/omap-usb-tll.c reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN; reg 340 drivers/mfd/omap-usb-tll.c reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN; reg 342 drivers/mfd/omap-usb-tll.c usbtll_write(base, OMAP_TLL_SHARED_CONF, reg); reg 346 drivers/mfd/omap-usb-tll.c reg = usbtll_read(base, OMAP_TLL_CHANNEL_CONF(i)); reg 349 drivers/mfd/omap-usb-tll.c reg |= ohci_omap3_fslsmode(pdata->port_mode[i]) reg 351 drivers/mfd/omap-usb-tll.c reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS; reg 358 drivers/mfd/omap-usb-tll.c reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE reg 360 drivers/mfd/omap-usb-tll.c reg |= OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF; reg 361 drivers/mfd/omap-usb-tll.c reg |= OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE; reg 367 drivers/mfd/omap-usb-tll.c reg |= OMAP_TLL_CHANNEL_CONF_DRVVBUS reg 374 drivers/mfd/omap-usb-tll.c reg |= OMAP_TLL_CHANNEL_CONF_CHANEN; reg 375 drivers/mfd/omap-usb-tll.c usbtll_write(base, OMAP_TLL_CHANNEL_CONF(i), reg); reg 513 drivers/mfd/palmas.c unsigned int reg, addr; reg 580 drivers/mfd/palmas.c reg = PALMAS_POLARITY_CTRL_INT_POLARITY; reg 582 drivers/mfd/palmas.c reg = 0; reg 585 drivers/mfd/palmas.c reg); reg 594 drivers/mfd/palmas.c reg = PALMAS_INT_CTRL_INT_CLEAR; reg 596 drivers/mfd/palmas.c regmap_write(palmas->regmap[slave], addr, reg); reg 610 drivers/mfd/palmas.c reg = pdata->pad1; reg 611 drivers/mfd/palmas.c ret = regmap_write(palmas->regmap[slave], addr, reg); reg 615 drivers/mfd/palmas.c ret = regmap_read(palmas->regmap[slave], addr, ®); reg 620 drivers/mfd/palmas.c if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0)) reg 622 drivers/mfd/palmas.c if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK)) reg 624 drivers/mfd/palmas.c else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) == reg 627 drivers/mfd/palmas.c else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) == reg 630 drivers/mfd/palmas.c if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK)) reg 632 drivers/mfd/palmas.c else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) == reg 635 drivers/mfd/palmas.c else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) == reg 638 drivers/mfd/palmas.c if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3)) reg 645 drivers/mfd/palmas.c reg = pdata->pad2; reg 646 drivers/mfd/palmas.c ret = regmap_write(palmas->regmap[slave], addr, reg); reg 650 drivers/mfd/palmas.c ret = regmap_read(palmas->regmap[slave], addr, ®); reg 655 drivers/mfd/palmas.c if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4)) reg 657 drivers/mfd/palmas.c if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK)) reg 659 drivers/mfd/palmas.c if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6)) reg 661 drivers/mfd/palmas.c if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK)) reg 668 drivers/mfd/palmas.c reg = pdata->power_ctrl; reg 673 drivers/mfd/palmas.c ret = regmap_write(palmas->regmap[slave], addr, reg); reg 27 drivers/mfd/pcf50633-core.c int pcf50633_read_block(struct pcf50633 *pcf, u8 reg, reg 32 drivers/mfd/pcf50633-core.c ret = regmap_raw_read(pcf->regmap, reg, data, nr_regs); reg 41 drivers/mfd/pcf50633-core.c int pcf50633_write_block(struct pcf50633 *pcf , u8 reg, reg 44 drivers/mfd/pcf50633-core.c return regmap_raw_write(pcf->regmap, reg, data, nr_regs); reg 48 drivers/mfd/pcf50633-core.c u8 pcf50633_reg_read(struct pcf50633 *pcf, u8 reg) reg 53 drivers/mfd/pcf50633-core.c ret = regmap_read(pcf->regmap, reg, &val); reg 61 drivers/mfd/pcf50633-core.c int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val) reg 63 drivers/mfd/pcf50633-core.c return regmap_write(pcf->regmap, reg, val); reg 67 drivers/mfd/pcf50633-core.c int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val) reg 69 drivers/mfd/pcf50633-core.c return regmap_update_bits(pcf->regmap, reg, mask, val); reg 73 drivers/mfd/pcf50633-core.c int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 val) reg 75 drivers/mfd/pcf50633-core.c return regmap_update_bits(pcf->regmap, reg, val, 0); reg 35 drivers/mfd/pcf50633-gpio.c u8 reg; reg 37 drivers/mfd/pcf50633-gpio.c reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; reg 39 drivers/mfd/pcf50633-gpio.c return pcf50633_reg_set_bit_mask(pcf, reg, 0x07, val); reg 45 drivers/mfd/pcf50633-gpio.c u8 reg, val; reg 47 drivers/mfd/pcf50633-gpio.c reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; reg 48 drivers/mfd/pcf50633-gpio.c val = pcf50633_reg_read(pcf, reg) & 0x07; reg 56 drivers/mfd/pcf50633-gpio.c u8 val, reg; reg 58 drivers/mfd/pcf50633-gpio.c reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; reg 61 drivers/mfd/pcf50633-gpio.c return pcf50633_reg_set_bit_mask(pcf, reg, 1 << 3, val); reg 67 drivers/mfd/pcf50633-gpio.c u8 reg, val; reg 69 drivers/mfd/pcf50633-gpio.c reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG; reg 70 drivers/mfd/pcf50633-gpio.c val = pcf50633_reg_read(pcf, reg); reg 79 drivers/mfd/pcf50633-gpio.c u8 reg, val, mask; reg 82 drivers/mfd/pcf50633-gpio.c reg = pcf50633_regulator_registers[regulator] + 1; reg 87 drivers/mfd/pcf50633-gpio.c return pcf50633_reg_set_bit_mask(pcf, reg, mask, val); reg 52 drivers/mfd/pcf50633-irq.c u8 reg, bit; reg 56 drivers/mfd/pcf50633-irq.c reg = PCF50633_REG_INT1M + idx; reg 59 drivers/mfd/pcf50633-irq.c pcf50633_reg_set_bit_mask(pcf, reg, bit, mask ? bit : 0); reg 91 drivers/mfd/pcf50633-irq.c u8 reg, bits; reg 93 drivers/mfd/pcf50633-irq.c reg = irq >> 3; reg 96 drivers/mfd/pcf50633-irq.c return pcf->mask_regs[reg] & bits; reg 184 drivers/mfd/rc5t583.c static bool volatile_reg(struct device *dev, unsigned int reg) reg 187 drivers/mfd/rc5t583.c switch (reg) { reg 206 drivers/mfd/rc5t583.c if ((reg >= RC5T583_GPIO_IOSEL) && reg 207 drivers/mfd/rc5t583.c (reg <= RC5T583_GPIO_GPOFUNC)) reg 211 drivers/mfd/rc5t583.c if ((reg >= RC5T583_SLPSEQ1) && (reg <= RC5T583_SLPSEQ11)) reg 215 drivers/mfd/rc5t583.c if ((reg >= RC5T583_REG_DC0CTL) && (reg <= RC5T583_REG_SR3CTL)) reg 217 drivers/mfd/rc5t583.c if ((reg >= RC5T583_REG_LDOEN1) && reg 218 drivers/mfd/rc5t583.c (reg <= RC5T583_REG_LDO9DAC_DS)) reg 143 drivers/mfd/retu-mfd.c int retu_read(struct retu_dev *rdev, u8 reg) reg 149 drivers/mfd/retu-mfd.c ret = regmap_read(rdev->regmap, reg, &value); reg 156 drivers/mfd/retu-mfd.c int retu_write(struct retu_dev *rdev, u8 reg, u16 data) reg 161 drivers/mfd/retu-mfd.c ret = regmap_write(rdev->regmap, reg, data); reg 171 drivers/mfd/retu-mfd.c int reg; reg 176 drivers/mfd/retu-mfd.c regmap_read(rdev->regmap, RETU_REG_CC1, ®); reg 177 drivers/mfd/retu-mfd.c regmap_write(rdev->regmap, RETU_REG_CC1, reg | 2); reg 189 drivers/mfd/retu-mfd.c static int retu_regmap_read(void *context, const void *reg, size_t reg_size, reg 198 drivers/mfd/retu-mfd.c ret = i2c_smbus_read_word_data(i2c, *(u8 const *)reg); reg 208 drivers/mfd/retu-mfd.c u8 reg; reg 213 drivers/mfd/retu-mfd.c BUG_ON(count != sizeof(reg) + sizeof(val)); reg 214 drivers/mfd/retu-mfd.c memcpy(®, data, sizeof(reg)); reg 215 drivers/mfd/retu-mfd.c memcpy(&val, data + sizeof(reg), sizeof(val)); reg 216 drivers/mfd/retu-mfd.c return i2c_smbus_write_word_data(i2c, reg, val); reg 30 drivers/mfd/rk808.c static bool rk808_is_volatile_reg(struct device *dev, unsigned int reg) reg 40 drivers/mfd/rk808.c switch (reg) { reg 58 drivers/mfd/rk808.c static bool rk817_is_volatile_reg(struct device *dev, unsigned int reg) reg 66 drivers/mfd/rk808.c switch (reg) { reg 23 drivers/mfd/rn5t618.c static bool rn5t618_volatile_reg(struct device *dev, unsigned int reg) reg 25 drivers/mfd/rn5t618.c switch (reg) { reg 126 drivers/mfd/sec-core.c static bool s2mpa01_volatile(struct device *dev, unsigned int reg) reg 128 drivers/mfd/sec-core.c switch (reg) { reg 138 drivers/mfd/sec-core.c static bool s2mps11_volatile(struct device *dev, unsigned int reg) reg 140 drivers/mfd/sec-core.c switch (reg) { reg 150 drivers/mfd/sec-core.c static bool s2mpu02_volatile(struct device *dev, unsigned int reg) reg 152 drivers/mfd/sec-core.c switch (reg) { reg 162 drivers/mfd/sec-core.c static bool s5m8763_volatile(struct device *dev, unsigned int reg) reg 164 drivers/mfd/sec-core.c switch (reg) { reg 475 drivers/mfd/sec-core.c unsigned int reg, mask; reg 482 drivers/mfd/sec-core.c reg = S2MPS11_REG_CTRL1; reg 496 drivers/mfd/sec-core.c regmap_update_bits(sec_pmic->regmap_pmic, reg, mask, 0); reg 171 drivers/mfd/si476x-prop.c unsigned int reg) reg 176 drivers/mfd/si476x-prop.c return si476x_core_is_valid_property(core, (u16) reg); reg 181 drivers/mfd/si476x-prop.c unsigned int reg) reg 186 drivers/mfd/si476x-prop.c return si476x_core_is_valid_property(core, (u16) reg) && reg 187 drivers/mfd/si476x-prop.c !si476x_core_is_readonly_property(core, (u16) reg); reg 191 drivers/mfd/si476x-prop.c static int si476x_core_regmap_write(void *context, unsigned int reg, reg 194 drivers/mfd/si476x-prop.c return si476x_core_cmd_set_property(context, reg, val); reg 197 drivers/mfd/si476x-prop.c static int si476x_core_regmap_read(void *context, unsigned int reg, reg 203 drivers/mfd/si476x-prop.c err = si476x_core_cmd_get_property(core, reg); reg 286 drivers/mfd/sm501.c unsigned long reg, reg 296 drivers/mfd/sm501.c data = smc501_readl(sm->regs + reg); reg 300 drivers/mfd/sm501.c smc501_writel(data, sm->regs + reg); reg 518 drivers/mfd/sm501.c u64 reg; reg 536 drivers/mfd/sm501.c reg = to.shift & 0x07;/* bottom 3 bits are shift */ reg 538 drivers/mfd/sm501.c reg |= 0x08; /* /3 divider required */ reg 540 drivers/mfd/sm501.c reg |= 0x10; /* /5 divider required */ reg 541 drivers/mfd/sm501.c reg |= 0x40; /* select the programmable PLL */ reg 546 drivers/mfd/sm501.c reg = to.shift & 0x07;/* bottom 3 bits are shift */ reg 548 drivers/mfd/sm501.c reg |= 0x08; /* /3 divider required */ reg 550 drivers/mfd/sm501.c reg |= 0x10; /* /5 divider required */ reg 552 drivers/mfd/sm501.c reg |= 0x20; /* which mclk pll is source */ reg 561 drivers/mfd/sm501.c reg=to.shift & 0x07; /* bottom 3 bits are shift */ reg 563 drivers/mfd/sm501.c reg |= 0x08; /* /3 divider required */ reg 565 drivers/mfd/sm501.c reg |= 0x10; /* which mclk pll is source */ reg 573 drivers/mfd/sm501.c reg=to.shift & 0x07; /* bottom 3 bits are shift */ reg 575 drivers/mfd/sm501.c reg |= 0x08; /* /3 divider required */ reg 577 drivers/mfd/sm501.c reg |= 0x10; /* which mclk pll is source */ reg 591 drivers/mfd/sm501.c clock |= reg<<clksrc; reg 1211 drivers/mfd/sm501.c unsigned int reg; reg 1215 drivers/mfd/sm501.c for (reg = 0x00; reg < 0x70; reg += 4) { reg 1217 drivers/mfd/sm501.c reg, smc501_readl(sm->regs + reg)); reg 1236 drivers/mfd/sm501.c unsigned long reg, reg 1241 drivers/mfd/sm501.c tmp = smc501_readl(sm->regs + reg); reg 1244 drivers/mfd/sm501.c smc501_writel(tmp, sm->regs + reg); reg 121 drivers/mfd/sprd-sc27xx-spi.c const void *reg, size_t reg_size, reg 134 drivers/mfd/sprd-sc27xx-spi.c memcpy(rx_buf, reg, sizeof(u32)); reg 75 drivers/mfd/ssbi.c static inline u32 ssbi_readl(struct ssbi *ssbi, u32 reg) reg 77 drivers/mfd/ssbi.c return readl(ssbi->base + reg); reg 80 drivers/mfd/ssbi.c static inline void ssbi_writel(struct ssbi *ssbi, u32 val, u32 reg) reg 82 drivers/mfd/ssbi.c writel(val, ssbi->base + reg); reg 92 drivers/mfd/sta2x11-mfd.c u32 __sta2x11_mfd_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val, reg 111 drivers/mfd/sta2x11-mfd.c r = readl(regs + reg); reg 115 drivers/mfd/sta2x11-mfd.c writel(r, regs + reg); reg 171 drivers/mfd/sta2x11-mfd.c static bool sta2x11_sctl_writeable_reg(struct device *dev, unsigned int reg) reg 173 drivers/mfd/sta2x11-mfd.c return !__reg_within_range(reg, SCTL_SCPCIECSBRST, SCTL_SCRSTSTA); reg 186 drivers/mfd/sta2x11-mfd.c static bool sta2x11_scr_readable_reg(struct device *dev, unsigned int reg) reg 188 drivers/mfd/sta2x11-mfd.c return (reg == STA2X11_SECR_CR) || reg 189 drivers/mfd/sta2x11-mfd.c __reg_within_range(reg, STA2X11_SECR_FVR0, STA2X11_SECR_FVR1); reg 192 drivers/mfd/sta2x11-mfd.c static bool sta2x11_scr_writeable_reg(struct device *dev, unsigned int reg) reg 208 drivers/mfd/sta2x11-mfd.c static bool sta2x11_apbreg_readable_reg(struct device *dev, unsigned int reg) reg 211 drivers/mfd/sta2x11-mfd.c if (reg >= APBREG_BSR_SARAC) reg 212 drivers/mfd/sta2x11-mfd.c reg -= APBREG_BSR_SARAC; reg 213 drivers/mfd/sta2x11-mfd.c switch (reg) { reg 227 drivers/mfd/sta2x11-mfd.c static bool sta2x11_apbreg_writeable_reg(struct device *dev, unsigned int reg) reg 229 drivers/mfd/sta2x11-mfd.c if (reg >= APBREG_BSR_SARAC) reg 230 drivers/mfd/sta2x11-mfd.c reg -= APBREG_BSR_SARAC; reg 231 drivers/mfd/sta2x11-mfd.c if (!sta2x11_apbreg_readable_reg(dev, reg)) reg 233 drivers/mfd/sta2x11-mfd.c return reg != APBREG_PAER; reg 248 drivers/mfd/sta2x11-mfd.c unsigned int reg) reg 250 drivers/mfd/sta2x11-mfd.c return reg <= PCIE_SoC_INT_ROUTER_STATUS3_REG || reg 251 drivers/mfd/sta2x11-mfd.c __reg_within_range(reg, DMA_IP_CTRL_REG, SPARE3_RESERVED) || reg 252 drivers/mfd/sta2x11-mfd.c __reg_within_range(reg, MASTER_LOCK_REG, reg 254 drivers/mfd/sta2x11-mfd.c reg == MSP_CLK_CTRL_REG || reg 255 drivers/mfd/sta2x11-mfd.c __reg_within_range(reg, COMPENSATION_REG1, TEST_CTL_REG); reg 259 drivers/mfd/sta2x11-mfd.c unsigned int reg) reg 261 drivers/mfd/sta2x11-mfd.c if (!sta2x11_apb_soc_regs_readable_reg(dev, reg)) reg 263 drivers/mfd/sta2x11-mfd.c switch (reg) { reg 50 drivers/mfd/stm32-timers.c enum stm32_timers_dmas id, u32 reg, reg 71 drivers/mfd/stm32-timers.c if (!num_reg || !bursts || reg > STM32_TIMERS_MAX_REGISTERS || reg 72 drivers/mfd/stm32-timers.c (reg + num_reg * sizeof(u32)) > STM32_TIMERS_MAX_REGISTERS) reg 114 drivers/mfd/stm32-timers.c dba = FIELD_PREP(TIM_DCR_DBA, reg >> 2); reg 17 drivers/mfd/stmfx.c static bool stmfx_reg_volatile(struct device *dev, unsigned int reg) reg 19 drivers/mfd/stmfx.c switch (reg) { reg 44 drivers/mfd/stmfx.c static bool stmfx_reg_writeable(struct device *dev, unsigned int reg) reg 46 drivers/mfd/stmfx.c return (reg >= STMFX_REG_SYS_CTRL); reg 20 drivers/mfd/stmpe-i2c.c static int i2c_reg_read(struct stmpe *stmpe, u8 reg) reg 24 drivers/mfd/stmpe-i2c.c return i2c_smbus_read_byte_data(i2c, reg); reg 27 drivers/mfd/stmpe-i2c.c static int i2c_reg_write(struct stmpe *stmpe, u8 reg, u8 val) reg 31 drivers/mfd/stmpe-i2c.c return i2c_smbus_write_byte_data(i2c, reg, val); reg 34 drivers/mfd/stmpe-i2c.c static int i2c_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values) reg 38 drivers/mfd/stmpe-i2c.c return i2c_smbus_read_i2c_block_data(i2c, reg, length, values); reg 41 drivers/mfd/stmpe-i2c.c static int i2c_block_write(struct stmpe *stmpe, u8 reg, u8 length, reg 46 drivers/mfd/stmpe-i2c.c return i2c_smbus_write_i2c_block_data(i2c, reg, length, values); reg 20 drivers/mfd/stmpe-spi.c static int spi_reg_read(struct stmpe *stmpe, u8 reg) reg 23 drivers/mfd/stmpe-spi.c int status = spi_w8r16(spi, reg | READ_CMD); reg 28 drivers/mfd/stmpe-spi.c static int spi_reg_write(struct stmpe *stmpe, u8 reg, u8 val) reg 31 drivers/mfd/stmpe-spi.c u16 cmd = (val << 8) | reg; reg 36 drivers/mfd/stmpe-spi.c static int spi_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values) reg 41 drivers/mfd/stmpe-spi.c ret = spi_reg_read(stmpe, reg + i); reg 50 drivers/mfd/stmpe-spi.c static int spi_block_write(struct stmpe *stmpe, u8 reg, u8 length, reg 55 drivers/mfd/stmpe-spi.c for (i = length; i > 0; i--, reg++) { reg 56 drivers/mfd/stmpe-spi.c ret = spi_reg_write(stmpe, reg, *(values + i - 1)); reg 57 drivers/mfd/stmpe.c static int __stmpe_reg_read(struct stmpe *stmpe, u8 reg) reg 61 drivers/mfd/stmpe.c ret = stmpe->ci->read_byte(stmpe, reg); reg 63 drivers/mfd/stmpe.c dev_err(stmpe->dev, "failed to read reg %#x: %d\n", reg, ret); reg 65 drivers/mfd/stmpe.c dev_vdbg(stmpe->dev, "rd: reg %#x => data %#x\n", reg, ret); reg 70 drivers/mfd/stmpe.c static int __stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val) reg 74 drivers/mfd/stmpe.c dev_vdbg(stmpe->dev, "wr: reg %#x <= %#x\n", reg, val); reg 76 drivers/mfd/stmpe.c ret = stmpe->ci->write_byte(stmpe, reg, val); reg 78 drivers/mfd/stmpe.c dev_err(stmpe->dev, "failed to write reg %#x: %d\n", reg, ret); reg 83 drivers/mfd/stmpe.c static int __stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) reg 87 drivers/mfd/stmpe.c ret = __stmpe_reg_read(stmpe, reg); reg 94 drivers/mfd/stmpe.c return __stmpe_reg_write(stmpe, reg, ret); reg 97 drivers/mfd/stmpe.c static int __stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, reg 102 drivers/mfd/stmpe.c ret = stmpe->ci->read_block(stmpe, reg, length, values); reg 104 drivers/mfd/stmpe.c dev_err(stmpe->dev, "failed to read regs %#x: %d\n", reg, ret); reg 106 drivers/mfd/stmpe.c dev_vdbg(stmpe->dev, "rd: reg %#x (%d) => ret %#x\n", reg, length, ret); reg 112 drivers/mfd/stmpe.c static int __stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length, reg 117 drivers/mfd/stmpe.c dev_vdbg(stmpe->dev, "wr: regs %#x (%d)\n", reg, length); reg 120 drivers/mfd/stmpe.c ret = stmpe->ci->write_block(stmpe, reg, length, values); reg 122 drivers/mfd/stmpe.c dev_err(stmpe->dev, "failed to write regs %#x: %d\n", reg, ret); reg 166 drivers/mfd/stmpe.c int stmpe_reg_read(struct stmpe *stmpe, u8 reg) reg 171 drivers/mfd/stmpe.c ret = __stmpe_reg_read(stmpe, reg); reg 184 drivers/mfd/stmpe.c int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val) reg 189 drivers/mfd/stmpe.c ret = __stmpe_reg_write(stmpe, reg, val); reg 203 drivers/mfd/stmpe.c int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) reg 208 drivers/mfd/stmpe.c ret = __stmpe_set_bits(stmpe, reg, mask, val); reg 222 drivers/mfd/stmpe.c int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values) reg 227 drivers/mfd/stmpe.c ret = __stmpe_block_read(stmpe, reg, length, values); reg 241 drivers/mfd/stmpe.c int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length, reg 247 drivers/mfd/stmpe.c ret = __stmpe_block_write(stmpe, reg, length, values); reg 92 drivers/mfd/stmpe.h int (*read_byte)(struct stmpe *stmpe, u8 reg); reg 93 drivers/mfd/stmpe.h int (*write_byte)(struct stmpe *stmpe, u8 reg, u8 val); reg 94 drivers/mfd/stmpe.h int (*read_block)(struct stmpe *stmpe, u8 reg, u8 len, u8 *values); reg 95 drivers/mfd/stmpe.h int (*write_block)(struct stmpe *stmpe, u8 reg, u8 len, reg 126 drivers/mfd/stpmic1.c u32 reg; reg 145 drivers/mfd/stpmic1.c ret = regmap_read(ddata->regmap, VERSION_SR, ®); reg 150 drivers/mfd/stpmic1.c dev_info(dev, "PMIC Chip Version: 0x%x\n", reg); reg 44 drivers/mfd/stw481x.c static int stw481x_get_pctl_reg(struct stw481x *stw481x, u8 reg) reg 46 drivers/mfd/stw481x.c u8 msb = (reg >> 3) & 0x03; reg 47 drivers/mfd/stw481x.c u8 lsb = (reg << 5) & 0xe0; reg 66 drivers/mfd/stw481x.c if (vrfy != reg) reg 42 drivers/mfd/tc3589x.c int tc3589x_reg_read(struct tc3589x *tc3589x, u8 reg) reg 46 drivers/mfd/tc3589x.c ret = i2c_smbus_read_byte_data(tc3589x->i2c, reg); reg 49 drivers/mfd/tc3589x.c reg, ret); reg 61 drivers/mfd/tc3589x.c int tc3589x_reg_write(struct tc3589x *tc3589x, u8 reg, u8 data) reg 65 drivers/mfd/tc3589x.c ret = i2c_smbus_write_byte_data(tc3589x->i2c, reg, data); reg 68 drivers/mfd/tc3589x.c reg, ret); reg 81 drivers/mfd/tc3589x.c int tc3589x_block_read(struct tc3589x *tc3589x, u8 reg, u8 length, u8 *values) reg 85 drivers/mfd/tc3589x.c ret = i2c_smbus_read_i2c_block_data(tc3589x->i2c, reg, length, values); reg 88 drivers/mfd/tc3589x.c reg, ret); reg 101 drivers/mfd/tc3589x.c int tc3589x_block_write(struct tc3589x *tc3589x, u8 reg, u8 length, reg 106 drivers/mfd/tc3589x.c ret = i2c_smbus_write_i2c_block_data(tc3589x->i2c, reg, length, reg 110 drivers/mfd/tc3589x.c reg, ret); reg 123 drivers/mfd/tc3589x.c int tc3589x_set_bits(struct tc3589x *tc3589x, u8 reg, u8 mask, u8 val) reg 129 drivers/mfd/tc3589x.c ret = tc3589x_reg_read(tc3589x, reg); reg 136 drivers/mfd/tc3589x.c ret = tc3589x_reg_write(tc3589x, reg, ret); reg 55 drivers/mfd/ti_am335x_tscadc.c u32 reg; reg 57 drivers/mfd/ti_am335x_tscadc.c regmap_read(tscadc->regmap, REG_ADCFSM, ®); reg 58 drivers/mfd/ti_am335x_tscadc.c if (reg & SEQ_STATUS) { reg 73 drivers/mfd/ti_am335x_tscadc.c regmap_read(tscadc->regmap, REG_ADCFSM, ®); reg 74 drivers/mfd/ti_am335x_tscadc.c WARN_ON((reg & SEQ_STATUS) && !(reg & CHARGE_STEP)); reg 37 drivers/mfd/tps6507x.c static int tps6507x_i2c_read_device(struct tps6507x_dev *tps6507x, char reg, reg 48 drivers/mfd/tps6507x.c xfer[0].buf = ® reg 65 drivers/mfd/tps6507x.c static int tps6507x_i2c_write_device(struct tps6507x_dev *tps6507x, char reg, reg 76 drivers/mfd/tps6507x.c msg[0] = reg; reg 134 drivers/mfd/tps65090.c static bool is_volatile_reg(struct device *dev, unsigned int reg) reg 137 drivers/mfd/tps65090.c switch (reg) { reg 198 drivers/mfd/tps65217.c int tps65217_reg_read(struct tps65217 *tps, unsigned int reg, reg 201 drivers/mfd/tps65217.c return regmap_read(tps->regmap, reg, val); reg 213 drivers/mfd/tps65217.c int tps65217_reg_write(struct tps65217 *tps, unsigned int reg, reg 221 drivers/mfd/tps65217.c return regmap_write(tps->regmap, reg, val); reg 223 drivers/mfd/tps65217.c xor_reg_val = reg ^ TPS65217_PASSWORD_REGS_UNLOCK; reg 229 drivers/mfd/tps65217.c return regmap_write(tps->regmap, reg, val); reg 231 drivers/mfd/tps65217.c xor_reg_val = reg ^ TPS65217_PASSWORD_REGS_UNLOCK; reg 236 drivers/mfd/tps65217.c ret = regmap_write(tps->regmap, reg, val); reg 243 drivers/mfd/tps65217.c return regmap_write(tps->regmap, reg, val); reg 259 drivers/mfd/tps65217.c static int tps65217_update_bits(struct tps65217 *tps, unsigned int reg, reg 265 drivers/mfd/tps65217.c ret = tps65217_reg_read(tps, reg, &data); reg 267 drivers/mfd/tps65217.c dev_err(tps->dev, "Read from reg 0x%x failed\n", reg); reg 274 drivers/mfd/tps65217.c ret = tps65217_reg_write(tps, reg, data, level); reg 276 drivers/mfd/tps65217.c dev_err(tps->dev, "Write for reg 0x%x failed\n", reg); reg 281 drivers/mfd/tps65217.c int tps65217_set_bits(struct tps65217 *tps, unsigned int reg, reg 284 drivers/mfd/tps65217.c return tps65217_update_bits(tps, reg, mask, val, level); reg 288 drivers/mfd/tps65217.c int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg, reg 291 drivers/mfd/tps65217.c return tps65217_update_bits(tps, reg, mask, 0, level); reg 295 drivers/mfd/tps65217.c static bool tps65217_volatile_reg(struct device *dev, unsigned int reg) reg 297 drivers/mfd/tps65217.c switch (reg) { reg 56 drivers/mfd/tps65218.c int tps65218_reg_write(struct tps65218 *tps, unsigned int reg, reg 64 drivers/mfd/tps65218.c return regmap_write(tps->regmap, reg, val); reg 66 drivers/mfd/tps65218.c xor_reg_val = reg ^ TPS65218_PASSWORD_REGS_UNLOCK; reg 72 drivers/mfd/tps65218.c return regmap_write(tps->regmap, reg, val); reg 88 drivers/mfd/tps65218.c static int tps65218_update_bits(struct tps65218 *tps, unsigned int reg, reg 94 drivers/mfd/tps65218.c ret = regmap_read(tps->regmap, reg, &data); reg 96 drivers/mfd/tps65218.c dev_err(tps->dev, "Read from reg 0x%x failed\n", reg); reg 104 drivers/mfd/tps65218.c ret = tps65218_reg_write(tps, reg, data, level); reg 106 drivers/mfd/tps65218.c dev_err(tps->dev, "Write for reg 0x%x failed\n", reg); reg 112 drivers/mfd/tps65218.c int tps65218_set_bits(struct tps65218 *tps, unsigned int reg, reg 115 drivers/mfd/tps65218.c return tps65218_update_bits(tps, reg, mask, val, level); reg 119 drivers/mfd/tps65218.c int tps65218_clear_bits(struct tps65218 *tps, unsigned int reg, reg 122 drivers/mfd/tps65218.c return tps65218_update_bits(tps, reg, mask, 0, level); reg 140 drivers/mfd/tps6586x.c int tps6586x_write(struct device *dev, int reg, uint8_t val) reg 144 drivers/mfd/tps6586x.c return regmap_write(tps6586x->regmap, reg, val); reg 148 drivers/mfd/tps6586x.c int tps6586x_writes(struct device *dev, int reg, int len, uint8_t *val) reg 152 drivers/mfd/tps6586x.c return regmap_bulk_write(tps6586x->regmap, reg, val, len); reg 156 drivers/mfd/tps6586x.c int tps6586x_read(struct device *dev, int reg, uint8_t *val) reg 162 drivers/mfd/tps6586x.c ret = regmap_read(tps6586x->regmap, reg, &rval); reg 169 drivers/mfd/tps6586x.c int tps6586x_reads(struct device *dev, int reg, int len, uint8_t *val) reg 173 drivers/mfd/tps6586x.c return regmap_bulk_read(tps6586x->regmap, reg, val, len); reg 177 drivers/mfd/tps6586x.c int tps6586x_set_bits(struct device *dev, int reg, uint8_t bit_mask) reg 181 drivers/mfd/tps6586x.c return regmap_update_bits(tps6586x->regmap, reg, bit_mask, bit_mask); reg 185 drivers/mfd/tps6586x.c int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask) reg 189 drivers/mfd/tps6586x.c return regmap_update_bits(tps6586x->regmap, reg, bit_mask, 0); reg 193 drivers/mfd/tps6586x.c int tps6586x_update(struct device *dev, int reg, uint8_t val, uint8_t mask) reg 197 drivers/mfd/tps6586x.c return regmap_update_bits(tps6586x->regmap, reg, mask, val); reg 446 drivers/mfd/tps6586x.c static bool is_volatile_reg(struct device *dev, unsigned int reg) reg 449 drivers/mfd/tps6586x.c if ((reg >= TPS6586X_INT_MASK1) && (reg <= TPS6586X_INT_MASK5)) reg 259 drivers/mfd/tps65910.c static bool is_volatile_reg(struct device *dev, unsigned int reg) reg 268 drivers/mfd/tps65910.c if ((reg >= TPS65910_VIO) && (reg <= TPS65910_VDAC)) { reg 271 drivers/mfd/tps65910.c if ((reg == TPS65911_VDDCTRL_OP) || reg 272 drivers/mfd/tps65910.c (reg == TPS65911_VDDCTRL_SR)) reg 33 drivers/mfd/tps65911-comparator.c int reg; reg 41 drivers/mfd/tps65911-comparator.c .reg = TPS65911_VMBCH, reg 47 drivers/mfd/tps65911-comparator.c .reg = TPS65911_VMBCH2, reg 72 drivers/mfd/tps65911-comparator.c ret = tps65910_reg_write(tps65910, tps_comp.reg, val); reg 83 drivers/mfd/tps65911-comparator.c ret = tps65910_reg_read(tps65910, tps_comp.reg, &val); reg 77 drivers/mfd/tps80031.c u8 reg; reg 127 drivers/mfd/tps80031.c .reg = TPS80031_CFG_INPUT_PUPD##_reg, \ reg 237 drivers/mfd/tps80031.c tps80031_update(tps80031->dev, TPS80031_SLAVE_ID1, pupd->reg, reg 313 drivers/mfd/tps80031.c static bool rd_wr_reg_id0(struct device *dev, unsigned int reg) reg 315 drivers/mfd/tps80031.c switch (reg) { reg 323 drivers/mfd/tps80031.c static bool rd_wr_reg_id1(struct device *dev, unsigned int reg) reg 325 drivers/mfd/tps80031.c switch (reg) { reg 343 drivers/mfd/tps80031.c static bool is_volatile_reg_id1(struct device *dev, unsigned int reg) reg 345 drivers/mfd/tps80031.c switch (reg) { reg 358 drivers/mfd/tps80031.c static bool rd_wr_reg_id2(struct device *dev, unsigned int reg) reg 360 drivers/mfd/tps80031.c switch (reg) { reg 375 drivers/mfd/tps80031.c static bool rd_wr_reg_id3(struct device *dev, unsigned int reg) reg 377 drivers/mfd/tps80031.c switch (reg) { reg 272 drivers/mfd/twl-core.c static bool twl4030_49_nop_reg(struct device *dev, unsigned int reg) reg 274 drivers/mfd/twl-core.c switch (reg) { reg 440 drivers/mfd/twl-core.c int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes) reg 448 drivers/mfd/twl-core.c ret = regmap_bulk_write(regmap, twl_priv->twl_map[mod_no].base + reg, reg 453 drivers/mfd/twl-core.c DRIVER_NAME, mod_no, reg, num_bytes); reg 468 drivers/mfd/twl-core.c int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes) reg 476 drivers/mfd/twl-core.c ret = regmap_bulk_read(regmap, twl_priv->twl_map[mod_no].base + reg, reg 481 drivers/mfd/twl-core.c DRIVER_NAME, mod_no, reg, num_bytes); reg 29 drivers/mfd/twl4030-audio.c u8 reg; reg 50 drivers/mfd/twl4030-audio.c audio->resource[id].reg); reg 58 drivers/mfd/twl4030-audio.c val, audio->resource[id].reg); reg 69 drivers/mfd/twl4030-audio.c audio->resource[id].reg); reg 218 drivers/mfd/twl4030-audio.c audio->resource[TWL4030_AUDIO_RES_POWER].reg = TWL4030_REG_CODEC_MODE; reg 222 drivers/mfd/twl4030-audio.c audio->resource[TWL4030_AUDIO_RES_APLL].reg = TWL4030_REG_APLL_CTL; reg 30 drivers/mfd/twl6040.c #define VIBRACTRL_MEMBER(reg) ((reg == TWL6040_REG_VIBCTLL) ? 0 : 1) reg 99 drivers/mfd/twl6040.c int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg) reg 104 drivers/mfd/twl6040.c ret = regmap_read(twl6040->regmap, reg, &val); reg 112 drivers/mfd/twl6040.c int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg, u8 val) reg 116 drivers/mfd/twl6040.c ret = regmap_write(twl6040->regmap, reg, val); reg 122 drivers/mfd/twl6040.c int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask) reg 124 drivers/mfd/twl6040.c return regmap_update_bits(twl6040->regmap, reg, mask, mask); reg 128 drivers/mfd/twl6040.c int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask) reg 130 drivers/mfd/twl6040.c return regmap_update_bits(twl6040->regmap, reg, mask, 0); reg 532 drivers/mfd/twl6040.c unsigned int reg; reg 536 drivers/mfd/twl6040.c ret = regmap_read(twl6040->regmap, TWL6040_REG_VIBCTLL, ®); reg 539 drivers/mfd/twl6040.c status = reg; reg 541 drivers/mfd/twl6040.c ret = regmap_read(twl6040->regmap, TWL6040_REG_VIBCTLR, ®); reg 544 drivers/mfd/twl6040.c status |= reg; reg 564 drivers/mfd/twl6040.c static bool twl6040_readable_reg(struct device *dev, unsigned int reg) reg 567 drivers/mfd/twl6040.c if (!reg) reg 572 drivers/mfd/twl6040.c static bool twl6040_volatile_reg(struct device *dev, unsigned int reg) reg 574 drivers/mfd/twl6040.c switch (reg) { reg 587 drivers/mfd/twl6040.c static bool twl6040_writeable_reg(struct device *dev, unsigned int reg) reg 589 drivers/mfd/twl6040.c switch (reg) { reg 21 drivers/mfd/wl1273-core.c static int wl1273_fm_read_reg(struct wl1273_core *core, u8 reg, u16 *value) reg 27 drivers/mfd/wl1273-core.c r = i2c_smbus_read_i2c_block_data(client, reg, sizeof(b), b); reg 29 drivers/mfd/wl1273-core.c dev_err(&client->dev, "%s: Read: %d fails.\n", __func__, reg); reg 992 drivers/mfd/wm5102-tables.c static bool wm5102_readable_register(struct device *dev, unsigned int reg) reg 994 drivers/mfd/wm5102-tables.c switch (reg) { reg 1815 drivers/mfd/wm5102-tables.c if ((reg >= 0x100000 && reg < 0x106000) || reg 1816 drivers/mfd/wm5102-tables.c (reg >= 0x180000 && reg < 0x180800) || reg 1817 drivers/mfd/wm5102-tables.c (reg >= 0x190000 && reg < 0x194800) || reg 1818 drivers/mfd/wm5102-tables.c (reg >= 0x1a8000 && reg < 0x1a9800)) reg 1825 drivers/mfd/wm5102-tables.c static bool wm5102_volatile_register(struct device *dev, unsigned int reg) reg 1827 drivers/mfd/wm5102-tables.c switch (reg) { reg 1902 drivers/mfd/wm5102-tables.c if ((reg >= 0x100000 && reg < 0x106000) || reg 1903 drivers/mfd/wm5102-tables.c (reg >= 0x180000 && reg < 0x180800) || reg 1904 drivers/mfd/wm5102-tables.c (reg >= 0x190000 && reg < 0x194800) || reg 1905 drivers/mfd/wm5102-tables.c (reg >= 0x1a8000 && reg < 0x1a9800)) reg 1815 drivers/mfd/wm5110-tables.c static bool wm5110_is_rev_b_adsp_memory(unsigned int reg) reg 1817 drivers/mfd/wm5110-tables.c if ((reg >= 0x100000 && reg < 0x103000) || reg 1818 drivers/mfd/wm5110-tables.c (reg >= 0x180000 && reg < 0x181000) || reg 1819 drivers/mfd/wm5110-tables.c (reg >= 0x190000 && reg < 0x192000) || reg 1820 drivers/mfd/wm5110-tables.c (reg >= 0x1a8000 && reg < 0x1a9000) || reg 1821 drivers/mfd/wm5110-tables.c (reg >= 0x200000 && reg < 0x209000) || reg 1822 drivers/mfd/wm5110-tables.c (reg >= 0x280000 && reg < 0x281000) || reg 1823 drivers/mfd/wm5110-tables.c (reg >= 0x290000 && reg < 0x29a000) || reg 1824 drivers/mfd/wm5110-tables.c (reg >= 0x2a8000 && reg < 0x2aa000) || reg 1825 drivers/mfd/wm5110-tables.c (reg >= 0x300000 && reg < 0x30f000) || reg 1826 drivers/mfd/wm5110-tables.c (reg >= 0x380000 && reg < 0x382000) || reg 1827 drivers/mfd/wm5110-tables.c (reg >= 0x390000 && reg < 0x39e000) || reg 1828 drivers/mfd/wm5110-tables.c (reg >= 0x3a8000 && reg < 0x3b6000) || reg 1829 drivers/mfd/wm5110-tables.c (reg >= 0x400000 && reg < 0x403000) || reg 1830 drivers/mfd/wm5110-tables.c (reg >= 0x480000 && reg < 0x481000) || reg 1831 drivers/mfd/wm5110-tables.c (reg >= 0x490000 && reg < 0x492000) || reg 1832 drivers/mfd/wm5110-tables.c (reg >= 0x4a8000 && reg < 0x4a9000)) reg 1838 drivers/mfd/wm5110-tables.c static bool wm5110_is_rev_d_adsp_memory(unsigned int reg) reg 1840 drivers/mfd/wm5110-tables.c if ((reg >= 0x100000 && reg < 0x106000) || reg 1841 drivers/mfd/wm5110-tables.c (reg >= 0x180000 && reg < 0x182000) || reg 1842 drivers/mfd/wm5110-tables.c (reg >= 0x190000 && reg < 0x198000) || reg 1843 drivers/mfd/wm5110-tables.c (reg >= 0x1a8000 && reg < 0x1aa000) || reg 1844 drivers/mfd/wm5110-tables.c (reg >= 0x200000 && reg < 0x20f000) || reg 1845 drivers/mfd/wm5110-tables.c (reg >= 0x280000 && reg < 0x282000) || reg 1846 drivers/mfd/wm5110-tables.c (reg >= 0x290000 && reg < 0x29c000) || reg 1847 drivers/mfd/wm5110-tables.c (reg >= 0x2a6000 && reg < 0x2b4000) || reg 1848 drivers/mfd/wm5110-tables.c (reg >= 0x300000 && reg < 0x30f000) || reg 1849 drivers/mfd/wm5110-tables.c (reg >= 0x380000 && reg < 0x382000) || reg 1850 drivers/mfd/wm5110-tables.c (reg >= 0x390000 && reg < 0x3a2000) || reg 1851 drivers/mfd/wm5110-tables.c (reg >= 0x3a6000 && reg < 0x3b4000) || reg 1852 drivers/mfd/wm5110-tables.c (reg >= 0x400000 && reg < 0x406000) || reg 1853 drivers/mfd/wm5110-tables.c (reg >= 0x480000 && reg < 0x482000) || reg 1854 drivers/mfd/wm5110-tables.c (reg >= 0x490000 && reg < 0x498000) || reg 1855 drivers/mfd/wm5110-tables.c (reg >= 0x4a8000 && reg < 0x4aa000)) reg 1861 drivers/mfd/wm5110-tables.c static bool wm5110_is_adsp_memory(struct device *dev, unsigned int reg) reg 1867 drivers/mfd/wm5110-tables.c return wm5110_is_rev_b_adsp_memory(reg); reg 1869 drivers/mfd/wm5110-tables.c return wm5110_is_rev_d_adsp_memory(reg); reg 1873 drivers/mfd/wm5110-tables.c static bool wm5110_readable_register(struct device *dev, unsigned int reg) reg 1875 drivers/mfd/wm5110-tables.c switch (reg) { reg 3012 drivers/mfd/wm5110-tables.c return wm5110_is_adsp_memory(dev, reg); reg 3016 drivers/mfd/wm5110-tables.c static bool wm5110_volatile_register(struct device *dev, unsigned int reg) reg 3018 drivers/mfd/wm5110-tables.c switch (reg) { reg 3188 drivers/mfd/wm5110-tables.c return wm5110_is_adsp_memory(dev, reg); reg 92 drivers/mfd/wm831x-core.c static int wm831x_reg_locked(struct wm831x *wm831x, unsigned short reg) reg 97 drivers/mfd/wm831x-core.c switch (reg) { reg 163 drivers/mfd/wm831x-core.c static bool wm831x_reg_readable(struct device *dev, unsigned int reg) reg 165 drivers/mfd/wm831x-core.c switch (reg) { reg 342 drivers/mfd/wm831x-core.c static bool wm831x_reg_writeable(struct device *dev, unsigned int reg) reg 346 drivers/mfd/wm831x-core.c if (wm831x_reg_locked(wm831x, reg)) reg 349 drivers/mfd/wm831x-core.c switch (reg) { reg 479 drivers/mfd/wm831x-core.c static bool wm831x_reg_volatile(struct device *dev, unsigned int reg) reg 481 drivers/mfd/wm831x-core.c switch (reg) { reg 515 drivers/mfd/wm831x-core.c int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg) reg 520 drivers/mfd/wm831x-core.c ret = regmap_read(wm831x->regmap, reg, &val); reg 537 drivers/mfd/wm831x-core.c int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg, reg 540 drivers/mfd/wm831x-core.c return regmap_bulk_read(wm831x->regmap, reg, buf, count); reg 544 drivers/mfd/wm831x-core.c static int wm831x_write(struct wm831x *wm831x, unsigned short reg, reg 554 drivers/mfd/wm831x-core.c if (wm831x_reg_locked(wm831x, reg)) reg 558 drivers/mfd/wm831x-core.c buf[i], reg + i, reg + i); reg 559 drivers/mfd/wm831x-core.c ret = regmap_write(wm831x->regmap, reg + i, buf[i]); reg 574 drivers/mfd/wm831x-core.c int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg, reg 581 drivers/mfd/wm831x-core.c ret = wm831x_write(wm831x, reg, 2, &val); reg 597 drivers/mfd/wm831x-core.c int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg, reg 604 drivers/mfd/wm831x-core.c if (!wm831x_reg_locked(wm831x, reg)) reg 605 drivers/mfd/wm831x-core.c ret = regmap_update_bits(wm831x->regmap, reg, mask, val); reg 1893 drivers/mfd/wm831x-core.c int reg, mask; reg 1901 drivers/mfd/wm831x-core.c reg = wm831x_reg_read(wm831x, WM831X_INTERRUPT_STATUS_2_MASK); reg 1911 drivers/mfd/wm831x-core.c if (reg & mask) reg 1912 drivers/mfd/wm831x-core.c reg = wm831x_reg_read(wm831x, reg 1915 drivers/mfd/wm831x-core.c if (reg & mask) { reg 1918 drivers/mfd/wm831x-core.c reg & mask); reg 1920 drivers/mfd/wm831x-core.c reg & mask); reg 27 drivers/mfd/wm831x-irq.c int reg; reg 34 drivers/mfd/wm831x-irq.c .reg = 1, reg 39 drivers/mfd/wm831x-irq.c .reg = 5, reg 44 drivers/mfd/wm831x-irq.c .reg = 5, reg 49 drivers/mfd/wm831x-irq.c .reg = 5, reg 54 drivers/mfd/wm831x-irq.c .reg = 5, reg 59 drivers/mfd/wm831x-irq.c .reg = 5, reg 64 drivers/mfd/wm831x-irq.c .reg = 5, reg 69 drivers/mfd/wm831x-irq.c .reg = 5, reg 74 drivers/mfd/wm831x-irq.c .reg = 5, reg 79 drivers/mfd/wm831x-irq.c .reg = 5, reg 84 drivers/mfd/wm831x-irq.c .reg = 5, reg 89 drivers/mfd/wm831x-irq.c .reg = 5, reg 94 drivers/mfd/wm831x-irq.c .reg = 5, reg 99 drivers/mfd/wm831x-irq.c .reg = 5, reg 104 drivers/mfd/wm831x-irq.c .reg = 5, reg 109 drivers/mfd/wm831x-irq.c .reg = 5, reg 114 drivers/mfd/wm831x-irq.c .reg = 5, reg 119 drivers/mfd/wm831x-irq.c .reg = 1, reg 124 drivers/mfd/wm831x-irq.c .reg = 1, reg 129 drivers/mfd/wm831x-irq.c .reg = 1, reg 134 drivers/mfd/wm831x-irq.c .reg = 1, reg 139 drivers/mfd/wm831x-irq.c .reg = 1, reg 144 drivers/mfd/wm831x-irq.c .reg = 1, reg 149 drivers/mfd/wm831x-irq.c .reg = 1, reg 154 drivers/mfd/wm831x-irq.c .reg = 2, reg 159 drivers/mfd/wm831x-irq.c .reg = 2, reg 164 drivers/mfd/wm831x-irq.c .reg = 2, reg 169 drivers/mfd/wm831x-irq.c .reg = 2, reg 174 drivers/mfd/wm831x-irq.c .reg = 2, reg 179 drivers/mfd/wm831x-irq.c .reg = 2, reg 184 drivers/mfd/wm831x-irq.c .reg = 2, reg 189 drivers/mfd/wm831x-irq.c .reg = 2, reg 194 drivers/mfd/wm831x-irq.c .reg = 1, reg 199 drivers/mfd/wm831x-irq.c .reg = 1, reg 204 drivers/mfd/wm831x-irq.c .reg = 1, reg 209 drivers/mfd/wm831x-irq.c .reg = 1, reg 214 drivers/mfd/wm831x-irq.c .reg = 1, reg 219 drivers/mfd/wm831x-irq.c .reg = 1, reg 224 drivers/mfd/wm831x-irq.c .reg = 1, reg 229 drivers/mfd/wm831x-irq.c .reg = 2, reg 234 drivers/mfd/wm831x-irq.c .reg = 2, reg 239 drivers/mfd/wm831x-irq.c .reg = 4, reg 244 drivers/mfd/wm831x-irq.c .reg = 4, reg 249 drivers/mfd/wm831x-irq.c .reg = 3, reg 254 drivers/mfd/wm831x-irq.c .reg = 3, reg 259 drivers/mfd/wm831x-irq.c .reg = 3, reg 264 drivers/mfd/wm831x-irq.c .reg = 3, reg 269 drivers/mfd/wm831x-irq.c .reg = 3, reg 274 drivers/mfd/wm831x-irq.c .reg = 3, reg 279 drivers/mfd/wm831x-irq.c .reg = 3, reg 284 drivers/mfd/wm831x-irq.c .reg = 3, reg 289 drivers/mfd/wm831x-irq.c .reg = 3, reg 294 drivers/mfd/wm831x-irq.c .reg = 3, reg 299 drivers/mfd/wm831x-irq.c .reg = 4, reg 304 drivers/mfd/wm831x-irq.c .reg = 4, reg 309 drivers/mfd/wm831x-irq.c .reg = 4, reg 314 drivers/mfd/wm831x-irq.c .reg = 4, reg 321 drivers/mfd/wm831x-irq.c return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg; reg 375 drivers/mfd/wm831x-irq.c wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask; reg 384 drivers/mfd/wm831x-irq.c wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask; reg 479 drivers/mfd/wm831x-irq.c int offset = wm831x_irqs[i].reg - 1; reg 63 drivers/mfd/wm8350-core.c int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask) reg 65 drivers/mfd/wm8350-core.c return regmap_update_bits(wm8350->regmap, reg, mask, 0); reg 69 drivers/mfd/wm8350-core.c int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask) reg 71 drivers/mfd/wm8350-core.c return regmap_update_bits(wm8350->regmap, reg, mask, mask); reg 75 drivers/mfd/wm8350-core.c u16 wm8350_reg_read(struct wm8350 *wm8350, int reg) reg 80 drivers/mfd/wm8350-core.c err = regmap_read(wm8350->regmap, reg, &data); reg 82 drivers/mfd/wm8350-core.c dev_err(wm8350->dev, "read from reg R%d failed\n", reg); reg 88 drivers/mfd/wm8350-core.c int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val) reg 92 drivers/mfd/wm8350-core.c ret = regmap_write(wm8350->regmap, reg, val); reg 95 drivers/mfd/wm8350-core.c dev_err(wm8350->dev, "write to reg R%d failed\n", reg); reg 186 drivers/mfd/wm8350-core.c u16 reg, result = 0; reg 197 drivers/mfd/wm8350-core.c reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5); reg 198 drivers/mfd/wm8350-core.c wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5, reg | WM8350_AUXADC_ENA); reg 201 drivers/mfd/wm8350-core.c reg = scale << 13; reg 202 drivers/mfd/wm8350-core.c reg |= vref << 12; reg 203 drivers/mfd/wm8350-core.c wm8350_reg_write(wm8350, WM8350_AUX1_READBACK + channel, reg); reg 206 drivers/mfd/wm8350-core.c reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1); reg 207 drivers/mfd/wm8350-core.c reg |= 1 << channel | WM8350_AUXADC_POLL; reg 208 drivers/mfd/wm8350-core.c wm8350_reg_write(wm8350, WM8350_DIGITISER_CONTROL_1, reg); reg 219 drivers/mfd/wm8350-core.c reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1); reg 220 drivers/mfd/wm8350-core.c if (reg & WM8350_AUXADC_POLL) reg 227 drivers/mfd/wm8350-core.c reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5); reg 229 drivers/mfd/wm8350-core.c reg & ~WM8350_AUXADC_ENA); reg 47 drivers/mfd/wm8350-gpio.c u16 reg; reg 52 drivers/mfd/wm8350-gpio.c reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1) reg 55 drivers/mfd/wm8350-gpio.c reg | ((func & 0xf) << 0)); reg 58 drivers/mfd/wm8350-gpio.c reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1) reg 61 drivers/mfd/wm8350-gpio.c reg | ((func & 0xf) << 4)); reg 64 drivers/mfd/wm8350-gpio.c reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1) reg 67 drivers/mfd/wm8350-gpio.c reg | ((func & 0xf) << 8)); reg 70 drivers/mfd/wm8350-gpio.c reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_1) reg 73 drivers/mfd/wm8350-gpio.c reg | ((func & 0xf) << 12)); reg 76 drivers/mfd/wm8350-gpio.c reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2) reg 79 drivers/mfd/wm8350-gpio.c reg | ((func & 0xf) << 0)); reg 82 drivers/mfd/wm8350-gpio.c reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2) reg 85 drivers/mfd/wm8350-gpio.c reg | ((func & 0xf) << 4)); reg 88 drivers/mfd/wm8350-gpio.c reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2) reg 91 drivers/mfd/wm8350-gpio.c reg | ((func & 0xf) << 8)); reg 94 drivers/mfd/wm8350-gpio.c reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_2) reg 97 drivers/mfd/wm8350-gpio.c reg | ((func & 0xf) << 12)); reg 100 drivers/mfd/wm8350-gpio.c reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3) reg 103 drivers/mfd/wm8350-gpio.c reg | ((func & 0xf) << 0)); reg 106 drivers/mfd/wm8350-gpio.c reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3) reg 109 drivers/mfd/wm8350-gpio.c reg | ((func & 0xf) << 4)); reg 112 drivers/mfd/wm8350-gpio.c reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3) reg 115 drivers/mfd/wm8350-gpio.c reg | ((func & 0xf) << 8)); reg 118 drivers/mfd/wm8350-gpio.c reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_3) reg 121 drivers/mfd/wm8350-gpio.c reg | ((func & 0xf) << 12)); reg 124 drivers/mfd/wm8350-gpio.c reg = wm8350_reg_read(wm8350, WM8350_GPIO_FUNCTION_SELECT_4) reg 127 drivers/mfd/wm8350-gpio.c reg | ((func & 0xf) << 0)); reg 36 drivers/mfd/wm8350-irq.c int reg; reg 44 drivers/mfd/wm8350-irq.c .reg = WM8350_OVER_CURRENT_INT_OFFSET, reg 50 drivers/mfd/wm8350-irq.c .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, reg 55 drivers/mfd/wm8350-irq.c .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, reg 60 drivers/mfd/wm8350-irq.c .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, reg 65 drivers/mfd/wm8350-irq.c .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, reg 70 drivers/mfd/wm8350-irq.c .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, reg 75 drivers/mfd/wm8350-irq.c .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, reg 80 drivers/mfd/wm8350-irq.c .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, reg 85 drivers/mfd/wm8350-irq.c .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, reg 90 drivers/mfd/wm8350-irq.c .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, reg 95 drivers/mfd/wm8350-irq.c .reg = WM8350_UNDER_VOLTAGE_INT_OFFSET, reg 100 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_1, reg 105 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_1, reg 110 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_1, reg 115 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_1, reg 120 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_1, reg 125 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_1, reg 130 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_1, reg 135 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_1, reg 140 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_1, reg 145 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_1, reg 150 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_1, reg 155 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_1, reg 160 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_1, reg 165 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_2, reg 170 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_2, reg 175 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_2, reg 180 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_2, reg 185 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_2, reg 190 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_2, reg 195 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_2, reg 200 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_2, reg 205 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_2, reg 210 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_2, reg 215 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_2, reg 220 drivers/mfd/wm8350-irq.c .reg = WM8350_INT_OFFSET_2, reg 226 drivers/mfd/wm8350-irq.c .reg = WM8350_COMPARATOR_INT_OFFSET, reg 231 drivers/mfd/wm8350-irq.c .reg = WM8350_COMPARATOR_INT_OFFSET, reg 236 drivers/mfd/wm8350-irq.c .reg = WM8350_COMPARATOR_INT_OFFSET, reg 241 drivers/mfd/wm8350-irq.c .reg = WM8350_COMPARATOR_INT_OFFSET, reg 246 drivers/mfd/wm8350-irq.c .reg = WM8350_COMPARATOR_INT_OFFSET, reg 251 drivers/mfd/wm8350-irq.c .reg = WM8350_COMPARATOR_INT_OFFSET, reg 256 drivers/mfd/wm8350-irq.c .reg = WM8350_COMPARATOR_INT_OFFSET, reg 261 drivers/mfd/wm8350-irq.c .reg = WM8350_COMPARATOR_INT_OFFSET, reg 266 drivers/mfd/wm8350-irq.c .reg = WM8350_COMPARATOR_INT_OFFSET, reg 271 drivers/mfd/wm8350-irq.c .reg = WM8350_COMPARATOR_INT_OFFSET, reg 276 drivers/mfd/wm8350-irq.c .reg = WM8350_COMPARATOR_INT_OFFSET, reg 281 drivers/mfd/wm8350-irq.c .reg = WM8350_COMPARATOR_INT_OFFSET, reg 286 drivers/mfd/wm8350-irq.c .reg = WM8350_COMPARATOR_INT_OFFSET, reg 291 drivers/mfd/wm8350-irq.c .reg = WM8350_COMPARATOR_INT_OFFSET, reg 296 drivers/mfd/wm8350-irq.c .reg = WM8350_GPIO_INT_OFFSET, reg 301 drivers/mfd/wm8350-irq.c .reg = WM8350_GPIO_INT_OFFSET, reg 306 drivers/mfd/wm8350-irq.c .reg = WM8350_GPIO_INT_OFFSET, reg 311 drivers/mfd/wm8350-irq.c .reg = WM8350_GPIO_INT_OFFSET, reg 316 drivers/mfd/wm8350-irq.c .reg = WM8350_GPIO_INT_OFFSET, reg 321 drivers/mfd/wm8350-irq.c .reg = WM8350_GPIO_INT_OFFSET, reg 326 drivers/mfd/wm8350-irq.c .reg = WM8350_GPIO_INT_OFFSET, reg 331 drivers/mfd/wm8350-irq.c .reg = WM8350_GPIO_INT_OFFSET, reg 336 drivers/mfd/wm8350-irq.c .reg = WM8350_GPIO_INT_OFFSET, reg 341 drivers/mfd/wm8350-irq.c .reg = WM8350_GPIO_INT_OFFSET, reg 346 drivers/mfd/wm8350-irq.c .reg = WM8350_GPIO_INT_OFFSET, reg 351 drivers/mfd/wm8350-irq.c .reg = WM8350_GPIO_INT_OFFSET, reg 356 drivers/mfd/wm8350-irq.c .reg = WM8350_GPIO_INT_OFFSET, reg 399 drivers/mfd/wm8350-irq.c if (!read_done[data->reg]) { reg 400 drivers/mfd/wm8350-irq.c sub_reg[data->reg] = reg 402 drivers/mfd/wm8350-irq.c data->reg); reg 403 drivers/mfd/wm8350-irq.c sub_reg[data->reg] &= ~wm8350->irq_masks[data->reg]; reg 404 drivers/mfd/wm8350-irq.c read_done[data->reg] = 1; reg 407 drivers/mfd/wm8350-irq.c if (sub_reg[data->reg] & data->mask) reg 443 drivers/mfd/wm8350-irq.c wm8350->irq_masks[irq_data->reg] &= ~irq_data->mask; reg 452 drivers/mfd/wm8350-irq.c wm8350->irq_masks[irq_data->reg] |= irq_data->mask; reg 281 drivers/mfd/wm8350-regmap.c static bool wm8350_readable(struct device *dev, unsigned int reg) reg 283 drivers/mfd/wm8350-regmap.c return wm8350_reg_io_map[reg].readable; reg 286 drivers/mfd/wm8350-regmap.c static bool wm8350_writeable(struct device *dev, unsigned int reg) reg 291 drivers/mfd/wm8350-regmap.c if ((reg >= WM8350_GPIO_FUNCTION_SELECT_1 && reg 292 drivers/mfd/wm8350-regmap.c reg <= WM8350_GPIO_FUNCTION_SELECT_4) || reg 293 drivers/mfd/wm8350-regmap.c (reg >= WM8350_BATTERY_CHARGER_CONTROL_1 && reg 294 drivers/mfd/wm8350-regmap.c reg <= WM8350_BATTERY_CHARGER_CONTROL_3)) reg 298 drivers/mfd/wm8350-regmap.c return wm8350_reg_io_map[reg].writable; reg 301 drivers/mfd/wm8350-regmap.c static bool wm8350_volatile(struct device *dev, unsigned int reg) reg 303 drivers/mfd/wm8350-regmap.c return wm8350_reg_io_map[reg].vol; reg 306 drivers/mfd/wm8350-regmap.c static bool wm8350_precious(struct device *dev, unsigned int reg) reg 308 drivers/mfd/wm8350-regmap.c switch (reg) { reg 21 drivers/mfd/wm8400-core.c static bool wm8400_volatile(struct device *dev, unsigned int reg) reg 23 drivers/mfd/wm8400-core.c switch (reg) { reg 54 drivers/mfd/wm8400-core.c unsigned int reg; reg 60 drivers/mfd/wm8400-core.c ret = regmap_read(wm8400->regmap, WM8400_RESET_ID, ®); reg 65 drivers/mfd/wm8400-core.c if (reg != 0x6172) { reg 67 drivers/mfd/wm8400-core.c reg); reg 71 drivers/mfd/wm8400-core.c ret = regmap_read(wm8400->regmap, WM8400_ID, ®); reg 76 drivers/mfd/wm8400-core.c reg = (reg & WM8400_CHIP_REV_MASK) >> WM8400_CHIP_REV_SHIFT; reg 77 drivers/mfd/wm8400-core.c dev_info(wm8400->dev, "WM8400 revision %x\n", reg); reg 764 drivers/mfd/wm8994-regmap.c static bool wm1811_readable_register(struct device *dev, unsigned int reg) reg 766 drivers/mfd/wm8994-regmap.c switch (reg) { reg 1011 drivers/mfd/wm8994-regmap.c static bool wm8994_readable_register(struct device *dev, unsigned int reg) reg 1013 drivers/mfd/wm8994-regmap.c switch (reg) { reg 1061 drivers/mfd/wm8994-regmap.c return wm1811_readable_register(dev, reg); reg 1065 drivers/mfd/wm8994-regmap.c static bool wm8958_readable_register(struct device *dev, unsigned int reg) reg 1067 drivers/mfd/wm8994-regmap.c switch (reg) { reg 1171 drivers/mfd/wm8994-regmap.c return wm8994_readable_register(dev, reg); reg 1175 drivers/mfd/wm8994-regmap.c static bool wm8994_volatile_register(struct device *dev, unsigned int reg) reg 1177 drivers/mfd/wm8994-regmap.c switch (reg) { reg 1192 drivers/mfd/wm8994-regmap.c static bool wm1811_volatile_register(struct device *dev, unsigned int reg) reg 1196 drivers/mfd/wm8994-regmap.c switch (reg) { reg 1203 drivers/mfd/wm8994-regmap.c return wm8994_volatile_register(dev, reg); reg 1207 drivers/mfd/wm8994-regmap.c static bool wm8958_volatile_register(struct device *dev, unsigned int reg) reg 1209 drivers/mfd/wm8994-regmap.c switch (reg) { reg 1233 drivers/mfd/wm8994-regmap.c return wm8994_volatile_register(dev, reg); reg 788 drivers/mfd/wm8997-tables.c static bool wm8997_readable_register(struct device *dev, unsigned int reg) reg 790 drivers/mfd/wm8997-tables.c switch (reg) { reg 1466 drivers/mfd/wm8997-tables.c static bool wm8997_volatile_register(struct device *dev, unsigned int reg) reg 1468 drivers/mfd/wm8997-tables.c switch (reg) { reg 817 drivers/mfd/wm8998-tables.c static bool wm8998_readable_register(struct device *dev, unsigned int reg) reg 819 drivers/mfd/wm8998-tables.c switch (reg) { reg 1507 drivers/mfd/wm8998-tables.c static bool wm8998_volatile_register(struct device *dev, unsigned int reg) reg 1509 drivers/mfd/wm8998-tables.c switch (reg) { reg 35 drivers/mfd/wm97xx-core.c static bool wm97xx_readable_reg(struct device *dev, unsigned int reg) reg 37 drivers/mfd/wm97xx-core.c switch (reg) { reg 51 drivers/mfd/wm97xx-core.c static bool wm97xx_writeable_reg(struct device *dev, unsigned int reg) reg 53 drivers/mfd/wm97xx-core.c switch (reg) { reg 58 drivers/mfd/wm97xx-core.c return wm97xx_readable_reg(dev, reg); reg 112 drivers/mfd/wm97xx-core.c static bool wm9712_volatile_reg(struct device *dev, unsigned int reg) reg 114 drivers/mfd/wm97xx-core.c switch (reg) { reg 118 drivers/mfd/wm97xx-core.c return regmap_ac97_default_volatile(dev, reg); reg 19 drivers/misc/ad525x_dpot-i2c.c static int write_r8d8(void *client, u8 reg, u8 val) reg 21 drivers/misc/ad525x_dpot-i2c.c return i2c_smbus_write_byte_data(client, reg, val); reg 24 drivers/misc/ad525x_dpot-i2c.c static int write_r8d16(void *client, u8 reg, u16 val) reg 26 drivers/misc/ad525x_dpot-i2c.c return i2c_smbus_write_word_data(client, reg, val); reg 34 drivers/misc/ad525x_dpot-i2c.c static int read_r8d8(void *client, u8 reg) reg 36 drivers/misc/ad525x_dpot-i2c.c return i2c_smbus_read_byte_data(client, reg); reg 39 drivers/misc/ad525x_dpot-i2c.c static int read_r8d16(void *client, u8 reg) reg 41 drivers/misc/ad525x_dpot-i2c.c return i2c_smbus_read_word_data(client, reg); reg 21 drivers/misc/ad525x_dpot-spi.c static int write16(void *client, u8 reg, u8 val) reg 23 drivers/misc/ad525x_dpot-spi.c u8 data[2] = {reg, val}; reg 28 drivers/misc/ad525x_dpot-spi.c static int write24(void *client, u8 reg, u16 val) reg 30 drivers/misc/ad525x_dpot-spi.c u8 data[3] = {reg, val >> 8, val}; reg 47 drivers/misc/ad525x_dpot-spi.c static int read16(void *client, u8 reg) reg 52 drivers/misc/ad525x_dpot-spi.c write16(client, reg, 0); reg 60 drivers/misc/ad525x_dpot-spi.c static int read24(void *client, u8 reg) reg 65 drivers/misc/ad525x_dpot-spi.c write24(client, reg, 0); reg 101 drivers/misc/ad525x_dpot.c static inline int dpot_read_r8d8(struct dpot_data *dpot, u8 reg) reg 103 drivers/misc/ad525x_dpot.c return dpot->bdata.bops->read_r8d8(dpot->bdata.client, reg); reg 106 drivers/misc/ad525x_dpot.c static inline int dpot_read_r8d16(struct dpot_data *dpot, u8 reg) reg 108 drivers/misc/ad525x_dpot.c return dpot->bdata.bops->read_r8d16(dpot->bdata.client, reg); reg 116 drivers/misc/ad525x_dpot.c static inline int dpot_write_r8d8(struct dpot_data *dpot, u8 reg, u16 val) reg 118 drivers/misc/ad525x_dpot.c return dpot->bdata.bops->write_r8d8(dpot->bdata.client, reg, val); reg 121 drivers/misc/ad525x_dpot.c static inline int dpot_write_r8d16(struct dpot_data *dpot, u8 reg, u16 val) reg 123 drivers/misc/ad525x_dpot.c return dpot->bdata.bops->write_r8d16(dpot->bdata.client, reg, val); reg 126 drivers/misc/ad525x_dpot.c static s32 dpot_read_spi(struct dpot_data *dpot, u8 reg) reg 131 drivers/misc/ad525x_dpot.c if (!(reg & (DPOT_ADDR_EEPROM | DPOT_ADDR_CMD))) { reg 134 drivers/misc/ad525x_dpot.c return dpot->rdac_cache[reg & DPOT_RDAC_MASK]; reg 162 drivers/misc/ad525x_dpot.c } else if (reg & DPOT_ADDR_EEPROM) { reg 174 drivers/misc/ad525x_dpot.c static s32 dpot_read_i2c(struct dpot_data *dpot, u8 reg) reg 190 drivers/misc/ad525x_dpot.c ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ? reg 199 drivers/misc/ad525x_dpot.c ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ? reg 220 drivers/misc/ad525x_dpot.c if ((reg & DPOT_REG_TOL) || (dpot->max_pos > 256)) reg 221 drivers/misc/ad525x_dpot.c return dpot_read_r8d16(dpot, (reg & 0xF8) | reg 222 drivers/misc/ad525x_dpot.c ((reg & 0x7) << 1)); reg 224 drivers/misc/ad525x_dpot.c return dpot_read_r8d8(dpot, reg); reg 228 drivers/misc/ad525x_dpot.c static s32 dpot_read(struct dpot_data *dpot, u8 reg) reg 231 drivers/misc/ad525x_dpot.c return dpot_read_spi(dpot, reg); reg 233 drivers/misc/ad525x_dpot.c return dpot_read_i2c(dpot, reg); reg 236 drivers/misc/ad525x_dpot.c static s32 dpot_write_spi(struct dpot_data *dpot, u8 reg, u16 value) reg 240 drivers/misc/ad525x_dpot.c if (!(reg & (DPOT_ADDR_EEPROM | DPOT_ADDR_CMD | DPOT_ADDR_OTP))) { reg 242 drivers/misc/ad525x_dpot.c dpot->rdac_cache[reg & DPOT_RDAC_MASK] = value; reg 246 drivers/misc/ad525x_dpot.c val = ((reg & DPOT_RDAC_MASK) << reg 251 drivers/misc/ad525x_dpot.c val = ((reg & DPOT_RDAC_MASK) << reg 285 drivers/misc/ad525x_dpot.c val = DPOT_SPI_RDAC | (reg & DPOT_RDAC_MASK); reg 287 drivers/misc/ad525x_dpot.c } else if (reg & DPOT_ADDR_EEPROM) { reg 288 drivers/misc/ad525x_dpot.c val = DPOT_SPI_EEPROM | (reg & DPOT_RDAC_MASK); reg 289 drivers/misc/ad525x_dpot.c } else if (reg & DPOT_ADDR_CMD) { reg 290 drivers/misc/ad525x_dpot.c switch (reg) { reg 304 drivers/misc/ad525x_dpot.c } else if (reg & DPOT_ADDR_OTP) { reg 325 drivers/misc/ad525x_dpot.c static s32 dpot_write_i2c(struct dpot_data *dpot, u8 reg, u16 value) reg 342 drivers/misc/ad525x_dpot.c ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ? reg 347 drivers/misc/ad525x_dpot.c if (reg & DPOT_ADDR_OTP) { reg 356 drivers/misc/ad525x_dpot.c ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ? reg 358 drivers/misc/ad525x_dpot.c if (reg & DPOT_ADDR_OTP) { reg 366 drivers/misc/ad525x_dpot.c if (reg & DPOT_ADDR_OTP) { reg 378 drivers/misc/ad525x_dpot.c if (reg & DPOT_ADDR_OTP) reg 388 drivers/misc/ad525x_dpot.c if (reg & DPOT_ADDR_CMD) reg 389 drivers/misc/ad525x_dpot.c return dpot_write_d8(dpot, reg); reg 392 drivers/misc/ad525x_dpot.c return dpot_write_r8d16(dpot, (reg & 0xF8) | reg 393 drivers/misc/ad525x_dpot.c ((reg & 0x7) << 1), value); reg 396 drivers/misc/ad525x_dpot.c return dpot_write_r8d8(dpot, reg, value); reg 400 drivers/misc/ad525x_dpot.c static s32 dpot_write(struct dpot_data *dpot, u8 reg, u16 value) reg 403 drivers/misc/ad525x_dpot.c return dpot_write_spi(dpot, reg, value); reg 405 drivers/misc/ad525x_dpot.c return dpot_write_i2c(dpot, reg, value); reg 412 drivers/misc/ad525x_dpot.c char *buf, u32 reg) reg 417 drivers/misc/ad525x_dpot.c if (reg & DPOT_ADDR_OTP_EN) reg 419 drivers/misc/ad525x_dpot.c test_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask) ? reg 424 drivers/misc/ad525x_dpot.c value = dpot_read(data, reg); reg 437 drivers/misc/ad525x_dpot.c if (reg & DPOT_REG_TOL) reg 445 drivers/misc/ad525x_dpot.c const char *buf, size_t count, u32 reg) reg 451 drivers/misc/ad525x_dpot.c if (reg & DPOT_ADDR_OTP_EN) { reg 453 drivers/misc/ad525x_dpot.c set_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask); reg 455 drivers/misc/ad525x_dpot.c clear_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask); reg 460 drivers/misc/ad525x_dpot.c if ((reg & DPOT_ADDR_OTP) && reg 461 drivers/misc/ad525x_dpot.c !test_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask)) reg 472 drivers/misc/ad525x_dpot.c dpot_write(data, reg, value); reg 473 drivers/misc/ad525x_dpot.c if (reg & DPOT_ADDR_EEPROM) reg 475 drivers/misc/ad525x_dpot.c else if (reg & DPOT_ADDR_OTP) reg 484 drivers/misc/ad525x_dpot.c const char *buf, size_t count, u32 reg) reg 489 drivers/misc/ad525x_dpot.c dpot_write(data, reg, 0); reg 512 drivers/misc/ad525x_dpot.c #define DPOT_DEVICE_SHOW_SET(name, reg) \ reg 513 drivers/misc/ad525x_dpot.c DPOT_DEVICE_SHOW(name, reg) \ reg 514 drivers/misc/ad525x_dpot.c DPOT_DEVICE_SET(name, reg) \ reg 517 drivers/misc/ad525x_dpot.c #define DPOT_DEVICE_SHOW_ONLY(name, reg) \ reg 518 drivers/misc/ad525x_dpot.c DPOT_DEVICE_SHOW(name, reg) \ reg 198 drivers/misc/ad525x_dpot.h int (*read_r8d8)(void *client, u8 reg); reg 199 drivers/misc/ad525x_dpot.h int (*read_r8d16)(void *client, u8 reg); reg 201 drivers/misc/ad525x_dpot.h int (*write_r8d8)(void *client, u8 reg, u8 val); reg 202 drivers/misc/ad525x_dpot.h int (*write_r8d16)(void *client, u8 reg, u16 val); reg 186 drivers/misc/apds990x.c static int apds990x_read_byte(struct apds990x_chip *chip, u8 reg, u8 *data) reg 191 drivers/misc/apds990x.c reg &= ~APDS990x_CMD_TYPE_MASK; reg 192 drivers/misc/apds990x.c reg |= APDS990x_CMD | APDS990x_CMD_TYPE_RB; reg 194 drivers/misc/apds990x.c ret = i2c_smbus_read_byte_data(client, reg); reg 199 drivers/misc/apds990x.c static int apds990x_read_word(struct apds990x_chip *chip, u8 reg, u16 *data) reg 204 drivers/misc/apds990x.c reg &= ~APDS990x_CMD_TYPE_MASK; reg 205 drivers/misc/apds990x.c reg |= APDS990x_CMD | APDS990x_CMD_TYPE_INC; reg 207 drivers/misc/apds990x.c ret = i2c_smbus_read_word_data(client, reg); reg 212 drivers/misc/apds990x.c static int apds990x_write_byte(struct apds990x_chip *chip, u8 reg, u8 data) reg 217 drivers/misc/apds990x.c reg &= ~APDS990x_CMD_TYPE_MASK; reg 218 drivers/misc/apds990x.c reg |= APDS990x_CMD | APDS990x_CMD_TYPE_RB; reg 220 drivers/misc/apds990x.c ret = i2c_smbus_write_byte_data(client, reg, data); reg 224 drivers/misc/apds990x.c static int apds990x_write_word(struct apds990x_chip *chip, u8 reg, u16 data) reg 229 drivers/misc/apds990x.c reg &= ~APDS990x_CMD_TYPE_MASK; reg 230 drivers/misc/apds990x.c reg |= APDS990x_CMD | APDS990x_CMD_TYPE_INC; reg 232 drivers/misc/apds990x.c ret = i2c_smbus_write_word_data(client, reg, data); reg 239 drivers/misc/apds990x.c u8 reg = APDS990X_EN_AIEN | APDS990X_EN_PON | APDS990X_EN_AEN | reg 243 drivers/misc/apds990x.c reg |= APDS990X_EN_PIEN | APDS990X_EN_PEN; reg 245 drivers/misc/apds990x.c return apds990x_write_byte(chip, APDS990X_ENABLE, reg); reg 456 drivers/misc/apds990x.c u8 reg = APDS990x_CMD | APDS990x_CMD_TYPE_SPE; reg 460 drivers/misc/apds990x.c reg |= APDS990X_INT_ACK_ALS; reg 463 drivers/misc/apds990x.c reg |= APDS990X_INT_ACK_PS; reg 466 drivers/misc/apds990x.c reg |= APDS990X_INT_ACK_BOTH; reg 470 drivers/misc/apds990x.c ret = i2c_smbus_read_byte_data(client, reg); reg 62 drivers/misc/cardreader/rtl8411.c u32 reg = 0; reg 64 drivers/misc/cardreader/rtl8411.c rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®); reg 65 drivers/misc/cardreader/rtl8411.c pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); reg 67 drivers/misc/cardreader/rtl8411.c if (!rtsx_vendor_setting_valid(reg)) reg 70 drivers/misc/cardreader/rtl8411.c pcr->aspm_en = rtsx_reg_to_aspm(reg); reg 72 drivers/misc/cardreader/rtl8411.c map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg)); reg 74 drivers/misc/cardreader/rtl8411.c map_sd_drive(rtl8411b_reg_to_sd30_drive_sel_3v3(reg)); reg 26 drivers/misc/cardreader/rts5209.c u32 reg; reg 28 drivers/misc/cardreader/rts5209.c rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®); reg 29 drivers/misc/cardreader/rts5209.c pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); reg 31 drivers/misc/cardreader/rts5209.c if (rts5209_vendor_setting1_valid(reg)) { reg 32 drivers/misc/cardreader/rts5209.c if (rts5209_reg_check_ms_pmos(reg)) reg 34 drivers/misc/cardreader/rts5209.c pcr->aspm_en = rts5209_reg_to_aspm(reg); reg 37 drivers/misc/cardreader/rts5209.c rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®); reg 38 drivers/misc/cardreader/rts5209.c pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); reg 40 drivers/misc/cardreader/rts5209.c if (rts5209_vendor_setting2_valid(reg)) { reg 42 drivers/misc/cardreader/rts5209.c rts5209_reg_to_sd30_drive_sel_1v8(reg); reg 44 drivers/misc/cardreader/rts5209.c rts5209_reg_to_sd30_drive_sel_3v3(reg); reg 45 drivers/misc/cardreader/rts5209.c pcr->card_drive_sel = rts5209_reg_to_card_drive_sel(reg); reg 59 drivers/misc/cardreader/rts5227.c u32 reg; reg 61 drivers/misc/cardreader/rts5227.c rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®); reg 62 drivers/misc/cardreader/rts5227.c pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); reg 64 drivers/misc/cardreader/rts5227.c if (!rtsx_vendor_setting_valid(reg)) reg 67 drivers/misc/cardreader/rts5227.c pcr->aspm_en = rtsx_reg_to_aspm(reg); reg 68 drivers/misc/cardreader/rts5227.c pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); reg 70 drivers/misc/cardreader/rts5227.c pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg); reg 72 drivers/misc/cardreader/rts5227.c rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®); reg 73 drivers/misc/cardreader/rts5227.c pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); reg 74 drivers/misc/cardreader/rts5227.c pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg); reg 75 drivers/misc/cardreader/rts5227.c if (rtsx_reg_check_reverse_socket(reg)) reg 26 drivers/misc/cardreader/rts5229.c u32 reg; reg 28 drivers/misc/cardreader/rts5229.c rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®); reg 29 drivers/misc/cardreader/rts5229.c pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); reg 31 drivers/misc/cardreader/rts5229.c if (!rtsx_vendor_setting_valid(reg)) reg 34 drivers/misc/cardreader/rts5229.c pcr->aspm_en = rtsx_reg_to_aspm(reg); reg 36 drivers/misc/cardreader/rts5229.c map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg)); reg 38 drivers/misc/cardreader/rts5229.c pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg); reg 40 drivers/misc/cardreader/rts5229.c rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®); reg 41 drivers/misc/cardreader/rts5229.c pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); reg 43 drivers/misc/cardreader/rts5229.c map_sd_drive(rtsx_reg_to_sd30_drive_sel_3v3(reg)); reg 58 drivers/misc/cardreader/rts5249.c u32 reg; reg 60 drivers/misc/cardreader/rts5249.c rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®); reg 61 drivers/misc/cardreader/rts5249.c pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); reg 63 drivers/misc/cardreader/rts5249.c if (!rtsx_vendor_setting_valid(reg)) { reg 68 drivers/misc/cardreader/rts5249.c pcr->aspm_en = rtsx_reg_to_aspm(reg); reg 69 drivers/misc/cardreader/rts5249.c pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); reg 71 drivers/misc/cardreader/rts5249.c pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg); reg 73 drivers/misc/cardreader/rts5249.c rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®); reg 74 drivers/misc/cardreader/rts5249.c pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); reg 75 drivers/misc/cardreader/rts5249.c pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg); reg 76 drivers/misc/cardreader/rts5249.c if (rtsx_reg_check_reverse_socket(reg)) reg 67 drivers/misc/cardreader/rts5260.c u32 reg; reg 69 drivers/misc/cardreader/rts5260.c rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®); reg 70 drivers/misc/cardreader/rts5260.c pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); reg 72 drivers/misc/cardreader/rts5260.c if (!rtsx_vendor_setting_valid(reg)) { reg 77 drivers/misc/cardreader/rts5260.c pcr->aspm_en = rtsx_reg_to_aspm(reg); reg 78 drivers/misc/cardreader/rts5260.c pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); reg 80 drivers/misc/cardreader/rts5260.c pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg); reg 82 drivers/misc/cardreader/rts5260.c rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®); reg 83 drivers/misc/cardreader/rts5260.c pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); reg 84 drivers/misc/cardreader/rts5260.c pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg); reg 85 drivers/misc/cardreader/rts5260.c if (rtsx_reg_check_reverse_socket(reg)) reg 568 drivers/misc/cardreader/rtsx_pcr.c u16 reg; reg 575 drivers/misc/cardreader/rtsx_pcr.c reg = PPBUF_BASE2; reg 580 drivers/misc/cardreader/rtsx_pcr.c rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); reg 594 drivers/misc/cardreader/rtsx_pcr.c rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); reg 611 drivers/misc/cardreader/rtsx_pcr.c u16 reg; reg 618 drivers/misc/cardreader/rtsx_pcr.c reg = PPBUF_BASE2; reg 624 drivers/misc/cardreader/rtsx_pcr.c reg++, 0xFF, *ptr); reg 638 drivers/misc/cardreader/rtsx_pcr.c reg++, 0xFF, *ptr); reg 69 drivers/misc/cardreader/rtsx_pcr.h #define rtsx_vendor_setting_valid(reg) (!((reg) & 0x1000000)) reg 70 drivers/misc/cardreader/rtsx_pcr.h #define rts5209_vendor_setting1_valid(reg) (!((reg) & 0x80)) reg 71 drivers/misc/cardreader/rtsx_pcr.h #define rts5209_vendor_setting2_valid(reg) ((reg) & 0x80) reg 73 drivers/misc/cardreader/rtsx_pcr.h #define rtsx_reg_to_aspm(reg) (((reg) >> 28) & 0x03) reg 74 drivers/misc/cardreader/rtsx_pcr.h #define rtsx_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 26) & 0x03) reg 75 drivers/misc/cardreader/rtsx_pcr.h #define rtsx_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x03) reg 76 drivers/misc/cardreader/rtsx_pcr.h #define rtsx_reg_to_card_drive_sel(reg) ((((reg) >> 25) & 0x01) << 6) reg 77 drivers/misc/cardreader/rtsx_pcr.h #define rtsx_reg_check_reverse_socket(reg) ((reg) & 0x4000) reg 78 drivers/misc/cardreader/rtsx_pcr.h #define rts5209_reg_to_aspm(reg) (((reg) >> 5) & 0x03) reg 79 drivers/misc/cardreader/rtsx_pcr.h #define rts5209_reg_check_ms_pmos(reg) (!((reg) & 0x08)) reg 80 drivers/misc/cardreader/rtsx_pcr.h #define rts5209_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 3) & 0x07) reg 81 drivers/misc/cardreader/rtsx_pcr.h #define rts5209_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x07) reg 82 drivers/misc/cardreader/rtsx_pcr.h #define rts5209_reg_to_card_drive_sel(reg) ((reg) >> 8) reg 83 drivers/misc/cardreader/rtsx_pcr.h #define rtl8411_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x07) reg 84 drivers/misc/cardreader/rtsx_pcr.h #define rtl8411b_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x03) reg 18 drivers/misc/cb710/core.c int reg, uint32_t mask, uint32_t xor) reg 22 drivers/misc/cb710/core.c pci_read_config_dword(pdev, reg, &rval); reg 24 drivers/misc/cb710/core.c pci_write_config_dword(pdev, reg, rval); reg 31 drivers/misc/cb710/debug.c u##t *reg, unsigned select) \ reg 35 drivers/misc/cb710/debug.c for (i = 0; i < ARRAY_SIZE(allow); ++i, reg += 16/(t/8)) { \ reg 42 drivers/misc/cb710/debug.c reg[j] = ioread##t(iobase \ reg 55 drivers/misc/cb710/debug.c const u##t *reg, unsigned select) \ reg 63 drivers/misc/cb710/debug.c for (i = 0; i < ARRAY_SIZE(allow); ++i, reg += 16/(t/8)) { \ reg 72 drivers/misc/cb710/debug.c p += sprintf(p, format, reg[j]); \ reg 228 drivers/misc/cs5535-mfgpt.c uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer, uint16_t reg) reg 230 drivers/misc/cs5535-mfgpt.c return inw(timer->chip->base + reg + (timer->nr * 8)); reg 234 drivers/misc/cs5535-mfgpt.c void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg, reg 237 drivers/misc/cs5535-mfgpt.c outw(value, timer->chip->base + reg + (timer->nr * 8)); reg 56 drivers/misc/cxl/cxl.h #define cxl_reg_off(reg) \ reg 57 drivers/misc/cxl/cxl.h (reg.x) reg 774 drivers/misc/cxl/cxl.h static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg) reg 777 drivers/misc/cxl/cxl.h return cxl->native->p1_mmio + cxl_reg_off(reg); reg 780 drivers/misc/cxl/cxl.h static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val) reg 783 drivers/misc/cxl/cxl.h out_be64(_cxl_p1_addr(cxl, reg), val); reg 786 drivers/misc/cxl/cxl.h static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg) reg 789 drivers/misc/cxl/cxl.h return in_be64(_cxl_p1_addr(cxl, reg)); reg 794 drivers/misc/cxl/cxl.h static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg) reg 797 drivers/misc/cxl/cxl.h return afu->native->p1n_mmio + cxl_reg_off(reg); reg 800 drivers/misc/cxl/cxl.h static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val) reg 803 drivers/misc/cxl/cxl.h out_be64(_cxl_p1n_addr(afu, reg), val); reg 806 drivers/misc/cxl/cxl.h static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg) reg 809 drivers/misc/cxl/cxl.h return in_be64(_cxl_p1n_addr(afu, reg)); reg 814 drivers/misc/cxl/cxl.h static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg) reg 816 drivers/misc/cxl/cxl.h return afu->p2n_mmio + cxl_reg_off(reg); reg 819 drivers/misc/cxl/cxl.h static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val) reg 822 drivers/misc/cxl/cxl.h out_be64(_cxl_p2n_addr(afu, reg), val); reg 825 drivers/misc/cxl/cxl.h static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg) reg 828 drivers/misc/cxl/cxl.h return in_be64(_cxl_p2n_addr(afu, reg)); reg 1025 drivers/misc/cxl/cxl.h int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg); reg 361 drivers/misc/cxl/hcalls.c long cxl_h_get_fn_error_interrupt(u64 unit_address, u64 *reg) reg 365 drivers/misc/cxl/hcalls.c 0, 0, 0, 0, reg); reg 135 drivers/misc/cxl/hcalls.h long cxl_h_get_fn_error_interrupt(u64 unit_address, u64 *reg); reg 349 drivers/misc/cxl/native.c u64 reg; reg 363 drivers/misc/cxl/native.c reg = cxl_p1_read(adapter, CXL_PSL_Control); reg 364 drivers/misc/cxl/native.c reg |= CXL_PSL_Control_Fr; reg 365 drivers/misc/cxl/native.c cxl_p1_write(adapter, CXL_PSL_Control, reg); reg 367 drivers/misc/cxl/native.c reg = cxl_p1_read(adapter, CXL_PSL_Control); reg 368 drivers/misc/cxl/native.c while ((reg & CXL_PSL_Control_Fs_MASK) != CXL_PSL_Control_Fs_Complete) { reg 379 drivers/misc/cxl/native.c reg = cxl_p1_read(adapter, CXL_PSL_Control); reg 382 drivers/misc/cxl/native.c reg &= ~CXL_PSL_Control_Fr; reg 383 drivers/misc/cxl/native.c cxl_p1_write(adapter, CXL_PSL_Control, reg); reg 439 drivers/misc/cxl/pci.c int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg) reg 478 drivers/misc/cxl/pci.c *reg = xsl_dsnctl; reg 929 drivers/misc/cxl/pci.c u64 reg; reg 936 drivers/misc/cxl/pci.c reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An); reg 937 drivers/misc/cxl/pci.c if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { reg 938 drivers/misc/cxl/pci.c dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg); reg 948 drivers/misc/cxl/pci.c reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An); reg 949 drivers/misc/cxl/pci.c if (reg) { reg 950 drivers/misc/cxl/pci.c dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg); reg 951 drivers/misc/cxl/pci.c if (reg & CXL_PSL9_DSISR_An_TF) reg 957 drivers/misc/cxl/pci.c reg = cxl_p1n_read(afu, CXL_PSL_SERR_An); reg 958 drivers/misc/cxl/pci.c if (reg) { reg 959 drivers/misc/cxl/pci.c if (reg & ~0x000000007fffffff) reg 960 drivers/misc/cxl/pci.c dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg); reg 961 drivers/misc/cxl/pci.c cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff); reg 964 drivers/misc/cxl/pci.c reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); reg 965 drivers/misc/cxl/pci.c if (reg) { reg 966 drivers/misc/cxl/pci.c dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg); reg 967 drivers/misc/cxl/pci.c cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg); reg 975 drivers/misc/cxl/pci.c u64 reg; reg 982 drivers/misc/cxl/pci.c reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An); reg 983 drivers/misc/cxl/pci.c if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { reg 984 drivers/misc/cxl/pci.c dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg); reg 1003 drivers/misc/cxl/pci.c reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An); reg 1004 drivers/misc/cxl/pci.c if (reg) { reg 1005 drivers/misc/cxl/pci.c dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg); reg 1006 drivers/misc/cxl/pci.c if (reg & CXL_PSL_DSISR_TRANS) reg 1012 drivers/misc/cxl/pci.c reg = cxl_p1n_read(afu, CXL_PSL_SERR_An); reg 1013 drivers/misc/cxl/pci.c if (reg) { reg 1014 drivers/misc/cxl/pci.c if (reg & ~0xffff) reg 1015 drivers/misc/cxl/pci.c dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg); reg 1016 drivers/misc/cxl/pci.c cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff); reg 1019 drivers/misc/cxl/pci.c reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); reg 1020 drivers/misc/cxl/pci.c if (reg) { reg 1021 drivers/misc/cxl/pci.c dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg); reg 1022 drivers/misc/cxl/pci.c cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg); reg 456 drivers/misc/genwqe/card_base.h int genwqe_write_vreg(struct genwqe_dev *cd, u32 reg, u64 val, int func); reg 466 drivers/misc/genwqe/card_base.h u64 genwqe_read_vreg(struct genwqe_dev *cd, u32 reg, int func); reg 987 drivers/misc/genwqe/card_utils.c int genwqe_write_vreg(struct genwqe_dev *cd, u32 reg, u64 val, int func) reg 990 drivers/misc/genwqe/card_utils.c __genwqe_writeq(cd, reg, val); reg 1000 drivers/misc/genwqe/card_utils.c u64 genwqe_read_vreg(struct genwqe_dev *cd, u32 reg, int func) reg 1003 drivers/misc/genwqe/card_utils.c return __genwqe_readq(cd, reg); reg 1421 drivers/misc/habanalabs/device.c inline u32 hl_rreg(struct hl_device *hdev, u32 reg) reg 1423 drivers/misc/habanalabs/device.c return readl(hdev->rmmio + reg); reg 1436 drivers/misc/habanalabs/device.c inline void hl_wreg(struct hl_device *hdev, u32 reg, u32 val) reg 1438 drivers/misc/habanalabs/device.c writel(val, hdev->rmmio + reg); reg 531 drivers/misc/habanalabs/goya/goya.c static void goya_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid) reg 534 drivers/misc/habanalabs/goya/goya.c WREG32_AND(reg, ~0x7FF); reg 535 drivers/misc/habanalabs/goya/goya.c WREG32_OR(reg, asid); reg 584 drivers/misc/habanalabs/habanalabs.h u32 (*rreg)(struct hl_device *hdev, u32 reg); reg 585 drivers/misc/habanalabs/habanalabs.h void (*wreg)(struct hl_device *hdev, u32 reg, u32 val); reg 1031 drivers/misc/habanalabs/habanalabs.h u32 hl_rreg(struct hl_device *hdev, u32 reg); reg 1032 drivers/misc/habanalabs/habanalabs.h void hl_wreg(struct hl_device *hdev, u32 reg, u32 val); reg 1034 drivers/misc/habanalabs/habanalabs.h #define RREG32(reg) hdev->asic_funcs->rreg(hdev, (reg)) reg 1035 drivers/misc/habanalabs/habanalabs.h #define WREG32(reg, v) hdev->asic_funcs->wreg(hdev, (reg), (v)) reg 1036 drivers/misc/habanalabs/habanalabs.h #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \ reg 1037 drivers/misc/habanalabs/habanalabs.h hdev->asic_funcs->rreg(hdev, (reg))) reg 1039 drivers/misc/habanalabs/habanalabs.h #define WREG32_P(reg, val, mask) \ reg 1041 drivers/misc/habanalabs/habanalabs.h u32 tmp_ = RREG32(reg); \ reg 1044 drivers/misc/habanalabs/habanalabs.h WREG32(reg, tmp_); \ reg 1046 drivers/misc/habanalabs/habanalabs.h #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) reg 1047 drivers/misc/habanalabs/habanalabs.h #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) reg 1049 drivers/misc/habanalabs/habanalabs.h #define REG_FIELD_SHIFT(reg, field) reg##_##field##_SHIFT reg 1050 drivers/misc/habanalabs/habanalabs.h #define REG_FIELD_MASK(reg, field) reg##_##field##_MASK reg 1051 drivers/misc/habanalabs/habanalabs.h #define WREG32_FIELD(reg, field, val) \ reg 1052 drivers/misc/habanalabs/habanalabs.h WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | \ reg 1053 drivers/misc/habanalabs/habanalabs.h (val) << REG_FIELD_SHIFT(reg, field)) reg 381 drivers/misc/ics932s401.c int reg; reg 388 drivers/misc/ics932s401.c reg = ICS932S401_REG_SRC_SPREAD1; reg 390 drivers/misc/ics932s401.c reg = ICS932S401_REG_CPU_SPREAD1; reg 394 drivers/misc/ics932s401.c val = data->regs[reg] | (data->regs[reg + 1] << 8); reg 65 drivers/misc/isl29003.c u32 reg, u8 mask, u8 shift) reg 69 drivers/misc/isl29003.c return (data->reg_cache[reg] & mask) >> shift; reg 73 drivers/misc/isl29003.c u32 reg, u8 mask, u8 shift, u8 val) reg 79 drivers/misc/isl29003.c if (reg >= ISL29003_NUM_CACHABLE_REGS) reg 84 drivers/misc/isl29003.c tmp = data->reg_cache[reg]; reg 88 drivers/misc/isl29003.c ret = i2c_smbus_write_byte_data(client, reg, tmp); reg 90 drivers/misc/isl29003.c data->reg_cache[reg] = tmp; reg 116 drivers/misc/lis3lv02d/lis3lv02d.c static s16 lis3lv02d_read_8(struct lis3lv02d *lis3, int reg) reg 119 drivers/misc/lis3lv02d/lis3lv02d.c if (lis3->read(lis3, reg, &lo) < 0) reg 125 drivers/misc/lis3lv02d/lis3lv02d.c static s16 lis3lv02d_read_12(struct lis3lv02d *lis3, int reg) reg 129 drivers/misc/lis3lv02d/lis3lv02d.c lis3->read(lis3, reg - 1, &lo); reg 130 drivers/misc/lis3lv02d/lis3lv02d.c lis3->read(lis3, reg, &hi); reg 136 drivers/misc/lis3lv02d/lis3lv02d.c static s16 lis331dlh_read_data(struct lis3lv02d *lis3, int reg) reg 141 drivers/misc/lis3lv02d/lis3lv02d.c lis3->read(lis3, reg - 1, &lo); reg 142 drivers/misc/lis3lv02d/lis3lv02d.c lis3->read(lis3, reg, &hi); reg 258 drivers/misc/lis3lv02d/lis3lv02d.c u8 ctlreg, reg; reg 292 drivers/misc/lis3lv02d/lis3lv02d.c lis3->read(lis3, ctlreg, ®); reg 293 drivers/misc/lis3lv02d/lis3lv02d.c lis3->write(lis3, ctlreg, (reg | selftest)); reg 304 drivers/misc/lis3lv02d/lis3lv02d.c lis3->write(lis3, ctlreg, reg); reg 398 drivers/misc/lis3lv02d/lis3lv02d.c u8 reg; reg 409 drivers/misc/lis3lv02d/lis3lv02d.c lis3->read(lis3, CTRL_REG2, ®); reg 411 drivers/misc/lis3lv02d/lis3lv02d.c reg |= CTRL2_BDU | CTRL2_BOOT; reg 413 drivers/misc/lis3lv02d/lis3lv02d.c reg |= CTRL2_BOOT_3DLH; reg 415 drivers/misc/lis3lv02d/lis3lv02d.c reg |= CTRL2_BOOT_8B; reg 416 drivers/misc/lis3lv02d/lis3lv02d.c lis3->write(lis3, CTRL_REG2, reg); reg 419 drivers/misc/lis3lv02d/lis3lv02d.c lis3->read(lis3, CTRL_REG4, ®); reg 420 drivers/misc/lis3lv02d/lis3lv02d.c reg |= CTRL4_BDU; reg 421 drivers/misc/lis3lv02d/lis3lv02d.c lis3->write(lis3, CTRL_REG4, reg); reg 264 drivers/misc/lis3lv02d/lis3lv02d.h int (*write) (struct lis3lv02d *lis3, int reg, u8 val); reg 265 drivers/misc/lis3lv02d/lis3lv02d.h int (*read) (struct lis3lv02d *lis3, int reg, u8 *ret); reg 266 drivers/misc/lis3lv02d/lis3lv02d.h int (*blkread) (struct lis3lv02d *lis3, int reg, int len, u8 *ret); reg 276 drivers/misc/lis3lv02d/lis3lv02d.h s16 (*read_data) (struct lis3lv02d *lis3, int reg); reg 46 drivers/misc/lis3lv02d/lis3lv02d_i2c.c static inline s32 lis3_i2c_write(struct lis3lv02d *lis3, int reg, u8 value) reg 49 drivers/misc/lis3lv02d/lis3lv02d_i2c.c return i2c_smbus_write_byte_data(c, reg, value); reg 52 drivers/misc/lis3lv02d/lis3lv02d_i2c.c static inline s32 lis3_i2c_read(struct lis3lv02d *lis3, int reg, u8 *v) reg 55 drivers/misc/lis3lv02d/lis3lv02d_i2c.c *v = i2c_smbus_read_byte_data(c, reg); reg 59 drivers/misc/lis3lv02d/lis3lv02d_i2c.c static inline s32 lis3_i2c_blockread(struct lis3lv02d *lis3, int reg, int len, reg 63 drivers/misc/lis3lv02d/lis3lv02d_i2c.c reg |= (1 << 7); /* 7th bit enables address auto incrementation */ reg 64 drivers/misc/lis3lv02d/lis3lv02d_i2c.c return i2c_smbus_read_i2c_block_data(c, reg, len, v); reg 69 drivers/misc/lis3lv02d/lis3lv02d_i2c.c u8 reg; reg 74 drivers/misc/lis3lv02d/lis3lv02d_i2c.c lis3->read(lis3, WHO_AM_I, ®); reg 75 drivers/misc/lis3lv02d/lis3lv02d_i2c.c if (reg != lis3->whoami) reg 79 drivers/misc/lis3lv02d/lis3lv02d_i2c.c ret = lis3->read(lis3, CTRL_REG1, ®); reg 84 drivers/misc/lis3lv02d/lis3lv02d_i2c.c reg |= CTRL1_PM0 | CTRL1_Xen | CTRL1_Yen | CTRL1_Zen; reg 86 drivers/misc/lis3lv02d/lis3lv02d_i2c.c reg |= CTRL1_PD0 | CTRL1_Xen | CTRL1_Yen | CTRL1_Zen; reg 88 drivers/misc/lis3lv02d/lis3lv02d_i2c.c return lis3->write(lis3, CTRL_REG1, reg); reg 25 drivers/misc/lis3lv02d/lis3lv02d_spi.c static int lis3_spi_read(struct lis3lv02d *lis3, int reg, u8 *v) reg 28 drivers/misc/lis3lv02d/lis3lv02d_spi.c int ret = spi_w8r8(spi, reg | LIS3_SPI_READ); reg 36 drivers/misc/lis3lv02d/lis3lv02d_spi.c static int lis3_spi_write(struct lis3lv02d *lis3, int reg, u8 val) reg 38 drivers/misc/lis3lv02d/lis3lv02d_spi.c u8 tmp[2] = { reg, val }; reg 45 drivers/misc/lis3lv02d/lis3lv02d_spi.c u8 reg; reg 49 drivers/misc/lis3lv02d/lis3lv02d_spi.c ret = lis3->read(lis3, CTRL_REG1, ®); reg 53 drivers/misc/lis3lv02d/lis3lv02d_spi.c reg |= CTRL1_PD0 | CTRL1_Xen | CTRL1_Yen | CTRL1_Zen; reg 54 drivers/misc/lis3lv02d/lis3lv02d_spi.c return lis3->write(lis3, CTRL_REG1, reg); reg 83 drivers/misc/mei/hw-me.c u32 reg; reg 85 drivers/misc/mei/hw-me.c reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA); reg 86 drivers/misc/mei/hw-me.c trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg); reg 88 drivers/misc/mei/hw-me.c return reg; reg 100 drivers/misc/mei/hw-me.c u32 reg; reg 102 drivers/misc/mei/hw-me.c reg = mei_me_reg_read(to_me_hw(dev), H_CSR); reg 103 drivers/misc/mei/hw-me.c trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg); reg 105 drivers/misc/mei/hw-me.c return reg; reg 114 drivers/misc/mei/hw-me.c static inline void mei_hcsr_write(struct mei_device *dev, u32 reg) reg 116 drivers/misc/mei/hw-me.c trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg); reg 117 drivers/misc/mei/hw-me.c mei_me_reg_write(to_me_hw(dev), H_CSR, reg); reg 127 drivers/misc/mei/hw-me.c static inline void mei_hcsr_set(struct mei_device *dev, u32 reg) reg 129 drivers/misc/mei/hw-me.c reg &= ~H_CSR_IS_MASK; reg 130 drivers/misc/mei/hw-me.c mei_hcsr_write(dev, reg); reg 155 drivers/misc/mei/hw-me.c u32 reg; reg 157 drivers/misc/mei/hw-me.c reg = mei_me_reg_read(to_me_hw(dev), H_D0I3C); reg 158 drivers/misc/mei/hw-me.c trace_mei_reg_read(dev->dev, "H_D0I3C", H_D0I3C, reg); reg 160 drivers/misc/mei/hw-me.c return reg; reg 169 drivers/misc/mei/hw-me.c static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg) reg 171 drivers/misc/mei/hw-me.c trace_mei_reg_write(dev->dev, "H_D0I3C", H_D0I3C, reg); reg 172 drivers/misc/mei/hw-me.c mei_me_reg_write(to_me_hw(dev), H_D0I3C, reg); reg 218 drivers/misc/mei/hw-me.c u32 hcsr, reg; reg 224 drivers/misc/mei/hw-me.c reg = 0; reg 225 drivers/misc/mei/hw-me.c pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®); reg 226 drivers/misc/mei/hw-me.c trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg); reg 228 drivers/misc/mei/hw-me.c ((reg & PCI_CFG_HFS_1_D0I3_MSK) == PCI_CFG_HFS_1_D0I3_MSK); reg 232 drivers/misc/mei/hw-me.c reg = mei_me_d0i3c_read(dev); reg 233 drivers/misc/mei/hw-me.c if (reg & H_D0I3C_I3) reg 554 drivers/misc/mei/hw-me.c u32 reg = 0; reg 556 drivers/misc/mei/hw-me.c memcpy(®, (const u8 *)data + data_len - rem, rem); reg 557 drivers/misc/mei/hw-me.c mei_me_hcbww_write(dev, reg); reg 612 drivers/misc/mei/hw-me.c u32 reg = mei_me_mecbrw_read(dev); reg 614 drivers/misc/mei/hw-me.c memcpy(reg_buf, ®, buffer_length); reg 629 drivers/misc/mei/hw-me.c u32 reg; reg 631 drivers/misc/mei/hw-me.c reg = mei_me_reg_read(hw, H_HPG_CSR); reg 632 drivers/misc/mei/hw-me.c trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); reg 634 drivers/misc/mei/hw-me.c reg |= H_HPG_CSR_PGI; reg 636 drivers/misc/mei/hw-me.c trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); reg 637 drivers/misc/mei/hw-me.c mei_me_reg_write(hw, H_HPG_CSR, reg); reg 648 drivers/misc/mei/hw-me.c u32 reg; reg 650 drivers/misc/mei/hw-me.c reg = mei_me_reg_read(hw, H_HPG_CSR); reg 651 drivers/misc/mei/hw-me.c trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); reg 653 drivers/misc/mei/hw-me.c WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n"); reg 655 drivers/misc/mei/hw-me.c reg |= H_HPG_CSR_PGIHEXR; reg 657 drivers/misc/mei/hw-me.c trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg); reg 658 drivers/misc/mei/hw-me.c mei_me_reg_write(hw, H_HPG_CSR, reg); reg 774 drivers/misc/mei/hw-me.c u32 reg = mei_me_mecsr_read(dev); reg 779 drivers/misc/mei/hw-me.c if ((reg & ME_PGIC_HRA) == 0) reg 790 drivers/misc/mei/hw-me.c !!(reg & ME_PGIC_HRA), reg 809 drivers/misc/mei/hw-me.c u32 reg = mei_me_d0i3c_read(dev); reg 811 drivers/misc/mei/hw-me.c reg |= H_D0I3C_I3; reg 813 drivers/misc/mei/hw-me.c reg |= H_D0I3C_IR; reg 815 drivers/misc/mei/hw-me.c reg &= ~H_D0I3C_IR; reg 816 drivers/misc/mei/hw-me.c mei_me_d0i3c_write(dev, reg); reg 818 drivers/misc/mei/hw-me.c reg = mei_me_d0i3c_read(dev); reg 819 drivers/misc/mei/hw-me.c return reg; reg 831 drivers/misc/mei/hw-me.c u32 reg = mei_me_d0i3c_read(dev); reg 833 drivers/misc/mei/hw-me.c reg &= ~H_D0I3C_I3; reg 834 drivers/misc/mei/hw-me.c reg |= H_D0I3C_IR; reg 835 drivers/misc/mei/hw-me.c mei_me_d0i3c_write(dev, reg); reg 837 drivers/misc/mei/hw-me.c reg = mei_me_d0i3c_read(dev); reg 838 drivers/misc/mei/hw-me.c return reg; reg 854 drivers/misc/mei/hw-me.c u32 reg; reg 856 drivers/misc/mei/hw-me.c reg = mei_me_d0i3c_read(dev); reg 857 drivers/misc/mei/hw-me.c if (reg & H_D0I3C_I3) { reg 885 drivers/misc/mei/hw-me.c reg = mei_me_d0i3_set(dev, true); reg 886 drivers/misc/mei/hw-me.c if (!(reg & H_D0I3C_CIP)) { reg 898 drivers/misc/mei/hw-me.c reg = mei_me_d0i3c_read(dev); reg 899 drivers/misc/mei/hw-me.c if (!(reg & H_D0I3C_I3)) { reg 927 drivers/misc/mei/hw-me.c u32 reg; reg 929 drivers/misc/mei/hw-me.c reg = mei_me_d0i3c_read(dev); reg 930 drivers/misc/mei/hw-me.c if (reg & H_D0I3C_I3) { reg 956 drivers/misc/mei/hw-me.c u32 reg; reg 960 drivers/misc/mei/hw-me.c reg = mei_me_d0i3c_read(dev); reg 961 drivers/misc/mei/hw-me.c if (!(reg & H_D0I3C_I3)) { reg 968 drivers/misc/mei/hw-me.c reg = mei_me_d0i3_unset(dev); reg 969 drivers/misc/mei/hw-me.c if (!(reg & H_D0I3C_CIP)) { reg 981 drivers/misc/mei/hw-me.c reg = mei_me_d0i3c_read(dev); reg 982 drivers/misc/mei/hw-me.c if (reg & H_D0I3C_I3) { reg 1328 drivers/misc/mei/hw-me.c u32 reg; reg 1330 drivers/misc/mei/hw-me.c pci_read_config_dword(pdev, PCI_CFG_HFS_2, ®); reg 1331 drivers/misc/mei/hw-me.c trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_2", PCI_CFG_HFS_2, reg); reg 1333 drivers/misc/mei/hw-me.c return (reg & 0x600) == 0x200; reg 1341 drivers/misc/mei/hw-me.c u32 reg; reg 1349 drivers/misc/mei/hw-me.c pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_1, ®); reg 1350 drivers/misc/mei/hw-me.c trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg); reg 1352 drivers/misc/mei/hw-me.c return (reg & 0xf0000) == 0xf0000; reg 186 drivers/misc/mei/hw-txe.c u32 reg; reg 188 drivers/misc/mei/hw-txe.c reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG); reg 189 drivers/misc/mei/hw-txe.c return reg & SICR_HOST_ALIVENESS_REQ_REQUESTED; reg 203 drivers/misc/mei/hw-txe.c u32 reg; reg 205 drivers/misc/mei/hw-txe.c reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG); reg 206 drivers/misc/mei/hw-txe.c return reg & HICR_HOST_ALIVENESS_RESP_ACK; reg 593 drivers/misc/mei/hw-txe.c u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); reg 595 drivers/misc/mei/hw-txe.c return !!(reg & HICR_SEC_IPC_READINESS_HOST_RDY); reg 737 drivers/misc/mei/hw-txe.c u32 reg = 0; reg 739 drivers/misc/mei/hw-txe.c memcpy(®, (const u8 *)data + data_len - rem, rem); reg 740 drivers/misc/mei/hw-txe.c mei_txe_input_payload_write(dev, i + j, reg); reg 817 drivers/misc/mei/hw-txe.c u32 *reg_buf, reg; reg 832 drivers/misc/mei/hw-txe.c reg = mei_txe_out_data_read(dev, i + 1); reg 833 drivers/misc/mei/hw-txe.c dev_dbg(dev->dev, "buf[%d] = 0x%08X\n", i, reg); reg 834 drivers/misc/mei/hw-txe.c *reg_buf++ = reg; reg 838 drivers/misc/mei/hw-txe.c reg = mei_txe_out_data_read(dev, i + 1); reg 839 drivers/misc/mei/hw-txe.c memcpy(reg_buf, ®, rem); reg 20 drivers/misc/mei/mei-trace.h TP_PROTO(const struct device *dev, const char *reg, u32 offs, u32 val), reg 21 drivers/misc/mei/mei-trace.h TP_ARGS(dev, reg, offs, val), reg 24 drivers/misc/mei/mei-trace.h __field(const char *, reg) reg 30 drivers/misc/mei/mei-trace.h __entry->reg = reg; reg 35 drivers/misc/mei/mei-trace.h __get_str(dev), __entry->reg, __entry->offs, __entry->val) reg 39 drivers/misc/mei/mei-trace.h TP_PROTO(const struct device *dev, const char *reg, u32 offs, u32 val), reg 40 drivers/misc/mei/mei-trace.h TP_ARGS(dev, reg, offs, val), reg 43 drivers/misc/mei/mei-trace.h __field(const char *, reg) reg 49 drivers/misc/mei/mei-trace.h __entry->reg = reg; reg 54 drivers/misc/mei/mei-trace.h __get_str(dev), __entry->reg, __entry->offs, __entry->val) reg 58 drivers/misc/mei/mei-trace.h TP_PROTO(const struct device *dev, const char *reg, u32 offs, u32 val), reg 59 drivers/misc/mei/mei-trace.h TP_ARGS(dev, reg, offs, val), reg 62 drivers/misc/mei/mei-trace.h __field(const char *, reg) reg 68 drivers/misc/mei/mei-trace.h __entry->reg = reg; reg 73 drivers/misc/mei/mei-trace.h __get_str(dev), __entry->reg, __entry->offs, __entry->val) reg 50 drivers/misc/mic/host/mic_debugfs.c u32 reg = mdev->ops->get_postcode(mdev); reg 52 drivers/misc/mic/host/mic_debugfs.c seq_printf(s, "%c%c", reg & 0xff, (reg >> 8) & 0xff); reg 61 drivers/misc/mic/host/mic_debugfs.c int reg; reg 77 drivers/misc/mic/host/mic_debugfs.c reg = mdev->intr_ops->read_msi_to_src_map(mdev, entry); reg 80 drivers/misc/mic/host/mic_debugfs.c "IRQ:", vector, "Entry:", entry, i, reg); reg 68 drivers/misc/mic/host/mic_x100.c u32 reg; reg 73 drivers/misc/mic/host/mic_x100.c reg = mic_mmio_read(mw, sice0); reg 74 drivers/misc/mic/host/mic_x100.c reg |= MIC_X100_SBOX_DBR_BITS(0xf) | MIC_X100_SBOX_DMA_BITS(0xff); reg 75 drivers/misc/mic/host/mic_x100.c mic_mmio_write(mw, reg, sice0); reg 82 drivers/misc/mic/host/mic_x100.c reg = mic_mmio_read(mw, siac0); reg 83 drivers/misc/mic/host/mic_x100.c reg |= MIC_X100_SBOX_DBR_BITS(0xf) | reg 85 drivers/misc/mic/host/mic_x100.c mic_mmio_write(mw, reg, siac0); reg 95 drivers/misc/mic/host/mic_x100.c u32 reg; reg 101 drivers/misc/mic/host/mic_x100.c reg = mic_mmio_read(mw, sice0); reg 102 drivers/misc/mic/host/mic_x100.c mic_mmio_write(mw, reg, sicc0); reg 105 drivers/misc/mic/host/mic_x100.c reg = mic_mmio_read(mw, siac0); reg 106 drivers/misc/mic/host/mic_x100.c reg &= ~(MIC_X100_SBOX_DBR_BITS(0xf) | reg 108 drivers/misc/mic/host/mic_x100.c mic_mmio_write(mw, reg, siac0); reg 173 drivers/misc/mic/host/mic_x100.c u32 reg = mic_mmio_read(&mdev->mmio, sicr0); reg 174 drivers/misc/mic/host/mic_x100.c mic_mmio_write(&mdev->mmio, reg, sicr0); reg 175 drivers/misc/mic/host/mic_x100.c return reg; reg 239 drivers/misc/mic/host/mic_x100.c unsigned long reg; reg 244 drivers/misc/mic/host/mic_x100.c reg = mic_mmio_read(mw, mxar); reg 246 drivers/misc/mic/host/mic_x100.c __set_bit(offset, ®); reg 248 drivers/misc/mic/host/mic_x100.c __clear_bit(offset, ®); reg 249 drivers/misc/mic/host/mic_x100.c mic_mmio_write(mw, reg, mxar); reg 302 drivers/misc/mic/scif/scif_fd.c struct scifioctl_reg reg; reg 305 drivers/misc/mic/scif/scif_fd.c if (copy_from_user(®, argp, sizeof(reg))) { reg 309 drivers/misc/mic/scif/scif_fd.c if (reg.flags & SCIF_MAP_KERNEL) { reg 313 drivers/misc/mic/scif/scif_fd.c ret = scif_register(priv, (void *)reg.addr, reg.len, reg 314 drivers/misc/mic/scif/scif_fd.c reg.offset, reg.prot, reg.flags); reg 321 drivers/misc/mic/scif/scif_fd.c ->out_offset, &ret, sizeof(reg.out_offset))) { reg 101 drivers/misc/ocxl/link.c u64 reg; reg 105 drivers/misc/ocxl/link.c reg = in_be64(spa->reg_pe_handle); reg 106 drivers/misc/ocxl/link.c *pe = reg & SPA_PE_MASK; reg 111 drivers/misc/ocxl/link.c u64 reg = 0; reg 115 drivers/misc/ocxl/link.c reg = PPC_BIT(31); reg 117 drivers/misc/ocxl/link.c reg = PPC_BIT(30); reg 121 drivers/misc/ocxl/link.c if (reg) { reg 123 drivers/misc/ocxl/link.c spa->xsl_fault.dsisr, spa->xsl_fault.dar, reg); reg 124 drivers/misc/ocxl/link.c out_be64(spa->reg_tfc, reg); reg 142 drivers/misc/pci_endpoint_test.c u32 reg; reg 144 drivers/misc/pci_endpoint_test.c reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS); reg 145 drivers/misc/pci_endpoint_test.c if (reg & STATUS_IRQ_RAISED) { reg 148 drivers/misc/pci_endpoint_test.c reg &= ~STATUS_IRQ_RAISED; reg 151 drivers/misc/pci_endpoint_test.c reg); reg 425 drivers/misc/pci_endpoint_test.c u32 reg; reg 482 drivers/misc/pci_endpoint_test.c reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS); reg 483 drivers/misc/pci_endpoint_test.c if (reg & STATUS_READ_SUCCESS) reg 101 drivers/misc/phantom.c if (r.reg > 7) reg 105 drivers/misc/phantom.c if (r.reg == PHN_CONTROL && (r.value & PHN_CTL_IRQ) && reg 111 drivers/misc/phantom.c pr_debug("phantom: writing %x to %u\n", r.value, r.reg); reg 114 drivers/misc/phantom.c if (r.reg == PHN_CONTROL && (dev->status & PHB_NOT_OH)) { reg 120 drivers/misc/phantom.c iowrite32(r.value, dev->iaddr + r.reg); reg 123 drivers/misc/phantom.c if (r.reg == PHN_CONTROL && !(r.value & PHN_CTL_IRQ)) reg 150 drivers/misc/phantom.c if (r.reg > 7) reg 153 drivers/misc/phantom.c r.value = ioread32(dev->iaddr + r.reg); reg 604 drivers/misc/xilinx_sdfec.c u32 reg = 0; reg 636 drivers/misc/xilinx_sdfec.c base_addr + ((offset + reg) * reg 638 drivers/misc/xilinx_sdfec.c addr[reg]); reg 639 drivers/misc/xilinx_sdfec.c reg++; reg 640 drivers/misc/xilinx_sdfec.c } while ((reg < len) && reg 641 drivers/misc/xilinx_sdfec.c ((reg * XSDFEC_REG_WIDTH_JUMP) % PAGE_SIZE)); reg 644 drivers/misc/xilinx_sdfec.c return reg; reg 1089 drivers/mmc/core/core.c u32 reg; reg 1092 drivers/mmc/core/core.c ret = of_property_read_u32(node, "reg", ®); reg 1096 drivers/mmc/core/core.c return reg; reg 62 drivers/mmc/core/sdio_io.c unsigned char reg; reg 70 drivers/mmc/core/sdio_io.c ret = mmc_io_rw_direct(func->card, 0, 0, SDIO_CCCR_IOEx, 0, ®); reg 74 drivers/mmc/core/sdio_io.c reg |= 1 << func->num; reg 76 drivers/mmc/core/sdio_io.c ret = mmc_io_rw_direct(func->card, 1, 0, SDIO_CCCR_IOEx, reg, NULL); reg 83 drivers/mmc/core/sdio_io.c ret = mmc_io_rw_direct(func->card, 0, 0, SDIO_CCCR_IORx, 0, ®); reg 86 drivers/mmc/core/sdio_io.c if (reg & (1 << func->num)) reg 113 drivers/mmc/core/sdio_io.c unsigned char reg; reg 120 drivers/mmc/core/sdio_io.c ret = mmc_io_rw_direct(func->card, 0, 0, SDIO_CCCR_IOEx, 0, ®); reg 124 drivers/mmc/core/sdio_io.c reg &= ~(1 << func->num); reg 126 drivers/mmc/core/sdio_io.c ret = mmc_io_rw_direct(func->card, 1, 0, SDIO_CCCR_IOEx, reg, NULL); reg 302 drivers/mmc/core/sdio_irq.c unsigned char reg; reg 314 drivers/mmc/core/sdio_irq.c ret = mmc_io_rw_direct(func->card, 0, 0, SDIO_CCCR_IENx, 0, ®); reg 318 drivers/mmc/core/sdio_irq.c reg |= 1 << func->num; reg 320 drivers/mmc/core/sdio_irq.c reg |= 1; /* Master interrupt enable */ reg 322 drivers/mmc/core/sdio_irq.c ret = mmc_io_rw_direct(func->card, 1, 0, SDIO_CCCR_IENx, reg, NULL); reg 345 drivers/mmc/core/sdio_irq.c unsigned char reg; reg 358 drivers/mmc/core/sdio_irq.c ret = mmc_io_rw_direct(func->card, 0, 0, SDIO_CCCR_IENx, 0, ®); reg 362 drivers/mmc/core/sdio_irq.c reg &= ~(1 << func->num); reg 365 drivers/mmc/core/sdio_irq.c if (!(reg & 0xFE)) reg 366 drivers/mmc/core/sdio_irq.c reg = 0; reg 368 drivers/mmc/core/sdio_irq.c ret = mmc_io_rw_direct(func->card, 1, 0, SDIO_CCCR_IENx, reg, NULL); reg 167 drivers/mmc/host/atmel-mci.c #define atmci_readl(port, reg) \ reg 168 drivers/mmc/host/atmel-mci.c __raw_readl((port)->regs + reg) reg 169 drivers/mmc/host/atmel-mci.c #define atmci_writel(port, reg, value) \ reg 170 drivers/mmc/host/atmel-mci.c __raw_writel((value), (port)->regs + reg) reg 178 drivers/mmc/host/cavium.c static void clear_bus_id(u64 *reg) reg 182 drivers/mmc/host/cavium.c *reg &= ~bus_id_mask; reg 185 drivers/mmc/host/cavium.c static void set_bus_id(u64 *reg, int bus_id) reg 187 drivers/mmc/host/cavium.c clear_bus_id(reg); reg 188 drivers/mmc/host/cavium.c *reg |= FIELD_PREP(GENMASK(61, 60), bus_id); reg 191 drivers/mmc/host/cavium.c static int get_bus_id(u64 reg) reg 193 drivers/mmc/host/cavium.c return FIELD_GET(GENMASK_ULL(61, 60), reg); reg 355 drivers/mmc/host/cqhci.c u32 reg; reg 366 drivers/mmc/host/cqhci.c err = readx_poll_timeout(cqhci_read_ctl, cq_host, reg, reg 367 drivers/mmc/host/cqhci.c reg & CQHCI_HALT, 0, CQHCI_OFF_TIMEOUT); reg 203 drivers/mmc/host/cqhci.h void (*write_l)(struct cqhci_host *host, u32 val, int reg); reg 204 drivers/mmc/host/cqhci.h u32 (*read_l)(struct cqhci_host *host, int reg); reg 211 drivers/mmc/host/cqhci.h static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg) reg 214 drivers/mmc/host/cqhci.h host->ops->write_l(host, val, reg); reg 216 drivers/mmc/host/cqhci.h writel_relaxed(val, host->mmio + reg); reg 219 drivers/mmc/host/cqhci.h static inline u32 cqhci_readl(struct cqhci_host *host, int reg) reg 222 drivers/mmc/host/cqhci.h return host->ops->read_l(host, reg); reg 224 drivers/mmc/host/cqhci.h return readl_relaxed(host->mmio + reg); reg 25 drivers/mmc/host/dw_mmc-bluefield.c u32 reg; reg 28 drivers/mmc/host/dw_mmc-bluefield.c reg = mci_readl(host, UHS_REG_EXT); reg 29 drivers/mmc/host/dw_mmc-bluefield.c reg &= ~UHS_REG_EXT_SAMPLE_MASK; reg 30 drivers/mmc/host/dw_mmc-bluefield.c reg |= FIELD_PREP(UHS_REG_EXT_SAMPLE_MASK, reg 32 drivers/mmc/host/dw_mmc-bluefield.c reg &= ~UHS_REG_EXT_DRIVE_MASK; reg 33 drivers/mmc/host/dw_mmc-bluefield.c reg |= FIELD_PREP(UHS_REG_EXT_DRIVE_MASK, BLUEFIELD_UHS_REG_EXT_DRIVE); reg 34 drivers/mmc/host/dw_mmc-bluefield.c mci_writel(host, UHS_REG_EXT, reg); reg 58 drivers/mmc/host/dw_mmc-k3.c struct regmap *reg; reg 125 drivers/mmc/host/dw_mmc-k3.c priv->reg = syscon_regmap_lookup_by_phandle(host->dev->of_node, reg 127 drivers/mmc/host/dw_mmc-k3.c if (IS_ERR(priv->reg)) reg 128 drivers/mmc/host/dw_mmc-k3.c priv->reg = NULL; reg 152 drivers/mmc/host/dw_mmc-k3.c if (!priv || !priv->reg) reg 156 drivers/mmc/host/dw_mmc-k3.c ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3, reg 161 drivers/mmc/host/dw_mmc-k3.c ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3, reg 287 drivers/mmc/host/dw_mmc-k3.c ret = regmap_update_bits(priv->reg, SOC_SCTRL_SCPERCTRL5, reg 412 drivers/mmc/host/dw_mmc-k3.c if (!priv || !priv->reg) reg 461 drivers/mmc/host/dw_mmc.h #define mci_readl(dev, reg) \ reg 462 drivers/mmc/host/dw_mmc.h readl_relaxed((dev)->regs + SDMMC_##reg) reg 463 drivers/mmc/host/dw_mmc.h #define mci_writel(dev, reg, value) \ reg 464 drivers/mmc/host/dw_mmc.h writel_relaxed((value), (dev)->regs + SDMMC_##reg) reg 467 drivers/mmc/host/dw_mmc.h #define mci_readw(dev, reg) \ reg 468 drivers/mmc/host/dw_mmc.h readw_relaxed((dev)->regs + SDMMC_##reg) reg 469 drivers/mmc/host/dw_mmc.h #define mci_writew(dev, reg, value) \ reg 470 drivers/mmc/host/dw_mmc.h writew_relaxed((value), (dev)->regs + SDMMC_##reg) reg 474 drivers/mmc/host/dw_mmc.h #define mci_readq(dev, reg) \ reg 475 drivers/mmc/host/dw_mmc.h readq_relaxed((dev)->regs + SDMMC_##reg) reg 476 drivers/mmc/host/dw_mmc.h #define mci_writeq(dev, reg, value) \ reg 477 drivers/mmc/host/dw_mmc.h writeq_relaxed((value), (dev)->regs + SDMMC_##reg) reg 487 drivers/mmc/host/dw_mmc.h #define mci_readq(dev, reg) \ reg 488 drivers/mmc/host/dw_mmc.h (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg)) reg 489 drivers/mmc/host/dw_mmc.h #define mci_writeq(dev, reg, value) \ reg 490 drivers/mmc/host/dw_mmc.h (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) reg 451 drivers/mmc/host/meson-gx-mmc.c mux->reg = host->regs + SD_EMMC_CLOCK; reg 473 drivers/mmc/host/meson-gx-mmc.c div->reg = host->regs + SD_EMMC_CLOCK; reg 125 drivers/mmc/host/meson-mx-sdio.c static void meson_mx_mmc_mask_bits(struct mmc_host *mmc, char reg, u32 mask, reg 131 drivers/mmc/host/meson-mx-sdio.c regval = readl(host->base + reg); reg 135 drivers/mmc/host/meson-mx-sdio.c writel(regval, host->base + reg); reg 613 drivers/mmc/host/meson-mx-sdio.c host->cfg_div.reg = host->base + MESON_MX_SDIO_CONF; reg 544 drivers/mmc/host/mtk-sd.c static void sdr_set_bits(void __iomem *reg, u32 bs) reg 546 drivers/mmc/host/mtk-sd.c u32 val = readl(reg); reg 549 drivers/mmc/host/mtk-sd.c writel(val, reg); reg 552 drivers/mmc/host/mtk-sd.c static void sdr_clr_bits(void __iomem *reg, u32 bs) reg 554 drivers/mmc/host/mtk-sd.c u32 val = readl(reg); reg 557 drivers/mmc/host/mtk-sd.c writel(val, reg); reg 560 drivers/mmc/host/mtk-sd.c static void sdr_set_field(void __iomem *reg, u32 field, u32 val) reg 562 drivers/mmc/host/mtk-sd.c unsigned int tv = readl(reg); reg 566 drivers/mmc/host/mtk-sd.c writel(tv, reg); reg 569 drivers/mmc/host/mtk-sd.c static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) reg 571 drivers/mmc/host/mtk-sd.c unsigned int tv = readl(reg); reg 202 drivers/mmc/host/mxcmmc.c static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg) reg 205 drivers/mmc/host/mxcmmc.c return ioread32be(host->base + reg); reg 207 drivers/mmc/host/mxcmmc.c return readl(host->base + reg); reg 210 drivers/mmc/host/mxcmmc.c static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg) reg 213 drivers/mmc/host/mxcmmc.c iowrite32be(val, host->base + reg); reg 215 drivers/mmc/host/mxcmmc.c writel(val, host->base + reg); reg 218 drivers/mmc/host/mxcmmc.c static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg) reg 221 drivers/mmc/host/mxcmmc.c return ioread32be(host->base + reg); reg 223 drivers/mmc/host/mxcmmc.c return readw(host->base + reg); reg 226 drivers/mmc/host/mxcmmc.c static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg) reg 229 drivers/mmc/host/mxcmmc.c iowrite32be(val, host->base + reg); reg 231 drivers/mmc/host/mxcmmc.c writew(val, host->base + reg); reg 79 drivers/mmc/host/omap.c #define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift) reg 80 drivers/mmc/host/omap.c #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg)) reg 81 drivers/mmc/host/omap.c #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg)) reg 914 drivers/mmc/host/omap.c u16 reg; reg 916 drivers/mmc/host/omap.c reg = OMAP_MMC_READ(host, SDIO); reg 917 drivers/mmc/host/omap.c reg &= ~(1 << 5); reg 918 drivers/mmc/host/omap.c OMAP_MMC_WRITE(host, SDIO, reg); reg 926 drivers/mmc/host/omap.c u16 reg; reg 933 drivers/mmc/host/omap.c reg = OMAP_MMC_READ(host, SDIO); reg 935 drivers/mmc/host/omap.c reg |= (1 << 5); reg 938 drivers/mmc/host/omap.c reg &= ~(1 << 5); reg 939 drivers/mmc/host/omap.c OMAP_MMC_WRITE(host, SDIO, reg); reg 158 drivers/mmc/host/omap_hsmmc.c #define OMAP_HSMMC_READ(base, reg) \ reg 159 drivers/mmc/host/omap_hsmmc.c __raw_readl((base) + OMAP_HSMMC_##reg) reg 161 drivers/mmc/host/omap_hsmmc.c #define OMAP_HSMMC_WRITE(base, reg, val) \ reg 162 drivers/mmc/host/omap_hsmmc.c __raw_writel((val), (base) + OMAP_HSMMC_##reg) reg 361 drivers/mmc/host/omap_hsmmc.c static int omap_hsmmc_disable_boot_regulator(struct regulator *reg) reg 365 drivers/mmc/host/omap_hsmmc.c if (IS_ERR(reg)) reg 368 drivers/mmc/host/omap_hsmmc.c if (regulator_is_enabled(reg)) { reg 369 drivers/mmc/host/omap_hsmmc.c ret = regulator_enable(reg); reg 373 drivers/mmc/host/omap_hsmmc.c ret = regulator_disable(reg); reg 722 drivers/mmc/host/omap_hsmmc.c int reg = 0; reg 733 drivers/mmc/host/omap_hsmmc.c while ((reg != CC_EN) && time_before(jiffies, timeout)) reg 734 drivers/mmc/host/omap_hsmmc.c reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; reg 1307 drivers/mmc/host/omap_hsmmc.c uint32_t reg, clkd, dto = 0; reg 1309 drivers/mmc/host/omap_hsmmc.c reg = OMAP_HSMMC_READ(host->base, SYSCTL); reg 1310 drivers/mmc/host/omap_hsmmc.c clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; reg 1334 drivers/mmc/host/omap_hsmmc.c reg &= ~DTO_MASK; reg 1335 drivers/mmc/host/omap_hsmmc.c reg |= dto << DTO_SHIFT; reg 1336 drivers/mmc/host/omap_hsmmc.c OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); reg 200 drivers/mmc/host/sdhci-acpi.c u8 reg; reg 202 drivers/mmc/host/sdhci-acpi.c reg = sdhci_readb(host, SDHCI_POWER_CONTROL); reg 203 drivers/mmc/host/sdhci-acpi.c reg |= 0x10; reg 204 drivers/mmc/host/sdhci-acpi.c sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); reg 207 drivers/mmc/host/sdhci-acpi.c reg &= ~0x10; reg 208 drivers/mmc/host/sdhci-acpi.c sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); reg 96 drivers/mmc/host/sdhci-cadence.c void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04; reg 102 drivers/mmc/host/sdhci-cadence.c writel(tmp, reg); reg 105 drivers/mmc/host/sdhci-cadence.c writel(tmp, reg); reg 107 drivers/mmc/host/sdhci-cadence.c ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10); reg 112 drivers/mmc/host/sdhci-cadence.c writel(tmp, reg); reg 251 drivers/mmc/host/sdhci-cadence.c void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06; reg 258 drivers/mmc/host/sdhci-cadence.c tmp = readl(reg); reg 269 drivers/mmc/host/sdhci-cadence.c writel(tmp, reg); reg 271 drivers/mmc/host/sdhci-cadence.c ret = readl_poll_timeout(reg, tmp, reg 19 drivers/mmc/host/sdhci-dove.c static u16 sdhci_dove_readw(struct sdhci_host *host, int reg) reg 23 drivers/mmc/host/sdhci-dove.c switch (reg) { reg 29 drivers/mmc/host/sdhci-dove.c ret = readw(host->ioaddr + reg); reg 34 drivers/mmc/host/sdhci-dove.c static u32 sdhci_dove_readl(struct sdhci_host *host, int reg) reg 38 drivers/mmc/host/sdhci-dove.c ret = readl(host->ioaddr + reg); reg 40 drivers/mmc/host/sdhci-dove.c switch (reg) { reg 297 drivers/mmc/host/sdhci-esdhc-imx.c static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) reg 299 drivers/mmc/host/sdhci-esdhc-imx.c void __iomem *base = host->ioaddr + (reg & ~0x3); reg 300 drivers/mmc/host/sdhci-esdhc-imx.c u32 shift = (reg & 0x3) * 8; reg 305 drivers/mmc/host/sdhci-esdhc-imx.c static u32 esdhc_readl_le(struct sdhci_host *host, int reg) reg 309 drivers/mmc/host/sdhci-esdhc-imx.c u32 val = readl(host->ioaddr + reg); reg 311 drivers/mmc/host/sdhci-esdhc-imx.c if (unlikely(reg == SDHCI_PRESENT_STATE)) { reg 321 drivers/mmc/host/sdhci-esdhc-imx.c if (unlikely(reg == SDHCI_CAPABILITIES)) { reg 339 drivers/mmc/host/sdhci-esdhc-imx.c if (unlikely(reg == SDHCI_CAPABILITIES_1)) { reg 364 drivers/mmc/host/sdhci-esdhc-imx.c if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { reg 371 drivers/mmc/host/sdhci-esdhc-imx.c if (unlikely(reg == SDHCI_INT_STATUS)) { reg 393 drivers/mmc/host/sdhci-esdhc-imx.c static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) reg 399 drivers/mmc/host/sdhci-esdhc-imx.c if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || reg 400 drivers/mmc/host/sdhci-esdhc-imx.c reg == SDHCI_INT_STATUS)) { reg 424 drivers/mmc/host/sdhci-esdhc-imx.c && (reg == SDHCI_INT_STATUS) reg 441 drivers/mmc/host/sdhci-esdhc-imx.c writel(val, host->ioaddr + reg); reg 444 drivers/mmc/host/sdhci-esdhc-imx.c static u16 esdhc_readw_le(struct sdhci_host *host, int reg) reg 451 drivers/mmc/host/sdhci-esdhc-imx.c if (unlikely(reg == SDHCI_HOST_VERSION)) { reg 452 drivers/mmc/host/sdhci-esdhc-imx.c reg ^= 2; reg 462 drivers/mmc/host/sdhci-esdhc-imx.c if (unlikely(reg == SDHCI_HOST_CONTROL2)) { reg 485 drivers/mmc/host/sdhci-esdhc-imx.c if (unlikely(reg == SDHCI_TRANSFER_MODE)) { reg 501 drivers/mmc/host/sdhci-esdhc-imx.c return readw(host->ioaddr + reg); reg 504 drivers/mmc/host/sdhci-esdhc-imx.c static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) reg 510 drivers/mmc/host/sdhci-esdhc-imx.c switch (reg) { reg 622 drivers/mmc/host/sdhci-esdhc-imx.c esdhc_clrset_le(host, 0xffff, val, reg); reg 625 drivers/mmc/host/sdhci-esdhc-imx.c static u8 esdhc_readb_le(struct sdhci_host *host, int reg) reg 630 drivers/mmc/host/sdhci-esdhc-imx.c switch (reg) { reg 632 drivers/mmc/host/sdhci-esdhc-imx.c val = readl(host->ioaddr + reg); reg 641 drivers/mmc/host/sdhci-esdhc-imx.c return readb(host->ioaddr + reg); reg 644 drivers/mmc/host/sdhci-esdhc-imx.c static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) reg 651 drivers/mmc/host/sdhci-esdhc-imx.c switch (reg) { reg 677 drivers/mmc/host/sdhci-esdhc-imx.c esdhc_clrset_le(host, mask, new_val, reg); reg 684 drivers/mmc/host/sdhci-esdhc-imx.c esdhc_clrset_le(host, 0xff, val, reg); reg 686 drivers/mmc/host/sdhci-esdhc-imx.c if (reg == SDHCI_SOFTWARE_RESET) { reg 870 drivers/mmc/host/sdhci-esdhc-imx.c u32 reg; reg 875 drivers/mmc/host/sdhci-esdhc-imx.c reg = readl(host->ioaddr + ESDHC_MIX_CTRL); reg 876 drivers/mmc/host/sdhci-esdhc-imx.c reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | reg 878 drivers/mmc/host/sdhci-esdhc-imx.c writel(reg, host->ioaddr + ESDHC_MIX_CTRL); reg 887 drivers/mmc/host/sdhci-esdhc-imx.c u32 reg; reg 889 drivers/mmc/host/sdhci-esdhc-imx.c reg = readl(host->ioaddr + ESDHC_MIX_CTRL); reg 890 drivers/mmc/host/sdhci-esdhc-imx.c reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; reg 891 drivers/mmc/host/sdhci-esdhc-imx.c reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; reg 892 drivers/mmc/host/sdhci-esdhc-imx.c writel(reg, host->ioaddr + ESDHC_MIX_CTRL); reg 1250 drivers/mmc/host/sdhci-esdhc-imx.c u32 reg; reg 1258 drivers/mmc/host/sdhci-esdhc-imx.c reg = sdhci_readl(host, SDHCI_PRESENT_STATE); reg 1259 drivers/mmc/host/sdhci-esdhc-imx.c while (reg & SDHCI_DATA_AVAILABLE) { reg 1261 drivers/mmc/host/sdhci-esdhc-imx.c reg = sdhci_readl(host, SDHCI_PRESENT_STATE); reg 41 drivers/mmc/host/sdhci-iproc.c #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18) reg 43 drivers/mmc/host/sdhci-iproc.c static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg) reg 45 drivers/mmc/host/sdhci-iproc.c u32 val = readl(host->ioaddr + reg); reg 48 drivers/mmc/host/sdhci-iproc.c mmc_hostname(host->mmc), reg, val); reg 52 drivers/mmc/host/sdhci-iproc.c static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg) reg 59 drivers/mmc/host/sdhci-iproc.c if ((reg == SDHCI_TRANSFER_MODE) && iproc_host->is_cmd_shadowed) { reg 62 drivers/mmc/host/sdhci-iproc.c } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) && reg 67 drivers/mmc/host/sdhci-iproc.c val = sdhci_iproc_readl(host, (reg & ~3)); reg 69 drivers/mmc/host/sdhci-iproc.c word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff; reg 73 drivers/mmc/host/sdhci-iproc.c static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg) reg 75 drivers/mmc/host/sdhci-iproc.c u32 val = sdhci_iproc_readl(host, (reg & ~3)); reg 76 drivers/mmc/host/sdhci-iproc.c u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff; reg 80 drivers/mmc/host/sdhci-iproc.c static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg) reg 83 drivers/mmc/host/sdhci-iproc.c mmc_hostname(host->mmc), reg, val); reg 85 drivers/mmc/host/sdhci-iproc.c writel(val, host->ioaddr + reg); reg 115 drivers/mmc/host/sdhci-iproc.c static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg) reg 119 drivers/mmc/host/sdhci-iproc.c u32 word_shift = REG_OFFSET_IN_BITS(reg); reg 123 drivers/mmc/host/sdhci-iproc.c if (reg == SDHCI_COMMAND) { reg 132 drivers/mmc/host/sdhci-iproc.c } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) && reg 138 drivers/mmc/host/sdhci-iproc.c oldval = sdhci_iproc_readl(host, (reg & ~3)); reg 142 drivers/mmc/host/sdhci-iproc.c if (reg == SDHCI_TRANSFER_MODE) { reg 146 drivers/mmc/host/sdhci-iproc.c } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) { reg 152 drivers/mmc/host/sdhci-iproc.c sdhci_iproc_writel(host, newval, reg & ~3); reg 156 drivers/mmc/host/sdhci-iproc.c static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg) reg 158 drivers/mmc/host/sdhci-iproc.c u32 oldval = sdhci_iproc_readl(host, (reg & ~3)); reg 159 drivers/mmc/host/sdhci-iproc.c u32 byte_shift = REG_OFFSET_IN_BITS(reg); reg 163 drivers/mmc/host/sdhci-iproc.c sdhci_iproc_writel(host, newval, reg & ~3); reg 1583 drivers/mmc/host/sdhci-msm.c static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg) reg 1589 drivers/mmc/host/sdhci-msm.c switch (reg) { reg 1628 drivers/mmc/host/sdhci-msm.c static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg) reg 1632 drivers/mmc/host/sdhci-msm.c req_type = __sdhci_msm_check_write(host, val, reg); reg 1633 drivers/mmc/host/sdhci-msm.c writew_relaxed(val, host->ioaddr + reg); reg 1640 drivers/mmc/host/sdhci-msm.c static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg) reg 1644 drivers/mmc/host/sdhci-msm.c req_type = __sdhci_msm_check_write(host, val, reg); reg 1646 drivers/mmc/host/sdhci-msm.c writeb_relaxed(val, host->ioaddr + reg); reg 52 drivers/mmc/host/sdhci-of-arasan.c u32 reg; reg 112 drivers/mmc/host/sdhci-of-arasan.c .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 }, reg 113 drivers/mmc/host/sdhci-of-arasan.c .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0}, reg 118 drivers/mmc/host/sdhci-of-arasan.c .baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 }, reg 119 drivers/mmc/host/sdhci-of-arasan.c .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 }, reg 142 drivers/mmc/host/sdhci-of-arasan.c u32 reg = fld->reg; reg 157 drivers/mmc/host/sdhci-of-arasan.c ret = regmap_write(soc_ctl_base, reg, reg 161 drivers/mmc/host/sdhci-of-arasan.c ret = regmap_update_bits(soc_ctl_base, reg, reg 342 drivers/mmc/host/sdhci-of-arasan.c u32 reg; reg 344 drivers/mmc/host/sdhci-of-arasan.c reg = sdhci_readl(host, SDHCI_PRESENT_STATE); reg 345 drivers/mmc/host/sdhci-of-arasan.c while (reg & SDHCI_DATA_AVAILABLE) { reg 347 drivers/mmc/host/sdhci-of-arasan.c reg = sdhci_readl(host, SDHCI_PRESENT_STATE); reg 322 drivers/mmc/host/sdhci-of-esdhc.c static u32 esdhc_be_readl(struct sdhci_host *host, int reg) reg 327 drivers/mmc/host/sdhci-of-esdhc.c if (reg == SDHCI_CAPABILITIES_1) reg 330 drivers/mmc/host/sdhci-of-esdhc.c value = ioread32be(host->ioaddr + reg); reg 332 drivers/mmc/host/sdhci-of-esdhc.c ret = esdhc_readl_fixup(host, reg, value); reg 337 drivers/mmc/host/sdhci-of-esdhc.c static u32 esdhc_le_readl(struct sdhci_host *host, int reg) reg 342 drivers/mmc/host/sdhci-of-esdhc.c if (reg == SDHCI_CAPABILITIES_1) reg 345 drivers/mmc/host/sdhci-of-esdhc.c value = ioread32(host->ioaddr + reg); reg 347 drivers/mmc/host/sdhci-of-esdhc.c ret = esdhc_readl_fixup(host, reg, value); reg 352 drivers/mmc/host/sdhci-of-esdhc.c static u16 esdhc_be_readw(struct sdhci_host *host, int reg) reg 356 drivers/mmc/host/sdhci-of-esdhc.c int base = reg & ~0x3; reg 359 drivers/mmc/host/sdhci-of-esdhc.c ret = esdhc_readw_fixup(host, reg, value); reg 363 drivers/mmc/host/sdhci-of-esdhc.c static u16 esdhc_le_readw(struct sdhci_host *host, int reg) reg 367 drivers/mmc/host/sdhci-of-esdhc.c int base = reg & ~0x3; reg 370 drivers/mmc/host/sdhci-of-esdhc.c ret = esdhc_readw_fixup(host, reg, value); reg 374 drivers/mmc/host/sdhci-of-esdhc.c static u8 esdhc_be_readb(struct sdhci_host *host, int reg) reg 378 drivers/mmc/host/sdhci-of-esdhc.c int base = reg & ~0x3; reg 381 drivers/mmc/host/sdhci-of-esdhc.c ret = esdhc_readb_fixup(host, reg, value); reg 385 drivers/mmc/host/sdhci-of-esdhc.c static u8 esdhc_le_readb(struct sdhci_host *host, int reg) reg 389 drivers/mmc/host/sdhci-of-esdhc.c int base = reg & ~0x3; reg 392 drivers/mmc/host/sdhci-of-esdhc.c ret = esdhc_readb_fixup(host, reg, value); reg 396 drivers/mmc/host/sdhci-of-esdhc.c static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) reg 400 drivers/mmc/host/sdhci-of-esdhc.c value = esdhc_writel_fixup(host, reg, val, 0); reg 401 drivers/mmc/host/sdhci-of-esdhc.c iowrite32be(value, host->ioaddr + reg); reg 404 drivers/mmc/host/sdhci-of-esdhc.c static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) reg 408 drivers/mmc/host/sdhci-of-esdhc.c value = esdhc_writel_fixup(host, reg, val, 0); reg 409 drivers/mmc/host/sdhci-of-esdhc.c iowrite32(value, host->ioaddr + reg); reg 412 drivers/mmc/host/sdhci-of-esdhc.c static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) reg 416 drivers/mmc/host/sdhci-of-esdhc.c int base = reg & ~0x3; reg 421 drivers/mmc/host/sdhci-of-esdhc.c ret = esdhc_writew_fixup(host, reg, val, value); reg 422 drivers/mmc/host/sdhci-of-esdhc.c if (reg != SDHCI_TRANSFER_MODE) reg 438 drivers/mmc/host/sdhci-of-esdhc.c static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) reg 442 drivers/mmc/host/sdhci-of-esdhc.c int base = reg & ~0x3; reg 447 drivers/mmc/host/sdhci-of-esdhc.c ret = esdhc_writew_fixup(host, reg, val, value); reg 448 drivers/mmc/host/sdhci-of-esdhc.c if (reg != SDHCI_TRANSFER_MODE) reg 464 drivers/mmc/host/sdhci-of-esdhc.c static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) reg 466 drivers/mmc/host/sdhci-of-esdhc.c int base = reg & ~0x3; reg 471 drivers/mmc/host/sdhci-of-esdhc.c ret = esdhc_writeb_fixup(host, reg, val, value); reg 475 drivers/mmc/host/sdhci-of-esdhc.c static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) reg 477 drivers/mmc/host/sdhci-of-esdhc.c int base = reg & ~0x3; reg 482 drivers/mmc/host/sdhci-of-esdhc.c ret = esdhc_writeb_fixup(host, reg, val, value); reg 32 drivers/mmc/host/sdhci-of-hlwd.c static void sdhci_hlwd_writel(struct sdhci_host *host, u32 val, int reg) reg 34 drivers/mmc/host/sdhci-of-hlwd.c sdhci_be32bs_writel(host, val, reg); reg 38 drivers/mmc/host/sdhci-of-hlwd.c static void sdhci_hlwd_writew(struct sdhci_host *host, u16 val, int reg) reg 40 drivers/mmc/host/sdhci-of-hlwd.c sdhci_be32bs_writew(host, val, reg); reg 44 drivers/mmc/host/sdhci-of-hlwd.c static void sdhci_hlwd_writeb(struct sdhci_host *host, u8 val, int reg) reg 46 drivers/mmc/host/sdhci-of-hlwd.c sdhci_be32bs_writeb(host, val, reg); reg 196 drivers/mmc/host/sdhci-omap.c u32 reg; reg 199 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL); reg 200 drivers/mmc/host/sdhci-omap.c reg &= ~HCTL_SDVS_MASK; reg 203 drivers/mmc/host/sdhci-omap.c reg |= HCTL_SDVS_33; reg 205 drivers/mmc/host/sdhci-omap.c reg |= HCTL_SDVS_18; reg 207 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg); reg 209 drivers/mmc/host/sdhci-omap.c reg |= HCTL_SDBP; reg 210 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg); reg 230 drivers/mmc/host/sdhci-omap.c u32 reg; reg 232 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); reg 234 drivers/mmc/host/sdhci-omap.c reg |= (CON_CTPL | CON_CLKEXTFREE); reg 236 drivers/mmc/host/sdhci-omap.c reg &= ~(CON_CTPL | CON_CLKEXTFREE); reg 237 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); reg 246 drivers/mmc/host/sdhci-omap.c u32 reg; reg 248 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL); reg 249 drivers/mmc/host/sdhci-omap.c reg |= DLL_FORCE_VALUE; reg 250 drivers/mmc/host/sdhci-omap.c reg &= ~DLL_FORCE_SR_C_MASK; reg 251 drivers/mmc/host/sdhci-omap.c reg |= (count << DLL_FORCE_SR_C_SHIFT); reg 252 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); reg 254 drivers/mmc/host/sdhci-omap.c reg |= DLL_CALIB; reg 255 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); reg 257 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL); reg 258 drivers/mmc/host/sdhci-omap.c if (reg & DLL_CALIB) reg 261 drivers/mmc/host/sdhci-omap.c reg &= ~DLL_CALIB; reg 262 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); reg 267 drivers/mmc/host/sdhci-omap.c u32 reg; reg 269 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); reg 270 drivers/mmc/host/sdhci-omap.c reg &= ~AC12_SCLK_SEL; reg 271 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg); reg 273 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL); reg 274 drivers/mmc/host/sdhci-omap.c reg &= ~(DLL_FORCE_VALUE | DLL_SWT); reg 275 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); reg 294 drivers/mmc/host/sdhci-omap.c u32 reg; reg 301 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2); reg 302 drivers/mmc/host/sdhci-omap.c if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50)) reg 315 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL); reg 316 drivers/mmc/host/sdhci-omap.c reg |= DLL_SWT; reg 317 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg); reg 434 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); reg 435 drivers/mmc/host/sdhci-omap.c if (!(reg & AC12_SCLK_SEL)) { reg 463 drivers/mmc/host/sdhci-omap.c u32 reg, ac12; reg 473 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); reg 475 drivers/mmc/host/sdhci-omap.c reg &= ~CON_CLKEXTFREE; reg 477 drivers/mmc/host/sdhci-omap.c reg |= CON_CLKEXTFREE; reg 478 drivers/mmc/host/sdhci-omap.c reg |= CON_PADEN; reg 479 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); reg 491 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE); reg 492 drivers/mmc/host/sdhci-omap.c if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0)) reg 495 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); reg 496 drivers/mmc/host/sdhci-omap.c reg &= ~(CON_CLKEXTFREE | CON_PADEN); reg 497 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); reg 509 drivers/mmc/host/sdhci-omap.c u32 reg; reg 522 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA); reg 523 drivers/mmc/host/sdhci-omap.c if (!(reg & CAPA_VS33)) reg 528 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); reg 529 drivers/mmc/host/sdhci-omap.c reg &= ~AC12_V1V8_SIGEN; reg 530 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg); reg 534 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA); reg 535 drivers/mmc/host/sdhci-omap.c if (!(reg & CAPA_VS18)) reg 540 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); reg 541 drivers/mmc/host/sdhci-omap.c reg |= AC12_V1V8_SIGEN; reg 542 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg); reg 595 drivers/mmc/host/sdhci-omap.c u32 reg; reg 600 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); reg 602 drivers/mmc/host/sdhci-omap.c reg |= CON_OD; reg 604 drivers/mmc/host/sdhci-omap.c reg &= ~CON_OD; reg 605 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); reg 639 drivers/mmc/host/sdhci-omap.c u32 reg; reg 641 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL); reg 642 drivers/mmc/host/sdhci-omap.c reg |= SYSCTL_CEN; reg 643 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg); reg 648 drivers/mmc/host/sdhci-omap.c u32 reg; reg 650 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL); reg 651 drivers/mmc/host/sdhci-omap.c reg &= ~SYSCTL_CEN; reg 652 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg); reg 683 drivers/mmc/host/sdhci-omap.c u32 reg; reg 687 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); reg 688 drivers/mmc/host/sdhci-omap.c reg |= CON_DMA_MASTER; reg 689 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); reg 705 drivers/mmc/host/sdhci-omap.c u32 reg; reg 707 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); reg 709 drivers/mmc/host/sdhci-omap.c reg |= CON_DW8; reg 711 drivers/mmc/host/sdhci-omap.c reg &= ~CON_DW8; reg 712 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); reg 719 drivers/mmc/host/sdhci-omap.c u32 reg; reg 732 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); reg 733 drivers/mmc/host/sdhci-omap.c reg |= CON_INIT; reg 734 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); reg 749 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); reg 750 drivers/mmc/host/sdhci-omap.c reg &= ~CON_INIT; reg 751 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); reg 760 drivers/mmc/host/sdhci-omap.c u32 reg; reg 766 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); reg 768 drivers/mmc/host/sdhci-omap.c reg |= CON_DDR; reg 770 drivers/mmc/host/sdhci-omap.c reg &= ~CON_DDR; reg 771 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); reg 841 drivers/mmc/host/sdhci-omap.c u32 reg; reg 853 drivers/mmc/host/sdhci-omap.c reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA); reg 854 drivers/mmc/host/sdhci-omap.c reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33); reg 857 drivers/mmc/host/sdhci-omap.c reg |= CAPA_VS33; reg 859 drivers/mmc/host/sdhci-omap.c reg |= CAPA_VS18; reg 861 drivers/mmc/host/sdhci-omap.c sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg); reg 583 drivers/mmc/host/sdhci-pci-core.c u8 reg; reg 585 drivers/mmc/host/sdhci-pci-core.c reg = sdhci_readb(host, SDHCI_POWER_CONTROL); reg 586 drivers/mmc/host/sdhci-pci-core.c reg |= 0x10; reg 587 drivers/mmc/host/sdhci-pci-core.c sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); reg 590 drivers/mmc/host/sdhci-pci-core.c reg &= ~0x10; reg 591 drivers/mmc/host/sdhci-pci-core.c sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); reg 639 drivers/mmc/host/sdhci-pci-core.c u8 reg; reg 651 drivers/mmc/host/sdhci-pci-core.c reg = sdhci_readb(host, SDHCI_POWER_CONTROL); reg 652 drivers/mmc/host/sdhci-pci-core.c if (reg & SDHCI_POWER_ON) reg 655 drivers/mmc/host/sdhci-pci-core.c reg |= SDHCI_POWER_ON; reg 656 drivers/mmc/host/sdhci-pci-core.c sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); reg 34 drivers/mmc/host/sdhci-pci-dwc-mshc.c u32 reg, vendor_ptr; reg 39 drivers/mmc/host/sdhci-pci-dwc-mshc.c reg = sdhci_readl(host, (SDHC_AT_CTRL_R + vendor_ptr)); reg 40 drivers/mmc/host/sdhci-pci-dwc-mshc.c reg &= ~SDHC_SW_TUNE_EN; reg 41 drivers/mmc/host/sdhci-pci-dwc-mshc.c sdhci_writel(host, reg, (SDHC_AT_CTRL_R + vendor_ptr)); reg 47 drivers/mmc/host/sdhci-pci-dwc-mshc.c reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); reg 48 drivers/mmc/host/sdhci-pci-dwc-mshc.c reg |= SDHC_CCLK_MMCM_RST; reg 49 drivers/mmc/host/sdhci-pci-dwc-mshc.c sdhci_writel(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); reg 63 drivers/mmc/host/sdhci-pci-dwc-mshc.c reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); reg 64 drivers/mmc/host/sdhci-pci-dwc-mshc.c reg &= ~SDHC_CCLK_MMCM_RST; reg 65 drivers/mmc/host/sdhci-pci-dwc-mshc.c sdhci_writel(host, reg, (SDHC_GPIO_OUT + vendor_ptr)); reg 331 drivers/mmc/host/sdhci-pci-gli.c static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg) reg 335 drivers/mmc/host/sdhci-pci-gli.c value = readl(host->ioaddr + reg); reg 336 drivers/mmc/host/sdhci-pci-gli.c if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff))) reg 187 drivers/mmc/host/sdhci-pci-o2micro.c u16 reg; reg 190 drivers/mmc/host/sdhci-pci-o2micro.c reg = sdhci_readw(host, O2_SD_VENDOR_SETTING); reg 191 drivers/mmc/host/sdhci-pci-o2micro.c reg &= ~O2_SD_HW_TUNING_DISABLE; reg 192 drivers/mmc/host/sdhci-pci-o2micro.c sdhci_writew(host, reg, O2_SD_VENDOR_SETTING); reg 517 drivers/mmc/host/sdhci-pci-o2micro.c u32 reg, caps; reg 539 drivers/mmc/host/sdhci-pci-o2micro.c reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); reg 540 drivers/mmc/host/sdhci-pci-o2micro.c if (reg & 0x1) reg 547 drivers/mmc/host/sdhci-pci-o2micro.c O2_SD_MISC_SETTING, ®); reg 550 drivers/mmc/host/sdhci-pci-o2micro.c if (reg & (1 << 4)) { reg 569 drivers/mmc/host/sdhci-pci-o2micro.c reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); reg 570 drivers/mmc/host/sdhci-pci-o2micro.c reg |= (1 << 12); reg 571 drivers/mmc/host/sdhci-pci-o2micro.c sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2); reg 36 drivers/mmc/host/sdhci-pltfm.h static inline u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg) reg 38 drivers/mmc/host/sdhci-pltfm.h return in_be32(host->ioaddr + reg); reg 41 drivers/mmc/host/sdhci-pltfm.h static inline u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg) reg 43 drivers/mmc/host/sdhci-pltfm.h return in_be16(host->ioaddr + (reg ^ 0x2)); reg 46 drivers/mmc/host/sdhci-pltfm.h static inline u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg) reg 48 drivers/mmc/host/sdhci-pltfm.h return in_8(host->ioaddr + (reg ^ 0x3)); reg 52 drivers/mmc/host/sdhci-pltfm.h u32 val, int reg) reg 54 drivers/mmc/host/sdhci-pltfm.h out_be32(host->ioaddr + reg, val); reg 58 drivers/mmc/host/sdhci-pltfm.h u16 val, int reg) reg 61 drivers/mmc/host/sdhci-pltfm.h int base = reg & ~0x3; reg 62 drivers/mmc/host/sdhci-pltfm.h int shift = (reg & 0x2) * 8; reg 64 drivers/mmc/host/sdhci-pltfm.h switch (reg) { reg 81 drivers/mmc/host/sdhci-pltfm.h static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg) reg 83 drivers/mmc/host/sdhci-pltfm.h int base = reg & ~0x3; reg 84 drivers/mmc/host/sdhci-pltfm.h int shift = (reg & 0x3) * 8; reg 40 drivers/mmc/host/sdhci-sirf.c static u32 sdhci_sirf_readl_le(struct sdhci_host *host, int reg) reg 42 drivers/mmc/host/sdhci-sirf.c u32 val = readl(host->ioaddr + reg); reg 44 drivers/mmc/host/sdhci-sirf.c if (unlikely((reg == SDHCI_CAPABILITIES_1) && reg 51 drivers/mmc/host/sdhci-sirf.c if (unlikely(reg == SDHCI_SLOT_INT_STATUS)) { reg 60 drivers/mmc/host/sdhci-sirf.c static u16 sdhci_sirf_readw_le(struct sdhci_host *host, int reg) reg 64 drivers/mmc/host/sdhci-sirf.c ret = readw(host->ioaddr + reg); reg 66 drivers/mmc/host/sdhci-sirf.c if (unlikely(reg == SDHCI_HOST_VERSION)) { reg 113 drivers/mmc/host/sdhci-sprd.c static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) reg 115 drivers/mmc/host/sdhci-sprd.c if (unlikely(reg == SDHCI_MAX_CURRENT)) reg 118 drivers/mmc/host/sdhci-sprd.c return readl_relaxed(host->ioaddr + reg); reg 121 drivers/mmc/host/sdhci-sprd.c static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) reg 124 drivers/mmc/host/sdhci-sprd.c if (unlikely(reg == SDHCI_MAX_CURRENT)) reg 127 drivers/mmc/host/sdhci-sprd.c if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) reg 130 drivers/mmc/host/sdhci-sprd.c writel_relaxed(val, host->ioaddr + reg); reg 133 drivers/mmc/host/sdhci-sprd.c static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) reg 136 drivers/mmc/host/sdhci-sprd.c if (unlikely(reg == SDHCI_BLOCK_COUNT)) reg 139 drivers/mmc/host/sdhci-sprd.c writew_relaxed(val, host->ioaddr + reg); reg 142 drivers/mmc/host/sdhci-sprd.c static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) reg 152 drivers/mmc/host/sdhci-sprd.c if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { reg 153 drivers/mmc/host/sdhci-sprd.c if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) reg 157 drivers/mmc/host/sdhci-sprd.c writeb_relaxed(val, host->ioaddr + reg); reg 307 drivers/mmc/host/sdhci-st.c static u32 sdhci_st_readl(struct sdhci_host *host, int reg) reg 311 drivers/mmc/host/sdhci-st.c switch (reg) { reg 313 drivers/mmc/host/sdhci-st.c ret = readl_relaxed(host->ioaddr + reg); reg 318 drivers/mmc/host/sdhci-st.c ret = readl_relaxed(host->ioaddr + reg); reg 155 drivers/mmc/host/sdhci-tegra.c static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) reg 162 drivers/mmc/host/sdhci-tegra.c (reg == SDHCI_HOST_VERSION))) { reg 167 drivers/mmc/host/sdhci-tegra.c return readw(host->ioaddr + reg); reg 170 drivers/mmc/host/sdhci-tegra.c static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) reg 174 drivers/mmc/host/sdhci-tegra.c switch (reg) { reg 188 drivers/mmc/host/sdhci-tegra.c writew(val, host->ioaddr + reg); reg 191 drivers/mmc/host/sdhci-tegra.c static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) reg 201 drivers/mmc/host/sdhci-tegra.c if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) reg 204 drivers/mmc/host/sdhci-tegra.c writel(val, host->ioaddr + reg); reg 207 drivers/mmc/host/sdhci-tegra.c (reg == SDHCI_INT_ENABLE))) { reg 221 drivers/mmc/host/sdhci-tegra.c u32 reg; reg 223 drivers/mmc/host/sdhci-tegra.c reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); reg 224 drivers/mmc/host/sdhci-tegra.c status = !!(reg & SDHCI_CLOCK_CARD_EN); reg 230 drivers/mmc/host/sdhci-tegra.c reg |= SDHCI_CLOCK_CARD_EN; reg 232 drivers/mmc/host/sdhci-tegra.c reg &= ~SDHCI_CLOCK_CARD_EN; reg 234 drivers/mmc/host/sdhci-tegra.c sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); reg 239 drivers/mmc/host/sdhci-tegra.c static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg) reg 245 drivers/mmc/host/sdhci-tegra.c if (reg == SDHCI_COMMAND) { reg 254 drivers/mmc/host/sdhci-tegra.c writew(val, host->ioaddr + reg); reg 312 drivers/mmc/host/sdhci-tegra.c u32 reg; reg 323 drivers/mmc/host/sdhci-tegra.c reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); reg 324 drivers/mmc/host/sdhci-tegra.c reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; reg 325 drivers/mmc/host/sdhci-tegra.c reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; reg 326 drivers/mmc/host/sdhci-tegra.c sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); reg 434 drivers/mmc/host/sdhci-tegra.c u32 reg; reg 436 drivers/mmc/host/sdhci-tegra.c reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); reg 437 drivers/mmc/host/sdhci-tegra.c reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; reg 438 drivers/mmc/host/sdhci-tegra.c reg |= pdpu; reg 439 drivers/mmc/host/sdhci-tegra.c sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); reg 452 drivers/mmc/host/sdhci-tegra.c u32 reg; reg 481 drivers/mmc/host/sdhci-tegra.c reg = sdhci_readl(host, reg 483 drivers/mmc/host/sdhci-tegra.c reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK; reg 484 drivers/mmc/host/sdhci-tegra.c reg |= (drvup << 20) | (drvdn << 12); reg 485 drivers/mmc/host/sdhci-tegra.c sdhci_writel(host, reg, reg 521 drivers/mmc/host/sdhci-tegra.c u32 reg; reg 545 drivers/mmc/host/sdhci-tegra.c reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); reg 546 drivers/mmc/host/sdhci-tegra.c reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; reg 547 drivers/mmc/host/sdhci-tegra.c sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); reg 552 drivers/mmc/host/sdhci-tegra.c reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), reg 563 drivers/mmc/host/sdhci-tegra.c reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); reg 564 drivers/mmc/host/sdhci-tegra.c reg &= ~SDHCI_AUTO_CAL_ENABLE; reg 565 drivers/mmc/host/sdhci-tegra.c sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); reg 783 drivers/mmc/host/sdhci-tegra.c u32 reg; reg 786 drivers/mmc/host/sdhci-tegra.c reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); reg 787 drivers/mmc/host/sdhci-tegra.c reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE; reg 788 drivers/mmc/host/sdhci-tegra.c sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); reg 792 drivers/mmc/host/sdhci-tegra.c reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE), reg 1130 drivers/mmc/host/sdhci-tegra.c static void tegra_cqhci_writel(struct cqhci_host *cq_host, u32 val, int reg) reg 1145 drivers/mmc/host/sdhci-tegra.c if (reg == CQHCI_CTL && !(val & CQHCI_HALT) && reg 1148 drivers/mmc/host/sdhci-tegra.c writel(val, cq_host->mmio + reg); reg 1161 drivers/mmc/host/sdhci-tegra.c writel(val, cq_host->mmio + reg); reg 1163 drivers/mmc/host/sdhci-tegra.c writel(val, cq_host->mmio + reg); reg 153 drivers/mmc/host/sdhci-xenon-phy.c void __iomem *reg; reg 229 drivers/mmc/host/sdhci-xenon-phy.c u32 reg; reg 235 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, phy_regs->timing_adj); reg 236 drivers/mmc/host/sdhci-xenon-phy.c reg |= XENON_PHY_INITIALIZAION; reg 237 drivers/mmc/host/sdhci-xenon-phy.c sdhci_writel(host, reg, phy_regs->timing_adj); reg 240 drivers/mmc/host/sdhci-xenon-phy.c wait = ((reg >> XENON_FC_SYNC_RST_DURATION_SHIFT) & reg 243 drivers/mmc/host/sdhci-xenon-phy.c wait += ((reg >> XENON_FC_SYNC_RST_EN_DURATION_SHIFT) & reg 246 drivers/mmc/host/sdhci-xenon-phy.c wait += ((reg >> XENON_FC_SYNC_EN_DURATION_SHIFT) & reg 249 drivers/mmc/host/sdhci-xenon-phy.c wait += ((reg >> XENON_WAIT_CYCLE_BEFORE_USING_SHIFT) & reg 265 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, phy_regs->timing_adj); reg 266 drivers/mmc/host/sdhci-xenon-phy.c reg &= XENON_PHY_INITIALIZAION; reg 267 drivers/mmc/host/sdhci-xenon-phy.c if (reg) { reg 287 drivers/mmc/host/sdhci-xenon-phy.c writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg); reg 290 drivers/mmc/host/sdhci-xenon-phy.c writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg); reg 292 drivers/mmc/host/sdhci-xenon-phy.c writel(ARMADA_3700_SOC_PAD_3_3V, params->pad_ctrl.reg); reg 308 drivers/mmc/host/sdhci-xenon-phy.c if (!params->pad_ctrl.reg) reg 322 drivers/mmc/host/sdhci-xenon-phy.c u32 reg; reg 331 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, phy_regs->dll_ctrl); reg 332 drivers/mmc/host/sdhci-xenon-phy.c if (reg & XENON_DLL_ENABLE) reg 336 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, phy_regs->dll_ctrl); reg 337 drivers/mmc/host/sdhci-xenon-phy.c reg |= (XENON_DLL_ENABLE | XENON_DLL_FAST_LOCK); reg 344 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~((XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL0_SHIFT) | reg 346 drivers/mmc/host/sdhci-xenon-phy.c reg |= ((XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL0_SHIFT) | reg 349 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~XENON_DLL_BYPASS_EN; reg 350 drivers/mmc/host/sdhci-xenon-phy.c reg |= phy_regs->dll_update; reg 352 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~XENON_DLL_REFCLK_SEL; reg 353 drivers/mmc/host/sdhci-xenon-phy.c sdhci_writel(host, reg, phy_regs->dll_ctrl); reg 381 drivers/mmc/host/sdhci-xenon-phy.c u32 reg, tuning_step; reg 392 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL); reg 393 drivers/mmc/host/sdhci-xenon-phy.c tuning_step = reg / params->tun_step_divider; reg 402 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL); reg 403 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~(XENON_TUN_CONSECUTIVE_TIMES_MASK << reg 405 drivers/mmc/host/sdhci-xenon-phy.c reg |= (params->nr_tun_times << XENON_TUN_CONSECUTIVE_TIMES_SHIFT); reg 406 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~(XENON_TUNING_STEP_MASK << XENON_TUNING_STEP_SHIFT); reg 407 drivers/mmc/host/sdhci-xenon-phy.c reg |= (tuning_step << XENON_TUNING_STEP_SHIFT); reg 408 drivers/mmc/host/sdhci-xenon-phy.c sdhci_writel(host, reg, XENON_SLOT_OP_STATUS_CTRL); reg 417 drivers/mmc/host/sdhci-xenon-phy.c u32 reg; reg 420 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); reg 421 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~(XENON_ENABLE_DATA_STROBE | XENON_ENABLE_RESP_STROBE); reg 422 drivers/mmc/host/sdhci-xenon-phy.c sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL); reg 426 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL); reg 427 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~(XENON_EMMC5_FC_QSP_PD | XENON_EMMC5_FC_QSP_PU); reg 428 drivers/mmc/host/sdhci-xenon-phy.c sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL); reg 430 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1); reg 431 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~(XENON_EMMC5_1_FC_QSP_PD | XENON_EMMC5_1_FC_QSP_PU); reg 432 drivers/mmc/host/sdhci-xenon-phy.c sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1); reg 441 drivers/mmc/host/sdhci-xenon-phy.c u32 reg; reg 454 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); reg 455 drivers/mmc/host/sdhci-xenon-phy.c reg |= XENON_ENABLE_DATA_STROBE; reg 464 drivers/mmc/host/sdhci-xenon-phy.c reg |= XENON_ENABLE_RESP_STROBE; reg 465 drivers/mmc/host/sdhci-xenon-phy.c sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL); reg 469 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL); reg 470 drivers/mmc/host/sdhci-xenon-phy.c reg |= XENON_EMMC5_FC_QSP_PD; reg 471 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~XENON_EMMC5_FC_QSP_PU; reg 472 drivers/mmc/host/sdhci-xenon-phy.c sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL); reg 474 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1); reg 475 drivers/mmc/host/sdhci-xenon-phy.c reg |= XENON_EMMC5_1_FC_QSP_PD; reg 476 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~XENON_EMMC5_1_FC_QSP_PU; reg 477 drivers/mmc/host/sdhci-xenon-phy.c sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1); reg 496 drivers/mmc/host/sdhci-xenon-phy.c u32 reg; reg 502 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, phy_regs->timing_adj); reg 513 drivers/mmc/host/sdhci-xenon-phy.c reg |= XENON_TIMING_ADJUST_SLOW_MODE; reg 516 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~XENON_TIMING_ADJUST_SLOW_MODE; reg 526 drivers/mmc/host/sdhci-xenon-phy.c reg |= XENON_TIMING_ADJUST_SLOW_MODE; reg 532 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~XENON_TIMING_ADJUST_SLOW_MODE; reg 536 drivers/mmc/host/sdhci-xenon-phy.c sdhci_writel(host, reg, phy_regs->timing_adj); reg 547 drivers/mmc/host/sdhci-xenon-phy.c u32 reg; reg 556 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, phy_regs->pad_ctrl); reg 557 drivers/mmc/host/sdhci-xenon-phy.c reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN | reg 560 drivers/mmc/host/sdhci-xenon-phy.c reg |= XENON_FC_ALL_CMOS_RECEIVER; reg 561 drivers/mmc/host/sdhci-xenon-phy.c sdhci_writel(host, reg, phy_regs->pad_ctrl); reg 565 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL); reg 566 drivers/mmc/host/sdhci-xenon-phy.c reg |= (XENON_EMMC5_FC_CMD_PU | XENON_EMMC5_FC_DQ_PU); reg 567 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~(XENON_EMMC5_FC_CMD_PD | XENON_EMMC5_FC_DQ_PD); reg 568 drivers/mmc/host/sdhci-xenon-phy.c sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL); reg 570 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1); reg 571 drivers/mmc/host/sdhci-xenon-phy.c reg |= (XENON_EMMC5_1_FC_CMD_PU | XENON_EMMC5_1_FC_DQ_PU); reg 572 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~(XENON_EMMC5_1_FC_CMD_PD | XENON_EMMC5_1_FC_DQ_PD); reg 573 drivers/mmc/host/sdhci-xenon-phy.c sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1); reg 585 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, phy_regs->timing_adj); reg 587 drivers/mmc/host/sdhci-xenon-phy.c reg |= XENON_TIMING_ADJUST_SDIO_MODE; reg 589 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~XENON_TIMING_ADJUST_SDIO_MODE; reg 590 drivers/mmc/host/sdhci-xenon-phy.c sdhci_writel(host, reg, phy_regs->timing_adj); reg 600 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, phy_regs->pad_ctrl2); reg 601 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK); reg 602 drivers/mmc/host/sdhci-xenon-phy.c reg |= ((params->znr << XENON_ZNR_SHIFT) | params->zpr); reg 603 drivers/mmc/host/sdhci-xenon-phy.c sdhci_writel(host, reg, phy_regs->pad_ctrl2); reg 609 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); reg 610 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~SDHCI_CLOCK_CARD_EN; reg 611 drivers/mmc/host/sdhci-xenon-phy.c sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); reg 613 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, phy_regs->func_ctrl); reg 616 drivers/mmc/host/sdhci-xenon-phy.c reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | reg 618 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~XENON_DQ_ASYNC_MODE; reg 622 drivers/mmc/host/sdhci-xenon-phy.c reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | reg 626 drivers/mmc/host/sdhci-xenon-phy.c reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | reg 628 drivers/mmc/host/sdhci-xenon-phy.c reg |= XENON_DQ_ASYNC_MODE; reg 630 drivers/mmc/host/sdhci-xenon-phy.c sdhci_writel(host, reg, phy_regs->func_ctrl); reg 633 drivers/mmc/host/sdhci-xenon-phy.c reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); reg 634 drivers/mmc/host/sdhci-xenon-phy.c reg |= SDHCI_CLOCK_CARD_EN; reg 635 drivers/mmc/host/sdhci-xenon-phy.c sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); reg 669 drivers/mmc/host/sdhci-xenon-phy.c params->pad_ctrl.reg = devm_ioremap_resource(mmc_dev(host->mmc), reg 671 drivers/mmc/host/sdhci-xenon-phy.c if (IS_ERR(params->pad_ctrl.reg)) reg 672 drivers/mmc/host/sdhci-xenon-phy.c return PTR_ERR(params->pad_ctrl.reg); reg 26 drivers/mmc/host/sdhci-xenon.c u32 reg; reg 29 drivers/mmc/host/sdhci-xenon.c reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); reg 30 drivers/mmc/host/sdhci-xenon.c reg |= SDHCI_CLOCK_INT_EN; reg 31 drivers/mmc/host/sdhci-xenon.c sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL); reg 37 drivers/mmc/host/sdhci-xenon.c reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); reg 38 drivers/mmc/host/sdhci-xenon.c if (reg & SDHCI_CLOCK_INT_STABLE) reg 54 drivers/mmc/host/sdhci-xenon.c u32 reg; reg 57 drivers/mmc/host/sdhci-xenon.c reg = sdhci_readl(host, XENON_SYS_OP_CTRL); reg 61 drivers/mmc/host/sdhci-xenon.c reg |= mask; reg 63 drivers/mmc/host/sdhci-xenon.c reg &= ~mask; reg 65 drivers/mmc/host/sdhci-xenon.c sdhci_writel(host, reg, XENON_SYS_OP_CTRL); reg 71 drivers/mmc/host/sdhci-xenon.c u32 reg; reg 73 drivers/mmc/host/sdhci-xenon.c reg = sdhci_readl(host, XENON_SYS_OP_CTRL); reg 75 drivers/mmc/host/sdhci-xenon.c reg &= ~XENON_AUTO_CLKGATE_DISABLE_MASK; reg 77 drivers/mmc/host/sdhci-xenon.c reg |= XENON_AUTO_CLKGATE_DISABLE_MASK; reg 78 drivers/mmc/host/sdhci-xenon.c sdhci_writel(host, reg, XENON_SYS_OP_CTRL); reg 85 drivers/mmc/host/sdhci-xenon.c u32 reg; reg 87 drivers/mmc/host/sdhci-xenon.c reg = sdhci_readl(host, XENON_SYS_OP_CTRL); reg 88 drivers/mmc/host/sdhci-xenon.c reg |= (BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT); reg 89 drivers/mmc/host/sdhci-xenon.c sdhci_writel(host, reg, XENON_SYS_OP_CTRL); reg 103 drivers/mmc/host/sdhci-xenon.c u32 reg; reg 105 drivers/mmc/host/sdhci-xenon.c reg = sdhci_readl(host, XENON_SYS_OP_CTRL); reg 106 drivers/mmc/host/sdhci-xenon.c reg &= ~(BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT); reg 107 drivers/mmc/host/sdhci-xenon.c sdhci_writel(host, reg, XENON_SYS_OP_CTRL); reg 114 drivers/mmc/host/sdhci-xenon.c u32 reg; reg 116 drivers/mmc/host/sdhci-xenon.c reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); reg 117 drivers/mmc/host/sdhci-xenon.c reg |= BIT(sdhc_id); reg 118 drivers/mmc/host/sdhci-xenon.c sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL); reg 124 drivers/mmc/host/sdhci-xenon.c u32 reg; reg 126 drivers/mmc/host/sdhci-xenon.c reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); reg 127 drivers/mmc/host/sdhci-xenon.c reg |= XENON_MASK_CMD_CONFLICT_ERR; reg 128 drivers/mmc/host/sdhci-xenon.c sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL); reg 135 drivers/mmc/host/sdhci-xenon.c u32 reg; reg 138 drivers/mmc/host/sdhci-xenon.c reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL); reg 139 drivers/mmc/host/sdhci-xenon.c reg &= ~XENON_RETUNING_COMPATIBLE; reg 140 drivers/mmc/host/sdhci-xenon.c sdhci_writel(host, reg, XENON_SLOT_RETUNING_REQ_CTRL); reg 143 drivers/mmc/host/sdhci-xenon.c reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); reg 144 drivers/mmc/host/sdhci-xenon.c reg &= ~SDHCI_INT_RETUNE; reg 145 drivers/mmc/host/sdhci-xenon.c sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE); reg 146 drivers/mmc/host/sdhci-xenon.c reg = sdhci_readl(host, SDHCI_INT_ENABLE); reg 147 drivers/mmc/host/sdhci-xenon.c reg &= ~SDHCI_INT_RETUNE; reg 148 drivers/mmc/host/sdhci-xenon.c sdhci_writel(host, reg, SDHCI_INT_ENABLE); reg 275 drivers/mmc/host/sdhci-xenon.c u32 reg; reg 291 drivers/mmc/host/sdhci-xenon.c reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); reg 292 drivers/mmc/host/sdhci-xenon.c reg &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; reg 293 drivers/mmc/host/sdhci-xenon.c sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); reg 373 drivers/mmc/host/sdhci-xenon.c u32 reg; reg 383 drivers/mmc/host/sdhci-xenon.c reg = sdhci_readl(host, XENON_SYS_CFG_INFO); reg 384 drivers/mmc/host/sdhci-xenon.c reg |= (1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT)); reg 385 drivers/mmc/host/sdhci-xenon.c sdhci_writel(host, reg, XENON_SYS_CFG_INFO); reg 388 drivers/mmc/host/sdhci-xenon.c reg = sdhci_readl(host, XENON_SYS_CFG_INFO); reg 389 drivers/mmc/host/sdhci-xenon.c reg &= ~(1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT)); reg 390 drivers/mmc/host/sdhci-xenon.c sdhci_writel(host, reg, XENON_SYS_CFG_INFO); reg 1438 drivers/mmc/host/sdhci.c int i, reg; reg 1441 drivers/mmc/host/sdhci.c reg = SDHCI_RESPONSE + (3 - i) * 4; reg 1442 drivers/mmc/host/sdhci.c cmd->resp[i] = sdhci_readl(host, reg); reg 613 drivers/mmc/host/sdhci.h u32 (*read_l)(struct sdhci_host *host, int reg); reg 614 drivers/mmc/host/sdhci.h u16 (*read_w)(struct sdhci_host *host, int reg); reg 615 drivers/mmc/host/sdhci.h u8 (*read_b)(struct sdhci_host *host, int reg); reg 616 drivers/mmc/host/sdhci.h void (*write_l)(struct sdhci_host *host, u32 val, int reg); reg 617 drivers/mmc/host/sdhci.h void (*write_w)(struct sdhci_host *host, u16 val, int reg); reg 618 drivers/mmc/host/sdhci.h void (*write_b)(struct sdhci_host *host, u8 val, int reg); reg 653 drivers/mmc/host/sdhci.h static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) reg 656 drivers/mmc/host/sdhci.h host->ops->write_l(host, val, reg); reg 658 drivers/mmc/host/sdhci.h writel(val, host->ioaddr + reg); reg 661 drivers/mmc/host/sdhci.h static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) reg 664 drivers/mmc/host/sdhci.h host->ops->write_w(host, val, reg); reg 666 drivers/mmc/host/sdhci.h writew(val, host->ioaddr + reg); reg 669 drivers/mmc/host/sdhci.h static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) reg 672 drivers/mmc/host/sdhci.h host->ops->write_b(host, val, reg); reg 674 drivers/mmc/host/sdhci.h writeb(val, host->ioaddr + reg); reg 677 drivers/mmc/host/sdhci.h static inline u32 sdhci_readl(struct sdhci_host *host, int reg) reg 680 drivers/mmc/host/sdhci.h return host->ops->read_l(host, reg); reg 682 drivers/mmc/host/sdhci.h return readl(host->ioaddr + reg); reg 685 drivers/mmc/host/sdhci.h static inline u16 sdhci_readw(struct sdhci_host *host, int reg) reg 688 drivers/mmc/host/sdhci.h return host->ops->read_w(host, reg); reg 690 drivers/mmc/host/sdhci.h return readw(host->ioaddr + reg); reg 693 drivers/mmc/host/sdhci.h static inline u8 sdhci_readb(struct sdhci_host *host, int reg) reg 696 drivers/mmc/host/sdhci.h return host->ops->read_b(host, reg); reg 698 drivers/mmc/host/sdhci.h return readb(host->ioaddr + reg); reg 703 drivers/mmc/host/sdhci.h static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) reg 705 drivers/mmc/host/sdhci.h writel(val, host->ioaddr + reg); reg 708 drivers/mmc/host/sdhci.h static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) reg 710 drivers/mmc/host/sdhci.h writew(val, host->ioaddr + reg); reg 713 drivers/mmc/host/sdhci.h static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) reg 715 drivers/mmc/host/sdhci.h writeb(val, host->ioaddr + reg); reg 718 drivers/mmc/host/sdhci.h static inline u32 sdhci_readl(struct sdhci_host *host, int reg) reg 720 drivers/mmc/host/sdhci.h return readl(host->ioaddr + reg); reg 723 drivers/mmc/host/sdhci.h static inline u16 sdhci_readw(struct sdhci_host *host, int reg) reg 725 drivers/mmc/host/sdhci.h return readw(host->ioaddr + reg); reg 728 drivers/mmc/host/sdhci.h static inline u8 sdhci_readb(struct sdhci_host *host, int reg) reg 730 drivers/mmc/host/sdhci.h return readb(host->ioaddr + reg); reg 218 drivers/mmc/host/sdhci_am654.c static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) reg 222 drivers/mmc/host/sdhci_am654.c if (reg == SDHCI_HOST_CONTROL) { reg 236 drivers/mmc/host/sdhci_am654.c writeb(val, host->ioaddr + reg); reg 119 drivers/mmc/host/sdhci_f_sdh30.c u32 reg = 0; reg 188 drivers/mmc/host/sdhci_f_sdh30.c reg = sdhci_readl(host, F_SDH30_ESD_CONTROL); reg 189 drivers/mmc/host/sdhci_f_sdh30.c sdhci_writel(host, reg & ~F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL); reg 191 drivers/mmc/host/sdhci_f_sdh30.c sdhci_writel(host, reg | F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL); reg 193 drivers/mmc/host/sdhci_f_sdh30.c reg = sdhci_readl(host, SDHCI_CAPABILITIES); reg 194 drivers/mmc/host/sdhci_f_sdh30.c if (reg & SDHCI_CAN_DO_8BIT) reg 89 drivers/mmc/host/sdricoh_cs.c unsigned int reg) reg 91 drivers/mmc/host/sdricoh_cs.c unsigned int value = readl(host->iobase + reg); reg 92 drivers/mmc/host/sdricoh_cs.c dev_vdbg(host->dev, "rl %x 0x%x\n", reg, value); reg 96 drivers/mmc/host/sdricoh_cs.c static inline void sdricoh_writel(struct sdricoh_host *host, unsigned int reg, reg 99 drivers/mmc/host/sdricoh_cs.c writel(value, host->iobase + reg); reg 100 drivers/mmc/host/sdricoh_cs.c dev_vdbg(host->dev, "wl %x 0x%x\n", reg, value); reg 105 drivers/mmc/host/sdricoh_cs.c unsigned int reg) reg 107 drivers/mmc/host/sdricoh_cs.c unsigned int value = readw(host->iobase + reg); reg 108 drivers/mmc/host/sdricoh_cs.c dev_vdbg(host->dev, "rb %x 0x%x\n", reg, value); reg 112 drivers/mmc/host/sdricoh_cs.c static inline void sdricoh_writew(struct sdricoh_host *host, unsigned int reg, reg 115 drivers/mmc/host/sdricoh_cs.c writew(value, host->iobase + reg); reg 116 drivers/mmc/host/sdricoh_cs.c dev_vdbg(host->dev, "ww %x 0x%x\n", reg, value); reg 120 drivers/mmc/host/sdricoh_cs.c unsigned int reg) reg 122 drivers/mmc/host/sdricoh_cs.c unsigned int value = readb(host->iobase + reg); reg 123 drivers/mmc/host/sdricoh_cs.c dev_vdbg(host->dev, "rb %x 0x%x\n", reg, value); reg 261 drivers/mmc/host/sh_mmcif.c unsigned int reg, u32 val) reg 263 drivers/mmc/host/sh_mmcif.c writel(val | readl(host->addr + reg), host->addr + reg); reg 267 drivers/mmc/host/sh_mmcif.c unsigned int reg, u32 val) reg 269 drivers/mmc/host/sh_mmcif.c writel(~val & readl(host->addr + reg), host->addr + reg); reg 1392 drivers/mmc/host/sh_mmcif.c void __iomem *reg; reg 1401 drivers/mmc/host/sh_mmcif.c reg = devm_ioremap_resource(dev, res); reg 1402 drivers/mmc/host/sh_mmcif.c if (IS_ERR(reg)) reg 1403 drivers/mmc/host/sh_mmcif.c return PTR_ERR(reg); reg 1415 drivers/mmc/host/sh_mmcif.c host->addr = reg; reg 76 drivers/mmc/host/sunxi-mmc.c #define mmc_readl(host, reg) \ reg 77 drivers/mmc/host/sunxi-mmc.c readl((host)->reg_base + SDXC_##reg) reg 78 drivers/mmc/host/sunxi-mmc.c #define mmc_writel(host, reg, value) \ reg 79 drivers/mmc/host/sunxi-mmc.c writel((value), (host)->reg_base + SDXC_##reg) reg 916 drivers/mmc/host/tmio_mmc_core.c u16 reg = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT) reg 921 drivers/mmc/host/tmio_mmc_core.c reg |= CARD_OPT_WIDTH; reg 923 drivers/mmc/host/tmio_mmc_core.c reg |= CARD_OPT_WIDTH8; reg 925 drivers/mmc/host/tmio_mmc_core.c sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, reg); reg 208 drivers/mmc/host/usdhi6rol0.c static void usdhi6_write(struct usdhi6_host *host, u32 reg, u32 data) reg 210 drivers/mmc/host/usdhi6rol0.c iowrite32(data, host->base + reg); reg 212 drivers/mmc/host/usdhi6rol0.c host->base, reg, data); reg 215 drivers/mmc/host/usdhi6rol0.c static void usdhi6_write16(struct usdhi6_host *host, u32 reg, u16 data) reg 217 drivers/mmc/host/usdhi6rol0.c iowrite16(data, host->base + reg); reg 219 drivers/mmc/host/usdhi6rol0.c host->base, reg, data); reg 222 drivers/mmc/host/usdhi6rol0.c static u32 usdhi6_read(struct usdhi6_host *host, u32 reg) reg 224 drivers/mmc/host/usdhi6rol0.c u32 data = ioread32(host->base + reg); reg 226 drivers/mmc/host/usdhi6rol0.c host->base, reg, data); reg 230 drivers/mmc/host/usdhi6rol0.c static u16 usdhi6_read16(struct usdhi6_host *host, u32 reg) reg 232 drivers/mmc/host/usdhi6rol0.c u16 data = ioread16(host->base + reg); reg 234 drivers/mmc/host/usdhi6rol0.c host->base, reg, data); reg 135 drivers/mmc/host/vub300.c struct offload_registers_access reg[INTERRUPT_REGISTER_ACCESSES]; reg 150 drivers/mmc/host/vub300.c struct offload_registers_access reg[PIGGYBACK_REGISTER_ACCESSES]; reg 330 drivers/mmc/host/vub300.c struct offload_registers_access reg[MAXREGS]; reg 534 drivers/mmc/host/vub300.c memcpy(&vub300->fn[func].reg[MAXREGMASK & r], register_access, reg 616 drivers/mmc/host/vub300.c add_offloaded_reg(vub300, &vub300->resp.irq.reg[ri]); reg 634 drivers/mmc/host/vub300.c add_offloaded_reg(vub300, &vub300->resp.irq.reg[ri]); reg 1648 drivers/mmc/host/vub300.c add_offloaded_reg(vub300, &vub300->resp.pig.reg[ri]); reg 1662 drivers/mmc/host/vub300.c add_offloaded_reg(vub300, &vub300->resp.pig.reg[ri]); reg 1687 drivers/mmc/host/vub300.c add_offloaded_reg(vub300, &vub300->resp.pig.reg[ri]); reg 1803 drivers/mmc/host/vub300.c struct offload_registers_access *rf = &vub300->fn[Function].reg[first]; reg 1825 drivers/mmc/host/vub300.c &vub300->fn[Function].reg[point]; reg 1858 drivers/mmc/host/vub300.c u32 reg = REG(cmd); reg 1861 drivers/mmc/host/vub300.c (vub300->sdio_register[i].sdio_reg == reg)) { reg 97 drivers/mmc/host/wbsd.c static inline void wbsd_write_config(struct wbsd_host *host, u8 reg, u8 value) reg 101 drivers/mmc/host/wbsd.c outb(reg, host->config); reg 105 drivers/mmc/host/wbsd.c static inline u8 wbsd_read_config(struct wbsd_host *host, u8 reg) reg 109 drivers/mmc/host/wbsd.c outb(reg, host->config); reg 92 drivers/mtd/devices/docg3.c static inline u8 doc_readb(struct docg3 *docg3, u16 reg) reg 94 drivers/mtd/devices/docg3.c u8 val = readb(docg3->cascade->base + reg); reg 96 drivers/mtd/devices/docg3.c trace_docg3_io(0, 8, reg, (int)val); reg 100 drivers/mtd/devices/docg3.c static inline u16 doc_readw(struct docg3 *docg3, u16 reg) reg 102 drivers/mtd/devices/docg3.c u16 val = readw(docg3->cascade->base + reg); reg 104 drivers/mtd/devices/docg3.c trace_docg3_io(0, 16, reg, (int)val); reg 108 drivers/mtd/devices/docg3.c static inline void doc_writeb(struct docg3 *docg3, u8 val, u16 reg) reg 110 drivers/mtd/devices/docg3.c writeb(val, docg3->cascade->base + reg); reg 111 drivers/mtd/devices/docg3.c trace_docg3_io(1, 8, reg, val); reg 114 drivers/mtd/devices/docg3.c static inline void doc_writew(struct docg3 *docg3, u16 val, u16 reg) reg 116 drivers/mtd/devices/docg3.c writew(val, docg3->cascade->base + reg); reg 117 drivers/mtd/devices/docg3.c trace_docg3_io(1, 16, reg, val); reg 137 drivers/mtd/devices/docg3.c static int doc_register_readb(struct docg3 *docg3, int reg) reg 141 drivers/mtd/devices/docg3.c doc_writew(docg3, reg, DOC_READADDRESS); reg 142 drivers/mtd/devices/docg3.c val = doc_readb(docg3, reg); reg 143 drivers/mtd/devices/docg3.c doc_vdbg("Read register %04x : %02x\n", reg, val); reg 147 drivers/mtd/devices/docg3.c static int doc_register_readw(struct docg3 *docg3, int reg) reg 151 drivers/mtd/devices/docg3.c doc_writew(docg3, reg, DOC_READADDRESS); reg 152 drivers/mtd/devices/docg3.c val = doc_readw(docg3, reg); reg 153 drivers/mtd/devices/docg3.c doc_vdbg("Read register %04x : %04x\n", reg, val); reg 320 drivers/mtd/devices/docg3.h TP_PROTO(int op, int width, u16 reg, int val), reg 321 drivers/mtd/devices/docg3.h TP_ARGS(op, width, reg, val), reg 325 drivers/mtd/devices/docg3.h __field(u16, reg) reg 330 drivers/mtd/devices/docg3.h __entry->reg = reg; reg 334 drivers/mtd/devices/docg3.h __entry->reg, __entry->val) reg 138 drivers/mtd/maps/scb2_flash.c u8 reg; reg 141 drivers/mtd/maps/scb2_flash.c pci_read_config_byte(dev, CSB5_FCR, ®); reg 142 drivers/mtd/maps/scb2_flash.c pci_write_config_byte(dev, CSB5_FCR, reg | CSB5_FCR_DECODE_ALL); reg 59 drivers/mtd/nand/onenand/omap2.c static inline unsigned short read_reg(struct omap2_onenand *c, int reg) reg 61 drivers/mtd/nand/onenand/omap2.c return readw(c->onenand.base + reg); reg 65 drivers/mtd/nand/onenand/omap2.c int reg) reg 67 drivers/mtd/nand/onenand/omap2.c writew(value, c->onenand.base + reg); reg 74 drivers/mtd/nand/onenand/omap2.c unsigned short reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT; reg 76 drivers/mtd/nand/onenand/omap2.c reg |= latency << ONENAND_SYS_CFG1_BRL_SHIFT; reg 82 drivers/mtd/nand/onenand/omap2.c reg |= ONENAND_SYS_CFG1_BL_4; reg 85 drivers/mtd/nand/onenand/omap2.c reg |= ONENAND_SYS_CFG1_BL_8; reg 88 drivers/mtd/nand/onenand/omap2.c reg |= ONENAND_SYS_CFG1_BL_16; reg 91 drivers/mtd/nand/onenand/omap2.c reg |= ONENAND_SYS_CFG1_BL_32; reg 98 drivers/mtd/nand/onenand/omap2.c reg |= ONENAND_SYS_CFG1_HF; reg 100 drivers/mtd/nand/onenand/omap2.c reg |= ONENAND_SYS_CFG1_VHF; reg 102 drivers/mtd/nand/onenand/omap2.c reg |= ONENAND_SYS_CFG1_SYNC_READ; reg 104 drivers/mtd/nand/onenand/omap2.c reg |= ONENAND_SYS_CFG1_SYNC_WRITE; reg 106 drivers/mtd/nand/onenand/omap2.c write_reg(c, reg, ONENAND_REG_SYS_CFG1); reg 220 drivers/mtd/nand/onenand/samsung.c int reg = addr - this->base; reg 221 drivers/mtd/nand/onenand/samsung.c int word_addr = reg >> 1; reg 225 drivers/mtd/nand/onenand/samsung.c switch (reg) { reg 270 drivers/mtd/nand/onenand/samsung.c unsigned int reg = addr - this->base; reg 271 drivers/mtd/nand/onenand/samsung.c unsigned int word_addr = reg >> 1; reg 274 drivers/mtd/nand/onenand/samsung.c switch (reg) { reg 605 drivers/mtd/nand/raw/brcmnand/brcmnand.c enum brcmnand_reg reg) reg 607 drivers/mtd/nand/raw/brcmnand/brcmnand.c u16 offs = ctrl->reg_offsets[reg]; reg 616 drivers/mtd/nand/raw/brcmnand/brcmnand.c enum brcmnand_reg reg, u32 val) reg 618 drivers/mtd/nand/raw/brcmnand/brcmnand.c u16 offs = ctrl->reg_offsets[reg]; reg 625 drivers/mtd/nand/raw/brcmnand/brcmnand.c enum brcmnand_reg reg, u32 mask, unsigned reg 628 drivers/mtd/nand/raw/brcmnand/brcmnand.c u32 tmp = brcmnand_read_reg(ctrl, reg); reg 632 drivers/mtd/nand/raw/brcmnand/brcmnand.c brcmnand_write_reg(ctrl, reg, tmp); reg 695 drivers/mtd/nand/raw/brcmnand/brcmnand.c enum brcmnand_cs_reg reg) reg 702 drivers/mtd/nand/raw/brcmnand/brcmnand.c cs_offs = ctrl->cs0_offsets[reg]; reg 704 drivers/mtd/nand/raw/brcmnand/brcmnand.c cs_offs = ctrl->cs_offsets[reg]; reg 723 drivers/mtd/nand/raw/brcmnand/brcmnand.c enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD; reg 737 drivers/mtd/nand/raw/brcmnand/brcmnand.c reg = BRCMNAND_CORR_THRESHOLD_EXT; reg 741 drivers/mtd/nand/raw/brcmnand/brcmnand.c reg = BRCMNAND_CORR_THRESHOLD_EXT; reg 744 drivers/mtd/nand/raw/brcmnand/brcmnand.c brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val); reg 95 drivers/mtd/nand/raw/denali.c iowrite32(U32_MAX, denali->reg + INTR_EN(i)); reg 96 drivers/mtd/nand/raw/denali.c iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE); reg 104 drivers/mtd/nand/raw/denali.c iowrite32(0, denali->reg + INTR_EN(i)); reg 105 drivers/mtd/nand/raw/denali.c iowrite32(0, denali->reg + GLOBAL_INT_ENABLE); reg 112 drivers/mtd/nand/raw/denali.c iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); reg 133 drivers/mtd/nand/raw/denali.c irq_status = ioread32(denali->reg + INTR_STATUS(i)); reg 202 drivers/mtd/nand/raw/denali.c denali->reg + PAGES_PER_BLOCK); reg 204 drivers/mtd/nand/raw/denali.c denali->reg + DEVICE_WIDTH); reg 205 drivers/mtd/nand/raw/denali.c iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE); reg 206 drivers/mtd/nand/raw/denali.c iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE); reg 209 drivers/mtd/nand/raw/denali.c denali->reg + TWO_ROW_ADDR_CYCLES); reg 212 drivers/mtd/nand/raw/denali.c denali->reg + ECC_CORRECTION); reg 213 drivers/mtd/nand/raw/denali.c iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE); reg 214 drivers/mtd/nand/raw/denali.c iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE); reg 215 drivers/mtd/nand/raw/denali.c iowrite32(chip->ecc.steps, denali->reg + CFG_NUM_DATA_BLOCKS); reg 221 drivers/mtd/nand/raw/denali.c iowrite32(sel->hwhr2_and_we_2_re, denali->reg + TWHR2_AND_WE_2_RE); reg 223 drivers/mtd/nand/raw/denali.c denali->reg + TCWAW_AND_ADDR_2_DATA); reg 224 drivers/mtd/nand/raw/denali.c iowrite32(sel->re_2_we, denali->reg + RE_2_WE); reg 225 drivers/mtd/nand/raw/denali.c iowrite32(sel->acc_clks, denali->reg + ACC_CLKS); reg 226 drivers/mtd/nand/raw/denali.c iowrite32(sel->rdwr_en_lo_cnt, denali->reg + RDWR_EN_LO_CNT); reg 227 drivers/mtd/nand/raw/denali.c iowrite32(sel->rdwr_en_hi_cnt, denali->reg + RDWR_EN_HI_CNT); reg 228 drivers/mtd/nand/raw/denali.c iowrite32(sel->cs_setup_cnt, denali->reg + CS_SETUP_CNT); reg 229 drivers/mtd/nand/raw/denali.c iowrite32(sel->re_2_re, denali->reg + RE_2_RE); reg 448 drivers/mtd/nand/raw/denali.c ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank)); reg 491 drivers/mtd/nand/raw/denali.c err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS); reg 495 drivers/mtd/nand/raw/denali.c err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO); reg 684 drivers/mtd/nand/raw/denali.c iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE); reg 690 drivers/mtd/nand/raw/denali.c ioread32(denali->reg + DMA_ENABLE); reg 701 drivers/mtd/nand/raw/denali.c iowrite32(0, denali->reg + DMA_ENABLE); reg 804 drivers/mtd/nand/raw/denali.c tmp = ioread32(denali->reg + ACC_CLKS); reg 813 drivers/mtd/nand/raw/denali.c tmp = ioread32(denali->reg + RE_2_WE); reg 822 drivers/mtd/nand/raw/denali.c tmp = ioread32(denali->reg + RE_2_RE); reg 836 drivers/mtd/nand/raw/denali.c tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); reg 851 drivers/mtd/nand/raw/denali.c tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA); reg 861 drivers/mtd/nand/raw/denali.c tmp = ioread32(denali->reg + RDWR_EN_HI_CNT); reg 874 drivers/mtd/nand/raw/denali.c tmp = ioread32(denali->reg + RDWR_EN_LO_CNT); reg 885 drivers/mtd/nand/raw/denali.c tmp = ioread32(denali->reg + CS_SETUP_CNT); reg 950 drivers/mtd/nand/raw/denali.c denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED); reg 958 drivers/mtd/nand/raw/denali.c iowrite32(1, denali->reg + DEVICES_CONNECTED); reg 1251 drivers/mtd/nand/raw/denali.c u32 features = ioread32(denali->reg + FEATURES); reg 1266 drivers/mtd/nand/raw/denali.c denali->revision = swab16(ioread32(denali->reg + REVISION)); reg 1308 drivers/mtd/nand/raw/denali.c denali->oob_skip_bytes = ioread32(denali->reg + SPARE_AREA_SKIP_BYTES); reg 1312 drivers/mtd/nand/raw/denali.c denali->reg + SPARE_AREA_SKIP_BYTES); reg 1315 drivers/mtd/nand/raw/denali.c iowrite32(0, denali->reg + TRANSFER_SPARE_REG); reg 1316 drivers/mtd/nand/raw/denali.c iowrite32(GENMASK(denali->nbanks - 1, 0), denali->reg + RB_PIN_ENABLED); reg 1317 drivers/mtd/nand/raw/denali.c iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE); reg 1318 drivers/mtd/nand/raw/denali.c iowrite32(ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE); reg 1319 drivers/mtd/nand/raw/denali.c iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER); reg 367 drivers/mtd/nand/raw/denali.h void __iomem *reg; reg 176 drivers/mtd/nand/raw/denali_dt.c denali->reg = devm_ioremap_resource(dev, res); reg 177 drivers/mtd/nand/raw/denali_dt.c if (IS_ERR(denali->reg)) reg 178 drivers/mtd/nand/raw/denali_dt.c return PTR_ERR(denali->reg); reg 77 drivers/mtd/nand/raw/denali_pci.c denali->reg = ioremap_nocache(csr_base, csr_len); reg 78 drivers/mtd/nand/raw/denali_pci.c if (!denali->reg) { reg 123 drivers/mtd/nand/raw/denali_pci.c iounmap(denali->reg); reg 132 drivers/mtd/nand/raw/denali_pci.c iounmap(denali->reg); reg 1417 drivers/mtd/nand/raw/diskonchip.c int reg, len, numchips; reg 1452 drivers/mtd/nand/raw/diskonchip.c reg = DoC_2k_ECCStatus; reg 1455 drivers/mtd/nand/raw/diskonchip.c reg = DoC_ECCConf; reg 1481 drivers/mtd/nand/raw/diskonchip.c reg = DoC_Mplus_Toggle; reg 1497 drivers/mtd/nand/raw/diskonchip.c tmp = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT; reg 1498 drivers/mtd/nand/raw/diskonchip.c tmpb = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT; reg 1499 drivers/mtd/nand/raw/diskonchip.c tmpc = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT; reg 56 drivers/mtd/nand/raw/fsmc_nand.c #define FSMC_NOR_REG(base, bank, reg) ((base) + \ reg 58 drivers/mtd/nand/raw/fsmc_nand.c (reg)) reg 197 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c u32 reg; reg 202 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c reg = readl(r->gpmi_regs + i * 0x10); reg 203 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg); reg 209 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c reg = readl(r->bch_regs + i * 0x10); reg 210 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg); reg 144 drivers/mtd/nand/raw/hisi504_nand.c static inline unsigned int hinfc_read(struct hinfc_host *host, unsigned int reg) reg 146 drivers/mtd/nand/raw/hisi504_nand.c return readl(host->iobase + reg); reg 150 drivers/mtd/nand/raw/hisi504_nand.c unsigned int reg) reg 152 drivers/mtd/nand/raw/hisi504_nand.c writel(value, host->iobase + reg); reg 315 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c const __be32 *reg; reg 320 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c reg = of_get_property(np, "reg", NULL); reg 321 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c if (!reg) reg 324 drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c cs->bank = be32_to_cpu(*reg); reg 75 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c u32 reg, max_value; reg 105 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c reg = params->size << BCH_BHCNT_ENC_COUNT_SHIFT; reg 106 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c reg |= (params->size + params->bytes) << BCH_BHCNT_DEC_COUNT_SHIFT; reg 107 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c writel(reg, bch->base + BCH_BHCNT); reg 161 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c u32 reg; reg 170 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c ret = readl_relaxed_poll_timeout(bch->base + BCH_BHINT, reg, reg 171 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c reg & irq, 0, BCH_TIMEOUT_US); reg 176 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c *status = reg; reg 178 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c writel(reg, bch->base + BCH_BHINT); reg 218 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c u32 reg, errors, bit; reg 233 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c ret = jz4725b_bch_wait_complete(bch, BCH_BHINT_DECF, ®); reg 239 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c if (reg & (BCH_BHINT_ALL_F | BCH_BHINT_ALL_0)) { reg 245 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c if (reg & BCH_BHINT_UNCOR) { reg 251 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c errors = (reg & BCH_BHINT_ERRC_MASK) >> BCH_BHINT_ERRC_SHIFT; reg 256 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c bit = (reg & BCH_BHERR_INDEX1_MASK) >> BCH_BHERR_INDEX1_SHIFT; reg 258 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c reg = readl(bch->base + BCH_BHERR0 + (i * 4)); reg 259 drivers/mtd/nand/raw/ingenic/jz4725b_bch.c bit = (reg & BCH_BHERR_INDEX0_MASK) >> BCH_BHERR_INDEX0_SHIFT; reg 47 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c uint32_t reg; reg 53 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); reg 54 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg |= JZ_NAND_ECC_CTRL_RESET; reg 55 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg |= JZ_NAND_ECC_CTRL_ENABLE; reg 56 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg |= JZ_NAND_ECC_CTRL_RS; reg 58 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg |= JZ_NAND_ECC_CTRL_ENCODING; reg 60 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg &= ~JZ_NAND_ECC_CTRL_ENCODING; reg 62 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); reg 69 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c uint32_t reg, status; reg 82 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); reg 83 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg &= ~JZ_NAND_ECC_CTRL_ENABLE; reg 84 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); reg 122 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c uint32_t reg, status, error; reg 130 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); reg 131 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg |= JZ_NAND_ECC_CTRL_PAR_READY; reg 132 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); reg 141 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); reg 142 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg &= ~JZ_NAND_ECC_CTRL_ENABLE; reg 143 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); reg 166 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c u32 reg; reg 169 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); reg 170 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c reg &= ~JZ_NAND_ECC_CTRL_ENABLE; reg 171 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); reg 65 drivers/mtd/nand/raw/ingenic/jz4780_bch.c u32 reg; reg 71 drivers/mtd/nand/raw/ingenic/jz4780_bch.c reg = params->size << BCH_BHCNT_BLOCKSIZE_SHIFT; reg 72 drivers/mtd/nand/raw/ingenic/jz4780_bch.c reg |= params->bytes << BCH_BHCNT_PARITYSIZE_SHIFT; reg 73 drivers/mtd/nand/raw/ingenic/jz4780_bch.c writel(reg, bch->base + BCH_BHCNT); reg 76 drivers/mtd/nand/raw/ingenic/jz4780_bch.c reg = BCH_BHCR_BCHE | BCH_BHCR_INIT; reg 77 drivers/mtd/nand/raw/ingenic/jz4780_bch.c reg |= params->strength << BCH_BHCR_BSEL_SHIFT; reg 79 drivers/mtd/nand/raw/ingenic/jz4780_bch.c reg |= BCH_BHCR_ENCE; reg 80 drivers/mtd/nand/raw/ingenic/jz4780_bch.c writel(reg, bch->base + BCH_BHCR); reg 139 drivers/mtd/nand/raw/ingenic/jz4780_bch.c u32 reg; reg 148 drivers/mtd/nand/raw/ingenic/jz4780_bch.c ret = readl_poll_timeout(bch->base + BCH_BHINT, reg, reg 149 drivers/mtd/nand/raw/ingenic/jz4780_bch.c (reg & irq) == irq, 0, BCH_TIMEOUT_US); reg 154 drivers/mtd/nand/raw/ingenic/jz4780_bch.c *status = reg; reg 156 drivers/mtd/nand/raw/ingenic/jz4780_bch.c writel(reg, bch->base + BCH_BHINT); reg 187 drivers/mtd/nand/raw/ingenic/jz4780_bch.c u32 reg, mask, index; reg 196 drivers/mtd/nand/raw/ingenic/jz4780_bch.c if (!jz4780_bch_wait_complete(bch, BCH_BHINT_DECF, ®)) { reg 202 drivers/mtd/nand/raw/ingenic/jz4780_bch.c if (reg & BCH_BHINT_UNCOR) { reg 209 drivers/mtd/nand/raw/ingenic/jz4780_bch.c if (reg & BCH_BHINT_ERR) { reg 210 drivers/mtd/nand/raw/ingenic/jz4780_bch.c count = (reg & BCH_BHINT_ERRC_MASK) >> BCH_BHINT_ERRC_SHIFT; reg 211 drivers/mtd/nand/raw/ingenic/jz4780_bch.c ret = (reg & BCH_BHINT_TERRC_MASK) >> BCH_BHINT_TERRC_SHIFT; reg 214 drivers/mtd/nand/raw/ingenic/jz4780_bch.c reg = readl(bch->base + BCH_BHERR0 + (i * 4)); reg 215 drivers/mtd/nand/raw/ingenic/jz4780_bch.c mask = (reg & BCH_BHERR_MASK_MASK) >> reg 217 drivers/mtd/nand/raw/ingenic/jz4780_bch.c index = (reg & BCH_BHERR_INDEX_MASK) >> reg 501 drivers/mtd/nand/raw/marvell_nand.c u32 reg; reg 504 drivers/mtd/nand/raw/marvell_nand.c reg = readl_relaxed(nfc->regs + NDCR); reg 505 drivers/mtd/nand/raw/marvell_nand.c writel_relaxed(reg | int_mask, nfc->regs + NDCR); reg 510 drivers/mtd/nand/raw/marvell_nand.c u32 reg; reg 513 drivers/mtd/nand/raw/marvell_nand.c reg = readl_relaxed(nfc->regs + NDCR); reg 514 drivers/mtd/nand/raw/marvell_nand.c writel_relaxed(reg & ~int_mask, nfc->regs + NDCR); reg 519 drivers/mtd/nand/raw/marvell_nand.c u32 reg; reg 521 drivers/mtd/nand/raw/marvell_nand.c reg = readl_relaxed(nfc->regs + NDSR); reg 524 drivers/mtd/nand/raw/marvell_nand.c return reg & int_mask; reg 803 drivers/mtd/nand/raw/marvell_nand.c u32 reg; reg 805 drivers/mtd/nand/raw/marvell_nand.c reg = readl_relaxed(nfc->regs + NDCR); reg 806 drivers/mtd/nand/raw/marvell_nand.c writel_relaxed(reg | NDCR_DMA_EN, nfc->regs + NDCR); reg 811 drivers/mtd/nand/raw/marvell_nand.c u32 reg; reg 813 drivers/mtd/nand/raw/marvell_nand.c reg = readl_relaxed(nfc->regs + NDCR); reg 814 drivers/mtd/nand/raw/marvell_nand.c writel_relaxed(reg & ~NDCR_DMA_EN, nfc->regs + NDCR); reg 121 drivers/mtd/nand/raw/mpc5121_nfc.c static inline u16 nfc_read(struct mtd_info *mtd, uint reg) reg 126 drivers/mtd/nand/raw/mpc5121_nfc.c return in_be16(prv->regs + reg); reg 130 drivers/mtd/nand/raw/mpc5121_nfc.c static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val) reg 135 drivers/mtd/nand/raw/mpc5121_nfc.c out_be16(prv->regs + reg, val); reg 139 drivers/mtd/nand/raw/mpc5121_nfc.c static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits) reg 141 drivers/mtd/nand/raw/mpc5121_nfc.c nfc_write(mtd, reg, nfc_read(mtd, reg) | bits); reg 145 drivers/mtd/nand/raw/mpc5121_nfc.c static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits) reg 147 drivers/mtd/nand/raw/mpc5121_nfc.c nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits); reg 168 drivers/mtd/nand/raw/mtk_ecc.c u32 reg, i; reg 187 drivers/mtd/nand/raw/mtk_ecc.c reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); reg 188 drivers/mtd/nand/raw/mtk_ecc.c reg |= (enc_sz << ECC_MS_SHIFT); reg 189 drivers/mtd/nand/raw/mtk_ecc.c writel(reg, ecc->regs + ECC_ENCCNFG); reg 200 drivers/mtd/nand/raw/mtk_ecc.c reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); reg 201 drivers/mtd/nand/raw/mtk_ecc.c reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT; reg 202 drivers/mtd/nand/raw/mtk_ecc.c reg |= DEC_EMPTY_EN; reg 203 drivers/mtd/nand/raw/mtk_ecc.c writel(reg, ecc->regs + ECC_DECCNFG); reg 229 drivers/mtd/nand/raw/mtk_nand.c static inline void nfi_writel(struct mtk_nfc *nfc, u32 val, u32 reg) reg 231 drivers/mtd/nand/raw/mtk_nand.c writel(val, nfc->regs + reg); reg 234 drivers/mtd/nand/raw/mtk_nand.c static inline void nfi_writew(struct mtk_nfc *nfc, u16 val, u32 reg) reg 236 drivers/mtd/nand/raw/mtk_nand.c writew(val, nfc->regs + reg); reg 239 drivers/mtd/nand/raw/mtk_nand.c static inline void nfi_writeb(struct mtk_nfc *nfc, u8 val, u32 reg) reg 241 drivers/mtd/nand/raw/mtk_nand.c writeb(val, nfc->regs + reg); reg 244 drivers/mtd/nand/raw/mtk_nand.c static inline u32 nfi_readl(struct mtk_nfc *nfc, u32 reg) reg 246 drivers/mtd/nand/raw/mtk_nand.c return readl_relaxed(nfc->regs + reg); reg 249 drivers/mtd/nand/raw/mtk_nand.c static inline u16 nfi_readw(struct mtk_nfc *nfc, u32 reg) reg 251 drivers/mtd/nand/raw/mtk_nand.c return readw_relaxed(nfc->regs + reg); reg 254 drivers/mtd/nand/raw/mtk_nand.c static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg) reg 256 drivers/mtd/nand/raw/mtk_nand.c return readb_relaxed(nfc->regs + reg); reg 442 drivers/mtd/nand/raw/mtk_nand.c u32 reg; reg 445 drivers/mtd/nand/raw/mtk_nand.c reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK; reg 446 drivers/mtd/nand/raw/mtk_nand.c if (reg != NFI_FSM_CUSTDATA) { reg 447 drivers/mtd/nand/raw/mtk_nand.c reg = nfi_readw(nfc, NFI_CNFG); reg 448 drivers/mtd/nand/raw/mtk_nand.c reg |= CNFG_BYTE_RW | CNFG_READ_EN; reg 449 drivers/mtd/nand/raw/mtk_nand.c nfi_writew(nfc, reg, NFI_CNFG); reg 455 drivers/mtd/nand/raw/mtk_nand.c reg = (nfc->caps->max_sector << CON_SEC_SHIFT) | CON_BRD; reg 456 drivers/mtd/nand/raw/mtk_nand.c nfi_writel(nfc, reg, NFI_CON); reg 478 drivers/mtd/nand/raw/mtk_nand.c u32 reg; reg 480 drivers/mtd/nand/raw/mtk_nand.c reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK; reg 482 drivers/mtd/nand/raw/mtk_nand.c if (reg != NFI_FSM_CUSTDATA) { reg 483 drivers/mtd/nand/raw/mtk_nand.c reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW; reg 484 drivers/mtd/nand/raw/mtk_nand.c nfi_writew(nfc, reg, NFI_CNFG); reg 486 drivers/mtd/nand/raw/mtk_nand.c reg = nfc->caps->max_sector << CON_SEC_SHIFT | CON_BWR; reg 487 drivers/mtd/nand/raw/mtk_nand.c nfi_writel(nfc, reg, NFI_CON); reg 751 drivers/mtd/nand/raw/mtk_nand.c u32 reg; reg 761 drivers/mtd/nand/raw/mtk_nand.c reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AHB | CNFG_DMA_BURST_EN; reg 762 drivers/mtd/nand/raw/mtk_nand.c nfi_writew(nfc, reg, NFI_CNFG); reg 770 drivers/mtd/nand/raw/mtk_nand.c reg = nfi_readl(nfc, NFI_CON) | CON_BWR; reg 771 drivers/mtd/nand/raw/mtk_nand.c nfi_writel(nfc, reg, NFI_CON); reg 782 drivers/mtd/nand/raw/mtk_nand.c ret = readl_poll_timeout_atomic(nfc->regs + NFI_ADDRCNTR, reg, reg 783 drivers/mtd/nand/raw/mtk_nand.c ADDRCNTR_SEC(reg) >= chip->ecc.steps, reg 803 drivers/mtd/nand/raw/mtk_nand.c u32 reg; reg 810 drivers/mtd/nand/raw/mtk_nand.c reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AUTO_FMT_EN; reg 811 drivers/mtd/nand/raw/mtk_nand.c nfi_writew(nfc, reg | CNFG_HW_ECC_EN, NFI_CNFG); reg 818 drivers/mtd/nand/raw/mtk_nand.c reg = nfi_readw(nfc, NFI_CNFG); reg 819 drivers/mtd/nand/raw/mtk_nand.c reg &= ~(CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN); reg 820 drivers/mtd/nand/raw/mtk_nand.c nfi_writew(nfc, reg, NFI_CNFG); reg 916 drivers/mtd/nand/raw/mtk_nand.c u32 column, sectors, start, end, reg; reg 942 drivers/mtd/nand/raw/mtk_nand.c reg = nfi_readw(nfc, NFI_CNFG); reg 943 drivers/mtd/nand/raw/mtk_nand.c reg |= CNFG_READ_EN | CNFG_DMA_BURST_EN | CNFG_AHB; reg 945 drivers/mtd/nand/raw/mtk_nand.c reg |= CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN; reg 946 drivers/mtd/nand/raw/mtk_nand.c nfi_writew(nfc, reg, NFI_CNFG); reg 955 drivers/mtd/nand/raw/mtk_nand.c reg &= ~(CNFG_DMA_BURST_EN | CNFG_AHB | CNFG_READ_EN | reg 957 drivers/mtd/nand/raw/mtk_nand.c nfi_writew(nfc, reg, NFI_CNFG); reg 963 drivers/mtd/nand/raw/mtk_nand.c nfi_writew(nfc, reg, NFI_CNFG); reg 971 drivers/mtd/nand/raw/mtk_nand.c reg = nfi_readl(nfc, NFI_CON) | CON_BRD; reg 972 drivers/mtd/nand/raw/mtk_nand.c nfi_writel(nfc, reg, NFI_CON); reg 979 drivers/mtd/nand/raw/mtk_nand.c rc = readl_poll_timeout_atomic(nfc->regs + NFI_BYTELEN, reg, reg 980 drivers/mtd/nand/raw/mtk_nand.c ADDRCNTR_SEC(reg) >= sectors, 10, reg 260 drivers/mtd/nand/raw/nand_hynix.c int mode, int reg, bool inv, u8 *val) reg 263 drivers/mtd/nand/raw/nand_hynix.c int val_offs = (mode * nregs) + reg; reg 188 drivers/mtd/nand/raw/ndfc.c const __be32 *reg; reg 194 drivers/mtd/nand/raw/ndfc.c reg = of_get_property(ofdev->dev.of_node, "reg", &len); reg 195 drivers/mtd/nand/raw/ndfc.c if (reg == NULL || len != 12) { reg 200 drivers/mtd/nand/raw/ndfc.c cs = be32_to_cpu(reg[0]); reg 222 drivers/mtd/nand/raw/ndfc.c reg = of_get_property(ofdev->dev.of_node, "ccr", NULL); reg 223 drivers/mtd/nand/raw/ndfc.c if (reg) reg 224 drivers/mtd/nand/raw/ndfc.c ccr |= be32_to_cpup(reg); reg 229 drivers/mtd/nand/raw/ndfc.c reg = of_get_property(ofdev->dev.of_node, "bank-settings", NULL); reg 230 drivers/mtd/nand/raw/ndfc.c if (reg) { reg 232 drivers/mtd/nand/raw/ndfc.c out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg)); reg 167 drivers/mtd/nand/raw/omap2.c struct gpmc_nand_regs reg; reg 197 drivers/mtd/nand/raw/omap2.c if (readl(info->reg.gpmc_prefetch_control)) reg 201 drivers/mtd/nand/raw/omap2.c writel(u32_count, info->reg.gpmc_prefetch_config2); reg 209 drivers/mtd/nand/raw/omap2.c writel(val, info->reg.gpmc_prefetch_config1); reg 212 drivers/mtd/nand/raw/omap2.c writel(0x1, info->reg.gpmc_prefetch_control); reg 225 drivers/mtd/nand/raw/omap2.c config1 = readl(info->reg.gpmc_prefetch_config1); reg 230 drivers/mtd/nand/raw/omap2.c writel(0x0, info->reg.gpmc_prefetch_control); reg 233 drivers/mtd/nand/raw/omap2.c writel(0x0, info->reg.gpmc_prefetch_config1); reg 255 drivers/mtd/nand/raw/omap2.c writeb(cmd, info->reg.gpmc_nand_command); reg 258 drivers/mtd/nand/raw/omap2.c writeb(cmd, info->reg.gpmc_nand_address); reg 261 drivers/mtd/nand/raw/omap2.c writeb(cmd, info->reg.gpmc_nand_data); reg 370 drivers/mtd/nand/raw/omap2.c r_count = readl(info->reg.gpmc_prefetch_status); reg 417 drivers/mtd/nand/raw/omap2.c w_count = readl(info->reg.gpmc_prefetch_status); reg 429 drivers/mtd/nand/raw/omap2.c val = readl(info->reg.gpmc_prefetch_status); reg 506 drivers/mtd/nand/raw/omap2.c val = readl(info->reg.gpmc_prefetch_status); reg 574 drivers/mtd/nand/raw/omap2.c bytes = readl(info->reg.gpmc_prefetch_status); reg 701 drivers/mtd/nand/raw/omap2.c val = readl(info->reg.gpmc_prefetch_status); reg 926 drivers/mtd/nand/raw/omap2.c val = readl(info->reg.gpmc_ecc_config); reg 931 drivers/mtd/nand/raw/omap2.c val = readl(info->reg.gpmc_ecc1_result); reg 953 drivers/mtd/nand/raw/omap2.c writel(val, info->reg.gpmc_ecc_control); reg 958 drivers/mtd/nand/raw/omap2.c writel(val, info->reg.gpmc_ecc_size_config); reg 963 drivers/mtd/nand/raw/omap2.c writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); reg 966 drivers/mtd/nand/raw/omap2.c writel(ECCCLEAR, info->reg.gpmc_ecc_control); reg 976 drivers/mtd/nand/raw/omap2.c writel(val, info->reg.gpmc_ecc_config); reg 998 drivers/mtd/nand/raw/omap2.c writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command); reg 1000 drivers/mtd/nand/raw/omap2.c status = readb(info->reg.gpmc_nand_data); reg 1006 drivers/mtd/nand/raw/omap2.c status = readb(info->reg.gpmc_nand_data); reg 1103 drivers/mtd/nand/raw/omap2.c writel(ECC1, info->reg.gpmc_ecc_control); reg 1107 drivers/mtd/nand/raw/omap2.c writel(val, info->reg.gpmc_ecc_size_config); reg 1120 drivers/mtd/nand/raw/omap2.c writel(val, info->reg.gpmc_ecc_config); reg 1123 drivers/mtd/nand/raw/omap2.c writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); reg 1145 drivers/mtd/nand/raw/omap2.c struct gpmc_nand_regs *gpmc_regs = &info->reg; reg 1290 drivers/mtd/nand/raw/omap2.c nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; reg 2193 drivers/mtd/nand/raw/omap2.c info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs); reg 183 drivers/mtd/nand/raw/qcom_nandc.c #define nandc_set_read_loc(nandc, reg, offset, size, is_last) \ reg 184 drivers/mtd/nand/raw/qcom_nandc.c nandc_set_reg(nandc, NAND_READ_LOCATION_##reg, \ reg 193 drivers/mtd/nand/raw/qcom_nandc.c #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg)) reg 651 drivers/mtd/nand/raw/qcom_nandc.c __le32 *reg; reg 653 drivers/mtd/nand/raw/qcom_nandc.c reg = offset_to_nandc_reg(regs, offset); reg 655 drivers/mtd/nand/raw/qcom_nandc.c if (reg) reg 656 drivers/mtd/nand/raw/qcom_nandc.c *reg = cpu_to_le32(val); reg 36 drivers/mtd/nand/raw/r852.c uint8_t reg = readb(dev->mmio + address); reg 37 drivers/mtd/nand/raw/r852.c return reg; reg 51 drivers/mtd/nand/raw/r852.c uint32_t reg = le32_to_cpu(readl(dev->mmio + address)); reg 52 drivers/mtd/nand/raw/r852.c return reg; reg 233 drivers/mtd/nand/raw/r852.c uint32_t reg; reg 247 drivers/mtd/nand/raw/r852.c reg = buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24; reg 248 drivers/mtd/nand/raw/r852.c r852_write_reg_dword(dev, R852_DATALINE, reg); reg 267 drivers/mtd/nand/raw/r852.c uint32_t reg; reg 285 drivers/mtd/nand/raw/r852.c reg = r852_read_reg_dword(dev, R852_DATALINE); reg 286 drivers/mtd/nand/raw/r852.c *buf++ = reg & 0xFF; reg 287 drivers/mtd/nand/raw/r852.c *buf++ = (reg >> 8) & 0xFF; reg 288 drivers/mtd/nand/raw/r852.c *buf++ = (reg >> 16) & 0xFF; reg 289 drivers/mtd/nand/raw/r852.c *buf++ = (reg >> 24) & 0xFF; reg 560 drivers/mtd/nand/raw/r852.c uint8_t reg; reg 563 drivers/mtd/nand/raw/r852.c reg = r852_read_reg(dev, R852_CARD_STA); reg 564 drivers/mtd/nand/raw/r852.c dev->card_detected = !!(reg & R852_CARD_STA_PRESENT); reg 603 drivers/mtd/nand/raw/r852.c uint8_t reg; reg 615 drivers/mtd/nand/raw/r852.c reg = r852_read_reg(dev, R852_DMA_CAP); reg 616 drivers/mtd/nand/raw/r852.c dev->sm = (reg & (R852_DMA1 | R852_DMA2)) && (reg & R852_SMBIT); reg 707 drivers/mtd/nand/raw/r852.c uint8_t reg; reg 708 drivers/mtd/nand/raw/r852.c reg = r852_read_reg(dev, R852_CARD_IRQ_ENABLE); reg 709 drivers/mtd/nand/raw/r852.c r852_write_reg(dev, R852_CARD_IRQ_ENABLE, reg & ~R852_CARD_IRQ_MASK); reg 711 drivers/mtd/nand/raw/r852.c reg = r852_read_reg_dword(dev, R852_DMA_IRQ_ENABLE); reg 713 drivers/mtd/nand/raw/r852.c reg & ~R852_DMA_IRQ_MASK); reg 386 drivers/mtd/nand/raw/sh_flctl.c uint32_t reg; reg 404 drivers/mtd/nand/raw/sh_flctl.c reg = readl(FLINTDMACR(flctl)); reg 405 drivers/mtd/nand/raw/sh_flctl.c reg |= DREQ0EN; reg 406 drivers/mtd/nand/raw/sh_flctl.c writel(reg, FLINTDMACR(flctl)); reg 438 drivers/mtd/nand/raw/sh_flctl.c reg = readl(FLINTDMACR(flctl)); reg 439 drivers/mtd/nand/raw/sh_flctl.c reg &= ~DREQ0EN; reg 440 drivers/mtd/nand/raw/sh_flctl.c writel(reg, FLINTDMACR(flctl)); reg 1126 drivers/mtd/nand/raw/sh_flctl.c flctl->reg = devm_ioremap_resource(&pdev->dev, res); reg 1127 drivers/mtd/nand/raw/sh_flctl.c if (IS_ERR(flctl->reg)) reg 1128 drivers/mtd/nand/raw/sh_flctl.c return PTR_ERR(flctl->reg); reg 310 drivers/mtd/nand/raw/tegra_nand.c u32 reg; reg 320 drivers/mtd/nand/raw/tegra_nand.c reg = readl_relaxed(ctrl->regs + (i * 4)); reg 321 drivers/mtd/nand/raw/tegra_nand.c dev_err(ctrl->dev, "%s: 0x%08x\n", reg_name, reg); reg 355 drivers/mtd/nand/raw/tegra_nand.c u32 reg, cmd = 0; reg 411 drivers/mtd/nand/raw/tegra_nand.c memcpy(®, instr->ctx.data.buf.out + offset, size); reg 413 drivers/mtd/nand/raw/tegra_nand.c writel_relaxed(reg, ctrl->regs + RESP); reg 434 drivers/mtd/nand/raw/tegra_nand.c reg = readl_relaxed(ctrl->regs + RESP); reg 435 drivers/mtd/nand/raw/tegra_nand.c memcpy(instr_data_in->ctx.data.buf.in + offset, ®, size); reg 785 drivers/mtd/nand/raw/tegra_nand.c u32 val, reg = 0; reg 789 drivers/mtd/nand/raw/tegra_nand.c reg |= TIMING_TCR_TAR_TRR(OFFSET(val, 3)); reg 794 drivers/mtd/nand/raw/tegra_nand.c reg |= TIMING_TCS(OFFSET(val, 2)); reg 798 drivers/mtd/nand/raw/tegra_nand.c reg |= TIMING_TRP(OFFSET(val, 1)) | TIMING_TRP_RESP(OFFSET(val, 1)); reg 800 drivers/mtd/nand/raw/tegra_nand.c reg |= TIMING_TWB(OFFSET(DIV_ROUND_UP(timings->tWB_max, period), 1)); reg 801 drivers/mtd/nand/raw/tegra_nand.c reg |= TIMING_TWHR(OFFSET(DIV_ROUND_UP(timings->tWHR_min, period), 1)); reg 802 drivers/mtd/nand/raw/tegra_nand.c reg |= TIMING_TWH(OFFSET(DIV_ROUND_UP(timings->tWH_min, period), 1)); reg 803 drivers/mtd/nand/raw/tegra_nand.c reg |= TIMING_TWP(OFFSET(DIV_ROUND_UP(timings->tWP_min, period), 1)); reg 804 drivers/mtd/nand/raw/tegra_nand.c reg |= TIMING_TRH(OFFSET(DIV_ROUND_UP(timings->tREH_min, period), 1)); reg 806 drivers/mtd/nand/raw/tegra_nand.c writel_relaxed(reg, ctrl->regs + TIMING_1); reg 809 drivers/mtd/nand/raw/tegra_nand.c reg = TIMING_TADL(OFFSET(val, 3)); reg 811 drivers/mtd/nand/raw/tegra_nand.c writel_relaxed(reg, ctrl->regs + TIMING_2); reg 83 drivers/mtd/nand/raw/txx9ndfmc.c static void __iomem *ndregaddr(struct platform_device *dev, unsigned int reg) reg 88 drivers/mtd/nand/raw/txx9ndfmc.c return drvdata->base + (reg << plat->shift); reg 91 drivers/mtd/nand/raw/txx9ndfmc.c static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg) reg 93 drivers/mtd/nand/raw/txx9ndfmc.c return __raw_readl(ndregaddr(dev, reg)); reg 97 drivers/mtd/nand/raw/txx9ndfmc.c u32 val, unsigned int reg) reg 99 drivers/mtd/nand/raw/txx9ndfmc.c __raw_writel(val, ndregaddr(dev, reg)); reg 173 drivers/mtd/nand/raw/vf610_nfc.c static inline u32 vf610_nfc_read(struct vf610_nfc *nfc, uint reg) reg 175 drivers/mtd/nand/raw/vf610_nfc.c return readl(nfc->regs + reg); reg 178 drivers/mtd/nand/raw/vf610_nfc.c static inline void vf610_nfc_write(struct vf610_nfc *nfc, uint reg, u32 val) reg 180 drivers/mtd/nand/raw/vf610_nfc.c writel(val, nfc->regs + reg); reg 183 drivers/mtd/nand/raw/vf610_nfc.c static inline void vf610_nfc_set(struct vf610_nfc *nfc, uint reg, u32 bits) reg 185 drivers/mtd/nand/raw/vf610_nfc.c vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) | bits); reg 188 drivers/mtd/nand/raw/vf610_nfc.c static inline void vf610_nfc_clear(struct vf610_nfc *nfc, uint reg, u32 bits) reg 190 drivers/mtd/nand/raw/vf610_nfc.c vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) & ~bits); reg 193 drivers/mtd/nand/raw/vf610_nfc.c static inline void vf610_nfc_set_field(struct vf610_nfc *nfc, u32 reg, reg 196 drivers/mtd/nand/raw/vf610_nfc.c vf610_nfc_write(nfc, reg, reg 197 drivers/mtd/nand/raw/vf610_nfc.c (vf610_nfc_read(nfc, reg) & (~mask)) | val << shift); reg 22 drivers/mtd/nand/spi/core.c static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) reg 24 drivers/mtd/nand/spi/core.c struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg, reg 36 drivers/mtd/nand/spi/core.c static int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val) reg 38 drivers/mtd/nand/spi/core.c struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg, reg 76 drivers/mtd/parsers/ofpart.c const __be32 *reg; reg 83 drivers/mtd/parsers/ofpart.c reg = of_get_property(pp, "reg", &len); reg 84 drivers/mtd/parsers/ofpart.c if (!reg) { reg 105 drivers/mtd/parsers/ofpart.c parts[i].offset = of_read_number(reg, a_cells); reg 106 drivers/mtd/parsers/ofpart.c parts[i].size = of_read_number(reg + a_cells, s_cells); reg 264 drivers/mtd/spi-nor/aspeed-smc.c u32 reg; reg 266 drivers/mtd/spi-nor/aspeed-smc.c reg = readl(controller->regs + CONFIG_REG); reg 268 drivers/mtd/spi-nor/aspeed-smc.c if (reg & aspeed_smc_chip_write_bit(chip)) reg 272 drivers/mtd/spi-nor/aspeed-smc.c controller->regs + CONFIG_REG, reg); reg 273 drivers/mtd/spi-nor/aspeed-smc.c reg |= aspeed_smc_chip_write_bit(chip); reg 274 drivers/mtd/spi-nor/aspeed-smc.c writel(reg, controller->regs + CONFIG_REG); reg 441 drivers/mtd/spi-nor/aspeed-smc.c u32 reg; reg 444 drivers/mtd/spi-nor/aspeed-smc.c reg = readl(SEGMENT_ADDR_REG(controller, chip->cs)); reg 446 drivers/mtd/spi-nor/aspeed-smc.c if (SEGMENT_ADDR_START(reg) >= SEGMENT_ADDR_END(reg)) reg 449 drivers/mtd/spi-nor/aspeed-smc.c offset = SEGMENT_ADDR_START(reg) - res->start; reg 598 drivers/mtd/spi-nor/aspeed-smc.c u32 reg; reg 600 drivers/mtd/spi-nor/aspeed-smc.c reg = readl(controller->regs + CONFIG_REG); reg 602 drivers/mtd/spi-nor/aspeed-smc.c reg |= aspeed_smc_chip_write_bit(chip); reg 603 drivers/mtd/spi-nor/aspeed-smc.c writel(reg, controller->regs + CONFIG_REG); reg 609 drivers/mtd/spi-nor/aspeed-smc.c u32 reg; reg 613 drivers/mtd/spi-nor/aspeed-smc.c reg = readl(controller->regs + CONFIG_REG); reg 614 drivers/mtd/spi-nor/aspeed-smc.c reg &= ~(3 << (chip->cs * 2)); reg 615 drivers/mtd/spi-nor/aspeed-smc.c reg |= chip->type << (chip->cs * 2); reg 616 drivers/mtd/spi-nor/aspeed-smc.c writel(reg, controller->regs + CONFIG_REG); reg 627 drivers/mtd/spi-nor/aspeed-smc.c u32 reg; reg 629 drivers/mtd/spi-nor/aspeed-smc.c reg = readl(controller->regs + CE_CONTROL_REG); reg 630 drivers/mtd/spi-nor/aspeed-smc.c reg |= 1 << chip->cs; reg 631 drivers/mtd/spi-nor/aspeed-smc.c writel(reg, controller->regs + CE_CONTROL_REG); reg 650 drivers/mtd/spi-nor/aspeed-smc.c u32 reg, base_reg; reg 677 drivers/mtd/spi-nor/aspeed-smc.c reg = readl(chip->ctl); reg 678 drivers/mtd/spi-nor/aspeed-smc.c dev_dbg(controller->dev, "control register: %08x\n", reg); reg 680 drivers/mtd/spi-nor/aspeed-smc.c base_reg = reg & CONTROL_KEEP_MASK; reg 681 drivers/mtd/spi-nor/aspeed-smc.c if (base_reg != reg) { reg 693 drivers/mtd/spi-nor/aspeed-smc.c if ((reg & CONTROL_COMMAND_MODE_MASK) == reg 695 drivers/mtd/spi-nor/aspeed-smc.c chip->ctl_val[smc_read] = reg; reg 245 drivers/mtd/spi-nor/cadence-quadspi.c static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) reg 249 drivers/mtd/spi-nor/cadence-quadspi.c return readl_relaxed_poll_timeout(reg, val, reg 256 drivers/mtd/spi-nor/cadence-quadspi.c u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); reg 258 drivers/mtd/spi-nor/cadence-quadspi.c return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB); reg 263 drivers/mtd/spi-nor/cadence-quadspi.c u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); reg 265 drivers/mtd/spi-nor/cadence-quadspi.c reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; reg 266 drivers/mtd/spi-nor/cadence-quadspi.c return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; reg 333 drivers/mtd/spi-nor/cadence-quadspi.c static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) reg 339 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_CMDCTRL); reg 341 drivers/mtd/spi-nor/cadence-quadspi.c reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; reg 342 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_CMDCTRL); reg 365 drivers/mtd/spi-nor/cadence-quadspi.c unsigned int reg; reg 375 drivers/mtd/spi-nor/cadence-quadspi.c reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB; reg 380 drivers/mtd/spi-nor/cadence-quadspi.c reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); reg 383 drivers/mtd/spi-nor/cadence-quadspi.c reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) reg 385 drivers/mtd/spi-nor/cadence-quadspi.c status = cqspi_exec_flash_cmd(cqspi, reg); reg 389 drivers/mtd/spi-nor/cadence-quadspi.c reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); reg 393 drivers/mtd/spi-nor/cadence-quadspi.c memcpy(rxbuf, ®, read_len); reg 397 drivers/mtd/spi-nor/cadence-quadspi.c reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); reg 400 drivers/mtd/spi-nor/cadence-quadspi.c memcpy(rxbuf, ®, read_len); reg 412 drivers/mtd/spi-nor/cadence-quadspi.c unsigned int reg; reg 424 drivers/mtd/spi-nor/cadence-quadspi.c reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; reg 426 drivers/mtd/spi-nor/cadence-quadspi.c reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); reg 427 drivers/mtd/spi-nor/cadence-quadspi.c reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) reg 442 drivers/mtd/spi-nor/cadence-quadspi.c ret = cqspi_exec_flash_cmd(cqspi, reg); reg 452 drivers/mtd/spi-nor/cadence-quadspi.c unsigned int reg; reg 454 drivers/mtd/spi-nor/cadence-quadspi.c reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; reg 455 drivers/mtd/spi-nor/cadence-quadspi.c reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); reg 456 drivers/mtd/spi-nor/cadence-quadspi.c reg |= ((nor->addr_width - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) reg 461 drivers/mtd/spi-nor/cadence-quadspi.c return cqspi_exec_flash_cmd(cqspi, reg); reg 470 drivers/mtd/spi-nor/cadence-quadspi.c unsigned int reg; reg 472 drivers/mtd/spi-nor/cadence-quadspi.c reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; reg 473 drivers/mtd/spi-nor/cadence-quadspi.c reg |= cqspi_calc_rdreg(nor, nor->read_opcode); reg 481 drivers/mtd/spi-nor/cadence-quadspi.c reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB); reg 490 drivers/mtd/spi-nor/cadence-quadspi.c reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) reg 494 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_RD_INSTR); reg 497 drivers/mtd/spi-nor/cadence-quadspi.c reg = readl(reg_base + CQSPI_REG_SIZE); reg 498 drivers/mtd/spi-nor/cadence-quadspi.c reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; reg 499 drivers/mtd/spi-nor/cadence-quadspi.c reg |= (nor->addr_width - 1); reg 500 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_SIZE); reg 598 drivers/mtd/spi-nor/cadence-quadspi.c unsigned int reg; reg 604 drivers/mtd/spi-nor/cadence-quadspi.c reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; reg 605 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_WR_INSTR); reg 606 drivers/mtd/spi-nor/cadence-quadspi.c reg = cqspi_calc_rdreg(nor, nor->program_opcode); reg 607 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_RD_INSTR); reg 609 drivers/mtd/spi-nor/cadence-quadspi.c reg = readl(reg_base + CQSPI_REG_SIZE); reg 610 drivers/mtd/spi-nor/cadence-quadspi.c reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; reg 611 drivers/mtd/spi-nor/cadence-quadspi.c reg |= (nor->addr_width - 1); reg 612 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_SIZE); reg 715 drivers/mtd/spi-nor/cadence-quadspi.c unsigned int reg; reg 717 drivers/mtd/spi-nor/cadence-quadspi.c reg = readl(reg_base + CQSPI_REG_CONFIG); reg 719 drivers/mtd/spi-nor/cadence-quadspi.c reg |= CQSPI_REG_CONFIG_DECODE_MASK; reg 721 drivers/mtd/spi-nor/cadence-quadspi.c reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; reg 732 drivers/mtd/spi-nor/cadence-quadspi.c reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK reg 734 drivers/mtd/spi-nor/cadence-quadspi.c reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) reg 736 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_CONFIG); reg 744 drivers/mtd/spi-nor/cadence-quadspi.c unsigned int reg; reg 747 drivers/mtd/spi-nor/cadence-quadspi.c reg = readl(iobase + CQSPI_REG_SIZE); reg 748 drivers/mtd/spi-nor/cadence-quadspi.c reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB); reg 749 drivers/mtd/spi-nor/cadence-quadspi.c reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB); reg 750 drivers/mtd/spi-nor/cadence-quadspi.c reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; reg 751 drivers/mtd/spi-nor/cadence-quadspi.c reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB); reg 752 drivers/mtd/spi-nor/cadence-quadspi.c reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB); reg 753 drivers/mtd/spi-nor/cadence-quadspi.c reg |= (nor->addr_width - 1); reg 754 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, iobase + CQSPI_REG_SIZE); reg 783 drivers/mtd/spi-nor/cadence-quadspi.c unsigned int reg; reg 798 drivers/mtd/spi-nor/cadence-quadspi.c reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) reg 800 drivers/mtd/spi-nor/cadence-quadspi.c reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) reg 802 drivers/mtd/spi-nor/cadence-quadspi.c reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) reg 804 drivers/mtd/spi-nor/cadence-quadspi.c reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) reg 806 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, iobase + CQSPI_REG_DELAY); reg 813 drivers/mtd/spi-nor/cadence-quadspi.c u32 reg, div; reg 818 drivers/mtd/spi-nor/cadence-quadspi.c reg = readl(reg_base + CQSPI_REG_CONFIG); reg 819 drivers/mtd/spi-nor/cadence-quadspi.c reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); reg 820 drivers/mtd/spi-nor/cadence-quadspi.c reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; reg 821 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_CONFIG); reg 829 drivers/mtd/spi-nor/cadence-quadspi.c unsigned int reg; reg 831 drivers/mtd/spi-nor/cadence-quadspi.c reg = readl(reg_base + CQSPI_REG_READCAPTURE); reg 834 drivers/mtd/spi-nor/cadence-quadspi.c reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); reg 836 drivers/mtd/spi-nor/cadence-quadspi.c reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); reg 838 drivers/mtd/spi-nor/cadence-quadspi.c reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK reg 841 drivers/mtd/spi-nor/cadence-quadspi.c reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) reg 844 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_READCAPTURE); reg 850 drivers/mtd/spi-nor/cadence-quadspi.c unsigned int reg; reg 852 drivers/mtd/spi-nor/cadence-quadspi.c reg = readl(reg_base + CQSPI_REG_CONFIG); reg 855 drivers/mtd/spi-nor/cadence-quadspi.c reg |= CQSPI_REG_CONFIG_ENABLE_MASK; reg 857 drivers/mtd/spi-nor/cadence-quadspi.c reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; reg 859 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, reg_base + CQSPI_REG_CONFIG); reg 1172 drivers/mtd/spi-nor/cadence-quadspi.c u32 reg; reg 1197 drivers/mtd/spi-nor/cadence-quadspi.c reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); reg 1198 drivers/mtd/spi-nor/cadence-quadspi.c reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; reg 1199 drivers/mtd/spi-nor/cadence-quadspi.c writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); reg 105 drivers/mtd/spi-nor/hisi-sfc.c u32 reg; reg 107 drivers/mtd/spi-nor/hisi-sfc.c return readl_poll_timeout(host->regbase + FMC_INT, reg, reg 108 drivers/mtd/spi-nor/hisi-sfc.c (reg & FMC_INT_OP_DONE), 0, FMC_WAIT_TIMEOUT); reg 139 drivers/mtd/spi-nor/hisi-sfc.c u32 reg; reg 141 drivers/mtd/spi-nor/hisi-sfc.c reg = TIMING_CFG_TCSH(CS_HOLD_TIME) reg 144 drivers/mtd/spi-nor/hisi-sfc.c writel(reg, host->regbase + FMC_SPI_TIMING_CFG); reg 184 drivers/mtd/spi-nor/hisi-sfc.c u32 reg; reg 186 drivers/mtd/spi-nor/hisi-sfc.c reg = FMC_CMD_CMD1(opcode); reg 187 drivers/mtd/spi-nor/hisi-sfc.c writel(reg, host->regbase + FMC_CMD); reg 189 drivers/mtd/spi-nor/hisi-sfc.c reg = FMC_DATA_NUM_CNT(len); reg 190 drivers/mtd/spi-nor/hisi-sfc.c writel(reg, host->regbase + FMC_DATA_NUM); reg 192 drivers/mtd/spi-nor/hisi-sfc.c reg = OP_CFG_FM_CS(priv->chipselect); reg 193 drivers/mtd/spi-nor/hisi-sfc.c writel(reg, host->regbase + FMC_OP_CFG); reg 196 drivers/mtd/spi-nor/hisi-sfc.c reg = FMC_OP_CMD1_EN | FMC_OP_REG_OP_START | optype; reg 197 drivers/mtd/spi-nor/hisi-sfc.c writel(reg, host->regbase + FMC_OP); reg 235 drivers/mtd/spi-nor/hisi-sfc.c u32 reg; reg 237 drivers/mtd/spi-nor/hisi-sfc.c reg = readl(host->regbase + FMC_CFG); reg 238 drivers/mtd/spi-nor/hisi-sfc.c reg &= ~(FMC_CFG_OP_MODE_MASK | SPI_NOR_ADDR_MODE_MASK); reg 239 drivers/mtd/spi-nor/hisi-sfc.c reg |= FMC_CFG_OP_MODE_NORMAL; reg 240 drivers/mtd/spi-nor/hisi-sfc.c reg |= (nor->addr_width == 4) ? SPI_NOR_ADDR_MODE_4BYTES reg 242 drivers/mtd/spi-nor/hisi-sfc.c writel(reg, host->regbase + FMC_CFG); reg 248 drivers/mtd/spi-nor/hisi-sfc.c reg = OP_CFG_FM_CS(priv->chipselect); reg 253 drivers/mtd/spi-nor/hisi-sfc.c reg |= OP_CFG_MEM_IF_TYPE(if_type); reg 255 drivers/mtd/spi-nor/hisi-sfc.c reg |= OP_CFG_DUMMY_NUM(nor->read_dummy >> 3); reg 256 drivers/mtd/spi-nor/hisi-sfc.c writel(reg, host->regbase + FMC_OP_CFG); reg 259 drivers/mtd/spi-nor/hisi-sfc.c reg = OP_CTRL_RW_OP(op_type) | OP_CTRL_DMA_OP_READY; reg 260 drivers/mtd/spi-nor/hisi-sfc.c reg |= (op_type == FMC_OP_READ) reg 263 drivers/mtd/spi-nor/hisi-sfc.c writel(reg, host->regbase + FMC_OP_DMA); reg 145 drivers/mtd/spi-nor/mtk-quadspi.c int reg; reg 149 drivers/mtd/spi-nor/mtk-quadspi.c return readl_poll_timeout(mtk_nor->base + MTK_NOR_CMD_REG, reg, reg 150 drivers/mtd/spi-nor/mtk-quadspi.c !(reg & val), 100, 10000); reg 205 drivers/mtd/spi-nor/mtk-quadspi.c u8 reg; reg 212 drivers/mtd/spi-nor/mtk-quadspi.c return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg, reg 213 drivers/mtd/spi-nor/mtk-quadspi.c 0x01 == (reg & 0x01), 100, 10000); reg 218 drivers/mtd/spi-nor/mtk-quadspi.c u8 reg; reg 221 drivers/mtd/spi-nor/mtk-quadspi.c return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg, reg 222 drivers/mtd/spi-nor/mtk-quadspi.c MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100, reg 16 drivers/mux/adgs1408.c #define ADGS1408_REG_READ(reg) ((reg) | 0x80) reg 39 drivers/mux/adgs1408.c u8 reg; reg 42 drivers/mux/adgs1408.c reg = ADGS1408_DISABLE; reg 44 drivers/mux/adgs1408.c reg = ADGS1408_MUX(state); reg 46 drivers/mux/adgs1408.c return adgs1408_spi_reg_write(spi, ADGS1408_SW_DATA, reg); reg 78 drivers/mux/mmio.c u32 reg, mask; reg 82 drivers/mux/mmio.c 2 * i, ®); reg 92 drivers/mux/mmio.c field.reg = reg; reg 278 drivers/net/can/at91_can.c static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg) reg 280 drivers/net/can/at91_can.c return readl_relaxed(priv->reg_base + reg); reg 283 drivers/net/can/at91_can.c static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg, reg 286 drivers/net/can/at91_can.c writel_relaxed(value, priv->reg_base + reg); reg 49 drivers/net/can/c_can/c_can.c #define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) reg 258 drivers/net/can/c_can/c_can.c int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface); reg 260 drivers/net/can/c_can/c_can.c priv->write_reg32(priv, reg, (cmd << 16) | obj); reg 263 drivers/net/can/c_can/c_can.c if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY)) reg 189 drivers/net/can/c_can/c_can.h unsigned int reg; /* register index within syscon */ reg 204 drivers/net/can/c_can/c_can.h u16 (*read_reg) (const struct c_can_priv *priv, enum reg index); reg 205 drivers/net/can/c_can/c_can.h void (*write_reg) (const struct c_can_priv *priv, enum reg index, u16 val); reg 206 drivers/net/can/c_can/c_can.h u32 (*read_reg32) (const struct c_can_priv *priv, enum reg index); reg 207 drivers/net/can/c_can/c_can.h void (*write_reg32) (const struct c_can_priv *priv, enum reg index, u32 val); reg 51 drivers/net/can/c_can/c_can_pci.c enum reg index) reg 57 drivers/net/can/c_can/c_can_pci.c enum reg index, u16 val) reg 63 drivers/net/can/c_can/c_can_pci.c enum reg index) reg 69 drivers/net/can/c_can/c_can_pci.c enum reg index, u16 val) reg 75 drivers/net/can/c_can/c_can_pci.c enum reg index) reg 81 drivers/net/can/c_can/c_can_pci.c enum reg index, u16 val) reg 86 drivers/net/can/c_can/c_can_pci.c static u32 c_can_pci_read_reg32(const struct c_can_priv *priv, enum reg index) reg 96 drivers/net/can/c_can/c_can_pci.c static void c_can_pci_write_reg32(const struct c_can_priv *priv, enum reg index, reg 51 drivers/net/can/c_can/c_can_platform.c enum reg index) reg 57 drivers/net/can/c_can/c_can_platform.c enum reg index, u16 val) reg 63 drivers/net/can/c_can/c_can_platform.c enum reg index) reg 69 drivers/net/can/c_can/c_can_platform.c enum reg index, u16 val) reg 87 drivers/net/can/c_can/c_can_platform.c regmap_read(raminit->syscon, raminit->reg, &ctrl); reg 104 drivers/net/can/c_can/c_can_platform.c regmap_read(raminit->syscon, raminit->reg, &ctrl); reg 114 drivers/net/can/c_can/c_can_platform.c regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl); reg 126 drivers/net/can/c_can/c_can_platform.c regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl); reg 132 drivers/net/can/c_can/c_can_platform.c regmap_update_bits(raminit->syscon, raminit->reg, reg 142 drivers/net/can/c_can/c_can_platform.c static u32 c_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index) reg 152 drivers/net/can/c_can/c_can_platform.c static void c_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index, reg 159 drivers/net/can/c_can/c_can_platform.c static u32 d_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index) reg 164 drivers/net/can/c_can/c_can_platform.c static void d_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index, reg 346 drivers/net/can/c_can/c_can_platform.c &raminit->reg)) { reg 172 drivers/net/can/cc770/cc770.h u8 (*read_reg)(const struct cc770_priv *priv, int reg); reg 173 drivers/net/can/cc770/cc770.h void (*write_reg)(const struct cc770_priv *priv, int reg, u8 val); reg 112 drivers/net/can/cc770/cc770_isa.c static u8 cc770_isa_mem_read_reg(const struct cc770_priv *priv, int reg) reg 114 drivers/net/can/cc770/cc770_isa.c return readb(priv->reg_base + reg); reg 118 drivers/net/can/cc770/cc770_isa.c int reg, u8 val) reg 120 drivers/net/can/cc770/cc770_isa.c writeb(val, priv->reg_base + reg); reg 123 drivers/net/can/cc770/cc770_isa.c static u8 cc770_isa_port_read_reg(const struct cc770_priv *priv, int reg) reg 125 drivers/net/can/cc770/cc770_isa.c return inb((unsigned long)priv->reg_base + reg); reg 129 drivers/net/can/cc770/cc770_isa.c int reg, u8 val) reg 131 drivers/net/can/cc770/cc770_isa.c outb(val, (unsigned long)priv->reg_base + reg); reg 135 drivers/net/can/cc770/cc770_isa.c int reg) reg 142 drivers/net/can/cc770/cc770_isa.c outb(reg, base); reg 150 drivers/net/can/cc770/cc770_isa.c int reg, u8 val) reg 156 drivers/net/can/cc770/cc770_isa.c outb(reg, base); reg 59 drivers/net/can/cc770/cc770_platform.c static u8 cc770_platform_read_reg(const struct cc770_priv *priv, int reg) reg 61 drivers/net/can/cc770/cc770_platform.c return ioread8(priv->reg_base + reg); reg 64 drivers/net/can/cc770/cc770_platform.c static void cc770_platform_write_reg(const struct cc770_priv *priv, int reg, reg 67 drivers/net/can/cc770/cc770_platform.c iowrite8(val, priv->reg_base + reg); reg 524 drivers/net/can/flexcan.c u32 reg; reg 526 drivers/net/can/flexcan.c reg = priv->read(®s->mcr); reg 527 drivers/net/can/flexcan.c reg &= ~FLEXCAN_MCR_MDIS; reg 528 drivers/net/can/flexcan.c priv->write(reg, ®s->mcr); reg 536 drivers/net/can/flexcan.c u32 reg; reg 538 drivers/net/can/flexcan.c reg = priv->read(®s->mcr); reg 539 drivers/net/can/flexcan.c reg |= FLEXCAN_MCR_MDIS; reg 540 drivers/net/can/flexcan.c priv->write(reg, ®s->mcr); reg 549 drivers/net/can/flexcan.c u32 reg; reg 551 drivers/net/can/flexcan.c reg = priv->read(®s->mcr); reg 552 drivers/net/can/flexcan.c reg |= FLEXCAN_MCR_HALT; reg 553 drivers/net/can/flexcan.c priv->write(reg, ®s->mcr); reg 568 drivers/net/can/flexcan.c u32 reg; reg 570 drivers/net/can/flexcan.c reg = priv->read(®s->mcr); reg 571 drivers/net/can/flexcan.c reg &= ~FLEXCAN_MCR_HALT; reg 572 drivers/net/can/flexcan.c priv->write(reg, ®s->mcr); reg 603 drivers/net/can/flexcan.c u32 reg = priv->read(®s->ecr); reg 605 drivers/net/can/flexcan.c bec->txerr = (reg >> 0) & 0xff; reg 606 drivers/net/can/flexcan.c bec->rxerr = (reg >> 8) & 0xff; reg 1001 drivers/net/can/flexcan.c u32 reg; reg 1003 drivers/net/can/flexcan.c reg = priv->read(®s->ctrl); reg 1004 drivers/net/can/flexcan.c reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | reg 1013 drivers/net/can/flexcan.c reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | reg 1020 drivers/net/can/flexcan.c reg |= FLEXCAN_CTRL_LPB; reg 1022 drivers/net/can/flexcan.c reg |= FLEXCAN_CTRL_LOM; reg 1024 drivers/net/can/flexcan.c reg |= FLEXCAN_CTRL_SMP; reg 1026 drivers/net/can/flexcan.c netdev_dbg(dev, "writing ctrl=0x%08x\n", reg); reg 1027 drivers/net/can/flexcan.c priv->write(reg, ®s->ctrl); reg 1388 drivers/net/can/flexcan.c u32 reg, err; reg 1399 drivers/net/can/flexcan.c reg = priv->read(®s->ctrl); reg 1401 drivers/net/can/flexcan.c reg |= FLEXCAN_CTRL_CLK_SRC; reg 1403 drivers/net/can/flexcan.c reg &= ~FLEXCAN_CTRL_CLK_SRC; reg 1404 drivers/net/can/flexcan.c priv->write(reg, ®s->ctrl); reg 1411 drivers/net/can/flexcan.c reg = priv->read(®s->mcr); reg 1412 drivers/net/can/flexcan.c reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | reg 1414 drivers/net/can/flexcan.c priv->write(reg, ®s->mcr); reg 1421 drivers/net/can/flexcan.c reg = priv->read(®s->mcr); reg 1422 drivers/net/can/flexcan.c if (!(reg & FLEXCAN_MCR_FEN)) { reg 318 drivers/net/can/grcan.c static inline u32 grcan_read_reg(u32 __iomem *reg) reg 320 drivers/net/can/grcan.c return ioread32be(reg); reg 323 drivers/net/can/grcan.c static inline void grcan_write_reg(u32 __iomem *reg, u32 val) reg 325 drivers/net/can/grcan.c iowrite32be(val, reg); reg 328 drivers/net/can/grcan.c static inline u32 grcan_read_reg(u32 __iomem *reg) reg 330 drivers/net/can/grcan.c return ioread32(reg); reg 333 drivers/net/can/grcan.c static inline void grcan_write_reg(u32 __iomem *reg, u32 val) reg 335 drivers/net/can/grcan.c iowrite32(val, reg); reg 339 drivers/net/can/grcan.c static inline void grcan_clear_bits(u32 __iomem *reg, u32 mask) reg 341 drivers/net/can/grcan.c grcan_write_reg(reg, grcan_read_reg(reg) & ~mask); reg 344 drivers/net/can/grcan.c static inline void grcan_set_bits(u32 __iomem *reg, u32 mask) reg 346 drivers/net/can/grcan.c grcan_write_reg(reg, grcan_read_reg(reg) | mask); reg 349 drivers/net/can/grcan.c static inline u32 grcan_read_bits(u32 __iomem *reg, u32 mask) reg 351 drivers/net/can/grcan.c return grcan_read_reg(reg) & mask; reg 354 drivers/net/can/grcan.c static inline void grcan_write_bits(u32 __iomem *reg, u32 value, u32 mask) reg 356 drivers/net/can/grcan.c u32 old = grcan_read_reg(reg); reg 358 drivers/net/can/grcan.c grcan_write_reg(reg, (old & ~mask) | (value & mask)); reg 323 drivers/net/can/m_can/m_can.c static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg) reg 325 drivers/net/can/m_can/m_can.c return cdev->ops->read_reg(cdev, reg); reg 328 drivers/net/can/m_can/m_can.c static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg, reg 331 drivers/net/can/m_can/m_can.c cdev->ops->write_reg(cdev, reg, val); reg 64 drivers/net/can/m_can/m_can.h u32 (*read_reg)(struct m_can_classdev *cdev, int reg); reg 65 drivers/net/can/m_can/m_can.h int (*write_reg)(struct m_can_classdev *cdev, int reg, int val); reg 17 drivers/net/can/m_can/m_can_platform.c static u32 iomap_read_reg(struct m_can_classdev *cdev, int reg) reg 21 drivers/net/can/m_can/m_can_platform.c return readl(priv->base + reg); reg 31 drivers/net/can/m_can/m_can_platform.c static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val) reg 35 drivers/net/can/m_can/m_can_platform.c writel(val, priv->base + reg); reg 189 drivers/net/can/m_can/tcan4x5x.c static int regmap_spi_gather_write(void *context, const void *reg, reg 202 drivers/net/can/m_can/tcan4x5x.c addr = TCAN4X5X_WRITE_CMD | (*((u16 *)reg) << 8) | val_len >> 2; reg 213 drivers/net/can/m_can/tcan4x5x.c u16 *reg = (u16 *)(data); reg 216 drivers/net/can/m_can/tcan4x5x.c return regmap_spi_gather_write(context, reg, 4, val, count - 4); reg 220 drivers/net/can/m_can/tcan4x5x.c const void *reg, size_t reg_len, reg 233 drivers/net/can/m_can/tcan4x5x.c const void *reg, size_t reg_size, reg 239 drivers/net/can/m_can/tcan4x5x.c u32 addr = TCAN4X5X_READ_CMD | (*((u16 *)reg) << 8) | val_size >> 2; reg 255 drivers/net/can/m_can/tcan4x5x.c static u32 tcan4x5x_read_reg(struct m_can_classdev *cdev, int reg) reg 260 drivers/net/can/m_can/tcan4x5x.c regmap_read(priv->regmap, priv->reg_offset + reg, &val); reg 275 drivers/net/can/m_can/tcan4x5x.c static int tcan4x5x_write_reg(struct m_can_classdev *cdev, int reg, int val) reg 279 drivers/net/can/m_can/tcan4x5x.c return regmap_write(priv->regmap, priv->reg_offset + reg, val); reg 290 drivers/net/can/m_can/tcan4x5x.c static int tcan4x5x_power_enable(struct regulator *reg, int enable) reg 292 drivers/net/can/m_can/tcan4x5x.c if (IS_ERR_OR_NULL(reg)) reg 296 drivers/net/can/m_can/tcan4x5x.c return regulator_enable(reg); reg 298 drivers/net/can/m_can/tcan4x5x.c return regulator_disable(reg); reg 302 drivers/net/can/m_can/tcan4x5x.c int reg, int val) reg 306 drivers/net/can/m_can/tcan4x5x.c return regmap_write(priv->regmap, reg, val); reg 632 drivers/net/can/pch_can.c u32 reg; reg 649 drivers/net/can/pch_can.c reg = ioread32(&priv->regs->ifregs[0].mcont); reg 651 drivers/net/can/pch_can.c if (reg & PCH_IF_MCONT_EOB) reg 655 drivers/net/can/pch_can.c if (reg & PCH_IF_MCONT_MSGLOST) { reg 661 drivers/net/can/pch_can.c } else if (!(reg & PCH_IF_MCONT_NEWDAT)) { reg 215 drivers/net/can/peak_canfd/peak_pciefd_main.c static inline u32 pciefd_sys_readreg(const struct pciefd_board *priv, u16 reg) reg 217 drivers/net/can/peak_canfd/peak_pciefd_main.c return readl(priv->reg_base + reg); reg 222 drivers/net/can/peak_canfd/peak_pciefd_main.c u32 val, u16 reg) reg 224 drivers/net/can/peak_canfd/peak_pciefd_main.c writel(val, priv->reg_base + reg); reg 228 drivers/net/can/peak_canfd/peak_pciefd_main.c static inline u32 pciefd_can_readreg(const struct pciefd_can *priv, u16 reg) reg 230 drivers/net/can/peak_canfd/peak_pciefd_main.c return readl(priv->reg_base + reg); reg 235 drivers/net/can/peak_canfd/peak_pciefd_main.c u32 val, u16 reg) reg 237 drivers/net/can/peak_canfd/peak_pciefd_main.c writel(val, priv->reg_base + reg); reg 558 drivers/net/can/rcar/rcar_canfd.c static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg) reg 560 drivers/net/can/rcar/rcar_canfd.c u32 data = readl(reg); reg 564 drivers/net/can/rcar/rcar_canfd.c writel(data, reg); reg 577 drivers/net/can/rcar/rcar_canfd.c static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val) reg 579 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_update(val, val, base + (reg)); reg 582 drivers/net/can/rcar/rcar_canfd.c static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val) reg 584 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_update(val, 0, base + (reg)); reg 587 drivers/net/can/rcar/rcar_canfd.c static void rcar_canfd_update_bit(void __iomem *base, u32 reg, reg 590 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_update(mask, val, base + (reg)); reg 158 drivers/net/can/sja1000/sja1000.h u8 (*read_reg) (const struct sja1000_priv *priv, int reg); reg 159 drivers/net/can/sja1000/sja1000.h void (*write_reg) (const struct sja1000_priv *priv, int reg, u8 val); reg 69 drivers/net/can/sja1000/sja1000_isa.c static u8 sja1000_isa_mem_read_reg(const struct sja1000_priv *priv, int reg) reg 71 drivers/net/can/sja1000/sja1000_isa.c return readb(priv->reg_base + reg); reg 75 drivers/net/can/sja1000/sja1000_isa.c int reg, u8 val) reg 77 drivers/net/can/sja1000/sja1000_isa.c writeb(val, priv->reg_base + reg); reg 80 drivers/net/can/sja1000/sja1000_isa.c static u8 sja1000_isa_port_read_reg(const struct sja1000_priv *priv, int reg) reg 82 drivers/net/can/sja1000/sja1000_isa.c return inb((unsigned long)priv->reg_base + reg); reg 86 drivers/net/can/sja1000/sja1000_isa.c int reg, u8 val) reg 88 drivers/net/can/sja1000/sja1000_isa.c outb(val, (unsigned long)priv->reg_base + reg); reg 92 drivers/net/can/sja1000/sja1000_isa.c int reg) reg 98 drivers/net/can/sja1000/sja1000_isa.c outb(reg, base); reg 106 drivers/net/can/sja1000/sja1000_isa.c int reg, u8 val) reg 111 drivers/net/can/sja1000/sja1000_isa.c outb(reg, base); reg 42 drivers/net/can/sja1000/sja1000_platform.c static u8 sp_read_reg8(const struct sja1000_priv *priv, int reg) reg 44 drivers/net/can/sja1000/sja1000_platform.c return ioread8(priv->reg_base + reg); reg 47 drivers/net/can/sja1000/sja1000_platform.c static void sp_write_reg8(const struct sja1000_priv *priv, int reg, u8 val) reg 49 drivers/net/can/sja1000/sja1000_platform.c iowrite8(val, priv->reg_base + reg); reg 52 drivers/net/can/sja1000/sja1000_platform.c static u8 sp_read_reg16(const struct sja1000_priv *priv, int reg) reg 54 drivers/net/can/sja1000/sja1000_platform.c return ioread8(priv->reg_base + reg * 2); reg 57 drivers/net/can/sja1000/sja1000_platform.c static void sp_write_reg16(const struct sja1000_priv *priv, int reg, u8 val) reg 59 drivers/net/can/sja1000/sja1000_platform.c iowrite8(val, priv->reg_base + reg * 2); reg 62 drivers/net/can/sja1000/sja1000_platform.c static u8 sp_read_reg32(const struct sja1000_priv *priv, int reg) reg 64 drivers/net/can/sja1000/sja1000_platform.c return ioread8(priv->reg_base + reg * 4); reg 67 drivers/net/can/sja1000/sja1000_platform.c static void sp_write_reg32(const struct sja1000_priv *priv, int reg, u8 val) reg 69 drivers/net/can/sja1000/sja1000_platform.c iowrite8(val, priv->reg_base + reg * 4); reg 72 drivers/net/can/sja1000/sja1000_platform.c static u8 sp_technologic_read_reg16(const struct sja1000_priv *priv, int reg) reg 79 drivers/net/can/sja1000/sja1000_platform.c iowrite16(reg, priv->reg_base + 0); reg 87 drivers/net/can/sja1000/sja1000_platform.c int reg, u8 val) reg 93 drivers/net/can/sja1000/sja1000_platform.c iowrite16(reg, priv->reg_base + 0); reg 67 drivers/net/can/sja1000/tscan1.c static u8 tscan1_read(const struct sja1000_priv *priv, int reg) reg 69 drivers/net/can/sja1000/tscan1.c return inb((unsigned long)priv->reg_base + reg); reg 73 drivers/net/can/sja1000/tscan1.c static void tscan1_write(const struct sja1000_priv *priv, int reg, u8 val) reg 75 drivers/net/can/sja1000/tscan1.c outb(val, (unsigned long)priv->reg_base + reg); reg 243 drivers/net/can/spi/hi311x.c static void hi3110_write(struct spi_device *spi, u8 reg, u8 val) reg 247 drivers/net/can/spi/hi311x.c priv->spi_tx_buf[0] = reg; reg 424 drivers/net/can/spi/hi311x.c u8 reg = 0; reg 433 drivers/net/can/spi/hi311x.c reg = HI3110_CTRL0_LOOPBACK_MODE; reg 435 drivers/net/can/spi/hi311x.c reg = HI3110_CTRL0_MONITOR_MODE; reg 437 drivers/net/can/spi/hi311x.c reg = HI3110_CTRL0_NORMAL_MODE; reg 439 drivers/net/can/spi/hi311x.c hi3110_write(spi, HI3110_WRITE_CTRL0, reg); reg 443 drivers/net/can/spi/hi311x.c reg = hi3110_read(spi, HI3110_READ_CTRL0); reg 444 drivers/net/can/spi/hi311x.c if ((reg & HI3110_CTRL0_MODE_MASK) != reg) reg 484 drivers/net/can/spi/hi311x.c u8 reg; reg 497 drivers/net/can/spi/hi311x.c reg = hi3110_read(spi, HI3110_READ_CTRL0); reg 498 drivers/net/can/spi/hi311x.c if ((reg & HI3110_CTRL0_MODE_MASK) != HI3110_CTRL0_INIT_MODE) reg 528 drivers/net/can/spi/hi311x.c static int hi3110_power_enable(struct regulator *reg, int enable) reg 530 drivers/net/can/spi/hi311x.c if (IS_ERR_OR_NULL(reg)) reg 534 drivers/net/can/spi/hi311x.c return regulator_enable(reg); reg 536 drivers/net/can/spi/hi311x.c return regulator_disable(reg); reg 286 drivers/net/can/spi/mcp251x.c static u8 mcp251x_read_reg(struct spi_device *spi, u8 reg) reg 292 drivers/net/can/spi/mcp251x.c priv->spi_tx_buf[1] = reg; reg 300 drivers/net/can/spi/mcp251x.c static void mcp251x_read_2regs(struct spi_device *spi, u8 reg, u8 *v1, u8 *v2) reg 305 drivers/net/can/spi/mcp251x.c priv->spi_tx_buf[1] = reg; reg 313 drivers/net/can/spi/mcp251x.c static void mcp251x_write_reg(struct spi_device *spi, u8 reg, u8 val) reg 318 drivers/net/can/spi/mcp251x.c priv->spi_tx_buf[1] = reg; reg 324 drivers/net/can/spi/mcp251x.c static void mcp251x_write_bits(struct spi_device *spi, u8 reg, reg 330 drivers/net/can/spi/mcp251x.c priv->spi_tx_buf[1] = reg; reg 623 drivers/net/can/spi/mcp251x.c static int mcp251x_power_enable(struct regulator *reg, int enable) reg 625 drivers/net/can/spi/mcp251x.c if (IS_ERR_OR_NULL(reg)) reg 629 drivers/net/can/spi/mcp251x.c return regulator_enable(reg); reg 631 drivers/net/can/spi/mcp251x.c return regulator_disable(reg); reg 228 drivers/net/can/ti_hecc.c u32 reg, u32 val) reg 230 drivers/net/can/ti_hecc.c __raw_writel(val, priv->mbx + mbxno * 0x10 + reg); reg 233 drivers/net/can/ti_hecc.c static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg) reg 235 drivers/net/can/ti_hecc.c return __raw_readl(priv->mbx + mbxno * 0x10 + reg); reg 238 drivers/net/can/ti_hecc.c static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val) reg 240 drivers/net/can/ti_hecc.c __raw_writel(val, priv->base + reg); reg 243 drivers/net/can/ti_hecc.c static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg) reg 245 drivers/net/can/ti_hecc.c return __raw_readl(priv->base + reg); reg 248 drivers/net/can/ti_hecc.c static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg, reg 251 drivers/net/can/ti_hecc.c hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask); reg 254 drivers/net/can/ti_hecc.c static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg, reg 257 drivers/net/can/ti_hecc.c hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask); reg 260 drivers/net/can/ti_hecc.c static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask) reg 262 drivers/net/can/ti_hecc.c return (hecc_read(priv, reg) & bit_mask) ? 1 : 0; reg 204 drivers/net/can/xilinx_can.c u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg); reg 205 drivers/net/can/xilinx_can.c void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg, reg 288 drivers/net/can/xilinx_can.c static void xcan_write_reg_le(const struct xcan_priv *priv, enum xcan_reg reg, reg 291 drivers/net/can/xilinx_can.c iowrite32(val, priv->reg_base + reg); reg 302 drivers/net/can/xilinx_can.c static u32 xcan_read_reg_le(const struct xcan_priv *priv, enum xcan_reg reg) reg 304 drivers/net/can/xilinx_can.c return ioread32(priv->reg_base + reg); reg 315 drivers/net/can/xilinx_can.c static void xcan_write_reg_be(const struct xcan_priv *priv, enum xcan_reg reg, reg 318 drivers/net/can/xilinx_can.c iowrite32be(val, priv->reg_base + reg); reg 329 drivers/net/can/xilinx_can.c static u32 xcan_read_reg_be(const struct xcan_priv *priv, enum xcan_reg reg) reg 331 drivers/net/can/xilinx_can.c return ioread32be(priv->reg_base + reg); reg 562 drivers/net/dsa/b53/b53_common.c u8 reg; reg 565 drivers/net/dsa/b53/b53_common.c b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); reg 566 drivers/net/dsa/b53/b53_common.c reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; reg 567 drivers/net/dsa/b53/b53_common.c b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); reg 580 drivers/net/dsa/b53/b53_common.c u16 reg; reg 613 drivers/net/dsa/b53/b53_common.c b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®); reg 615 drivers/net/dsa/b53/b53_common.c reg &= ~BIT(port); reg 617 drivers/net/dsa/b53/b53_common.c reg |= BIT(port); reg 618 drivers/net/dsa/b53/b53_common.c b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg); reg 623 drivers/net/dsa/b53/b53_common.c b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®); reg 625 drivers/net/dsa/b53/b53_common.c reg &= ~BIT(port); reg 627 drivers/net/dsa/b53/b53_common.c reg |= BIT(port); reg 628 drivers/net/dsa/b53/b53_common.c b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg); reg 717 drivers/net/dsa/b53/b53_common.c u8 mgmt, reg; reg 733 drivers/net/dsa/b53/b53_common.c b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); reg 734 drivers/net/dsa/b53/b53_common.c reg |= SW_RST | EN_SW_RST | EN_CH_RST; reg 735 drivers/net/dsa/b53/b53_common.c b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg); reg 738 drivers/net/dsa/b53/b53_common.c b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®); reg 739 drivers/net/dsa/b53/b53_common.c if (!(reg & SW_RST)) reg 769 drivers/net/dsa/b53/b53_common.c static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg) reg 776 drivers/net/dsa/b53/b53_common.c ret = priv->ops->phy_read16(priv, addr, reg, &value); reg 779 drivers/net/dsa/b53/b53_common.c reg * 2, &value); reg 784 drivers/net/dsa/b53/b53_common.c static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) reg 789 drivers/net/dsa/b53/b53_common.c return priv->ops->phy_write16(priv, addr, reg, val); reg 791 drivers/net/dsa/b53/b53_common.c return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val); reg 996 drivers/net/dsa/b53/b53_common.c u8 reg, val, off; reg 1007 drivers/net/dsa/b53/b53_common.c b53_read8(dev, B53_CTRL_PAGE, off, ®); reg 1008 drivers/net/dsa/b53/b53_common.c reg |= val; reg 1010 drivers/net/dsa/b53/b53_common.c reg |= PORT_OVERRIDE_LINK; reg 1012 drivers/net/dsa/b53/b53_common.c reg &= ~PORT_OVERRIDE_LINK; reg 1013 drivers/net/dsa/b53/b53_common.c b53_write8(dev, B53_CTRL_PAGE, off, reg); reg 1019 drivers/net/dsa/b53/b53_common.c u8 reg, val, off; reg 1030 drivers/net/dsa/b53/b53_common.c b53_read8(dev, B53_CTRL_PAGE, off, ®); reg 1031 drivers/net/dsa/b53/b53_common.c reg |= val; reg 1033 drivers/net/dsa/b53/b53_common.c reg |= PORT_OVERRIDE_FULL_DUPLEX; reg 1035 drivers/net/dsa/b53/b53_common.c reg &= ~PORT_OVERRIDE_FULL_DUPLEX; reg 1039 drivers/net/dsa/b53/b53_common.c reg |= PORT_OVERRIDE_SPEED_2000M; reg 1042 drivers/net/dsa/b53/b53_common.c reg |= PORT_OVERRIDE_SPEED_1000M; reg 1045 drivers/net/dsa/b53/b53_common.c reg |= PORT_OVERRIDE_SPEED_100M; reg 1048 drivers/net/dsa/b53/b53_common.c reg |= PORT_OVERRIDE_SPEED_10M; reg 1056 drivers/net/dsa/b53/b53_common.c reg |= PORT_OVERRIDE_RX_FLOW; reg 1058 drivers/net/dsa/b53/b53_common.c reg |= PORT_OVERRIDE_TX_FLOW; reg 1060 drivers/net/dsa/b53/b53_common.c b53_write8(dev, B53_CTRL_PAGE, off, reg); reg 1068 drivers/net/dsa/b53/b53_common.c u8 rgmii_ctrl = 0, reg = 0, off; reg 1128 drivers/net/dsa/b53/b53_common.c ®); reg 1131 drivers/net/dsa/b53/b53_common.c if (!(reg & PORT_OVERRIDE_RV_MII_25)) { reg 1133 drivers/net/dsa/b53/b53_common.c reg | PORT_OVERRIDE_RV_MII_25); reg 1135 drivers/net/dsa/b53/b53_common.c ®); reg 1137 drivers/net/dsa/b53/b53_common.c if (!(reg & PORT_OVERRIDE_RV_MII_25)) { reg 1416 drivers/net/dsa/b53/b53_common.c u8 reg; reg 1419 drivers/net/dsa/b53/b53_common.c b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); reg 1420 drivers/net/dsa/b53/b53_common.c if (!(reg & ARLTBL_START_DONE)) reg 1426 drivers/net/dsa/b53/b53_common.c dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); reg 1433 drivers/net/dsa/b53/b53_common.c u8 reg; reg 1438 drivers/net/dsa/b53/b53_common.c b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®); reg 1439 drivers/net/dsa/b53/b53_common.c reg |= ARLTBL_START_DONE; reg 1441 drivers/net/dsa/b53/b53_common.c reg |= ARLTBL_RW; reg 1443 drivers/net/dsa/b53/b53_common.c reg &= ~ARLTBL_RW; reg 1445 drivers/net/dsa/b53/b53_common.c reg &= ~ARLTBL_IVL_SVL_SELECT; reg 1447 drivers/net/dsa/b53/b53_common.c reg |= ARLTBL_IVL_SVL_SELECT; reg 1448 drivers/net/dsa/b53/b53_common.c b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg); reg 1584 drivers/net/dsa/b53/b53_common.c u8 reg; reg 1587 drivers/net/dsa/b53/b53_common.c b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®); reg 1588 drivers/net/dsa/b53/b53_common.c if (!(reg & ARL_SRCH_STDN)) reg 1591 drivers/net/dsa/b53/b53_common.c if (reg & ARL_SRCH_VLID) reg 1632 drivers/net/dsa/b53/b53_common.c u8 reg; reg 1635 drivers/net/dsa/b53/b53_common.c reg = ARL_SRCH_STDN; reg 1636 drivers/net/dsa/b53/b53_common.c b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg); reg 1668 drivers/net/dsa/b53/b53_common.c u16 pvlan, reg; reg 1675 drivers/net/dsa/b53/b53_common.c b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); reg 1676 drivers/net/dsa/b53/b53_common.c reg &= ~BIT(port); reg 1677 drivers/net/dsa/b53/b53_common.c if ((reg & BIT(cpu_port)) == BIT(cpu_port)) reg 1678 drivers/net/dsa/b53/b53_common.c reg &= ~BIT(cpu_port); reg 1679 drivers/net/dsa/b53/b53_common.c b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); reg 1691 drivers/net/dsa/b53/b53_common.c b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); reg 1692 drivers/net/dsa/b53/b53_common.c reg |= BIT(port); reg 1693 drivers/net/dsa/b53/b53_common.c b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); reg 1694 drivers/net/dsa/b53/b53_common.c dev->ports[i].vlan_ctl_mask = reg; reg 1715 drivers/net/dsa/b53/b53_common.c u16 pvlan, reg, pvid; reg 1724 drivers/net/dsa/b53/b53_common.c b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®); reg 1725 drivers/net/dsa/b53/b53_common.c reg &= ~BIT(port); reg 1726 drivers/net/dsa/b53/b53_common.c b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg); reg 1727 drivers/net/dsa/b53/b53_common.c dev->ports[port].vlan_ctl_mask = reg; reg 1741 drivers/net/dsa/b53/b53_common.c b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®); reg 1742 drivers/net/dsa/b53/b53_common.c reg |= BIT(port); reg 1743 drivers/net/dsa/b53/b53_common.c if (!(reg & BIT(cpu_port))) reg 1744 drivers/net/dsa/b53/b53_common.c reg |= BIT(cpu_port); reg 1745 drivers/net/dsa/b53/b53_common.c b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg); reg 1759 drivers/net/dsa/b53/b53_common.c u8 reg; reg 1782 drivers/net/dsa/b53/b53_common.c b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®); reg 1783 drivers/net/dsa/b53/b53_common.c reg &= ~PORT_CTRL_STP_STATE_MASK; reg 1784 drivers/net/dsa/b53/b53_common.c reg |= hw_state; reg 1785 drivers/net/dsa/b53/b53_common.c b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg); reg 1882 drivers/net/dsa/b53/b53_common.c u16 reg, loc; reg 1889 drivers/net/dsa/b53/b53_common.c b53_read16(dev, B53_MGMT_PAGE, loc, ®); reg 1890 drivers/net/dsa/b53/b53_common.c reg |= BIT(port); reg 1891 drivers/net/dsa/b53/b53_common.c b53_write16(dev, B53_MGMT_PAGE, loc, reg); reg 1893 drivers/net/dsa/b53/b53_common.c b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); reg 1894 drivers/net/dsa/b53/b53_common.c reg &= ~CAP_PORT_MASK; reg 1895 drivers/net/dsa/b53/b53_common.c reg |= mirror->to_local_port; reg 1896 drivers/net/dsa/b53/b53_common.c reg |= MIRROR_EN; reg 1897 drivers/net/dsa/b53/b53_common.c b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); reg 1908 drivers/net/dsa/b53/b53_common.c u16 reg, loc; reg 1916 drivers/net/dsa/b53/b53_common.c b53_read16(dev, B53_MGMT_PAGE, loc, ®); reg 1917 drivers/net/dsa/b53/b53_common.c reg &= ~BIT(port); reg 1918 drivers/net/dsa/b53/b53_common.c if (!(reg & MIRROR_MASK)) reg 1920 drivers/net/dsa/b53/b53_common.c b53_write16(dev, B53_MGMT_PAGE, loc, reg); reg 1926 drivers/net/dsa/b53/b53_common.c b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®); reg 1928 drivers/net/dsa/b53/b53_common.c b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®); reg 1929 drivers/net/dsa/b53/b53_common.c if (!(reg & MIRROR_MASK)) reg 1932 drivers/net/dsa/b53/b53_common.c b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®); reg 1935 drivers/net/dsa/b53/b53_common.c reg &= ~MIRROR_EN; reg 1936 drivers/net/dsa/b53/b53_common.c reg &= ~mirror->to_local_port; reg 1938 drivers/net/dsa/b53/b53_common.c b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg); reg 1945 drivers/net/dsa/b53/b53_common.c u16 reg; reg 1947 drivers/net/dsa/b53/b53_common.c b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®); reg 1949 drivers/net/dsa/b53/b53_common.c reg |= BIT(port); reg 1951 drivers/net/dsa/b53/b53_common.c reg &= ~BIT(port); reg 1952 drivers/net/dsa/b53/b53_common.c b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg); reg 1977 drivers/net/dsa/b53/b53_common.c u16 reg; reg 1982 drivers/net/dsa/b53/b53_common.c b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®); reg 1984 drivers/net/dsa/b53/b53_common.c e->eee_active = !!(reg & BIT(port)); reg 41 drivers/net/dsa/b53/b53_mdio.c static int b53_mdio_op(struct b53_device *dev, u8 page, u8 reg, u16 op) reg 59 drivers/net/dsa/b53/b53_mdio.c v = (reg << 8) | op; reg 79 drivers/net/dsa/b53/b53_mdio.c static int b53_mdio_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val) reg 84 drivers/net/dsa/b53/b53_mdio.c ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ); reg 94 drivers/net/dsa/b53/b53_mdio.c static int b53_mdio_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val) reg 99 drivers/net/dsa/b53/b53_mdio.c ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ); reg 108 drivers/net/dsa/b53/b53_mdio.c static int b53_mdio_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val) reg 113 drivers/net/dsa/b53/b53_mdio.c ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ); reg 124 drivers/net/dsa/b53/b53_mdio.c static int b53_mdio_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val) reg 131 drivers/net/dsa/b53/b53_mdio.c ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ); reg 146 drivers/net/dsa/b53/b53_mdio.c static int b53_mdio_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val) reg 153 drivers/net/dsa/b53/b53_mdio.c ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ); reg 168 drivers/net/dsa/b53/b53_mdio.c static int b53_mdio_write8(struct b53_device *dev, u8 page, u8 reg, u8 value) reg 178 drivers/net/dsa/b53/b53_mdio.c return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE); reg 181 drivers/net/dsa/b53/b53_mdio.c static int b53_mdio_write16(struct b53_device *dev, u8 page, u8 reg, reg 192 drivers/net/dsa/b53/b53_mdio.c return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE); reg 195 drivers/net/dsa/b53/b53_mdio.c static int b53_mdio_write32(struct b53_device *dev, u8 page, u8 reg, reg 211 drivers/net/dsa/b53/b53_mdio.c return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE); reg 214 drivers/net/dsa/b53/b53_mdio.c static int b53_mdio_write48(struct b53_device *dev, u8 page, u8 reg, reg 230 drivers/net/dsa/b53/b53_mdio.c return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE); reg 233 drivers/net/dsa/b53/b53_mdio.c static int b53_mdio_write64(struct b53_device *dev, u8 page, u8 reg, reg 249 drivers/net/dsa/b53/b53_mdio.c return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE); reg 252 drivers/net/dsa/b53/b53_mdio.c static int b53_mdio_phy_read16(struct b53_device *dev, int addr, int reg, reg 257 drivers/net/dsa/b53/b53_mdio.c *value = mdiobus_read_nested(bus, addr, reg); reg 262 drivers/net/dsa/b53/b53_mdio.c static int b53_mdio_phy_write16(struct b53_device *dev, int addr, int reg, reg 267 drivers/net/dsa/b53/b53_mdio.c return mdiobus_write_nested(bus, addr, reg, value); reg 31 drivers/net/dsa/b53/b53_mmap.c static int b53_mmap_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val) reg 36 drivers/net/dsa/b53/b53_mmap.c *val = readb(regs + (page << 8) + reg); reg 41 drivers/net/dsa/b53/b53_mmap.c static int b53_mmap_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val) reg 46 drivers/net/dsa/b53/b53_mmap.c if (WARN_ON(reg % 2)) reg 50 drivers/net/dsa/b53/b53_mmap.c *val = ioread16be(regs + (page << 8) + reg); reg 52 drivers/net/dsa/b53/b53_mmap.c *val = readw(regs + (page << 8) + reg); reg 57 drivers/net/dsa/b53/b53_mmap.c static int b53_mmap_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val) reg 62 drivers/net/dsa/b53/b53_mmap.c if (WARN_ON(reg % 4)) reg 66 drivers/net/dsa/b53/b53_mmap.c *val = ioread32be(regs + (page << 8) + reg); reg 68 drivers/net/dsa/b53/b53_mmap.c *val = readl(regs + (page << 8) + reg); reg 73 drivers/net/dsa/b53/b53_mmap.c static int b53_mmap_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val) reg 78 drivers/net/dsa/b53/b53_mmap.c if (WARN_ON(reg % 2)) reg 81 drivers/net/dsa/b53/b53_mmap.c if (reg % 4) { reg 86 drivers/net/dsa/b53/b53_mmap.c lo = ioread16be(regs + (page << 8) + reg); reg 87 drivers/net/dsa/b53/b53_mmap.c hi = ioread32be(regs + (page << 8) + reg + 2); reg 89 drivers/net/dsa/b53/b53_mmap.c lo = readw(regs + (page << 8) + reg); reg 90 drivers/net/dsa/b53/b53_mmap.c hi = readl(regs + (page << 8) + reg + 2); reg 99 drivers/net/dsa/b53/b53_mmap.c lo = ioread32be(regs + (page << 8) + reg); reg 100 drivers/net/dsa/b53/b53_mmap.c hi = ioread16be(regs + (page << 8) + reg + 4); reg 102 drivers/net/dsa/b53/b53_mmap.c lo = readl(regs + (page << 8) + reg); reg 103 drivers/net/dsa/b53/b53_mmap.c hi = readw(regs + (page << 8) + reg + 4); reg 112 drivers/net/dsa/b53/b53_mmap.c static int b53_mmap_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val) reg 118 drivers/net/dsa/b53/b53_mmap.c if (WARN_ON(reg % 4)) reg 122 drivers/net/dsa/b53/b53_mmap.c lo = ioread32be(regs + (page << 8) + reg); reg 123 drivers/net/dsa/b53/b53_mmap.c hi = ioread32be(regs + (page << 8) + reg + 4); reg 125 drivers/net/dsa/b53/b53_mmap.c lo = readl(regs + (page << 8) + reg); reg 126 drivers/net/dsa/b53/b53_mmap.c hi = readl(regs + (page << 8) + reg + 4); reg 134 drivers/net/dsa/b53/b53_mmap.c static int b53_mmap_write8(struct b53_device *dev, u8 page, u8 reg, u8 value) reg 139 drivers/net/dsa/b53/b53_mmap.c writeb(value, regs + (page << 8) + reg); reg 144 drivers/net/dsa/b53/b53_mmap.c static int b53_mmap_write16(struct b53_device *dev, u8 page, u8 reg, reg 150 drivers/net/dsa/b53/b53_mmap.c if (WARN_ON(reg % 2)) reg 154 drivers/net/dsa/b53/b53_mmap.c iowrite16be(value, regs + (page << 8) + reg); reg 156 drivers/net/dsa/b53/b53_mmap.c writew(value, regs + (page << 8) + reg); reg 161 drivers/net/dsa/b53/b53_mmap.c static int b53_mmap_write32(struct b53_device *dev, u8 page, u8 reg, reg 167 drivers/net/dsa/b53/b53_mmap.c if (WARN_ON(reg % 4)) reg 171 drivers/net/dsa/b53/b53_mmap.c iowrite32be(value, regs + (page << 8) + reg); reg 173 drivers/net/dsa/b53/b53_mmap.c writel(value, regs + (page << 8) + reg); reg 178 drivers/net/dsa/b53/b53_mmap.c static int b53_mmap_write48(struct b53_device *dev, u8 page, u8 reg, reg 181 drivers/net/dsa/b53/b53_mmap.c if (WARN_ON(reg % 2)) reg 184 drivers/net/dsa/b53/b53_mmap.c if (reg % 4) { reg 188 drivers/net/dsa/b53/b53_mmap.c b53_mmap_write16(dev, page, reg, lo); reg 189 drivers/net/dsa/b53/b53_mmap.c b53_mmap_write32(dev, page, reg + 2, hi); reg 194 drivers/net/dsa/b53/b53_mmap.c b53_mmap_write32(dev, page, reg, lo); reg 195 drivers/net/dsa/b53/b53_mmap.c b53_mmap_write16(dev, page, reg + 4, hi); reg 201 drivers/net/dsa/b53/b53_mmap.c static int b53_mmap_write64(struct b53_device *dev, u8 page, u8 reg, reg 209 drivers/net/dsa/b53/b53_mmap.c if (WARN_ON(reg % 4)) reg 212 drivers/net/dsa/b53/b53_mmap.c b53_mmap_write32(dev, page, reg, lo); reg 213 drivers/net/dsa/b53/b53_mmap.c b53_mmap_write32(dev, page, reg + 4, hi); reg 35 drivers/net/dsa/b53/b53_priv.h int (*read8)(struct b53_device *dev, u8 page, u8 reg, u8 *value); reg 36 drivers/net/dsa/b53/b53_priv.h int (*read16)(struct b53_device *dev, u8 page, u8 reg, u16 *value); reg 37 drivers/net/dsa/b53/b53_priv.h int (*read32)(struct b53_device *dev, u8 page, u8 reg, u32 *value); reg 38 drivers/net/dsa/b53/b53_priv.h int (*read48)(struct b53_device *dev, u8 page, u8 reg, u64 *value); reg 39 drivers/net/dsa/b53/b53_priv.h int (*read64)(struct b53_device *dev, u8 page, u8 reg, u64 *value); reg 40 drivers/net/dsa/b53/b53_priv.h int (*write8)(struct b53_device *dev, u8 page, u8 reg, u8 value); reg 41 drivers/net/dsa/b53/b53_priv.h int (*write16)(struct b53_device *dev, u8 page, u8 reg, u16 value); reg 42 drivers/net/dsa/b53/b53_priv.h int (*write32)(struct b53_device *dev, u8 page, u8 reg, u32 value); reg 43 drivers/net/dsa/b53/b53_priv.h int (*write48)(struct b53_device *dev, u8 page, u8 reg, u64 value); reg 44 drivers/net/dsa/b53/b53_priv.h int (*write64)(struct b53_device *dev, u8 page, u8 reg, u64 value); reg 45 drivers/net/dsa/b53/b53_priv.h int (*phy_read16)(struct b53_device *dev, int addr, int reg, u16 *value); reg 46 drivers/net/dsa/b53/b53_priv.h int (*phy_write16)(struct b53_device *dev, int addr, int reg, u16 value); reg 229 drivers/net/dsa/b53/b53_priv.h u8 reg, val_type val) \ reg 234 drivers/net/dsa/b53/b53_priv.h ret = dev->ops->type_op_size(dev, page, reg, val); \ reg 180 drivers/net/dsa/b53/b53_regs.h #define SPEED_PORT_FE(reg, port) (((reg) >> (port)) & 1) reg 181 drivers/net/dsa/b53/b53_regs.h #define SPEED_PORT_GE(reg, port) (((reg) >> 2 * (port)) & 3) reg 67 drivers/net/dsa/b53/b53_serdes.c u16 reg; reg 72 drivers/net/dsa/b53/b53_serdes.c reg = b53_serdes_read(dev, lane, B53_SERDES_DIGITAL_CONTROL(1), reg 75 drivers/net/dsa/b53/b53_serdes.c reg |= FIBER_MODE_1000X; reg 77 drivers/net/dsa/b53/b53_serdes.c reg &= ~FIBER_MODE_1000X; reg 79 drivers/net/dsa/b53/b53_serdes.c SERDES_DIGITAL_BLK, reg); reg 86 drivers/net/dsa/b53/b53_serdes.c u16 reg; reg 91 drivers/net/dsa/b53/b53_serdes.c reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR), reg 93 drivers/net/dsa/b53/b53_serdes.c reg |= BMCR_ANRESTART; reg 95 drivers/net/dsa/b53/b53_serdes.c SERDES_MII_BLK, reg); reg 145 drivers/net/dsa/b53/b53_serdes.c u16 reg; reg 150 drivers/net/dsa/b53/b53_serdes.c reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR), reg 153 drivers/net/dsa/b53/b53_serdes.c reg &= ~BMCR_PDOWN; reg 155 drivers/net/dsa/b53/b53_serdes.c reg |= BMCR_PDOWN; reg 157 drivers/net/dsa/b53/b53_serdes.c SERDES_MII_BLK, reg); reg 42 drivers/net/dsa/b53/b53_spi.c static inline int b53_spi_read_reg(struct spi_device *spi, u8 reg, u8 *val, reg 48 drivers/net/dsa/b53/b53_spi.c txbuf[1] = reg; reg 97 drivers/net/dsa/b53/b53_spi.c static int b53_spi_prepare_reg_read(struct spi_device *spi, u8 reg) reg 103 drivers/net/dsa/b53/b53_spi.c ret = b53_spi_read_reg(spi, reg, &rxbuf, 1); reg 124 drivers/net/dsa/b53/b53_spi.c static int b53_spi_read(struct b53_device *dev, u8 page, u8 reg, u8 *data, reg 134 drivers/net/dsa/b53/b53_spi.c ret = b53_spi_prepare_reg_read(spi, reg); reg 141 drivers/net/dsa/b53/b53_spi.c static int b53_spi_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val) reg 143 drivers/net/dsa/b53/b53_spi.c return b53_spi_read(dev, page, reg, val, 1); reg 146 drivers/net/dsa/b53/b53_spi.c static int b53_spi_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val) reg 148 drivers/net/dsa/b53/b53_spi.c int ret = b53_spi_read(dev, page, reg, (u8 *)val, 2); reg 156 drivers/net/dsa/b53/b53_spi.c static int b53_spi_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val) reg 158 drivers/net/dsa/b53/b53_spi.c int ret = b53_spi_read(dev, page, reg, (u8 *)val, 4); reg 166 drivers/net/dsa/b53/b53_spi.c static int b53_spi_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val) reg 171 drivers/net/dsa/b53/b53_spi.c ret = b53_spi_read(dev, page, reg, (u8 *)val, 6); reg 178 drivers/net/dsa/b53/b53_spi.c static int b53_spi_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val) reg 180 drivers/net/dsa/b53/b53_spi.c int ret = b53_spi_read(dev, page, reg, (u8 *)val, 8); reg 188 drivers/net/dsa/b53/b53_spi.c static int b53_spi_write8(struct b53_device *dev, u8 page, u8 reg, u8 value) reg 199 drivers/net/dsa/b53/b53_spi.c txbuf[1] = reg; reg 205 drivers/net/dsa/b53/b53_spi.c static int b53_spi_write16(struct b53_device *dev, u8 page, u8 reg, u16 value) reg 216 drivers/net/dsa/b53/b53_spi.c txbuf[1] = reg; reg 222 drivers/net/dsa/b53/b53_spi.c static int b53_spi_write32(struct b53_device *dev, u8 page, u8 reg, u32 value) reg 233 drivers/net/dsa/b53/b53_spi.c txbuf[1] = reg; reg 239 drivers/net/dsa/b53/b53_spi.c static int b53_spi_write48(struct b53_device *dev, u8 page, u8 reg, u64 value) reg 250 drivers/net/dsa/b53/b53_spi.c txbuf[1] = reg; reg 256 drivers/net/dsa/b53/b53_spi.c static int b53_spi_write64(struct b53_device *dev, u8 page, u8 reg, u64 value) reg 267 drivers/net/dsa/b53/b53_spi.c txbuf[1] = reg; reg 125 drivers/net/dsa/b53/b53_srab.c static int b53_srab_op(struct b53_device *dev, u8 page, u8 reg, u32 op) reg 134 drivers/net/dsa/b53/b53_srab.c (reg << B53_SRAB_CMDSTAT_REG) | reg 153 drivers/net/dsa/b53/b53_srab.c static int b53_srab_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val) reg 163 drivers/net/dsa/b53/b53_srab.c ret = b53_srab_op(dev, page, reg, 0); reg 175 drivers/net/dsa/b53/b53_srab.c static int b53_srab_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val) reg 185 drivers/net/dsa/b53/b53_srab.c ret = b53_srab_op(dev, page, reg, 0); reg 197 drivers/net/dsa/b53/b53_srab.c static int b53_srab_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val) reg 207 drivers/net/dsa/b53/b53_srab.c ret = b53_srab_op(dev, page, reg, 0); reg 219 drivers/net/dsa/b53/b53_srab.c static int b53_srab_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val) reg 229 drivers/net/dsa/b53/b53_srab.c ret = b53_srab_op(dev, page, reg, 0); reg 242 drivers/net/dsa/b53/b53_srab.c static int b53_srab_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val) reg 252 drivers/net/dsa/b53/b53_srab.c ret = b53_srab_op(dev, page, reg, 0); reg 265 drivers/net/dsa/b53/b53_srab.c static int b53_srab_write8(struct b53_device *dev, u8 page, u8 reg, u8 value) reg 277 drivers/net/dsa/b53/b53_srab.c ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE); reg 285 drivers/net/dsa/b53/b53_srab.c static int b53_srab_write16(struct b53_device *dev, u8 page, u8 reg, reg 298 drivers/net/dsa/b53/b53_srab.c ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE); reg 306 drivers/net/dsa/b53/b53_srab.c static int b53_srab_write32(struct b53_device *dev, u8 page, u8 reg, reg 319 drivers/net/dsa/b53/b53_srab.c ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE); reg 327 drivers/net/dsa/b53/b53_srab.c static int b53_srab_write48(struct b53_device *dev, u8 page, u8 reg, reg 341 drivers/net/dsa/b53/b53_srab.c ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE); reg 349 drivers/net/dsa/b53/b53_srab.c static int b53_srab_write64(struct b53_device *dev, u8 page, u8 reg, reg 363 drivers/net/dsa/b53/b53_srab.c ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE); reg 493 drivers/net/dsa/b53/b53_srab.c u32 reg; reg 495 drivers/net/dsa/b53/b53_srab.c reg = readl(priv->regs + B53_SRAB_CTRLS); reg 497 drivers/net/dsa/b53/b53_srab.c reg |= B53_SRAB_CTRLS_HOST_INTR; reg 499 drivers/net/dsa/b53/b53_srab.c reg &= ~B53_SRAB_CTRLS_HOST_INTR; reg 500 drivers/net/dsa/b53/b53_srab.c writel(reg, priv->regs + B53_SRAB_CTRLS); reg 540 drivers/net/dsa/b53/b53_srab.c u32 reg, off = 0; reg 556 drivers/net/dsa/b53/b53_srab.c reg = readl(priv->mux_config + B53_MUX_CONFIG_P5 + off); reg 557 drivers/net/dsa/b53/b53_srab.c switch (reg & MUX_CONFIG_MASK) { reg 38 drivers/net/dsa/bcm_sf2.c u32 reg, offset; reg 41 drivers/net/dsa/bcm_sf2.c reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); reg 42 drivers/net/dsa/bcm_sf2.c reg &= ~P_TXQ_PSM_VDD(port); reg 43 drivers/net/dsa/bcm_sf2.c core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); reg 49 drivers/net/dsa/bcm_sf2.c reg = core_readl(priv, CORE_SWITCH_CTRL); reg 50 drivers/net/dsa/bcm_sf2.c reg |= MII_DUMB_FWDG_EN; reg 51 drivers/net/dsa/bcm_sf2.c core_writel(priv, reg, CORE_SWITCH_CTRL); reg 56 drivers/net/dsa/bcm_sf2.c reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); reg 58 drivers/net/dsa/bcm_sf2.c reg |= i << (PRT_TO_QID_SHIFT * i); reg 59 drivers/net/dsa/bcm_sf2.c core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); reg 70 drivers/net/dsa/bcm_sf2.c reg = core_readl(priv, offset); reg 71 drivers/net/dsa/bcm_sf2.c reg |= (MII_SW_OR | LINK_STS); reg 72 drivers/net/dsa/bcm_sf2.c reg &= ~GMII_SPEED_UP_2G; reg 73 drivers/net/dsa/bcm_sf2.c core_writel(priv, reg, offset); reg 76 drivers/net/dsa/bcm_sf2.c reg = core_readl(priv, CORE_IMP_CTL); reg 77 drivers/net/dsa/bcm_sf2.c reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); reg 78 drivers/net/dsa/bcm_sf2.c reg &= ~(RX_DIS | TX_DIS); reg 79 drivers/net/dsa/bcm_sf2.c core_writel(priv, reg, CORE_IMP_CTL); reg 81 drivers/net/dsa/bcm_sf2.c reg = core_readl(priv, CORE_G_PCTL_PORT(port)); reg 82 drivers/net/dsa/bcm_sf2.c reg &= ~(RX_DIS | TX_DIS); reg 83 drivers/net/dsa/bcm_sf2.c core_writel(priv, reg, CORE_G_PCTL_PORT(port)); reg 90 drivers/net/dsa/bcm_sf2.c u32 reg; reg 92 drivers/net/dsa/bcm_sf2.c reg = reg_readl(priv, REG_SPHY_CNTRL); reg 94 drivers/net/dsa/bcm_sf2.c reg |= PHY_RESET; reg 95 drivers/net/dsa/bcm_sf2.c reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); reg 96 drivers/net/dsa/bcm_sf2.c reg_writel(priv, reg, REG_SPHY_CNTRL); reg 98 drivers/net/dsa/bcm_sf2.c reg = reg_readl(priv, REG_SPHY_CNTRL); reg 99 drivers/net/dsa/bcm_sf2.c reg &= ~PHY_RESET; reg 101 drivers/net/dsa/bcm_sf2.c reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; reg 102 drivers/net/dsa/bcm_sf2.c reg_writel(priv, reg, REG_SPHY_CNTRL); reg 104 drivers/net/dsa/bcm_sf2.c reg |= CK25_DIS; reg 106 drivers/net/dsa/bcm_sf2.c reg_writel(priv, reg, REG_SPHY_CNTRL); reg 110 drivers/net/dsa/bcm_sf2.c reg = reg_readl(priv, REG_LED_CNTRL(0)); reg 111 drivers/net/dsa/bcm_sf2.c reg |= SPDLNK_SRC_SEL; reg 112 drivers/net/dsa/bcm_sf2.c reg_writel(priv, reg, REG_LED_CNTRL(0)); reg 165 drivers/net/dsa/bcm_sf2.c u32 reg; reg 171 drivers/net/dsa/bcm_sf2.c reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); reg 172 drivers/net/dsa/bcm_sf2.c reg &= ~P_TXQ_PSM_VDD(port); reg 173 drivers/net/dsa/bcm_sf2.c core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); reg 176 drivers/net/dsa/bcm_sf2.c reg = core_readl(priv, CORE_DIS_LEARN); reg 177 drivers/net/dsa/bcm_sf2.c reg &= ~BIT(port); reg 178 drivers/net/dsa/bcm_sf2.c core_writel(priv, reg, CORE_DIS_LEARN); reg 187 drivers/net/dsa/bcm_sf2.c reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); reg 189 drivers/net/dsa/bcm_sf2.c reg |= i << (PRT_TO_QID_SHIFT * i); reg 190 drivers/net/dsa/bcm_sf2.c core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); reg 219 drivers/net/dsa/bcm_sf2.c reg = acb_readl(priv, ACB_QUEUE_CFG(port * reg 221 drivers/net/dsa/bcm_sf2.c reg &= ~XOFF_THRESHOLD_MASK; reg 222 drivers/net/dsa/bcm_sf2.c reg |= 24; reg 223 drivers/net/dsa/bcm_sf2.c acb_writel(priv, reg, ACB_QUEUE_CFG(port * reg 233 drivers/net/dsa/bcm_sf2.c u32 reg; reg 237 drivers/net/dsa/bcm_sf2.c reg = core_readl(priv, CORE_DIS_LEARN); reg 238 drivers/net/dsa/bcm_sf2.c reg |= BIT(port); reg 239 drivers/net/dsa/bcm_sf2.c core_writel(priv, reg, CORE_DIS_LEARN); reg 252 drivers/net/dsa/bcm_sf2.c reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); reg 253 drivers/net/dsa/bcm_sf2.c reg |= P_TXQ_PSM_VDD(port); reg 254 drivers/net/dsa/bcm_sf2.c core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); reg 262 drivers/net/dsa/bcm_sf2.c u32 reg; reg 264 drivers/net/dsa/bcm_sf2.c reg = reg_readl(priv, REG_SWITCH_CNTRL); reg 265 drivers/net/dsa/bcm_sf2.c reg |= MDIO_MASTER_SEL; reg 266 drivers/net/dsa/bcm_sf2.c reg_writel(priv, reg, REG_SWITCH_CNTRL); reg 269 drivers/net/dsa/bcm_sf2.c reg = 0x70; reg 270 drivers/net/dsa/bcm_sf2.c reg <<= 2; reg 271 drivers/net/dsa/bcm_sf2.c core_writel(priv, addr, reg); reg 274 drivers/net/dsa/bcm_sf2.c reg = 0x80 << 8 | regnum << 1; reg 275 drivers/net/dsa/bcm_sf2.c reg <<= 2; reg 278 drivers/net/dsa/bcm_sf2.c ret = core_readl(priv, reg); reg 280 drivers/net/dsa/bcm_sf2.c core_writel(priv, val, reg); reg 282 drivers/net/dsa/bcm_sf2.c reg = reg_readl(priv, REG_SWITCH_CNTRL); reg 283 drivers/net/dsa/bcm_sf2.c reg &= ~MDIO_MASTER_SEL; reg 284 drivers/net/dsa/bcm_sf2.c reg_writel(priv, reg, REG_SWITCH_CNTRL); reg 353 drivers/net/dsa/bcm_sf2.c u32 reg; reg 355 drivers/net/dsa/bcm_sf2.c reg = core_readl(priv, CORE_WATCHDOG_CTRL); reg 356 drivers/net/dsa/bcm_sf2.c reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; reg 357 drivers/net/dsa/bcm_sf2.c core_writel(priv, reg, CORE_WATCHDOG_CTRL); reg 360 drivers/net/dsa/bcm_sf2.c reg = core_readl(priv, CORE_WATCHDOG_CTRL); reg 361 drivers/net/dsa/bcm_sf2.c if (!(reg & SOFTWARE_RESET)) reg 540 drivers/net/dsa/bcm_sf2.c u32 reg, offset; reg 571 drivers/net/dsa/bcm_sf2.c reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); reg 572 drivers/net/dsa/bcm_sf2.c reg &= ~ID_MODE_DIS; reg 573 drivers/net/dsa/bcm_sf2.c reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); reg 574 drivers/net/dsa/bcm_sf2.c reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); reg 576 drivers/net/dsa/bcm_sf2.c reg |= port_mode; reg 578 drivers/net/dsa/bcm_sf2.c reg |= ID_MODE_DIS; reg 582 drivers/net/dsa/bcm_sf2.c reg |= TX_PAUSE_EN; reg 583 drivers/net/dsa/bcm_sf2.c reg |= RX_PAUSE_EN; reg 586 drivers/net/dsa/bcm_sf2.c reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); reg 590 drivers/net/dsa/bcm_sf2.c reg = SW_OVERRIDE; reg 593 drivers/net/dsa/bcm_sf2.c reg |= SPDSTS_1000 << SPEED_SHIFT; reg 596 drivers/net/dsa/bcm_sf2.c reg |= SPDSTS_100 << SPEED_SHIFT; reg 601 drivers/net/dsa/bcm_sf2.c reg |= LINK_STS; reg 603 drivers/net/dsa/bcm_sf2.c reg |= DUPLX_MODE; reg 605 drivers/net/dsa/bcm_sf2.c core_writel(priv, reg, offset); reg 612 drivers/net/dsa/bcm_sf2.c u32 reg; reg 620 drivers/net/dsa/bcm_sf2.c reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); reg 622 drivers/net/dsa/bcm_sf2.c reg |= RGMII_MODE_EN; reg 624 drivers/net/dsa/bcm_sf2.c reg &= ~RGMII_MODE_EN; reg 625 drivers/net/dsa/bcm_sf2.c reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); reg 682 drivers/net/dsa/bcm_sf2.c u32 reg; reg 685 drivers/net/dsa/bcm_sf2.c reg = acb_readl(priv, ACB_CONTROL); reg 686 drivers/net/dsa/bcm_sf2.c reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); reg 687 drivers/net/dsa/bcm_sf2.c acb_writel(priv, reg, ACB_CONTROL); reg 688 drivers/net/dsa/bcm_sf2.c reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT); reg 689 drivers/net/dsa/bcm_sf2.c reg |= ACB_EN | ACB_ALGORITHM; reg 690 drivers/net/dsa/bcm_sf2.c acb_writel(priv, reg, ACB_CONTROL); reg 815 drivers/net/dsa/bcm_sf2.c #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) reg 817 drivers/net/dsa/bcm_sf2.c static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, reg 822 drivers/net/dsa/bcm_sf2.c *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); reg 827 drivers/net/dsa/bcm_sf2.c static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, reg 832 drivers/net/dsa/bcm_sf2.c *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); reg 837 drivers/net/dsa/bcm_sf2.c static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, reg 842 drivers/net/dsa/bcm_sf2.c *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); reg 847 drivers/net/dsa/bcm_sf2.c static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, reg 852 drivers/net/dsa/bcm_sf2.c *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); reg 857 drivers/net/dsa/bcm_sf2.c static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, reg 862 drivers/net/dsa/bcm_sf2.c core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); reg 867 drivers/net/dsa/bcm_sf2.c static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, reg 872 drivers/net/dsa/bcm_sf2.c core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); reg 877 drivers/net/dsa/bcm_sf2.c static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, reg 882 drivers/net/dsa/bcm_sf2.c core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); reg 887 drivers/net/dsa/bcm_sf2.c static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, reg 892 drivers/net/dsa/bcm_sf2.c core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); reg 1062 drivers/net/dsa/bcm_sf2.c u32 reg, rev; reg 1178 drivers/net/dsa/bcm_sf2.c reg = core_readl(priv, CORE_GMNCFGCFG); reg 1179 drivers/net/dsa/bcm_sf2.c reg |= RST_MIB_CNT; reg 1180 drivers/net/dsa/bcm_sf2.c core_writel(priv, reg, CORE_GMNCFGCFG); reg 1181 drivers/net/dsa/bcm_sf2.c reg &= ~RST_MIB_CNT; reg 1182 drivers/net/dsa/bcm_sf2.c core_writel(priv, reg, CORE_GMNCFGCFG); reg 61 drivers/net/dsa/bcm_sf2.h void __iomem *reg; reg 187 drivers/net/dsa/bcm_sf2.h return readl_relaxed(priv->reg + priv->reg_offsets[off]); reg 192 drivers/net/dsa/bcm_sf2.h writel_relaxed(val, priv->reg + priv->reg_offsets[off]); reg 170 drivers/net/dsa/bcm_sf2_cfp.c u32 reg; reg 172 drivers/net/dsa/bcm_sf2_cfp.c reg = core_readl(priv, CORE_CFP_ACC); reg 173 drivers/net/dsa/bcm_sf2_cfp.c reg &= ~(OP_SEL_MASK | RAM_SEL_MASK); reg 174 drivers/net/dsa/bcm_sf2_cfp.c reg |= OP_STR_DONE | op; reg 175 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, reg, CORE_CFP_ACC); reg 178 drivers/net/dsa/bcm_sf2_cfp.c reg = core_readl(priv, CORE_CFP_ACC); reg 179 drivers/net/dsa/bcm_sf2_cfp.c if (!(reg & OP_STR_DONE)) reg 194 drivers/net/dsa/bcm_sf2_cfp.c u32 reg; reg 198 drivers/net/dsa/bcm_sf2_cfp.c reg = core_readl(priv, CORE_CFP_ACC); reg 199 drivers/net/dsa/bcm_sf2_cfp.c reg &= ~(XCESS_ADDR_MASK << XCESS_ADDR_SHIFT); reg 200 drivers/net/dsa/bcm_sf2_cfp.c reg |= addr << XCESS_ADDR_SHIFT; reg 201 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, reg, CORE_CFP_ACC); reg 218 drivers/net/dsa/bcm_sf2_cfp.c u32 reg; reg 224 drivers/net/dsa/bcm_sf2_cfp.c reg = CHANGE_FWRD_MAP_IB_REP_ARL | reg 228 drivers/net/dsa/bcm_sf2_cfp.c reg = 0; reg 232 drivers/net/dsa/bcm_sf2_cfp.c reg |= LOOP_BK_EN; reg 234 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, reg, CORE_ACT_POL_DATA0); reg 267 drivers/net/dsa/bcm_sf2_cfp.c u32 reg, offset; reg 273 drivers/net/dsa/bcm_sf2_cfp.c reg = 0; reg 278 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, reg, offset); reg 284 drivers/net/dsa/bcm_sf2_cfp.c reg = be16_to_cpu(ports->dst) >> 8; reg 289 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, reg, offset); reg 295 drivers/net/dsa/bcm_sf2_cfp.c reg = (be16_to_cpu(ports->dst) & 0xff) << 24 | reg 302 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, reg, offset); reg 308 drivers/net/dsa/bcm_sf2_cfp.c reg = (u32)(be32_to_cpu(addrs->dst) & 0xff) << 24 | reg 315 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, reg, offset); reg 323 drivers/net/dsa/bcm_sf2_cfp.c reg = (u32)(be32_to_cpu(addrs->src) & 0xff) << 24 | reg 330 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, reg, offset); reg 347 drivers/net/dsa/bcm_sf2_cfp.c u32 reg; reg 453 drivers/net/dsa/bcm_sf2_cfp.c reg = core_readl(priv, CORE_CFP_CTL_REG); reg 454 drivers/net/dsa/bcm_sf2_cfp.c reg |= BIT(port); reg 455 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, reg, CORE_CFP_CTL_REG); reg 474 drivers/net/dsa/bcm_sf2_cfp.c u32 reg, tmp, val, offset; reg 480 drivers/net/dsa/bcm_sf2_cfp.c reg = be32_to_cpu(ip6_addr[3]); reg 481 drivers/net/dsa/bcm_sf2_cfp.c val = (u32)be16_to_cpu(port) << 8 | ((reg >> 8) & 0xff); reg 493 drivers/net/dsa/bcm_sf2_cfp.c val = (u32)(reg & 0xff) << 24 | (u32)(reg >> 16) << 8 | reg 505 drivers/net/dsa/bcm_sf2_cfp.c reg = be32_to_cpu(ip6_addr[1]); reg 507 drivers/net/dsa/bcm_sf2_cfp.c ((reg >> 8) & 0xff); reg 519 drivers/net/dsa/bcm_sf2_cfp.c val = (u32)(reg & 0xff) << 24 | (u32)(reg >> 16) << 8 | reg 533 drivers/net/dsa/bcm_sf2_cfp.c reg = (u32)(tmp & 0xff) << 24 | (u32)(tmp >> 16) << 8 | reg 539 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, reg, offset); reg 611 drivers/net/dsa/bcm_sf2_cfp.c u32 reg; reg 697 drivers/net/dsa/bcm_sf2_cfp.c reg = 1 << L3_FRAMING_SHIFT | ip_proto << IPPROTO_SHIFT | reg 699 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, reg, CORE_CFP_DATA_PORT(6)); reg 704 drivers/net/dsa/bcm_sf2_cfp.c reg = layout->udfs[slice_num].mask_value | udf_upper_bits(num_udf); reg 705 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, reg, CORE_CFP_MASK_PORT(6)); reg 762 drivers/net/dsa/bcm_sf2_cfp.c reg = rule_index[0] << 24 | udf_upper_bits(num_udf) << 16 | reg 764 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, reg, CORE_CFP_DATA_PORT(6)); reg 767 drivers/net/dsa/bcm_sf2_cfp.c reg = XCESS_ADDR_MASK << 24 | udf_upper_bits(num_udf) << 16 | reg 769 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, reg, CORE_CFP_MASK_PORT(6)); reg 800 drivers/net/dsa/bcm_sf2_cfp.c reg = core_readl(priv, CORE_CFP_CTL_REG); reg 801 drivers/net/dsa/bcm_sf2_cfp.c reg |= BIT(port); reg 802 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, reg, CORE_CFP_CTL_REG); reg 918 drivers/net/dsa/bcm_sf2_cfp.c u32 reg; reg 931 drivers/net/dsa/bcm_sf2_cfp.c reg = core_readl(priv, CORE_CFP_DATA_PORT(6)); reg 933 drivers/net/dsa/bcm_sf2_cfp.c *next_loc = (reg >> 24) & CHAIN_ID_MASK; reg 936 drivers/net/dsa/bcm_sf2_cfp.c reg = core_readl(priv, CORE_CFP_DATA_PORT(0)); reg 937 drivers/net/dsa/bcm_sf2_cfp.c reg &= ~SLICE_VALID; reg 938 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, reg, CORE_CFP_DATA_PORT(0)); reg 1136 drivers/net/dsa/bcm_sf2_cfp.c u32 reg; reg 1138 drivers/net/dsa/bcm_sf2_cfp.c reg = core_readl(priv, CORE_CFP_ACC); reg 1139 drivers/net/dsa/bcm_sf2_cfp.c reg |= TCAM_RESET; reg 1140 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, reg, CORE_CFP_ACC); reg 1143 drivers/net/dsa/bcm_sf2_cfp.c reg = core_readl(priv, CORE_CFP_ACC); reg 1144 drivers/net/dsa/bcm_sf2_cfp.c if (!(reg & TCAM_RESET)) reg 1173 drivers/net/dsa/bcm_sf2_cfp.c u32 reg; reg 1178 drivers/net/dsa/bcm_sf2_cfp.c reg = core_readl(priv, CORE_CFP_CTL_REG); reg 1179 drivers/net/dsa/bcm_sf2_cfp.c reg &= ~CFP_EN_MAP_MASK; reg 1180 drivers/net/dsa/bcm_sf2_cfp.c core_writel(priv, reg, CORE_CFP_CTL_REG); reg 222 drivers/net/dsa/lan9303-core.c static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg) reg 232 drivers/net/dsa/lan9303-core.c ret = regmap_read(regmap, offset, reg); reg 248 drivers/net/dsa/lan9303-core.c u32 reg; reg 251 drivers/net/dsa/lan9303-core.c ret = lan9303_read(chip->regmap, offset, ®); reg 257 drivers/net/dsa/lan9303-core.c if (!(reg & mask)) reg 335 drivers/net/dsa/lan9303-core.c u32 reg; reg 337 drivers/net/dsa/lan9303-core.c reg = LAN9303_PMI_ACCESS_PHY_ADDR(addr); reg 338 drivers/net/dsa/lan9303-core.c reg |= LAN9303_PMI_ACCESS_MIIRINDA(regnum); reg 339 drivers/net/dsa/lan9303-core.c reg |= LAN9303_PMI_ACCESS_MII_WRITE; reg 353 drivers/net/dsa/lan9303-core.c ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg); reg 374 drivers/net/dsa/lan9303-core.c u32 reg; reg 377 drivers/net/dsa/lan9303-core.c reg = regnum; reg 378 drivers/net/dsa/lan9303-core.c reg |= LAN9303_SWITCH_CSR_CMD_LANES; reg 379 drivers/net/dsa/lan9303-core.c reg |= LAN9303_SWITCH_CSR_CMD_BUSY; reg 394 drivers/net/dsa/lan9303-core.c ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); reg 406 drivers/net/dsa/lan9303-core.c u32 reg; reg 409 drivers/net/dsa/lan9303-core.c reg = regnum; reg 410 drivers/net/dsa/lan9303-core.c reg |= LAN9303_SWITCH_CSR_CMD_LANES; reg 411 drivers/net/dsa/lan9303-core.c reg |= LAN9303_SWITCH_CSR_CMD_RW; reg 412 drivers/net/dsa/lan9303-core.c reg |= LAN9303_SWITCH_CSR_CMD_BUSY; reg 421 drivers/net/dsa/lan9303-core.c ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); reg 444 drivers/net/dsa/lan9303-core.c u32 reg; reg 446 drivers/net/dsa/lan9303-core.c ret = lan9303_read_switch_reg(chip, regnum, ®); reg 450 drivers/net/dsa/lan9303-core.c reg = (reg & ~mask) | val; reg 452 drivers/net/dsa/lan9303-core.c return lan9303_write_switch_reg(chip, regnum, reg); reg 471 drivers/net/dsa/lan9303-core.c int reg; reg 483 drivers/net/dsa/lan9303-core.c reg = chip->ops->phy_read(chip, 3, MII_LAN911X_SPECIAL_MODES); reg 484 drivers/net/dsa/lan9303-core.c if (reg < 0) { reg 485 drivers/net/dsa/lan9303-core.c dev_err(chip->dev, "Failed to detect phy config: %d\n", reg); reg 486 drivers/net/dsa/lan9303-core.c return reg; reg 489 drivers/net/dsa/lan9303-core.c chip->phy_addr_base = reg != 0 && reg != 0xffff; reg 537 drivers/net/dsa/lan9303-core.c u32 reg; reg 539 drivers/net/dsa/lan9303-core.c lan9303_read_switch_reg(chip, regno, ®); reg 540 drivers/net/dsa/lan9303-core.c if (!(reg & mask)) reg 841 drivers/net/dsa/lan9303-core.c u32 reg; reg 843 drivers/net/dsa/lan9303-core.c ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, ®); reg 854 drivers/net/dsa/lan9303-core.c if ((reg >> 16) != LAN9303_CHIP_ID) { reg 856 drivers/net/dsa/lan9303-core.c reg >> 16); reg 871 drivers/net/dsa/lan9303-core.c dev_info(chip->dev, "Found LAN9303 rev. %u\n", reg & 0xffff); reg 992 drivers/net/dsa/lan9303-core.c u32 reg; reg 996 drivers/net/dsa/lan9303-core.c chip, port, lan9303_mib[u].offset, ®); reg 1001 drivers/net/dsa/lan9303-core.c data[u] = reg; reg 25 drivers/net/dsa/lan9303_mdio.c static void lan9303_mdio_real_write(struct mdio_device *mdio, int reg, u16 val) reg 27 drivers/net/dsa/lan9303_mdio.c mdio->bus->write(mdio->bus, PHY_ADDR(reg), PHY_REG(reg), val); reg 30 drivers/net/dsa/lan9303_mdio.c static int lan9303_mdio_write(void *ctx, uint32_t reg, uint32_t val) reg 34 drivers/net/dsa/lan9303_mdio.c reg <<= 2; /* reg num to offset */ reg 36 drivers/net/dsa/lan9303_mdio.c lan9303_mdio_real_write(sw_dev->device, reg, val & 0xffff); reg 37 drivers/net/dsa/lan9303_mdio.c lan9303_mdio_real_write(sw_dev->device, reg + 2, (val >> 16) & 0xffff); reg 43 drivers/net/dsa/lan9303_mdio.c static u16 lan9303_mdio_real_read(struct mdio_device *mdio, int reg) reg 45 drivers/net/dsa/lan9303_mdio.c return mdio->bus->read(mdio->bus, PHY_ADDR(reg), PHY_REG(reg)); reg 48 drivers/net/dsa/lan9303_mdio.c static int lan9303_mdio_read(void *ctx, uint32_t reg, uint32_t *val) reg 52 drivers/net/dsa/lan9303_mdio.c reg <<= 2; /* reg num to offset */ reg 54 drivers/net/dsa/lan9303_mdio.c *val = lan9303_mdio_real_read(sw_dev->device, reg); reg 55 drivers/net/dsa/lan9303_mdio.c *val |= (lan9303_mdio_real_read(sw_dev->device, reg + 2) << 16); reg 61 drivers/net/dsa/lan9303_mdio.c static int lan9303_mdio_phy_write(struct lan9303 *chip, int phy, int reg, reg 66 drivers/net/dsa/lan9303_mdio.c return mdiobus_write_nested(sw_dev->device->bus, phy, reg, val); reg 69 drivers/net/dsa/lan9303_mdio.c static int lan9303_mdio_phy_read(struct lan9303 *chip, int phy, int reg) reg 73 drivers/net/dsa/lan9303_mdio.c return mdiobus_read_nested(sw_dev->device->bus, phy, reg); reg 438 drivers/net/dsa/lantiq_gswip.c static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) reg 452 drivers/net/dsa/lantiq_gswip.c (reg & GSWIP_MDIO_CTRL_REGAD_MASK), reg 458 drivers/net/dsa/lantiq_gswip.c static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg) reg 471 drivers/net/dsa/lantiq_gswip.c (reg & GSWIP_MDIO_CTRL_REGAD_MASK), reg 458 drivers/net/dsa/microchip/ksz8795.c static void ksz8795_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) reg 465 drivers/net/dsa/microchip/ksz8795.c switch (reg) { reg 549 drivers/net/dsa/microchip/ksz8795.c static void ksz8795_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) reg 554 drivers/net/dsa/microchip/ksz8795.c switch (reg) { reg 308 drivers/net/dsa/microchip/ksz9477.c static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg) reg 322 drivers/net/dsa/microchip/ksz9477.c switch (reg) { reg 352 drivers/net/dsa/microchip/ksz9477.c ksz_pread16(dev, addr, 0x100 + (reg << 1), &val); reg 358 drivers/net/dsa/microchip/ksz9477.c static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg, reg 368 drivers/net/dsa/microchip/ksz9477.c if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000) reg 370 drivers/net/dsa/microchip/ksz9477.c ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val); reg 125 drivers/net/dsa/microchip/ksz_common.c int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) reg 130 drivers/net/dsa/microchip/ksz_common.c dev->dev_ops->r_phy(dev, addr, reg, &val); reg 136 drivers/net/dsa/microchip/ksz_common.c int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) reg 140 drivers/net/dsa/microchip/ksz_common.c dev->dev_ops->w_phy(dev, addr, reg, val); reg 127 drivers/net/dsa/microchip/ksz_common.h void (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); reg 128 drivers/net/dsa/microchip/ksz_common.h void (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); reg 161 drivers/net/dsa/microchip/ksz_common.h int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg); reg 162 drivers/net/dsa/microchip/ksz_common.h int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val); reg 187 drivers/net/dsa/microchip/ksz_common.h static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) reg 190 drivers/net/dsa/microchip/ksz_common.h int ret = regmap_read(dev->regmap[0], reg, &value); reg 196 drivers/net/dsa/microchip/ksz_common.h static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) reg 199 drivers/net/dsa/microchip/ksz_common.h int ret = regmap_read(dev->regmap[1], reg, &value); reg 205 drivers/net/dsa/microchip/ksz_common.h static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) reg 208 drivers/net/dsa/microchip/ksz_common.h int ret = regmap_read(dev->regmap[2], reg, &value); reg 214 drivers/net/dsa/microchip/ksz_common.h static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) reg 219 drivers/net/dsa/microchip/ksz_common.h ret = regmap_bulk_read(dev->regmap[2], reg, value, 2); reg 230 drivers/net/dsa/microchip/ksz_common.h static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) reg 232 drivers/net/dsa/microchip/ksz_common.h return regmap_write(dev->regmap[0], reg, value); reg 235 drivers/net/dsa/microchip/ksz_common.h static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) reg 237 drivers/net/dsa/microchip/ksz_common.h return regmap_write(dev->regmap[1], reg, value); reg 240 drivers/net/dsa/microchip/ksz_common.h static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) reg 242 drivers/net/dsa/microchip/ksz_common.h return regmap_write(dev->regmap[2], reg, value); reg 245 drivers/net/dsa/microchip/ksz_common.h static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) reg 254 drivers/net/dsa/microchip/ksz_common.h return regmap_bulk_write(dev->regmap[2], reg, val, 2); reg 132 drivers/net/dsa/mt7530.c core_write(struct mt7530_priv *priv, u32 reg, u32 val) reg 138 drivers/net/dsa/mt7530.c core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); reg 144 drivers/net/dsa/mt7530.c core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) reg 151 drivers/net/dsa/mt7530.c val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); reg 154 drivers/net/dsa/mt7530.c core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); reg 160 drivers/net/dsa/mt7530.c core_set(struct mt7530_priv *priv, u32 reg, u32 val) reg 162 drivers/net/dsa/mt7530.c core_rmw(priv, reg, 0, val); reg 166 drivers/net/dsa/mt7530.c core_clear(struct mt7530_priv *priv, u32 reg, u32 val) reg 168 drivers/net/dsa/mt7530.c core_rmw(priv, reg, val, 0); reg 172 drivers/net/dsa/mt7530.c mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) reg 178 drivers/net/dsa/mt7530.c page = (reg >> 6) & 0x3ff; reg 179 drivers/net/dsa/mt7530.c r = (reg >> 2) & 0xf; reg 201 drivers/net/dsa/mt7530.c mt7530_mii_read(struct mt7530_priv *priv, u32 reg) reg 207 drivers/net/dsa/mt7530.c page = (reg >> 6) & 0x3ff; reg 208 drivers/net/dsa/mt7530.c r = (reg >> 2) & 0xf; reg 225 drivers/net/dsa/mt7530.c mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) reg 231 drivers/net/dsa/mt7530.c mt7530_mii_write(priv, reg, val); reg 244 drivers/net/dsa/mt7530.c val = mt7530_mii_read(p->priv, p->reg); reg 252 drivers/net/dsa/mt7530.c mt7530_read(struct mt7530_priv *priv, u32 reg) reg 256 drivers/net/dsa/mt7530.c INIT_MT7530_DUMMY_POLL(&p, priv, reg); reg 261 drivers/net/dsa/mt7530.c mt7530_rmw(struct mt7530_priv *priv, u32 reg, reg 269 drivers/net/dsa/mt7530.c val = mt7530_mii_read(priv, reg); reg 272 drivers/net/dsa/mt7530.c mt7530_mii_write(priv, reg, val); reg 278 drivers/net/dsa/mt7530.c mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) reg 280 drivers/net/dsa/mt7530.c mt7530_rmw(priv, reg, 0, val); reg 284 drivers/net/dsa/mt7530.c mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) reg 286 drivers/net/dsa/mt7530.c mt7530_rmw(priv, reg, val, 0); reg 324 drivers/net/dsa/mt7530.c u32 reg[3]; reg 329 drivers/net/dsa/mt7530.c reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); reg 332 drivers/net/dsa/mt7530.c __func__, __LINE__, i, reg[i]); reg 335 drivers/net/dsa/mt7530.c fdb->vid = (reg[1] >> CVID) & CVID_MASK; reg 336 drivers/net/dsa/mt7530.c fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; reg 337 drivers/net/dsa/mt7530.c fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; reg 338 drivers/net/dsa/mt7530.c fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; reg 339 drivers/net/dsa/mt7530.c fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; reg 340 drivers/net/dsa/mt7530.c fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; reg 341 drivers/net/dsa/mt7530.c fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; reg 342 drivers/net/dsa/mt7530.c fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; reg 343 drivers/net/dsa/mt7530.c fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; reg 344 drivers/net/dsa/mt7530.c fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; reg 352 drivers/net/dsa/mt7530.c u32 reg[3] = { 0 }; reg 355 drivers/net/dsa/mt7530.c reg[1] |= vid & CVID_MASK; reg 356 drivers/net/dsa/mt7530.c reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; reg 357 drivers/net/dsa/mt7530.c reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; reg 362 drivers/net/dsa/mt7530.c reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; reg 363 drivers/net/dsa/mt7530.c reg[1] |= mac[5] << MAC_BYTE_5; reg 364 drivers/net/dsa/mt7530.c reg[1] |= mac[4] << MAC_BYTE_4; reg 365 drivers/net/dsa/mt7530.c reg[0] |= mac[3] << MAC_BYTE_3; reg 366 drivers/net/dsa/mt7530.c reg[0] |= mac[2] << MAC_BYTE_2; reg 367 drivers/net/dsa/mt7530.c reg[0] |= mac[1] << MAC_BYTE_1; reg 368 drivers/net/dsa/mt7530.c reg[0] |= mac[0] << MAC_BYTE_0; reg 372 drivers/net/dsa/mt7530.c mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); reg 539 drivers/net/dsa/mt7530.c u32 reg, i; reg 544 drivers/net/dsa/mt7530.c reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; reg 546 drivers/net/dsa/mt7530.c data[i] = mt7530_read(priv, reg); reg 548 drivers/net/dsa/mt7530.c hi = mt7530_read(priv, reg + 4); reg 491 drivers/net/dsa/mt7530.h u16 reg; reg 497 drivers/net/dsa/mt7530.h u32 reg; reg 501 drivers/net/dsa/mt7530.h struct mt7530_priv *priv, u32 reg) reg 504 drivers/net/dsa/mt7530.h p->reg = reg; reg 17 drivers/net/dsa/mv88e6060.c static int reg_read(struct mv88e6060_priv *priv, int addr, int reg) reg 19 drivers/net/dsa/mv88e6060.c return mdiobus_read_nested(priv->bus, priv->sw_addr + addr, reg); reg 22 drivers/net/dsa/mv88e6060.c static int reg_write(struct mv88e6060_priv *priv, int addr, int reg, u16 val) reg 24 drivers/net/dsa/mv88e6060.c return mdiobus_write_nested(priv->bus, priv->sw_addr + addr, reg, val); reg 52 drivers/net/dsa/mv88e6xxx/chip.c int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) reg 58 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_smi_read(chip, addr, reg, val); reg 63 drivers/net/dsa/mv88e6xxx/chip.c addr, reg, *val); reg 68 drivers/net/dsa/mv88e6xxx/chip.c int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) reg 74 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_smi_write(chip, addr, reg, val); reg 79 drivers/net/dsa/mv88e6xxx/chip.c addr, reg, val); reg 84 drivers/net/dsa/mv88e6xxx/chip.c int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, reg 93 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_read(chip, addr, reg, &data); reg 107 drivers/net/dsa/mv88e6xxx/chip.c int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, reg 110 drivers/net/dsa/mv88e6xxx/chip.c return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), reg 147 drivers/net/dsa/mv88e6xxx/chip.c u16 reg; reg 152 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); reg 160 drivers/net/dsa/mv88e6xxx/chip.c if (reg & (1 << n)) { reg 172 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); reg 178 drivers/net/dsa/mv88e6xxx/chip.c } while (reg & ctl1); reg 202 drivers/net/dsa/mv88e6xxx/chip.c u16 reg; reg 205 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); reg 209 drivers/net/dsa/mv88e6xxx/chip.c reg &= ~mask; reg 210 drivers/net/dsa/mv88e6xxx/chip.c reg |= (~chip->g1_irq.masked & mask); reg 212 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); reg 280 drivers/net/dsa/mv88e6xxx/chip.c u16 reg, mask; reg 306 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); reg 738 drivers/net/dsa/mv88e6xxx/chip.c u16 reg = 0; reg 744 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_port_read(chip, port, s->reg, ®); reg 748 drivers/net/dsa/mv88e6xxx/chip.c low = reg; reg 750 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); reg 753 drivers/net/dsa/mv88e6xxx/chip.c low |= ((u32)reg) << 16; reg 757 drivers/net/dsa/mv88e6xxx/chip.c reg = bank1_select; reg 760 drivers/net/dsa/mv88e6xxx/chip.c reg |= s->reg | histogram; reg 761 drivers/net/dsa/mv88e6xxx/chip.c mv88e6xxx_g1_stats_read(chip, reg, &low); reg 763 drivers/net/dsa/mv88e6xxx/chip.c mv88e6xxx_g1_stats_read(chip, reg + 1, &high); reg 1026 drivers/net/dsa/mv88e6xxx/chip.c u16 reg; reg 1038 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_port_read(chip, port, i, ®); reg 1040 drivers/net/dsa/mv88e6xxx/chip.c p[i] = reg; reg 2394 drivers/net/dsa/mv88e6xxx/chip.c u16 reg; reg 2430 drivers/net/dsa/mv88e6xxx/chip.c reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | reg 2433 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); reg 2475 drivers/net/dsa/mv88e6xxx/chip.c reg = 1 << port; reg 2478 drivers/net/dsa/mv88e6xxx/chip.c reg = 0; reg 2481 drivers/net/dsa/mv88e6xxx/chip.c reg); reg 2763 drivers/net/dsa/mv88e6xxx/chip.c static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) reg 2774 drivers/net/dsa/mv88e6xxx/chip.c err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); reg 2777 drivers/net/dsa/mv88e6xxx/chip.c if (reg == MII_PHYSID2) { reg 2799 drivers/net/dsa/mv88e6xxx/chip.c static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) reg 2809 drivers/net/dsa/mv88e6xxx/chip.c err = chip->info->ops->phy_write(chip, bus, phy, reg, val); reg 321 drivers/net/dsa/mv88e6xxx/chip.h int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); reg 322 drivers/net/dsa/mv88e6xxx/chip.h int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); reg 353 drivers/net/dsa/mv88e6xxx/chip.h int addr, int reg, u16 *val); reg 356 drivers/net/dsa/mv88e6xxx/chip.h int addr, int reg, u16 val); reg 598 drivers/net/dsa/mv88e6xxx/chip.h int reg; reg 632 drivers/net/dsa/mv88e6xxx/chip.h int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val); reg 633 drivers/net/dsa/mv88e6xxx/chip.h int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val); reg 634 drivers/net/dsa/mv88e6xxx/chip.h int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, reg 636 drivers/net/dsa/mv88e6xxx/chip.h int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, reg 16 drivers/net/dsa/mv88e6xxx/global1.c int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) reg 20 drivers/net/dsa/mv88e6xxx/global1.c return mv88e6xxx_read(chip, addr, reg, val); reg 23 drivers/net/dsa/mv88e6xxx/global1.c int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) reg 27 drivers/net/dsa/mv88e6xxx/global1.c return mv88e6xxx_write(chip, addr, reg, val); reg 30 drivers/net/dsa/mv88e6xxx/global1.c int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int reg 33 drivers/net/dsa/mv88e6xxx/global1.c return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg, reg 37 drivers/net/dsa/mv88e6xxx/global1.c int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg, reg 40 drivers/net/dsa/mv88e6xxx/global1.c return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg, reg 84 drivers/net/dsa/mv88e6xxx/global1.c u16 reg; reg 87 drivers/net/dsa/mv88e6xxx/global1.c reg = (addr[0] << 8) | addr[1]; reg 88 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); reg 92 drivers/net/dsa/mv88e6xxx/global1.c reg = (addr[2] << 8) | addr[3]; reg 93 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); reg 97 drivers/net/dsa/mv88e6xxx/global1.c reg = (addr[4] << 8) | addr[5]; reg 98 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); reg 268 drivers/net/dsa/mv88e6xxx/global1.c u16 reg; reg 271 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); reg 275 drivers/net/dsa/mv88e6xxx/global1.c reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK | reg 278 drivers/net/dsa/mv88e6xxx/global1.c reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) | reg 281 drivers/net/dsa/mv88e6xxx/global1.c return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); reg 290 drivers/net/dsa/mv88e6xxx/global1.c u16 reg; reg 293 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); reg 297 drivers/net/dsa/mv88e6xxx/global1.c reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK; reg 298 drivers/net/dsa/mv88e6xxx/global1.c reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); reg 300 drivers/net/dsa/mv88e6xxx/global1.c return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); reg 306 drivers/net/dsa/mv88e6xxx/global1.c u16 reg; reg 308 drivers/net/dsa/mv88e6xxx/global1.c reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data; reg 310 drivers/net/dsa/mv88e6xxx/global1.c return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); reg 380 drivers/net/dsa/mv88e6xxx/global1.c u16 reg; reg 383 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); reg 387 drivers/net/dsa/mv88e6xxx/global1.c reg &= ~mask; reg 388 drivers/net/dsa/mv88e6xxx/global1.c reg |= val & mask; reg 390 drivers/net/dsa/mv88e6xxx/global1.c return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); reg 500 drivers/net/dsa/mv88e6xxx/global1.c u16 reg; reg 515 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); reg 519 drivers/net/dsa/mv88e6xxx/global1.c value = reg << 16; reg 521 drivers/net/dsa/mv88e6xxx/global1.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); reg 525 drivers/net/dsa/mv88e6xxx/global1.c *val = value | reg; reg 268 drivers/net/dsa/mv88e6xxx/global1.h int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val); reg 269 drivers/net/dsa/mv88e6xxx/global1.h int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val); reg 270 drivers/net/dsa/mv88e6xxx/global1.h int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int reg 272 drivers/net/dsa/mv88e6xxx/global1.h int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg, reg 137 drivers/net/dsa/mv88e6xxx/global1_vtu.c u16 *reg = ®s[i]; reg 140 drivers/net/dsa/mv88e6xxx/global1_vtu.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_DATA1 + i, reg); reg 174 drivers/net/dsa/mv88e6xxx/global1_vtu.c u16 reg = regs[i]; reg 177 drivers/net/dsa/mv88e6xxx/global1_vtu.c err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_VTU_DATA1 + i, reg); reg 192 drivers/net/dsa/mv88e6xxx/global1_vtu.c u16 *reg = ®s[i]; reg 195 drivers/net/dsa/mv88e6xxx/global1_vtu.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_DATA1 + i, reg); reg 224 drivers/net/dsa/mv88e6xxx/global1_vtu.c u16 reg = regs[i]; reg 227 drivers/net/dsa/mv88e6xxx/global1_vtu.c err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_VTU_DATA1 + i, reg); reg 19 drivers/net/dsa/mv88e6xxx/global2.c int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) reg 21 drivers/net/dsa/mv88e6xxx/global2.c return mv88e6xxx_read(chip, chip->info->global2_addr, reg, val); reg 24 drivers/net/dsa/mv88e6xxx/global2.c int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val) reg 26 drivers/net/dsa/mv88e6xxx/global2.c return mv88e6xxx_write(chip, chip->info->global2_addr, reg, val); reg 29 drivers/net/dsa/mv88e6xxx/global2.c int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg, int reg 32 drivers/net/dsa/mv88e6xxx/global2.c return mv88e6xxx_wait_bit(chip, chip->info->global2_addr, reg, reg 187 drivers/net/dsa/mv88e6xxx/global2.c int res, int reg) reg 193 drivers/net/dsa/mv88e6xxx/global2.c (res << 5) | reg); reg 605 drivers/net/dsa/mv88e6xxx/global2.c int reg) reg 621 drivers/net/dsa/mv88e6xxx/global2.c cmd |= reg & MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK; reg 628 drivers/net/dsa/mv88e6xxx/global2.c int reg) reg 630 drivers/net/dsa/mv88e6xxx/global2.c return mv88e6xxx_g2_smi_phy_access(chip, external, false, op, dev, reg); reg 635 drivers/net/dsa/mv88e6xxx/global2.c bool external, int dev, int reg, reg 645 drivers/net/dsa/mv88e6xxx/global2.c err = mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg); reg 654 drivers/net/dsa/mv88e6xxx/global2.c bool external, int dev, int reg, reg 668 drivers/net/dsa/mv88e6xxx/global2.c return mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg); reg 713 drivers/net/dsa/mv88e6xxx/global2.c bool external, int port, int reg, reg 716 drivers/net/dsa/mv88e6xxx/global2.c int dev = (reg >> 16) & 0x1f; reg 717 drivers/net/dsa/mv88e6xxx/global2.c int addr = reg & 0xffff; reg 745 drivers/net/dsa/mv88e6xxx/global2.c bool external, int port, int reg, reg 748 drivers/net/dsa/mv88e6xxx/global2.c int dev = (reg >> 16) & 0x1f; reg 749 drivers/net/dsa/mv88e6xxx/global2.c int addr = reg & 0xffff; reg 762 drivers/net/dsa/mv88e6xxx/global2.c int addr, int reg, u16 *val) reg 767 drivers/net/dsa/mv88e6xxx/global2.c if (reg & MII_ADDR_C45) reg 768 drivers/net/dsa/mv88e6xxx/global2.c return mv88e6xxx_g2_smi_phy_read_c45(chip, external, addr, reg, reg 771 drivers/net/dsa/mv88e6xxx/global2.c return mv88e6xxx_g2_smi_phy_read_data_c22(chip, external, addr, reg, reg 776 drivers/net/dsa/mv88e6xxx/global2.c int addr, int reg, u16 val) reg 781 drivers/net/dsa/mv88e6xxx/global2.c if (reg & MII_ADDR_C45) reg 782 drivers/net/dsa/mv88e6xxx/global2.c return mv88e6xxx_g2_smi_phy_write_c45(chip, external, addr, reg, reg 785 drivers/net/dsa/mv88e6xxx/global2.c return mv88e6xxx_g2_smi_phy_write_data_c22(chip, external, addr, reg, reg 792 drivers/net/dsa/mv88e6xxx/global2.c u16 reg; reg 794 drivers/net/dsa/mv88e6xxx/global2.c mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, ®); reg 796 drivers/net/dsa/mv88e6xxx/global2.c dev_info(chip->dev, "Watchdog event: 0x%04x", reg); reg 803 drivers/net/dsa/mv88e6xxx/global2.c u16 reg; reg 805 drivers/net/dsa/mv88e6xxx/global2.c mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, ®); reg 807 drivers/net/dsa/mv88e6xxx/global2.c reg &= ~(MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE | reg 810 drivers/net/dsa/mv88e6xxx/global2.c mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL, reg); reg 829 drivers/net/dsa/mv88e6xxx/global2.c u16 reg; reg 831 drivers/net/dsa/mv88e6xxx/global2.c mv88e6xxx_g2_read(chip, MV88E6250_G2_WDOG_CTL, ®); reg 833 drivers/net/dsa/mv88e6xxx/global2.c reg &= ~(MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE | reg 836 drivers/net/dsa/mv88e6xxx/global2.c mv88e6xxx_g2_write(chip, MV88E6250_G2_WDOG_CTL, reg); reg 867 drivers/net/dsa/mv88e6xxx/global2.c u16 reg; reg 871 drivers/net/dsa/mv88e6xxx/global2.c err = mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, ®); reg 874 drivers/net/dsa/mv88e6xxx/global2.c reg & MV88E6390_G2_WDOG_CTL_DATA_MASK); reg 878 drivers/net/dsa/mv88e6xxx/global2.c err = mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, ®); reg 881 drivers/net/dsa/mv88e6xxx/global2.c reg & MV88E6390_G2_WDOG_CTL_DATA_MASK); reg 1001 drivers/net/dsa/mv88e6xxx/global2.c u16 reg; reg 1004 drivers/net/dsa/mv88e6xxx/global2.c err = mv88e6xxx_g2_int_source(chip, ®); reg 1010 drivers/net/dsa/mv88e6xxx/global2.c if (reg & (1 << n)) { reg 296 drivers/net/dsa/mv88e6xxx/global2.h int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val); reg 297 drivers/net/dsa/mv88e6xxx/global2.h int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val); reg 298 drivers/net/dsa/mv88e6xxx/global2.h int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg, reg 306 drivers/net/dsa/mv88e6xxx/global2.h int addr, int reg, u16 *val); reg 309 drivers/net/dsa/mv88e6xxx/global2.h int addr, int reg, u16 val); reg 369 drivers/net/dsa/mv88e6xxx/global2.h static inline int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) reg 374 drivers/net/dsa/mv88e6xxx/global2.h static inline int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val) reg 380 drivers/net/dsa/mv88e6xxx/global2.h int reg, int bit, int val) reg 399 drivers/net/dsa/mv88e6xxx/global2.h int addr, int reg, u16 *val) reg 406 drivers/net/dsa/mv88e6xxx/global2.h int addr, int reg, u16 val) reg 15 drivers/net/dsa/mv88e6xxx/global2_scratch.c static int mv88e6xxx_g2_scratch_read(struct mv88e6xxx_chip *chip, int reg, reg 22 drivers/net/dsa/mv88e6xxx/global2_scratch.c reg << 8); reg 35 drivers/net/dsa/mv88e6xxx/global2_scratch.c static int mv88e6xxx_g2_scratch_write(struct mv88e6xxx_chip *chip, int reg, reg 38 drivers/net/dsa/mv88e6xxx/global2_scratch.c u16 value = (reg << 8) | data; reg 54 drivers/net/dsa/mv88e6xxx/global2_scratch.c int reg = base_reg + (offset / 8); reg 59 drivers/net/dsa/mv88e6xxx/global2_scratch.c err = mv88e6xxx_g2_scratch_read(chip, reg, &val); reg 80 drivers/net/dsa/mv88e6xxx/global2_scratch.c int reg = base_reg + (offset / 8); reg 85 drivers/net/dsa/mv88e6xxx/global2_scratch.c err = mv88e6xxx_g2_scratch_read(chip, reg, &val); reg 94 drivers/net/dsa/mv88e6xxx/global2_scratch.c return mv88e6xxx_g2_scratch_write(chip, reg, val); reg 130 drivers/net/dsa/mv88e6xxx/global2_scratch.c int reg; reg 132 drivers/net/dsa/mv88e6xxx/global2_scratch.c reg = MV88E6352_G2_SCRATCH_GPIO_DATA0 + offset; reg 139 drivers/net/dsa/mv88e6xxx/global2_scratch.c return mv88e6xxx_g2_scratch_write(chip, reg, chip->gpio_data[offset]); reg 191 drivers/net/dsa/mv88e6xxx/global2_scratch.c int reg = MV88E6352_G2_SCRATCH_GPIO_PCTL0 + (pin / 2); reg 197 drivers/net/dsa/mv88e6xxx/global2_scratch.c err = mv88e6xxx_g2_scratch_read(chip, reg, &val); reg 215 drivers/net/dsa/mv88e6xxx/global2_scratch.c int reg = MV88E6352_G2_SCRATCH_GPIO_PCTL0 + (pin / 2); reg 221 drivers/net/dsa/mv88e6xxx/global2_scratch.c err = mv88e6xxx_g2_scratch_read(chip, reg, &val); reg 227 drivers/net/dsa/mv88e6xxx/global2_scratch.c return mv88e6xxx_g2_scratch_write(chip, reg, val); reg 288 drivers/net/dsa/mv88e6xxx/hwtstamp.c struct sk_buff *skb, u16 reg, reg 306 drivers/net/dsa/mv88e6xxx/hwtstamp.c reg, buf, ARRAY_SIZE(buf)); reg 318 drivers/net/dsa/mv88e6xxx/hwtstamp.c err = mv88e6xxx_port_ptp_write(chip, ps->port_id, reg, 0); reg 17 drivers/net/dsa/mv88e6xxx/phy.c int addr, int reg, u16 *val) reg 19 drivers/net/dsa/mv88e6xxx/phy.c return mv88e6xxx_read(chip, addr, reg, val); reg 23 drivers/net/dsa/mv88e6xxx/phy.c int addr, int reg, u16 val) reg 25 drivers/net/dsa/mv88e6xxx/phy.c return mv88e6xxx_write(chip, addr, reg, val); reg 28 drivers/net/dsa/mv88e6xxx/phy.c int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy, int reg, u16 *val) reg 40 drivers/net/dsa/mv88e6xxx/phy.c return chip->info->ops->phy_read(chip, bus, addr, reg, val); reg 43 drivers/net/dsa/mv88e6xxx/phy.c int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, int reg, u16 val) reg 55 drivers/net/dsa/mv88e6xxx/phy.c return chip->info->ops->phy_write(chip, bus, addr, reg, val); reg 80 drivers/net/dsa/mv88e6xxx/phy.c u8 page, int reg, u16 *val) reg 85 drivers/net/dsa/mv88e6xxx/phy.c if (reg == MV88E6XXX_PHY_PAGE) reg 90 drivers/net/dsa/mv88e6xxx/phy.c err = mv88e6xxx_phy_read(chip, phy, reg, val); reg 98 drivers/net/dsa/mv88e6xxx/phy.c u8 page, int reg, u16 val) reg 103 drivers/net/dsa/mv88e6xxx/phy.c if (reg == MV88E6XXX_PHY_PAGE) reg 110 drivers/net/dsa/mv88e6xxx/phy.c err = mv88e6xxx_phy_write(chip, phy, reg, val); reg 204 drivers/net/dsa/mv88e6xxx/phy.c int addr, int reg, u16 *val) reg 210 drivers/net/dsa/mv88e6xxx/phy.c err = mv88e6xxx_read(chip, addr, reg, val); reg 218 drivers/net/dsa/mv88e6xxx/phy.c int addr, int reg, u16 val) reg 224 drivers/net/dsa/mv88e6xxx/phy.c err = mv88e6xxx_write(chip, addr, reg, val); reg 18 drivers/net/dsa/mv88e6xxx/phy.h int addr, int reg, u16 *val); reg 20 drivers/net/dsa/mv88e6xxx/phy.h int addr, int reg, u16 val); reg 22 drivers/net/dsa/mv88e6xxx/phy.h int addr, int reg, u16 *val); reg 24 drivers/net/dsa/mv88e6xxx/phy.h int addr, int reg, u16 val); reg 28 drivers/net/dsa/mv88e6xxx/phy.h int reg, u16 *val); reg 30 drivers/net/dsa/mv88e6xxx/phy.h int reg, u16 val); reg 32 drivers/net/dsa/mv88e6xxx/phy.h u8 page, int reg, u16 *val); reg 34 drivers/net/dsa/mv88e6xxx/phy.h u8 page, int reg, u16 val); reg 20 drivers/net/dsa/mv88e6xxx/port.c int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, reg 25 drivers/net/dsa/mv88e6xxx/port.c return mv88e6xxx_read(chip, addr, reg, val); reg 28 drivers/net/dsa/mv88e6xxx/port.c int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, reg 33 drivers/net/dsa/mv88e6xxx/port.c return mv88e6xxx_write(chip, addr, reg, val); reg 44 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 47 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); reg 52 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_STS_MY_PAUSE; reg 54 drivers/net/dsa/mv88e6xxx/port.c reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE; reg 56 drivers/net/dsa/mv88e6xxx/port.c return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); reg 71 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 74 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); reg 78 drivers/net/dsa/mv88e6xxx/port.c reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | reg 83 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK; reg 86 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK; reg 89 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK | reg 98 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); reg 103 drivers/net/dsa/mv88e6xxx/port.c reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no", reg 104 drivers/net/dsa/mv88e6xxx/port.c reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no"); reg 129 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 132 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); reg 136 drivers/net/dsa/mv88e6xxx/port.c reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | reg 141 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK; reg 144 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK | reg 154 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); reg 159 drivers/net/dsa/mv88e6xxx/port.c reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce", reg 160 drivers/net/dsa/mv88e6xxx/port.c reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down"); reg 167 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 170 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); reg 174 drivers/net/dsa/mv88e6xxx/port.c reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | reg 179 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX; reg 182 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX | reg 192 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); reg 197 drivers/net/dsa/mv88e6xxx/port.c reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce", reg 198 drivers/net/dsa/mv88e6xxx/port.c reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half"); reg 206 drivers/net/dsa/mv88e6xxx/port.c u16 reg, ctrl; reg 242 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®); reg 246 drivers/net/dsa/mv88e6xxx/port.c reg &= ~MV88E6XXX_PORT_MAC_CTL_SPEED_MASK; reg 248 drivers/net/dsa/mv88e6xxx/port.c reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED; reg 250 drivers/net/dsa/mv88e6xxx/port.c reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED; reg 254 drivers/net/dsa/mv88e6xxx/port.c reg |= ctrl; reg 256 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg); reg 400 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 450 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); reg 454 drivers/net/dsa/mv88e6xxx/port.c reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK; reg 455 drivers/net/dsa/mv88e6xxx/port.c reg |= cmode; reg 457 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg); reg 514 drivers/net/dsa/mv88e6xxx/port.c u16 reg, bits; reg 521 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®); reg 528 drivers/net/dsa/mv88e6xxx/port.c if ((reg & bits) == bits) reg 531 drivers/net/dsa/mv88e6xxx/port.c reg |= bits; reg 532 drivers/net/dsa/mv88e6xxx/port.c return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg); reg 564 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 566 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); reg 570 drivers/net/dsa/mv88e6xxx/port.c *cmode = reg & MV88E6185_PORT_STS_CMODE_MASK; reg 578 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 580 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); reg 584 drivers/net/dsa/mv88e6xxx/port.c *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK; reg 593 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 595 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); reg 600 drivers/net/dsa/mv88e6xxx/port.c switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) { reg 623 drivers/net/dsa/mv88e6xxx/port.c switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) { reg 647 drivers/net/dsa/mv88e6xxx/port.c state->link = !!(reg & MV88E6250_PORT_STS_LINK); reg 659 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 664 drivers/net/dsa/mv88e6xxx/port.c ®); reg 668 drivers/net/dsa/mv88e6xxx/port.c if ((reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK) && reg 669 drivers/net/dsa/mv88e6xxx/port.c (reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK)) reg 671 drivers/net/dsa/mv88e6xxx/port.c else if (reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK) reg 673 drivers/net/dsa/mv88e6xxx/port.c else if (reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK) reg 698 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); reg 702 drivers/net/dsa/mv88e6xxx/port.c switch (reg & MV88E6XXX_PORT_STS_SPEED_MASK) { reg 713 drivers/net/dsa/mv88e6xxx/port.c if ((reg & MV88E6XXX_PORT_STS_CMODE_MASK) == reg 721 drivers/net/dsa/mv88e6xxx/port.c state->duplex = reg & MV88E6XXX_PORT_STS_DUPLEX ? reg 723 drivers/net/dsa/mv88e6xxx/port.c state->link = !!(reg & MV88E6XXX_PORT_STS_LINK); reg 806 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 809 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); reg 813 drivers/net/dsa/mv88e6xxx/port.c reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK; reg 833 drivers/net/dsa/mv88e6xxx/port.c reg |= state; reg 835 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); reg 849 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 851 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); reg 855 drivers/net/dsa/mv88e6xxx/port.c reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK; reg 859 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED; reg 862 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED; reg 865 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED; reg 868 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA; reg 874 drivers/net/dsa/mv88e6xxx/port.c return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); reg 881 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 883 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); reg 887 drivers/net/dsa/mv88e6xxx/port.c reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; reg 891 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; reg 894 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; reg 900 drivers/net/dsa/mv88e6xxx/port.c return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); reg 907 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 909 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); reg 913 drivers/net/dsa/mv88e6xxx/port.c reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK; reg 917 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL; reg 920 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA; reg 923 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER; reg 926 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA; reg 932 drivers/net/dsa/mv88e6xxx/port.c return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); reg 939 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 941 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); reg 946 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; reg 948 drivers/net/dsa/mv88e6xxx/port.c reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN; reg 950 drivers/net/dsa/mv88e6xxx/port.c return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); reg 957 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 959 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®); reg 963 drivers/net/dsa/mv88e6xxx/port.c reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK; reg 966 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA; reg 968 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA; reg 970 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA; reg 972 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA; reg 974 drivers/net/dsa/mv88e6xxx/port.c return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); reg 1002 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 1005 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); reg 1009 drivers/net/dsa/mv88e6xxx/port.c reg &= ~mask; reg 1010 drivers/net/dsa/mv88e6xxx/port.c reg |= map & mask; reg 1012 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); reg 1024 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 1028 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); reg 1032 drivers/net/dsa/mv88e6xxx/port.c *fid = (reg & 0xf000) >> 12; reg 1037 drivers/net/dsa/mv88e6xxx/port.c ®); reg 1041 drivers/net/dsa/mv88e6xxx/port.c *fid |= (reg & upper_mask) << 4; reg 1050 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 1057 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®); reg 1061 drivers/net/dsa/mv88e6xxx/port.c reg &= 0x0fff; reg 1062 drivers/net/dsa/mv88e6xxx/port.c reg |= (fid & 0x000f) << 12; reg 1064 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg); reg 1071 drivers/net/dsa/mv88e6xxx/port.c ®); reg 1075 drivers/net/dsa/mv88e6xxx/port.c reg &= ~upper_mask; reg 1076 drivers/net/dsa/mv88e6xxx/port.c reg |= (fid >> 4) & upper_mask; reg 1079 drivers/net/dsa/mv88e6xxx/port.c reg); reg 1093 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 1097 drivers/net/dsa/mv88e6xxx/port.c ®); reg 1101 drivers/net/dsa/mv88e6xxx/port.c *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; reg 1108 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 1112 drivers/net/dsa/mv88e6xxx/port.c ®); reg 1116 drivers/net/dsa/mv88e6xxx/port.c reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK; reg 1117 drivers/net/dsa/mv88e6xxx/port.c reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK; reg 1120 drivers/net/dsa/mv88e6xxx/port.c reg); reg 1142 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 1144 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); reg 1149 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; reg 1151 drivers/net/dsa/mv88e6xxx/port.c reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD; reg 1153 drivers/net/dsa/mv88e6xxx/port.c return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); reg 1172 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 1174 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); reg 1178 drivers/net/dsa/mv88e6xxx/port.c reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK; reg 1179 drivers/net/dsa/mv88e6xxx/port.c reg |= upstream_port; reg 1181 drivers/net/dsa/mv88e6xxx/port.c return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); reg 1187 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 1190 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); reg 1194 drivers/net/dsa/mv88e6xxx/port.c reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; reg 1195 drivers/net/dsa/mv88e6xxx/port.c reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK; reg 1197 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); reg 1209 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 1212 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); reg 1216 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_CTL2_MAP_DA; reg 1218 drivers/net/dsa/mv88e6xxx/port.c return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); reg 1224 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 1227 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); reg 1231 drivers/net/dsa/mv88e6xxx/port.c reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK; reg 1234 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522; reg 1236 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048; reg 1238 drivers/net/dsa/mv88e6xxx/port.c reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240; reg 1242 drivers/net/dsa/mv88e6xxx/port.c return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); reg 1304 drivers/net/dsa/mv88e6xxx/port.c u16 reg; reg 1306 drivers/net/dsa/mv88e6xxx/port.c reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table | reg 1311 drivers/net/dsa/mv88e6xxx/port.c MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg); reg 1351 drivers/net/dsa/mv88e6xxx/port.c u16 reg, mask, val; reg 1409 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_POLICY_CTL, ®); reg 1413 drivers/net/dsa/mv88e6xxx/port.c reg &= ~mask; reg 1414 drivers/net/dsa/mv88e6xxx/port.c reg |= (val << shift) & mask; reg 1416 drivers/net/dsa/mv88e6xxx/port.c return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_POLICY_CTL, reg); reg 287 drivers/net/dsa/mv88e6xxx/port.h int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, reg 289 drivers/net/dsa/mv88e6xxx/port.h int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, reg 376 drivers/net/dsa/mv88e6xxx/port.h int port, int reg, u16 val); reg 379 drivers/net/dsa/mv88e6xxx/port.h int reg, u16 *val); reg 19 drivers/net/dsa/mv88e6xxx/port_hidden.c int port, int reg, u16 val) reg 33 drivers/net/dsa/mv88e6xxx/port_hidden.c reg; reg 48 drivers/net/dsa/mv88e6xxx/port_hidden.c int reg, u16 *val) reg 57 drivers/net/dsa/mv88e6xxx/port_hidden.c reg; reg 20 drivers/net/dsa/mv88e6xxx/serdes.c static int mv88e6352_serdes_read(struct mv88e6xxx_chip *chip, int reg, reg 25 drivers/net/dsa/mv88e6xxx/serdes.c reg, val); reg 28 drivers/net/dsa/mv88e6xxx/serdes.c static int mv88e6352_serdes_write(struct mv88e6xxx_chip *chip, int reg, reg 33 drivers/net/dsa/mv88e6xxx/serdes.c reg, val); reg 37 drivers/net/dsa/mv88e6xxx/serdes.c int lane, int device, int reg, u16 *val) reg 39 drivers/net/dsa/mv88e6xxx/serdes.c int reg_c45 = MII_ADDR_C45 | device << 16 | reg; reg 45 drivers/net/dsa/mv88e6xxx/serdes.c int lane, int device, int reg, u16 val) reg 47 drivers/net/dsa/mv88e6xxx/serdes.c int reg_c45 = MII_ADDR_C45 | device << 16 | reg; reg 97 drivers/net/dsa/mv88e6xxx/serdes.c int reg; reg 134 drivers/net/dsa/mv88e6xxx/serdes.c u16 reg; reg 137 drivers/net/dsa/mv88e6xxx/serdes.c err = mv88e6352_serdes_read(chip, stat->reg, ®); reg 143 drivers/net/dsa/mv88e6xxx/serdes.c val = reg; reg 146 drivers/net/dsa/mv88e6xxx/serdes.c err = mv88e6352_serdes_read(chip, stat->reg + 1, ®); reg 151 drivers/net/dsa/mv88e6xxx/serdes.c val = val << 16 | reg; reg 30 drivers/net/dsa/mv88e6xxx/smi.c int dev, int reg, u16 *data) reg 34 drivers/net/dsa/mv88e6xxx/smi.c ret = mdiobus_read_nested(chip->bus, dev, reg); reg 44 drivers/net/dsa/mv88e6xxx/smi.c int dev, int reg, u16 data) reg 48 drivers/net/dsa/mv88e6xxx/smi.c ret = mdiobus_write_nested(chip->bus, dev, reg, data); reg 56 drivers/net/dsa/mv88e6xxx/smi.c int dev, int reg, int bit, int val) reg 63 drivers/net/dsa/mv88e6xxx/smi.c err = mv88e6xxx_smi_direct_read(chip, dev, reg, &data); reg 82 drivers/net/dsa/mv88e6xxx/smi.c int dev, int reg, u16 *data) reg 84 drivers/net/dsa/mv88e6xxx/smi.c return mv88e6xxx_smi_direct_read(chip, chip->sw_addr + dev, reg, data); reg 88 drivers/net/dsa/mv88e6xxx/smi.c int dev, int reg, u16 data) reg 90 drivers/net/dsa/mv88e6xxx/smi.c return mv88e6xxx_smi_direct_write(chip, chip->sw_addr + dev, reg, data); reg 103 drivers/net/dsa/mv88e6xxx/smi.c int dev, int reg, u16 *data) reg 117 drivers/net/dsa/mv88e6xxx/smi.c (dev << 5) | reg); reg 131 drivers/net/dsa/mv88e6xxx/smi.c int dev, int reg, u16 data) reg 150 drivers/net/dsa/mv88e6xxx/smi.c (dev << 5) | reg); reg 38 drivers/net/dsa/mv88e6xxx/smi.h int dev, int reg, u16 *data) reg 41 drivers/net/dsa/mv88e6xxx/smi.h return chip->smi_ops->read(chip, dev, reg, data); reg 47 drivers/net/dsa/mv88e6xxx/smi.h int dev, int reg, u16 data) reg 50 drivers/net/dsa/mv88e6xxx/smi.h return chip->smi_ops->write(chip, dev, reg, data); reg 142 drivers/net/dsa/qca8k.c qca8k_read(struct qca8k_priv *priv, u32 reg) reg 147 drivers/net/dsa/qca8k.c qca8k_split_addr(reg, &r1, &r2, &page); reg 160 drivers/net/dsa/qca8k.c qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) reg 164 drivers/net/dsa/qca8k.c qca8k_split_addr(reg, &r1, &r2, &page); reg 175 drivers/net/dsa/qca8k.c qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val) reg 180 drivers/net/dsa/qca8k.c qca8k_split_addr(reg, &r1, &r2, &page); reg 196 drivers/net/dsa/qca8k.c qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val) reg 198 drivers/net/dsa/qca8k.c qca8k_rmw(priv, reg, 0, val); reg 202 drivers/net/dsa/qca8k.c qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val) reg 204 drivers/net/dsa/qca8k.c qca8k_rmw(priv, reg, val, 0); reg 208 drivers/net/dsa/qca8k.c qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val) reg 212 drivers/net/dsa/qca8k.c *val = qca8k_read(priv, reg); reg 218 drivers/net/dsa/qca8k.c qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val) reg 222 drivers/net/dsa/qca8k.c qca8k_write(priv, reg, val); reg 262 drivers/net/dsa/qca8k.c qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) reg 270 drivers/net/dsa/qca8k.c u32 val = qca8k_read(priv, reg); reg 284 drivers/net/dsa/qca8k.c u32 reg[4]; reg 289 drivers/net/dsa/qca8k.c reg[i] = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4)); reg 292 drivers/net/dsa/qca8k.c fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M; reg 294 drivers/net/dsa/qca8k.c fdb->aging = reg[2] & QCA8K_ATU_STATUS_M; reg 296 drivers/net/dsa/qca8k.c fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M; reg 298 drivers/net/dsa/qca8k.c fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff; reg 299 drivers/net/dsa/qca8k.c fdb->mac[1] = reg[1] & 0xff; reg 300 drivers/net/dsa/qca8k.c fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff; reg 301 drivers/net/dsa/qca8k.c fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff; reg 302 drivers/net/dsa/qca8k.c fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff; reg 303 drivers/net/dsa/qca8k.c fdb->mac[5] = reg[0] & 0xff; reg 310 drivers/net/dsa/qca8k.c u32 reg[3] = { 0 }; reg 314 drivers/net/dsa/qca8k.c reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S; reg 316 drivers/net/dsa/qca8k.c reg[2] |= aging & QCA8K_ATU_STATUS_M; reg 318 drivers/net/dsa/qca8k.c reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S; reg 320 drivers/net/dsa/qca8k.c reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S; reg 321 drivers/net/dsa/qca8k.c reg[1] |= mac[1]; reg 322 drivers/net/dsa/qca8k.c reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S; reg 323 drivers/net/dsa/qca8k.c reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S; reg 324 drivers/net/dsa/qca8k.c reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S; reg 325 drivers/net/dsa/qca8k.c reg[0] |= mac[5]; reg 329 drivers/net/dsa/qca8k.c qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]); reg 335 drivers/net/dsa/qca8k.c u32 reg; reg 338 drivers/net/dsa/qca8k.c reg = QCA8K_ATU_FUNC_BUSY; reg 339 drivers/net/dsa/qca8k.c reg |= cmd; reg 341 drivers/net/dsa/qca8k.c reg |= QCA8K_ATU_FUNC_PORT_EN; reg 342 drivers/net/dsa/qca8k.c reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S; reg 346 drivers/net/dsa/qca8k.c qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg); reg 354 drivers/net/dsa/qca8k.c reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC); reg 355 drivers/net/dsa/qca8k.c if (reg & QCA8K_ATU_FUNC_FULL) reg 424 drivers/net/dsa/qca8k.c u32 reg, val; reg 428 drivers/net/dsa/qca8k.c reg = QCA8K_REG_PORT0_PAD_CTRL; reg 431 drivers/net/dsa/qca8k.c reg = QCA8K_REG_PORT6_PAD_CTRL; reg 445 drivers/net/dsa/qca8k.c qca8k_write(priv, reg, val); reg 452 drivers/net/dsa/qca8k.c qca8k_write(priv, reg, reg 460 drivers/net/dsa/qca8k.c qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN); reg 576 drivers/net/dsa/qca8k.c u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg; reg 585 drivers/net/dsa/qca8k.c err = of_property_read_u32(port, "reg", ®); reg 592 drivers/net/dsa/qca8k.c if (!dsa_is_user_port(priv->ds, reg)) reg 596 drivers/net/dsa/qca8k.c external_mdio_mask |= BIT(reg); reg 598 drivers/net/dsa/qca8k.c internal_mdio_mask |= BIT(reg); reg 748 drivers/net/dsa/qca8k.c u32 reg; reg 757 drivers/net/dsa/qca8k.c reg = QCA8K_PORT_STATUS_SPEED_10; reg 760 drivers/net/dsa/qca8k.c reg = QCA8K_PORT_STATUS_SPEED_100; reg 763 drivers/net/dsa/qca8k.c reg = QCA8K_PORT_STATUS_SPEED_1000; reg 773 drivers/net/dsa/qca8k.c reg |= QCA8K_PORT_STATUS_DUPLEX; reg 777 drivers/net/dsa/qca8k.c reg |= QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_TXFLOW; reg 781 drivers/net/dsa/qca8k.c qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg); reg 804 drivers/net/dsa/qca8k.c u32 reg, i; reg 809 drivers/net/dsa/qca8k.c reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset; reg 811 drivers/net/dsa/qca8k.c data[i] = qca8k_read(priv, reg); reg 813 drivers/net/dsa/qca8k.c hi = qca8k_read(priv, reg + 4); reg 833 drivers/net/dsa/qca8k.c u32 reg; reg 836 drivers/net/dsa/qca8k.c reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL); reg 838 drivers/net/dsa/qca8k.c reg |= lpi_en; reg 840 drivers/net/dsa/qca8k.c reg &= ~lpi_en; reg 841 drivers/net/dsa/qca8k.c qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg); reg 304 drivers/net/dsa/realtek-smi-core.c static int realtek_smi_write(void *ctx, u32 reg, u32 val) reg 308 drivers/net/dsa/realtek-smi-core.c return realtek_smi_write_reg(smi, reg, val, true); reg 311 drivers/net/dsa/realtek-smi-core.c static int realtek_smi_read(void *ctx, u32 reg, u32 *val) reg 315 drivers/net/dsa/realtek-smi-core.c return realtek_smi_read_reg(smi, reg, val); reg 1297 drivers/net/dsa/rtl8366rb.c u32 reg; reg 1308 drivers/net/dsa/rtl8366rb.c reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum; reg 1310 drivers/net/dsa/rtl8366rb.c ret = regmap_write(smi->map, reg, 0); reg 1314 drivers/net/dsa/rtl8366rb.c phy, regnum, reg, ret); reg 1323 drivers/net/dsa/rtl8366rb.c phy, regnum, reg, val); reg 1331 drivers/net/dsa/rtl8366rb.c u32 reg; reg 1342 drivers/net/dsa/rtl8366rb.c reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum; reg 1345 drivers/net/dsa/rtl8366rb.c phy, regnum, reg, val); reg 1347 drivers/net/dsa/rtl8366rb.c ret = regmap_write(smi->map, reg, val); reg 376 drivers/net/dsa/vitesse-vsc73xx-core.c static int vsc73xx_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, reg 379 drivers/net/dsa/vitesse-vsc73xx-core.c return vsc->ops->read(vsc, block, subblock, reg, val); reg 382 drivers/net/dsa/vitesse-vsc73xx-core.c static int vsc73xx_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, reg 385 drivers/net/dsa/vitesse-vsc73xx-core.c return vsc->ops->write(vsc, block, subblock, reg, val); reg 389 drivers/net/dsa/vitesse-vsc73xx-core.c u8 reg, u32 mask, u32 val) reg 395 drivers/net/dsa/vitesse-vsc73xx-core.c ret = vsc73xx_read(vsc, block, subblock, reg, &orig); reg 400 drivers/net/dsa/vitesse-vsc73xx-core.c return vsc73xx_write(vsc, block, subblock, reg, tmp); reg 42 drivers/net/dsa/vitesse-vsc73xx-platform.c static u32 vsc73xx_make_addr(u8 block, u8 subblock, u8 reg) reg 50 drivers/net/dsa/vitesse-vsc73xx-platform.c ret |= reg << VSC73XX_CMD_PLATFORM_REGISTER_SHIFT; reg 56 drivers/net/dsa/vitesse-vsc73xx-platform.c u8 reg, u32 *val) reg 64 drivers/net/dsa/vitesse-vsc73xx-platform.c offset = vsc73xx_make_addr(block, subblock, reg); reg 74 drivers/net/dsa/vitesse-vsc73xx-platform.c u8 reg, u32 val) reg 82 drivers/net/dsa/vitesse-vsc73xx-platform.c offset = vsc73xx_make_addr(block, subblock, reg); reg 52 drivers/net/dsa/vitesse-vsc73xx-spi.c static int vsc73xx_spi_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, reg 78 drivers/net/dsa/vitesse-vsc73xx-spi.c cmd[1] = reg; reg 94 drivers/net/dsa/vitesse-vsc73xx-spi.c static int vsc73xx_spi_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, reg 120 drivers/net/dsa/vitesse-vsc73xx-spi.c cmd[1] = reg; reg 21 drivers/net/dsa/vitesse-vsc73xx.h int (*read)(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, reg 23 drivers/net/dsa/vitesse-vsc73xx.h int (*write)(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, reg 1217 drivers/net/ethernet/3com/3c515.c int win, reg; reg 1223 drivers/net/ethernet/3com/3c515.c for (reg = 0; reg < 16; reg++) reg 1224 drivers/net/ethernet/3com/3c515.c pr_cont(" %2.2x", inb(ioaddr + reg)); reg 608 drivers/net/ethernet/8390/ax88796.c u8 reg = ei_inb(ei_local->mem + AX_MEMR); reg 610 drivers/net/ethernet/8390/ax88796.c eeprom->reg_data_in = reg & AX_MEMR_EEI; reg 611 drivers/net/ethernet/8390/ax88796.c eeprom->reg_data_out = reg & AX_MEMR_EEO; /* Input pin */ reg 612 drivers/net/ethernet/8390/ax88796.c eeprom->reg_data_clock = reg & AX_MEMR_EECLK; reg 613 drivers/net/ethernet/8390/ax88796.c eeprom->reg_chip_select = reg & AX_MEMR_EECS; reg 619 drivers/net/ethernet/8390/ax88796.c u8 reg = ei_inb(ei_local->mem + AX_MEMR); reg 621 drivers/net/ethernet/8390/ax88796.c reg &= ~(AX_MEMR_EEI | AX_MEMR_EECLK | AX_MEMR_EECS); reg 624 drivers/net/ethernet/8390/ax88796.c reg |= AX_MEMR_EEI; reg 626 drivers/net/ethernet/8390/ax88796.c reg |= AX_MEMR_EECLK; reg 628 drivers/net/ethernet/8390/ax88796.c reg |= AX_MEMR_EECS; reg 630 drivers/net/ethernet/8390/ax88796.c ei_outb(reg, ei_local->mem + AX_MEMR); reg 88 drivers/net/ethernet/8390/stnic.c STNIC_READ (int reg) reg 92 drivers/net/ethernet/8390/stnic.c val = (*(vhalf *) (PA_83902 + ((reg) << 1)) >> 8) & 0xff; reg 98 drivers/net/ethernet/8390/stnic.c STNIC_WRITE (int reg, byte val) reg 100 drivers/net/ethernet/8390/stnic.c *(vhalf *) (PA_83902 + ((reg) << 1)) = ((half) (val) << 8); reg 255 drivers/net/ethernet/8390/xsurf100.c int reg; reg 281 drivers/net/ethernet/8390/xsurf100.c for (reg = 0; reg < 0x20; reg++) reg 282 drivers/net/ethernet/8390/xsurf100.c reg_offsets[reg] = 4 * reg; reg 1162 drivers/net/ethernet/aeroflex/greth.c static int greth_mdio_read(struct mii_bus *bus, int phy, int reg) reg 1170 drivers/net/ethernet/aeroflex/greth.c GRETH_REGSAVE(greth->regs->mdio, ((phy & 0x1F) << 11) | ((reg & 0x1F) << 6) | 2); reg 1184 drivers/net/ethernet/aeroflex/greth.c static int greth_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) reg 1192 drivers/net/ethernet/aeroflex/greth.c ((val & 0xFFFF) << 16) | ((phy & 0x1F) << 11) | ((reg & 0x1F) << 6) | 1); reg 499 drivers/net/ethernet/agere/et131x.c u32 reg; reg 508 drivers/net/ethernet/agere/et131x.c if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, ®)) reg 512 drivers/net/ethernet/agere/et131x.c if ((reg & 0x3000) == 0x3000) { reg 514 drivers/net/ethernet/agere/et131x.c *status = reg; reg 515 drivers/net/ethernet/agere/et131x.c return reg & 0xFF; reg 1158 drivers/net/ethernet/agere/et131x.c u32 __iomem *reg; reg 1161 drivers/net/ethernet/agere/et131x.c for (reg = &macstat->txrx_0_64_byte_frames; reg 1162 drivers/net/ethernet/agere/et131x.c reg <= &macstat->carry_reg2; reg++) reg 1163 drivers/net/ethernet/agere/et131x.c writel(0, reg); reg 1174 drivers/net/ethernet/agere/et131x.c u8 reg, u16 *value) reg 1193 drivers/net/ethernet/agere/et131x.c writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr); reg 1206 drivers/net/ethernet/agere/et131x.c "reg 0x%08x could not be read\n", reg); reg 1232 drivers/net/ethernet/agere/et131x.c static int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value) reg 1239 drivers/net/ethernet/agere/et131x.c return et131x_phy_mii_read(adapter, phydev->mdio.addr, reg, value); reg 1242 drivers/net/ethernet/agere/et131x.c static int et131x_mii_write(struct et131x_adapter *adapter, u8 addr, u8 reg, reg 1262 drivers/net/ethernet/agere/et131x.c writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr); reg 1278 drivers/net/ethernet/agere/et131x.c "reg 0x%08x could not be written", reg); reg 1284 drivers/net/ethernet/agere/et131x.c et131x_mii_read(adapter, reg, &tmp); reg 1305 drivers/net/ethernet/agere/et131x.c u16 reg; reg 1308 drivers/net/ethernet/agere/et131x.c et131x_mii_read(adapter, regnum, ®); reg 1310 drivers/net/ethernet/agere/et131x.c *value = (reg & mask) >> bitnum; reg 1424 drivers/net/ethernet/agere/et131x.c static int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg) reg 1431 drivers/net/ethernet/agere/et131x.c ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value); reg 1440 drivers/net/ethernet/agere/et131x.c int reg, u16 value) reg 1445 drivers/net/ethernet/agere/et131x.c return et131x_mii_write(adapter, phy_addr, reg, value); reg 1687 drivers/net/ethernet/agere/et131x.c u32 reg; reg 1690 drivers/net/ethernet/agere/et131x.c reg = ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET | reg 1693 drivers/net/ethernet/agere/et131x.c writel(reg, &adapter->regs->mac.cfg1); reg 1695 drivers/net/ethernet/agere/et131x.c reg = ET_RESET_ALL; reg 1696 drivers/net/ethernet/agere/et131x.c writel(reg, &adapter->regs->global.sw_reset); reg 1698 drivers/net/ethernet/agere/et131x.c reg = ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC | reg 1700 drivers/net/ethernet/agere/et131x.c writel(reg, &adapter->regs->mac.cfg1); reg 3195 drivers/net/ethernet/agere/et131x.c u16 reg; reg 3197 drivers/net/ethernet/agere/et131x.c et131x_mii_read(adapter, PHY_CONFIG, ®); reg 3198 drivers/net/ethernet/agere/et131x.c reg &= ~ET_PHY_CONFIG_TX_FIFO_DEPTH; reg 3199 drivers/net/ethernet/agere/et131x.c reg |= ET_PHY_CONFIG_FIFO_DEPTH_32; reg 3201 drivers/net/ethernet/agere/et131x.c PHY_CONFIG, reg); reg 958 drivers/net/ethernet/agere/et131x.h #define ET_MAC_MII_ADDR(phy, reg) ((phy) << 8 | (reg)) reg 559 drivers/net/ethernet/alacritech/slic.h static inline u32 slic_read(struct slic_device *sdev, unsigned int reg) reg 561 drivers/net/ethernet/alacritech/slic.h return ioread32(sdev->regs + reg); reg 564 drivers/net/ethernet/alacritech/slic.h static inline void slic_write(struct slic_device *sdev, unsigned int reg, reg 567 drivers/net/ethernet/alacritech/slic.h iowrite32(val, sdev->regs + reg); reg 142 drivers/net/ethernet/alacritech/slicoss.c u32 reg; reg 144 drivers/net/ethernet/alacritech/slicoss.c reg = (upr->type == SLIC_UPR_CONFIG) ? SLIC_REG_RCONFIG : reg 146 drivers/net/ethernet/alacritech/slicoss.c slic_write(sdev, reg, lower_32_bits(upr->paddr)); reg 200 drivers/net/ethernet/allwinner/sun4i-emac.c static void emac_outblk_32bit(void __iomem *reg, void *data, int count) reg 202 drivers/net/ethernet/allwinner/sun4i-emac.c writesl(reg, data, round_up(count, 4) / 4); reg 205 drivers/net/ethernet/allwinner/sun4i-emac.c static void emac_inblk_32bit(void __iomem *reg, void *data, int count) reg 207 drivers/net/ethernet/allwinner/sun4i-emac.c readsl(reg, data, round_up(count, 4) / 4); reg 47 drivers/net/ethernet/amd/am79c961a.c static void write_rreg(u_long base, u_int reg, u_int val) reg 53 drivers/net/ethernet/amd/am79c961a.c : "r" (val), "r" (reg), "r" (ISAIO_BASE + 0x0464)); reg 56 drivers/net/ethernet/amd/am79c961a.c static inline unsigned short read_rreg(u_long base_addr, u_int reg) reg 63 drivers/net/ethernet/amd/am79c961a.c : "r" (reg), "r" (ISAIO_BASE + 0x0464)); reg 67 drivers/net/ethernet/amd/am79c961a.c static inline void write_ireg(u_long base, u_int reg, u_int val) reg 73 drivers/net/ethernet/amd/am79c961a.c : "r" (val), "r" (reg), "r" (ISAIO_BASE + 0x0464)); reg 76 drivers/net/ethernet/amd/am79c961a.c static inline unsigned short read_ireg(u_long base_addr, u_int reg) reg 83 drivers/net/ethernet/amd/am79c961a.c : "r" (reg), "r" (ISAIO_BASE + 0x0464)); reg 100 drivers/net/ethernet/amd/amd8111e.c int phy_id, int reg, u32 *val) reg 111 drivers/net/ethernet/amd/amd8111e.c ((reg & 0x1f) << 16), mmio +PHY_ACCESS); reg 129 drivers/net/ethernet/amd/amd8111e.c int phy_id, int reg, u32 val) reg 140 drivers/net/ethernet/amd/amd8111e.c ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS); reg 272 drivers/net/ethernet/amd/au1000_eth.c static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg) reg 288 drivers/net/ethernet/amd/au1000_eth.c mii_control = MAC_SET_MII_SELECT_REG(reg) | reg 305 drivers/net/ethernet/amd/au1000_eth.c int reg, u16 value) reg 321 drivers/net/ethernet/amd/au1000_eth.c mii_control = MAC_SET_MII_SELECT_REG(reg) | reg 369 drivers/net/ethernet/amd/au1000_eth.c u32 reg; reg 373 drivers/net/ethernet/amd/au1000_eth.c reg = readl(&aup->mac->control); reg 374 drivers/net/ethernet/amd/au1000_eth.c reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE); reg 375 drivers/net/ethernet/amd/au1000_eth.c writel(reg, &aup->mac->control); reg 383 drivers/net/ethernet/amd/au1000_eth.c u32 reg; reg 387 drivers/net/ethernet/amd/au1000_eth.c reg = readl(&aup->mac->control); reg 388 drivers/net/ethernet/amd/au1000_eth.c reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE); reg 389 drivers/net/ethernet/amd/au1000_eth.c writel(reg, &aup->mac->control); reg 400 drivers/net/ethernet/amd/au1000_eth.c u32 reg; reg 432 drivers/net/ethernet/amd/au1000_eth.c reg = readl(&aup->mac->control); reg 434 drivers/net/ethernet/amd/au1000_eth.c reg |= MAC_FULL_DUPLEX; reg 435 drivers/net/ethernet/amd/au1000_eth.c reg &= ~MAC_DISABLE_RX_OWN; reg 437 drivers/net/ethernet/amd/au1000_eth.c reg &= ~MAC_FULL_DUPLEX; reg 438 drivers/net/ethernet/amd/au1000_eth.c reg |= MAC_DISABLE_RX_OWN; reg 440 drivers/net/ethernet/amd/au1000_eth.c writel(reg, &aup->mac->control); reg 1029 drivers/net/ethernet/amd/au1000_eth.c u32 reg; reg 1032 drivers/net/ethernet/amd/au1000_eth.c reg = readl(&aup->mac->control); reg 1034 drivers/net/ethernet/amd/au1000_eth.c reg |= MAC_PROMISCUOUS; reg 1037 drivers/net/ethernet/amd/au1000_eth.c reg |= MAC_PASS_ALL_MULTI; reg 1038 drivers/net/ethernet/amd/au1000_eth.c reg &= ~MAC_PROMISCUOUS; reg 1050 drivers/net/ethernet/amd/au1000_eth.c reg &= ~MAC_PROMISCUOUS; reg 1051 drivers/net/ethernet/amd/au1000_eth.c reg |= MAC_HASH_MODE; reg 1053 drivers/net/ethernet/amd/au1000_eth.c writel(reg, &aup->mac->control); reg 159 drivers/net/ethernet/amd/ni65.c #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);inw(PORT+L_ADDRREG); \ reg 161 drivers/net/ethernet/amd/ni65.c #define readreg(reg) (outw(reg,PORT+L_ADDRREG),inw(PORT+L_ADDRREG),\ reg 169 drivers/net/ethernet/amd/ni65.c #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);outw(val,PORT+L_DATAREG);} reg 170 drivers/net/ethernet/amd/ni65.c #define readreg(reg) (outw(reg,PORT+L_ADDRREG),inw(PORT+L_DATAREG)) reg 484 drivers/net/ethernet/amd/nmclan_cs.c static int mace_read(mace_private *lp, unsigned int ioaddr, int reg) reg 489 drivers/net/ethernet/amd/nmclan_cs.c switch (reg >> 4) { reg 491 drivers/net/ethernet/amd/nmclan_cs.c data = inb(ioaddr + AM2150_MACE_BASE + reg); reg 496 drivers/net/ethernet/amd/nmclan_cs.c data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F)); reg 511 drivers/net/ethernet/amd/nmclan_cs.c static void mace_write(mace_private *lp, unsigned int ioaddr, int reg, reg 516 drivers/net/ethernet/amd/nmclan_cs.c switch (reg >> 4) { reg 518 drivers/net/ethernet/amd/nmclan_cs.c outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg); reg 523 drivers/net/ethernet/amd/nmclan_cs.c outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F)); reg 530 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int reg, reg_val; reg 540 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg = MAC_Q0TFCR; reg 542 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val = XGMAC_IOREAD(pdata, reg); reg 544 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_IOWRITE(pdata, reg, reg_val); reg 546 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg += MAC_QTFCR_INC; reg 557 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int reg, reg_val; reg 584 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg = MAC_Q0TFCR; reg 586 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val = XGMAC_IOREAD(pdata, reg); reg 593 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_IOWRITE(pdata, reg, reg_val); reg 595 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg += MAC_QTFCR_INC; reg 1115 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int reg; reg 1120 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); reg 1122 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg &= ~(1 << (gpio + 16)); reg 1123 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); reg 1130 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int reg; reg 1135 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); reg 1137 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg |= (1 << (gpio + 16)); reg 1138 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); reg 1287 drivers/net/ethernet/amd/xgbe/xgbe-dev.c static unsigned int xgbe_create_mdio_sca(int port, int reg) reg 1291 drivers/net/ethernet/amd/xgbe/xgbe-dev.c da = (reg & MII_ADDR_C45) ? reg >> 16 : 0; reg 1294 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg); reg 1302 drivers/net/ethernet/amd/xgbe/xgbe-dev.c int reg, u16 val) reg 1308 drivers/net/ethernet/amd/xgbe/xgbe-dev.c mdio_sca = xgbe_create_mdio_sca(addr, reg); reg 1326 drivers/net/ethernet/amd/xgbe/xgbe-dev.c int reg) reg 1332 drivers/net/ethernet/amd/xgbe/xgbe-dev.c mdio_sca = xgbe_create_mdio_sca(addr, reg); reg 2606 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int i, j, reg, reg_val; reg 2637 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg = MAC_RQC2R; reg 2660 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_IOWRITE(pdata, reg, reg_val); reg 2661 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg += MAC_RQC2_INC; reg 2666 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg = MTL_RQDCM0R; reg 2674 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_IOWRITE(pdata, reg, reg_val); reg 2676 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg += MTL_RQDCM_INC; reg 2715 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int mask, reg, reg_val; reg 2743 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg = MTL_TCPM0R + (MTL_TCPM_INC * (i / MTL_TCPM_TC_PER_REG)); reg 2744 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val = XGMAC_IOREAD(pdata, reg); reg 2749 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_IOWRITE(pdata, reg, reg_val); reg 334 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c unsigned int reg; reg 336 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c reg = XI2C_IOREAD(pdata, IC_CON); reg 337 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c XI2C_SET_BITS(reg, IC_CON, MASTER_MODE, 1); reg 338 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c XI2C_SET_BITS(reg, IC_CON, SLAVE_DISABLE, 1); reg 339 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c XI2C_SET_BITS(reg, IC_CON, RESTART_EN, 1); reg 340 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c XI2C_SET_BITS(reg, IC_CON, SPEED, XGBE_STD_SPEED); reg 341 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c XI2C_SET_BITS(reg, IC_CON, RX_FIFO_FULL_HOLD, 1); reg 342 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c XI2C_IOWRITE(pdata, IC_CON, reg); reg 348 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c unsigned int reg; reg 350 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c reg = XI2C_IOREAD(pdata, IC_COMP_PARAM_1); reg 351 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c i2c->max_speed_mode = XI2C_GET_BITS(reg, IC_COMP_PARAM_1, reg 353 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c i2c->rx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1, reg 355 drivers/net/ethernet/amd/xgbe/xgbe-i2c.c i2c->tx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1, reg 149 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c int reg; reg 151 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); reg 152 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~XGBE_AN_CL37_INT_MASK; reg 153 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); reg 158 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c int reg; reg 160 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); reg 161 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~XGBE_AN_CL37_INT_MASK; reg 162 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); reg 164 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL); reg 165 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~XGBE_PCS_CL37_BP; reg 166 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg); reg 171 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c int reg; reg 173 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL); reg 174 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= XGBE_PCS_CL37_BP; reg 175 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg); reg 177 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); reg 178 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= XGBE_AN_CL37_INT_MASK; reg 179 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); reg 354 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c unsigned int reg; reg 356 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1); reg 357 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE; reg 360 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= MDIO_VEND2_CTRL1_AN_ENABLE; reg 363 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= MDIO_VEND2_CTRL1_AN_RESTART; reg 365 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg); reg 387 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c unsigned int reg; reg 390 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); reg 391 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~XGBE_KR_TRAINING_ENABLE; reg 392 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); reg 395 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); reg 396 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~MDIO_AN_CTRL1_ENABLE; reg 399 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= MDIO_AN_CTRL1_ENABLE; reg 402 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= MDIO_AN_CTRL1_RESTART; reg 404 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); reg 472 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c unsigned int ad_reg, lp_reg, reg; reg 484 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL); reg 485 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE); reg 487 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= pdata->fec_ability; reg 489 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg); reg 495 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); reg 496 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= XGBE_KR_TRAINING_ENABLE; reg 497 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= XGBE_KR_TRAINING_START; reg 498 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg); reg 530 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c unsigned int reg, ad_reg, lp_reg; reg 533 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); reg 537 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c if (!(reg & link_support)) reg 642 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c unsigned int reg; reg 648 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); reg 649 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c pdata->an_int = reg & XGBE_AN_CL37_INT_MASK; reg 650 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK; reg 654 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~XGBE_AN_CL37_INT_MASK; reg 655 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); reg 947 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c unsigned int reg; reg 952 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); reg 954 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= 0x100; reg 956 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~0x100; reg 959 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= 0x80; reg 961 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~0x80; reg 964 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= XGBE_AN_CL37_FD_MASK; reg 965 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~XGBE_AN_CL37_HD_MASK; reg 967 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg); reg 970 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); reg 971 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK; reg 972 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~XGBE_AN_CL37_PCS_MODE_MASK; reg 976 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= XGBE_AN_CL37_PCS_MODE_BASEX; reg 979 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= XGBE_AN_CL37_PCS_MODE_SGMII; reg 985 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= XGBE_AN_CL37_MII_CTRL_8BIT; reg 987 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); reg 996 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c unsigned int reg; reg 1001 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); reg 1003 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= 0xc000; reg 1005 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~0xc000; reg 1007 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg); reg 1010 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); reg 1012 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= 0x80; reg 1014 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~0x80; reg 1018 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= 0x20; reg 1020 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~0x20; reg 1022 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg); reg 1025 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); reg 1027 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= 0x400; reg 1029 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~0x400; reg 1032 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg |= 0x800; reg 1034 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~0x800; reg 1037 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c reg &= ~XGBE_XNP_NP_EXCHANGE; reg 1039 drivers/net/ethernet/amd/xgbe/xgbe-mdio.c XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); reg 215 drivers/net/ethernet/amd/xgbe/xgbe-pci.c unsigned int reg; reg 288 drivers/net/ethernet/amd/xgbe/xgbe-pci.c reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg); reg 289 drivers/net/ethernet/amd/xgbe/xgbe-pci.c pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); reg 291 drivers/net/ethernet/amd/xgbe/xgbe-pci.c pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); reg 320 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c unsigned int reg; reg 322 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); reg 324 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg |= MDIO_CTRL1_LPOWER; reg 325 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); reg 329 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg &= ~MDIO_CTRL1_LPOWER; reg 330 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); reg 370 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c unsigned int reg; reg 373 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); reg 374 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg &= ~MDIO_PCS_CTRL2_TYPE; reg 375 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg |= MDIO_PCS_CTRL2_10GBR; reg 376 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); reg 378 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); reg 379 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg &= ~MDIO_CTRL1_SPEEDSEL; reg 380 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg |= MDIO_CTRL1_SPEED10G; reg 381 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); reg 413 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c unsigned int reg; reg 416 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); reg 417 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg &= ~MDIO_PCS_CTRL2_TYPE; reg 418 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg |= MDIO_PCS_CTRL2_10GBX; reg 419 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); reg 421 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); reg 422 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg &= ~MDIO_CTRL1_SPEEDSEL; reg 423 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg |= MDIO_CTRL1_SPEED1G; reg 424 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); reg 456 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c unsigned int reg; reg 459 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); reg 460 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg &= ~MDIO_PCS_CTRL2_TYPE; reg 461 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg |= MDIO_PCS_CTRL2_10GBX; reg 462 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); reg 464 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); reg 465 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg &= ~MDIO_CTRL1_SPEEDSEL; reg 466 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg |= MDIO_CTRL1_SPEED1G; reg 467 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); reg 500 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c unsigned int reg; reg 502 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); reg 503 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg &= MDIO_PCS_CTRL2_TYPE; reg 505 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c if (reg == MDIO_PCS_CTRL2_10GBR) { reg 628 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c unsigned int reg; reg 635 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); reg 636 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); reg 638 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c return (reg & MDIO_STAT1_LSTATUS) ? 1 : 0; reg 654 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c unsigned int reg, count; reg 657 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); reg 658 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg |= MDIO_CTRL1_RESET; reg 659 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); reg 664 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); reg 665 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c } while ((reg & MDIO_CTRL1_RESET) && --count); reg 667 drivers/net/ethernet/amd/xgbe/xgbe-phy-v1.c if (reg & MDIO_CTRL1_RESET) reg 395 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg, reg 406 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c redrv_data[0] = ((reg >> 8) & 0xff) << 1; reg 407 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c redrv_data[1] = reg & 0xff; reg 478 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c void *reg, unsigned int reg_len, reg 490 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c i2c_op.buf = reg; reg 601 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c int reg, u16 val) reg 605 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c if (reg & MII_ADDR_C45) { reg 613 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val); reg 616 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val) reg 626 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c mii_data[0] = reg & 0xff; reg 638 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val) reg 649 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c ret = xgbe_phy_i2c_mii_write(pdata, reg, val); reg 651 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val); reg 661 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c int reg) reg 665 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c if (reg & MII_ADDR_C45) { reg 673 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg); reg 676 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg) reg 686 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c mii_reg = reg; reg 698 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg) reg 709 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c ret = xgbe_phy_i2c_mii_read(pdata, reg); reg 711 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c ret = xgbe_phy_mdio_mii_read(pdata, addr, reg); reg 905 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c int reg; reg 926 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c reg = phy_read(phy_data->phydev, 0x18); reg 927 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c phy_write(phy_data->phydev, 0x18, reg & ~0x0080); reg 931 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c reg = phy_read(phy_data->phydev, 0x1c); reg 932 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c reg &= 0x03ff; reg 933 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c reg &= ~0x0001; reg 934 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001); reg 937 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c reg = phy_read(phy_data->phydev, 0x00); reg 938 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c phy_write(phy_data->phydev, 0x00, reg | 0x00800); reg 942 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c reg = phy_read(phy_data->phydev, 0x1c); reg 943 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c reg &= 0x03ff; reg 944 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c reg &= ~0x0006; reg 945 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004); reg 948 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c reg = phy_read(phy_data->phydev, 0x00); reg 949 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c phy_write(phy_data->phydev, 0x00, reg & ~0x00800); reg 953 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c reg = phy_read(phy_data->phydev, 0x1c); reg 954 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c reg &= 0x03ff; reg 955 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c reg &= ~0x0001; reg 956 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg); reg 959 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c reg = phy_read(phy_data->phydev, 0x00); reg 960 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c phy_write(phy_data->phydev, 0x00, reg & ~0x00800); reg 2538 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c unsigned int reg; reg 2573 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); reg 2574 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); reg 2575 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c if (reg & MDIO_STAT1_LSTATUS) reg 12 drivers/net/ethernet/apm/xgene-v2/mdio.c static int xge_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 data) reg 19 drivers/net/ethernet/apm/xgene-v2/mdio.c SET_REG_BITS(&val, REG_ADDR, reg); reg 36 drivers/net/ethernet/apm/xgene-v2/mdio.c static int xge_mdio_read(struct mii_bus *bus, int phy_id, int reg) reg 43 drivers/net/ethernet/apm/xgene-v2/mdio.c SET_REG_BITS(&val, REG_ADDR, reg); reg 15 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c u32 *reg) reg 17 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c *reg = SET_VAL(SB_IPFRAG, frag) | reg 648 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c u32 sband, reg = 0; reg 655 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c xgene_cle_sband_to_hw(0, XGENE_CLE_IPV4, XGENE_CLE_TCP, hdr_len, ®); reg 656 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c sband = reg; reg 660 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c xgene_cle_sband_to_hw(1, XGENE_CLE_IPV4, XGENE_CLE_UDP, hdr_len, ®); reg 661 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c sband |= (reg << 16); reg 670 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c hdr_len, ®); reg 671 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c sband = reg; reg 676 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c hdr_len, ®); reg 677 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c sband |= (reg << 16); reg 114 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c u32 reg, u16 data) reg 119 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c addr = PHY_ADDR(phy_id) | REG_ADDR(reg); reg 135 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c static u32 xgene_mii_phy_read(struct xgene_enet_pdata *p, u8 phy_id, u32 reg) reg 140 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c addr = PHY_ADDR(phy_id) | REG_ADDR(reg); reg 36 drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg) reg 38 drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c u32 value = readl(hw->mmio + reg); reg 48 drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value) reg 50 drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c writel(value, hw->mmio + reg); reg 57 drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c u64 aq_hw_read_reg64(struct aq_hw_s *hw, u32 reg) reg 59 drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c u64 value = aq_hw_read_reg(hw, reg); reg 61 drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c value |= (u64)aq_hw_read_reg(hw, reg + 4) << 32; reg 33 drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg); reg 34 drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h void aq_hw_write_reg(struct aq_hw_s *hw, u32 reg, u32 value); reg 35 drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h u64 aq_hw_read_reg64(struct aq_hw_s *hw, u32 reg); reg 172 drivers/net/ethernet/arc/emac.h static inline void arc_reg_set(struct arc_emac_priv *priv, int reg, int value) reg 174 drivers/net/ethernet/arc/emac.h iowrite32(value, priv->regs + reg * sizeof(int)); reg 184 drivers/net/ethernet/arc/emac.h static inline unsigned int arc_reg_get(struct arc_emac_priv *priv, int reg) reg 186 drivers/net/ethernet/arc/emac.h return ioread32(priv->regs + reg * sizeof(int)); reg 198 drivers/net/ethernet/arc/emac.h static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask) reg 200 drivers/net/ethernet/arc/emac.h unsigned int value = arc_reg_get(priv, reg); reg 202 drivers/net/ethernet/arc/emac.h arc_reg_set(priv, reg, value | mask); reg 214 drivers/net/ethernet/arc/emac.h static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask) reg 216 drivers/net/ethernet/arc/emac.h unsigned int value = arc_reg_get(priv, reg); reg 218 drivers/net/ethernet/arc/emac.h arc_reg_set(priv, reg, value & ~mask); reg 50 drivers/net/ethernet/arc/emac_main.c unsigned int reg, state_changed = 0; reg 65 drivers/net/ethernet/arc/emac_main.c reg = arc_reg_get(priv, R_CTRL); reg 68 drivers/net/ethernet/arc/emac_main.c reg |= ENFL_MASK; reg 70 drivers/net/ethernet/arc/emac_main.c reg &= ~ENFL_MASK; reg 72 drivers/net/ethernet/arc/emac_main.c arc_reg_set(priv, R_CTRL, reg); reg 352 drivers/net/ethernet/atheros/ag71xx.c static void ag71xx_wr(struct ag71xx *ag, unsigned int reg, u32 value) reg 354 drivers/net/ethernet/atheros/ag71xx.c iowrite32(value, ag->mac_base + reg); reg 356 drivers/net/ethernet/atheros/ag71xx.c (void)ioread32(ag->mac_base + reg); reg 359 drivers/net/ethernet/atheros/ag71xx.c static u32 ag71xx_rr(struct ag71xx *ag, unsigned int reg) reg 361 drivers/net/ethernet/atheros/ag71xx.c return ioread32(ag->mac_base + reg); reg 364 drivers/net/ethernet/atheros/ag71xx.c static void ag71xx_sb(struct ag71xx *ag, unsigned int reg, u32 mask) reg 368 drivers/net/ethernet/atheros/ag71xx.c r = ag->mac_base + reg; reg 374 drivers/net/ethernet/atheros/ag71xx.c static void ag71xx_cb(struct ag71xx *ag, unsigned int reg, u32 mask) reg 378 drivers/net/ethernet/atheros/ag71xx.c r = ag->mac_base + reg; reg 416 drivers/net/ethernet/atheros/ag71xx.c static int ag71xx_mdio_mii_read(struct mii_bus *bus, int addr, int reg) reg 426 drivers/net/ethernet/atheros/ag71xx.c ((addr & 0x1f) << MII_ADDR_SHIFT) | (reg & 0xff)); reg 439 drivers/net/ethernet/atheros/ag71xx.c addr, reg, val); reg 444 drivers/net/ethernet/atheros/ag71xx.c static int ag71xx_mdio_mii_write(struct mii_bus *bus, int addr, int reg, reg 450 drivers/net/ethernet/atheros/ag71xx.c addr, reg, val); reg 453 drivers/net/ethernet/atheros/ag71xx.c ((addr & 0x1f) << MII_ADDR_SHIFT) | (reg & 0xff)); reg 62 drivers/net/ethernet/atheros/alx/hw.c u16 reg, u16 *phy_data) reg 76 drivers/net/ethernet/atheros/alx/hw.c reg << ALX_MDIO_EXTN_REG_SHIFT; reg 85 drivers/net/ethernet/atheros/alx/hw.c reg << ALX_MDIO_REG_SHIFT | reg 99 drivers/net/ethernet/atheros/alx/hw.c u16 reg, u16 phy_data) reg 110 drivers/net/ethernet/atheros/alx/hw.c reg << ALX_MDIO_EXTN_REG_SHIFT; reg 120 drivers/net/ethernet/atheros/alx/hw.c reg << ALX_MDIO_REG_SHIFT | reg 129 drivers/net/ethernet/atheros/alx/hw.c static int __alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data) reg 131 drivers/net/ethernet/atheros/alx/hw.c return alx_read_phy_core(hw, false, 0, reg, phy_data); reg 134 drivers/net/ethernet/atheros/alx/hw.c static int __alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data) reg 136 drivers/net/ethernet/atheros/alx/hw.c return alx_write_phy_core(hw, false, 0, reg, phy_data); reg 139 drivers/net/ethernet/atheros/alx/hw.c static int __alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata) reg 141 drivers/net/ethernet/atheros/alx/hw.c return alx_read_phy_core(hw, true, dev, reg, pdata); reg 144 drivers/net/ethernet/atheros/alx/hw.c static int __alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data) reg 146 drivers/net/ethernet/atheros/alx/hw.c return alx_write_phy_core(hw, true, dev, reg, data); reg 149 drivers/net/ethernet/atheros/alx/hw.c static int __alx_read_phy_dbg(struct alx_hw *hw, u16 reg, u16 *pdata) reg 153 drivers/net/ethernet/atheros/alx/hw.c err = __alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, reg); reg 160 drivers/net/ethernet/atheros/alx/hw.c static int __alx_write_phy_dbg(struct alx_hw *hw, u16 reg, u16 data) reg 164 drivers/net/ethernet/atheros/alx/hw.c err = __alx_write_phy_reg(hw, ALX_MII_DBG_ADDR, reg); reg 171 drivers/net/ethernet/atheros/alx/hw.c int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data) reg 176 drivers/net/ethernet/atheros/alx/hw.c err = __alx_read_phy_reg(hw, reg, phy_data); reg 182 drivers/net/ethernet/atheros/alx/hw.c int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data) reg 187 drivers/net/ethernet/atheros/alx/hw.c err = __alx_write_phy_reg(hw, reg, phy_data); reg 193 drivers/net/ethernet/atheros/alx/hw.c int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata) reg 198 drivers/net/ethernet/atheros/alx/hw.c err = __alx_read_phy_ext(hw, dev, reg, pdata); reg 204 drivers/net/ethernet/atheros/alx/hw.c int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data) reg 209 drivers/net/ethernet/atheros/alx/hw.c err = __alx_write_phy_ext(hw, dev, reg, data); reg 215 drivers/net/ethernet/atheros/alx/hw.c static int alx_read_phy_dbg(struct alx_hw *hw, u16 reg, u16 *pdata) reg 220 drivers/net/ethernet/atheros/alx/hw.c err = __alx_read_phy_dbg(hw, reg, pdata); reg 226 drivers/net/ethernet/atheros/alx/hw.c static int alx_write_phy_dbg(struct alx_hw *hw, u16 reg, u16 data) reg 231 drivers/net/ethernet/atheros/alx/hw.c err = __alx_write_phy_dbg(hw, reg, data); reg 259 drivers/net/ethernet/atheros/alx/hw.c static bool alx_wait_reg(struct alx_hw *hw, u32 reg, u32 wait, u32 *val) reg 265 drivers/net/ethernet/atheros/alx/hw.c read = alx_read_mem32(hw, reg); reg 1036 drivers/net/ethernet/atheros/alx/hw.c u32 reg, val; reg 1038 drivers/net/ethernet/atheros/alx/hw.c reg = ALX_MSIX_ENTRY_BASE + index * PCI_MSIX_ENTRY_SIZE + reg 1043 drivers/net/ethernet/atheros/alx/hw.c alx_write_mem32(hw, reg, val); reg 516 drivers/net/ethernet/atheros/alx/hw.h static inline void alx_write_mem8(struct alx_hw *hw, u32 reg, u8 val) reg 518 drivers/net/ethernet/atheros/alx/hw.h writeb(val, hw->hw_addr + reg); reg 521 drivers/net/ethernet/atheros/alx/hw.h static inline void alx_write_mem16(struct alx_hw *hw, u32 reg, u16 val) reg 523 drivers/net/ethernet/atheros/alx/hw.h writew(val, hw->hw_addr + reg); reg 526 drivers/net/ethernet/atheros/alx/hw.h static inline u16 alx_read_mem16(struct alx_hw *hw, u32 reg) reg 528 drivers/net/ethernet/atheros/alx/hw.h return readw(hw->hw_addr + reg); reg 531 drivers/net/ethernet/atheros/alx/hw.h static inline void alx_write_mem32(struct alx_hw *hw, u32 reg, u32 val) reg 533 drivers/net/ethernet/atheros/alx/hw.h writel(val, hw->hw_addr + reg); reg 536 drivers/net/ethernet/atheros/alx/hw.h static inline u32 alx_read_mem32(struct alx_hw *hw, u32 reg) reg 538 drivers/net/ethernet/atheros/alx/hw.h return readl(hw->hw_addr + reg); reg 552 drivers/net/ethernet/atheros/alx/hw.h int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data); reg 553 drivers/net/ethernet/atheros/alx/hw.h int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data); reg 554 drivers/net/ethernet/atheros/alx/hw.h int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata); reg 555 drivers/net/ethernet/atheros/alx/hw.h int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data); reg 560 drivers/net/ethernet/atheros/alx/main.c u32 crc32, bit, reg; reg 563 drivers/net/ethernet/atheros/alx/main.c reg = (crc32 >> 31) & 0x1; reg 566 drivers/net/ethernet/atheros/alx/main.c mc_hash[reg] |= BIT(bit); reg 546 drivers/net/ethernet/atheros/atl1c/atl1c.h #define AT_WRITE_REG(a, reg, value) ( \ reg 547 drivers/net/ethernet/atheros/atl1c/atl1c.h writel((value), ((a)->hw_addr + reg))) reg 552 drivers/net/ethernet/atheros/atl1c/atl1c.h #define AT_READ_REG(a, reg, pdata) do { \ reg 554 drivers/net/ethernet/atheros/atl1c/atl1c.h readl((a)->hw_addr + reg); \ reg 555 drivers/net/ethernet/atheros/atl1c/atl1c.h *(u32 *)pdata = readl((a)->hw_addr + reg); \ reg 557 drivers/net/ethernet/atheros/atl1c/atl1c.h *(u32 *)pdata = readl((a)->hw_addr + reg); \ reg 561 drivers/net/ethernet/atheros/atl1c/atl1c.h #define AT_WRITE_REGB(a, reg, value) (\ reg 562 drivers/net/ethernet/atheros/atl1c/atl1c.h writeb((value), ((a)->hw_addr + reg))) reg 564 drivers/net/ethernet/atheros/atl1c/atl1c.h #define AT_READ_REGB(a, reg) (\ reg 565 drivers/net/ethernet/atheros/atl1c/atl1c.h readb((a)->hw_addr + reg)) reg 567 drivers/net/ethernet/atheros/atl1c/atl1c.h #define AT_WRITE_REGW(a, reg, value) (\ reg 568 drivers/net/ethernet/atheros/atl1c/atl1c.h writew((value), ((a)->hw_addr + reg))) reg 570 drivers/net/ethernet/atheros/atl1c/atl1c.h #define AT_READ_REGW(a, reg, pdata) do { \ reg 572 drivers/net/ethernet/atheros/atl1c/atl1c.h readw((a)->hw_addr + reg); \ reg 573 drivers/net/ethernet/atheros/atl1c/atl1c.h *(u16 *)pdata = readw((a)->hw_addr + reg); \ reg 575 drivers/net/ethernet/atheros/atl1c/atl1c.h *(u16 *)pdata = readw((a)->hw_addr + reg); \ reg 579 drivers/net/ethernet/atheros/atl1c/atl1c.h #define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \ reg 580 drivers/net/ethernet/atheros/atl1c/atl1c.h writel((value), (((a)->hw_addr + reg) + ((offset) << 2)))) reg 582 drivers/net/ethernet/atheros/atl1c/atl1c.h #define AT_READ_REG_ARRAY(a, reg, offset) ( \ reg 583 drivers/net/ethernet/atheros/atl1c/atl1c.h readl(((a)->hw_addr + reg) + ((offset) << 2))) reg 303 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c u16 reg, u16 *phy_data) reg 317 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c val = FIELDX(MDIO_EXTN_DEVAD, dev) | FIELDX(MDIO_EXTN_REG, reg); reg 327 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c FIELDX(MDIO_CTRL_REG, reg) | reg 352 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c u16 reg, u16 phy_data) reg 366 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c val = FIELDX(MDIO_EXTN_DEVAD, dev) | FIELDX(MDIO_EXTN_REG, reg); reg 377 drivers/net/ethernet/atheros/atl1c/atl1c_hw.c FIELDX(MDIO_CTRL_REG, reg) | reg 44 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h u16 reg, u16 *phy_data); reg 46 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h u16 reg, u16 phy_data); reg 1544 drivers/net/ethernet/atheros/atl1c/atl1c_main.c u16 reg; reg 1547 drivers/net/ethernet/atheros/atl1c/atl1c_main.c reg = type == atl1c_trans_high ? REG_TPD_PRI1_CIDX : REG_TPD_PRI0_CIDX; reg 1549 drivers/net/ethernet/atheros/atl1c/atl1c_main.c AT_READ_REGW(&adapter->hw, reg, &hw_next_to_clean); reg 2192 drivers/net/ethernet/atheros/atl1c/atl1c_main.c u16 reg; reg 2194 drivers/net/ethernet/atheros/atl1c/atl1c_main.c reg = type == atl1c_trans_high ? REG_TPD_PRI1_PIDX : REG_TPD_PRI0_PIDX; reg 2195 drivers/net/ethernet/atheros/atl1c/atl1c_main.c AT_WRITE_REGW(&adapter->hw, reg, tpd_ring->next_to_use); reg 457 drivers/net/ethernet/atheros/atl1e/atl1e.h #define AT_WRITE_REG(a, reg, value) ( \ reg 458 drivers/net/ethernet/atheros/atl1e/atl1e.h writel((value), ((a)->hw_addr + reg))) reg 463 drivers/net/ethernet/atheros/atl1e/atl1e.h #define AT_READ_REG(a, reg) ( \ reg 464 drivers/net/ethernet/atheros/atl1e/atl1e.h readl((a)->hw_addr + reg)) reg 466 drivers/net/ethernet/atheros/atl1e/atl1e.h #define AT_WRITE_REGB(a, reg, value) (\ reg 467 drivers/net/ethernet/atheros/atl1e/atl1e.h writeb((value), ((a)->hw_addr + reg))) reg 469 drivers/net/ethernet/atheros/atl1e/atl1e.h #define AT_READ_REGB(a, reg) (\ reg 470 drivers/net/ethernet/atheros/atl1e/atl1e.h readb((a)->hw_addr + reg)) reg 472 drivers/net/ethernet/atheros/atl1e/atl1e.h #define AT_WRITE_REGW(a, reg, value) (\ reg 473 drivers/net/ethernet/atheros/atl1e/atl1e.h writew((value), ((a)->hw_addr + reg))) reg 475 drivers/net/ethernet/atheros/atl1e/atl1e.h #define AT_READ_REGW(a, reg) (\ reg 476 drivers/net/ethernet/atheros/atl1e/atl1e.h readw((a)->hw_addr + reg)) reg 478 drivers/net/ethernet/atheros/atl1e/atl1e.h #define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \ reg 479 drivers/net/ethernet/atheros/atl1e/atl1e.h writel((value), (((a)->hw_addr + reg) + ((offset) << 2)))) reg 481 drivers/net/ethernet/atheros/atl1e/atl1e.h #define AT_READ_REG_ARRAY(a, reg, offset) ( \ reg 482 drivers/net/ethernet/atheros/atl1e/atl1e.h readl(((a)->hw_addr + reg) + ((offset) << 2))) reg 422 drivers/net/ethernet/atheros/atlx/atl1.c u16 reg; reg 433 drivers/net/ethernet/atheros/atlx/atl1.c reg = 0; reg 440 drivers/net/ethernet/atheros/atlx/atl1.c if (reg == REG_MAC_STA_ADDR) reg 442 drivers/net/ethernet/atheros/atlx/atl1.c else if (reg == (REG_MAC_STA_ADDR + 4)) reg 447 drivers/net/ethernet/atheros/atlx/atl1.c reg = (u16) (control >> 16); reg 466 drivers/net/ethernet/atheros/atlx/atl1.c reg = 0; reg 472 drivers/net/ethernet/atheros/atlx/atl1.c if (reg == REG_MAC_STA_ADDR) reg 474 drivers/net/ethernet/atheros/atlx/atl1.c else if (reg == (REG_MAC_STA_ADDR + 4)) reg 479 drivers/net/ethernet/atheros/atlx/atl1.c reg = (u16) (control >> 16); reg 1710 drivers/net/ethernet/atheros/atlx/atl2.c static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) reg 1713 drivers/net/ethernet/atheros/atlx/atl2.c pci_read_config_word(adapter->pdev, reg, value); reg 1716 drivers/net/ethernet/atheros/atlx/atl2.c static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) reg 1719 drivers/net/ethernet/atheros/atlx/atl2.c pci_write_config_word(adapter->pdev, reg, *value); reg 38 drivers/net/ethernet/atheros/atlx/atl2.h #define ATL2_WRITE_REG(a, reg, value) (iowrite32((value), \ reg 39 drivers/net/ethernet/atheros/atlx/atl2.h ((a)->hw_addr + (reg)))) reg 43 drivers/net/ethernet/atheros/atlx/atl2.h #define ATL2_READ_REG(a, reg) (ioread32((a)->hw_addr + (reg))) reg 45 drivers/net/ethernet/atheros/atlx/atl2.h #define ATL2_WRITE_REGB(a, reg, value) (iowrite8((value), \ reg 46 drivers/net/ethernet/atheros/atlx/atl2.h ((a)->hw_addr + (reg)))) reg 48 drivers/net/ethernet/atheros/atlx/atl2.h #define ATL2_READ_REGB(a, reg) (ioread8((a)->hw_addr + (reg))) reg 50 drivers/net/ethernet/atheros/atlx/atl2.h #define ATL2_WRITE_REGW(a, reg, value) (iowrite16((value), \ reg 51 drivers/net/ethernet/atheros/atlx/atl2.h ((a)->hw_addr + (reg)))) reg 53 drivers/net/ethernet/atheros/atlx/atl2.h #define ATL2_READ_REGW(a, reg) (ioread16((a)->hw_addr + (reg))) reg 55 drivers/net/ethernet/atheros/atlx/atl2.h #define ATL2_WRITE_REG_ARRAY(a, reg, offset, value) \ reg 56 drivers/net/ethernet/atheros/atlx/atl2.h (iowrite32((value), (((a)->hw_addr + (reg)) + ((offset) << 2)))) reg 58 drivers/net/ethernet/atheros/atlx/atl2.h #define ATL2_READ_REG_ARRAY(a, reg, offset) \ reg 59 drivers/net/ethernet/atheros/atlx/atl2.h (ioread32(((a)->hw_addr + (reg)) + ((offset) << 2))) reg 76 drivers/net/ethernet/atheros/atlx/atl2.h static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value); reg 77 drivers/net/ethernet/atheros/atlx/atl2.h static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value); reg 35 drivers/net/ethernet/aurora/nb8800.c static inline u8 nb8800_readb(struct nb8800_priv *priv, int reg) reg 37 drivers/net/ethernet/aurora/nb8800.c return readb_relaxed(priv->base + reg); reg 40 drivers/net/ethernet/aurora/nb8800.c static inline u32 nb8800_readl(struct nb8800_priv *priv, int reg) reg 42 drivers/net/ethernet/aurora/nb8800.c return readl_relaxed(priv->base + reg); reg 45 drivers/net/ethernet/aurora/nb8800.c static inline void nb8800_writeb(struct nb8800_priv *priv, int reg, u8 val) reg 47 drivers/net/ethernet/aurora/nb8800.c writeb_relaxed(val, priv->base + reg); reg 50 drivers/net/ethernet/aurora/nb8800.c static inline void nb8800_writew(struct nb8800_priv *priv, int reg, u16 val) reg 52 drivers/net/ethernet/aurora/nb8800.c writew_relaxed(val, priv->base + reg); reg 55 drivers/net/ethernet/aurora/nb8800.c static inline void nb8800_writel(struct nb8800_priv *priv, int reg, u32 val) reg 57 drivers/net/ethernet/aurora/nb8800.c writel_relaxed(val, priv->base + reg); reg 60 drivers/net/ethernet/aurora/nb8800.c static inline void nb8800_maskb(struct nb8800_priv *priv, int reg, reg 63 drivers/net/ethernet/aurora/nb8800.c u32 old = nb8800_readb(priv, reg); reg 67 drivers/net/ethernet/aurora/nb8800.c nb8800_writeb(priv, reg, new); reg 70 drivers/net/ethernet/aurora/nb8800.c static inline void nb8800_maskl(struct nb8800_priv *priv, int reg, reg 73 drivers/net/ethernet/aurora/nb8800.c u32 old = nb8800_readl(priv, reg); reg 77 drivers/net/ethernet/aurora/nb8800.c nb8800_writel(priv, reg, new); reg 80 drivers/net/ethernet/aurora/nb8800.c static inline void nb8800_modb(struct nb8800_priv *priv, int reg, u8 bits, reg 83 drivers/net/ethernet/aurora/nb8800.c nb8800_maskb(priv, reg, bits, set ? bits : 0); reg 86 drivers/net/ethernet/aurora/nb8800.c static inline void nb8800_setb(struct nb8800_priv *priv, int reg, u8 bits) reg 88 drivers/net/ethernet/aurora/nb8800.c nb8800_maskb(priv, reg, bits, bits); reg 91 drivers/net/ethernet/aurora/nb8800.c static inline void nb8800_clearb(struct nb8800_priv *priv, int reg, u8 bits) reg 93 drivers/net/ethernet/aurora/nb8800.c nb8800_maskb(priv, reg, bits, 0); reg 96 drivers/net/ethernet/aurora/nb8800.c static inline void nb8800_modl(struct nb8800_priv *priv, int reg, u32 bits, reg 99 drivers/net/ethernet/aurora/nb8800.c nb8800_maskl(priv, reg, bits, set ? bits : 0); reg 102 drivers/net/ethernet/aurora/nb8800.c static inline void nb8800_setl(struct nb8800_priv *priv, int reg, u32 bits) reg 104 drivers/net/ethernet/aurora/nb8800.c nb8800_maskl(priv, reg, bits, bits); reg 107 drivers/net/ethernet/aurora/nb8800.c static inline void nb8800_clearl(struct nb8800_priv *priv, int reg, u32 bits) reg 109 drivers/net/ethernet/aurora/nb8800.c nb8800_maskl(priv, reg, bits, 0); reg 137 drivers/net/ethernet/aurora/nb8800.c static int nb8800_mdio_read(struct mii_bus *bus, int phy_id, int reg) reg 143 drivers/net/ethernet/aurora/nb8800.c err = nb8800_mdio_cmd(bus, MDIO_CMD_ADDR(phy_id) | MDIO_CMD_REG(reg)); reg 154 drivers/net/ethernet/aurora/nb8800.c static int nb8800_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val) reg 156 drivers/net/ethernet/aurora/nb8800.c u32 cmd = MDIO_CMD_ADDR(phy_id) | MDIO_CMD_REG(reg) | reg 166 drivers/net/ethernet/broadcom/b44.c static inline unsigned long br32(const struct b44 *bp, unsigned long reg) reg 168 drivers/net/ethernet/broadcom/b44.c return ssb_read32(bp->sdev, reg); reg 172 drivers/net/ethernet/broadcom/b44.c unsigned long reg, unsigned long val) reg 174 drivers/net/ethernet/broadcom/b44.c ssb_write32(bp->sdev, reg, val); reg 177 drivers/net/ethernet/broadcom/b44.c static int b44_wait_bit(struct b44 *bp, unsigned long reg, reg 183 drivers/net/ethernet/broadcom/b44.c u32 val = br32(bp, reg); reg 194 drivers/net/ethernet/broadcom/b44.c bit, reg, clear ? "clear" : "set"); reg 259 drivers/net/ethernet/broadcom/b44.c static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val) reg 267 drivers/net/ethernet/broadcom/b44.c (reg << MDIO_DATA_RA_SHIFT) | reg 275 drivers/net/ethernet/broadcom/b44.c static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val) reg 281 drivers/net/ethernet/broadcom/b44.c (reg << MDIO_DATA_RA_SHIFT) | reg 287 drivers/net/ethernet/broadcom/b44.c static inline int b44_readphy(struct b44 *bp, int reg, u32 *val) reg 292 drivers/net/ethernet/broadcom/b44.c return __b44_readphy(bp, bp->phy_addr, reg, val); reg 295 drivers/net/ethernet/broadcom/b44.c static inline int b44_writephy(struct b44 *bp, int reg, u32 val) reg 300 drivers/net/ethernet/broadcom/b44.c return __b44_writephy(bp, bp->phy_addr, reg, val); reg 504 drivers/net/ethernet/broadcom/b44.c unsigned long reg; reg 510 drivers/net/ethernet/broadcom/b44.c for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) { reg 511 drivers/net/ethernet/broadcom/b44.c *val++ += br32(bp, reg); reg 515 drivers/net/ethernet/broadcom/b44.c reg += 8*4UL; reg 517 drivers/net/ethernet/broadcom/b44.c for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) { reg 518 drivers/net/ethernet/broadcom/b44.c *val++ += br32(bp, reg); reg 1271 drivers/net/ethernet/broadcom/b44.c unsigned long reg; reg 1274 drivers/net/ethernet/broadcom/b44.c for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) reg 1275 drivers/net/ethernet/broadcom/b44.c br32(bp, reg); reg 1276 drivers/net/ethernet/broadcom/b44.c for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) reg 1277 drivers/net/ethernet/broadcom/b44.c br32(bp, reg); reg 1930 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 reg; reg 1936 drivers/net/ethernet/broadcom/bcm63xx_enet.c reg = ENETSW_MDIOC_RD_MASK | reg 1941 drivers/net/ethernet/broadcom/bcm63xx_enet.c reg |= ENETSW_MDIOC_EXT_MASK; reg 1943 drivers/net/ethernet/broadcom/bcm63xx_enet.c enetsw_writel(priv, reg, ENETSW_MDIOC_REG); reg 1954 drivers/net/ethernet/broadcom/bcm63xx_enet.c u32 reg; reg 1959 drivers/net/ethernet/broadcom/bcm63xx_enet.c reg = ENETSW_MDIOC_WR_MASK | reg 1964 drivers/net/ethernet/broadcom/bcm63xx_enet.c reg |= ENETSW_MDIOC_EXT_MASK; reg 1966 drivers/net/ethernet/broadcom/bcm63xx_enet.c reg |= data; reg 1968 drivers/net/ethernet/broadcom/bcm63xx_enet.c enetsw_writel(priv, reg, ENETSW_MDIOC_REG); reg 2551 drivers/net/ethernet/broadcom/bcm63xx_enet.c int reg; reg 2555 drivers/net/ethernet/broadcom/bcm63xx_enet.c reg = s->mib_reg; reg 2556 drivers/net/ethernet/broadcom/bcm63xx_enet.c if (reg == -1) reg 2559 drivers/net/ethernet/broadcom/bcm63xx_enet.c lo = enetsw_readl(priv, ENETSW_MIB_REG(reg)); reg 2563 drivers/net/ethernet/broadcom/bcm63xx_enet.c hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1)); reg 32 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg = readl_relaxed(priv->base + offset + off); \ reg 33 drivers/net/ethernet/broadcom/bcmsysport.c return reg; \ reg 121 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 124 drivers/net/ethernet/broadcom/bcmsysport.c reg = rxchk_readl(priv, RXCHK_CONTROL); reg 128 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~RXCHK_L2_HDR_DIS; reg 130 drivers/net/ethernet/broadcom/bcmsysport.c reg |= RXCHK_EN; reg 132 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~RXCHK_EN; reg 138 drivers/net/ethernet/broadcom/bcmsysport.c reg |= RXCHK_SKIP_FCS; reg 140 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~RXCHK_SKIP_FCS; reg 147 drivers/net/ethernet/broadcom/bcmsysport.c reg |= RXCHK_BRCM_TAG_EN; reg 149 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~RXCHK_BRCM_TAG_EN; reg 151 drivers/net/ethernet/broadcom/bcmsysport.c rxchk_writel(priv, reg, RXCHK_CONTROL); reg 158 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 164 drivers/net/ethernet/broadcom/bcmsysport.c reg = tdma_readl(priv, TDMA_CONTROL); reg 166 drivers/net/ethernet/broadcom/bcmsysport.c reg |= tdma_control_bit(priv, TSB_EN); reg 168 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~tdma_control_bit(priv, TSB_EN); reg 169 drivers/net/ethernet/broadcom/bcmsysport.c tdma_writel(priv, reg, TDMA_CONTROL); reg 563 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 565 drivers/net/ethernet/broadcom/bcmsysport.c reg = rdma_readl(priv, RDMA_MBDONE_INTR); reg 566 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~(RDMA_INTR_THRESH_MASK | reg 568 drivers/net/ethernet/broadcom/bcmsysport.c reg |= pkts; reg 569 drivers/net/ethernet/broadcom/bcmsysport.c reg |= DIV_ROUND_UP(usecs * 1000, 8192) << RDMA_TIMEOUT_SHIFT; reg 570 drivers/net/ethernet/broadcom/bcmsysport.c rdma_writel(priv, reg, RDMA_MBDONE_INTR); reg 577 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 579 drivers/net/ethernet/broadcom/bcmsysport.c reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(ring->index)); reg 580 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~(RING_INTR_THRESH_MASK | reg 582 drivers/net/ethernet/broadcom/bcmsysport.c reg |= ec->tx_max_coalesced_frames; reg 583 drivers/net/ethernet/broadcom/bcmsysport.c reg |= DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000, 8192) << reg 585 drivers/net/ethernet/broadcom/bcmsysport.c tdma_writel(priv, reg, TDMA_DESC_RING_INTR_CONTROL(ring->index)); reg 592 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 594 drivers/net/ethernet/broadcom/bcmsysport.c reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(0)); reg 596 drivers/net/ethernet/broadcom/bcmsysport.c ec->tx_coalesce_usecs = (reg >> RING_TIMEOUT_SHIFT) * 8192 / 1000; reg 597 drivers/net/ethernet/broadcom/bcmsysport.c ec->tx_max_coalesced_frames = reg & RING_INTR_THRESH_MASK; reg 599 drivers/net/ethernet/broadcom/bcmsysport.c reg = rdma_readl(priv, RDMA_MBDONE_INTR); reg 601 drivers/net/ethernet/broadcom/bcmsysport.c ec->rx_coalesce_usecs = (reg >> RDMA_TIMEOUT_SHIFT) * 8192 / 1000; reg 602 drivers/net/ethernet/broadcom/bcmsysport.c ec->rx_max_coalesced_frames = reg & RDMA_INTR_THRESH_MASK; reg 1029 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg, bit; reg 1031 drivers/net/ethernet/broadcom/bcmsysport.c reg = umac_readl(priv, UMAC_MPD_CTRL); reg 1033 drivers/net/ethernet/broadcom/bcmsysport.c reg |= MPD_EN; reg 1035 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~MPD_EN; reg 1036 drivers/net/ethernet/broadcom/bcmsysport.c umac_writel(priv, reg, UMAC_MPD_CTRL); reg 1043 drivers/net/ethernet/broadcom/bcmsysport.c reg = rbuf_readl(priv, RBUF_CONTROL); reg 1045 drivers/net/ethernet/broadcom/bcmsysport.c reg |= bit; reg 1047 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~bit; reg 1048 drivers/net/ethernet/broadcom/bcmsysport.c rbuf_writel(priv, reg, RBUF_CONTROL); reg 1054 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 1057 drivers/net/ethernet/broadcom/bcmsysport.c reg = rxchk_readl(priv, RXCHK_CONTROL); reg 1058 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~(RXCHK_BRCM_TAG_MATCH_MASK << reg 1060 drivers/net/ethernet/broadcom/bcmsysport.c rxchk_writel(priv, reg, RXCHK_CONTROL); reg 1074 drivers/net/ethernet/broadcom/bcmsysport.c reg = intrl2_0_readl(priv, INTRL2_CPU_STATUS); reg 1075 drivers/net/ethernet/broadcom/bcmsysport.c if (reg & INTRL2_0_MPD) reg 1078 drivers/net/ethernet/broadcom/bcmsysport.c if (reg & INTRL2_0_BRCM_MATCH_TAG) { reg 1079 drivers/net/ethernet/broadcom/bcmsysport.c reg = rxchk_readl(priv, RXCHK_BRCM_TAG_MATCH_STATUS) & reg 1082 drivers/net/ethernet/broadcom/bcmsysport.c "Wake-on-LAN (filters 0x%02x) interrupt!\n", reg); reg 1374 drivers/net/ethernet/broadcom/bcmsysport.c u32 cmd_bits = 0, reg; reg 1422 drivers/net/ethernet/broadcom/bcmsysport.c reg = umac_readl(priv, UMAC_CMD); reg 1423 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | reg 1426 drivers/net/ethernet/broadcom/bcmsysport.c reg |= cmd_bits; reg 1427 drivers/net/ethernet/broadcom/bcmsysport.c umac_writel(priv, reg, UMAC_CMD); reg 1470 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 1499 drivers/net/ethernet/broadcom/bcmsysport.c reg = tdma_readl(priv, TDMA_DESC_RING_MAPPING(index)); reg 1500 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~(RING_QID_MASK | RING_PORT_ID_MASK << RING_PORT_ID_SHIFT); reg 1502 drivers/net/ethernet/broadcom/bcmsysport.c reg |= ring->switch_queue & RING_QID_MASK; reg 1503 drivers/net/ethernet/broadcom/bcmsysport.c reg |= ring->switch_port << RING_PORT_ID_SHIFT; reg 1505 drivers/net/ethernet/broadcom/bcmsysport.c reg |= RING_IGNORE_STATUS; reg 1507 drivers/net/ethernet/broadcom/bcmsysport.c tdma_writel(priv, reg, TDMA_DESC_RING_MAPPING(index)); reg 1511 drivers/net/ethernet/broadcom/bcmsysport.c reg = tdma_readl(priv, TDMA_CONTROL); reg 1512 drivers/net/ethernet/broadcom/bcmsysport.c reg |= tdma_control_bit(priv, ACB_ALGO); reg 1513 drivers/net/ethernet/broadcom/bcmsysport.c tdma_writel(priv, reg, TDMA_CONTROL); reg 1518 drivers/net/ethernet/broadcom/bcmsysport.c reg = tdma_readl(priv, TDMA_CONTROL); reg 1520 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~BIT(TSB_SWAP1); reg 1523 drivers/net/ethernet/broadcom/bcmsysport.c reg |= tdma_control_bit(priv, TSB_SWAP0); reg 1525 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~tdma_control_bit(priv, TSB_SWAP0); reg 1526 drivers/net/ethernet/broadcom/bcmsysport.c tdma_writel(priv, reg, TDMA_CONTROL); reg 1536 drivers/net/ethernet/broadcom/bcmsysport.c reg = tdma_readl(priv, TDMA_TIER1_ARB_0_QUEUE_EN); reg 1537 drivers/net/ethernet/broadcom/bcmsysport.c reg |= (1 << index); reg 1538 drivers/net/ethernet/broadcom/bcmsysport.c tdma_writel(priv, reg, TDMA_TIER1_ARB_0_QUEUE_EN); reg 1554 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 1557 drivers/net/ethernet/broadcom/bcmsysport.c reg = tdma_readl(priv, TDMA_STATUS); reg 1558 drivers/net/ethernet/broadcom/bcmsysport.c if (!(reg & TDMA_DISABLED)) reg 1586 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 1588 drivers/net/ethernet/broadcom/bcmsysport.c reg = rdma_readl(priv, RDMA_CONTROL); reg 1590 drivers/net/ethernet/broadcom/bcmsysport.c reg |= RDMA_EN; reg 1592 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~RDMA_EN; reg 1593 drivers/net/ethernet/broadcom/bcmsysport.c rdma_writel(priv, reg, RDMA_CONTROL); reg 1597 drivers/net/ethernet/broadcom/bcmsysport.c reg = rdma_readl(priv, RDMA_STATUS); reg 1598 drivers/net/ethernet/broadcom/bcmsysport.c if (!!(reg & RDMA_DISABLED) == !enable) reg 1613 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 1615 drivers/net/ethernet/broadcom/bcmsysport.c reg = tdma_readl(priv, TDMA_CONTROL); reg 1617 drivers/net/ethernet/broadcom/bcmsysport.c reg |= tdma_control_bit(priv, TDMA_EN); reg 1619 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~tdma_control_bit(priv, TDMA_EN); reg 1620 drivers/net/ethernet/broadcom/bcmsysport.c tdma_writel(priv, reg, TDMA_CONTROL); reg 1624 drivers/net/ethernet/broadcom/bcmsysport.c reg = tdma_readl(priv, TDMA_STATUS); reg 1625 drivers/net/ethernet/broadcom/bcmsysport.c if (!!(reg & TDMA_DISABLED) == !enable) reg 1639 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 1667 drivers/net/ethernet/broadcom/bcmsysport.c reg = rdma_readl(priv, RDMA_STATUS); reg 1668 drivers/net/ethernet/broadcom/bcmsysport.c if (!(reg & RDMA_DISABLED)) reg 1694 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 1697 drivers/net/ethernet/broadcom/bcmsysport.c reg = rdma_readl(priv, RDMA_STATUS); reg 1698 drivers/net/ethernet/broadcom/bcmsysport.c if (!(reg & RDMA_DISABLED)) reg 1719 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 1724 drivers/net/ethernet/broadcom/bcmsysport.c reg = umac_readl(priv, UMAC_CMD); reg 1726 drivers/net/ethernet/broadcom/bcmsysport.c reg |= CMD_PROMISC; reg 1728 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~CMD_PROMISC; reg 1729 drivers/net/ethernet/broadcom/bcmsysport.c umac_writel(priv, reg, UMAC_CMD); reg 1739 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 1742 drivers/net/ethernet/broadcom/bcmsysport.c reg = umac_readl(priv, UMAC_CMD); reg 1744 drivers/net/ethernet/broadcom/bcmsysport.c reg |= mask; reg 1746 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~mask; reg 1747 drivers/net/ethernet/broadcom/bcmsysport.c umac_writel(priv, reg, UMAC_CMD); reg 1749 drivers/net/ethernet/broadcom/bcmsysport.c reg = gib_readl(priv, GIB_CONTROL); reg 1751 drivers/net/ethernet/broadcom/bcmsysport.c reg |= mask; reg 1753 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~mask; reg 1754 drivers/net/ethernet/broadcom/bcmsysport.c gib_writel(priv, reg, GIB_CONTROL); reg 1766 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 1771 drivers/net/ethernet/broadcom/bcmsysport.c reg = umac_readl(priv, UMAC_CMD); reg 1772 drivers/net/ethernet/broadcom/bcmsysport.c reg |= CMD_SW_RESET; reg 1773 drivers/net/ethernet/broadcom/bcmsysport.c umac_writel(priv, reg, UMAC_CMD); reg 1775 drivers/net/ethernet/broadcom/bcmsysport.c reg = umac_readl(priv, UMAC_CMD); reg 1776 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~CMD_SW_RESET; reg 1777 drivers/net/ethernet/broadcom/bcmsysport.c umac_writel(priv, reg, UMAC_CMD); reg 1868 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 1870 drivers/net/ethernet/broadcom/bcmsysport.c reg = rbuf_readl(priv, RBUF_CONTROL); reg 1871 drivers/net/ethernet/broadcom/bcmsysport.c reg |= RBUF_4B_ALGN | RBUF_RSB_EN; reg 1874 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~RBUF_RSB_SWAP1; reg 1878 drivers/net/ethernet/broadcom/bcmsysport.c reg |= RBUF_RSB_SWAP0; reg 1880 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~RBUF_RSB_SWAP0; reg 1881 drivers/net/ethernet/broadcom/bcmsysport.c rbuf_writel(priv, reg, RBUF_CONTROL); reg 1896 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 1898 drivers/net/ethernet/broadcom/bcmsysport.c reg = gib_readl(priv, GIB_CONTROL); reg 1901 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~(GIB_PAD_EXTENSION_MASK << GIB_PAD_EXTENSION_SHIFT); reg 1902 drivers/net/ethernet/broadcom/bcmsysport.c reg |= ENET_BRCM_TAG_LEN << GIB_PAD_EXTENSION_SHIFT; reg 1904 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~(GIB_IPG_LEN_MASK << GIB_IPG_LEN_SHIFT); reg 1905 drivers/net/ethernet/broadcom/bcmsysport.c reg |= 12 << GIB_IPG_LEN_SHIFT; reg 1906 drivers/net/ethernet/broadcom/bcmsysport.c gib_writel(priv, reg, GIB_CONTROL); reg 2089 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 2092 drivers/net/ethernet/broadcom/bcmsysport.c reg = rxchk_readl(priv, RXCHK_BRCM_TAG(index)); reg 2093 drivers/net/ethernet/broadcom/bcmsysport.c reg >>= RXCHK_BRCM_TAG_CID_SHIFT; reg 2094 drivers/net/ethernet/broadcom/bcmsysport.c reg &= RXCHK_BRCM_TAG_CID_MASK; reg 2095 drivers/net/ethernet/broadcom/bcmsysport.c if (reg == location) reg 2121 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 2145 drivers/net/ethernet/broadcom/bcmsysport.c reg = rxchk_readl(priv, RXCHK_BRCM_TAG(index)); reg 2146 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~(RXCHK_BRCM_TAG_CID_MASK << RXCHK_BRCM_TAG_CID_SHIFT); reg 2147 drivers/net/ethernet/broadcom/bcmsysport.c reg |= nfc->fs.location << RXCHK_BRCM_TAG_CID_SHIFT; reg 2148 drivers/net/ethernet/broadcom/bcmsysport.c rxchk_writel(priv, reg, RXCHK_BRCM_TAG(index)); reg 2597 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 2599 drivers/net/ethernet/broadcom/bcmsysport.c reg = umac_readl(priv, UMAC_MPD_CTRL); reg 2601 drivers/net/ethernet/broadcom/bcmsysport.c reg |= MPD_EN; reg 2602 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~PSW_EN; reg 2609 drivers/net/ethernet/broadcom/bcmsysport.c reg |= PSW_EN; reg 2611 drivers/net/ethernet/broadcom/bcmsysport.c umac_writel(priv, reg, UMAC_MPD_CTRL); reg 2615 drivers/net/ethernet/broadcom/bcmsysport.c reg = rbuf_readl(priv, RBUF_CONTROL); reg 2617 drivers/net/ethernet/broadcom/bcmsysport.c reg |= RBUF_ACPI_EN_LITE; reg 2619 drivers/net/ethernet/broadcom/bcmsysport.c reg |= RBUF_ACPI_EN; reg 2620 drivers/net/ethernet/broadcom/bcmsysport.c rbuf_writel(priv, reg, RBUF_CONTROL); reg 2623 drivers/net/ethernet/broadcom/bcmsysport.c reg = rxchk_readl(priv, RXCHK_CONTROL); reg 2624 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~(RXCHK_BRCM_TAG_MATCH_MASK << reg 2627 drivers/net/ethernet/broadcom/bcmsysport.c reg |= BIT(RXCHK_BRCM_TAG_MATCH_SHIFT + i); reg 2630 drivers/net/ethernet/broadcom/bcmsysport.c reg |= RXCHK_EN | RXCHK_BRCM_TAG_EN; reg 2631 drivers/net/ethernet/broadcom/bcmsysport.c rxchk_writel(priv, reg, RXCHK_CONTROL); reg 2636 drivers/net/ethernet/broadcom/bcmsysport.c reg = rbuf_readl(priv, RBUF_STATUS); reg 2637 drivers/net/ethernet/broadcom/bcmsysport.c if (reg & RBUF_WOL_MODE) reg 2664 drivers/net/ethernet/broadcom/bcmsysport.c u32 reg; reg 2686 drivers/net/ethernet/broadcom/bcmsysport.c reg = rxchk_readl(priv, RXCHK_CONTROL); reg 2687 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~RXCHK_EN; reg 2688 drivers/net/ethernet/broadcom/bcmsysport.c rxchk_writel(priv, reg, RXCHK_CONTROL); reg 15 drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c static bool bcma_mdio_wait_value(struct bcma_device *core, u16 reg, u32 mask, reg 22 drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c val = bcma_read32(core, reg); reg 27 drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c dev_err(&core->dev, "Timeout waiting for reg 0x%X\n", reg); reg 35 drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c static u16 bcma_mdio_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg) reg 71 drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c tmp |= reg << BGMAC_PA_REG_SHIFT; reg 77 drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c phyaddr, reg); reg 85 drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c static int bcma_mdio_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, reg 115 drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c tmp |= reg << BGMAC_PA_REG_SHIFT; reg 122 drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c phyaddr, reg); reg 21 drivers/net/ethernet/broadcom/bgmac.c static bool bgmac_wait_value(struct bgmac *bgmac, u16 reg, u32 mask, reg 28 drivers/net/ethernet/broadcom/bgmac.c val = bgmac_read(bgmac, reg); reg 33 drivers/net/ethernet/broadcom/bgmac.c dev_err(bgmac->dev, "Timeout waiting for reg 0x%X\n", reg); reg 493 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) reg 508 drivers/net/ethernet/broadcom/bnx2.c val1 = (bp->phy_addr << 21) | (reg << 16) | reg 550 drivers/net/ethernet/broadcom/bnx2.c bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) reg 565 drivers/net/ethernet/broadcom/bnx2.c val1 = (bp->phy_addr << 21) | (reg << 16) | val | reg 1645 drivers/net/ethernet/broadcom/bnx2.c u32 reg; reg 1653 drivers/net/ethernet/broadcom/bnx2.c bnx2_read_phy(bp, bp->mii_bmcr, ®); reg 1654 drivers/net/ethernet/broadcom/bnx2.c if (!(reg & BMCR_RESET)) { reg 1950 drivers/net/ethernet/broadcom/bnx2.c u32 reg; reg 1954 drivers/net/ethernet/broadcom/bnx2.c reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG); reg 1955 drivers/net/ethernet/broadcom/bnx2.c reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK; reg 1956 drivers/net/ethernet/broadcom/bnx2.c if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) { reg 6490 drivers/net/ethernet/broadcom/bnx2.c u32 reg, bdidx, cid, valid; reg 6518 drivers/net/ethernet/broadcom/bnx2.c for (reg = BNX2_TXP_CPU_MODE; reg <= BNX2_CP_CPU_MODE; reg += 0x40000) reg 6520 drivers/net/ethernet/broadcom/bnx2.c reg, bnx2_reg_rd_ind(bp, reg), reg 6521 drivers/net/ethernet/broadcom/bnx2.c bnx2_reg_rd_ind(bp, reg + 4), reg 6522 drivers/net/ethernet/broadcom/bnx2.c bnx2_reg_rd_ind(bp, reg + 8), reg 6523 drivers/net/ethernet/broadcom/bnx2.c bnx2_reg_rd_ind(bp, reg + 0x1c), reg 6524 drivers/net/ethernet/broadcom/bnx2.c bnx2_reg_rd_ind(bp, reg + 0x1c), reg 6525 drivers/net/ethernet/broadcom/bnx2.c bnx2_reg_rd_ind(bp, reg + 0x20)); reg 7986 drivers/net/ethernet/broadcom/bnx2.c u32 reg; reg 7988 drivers/net/ethernet/broadcom/bnx2.c reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS); reg 7989 drivers/net/ethernet/broadcom/bnx2.c if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { reg 8024 drivers/net/ethernet/broadcom/bnx2.c if (reg & BNX2_PCICFG_MISC_STATUS_M66EN) reg 8030 drivers/net/ethernet/broadcom/bnx2.c if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET) reg 8108 drivers/net/ethernet/broadcom/bnx2.c u32 reg; reg 8247 drivers/net/ethernet/broadcom/bnx2.c reg = BNX2_RD(bp, PCI_COMMAND); reg 8248 drivers/net/ethernet/broadcom/bnx2.c reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); reg 8249 drivers/net/ethernet/broadcom/bnx2.c BNX2_WR(bp, PCI_COMMAND, reg); reg 8260 drivers/net/ethernet/broadcom/bnx2.c reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE); reg 8265 drivers/net/ethernet/broadcom/bnx2.c if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) == reg 8276 drivers/net/ethernet/broadcom/bnx2.c reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE); reg 8278 drivers/net/ethernet/broadcom/bnx2.c if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) != reg 8288 drivers/net/ethernet/broadcom/bnx2.c reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV); reg 8297 drivers/net/ethernet/broadcom/bnx2.c num = (u8) (reg >> (24 - (i * 8))); reg 8307 drivers/net/ethernet/broadcom/bnx2.c reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE); reg 8308 drivers/net/ethernet/broadcom/bnx2.c if (reg & BNX2_PORT_FEATURE_WOL_ENABLED) reg 8311 drivers/net/ethernet/broadcom/bnx2.c if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) { reg 8315 drivers/net/ethernet/broadcom/bnx2.c reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); reg 8316 drivers/net/ethernet/broadcom/bnx2.c if (reg & BNX2_CONDITION_MFW_RUN_MASK) reg 8321 drivers/net/ethernet/broadcom/bnx2.c reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION); reg 8322 drivers/net/ethernet/broadcom/bnx2.c reg &= BNX2_CONDITION_MFW_RUN_MASK; reg 8323 drivers/net/ethernet/broadcom/bnx2.c if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN && reg 8324 drivers/net/ethernet/broadcom/bnx2.c reg != BNX2_CONDITION_MFW_RUN_NONE) { reg 8330 drivers/net/ethernet/broadcom/bnx2.c reg = bnx2_reg_rd_ind(bp, addr + i * 4); reg 8331 drivers/net/ethernet/broadcom/bnx2.c reg = be32_to_cpu(reg); reg 8332 drivers/net/ethernet/broadcom/bnx2.c memcpy(&bp->fw_version[j], ®, 4); reg 8337 drivers/net/ethernet/broadcom/bnx2.c reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER); reg 8338 drivers/net/ethernet/broadcom/bnx2.c bp->mac_addr[0] = (u8) (reg >> 8); reg 8339 drivers/net/ethernet/broadcom/bnx2.c bp->mac_addr[1] = (u8) reg; reg 8341 drivers/net/ethernet/broadcom/bnx2.c reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER); reg 8342 drivers/net/ethernet/broadcom/bnx2.c bp->mac_addr[2] = (u8) (reg >> 24); reg 8343 drivers/net/ethernet/broadcom/bnx2.c bp->mac_addr[3] = (u8) (reg >> 16); reg 8344 drivers/net/ethernet/broadcom/bnx2.c bp->mac_addr[4] = (u8) (reg >> 8); reg 8345 drivers/net/ethernet/broadcom/bnx2.c bp->mac_addr[5] = (u8) reg; reg 8380 drivers/net/ethernet/broadcom/bnx2.c reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG); reg 8381 drivers/net/ethernet/broadcom/bnx2.c if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) { reg 8395 drivers/net/ethernet/broadcom/bnx2.c if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G) reg 227 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) reg 228 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) reg 2052 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, reg 2063 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, reg 2069 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h val = REG_RD(bp, reg); reg 198 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h static void bnx2x_wr_64(struct bnx2x *bp, u32 reg, u32 val_lo, reg 205 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h REG_WR_DMAE_LEN(bp, reg, wb_write, 2); reg 679 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h u32 reg; reg 682 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx*8; reg 684 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8; reg 686 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h bnx2x_wr_64(bp, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping)); reg 875 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h u32 base_reg, u32 reg) reg 882 drivers/net/ethernet/broadcom/bnx2x/bnx2x_init_ops.h bnx2x_init_wr_wb(bp, reg + i*8, wb_data, 2); reg 220 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) reg 222 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val = REG_RD(bp, reg); reg 225 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, reg, val); reg 229 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) reg 231 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 val = REG_RD(bp, reg); reg 234 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c REG_WR(bp, reg, val); reg 2590 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 reg, u16 val) reg 2601 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c tmp = ((phy->addr << 21) | (reg << 16) | val | reg 2625 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 reg, u16 *ret_val) reg 2637 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = ((phy->addr << 21) | (reg << 16) | reg 2666 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u8 devad, u16 reg, u16 *ret_val) reg 2682 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val = ((phy->addr << 21) | (devad << 16) | reg | reg 2741 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u8 devad, u16 reg, u16 val) reg 2758 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c tmp = ((phy->addr << 21) | (devad << 16) | reg | reg 3168 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u8 devad, u16 reg, u16 or_val) reg 3171 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_read(bp, phy, devad, reg, &val); reg 3172 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); reg 3177 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u8 devad, u16 reg, u16 and_val) reg 3180 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_read(bp, phy, devad, reg, &val); reg 3181 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_write(bp, phy, devad, reg, val & and_val); reg 3185 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u8 devad, u16 reg, u16 *ret_val) reg 3195 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg, ret_val); reg 3202 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u8 devad, u16 reg, u16 val) reg 3212 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg, val); reg 3655 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, reg 3690 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, reg 3744 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, reg 3897 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, reg 4315 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, reg 8917 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 reg; reg 8919 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg = MDIO_XS_8706_REG_BANK_RX0 + reg 8922 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); reg 8928 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c " reg 0x%x <-- val 0x%x\n", reg, val); reg 8929 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); reg 9670 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c reg_set[i].reg, reg_set[i].val); reg 9759 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, reg 146 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h u16 reg; reg 394 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h u8 devad, u16 reg, u16 *ret_val); reg 397 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h u8 devad, u16 reg, u16 val); reg 1273 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, reg 1279 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) reg 1285 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, reg 1288 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); reg 4571 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c static void _print_parity(struct bnx2x *bp, u32 reg) reg 4573 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c pr_cont(" [0x%08x] ", REG_RD(bp, reg)); reg 7497 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val, reg; reg 7643 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0; reg 7644 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, reg, reg 7645 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_RD(bp, reg) & reg 7648 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0; reg 7649 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR(bp, reg, reg 7650 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_RD(bp, reg) & reg 7722 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c int reg; reg 7726 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c reg = PXP2_REG_RQ_ONCHIP_AT + index*8; reg 7728 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; reg 7732 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c REG_WR_DMAE(bp, reg, wb_write, 2); reg 1971 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c u32 reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + qid * 4; reg 1974 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c REG_WR(bp, reg, val); reg 1917 drivers/net/ethernet/broadcom/bnxt/bnxt.c u32 reg = fw_health->regs[reg_idx]; reg 1920 drivers/net/ethernet/broadcom/bnxt/bnxt.c reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); reg 1921 drivers/net/ethernet/broadcom/bnxt/bnxt.c reg_off = BNXT_FW_HEALTH_REG_OFF(reg); reg 7070 drivers/net/ethernet/broadcom/bnxt/bnxt.c u32 reg = fw_health->regs[i]; reg 7072 drivers/net/ethernet/broadcom/bnxt/bnxt.c if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC) reg 7075 drivers/net/ethernet/broadcom/bnxt/bnxt.c reg_base = reg & BNXT_GRC_BASE_MASK; reg 7076 drivers/net/ethernet/broadcom/bnxt/bnxt.c if ((reg & BNXT_GRC_BASE_MASK) != reg_base) reg 7079 drivers/net/ethernet/broadcom/bnxt/bnxt.c (reg & BNXT_GRC_OFFSET_MASK); reg 9337 drivers/net/ethernet/broadcom/bnxt/bnxt.c static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg, reg 9350 drivers/net/ethernet/broadcom/bnxt/bnxt.c req.reg_addr = cpu_to_le16(reg & 0x1f); reg 9355 drivers/net/ethernet/broadcom/bnxt/bnxt.c req.reg_addr = cpu_to_le16(reg); reg 9366 drivers/net/ethernet/broadcom/bnxt/bnxt.c static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg, reg 9377 drivers/net/ethernet/broadcom/bnxt/bnxt.c req.reg_addr = cpu_to_le16(reg & 0x1f); reg 9382 drivers/net/ethernet/broadcom/bnxt/bnxt.c req.reg_addr = cpu_to_le16(reg); reg 10594 drivers/net/ethernet/broadcom/bnxt/bnxt.c u32 reg = fw_health->fw_reset_seq_regs[reg_idx]; reg 10599 drivers/net/ethernet/broadcom/bnxt/bnxt.c reg_type = BNXT_FW_HEALTH_REG_TYPE(reg); reg 10600 drivers/net/ethernet/broadcom/bnxt/bnxt.c reg_off = BNXT_FW_HEALTH_REG_OFF(reg); reg 1394 drivers/net/ethernet/broadcom/bnxt/bnxt.h #define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK) reg 1395 drivers/net/ethernet/broadcom/bnxt/bnxt.h #define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK) reg 263 drivers/net/ethernet/broadcom/cnic.c static void cnic_ulp_ctl(struct cnic_dev *dev, int ulp_type, bool reg, int state) reg 272 drivers/net/ethernet/broadcom/cnic.c if (reg) { reg 925 drivers/net/ethernet/broadcom/cnic.c u32 j, reg, off, lo, hi; reg 932 drivers/net/ethernet/broadcom/cnic.c reg = cnic_reg_rd_ind(dev, off); reg 933 drivers/net/ethernet/broadcom/cnic.c lo = reg >> 16; reg 934 drivers/net/ethernet/broadcom/cnic.c hi = reg & 0xffff; reg 630 drivers/net/ethernet/broadcom/genet/bcmgenet.c u32 reg; reg 634 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i); reg 635 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~DMA_TIMEOUT_MASK; reg 636 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= DIV_ROUND_UP(usecs * 1000, 8192); reg 637 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i); reg 1022 drivers/net/ethernet/broadcom/genet/bcmgenet.c u32 reg; reg 1029 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); reg 1031 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= EEE_EN; reg 1033 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~EEE_EN; reg 1034 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); reg 1037 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_readl(priv->base + off); reg 1039 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= TBUF_EEE_EN | TBUF_PM_EN; reg 1041 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); reg 1042 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_writel(reg, priv->base + off); reg 1045 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); reg 1047 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= RBUF_EEE_EN | RBUF_PM_EN; reg 1049 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); reg 1050 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); reg 1137 drivers/net/ethernet/broadcom/genet/bcmgenet.c u32 reg; reg 1151 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); reg 1153 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= EXT_PWR_DOWN_PHY_EN | reg 1160 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= EXT_PWR_DOWN_PHY; reg 1162 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); reg 1163 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); reg 1178 drivers/net/ethernet/broadcom/genet/bcmgenet.c u32 reg; reg 1183 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); reg 1187 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); reg 1189 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~(EXT_PWR_DOWN_PHY_EN | reg 1195 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= EXT_PHY_RESET; reg 1196 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); reg 1199 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~EXT_PHY_RESET; reg 1201 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~EXT_PWR_DOWN_PHY; reg 1202 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= EXT_PWR_DN_EN_LD; reg 1204 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); reg 1211 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= EXT_PWR_DN_EN_LD; reg 1212 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); reg 1975 drivers/net/ethernet/broadcom/genet/bcmgenet.c u32 reg; reg 1977 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_umac_readl(priv, UMAC_CMD); reg 1979 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= mask; reg 1981 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~mask; reg 1982 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_umac_writel(priv, reg, UMAC_CMD); reg 2036 drivers/net/ethernet/broadcom/genet/bcmgenet.c u32 reg; reg 2052 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); reg 2053 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= RBUF_ALIGN_2B; reg 2054 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); reg 2063 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_bp_mc_get(priv); reg 2064 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= BIT(priv->hw_params->bp_in_en_shift); reg 2068 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= priv->hw_params->bp_in_mask; reg 2070 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~priv->hw_params->bp_in_mask; reg 2071 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_bp_mc_set(priv, reg); reg 2456 drivers/net/ethernet/broadcom/genet/bcmgenet.c u32 reg; reg 2461 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_tdma_readl(priv, DMA_CTRL); reg 2462 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~DMA_EN; reg 2463 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_tdma_writel(priv, reg, DMA_CTRL); reg 2467 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_tdma_readl(priv, DMA_STATUS); reg 2468 drivers/net/ethernet/broadcom/genet/bcmgenet.c if (reg & DMA_DISABLED) reg 2483 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_rdma_readl(priv, DMA_CTRL); reg 2484 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~DMA_EN; reg 2485 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_rdma_writel(priv, reg, DMA_CTRL); reg 2490 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_rdma_readl(priv, DMA_STATUS); reg 2491 drivers/net/ethernet/broadcom/genet/bcmgenet.c if (reg & DMA_DISABLED) reg 2505 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_rdma_readl(priv, DMA_CTRL); reg 2506 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~dma_ctrl; reg 2507 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_rdma_writel(priv, reg, DMA_CTRL); reg 2512 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_tdma_readl(priv, DMA_CTRL); reg 2513 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~dma_ctrl; reg 2514 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_tdma_writel(priv, reg, DMA_CTRL); reg 2762 drivers/net/ethernet/broadcom/genet/bcmgenet.c u32 reg; reg 2764 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_rbuf_ctrl_get(priv); reg 2765 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= BIT(1); reg 2766 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_rbuf_ctrl_set(priv, reg); reg 2769 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~BIT(1); reg 2770 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_rbuf_ctrl_set(priv, reg); reg 2785 drivers/net/ethernet/broadcom/genet/bcmgenet.c u32 reg; reg 2790 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_tdma_readl(priv, DMA_CTRL); reg 2791 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~dma_ctrl; reg 2792 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_tdma_writel(priv, reg, DMA_CTRL); reg 2794 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_rdma_readl(priv, DMA_CTRL); reg 2795 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~dma_ctrl; reg 2796 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_rdma_writel(priv, reg, DMA_CTRL); reg 2807 drivers/net/ethernet/broadcom/genet/bcmgenet.c u32 reg; reg 2809 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_rdma_readl(priv, DMA_CTRL); reg 2810 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= dma_ctrl; reg 2811 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_rdma_writel(priv, reg, DMA_CTRL); reg 2813 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_tdma_readl(priv, DMA_CTRL); reg 2814 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= dma_ctrl; reg 2815 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_tdma_writel(priv, reg, DMA_CTRL); reg 2871 drivers/net/ethernet/broadcom/genet/bcmgenet.c u32 reg; reg 2891 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_umac_readl(priv, UMAC_CMD); reg 2892 drivers/net/ethernet/broadcom/genet/bcmgenet.c priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); reg 2897 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); reg 2898 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= EXT_ENERGY_DET_MASK; reg 2899 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); reg 3109 drivers/net/ethernet/broadcom/genet/bcmgenet.c u32 reg; reg 3123 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_umac_readl(priv, UMAC_CMD); reg 3126 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= CMD_PROMISC; reg 3127 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_umac_writel(priv, reg, UMAC_CMD); reg 3131 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~CMD_PROMISC; reg 3132 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_umac_writel(priv, reg, UMAC_CMD); reg 3151 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter); reg 3152 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); reg 3325 drivers/net/ethernet/broadcom/genet/bcmgenet.c u32 reg; reg 3352 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); reg 3353 drivers/net/ethernet/broadcom/genet/bcmgenet.c major = (reg >> 24 & 0x0f); reg 3368 drivers/net/ethernet/broadcom/genet/bcmgenet.c major, (reg >> 16) & 0x0f, reg & 0xffff); reg 3382 drivers/net/ethernet/broadcom/genet/bcmgenet.c gphy_rev = reg & 0xffff; reg 3616 drivers/net/ethernet/broadcom/genet/bcmgenet.c u32 reg; reg 3649 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); reg 3650 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= EXT_ENERGY_DET_MASK; reg 3651 drivers/net/ethernet/broadcom/genet/bcmgenet.c bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); reg 44 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c u32 reg; reg 51 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg = bcmgenet_umac_readl(priv, UMAC_MPD_PW_MS); reg 52 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c put_unaligned_be16(reg, &wol->sopass[0]); reg 53 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg = bcmgenet_umac_readl(priv, UMAC_MPD_PW_LS); reg 54 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c put_unaligned_be32(reg, &wol->sopass[2]); reg 65 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c u32 reg; reg 73 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg = bcmgenet_umac_readl(priv, UMAC_MPD_CTRL); reg 79 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg |= MPD_PW_EN; reg 81 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg &= ~MPD_PW_EN; reg 83 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c bcmgenet_umac_writel(priv, reg, UMAC_MPD_CTRL); reg 128 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c u32 reg; reg 136 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg = bcmgenet_umac_readl(priv, UMAC_CMD); reg 137 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg &= ~CMD_RX_EN; reg 138 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c bcmgenet_umac_writel(priv, reg, UMAC_CMD); reg 141 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg = bcmgenet_umac_readl(priv, UMAC_MPD_CTRL); reg 142 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg |= MPD_EN; reg 143 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c bcmgenet_umac_writel(priv, reg, UMAC_MPD_CTRL); reg 148 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg = bcmgenet_umac_readl(priv, UMAC_MPD_CTRL); reg 149 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg &= ~MPD_EN; reg 150 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c bcmgenet_umac_writel(priv, reg, UMAC_MPD_CTRL); reg 158 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg = bcmgenet_umac_readl(priv, UMAC_CMD); reg 160 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg |= CMD_CRC_FWD; reg 163 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg |= CMD_RX_EN; reg 164 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c bcmgenet_umac_writel(priv, reg, UMAC_CMD); reg 167 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); reg 168 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg &= ~EXT_ENERGY_DET_MASK; reg 169 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); reg 178 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c u32 reg; reg 185 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg = bcmgenet_umac_readl(priv, UMAC_MPD_CTRL); reg 186 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c if (!(reg & MPD_EN)) reg 188 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg &= ~MPD_EN; reg 189 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c bcmgenet_umac_writel(priv, reg, UMAC_MPD_CTRL); reg 192 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg = bcmgenet_umac_readl(priv, UMAC_CMD); reg 193 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c reg &= ~CMD_CRC_FWD; reg 194 drivers/net/ethernet/broadcom/genet/bcmgenet_wol.c bcmgenet_umac_writel(priv, reg, UMAC_CMD); reg 35 drivers/net/ethernet/broadcom/genet/bcmmii.c u32 reg, cmd_bits = 0; reg 88 drivers/net/ethernet/broadcom/genet/bcmmii.c reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); reg 89 drivers/net/ethernet/broadcom/genet/bcmmii.c reg &= ~OOB_DISABLE; reg 90 drivers/net/ethernet/broadcom/genet/bcmmii.c reg |= RGMII_LINK; reg 91 drivers/net/ethernet/broadcom/genet/bcmmii.c bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); reg 93 drivers/net/ethernet/broadcom/genet/bcmmii.c reg = bcmgenet_umac_readl(priv, UMAC_CMD); reg 94 drivers/net/ethernet/broadcom/genet/bcmmii.c reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | reg 97 drivers/net/ethernet/broadcom/genet/bcmmii.c reg |= cmd_bits; reg 98 drivers/net/ethernet/broadcom/genet/bcmmii.c bcmgenet_umac_writel(priv, reg, UMAC_CMD); reg 116 drivers/net/ethernet/broadcom/genet/bcmmii.c u32 reg; reg 120 drivers/net/ethernet/broadcom/genet/bcmmii.c reg = bcmgenet_umac_readl(priv, UMAC_MODE); reg 121 drivers/net/ethernet/broadcom/genet/bcmmii.c status->link = !!(reg & MODE_LINK_STATUS); reg 130 drivers/net/ethernet/broadcom/genet/bcmmii.c u32 reg = 0; reg 134 drivers/net/ethernet/broadcom/genet/bcmmii.c reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); reg 136 drivers/net/ethernet/broadcom/genet/bcmmii.c reg &= ~EXT_CK25_DIS; reg 137 drivers/net/ethernet/broadcom/genet/bcmmii.c bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); reg 140 drivers/net/ethernet/broadcom/genet/bcmmii.c reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN); reg 141 drivers/net/ethernet/broadcom/genet/bcmmii.c reg |= EXT_GPHY_RESET; reg 142 drivers/net/ethernet/broadcom/genet/bcmmii.c bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); reg 145 drivers/net/ethernet/broadcom/genet/bcmmii.c reg &= ~EXT_GPHY_RESET; reg 147 drivers/net/ethernet/broadcom/genet/bcmmii.c reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | reg 149 drivers/net/ethernet/broadcom/genet/bcmmii.c bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); reg 151 drivers/net/ethernet/broadcom/genet/bcmmii.c reg |= EXT_CK25_DIS; reg 153 drivers/net/ethernet/broadcom/genet/bcmmii.c bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); reg 162 drivers/net/ethernet/broadcom/genet/bcmmii.c u32 reg; reg 166 drivers/net/ethernet/broadcom/genet/bcmmii.c reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL); reg 167 drivers/net/ethernet/broadcom/genet/bcmmii.c reg |= LED_ACT_SOURCE_MAC; reg 168 drivers/net/ethernet/broadcom/genet/bcmmii.c bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL); reg 186 drivers/net/ethernet/broadcom/genet/bcmmii.c u32 reg; reg 189 drivers/net/ethernet/broadcom/genet/bcmmii.c reg = bcmgenet_umac_readl(priv, UMAC_CMD); reg 190 drivers/net/ethernet/broadcom/genet/bcmmii.c if (reg & CMD_SW_RESET) { reg 210 drivers/net/ethernet/broadcom/genet/bcmmii.c reg &= ~(CMD_SW_RESET | CMD_LCL_LOOP_EN); reg 211 drivers/net/ethernet/broadcom/genet/bcmmii.c bcmgenet_umac_writel(priv, reg, UMAC_CMD); reg 293 drivers/net/ethernet/broadcom/genet/bcmmii.c reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); reg 294 drivers/net/ethernet/broadcom/genet/bcmmii.c reg |= id_mode_dis; reg 296 drivers/net/ethernet/broadcom/genet/bcmmii.c reg |= RGMII_MODE_EN_V123; reg 298 drivers/net/ethernet/broadcom/genet/bcmmii.c reg |= RGMII_MODE_EN; reg 299 drivers/net/ethernet/broadcom/genet/bcmmii.c bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); reg 1386 drivers/net/ethernet/broadcom/sb1250-mac.c uint64_t reg; reg 1487 drivers/net/ethernet/broadcom/sb1250-mac.c reg = sbmac_addr2reg(s->sbm_hwaddr); reg 1490 drivers/net/ethernet/broadcom/sb1250-mac.c __raw_writeq(reg, port); reg 1493 drivers/net/ethernet/broadcom/sb1250-mac.c __raw_writeq(reg, port); reg 1687 drivers/net/ethernet/broadcom/sb1250-mac.c uint64_t reg; reg 1693 drivers/net/ethernet/broadcom/sb1250-mac.c reg = __raw_readq(sc->sbm_rxfilter); reg 1694 drivers/net/ethernet/broadcom/sb1250-mac.c reg |= M_MAC_ALLPKT_EN; reg 1695 drivers/net/ethernet/broadcom/sb1250-mac.c __raw_writeq(reg, sc->sbm_rxfilter); reg 1698 drivers/net/ethernet/broadcom/sb1250-mac.c reg = __raw_readq(sc->sbm_rxfilter); reg 1699 drivers/net/ethernet/broadcom/sb1250-mac.c reg &= ~M_MAC_ALLPKT_EN; reg 1700 drivers/net/ethernet/broadcom/sb1250-mac.c __raw_writeq(reg, sc->sbm_rxfilter); reg 1718 drivers/net/ethernet/broadcom/sb1250-mac.c uint64_t reg; reg 1721 drivers/net/ethernet/broadcom/sb1250-mac.c reg = __raw_readq(sc->sbm_rxfilter); reg 1722 drivers/net/ethernet/broadcom/sb1250-mac.c reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15); reg 1723 drivers/net/ethernet/broadcom/sb1250-mac.c __raw_writeq(reg, sc->sbm_rxfilter); reg 1750 drivers/net/ethernet/broadcom/sb1250-mac.c uint64_t reg = 0; reg 1754 drivers/net/ethernet/broadcom/sb1250-mac.c reg |= (uint64_t) *(--ptr); reg 1755 drivers/net/ethernet/broadcom/sb1250-mac.c reg <<= 8; reg 1756 drivers/net/ethernet/broadcom/sb1250-mac.c reg |= (uint64_t) *(--ptr); reg 1757 drivers/net/ethernet/broadcom/sb1250-mac.c reg <<= 8; reg 1758 drivers/net/ethernet/broadcom/sb1250-mac.c reg |= (uint64_t) *(--ptr); reg 1759 drivers/net/ethernet/broadcom/sb1250-mac.c reg <<= 8; reg 1760 drivers/net/ethernet/broadcom/sb1250-mac.c reg |= (uint64_t) *(--ptr); reg 1761 drivers/net/ethernet/broadcom/sb1250-mac.c reg <<= 8; reg 1762 drivers/net/ethernet/broadcom/sb1250-mac.c reg |= (uint64_t) *(--ptr); reg 1763 drivers/net/ethernet/broadcom/sb1250-mac.c reg <<= 8; reg 1764 drivers/net/ethernet/broadcom/sb1250-mac.c reg |= (uint64_t) *(--ptr); reg 1766 drivers/net/ethernet/broadcom/sb1250-mac.c return reg; reg 2060 drivers/net/ethernet/broadcom/sb1250-mac.c uint64_t reg; reg 2086 drivers/net/ethernet/broadcom/sb1250-mac.c reg = __raw_readq(sc->sbm_rxfilter); reg 2087 drivers/net/ethernet/broadcom/sb1250-mac.c reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN); reg 2088 drivers/net/ethernet/broadcom/sb1250-mac.c __raw_writeq(reg, sc->sbm_rxfilter); reg 2095 drivers/net/ethernet/broadcom/sb1250-mac.c reg = __raw_readq(sc->sbm_rxfilter); reg 2096 drivers/net/ethernet/broadcom/sb1250-mac.c reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN); reg 2097 drivers/net/ethernet/broadcom/sb1250-mac.c __raw_writeq(reg, sc->sbm_rxfilter); reg 2115 drivers/net/ethernet/broadcom/sb1250-mac.c reg = sbmac_addr2reg(ha->addr); reg 2117 drivers/net/ethernet/broadcom/sb1250-mac.c __raw_writeq(reg, port); reg 2127 drivers/net/ethernet/broadcom/sb1250-mac.c reg = __raw_readq(sc->sbm_rxfilter); reg 2128 drivers/net/ethernet/broadcom/sb1250-mac.c reg |= M_MAC_MCAST_EN; reg 2129 drivers/net/ethernet/broadcom/sb1250-mac.c __raw_writeq(reg, sc->sbm_rxfilter); reg 618 drivers/net/ethernet/broadcom/tg3.c #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) reg 619 drivers/net/ethernet/broadcom/tg3.c #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) reg 620 drivers/net/ethernet/broadcom/tg3.c #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) reg 621 drivers/net/ethernet/broadcom/tg3.c #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) reg 622 drivers/net/ethernet/broadcom/tg3.c #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) reg 624 drivers/net/ethernet/broadcom/tg3.c #define tw32(reg, val) tp->write32(tp, reg, val) reg 625 drivers/net/ethernet/broadcom/tg3.c #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0) reg 626 drivers/net/ethernet/broadcom/tg3.c #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us)) reg 627 drivers/net/ethernet/broadcom/tg3.c #define tr32(reg) tp->read32(tp, reg) reg 1121 drivers/net/ethernet/broadcom/tg3.c static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, reg 1140 drivers/net/ethernet/broadcom/tg3.c frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & reg 1175 drivers/net/ethernet/broadcom/tg3.c static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) reg 1177 drivers/net/ethernet/broadcom/tg3.c return __tg3_readphy(tp, tp->phy_addr, reg, val); reg 1180 drivers/net/ethernet/broadcom/tg3.c static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, reg 1188 drivers/net/ethernet/broadcom/tg3.c (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL)) reg 1201 drivers/net/ethernet/broadcom/tg3.c frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & reg 1234 drivers/net/ethernet/broadcom/tg3.c static int tg3_writephy(struct tg3 *tp, int reg, u32 val) reg 1236 drivers/net/ethernet/broadcom/tg3.c return __tg3_writephy(tp, tp->phy_addr, reg, val); reg 1285 drivers/net/ethernet/broadcom/tg3.c static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) reg 1289 drivers/net/ethernet/broadcom/tg3.c err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); reg 1296 drivers/net/ethernet/broadcom/tg3.c static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) reg 1300 drivers/net/ethernet/broadcom/tg3.c err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); reg 1307 drivers/net/ethernet/broadcom/tg3.c static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) reg 1312 drivers/net/ethernet/broadcom/tg3.c (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) | reg 1320 drivers/net/ethernet/broadcom/tg3.c static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) reg 1322 drivers/net/ethernet/broadcom/tg3.c if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC) reg 1325 drivers/net/ethernet/broadcom/tg3.c return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); reg 1349 drivers/net/ethernet/broadcom/tg3.c static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val) reg 1352 drivers/net/ethernet/broadcom/tg3.c reg | val | MII_TG3_MISC_SHDW_WREN); reg 1386 drivers/net/ethernet/broadcom/tg3.c static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) reg 1393 drivers/net/ethernet/broadcom/tg3.c if (__tg3_readphy(tp, mii_id, reg, &val)) reg 1401 drivers/net/ethernet/broadcom/tg3.c static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) reg 1408 drivers/net/ethernet/broadcom/tg3.c if (__tg3_writephy(tp, mii_id, reg, val)) reg 1511 drivers/net/ethernet/broadcom/tg3.c u32 reg; reg 1559 drivers/net/ethernet/broadcom/tg3.c if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) reg 1671 drivers/net/ethernet/broadcom/tg3.c u32 reg, val; reg 1674 drivers/net/ethernet/broadcom/tg3.c if (!tg3_readphy(tp, MII_BMCR, ®)) reg 1675 drivers/net/ethernet/broadcom/tg3.c val = reg << 16; reg 1676 drivers/net/ethernet/broadcom/tg3.c if (!tg3_readphy(tp, MII_BMSR, ®)) reg 1677 drivers/net/ethernet/broadcom/tg3.c val |= (reg & 0xffff); reg 1681 drivers/net/ethernet/broadcom/tg3.c if (!tg3_readphy(tp, MII_ADVERTISE, ®)) reg 1682 drivers/net/ethernet/broadcom/tg3.c val = reg << 16; reg 1683 drivers/net/ethernet/broadcom/tg3.c if (!tg3_readphy(tp, MII_LPA, ®)) reg 1684 drivers/net/ethernet/broadcom/tg3.c val |= (reg & 0xffff); reg 1689 drivers/net/ethernet/broadcom/tg3.c if (!tg3_readphy(tp, MII_CTRL1000, ®)) reg 1690 drivers/net/ethernet/broadcom/tg3.c val = reg << 16; reg 1691 drivers/net/ethernet/broadcom/tg3.c if (!tg3_readphy(tp, MII_STAT1000, ®)) reg 1692 drivers/net/ethernet/broadcom/tg3.c val |= (reg & 0xffff); reg 1696 drivers/net/ethernet/broadcom/tg3.c if (!tg3_readphy(tp, MII_PHYADDR, ®)) reg 1697 drivers/net/ethernet/broadcom/tg3.c val = reg << 16; reg 2231 drivers/net/ethernet/broadcom/tg3.c u32 reg; reg 2243 drivers/net/ethernet/broadcom/tg3.c reg = MII_TG3_MISC_SHDW_SCR5_LPED | reg 2248 drivers/net/ethernet/broadcom/tg3.c reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; reg 2250 drivers/net/ethernet/broadcom/tg3.c tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg); reg 2253 drivers/net/ethernet/broadcom/tg3.c reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS; reg 2255 drivers/net/ethernet/broadcom/tg3.c reg |= MII_TG3_MISC_SHDW_APD_ENABLE; reg 2257 drivers/net/ethernet/broadcom/tg3.c tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg); reg 2272 drivers/net/ethernet/broadcom/tg3.c u32 reg = MII_TG3_FET_SHDW_MISCCTRL; reg 2276 drivers/net/ethernet/broadcom/tg3.c if (!tg3_readphy(tp, reg, &phy)) { reg 2281 drivers/net/ethernet/broadcom/tg3.c tg3_writephy(tp, reg, phy); reg 4964 drivers/net/ethernet/broadcom/tg3.c u32 reg, bit; reg 4967 drivers/net/ethernet/broadcom/tg3.c reg = MII_TG3_FET_GEN_STAT; reg 4970 drivers/net/ethernet/broadcom/tg3.c reg = MII_TG3_EXT_STAT; reg 4974 drivers/net/ethernet/broadcom/tg3.c if (!tg3_readphy(tp, reg, &val) && (val & bit)) reg 9448 drivers/net/ethernet/broadcom/tg3.c u32 reg; reg 9450 drivers/net/ethernet/broadcom/tg3.c reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; reg 9451 drivers/net/ethernet/broadcom/tg3.c tw32(reg, ec->tx_coalesce_usecs); reg 9452 drivers/net/ethernet/broadcom/tg3.c reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; reg 9453 drivers/net/ethernet/broadcom/tg3.c tw32(reg, ec->tx_max_coalesced_frames); reg 9454 drivers/net/ethernet/broadcom/tg3.c reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; reg 9455 drivers/net/ethernet/broadcom/tg3.c tw32(reg, ec->tx_max_coalesced_frames_irq); reg 9483 drivers/net/ethernet/broadcom/tg3.c u32 reg; reg 9485 drivers/net/ethernet/broadcom/tg3.c reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; reg 9486 drivers/net/ethernet/broadcom/tg3.c tw32(reg, ec->rx_coalesce_usecs); reg 9487 drivers/net/ethernet/broadcom/tg3.c reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; reg 9488 drivers/net/ethernet/broadcom/tg3.c tw32(reg, ec->rx_max_coalesced_frames); reg 9489 drivers/net/ethernet/broadcom/tg3.c reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; reg 9490 drivers/net/ethernet/broadcom/tg3.c tw32(reg, ec->rx_max_coalesced_frames_irq); reg 9717 drivers/net/ethernet/broadcom/tg3.c u32 reg; reg 9721 drivers/net/ethernet/broadcom/tg3.c reg = 0xffffffff; reg 9724 drivers/net/ethernet/broadcom/tg3.c reg ^= buf[j]; reg 9727 drivers/net/ethernet/broadcom/tg3.c tmp = reg & 0x01; reg 9729 drivers/net/ethernet/broadcom/tg3.c reg >>= 1; reg 9732 drivers/net/ethernet/broadcom/tg3.c reg ^= CRC32_POLY_LE; reg 9736 drivers/net/ethernet/broadcom/tg3.c return ~reg; reg 9849 drivers/net/ethernet/broadcom/tg3.c u32 reg = MAC_RSS_INDIR_TBL_0; reg 9858 drivers/net/ethernet/broadcom/tg3.c tw32(reg, val); reg 9859 drivers/net/ethernet/broadcom/tg3.c reg += 4; reg 16096 drivers/net/ethernet/broadcom/tg3.c u32 reg; reg 16114 drivers/net/ethernet/broadcom/tg3.c reg = TG3PCI_GEN2_PRODID_ASICREV; reg 16125 drivers/net/ethernet/broadcom/tg3.c reg = TG3PCI_GEN15_PRODID_ASICREV; reg 16127 drivers/net/ethernet/broadcom/tg3.c reg = TG3PCI_PRODID_ASICREV; reg 16129 drivers/net/ethernet/broadcom/tg3.c pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id); reg 685 drivers/net/ethernet/cadence/macb.h #define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg) reg 686 drivers/net/ethernet/cadence/macb.h #define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value)) reg 687 drivers/net/ethernet/cadence/macb.h #define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg) reg 688 drivers/net/ethernet/cadence/macb.h #define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value)) reg 689 drivers/net/ethernet/cadence/macb.h #define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg) reg 690 drivers/net/ethernet/cadence/macb.h #define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value)) reg 691 drivers/net/ethernet/cadence/macb.h #define gem_readl_n(port, reg, idx) (port)->macb_reg_readl((port), GEM_##reg + idx * 4) reg 692 drivers/net/ethernet/cadence/macb.h #define gem_writel_n(port, reg, idx, value) (port)->macb_reg_writel((port), GEM_##reg + idx * 4, (value)) reg 43 drivers/net/ethernet/cadence/macb_main.c void __iomem *reg; reg 455 drivers/net/ethernet/cadence/macb_main.c u32 reg; reg 457 drivers/net/ethernet/cadence/macb_main.c reg = macb_readl(bp, NCFGR); reg 458 drivers/net/ethernet/cadence/macb_main.c reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); reg 460 drivers/net/ethernet/cadence/macb_main.c reg &= ~GEM_BIT(GBE); reg 463 drivers/net/ethernet/cadence/macb_main.c reg |= MACB_BIT(FD); reg 465 drivers/net/ethernet/cadence/macb_main.c reg |= MACB_BIT(SPD); reg 468 drivers/net/ethernet/cadence/macb_main.c reg |= GEM_BIT(GBE); reg 470 drivers/net/ethernet/cadence/macb_main.c macb_or_gem_writel(bp, NCFGR, reg); reg 3480 drivers/net/ethernet/cadence/macb_main.c u32 val, reg; reg 3582 drivers/net/ethernet/cadence/macb_main.c reg = gem_readl(bp, DCFG8); reg 3583 drivers/net/ethernet/cadence/macb_main.c bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3), reg 3584 drivers/net/ethernet/cadence/macb_main.c GEM_BFEXT(T2SCR, reg)); reg 3587 drivers/net/ethernet/cadence/macb_main.c if (GEM_BFEXT(SCR2ETH, reg) > 0) { reg 3589 drivers/net/ethernet/cadence/macb_main.c reg = 0; reg 3590 drivers/net/ethernet/cadence/macb_main.c reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg); reg 3591 drivers/net/ethernet/cadence/macb_main.c gem_writel_n(bp, ETHT, SCRT2_ETHT, reg); reg 3946 drivers/net/ethernet/cadence/macb_main.c u32 reg; reg 3960 drivers/net/ethernet/cadence/macb_main.c reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG); reg 3962 drivers/net/ethernet/cadence/macb_main.c reg |= MACB_BIT(RM9200_RMII); reg 3964 drivers/net/ethernet/cadence/macb_main.c macb_writel(bp, NCFGR, reg); reg 4005 drivers/net/ethernet/cadence/macb_main.c iowrite32(1, mgmt->reg); reg 4007 drivers/net/ethernet/cadence/macb_main.c iowrite32(0, mgmt->reg); reg 4057 drivers/net/ethernet/cadence/macb_main.c mgmt->reg = devm_platform_ioremap_resource(pdev, 1); reg 4058 drivers/net/ethernet/cadence/macb_main.c if (IS_ERR(mgmt->reg)) reg 4059 drivers/net/ethernet/cadence/macb_main.c return PTR_ERR(mgmt->reg); reg 32 drivers/net/ethernet/calxeda/xgmac.c #define XGMAC_ADDR_HIGH(reg) (0x00000040 + ((reg) * 8)) reg 33 drivers/net/ethernet/calxeda/xgmac.c #define XGMAC_ADDR_LOW(reg) (0x00000044 + ((reg) * 8)) reg 508 drivers/net/ethernet/calxeda/xgmac.c u32 reg = readl(ioaddr + XGMAC_OMR); reg 509 drivers/net/ethernet/calxeda/xgmac.c writel(reg | XGMAC_OMR_FTF, ioaddr + XGMAC_OMR); reg 646 drivers/net/ethernet/calxeda/xgmac.c u32 reg; reg 663 drivers/net/ethernet/calxeda/xgmac.c reg = readl(priv->base + XGMAC_OMR); reg 664 drivers/net/ethernet/calxeda/xgmac.c reg |= XGMAC_OMR_EFC; reg 665 drivers/net/ethernet/calxeda/xgmac.c writel(reg, priv->base + XGMAC_OMR); reg 669 drivers/net/ethernet/calxeda/xgmac.c reg = readl(priv->base + XGMAC_OMR); reg 670 drivers/net/ethernet/calxeda/xgmac.c reg &= ~XGMAC_OMR_EFC; reg 671 drivers/net/ethernet/calxeda/xgmac.c writel(reg, priv->base + XGMAC_OMR); reg 906 drivers/net/ethernet/calxeda/xgmac.c u32 reg, value; reg 916 drivers/net/ethernet/calxeda/xgmac.c reg = readl(priv->base + XGMAC_DMA_CONTROL); reg 917 drivers/net/ethernet/calxeda/xgmac.c writel(reg & ~DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL); reg 927 drivers/net/ethernet/calxeda/xgmac.c writel(reg | DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL); reg 1276 drivers/net/ethernet/calxeda/xgmac.c int reg = 1; reg 1301 drivers/net/ethernet/calxeda/xgmac.c xgmac_set_mac_addr(ioaddr, ha->addr, reg); reg 1302 drivers/net/ethernet/calxeda/xgmac.c reg++; reg 1311 drivers/net/ethernet/calxeda/xgmac.c if ((netdev_mc_count(dev) + reg - 1) > priv->max_macs) { reg 1326 drivers/net/ethernet/calxeda/xgmac.c xgmac_set_mac_addr(ioaddr, ha->addr, reg); reg 1327 drivers/net/ethernet/calxeda/xgmac.c reg++; reg 1332 drivers/net/ethernet/calxeda/xgmac.c for (i = reg; i <= priv->max_macs; i++) reg 535 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c u32 reg; reg 543 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c reg = CN6XXX_SLI_PKT_TIME_INT_ENB; reg 544 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c value = octeon_read_csr(oct, reg); reg 546 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c octeon_write_csr(oct, reg, value); reg 547 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c reg = CN6XXX_SLI_PKT_CNT_INT_ENB; reg 548 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c value = octeon_read_csr(oct, reg); reg 550 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c octeon_write_csr(oct, reg, value); reg 2539 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c u32 reg; reg 2549 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_PKT_MAC_RINFO64(oct->pcie_port, oct->pf_num); reg 2552 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, oct->pcie_port, oct->pf_num, reg 2553 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c (u64)octeon_read_csr64(oct, reg)); reg 2556 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num); reg 2559 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, oct->pcie_port, oct->pf_num, reg 2560 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c (u64)octeon_read_csr64(oct, reg)); reg 2563 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num); reg 2566 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, oct->pcie_port, oct->pf_num, reg 2567 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c (u64)octeon_read_csr64(oct, reg)); reg 2570 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = 0x29120; reg 2571 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c len += sprintf(s + len, "\n[%08x] (SLI_PKT_MEM_CTL): %016llx\n", reg, reg 2572 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c (u64)octeon_read_csr64(oct, reg)); reg 2575 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = 0x27300 + oct->pcie_port * CN23XX_MAC_INT_OFFSET + reg 2578 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c s + len, "\n[%08x] (SLI_MAC%d_PF%d_PKT_VF_INT): %016llx\n", reg, reg 2579 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c oct->pcie_port, oct->pf_num, (u64)octeon_read_csr64(oct, reg)); reg 2582 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = 0x27200 + oct->pcie_port * CN23XX_MAC_INT_OFFSET + reg 2586 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, oct->pcie_port, oct->pf_num, reg 2587 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c (u64)octeon_read_csr64(oct, reg)); reg 2590 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_PKT_CNT_INT; reg 2591 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c len += sprintf(s + len, "\n[%08x] (SLI_PKT_CNT_INT): %016llx\n", reg, reg 2592 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c (u64)octeon_read_csr64(oct, reg)); reg 2595 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_PKT_TIME_INT; reg 2596 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c len += sprintf(s + len, "\n[%08x] (SLI_PKT_TIME_INT): %016llx\n", reg, reg 2597 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c (u64)octeon_read_csr64(oct, reg)); reg 2600 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = 0x29160; reg 2601 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c len += sprintf(s + len, "\n[%08x] (SLI_PKT_INT): %016llx\n", reg, reg 2602 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c (u64)octeon_read_csr64(oct, reg)); reg 2605 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_OQ_WMARK; reg 2607 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, (u64)octeon_read_csr64(oct, reg)); reg 2610 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_PKT_IOQ_RING_RST; reg 2611 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c len += sprintf(s + len, "\n[%08x] (SLI_PKT_RING_RST): %016llx\n", reg, reg 2612 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c (u64)octeon_read_csr64(oct, reg)); reg 2615 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_GBL_CONTROL; reg 2617 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c "\n[%08x] (SLI_PKT_GBL_CONTROL): %016llx\n", reg, reg 2618 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c (u64)octeon_read_csr64(oct, reg)); reg 2621 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = 0x29220; reg 2623 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, (u64)octeon_read_csr64(oct, reg)); reg 2628 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_OUT_BP_EN_W1S; reg 2631 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, (u64)octeon_read_csr64(oct, reg)); reg 2634 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_OUT_BP_EN2_W1S; reg 2637 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, (u64)octeon_read_csr64(oct, reg)); reg 2641 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_OQ_BUFF_INFO_SIZE(i); reg 2644 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2649 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_IQ_INSTR_COUNT64(i); reg 2652 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2657 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_OQ_PKTS_CREDIT(i); reg 2660 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2665 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_OQ_SIZE(i); reg 2668 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2673 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_OQ_PKT_CONTROL(i); reg 2677 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2682 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_OQ_BASE_ADDR64(i); reg 2685 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2690 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_OQ_PKT_INT_LEVELS(i); reg 2693 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2698 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_OQ_PKTS_SENT(i); reg 2700 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2705 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = 0x100c0 + i * CN23XX_OQ_OFFSET; reg 2708 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2712 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_IQ_PKT_CONTROL64(i); reg 2716 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2721 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_IQ_BASE_ADDR64(i); reg 2724 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c "\n[%08x] (SLI_PKT%d_INSTR_BADDR): %016llx\n", reg, reg 2725 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c i, (u64)octeon_read_csr64(oct, reg)); reg 2730 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_IQ_DOORBELL(i); reg 2734 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2739 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_IQ_SIZE(i); reg 2743 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2748 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_SLI_IQ_INSTR_COUNT64(i); reg 2751 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2760 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c u32 reg; reg 2768 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_VF_SLI_OQ_BUFF_INFO_SIZE(i); reg 2771 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2775 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_VF_SLI_IQ_INSTR_COUNT64(i); reg 2778 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2782 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_VF_SLI_OQ_PKTS_CREDIT(i); reg 2785 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2789 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_VF_SLI_OQ_SIZE(i); reg 2792 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2796 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_VF_SLI_OQ_PKT_CONTROL(i); reg 2799 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2803 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_VF_SLI_OQ_BASE_ADDR64(i); reg 2806 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2810 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(i); reg 2813 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2817 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_VF_SLI_OQ_PKTS_SENT(i); reg 2819 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2823 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = 0x100c0 + i * CN23XX_VF_OQ_OFFSET; reg 2826 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2830 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = 0x100d0 + i * CN23XX_VF_IQ_OFFSET; reg 2833 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2837 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_VF_SLI_IQ_PKT_CONTROL64(i); reg 2840 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2844 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_VF_SLI_IQ_BASE_ADDR64(i); reg 2847 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2851 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_VF_SLI_IQ_DOORBELL(i); reg 2854 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2858 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_VF_SLI_IQ_SIZE(i); reg 2861 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2865 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN23XX_VF_SLI_IQ_INSTR_COUNT64(i); reg 2868 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, (u64)octeon_read_csr64(oct, reg)); reg 2876 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c u32 reg; reg 2882 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN6XXX_WIN_WR_ADDR_LO; reg 2884 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c CN6XXX_WIN_WR_ADDR_LO, octeon_read_csr(oct, reg)); reg 2885 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN6XXX_WIN_WR_ADDR_HI; reg 2887 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c CN6XXX_WIN_WR_ADDR_HI, octeon_read_csr(oct, reg)); reg 2888 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN6XXX_WIN_RD_ADDR_LO; reg 2890 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c CN6XXX_WIN_RD_ADDR_LO, octeon_read_csr(oct, reg)); reg 2891 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN6XXX_WIN_RD_ADDR_HI; reg 2893 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c CN6XXX_WIN_RD_ADDR_HI, octeon_read_csr(oct, reg)); reg 2894 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN6XXX_WIN_WR_DATA_LO; reg 2896 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c CN6XXX_WIN_WR_DATA_LO, octeon_read_csr(oct, reg)); reg 2897 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN6XXX_WIN_WR_DATA_HI; reg 2899 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c CN6XXX_WIN_WR_DATA_HI, octeon_read_csr(oct, reg)); reg 2916 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN6XXX_SLI_OQ_PKTS_SENT(i); reg 2918 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, octeon_read_csr(oct, reg)); reg 2919 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN6XXX_SLI_OQ_PKTS_CREDIT(i); reg 2921 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, octeon_read_csr(oct, reg)); reg 2923 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN6XXX_SLI_OQ_INT_LEVEL_PKTS; reg 2925 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, octeon_read_csr(oct, reg)); reg 2926 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN6XXX_SLI_OQ_INT_LEVEL_TIME; reg 2928 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, octeon_read_csr(oct, reg)); reg 2932 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c u32 reg; reg 2934 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN6XXX_SLI_IQ_DOORBELL(i); reg 2936 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, octeon_read_csr(oct, reg)); reg 2937 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN6XXX_SLI_IQ_INSTR_COUNT(i); reg 2939 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg, i, octeon_read_csr(oct, reg)); reg 2947 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN6XXX_DMA_PKT_INT_LEVEL(0); reg 2949 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c CN6XXX_DMA_PKT_INT_LEVEL(0), octeon_read_csr(oct, reg)); reg 2950 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN6XXX_DMA_TIME_INT_LEVEL(0); reg 2953 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c octeon_read_csr(oct, reg)); reg 2958 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN6XXX_DMA_PKT_INT_LEVEL(1); reg 2961 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c octeon_read_csr(oct, reg)); reg 2962 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = CN6XXX_DMA_PKT_INT_LEVEL(1); reg 2965 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c octeon_read_csr(oct, reg)); reg 2972 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c reg = lio_pci_readq(oct, CN6XXX_BAR1_REG(i, oct->pcie_port)); reg 2974 drivers/net/ethernet/cavium/liquidio/lio_ethtool.c CN6XXX_BAR1_REG(i, oct->pcie_port), i, reg); reg 365 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c struct ethtool_regs *regs, void *reg) reg 368 drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c u64 *p = (u64 *)reg; reg 1670 drivers/net/ethernet/cavium/thunder/nicvf_main.c #define GET_RX_STATS(reg) \ reg 1671 drivers/net/ethernet/cavium/thunder/nicvf_main.c nicvf_reg_read(nic, NIC_VNIC_RX_STAT_0_13 | (reg << 3)) reg 1672 drivers/net/ethernet/cavium/thunder/nicvf_main.c #define GET_TX_STATS(reg) \ reg 1673 drivers/net/ethernet/cavium/thunder/nicvf_main.c nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | (reg << 3)) reg 32 drivers/net/ethernet/cavium/thunder/nicvf_queues.c u64 reg, int bit_pos, int bits, int val) reg 42 drivers/net/ethernet/cavium/thunder/nicvf_queues.c reg_val = nicvf_queue_reg_read(nic, reg, qidx); reg 48 drivers/net/ethernet/cavium/thunder/nicvf_queues.c netdev_err(nic->netdev, "Poll on reg 0x%llx failed\n", reg); reg 1815 drivers/net/ethernet/cavium/thunder/nicvf_queues.c #define GET_RQ_STATS(reg) \ reg 1817 drivers/net/ethernet/cavium/thunder/nicvf_queues.c (rq_idx << NIC_Q_NUM_SHIFT) | (reg << 3)) reg 1828 drivers/net/ethernet/cavium/thunder/nicvf_queues.c #define GET_SQ_STATS(reg) \ reg 1830 drivers/net/ethernet/cavium/thunder/nicvf_queues.c (sq_idx << NIC_Q_NUM_SHIFT) | (reg << 3)) reg 128 drivers/net/ethernet/cavium/thunder/thunder_bgx.c static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero) reg 134 drivers/net/ethernet/cavium/thunder/thunder_bgx.c reg_val = bgx_reg_read(bgx, lmac, reg); reg 110 drivers/net/ethernet/chelsio/cxgb/cphy.h static inline int cphy_mdio_read(struct cphy *cphy, int mmd, int reg, reg 114 drivers/net/ethernet/chelsio/cxgb/cphy.h reg); reg 119 drivers/net/ethernet/chelsio/cxgb/cphy.h static inline int cphy_mdio_write(struct cphy *cphy, int mmd, int reg, reg 123 drivers/net/ethernet/chelsio/cxgb/cphy.h reg, val); reg 126 drivers/net/ethernet/chelsio/cxgb/cphy.h static inline int simple_mdio_read(struct cphy *cphy, int reg, reg 129 drivers/net/ethernet/chelsio/cxgb/cphy.h return cphy_mdio_read(cphy, MDIO_DEVAD_NONE, reg, valp); reg 132 drivers/net/ethernet/chelsio/cxgb/cphy.h static inline int simple_mdio_write(struct cphy *cphy, int reg, reg 135 drivers/net/ethernet/chelsio/cxgb/cphy.h return cphy_mdio_write(cphy, MDIO_DEVAD_NONE, reg, val); reg 215 drivers/net/ethernet/chelsio/cxgb/fpga_defs.h #define MAC_REG_ADDR(idx, reg) (MAC_REG_BASE + (idx) * 128 + (reg)) reg 18 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c static void mdio_set_bit(struct cphy *cphy, int reg, u32 bitval) reg 22 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c (void) simple_mdio_read(cphy, reg, &val); reg 23 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c (void) simple_mdio_write(cphy, reg, val | bitval); reg 29 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c static void mdio_clear_bit(struct cphy *cphy, int reg, u32 bitval) reg 33 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c (void) simple_mdio_read(cphy, reg, &val); reg 34 drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.c (void) simple_mdio_write(cphy, reg, val & ~bitval); reg 94 drivers/net/ethernet/chelsio/cxgb/pm3393.c static int pmread(struct cmac *cmac, u32 reg, u32 * data32) reg 96 drivers/net/ethernet/chelsio/cxgb/pm3393.c t1_tpi_read(cmac->adapter, OFFSET(reg), data32); reg 100 drivers/net/ethernet/chelsio/cxgb/pm3393.c static int pmwrite(struct cmac *cmac, u32 reg, u32 data32) reg 102 drivers/net/ethernet/chelsio/cxgb/pm3393.c t1_tpi_write(cmac->adapter, OFFSET(reg), data32); reg 61 drivers/net/ethernet/chelsio/cxgb/subr.c static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity, reg 65 drivers/net/ethernet/chelsio/cxgb/subr.c u32 val = readl(adapter->regs + reg) & mask; reg 589 drivers/net/ethernet/chelsio/cxgb/vsc7326.c unsigned int reg; reg 593 drivers/net/ethernet/chelsio/cxgb/vsc7326.c #define HW_STAT(reg, stat_name) \ reg 594 drivers/net/ethernet/chelsio/cxgb/vsc7326.c { reg, (&((struct cmac_statistics *)NULL)->stat_name) - (u64 *)NULL } reg 623 drivers/net/ethernet/chelsio/cxgb/vsc7326.c rmon_update(mac, CRA(0x4, port, p->reg), stats + p->offset); reg 561 drivers/net/ethernet/chelsio/cxgb3/common.h static inline int t3_mdio_read(struct cphy *phy, int mmd, int reg, reg 564 drivers/net/ethernet/chelsio/cxgb3/common.h int rc = phy->mdio.mdio_read(phy->mdio.dev, phy->mdio.prtad, mmd, reg); reg 569 drivers/net/ethernet/chelsio/cxgb3/common.h static inline int t3_mdio_write(struct cphy *phy, int mmd, int reg, reg 573 drivers/net/ethernet/chelsio/cxgb3/common.h reg, val); reg 646 drivers/net/ethernet/chelsio/cxgb3/common.h int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, reg 648 drivers/net/ethernet/chelsio/cxgb3/common.h static inline int t3_wait_op_done(struct adapter *adapter, int reg, u32 mask, reg 651 drivers/net/ethernet/chelsio/cxgb3/common.h return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts, reg 654 drivers/net/ethernet/chelsio/cxgb3/common.h int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, reg 55 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, reg 59 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u32 val = t3_read_reg(adapter, reg); reg 328 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, reg 334 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c ret = t3_mdio_read(phy, mmd, reg, &val); reg 337 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c ret = t3_mdio_write(phy, mmd, reg, val | set); reg 1432 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c static int t3_handle_intr_status(struct adapter *adapter, unsigned int reg, reg 1438 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c unsigned int status = t3_read_reg(adapter, reg) & mask; reg 1455 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c t3_write_reg(adapter, reg, status); reg 2593 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c #define mem_region(adap, start, size, reg) \ reg 2594 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c t3_write_reg((adap), A_ ## reg, (start)); \ reg 266 drivers/net/ethernet/chelsio/cxgb3/xgmac.c unsigned int i, reg = mac->offset + A_XGM_RX_EXACT_MATCH_LOW_1; reg 268 drivers/net/ethernet/chelsio/cxgb3/xgmac.c for (i = 0; i < EXACT_ADDR_FILTERS; i++, reg += 8) { reg 269 drivers/net/ethernet/chelsio/cxgb3/xgmac.c u32 v = t3_read_reg(mac->adapter, reg); reg 270 drivers/net/ethernet/chelsio/cxgb3/xgmac.c t3_write_reg(mac->adapter, reg, v); reg 277 drivers/net/ethernet/chelsio/cxgb3/xgmac.c unsigned int i, reg = mac->offset + A_XGM_RX_EXACT_MATCH_HIGH_1; reg 279 drivers/net/ethernet/chelsio/cxgb3/xgmac.c for (i = 0; i < EXACT_ADDR_FILTERS; i++, reg += 8) { reg 280 drivers/net/ethernet/chelsio/cxgb3/xgmac.c u32 v = t3_read_reg(mac->adapter, reg); reg 281 drivers/net/ethernet/chelsio/cxgb3/xgmac.c t3_write_reg(mac->adapter, reg, v); reg 349 drivers/net/ethernet/chelsio/cxgb3/xgmac.c unsigned int thres, v, reg; reg 371 drivers/net/ethernet/chelsio/cxgb3/xgmac.c reg = adap->params.rev == T3_REV_B2 ? reg 375 drivers/net/ethernet/chelsio/cxgb3/xgmac.c if (t3_wait_op_done(adap, reg + mac->offset, reg 601 drivers/net/ethernet/chelsio/cxgb3/xgmac.c #define RMON_UPDATE(mac, name, reg) \ reg 602 drivers/net/ethernet/chelsio/cxgb3/xgmac.c (mac)->stats.name += (u64)RMON_READ(mac, A_XGM_STAT_##reg) reg 264 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c #define ulp_region(reg) do { \ reg 265 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c md->base = t4_read_reg(padap, ULP_ ## reg ## _LLIMIT_A);\ reg 266 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c (md++)->limit = t4_read_reg(padap, ULP_ ## reg ## _ULIMIT_A);\ reg 1578 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val); reg 1610 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h u32 t4_read_pcie_cfg4(struct adapter *adap, int reg); reg 1828 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h unsigned int mmd, unsigned int reg, u16 *valp); reg 1830 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h unsigned int mmd, unsigned int reg, u16 val); reg 1835 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c u32 reg; reg 1848 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c reg = t4_read_reg(adap, LE_DB_RSP_CODE_0_A); reg 1849 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (TCAM_ACTV_HIT_G(reg) != 4) { reg 1854 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c reg = t4_read_reg(adap, LE_DB_RSP_CODE_1_A); reg 1855 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (HASH_ACTV_HIT_G(reg) != 4) { reg 57 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, reg 61 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 val = t4_read_reg(adapter, reg); reg 75 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, reg 78 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, reg 152 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val) reg 154 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg); reg 731 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 t4_read_pcie_cfg4(struct adapter *adap, int reg) reg 751 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c ldst_cmd.u.pcie.r = reg; reg 764 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c t4_hw_pci_read_cfg4(adap, reg, &val); reg 2680 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c unsigned int reg = reg_ranges[range]; reg 2682 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 *bufp = (u32 *)((char *)buf + reg); reg 2687 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c while (reg <= last_reg && bufp < buf_end) { reg 2688 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c *bufp++ = t4_read_reg(adap, reg); reg 2689 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c reg += sizeof(u32); reg 4317 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg, reg 4322 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c unsigned int status = t4_read_reg(adapter, reg); reg 4340 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c t4_write_reg(adapter, reg, status); reg 6553 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c unsigned int mmd, unsigned int reg, u16 *valp) reg 6567 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c c.u.mdio.raddr = cpu_to_be16(reg); reg 6587 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c unsigned int mmd, unsigned int reg, u16 val) reg 6600 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c c.u.mdio.raddr = cpu_to_be16(reg); reg 46 drivers/net/ethernet/chelsio/cxgb4/t4_regs.h #define PF_REG(idx, reg) (PF_BASE(idx) + (reg)) reg 59 drivers/net/ethernet/chelsio/cxgb4/t4_regs.h #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg)) reg 62 drivers/net/ethernet/chelsio/cxgb4/t4_regs.h #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx) reg 3176 drivers/net/ethernet/chelsio/cxgb4/t4_regs.h #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg)) reg 3181 drivers/net/ethernet/chelsio/cxgb4/t4_regs.h #define MC_REG(reg, idx) (reg + MC_STRIDE * idx) reg 3201 drivers/net/ethernet/chelsio/cxgb4/t4_regs.h #define EDC_T5_REG(reg, idx) (reg + EDC_T5_STRIDE * idx) reg 185 drivers/net/ethernet/cirrus/ep93xx_eth.c static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg) reg 191 drivers/net/ethernet/cirrus/ep93xx_eth.c wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg); reg 209 drivers/net/ethernet/cirrus/ep93xx_eth.c static void ep93xx_mdio_write(struct net_device *dev, int phy_id, int reg, int data) reg 215 drivers/net/ethernet/cirrus/ep93xx_eth.c wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg); reg 31 drivers/net/ethernet/cisco/enic/vnic_dev.h static inline u64 readq(void __iomem *reg) reg 33 drivers/net/ethernet/cisco/enic/vnic_dev.h return (((u64)readl(reg + 0x4UL) << 32) | reg 34 drivers/net/ethernet/cisco/enic/vnic_dev.h (u64)readl(reg)); reg 37 drivers/net/ethernet/cisco/enic/vnic_dev.h static inline void writeq(u64 val, void __iomem *reg) reg 39 drivers/net/ethernet/cisco/enic/vnic_dev.h writel(val & 0xffffffff, reg); reg 40 drivers/net/ethernet/cisco/enic/vnic_dev.h writel(val >> 32, reg + 0x4UL); reg 229 drivers/net/ethernet/cortina/gemini.c u32 reg; reg 233 drivers/net/ethernet/cortina/gemini.c reg = readl(port->gmac_base + GMAC_CONFIG0); reg 234 drivers/net/ethernet/cortina/gemini.c reg = (reg & ~vmask) | val; reg 235 drivers/net/ethernet/cortina/gemini.c writel(reg, port->gmac_base + GMAC_CONFIG0); reg 244 drivers/net/ethernet/cortina/gemini.c u32 reg; reg 248 drivers/net/ethernet/cortina/gemini.c reg = readl(port->gmac_base + GMAC_CONFIG0); reg 249 drivers/net/ethernet/cortina/gemini.c reg &= ~CONFIG0_TX_RX_DISABLE; reg 250 drivers/net/ethernet/cortina/gemini.c writel(reg, port->gmac_base + GMAC_CONFIG0); reg 1541 drivers/net/ethernet/cortina/gemini.c u32 reg[5]; reg 1544 drivers/net/ethernet/cortina/gemini.c reg[0] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_0_REG); reg 1545 drivers/net/ethernet/cortina/gemini.c reg[1] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_1_REG); reg 1546 drivers/net/ethernet/cortina/gemini.c reg[2] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_2_REG); reg 1547 drivers/net/ethernet/cortina/gemini.c reg[3] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_3_REG); reg 1548 drivers/net/ethernet/cortina/gemini.c reg[4] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); reg 1550 drivers/net/ethernet/cortina/gemini.c reg[0], reg[1], reg[2], reg[3], reg[4]); reg 1553 drivers/net/ethernet/cortina/gemini.c reg[0] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG); reg 1554 drivers/net/ethernet/cortina/gemini.c reg[1] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG); reg 1555 drivers/net/ethernet/cortina/gemini.c reg[2] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG); reg 1556 drivers/net/ethernet/cortina/gemini.c reg[3] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG); reg 1557 drivers/net/ethernet/cortina/gemini.c reg[4] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); reg 1559 drivers/net/ethernet/cortina/gemini.c reg[0], reg[1], reg[2], reg[3], reg[4]); reg 1562 drivers/net/ethernet/cortina/gemini.c reg[0] = readl(port->dma_base + GMAC_DMA_RX_FIRST_DESC_REG); reg 1563 drivers/net/ethernet/cortina/gemini.c reg[1] = readl(port->dma_base + GMAC_DMA_RX_CURR_DESC_REG); reg 1564 drivers/net/ethernet/cortina/gemini.c reg[2] = GET_RPTR(port->rxq_rwptr); reg 1565 drivers/net/ethernet/cortina/gemini.c reg[3] = GET_WPTR(port->rxq_rwptr); reg 1567 drivers/net/ethernet/cortina/gemini.c reg[0], reg[1], reg[2], reg[3]); reg 1569 drivers/net/ethernet/cortina/gemini.c reg[0] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD0_REG); reg 1570 drivers/net/ethernet/cortina/gemini.c reg[1] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD1_REG); reg 1571 drivers/net/ethernet/cortina/gemini.c reg[2] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD2_REG); reg 1572 drivers/net/ethernet/cortina/gemini.c reg[3] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD3_REG); reg 1574 drivers/net/ethernet/cortina/gemini.c reg[0], reg[1], reg[2], reg[3]); reg 1579 drivers/net/ethernet/cortina/gemini.c reg[0] = readl(port->dma_base + GMAC_DMA_TX_FIRST_DESC_REG); reg 1580 drivers/net/ethernet/cortina/gemini.c reg[1] = readl(port->dma_base + GMAC_DMA_TX_CURR_DESC_REG); reg 1581 drivers/net/ethernet/cortina/gemini.c reg[2] = GET_RPTR(ptr_reg); reg 1582 drivers/net/ethernet/cortina/gemini.c reg[3] = GET_WPTR(ptr_reg); reg 1584 drivers/net/ethernet/cortina/gemini.c reg[0], reg[1], reg[2], reg[3]); reg 1586 drivers/net/ethernet/cortina/gemini.c reg[0] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD0_REG); reg 1587 drivers/net/ethernet/cortina/gemini.c reg[1] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD1_REG); reg 1588 drivers/net/ethernet/cortina/gemini.c reg[2] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD2_REG); reg 1589 drivers/net/ethernet/cortina/gemini.c reg[3] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD3_REG); reg 1591 drivers/net/ethernet/cortina/gemini.c reg[0], reg[1], reg[2], reg[3]); reg 1596 drivers/net/ethernet/cortina/gemini.c reg[0] = GET_RPTR(ptr_reg); reg 1597 drivers/net/ethernet/cortina/gemini.c reg[1] = GET_WPTR(ptr_reg); reg 1601 drivers/net/ethernet/cortina/gemini.c reg[2] = GET_RPTR(ptr_reg); reg 1602 drivers/net/ethernet/cortina/gemini.c reg[3] = GET_WPTR(ptr_reg); reg 1604 drivers/net/ethernet/cortina/gemini.c reg[0], reg[1], reg[2], reg[3]); reg 2008 drivers/net/ethernet/cortina/gemini.c u32 reg; reg 2012 drivers/net/ethernet/cortina/gemini.c reg = readl(port->gmac_base + GMAC_CONFIG0); reg 2013 drivers/net/ethernet/cortina/gemini.c reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM; reg 2014 drivers/net/ethernet/cortina/gemini.c writel(reg, port->gmac_base + GMAC_CONFIG0); reg 158 drivers/net/ethernet/davicom/dm9000.c ior(struct board_info *db, int reg) reg 160 drivers/net/ethernet/davicom/dm9000.c writeb(reg, db->io_addr); reg 169 drivers/net/ethernet/davicom/dm9000.c iow(struct board_info *db, int reg, int value) reg 171 drivers/net/ethernet/davicom/dm9000.c writeb(reg, db->io_addr); reg 198 drivers/net/ethernet/davicom/dm9000.c static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count) reg 200 drivers/net/ethernet/davicom/dm9000.c iowrite8_rep(reg, data, count); reg 203 drivers/net/ethernet/davicom/dm9000.c static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count) reg 205 drivers/net/ethernet/davicom/dm9000.c iowrite16_rep(reg, data, (count+1) >> 1); reg 208 drivers/net/ethernet/davicom/dm9000.c static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count) reg 210 drivers/net/ethernet/davicom/dm9000.c iowrite32_rep(reg, data, (count+3) >> 2); reg 215 drivers/net/ethernet/davicom/dm9000.c static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count) reg 217 drivers/net/ethernet/davicom/dm9000.c ioread8_rep(reg, data, count); reg 221 drivers/net/ethernet/davicom/dm9000.c static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count) reg 223 drivers/net/ethernet/davicom/dm9000.c ioread16_rep(reg, data, (count+1) >> 1); reg 226 drivers/net/ethernet/davicom/dm9000.c static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count) reg 228 drivers/net/ethernet/davicom/dm9000.c ioread32_rep(reg, data, (count+3) >> 2); reg 233 drivers/net/ethernet/davicom/dm9000.c static void dm9000_dumpblk_8bit(void __iomem *reg, int count) reg 239 drivers/net/ethernet/davicom/dm9000.c tmp = readb(reg); reg 242 drivers/net/ethernet/davicom/dm9000.c static void dm9000_dumpblk_16bit(void __iomem *reg, int count) reg 250 drivers/net/ethernet/davicom/dm9000.c tmp = readw(reg); reg 253 drivers/net/ethernet/davicom/dm9000.c static void dm9000_dumpblk_32bit(void __iomem *reg, int count) reg 261 drivers/net/ethernet/davicom/dm9000.c tmp = readl(reg); reg 278 drivers/net/ethernet/davicom/dm9000.c dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg) reg 293 drivers/net/ethernet/davicom/dm9000.c iow(db, DM9000_EPAR, DM9000_PHY | reg); reg 317 drivers/net/ethernet/davicom/dm9000.c dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret); reg 324 drivers/net/ethernet/davicom/dm9000.c int phyaddr_unused, int reg, int value) reg 330 drivers/net/ethernet/davicom/dm9000.c dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value); reg 340 drivers/net/ethernet/davicom/dm9000.c iow(db, DM9000_EPAR, DM9000_PHY | reg); reg 422 drivers/net/ethernet/davicom/dm9000.c dm9000_read_locked(struct board_info *db, int reg) reg 428 drivers/net/ethernet/davicom/dm9000.c ret = ior(db, reg); reg 372 drivers/net/ethernet/dec/tulip/de2104x.c #define dr32(reg) ioread32(de->regs + (reg)) reg 373 drivers/net/ethernet/dec/tulip/de2104x.c #define dw32(reg, val) iowrite32((val), de->regs + (reg)) reg 495 drivers/net/ethernet/dec/tulip/de4x5.c int reg; reg 506 drivers/net/ethernet/dec/tulip/de4x5.c int reg; reg 932 drivers/net/ethernet/dec/tulip/de4x5.c static int test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec); reg 3445 drivers/net/ethernet/dec/tulip/de4x5.c test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec) reg 3455 drivers/net/ethernet/dec/tulip/de4x5.c reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask; reg 3456 drivers/net/ethernet/dec/tulip/de4x5.c test = (reg ^ (pol ? ~0 : 0)) & mask; reg 3459 drivers/net/ethernet/dec/tulip/de4x5.c reg = 100 | TIMER_CB; reg 3464 drivers/net/ethernet/dec/tulip/de4x5.c return reg; reg 3475 drivers/net/ethernet/dec/tulip/de4x5.c spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII); reg 5004 drivers/net/ethernet/dec/tulip/de4x5.c lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */ reg 145 drivers/net/ethernet/dec/tulip/dmfe.c #define dw32(reg, val) iowrite32(val, ioaddr + (reg)) reg 146 drivers/net/ethernet/dec/tulip/dmfe.c #define dw16(reg, val) iowrite16(val, ioaddr + (reg)) reg 147 drivers/net/ethernet/dec/tulip/dmfe.c #define dr32(reg) ioread32(ioaddr + (reg)) reg 148 drivers/net/ethernet/dec/tulip/dmfe.c #define dr16(reg) ioread16(ioaddr + (reg)) reg 149 drivers/net/ethernet/dec/tulip/dmfe.c #define dr8(reg) ioread8(ioaddr + (reg)) reg 298 drivers/net/ethernet/dec/tulip/tulip_core.c u32 reg; reg 319 drivers/net/ethernet/dec/tulip/tulip_core.c pci_read_config_dword(tp->pdev, PCI_COMMAND, ®); /* flush write */ reg 326 drivers/net/ethernet/dec/tulip/tulip_core.c pci_read_config_dword(tp->pdev, PCI_COMMAND, ®); /* flush write */ reg 37 drivers/net/ethernet/dec/tulip/uli526x.c #define uw32(reg, val) iowrite32(val, ioaddr + (reg)) reg 38 drivers/net/ethernet/dec/tulip/uli526x.c #define ur32(reg) ioread32(ioaddr + (reg)) reg 43 drivers/net/ethernet/dec/tulip/xircom_cb.c #define xw32(reg, val) iowrite32(val, ioaddr + (reg)) reg 44 drivers/net/ethernet/dec/tulip/xircom_cb.c #define xr32(reg) ioread32(ioaddr + (reg)) reg 45 drivers/net/ethernet/dec/tulip/xircom_cb.c #define xr8(reg) ioread8(ioaddr + (reg)) reg 16 drivers/net/ethernet/dlink/dl2k.c #define dw32(reg, val) iowrite32(val, ioaddr + (reg)) reg 17 drivers/net/ethernet/dlink/dl2k.c #define dw16(reg, val) iowrite16(val, ioaddr + (reg)) reg 18 drivers/net/ethernet/dlink/dl2k.c #define dw8(reg, val) iowrite8(val, ioaddr + (reg)) reg 19 drivers/net/ethernet/dlink/dl2k.c #define dr32(reg) ioread32(ioaddr + (reg)) reg 20 drivers/net/ethernet/dlink/dl2k.c #define dr16(reg) ioread16(ioaddr + (reg)) reg 21 drivers/net/ethernet/dlink/dl2k.c #define dr8(reg) ioread8(ioaddr + (reg)) reg 27 drivers/net/ethernet/dnet.c static u16 dnet_readw_mac(struct dnet *bp, u16 reg) reg 32 drivers/net/ethernet/dnet.c dnet_writel(bp, reg, MACREG_ADDR); reg 46 drivers/net/ethernet/dnet.c static void dnet_writew_mac(struct dnet *bp, u16 reg, u16 val) reg 52 drivers/net/ethernet/dnet.c dnet_writel(bp, reg | DNET_INTERNAL_WRITE, MACREG_ADDR); reg 341 drivers/net/ethernet/dnet.c u32 __iomem *reg = bp->regs + DNET_RX_PKT_IGNR_CNT; reg 348 drivers/net/ethernet/dnet.c for (; p < end; p++, reg++) reg 349 drivers/net/ethernet/dnet.c *p += readl(reg); reg 351 drivers/net/ethernet/dnet.c reg = bp->regs + DNET_TX_UNICAST_CNT; reg 358 drivers/net/ethernet/dnet.c for (; p < end; p++, reg++) reg 359 drivers/net/ethernet/dnet.c *p += readl(reg); reg 15 drivers/net/ethernet/dnet.h #define dnet_writel(port, value, reg) \ reg 16 drivers/net/ethernet/dnet.h writel((value), (port)->regs + DNET_##reg) reg 17 drivers/net/ethernet/dnet.h #define dnet_readl(port, reg) readl((port)->regs + DNET_##reg) reg 175 drivers/net/ethernet/emulex/benet/be_main.c u32 reg, enabled; reg 178 drivers/net/ethernet/emulex/benet/be_main.c ®); reg 179 drivers/net/ethernet/emulex/benet/be_main.c enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; reg 182 drivers/net/ethernet/emulex/benet/be_main.c reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; reg 184 drivers/net/ethernet/emulex/benet/be_main.c reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; reg 189 drivers/net/ethernet/emulex/benet/be_main.c PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET, reg); reg 119 drivers/net/ethernet/ethoc.c #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \ reg 120 drivers/net/ethernet/ethoc.c MIIADDRESS_RGAD(reg)) reg 589 drivers/net/ethernet/ethoc.c u32 reg; reg 591 drivers/net/ethernet/ethoc.c reg = ethoc_read(priv, MAC_ADDR0); reg 592 drivers/net/ethernet/ethoc.c mac[2] = (reg >> 24) & 0xff; reg 593 drivers/net/ethernet/ethoc.c mac[3] = (reg >> 16) & 0xff; reg 594 drivers/net/ethernet/ethoc.c mac[4] = (reg >> 8) & 0xff; reg 595 drivers/net/ethernet/ethoc.c mac[5] = (reg >> 0) & 0xff; reg 597 drivers/net/ethernet/ethoc.c reg = ethoc_read(priv, MAC_ADDR1); reg 598 drivers/net/ethernet/ethoc.c mac[0] = (reg >> 8) & 0xff; reg 599 drivers/net/ethernet/ethoc.c mac[1] = (reg >> 0) & 0xff; reg 621 drivers/net/ethernet/ethoc.c static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg) reg 626 drivers/net/ethernet/ethoc.c ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg)); reg 643 drivers/net/ethernet/ethoc.c static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) reg 648 drivers/net/ethernet/ethoc.c ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg)); reg 40 drivers/net/ethernet/ezchip/nps_enet.c u32 *reg = (u32 *)dst, len = length / sizeof(u32); reg 45 drivers/net/ethernet/ezchip/nps_enet.c ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, reg, len); reg 46 drivers/net/ethernet/ezchip/nps_enet.c reg += len; reg 48 drivers/net/ethernet/ezchip/nps_enet.c for (i = 0; i < len; i++, reg++) { reg 51 drivers/net/ethernet/ezchip/nps_enet.c put_unaligned_be32(buf, reg); reg 59 drivers/net/ethernet/ezchip/nps_enet.c memcpy((u8 *)reg, &buf, last); reg 176 drivers/net/ethernet/ezchip/nps_enet.h s32 reg, s32 value) reg 178 drivers/net/ethernet/ezchip/nps_enet.h iowrite32be(value, priv->regs_base + reg); reg 188 drivers/net/ethernet/ezchip/nps_enet.h static inline u32 nps_enet_reg_get(struct nps_enet_priv *priv, s32 reg) reg 190 drivers/net/ethernet/ezchip/nps_enet.h return ioread32be(priv->regs_base + reg); reg 246 drivers/net/ethernet/faraday/ftgmac100.c u32 reg, rfifo_sz, tfifo_sz; reg 249 drivers/net/ethernet/faraday/ftgmac100.c reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR); reg 250 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR); reg 296 drivers/net/ethernet/faraday/ftgmac100.c reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR); reg 297 drivers/net/ethernet/faraday/ftgmac100.c rfifo_sz = reg & 0x00000007; reg 298 drivers/net/ethernet/faraday/ftgmac100.c tfifo_sz = (reg >> 3) & 0x00000007; reg 299 drivers/net/ethernet/faraday/ftgmac100.c reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR); reg 300 drivers/net/ethernet/faraday/ftgmac100.c reg &= ~0x3f000000; reg 301 drivers/net/ethernet/faraday/ftgmac100.c reg |= (tfifo_sz << 27); reg 302 drivers/net/ethernet/faraday/ftgmac100.c reg |= (rfifo_sz << 24); reg 303 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR); reg 1615 drivers/net/ethernet/faraday/ftgmac100.c u32 reg; reg 1629 drivers/net/ethernet/faraday/ftgmac100.c reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR); reg 1630 drivers/net/ethernet/faraday/ftgmac100.c reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE; reg 1631 drivers/net/ethernet/faraday/ftgmac100.c iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR); reg 752 drivers/net/ethernet/faraday/ftmac100.c static int ftmac100_mdio_read(struct net_device *netdev, int phy_id, int reg) reg 759 drivers/net/ethernet/faraday/ftmac100.c FTMAC100_PHYCR_REGAD(reg) | reg 777 drivers/net/ethernet/faraday/ftmac100.c static void ftmac100_mdio_write(struct net_device *netdev, int phy_id, int reg, reg 785 drivers/net/ethernet/faraday/ftmac100.c FTMAC100_PHYCR_REGAD(reg) | reg 990 drivers/net/ethernet/freescale/enetc/enetc.c cbdr->pir = hw->reg + ENETC_SICBDRPIR; reg 991 drivers/net/ethernet/freescale/enetc/enetc.c cbdr->cir = hw->reg + ENETC_SICBDRCIR; reg 1132 drivers/net/ethernet/freescale/enetc/enetc.c tx_ring->tpir = hw->reg + ENETC_BDR(TX, idx, ENETC_TBPIR); reg 1133 drivers/net/ethernet/freescale/enetc/enetc.c tx_ring->tcir = hw->reg + ENETC_BDR(TX, idx, ENETC_TBCIR); reg 1134 drivers/net/ethernet/freescale/enetc/enetc.c tx_ring->idr = hw->reg + ENETC_SITXIDR; reg 1166 drivers/net/ethernet/freescale/enetc/enetc.c rx_ring->rcir = hw->reg + ENETC_BDR(RX, idx, ENETC_RBCIR); reg 1167 drivers/net/ethernet/freescale/enetc/enetc.c rx_ring->idr = hw->reg + ENETC_SIRXIDR; reg 1247 drivers/net/ethernet/freescale/enetc/enetc.c v->tbier_base = hw->reg + ENETC_BDR(TX, 0, ENETC_TBIER); reg 1248 drivers/net/ethernet/freescale/enetc/enetc.c v->rbier = hw->reg + ENETC_BDR(RX, i, ENETC_RBIER); reg 1518 drivers/net/ethernet/freescale/enetc/enetc.c u32 reg; reg 1522 drivers/net/ethernet/freescale/enetc/enetc.c reg = enetc_rd(hw, ENETC_SIMR); reg 1523 drivers/net/ethernet/freescale/enetc/enetc.c reg &= ~ENETC_SIMR_RSSE; reg 1524 drivers/net/ethernet/freescale/enetc/enetc.c reg |= (en) ? ENETC_SIMR_RSSE : 0; reg 1525 drivers/net/ethernet/freescale/enetc/enetc.c enetc_wr(hw, ENETC_SIMR, reg); reg 1777 drivers/net/ethernet/freescale/enetc/enetc.c hw->reg = ioremap(pci_resource_start(pdev, ENETC_BAR_REGS), len); reg 1778 drivers/net/ethernet/freescale/enetc/enetc.c if (!hw->reg) { reg 1784 drivers/net/ethernet/freescale/enetc/enetc.c hw->port = hw->reg + ENETC_PORT_BASE; reg 1786 drivers/net/ethernet/freescale/enetc/enetc.c hw->global = hw->reg + ENETC_GLOBAL_BASE; reg 1808 drivers/net/ethernet/freescale/enetc/enetc.c iounmap(hw->reg); reg 93 drivers/net/ethernet/freescale/enetc/enetc_ethtool.c int reg; reg 123 drivers/net/ethernet/freescale/enetc/enetc_ethtool.c int reg; reg 256 drivers/net/ethernet/freescale/enetc/enetc_ethtool.c data[o++] = enetc_rd64(hw, enetc_si_counters[i].reg); reg 270 drivers/net/ethernet/freescale/enetc/enetc_ethtool.c data[o++] = enetc_port_rd(hw, enetc_port_counters[i].reg); reg 292 drivers/net/ethernet/freescale/enetc/enetc_hw.h void __iomem *reg; reg 300 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define enetc_rd_reg(reg) ioread32((reg)) reg 301 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define enetc_wr_reg(reg, val) iowrite32((val), (reg)) reg 303 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define enetc_rd_reg64(reg) ioread64((reg)) reg 306 drivers/net/ethernet/freescale/enetc/enetc_hw.h static inline u64 enetc_rd_reg64(void __iomem *reg) reg 311 drivers/net/ethernet/freescale/enetc/enetc_hw.h high = ioread32(reg + 4); reg 312 drivers/net/ethernet/freescale/enetc/enetc_hw.h low = ioread32(reg); reg 313 drivers/net/ethernet/freescale/enetc/enetc_hw.h tmp = ioread32(reg + 4); reg 320 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off)) reg 321 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val) reg 322 drivers/net/ethernet/freescale/enetc/enetc_hw.h #define enetc_rd64(hw, off) enetc_rd_reg64((hw)->reg + (off)) reg 493 drivers/net/ethernet/freescale/enetc/enetc_hw.h *(u32 *)addr = __raw_readl(hw->reg + ENETC_SIPMAR0); reg 494 drivers/net/ethernet/freescale/enetc/enetc_hw.h *(u16 *)(addr + 4) = __raw_readw(hw->reg + ENETC_SIPMAR1); reg 345 drivers/net/ethernet/freescale/enetc/enetc_pf.c u32 reg; reg 347 drivers/net/ethernet/freescale/enetc/enetc_pf.c reg = enetc_port_rd(hw, ENETC_PM0_IF_MODE); reg 348 drivers/net/ethernet/freescale/enetc/enetc_pf.c if (reg & ENETC_PMO_IFM_RG) { reg 350 drivers/net/ethernet/freescale/enetc/enetc_pf.c reg = (reg & ~ENETC_PM0_IFM_RLP) | reg 352 drivers/net/ethernet/freescale/enetc/enetc_pf.c enetc_port_wr(hw, ENETC_PM0_IF_MODE, reg); reg 355 drivers/net/ethernet/freescale/enetc/enetc_pf.c reg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG); reg 356 drivers/net/ethernet/freescale/enetc/enetc_pf.c reg = (reg & ~ENETC_PM0_CMD_XGLP) | reg 358 drivers/net/ethernet/freescale/enetc/enetc_pf.c reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) | reg 360 drivers/net/ethernet/freescale/enetc/enetc_pf.c enetc_port_wr(hw, ENETC_PM0_CMD_CFG, reg); reg 361 drivers/net/ethernet/freescale/enetc/enetc_pf.c enetc_port_wr(hw, ENETC_PM1_CMD_CFG, reg); reg 493 drivers/net/ethernet/freescale/fec.h u8 reg; reg 1140 drivers/net/ethernet/freescale/fec_main.c regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, reg 1144 drivers/net/ethernet/freescale/fec_main.c regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, reg 3476 drivers/net/ethernet/freescale/fec_main.c fep->stop_gpr.reg = dev_info->stop_gpr_reg; reg 28 drivers/net/ethernet/freescale/fec_mpc52xx_phy.c int reg, u32 value) reg 35 drivers/net/ethernet/freescale/fec_mpc52xx_phy.c value |= (reg << FEC_MII_DATA_RA_SHIFT) & FEC_MII_DATA_RA_MSK; reg 51 drivers/net/ethernet/freescale/fec_mpc52xx_phy.c static int mpc52xx_fec_mdio_read(struct mii_bus *bus, int phy_id, int reg) reg 53 drivers/net/ethernet/freescale/fec_mpc52xx_phy.c return mpc52xx_fec_mdio_transfer(bus, phy_id, reg, FEC_MII_READ_FRAME); reg 56 drivers/net/ethernet/freescale/fec_mpc52xx_phy.c static int mpc52xx_fec_mdio_write(struct mii_bus *bus, int phy_id, int reg, reg 59 drivers/net/ethernet/freescale/fec_mpc52xx_phy.c return mpc52xx_fec_mdio_transfer(bus, phy_id, reg, reg 1848 drivers/net/ethernet/freescale/fman/fman.c u32 devdisr2, reg; reg 1871 drivers/net/ethernet/freescale/fman/fman.c reg = devdisr2 & ~FMAN1_ALL_MACS_MASK; reg 1873 drivers/net/ethernet/freescale/fman/fman.c reg = devdisr2 & ~FMAN2_ALL_MACS_MASK; reg 1876 drivers/net/ethernet/freescale/fman/fman.c iowrite32be(reg, &guts_regs->devdisr2); reg 2138 drivers/net/ethernet/freescale/fman/fman.c u32 enq_th, deq_th, reg; reg 2154 drivers/net/ethernet/freescale/fman/fman.c reg = ioread32be(&fman->qmi_regs->fmqm_gc); reg 2155 drivers/net/ethernet/freescale/fman/fman.c reg &= ~QMI_CFG_ENQ_MASK; reg 2156 drivers/net/ethernet/freescale/fman/fman.c reg |= (enq_th << QMI_CFG_ENQ_SHIFT); reg 2157 drivers/net/ethernet/freescale/fman/fman.c iowrite32be(reg, &fman->qmi_regs->fmqm_gc); reg 2170 drivers/net/ethernet/freescale/fman/fman.c reg = ioread32be(&fman->qmi_regs->fmqm_gc); reg 2171 drivers/net/ethernet/freescale/fman/fman.c reg &= ~QMI_CFG_DEQ_MASK; reg 2172 drivers/net/ethernet/freescale/fman/fman.c reg |= deq_th; reg 2173 drivers/net/ethernet/freescale/fman/fman.c iowrite32be(reg, &fman->qmi_regs->fmqm_gc); reg 540 drivers/net/ethernet/freescale/fman/fman_dtsec.c u32 __iomem *reg; reg 543 drivers/net/ethernet/freescale/fman/fman_dtsec.c reg = ®s->gaddr[reg_idx - 8]; reg 545 drivers/net/ethernet/freescale/fman/fman_dtsec.c reg = ®s->igaddr[reg_idx]; reg 548 drivers/net/ethernet/freescale/fman/fman_dtsec.c iowrite32be(ioread32be(reg) | bit_mask, reg); reg 550 drivers/net/ethernet/freescale/fman/fman_dtsec.c iowrite32be(ioread32be(reg) & (~bit_mask), reg); reg 1402 drivers/net/ethernet/freescale/fman/fman_port.c u32 reg; reg 1404 drivers/net/ethernet/freescale/fman/fman_port.c reg = 0x00001013; reg 1405 drivers/net/ethernet/freescale/fman/fman_port.c iowrite32be(reg, &port->bmi_regs->tx.fmbm_tfp); reg 384 drivers/net/ethernet/freescale/ucc_geth.c static void set_mac_addr(__be16 __iomem *reg, u8 *mac) reg 386 drivers/net/ethernet/freescale/ucc_geth.c out_be16(®[0], ((u16)mac[5] << 8) | mac[4]); reg 387 drivers/net/ethernet/freescale/ucc_geth.c out_be16(®[1], ((u16)mac[3] << 8) | mac[2]); reg 388 drivers/net/ethernet/freescale/ucc_geth.c out_be16(®[2], ((u16)mac[1] << 8) | mac[0]); reg 80 drivers/net/ethernet/hisilicon/hisi_femac.c #define GLB_MAC_H16(reg) (GLB_MAC_H16_BASE + ((reg) * 0x8)) reg 81 drivers/net/ethernet/hisilicon/hisi_femac.c #define GLB_MAC_L32(reg) (GLB_MAC_L32_BASE + ((reg) * 0x8)) reg 432 drivers/net/ethernet/hisilicon/hisi_femac.c u32 reg; reg 434 drivers/net/ethernet/hisilicon/hisi_femac.c reg = mac[1] | (mac[0] << 8); reg 435 drivers/net/ethernet/hisilicon/hisi_femac.c writel(reg, priv->glb_base + GLB_HOSTMAC_H16); reg 437 drivers/net/ethernet/hisilicon/hisi_femac.c reg = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24); reg 438 drivers/net/ethernet/hisilicon/hisi_femac.c writel(reg, priv->glb_base + GLB_HOSTMAC_L32); reg 623 drivers/net/ethernet/hisilicon/hisi_femac.c int reg = MAX_UNICAST_ADDRESSES; reg 627 drivers/net/ethernet/hisilicon/hisi_femac.c for (i = reg; i < MAX_MAC_FILTER_NUM; i++) reg 631 drivers/net/ethernet/hisilicon/hisi_femac.c hisi_femac_set_hw_addr_filter(priv, ha->addr, reg); reg 632 drivers/net/ethernet/hisilicon/hisi_femac.c reg++; reg 649 drivers/net/ethernet/hisilicon/hisi_femac.c int reg = 0; reg 653 drivers/net/ethernet/hisilicon/hisi_femac.c for (i = reg; i < MAX_UNICAST_ADDRESSES; i++) reg 657 drivers/net/ethernet/hisilicon/hisi_femac.c hisi_femac_set_hw_addr_filter(priv, ha->addr, reg); reg 658 drivers/net/ethernet/hisilicon/hisi_femac.c reg++; reg 932 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c static int hix5hd2_mdio_read(struct mii_bus *bus, int phy, int reg) reg 942 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(MDIO_READ | phy << 8 | reg, base + MDIO_SINGLE_CMD); reg 960 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c static int hix5hd2_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) reg 971 drivers/net/ethernet/hisilicon/hix5hd2_gmac.c writel_relaxed(MDIO_WRITE | phy << 8 | reg, base + MDIO_SINGLE_CMD); reg 351 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c u32 reg; reg 356 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i; reg 357 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 0); reg 361 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i; reg 362 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 1); reg 368 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i; reg 372 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S); reg 395 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c u32 reg; reg 400 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i; reg 401 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); reg 408 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); reg 410 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i; reg 411 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); reg 416 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); reg 418 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i; reg 419 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); reg 424 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); reg 426 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i; reg 427 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); reg 434 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); reg 437 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i; reg 438 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); reg 445 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); reg 450 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i; reg 451 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); reg 456 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); reg 461 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i; reg 462 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); reg 467 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); reg 474 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c u32 reg; reg 479 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i; reg 480 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); reg 487 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); reg 489 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i; reg 490 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); reg 495 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); reg 497 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i; reg 498 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); reg 503 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); reg 505 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i; reg 506 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); reg 513 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); reg 516 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i; reg 517 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); reg 524 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); reg 529 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i; reg 530 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); reg 540 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); reg 545 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i; reg 546 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg); reg 553 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg); reg 1270 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c u32 reg; reg 1281 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i; reg 1282 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_set_dev_field(dsaf_dev, reg, reg 1289 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i; reg 1290 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_set_dev_field(dsaf_dev, reg, reg 1293 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_set_dev_field(dsaf_dev, reg, reg 1296 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_set_dev_field(dsaf_dev, reg, reg 1299 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_set_dev_field(dsaf_dev, reg, reg 1302 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_set_dev_field(dsaf_dev, reg, reg 1305 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_set_dev_field(dsaf_dev, reg, reg 1311 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c reg = DSAF_INODE_PRI_TC_CFG_0_REG + 0x80 * i; reg 1312 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c dsaf_write_dev(dsaf_dev, reg, tc_cfg); reg 33 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val) reg 36 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val); reg 38 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c dsaf_write_reg(dsaf_dev->sc_base, reg, val); reg 41 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg) reg 47 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c err = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg, &ret); reg 52 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c ret = dsaf_read_reg(dsaf_dev->sc_base, reg); reg 509 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c u32 reg; reg 519 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c reg = HNS_MAC_HILINK4_REG; reg 521 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c reg = HNS_MAC_HILINK3_REG; reg 524 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c reg = HNS_MAC_HILINK4V2_REG; reg 526 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c reg = HNS_MAC_HILINK3V2_REG; reg 529 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c mode = dsaf_read_sub(mac_cb->dsaf_dev, reg); reg 629 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c #define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2) reg 574 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c u64 reg; reg 576 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c reg = RCB_CFG_PKTLINE_REG + (port_idx + HNS_RCB_TX_PKTLINE_OFFSET) * 4; reg 577 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c return dsaf_read_dev(rcb_common, reg); reg 645 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c u64 reg; reg 656 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c reg = RCB_CFG_PKTLINE_REG + (port_idx + HNS_RCB_TX_PKTLINE_OFFSET) * 4; reg 657 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c dsaf_write_dev(rcb_common, reg, coalesced_frames); reg 1017 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h static inline void dsaf_write_reg(u8 __iomem *base, u32 reg, u32 value) reg 1019 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h writel(value, base + reg); reg 1022 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h #define dsaf_write_dev(a, reg, value) \ reg 1023 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h dsaf_write_reg((a)->io_base, (reg), (value)) reg 1025 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h static inline u32 dsaf_read_reg(u8 __iomem *base, u32 reg) reg 1027 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h return readl(base + reg); reg 1030 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h static inline void dsaf_write_syscon(struct regmap *base, u32 reg, u32 value) reg 1032 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h regmap_write(base, reg, value); reg 1035 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h static inline int dsaf_read_syscon(struct regmap *base, u32 reg, u32 *val) reg 1037 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h return regmap_read(base, reg, val); reg 1040 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h #define dsaf_read_dev(a, reg) \ reg 1041 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h dsaf_read_reg((a)->io_base, (reg)) reg 1052 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h static inline void dsaf_set_reg_field(u8 __iomem *base, u32 reg, u32 mask, reg 1055 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h u32 origin = dsaf_read_reg(base, reg); reg 1058 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h dsaf_write_reg(base, reg, origin); reg 1061 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h #define dsaf_set_dev_field(dev, reg, mask, shift, val) \ reg 1062 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h dsaf_set_reg_field((dev)->io_base, (reg), (mask), (shift), (val)) reg 1064 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h #define dsaf_set_dev_bit(dev, reg, bit, val) \ reg 1065 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h dsaf_set_reg_field((dev)->io_base, (reg), (1ull << (bit)), (bit), (val)) reg 1072 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h static inline u32 dsaf_get_reg_field(u8 __iomem *base, u32 reg, u32 mask, reg 1077 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h origin = dsaf_read_reg(base, reg); reg 1081 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h #define dsaf_get_dev_field(dev, reg, mask, shift) \ reg 1082 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h dsaf_get_reg_field((dev)->io_base, (reg), (mask), (shift)) reg 1084 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h #define dsaf_get_dev_bit(dev, reg, bit) \ reg 1085 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h dsaf_get_reg_field((dev)->io_base, (reg), (1ull << (bit)), (bit)) reg 577 drivers/net/ethernet/hisilicon/hns3/hns3_enet.h static inline u32 hns3_read_reg(void __iomem *base, u32 reg) reg 579 drivers/net/ethernet/hisilicon/hns3/hns3_enet.h return readl(base + reg); reg 582 drivers/net/ethernet/hisilicon/hns3/hns3_enet.h static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value) reg 586 drivers/net/ethernet/hisilicon/hns3/hns3_enet.h writel(value, reg_addr + reg); reg 598 drivers/net/ethernet/hisilicon/hns3/hns3_enet.h #define hns3_read_dev(a, reg) \ reg 599 drivers/net/ethernet/hisilicon/hns3/hns3_enet.h hns3_read_reg((a)->io_base, (reg)) reg 608 drivers/net/ethernet/hisilicon/hns3/hns3_enet.h #define hns3_write_dev(a, reg, value) \ reg 609 drivers/net/ethernet/hisilicon/hns3/hns3_enet.h hns3_write_reg((a)->io_base, (reg), (value)) reg 1067 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) reg 1069 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h writel(value, base + reg); reg 1072 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define hclge_write_dev(a, reg, value) \ reg 1073 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h hclge_write_reg((a)->io_base, (reg), (value)) reg 1074 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h #define hclge_read_dev(a, reg) \ reg 1075 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h hclge_read_reg((a)->io_base, (reg)) reg 1077 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) reg 1081 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h return readl(reg_addr + reg); reg 634 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c static void hclge_log_error(struct device *dev, char *reg, reg 641 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c reg, err->msg, err_sts); reg 3164 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c u32 val, reg, reg_bit; reg 3169 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg = HCLGE_GLOBAL_RESET_REG; reg 3173 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg = HCLGE_GLOBAL_RESET_REG; reg 3177 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg = HCLGE_FUN_RST_ING; reg 3203 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c val = hclge_read_dev(&hdev->hw, reg); reg 3206 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c val = hclge_read_dev(&hdev->hw, reg); reg 9833 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c u32 *reg = data; reg 9841 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *reg++ = le32_to_cpu(desc[desc_index].data[index]); reg 9844 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *reg++ = SEPARATOR_VALUE; reg 9880 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c u32 *reg = data; reg 9911 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg += hclge_dfx_reg_fetch_data(desc_src, bd_num, reg); reg 9926 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c u32 *reg = data; reg 9932 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *reg++ = hclge_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); reg 9934 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *reg++ = SEPARATOR_VALUE; reg 9940 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *reg++ = hclge_read_dev(&hdev->hw, common_reg_addr_list[i]); reg 9942 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *reg++ = SEPARATOR_VALUE; reg 9949 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *reg++ = hclge_read_dev(&hdev->hw, reg 9953 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *reg++ = SEPARATOR_VALUE; reg 9961 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *reg++ = hclge_read_dev(&hdev->hw, reg 9965 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *reg++ = SEPARATOR_VALUE; reg 10022 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c u32 *reg = data; reg 10033 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg += hclge_fetch_pf_reg(hdev, reg, kinfo); reg 10035 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, reg); reg 10042 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg += reg_num; reg 10045 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *reg++ = SEPARATOR_VALUE; reg 10047 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, reg); reg 10054 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c reg += reg_num; reg 10057 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c *reg++ = SEPARATOR_VALUE; reg 10059 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c ret = hclge_get_dfx_reg(hdev, reg); reg 256 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h static inline void hclgevf_write_reg(void __iomem *base, u32 reg, u32 value) reg 258 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h writel(value, base + reg); reg 261 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h static inline u32 hclgevf_read_reg(u8 __iomem *base, u32 reg) reg 265 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h return readl(reg_addr + reg); reg 268 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h #define hclgevf_write_dev(a, reg, value) \ reg 269 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h hclgevf_write_reg((a)->io_base, (reg), (value)) reg 270 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h #define hclgevf_read_dev(a, reg) \ reg 271 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h hclgevf_read_reg((a)->io_base, (reg)) reg 3034 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c u32 *reg = data; reg 3042 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); reg 3044 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c *reg++ = SEPARATOR_VALUE; reg 3049 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]); reg 3051 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c *reg++ = SEPARATOR_VALUE; reg 3057 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c *reg++ = hclgevf_read_dev(&hdev->hw, reg 3061 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c *reg++ = SEPARATOR_VALUE; reg 3068 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c *reg++ = hclgevf_read_dev(&hdev->hw, reg 3072 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c *reg++ = SEPARATOR_VALUE; reg 95 drivers/net/ethernet/hisilicon/hns_mdio.c static void mdio_write_reg(u8 __iomem *base, u32 reg, u32 value) reg 97 drivers/net/ethernet/hisilicon/hns_mdio.c writel_relaxed(value, base + reg); reg 100 drivers/net/ethernet/hisilicon/hns_mdio.c #define MDIO_WRITE_REG(a, reg, value) \ reg 101 drivers/net/ethernet/hisilicon/hns_mdio.c mdio_write_reg((a)->vbase, (reg), (value)) reg 103 drivers/net/ethernet/hisilicon/hns_mdio.c static u32 mdio_read_reg(u8 __iomem *base, u32 reg) reg 105 drivers/net/ethernet/hisilicon/hns_mdio.c return readl_relaxed(base + reg); reg 116 drivers/net/ethernet/hisilicon/hns_mdio.c static void mdio_set_reg_field(u8 __iomem *base, u32 reg, u32 mask, u32 shift, reg 119 drivers/net/ethernet/hisilicon/hns_mdio.c u32 origin = mdio_read_reg(base, reg); reg 122 drivers/net/ethernet/hisilicon/hns_mdio.c mdio_write_reg(base, reg, origin); reg 125 drivers/net/ethernet/hisilicon/hns_mdio.c #define MDIO_SET_REG_FIELD(dev, reg, mask, shift, val) \ reg 126 drivers/net/ethernet/hisilicon/hns_mdio.c mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val)) reg 128 drivers/net/ethernet/hisilicon/hns_mdio.c static u32 mdio_get_reg_field(u8 __iomem *base, u32 reg, u32 mask, u32 shift) reg 132 drivers/net/ethernet/hisilicon/hns_mdio.c origin = mdio_read_reg(base, reg); reg 136 drivers/net/ethernet/hisilicon/hns_mdio.c #define MDIO_GET_REG_FIELD(dev, reg, mask, shift) \ reg 137 drivers/net/ethernet/hisilicon/hns_mdio.c mdio_get_reg_field((dev)->vbase, (reg), (mask), (shift)) reg 139 drivers/net/ethernet/hisilicon/hns_mdio.c #define MDIO_GET_REG_BIT(dev, reg, bit) \ reg 140 drivers/net/ethernet/hisilicon/hns_mdio.c mdio_get_reg_field((dev)->vbase, (reg), 0x1ull, (bit)) reg 224 drivers/net/ethernet/hisilicon/hns_mdio.c u16 reg = (u16)(regnum & 0xffff); reg 231 drivers/net/ethernet/hisilicon/hns_mdio.c phy_id, is_c45, devad, reg, data); reg 241 drivers/net/ethernet/hisilicon/hns_mdio.c cmd_reg_cfg = reg; reg 246 drivers/net/ethernet/hisilicon/hns_mdio.c MDIO_ADDR_DATA_S, reg); reg 286 drivers/net/ethernet/hisilicon/hns_mdio.c u16 reg = (u16)(regnum & 0xffff); reg 292 drivers/net/ethernet/hisilicon/hns_mdio.c phy_id, is_c45, devad, reg); reg 303 drivers/net/ethernet/hisilicon/hns_mdio.c MDIO_C22_READ, phy_id, reg); reg 306 drivers/net/ethernet/hisilicon/hns_mdio.c MDIO_ADDR_DATA_S, reg); reg 581 drivers/net/ethernet/hp/hp100.h #define hp100_inb( reg ) \ reg 582 drivers/net/ethernet/hp/hp100.h inb( ioaddr + HP100_REG_##reg ) reg 583 drivers/net/ethernet/hp/hp100.h #define hp100_inw( reg ) \ reg 584 drivers/net/ethernet/hp/hp100.h inw( ioaddr + HP100_REG_##reg ) reg 585 drivers/net/ethernet/hp/hp100.h #define hp100_inl( reg ) \ reg 586 drivers/net/ethernet/hp/hp100.h inl( ioaddr + HP100_REG_##reg ) reg 587 drivers/net/ethernet/hp/hp100.h #define hp100_outb( data, reg ) \ reg 588 drivers/net/ethernet/hp/hp100.h outb( data, ioaddr + HP100_REG_##reg ) reg 589 drivers/net/ethernet/hp/hp100.h #define hp100_outw( data, reg ) \ reg 590 drivers/net/ethernet/hp/hp100.h outw( data, ioaddr + HP100_REG_##reg ) reg 591 drivers/net/ethernet/hp/hp100.h #define hp100_outl( data, reg ) \ reg 592 drivers/net/ethernet/hp/hp100.h outl( data, ioaddr + HP100_REG_##reg ) reg 593 drivers/net/ethernet/hp/hp100.h #define hp100_orb( data, reg ) \ reg 594 drivers/net/ethernet/hp/hp100.h outb( inb( ioaddr + HP100_REG_##reg ) | (data), ioaddr + HP100_REG_##reg ) reg 595 drivers/net/ethernet/hp/hp100.h #define hp100_orw( data, reg ) \ reg 596 drivers/net/ethernet/hp/hp100.h outw( inw( ioaddr + HP100_REG_##reg ) | (data), ioaddr + HP100_REG_##reg ) reg 597 drivers/net/ethernet/hp/hp100.h #define hp100_andb( data, reg ) \ reg 598 drivers/net/ethernet/hp/hp100.h outb( inb( ioaddr + HP100_REG_##reg ) & (data), ioaddr + HP100_REG_##reg ) reg 599 drivers/net/ethernet/hp/hp100.h #define hp100_andw( data, reg ) \ reg 600 drivers/net/ethernet/hp/hp100.h outw( inw( ioaddr + HP100_REG_##reg ) & (data), ioaddr + HP100_REG_##reg ) reg 236 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h static inline u32 hinic_hwif_read_reg(struct hinic_hwif *hwif, u32 reg) reg 238 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h return be32_to_cpu(readl(hwif->cfg_regs_bar + reg)); reg 241 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h static inline void hinic_hwif_write_reg(struct hinic_hwif *hwif, u32 reg, reg 244 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h writel(cpu_to_be32(val), hwif->cfg_regs_bar + reg); reg 430 drivers/net/ethernet/ibm/emac/core.c int slot, reg, mask; reg 435 drivers/net/ethernet/ibm/emac/core.c reg = EMAC_XAHT_SLOT_TO_REG(dev, slot); reg 438 drivers/net/ethernet/ibm/emac/core.c gaht_temp[reg] |= mask; reg 799 drivers/net/ethernet/ibm/emac/core.c static int __emac_mdio_read(struct emac_instance *dev, u8 id, u8 reg) reg 807 drivers/net/ethernet/ibm/emac/core.c DBG2(dev, "mdio_read(%02x,%02x)" NL, id, reg); reg 836 drivers/net/ethernet/ibm/emac/core.c r |= (reg & EMAC_STACR_PRA_MASK) reg 851 drivers/net/ethernet/ibm/emac/core.c DBG(dev, "mdio_read(%02x, %02x) failed" NL, id, reg); reg 870 drivers/net/ethernet/ibm/emac/core.c static void __emac_mdio_write(struct emac_instance *dev, u8 id, u8 reg, reg 879 drivers/net/ethernet/ibm/emac/core.c DBG2(dev, "mdio_write(%02x,%02x,%04x)" NL, id, reg, val); reg 908 drivers/net/ethernet/ibm/emac/core.c r |= (reg & EMAC_STACR_PRA_MASK) | reg 931 drivers/net/ethernet/ibm/emac/core.c static int emac_mdio_read(struct net_device *ndev, int id, int reg) reg 939 drivers/net/ethernet/ibm/emac/core.c (u8) id, (u8) reg); reg 943 drivers/net/ethernet/ibm/emac/core.c static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val) reg 950 drivers/net/ethernet/ibm/emac/core.c (u8) id, (u8) reg, (u16) val); reg 213 drivers/net/ethernet/ibm/emac/mal.h static inline u32 get_mal_dcrn(struct mal_instance *mal, int reg) reg 215 drivers/net/ethernet/ibm/emac/mal.h return dcr_read(mal->dcr_host, reg); reg 218 drivers/net/ethernet/ibm/emac/mal.h static inline void set_mal_dcrn(struct mal_instance *mal, int reg, u32 val) reg 220 drivers/net/ethernet/ibm/emac/mal.h dcr_write(mal->dcr_host, reg, val); reg 35 drivers/net/ethernet/ibm/emac/phy.c static inline int _phy_read(struct mii_phy *phy, int reg) reg 37 drivers/net/ethernet/ibm/emac/phy.c return phy->mdio_read(phy->dev, phy->address, reg); reg 40 drivers/net/ethernet/ibm/emac/phy.c static inline void _phy_write(struct mii_phy *phy, int reg, int val) reg 42 drivers/net/ethernet/ibm/emac/phy.c phy->mdio_write(phy->dev, phy->address, reg, val); reg 45 drivers/net/ethernet/ibm/emac/phy.c static inline int gpcs_phy_read(struct mii_phy *phy, int reg) reg 47 drivers/net/ethernet/ibm/emac/phy.c return phy->mdio_read(phy->dev, phy->gpcs_address, reg); reg 50 drivers/net/ethernet/ibm/emac/phy.c static inline void gpcs_phy_write(struct mii_phy *phy, int reg, int val) reg 52 drivers/net/ethernet/ibm/emac/phy.c phy->mdio_write(phy->dev, phy->gpcs_address, reg, val); reg 71 drivers/net/ethernet/ibm/emac/phy.h int (*mdio_read) (struct net_device * dev, int addr, int reg); reg 72 drivers/net/ethernet/ibm/emac/phy.h void (*mdio_write) (struct net_device * dev, int addr, int reg, reg 545 drivers/net/ethernet/intel/e100.c u16 (*mdio_ctrl)(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data); reg 905 drivers/net/ethernet/intel/e100.c static int mdio_read(struct net_device *netdev, int addr, int reg) reg 908 drivers/net/ethernet/intel/e100.c return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0); reg 911 drivers/net/ethernet/intel/e100.c static void mdio_write(struct net_device *netdev, int addr, int reg, int data) reg 915 drivers/net/ethernet/intel/e100.c nic->mdio_ctrl(nic, addr, mdi_write, reg, data); reg 919 drivers/net/ethernet/intel/e100.c static u16 mdio_ctrl_hw(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data) reg 943 drivers/net/ethernet/intel/e100.c iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl); reg 954 drivers/net/ethernet/intel/e100.c addr, reg, data, data_out); reg 962 drivers/net/ethernet/intel/e100.c u32 reg, reg 965 drivers/net/ethernet/intel/e100.c if ((reg == MII_BMCR) && (dir == mdi_write)) { reg 980 drivers/net/ethernet/intel/e100.c return mdio_ctrl_hw(nic, addr, dir, reg, data); reg 992 drivers/net/ethernet/intel/e100.c u32 reg, reg 1000 drivers/net/ethernet/intel/e100.c switch (reg) { reg 1017 drivers/net/ethernet/intel/e100.c addr, reg, data); reg 1021 drivers/net/ethernet/intel/e100.c switch (reg) { reg 1026 drivers/net/ethernet/intel/e100.c addr, reg, data); reg 653 drivers/net/ethernet/intel/e1000/e1000_ethtool.c static bool reg_pattern_test(struct e1000_adapter *adapter, u64 *data, int reg, reg 660 drivers/net/ethernet/intel/e1000/e1000_ethtool.c u8 __iomem *address = hw->hw_addr + reg; reg 670 drivers/net/ethernet/intel/e1000/e1000_ethtool.c reg, read, (write & test[i] & mask)); reg 671 drivers/net/ethernet/intel/e1000/e1000_ethtool.c *data = reg; reg 678 drivers/net/ethernet/intel/e1000/e1000_ethtool.c static bool reg_set_and_check(struct e1000_adapter *adapter, u64 *data, int reg, reg 682 drivers/net/ethernet/intel/e1000/e1000_ethtool.c u8 __iomem *address = hw->hw_addr + reg; reg 690 drivers/net/ethernet/intel/e1000/e1000_ethtool.c reg, (read & mask), (write & mask)); reg 691 drivers/net/ethernet/intel/e1000/e1000_ethtool.c *data = reg; reg 697 drivers/net/ethernet/intel/e1000/e1000_ethtool.c #define REG_PATTERN_TEST(reg, mask, write) \ reg 701 drivers/net/ethernet/intel/e1000/e1000_ethtool.c ? E1000_##reg : E1000_82542_##reg, \ reg 706 drivers/net/ethernet/intel/e1000/e1000_ethtool.c #define REG_SET_AND_CHECK(reg, mask, write) \ reg 710 drivers/net/ethernet/intel/e1000/e1000_ethtool.c ? E1000_##reg : E1000_82542_##reg, \ reg 347 drivers/net/ethernet/intel/e1000/e1000_hw.h s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data); reg 350 drivers/net/ethernet/intel/e1000/e1000_hw.h s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data); reg 379 drivers/net/ethernet/intel/e1000/e1000_hw.h #define E1000_READ_REG_IO(a, reg) \ reg 380 drivers/net/ethernet/intel/e1000/e1000_hw.h e1000_read_reg_io((a), E1000_##reg) reg 381 drivers/net/ethernet/intel/e1000/e1000_hw.h #define E1000_WRITE_REG_IO(a, reg, val) \ reg 382 drivers/net/ethernet/intel/e1000/e1000_hw.h e1000_write_reg_io((a), E1000_##reg, val) reg 2915 drivers/net/ethernet/intel/e1000/e1000_hw.h #define PHY_REG(page, reg) \ reg 2916 drivers/net/ethernet/intel/e1000/e1000_hw.h (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) reg 28 drivers/net/ethernet/intel/e1000/e1000_osdep.h #define er32(reg) \ reg 30 drivers/net/ethernet/intel/e1000/e1000_osdep.h ? E1000_##reg : E1000_82542_##reg))) reg 32 drivers/net/ethernet/intel/e1000/e1000_osdep.h #define ew32(reg, value) \ reg 34 drivers/net/ethernet/intel/e1000/e1000_osdep.h ? E1000_##reg : E1000_82542_##reg)))) reg 36 drivers/net/ethernet/intel/e1000/e1000_osdep.h #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \ reg 38 drivers/net/ethernet/intel/e1000/e1000_osdep.h (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ reg 41 drivers/net/ethernet/intel/e1000/e1000_osdep.h #define E1000_READ_REG_ARRAY(a, reg, offset) ( \ reg 43 drivers/net/ethernet/intel/e1000/e1000_osdep.h (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ reg 49 drivers/net/ethernet/intel/e1000/e1000_osdep.h #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \ reg 51 drivers/net/ethernet/intel/e1000/e1000_osdep.h (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ reg 54 drivers/net/ethernet/intel/e1000/e1000_osdep.h #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \ reg 56 drivers/net/ethernet/intel/e1000/e1000_osdep.h (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ reg 59 drivers/net/ethernet/intel/e1000/e1000_osdep.h #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \ reg 61 drivers/net/ethernet/intel/e1000/e1000_osdep.h (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ reg 64 drivers/net/ethernet/intel/e1000/e1000_osdep.h #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \ reg 66 drivers/net/ethernet/intel/e1000/e1000_osdep.h (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ reg 71 drivers/net/ethernet/intel/e1000/e1000_osdep.h #define E1000_WRITE_ICH_FLASH_REG(a, reg, value) ( \ reg 72 drivers/net/ethernet/intel/e1000/e1000_osdep.h writel((value), ((a)->flash_address + reg))) reg 74 drivers/net/ethernet/intel/e1000/e1000_osdep.h #define E1000_READ_ICH_FLASH_REG(a, reg) ( \ reg 75 drivers/net/ethernet/intel/e1000/e1000_osdep.h readl((a)->flash_address + reg)) reg 77 drivers/net/ethernet/intel/e1000/e1000_osdep.h #define E1000_WRITE_ICH_FLASH_REG16(a, reg, value) ( \ reg 78 drivers/net/ethernet/intel/e1000/e1000_osdep.h writew((value), ((a)->flash_address + reg))) reg 80 drivers/net/ethernet/intel/e1000/e1000_osdep.h #define E1000_READ_ICH_FLASH_REG16(a, reg) ( \ reg 81 drivers/net/ethernet/intel/e1000/e1000_osdep.h readw((a)->flash_address + reg)) reg 839 drivers/net/ethernet/intel/e1000e/80003es2lan.c u32 reg; reg 842 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg = er32(TXDCTL(0)); reg 843 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg |= BIT(22); reg 844 drivers/net/ethernet/intel/e1000e/80003es2lan.c ew32(TXDCTL(0), reg); reg 847 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg = er32(TXDCTL(1)); reg 848 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg |= BIT(22); reg 849 drivers/net/ethernet/intel/e1000e/80003es2lan.c ew32(TXDCTL(1), reg); reg 852 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg = er32(TARC(0)); reg 853 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg &= ~(0xF << 27); /* 30:27 */ reg 855 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg &= ~BIT(20); reg 856 drivers/net/ethernet/intel/e1000e/80003es2lan.c ew32(TARC(0), reg); reg 859 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg = er32(TARC(1)); reg 861 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg &= ~BIT(28); reg 863 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg |= BIT(28); reg 864 drivers/net/ethernet/intel/e1000e/80003es2lan.c ew32(TARC(1), reg); reg 869 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg = er32(RFCTL); reg 870 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); reg 871 drivers/net/ethernet/intel/e1000e/80003es2lan.c ew32(RFCTL, reg); reg 884 drivers/net/ethernet/intel/e1000e/80003es2lan.c u32 reg; reg 947 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL; reg 950 drivers/net/ethernet/intel/e1000e/80003es2lan.c ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); reg 954 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE; reg 955 drivers/net/ethernet/intel/e1000e/80003es2lan.c ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data); reg 959 drivers/net/ethernet/intel/e1000e/80003es2lan.c ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); reg 972 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg = er32(CTRL_EXT); reg 973 drivers/net/ethernet/intel/e1000e/80003es2lan.c reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK; reg 974 drivers/net/ethernet/intel/e1000e/80003es2lan.c ew32(CTRL_EXT, reg); reg 1144 drivers/net/ethernet/intel/e1000e/82571.c u32 reg; reg 1147 drivers/net/ethernet/intel/e1000e/82571.c reg = er32(TXDCTL(0)); reg 1148 drivers/net/ethernet/intel/e1000e/82571.c reg |= BIT(22); reg 1149 drivers/net/ethernet/intel/e1000e/82571.c ew32(TXDCTL(0), reg); reg 1152 drivers/net/ethernet/intel/e1000e/82571.c reg = er32(TXDCTL(1)); reg 1153 drivers/net/ethernet/intel/e1000e/82571.c reg |= BIT(22); reg 1154 drivers/net/ethernet/intel/e1000e/82571.c ew32(TXDCTL(1), reg); reg 1157 drivers/net/ethernet/intel/e1000e/82571.c reg = er32(TARC(0)); reg 1158 drivers/net/ethernet/intel/e1000e/82571.c reg &= ~(0xF << 27); /* 30:27 */ reg 1162 drivers/net/ethernet/intel/e1000e/82571.c reg |= BIT(23) | BIT(24) | BIT(25) | BIT(26); reg 1166 drivers/net/ethernet/intel/e1000e/82571.c reg |= BIT(26); reg 1171 drivers/net/ethernet/intel/e1000e/82571.c ew32(TARC(0), reg); reg 1174 drivers/net/ethernet/intel/e1000e/82571.c reg = er32(TARC(1)); reg 1178 drivers/net/ethernet/intel/e1000e/82571.c reg &= ~(BIT(29) | BIT(30)); reg 1179 drivers/net/ethernet/intel/e1000e/82571.c reg |= BIT(22) | BIT(24) | BIT(25) | BIT(26); reg 1181 drivers/net/ethernet/intel/e1000e/82571.c reg &= ~BIT(28); reg 1183 drivers/net/ethernet/intel/e1000e/82571.c reg |= BIT(28); reg 1184 drivers/net/ethernet/intel/e1000e/82571.c ew32(TARC(1), reg); reg 1195 drivers/net/ethernet/intel/e1000e/82571.c reg = er32(CTRL); reg 1196 drivers/net/ethernet/intel/e1000e/82571.c reg &= ~BIT(29); reg 1197 drivers/net/ethernet/intel/e1000e/82571.c ew32(CTRL, reg); reg 1208 drivers/net/ethernet/intel/e1000e/82571.c reg = er32(CTRL_EXT); reg 1209 drivers/net/ethernet/intel/e1000e/82571.c reg &= ~BIT(23); reg 1210 drivers/net/ethernet/intel/e1000e/82571.c reg |= BIT(22); reg 1211 drivers/net/ethernet/intel/e1000e/82571.c ew32(CTRL_EXT, reg); reg 1218 drivers/net/ethernet/intel/e1000e/82571.c reg = er32(PBA_ECC); reg 1219 drivers/net/ethernet/intel/e1000e/82571.c reg |= E1000_PBA_ECC_CORR_EN; reg 1220 drivers/net/ethernet/intel/e1000e/82571.c ew32(PBA_ECC, reg); reg 1227 drivers/net/ethernet/intel/e1000e/82571.c reg = er32(CTRL_EXT); reg 1228 drivers/net/ethernet/intel/e1000e/82571.c reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; reg 1229 drivers/net/ethernet/intel/e1000e/82571.c ew32(CTRL_EXT, reg); reg 1236 drivers/net/ethernet/intel/e1000e/82571.c reg = er32(RFCTL); reg 1237 drivers/net/ethernet/intel/e1000e/82571.c reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); reg 1238 drivers/net/ethernet/intel/e1000e/82571.c ew32(RFCTL, reg); reg 1245 drivers/net/ethernet/intel/e1000e/82571.c reg = er32(GCR); reg 1246 drivers/net/ethernet/intel/e1000e/82571.c reg |= BIT(22); reg 1247 drivers/net/ethernet/intel/e1000e/82571.c ew32(GCR, reg); reg 1255 drivers/net/ethernet/intel/e1000e/82571.c reg = er32(GCR2); reg 1256 drivers/net/ethernet/intel/e1000e/82571.c reg |= 1; reg 1257 drivers/net/ethernet/intel/e1000e/82571.c ew32(GCR2, reg); reg 769 drivers/net/ethernet/intel/e1000e/defines.h #define GG82563_REG(page, reg) \ reg 770 drivers/net/ethernet/intel/e1000e/defines.h (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) reg 572 drivers/net/ethernet/intel/e1000e/e1000.h static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) reg 574 drivers/net/ethernet/intel/e1000e/e1000.h return readl(hw->hw_addr + reg); reg 577 drivers/net/ethernet/intel/e1000e/e1000.h #define er32(reg) __er32(hw, E1000_##reg) reg 580 drivers/net/ethernet/intel/e1000e/e1000.h void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val); reg 582 drivers/net/ethernet/intel/e1000e/e1000.h #define ew32(reg, val) __ew32(hw, E1000_##reg, (val)) reg 586 drivers/net/ethernet/intel/e1000e/e1000.h #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ reg 587 drivers/net/ethernet/intel/e1000e/e1000.h (__ew32((a), (reg + ((offset) << 2)), (value))) reg 589 drivers/net/ethernet/intel/e1000e/e1000.h #define E1000_READ_REG_ARRAY(a, reg, offset) \ reg 590 drivers/net/ethernet/intel/e1000e/e1000.h (readl((a)->hw_addr + reg + ((offset) << 2))) reg 769 drivers/net/ethernet/intel/e1000e/ethtool.c int reg, int offset, u32 mask, u32 write) reg 776 drivers/net/ethernet/intel/e1000e/ethtool.c E1000_WRITE_REG_ARRAY(&adapter->hw, reg, offset, reg 778 drivers/net/ethernet/intel/e1000e/ethtool.c val = E1000_READ_REG_ARRAY(&adapter->hw, reg, offset); reg 781 drivers/net/ethernet/intel/e1000e/ethtool.c reg + (offset << 2), val, reg 783 drivers/net/ethernet/intel/e1000e/ethtool.c *data = reg; reg 791 drivers/net/ethernet/intel/e1000e/ethtool.c int reg, u32 mask, u32 write) reg 795 drivers/net/ethernet/intel/e1000e/ethtool.c __ew32(&adapter->hw, reg, write & mask); reg 796 drivers/net/ethernet/intel/e1000e/ethtool.c val = __er32(&adapter->hw, reg); reg 799 drivers/net/ethernet/intel/e1000e/ethtool.c reg, (val & mask), (write & mask)); reg 800 drivers/net/ethernet/intel/e1000e/ethtool.c *data = reg; reg 806 drivers/net/ethernet/intel/e1000e/ethtool.c #define REG_PATTERN_TEST_ARRAY(reg, offset, mask, write) \ reg 808 drivers/net/ethernet/intel/e1000e/ethtool.c if (reg_pattern_test(adapter, data, reg, offset, mask, write)) \ reg 811 drivers/net/ethernet/intel/e1000e/ethtool.c #define REG_PATTERN_TEST(reg, mask, write) \ reg 812 drivers/net/ethernet/intel/e1000e/ethtool.c REG_PATTERN_TEST_ARRAY(reg, 0, mask, write) reg 814 drivers/net/ethernet/intel/e1000e/ethtool.c #define REG_SET_AND_CHECK(reg, mask, write) \ reg 816 drivers/net/ethernet/intel/e1000e/ethtool.c if (reg_set_and_check(adapter, data, reg, mask, write)) \ reg 141 drivers/net/ethernet/intel/e1000e/ich8lan.c static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) reg 143 drivers/net/ethernet/intel/e1000e/ich8lan.c return readw(hw->flash_address + reg); reg 146 drivers/net/ethernet/intel/e1000e/ich8lan.c static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) reg 148 drivers/net/ethernet/intel/e1000e/ich8lan.c return readl(hw->flash_address + reg); reg 151 drivers/net/ethernet/intel/e1000e/ich8lan.c static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) reg 153 drivers/net/ethernet/intel/e1000e/ich8lan.c writew(val, hw->flash_address + reg); reg 156 drivers/net/ethernet/intel/e1000e/ich8lan.c static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) reg 158 drivers/net/ethernet/intel/e1000e/ich8lan.c writel(val, hw->flash_address + reg); reg 161 drivers/net/ethernet/intel/e1000e/ich8lan.c #define er16flash(reg) __er16flash(hw, (reg)) reg 162 drivers/net/ethernet/intel/e1000e/ich8lan.c #define er32flash(reg) __er32flash(hw, (reg)) reg 163 drivers/net/ethernet/intel/e1000e/ich8lan.c #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) reg 164 drivers/net/ethernet/intel/e1000e/ich8lan.c #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) reg 905 drivers/net/ethernet/intel/e1000e/ich8lan.c u16 reg; reg 914 drivers/net/ethernet/intel/e1000e/ich8lan.c ®); reg 921 drivers/net/ethernet/intel/e1000e/ich8lan.c reg & reg 933 drivers/net/ethernet/intel/e1000e/ich8lan.c reg); reg 945 drivers/net/ethernet/intel/e1000e/ich8lan.c ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®); reg 950 drivers/net/ethernet/intel/e1000e/ich8lan.c reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; reg 954 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; reg 960 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= 50 << reg 967 drivers/net/ethernet/intel/e1000e/ich8lan.c ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg); reg 996 drivers/net/ethernet/intel/e1000e/ich8lan.c u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | reg 1056 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); reg 1057 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32(LTRV, reg); reg 2269 drivers/net/ethernet/intel/e1000e/ich8lan.c u32 reg = 0; reg 2291 drivers/net/ethernet/intel/e1000e/ich8lan.c reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); reg 2292 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= E1000_CTRL_FRCSPD; reg 2293 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32(CTRL, reg); reg 2825 drivers/net/ethernet/intel/e1000e/ich8lan.c u16 reg; reg 2851 drivers/net/ethernet/intel/e1000e/ich8lan.c e1e_rphy(hw, BM_PORT_GEN_CFG, ®); reg 2852 drivers/net/ethernet/intel/e1000e/ich8lan.c reg &= ~BM_WUC_HOST_WU_BIT; reg 2853 drivers/net/ethernet/intel/e1000e/ich8lan.c e1e_wphy(hw, BM_PORT_GEN_CFG, reg); reg 4642 drivers/net/ethernet/intel/e1000e/ich8lan.c u32 ctrl, reg; reg 4709 drivers/net/ethernet/intel/e1000e/ich8lan.c reg = er32(FEXTNVM3); reg 4710 drivers/net/ethernet/intel/e1000e/ich8lan.c reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; reg 4711 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; reg 4712 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32(FEXTNVM3, reg); reg 4738 drivers/net/ethernet/intel/e1000e/ich8lan.c reg = er32(KABGTXD); reg 4739 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= E1000_KABGTXD_BGSQLBIAS; reg 4740 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32(KABGTXD, reg); reg 4842 drivers/net/ethernet/intel/e1000e/ich8lan.c u32 reg; reg 4845 drivers/net/ethernet/intel/e1000e/ich8lan.c reg = er32(CTRL_EXT); reg 4846 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= BIT(22); reg 4849 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= E1000_CTRL_EXT_PHYPDEN; reg 4850 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32(CTRL_EXT, reg); reg 4853 drivers/net/ethernet/intel/e1000e/ich8lan.c reg = er32(TXDCTL(0)); reg 4854 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= BIT(22); reg 4855 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32(TXDCTL(0), reg); reg 4858 drivers/net/ethernet/intel/e1000e/ich8lan.c reg = er32(TXDCTL(1)); reg 4859 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= BIT(22); reg 4860 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32(TXDCTL(1), reg); reg 4863 drivers/net/ethernet/intel/e1000e/ich8lan.c reg = er32(TARC(0)); reg 4865 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= BIT(28) | BIT(29); reg 4866 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27); reg 4867 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32(TARC(0), reg); reg 4870 drivers/net/ethernet/intel/e1000e/ich8lan.c reg = er32(TARC(1)); reg 4872 drivers/net/ethernet/intel/e1000e/ich8lan.c reg &= ~BIT(28); reg 4874 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= BIT(28); reg 4875 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= BIT(24) | BIT(26) | BIT(30); reg 4876 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32(TARC(1), reg); reg 4880 drivers/net/ethernet/intel/e1000e/ich8lan.c reg = er32(STATUS); reg 4881 drivers/net/ethernet/intel/e1000e/ich8lan.c reg &= ~BIT(31); reg 4882 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32(STATUS, reg); reg 4888 drivers/net/ethernet/intel/e1000e/ich8lan.c reg = er32(RFCTL); reg 4889 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); reg 4895 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); reg 4896 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32(RFCTL, reg); reg 4900 drivers/net/ethernet/intel/e1000e/ich8lan.c reg = er32(PBECCSTS); reg 4901 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= E1000_PBECCSTS_ECC_ENABLE; reg 4902 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32(PBECCSTS, reg); reg 4904 drivers/net/ethernet/intel/e1000e/ich8lan.c reg = er32(CTRL); reg 4905 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= E1000_CTRL_MEHE; reg 4906 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32(CTRL, reg); reg 5203 drivers/net/ethernet/intel/e1000e/ich8lan.c u32 reg; reg 5213 drivers/net/ethernet/intel/e1000e/ich8lan.c reg = er32(PHY_CTRL); reg 5214 drivers/net/ethernet/intel/e1000e/ich8lan.c reg |= (E1000_PHY_CTRL_GBE_DISABLE | reg 5216 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32(PHY_CTRL, reg); reg 5236 drivers/net/ethernet/intel/e1000e/ich8lan.c reg = er32(CTRL); reg 5237 drivers/net/ethernet/intel/e1000e/ich8lan.c ew32(CTRL, reg | E1000_CTRL_PHY_RST); reg 107 drivers/net/ethernet/intel/e1000e/ich8lan.h #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ reg 108 drivers/net/ethernet/intel/e1000e/ich8lan.h ((reg) & MAX_PHY_REG_ADDRESS)) reg 49 drivers/net/ethernet/intel/e1000e/mac.c u32 reg; reg 54 drivers/net/ethernet/intel/e1000e/mac.c reg = er32(STATUS); reg 55 drivers/net/ethernet/intel/e1000e/mac.c bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; reg 132 drivers/net/ethernet/intel/e1000e/netdev.c void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) reg 137 drivers/net/ethernet/intel/e1000e/netdev.c writel(val, hw->hw_addr + reg); reg 4169 drivers/net/ethernet/intel/e1000e/netdev.c u32 reg; reg 4172 drivers/net/ethernet/intel/e1000e/netdev.c reg = er32(FEXTNVM7); reg 4173 drivers/net/ethernet/intel/e1000e/netdev.c reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; reg 4174 drivers/net/ethernet/intel/e1000e/netdev.c ew32(FEXTNVM7, reg); reg 4176 drivers/net/ethernet/intel/e1000e/netdev.c reg = er32(FEXTNVM9); reg 4177 drivers/net/ethernet/intel/e1000e/netdev.c reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | reg 4179 drivers/net/ethernet/intel/e1000e/netdev.c ew32(FEXTNVM9, reg); reg 125 drivers/net/ethernet/intel/e1000e/nvm.c u32 i, reg = 0; reg 129 drivers/net/ethernet/intel/e1000e/nvm.c reg = er32(EERD); reg 131 drivers/net/ethernet/intel/e1000e/nvm.c reg = er32(EEWR); reg 133 drivers/net/ethernet/intel/e1000e/nvm.c if (reg & E1000_NVM_RW_REG_DONE) reg 2317 drivers/net/ethernet/intel/e1000e/phy.c static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) reg 2321 drivers/net/ethernet/intel/e1000e/phy.c if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) reg 2639 drivers/net/ethernet/intel/e1000e/phy.c u16 reg = BM_PHY_REG_NUM(offset); reg 2658 drivers/net/ethernet/intel/e1000e/phy.c e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg); reg 2661 drivers/net/ethernet/intel/e1000e/phy.c ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); reg 2678 drivers/net/ethernet/intel/e1000e/phy.c e_dbg("Could not access PHY reg %d.%d\n", page, reg); reg 2741 drivers/net/ethernet/intel/e1000e/phy.c u16 reg = BM_PHY_REG_NUM(offset); reg 2767 drivers/net/ethernet/intel/e1000e/phy.c if (reg > MAX_PHY_MULTI_PAGE_REG) { reg 2780 drivers/net/ethernet/intel/e1000e/phy.c page << IGP_PAGE_SHIFT, reg); reg 2782 drivers/net/ethernet/intel/e1000e/phy.c ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data); reg 2848 drivers/net/ethernet/intel/e1000e/phy.c u16 reg = BM_PHY_REG_NUM(offset); reg 2880 drivers/net/ethernet/intel/e1000e/phy.c !(MAX_PHY_REG_ADDRESS & reg) && (data & BIT(11))) { reg 2890 drivers/net/ethernet/intel/e1000e/phy.c if (reg > MAX_PHY_MULTI_PAGE_REG) { reg 2903 drivers/net/ethernet/intel/e1000e/phy.c page << IGP_PAGE_SHIFT, reg); reg 2905 drivers/net/ethernet/intel/e1000e/phy.c ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, reg 94 drivers/net/ethernet/intel/e1000e/phy.h #define BM_PHY_REG(page, reg) \ reg 95 drivers/net/ethernet/intel/e1000e/phy.h (((reg) & MAX_PHY_REG_ADDRESS) |\ reg 97 drivers/net/ethernet/intel/e1000e/phy.h (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT))) reg 187 drivers/net/ethernet/intel/fm10k/fm10k_common.c u32 reg; reg 198 drivers/net/ethernet/intel/fm10k/fm10k_common.c reg = fm10k_read_reg(hw, FM10K_TXDCTL(i)); reg 200 drivers/net/ethernet/intel/fm10k/fm10k_common.c reg & ~FM10K_TXDCTL_ENABLE); reg 201 drivers/net/ethernet/intel/fm10k/fm10k_common.c reg = fm10k_read_reg(hw, FM10K_RXQCTL(i)); reg 203 drivers/net/ethernet/intel/fm10k/fm10k_common.c reg & ~FM10K_RXQCTL_ENABLE); reg 216 drivers/net/ethernet/intel/fm10k/fm10k_common.c reg = fm10k_read_reg(hw, FM10K_TXDCTL(i)); reg 217 drivers/net/ethernet/intel/fm10k/fm10k_common.c if (!~reg || !(reg & FM10K_TXDCTL_ENABLE)) { reg 218 drivers/net/ethernet/intel/fm10k/fm10k_common.c reg = fm10k_read_reg(hw, FM10K_RXQCTL(i)); reg 219 drivers/net/ethernet/intel/fm10k/fm10k_common.c if (!~reg || !(reg & FM10K_RXQCTL_ENABLE)) { reg 12 drivers/net/ethernet/intel/fm10k/fm10k_common.h u16 fm10k_read_pci_cfg_word(struct fm10k_hw *hw, u32 reg); reg 15 drivers/net/ethernet/intel/fm10k/fm10k_common.h u32 fm10k_read_reg(struct fm10k_hw *hw, int reg); reg 18 drivers/net/ethernet/intel/fm10k/fm10k_common.h #define fm10k_write_reg(hw, reg, val) \ reg 22 drivers/net/ethernet/intel/fm10k/fm10k_common.h writel((val), &hw_addr[(reg)]); \ reg 26 drivers/net/ethernet/intel/fm10k/fm10k_common.h #define fm10k_write_sw_reg(hw, reg, val) \ reg 30 drivers/net/ethernet/intel/fm10k/fm10k_common.h writel((val), &sw_addr[(reg)]); \ reg 34 drivers/net/ethernet/intel/fm10k/fm10k_pci.c u16 fm10k_read_pci_cfg_word(struct fm10k_hw *hw, u32 reg) reg 42 drivers/net/ethernet/intel/fm10k/fm10k_pci.c pci_read_config_word(interface->pdev, reg, &value); reg 49 drivers/net/ethernet/intel/fm10k/fm10k_pci.c u32 fm10k_read_reg(struct fm10k_hw *hw, int reg) reg 57 drivers/net/ethernet/intel/fm10k/fm10k_pci.c value = readl(&hw_addr[reg]); reg 58 drivers/net/ethernet/intel/fm10k/fm10k_pci.c if (!(~value) && (!reg || !(~readl(hw_addr)))) { reg 17 drivers/net/ethernet/intel/fm10k/fm10k_pf.c u32 reg; reg 45 drivers/net/ethernet/intel/fm10k/fm10k_pf.c reg = fm10k_read_reg(hw, FM10K_DMA_CTRL); reg 46 drivers/net/ethernet/intel/fm10k/fm10k_pf.c if (reg & (FM10K_DMA_CTRL_TX_ACTIVE | FM10K_DMA_CTRL_RX_ACTIVE)) reg 51 drivers/net/ethernet/intel/fm10k/fm10k_pf.c reg = FM10K_DMA_CTRL_DATAPATH_RESET; reg 52 drivers/net/ethernet/intel/fm10k/fm10k_pf.c fm10k_write_reg(hw, FM10K_DMA_CTRL, reg); reg 59 drivers/net/ethernet/intel/fm10k/fm10k_pf.c reg = fm10k_read_reg(hw, FM10K_IP); reg 60 drivers/net/ethernet/intel/fm10k/fm10k_pf.c if (!(reg & FM10K_IP_NOTINRESET)) reg 196 drivers/net/ethernet/intel/fm10k/fm10k_pf.c u32 vlan_table, reg, mask, bit, len; reg 223 drivers/net/ethernet/intel/fm10k/fm10k_pf.c for (reg = FM10K_VLAN_TABLE(vsi, vid / 32), bit = vid % 32; reg 225 drivers/net/ethernet/intel/fm10k/fm10k_pf.c len -= 32 - bit, reg++, bit = 0) { reg 227 drivers/net/ethernet/intel/fm10k/fm10k_pf.c vlan_table = fm10k_read_reg(hw, reg); reg 235 drivers/net/ethernet/intel/fm10k/fm10k_pf.c fm10k_write_reg(hw, reg, vlan_table ^ mask); reg 272 drivers/net/ethernet/intel/i40e/i40e_adminq.c u32 reg = 0; reg 285 drivers/net/ethernet/intel/i40e/i40e_adminq.c reg = rd32(hw, hw->aq.asq.bal); reg 286 drivers/net/ethernet/intel/i40e/i40e_adminq.c if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa)) reg 301 drivers/net/ethernet/intel/i40e/i40e_adminq.c u32 reg = 0; reg 317 drivers/net/ethernet/intel/i40e/i40e_adminq.c reg = rd32(hw, hw->aq.arq.bal); reg 318 drivers/net/ethernet/intel/i40e/i40e_adminq.c if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa)) reg 580 drivers/net/ethernet/intel/i40e/i40e_client.c u32 v_idx, i, reg_idx, reg; reg 606 drivers/net/ethernet/intel/i40e/i40e_client.c reg = (qv_info->ceq_idx & reg 610 drivers/net/ethernet/intel/i40e/i40e_client.c wr32(hw, reg_idx, reg); reg 612 drivers/net/ethernet/intel/i40e/i40e_client.c reg = (I40E_PFINT_CEQCTL_CAUSE_ENA_MASK | reg 618 drivers/net/ethernet/intel/i40e/i40e_client.c wr32(hw, I40E_PFINT_CEQCTL(qv_info->ceq_idx), reg); reg 621 drivers/net/ethernet/intel/i40e/i40e_client.c reg = (I40E_PFINT_AEQCTL_CAUSE_ENA_MASK | reg 626 drivers/net/ethernet/intel/i40e/i40e_client.c wr32(hw, I40E_PFINT_AEQCTL, reg); reg 1205 drivers/net/ethernet/intel/i40e/i40e_common.c u32 cnt, reg = 0; reg 1208 drivers/net/ethernet/intel/i40e/i40e_common.c reg = rd32(hw, I40E_GLGEN_RSTAT); reg 1209 drivers/net/ethernet/intel/i40e/i40e_common.c if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) reg 1215 drivers/net/ethernet/intel/i40e/i40e_common.c hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg); reg 1233 drivers/net/ethernet/intel/i40e/i40e_common.c u32 reg = 0; reg 1250 drivers/net/ethernet/intel/i40e/i40e_common.c reg = rd32(hw, I40E_GLGEN_RSTAT); reg 1251 drivers/net/ethernet/intel/i40e/i40e_common.c if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) reg 1255 drivers/net/ethernet/intel/i40e/i40e_common.c if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { reg 1262 drivers/net/ethernet/intel/i40e/i40e_common.c reg = rd32(hw, I40E_GLNVM_ULD); reg 1263 drivers/net/ethernet/intel/i40e/i40e_common.c reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | reg 1265 drivers/net/ethernet/intel/i40e/i40e_common.c if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | reg 1272 drivers/net/ethernet/intel/i40e/i40e_common.c if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | reg 1275 drivers/net/ethernet/intel/i40e/i40e_common.c hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg); reg 1288 drivers/net/ethernet/intel/i40e/i40e_common.c reg = rd32(hw, I40E_PFGEN_CTRL); reg 1290 drivers/net/ethernet/intel/i40e/i40e_common.c (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); reg 1292 drivers/net/ethernet/intel/i40e/i40e_common.c reg = rd32(hw, I40E_PFGEN_CTRL); reg 1293 drivers/net/ethernet/intel/i40e/i40e_common.c if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) reg 1303 drivers/net/ethernet/intel/i40e/i40e_common.c } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { reg 1416 drivers/net/ethernet/intel/i40e/i40e_common.c u32 reg; reg 1422 drivers/net/ethernet/intel/i40e/i40e_common.c reg = rd32(hw, I40E_GLLAN_RCTL_0); reg 1426 drivers/net/ethernet/intel/i40e/i40e_common.c wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK))); reg 1428 drivers/net/ethernet/intel/i40e/i40e_common.c wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK)); reg 4657 drivers/net/ethernet/intel/i40e/i40e_common.c u16 reg, u8 phy_addr, u16 *value) reg 4664 drivers/net/ethernet/intel/i40e/i40e_common.c command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | reg 4702 drivers/net/ethernet/intel/i40e/i40e_common.c u16 reg, u8 phy_addr, u16 value) reg 4712 drivers/net/ethernet/intel/i40e/i40e_common.c command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | reg 4743 drivers/net/ethernet/intel/i40e/i40e_common.c u8 page, u16 reg, u8 phy_addr, u16 *value) reg 4750 drivers/net/ethernet/intel/i40e/i40e_common.c command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | reg 4817 drivers/net/ethernet/intel/i40e/i40e_common.c u8 page, u16 reg, u8 phy_addr, u16 value) reg 4824 drivers/net/ethernet/intel/i40e/i40e_common.c command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | reg 4884 drivers/net/ethernet/intel/i40e/i40e_common.c u8 page, u16 reg, u8 phy_addr, u16 value) reg 4890 drivers/net/ethernet/intel/i40e/i40e_common.c status = i40e_write_phy_register_clause22(hw, reg, phy_addr, reg 4898 drivers/net/ethernet/intel/i40e/i40e_common.c status = i40e_write_phy_register_clause45(hw, page, reg, reg 4920 drivers/net/ethernet/intel/i40e/i40e_common.c u8 page, u16 reg, u8 phy_addr, u16 *value) reg 4926 drivers/net/ethernet/intel/i40e/i40e_common.c status = i40e_read_phy_register_clause22(hw, reg, phy_addr, reg 4935 drivers/net/ethernet/intel/i40e/i40e_common.c status = i40e_read_phy_register_clause45(hw, page, reg, reg 17 drivers/net/ethernet/intel/i40e/i40e_dcb.c u32 reg; reg 22 drivers/net/ethernet/intel/i40e/i40e_dcb.c reg = rd32(hw, I40E_PRTDCB_GENS); reg 23 drivers/net/ethernet/intel/i40e/i40e_dcb.c *status = (u16)((reg & I40E_PRTDCB_GENS_DCBX_STATUS_MASK) >> reg 14 drivers/net/ethernet/intel/i40e/i40e_diag.c u32 reg, u32 mask) reg 22 drivers/net/ethernet/intel/i40e/i40e_diag.c orig_val = rd32(hw, reg); reg 25 drivers/net/ethernet/intel/i40e/i40e_diag.c wr32(hw, reg, (pat & mask)); reg 26 drivers/net/ethernet/intel/i40e/i40e_diag.c val = rd32(hw, reg); reg 30 drivers/net/ethernet/intel/i40e/i40e_diag.c __func__, reg, pat, val); reg 35 drivers/net/ethernet/intel/i40e/i40e_diag.c wr32(hw, reg, orig_val); reg 36 drivers/net/ethernet/intel/i40e/i40e_diag.c val = rd32(hw, reg); reg 40 drivers/net/ethernet/intel/i40e/i40e_diag.c __func__, reg, orig_val, val); reg 80 drivers/net/ethernet/intel/i40e/i40e_diag.c u32 reg, mask; reg 102 drivers/net/ethernet/intel/i40e/i40e_diag.c reg = i40e_reg_list[i].offset + reg 104 drivers/net/ethernet/intel/i40e/i40e_diag.c ret_code = i40e_diag_reg_pattern_test(hw, reg, mask); reg 1717 drivers/net/ethernet/intel/i40e/i40e_ethtool.c u32 reg; reg 1732 drivers/net/ethernet/intel/i40e/i40e_ethtool.c reg = i40e_reg_list[i].offset reg 1734 drivers/net/ethernet/intel/i40e/i40e_ethtool.c reg_buf[ri++] = rd32(hw, reg); reg 591 drivers/net/ethernet/intel/i40e/i40e_main.c static void i40e_stat_update32(struct i40e_hw *hw, u32 reg, reg 596 drivers/net/ethernet/intel/i40e/i40e_main.c new_data = rd32(hw, reg); reg 611 drivers/net/ethernet/intel/i40e/i40e_main.c static void i40e_stat_update_and_clear32(struct i40e_hw *hw, u32 reg, u64 *stat) reg 613 drivers/net/ethernet/intel/i40e/i40e_main.c u32 new_data = rd32(hw, reg); reg 615 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, reg, 1); /* must write a nonzero value to clear register */ reg 8888 drivers/net/ethernet/intel/i40e/i40e_main.c int reg; reg 8919 drivers/net/ethernet/intel/i40e/i40e_main.c reg = rd32(&pf->hw, I40E_PFQF_CTL_1); reg 8920 drivers/net/ethernet/intel/i40e/i40e_main.c if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK)) reg 8923 drivers/net/ethernet/intel/i40e/i40e_main.c if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) { reg 10262 drivers/net/ethernet/intel/i40e/i40e_main.c u32 reg; reg 10269 drivers/net/ethernet/intel/i40e/i40e_main.c reg = rd32(hw, I40E_GL_MDET_TX); reg 10270 drivers/net/ethernet/intel/i40e/i40e_main.c if (reg & I40E_GL_MDET_TX_VALID_MASK) { reg 10271 drivers/net/ethernet/intel/i40e/i40e_main.c u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >> reg 10273 drivers/net/ethernet/intel/i40e/i40e_main.c u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >> reg 10275 drivers/net/ethernet/intel/i40e/i40e_main.c u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >> reg 10277 drivers/net/ethernet/intel/i40e/i40e_main.c u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >> reg 10286 drivers/net/ethernet/intel/i40e/i40e_main.c reg = rd32(hw, I40E_GL_MDET_RX); reg 10287 drivers/net/ethernet/intel/i40e/i40e_main.c if (reg & I40E_GL_MDET_RX_VALID_MASK) { reg 10288 drivers/net/ethernet/intel/i40e/i40e_main.c u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >> reg 10290 drivers/net/ethernet/intel/i40e/i40e_main.c u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >> reg 10292 drivers/net/ethernet/intel/i40e/i40e_main.c u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >> reg 10303 drivers/net/ethernet/intel/i40e/i40e_main.c reg = rd32(hw, I40E_PF_MDET_TX); reg 10304 drivers/net/ethernet/intel/i40e/i40e_main.c if (reg & I40E_PF_MDET_TX_VALID_MASK) { reg 10308 drivers/net/ethernet/intel/i40e/i40e_main.c reg = rd32(hw, I40E_PF_MDET_RX); reg 10309 drivers/net/ethernet/intel/i40e/i40e_main.c if (reg & I40E_PF_MDET_RX_VALID_MASK) { reg 10318 drivers/net/ethernet/intel/i40e/i40e_main.c reg = rd32(hw, I40E_VP_MDET_TX(i)); reg 10319 drivers/net/ethernet/intel/i40e/i40e_main.c if (reg & I40E_VP_MDET_TX_VALID_MASK) { reg 10329 drivers/net/ethernet/intel/i40e/i40e_main.c reg = rd32(hw, I40E_VP_MDET_RX(i)); reg 10330 drivers/net/ethernet/intel/i40e/i40e_main.c if (reg & I40E_VP_MDET_RX_VALID_MASK) { reg 10343 drivers/net/ethernet/intel/i40e/i40e_main.c reg = rd32(hw, I40E_PFINT_ICR0_ENA); reg 10344 drivers/net/ethernet/intel/i40e/i40e_main.c reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; reg 10345 drivers/net/ethernet/intel/i40e/i40e_main.c wr32(hw, I40E_PFINT_ICR0_ENA, reg); reg 15491 drivers/net/ethernet/intel/i40e/i40e_main.c u32 reg; reg 15504 drivers/net/ethernet/intel/i40e/i40e_main.c reg = rd32(&pf->hw, I40E_GLGEN_RTRIG); reg 15505 drivers/net/ethernet/intel/i40e/i40e_main.c if (reg == 0) reg 26 drivers/net/ethernet/intel/i40e/i40e_osdep.h #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg))) reg 27 drivers/net/ethernet/intel/i40e/i40e_osdep.h #define rd32(a, reg) readl((a)->hw_addr + (reg)) reg 29 drivers/net/ethernet/intel/i40e/i40e_osdep.h #define wr64(a, reg, value) writeq((value), ((a)->hw_addr + (reg))) reg 30 drivers/net/ethernet/intel/i40e/i40e_osdep.h #define rd64(a, reg) readq((a)->hw_addr + (reg)) reg 422 drivers/net/ethernet/intel/i40e/i40e_prototype.h u16 reg, u8 phy_addr, u16 *value); reg 424 drivers/net/ethernet/intel/i40e/i40e_prototype.h u16 reg, u8 phy_addr, u16 value); reg 426 drivers/net/ethernet/intel/i40e/i40e_prototype.h u8 page, u16 reg, u8 phy_addr, u16 *value); reg 428 drivers/net/ethernet/intel/i40e/i40e_prototype.h u8 page, u16 reg, u8 phy_addr, u16 value); reg 429 drivers/net/ethernet/intel/i40e/i40e_prototype.h i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page, u16 reg, reg 431 drivers/net/ethernet/intel/i40e/i40e_prototype.h i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page, u16 reg, reg 292 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c u32 reg, reg_idx; reg 329 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = ((qtype << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT) | pf_queue_id); reg 331 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c wr32(hw, reg_idx, reg); reg 360 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = (vector_id) | reg 365 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c wr32(hw, reg_idx, reg); reg 373 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = rd32(hw, I40E_GLINT_CTL); reg 374 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (!(reg & I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK)) { reg 375 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg |= I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK; reg 376 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c wr32(hw, I40E_GLINT_CTL, reg); reg 404 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c u32 v_idx, reg_idx, reg; reg 415 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = rd32(hw, I40E_VPINT_CEQCTL(reg_idx)); reg 416 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c next_q_index = (reg & I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK) reg 418 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c next_q_type = (reg & I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK) reg 422 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = (next_q_index & reg 427 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c wr32(hw, I40E_VPINT_LNKLSTN(reg_idx), reg); reg 447 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c u32 v_idx, i, reg_idx, reg; reg 494 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = rd32(hw, I40E_VPINT_LNKLSTN(reg_idx)); reg 495 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c next_q_idx = ((reg & I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK) >> reg 497 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c next_q_type = ((reg & I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK) >> reg 502 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = (I40E_VPINT_CEQCTL_CAUSE_ENA_MASK | reg 507 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c wr32(hw, I40E_VPINT_CEQCTL(reg_idx), reg); reg 510 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = (qv_info->ceq_idx & reg 514 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c wr32(hw, I40E_VPINT_LNKLSTN(reg_idx), reg); reg 518 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = (I40E_VPINT_AEQCTL_CAUSE_ENA_MASK | reg 522 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c wr32(hw, I40E_VPINT_AEQCTL(vf->vf_id), reg); reg 803 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c u32 reg, num_tc = 1; /* VF has at least one traffic class */ reg 822 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = 0x07FF07FF; reg 827 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = qid; reg 830 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg |= qid << 16; reg 834 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg); reg 850 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c u32 reg, total_qps = 0; reg 870 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = (qid & I40E_VPLAN_QTABLE_QINDEX_MASK); reg 872 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg); reg 888 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c u32 reg; reg 898 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = I40E_VPLAN_MAPENA_TXRX_ENA_MASK; reg 899 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c wr32(hw, I40E_VPLAN_MAPENA(vf->vf_id), reg); reg 937 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c u32 reg_idx, reg; reg 998 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = (I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK | reg 1000 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c wr32(hw, reg_idx, reg); reg 1095 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c u32 reg; reg 1102 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = rd32(hw, I40E_PF_PCI_CIAD); reg 1103 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if ((reg & VF_TRANS_PENDING_MASK) == 0) reg 1245 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c u32 reg, reg_idx, bit_idx; reg 1263 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id)); reg 1264 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg |= I40E_VPGEN_VFRTRIG_VFSWR_MASK; reg 1265 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id), reg); reg 1291 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c u32 reg; reg 1309 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id)); reg 1310 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg &= ~I40E_VPGEN_VFRTRIG_VFSWR_MASK; reg 1311 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id), reg); reg 1345 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c u32 reg; reg 1366 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = rd32(hw, I40E_VPGEN_VFRSTAT(vf->vf_id)); reg 1367 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (reg & I40E_VPGEN_VFRSTAT_VFRD_MASK) { reg 1410 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c u32 reg; reg 1438 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = rd32(hw, I40E_VPGEN_VFRSTAT(vf->vf_id)); reg 1439 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (!(reg & I40E_VPGEN_VFRSTAT_VFRD_MASK)) reg 3887 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c u32 reg, reg_idx, bit_idx; reg 3899 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = rd32(hw, I40E_PFINT_ICR0_ENA); reg 3900 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg |= I40E_PFINT_ICR0_ENA_VFLR_MASK; reg 3901 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c wr32(hw, I40E_PFINT_ICR0_ENA, reg); reg 3910 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c reg = rd32(hw, I40E_GLGEN_VFLRSTAT(reg_idx)); reg 3911 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (reg & BIT(bit_idx)) reg 259 drivers/net/ethernet/intel/iavf/iavf_adminq.c u32 reg = 0; reg 272 drivers/net/ethernet/intel/iavf/iavf_adminq.c reg = rd32(hw, hw->aq.asq.bal); reg 273 drivers/net/ethernet/intel/iavf/iavf_adminq.c if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa)) reg 288 drivers/net/ethernet/intel/iavf/iavf_adminq.c u32 reg = 0; reg 304 drivers/net/ethernet/intel/iavf/iavf_adminq.c reg = rd32(hw, hw->aq.arq.bal); reg 305 drivers/net/ethernet/intel/iavf/iavf_adminq.c if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa)) reg 22 drivers/net/ethernet/intel/iavf/iavf_osdep.h #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg))) reg 23 drivers/net/ethernet/intel/iavf/iavf_osdep.h #define rd32(a, reg) readl((a)->hw_addr + (reg)) reg 25 drivers/net/ethernet/intel/iavf/iavf_osdep.h #define wr64(a, reg, value) writeq((value), ((a)->hw_addr + (reg))) reg 26 drivers/net/ethernet/intel/iavf/iavf_osdep.h #define rd64(a, reg) readq((a)->hw_addr + (reg)) reg 937 drivers/net/ethernet/intel/ice/ice_common.c u32 cnt, reg = 0, grst_delay, uld_mask; reg 948 drivers/net/ethernet/intel/ice/ice_common.c reg = rd32(hw, GLGEN_RSTAT); reg 949 drivers/net/ethernet/intel/ice/ice_common.c if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) reg 971 drivers/net/ethernet/intel/ice/ice_common.c reg = rd32(hw, GLNVM_ULD) & uld_mask; reg 972 drivers/net/ethernet/intel/ice/ice_common.c if (reg == uld_mask) { reg 983 drivers/net/ethernet/intel/ice/ice_common.c reg); reg 999 drivers/net/ethernet/intel/ice/ice_common.c u32 cnt, reg; reg 1016 drivers/net/ethernet/intel/ice/ice_common.c reg = rd32(hw, PFGEN_CTRL); reg 1018 drivers/net/ethernet/intel/ice/ice_common.c wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); reg 1021 drivers/net/ethernet/intel/ice/ice_common.c reg = rd32(hw, PFGEN_CTRL); reg 1022 drivers/net/ethernet/intel/ice/ice_common.c if (!(reg & PFGEN_CTRL_PFSWR_M)) reg 3468 drivers/net/ethernet/intel/ice/ice_common.c ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, reg 3471 drivers/net/ethernet/intel/ice/ice_common.c u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); reg 3505 drivers/net/ethernet/intel/ice/ice_common.c ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, reg 3510 drivers/net/ethernet/intel/ice/ice_common.c new_data = rd32(hw, reg); reg 137 drivers/net/ethernet/intel/ice/ice_common.h ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, reg 140 drivers/net/ethernet/intel/ice/ice_common.h ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, reg 178 drivers/net/ethernet/intel/ice/ice_dcb.c u32 reg; reg 180 drivers/net/ethernet/intel/ice/ice_dcb.c reg = rd32(hw, PRTDCB_GENS); reg 181 drivers/net/ethernet/intel/ice/ice_dcb.c return (u8)((reg & PRTDCB_GENS_DCBX_STATUS_M) >> reg 342 drivers/net/ethernet/intel/ice/ice_ethtool.c static int ice_reg_pattern_test(struct ice_hw *hw, u32 reg, u32 mask) reg 352 drivers/net/ethernet/intel/ice/ice_ethtool.c orig_val = rd32(hw, reg); reg 356 drivers/net/ethernet/intel/ice/ice_ethtool.c wr32(hw, reg, pattern); reg 357 drivers/net/ethernet/intel/ice/ice_ethtool.c val = rd32(hw, reg); reg 362 drivers/net/ethernet/intel/ice/ice_ethtool.c , __func__, reg, pattern, val); reg 366 drivers/net/ethernet/intel/ice/ice_ethtool.c wr32(hw, reg, orig_val); reg 367 drivers/net/ethernet/intel/ice/ice_ethtool.c val = rd32(hw, reg); reg 371 drivers/net/ethernet/intel/ice/ice_ethtool.c , __func__, reg, orig_val, val); reg 413 drivers/net/ethernet/intel/ice/ice_ethtool.c u32 reg = ice_reg_list[i].address + reg 417 drivers/net/ethernet/intel/ice/ice_ethtool.c if (ice_reg_pattern_test(hw, reg, mask)) reg 2897 drivers/net/ethernet/intel/ice/ice_lib.c u16 reg; reg 2899 drivers/net/ethernet/intel/ice/ice_lib.c reg = vsi->tx_rings[i]->reg_idx; reg 2900 drivers/net/ethernet/intel/ice/ice_lib.c val = rd32(hw, QINT_TQCTL(reg)); reg 2902 drivers/net/ethernet/intel/ice/ice_lib.c wr32(hw, QINT_TQCTL(reg), val); reg 2910 drivers/net/ethernet/intel/ice/ice_lib.c u16 reg; reg 2912 drivers/net/ethernet/intel/ice/ice_lib.c reg = vsi->rx_rings[i]->reg_idx; reg 2913 drivers/net/ethernet/intel/ice/ice_lib.c val = rd32(hw, QINT_RQCTL(reg)); reg 2915 drivers/net/ethernet/intel/ice/ice_lib.c wr32(hw, QINT_RQCTL(reg), val); reg 1227 drivers/net/ethernet/intel/ice/ice_main.c u32 reg; reg 1234 drivers/net/ethernet/intel/ice/ice_main.c reg = rd32(hw, GL_MDET_TX_PQM); reg 1235 drivers/net/ethernet/intel/ice/ice_main.c if (reg & GL_MDET_TX_PQM_VALID_M) { reg 1236 drivers/net/ethernet/intel/ice/ice_main.c u8 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >> reg 1238 drivers/net/ethernet/intel/ice/ice_main.c u16 vf_num = (reg & GL_MDET_TX_PQM_VF_NUM_M) >> reg 1240 drivers/net/ethernet/intel/ice/ice_main.c u8 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >> reg 1242 drivers/net/ethernet/intel/ice/ice_main.c u16 queue = ((reg & GL_MDET_TX_PQM_QNUM_M) >> reg 1252 drivers/net/ethernet/intel/ice/ice_main.c reg = rd32(hw, GL_MDET_TX_TCLAN); reg 1253 drivers/net/ethernet/intel/ice/ice_main.c if (reg & GL_MDET_TX_TCLAN_VALID_M) { reg 1254 drivers/net/ethernet/intel/ice/ice_main.c u8 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >> reg 1256 drivers/net/ethernet/intel/ice/ice_main.c u16 vf_num = (reg & GL_MDET_TX_TCLAN_VF_NUM_M) >> reg 1258 drivers/net/ethernet/intel/ice/ice_main.c u8 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >> reg 1260 drivers/net/ethernet/intel/ice/ice_main.c u16 queue = ((reg & GL_MDET_TX_TCLAN_QNUM_M) >> reg 1270 drivers/net/ethernet/intel/ice/ice_main.c reg = rd32(hw, GL_MDET_RX); reg 1271 drivers/net/ethernet/intel/ice/ice_main.c if (reg & GL_MDET_RX_VALID_M) { reg 1272 drivers/net/ethernet/intel/ice/ice_main.c u8 pf_num = (reg & GL_MDET_RX_PF_NUM_M) >> reg 1274 drivers/net/ethernet/intel/ice/ice_main.c u16 vf_num = (reg & GL_MDET_RX_VF_NUM_M) >> reg 1276 drivers/net/ethernet/intel/ice/ice_main.c u8 event = (reg & GL_MDET_RX_MAL_TYPE_M) >> reg 1278 drivers/net/ethernet/intel/ice/ice_main.c u16 queue = ((reg & GL_MDET_RX_QNUM_M) >> reg 1291 drivers/net/ethernet/intel/ice/ice_main.c reg = rd32(hw, PF_MDET_TX_PQM); reg 1292 drivers/net/ethernet/intel/ice/ice_main.c if (reg & PF_MDET_TX_PQM_VALID_M) { reg 1298 drivers/net/ethernet/intel/ice/ice_main.c reg = rd32(hw, PF_MDET_TX_TCLAN); reg 1299 drivers/net/ethernet/intel/ice/ice_main.c if (reg & PF_MDET_TX_TCLAN_VALID_M) { reg 1305 drivers/net/ethernet/intel/ice/ice_main.c reg = rd32(hw, PF_MDET_RX); reg 1306 drivers/net/ethernet/intel/ice/ice_main.c if (reg & PF_MDET_RX_VALID_M) { reg 1324 drivers/net/ethernet/intel/ice/ice_main.c reg = rd32(hw, VP_MDET_TX_PQM(i)); reg 1325 drivers/net/ethernet/intel/ice/ice_main.c if (reg & VP_MDET_TX_PQM_VALID_M) { reg 1332 drivers/net/ethernet/intel/ice/ice_main.c reg = rd32(hw, VP_MDET_TX_TCLAN(i)); reg 1333 drivers/net/ethernet/intel/ice/ice_main.c if (reg & VP_MDET_TX_TCLAN_VALID_M) { reg 1340 drivers/net/ethernet/intel/ice/ice_main.c reg = rd32(hw, VP_MDET_TX_TDPU(i)); reg 1341 drivers/net/ethernet/intel/ice/ice_main.c if (reg & VP_MDET_TX_TDPU_VALID_M) { reg 1348 drivers/net/ethernet/intel/ice/ice_main.c reg = rd32(hw, VP_MDET_RX(i)); reg 1349 drivers/net/ethernet/intel/ice/ice_main.c if (reg & VP_MDET_RX_VALID_M) { reg 3082 drivers/net/ethernet/intel/ice/ice_main.c u32 reg; reg 3097 drivers/net/ethernet/intel/ice/ice_main.c reg = rd32(&pf->hw, GLGEN_RTRIG); reg 3098 drivers/net/ethernet/intel/ice/ice_main.c if (!reg) reg 13 drivers/net/ethernet/intel/ice/ice_osdep.h #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg))) reg 14 drivers/net/ethernet/intel/ice/ice_osdep.h #define rd32(a, reg) readl((a)->hw_addr + (reg)) reg 15 drivers/net/ethernet/intel/ice/ice_osdep.h #define wr64(a, reg, value) writeq((value), ((a)->hw_addr + (reg))) reg 16 drivers/net/ethernet/intel/ice/ice_osdep.h #define rd64(a, reg) readq((a)->hw_addr + (reg)) reg 199 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c u32 reg; reg 201 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c reg = (((1 << GLINT_VECT2FUNC_IS_PF_S) & reg 205 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c wr32(hw, GLINT_VECT2FUNC(v), reg); reg 369 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c u32 reg, reg_idx, bit_idx; reg 400 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c reg = rd32(hw, VPGEN_VFRTRIG(vf->vf_id)); reg 401 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c reg |= VPGEN_VFRTRIG_VFSWR_M; reg 402 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c wr32(hw, VPGEN_VFRTRIG(vf->vf_id), reg); reg 413 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c reg = rd32(hw, PF_PCI_CIAD); reg 415 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c if ((reg & VF_TRANS_PENDING_M) == 0) reg 640 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c u32 reg; reg 651 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c reg = (((abs_first << VPINT_ALLOC_FIRST_S) & VPINT_ALLOC_FIRST_M) | reg 654 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c wr32(hw, VPINT_ALLOC(vf->vf_id), reg); reg 656 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c reg = (((abs_first << VPINT_ALLOC_PCI_FIRST_S) reg 660 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c wr32(hw, VPINT_ALLOC_PCI(vf->vf_id), reg); reg 663 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c reg = (((abs_vf_id << GLINT_VECT2FUNC_VF_NUM_S) & reg 667 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c wr32(hw, GLINT_VECT2FUNC(v), reg); reg 683 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c reg = (((vsi->txq_map[0] << VPLAN_TX_QBASE_VFFIRSTQ_S) & reg 687 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c wr32(hw, VPLAN_TX_QBASE(vf->vf_id), reg); reg 702 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c reg = (((vsi->rxq_map[0] << VPLAN_RX_QBASE_VFFIRSTQ_S) & reg 706 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c wr32(hw, VPLAN_RX_QBASE(vf->vf_id), reg); reg 938 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c u32 reg; reg 955 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c reg = rd32(hw, VPGEN_VFRTRIG(vf->vf_id)); reg 956 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c reg &= ~VPGEN_VFRTRIG_VFSWR_M; reg 957 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c wr32(hw, VPGEN_VFRTRIG(vf->vf_id), reg); reg 1107 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c u32 reg; reg 1110 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c reg = rd32(hw, VPGEN_VFRSTAT(vf->vf_id)); reg 1111 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c if (!(reg & VPGEN_VFRSTAT_VFRD_M)) { reg 1168 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c u32 reg; reg 1206 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c reg = rd32(hw, VPGEN_VFRSTAT(vf->vf_id)); reg 1207 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c if (reg & VPGEN_VFRSTAT_VFRD_M) { reg 1481 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c u32 reg; reg 1494 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c reg = rd32(hw, GLGEN_VFLRSTAT(reg_idx)); reg 1495 drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c if (reg & BIT(bit_idx)) reg 90 drivers/net/ethernet/intel/igb/e1000_82575.c u32 reg = 0; reg 96 drivers/net/ethernet/intel/igb/e1000_82575.c reg = rd32(E1000_MDIC); reg 97 drivers/net/ethernet/intel/igb/e1000_82575.c ext_mdio = !!(reg & E1000_MDIC_DEST); reg 104 drivers/net/ethernet/intel/igb/e1000_82575.c reg = rd32(E1000_MDICNFG); reg 105 drivers/net/ethernet/intel/igb/e1000_82575.c ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); reg 1326 drivers/net/ethernet/intel/igb/e1000_82575.c u32 reg; reg 1334 drivers/net/ethernet/intel/igb/e1000_82575.c reg = rd32(E1000_PCS_CFG0); reg 1335 drivers/net/ethernet/intel/igb/e1000_82575.c reg |= E1000_PCS_CFG_PCS_EN; reg 1336 drivers/net/ethernet/intel/igb/e1000_82575.c wr32(E1000_PCS_CFG0, reg); reg 1339 drivers/net/ethernet/intel/igb/e1000_82575.c reg = rd32(E1000_CTRL_EXT); reg 1340 drivers/net/ethernet/intel/igb/e1000_82575.c reg &= ~E1000_CTRL_EXT_SDP3_DATA; reg 1341 drivers/net/ethernet/intel/igb/e1000_82575.c wr32(E1000_CTRL_EXT, reg); reg 1421 drivers/net/ethernet/intel/igb/e1000_82575.c u32 reg; reg 1429 drivers/net/ethernet/intel/igb/e1000_82575.c reg = rd32(E1000_PCS_CFG0); reg 1430 drivers/net/ethernet/intel/igb/e1000_82575.c reg &= ~E1000_PCS_CFG_PCS_EN; reg 1431 drivers/net/ethernet/intel/igb/e1000_82575.c wr32(E1000_PCS_CFG0, reg); reg 1434 drivers/net/ethernet/intel/igb/e1000_82575.c reg = rd32(E1000_CTRL_EXT); reg 1435 drivers/net/ethernet/intel/igb/e1000_82575.c reg |= E1000_CTRL_EXT_SDP3_DATA; reg 1436 drivers/net/ethernet/intel/igb/e1000_82575.c wr32(E1000_CTRL_EXT, reg); reg 1656 drivers/net/ethernet/intel/igb/e1000_82575.c u32 ctrl_ext, ctrl_reg, reg, anadv_reg; reg 1687 drivers/net/ethernet/intel/igb/e1000_82575.c reg = rd32(E1000_CONNSW); reg 1688 drivers/net/ethernet/intel/igb/e1000_82575.c reg |= E1000_CONNSW_ENRGSRC; reg 1689 drivers/net/ethernet/intel/igb/e1000_82575.c wr32(E1000_CONNSW, reg); reg 1692 drivers/net/ethernet/intel/igb/e1000_82575.c reg = rd32(E1000_PCS_LCTL); reg 1702 drivers/net/ethernet/intel/igb/e1000_82575.c reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); reg 1729 drivers/net/ethernet/intel/igb/e1000_82575.c reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; reg 1740 drivers/net/ethernet/intel/igb/e1000_82575.c reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | reg 1745 drivers/net/ethernet/intel/igb/e1000_82575.c reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ reg 1749 drivers/net/ethernet/intel/igb/e1000_82575.c reg &= ~E1000_PCS_LCTL_FORCE_FCTRL; reg 1768 drivers/net/ethernet/intel/igb/e1000_82575.c hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); reg 1771 drivers/net/ethernet/intel/igb/e1000_82575.c reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ reg 1774 drivers/net/ethernet/intel/igb/e1000_82575.c reg |= E1000_PCS_LCTL_FORCE_FCTRL; reg 1776 drivers/net/ethernet/intel/igb/e1000_82575.c hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); reg 1779 drivers/net/ethernet/intel/igb/e1000_82575.c wr32(E1000_PCS_LCTL, reg); reg 549 drivers/net/ethernet/intel/igb/e1000_hw.h s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); reg 550 drivers/net/ethernet/intel/igb/e1000_hw.h s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); reg 552 drivers/net/ethernet/intel/igb/e1000_hw.h void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); reg 553 drivers/net/ethernet/intel/igb/e1000_hw.h void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); reg 630 drivers/net/ethernet/intel/igb/e1000_i210.c u32 i, reg; reg 633 drivers/net/ethernet/intel/igb/e1000_i210.c reg = rd32(E1000_EECD); reg 634 drivers/net/ethernet/intel/igb/e1000_i210.c if (reg & E1000_EECD_FLUDONE_I210) { reg 29 drivers/net/ethernet/intel/igb/e1000_mac.c u32 reg; reg 58 drivers/net/ethernet/intel/igb/e1000_mac.c reg = rd32(E1000_STATUS); reg 59 drivers/net/ethernet/intel/igb/e1000_mac.c bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; reg 1588 drivers/net/ethernet/intel/igb/e1000_mac.c s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, reg 1596 drivers/net/ethernet/intel/igb/e1000_mac.c wr32(reg, regvalue); reg 1601 drivers/net/ethernet/intel/igb/e1000_mac.c regvalue = rd32(reg); reg 1606 drivers/net/ethernet/intel/igb/e1000_mac.c hw_dbg("Reg %08x did not indicate ready\n", reg); reg 34 drivers/net/ethernet/intel/igb/e1000_mac.h s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, reg 130 drivers/net/ethernet/intel/igb/e1000_nvm.c u32 i, reg = 0; reg 135 drivers/net/ethernet/intel/igb/e1000_nvm.c reg = rd32(E1000_EERD); reg 137 drivers/net/ethernet/intel/igb/e1000_nvm.c reg = rd32(E1000_EEWR); reg 139 drivers/net/ethernet/intel/igb/e1000_nvm.c if (reg & E1000_NVM_RW_REG_DONE) { reg 353 drivers/net/ethernet/intel/igb/e1000_regs.h u32 igb_rd32(struct e1000_hw *hw, u32 reg); reg 356 drivers/net/ethernet/intel/igb/e1000_regs.h #define wr32(reg, val) \ reg 360 drivers/net/ethernet/intel/igb/e1000_regs.h writel((val), &hw_addr[(reg)]); \ reg 363 drivers/net/ethernet/intel/igb/e1000_regs.h #define rd32(reg) (igb_rd32(hw, reg)) reg 367 drivers/net/ethernet/intel/igb/e1000_regs.h #define array_wr32(reg, offset, value) \ reg 368 drivers/net/ethernet/intel/igb/e1000_regs.h wr32((reg) + ((offset) << 2), (value)) reg 370 drivers/net/ethernet/intel/igb/e1000_regs.h #define array_rd32(reg, offset) (igb_rd32(hw, reg + ((offset) << 2))) reg 987 drivers/net/ethernet/intel/igb/igb_ethtool.c u16 reg; reg 1204 drivers/net/ethernet/intel/igb/igb_ethtool.c int reg, u32 mask, u32 write) reg 1211 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(reg, (_test[pat] & write)); reg 1212 drivers/net/ethernet/intel/igb/igb_ethtool.c val = rd32(reg) & mask; reg 1216 drivers/net/ethernet/intel/igb/igb_ethtool.c reg, val, (_test[pat] & write & mask)); reg 1217 drivers/net/ethernet/intel/igb/igb_ethtool.c *data = reg; reg 1226 drivers/net/ethernet/intel/igb/igb_ethtool.c int reg, u32 mask, u32 write) reg 1231 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(reg, write & mask); reg 1232 drivers/net/ethernet/intel/igb/igb_ethtool.c val = rd32(reg); reg 1236 drivers/net/ethernet/intel/igb/igb_ethtool.c reg, (val & mask), (write & mask)); reg 1237 drivers/net/ethernet/intel/igb/igb_ethtool.c *data = reg; reg 1244 drivers/net/ethernet/intel/igb/igb_ethtool.c #define REG_PATTERN_TEST(reg, mask, write) \ reg 1246 drivers/net/ethernet/intel/igb/igb_ethtool.c if (reg_pattern_test(adapter, data, reg, mask, write)) \ reg 1250 drivers/net/ethernet/intel/igb/igb_ethtool.c #define REG_SET_AND_CHECK(reg, mask, write) \ reg 1252 drivers/net/ethernet/intel/igb/igb_ethtool.c if (reg_set_and_check(adapter, data, reg, mask, write)) \ reg 1310 drivers/net/ethernet/intel/igb/igb_ethtool.c while (test->reg) { reg 1314 drivers/net/ethernet/intel/igb/igb_ethtool.c REG_PATTERN_TEST(test->reg + reg 1320 drivers/net/ethernet/intel/igb/igb_ethtool.c REG_SET_AND_CHECK(test->reg + reg 1327 drivers/net/ethernet/intel/igb/igb_ethtool.c (adapter->hw.hw_addr + test->reg) reg 1331 drivers/net/ethernet/intel/igb/igb_ethtool.c REG_PATTERN_TEST(test->reg + (i * 4), reg 1336 drivers/net/ethernet/intel/igb/igb_ethtool.c REG_PATTERN_TEST(test->reg + (i * 8), reg 1341 drivers/net/ethernet/intel/igb/igb_ethtool.c REG_PATTERN_TEST((test->reg + 4) + (i * 8), reg 1667 drivers/net/ethernet/intel/igb/igb_ethtool.c u32 reg; reg 1669 drivers/net/ethernet/intel/igb/igb_ethtool.c reg = rd32(E1000_CTRL_EXT); reg 1672 drivers/net/ethernet/intel/igb/igb_ethtool.c if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) { reg 1680 drivers/net/ethernet/intel/igb/igb_ethtool.c reg = rd32(E1000_MPHY_ADDR_CTL); reg 1681 drivers/net/ethernet/intel/igb/igb_ethtool.c reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | reg 1683 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(E1000_MPHY_ADDR_CTL, reg); reg 1685 drivers/net/ethernet/intel/igb/igb_ethtool.c reg = rd32(E1000_MPHY_DATA); reg 1686 drivers/net/ethernet/intel/igb/igb_ethtool.c reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN; reg 1687 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(E1000_MPHY_DATA, reg); reg 1690 drivers/net/ethernet/intel/igb/igb_ethtool.c reg = rd32(E1000_RCTL); reg 1691 drivers/net/ethernet/intel/igb/igb_ethtool.c reg |= E1000_RCTL_LBM_TCVR; reg 1692 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(E1000_RCTL, reg); reg 1696 drivers/net/ethernet/intel/igb/igb_ethtool.c reg = rd32(E1000_CTRL); reg 1697 drivers/net/ethernet/intel/igb/igb_ethtool.c reg &= ~(E1000_CTRL_RFCE | reg 1700 drivers/net/ethernet/intel/igb/igb_ethtool.c reg |= E1000_CTRL_SLU | reg 1702 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(E1000_CTRL, reg); reg 1705 drivers/net/ethernet/intel/igb/igb_ethtool.c reg = rd32(E1000_CONNSW); reg 1706 drivers/net/ethernet/intel/igb/igb_ethtool.c reg &= ~E1000_CONNSW_ENRGSRC; reg 1707 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(E1000_CONNSW, reg); reg 1713 drivers/net/ethernet/intel/igb/igb_ethtool.c reg = rd32(E1000_PCS_CFG0); reg 1714 drivers/net/ethernet/intel/igb/igb_ethtool.c reg |= E1000_PCS_CFG_IGN_SD; reg 1715 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(E1000_PCS_CFG0, reg); reg 1719 drivers/net/ethernet/intel/igb/igb_ethtool.c reg = rd32(E1000_PCS_LCTL); reg 1720 drivers/net/ethernet/intel/igb/igb_ethtool.c reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/ reg 1721 drivers/net/ethernet/intel/igb/igb_ethtool.c reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ reg 1726 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(E1000_PCS_LCTL, reg); reg 1745 drivers/net/ethernet/intel/igb/igb_ethtool.c u32 reg; reg 1748 drivers/net/ethernet/intel/igb/igb_ethtool.c reg = rd32(E1000_MPHY_ADDR_CTL); reg 1749 drivers/net/ethernet/intel/igb/igb_ethtool.c reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | reg 1751 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(E1000_MPHY_ADDR_CTL, reg); reg 1753 drivers/net/ethernet/intel/igb/igb_ethtool.c reg = rd32(E1000_MPHY_DATA); reg 1754 drivers/net/ethernet/intel/igb/igb_ethtool.c reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN; reg 1755 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(E1000_MPHY_DATA, reg); reg 3312 drivers/net/ethernet/intel/igb/igb_ethtool.c u32 reg = E1000_RETA(0); reg 3338 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(reg, val << shift); reg 3339 drivers/net/ethernet/intel/igb/igb_ethtool.c reg += 4; reg 740 drivers/net/ethernet/intel/igb/igb_main.c u32 igb_rd32(struct e1000_hw *hw, u32 reg) reg 749 drivers/net/ethernet/intel/igb/igb_main.c value = readl(&hw_addr[reg]); reg 752 drivers/net/ethernet/intel/igb/igb_main.c if (!(~value) && (!reg || !(~readl(hw_addr)))) { reg 757 drivers/net/ethernet/intel/igb/igb_main.c "igb: Failed to read reg 0x%x!\n", reg); reg 4418 drivers/net/ethernet/intel/igb/igb_main.c u32 val, reg; reg 4424 drivers/net/ethernet/intel/igb/igb_main.c reg = E1000_DVMOLR(vfn); reg 4426 drivers/net/ethernet/intel/igb/igb_main.c reg = E1000_VMOLR(vfn); reg 4428 drivers/net/ethernet/intel/igb/igb_main.c val = rd32(reg); reg 4433 drivers/net/ethernet/intel/igb/igb_main.c wr32(reg, val); reg 6267 drivers/net/ethernet/intel/igb/igb_main.c u32 reg, mpc; reg 6382 drivers/net/ethernet/intel/igb/igb_main.c reg = rd32(E1000_CTRL_EXT); reg 6383 drivers/net/ethernet/intel/igb/igb_main.c if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { reg 6439 drivers/net/ethernet/intel/igb/igb_main.c reg = rd32(E1000_MANC); reg 6440 drivers/net/ethernet/intel/igb/igb_main.c if (reg & E1000_MANC_EN_BMC2OS) { reg 7108 drivers/net/ethernet/intel/igb/igb_main.c u32 reg, msgbuf[3]; reg 7118 drivers/net/ethernet/intel/igb/igb_main.c reg = rd32(E1000_VFTE); reg 7119 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_VFTE, reg | BIT(vf)); reg 7120 drivers/net/ethernet/intel/igb/igb_main.c reg = rd32(E1000_VFRE); reg 7121 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_VFRE, reg | BIT(vf)); reg 8561 drivers/net/ethernet/intel/igb/igb_main.c void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) reg 8565 drivers/net/ethernet/intel/igb/igb_main.c pci_read_config_word(adapter->pdev, reg, value); reg 8568 drivers/net/ethernet/intel/igb/igb_main.c void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) reg 8572 drivers/net/ethernet/intel/igb/igb_main.c pci_write_config_word(adapter->pdev, reg, *value); reg 8575 drivers/net/ethernet/intel/igb/igb_main.c s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) reg 8579 drivers/net/ethernet/intel/igb/igb_main.c if (pcie_capability_read_word(adapter->pdev, reg, value)) reg 8585 drivers/net/ethernet/intel/igb/igb_main.c s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) reg 8589 drivers/net/ethernet/intel/igb/igb_main.c if (pcie_capability_write_word(adapter->pdev, reg, *value)) reg 9343 drivers/net/ethernet/intel/igb/igb_main.c u32 reg; reg 9355 drivers/net/ethernet/intel/igb/igb_main.c reg = rd32(E1000_DTXCTL); reg 9356 drivers/net/ethernet/intel/igb/igb_main.c reg |= E1000_DTXCTL_VLAN_ADDED; reg 9357 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_DTXCTL, reg); reg 9361 drivers/net/ethernet/intel/igb/igb_main.c reg = rd32(E1000_RPLOLR); reg 9362 drivers/net/ethernet/intel/igb/igb_main.c reg |= E1000_RPLOLR_STRVLAN; reg 9363 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_RPLOLR, reg); reg 9389 drivers/net/ethernet/intel/igb/igb_main.c u32 reg; reg 9399 drivers/net/ethernet/intel/igb/igb_main.c reg = rd32(E1000_FCRTC); reg 9400 drivers/net/ethernet/intel/igb/igb_main.c reg &= ~E1000_FCRTC_RTH_COAL_MASK; reg 9401 drivers/net/ethernet/intel/igb/igb_main.c reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) reg 9403 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_FCRTC, reg); reg 9409 drivers/net/ethernet/intel/igb/igb_main.c reg = rd32(E1000_DMACR); reg 9410 drivers/net/ethernet/intel/igb/igb_main.c reg &= ~E1000_DMACR_DMACTHR_MASK; reg 9411 drivers/net/ethernet/intel/igb/igb_main.c reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) reg 9415 drivers/net/ethernet/intel/igb/igb_main.c reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); reg 9418 drivers/net/ethernet/intel/igb/igb_main.c reg |= (1000 >> 5); reg 9422 drivers/net/ethernet/intel/igb/igb_main.c reg &= ~E1000_DMACR_DC_BMC2OSW_EN; reg 9424 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_DMACR, reg); reg 9431 drivers/net/ethernet/intel/igb/igb_main.c reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); reg 9433 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_DMCTLX, reg); reg 9444 drivers/net/ethernet/intel/igb/igb_main.c reg = rd32(E1000_PCIEMISC); reg 9445 drivers/net/ethernet/intel/igb/igb_main.c reg &= ~E1000_PCIEMISC_LX_DECISION; reg 9446 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_PCIEMISC, reg); reg 9449 drivers/net/ethernet/intel/igb/igb_main.c u32 reg = rd32(E1000_PCIEMISC); reg 9451 drivers/net/ethernet/intel/igb/igb_main.c wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); reg 1817 drivers/net/ethernet/intel/igbvf/netdev.c #define UPDATE_VF_COUNTER(reg, name) \ reg 1819 drivers/net/ethernet/intel/igbvf/netdev.c u32 current_counter = er32(reg); \ reg 76 drivers/net/ethernet/intel/igbvf/regs.h #define er32(reg) readl(hw->hw_addr + E1000_##reg) reg 77 drivers/net/ethernet/intel/igbvf/regs.h #define ew32(reg, val) writel((val), hw->hw_addr + E1000_##reg) reg 78 drivers/net/ethernet/intel/igbvf/regs.h #define array_er32(reg, offset) \ reg 79 drivers/net/ethernet/intel/igbvf/regs.h readl(hw->hw_addr + E1000_##reg + (offset << 2)) reg 80 drivers/net/ethernet/intel/igbvf/regs.h #define array_ew32(reg, offset, val) \ reg 81 drivers/net/ethernet/intel/igbvf/regs.h writel((val), hw->hw_addr + E1000_##reg + (offset << 2)) reg 1479 drivers/net/ethernet/intel/igc/igc_ethtool.c u32 reg = IGC_RETA(0); reg 1492 drivers/net/ethernet/intel/igc/igc_ethtool.c wr32(reg, val << shift); reg 1493 drivers/net/ethernet/intel/igc/igc_ethtool.c reg += 4; reg 306 drivers/net/ethernet/intel/igc/igc_hw.h s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); reg 307 drivers/net/ethernet/intel/igc/igc_hw.h s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); reg 308 drivers/net/ethernet/intel/igc/igc_hw.h void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); reg 309 drivers/net/ethernet/intel/igc/igc_hw.h void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); reg 347 drivers/net/ethernet/intel/igc/igc_i225.c u32 i, reg; reg 350 drivers/net/ethernet/intel/igc/igc_i225.c reg = rd32(IGC_EECD); reg 351 drivers/net/ethernet/intel/igc/igc_i225.c if (reg & IGC_EECD_FLUDONE_I225) { reg 3994 drivers/net/ethernet/intel/igc/igc_main.c void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value) reg 3998 drivers/net/ethernet/intel/igc/igc_main.c pci_read_config_word(adapter->pdev, reg, value); reg 4001 drivers/net/ethernet/intel/igc/igc_main.c void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value) reg 4005 drivers/net/ethernet/intel/igc/igc_main.c pci_write_config_word(adapter->pdev, reg, *value); reg 4008 drivers/net/ethernet/intel/igc/igc_main.c s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value) reg 4015 drivers/net/ethernet/intel/igc/igc_main.c pcie_capability_read_word(adapter->pdev, reg, value); reg 4020 drivers/net/ethernet/intel/igc/igc_main.c s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value) reg 4027 drivers/net/ethernet/intel/igc/igc_main.c pcie_capability_write_word(adapter->pdev, reg, *value); reg 4032 drivers/net/ethernet/intel/igc/igc_main.c u32 igc_rd32(struct igc_hw *hw, u32 reg) reg 4041 drivers/net/ethernet/intel/igc/igc_main.c value = readl(&hw_addr[reg]); reg 4044 drivers/net/ethernet/intel/igc/igc_main.c if (!(~value) && (!reg || !(~readl(hw_addr)))) { reg 4051 drivers/net/ethernet/intel/igc/igc_main.c "igc: Failed to read reg 0x%x!\n", reg); reg 19 drivers/net/ethernet/intel/igc/igc_nvm.c u32 i, reg = 0; reg 23 drivers/net/ethernet/intel/igc/igc_nvm.c reg = rd32(IGC_EERD); reg 25 drivers/net/ethernet/intel/igc/igc_nvm.c reg = rd32(IGC_EEWR); reg 27 drivers/net/ethernet/intel/igc/igc_nvm.c if (reg & IGC_NVM_RW_REG_DONE) { reg 220 drivers/net/ethernet/intel/igc/igc_regs.h u32 igc_rd32(struct igc_hw *hw, u32 reg); reg 223 drivers/net/ethernet/intel/igc/igc_regs.h #define wr32(reg, val) \ reg 227 drivers/net/ethernet/intel/igc/igc_regs.h writel((val), &hw_addr[(reg)]); \ reg 230 drivers/net/ethernet/intel/igc/igc_regs.h #define rd32(reg) (igc_rd32(hw, reg)) reg 234 drivers/net/ethernet/intel/igc/igc_regs.h #define array_wr32(reg, offset, value) \ reg 235 drivers/net/ethernet/intel/igc/igc_regs.h wr32((reg) + ((offset) << 2), (value)) reg 237 drivers/net/ethernet/intel/igc/igc_regs.h #define array_rd32(reg, offset) (igc_rd32(hw, (reg) + ((offset) << 2))) reg 71 drivers/net/ethernet/intel/ixgb/ixgb_ee.h u16 ixgb_read_eeprom(struct ixgb_hw *hw, u16 reg); reg 77 drivers/net/ethernet/intel/ixgb/ixgb_ee.h void ixgb_write_eeprom(struct ixgb_hw *hw, u16 reg, u16 data); reg 207 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c u32 *reg = p; reg 208 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c u32 *reg_start = reg; reg 217 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, CTRL0); /* 0 */ reg 218 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, CTRL1); /* 1 */ reg 219 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, STATUS); /* 2 */ reg 220 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, EECD); /* 3 */ reg 221 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, MFS); /* 4 */ reg 224 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, ICR); /* 5 */ reg 225 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, ICS); /* 6 */ reg 226 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, IMS); /* 7 */ reg 227 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, IMC); /* 8 */ reg 230 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, RCTL); /* 9 */ reg 231 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, FCRTL); /* 10 */ reg 232 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, FCRTH); /* 11 */ reg 233 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, RDBAL); /* 12 */ reg 234 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, RDBAH); /* 13 */ reg 235 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, RDLEN); /* 14 */ reg 236 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, RDH); /* 15 */ reg 237 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, RDT); /* 16 */ reg 238 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, RDTR); /* 17 */ reg 239 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, RXDCTL); /* 18 */ reg 240 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, RAIDC); /* 19 */ reg 241 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, RXCSUM); /* 20 */ reg 245 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG_ARRAY(hw, RAL, (i << 1)); /*21,...,51 */ reg 246 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG_ARRAY(hw, RAH, (i << 1)); /*22,...,52 */ reg 250 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, TCTL); /* 53 */ reg 251 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, TDBAL); /* 54 */ reg 252 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, TDBAH); /* 55 */ reg 253 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, TDLEN); /* 56 */ reg 254 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, TDH); /* 57 */ reg 255 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, TDT); /* 58 */ reg 256 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, TIDV); /* 59 */ reg 257 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, TXDCTL); /* 60 */ reg 258 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, TSPMT); /* 61 */ reg 259 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, PAP); /* 62 */ reg 262 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, PCSC1); /* 63 */ reg 263 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, PCSC2); /* 64 */ reg 264 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, PCSS1); /* 65 */ reg 265 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, PCSS2); /* 66 */ reg 266 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, XPCSS); /* 67 */ reg 267 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, UCCR); /* 68 */ reg 268 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, XPCSTC); /* 69 */ reg 269 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, MACA); /* 70 */ reg 270 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, APAE); /* 71 */ reg 271 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, ARD); /* 72 */ reg 272 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, AIS); /* 73 */ reg 273 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, MSCA); /* 74 */ reg 274 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_READ_REG(hw, MSRWD); /* 75 */ reg 277 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, tprl); /* 76 */ reg 278 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, tprh); /* 77 */ reg 279 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, gprcl); /* 78 */ reg 280 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, gprch); /* 79 */ reg 281 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, bprcl); /* 80 */ reg 282 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, bprch); /* 81 */ reg 283 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, mprcl); /* 82 */ reg 284 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, mprch); /* 83 */ reg 285 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, uprcl); /* 84 */ reg 286 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, uprch); /* 85 */ reg 287 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, vprcl); /* 86 */ reg 288 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, vprch); /* 87 */ reg 289 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, jprcl); /* 88 */ reg 290 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, jprch); /* 89 */ reg 291 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, gorcl); /* 90 */ reg 292 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, gorch); /* 91 */ reg 293 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, torl); /* 92 */ reg 294 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, torh); /* 93 */ reg 295 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, rnbc); /* 94 */ reg 296 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, ruc); /* 95 */ reg 297 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, roc); /* 96 */ reg 298 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, rlec); /* 97 */ reg 299 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, crcerrs); /* 98 */ reg 300 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, icbc); /* 99 */ reg 301 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, ecbc); /* 100 */ reg 302 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, mpc); /* 101 */ reg 303 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, tptl); /* 102 */ reg 304 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, tpth); /* 103 */ reg 305 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, gptcl); /* 104 */ reg 306 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, gptch); /* 105 */ reg 307 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, bptcl); /* 106 */ reg 308 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, bptch); /* 107 */ reg 309 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, mptcl); /* 108 */ reg 310 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, mptch); /* 109 */ reg 311 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, uptcl); /* 110 */ reg 312 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, uptch); /* 111 */ reg 313 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, vptcl); /* 112 */ reg 314 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, vptch); /* 113 */ reg 315 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, jptcl); /* 114 */ reg 316 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, jptch); /* 115 */ reg 317 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, gotcl); /* 116 */ reg 318 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, gotch); /* 117 */ reg 319 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, totl); /* 118 */ reg 320 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, toth); /* 119 */ reg 321 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, dc); /* 120 */ reg 322 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, plt64c); /* 121 */ reg 323 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, tsctc); /* 122 */ reg 324 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, tsctfc); /* 123 */ reg 325 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, ibic); /* 124 */ reg 326 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, rfc); /* 125 */ reg 327 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, lfc); /* 126 */ reg 328 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, pfrc); /* 127 */ reg 329 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, pftc); /* 128 */ reg 330 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, mcfrc); /* 129 */ reg 331 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, mcftc); /* 130 */ reg 332 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, xonrxc); /* 131 */ reg 333 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, xontxc); /* 132 */ reg 334 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, xoffrxc); /* 133 */ reg 335 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, xofftxc); /* 134 */ reg 336 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c *reg++ = IXGB_GET_STAT(adapter, rjc); /* 135 */ reg 338 drivers/net/ethernet/intel/ixgb/ixgb_ethtool.c regs->len = (reg - reg_start) * sizeof(u32); reg 763 drivers/net/ethernet/intel/ixgb/ixgb_hw.h u32 reg, reg 23 drivers/net/ethernet/intel/ixgb/ixgb_osdep.h #define IXGB_WRITE_REG(a, reg, value) ( \ reg 24 drivers/net/ethernet/intel/ixgb/ixgb_osdep.h writel((value), ((a)->hw_addr + IXGB_##reg))) reg 26 drivers/net/ethernet/intel/ixgb/ixgb_osdep.h #define IXGB_READ_REG(a, reg) ( \ reg 27 drivers/net/ethernet/intel/ixgb/ixgb_osdep.h readl((a)->hw_addr + IXGB_##reg)) reg 29 drivers/net/ethernet/intel/ixgb/ixgb_osdep.h #define IXGB_WRITE_REG_ARRAY(a, reg, offset, value) ( \ reg 30 drivers/net/ethernet/intel/ixgb/ixgb_osdep.h writel((value), ((a)->hw_addr + IXGB_##reg + ((offset) << 2)))) reg 32 drivers/net/ethernet/intel/ixgb/ixgb_osdep.h #define IXGB_READ_REG_ARRAY(a, reg, offset) ( \ reg 33 drivers/net/ethernet/intel/ixgb/ixgb_osdep.h readl((a)->hw_addr + IXGB_##reg + ((offset) << 2))) reg 278 drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c u32 reg; reg 396 drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c reg = hw->fc.pause_time * 0x00010001; reg 398 drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); reg 908 drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val) reg 913 drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); reg 930 drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val) reg 934 drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c atlas_ctl = (reg << 8) | val; reg 1514 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c #define IXGBE_WRITE_REG_BE32(a, reg, value) \ reg 1515 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value))) reg 1737 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) reg 1742 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c (reg << 8)); reg 1759 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) reg 1763 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c core_ctl = (reg << 8) | val; reg 117 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c u32 reg = 0, reg_bp = 0; reg 151 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); reg 175 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); reg 187 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c reg |= IXGBE_PCS1GANA_ASM_PAUSE; reg 188 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; reg 209 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; reg 226 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); reg 227 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); reg 231 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; reg 233 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); reg 234 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); reg 257 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); reg 684 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c u32 reg; reg 686 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c reg = IXGBE_READ_REG(hw, IXGBE_STATUS); reg 687 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; reg 691 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); reg 692 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c if (reg & IXGBE_FACTPS_LFS) reg 1318 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c u32 reg; reg 1322 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c reg = IXGBE_READ_REG(hw, IXGBE_EERD); reg 1324 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c reg = IXGBE_READ_REG(hw, IXGBE_EEWR); reg 1326 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c if (reg & IXGBE_EEPROM_RW_REG_DONE) { reg 2143 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c u32 reg; reg 2246 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c reg = hw->fc.pause_time * 0x00010001; reg 2248 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); reg 136 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg); reg 137 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value); reg 144 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h static inline void ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 value) reg 150 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h writel(value, reg_addr + reg); reg 152 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h #define IXGBE_WRITE_REG(a, reg, value) ixgbe_write_reg((a), (reg), (value)) reg 163 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h static inline void ixgbe_write_reg64(struct ixgbe_hw *hw, u32 reg, u64 value) reg 169 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h writeq(value, reg_addr + reg); reg 171 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h #define IXGBE_WRITE_REG64(a, reg, value) ixgbe_write_reg64((a), (reg), (value)) reg 173 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg); reg 174 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h #define IXGBE_READ_REG(a, reg) ixgbe_read_reg((a), (reg)) reg 176 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) \ reg 177 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h ixgbe_write_reg((a), (reg) + ((offset) << 2), (value)) reg 179 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h #define IXGBE_READ_REG_ARRAY(a, reg, offset) \ reg 180 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h ixgbe_read_reg((a), (reg) + ((offset) << 2)) reg 369 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c u32 reg, i; reg 371 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); reg 374 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT)); reg 23 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c u32 reg = 0; reg 28 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; reg 29 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); reg 31 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg = IXGBE_READ_REG(hw, IXGBE_RMCS); reg 33 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg &= ~IXGBE_RMCS_ARBDIS; reg 35 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= IXGBE_RMCS_RRM; reg 37 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= IXGBE_RMCS_DFP; reg 39 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); reg 46 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); reg 49 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= IXGBE_RT2CR_LSP; reg 51 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg); reg 54 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); reg 55 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= IXGBE_RDRXCTL_RDMTS_1_2; reg 56 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= IXGBE_RDRXCTL_MPBEN; reg 57 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= IXGBE_RDRXCTL_MCEN; reg 58 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); reg 60 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL); reg 62 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg &= ~IXGBE_RXCTRL_DMBYPS; reg 63 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg); reg 84 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c u32 reg, max_credits; reg 87 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg = IXGBE_READ_REG(hw, IXGBE_DPMCS); reg 90 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg &= ~IXGBE_DPMCS_ARBDIS; reg 91 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= IXGBE_DPMCS_TSOEF; reg 94 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT); reg 96 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg); reg 101 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT; reg 102 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= refill[i]; reg 103 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT; reg 106 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= IXGBE_TDTQ2TCCR_GSP; reg 109 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= IXGBE_TDTQ2TCCR_LSP; reg 111 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg); reg 133 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c u32 reg; reg 136 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS); reg 138 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg &= ~IXGBE_PDPMCS_ARBDIS; reg 140 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM); reg 142 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg); reg 146 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg = refill[i]; reg 147 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT; reg 148 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT; reg 151 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= IXGBE_TDPT2TCCR_GSP; reg 154 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= IXGBE_TDPT2TCCR_LSP; reg 156 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg); reg 160 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL); reg 161 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= IXGBE_DTXCTL_ENDBUBD; reg 162 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg); reg 176 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c u32 fcrtl, reg; reg 180 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg = IXGBE_READ_REG(hw, IXGBE_RMCS); reg 181 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg &= ~IXGBE_RMCS_TFCE_802_3X; reg 182 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= IXGBE_RMCS_TFCE_PRIORITY; reg 183 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); reg 186 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); reg 187 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE); reg 190 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= IXGBE_FCTRL_RPFCE; reg 192 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg); reg 203 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; reg 205 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg); reg 209 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg = hw->fc.pause_time * 0x00010001; reg 211 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); reg 229 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c u32 reg = 0; reg 235 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i)); reg 236 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= ((0x1010101) * j); reg 237 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); reg 238 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1)); reg 239 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= ((0x1010101) * j); reg 240 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg); reg 244 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i)); reg 245 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c reg |= ((0x1010101) * i); reg 246 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.c IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg); reg 27 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c u32 reg = 0; reg 36 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS; reg 37 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); reg 40 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = 0; reg 42 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT)); reg 43 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); reg 49 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT); reg 51 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT; reg 54 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg |= IXGBE_RTRPT4C_LSP; reg 56 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); reg 63 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC; reg 64 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); reg 85 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c u32 reg, max_credits; reg 97 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT; reg 98 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg |= refill[i]; reg 99 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT; reg 102 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg |= IXGBE_RTTDT2C_GSP; reg 105 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg |= IXGBE_RTTDT2C_LSP; reg 107 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg); reg 114 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM; reg 115 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); reg 138 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c u32 reg; reg 145 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | reg 148 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); reg 151 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = 0; reg 153 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT)); reg 154 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg); reg 158 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = refill[i]; reg 159 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT; reg 160 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT; reg 163 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg |= IXGBE_RTTPT2C_GSP; reg 166 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg |= IXGBE_RTTPT2C_LSP; reg 168 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg); reg 175 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM | reg 177 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); reg 192 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c u32 i, j, fcrtl, reg; reg 199 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); reg 200 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg |= IXGBE_MFLCN_DPF; reg 207 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); reg 210 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT; reg 213 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg |= IXGBE_MFLCN_RPFCE; reg 215 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg); reg 235 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; reg 245 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; reg 249 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg); reg 258 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = hw->fc.pause_time * 0x00010001; reg 260 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); reg 277 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c u32 reg = 0; reg 287 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = 0x01010101 * (i / 4); reg 288 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); reg 300 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = 0x00000000; reg 302 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = 0x01010101; reg 304 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = 0x02020202; reg 306 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = 0x03030303; reg 308 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = 0x04040404; reg 310 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = 0x05050505; reg 312 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = 0x06060606; reg 314 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c reg = 0x07070707; reg 315 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.c IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg); reg 86 drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c u32 reg, value; reg 88 drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c cnt = sscanf(&ixgbe_dbg_reg_ops_buf[5], "%x %x", ®, &value); reg 90 drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c IXGBE_WRITE_REG(&adapter->hw, reg, value); reg 91 drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c value = IXGBE_READ_REG(&adapter->hw, reg); reg 92 drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c e_dev_info("write: 0x%08x = 0x%08x\n", reg, value); reg 97 drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c u32 reg, value; reg 99 drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c cnt = sscanf(&ixgbe_dbg_reg_ops_buf[4], "%x", ®); reg 101 drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c value = IXGBE_READ_REG(&adapter->hw, reg); reg 102 drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c e_dev_info("read 0x%08x = 0x%08x\n", reg, value); reg 1339 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c u16 reg; reg 1384 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c { .reg = 0 } reg 1412 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c { .reg = 0 } reg 1415 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg, reg 1427 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c before = ixgbe_read_reg(&adapter->hw, reg); reg 1428 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write); reg 1429 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c val = ixgbe_read_reg(&adapter->hw, reg); reg 1432 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c reg, val, (test_pattern[pat] & write & mask)); reg 1433 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c *data = reg; reg 1434 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c ixgbe_write_reg(&adapter->hw, reg, before); reg 1437 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c ixgbe_write_reg(&adapter->hw, reg, before); reg 1442 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg, reg 1451 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c before = ixgbe_read_reg(&adapter->hw, reg); reg 1452 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c ixgbe_write_reg(&adapter->hw, reg, write & mask); reg 1453 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c val = ixgbe_read_reg(&adapter->hw, reg); reg 1456 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c reg, (val & mask), (write & mask)); reg 1457 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c *data = reg; reg 1458 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c ixgbe_write_reg(&adapter->hw, reg, before); reg 1461 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c ixgbe_write_reg(&adapter->hw, reg, before); reg 1517 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c while (test->reg) { reg 1524 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c test->reg + (i * 0x40), reg 1530 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c test->reg + (i * 0x40), reg 1536 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c test->reg + (i * 0x40), reg 1541 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c test->reg + (i * 4), reg 1547 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c test->reg + (i * 8), reg 1553 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c (test->reg + 4) + (i * 8), reg 24 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c u32 reg; reg 33 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = IXGBE_READ_REG(hw, IXGBE_IPSTXIDX); reg 34 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg &= IXGBE_RXTXIDX_IPS_EN; reg 35 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg |= idx << IXGBE_RXTXIDX_IDX_SHIFT | IXGBE_RXTXIDX_WRITE; reg 36 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c IXGBE_WRITE_REG(hw, IXGBE_IPSTXIDX, reg); reg 52 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c u32 reg; reg 54 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = IXGBE_READ_REG(hw, IXGBE_IPSRXIDX); reg 55 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg &= IXGBE_RXTXIDX_IPS_EN; reg 56 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg |= tbl << IXGBE_RXIDX_TBL_SHIFT | reg 59 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c IXGBE_WRITE_REG(hw, IXGBE_IPSRXIDX, reg); reg 152 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c u32 reg; reg 155 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); reg 156 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg |= IXGBE_SECTXCTRL_TX_DIS; reg 157 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, reg); reg 159 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); reg 160 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg |= IXGBE_SECRXCTRL_RX_DIS; reg 161 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, reg); reg 179 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = IXGBE_READ_REG(hw, IXGBE_MACC); reg 180 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg |= IXGBE_MACC_FLU; reg 181 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c IXGBE_WRITE_REG(hw, IXGBE_MACC, reg); reg 183 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = IXGBE_READ_REG(hw, IXGBE_HLREG0); reg 184 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg |= IXGBE_HLREG0_LPBK; reg 185 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg); reg 203 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = IXGBE_READ_REG(hw, IXGBE_MACC); reg 204 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg &= ~IXGBE_MACC_FLU; reg 205 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c IXGBE_WRITE_REG(hw, IXGBE_MACC, reg); reg 207 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = IXGBE_READ_REG(hw, IXGBE_HLREG0); reg 208 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg &= ~IXGBE_HLREG0_LPBK; reg 209 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg); reg 222 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c u32 reg; reg 231 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); reg 232 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg |= IXGBE_SECTXCTRL_SECTX_DIS; reg 233 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg &= ~IXGBE_SECTXCTRL_STORE_FORWARD; reg 234 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, reg); reg 236 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); reg 237 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg |= IXGBE_SECRXCTRL_SECRX_DIS; reg 238 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, reg); reg 244 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); reg 245 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = (reg & 0xfffffff0) | 0x1; reg 246 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg); reg 264 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c u32 reg; reg 269 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); reg 270 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = (reg & 0xfffffff0) | 0x3; reg 271 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg); reg 277 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = IXGBE_READ_REG(hw, IXGBE_SECTXBUFFAF); reg 278 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = (reg & 0xfffffc00) | 0x15; reg 279 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c IXGBE_WRITE_REG(hw, IXGBE_SECTXBUFFAF, reg); reg 483 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c u32 mfval, manc, reg; reg 513 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = IXGBE_READ_REG(hw, MIPAF_ARR(3, i)); reg 514 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c if (reg == xs->id.daddr.a4) reg 520 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = IXGBE_READ_REG(hw, IXGBE_BMCIP(3)); reg 521 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c if (reg == xs->id.daddr.a4) reg 535 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = IXGBE_READ_REG(hw, MIPAF_ARR(i, j)); reg 536 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c if (reg != xs->id.daddr.a6[j]) reg 545 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c reg = IXGBE_READ_REG(hw, IXGBE_BMCIP(j)); reg 546 drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c if (reg != xs->id.daddr.a6[j]) reg 183 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u32 reg, u16 *value) reg 199 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c pcie_capability_read_word(parent_dev, reg, value); reg 291 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) reg 315 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c value = readl(reg_addr + reg); reg 332 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) reg 360 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c value = readl(reg_addr + reg); reg 362 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c value = ixgbe_check_remove(hw, reg); reg 378 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) reg 385 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c pci_read_config_word(adapter->pdev, reg, &value); reg 393 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) reg 400 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c pci_read_config_dword(adapter->pdev, reg, &value); reg 408 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) reg 414 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c pci_write_config_word(adapter->pdev, reg, value); reg 8988 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u32 reg, rsave; reg 8997 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); reg 8998 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c rsave = reg; reg 9001 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); reg 9005 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); reg 9008 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c if (reg != rsave) reg 9009 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); reg 9822 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u32 reg; reg 9867 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c reg = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) | ntohs(port) << port_shift; reg 9868 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, reg); reg 89 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c u16 reg, u16 *val, bool lock) reg 100 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ reg 101 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); reg 114 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) reg 167 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c u16 reg, u16 val, bool lock) reg 175 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ reg 176 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); reg 191 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) reg 2644 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c u16 reg; reg 2653 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, ®); reg 2658 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; reg 2662 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; reg 2665 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg); reg 173 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg, reg 175 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg, reg 813 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c u32 reg; reg 819 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg = IXGBE_QDE_WRITE | qde; reg 820 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg |= i << IXGBE_QDE_IDX_SHIFT; reg 821 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c IXGBE_WRITE_REG(hw, IXGBE_QDE, reg); reg 830 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c u32 reg, reg_offset, vf_shift; reg 851 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset)); reg 852 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg |= BIT(vf_shift); reg 853 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg); reg 856 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg = IXGBE_QDE_ENABLE; reg 858 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg |= IXGBE_QDE_HIDE_VLAN; reg 860 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c ixgbe_write_qde(adapter, vf, reg); reg 863 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset)); reg 864 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg |= BIT(vf_shift); reg 880 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg &= ~BIT(vf_shift); reg 882 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg); reg 888 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset)); reg 889 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c reg |= BIT(vf_shift); reg 890 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg); reg 3519 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h s32 (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val); reg 3520 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h s32 (*read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg, reg 3522 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h s32 (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val); reg 3523 drivers/net/ethernet/intel/ixgbe/ixgbe_type.h s32 (*write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg, reg 536 drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c u32 reg; reg 539 drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c reg = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); reg 540 drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c if (reg & IXGBE_EEC_FLUDONE) reg 94 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) reg 96 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value); reg 107 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) reg 109 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value); reg 120 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) reg 124 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value); reg 138 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) reg 142 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, reg 161 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u8 reg; reg 164 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); reg 167 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg |= IXGBE_PE_BIT1; reg 168 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); reg 172 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); reg 175 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg &= ~IXGBE_PE_BIT1; reg 176 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); reg 180 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); reg 183 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg &= ~IXGBE_PE_BIT1; reg 184 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); reg 190 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); reg 193 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg |= IXGBE_PE_BIT1; reg 194 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); reg 372 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u16 reg, u16 *val) reg 374 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true); reg 388 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u16 reg, u16 *val) reg 390 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false); reg 403 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u8 addr, u16 reg, u16 val) reg 405 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true); reg 419 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u8 addr, u16 reg, u16 val) reg 421 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false); reg 895 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + reg 897 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u32 value = IXGBE_READ_REG(hw, reg); reg 2332 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u16 reg; reg 2339 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c ®); reg 2341 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) reg 2347 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c ®); reg 2349 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | reg 2356 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c ®); reg 2362 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { reg 2367 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) { reg 2371 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c ®); reg 2376 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) { reg 2385 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c MDIO_MMD_AN, ®); reg 2387 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) reg 2392 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c MDIO_MMD_AN, ®); reg 2398 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) reg 2416 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u16 reg; reg 2435 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c MDIO_MMD_AN, ®); reg 2439 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; reg 2443 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c MDIO_MMD_AN, reg); reg 2451 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c ®); reg 2455 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN | reg 2460 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg); reg 2467 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c ®); reg 2471 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | reg 2476 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg); reg 2483 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c ®); reg 2487 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; reg 2491 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg); reg 3320 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u16 reg; reg 3325 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c ®); reg 3332 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { reg 3336 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c ®); reg 3340 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg &= ~IXGBE_MDIO_POWER_UP_STALL; reg 3345 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c reg); reg 566 drivers/net/ethernet/intel/ixgbevf/ethtool.c u16 reg; reg 601 drivers/net/ethernet/intel/ixgbevf/ethtool.c { .reg = 0 } reg 609 drivers/net/ethernet/intel/ixgbevf/ethtool.c int reg, u32 mask, u32 write) reg 618 drivers/net/ethernet/intel/ixgbevf/ethtool.c before = ixgbevf_read_reg(&adapter->hw, reg); reg 619 drivers/net/ethernet/intel/ixgbevf/ethtool.c ixgbe_write_reg(&adapter->hw, reg, reg 621 drivers/net/ethernet/intel/ixgbevf/ethtool.c val = ixgbevf_read_reg(&adapter->hw, reg); reg 625 drivers/net/ethernet/intel/ixgbevf/ethtool.c reg, val, reg 627 drivers/net/ethernet/intel/ixgbevf/ethtool.c *data = reg; reg 628 drivers/net/ethernet/intel/ixgbevf/ethtool.c ixgbe_write_reg(&adapter->hw, reg, before); reg 631 drivers/net/ethernet/intel/ixgbevf/ethtool.c ixgbe_write_reg(&adapter->hw, reg, before); reg 637 drivers/net/ethernet/intel/ixgbevf/ethtool.c int reg, u32 mask, u32 write) reg 645 drivers/net/ethernet/intel/ixgbevf/ethtool.c before = ixgbevf_read_reg(&adapter->hw, reg); reg 646 drivers/net/ethernet/intel/ixgbevf/ethtool.c ixgbe_write_reg(&adapter->hw, reg, write & mask); reg 647 drivers/net/ethernet/intel/ixgbevf/ethtool.c val = ixgbevf_read_reg(&adapter->hw, reg); reg 650 drivers/net/ethernet/intel/ixgbevf/ethtool.c reg, (val & mask), write & mask); reg 651 drivers/net/ethernet/intel/ixgbevf/ethtool.c *data = reg; reg 652 drivers/net/ethernet/intel/ixgbevf/ethtool.c ixgbe_write_reg(&adapter->hw, reg, before); reg 655 drivers/net/ethernet/intel/ixgbevf/ethtool.c ixgbe_write_reg(&adapter->hw, reg, before); reg 675 drivers/net/ethernet/intel/ixgbevf/ethtool.c while (test->reg) { reg 682 drivers/net/ethernet/intel/ixgbevf/ethtool.c test->reg + (i * 0x40), reg 688 drivers/net/ethernet/intel/ixgbevf/ethtool.c test->reg + (i * 0x40), reg 694 drivers/net/ethernet/intel/ixgbevf/ethtool.c test->reg + (i * 0x40), reg 699 drivers/net/ethernet/intel/ixgbevf/ethtool.c test->reg + (i * 4), reg 705 drivers/net/ethernet/intel/ixgbevf/ethtool.c test->reg + (i * 8), reg 711 drivers/net/ethernet/intel/ixgbevf/ethtool.c test->reg + 4 + (i * 8), reg 130 drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c static void ixgbevf_check_remove(struct ixgbe_hw *hw, u32 reg) reg 140 drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c if (reg == IXGBE_VFSTATUS) { reg 149 drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c u32 ixgbevf_read_reg(struct ixgbe_hw *hw, u32 reg) reg 156 drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c value = readl(reg_addr + reg); reg 158 drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c ixgbevf_check_remove(hw, reg); reg 3075 drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c #define UPDATE_VF_COUNTER_32bit(reg, last_counter, counter) \ reg 3077 drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c u32 current_counter = IXGBE_READ_REG(hw, reg); \ reg 825 drivers/net/ethernet/intel/ixgbevf/vf.c u32 reg; reg 830 drivers/net/ethernet/intel/ixgbevf/vf.c reg = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(0)); reg 832 drivers/net/ethernet/intel/ixgbevf/vf.c reg |= ((max_size + 4) | IXGBE_RXDCTL_RLPML_EN); reg 833 drivers/net/ethernet/intel/ixgbevf/vf.c IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(0), reg); reg 160 drivers/net/ethernet/intel/ixgbevf/vf.h static inline void ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 value) reg 166 drivers/net/ethernet/intel/ixgbevf/vf.h writel(value, reg_addr + reg); reg 171 drivers/net/ethernet/intel/ixgbevf/vf.h u32 ixgbevf_read_reg(struct ixgbe_hw *hw, u32 reg); reg 174 drivers/net/ethernet/intel/ixgbevf/vf.h static inline void ixgbe_write_reg_array(struct ixgbe_hw *hw, u32 reg, reg 177 drivers/net/ethernet/intel/ixgbevf/vf.h ixgbe_write_reg(hw, reg + (offset << 2), value); reg 182 drivers/net/ethernet/intel/ixgbevf/vf.h static inline u32 ixgbe_read_reg_array(struct ixgbe_hw *hw, u32 reg, reg 185 drivers/net/ethernet/intel/ixgbevf/vf.h return ixgbevf_read_reg(hw, reg + (offset << 2)); reg 47 drivers/net/ethernet/jme.c jme_mdio_read(struct net_device *netdev, int phy, int reg) reg 50 drivers/net/ethernet/jme.c int i, val, again = (reg == MII_BMSR) ? 1 : 0; reg 55 drivers/net/ethernet/jme.c smi_reg_addr(reg)); reg 66 drivers/net/ethernet/jme.c pr_err("phy(%d) read timeout : %d\n", phy, reg); reg 78 drivers/net/ethernet/jme.c int phy, int reg, int val) reg 85 drivers/net/ethernet/jme.c smi_phy_addr(phy) | smi_reg_addr(reg)); reg 95 drivers/net/ethernet/jme.c pr_err("phy(%d) write timeout : %d\n", phy, reg); reg 1667 drivers/net/ethernet/jme.c u32 reg; reg 1669 drivers/net/ethernet/jme.c reg = jread32(jme, JME_PHY_PWR); reg 1670 drivers/net/ethernet/jme.c reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW | reg 1672 drivers/net/ethernet/jme.c jwrite32(jme, JME_PHY_PWR, reg); reg 1674 drivers/net/ethernet/jme.c pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®); reg 1675 drivers/net/ethernet/jme.c reg &= ~PE1_GPREG0_PBG; reg 1676 drivers/net/ethernet/jme.c reg |= PE1_GPREG0_ENBG; reg 1677 drivers/net/ethernet/jme.c pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg); reg 1683 drivers/net/ethernet/jme.c u32 reg; reg 1685 drivers/net/ethernet/jme.c reg = jread32(jme, JME_PHY_PWR); reg 1686 drivers/net/ethernet/jme.c reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW | reg 1688 drivers/net/ethernet/jme.c jwrite32(jme, JME_PHY_PWR, reg); reg 1690 drivers/net/ethernet/jme.c pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®); reg 1691 drivers/net/ethernet/jme.c reg &= ~PE1_GPREG0_PBG; reg 1692 drivers/net/ethernet/jme.c reg |= PE1_GPREG0_PDD3COLD; reg 1693 drivers/net/ethernet/jme.c pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg); reg 2373 drivers/net/ethernet/jme.c mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len) reg 2378 drivers/net/ethernet/jme.c p[i >> 2] = jread32(jme, reg + i); reg 1175 drivers/net/ethernet/jme.h const char *msg, u32 val, u32 reg) reg 1178 drivers/net/ethernet/jme.h switch (reg & 0xF00) { reg 1180 drivers/net/ethernet/jme.h regname = MAC_REG_NAME[(reg & 0xFF) >> 2]; reg 1183 drivers/net/ethernet/jme.h regname = PE_REG_NAME[(reg & 0xFF) >> 2]; reg 1186 drivers/net/ethernet/jme.h regname = MISC_REG_NAME[(reg & 0xFF) >> 2]; reg 1196 drivers/net/ethernet/jme.h const char *msg, u32 val, u32 reg) {} reg 1202 drivers/net/ethernet/jme.h static inline u32 jread32(struct jme_adapter *jme, u32 reg) reg 1204 drivers/net/ethernet/jme.h return readl(jme->regs + reg); reg 1207 drivers/net/ethernet/jme.h static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val) reg 1209 drivers/net/ethernet/jme.h reg_dbg(jme, "REG WRITE", val, reg); reg 1210 drivers/net/ethernet/jme.h writel(val, jme->regs + reg); reg 1211 drivers/net/ethernet/jme.h reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg); reg 1214 drivers/net/ethernet/jme.h static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val) reg 1219 drivers/net/ethernet/jme.h reg_dbg(jme, "REG WRITE FLUSH", val, reg); reg 1220 drivers/net/ethernet/jme.h writel(val, jme->regs + reg); reg 1221 drivers/net/ethernet/jme.h readl(jme->regs + reg); reg 1222 drivers/net/ethernet/jme.h reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg); reg 295 drivers/net/ethernet/korina.c static int mdio_read(struct net_device *dev, int mii_id, int reg) reg 304 drivers/net/ethernet/korina.c writel(mii_id | reg, &lp->eth_regs->miimaddr); reg 311 drivers/net/ethernet/korina.c static void mdio_write(struct net_device *dev, int mii_id, int reg, int val) reg 319 drivers/net/ethernet/korina.c writel(mii_id | reg, &lp->eth_regs->miimaddr); reg 1413 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c static u32 mvpp2_read_index(struct mvpp2 *priv, u32 index, u32 reg) reg 1416 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c return mvpp2_read(priv, reg); reg 532 drivers/net/ethernet/marvell/octeontx2/af/mbox.h #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) reg 535 drivers/net/ethernet/marvell/octeontx2/af/mbox.h u64 reg[MAX_REGS_PER_MBOX_MSG]; reg 65 drivers/net/ethernet/marvell/octeontx2/af/rvu.c void __iomem *reg; reg 68 drivers/net/ethernet/marvell/octeontx2/af/rvu.c reg = rvu->afreg_base + ((block << 28) | offset); reg 70 drivers/net/ethernet/marvell/octeontx2/af/rvu.c reg_val = readq(reg); reg 193 drivers/net/ethernet/marvell/octeontx2/af/rvu.c u64 cfg, reg; reg 239 drivers/net/ethernet/marvell/octeontx2/af/rvu.c reg = is_pf ? RVU_PRIV_PFX_NIX0_CFG : RVU_PRIV_HWVFX_NIX0_CFG; reg 240 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); reg 247 drivers/net/ethernet/marvell/octeontx2/af/rvu.c reg = is_pf ? RVU_PRIV_PFX_CPT0_CFG : RVU_PRIV_HWVFX_CPT0_CFG; reg 248 drivers/net/ethernet/marvell/octeontx2/af/rvu.c cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16)); reg 265 drivers/net/ethernet/marvell/octeontx2/af/rvu.c u64 reg; reg 312 drivers/net/ethernet/marvell/octeontx2/af/rvu.c reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg; reg 313 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs); reg 1806 drivers/net/ethernet/marvell/octeontx2/af/rvu.c int reg = 0; reg 1812 drivers/net/ethernet/marvell/octeontx2/af/rvu.c reg = 1; reg 1817 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); reg 1818 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); reg 1853 drivers/net/ethernet/marvell/octeontx2/af/rvu.c int dev, vf, reg = 0; reg 1857 drivers/net/ethernet/marvell/octeontx2/af/rvu.c reg = 1; reg 1859 drivers/net/ethernet/marvell/octeontx2/af/rvu.c intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg)); reg 1869 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); reg 1870 drivers/net/ethernet/marvell/octeontx2/af/rvu.c rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf)); reg 326 drivers/net/ethernet/marvell/octeontx2/af/rvu.h bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); reg 419 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c u64 reg, head; reg 424 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c reg = rvu_read64(rvu, block->addr, NIX_AF_AQ_STATUS); reg 425 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c head = (reg >> 4) & AQ_PTR_MASK; reg 1397 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c int lvl, u64 reg, u64 regval) reg 1399 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c u64 regbase = reg & 0xFFFF; reg 1402 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c if (!rvu_check_valid_reg(TXSCHQ_HWREGMAP, lvl, reg)) reg 1405 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); reg 1441 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c u64 reg, regval; reg 1471 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c reg = NIX_AF_TL1X_TOPOLOGY(schq); reg 1473 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, reg, regval); reg 1474 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c reg = NIX_AF_TL1X_SCHEDULE(schq); reg 1476 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, reg, regval); reg 1477 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c reg = NIX_AF_TL1X_CIR(schq); reg 1479 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, reg, regval); reg 1495 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c u64 reg, regval, schq_regbase; reg 1531 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c reg = req->reg[idx]; reg 1533 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c schq_regbase = reg & 0xFFFF; reg 1536 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c txsch->lvl, reg, regval)) reg 1550 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c schq = TXSCHQ_IDX(reg, TXSCHQ_IDX_SHIFT); reg 1562 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, reg, regval); reg 1568 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c reg, BIT_ULL(49), true); reg 1852 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c u64 cfg, reg; reg 1863 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c reg = NIX_AF_MDQ_CONST; reg 1866 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c reg = NIX_AF_TL4_CONST; reg 1869 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c reg = NIX_AF_TL3_CONST; reg 1872 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c reg = NIX_AF_TL2_CONST; reg 1875 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c reg = NIX_AF_TL1_CONST; reg 1878 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, reg); reg 2918 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c u64 reg; reg 2932 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c reg = rvu_read64(rvu, blkaddr, reg 2934 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c if (req->fields[f] != (reg & req->field_mask)) reg 24 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c u64 reg, head; reg 29 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c reg = rvu_read64(rvu, block->addr, NPA_AF_AQ_STATUS); reg 30 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c head = (reg >> 4) & AQ_PTR_MASK; reg 846 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c u64 reg; reg 855 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c reg = NPC_AF_PKINDX_ACTION1(entry); reg 857 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c reg = NPC_AF_KPUX_ENTRYX_ACTION1(kpu, entry); reg 859 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, reg, *(u64 *)&action1); reg 875 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c reg = NPC_AF_PKINDX_ACTION0(entry); reg 877 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c reg = NPC_AF_KPUX_ENTRYX_ACTION0(kpu, entry); reg 879 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c rvu_write64(rvu, blkaddr, reg, *(u64 *)&action0); reg 42 drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c bool rvu_check_valid_reg(int regmap, int regblk, u64 reg) reg 48 drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c if (reg & 0x07) reg 63 drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c reg &= map->mask; reg 66 drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c if (reg >= map->range[idx].start && reg 67 drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c reg < map->range[idx].end) reg 96 drivers/net/ethernet/marvell/skge.c static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); reg 97 drivers/net/ethernet/marvell/skge.c static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); reg 177 drivers/net/ethernet/marvell/skge.c u32 reg = skge_read32(hw, B2_GP_IO); reg 178 drivers/net/ethernet/marvell/skge.c reg |= GP_DIR_9; reg 179 drivers/net/ethernet/marvell/skge.c reg &= ~GP_IO_9; reg 180 drivers/net/ethernet/marvell/skge.c skge_write32(hw, B2_GP_IO, reg); reg 1084 drivers/net/ethernet/marvell/skge.c static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) reg 1088 drivers/net/ethernet/marvell/skge.c xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); reg 1107 drivers/net/ethernet/marvell/skge.c static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg) reg 1110 drivers/net/ethernet/marvell/skge.c if (__xm_phy_read(hw, port, reg, &v)) reg 1115 drivers/net/ethernet/marvell/skge.c static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) reg 1119 drivers/net/ethernet/marvell/skge.c xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); reg 1168 drivers/net/ethernet/marvell/skge.c u32 reg; reg 1186 drivers/net/ethernet/marvell/skge.c reg = xm_read32(hw, port, XM_MODE); reg 1187 drivers/net/ethernet/marvell/skge.c xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF); reg 1188 drivers/net/ethernet/marvell/skge.c xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF); reg 1284 drivers/net/ethernet/marvell/skge.c u16 reg; reg 1312 drivers/net/ethernet/marvell/skge.c C0hack[i].reg, C0hack[i].val); reg 1322 drivers/net/ethernet/marvell/skge.c A1hack[i].reg, A1hack[i].val); reg 1711 drivers/net/ethernet/marvell/skge.c u32 reg = skge_read32(hw, B2_GP_IO); reg 1713 drivers/net/ethernet/marvell/skge.c reg |= GP_DIR_0; reg 1714 drivers/net/ethernet/marvell/skge.c reg &= ~GP_IO_0; reg 1716 drivers/net/ethernet/marvell/skge.c reg |= GP_DIR_2; reg 1717 drivers/net/ethernet/marvell/skge.c reg &= ~GP_IO_2; reg 1719 drivers/net/ethernet/marvell/skge.c skge_write32(hw, B2_GP_IO, reg); reg 1893 drivers/net/ethernet/marvell/skge.c static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) reg 1899 drivers/net/ethernet/marvell/skge.c GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg)); reg 1911 drivers/net/ethernet/marvell/skge.c static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) reg 1917 drivers/net/ethernet/marvell/skge.c | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); reg 1931 drivers/net/ethernet/marvell/skge.c static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg) reg 1934 drivers/net/ethernet/marvell/skge.c if (__gm_phy_read(hw, port, reg, &v)) reg 2043 drivers/net/ethernet/marvell/skge.c u32 reg; reg 2049 drivers/net/ethernet/marvell/skge.c reg = skge_read32(hw, B2_FAR); reg 2052 drivers/net/ethernet/marvell/skge.c skge_write32(hw, B2_FAR, reg); reg 2060 drivers/net/ethernet/marvell/skge.c u32 reg; reg 2066 drivers/net/ethernet/marvell/skge.c reg = skge_read32(hw, B2_GP_IO); reg 2067 drivers/net/ethernet/marvell/skge.c reg |= GP_DIR_9 | GP_IO_9; reg 2068 drivers/net/ethernet/marvell/skge.c skge_write32(hw, B2_GP_IO, reg); reg 2078 drivers/net/ethernet/marvell/skge.c reg = skge_read32(hw, B2_GP_IO); reg 2079 drivers/net/ethernet/marvell/skge.c reg |= GP_DIR_9; reg 2080 drivers/net/ethernet/marvell/skge.c reg &= ~GP_IO_9; reg 2081 drivers/net/ethernet/marvell/skge.c skge_write32(hw, B2_GP_IO, reg); reg 2085 drivers/net/ethernet/marvell/skge.c reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | reg 2087 drivers/net/ethernet/marvell/skge.c reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB; reg 2090 drivers/net/ethernet/marvell/skge.c skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET); reg 2091 drivers/net/ethernet/marvell/skge.c skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR); reg 2095 drivers/net/ethernet/marvell/skge.c reg = GM_GPCR_AU_ALL_DIS; reg 2097 drivers/net/ethernet/marvell/skge.c gma_read16(hw, port, GM_GP_CTRL) | reg); reg 2101 drivers/net/ethernet/marvell/skge.c reg &= ~GM_GPCR_SPEED_100; reg 2102 drivers/net/ethernet/marvell/skge.c reg |= GM_GPCR_SPEED_1000; reg 2105 drivers/net/ethernet/marvell/skge.c reg &= ~GM_GPCR_SPEED_1000; reg 2106 drivers/net/ethernet/marvell/skge.c reg |= GM_GPCR_SPEED_100; reg 2109 drivers/net/ethernet/marvell/skge.c reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); reg 2114 drivers/net/ethernet/marvell/skge.c reg |= GM_GPCR_DUP_FULL; reg 2116 drivers/net/ethernet/marvell/skge.c reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; reg 2121 drivers/net/ethernet/marvell/skge.c reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; reg 2125 drivers/net/ethernet/marvell/skge.c reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; reg 2133 drivers/net/ethernet/marvell/skge.c gma_write16(hw, port, GM_GP_CTRL, reg); reg 2139 drivers/net/ethernet/marvell/skge.c reg = gma_read16(hw, port, GM_PHY_ADDR); reg 2140 drivers/net/ethernet/marvell/skge.c gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); reg 2144 drivers/net/ethernet/marvell/skge.c gma_write16(hw, port, GM_PHY_ADDR, reg); reg 2163 drivers/net/ethernet/marvell/skge.c reg = DATA_BLIND_VAL(DATA_BLIND_DEF) reg 2168 drivers/net/ethernet/marvell/skge.c reg |= GM_SMOD_JUMBO_ENA; reg 2170 drivers/net/ethernet/marvell/skge.c gma_write16(hw, port, GM_SERIAL_MODE, reg); reg 2186 drivers/net/ethernet/marvell/skge.c reg = GMF_OPER_ON | GMF_RX_F_FL_ON; reg 2190 drivers/net/ethernet/marvell/skge.c reg &= ~GMF_RX_F_FL_ON; reg 2193 drivers/net/ethernet/marvell/skge.c skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg); reg 2298 drivers/net/ethernet/marvell/skge.c u16 reg; reg 2303 drivers/net/ethernet/marvell/skge.c reg = gma_read16(hw, port, GM_GP_CTRL); reg 2305 drivers/net/ethernet/marvell/skge.c reg |= GM_GPCR_DUP_FULL; reg 2308 drivers/net/ethernet/marvell/skge.c reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; reg 2309 drivers/net/ethernet/marvell/skge.c gma_write16(hw, port, GM_GP_CTRL, reg); reg 2976 drivers/net/ethernet/marvell/skge.c u16 reg; reg 2981 drivers/net/ethernet/marvell/skge.c reg = gma_read16(hw, port, GM_RX_CTRL); reg 2982 drivers/net/ethernet/marvell/skge.c reg |= GM_RXCR_UCF_ENA; reg 2985 drivers/net/ethernet/marvell/skge.c reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); reg 2989 drivers/net/ethernet/marvell/skge.c reg &= ~GM_RXCR_MCF_ENA; reg 2991 drivers/net/ethernet/marvell/skge.c reg |= GM_RXCR_MCF_ENA; reg 3010 drivers/net/ethernet/marvell/skge.c gma_write16(hw, port, GM_RX_CTRL, reg); reg 3518 drivers/net/ethernet/marvell/skge.c u32 reg; reg 3624 drivers/net/ethernet/marvell/skge.c pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®); reg 3625 drivers/net/ethernet/marvell/skge.c reg &= ~PCI_PHY_COMA; reg 3626 drivers/net/ethernet/marvell/skge.c pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg); reg 3913 drivers/net/ethernet/marvell/skge.c u32 reg; reg 3915 drivers/net/ethernet/marvell/skge.c pci_read_config_dword(pdev, PCI_DEV_REG2, ®); reg 3916 drivers/net/ethernet/marvell/skge.c reg |= PCI_REV_DESC; reg 3917 drivers/net/ethernet/marvell/skge.c pci_write_config_dword(pdev, PCI_DEV_REG2, reg); reg 482 drivers/net/ethernet/marvell/skge.h #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) reg 2482 drivers/net/ethernet/marvell/skge.h static inline u32 skge_read32(const struct skge_hw *hw, int reg) reg 2484 drivers/net/ethernet/marvell/skge.h return readl(hw->regs + reg); reg 2487 drivers/net/ethernet/marvell/skge.h static inline u16 skge_read16(const struct skge_hw *hw, int reg) reg 2489 drivers/net/ethernet/marvell/skge.h return readw(hw->regs + reg); reg 2492 drivers/net/ethernet/marvell/skge.h static inline u8 skge_read8(const struct skge_hw *hw, int reg) reg 2494 drivers/net/ethernet/marvell/skge.h return readb(hw->regs + reg); reg 2497 drivers/net/ethernet/marvell/skge.h static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val) reg 2499 drivers/net/ethernet/marvell/skge.h writel(val, hw->regs + reg); reg 2502 drivers/net/ethernet/marvell/skge.h static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val) reg 2504 drivers/net/ethernet/marvell/skge.h writew(val, hw->regs + reg); reg 2507 drivers/net/ethernet/marvell/skge.h static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val) reg 2509 drivers/net/ethernet/marvell/skge.h writeb(val, hw->regs + reg); reg 2513 drivers/net/ethernet/marvell/skge.h #define SK_REG(port,reg) (((port)<<7)+(u16)(reg)) reg 2514 drivers/net/ethernet/marvell/skge.h #define SK_XMAC_REG(port, reg) \ reg 2515 drivers/net/ethernet/marvell/skge.h ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1) reg 2517 drivers/net/ethernet/marvell/skge.h static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg) reg 2520 drivers/net/ethernet/marvell/skge.h v = skge_read16(hw, SK_XMAC_REG(port, reg)); reg 2521 drivers/net/ethernet/marvell/skge.h v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16; reg 2525 drivers/net/ethernet/marvell/skge.h static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg) reg 2527 drivers/net/ethernet/marvell/skge.h return skge_read16(hw, SK_XMAC_REG(port,reg)); reg 2541 drivers/net/ethernet/marvell/skge.h static inline void xm_outhash(const struct skge_hw *hw, int port, int reg, reg 2544 drivers/net/ethernet/marvell/skge.h xm_write16(hw, port, reg, (u16)hash[0] | ((u16)hash[1] << 8)); reg 2545 drivers/net/ethernet/marvell/skge.h xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8)); reg 2546 drivers/net/ethernet/marvell/skge.h xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8)); reg 2547 drivers/net/ethernet/marvell/skge.h xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8)); reg 2550 drivers/net/ethernet/marvell/skge.h static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg, reg 2553 drivers/net/ethernet/marvell/skge.h xm_write16(hw, port, reg, (u16)addr[0] | ((u16)addr[1] << 8)); reg 2554 drivers/net/ethernet/marvell/skge.h xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8)); reg 2555 drivers/net/ethernet/marvell/skge.h xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8)); reg 2558 drivers/net/ethernet/marvell/skge.h #define SK_GMAC_REG(port,reg) \ reg 2559 drivers/net/ethernet/marvell/skge.h (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg)) reg 2561 drivers/net/ethernet/marvell/skge.h static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg) reg 2563 drivers/net/ethernet/marvell/skge.h return skge_read16(hw, SK_GMAC_REG(port,reg)); reg 2566 drivers/net/ethernet/marvell/skge.h static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg) reg 2568 drivers/net/ethernet/marvell/skge.h return (u32) skge_read16(hw, SK_GMAC_REG(port,reg)) reg 2569 drivers/net/ethernet/marvell/skge.h | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16); reg 2577 drivers/net/ethernet/marvell/skge.h static inline void gma_set_addr(struct skge_hw *hw, int port, int reg, reg 2580 drivers/net/ethernet/marvell/skge.h gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8)); reg 2581 drivers/net/ethernet/marvell/skge.h gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8)); reg 2582 drivers/net/ethernet/marvell/skge.h gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8)); reg 150 drivers/net/ethernet/marvell/sky2.c static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) reg 156 drivers/net/ethernet/marvell/sky2.c GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); reg 177 drivers/net/ethernet/marvell/sky2.c static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) reg 182 drivers/net/ethernet/marvell/sky2.c | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); reg 204 drivers/net/ethernet/marvell/sky2.c static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) reg 207 drivers/net/ethernet/marvell/sky2.c __gm_phy_read(hw, port, reg, &v); reg 231 drivers/net/ethernet/marvell/sky2.c u32 reg; reg 235 drivers/net/ethernet/marvell/sky2.c reg = sky2_pci_read32(hw, PCI_DEV_REG4); reg 237 drivers/net/ethernet/marvell/sky2.c reg &= P_ASPM_CONTROL_MSK; reg 238 drivers/net/ethernet/marvell/sky2.c sky2_pci_write32(hw, PCI_DEV_REG4, reg); reg 240 drivers/net/ethernet/marvell/sky2.c reg = sky2_pci_read32(hw, PCI_DEV_REG5); reg 242 drivers/net/ethernet/marvell/sky2.c reg &= P_CTL_TIM_VMAIN_AV_MSK; reg 243 drivers/net/ethernet/marvell/sky2.c sky2_pci_write32(hw, PCI_DEV_REG5, reg); reg 250 drivers/net/ethernet/marvell/sky2.c reg = sky2_read32(hw, B2_GP_IO); reg 251 drivers/net/ethernet/marvell/sky2.c reg |= GLB_GPIO_STAT_RACE_DIS; reg 252 drivers/net/ethernet/marvell/sky2.c sky2_write32(hw, B2_GP_IO, reg); reg 285 drivers/net/ethernet/marvell/sky2.c u16 reg; reg 295 drivers/net/ethernet/marvell/sky2.c reg = gma_read16(hw, port, GM_RX_CTRL); reg 296 drivers/net/ethernet/marvell/sky2.c reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; reg 297 drivers/net/ethernet/marvell/sky2.c gma_write16(hw, port, GM_RX_CTRL, reg); reg 328 drivers/net/ethernet/marvell/sky2.c u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; reg 415 drivers/net/ethernet/marvell/sky2.c reg = 0; reg 446 drivers/net/ethernet/marvell/sky2.c reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS; reg 451 drivers/net/ethernet/marvell/sky2.c reg |= GM_GPCR_SPEED_1000; reg 455 drivers/net/ethernet/marvell/sky2.c reg |= GM_GPCR_SPEED_100; reg 460 drivers/net/ethernet/marvell/sky2.c reg |= GM_GPCR_DUP_FULL; reg 472 drivers/net/ethernet/marvell/sky2.c reg |= GM_GPCR_AU_FCT_DIS; reg 473 drivers/net/ethernet/marvell/sky2.c reg |= gm_fc_disable[sky2->flow_mode]; reg 482 drivers/net/ethernet/marvell/sky2.c gma_write16(hw, port, GM_GP_CTRL, reg); reg 631 drivers/net/ethernet/marvell/sky2.c u16 reg, val; reg 671 drivers/net/ethernet/marvell/sky2.c gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13); reg 679 drivers/net/ethernet/marvell/sky2.c reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); reg 681 drivers/net/ethernet/marvell/sky2.c reg | PHY_M_10B_TE_ENABLE); reg 774 drivers/net/ethernet/marvell/sky2.c u16 reg; reg 776 drivers/net/ethernet/marvell/sky2.c reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE); reg 777 drivers/net/ethernet/marvell/sky2.c reg &= ~GM_SMOD_IPG_MSK; reg 779 drivers/net/ethernet/marvell/sky2.c reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000); reg 781 drivers/net/ethernet/marvell/sky2.c reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); reg 782 drivers/net/ethernet/marvell/sky2.c gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg); reg 790 drivers/net/ethernet/marvell/sky2.c u16 reg; reg 792 drivers/net/ethernet/marvell/sky2.c reg = gma_read16(hw, port, GM_GP_CTRL); reg 793 drivers/net/ethernet/marvell/sky2.c reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; reg 794 drivers/net/ethernet/marvell/sky2.c gma_write16(hw, port, GM_GP_CTRL, reg); reg 900 drivers/net/ethernet/marvell/sky2.c u16 reg; reg 935 drivers/net/ethernet/marvell/sky2.c reg = gma_read16(hw, port, GM_PHY_ADDR); reg 936 drivers/net/ethernet/marvell/sky2.c gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); reg 940 drivers/net/ethernet/marvell/sky2.c gma_write16(hw, port, GM_PHY_ADDR, reg); reg 960 drivers/net/ethernet/marvell/sky2.c reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | reg 964 drivers/net/ethernet/marvell/sky2.c reg |= GM_SMOD_JUMBO_ENA; reg 968 drivers/net/ethernet/marvell/sky2.c reg |= GM_NEW_FLOW_CTRL; reg 970 drivers/net/ethernet/marvell/sky2.c gma_write16(hw, port, GM_SERIAL_MODE, reg); reg 1001 drivers/net/ethernet/marvell/sky2.c reg = RX_GMF_FL_THR_DEF + 1; reg 1005 drivers/net/ethernet/marvell/sky2.c reg = 0x178; reg 1006 drivers/net/ethernet/marvell/sky2.c sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg); reg 1017 drivers/net/ethernet/marvell/sky2.c reg = 1568 / 8; reg 1019 drivers/net/ethernet/marvell/sky2.c reg = 1024 / 8; reg 1020 drivers/net/ethernet/marvell/sky2.c sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg); reg 1029 drivers/net/ethernet/marvell/sky2.c reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA)); reg 1030 drivers/net/ethernet/marvell/sky2.c reg &= ~TX_DYN_WM_ENA; reg 1031 drivers/net/ethernet/marvell/sky2.c sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg); reg 2208 drivers/net/ethernet/marvell/sky2.c u16 reg; reg 2212 drivers/net/ethernet/marvell/sky2.c reg = gma_read16(hw, port, GM_GP_CTRL); reg 2213 drivers/net/ethernet/marvell/sky2.c reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); reg 2214 drivers/net/ethernet/marvell/sky2.c gma_write16(hw, port, GM_GP_CTRL, reg); reg 3302 drivers/net/ethernet/marvell/sky2.c u16 reg; reg 3309 drivers/net/ethernet/marvell/sky2.c reg = 10; reg 3315 drivers/net/ethernet/marvell/sky2.c reg = 3; reg 3318 drivers/net/ethernet/marvell/sky2.c reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE; reg 3319 drivers/net/ethernet/marvell/sky2.c reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT; reg 3323 drivers/net/ethernet/marvell/sky2.c sky2_pci_write16(hw, PSM_CONFIG_REG4, reg); reg 3326 drivers/net/ethernet/marvell/sky2.c reg = sky2_pci_read16(hw, PSM_CONFIG_REG3); reg 3327 drivers/net/ethernet/marvell/sky2.c if (reg & PCI_EXP_LNKCTL_ASPMC) reg 3330 drivers/net/ethernet/marvell/sky2.c reg); reg 3335 drivers/net/ethernet/marvell/sky2.c reg = sky2_read16(hw, GPHY_CTRL); reg 3336 drivers/net/ethernet/marvell/sky2.c sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL); reg 3339 drivers/net/ethernet/marvell/sky2.c reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL); reg 3340 drivers/net/ethernet/marvell/sky2.c sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1); reg 3847 drivers/net/ethernet/marvell/sky2.c u16 reg; reg 3855 drivers/net/ethernet/marvell/sky2.c reg = gma_read16(hw, port, GM_RX_CTRL); reg 3856 drivers/net/ethernet/marvell/sky2.c reg |= GM_RXCR_UCF_ENA; reg 3859 drivers/net/ethernet/marvell/sky2.c reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); reg 3863 drivers/net/ethernet/marvell/sky2.c reg &= ~GM_RXCR_MCF_ENA; reg 3865 drivers/net/ethernet/marvell/sky2.c reg |= GM_RXCR_MCF_ENA; reg 3883 drivers/net/ethernet/marvell/sky2.c gma_write16(hw, port, GM_RX_CTRL, reg); reg 4949 drivers/net/ethernet/marvell/sky2.c u32 reg; reg 4963 drivers/net/ethernet/marvell/sky2.c err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®); reg 4969 drivers/net/ethernet/marvell/sky2.c if (~reg == 0) { reg 5005 drivers/net/ethernet/marvell/sky2.c reg &= ~PCI_REV_DESC; reg 5006 drivers/net/ethernet/marvell/sky2.c err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg); reg 671 drivers/net/ethernet/marvell/sky2.h #define SK_REG(port,reg) (((port)<<7)+(reg)) reg 757 drivers/net/ethernet/marvell/sky2.h #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) reg 788 drivers/net/ethernet/marvell/sky2.h #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg)) reg 2321 drivers/net/ethernet/marvell/sky2.h static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg) reg 2323 drivers/net/ethernet/marvell/sky2.h return readl(hw->regs + reg); reg 2326 drivers/net/ethernet/marvell/sky2.h static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg) reg 2328 drivers/net/ethernet/marvell/sky2.h return readw(hw->regs + reg); reg 2331 drivers/net/ethernet/marvell/sky2.h static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg) reg 2333 drivers/net/ethernet/marvell/sky2.h return readb(hw->regs + reg); reg 2336 drivers/net/ethernet/marvell/sky2.h static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val) reg 2338 drivers/net/ethernet/marvell/sky2.h writel(val, hw->regs + reg); reg 2341 drivers/net/ethernet/marvell/sky2.h static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val) reg 2343 drivers/net/ethernet/marvell/sky2.h writew(val, hw->regs + reg); reg 2346 drivers/net/ethernet/marvell/sky2.h static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val) reg 2348 drivers/net/ethernet/marvell/sky2.h writeb(val, hw->regs + reg); reg 2352 drivers/net/ethernet/marvell/sky2.h #define SK_GMAC_REG(port,reg) \ reg 2353 drivers/net/ethernet/marvell/sky2.h (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg)) reg 2356 drivers/net/ethernet/marvell/sky2.h static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg) reg 2358 drivers/net/ethernet/marvell/sky2.h return sky2_read16(hw, SK_GMAC_REG(port,reg)); reg 2361 drivers/net/ethernet/marvell/sky2.h static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg) reg 2363 drivers/net/ethernet/marvell/sky2.h unsigned base = SK_GMAC_REG(port, reg); reg 2368 drivers/net/ethernet/marvell/sky2.h static inline u64 gma_read64(struct sky2_hw *hw, unsigned port, unsigned reg) reg 2370 drivers/net/ethernet/marvell/sky2.h unsigned base = SK_GMAC_REG(port, reg); reg 2379 drivers/net/ethernet/marvell/sky2.h static inline u32 get_stats32(struct sky2_hw *hw, unsigned port, unsigned reg) reg 2384 drivers/net/ethernet/marvell/sky2.h val = gma_read32(hw, port, reg); reg 2385 drivers/net/ethernet/marvell/sky2.h } while (gma_read32(hw, port, reg) != val); reg 2390 drivers/net/ethernet/marvell/sky2.h static inline u64 get_stats64(struct sky2_hw *hw, unsigned port, unsigned reg) reg 2395 drivers/net/ethernet/marvell/sky2.h val = gma_read64(hw, port, reg); reg 2396 drivers/net/ethernet/marvell/sky2.h } while (gma_read64(hw, port, reg) != val); reg 2406 drivers/net/ethernet/marvell/sky2.h static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg, reg 2409 drivers/net/ethernet/marvell/sky2.h gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8)); reg 2410 drivers/net/ethernet/marvell/sky2.h gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8)); reg 2411 drivers/net/ethernet/marvell/sky2.h gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8)); reg 2415 drivers/net/ethernet/marvell/sky2.h static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg) reg 2417 drivers/net/ethernet/marvell/sky2.h return sky2_read32(hw, Y2_CFG_SPC + reg); reg 2420 drivers/net/ethernet/marvell/sky2.h static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg) reg 2422 drivers/net/ethernet/marvell/sky2.h return sky2_read16(hw, Y2_CFG_SPC + reg); reg 2425 drivers/net/ethernet/marvell/sky2.h static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val) reg 2427 drivers/net/ethernet/marvell/sky2.h sky2_write32(hw, Y2_CFG_SPC + reg, val); reg 2430 drivers/net/ethernet/marvell/sky2.h static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val) reg 2432 drivers/net/ethernet/marvell/sky2.h sky2_write16(hw, Y2_CFG_SPC + reg, val); reg 58 drivers/net/ethernet/mediatek/mtk_eth_soc.c void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) reg 60 drivers/net/ethernet/mediatek/mtk_eth_soc.c __raw_writel(val, eth->base + reg); reg 63 drivers/net/ethernet/mediatek/mtk_eth_soc.c u32 mtk_r32(struct mtk_eth *eth, unsigned reg) reg 65 drivers/net/ethernet/mediatek/mtk_eth_soc.c return __raw_readl(eth->base + reg); reg 68 drivers/net/ethernet/mediatek/mtk_eth_soc.c u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) reg 72 drivers/net/ethernet/mediatek/mtk_eth_soc.c val = mtk_r32(eth, reg); reg 75 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, val, reg); reg 76 drivers/net/ethernet/mediatek/mtk_eth_soc.c return reg; reg 926 drivers/net/ethernet/mediatek/mtk_eth_soc.h void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); reg 927 drivers/net/ethernet/mediatek/mtk_eth_soc.h u32 mtk_r32(struct mtk_eth *eth, unsigned reg); reg 753 drivers/net/ethernet/mellanox/mlx4/en_tx.c mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl, reg 224 drivers/net/ethernet/mellanox/mlx4/pd.c bf->reg = uar->bf_map + idx * dev->caps.bf_reg_size; reg 255 drivers/net/ethernet/mellanox/mlx4/pd.c idx = (bf->reg - bf->uar->bf_map) / dev->caps.bf_reg_size; reg 289 drivers/net/ethernet/mellanox/mlxsw/core.c const struct mlxsw_reg_info *reg, reg 293 drivers/net/ethernet/mellanox/mlxsw/core.c mlxsw_emad_reg_tlv_len_set(reg_tlv, reg->len / sizeof(u32) + 1); reg 294 drivers/net/ethernet/mellanox/mlxsw/core.c memcpy(reg_tlv + sizeof(u32), payload, reg->len); reg 298 drivers/net/ethernet/mellanox/mlxsw/core.c const struct mlxsw_reg_info *reg, reg 306 drivers/net/ethernet/mellanox/mlxsw/core.c mlxsw_emad_op_tlv_register_id_set(op_tlv, reg->id); reg 335 drivers/net/ethernet/mellanox/mlxsw/core.c const struct mlxsw_reg_info *reg, reg 345 drivers/net/ethernet/mellanox/mlxsw/core.c buf = skb_push(skb, reg->len + sizeof(u32)); reg 346 drivers/net/ethernet/mellanox/mlxsw/core.c mlxsw_emad_pack_reg_tlv(buf, reg, payload); reg 349 drivers/net/ethernet/mellanox/mlxsw/core.c mlxsw_emad_pack_op_tlv(buf, reg, type, tid); reg 430 drivers/net/ethernet/mellanox/mlxsw/core.c const struct mlxsw_reg_info *reg; reg 533 drivers/net/ethernet/mellanox/mlxsw/core.c trans->reg->len, trans->cb_priv); reg 645 drivers/net/ethernet/mellanox/mlxsw/core.c const struct mlxsw_reg_info *reg, reg 657 drivers/net/ethernet/mellanox/mlxsw/core.c tid, reg->id, mlxsw_reg_id_str(reg->id), reg 660 drivers/net/ethernet/mellanox/mlxsw/core.c skb = mlxsw_emad_alloc(mlxsw_core, reg->len); reg 674 drivers/net/ethernet/mellanox/mlxsw/core.c trans->reg = reg; reg 677 drivers/net/ethernet/mellanox/mlxsw/core.c mlxsw_emad_construct(skb, reg, payload, type, trans->tid); reg 1382 drivers/net/ethernet/mellanox/mlxsw/core.c struct mlxsw_reg_info reg; reg 1387 drivers/net/ethernet/mellanox/mlxsw/core.c reg.id = mlxsw_emad_op_tlv_register_id_get(op_tlv); reg 1388 drivers/net/ethernet/mellanox/mlxsw/core.c reg.len = (mlxsw_emad_reg_tlv_len_get(reg_tlv) - 1) * sizeof(u32); reg 1390 drivers/net/ethernet/mellanox/mlxsw/core.c event_listener_item->el.func(®, payload, event_listener_item->priv); reg 1561 drivers/net/ethernet/mellanox/mlxsw/core.c const struct mlxsw_reg_info *reg, reg 1576 drivers/net/ethernet/mellanox/mlxsw/core.c err = mlxsw_emad_reg_access(mlxsw_core, reg, payload, type, trans, reg 1586 drivers/net/ethernet/mellanox/mlxsw/core.c const struct mlxsw_reg_info *reg, char *payload, reg 1590 drivers/net/ethernet/mellanox/mlxsw/core.c return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload, reg 1597 drivers/net/ethernet/mellanox/mlxsw/core.c const struct mlxsw_reg_info *reg, char *payload, reg 1601 drivers/net/ethernet/mellanox/mlxsw/core.c return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload, reg 1621 drivers/net/ethernet/mellanox/mlxsw/core.c trans->tid, trans->reg->id, reg 1622 drivers/net/ethernet/mellanox/mlxsw/core.c mlxsw_reg_id_str(trans->reg->id), reg 1653 drivers/net/ethernet/mellanox/mlxsw/core.c const struct mlxsw_reg_info *reg, reg 1663 drivers/net/ethernet/mellanox/mlxsw/core.c reg->id, mlxsw_reg_id_str(reg->id), reg 1676 drivers/net/ethernet/mellanox/mlxsw/core.c mlxsw_emad_pack_op_tlv(in_mbox, reg, type, reg 1679 drivers/net/ethernet/mellanox/mlxsw/core.c mlxsw_emad_pack_reg_tlv(tmp, reg, payload); reg 1686 drivers/net/ethernet/mellanox/mlxsw/core.c reset_ok = reg->id == MLXSW_REG_MRSR_ID; reg 1703 drivers/net/ethernet/mellanox/mlxsw/core.c reg->len); reg 1710 drivers/net/ethernet/mellanox/mlxsw/core.c reg->id, mlxsw_reg_id_str(reg->id), reg 1725 drivers/net/ethernet/mellanox/mlxsw/core.c const struct mlxsw_reg_info *reg, reg 1737 drivers/net/ethernet/mellanox/mlxsw/core.c return mlxsw_core_reg_access_cmd(mlxsw_core, reg, reg 1740 drivers/net/ethernet/mellanox/mlxsw/core.c err = mlxsw_core_reg_access_emad(mlxsw_core, reg, reg 1750 drivers/net/ethernet/mellanox/mlxsw/core.c const struct mlxsw_reg_info *reg, char *payload) reg 1752 drivers/net/ethernet/mellanox/mlxsw/core.c return mlxsw_core_reg_access(mlxsw_core, reg, payload, reg 1758 drivers/net/ethernet/mellanox/mlxsw/core.c const struct mlxsw_reg_info *reg, char *payload) reg 1760 drivers/net/ethernet/mellanox/mlxsw/core.c return mlxsw_core_reg_access(mlxsw_core, reg, payload, reg 62 drivers/net/ethernet/mellanox/mlxsw/core.h void (*func)(const struct mlxsw_reg_info *reg, reg 139 drivers/net/ethernet/mellanox/mlxsw/core.h const struct mlxsw_reg_info *reg, char *payload, reg 143 drivers/net/ethernet/mellanox/mlxsw/core.h const struct mlxsw_reg_info *reg, char *payload, reg 149 drivers/net/ethernet/mellanox/mlxsw/core.h const struct mlxsw_reg_info *reg, char *payload); reg 151 drivers/net/ethernet/mellanox/mlxsw/core.h const struct mlxsw_reg_info *reg, char *payload); reg 25 drivers/net/ethernet/mellanox/mlxsw/pci.c #define mlxsw_pci_write32(mlxsw_pci, reg, val) \ reg 26 drivers/net/ethernet/mellanox/mlxsw/pci.c iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) reg 27 drivers/net/ethernet/mellanox/mlxsw/pci.c #define mlxsw_pci_read32(mlxsw_pci, reg) \ reg 28 drivers/net/ethernet/mellanox/mlxsw/pci.c ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) reg 47 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); reg 70 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); reg 87 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); reg 94 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); reg 100 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); reg 106 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); reg 137 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); reg 144 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); reg 152 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); reg 162 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); reg 187 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); reg 196 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); reg 225 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); reg 259 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); reg 268 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); reg 277 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); reg 291 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, reg 305 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, reg 323 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, reg 332 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, reg 339 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, reg 359 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, reg 368 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, reg 381 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, reg 388 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, reg 434 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, reg 447 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, reg 454 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, reg 461 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, reg 497 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, reg 505 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, reg 514 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, reg 535 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, reg 542 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, reg 554 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, reg 564 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, reg 602 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); reg 608 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); reg 618 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); reg 632 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, reg 654 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, reg 661 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, reg 669 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, reg 676 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, reg 683 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, reg 699 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, reg 717 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, reg 729 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, reg 738 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, reg 753 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, reg 784 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); reg 801 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); reg 828 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); reg 835 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); reg 841 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); reg 871 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); reg 878 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); reg 884 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); reg 891 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); reg 897 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); reg 903 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, reg 911 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, reg 920 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, reg 928 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, reg 967 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); reg 974 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); reg 980 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); reg 986 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); reg 992 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); reg 1030 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); reg 1042 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); reg 1058 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); reg 1065 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); reg 1071 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); reg 1077 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); reg 1083 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); reg 1113 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); reg 1120 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); reg 1127 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); reg 1133 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); reg 1139 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); reg 1145 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); reg 1151 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); reg 1183 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); reg 1210 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); reg 1218 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); reg 1232 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); reg 1238 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); reg 1244 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); reg 1250 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); reg 1256 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); reg 1283 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); reg 1289 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); reg 1311 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); reg 1317 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); reg 1361 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); reg 1370 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); reg 1382 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); reg 1442 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); reg 1448 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); reg 1481 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); reg 1488 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); reg 1494 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); reg 1501 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); reg 1556 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); reg 1563 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); reg 1582 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); reg 1607 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); reg 1615 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); reg 1630 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); reg 1639 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); reg 1645 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); reg 1651 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); reg 1659 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); reg 1667 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); reg 1698 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); reg 1706 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); reg 1736 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); reg 1742 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); reg 1750 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); reg 1759 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); reg 1767 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); reg 1776 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); reg 1784 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); reg 1818 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); reg 1824 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); reg 1831 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, reg 1838 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, reg 1876 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); reg 1882 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); reg 1888 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, reg 1896 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, reg 1903 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, reg 1954 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); reg 1960 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); reg 1968 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); reg 1976 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); reg 1984 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); reg 1992 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); reg 2000 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); reg 2008 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); reg 2016 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); reg 2024 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); reg 2059 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); reg 2084 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); reg 2094 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); reg 2100 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); reg 2108 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); reg 2115 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); reg 2143 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); reg 2150 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); reg 2159 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, reg 2193 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); reg 2200 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); reg 2208 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); reg 2214 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); reg 2261 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); reg 2268 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); reg 2279 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); reg 2289 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); reg 2296 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); reg 2304 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, reg 2315 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, reg 2357 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); reg 2363 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); reg 2398 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); reg 2404 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); reg 2410 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); reg 2416 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, reg 2423 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); reg 2429 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, reg 2463 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); reg 2472 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); reg 2480 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); reg 2489 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); reg 2526 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); reg 2533 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); reg 2560 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); reg 2567 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); reg 2590 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); reg 2595 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); reg 2604 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); reg 2610 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, reg 2619 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, reg 2628 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, reg 2635 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, reg 2665 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); reg 2672 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); reg 2684 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); reg 2693 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); reg 2699 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); reg 2706 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); reg 2713 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); reg 2719 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); reg 2725 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); reg 2733 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); reg 2778 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); reg 2794 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); reg 2818 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); reg 2836 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); reg 2844 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); reg 2850 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, reg 2858 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, reg 2865 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); reg 2872 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); reg 2883 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); reg 2890 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); reg 2902 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); reg 2910 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); reg 2923 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); reg 2933 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); reg 2940 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); reg 2981 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); reg 2987 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); reg 2993 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); reg 3002 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); reg 3010 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); reg 3036 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); reg 3042 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); reg 3048 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); reg 3055 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); reg 3064 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); reg 3073 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); reg 3081 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); reg 3126 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); reg 3134 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, reg 3143 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, reg 3152 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, reg 3193 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); reg 3199 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, reg 3206 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11, reg 3213 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, reg 3250 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); reg 3261 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); reg 3291 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); reg 3297 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); reg 3304 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); reg 3312 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); reg 3325 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); reg 3338 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); reg 3351 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); reg 3360 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); reg 3370 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); reg 3378 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); reg 3394 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); reg 3428 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); reg 3435 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); reg 3441 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); reg 3451 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); reg 3477 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); reg 3493 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); reg 3499 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); reg 3507 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); reg 3516 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); reg 3528 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); reg 3544 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); reg 3555 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); reg 3564 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); reg 3575 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); reg 3584 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); reg 3593 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); reg 3603 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); reg 3641 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); reg 3647 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); reg 3653 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); reg 3682 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); reg 3688 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, reg 3697 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, reg 3705 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, reg 3714 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, reg 3722 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, reg 3731 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, reg 3771 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); reg 3779 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, reg 3786 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, reg 3822 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); reg 3829 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); reg 3860 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); reg 3868 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); reg 3876 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); reg 3883 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); reg 3891 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); reg 3897 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); reg 3905 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); reg 3915 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); reg 3925 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); reg 3959 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); reg 3965 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); reg 3974 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); reg 3980 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); reg 3986 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false); reg 3993 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false); reg 4014 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); reg 4023 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); reg 4031 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); reg 4040 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); reg 4070 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); reg 4076 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); reg 4088 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); reg 4100 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); reg 4119 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); reg 4153 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); reg 4159 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); reg 4172 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); reg 4178 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); reg 4184 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); reg 4190 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); reg 4196 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); reg 4202 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); reg 4208 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); reg 4214 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); reg 4220 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); reg 4238 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); reg 4334 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); reg 4340 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); reg 4347 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); reg 4373 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); reg 4379 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); reg 4390 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); reg 4400 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); reg 4406 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); reg 4413 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); reg 4422 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); reg 4450 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); reg 4458 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); reg 4467 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); reg 4476 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); reg 4488 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); reg 4495 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); reg 4502 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); reg 4510 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); reg 4518 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); reg 4530 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); reg 4538 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); reg 4546 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); reg 4555 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); reg 4592 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); reg 4600 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); reg 4608 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); reg 4639 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); reg 4647 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); reg 4657 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); reg 4664 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, reg 4670 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, reg 4676 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, reg 4682 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, reg 4688 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, reg 4694 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, reg 4700 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, reg 4706 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, reg 4712 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, reg 4718 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, reg 4724 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, reg 4730 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, reg 4736 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, reg 4742 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, reg 4748 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, reg 4754 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, reg 4760 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, reg 4766 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, reg 4772 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, reg 4780 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, if_in_discards, reg 4786 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, if_out_discards, reg 4792 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, if_out_errors, reg 4800 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, reg 4806 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, reg 4812 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, reg 4818 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, reg 4824 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, reg 4830 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, reg 4836 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, reg 4842 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, reg 4848 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, reg 4854 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, reg 4860 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, reg 4866 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, reg 4872 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, reg 4880 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, reg 4886 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, reg 4892 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, reg 4898 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, reg 4906 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ecn_marked, reg 4914 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ingress_general, reg 4920 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, reg 4926 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, reg 4932 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, reg 4938 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, reg 4944 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, loopback_filter, reg 4950 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, egress_general, reg 4956 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, egress_hoq, reg 4962 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, reg 4968 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, reg 4974 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, reg 4980 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, egress_sll, reg 4988 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, rx_octets, reg 4994 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, rx_frames, reg 5000 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, tx_octets, reg 5006 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, tx_frames, reg 5012 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, rx_pause, reg 5018 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, reg 5024 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, tx_pause, reg 5030 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, reg 5036 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, reg 5047 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, reg 5055 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, reg 5063 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ppcnt, wred_discard, reg 5092 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); reg 5098 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); reg 5124 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); reg 5130 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); reg 5136 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); reg 5143 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); reg 5150 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); reg 5157 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); reg 5166 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); reg 5173 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); reg 5207 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); reg 5214 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); reg 5222 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); reg 5232 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); reg 5241 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); reg 5248 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); reg 5259 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, reg 5271 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, reg 5317 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); reg 5323 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); reg 5330 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); reg 5353 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8); reg 5364 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); reg 5389 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); reg 5397 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); reg 5441 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); reg 5452 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); reg 5460 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); reg 5473 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); reg 5479 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); reg 5494 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); reg 5502 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); reg 5514 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); reg 5561 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); reg 5589 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); reg 5595 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); reg 5604 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); reg 5620 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); reg 5649 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); reg 5655 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); reg 5662 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); reg 5672 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); reg 5683 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); reg 5699 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); reg 5722 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); reg 5729 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); reg 5736 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); reg 5742 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); reg 5748 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); reg 5765 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); reg 5781 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); reg 5787 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); reg 5796 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); reg 5805 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); reg 5813 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); reg 5821 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); reg 5830 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); reg 5836 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); reg 5842 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); reg 5848 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); reg 5855 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); reg 5862 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); reg 5869 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); reg 5877 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); reg 5886 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); reg 5905 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); reg 5912 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); reg 5918 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); reg 5934 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); reg 5949 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); reg 5959 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); reg 5967 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); reg 5974 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); reg 5980 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); reg 5981 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); reg 5988 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); reg 6007 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); reg 6013 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); reg 6019 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); reg 6025 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); reg 6131 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); reg 6142 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); reg 6151 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); reg 6196 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); reg 6210 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); reg 6217 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); reg 6249 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); reg 6258 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); reg 6264 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); reg 6278 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); reg 6284 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); reg 6297 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); reg 6303 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); reg 6317 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); reg 6324 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); reg 6331 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); reg 6346 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); reg 6352 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); reg 6414 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, reg 6421 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, reg 6444 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); reg 6462 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); reg 6477 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); reg 6483 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); reg 6489 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); reg 6495 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); reg 6502 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); reg 6509 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); reg 6516 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); reg 6522 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); reg 6528 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); reg 6535 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); reg 6542 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); reg 6573 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); reg 6579 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); reg 6585 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); reg 6592 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); reg 6598 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); reg 6628 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); reg 6640 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); reg 6648 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); reg 6680 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); reg 6686 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); reg 6698 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); reg 6706 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, reg 6746 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); reg 6752 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); reg 6760 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); reg 6786 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); reg 6819 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); reg 6828 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); reg 6835 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); reg 6848 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); reg 6856 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); reg 6866 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); reg 6867 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); reg 6880 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); reg 6890 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); reg 6907 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); reg 6922 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); reg 6930 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); reg 6937 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); reg 6947 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); reg 6954 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); reg 6966 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); reg 6974 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); reg 7070 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); reg 7101 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); reg 7110 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); reg 7116 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); reg 7122 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); reg 7123 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); reg 7136 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); reg 7150 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); reg 7156 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); reg 7162 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); reg 7168 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); reg 7220 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); reg 7227 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); reg 7233 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); reg 7239 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); reg 7245 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); reg 7251 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); reg 7298 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); reg 7308 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); reg 7318 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); reg 7325 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); reg 7338 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); reg 7345 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); reg 7366 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, reg 7376 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, reg 7386 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, reg 7393 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, reg 7400 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, reg 7410 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, reg 7417 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, reg 7424 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, reg 7462 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); reg 7469 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); reg 7476 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); reg 7484 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); reg 7504 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); reg 7518 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); reg 7529 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); reg 7536 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); reg 7545 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); reg 7552 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); reg 7593 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); reg 7599 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); reg 7606 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); reg 7612 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); reg 7621 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); reg 7631 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); reg 7639 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); reg 7671 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); reg 7677 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); reg 7683 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); reg 7705 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); reg 7738 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); reg 7803 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); reg 7813 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); reg 7830 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); reg 7837 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); reg 7843 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); reg 7849 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); reg 7860 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); reg 7866 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); reg 7872 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); reg 7873 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); reg 7880 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); reg 7881 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); reg 7887 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); reg 7888 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); reg 7895 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); reg 7896 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); reg 7909 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, reg 7985 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); reg 7993 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); reg 8001 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); reg 8034 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); reg 8041 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); reg 8065 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); reg 8071 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); reg 8094 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); reg 8100 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); reg 8106 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); reg 8143 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); reg 8171 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); reg 8192 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); reg 8205 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); reg 8211 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); reg 8217 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); reg 8224 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); reg 8233 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); reg 8241 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); reg 8247 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); reg 8255 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); reg 8305 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); reg 8314 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); reg 8321 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, reg 8329 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, reg 8376 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); reg 8382 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); reg 8388 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); reg 8394 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); reg 8400 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); reg 8406 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); reg 8412 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); reg 8448 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); reg 8477 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); reg 8483 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); reg 8489 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); reg 8500 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); reg 8510 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); reg 8534 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); reg 8544 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); reg 8558 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); reg 8564 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); reg 8570 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); reg 8585 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); reg 8591 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); reg 8597 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); reg 8603 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); reg 8604 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); reg 8610 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); reg 8611 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); reg 8682 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); reg 8693 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); reg 8700 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); reg 8706 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); reg 8732 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); reg 8740 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); reg 8745 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); reg 8750 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); reg 8755 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); reg 8789 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); reg 8810 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); reg 8820 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); reg 8827 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); reg 8853 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); reg 8864 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); reg 8872 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); reg 8882 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); reg 8913 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); reg 8921 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); reg 8927 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); reg 8954 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); reg 8964 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); reg 8971 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); reg 8978 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); reg 8984 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); reg 8991 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); reg 8997 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); reg 9045 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); reg 9052 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); reg 9058 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); reg 9065 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); reg 9071 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); reg 9079 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); reg 9120 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); reg 9127 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); reg 9133 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); reg 9139 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); reg 9169 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); reg 9175 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); reg 9184 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); reg 9207 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); reg 9213 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); reg 9226 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); reg 9232 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); reg 9238 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); reg 9266 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); reg 9274 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); reg 9282 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); reg 9308 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); reg 9317 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); reg 9338 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); reg 9347 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); reg 9379 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8); reg 9390 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); reg 9396 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); reg 9403 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); reg 9410 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, reg 9418 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, reg 9426 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, reg 9436 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, reg 9444 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, reg 9484 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); reg 9492 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); reg 9521 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); reg 9527 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); reg 9533 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); reg 9576 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); reg 9582 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); reg 9588 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); reg 9594 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); reg 9610 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); reg 9627 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); reg 9633 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); reg 9640 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); reg 9657 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); reg 9664 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); reg 9674 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); reg 9684 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); reg 9691 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); reg 9698 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); reg 9705 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); reg 9711 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); reg 9718 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); reg 9758 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); reg 9771 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); reg 9778 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); reg 9784 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); reg 9790 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); reg 9797 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); reg 9803 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); reg 9810 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); reg 9845 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); reg 9867 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8); reg 9873 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); reg 9896 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); reg 9902 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); reg 9926 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); reg 9932 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); reg 9939 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); reg 9947 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); reg 9954 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); reg 9989 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); reg 9995 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); reg 10001 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); reg 10027 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); reg 10034 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); reg 10062 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); reg 10068 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); reg 10074 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); reg 10081 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); reg 10092 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); reg 10124 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); reg 10134 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); reg 10140 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); reg 10146 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); reg 10156 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); reg 10170 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); reg 10176 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); reg 10210 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); reg 10216 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); reg 10222 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); reg 10228 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); reg 10236 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); reg 10243 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); reg 10249 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); reg 10262 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); reg 10299 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); reg 10305 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); reg 10318 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); reg 10324 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); reg 10360 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); reg 10369 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); reg 10379 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); reg 10388 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); reg 10398 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); reg 10410 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, reg 10418 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, reg 10449 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); reg 10457 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); reg 10616 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); reg 10622 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); reg 10633 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); reg 10643 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); reg 4195 drivers/net/ethernet/mellanox/mlxsw/spectrum.c static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg, reg 4244 drivers/net/ethernet/mellanox/mlxsw/spectrum.c static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg, reg 4252 drivers/net/ethernet/mellanox/mlxsw/spectrum.c static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg, reg 375 drivers/net/ethernet/mellanox/mlxsw/switchib.c static void mlxsw_sib_pude_event_func(const struct mlxsw_reg_info *reg, reg 1323 drivers/net/ethernet/mellanox/mlxsw/switchx2.c static void mlxsw_sx_pude_event_func(const struct mlxsw_reg_info *reg, reg 193 drivers/net/ethernet/micrel/ks8842.c u16 reg; reg 195 drivers/net/ethernet/micrel/ks8842.c reg = ioread16(adapter->hw_addr + offset); reg 196 drivers/net/ethernet/micrel/ks8842.c reg |= bits; reg 197 drivers/net/ethernet/micrel/ks8842.c iowrite16(reg, adapter->hw_addr + offset); reg 203 drivers/net/ethernet/micrel/ks8842.c u16 reg; reg 205 drivers/net/ethernet/micrel/ks8842.c reg = ioread16(adapter->hw_addr + offset); reg 206 drivers/net/ethernet/micrel/ks8842.c reg &= ~bits; reg 207 drivers/net/ethernet/micrel/ks8842.c iowrite16(reg, adapter->hw_addr + offset); reg 169 drivers/net/ethernet/micrel/ks8851.c static void ks8851_wrreg16(struct ks8851_net *ks, unsigned reg, unsigned val) reg 176 drivers/net/ethernet/micrel/ks8851.c txb[0] = cpu_to_le16(MK_OP(reg & 2 ? 0xC : 0x03, reg) | KS_SPIOP_WR); reg 196 drivers/net/ethernet/micrel/ks8851.c static void ks8851_wrreg8(struct ks8851_net *ks, unsigned reg, unsigned val) reg 204 drivers/net/ethernet/micrel/ks8851.c bit = 1 << (reg & 3); reg 206 drivers/net/ethernet/micrel/ks8851.c txb[0] = cpu_to_le16(MK_OP(bit, reg) | KS_SPIOP_WR); reg 276 drivers/net/ethernet/micrel/ks8851.c static unsigned ks8851_rdreg8(struct ks8851_net *ks, unsigned reg) reg 280 drivers/net/ethernet/micrel/ks8851.c ks8851_rdreg(ks, MK_OP(1 << (reg & 3), reg), rxb, 1); reg 291 drivers/net/ethernet/micrel/ks8851.c static unsigned ks8851_rdreg16(struct ks8851_net *ks, unsigned reg) reg 295 drivers/net/ethernet/micrel/ks8851.c ks8851_rdreg(ks, MK_OP(reg & 2 ? 0xC : 0x3, reg), (u8 *)&rx, 2); reg 308 drivers/net/ethernet/micrel/ks8851.c static unsigned ks8851_rdreg32(struct ks8851_net *ks, unsigned reg) reg 312 drivers/net/ethernet/micrel/ks8851.c WARN_ON(reg & 3); reg 314 drivers/net/ethernet/micrel/ks8851.c ks8851_rdreg(ks, MK_OP(0xf, reg), (u8 *)&rx, 4); reg 1283 drivers/net/ethernet/micrel/ks8851.c static int ks8851_phy_reg(int reg) reg 1285 drivers/net/ethernet/micrel/ks8851.c switch (reg) { reg 1318 drivers/net/ethernet/micrel/ks8851.c static int ks8851_phy_read(struct net_device *dev, int phy_addr, int reg) reg 1324 drivers/net/ethernet/micrel/ks8851.c ksreg = ks8851_phy_reg(reg); reg 1336 drivers/net/ethernet/micrel/ks8851.c int phy, int reg, int value) reg 1341 drivers/net/ethernet/micrel/ks8851.c ksreg = ks8851_phy_reg(reg); reg 1056 drivers/net/ethernet/micrel/ks8851_mll.c static int ks_phy_reg(int reg) reg 1058 drivers/net/ethernet/micrel/ks8851_mll.c switch (reg) { reg 1091 drivers/net/ethernet/micrel/ks8851_mll.c static int ks_phy_read(struct net_device *netdev, int phy_addr, int reg) reg 1097 drivers/net/ethernet/micrel/ks8851_mll.c ksreg = ks_phy_reg(reg); reg 1109 drivers/net/ethernet/micrel/ks8851_mll.c int phy, int reg, int value) reg 1114 drivers/net/ethernet/micrel/ks8851_mll.c ksreg = ks_phy_reg(reg); reg 1650 drivers/net/ethernet/micrel/ksz884x.c #define HW_DELAY(hw, reg) \ reg 1653 drivers/net/ethernet/micrel/ksz884x.c dummy = readw(hw->io + reg); \ reg 2965 drivers/net/ethernet/micrel/ksz884x.c static void hw_r_phy(struct ksz_hw *hw, int port, u16 reg, u16 *val) reg 2969 drivers/net/ethernet/micrel/ksz884x.c phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg; reg 2982 drivers/net/ethernet/micrel/ksz884x.c static void hw_w_phy(struct ksz_hw *hw, int port, u16 reg, u16 val) reg 2986 drivers/net/ethernet/micrel/ksz884x.c phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg; reg 3068 drivers/net/ethernet/micrel/ksz884x.c static void spi_reg(struct ksz_hw *hw, u8 data, u8 reg) reg 3085 drivers/net/ethernet/micrel/ksz884x.c (reg & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) : reg 3111 drivers/net/ethernet/micrel/ksz884x.c static u16 eeprom_read(struct ksz_hw *hw, u8 reg) reg 3117 drivers/net/ethernet/micrel/ksz884x.c spi_reg(hw, AT93C_READ, reg); reg 3133 drivers/net/ethernet/micrel/ksz884x.c static void eeprom_write(struct ksz_hw *hw, u8 reg, u16 data) reg 3146 drivers/net/ethernet/micrel/ksz884x.c spi_reg(hw, AT93C_ERASE, reg); reg 3162 drivers/net/ethernet/micrel/ksz884x.c spi_reg(hw, AT93C_WRITE, reg); reg 359 drivers/net/ethernet/microchip/enc28j60.c u16 reg; reg 361 drivers/net/ethernet/microchip/enc28j60.c reg = nolock_regw_read(priv, ERDPTL); reg 362 drivers/net/ethernet/microchip/enc28j60.c if (reg != addr) reg 365 drivers/net/ethernet/microchip/enc28j60.c __func__, reg, addr); reg 385 drivers/net/ethernet/microchip/enc28j60.c u16 reg; reg 386 drivers/net/ethernet/microchip/enc28j60.c reg = nolock_regw_read(priv, EWRPTL); reg 387 drivers/net/ethernet/microchip/enc28j60.c if (reg != TXSTART_INIT) reg 390 drivers/net/ethernet/microchip/enc28j60.c __func__, reg, TXSTART_INIT); reg 410 drivers/net/ethernet/microchip/enc28j60.c static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val) reg 416 drivers/net/ethernet/microchip/enc28j60.c while ((nolock_regb_read(priv, reg) & mask) != val) { reg 419 drivers/net/ethernet/microchip/enc28j60.c dev_dbg(dev, "reg %02x ready timeout!\n", reg); reg 652 drivers/net/ethernet/microchip/enc28j60.c u8 reg; reg 680 drivers/net/ethernet/microchip/enc28j60.c reg = locked_regb_read(priv, EREVID); reg 682 drivers/net/ethernet/microchip/enc28j60.c dev_info(dev, "chip RevID: 0x%02x\n", reg); reg 683 drivers/net/ethernet/microchip/enc28j60.c if (reg == 0x00 || reg == 0xff) { reg 686 drivers/net/ethernet/microchip/enc28j60.c __func__, reg); reg 995 drivers/net/ethernet/microchip/enc28j60.c u16 reg; reg 996 drivers/net/ethernet/microchip/enc28j60.c reg = nolock_regw_read(priv, ERXRDPTL); reg 997 drivers/net/ethernet/microchip/enc28j60.c if (reg != erxrdpt) reg 1000 drivers/net/ethernet/microchip/enc28j60.c __func__, reg, erxrdpt); reg 1049 drivers/net/ethernet/microchip/enc28j60.c u16 reg; reg 1052 drivers/net/ethernet/microchip/enc28j60.c reg = enc28j60_phy_read(priv, PHSTAT2); reg 1056 drivers/net/ethernet/microchip/enc28j60.c enc28j60_phy_read(priv, PHSTAT1), reg); reg 1057 drivers/net/ethernet/microchip/enc28j60.c duplex = reg & PHSTAT2_DPXSTAT; reg 1059 drivers/net/ethernet/microchip/enc28j60.c if (reg & PHSTAT2_LSTAT) { reg 65 drivers/net/ethernet/microchip/encx24j600-regmap.c static int regmap_encx24j600_sfr_read(void *context, u8 reg, u8 *val, reg 69 drivers/net/ethernet/microchip/encx24j600-regmap.c u8 banked_reg = reg & ADDR_MASK; reg 70 drivers/net/ethernet/microchip/encx24j600-regmap.c u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); reg 76 drivers/net/ethernet/microchip/encx24j600-regmap.c if (reg < 0x80) { reg 86 drivers/net/ethernet/microchip/encx24j600-regmap.c switch (reg) { reg 109 drivers/net/ethernet/microchip/encx24j600-regmap.c tx_buf[i++] = reg; reg 117 drivers/net/ethernet/microchip/encx24j600-regmap.c u8 reg, u8 *val, size_t len, reg 120 drivers/net/ethernet/microchip/encx24j600-regmap.c u8 banked_reg = reg & ADDR_MASK; reg 121 drivers/net/ethernet/microchip/encx24j600-regmap.c u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); reg 125 drivers/net/ethernet/microchip/encx24j600-regmap.c { .tx_buf = ®, .len = sizeof(reg), }, reg 128 drivers/net/ethernet/microchip/encx24j600-regmap.c if (reg < 0x80) { reg 140 drivers/net/ethernet/microchip/encx24j600-regmap.c switch (reg) { reg 165 drivers/net/ethernet/microchip/encx24j600-regmap.c t[1].tx_buf = ® reg 173 drivers/net/ethernet/microchip/encx24j600-regmap.c static int regmap_encx24j600_sfr_write(void *context, u8 reg, u8 *val, reg 178 drivers/net/ethernet/microchip/encx24j600-regmap.c return regmap_encx24j600_sfr_update(ctx, reg, val, len, WCRU, WCRCODE); reg 182 drivers/net/ethernet/microchip/encx24j600-regmap.c u8 reg, u8 val) reg 184 drivers/net/ethernet/microchip/encx24j600-regmap.c return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFSU, BFSCODE); reg 188 drivers/net/ethernet/microchip/encx24j600-regmap.c u8 reg, u8 val) reg 190 drivers/net/ethernet/microchip/encx24j600-regmap.c return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFCU, BFCCODE); reg 193 drivers/net/ethernet/microchip/encx24j600-regmap.c static int regmap_encx24j600_reg_update_bits(void *context, unsigned int reg, reg 203 drivers/net/ethernet/microchip/encx24j600-regmap.c if ((reg >= 0x40 && reg < 0x6c) || reg >= 0x80) reg 207 drivers/net/ethernet/microchip/encx24j600-regmap.c ret = regmap_encx24j600_sfr_set_bits(ctx, reg, set_mask); reg 212 drivers/net/ethernet/microchip/encx24j600-regmap.c ret = regmap_encx24j600_sfr_set_bits(ctx, reg + 1, set_mask); reg 215 drivers/net/ethernet/microchip/encx24j600-regmap.c ret = regmap_encx24j600_sfr_clr_bits(ctx, reg, clr_mask); reg 220 drivers/net/ethernet/microchip/encx24j600-regmap.c ret = regmap_encx24j600_sfr_clr_bits(ctx, reg + 1, clr_mask); reg 225 drivers/net/ethernet/microchip/encx24j600-regmap.c int regmap_encx24j600_spi_write(void *context, u8 reg, const u8 *data, reg 230 drivers/net/ethernet/microchip/encx24j600-regmap.c if (reg < 0xc0) reg 231 drivers/net/ethernet/microchip/encx24j600-regmap.c return encx24j600_cmdn(ctx, reg, data, count); reg 234 drivers/net/ethernet/microchip/encx24j600-regmap.c return spi_write(ctx->spi, ®, 1); reg 238 drivers/net/ethernet/microchip/encx24j600-regmap.c int regmap_encx24j600_spi_read(void *context, u8 reg, u8 *data, size_t count) reg 242 drivers/net/ethernet/microchip/encx24j600-regmap.c if (reg == RBSEL && count > 1) reg 245 drivers/net/ethernet/microchip/encx24j600-regmap.c return spi_write_then_read(ctx->spi, ®, sizeof(reg), data, count); reg 253 drivers/net/ethernet/microchip/encx24j600-regmap.c u8 reg = dout[0]; reg 257 drivers/net/ethernet/microchip/encx24j600-regmap.c if (reg > 0xa0) reg 258 drivers/net/ethernet/microchip/encx24j600-regmap.c return regmap_encx24j600_spi_write(context, reg, dout, len); reg 263 drivers/net/ethernet/microchip/encx24j600-regmap.c return regmap_encx24j600_sfr_write(context, reg, dout, len); reg 270 drivers/net/ethernet/microchip/encx24j600-regmap.c u8 reg = *(const u8 *)reg_buf; reg 273 drivers/net/ethernet/microchip/encx24j600-regmap.c pr_err("%s: reg=%02x reg_size=%zu\n", __func__, reg, reg_size); reg 277 drivers/net/ethernet/microchip/encx24j600-regmap.c if (reg > 0xa0) reg 278 drivers/net/ethernet/microchip/encx24j600-regmap.c return regmap_encx24j600_spi_read(context, reg, val, val_size); reg 281 drivers/net/ethernet/microchip/encx24j600-regmap.c pr_err("%s: reg=%02x val_size=%zu\n", __func__, reg, val_size); reg 285 drivers/net/ethernet/microchip/encx24j600-regmap.c return regmap_encx24j600_sfr_read(context, reg, val, val_size); reg 288 drivers/net/ethernet/microchip/encx24j600-regmap.c static bool encx24j600_regmap_readable(struct device *dev, unsigned int reg) reg 290 drivers/net/ethernet/microchip/encx24j600-regmap.c if ((reg < 0x36) || reg 291 drivers/net/ethernet/microchip/encx24j600-regmap.c ((reg >= 0x40) && (reg < 0x4c)) || reg 292 drivers/net/ethernet/microchip/encx24j600-regmap.c ((reg >= 0x52) && (reg < 0x56)) || reg 293 drivers/net/ethernet/microchip/encx24j600-regmap.c ((reg >= 0x60) && (reg < 0x66)) || reg 294 drivers/net/ethernet/microchip/encx24j600-regmap.c ((reg >= 0x68) && (reg < 0x80)) || reg 295 drivers/net/ethernet/microchip/encx24j600-regmap.c ((reg >= 0x86) && (reg < 0x92)) || reg 296 drivers/net/ethernet/microchip/encx24j600-regmap.c (reg == 0xc8)) reg 302 drivers/net/ethernet/microchip/encx24j600-regmap.c static bool encx24j600_regmap_writeable(struct device *dev, unsigned int reg) reg 304 drivers/net/ethernet/microchip/encx24j600-regmap.c if ((reg < 0x12) || reg 305 drivers/net/ethernet/microchip/encx24j600-regmap.c ((reg >= 0x14) && (reg < 0x1a)) || reg 306 drivers/net/ethernet/microchip/encx24j600-regmap.c ((reg >= 0x1c) && (reg < 0x36)) || reg 307 drivers/net/ethernet/microchip/encx24j600-regmap.c ((reg >= 0x40) && (reg < 0x4c)) || reg 308 drivers/net/ethernet/microchip/encx24j600-regmap.c ((reg >= 0x52) && (reg < 0x56)) || reg 309 drivers/net/ethernet/microchip/encx24j600-regmap.c ((reg >= 0x60) && (reg < 0x68)) || reg 310 drivers/net/ethernet/microchip/encx24j600-regmap.c ((reg >= 0x6c) && (reg < 0x80)) || reg 311 drivers/net/ethernet/microchip/encx24j600-regmap.c ((reg >= 0x86) && (reg < 0x92)) || reg 312 drivers/net/ethernet/microchip/encx24j600-regmap.c ((reg >= 0xc0) && (reg < 0xc8)) || reg 313 drivers/net/ethernet/microchip/encx24j600-regmap.c ((reg >= 0xca) && (reg < 0xf0))) reg 319 drivers/net/ethernet/microchip/encx24j600-regmap.c static bool encx24j600_regmap_volatile(struct device *dev, unsigned int reg) reg 321 drivers/net/ethernet/microchip/encx24j600-regmap.c switch (reg) { reg 340 drivers/net/ethernet/microchip/encx24j600-regmap.c static bool encx24j600_regmap_precious(struct device *dev, unsigned int reg) reg 343 drivers/net/ethernet/microchip/encx24j600-regmap.c if (((reg >= 0xc0) && (reg < 0xc8)) || reg 344 drivers/net/ethernet/microchip/encx24j600-regmap.c ((reg >= 0xca) && (reg < 0xf0))) reg 350 drivers/net/ethernet/microchip/encx24j600-regmap.c static int regmap_encx24j600_phy_reg_read(void *context, unsigned int reg, reg 357 drivers/net/ethernet/microchip/encx24j600-regmap.c reg = MIREGADR_VAL | (reg & PHREG_MASK); reg 358 drivers/net/ethernet/microchip/encx24j600-regmap.c ret = regmap_write(ctx->regmap, MIREGADR, reg); reg 383 drivers/net/ethernet/microchip/encx24j600-regmap.c reg & PHREG_MASK); reg 388 drivers/net/ethernet/microchip/encx24j600-regmap.c static int regmap_encx24j600_phy_reg_write(void *context, unsigned int reg, reg 395 drivers/net/ethernet/microchip/encx24j600-regmap.c reg = MIREGADR_VAL | (reg & PHREG_MASK); reg 396 drivers/net/ethernet/microchip/encx24j600-regmap.c ret = regmap_write(ctx->regmap, MIREGADR, reg); reg 412 drivers/net/ethernet/microchip/encx24j600-regmap.c reg & PHREG_MASK, val); reg 417 drivers/net/ethernet/microchip/encx24j600-regmap.c static bool encx24j600_phymap_readable(struct device *dev, unsigned int reg) reg 419 drivers/net/ethernet/microchip/encx24j600-regmap.c switch (reg) { reg 434 drivers/net/ethernet/microchip/encx24j600-regmap.c static bool encx24j600_phymap_writeable(struct device *dev, unsigned int reg) reg 436 drivers/net/ethernet/microchip/encx24j600-regmap.c switch (reg) { reg 451 drivers/net/ethernet/microchip/encx24j600-regmap.c static bool encx24j600_phymap_volatile(struct device *dev, unsigned int reg) reg 453 drivers/net/ethernet/microchip/encx24j600-regmap.c switch (reg) { reg 98 drivers/net/ethernet/microchip/encx24j600.c static u16 encx24j600_read_reg(struct encx24j600_priv *priv, u8 reg) reg 102 drivers/net/ethernet/microchip/encx24j600.c int ret = regmap_read(priv->ctx.regmap, reg, &val); reg 106 drivers/net/ethernet/microchip/encx24j600.c __func__, ret, reg); reg 110 drivers/net/ethernet/microchip/encx24j600.c static void encx24j600_write_reg(struct encx24j600_priv *priv, u8 reg, u16 val) reg 113 drivers/net/ethernet/microchip/encx24j600.c int ret = regmap_write(priv->ctx.regmap, reg, val); reg 117 drivers/net/ethernet/microchip/encx24j600.c __func__, ret, reg, val); reg 120 drivers/net/ethernet/microchip/encx24j600.c static void encx24j600_update_reg(struct encx24j600_priv *priv, u8 reg, reg 124 drivers/net/ethernet/microchip/encx24j600.c int ret = regmap_update_bits(priv->ctx.regmap, reg, mask, val); reg 128 drivers/net/ethernet/microchip/encx24j600.c __func__, ret, reg, val, mask); reg 131 drivers/net/ethernet/microchip/encx24j600.c static u16 encx24j600_read_phy(struct encx24j600_priv *priv, u8 reg) reg 135 drivers/net/ethernet/microchip/encx24j600.c int ret = regmap_read(priv->ctx.phymap, reg, &val); reg 139 drivers/net/ethernet/microchip/encx24j600.c __func__, ret, reg); reg 143 drivers/net/ethernet/microchip/encx24j600.c static void encx24j600_write_phy(struct encx24j600_priv *priv, u8 reg, u16 val) reg 146 drivers/net/ethernet/microchip/encx24j600.c int ret = regmap_write(priv->ctx.phymap, reg, val); reg 150 drivers/net/ethernet/microchip/encx24j600.c __func__, ret, reg, val); reg 153 drivers/net/ethernet/microchip/encx24j600.c static void encx24j600_clr_bits(struct encx24j600_priv *priv, u8 reg, u16 mask) reg 155 drivers/net/ethernet/microchip/encx24j600.c encx24j600_update_reg(priv, reg, mask, 0); reg 158 drivers/net/ethernet/microchip/encx24j600.c static void encx24j600_set_bits(struct encx24j600_priv *priv, u8 reg, u16 mask) reg 160 drivers/net/ethernet/microchip/encx24j600.c encx24j600_update_reg(priv, reg, mask, mask); reg 173 drivers/net/ethernet/microchip/encx24j600.c static int encx24j600_raw_read(struct encx24j600_priv *priv, u8 reg, u8 *data, reg 179 drivers/net/ethernet/microchip/encx24j600.c ret = regmap_encx24j600_spi_read(&priv->ctx, reg, data, count); reg 185 drivers/net/ethernet/microchip/encx24j600.c static int encx24j600_raw_write(struct encx24j600_priv *priv, u8 reg, reg 191 drivers/net/ethernet/microchip/encx24j600.c ret = regmap_encx24j600_spi_write(&priv->ctx, reg, data, count); reg 916 drivers/net/ethernet/microchip/encx24j600.c u8 reg; reg 920 drivers/net/ethernet/microchip/encx24j600.c for (reg = 0; reg < SFR_REG_COUNT; reg += 2) { reg 923 drivers/net/ethernet/microchip/encx24j600.c regmap_read(priv->ctx.regmap, reg, &val); reg 924 drivers/net/ethernet/microchip/encx24j600.c buff[reg] = val & 0xffff; reg 433 drivers/net/ethernet/microchip/encx24j600_hw.h int regmap_encx24j600_spi_write(void *context, u8 reg, const u8 *data, reg 435 drivers/net/ethernet/microchip/encx24j600_hw.h int regmap_encx24j600_spi_read(void *context, u8 reg, u8 *data, size_t count); reg 43 drivers/net/ethernet/moxa/moxart_ether.c unsigned int reg, unsigned long value) reg 47 drivers/net/ethernet/moxa/moxart_ether.c writel(value, priv->base + reg); reg 76 drivers/net/ethernet/mscc/ocelot.h #define REG(reg, offset) [reg & REG_MASK] = offset reg 514 drivers/net/ethernet/mscc/ocelot.h u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset); reg 515 drivers/net/ethernet/mscc/ocelot.h #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) reg 516 drivers/net/ethernet/mscc/ocelot.h #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi)) reg 517 drivers/net/ethernet/mscc/ocelot.h #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri)) reg 518 drivers/net/ethernet/mscc/ocelot.h #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0) reg 520 drivers/net/ethernet/mscc/ocelot.h void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset); reg 521 drivers/net/ethernet/mscc/ocelot.h #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) reg 522 drivers/net/ethernet/mscc/ocelot.h #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi)) reg 523 drivers/net/ethernet/mscc/ocelot.h #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri)) reg 524 drivers/net/ethernet/mscc/ocelot.h #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0) reg 526 drivers/net/ethernet/mscc/ocelot.h void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg, reg 528 drivers/net/ethernet/mscc/ocelot.h #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) reg 529 drivers/net/ethernet/mscc/ocelot.h #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi)) reg 530 drivers/net/ethernet/mscc/ocelot.h #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri)) reg 531 drivers/net/ethernet/mscc/ocelot.h #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0) reg 533 drivers/net/ethernet/mscc/ocelot.h u32 ocelot_port_readl(struct ocelot_port *port, u32 reg); reg 534 drivers/net/ethernet/mscc/ocelot.h void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg); reg 542 drivers/net/ethernet/mscc/ocelot.h #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val)) reg 543 drivers/net/ethernet/mscc/ocelot.h #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val)) reg 13 drivers/net/ethernet/mscc/ocelot_io.c u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset) reg 15 drivers/net/ethernet/mscc/ocelot_io.c u16 target = reg >> TARGET_OFFSET; reg 21 drivers/net/ethernet/mscc/ocelot_io.c ocelot->map[target][reg & REG_MASK] + offset, &val); reg 26 drivers/net/ethernet/mscc/ocelot_io.c void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset) reg 28 drivers/net/ethernet/mscc/ocelot_io.c u16 target = reg >> TARGET_OFFSET; reg 33 drivers/net/ethernet/mscc/ocelot_io.c ocelot->map[target][reg & REG_MASK] + offset, val); reg 37 drivers/net/ethernet/mscc/ocelot_io.c void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg, reg 40 drivers/net/ethernet/mscc/ocelot_io.c u16 target = reg >> TARGET_OFFSET; reg 45 drivers/net/ethernet/mscc/ocelot_io.c ocelot->map[target][reg & REG_MASK] + offset, reg 50 drivers/net/ethernet/mscc/ocelot_io.c u32 ocelot_port_readl(struct ocelot_port *port, u32 reg) reg 52 drivers/net/ethernet/mscc/ocelot_io.c return readl(port->regs + reg); reg 56 drivers/net/ethernet/mscc/ocelot_io.c void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg) reg 58 drivers/net/ethernet/mscc/ocelot_io.c writel(val, port->regs + reg); reg 70 drivers/net/ethernet/mscc/ocelot_io.c u32 reg = regfields[i].reg; reg 72 drivers/net/ethernet/mscc/ocelot_io.c if (!reg) reg 75 drivers/net/ethernet/mscc/ocelot_io.c target = regfields[i].reg >> TARGET_OFFSET; reg 77 drivers/net/ethernet/mscc/ocelot_io.c regfield.reg = ocelot->map[target][reg & REG_MASK]; reg 56 drivers/net/ethernet/natsemi/jazzsonic.c #define SONIC_READ(reg) (*((volatile unsigned int *)dev->base_addr+reg)) reg 58 drivers/net/ethernet/natsemi/jazzsonic.c #define SONIC_WRITE(reg,val) \ reg 60 drivers/net/ethernet/natsemi/jazzsonic.c *((volatile unsigned int *)dev->base_addr+(reg)) = (val); \ reg 68 drivers/net/ethernet/natsemi/macsonic.c #define SONIC_READ(reg) (nubus_readw(dev->base_addr + (reg * 4) \ reg 70 drivers/net/ethernet/natsemi/macsonic.c #define SONIC_WRITE(reg,val) (nubus_writew(val, dev->base_addr + (reg * 4) \ reg 600 drivers/net/ethernet/natsemi/natsemi.c static int mdio_read(struct net_device *dev, int reg); reg 601 drivers/net/ethernet/natsemi/natsemi.c static void mdio_write(struct net_device *dev, int reg, u16 data); reg 603 drivers/net/ethernet/natsemi/natsemi.c static int miiport_read(struct net_device *dev, int phy_id, int reg); reg 604 drivers/net/ethernet/natsemi/natsemi.c static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data); reg 1080 drivers/net/ethernet/natsemi/natsemi.c static int miiport_read(struct net_device *dev, int phy_id, int reg) reg 1090 drivers/net/ethernet/natsemi/natsemi.c cmd = (0x06 << 10) | (phy_id << 5) | reg; reg 1105 drivers/net/ethernet/natsemi/natsemi.c static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data) reg 1113 drivers/net/ethernet/natsemi/natsemi.c cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data; reg 1119 drivers/net/ethernet/natsemi/natsemi.c static int mdio_read(struct net_device *dev, int reg) reg 1129 drivers/net/ethernet/natsemi/natsemi.c return readw(ioaddr+BasicControl+(reg<<2)); reg 1131 drivers/net/ethernet/natsemi/natsemi.c return miiport_read(dev, np->phy_addr_external, reg); reg 1134 drivers/net/ethernet/natsemi/natsemi.c static void mdio_write(struct net_device *dev, int reg, u16 data) reg 1141 drivers/net/ethernet/natsemi/natsemi.c writew(data, ioaddr+BasicControl+(reg<<2)); reg 1143 drivers/net/ethernet/natsemi/natsemi.c miiport_write(dev, np->phy_addr_external, reg, data); reg 1790 drivers/net/ethernet/natsemi/ns83820.c static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg) reg 1810 drivers/net/ethernet/natsemi/ns83820.c ns83820_mii_write_bit(dev, reg & (0x10 >> i)); reg 1824 drivers/net/ethernet/natsemi/ns83820.c static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data) reg 1843 drivers/net/ethernet/natsemi/ns83820.c ns83820_mii_write_bit(dev, reg & (0x10 >> i)); reg 70 drivers/net/ethernet/natsemi/xtsonic.c #define SONIC_READ(reg) \ reg 71 drivers/net/ethernet/natsemi/xtsonic.c (0xffff & *((volatile unsigned int *)dev->base_addr+reg)) reg 73 drivers/net/ethernet/natsemi/xtsonic.c #define SONIC_WRITE(reg,val) \ reg 74 drivers/net/ethernet/natsemi/xtsonic.c *((volatile unsigned int *)dev->base_addr+reg) = val reg 5361 drivers/net/ethernet/neterion/s2io.c u64 reg; reg 5369 drivers/net/ethernet/neterion/s2io.c reg = readq(sp->bar0 + i); reg 5370 drivers/net/ethernet/neterion/s2io.c memcpy((reg_space + i), ®, 8); reg 119 drivers/net/ethernet/neterion/vxge/vxge-config.c __vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis) reg 127 drivers/net/ethernet/neterion/vxge/vxge-config.c val64 = readq(reg); reg 135 drivers/net/ethernet/neterion/vxge/vxge-config.c val64 = readq(reg); reg 132 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c u64 reg; reg 145 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c offset, ®); reg 152 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *reg_space++ = reg; reg 103 drivers/net/ethernet/netronome/nfp/bpf/jit.c struct nfp_insn_re_regs reg; reg 106 drivers/net/ethernet/netronome/nfp/bpf/jit.c err = swreg_to_restricted(reg_none(), lreg, rreg, ®, false); reg 111 drivers/net/ethernet/netronome/nfp/bpf/jit.c if (reg.swap) { reg 116 drivers/net/ethernet/netronome/nfp/bpf/jit.c if (reg.dst_lmextn || reg.src_lmextn) { reg 122 drivers/net/ethernet/netronome/nfp/bpf/jit.c __emit_cmd(nfp_prog, op, mode, xfer, reg.areg, reg.breg, size, ctx, reg 211 drivers/net/ethernet/netronome/nfp/bpf/jit.c struct nfp_insn_re_regs reg; reg 220 drivers/net/ethernet/netronome/nfp/bpf/jit.c err = swreg_to_restricted(reg_none(), src, reg_imm(bit), ®, false); reg 226 drivers/net/ethernet/netronome/nfp/bpf/jit.c __emit_br_bit(nfp_prog, reg.areg, reg.breg, addr, defer, set, reg 227 drivers/net/ethernet/netronome/nfp/bpf/jit.c reg.src_lmextn); reg 258 drivers/net/ethernet/netronome/nfp/bpf/jit.c struct nfp_insn_ur_regs reg; reg 261 drivers/net/ethernet/netronome/nfp/bpf/jit.c err = swreg_to_unrestricted(reg_none(), base, reg_imm(0), ®); reg 267 drivers/net/ethernet/netronome/nfp/bpf/jit.c __emit_br_alu(nfp_prog, reg.areg, reg.breg, 0, defer, reg.dst_lmextn, reg 268 drivers/net/ethernet/netronome/nfp/bpf/jit.c reg.src_lmextn); reg 297 drivers/net/ethernet/netronome/nfp/bpf/jit.c struct nfp_insn_ur_regs reg; reg 305 drivers/net/ethernet/netronome/nfp/bpf/jit.c err = swreg_to_unrestricted(dst, dst, reg_imm(imm & 0xff), ®); reg 313 drivers/net/ethernet/netronome/nfp/bpf/jit.c swreg_type(dst) == NN_REG_NONE ? reg.dst : reg.areg, reg 314 drivers/net/ethernet/netronome/nfp/bpf/jit.c reg.breg, imm >> 8, width, invert, shift, reg 315 drivers/net/ethernet/netronome/nfp/bpf/jit.c reg.wr_both, reg.dst_lmextn, reg.src_lmextn); reg 366 drivers/net/ethernet/netronome/nfp/bpf/jit.c struct nfp_insn_re_regs reg; reg 369 drivers/net/ethernet/netronome/nfp/bpf/jit.c err = swreg_to_restricted(dst, lreg, rreg, ®, true); reg 375 drivers/net/ethernet/netronome/nfp/bpf/jit.c __emit_shf(nfp_prog, reg.dst, reg.dst_ab, sc, shift, reg 376 drivers/net/ethernet/netronome/nfp/bpf/jit.c reg.areg, op, reg.breg, reg.i8, reg.swap, reg.wr_both, reg 377 drivers/net/ethernet/netronome/nfp/bpf/jit.c reg.dst_lmextn, reg.src_lmextn); reg 418 drivers/net/ethernet/netronome/nfp/bpf/jit.c struct nfp_insn_ur_regs reg; reg 421 drivers/net/ethernet/netronome/nfp/bpf/jit.c err = swreg_to_unrestricted(dst, lreg, rreg, ®); reg 427 drivers/net/ethernet/netronome/nfp/bpf/jit.c __emit_alu(nfp_prog, reg.dst, reg.dst_ab, reg 428 drivers/net/ethernet/netronome/nfp/bpf/jit.c reg.areg, op, reg.breg, reg.swap, reg.wr_both, reg 429 drivers/net/ethernet/netronome/nfp/bpf/jit.c reg.dst_lmextn, reg.src_lmextn); reg 457 drivers/net/ethernet/netronome/nfp/bpf/jit.c struct nfp_insn_ur_regs reg; reg 470 drivers/net/ethernet/netronome/nfp/bpf/jit.c err = swreg_to_unrestricted(lreg, reg_none(), rreg, ®); reg 471 drivers/net/ethernet/netronome/nfp/bpf/jit.c areg = reg.dst; reg 473 drivers/net/ethernet/netronome/nfp/bpf/jit.c err = swreg_to_unrestricted(reg_none(), lreg, rreg, ®); reg 474 drivers/net/ethernet/netronome/nfp/bpf/jit.c areg = reg.areg; reg 482 drivers/net/ethernet/netronome/nfp/bpf/jit.c __emit_mul(nfp_prog, reg.dst_ab, areg, type, step, reg.breg, reg.swap, reg 483 drivers/net/ethernet/netronome/nfp/bpf/jit.c reg.wr_both, reg.dst_lmextn, reg.src_lmextn); reg 514 drivers/net/ethernet/netronome/nfp/bpf/jit.c struct nfp_insn_re_regs reg; reg 518 drivers/net/ethernet/netronome/nfp/bpf/jit.c err = swreg_to_restricted(dst, dst, src, ®, true); reg 524 drivers/net/ethernet/netronome/nfp/bpf/jit.c __emit_ld_field(nfp_prog, sc, reg.areg, bmask, reg.breg, shift, reg 525 drivers/net/ethernet/netronome/nfp/bpf/jit.c reg.i8, zero, reg.swap, reg.wr_both, reg 526 drivers/net/ethernet/netronome/nfp/bpf/jit.c reg.dst_lmextn, reg.src_lmextn); reg 555 drivers/net/ethernet/netronome/nfp/bpf/jit.c struct nfp_insn_ur_regs reg; reg 564 drivers/net/ethernet/netronome/nfp/bpf/jit.c err = swreg_to_unrestricted(reg_none(), src, reg_none(), ®); reg 565 drivers/net/ethernet/netronome/nfp/bpf/jit.c reg.breg = reg.areg; reg 567 drivers/net/ethernet/netronome/nfp/bpf/jit.c err = swreg_to_unrestricted(reg_none(), src, reg_imm(0), ®); reg 574 drivers/net/ethernet/netronome/nfp/bpf/jit.c __emit_lcsr(nfp_prog, reg.areg, reg.breg, true, addr, reg 575 drivers/net/ethernet/netronome/nfp/bpf/jit.c false, reg.src_lmextn); reg 1027 drivers/net/ethernet/netronome/nfp/bpf/jit.c swreg reg; reg 1068 drivers/net/ethernet/netronome/nfp/bpf/jit.c reg = reg_lm(lm3 ? 3 : 0, idx); reg 1070 drivers/net/ethernet/netronome/nfp/bpf/jit.c reg = imm_a(nfp_prog); reg 1077 drivers/net/ethernet/netronome/nfp/bpf/jit.c wrp_mov(nfp_prog, reg, reg_lm(0, idx)); reg 1080 drivers/net/ethernet/netronome/nfp/bpf/jit.c emit_ld_field_any(nfp_prog, reg_both(dst), mask, reg, sc, shf, new_gpr); reg 1096 drivers/net/ethernet/netronome/nfp/bpf/jit.c swreg reg; reg 1138 drivers/net/ethernet/netronome/nfp/bpf/jit.c reg = reg_lm(lm3 ? 3 : 0, idx); reg 1140 drivers/net/ethernet/netronome/nfp/bpf/jit.c reg = imm_a(nfp_prog); reg 1145 drivers/net/ethernet/netronome/nfp/bpf/jit.c wrp_mov(nfp_prog, reg, reg_lm(0, idx)); reg 1148 drivers/net/ethernet/netronome/nfp/bpf/jit.c emit_ld_field(nfp_prog, reg, mask, reg_b(src), sc, shf); reg 1152 drivers/net/ethernet/netronome/nfp/bpf/jit.c wrp_mov(nfp_prog, reg_lm(0, idx), reg); reg 1406 drivers/net/ethernet/netronome/nfp/bpf/jit.c u8 reg = insn->dst_reg * 2; reg 1418 drivers/net/ethernet/netronome/nfp/bpf/jit.c emit_alu(nfp_prog, reg_none(), reg_a(reg), alu_op, tmp_reg); reg 1420 drivers/net/ethernet/netronome/nfp/bpf/jit.c emit_alu(nfp_prog, reg_none(), tmp_reg, alu_op, reg_a(reg)); reg 1426 drivers/net/ethernet/netronome/nfp/bpf/jit.c reg_a(reg + 1), carry_op, tmp_reg); reg 1429 drivers/net/ethernet/netronome/nfp/bpf/jit.c tmp_reg, carry_op, reg_a(reg + 1)); reg 1734 drivers/net/ethernet/netronome/nfp/bpf/jit.c lm_off += meta->arg2.reg.var_off.value + meta->arg2.reg.off; reg 3757 drivers/net/ethernet/netronome/nfp/bpf/jit.c u8 reg; reg 3763 drivers/net/ethernet/netronome/nfp/bpf/jit.c for (reg = BPF_REG_6; reg <= BPF_REG_9; reg++) { reg 3764 drivers/net/ethernet/netronome/nfp/bpf/jit.c u8 adj = (reg - BPF_REG_0) * 2; reg 3765 drivers/net/ethernet/netronome/nfp/bpf/jit.c u8 idx = (reg - BPF_REG_6) * 2; reg 3772 drivers/net/ethernet/netronome/nfp/bpf/jit.c if (reg == BPF_REG_8) reg 3782 drivers/net/ethernet/netronome/nfp/bpf/jit.c u8 reg; reg 3788 drivers/net/ethernet/netronome/nfp/bpf/jit.c for (reg = BPF_REG_6; reg <= BPF_REG_9; reg++) { reg 3789 drivers/net/ethernet/netronome/nfp/bpf/jit.c u8 adj = (reg - BPF_REG_0) * 2; reg 3790 drivers/net/ethernet/netronome/nfp/bpf/jit.c u8 idx = (reg - BPF_REG_6) * 2; reg 3797 drivers/net/ethernet/netronome/nfp/bpf/jit.c if (reg == BPF_REG_8) reg 250 drivers/net/ethernet/netronome/nfp/bpf/main.h struct bpf_reg_state reg; reg 74 drivers/net/ethernet/netronome/nfp/bpf/verifier.c if (meta->arg2.reg.var_off.value != imm) reg 125 drivers/net/ethernet/netronome/nfp/bpf/verifier.c const struct bpf_reg_state *reg, reg 130 drivers/net/ethernet/netronome/nfp/bpf/verifier.c if (reg->type != PTR_TO_STACK) { reg 132 drivers/net/ethernet/netronome/nfp/bpf/verifier.c fname, reg->type); reg 135 drivers/net/ethernet/netronome/nfp/bpf/verifier.c if (!tnum_is_const(reg->var_off)) { reg 140 drivers/net/ethernet/netronome/nfp/bpf/verifier.c off = reg->var_off.value + reg->off; reg 150 drivers/net/ethernet/netronome/nfp/bpf/verifier.c old_off = old_arg->reg.var_off.value + old_arg->reg.off; reg 305 drivers/net/ethernet/netronome/nfp/bpf/verifier.c meta->arg2.reg = *reg2; reg 345 drivers/net/ethernet/netronome/nfp/bpf/verifier.c const struct bpf_reg_state *reg, reg 350 drivers/net/ethernet/netronome/nfp/bpf/verifier.c if (reg->frameno != env->cur_state->curframe) reg 353 drivers/net/ethernet/netronome/nfp/bpf/verifier.c if (!tnum_is_const(reg->var_off)) { reg 362 drivers/net/ethernet/netronome/nfp/bpf/verifier.c new_off = reg->off + reg->var_off.value; reg 418 drivers/net/ethernet/netronome/nfp/bpf/verifier.c const struct bpf_reg_state *reg, reg 426 drivers/net/ethernet/netronome/nfp/bpf/verifier.c if (!tnum_is_const(reg->var_off)) { reg 431 drivers/net/ethernet/netronome/nfp/bpf/verifier.c off = reg->var_off.value + meta->insn.off + reg->off; reg 433 drivers/net/ethernet/netronome/nfp/bpf/verifier.c offmap = map_to_offmap(reg->map_ptr); reg 454 drivers/net/ethernet/netronome/nfp/bpf/verifier.c const struct bpf_reg_state *reg = cur_regs(env) + reg_no; reg 457 drivers/net/ethernet/netronome/nfp/bpf/verifier.c if (reg->type != PTR_TO_CTX && reg 458 drivers/net/ethernet/netronome/nfp/bpf/verifier.c reg->type != PTR_TO_STACK && reg 459 drivers/net/ethernet/netronome/nfp/bpf/verifier.c reg->type != PTR_TO_MAP_VALUE && reg 460 drivers/net/ethernet/netronome/nfp/bpf/verifier.c reg->type != PTR_TO_PACKET) { reg 461 drivers/net/ethernet/netronome/nfp/bpf/verifier.c pr_vlog(env, "unsupported ptr type: %d\n", reg->type); reg 465 drivers/net/ethernet/netronome/nfp/bpf/verifier.c if (reg->type == PTR_TO_STACK) { reg 466 drivers/net/ethernet/netronome/nfp/bpf/verifier.c err = nfp_bpf_check_stack_access(nfp_prog, meta, reg, env); reg 471 drivers/net/ethernet/netronome/nfp/bpf/verifier.c if (reg->type == PTR_TO_MAP_VALUE) { reg 473 drivers/net/ethernet/netronome/nfp/bpf/verifier.c err = nfp_bpf_map_mark_used(env, meta, reg, reg 483 drivers/net/ethernet/netronome/nfp/bpf/verifier.c err = nfp_bpf_map_mark_used(env, meta, reg, reg 490 drivers/net/ethernet/netronome/nfp/bpf/verifier.c if (meta->ptr.type != NOT_INIT && meta->ptr.type != reg->type) { reg 492 drivers/net/ethernet/netronome/nfp/bpf/verifier.c meta->ptr.type, reg->type); reg 496 drivers/net/ethernet/netronome/nfp/bpf/verifier.c meta->ptr = *reg; reg 505 drivers/net/ethernet/netronome/nfp/bpf/verifier.c const struct bpf_reg_state *reg = cur_regs(env) + meta->insn.dst_reg; reg 507 drivers/net/ethernet/netronome/nfp/bpf/verifier.c if (reg->type == PTR_TO_CTX) { reg 25 drivers/net/ethernet/netronome/nfp/nfp_asm.c static bool unreg_is_imm(u16 reg) reg 27 drivers/net/ethernet/netronome/nfp/nfp_asm.c return (reg & UR_REG_IMM) == UR_REG_IMM; reg 73 drivers/net/ethernet/netronome/nfp/nfp_asm.c u16 reg; reg 78 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg = FIELD_GET(OP_IMMED_A_SRC, instr); reg 79 drivers/net/ethernet/netronome/nfp/nfp_asm.c if (!unreg_is_imm(reg)) reg 80 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg = FIELD_GET(OP_IMMED_B_SRC, instr); reg 82 drivers/net/ethernet/netronome/nfp/nfp_asm.c return (reg & 0xff) | FIELD_GET(OP_IMMED_IMM, instr) << 8; reg 113 drivers/net/ethernet/netronome/nfp/nfp_asm.c static u16 nfp_swreg_to_unreg(swreg reg, bool is_dst) reg 116 drivers/net/ethernet/netronome/nfp/nfp_asm.c u16 val = swreg_value(reg); reg 118 drivers/net/ethernet/netronome/nfp/nfp_asm.c switch (swreg_type(reg)) { reg 128 drivers/net/ethernet/netronome/nfp/nfp_asm.c lm_id = swreg_lm_idx(reg); reg 130 drivers/net/ethernet/netronome/nfp/nfp_asm.c switch (swreg_lm_mode(reg)) { reg 151 drivers/net/ethernet/netronome/nfp/nfp_asm.c swreg_lm_mode(reg)); reg 164 drivers/net/ethernet/netronome/nfp/nfp_asm.c pr_err("unrecognized reg encoding %08x\n", reg); reg 169 drivers/net/ethernet/netronome/nfp/nfp_asm.c struct nfp_insn_ur_regs *reg) reg 171 drivers/net/ethernet/netronome/nfp/nfp_asm.c memset(reg, 0, sizeof(*reg)); reg 178 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->dst_ab = ALU_DST_B; reg 180 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->wr_both = true; reg 181 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->dst = nfp_swreg_to_unreg(dst, true); reg 190 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->areg = nfp_swreg_to_unreg(rreg, false); reg 191 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->breg = nfp_swreg_to_unreg(lreg, false); reg 192 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->swap = true; reg 194 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->areg = nfp_swreg_to_unreg(lreg, false); reg 195 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->breg = nfp_swreg_to_unreg(rreg, false); reg 198 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->dst_lmextn = swreg_lmextn(dst); reg 199 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->src_lmextn = swreg_lmextn(lreg) | swreg_lmextn(rreg); reg 204 drivers/net/ethernet/netronome/nfp/nfp_asm.c static u16 nfp_swreg_to_rereg(swreg reg, bool is_dst, bool has_imm8, bool *i8) reg 206 drivers/net/ethernet/netronome/nfp/nfp_asm.c u16 val = swreg_value(reg); reg 209 drivers/net/ethernet/netronome/nfp/nfp_asm.c switch (swreg_type(reg)) { reg 217 drivers/net/ethernet/netronome/nfp/nfp_asm.c lm_id = swreg_lm_idx(reg); reg 219 drivers/net/ethernet/netronome/nfp/nfp_asm.c if (swreg_lm_mode(reg) != NN_LM_MOD_NONE) { reg 221 drivers/net/ethernet/netronome/nfp/nfp_asm.c swreg_lm_mode(reg)); reg 250 drivers/net/ethernet/netronome/nfp/nfp_asm.c struct nfp_insn_re_regs *reg, bool has_imm8) reg 252 drivers/net/ethernet/netronome/nfp/nfp_asm.c memset(reg, 0, sizeof(*reg)); reg 259 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->dst_ab = ALU_DST_B; reg 261 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->wr_both = true; reg 262 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->dst = nfp_swreg_to_rereg(dst, true, false, NULL); reg 271 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->areg = nfp_swreg_to_rereg(rreg, false, has_imm8, ®->i8); reg 272 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->breg = nfp_swreg_to_rereg(lreg, false, has_imm8, ®->i8); reg 273 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->swap = true; reg 275 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->areg = nfp_swreg_to_rereg(lreg, false, has_imm8, ®->i8); reg 276 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->breg = nfp_swreg_to_rereg(rreg, false, has_imm8, ®->i8); reg 279 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->dst_lmextn = swreg_lmextn(dst); reg 280 drivers/net/ethernet/netronome/nfp/nfp_asm.c reg->src_lmextn = swreg_lmextn(lreg) | swreg_lmextn(rreg); reg 339 drivers/net/ethernet/netronome/nfp/nfp_asm.h static inline u32 swreg_raw(swreg reg) reg 341 drivers/net/ethernet/netronome/nfp/nfp_asm.h return (__force u32)reg; reg 344 drivers/net/ethernet/netronome/nfp/nfp_asm.h static inline enum nfp_bpf_reg_type swreg_type(swreg reg) reg 346 drivers/net/ethernet/netronome/nfp/nfp_asm.h return FIELD_GET(NN_REG_TYPE, swreg_raw(reg)); reg 349 drivers/net/ethernet/netronome/nfp/nfp_asm.h static inline u16 swreg_value(swreg reg) reg 351 drivers/net/ethernet/netronome/nfp/nfp_asm.h return FIELD_GET(NN_REG_VAL, swreg_raw(reg)); reg 354 drivers/net/ethernet/netronome/nfp/nfp_asm.h static inline bool swreg_lm_idx(swreg reg) reg 356 drivers/net/ethernet/netronome/nfp/nfp_asm.h return FIELD_GET(NN_REG_LM_IDX_LO, swreg_raw(reg)); reg 359 drivers/net/ethernet/netronome/nfp/nfp_asm.h static inline bool swreg_lmextn(swreg reg) reg 361 drivers/net/ethernet/netronome/nfp/nfp_asm.h return FIELD_GET(NN_REG_LM_IDX_HI, swreg_raw(reg)); reg 364 drivers/net/ethernet/netronome/nfp/nfp_asm.h static inline enum nfp_bpf_lm_mode swreg_lm_mode(swreg reg) reg 366 drivers/net/ethernet/netronome/nfp/nfp_asm.h return FIELD_GET(NN_REG_LM_MOD, swreg_raw(reg)); reg 391 drivers/net/ethernet/netronome/nfp/nfp_asm.h struct nfp_insn_ur_regs *reg); reg 393 drivers/net/ethernet/netronome/nfp/nfp_asm.h struct nfp_insn_re_regs *reg, bool has_imm8); reg 59 drivers/net/ethernet/netronome/nfp/nfp_net_common.c u32 reg; reg 61 drivers/net/ethernet/netronome/nfp/nfp_net_common.c reg = readl(ctrl_bar + NFP_NET_CFG_VERSION); reg 62 drivers/net/ethernet/netronome/nfp/nfp_net_common.c put_unaligned_le32(reg, fw_ver); reg 123 drivers/net/ethernet/netronome/nfp/nfp_net_common.c u32 reg; reg 125 drivers/net/ethernet/netronome/nfp/nfp_net_common.c reg = nn_readl(nn, NFP_NET_CFG_UPDATE); reg 126 drivers/net/ethernet/netronome/nfp/nfp_net_common.c if (reg == 0) reg 128 drivers/net/ethernet/netronome/nfp/nfp_net_common.c if (reg & NFP_NET_CFG_UPDATE_ERR) { reg 130 drivers/net/ethernet/netronome/nfp/nfp_net_common.c reg, nn->reconfig_in_progress_update, reg 135 drivers/net/ethernet/netronome/nfp/nfp_net_common.c reg, nn->reconfig_in_progress_update, reg 3926 drivers/net/ethernet/netronome/nfp/nfp_net_common.c u32 reg; reg 3929 drivers/net/ethernet/netronome/nfp/nfp_net_common.c reg = nn_readl(nn, NFP_NET_CFG_RSS_CAP); reg 3930 drivers/net/ethernet/netronome/nfp/nfp_net_common.c rss_cap_hfunc = FIELD_GET(NFP_NET_CFG_RSS_CAP_HFUNC, reg); reg 4082 drivers/net/ethernet/netronome/nfp/nfp_net_common.c u32 reg; reg 4084 drivers/net/ethernet/netronome/nfp/nfp_net_common.c reg = nn_readl(nn, NFP_NET_CFG_RX_OFFSET); reg 4085 drivers/net/ethernet/netronome/nfp/nfp_net_common.c if (reg > NFP_NET_MAX_PREPEND) { reg 4086 drivers/net/ethernet/netronome/nfp/nfp_net_common.c nn_err(nn, "Invalid rx offset: %d\n", reg); reg 4089 drivers/net/ethernet/netronome/nfp/nfp_net_common.c nn->dp.rx_offset = reg; reg 1251 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c u32 reg; reg 1259 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c pci_read_config_dword(pdev, pos + 4, ®); reg 1260 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c put_unaligned_be16(reg >> 16, serial + 4); reg 1261 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c pci_read_config_dword(pdev, pos + 8, ®); reg 1262 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c put_unaligned_be32(reg, serial); reg 1271 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c u32 reg; reg 1279 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c pci_read_config_dword(pdev, pos + 4, ®); reg 1281 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c return reg & 0xffff; reg 124 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cpplib.c u32 reg; reg 128 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cpplib.c ®); reg 132 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cpplib.c *model = reg & NFP_PL_DEVICE_MODEL_MASK; reg 230 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c u64 nsp_status, reg; reg 237 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c err = nfp_cpp_readq(cpp, nsp_cpp, nsp_status, ®); reg 241 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c if (FIELD_GET(NSP_STATUS_MAGIC, reg) != NSP_MAGIC) { reg 246 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c state->ver.major = FIELD_GET(NSP_STATUS_MAJOR, reg); reg 247 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c state->ver.minor = FIELD_GET(NSP_STATUS_MINOR, reg); reg 260 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c if (reg & NSP_STATUS_BUSY) { reg 320 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c nfp_nsp_wait_reg(struct nfp_cpp *cpp, u64 *reg, u32 nsp_cpp, u64 addr, reg 329 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c err = nfp_cpp_readq(cpp, nsp_cpp, addr, reg); reg 333 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c if ((*reg & mask) == val) reg 361 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c u64 reg, ret_val, nsp_base, nsp_buffer, nsp_status, nsp_command; reg 389 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c err = nfp_nsp_wait_reg(cpp, ®, nsp_cpp, nsp_command, reg 398 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c err = nfp_nsp_wait_reg(cpp, ®, nsp_cpp, nsp_status, NSP_STATUS_BUSY, reg 411 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c err = FIELD_GET(NSP_STATUS_RESULT, reg); reg 441 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c u64 reg, cpp_buf; reg 448 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c ®); reg 452 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c cpp_id = FIELD_GET(NSP_DFLT_BUFFER_CPP, reg) << 8; reg 453 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c cpp_buf = FIELD_GET(NSP_DFLT_BUFFER_ADDRESS, reg); reg 629 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c u64 reg; reg 636 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c ®); reg 639 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c sg_ok = reg & BIT_ULL(arg->arg.code - 1); reg 661 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c u64 reg; reg 673 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c ®); reg 682 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c def_size = FIELD_GET(NSP_DFLT_BUFFER_SIZE_MB, reg) * SZ_1M + reg 683 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c FIELD_GET(NSP_DFLT_BUFFER_SIZE_4KB, reg) * SZ_4K; reg 684 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c dma_order = FIELD_GET(NSP_DFLT_BUFFER_DMA_CHUNK_ORDER, reg); reg 392 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c u64 reg; reg 401 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c reg = le64_to_cpu(entries[idx].state); reg 402 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c if (enable != FIELD_GET(NSP_ETH_CTRL_ENABLED, reg)) { reg 403 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c reg = le64_to_cpu(entries[idx].control); reg 404 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c reg &= ~NSP_ETH_CTRL_ENABLED; reg 405 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c reg |= FIELD_PREP(NSP_ETH_CTRL_ENABLED, enable); reg 406 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c entries[idx].control = cpu_to_le64(reg); reg 431 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c u64 reg; reg 448 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c reg = le64_to_cpu(entries[idx].state); reg 449 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c if (configed != FIELD_GET(NSP_ETH_STATE_CONFIGURED, reg)) { reg 450 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c reg = le64_to_cpu(entries[idx].control); reg 451 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c reg &= ~NSP_ETH_CTRL_CONFIGURED; reg 452 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c reg |= FIELD_PREP(NSP_ETH_CTRL_CONFIGURED, configed); reg 453 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c entries[idx].control = cpu_to_le64(reg); reg 468 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c u64 reg; reg 480 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c reg = le64_to_cpu(entries[idx].raw[raw_idx]); reg 481 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c if (val == (reg & mask) >> shift) reg 484 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c reg &= ~mask; reg 485 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c reg |= (val << shift) & mask; reg 486 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c entries[idx].raw[raw_idx] = cpu_to_le64(reg); reg 1095 drivers/net/ethernet/ni/nixge.c static int nixge_mdio_read(struct mii_bus *bus, int phy_id, int reg) reg 1102 drivers/net/ethernet/ni/nixge.c if (reg & MII_ADDR_C45) { reg 1103 drivers/net/ethernet/ni/nixge.c device = (reg >> 16) & 0x1f; reg 1105 drivers/net/ethernet/ni/nixge.c nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff); reg 1123 drivers/net/ethernet/ni/nixge.c device = reg & 0x1f; reg 1144 drivers/net/ethernet/ni/nixge.c static int nixge_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val) reg 1151 drivers/net/ethernet/ni/nixge.c if (reg & MII_ADDR_C45) { reg 1152 drivers/net/ethernet/ni/nixge.c device = (reg >> 16) & 0x1f; reg 1154 drivers/net/ethernet/ni/nixge.c nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff); reg 1179 drivers/net/ethernet/ni/nixge.c device = reg & 0x1f; reg 693 drivers/net/ethernet/nvidia/forcedeth.c __u32 reg; reg 1146 drivers/net/ethernet/nvidia/forcedeth.c u32 reg; reg 1151 drivers/net/ethernet/nvidia/forcedeth.c reg = readl(base + NvRegMIIControl); reg 1152 drivers/net/ethernet/nvidia/forcedeth.c if (reg & NVREG_MIICTL_INUSE) { reg 1157 drivers/net/ethernet/nvidia/forcedeth.c reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg; reg 1160 drivers/net/ethernet/nvidia/forcedeth.c reg |= NVREG_MIICTL_WRITE; reg 1162 drivers/net/ethernet/nvidia/forcedeth.c writel(reg, base + NvRegMIIControl); reg 1206 drivers/net/ethernet/nvidia/forcedeth.c int reg; reg 1220 drivers/net/ethernet/nvidia/forcedeth.c if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init)) reg 1229 drivers/net/ethernet/nvidia/forcedeth.c u32 reg; reg 1242 drivers/net/ethernet/nvidia/forcedeth.c reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); reg 1243 drivers/net/ethernet/nvidia/forcedeth.c reg |= PHY_REALTEK_INIT9; reg 1244 drivers/net/ethernet/nvidia/forcedeth.c if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) reg 1249 drivers/net/ethernet/nvidia/forcedeth.c reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); reg 1250 drivers/net/ethernet/nvidia/forcedeth.c if (!(reg & PHY_REALTEK_INIT11)) { reg 1251 drivers/net/ethernet/nvidia/forcedeth.c reg |= PHY_REALTEK_INIT11; reg 1252 drivers/net/ethernet/nvidia/forcedeth.c if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) reg 1392 drivers/net/ethernet/nvidia/forcedeth.c u32 mii_status, mii_control, mii_control_1000, reg; reg 1396 drivers/net/ethernet/nvidia/forcedeth.c reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); reg 1397 drivers/net/ethernet/nvidia/forcedeth.c reg &= ~PHY_MARVELL_E3016_INITMASK; reg 1398 drivers/net/ethernet/nvidia/forcedeth.c if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { reg 1429 drivers/net/ethernet/nvidia/forcedeth.c reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); reg 1430 drivers/net/ethernet/nvidia/forcedeth.c reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL | reg 1433 drivers/net/ethernet/nvidia/forcedeth.c if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { reg 1519 drivers/net/ethernet/nvidia/forcedeth.c mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); reg 2101 drivers/net/ethernet/nvidia/forcedeth.c u32 reg; reg 2105 drivers/net/ethernet/nvidia/forcedeth.c reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK; reg 2107 drivers/net/ethernet/nvidia/forcedeth.c reg |= low & NVREG_SLOTTIME_MASK; reg 2116 drivers/net/ethernet/nvidia/forcedeth.c writel(reg, base + NvRegSlotTime); reg 5013 drivers/net/ethernet/nvidia/forcedeth.c orig_read = readl(base + nv_registers_test[i].reg); reg 5018 drivers/net/ethernet/nvidia/forcedeth.c writel(orig_read, base + nv_registers_test[i].reg); reg 5020 drivers/net/ethernet/nvidia/forcedeth.c new_read = readl(base + nv_registers_test[i].reg); reg 5027 drivers/net/ethernet/nvidia/forcedeth.c writel(orig_read, base + nv_registers_test[i].reg); reg 5029 drivers/net/ethernet/nvidia/forcedeth.c } while (nv_registers_test[++i].reg != 0); reg 366 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h struct pch_gbe_regs __iomem *reg; reg 633 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg, reg 193 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_ethtool.c *regs_buff++ = ioread32(&hw->reg->INT_ST + i); reg 101 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg); reg 102 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg, reg 267 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD); reg 281 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c adr1a = ioread32(&hw->reg->mac_adr[0].high); reg 282 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c adr1b = ioread32(&hw->reg->mac_adr[0].low); reg 300 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c static void pch_gbe_wait_clr_bit(void *reg, u32 bit) reg 306 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c while ((ioread32(reg) & bit) && --tmp) reg 333 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c adrmask = ioread32(&hw->reg->ADDR_MASK); reg 334 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK); reg 336 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); reg 338 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(mar_high, &hw->reg->mac_adr[index].high); reg 339 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(mar_low, &hw->reg->mac_adr[index].low); reg 341 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK); reg 343 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); reg 354 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET); reg 355 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE); reg 356 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST); reg 366 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c rctl = ioread32(&hw->reg->MAC_RX_EN); reg 367 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN); reg 374 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c rctl = ioread32(&hw->reg->MAC_RX_EN); reg 375 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32((rctl | PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN); reg 392 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(0, &hw->reg->mac_adr[i].high); reg 393 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(0, &hw->reg->mac_adr[i].low); reg 395 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(0xFFFE, &hw->reg->ADDR_MASK); reg 397 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); reg 415 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c rx_fctrl = ioread32(&hw->reg->RX_FCTRL); reg 441 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(rx_fctrl, &hw->reg->RX_FCTRL); reg 444 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable); reg 459 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c wu_evt, ioread32(&hw->reg->ADDR_MASK)); reg 463 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c addr_mask = ioread32(&hw->reg->ADDR_MASK); reg 464 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK); reg 466 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY); reg 467 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(0, &hw->reg->WOL_ST); reg 468 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL); reg 469 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(0x02, &hw->reg->TCPIP_ACC); reg 470 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN); reg 472 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(0, &hw->reg->WOL_CTRL); reg 473 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(0, &hw->reg->WOL_ST); reg 488 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg, reg 499 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY)) reg 508 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) | reg 510 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c dir | data), &hw->reg->MIIM); reg 513 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c data_out = ioread32(&hw->reg->MIIM); reg 520 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg, reg 544 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1); reg 545 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(tmp2, &hw->reg->PAUSE_PKT2); reg 546 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(tmp3, &hw->reg->PAUSE_PKT3); reg 547 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4); reg 548 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5); reg 551 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ); reg 555 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c ioread32(&hw->reg->PAUSE_PKT1), reg 556 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c ioread32(&hw->reg->PAUSE_PKT2), reg 557 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c ioread32(&hw->reg->PAUSE_PKT3), reg 558 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c ioread32(&hw->reg->PAUSE_PKT4), reg 559 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c ioread32(&hw->reg->PAUSE_PKT5)); reg 653 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg) reg 658 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg, reg 670 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c int addr, int reg, int data) reg 675 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data); reg 749 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(0, &hw->reg->INT_EN); reg 750 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c ioread32(&hw->reg->INT_ST); reg 754 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c ioread32(&hw->reg->INT_EN)); reg 766 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN); reg 767 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c ioread32(&hw->reg->INT_ST); reg 769 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c ioread32(&hw->reg->INT_EN)); reg 789 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(tx_mode, &hw->reg->TX_MODE); reg 791 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c tcpip = ioread32(&hw->reg->TCPIP_ACC); reg 793 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(tcpip, &hw->reg->TCPIP_ACC); reg 813 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(tdba, &hw->reg->TX_DSC_BASE); reg 814 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(tdlen, &hw->reg->TX_DSC_SIZE); reg 815 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(tdba, &hw->reg->TX_DSC_SW_P); reg 818 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c dctrl = ioread32(&hw->reg->DMA_CTRL); reg 820 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(dctrl, &hw->reg->DMA_CTRL); reg 835 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(rx_mode, &hw->reg->RX_MODE); reg 837 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c tcpip = ioread32(&hw->reg->TCPIP_ACC); reg 841 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(tcpip, &hw->reg->TCPIP_ACC); reg 863 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c rxdma = ioread32(&hw->reg->DMA_CTRL); reg 865 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(rxdma, &hw->reg->DMA_CTRL); reg 869 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c ioread32(&hw->reg->MAC_RX_EN), reg 870 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c ioread32(&hw->reg->DMA_CTRL)); reg 876 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(rdba, &hw->reg->RX_DSC_BASE); reg 877 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(rdlen, &hw->reg->RX_DSC_SIZE); reg 878 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P); reg 948 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P); reg 949 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE); reg 980 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P); reg 981 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE); reg 1005 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(rgmii, &hw->reg->RGMII_CTRL); reg 1032 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(mode, &hw->reg->MODE); reg 1195 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c &hw->reg->TX_DSC_SW_P); reg 1255 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c rxdma = ioread32(&hw->reg->DMA_CTRL); reg 1257 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(rxdma, &hw->reg->DMA_CTRL); reg 1265 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c rxdma = ioread32(&hw->reg->DMA_CTRL); reg 1267 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(rxdma, &hw->reg->DMA_CTRL); reg 1287 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c int_st = ioread32(&hw->reg->INT_ST); reg 1288 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c int_st = int_st & ioread32(&hw->reg->INT_EN); reg 1300 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c int_en = ioread32(&hw->reg->INT_EN); reg 1302 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c &hw->reg->INT_EN); reg 1304 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c int_st |= ioread32(&hw->reg->INT_ST); reg 1305 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c int_st = int_st & ioread32(&hw->reg->INT_EN); reg 1319 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c int_en = ioread32(&hw->reg->INT_EN); reg 1320 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN); reg 1333 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c int_en = ioread32(&hw->reg->INT_EN); reg 1336 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(int_en, &hw->reg->INT_EN); reg 1342 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c IRQ_HANDLED, ioread32(&hw->reg->INT_EN)); reg 1410 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c &hw->reg->RX_DSC_SW_P); reg 2100 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c rctl = ioread32(&hw->reg->RX_MODE); reg 2114 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(rctl, &hw->reg->RX_MODE); reg 2132 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c adrmask = ioread32(&hw->reg->ADDR_MASK); reg 2133 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(adrmask | BIT(i), &hw->reg->ADDR_MASK); reg 2135 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); reg 2137 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(0, &hw->reg->mac_adr[i].high); reg 2138 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c iowrite32(0, &hw->reg->mac_adr[i].low); reg 2143 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c ioread32(&hw->reg->RX_MODE), mc_count); reg 2172 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c ioread32(&adapter->hw.reg->mac_adr[0].high), reg 2173 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c ioread32(&adapter->hw.reg->mac_adr[0].low)); reg 2537 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR]; reg 78 drivers/net/ethernet/pasemi/pasemi_mac.c static void write_iob_reg(unsigned int reg, unsigned int val) reg 80 drivers/net/ethernet/pasemi/pasemi_mac.c pasemi_write_iob_reg(reg, val); reg 83 drivers/net/ethernet/pasemi/pasemi_mac.c static unsigned int read_mac_reg(const struct pasemi_mac *mac, unsigned int reg) reg 85 drivers/net/ethernet/pasemi/pasemi_mac.c return pasemi_read_mac_reg(mac->dma_if, reg); reg 88 drivers/net/ethernet/pasemi/pasemi_mac.c static void write_mac_reg(const struct pasemi_mac *mac, unsigned int reg, reg 91 drivers/net/ethernet/pasemi/pasemi_mac.c pasemi_write_mac_reg(mac->dma_if, reg, val); reg 94 drivers/net/ethernet/pasemi/pasemi_mac.c static unsigned int read_dma_reg(unsigned int reg) reg 96 drivers/net/ethernet/pasemi/pasemi_mac.c return pasemi_read_dma_reg(reg); reg 99 drivers/net/ethernet/pasemi/pasemi_mac.c static void write_dma_reg(unsigned int reg, unsigned int val) reg 101 drivers/net/ethernet/pasemi/pasemi_mac.c pasemi_write_dma_reg(reg, val); reg 629 drivers/net/ethernet/pasemi/pasemi_mac.c unsigned int reg, pcnt; reg 636 drivers/net/ethernet/pasemi/pasemi_mac.c reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC; reg 639 drivers/net/ethernet/pasemi/pasemi_mac.c reg |= PAS_IOB_DMA_RXCH_RESET_TINTC; reg 641 drivers/net/ethernet/pasemi/pasemi_mac.c write_iob_reg(PAS_IOB_DMA_RXCH_RESET(mac->rx->chan.chno), reg); reg 646 drivers/net/ethernet/pasemi/pasemi_mac.c unsigned int reg, pcnt; reg 651 drivers/net/ethernet/pasemi/pasemi_mac.c reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC; reg 653 drivers/net/ethernet/pasemi/pasemi_mac.c write_iob_reg(PAS_IOB_DMA_TXCH_RESET(tx_ring(mac)->chan.chno), reg); reg 911 drivers/net/ethernet/pasemi/pasemi_mac.c unsigned int reg; reg 920 drivers/net/ethernet/pasemi/pasemi_mac.c reg = 0; reg 922 drivers/net/ethernet/pasemi/pasemi_mac.c reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; reg 924 drivers/net/ethernet/pasemi/pasemi_mac.c reg |= PAS_IOB_DMA_RXCH_RESET_DINTC; reg 928 drivers/net/ethernet/pasemi/pasemi_mac.c write_iob_reg(PAS_IOB_DMA_RXCH_RESET(chan->chno), reg); reg 952 drivers/net/ethernet/pasemi/pasemi_mac.c unsigned int reg; reg 957 drivers/net/ethernet/pasemi/pasemi_mac.c reg = 0; reg 960 drivers/net/ethernet/pasemi/pasemi_mac.c reg |= PAS_IOB_DMA_TXCH_RESET_SINTC; reg 962 drivers/net/ethernet/pasemi/pasemi_mac.c reg |= PAS_IOB_DMA_TXCH_RESET_DINTC; reg 968 drivers/net/ethernet/pasemi/pasemi_mac.c if (reg) reg 969 drivers/net/ethernet/pasemi/pasemi_mac.c write_iob_reg(PAS_IOB_DMA_TXCH_RESET(chan->chno), reg); reg 1596 drivers/net/ethernet/pasemi/pasemi_mac.c unsigned int reg; reg 1633 drivers/net/ethernet/pasemi/pasemi_mac.c reg = read_mac_reg(mac, PAS_MAC_CFG_MACCFG); reg 1634 drivers/net/ethernet/pasemi/pasemi_mac.c reg &= ~PAS_MAC_CFG_MACCFG_MAXF_M; reg 1635 drivers/net/ethernet/pasemi/pasemi_mac.c reg |= PAS_MAC_CFG_MACCFG_MAXF(new_mtu + ETH_HLEN + 4); reg 1636 drivers/net/ethernet/pasemi/pasemi_mac.c write_mac_reg(mac, PAS_MAC_CFG_MACCFG, reg); reg 87 drivers/net/ethernet/qlogic/netxen/netxen_nic.h #define NETXEN_CRB_NORMAL(reg) \ reg 88 drivers/net/ethernet/qlogic/netxen/netxen_nic.h ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST) reg 90 drivers/net/ethernet/qlogic/netxen/netxen_nic.h #define NETXEN_CRB_NORMALIZE(adapter, reg) \ reg 91 drivers/net/ethernet/qlogic/netxen/netxen_nic.h pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg)) reg 1647 drivers/net/ethernet/qlogic/netxen/netxen_nic.h int (*phy_read) (struct netxen_adapter *, u32 reg, u32 *); reg 1648 drivers/net/ethernet/qlogic/netxen/netxen_nic.h int (*phy_write) (struct netxen_adapter *, u32 reg, u32 val); reg 1687 drivers/net/ethernet/qlogic/netxen/netxen_nic.h int nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val); reg 1688 drivers/net/ethernet/qlogic/netxen/netxen_nic.h int nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val); reg 270 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c u32 cap, reg, val; reg 365 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c reg = le32_to_cpu(prsp_rds[i].host_producer_crb); reg 367 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c NETXEN_NIC_REG(reg - 0x200)); reg 376 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c reg = le32_to_cpu(prsp_sds[i].host_consumer_crb); reg 378 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c NETXEN_NIC_REG(reg - 0x200)); reg 380 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c reg = le32_to_cpu(prsp_sds[i].interrupt_crb); reg 382 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c NETXEN_NIC_REG(reg - 0x200)); reg 520 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val) reg 526 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c cmd.req.arg1 = reg; reg 543 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val) reg 549 drivers/net/ethernet/qlogic/netxen/netxen_nic_ctx.c cmd.req.arg1 = reg; reg 703 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h #define P3_LINK_SPEED_VAL(pcifn, reg) \ reg 704 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h (((reg) >> (8 * ((pcifn) & 0x3))) & P3_LINK_SPEED_MASK) reg 707 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h #define NETXEN_CAM_RAM(reg) (NETXEN_CAM_RAM_BASE + (reg)) reg 884 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h #define NETXEN_PCIX_PH_REG(reg) (NETXEN_CRB_PCIE + (reg)) reg 885 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h #define NETXEN_PCIX_PS_REG(reg) (NETXEN_CRB_PCIX_MD + (reg)) reg 887 drivers/net/ethernet/qlogic/netxen/netxen_nic_hdr.h #define NETXEN_PCIE_REG(reg) (NETXEN_CRB_PCIE + (reg)) reg 360 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c __u32 reg = 0x0200; reg 373 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c reg = (0x20 << port); reg 375 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c NXWR32(adapter, NETXEN_NIU_FRAME_COUNT_SELECT, reg); reg 384 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c reg = NXRD32(adapter, reg 388 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c reg = (reg | 0x2000UL); reg 390 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c reg = (reg & ~0x2000UL); reg 393 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c reg = (reg | 0x1000UL); reg 395 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c reg = (reg & ~0x1000UL); reg 398 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg); reg 77 drivers/net/ethernet/qlogic/qed/qed_cxt.c #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET reg 161 drivers/net/ethernet/qlogic/qed/qed_cxt.c u32 reg; reg 1217 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT); reg 1218 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT); reg 1219 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE); reg 1221 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT); reg 1222 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT); reg 1223 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE); reg 1225 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT); reg 1226 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT); reg 1227 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE); reg 1229 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT); reg 1230 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT); reg 1231 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE); reg 1233 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT); reg 1234 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT); reg 1235 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE); reg 1237 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT); reg 1238 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT); reg 1239 drivers/net/ethernet/qlogic/qed/qed_cxt.c clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE); reg 1603 drivers/net/ethernet/qlogic/qed/qed_cxt.c ilt_clients[i].first.reg, reg 1606 drivers/net/ethernet/qlogic/qed/qed_cxt.c ilt_clients[i].last.reg, ilt_clients[i].last.val); reg 1608 drivers/net/ethernet/qlogic/qed/qed_cxt.c ilt_clients[i].p_size.reg, reg 2708 drivers/net/ethernet/qlogic/qed/qed_debug.c const struct dbg_dump_reg *reg = reg 2714 drivers/net/ethernet/qlogic/qed/qed_debug.c addr = GET_FIELD(reg->data, DBG_DUMP_REG_ADDRESS); reg 2715 drivers/net/ethernet/qlogic/qed/qed_debug.c len = GET_FIELD(reg->data, DBG_DUMP_REG_LENGTH); reg 2716 drivers/net/ethernet/qlogic/qed/qed_debug.c wide_bus = GET_FIELD(reg->data, DBG_DUMP_REG_WIDE_BUS); reg 4202 drivers/net/ethernet/qlogic/qed/qed_debug.c const struct dbg_idle_chk_cond_reg *reg = &cond_regs[reg_id]; reg 4211 drivers/net/ethernet/qlogic/qed/qed_debug.c reg->entry_size; reg 4217 drivers/net/ethernet/qlogic/qed/qed_debug.c reg_hdr->start_entry = reg->start_entry; reg 4218 drivers/net/ethernet/qlogic/qed/qed_debug.c reg_hdr->size = reg->entry_size; reg 4221 drivers/net/ethernet/qlogic/qed/qed_debug.c reg->num_entries > 1 || reg->start_entry > 0 ? 1 : 0); reg 4232 drivers/net/ethernet/qlogic/qed/qed_debug.c const struct dbg_idle_chk_info_reg *reg = &info_regs[reg_id]; reg 4237 drivers/net/ethernet/qlogic/qed/qed_debug.c offset += IDLE_CHK_RESULT_REG_HDR_DWORDS + reg->size; reg 4241 drivers/net/ethernet/qlogic/qed/qed_debug.c block_id = GET_FIELD(reg->data, DBG_IDLE_CHK_INFO_REG_BLOCK_ID); reg 4257 drivers/net/ethernet/qlogic/qed/qed_debug.c eval_mode = GET_FIELD(reg->mode.data, reg 4261 drivers/net/ethernet/qlogic/qed/qed_debug.c GET_FIELD(reg->mode.data, reg 4271 drivers/net/ethernet/qlogic/qed/qed_debug.c addr = GET_FIELD(reg->data, reg 4273 drivers/net/ethernet/qlogic/qed/qed_debug.c wide_bus = GET_FIELD(reg->data, reg 4280 drivers/net/ethernet/qlogic/qed/qed_debug.c reg_hdr->size = reg->size; reg 4291 drivers/net/ethernet/qlogic/qed/qed_debug.c reg->size, wide_bus, reg 4378 drivers/net/ethernet/qlogic/qed/qed_debug.c const struct dbg_idle_chk_cond_reg *reg = reg 4386 drivers/net/ethernet/qlogic/qed/qed_debug.c addr = GET_FIELD(reg->data, reg 4389 drivers/net/ethernet/qlogic/qed/qed_debug.c GET_FIELD(reg->data, reg 4391 drivers/net/ethernet/qlogic/qed/qed_debug.c if (reg->num_entries > 1 || reg 4392 drivers/net/ethernet/qlogic/qed/qed_debug.c reg->start_entry > 0) { reg 4394 drivers/net/ethernet/qlogic/qed/qed_debug.c reg->entry_size > 1 ? reg 4395 drivers/net/ethernet/qlogic/qed/qed_debug.c roundup_pow_of_two(reg->entry_size) : reg 4397 drivers/net/ethernet/qlogic/qed/qed_debug.c addr += (reg->start_entry + entry_id) * reg 4402 drivers/net/ethernet/qlogic/qed/qed_debug.c if (next_reg_offset + reg->entry_size >= reg 4414 drivers/net/ethernet/qlogic/qed/qed_debug.c reg->entry_size, reg 1707 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg; reg 186 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _PQ_VALID, 1); \ reg 187 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _RL_VALID, \ reg 189 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _VP_PQ_ID, \ reg 191 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _RL_ID, rl_id); \ reg 192 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _VOQ, ext_voq); \ reg 193 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c SET_FIELD(__map.reg, \ reg 457 drivers/net/ethernet/qlogic/qed/qed_vf.c u32 reg; reg 466 drivers/net/ethernet/qlogic/qed/qed_vf.c reg = PXP_VF_BAR0_ME_OPAQUE_ADDRESS; reg 467 drivers/net/ethernet/qlogic/qed/qed_vf.c p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, reg); reg 469 drivers/net/ethernet/qlogic/qed/qed_vf.c reg = PXP_VF_BAR0_ME_CONCRETE_ADDRESS; reg 470 drivers/net/ethernet/qlogic/qed/qed_vf.c p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, reg); reg 176 drivers/net/ethernet/qlogic/qla3xxx.c static u32 ql_read_common_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg) reg 182 drivers/net/ethernet/qlogic/qla3xxx.c value = readl(reg); reg 188 drivers/net/ethernet/qlogic/qla3xxx.c static u32 ql_read_common_reg(struct ql3_adapter *qdev, u32 __iomem *reg) reg 190 drivers/net/ethernet/qlogic/qla3xxx.c return readl(reg); reg 193 drivers/net/ethernet/qlogic/qla3xxx.c static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg) reg 202 drivers/net/ethernet/qlogic/qla3xxx.c value = readl(reg); reg 208 drivers/net/ethernet/qlogic/qla3xxx.c static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg) reg 212 drivers/net/ethernet/qlogic/qla3xxx.c return readl(reg); reg 216 drivers/net/ethernet/qlogic/qla3xxx.c u32 __iomem *reg, u32 value) reg 221 drivers/net/ethernet/qlogic/qla3xxx.c writel(value, reg); reg 222 drivers/net/ethernet/qlogic/qla3xxx.c readl(reg); reg 227 drivers/net/ethernet/qlogic/qla3xxx.c u32 __iomem *reg, u32 value) reg 229 drivers/net/ethernet/qlogic/qla3xxx.c writel(value, reg); reg 230 drivers/net/ethernet/qlogic/qla3xxx.c readl(reg); reg 234 drivers/net/ethernet/qlogic/qla3xxx.c u32 __iomem *reg, u32 value) reg 236 drivers/net/ethernet/qlogic/qla3xxx.c writel(value, reg); reg 237 drivers/net/ethernet/qlogic/qla3xxx.c readl(reg); reg 242 drivers/net/ethernet/qlogic/qla3xxx.c u32 __iomem *reg, u32 value) reg 246 drivers/net/ethernet/qlogic/qla3xxx.c writel(value, reg); reg 247 drivers/net/ethernet/qlogic/qla3xxx.c readl(reg); reg 254 drivers/net/ethernet/qlogic/qla3xxx.c u32 __iomem *reg, u32 value) reg 258 drivers/net/ethernet/qlogic/qla3xxx.c writel(value, reg); reg 259 drivers/net/ethernet/qlogic/qla3xxx.c readl(reg); reg 266 drivers/net/ethernet/qlogic/qla3xxx.c u32 __iomem *reg, u32 value) reg 270 drivers/net/ethernet/qlogic/qla3xxx.c writel(value, reg); reg 271 drivers/net/ethernet/qlogic/qla3xxx.c readl(reg); reg 775 drivers/net/ethernet/qlogic/qla3xxx.c u16 reg; reg 778 drivers/net/ethernet/qlogic/qla3xxx.c ql_mii_read_reg(qdev, PETBI_TBI_CTRL, ®); reg 779 drivers/net/ethernet/qlogic/qla3xxx.c reg |= PETBI_TBI_AUTO_SENSE; reg 780 drivers/net/ethernet/qlogic/qla3xxx.c ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg); reg 799 drivers/net/ethernet/qlogic/qla3xxx.c u16 reg; reg 802 drivers/net/ethernet/qlogic/qla3xxx.c ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, ®, reg 804 drivers/net/ethernet/qlogic/qla3xxx.c reg |= PETBI_TBI_AUTO_SENSE; reg 805 drivers/net/ethernet/qlogic/qla3xxx.c ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg, reg 832 drivers/net/ethernet/qlogic/qla3xxx.c u16 reg; reg 834 drivers/net/ethernet/qlogic/qla3xxx.c if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, ®) < 0) reg 837 drivers/net/ethernet/qlogic/qla3xxx.c return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE; reg 909 drivers/net/ethernet/qlogic/qla3xxx.c u16 reg; reg 913 drivers/net/ethernet/qlogic/qla3xxx.c if (ql_mii_read_reg(qdev, 0x1A, ®) < 0) reg 916 drivers/net/ethernet/qlogic/qla3xxx.c reg = (reg >> 8) & 3; reg 920 drivers/net/ethernet/qlogic/qla3xxx.c if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0) reg 923 drivers/net/ethernet/qlogic/qla3xxx.c reg = (((reg & 0x18) >> 3) & 3); reg 926 drivers/net/ethernet/qlogic/qla3xxx.c switch (reg) { reg 940 drivers/net/ethernet/qlogic/qla3xxx.c u16 reg; reg 944 drivers/net/ethernet/qlogic/qla3xxx.c if (ql_mii_read_reg(qdev, 0x1A, ®)) reg 947 drivers/net/ethernet/qlogic/qla3xxx.c return ((reg & 0x0080) && (reg & 0x1000)) != 0; reg 951 drivers/net/ethernet/qlogic/qla3xxx.c if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0) reg 953 drivers/net/ethernet/qlogic/qla3xxx.c return (reg & PHY_AUX_DUPLEX_STAT) != 0; reg 960 drivers/net/ethernet/qlogic/qla3xxx.c u16 reg; reg 962 drivers/net/ethernet/qlogic/qla3xxx.c if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, ®) < 0) reg 965 drivers/net/ethernet/qlogic/qla3xxx.c return (reg & PHY_NEG_PAUSE) != 0; reg 1158 drivers/net/ethernet/qlogic/qla3xxx.c u16 reg; reg 1159 drivers/net/ethernet/qlogic/qla3xxx.c ql_mii_read_reg(qdev, 0x00, ®); reg 1160 drivers/net/ethernet/qlogic/qla3xxx.c return (reg & 0x1000) != 0; reg 1331 drivers/net/ethernet/qlogic/qla3xxx.c u16 reg; reg 1351 drivers/net/ethernet/qlogic/qla3xxx.c ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, ®, reg 1353 drivers/net/ethernet/qlogic/qla3xxx.c reg &= ~PHY_GIG_ALL_PARAMS; reg 1357 drivers/net/ethernet/qlogic/qla3xxx.c reg |= PHY_GIG_ADV_1000F; reg 1359 drivers/net/ethernet/qlogic/qla3xxx.c reg |= PHY_GIG_ADV_1000H; reg 1362 drivers/net/ethernet/qlogic/qla3xxx.c ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg, reg 1366 drivers/net/ethernet/qlogic/qla3xxx.c ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, ®, reg 1368 drivers/net/ethernet/qlogic/qla3xxx.c reg &= ~PHY_NEG_ALL_PARAMS; reg 1371 drivers/net/ethernet/qlogic/qla3xxx.c reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE; reg 1375 drivers/net/ethernet/qlogic/qla3xxx.c reg |= PHY_NEG_ADV_100F; reg 1378 drivers/net/ethernet/qlogic/qla3xxx.c reg |= PHY_NEG_ADV_10F; reg 1383 drivers/net/ethernet/qlogic/qla3xxx.c reg |= PHY_NEG_ADV_100H; reg 1386 drivers/net/ethernet/qlogic/qla3xxx.c reg |= PHY_NEG_ADV_10H; reg 1390 drivers/net/ethernet/qlogic/qla3xxx.c reg |= 1; reg 1392 drivers/net/ethernet/qlogic/qla3xxx.c ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg, reg 1395 drivers/net/ethernet/qlogic/qla3xxx.c ql_mii_read_reg_ex(qdev, CONTROL_REG, ®, PHYAddr[qdev->mac_index]); reg 1398 drivers/net/ethernet/qlogic/qla3xxx.c reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG, reg 1614 drivers/net/ethernet/qlogic/qla3xxx.c u32 reg; reg 1628 drivers/net/ethernet/qlogic/qla3xxx.c reg = MAC_MII_CONTROL_CLK_SEL_DIV28; reg 1631 drivers/net/ethernet/qlogic/qla3xxx.c reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16)); reg 1765 drivers/net/ethernet/qlogic/qla3xxx.c u32 reg; reg 1767 drivers/net/ethernet/qlogic/qla3xxx.c reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg); reg 1769 drivers/net/ethernet/qlogic/qla3xxx.c reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg); reg 1772 drivers/net/ethernet/qlogic/qla3xxx.c pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2; reg 1773 drivers/net/ethernet/qlogic/qla3xxx.c pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1; reg 348 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h #define QLCNIC_MBX_RSP(reg) LSW(reg) reg 349 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h #define QLCNIC_MBX_NUM_REGS(reg) (MSW(reg) & 0x1FF) reg 350 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h #define QLCNIC_MBX_STATUS(reg) (((reg) >> 25) & 0x7F) reg 539 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 reg, reg1, reg2, i, j, owner, class; reg 546 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c reg = reg1; reg 549 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3); reg 553 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c reg = reg2; reg 566 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c reg = reg1; reg 1437 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 val = 0, val1 = 0, reg = 0; reg 1449 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c reg = QLC_83XX_PORT0_THRESHOLD; reg 1453 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c reg = QLC_83XX_PORT1_THRESHOLD; reg 1456 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRD32(adapter, reg + (i * 0x4), &err); reg 1468 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c reg = QLC_83XX_PORT0_TC_MC_REG; reg 1472 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c reg = QLC_83XX_PORT1_TC_MC_REG; reg 1475 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRD32(adapter, reg + (i * 0x4), &err); reg 1487 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c reg = QLC_83XX_PORT0_TC_STATS; reg 1491 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c reg = QLC_83XX_PORT1_TC_STATS; reg 1494 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRD32(adapter, reg, &err); reg 1498 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c QLCWR32(adapter, reg, (val | (i << 29))); reg 1499 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c val = QLCRD32(adapter, reg, &err); reg 1521 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 reg = 0, i, j; reg 1534 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c reg = QLC_83XX_PORT0_THRESHOLD; reg 1536 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c reg = QLC_83XX_PORT1_THRESHOLD; reg 1539 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c QLCWR32(adapter, reg + (i * 0x4), 0x0); reg 1544 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c reg = QLC_83XX_PORT0_TC_MC_REG; reg 1546 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c reg = QLC_83XX_PORT1_TC_MC_REG; reg 1549 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF); reg 252 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c u32 cap, reg, val, reg2; reg 357 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c reg = le32_to_cpu(prsp_rds[i].host_producer_crb); reg 358 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c rds_ring->crb_rcv_producer = ahw->pci_base0 + reg; reg 366 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c reg = le32_to_cpu(prsp_sds[i].host_consumer_crb); reg 373 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c sds_ring->crb_sts_consumer = ahw->pci_base0 + reg; reg 292 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c u32 speed, reg; reg 329 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c reg = QLCRD32(adapter, reg 331 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c speed = P3P_LINK_SPEED_VAL(pcifn, reg); reg 512 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define P3P_LINK_SPEED_VAL(pcifn, reg) \ reg 513 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h (((reg) >> (8 * ((pcifn) & 0x3))) & P3P_LINK_SPEED_MASK) reg 516 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define QLCNIC_CAM_RAM(reg) (QLCNIC_CAM_RAM_BASE + (reg)) reg 589 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define QLCNIC_PCIX_PH_REG(reg) (QLCNIC_CRB_PCIE + (reg)) reg 590 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define QLCNIC_PCIX_PS_REG(reg) (QLCNIC_CRB_PCIX_MD + (reg)) reg 591 drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h #define QLCNIC_PCIE_REG(reg) (QLCNIC_CRB_PCIE + (reg)) reg 251 drivers/net/ethernet/qualcomm/emac/emac-mac.c u32 crc32, bit, reg, mta; reg 260 drivers/net/ethernet/qualcomm/emac/emac-mac.c reg = (crc32 >> 31) & 0x1; reg 263 drivers/net/ethernet/qualcomm/emac/emac-mac.c mta = readl(adpt->base + EMAC_HASH_TAB_REG0 + (reg << 2)); reg 265 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(mta, adpt->base + EMAC_HASH_TAB_REG0 + (reg << 2)); reg 1096 drivers/net/ethernet/qualcomm/emac/emac-mac.c u32 reg; reg 1098 drivers/net/ethernet/qualcomm/emac/emac-mac.c reg = readl_relaxed(adpt->base + rx_q->consume_reg); reg 1100 drivers/net/ethernet/qualcomm/emac/emac-mac.c hw_consume_idx = (reg & rx_q->consume_mask) >> rx_q->consume_shift; reg 1181 drivers/net/ethernet/qualcomm/emac/emac-mac.c u32 reg = readl_relaxed(adpt->base + tx_q->consume_reg); reg 1185 drivers/net/ethernet/qualcomm/emac/emac-mac.c hw_consume_idx = (reg & tx_q->consume_mask) >> tx_q->consume_shift; reg 47 drivers/net/ethernet/qualcomm/emac/emac-phy.c u32 reg; reg 52 drivers/net/ethernet/qualcomm/emac/emac-phy.c reg = SUP_PREAMBLE | reg 57 drivers/net/ethernet/qualcomm/emac/emac-phy.c writel(reg, adpt->base + EMAC_MDIO_CTRL); reg 59 drivers/net/ethernet/qualcomm/emac/emac-phy.c if (readl_poll_timeout(adpt->base + EMAC_MDIO_CTRL, reg, reg 60 drivers/net/ethernet/qualcomm/emac/emac-phy.c !(reg & (MDIO_START | MDIO_BUSY)), reg 64 drivers/net/ethernet/qualcomm/emac/emac-phy.c return (reg >> MDIO_DATA_SHFT) & MDIO_DATA_BMSK; reg 70 drivers/net/ethernet/qualcomm/emac/emac-phy.c u32 reg; reg 75 drivers/net/ethernet/qualcomm/emac/emac-phy.c reg = SUP_PREAMBLE | reg 81 drivers/net/ethernet/qualcomm/emac/emac-phy.c writel(reg, adpt->base + EMAC_MDIO_CTRL); reg 83 drivers/net/ethernet/qualcomm/emac/emac-phy.c if (readl_poll_timeout(adpt->base + EMAC_MDIO_CTRL, reg, reg 84 drivers/net/ethernet/qualcomm/emac/emac-phy.c !(reg & (MDIO_START | MDIO_BUSY)), reg 409 drivers/net/ethernet/qualcomm/emac/emac.c u32 reg; reg 429 drivers/net/ethernet/qualcomm/emac/emac.c reg = ((EMAC_DEF_RX_IRQ_MOD >> 1) << IRQ_MODERATOR2_INIT_SHFT) | reg 431 drivers/net/ethernet/qualcomm/emac/emac.c adpt->irq_mod = reg; reg 601 drivers/net/ethernet/qualcomm/emac/emac.c u32 reg; reg 698 drivers/net/ethernet/qualcomm/emac/emac.c reg = readl_relaxed(adpt->base + EMAC_DMA_MAS_CTRL); reg 699 drivers/net/ethernet/qualcomm/emac/emac.c devid = (reg & DEV_ID_NUM_BMSK) >> DEV_ID_NUM_SHFT; reg 700 drivers/net/ethernet/qualcomm/emac/emac.c revid = (reg & DEV_REV_NUM_BMSK) >> DEV_REV_NUM_SHFT; reg 701 drivers/net/ethernet/qualcomm/emac/emac.c reg = readl_relaxed(adpt->base + EMAC_CORE_HW_VERSION); reg 706 drivers/net/ethernet/qualcomm/emac/emac.c (reg & MAJOR_BMSK) >> MAJOR_SHFT, reg 707 drivers/net/ethernet/qualcomm/emac/emac.c (reg & MINOR_BMSK) >> MINOR_SHFT, reg 708 drivers/net/ethernet/qualcomm/emac/emac.c (reg & STEP_BMSK) >> STEP_SHFT); reg 44 drivers/net/ethernet/qualcomm/qca_7k.c qcaspi_read_register(struct qcaspi *qca, u16 reg, u16 *result) reg 56 drivers/net/ethernet/qualcomm/qca_7k.c tx_data = cpu_to_be16(QCA7K_SPI_READ | QCA7K_SPI_INTERNAL | reg); reg 85 drivers/net/ethernet/qualcomm/qca_7k.c __qcaspi_write_register(struct qcaspi *qca, u16 reg, u16 value) reg 96 drivers/net/ethernet/qualcomm/qca_7k.c tx_data[0] = cpu_to_be16(QCA7K_SPI_WRITE | QCA7K_SPI_INTERNAL | reg); reg 122 drivers/net/ethernet/qualcomm/qca_7k.c qcaspi_write_register(struct qcaspi *qca, u16 reg, u16 value, int retry) reg 128 drivers/net/ethernet/qualcomm/qca_7k.c ret = __qcaspi_write_register(qca, reg, value); reg 135 drivers/net/ethernet/qualcomm/qca_7k.c ret = qcaspi_read_register(qca, reg, &confirmed); reg 68 drivers/net/ethernet/qualcomm/qca_7k.h int qcaspi_read_register(struct qcaspi *qca, u16 reg, u16 *result); reg 69 drivers/net/ethernet/qualcomm/qca_7k.h int qcaspi_write_register(struct qcaspi *qca, u16 reg, u16 value, int retry); reg 198 drivers/net/ethernet/rdc/r6040.c static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg) reg 203 drivers/net/ethernet/rdc/r6040.c iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO); reg 220 drivers/net/ethernet/rdc/r6040.c int phy_addr, int reg, u16 val) reg 227 drivers/net/ethernet/rdc/r6040.c iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO); reg 239 drivers/net/ethernet/rdc/r6040.c static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg) reg 245 drivers/net/ethernet/rdc/r6040.c return r6040_phy_read(ioaddr, phy_addr, reg); reg 249 drivers/net/ethernet/rdc/r6040.c int reg, u16 value) reg 255 drivers/net/ethernet/rdc/r6040.c return r6040_phy_write(ioaddr, phy_addr, reg, value); reg 355 drivers/net/ethernet/realtek/8139cp.c #define cpr8(reg) readb(cp->regs + (reg)) reg 356 drivers/net/ethernet/realtek/8139cp.c #define cpr16(reg) readw(cp->regs + (reg)) reg 357 drivers/net/ethernet/realtek/8139cp.c #define cpr32(reg) readl(cp->regs + (reg)) reg 358 drivers/net/ethernet/realtek/8139cp.c #define cpw8(reg,val) writeb((val), cp->regs + (reg)) reg 359 drivers/net/ethernet/realtek/8139cp.c #define cpw16(reg,val) writew((val), cp->regs + (reg)) reg 360 drivers/net/ethernet/realtek/8139cp.c #define cpw32(reg,val) writel((val), cp->regs + (reg)) reg 361 drivers/net/ethernet/realtek/8139cp.c #define cpw8_f(reg,val) do { \ reg 362 drivers/net/ethernet/realtek/8139cp.c writeb((val), cp->regs + (reg)); \ reg 363 drivers/net/ethernet/realtek/8139cp.c readb(cp->regs + (reg)); \ reg 365 drivers/net/ethernet/realtek/8139cp.c #define cpw16_f(reg,val) do { \ reg 366 drivers/net/ethernet/realtek/8139cp.c writew((val), cp->regs + (reg)); \ reg 367 drivers/net/ethernet/realtek/8139cp.c readw(cp->regs + (reg)); \ reg 369 drivers/net/ethernet/realtek/8139cp.c #define cpw32_f(reg,val) do { \ reg 370 drivers/net/ethernet/realtek/8139cp.c writel((val), cp->regs + (reg)); \ reg 371 drivers/net/ethernet/realtek/8139cp.c readl(cp->regs + (reg)); \ reg 668 drivers/net/ethernet/realtek/8139too.c #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0) reg 669 drivers/net/ethernet/realtek/8139too.c #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0) reg 670 drivers/net/ethernet/realtek/8139too.c #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0) reg 673 drivers/net/ethernet/realtek/8139too.c #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg)) reg 674 drivers/net/ethernet/realtek/8139too.c #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg)) reg 675 drivers/net/ethernet/realtek/8139too.c #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg)) reg 678 drivers/net/ethernet/realtek/8139too.c #define RTL_R8(reg) ioread8 (ioaddr + (reg)) reg 679 drivers/net/ethernet/realtek/8139too.c #define RTL_R16(reg) ioread16 (ioaddr + (reg)) reg 680 drivers/net/ethernet/realtek/8139too.c #define RTL_R32(reg) ioread32 (ioaddr + (reg)) reg 159 drivers/net/ethernet/realtek/atp.h write_reg(short port, unsigned char reg, unsigned char value) reg 163 drivers/net/ethernet/realtek/atp.h outb(EOC | reg, port + PAR_DATA); reg 164 drivers/net/ethernet/realtek/atp.h outval = WrAddr | reg; reg 179 drivers/net/ethernet/realtek/atp.h write_reg_high(short port, unsigned char reg, unsigned char value) reg 181 drivers/net/ethernet/realtek/atp.h unsigned char outval = EOC | HNib | reg; reg 199 drivers/net/ethernet/realtek/atp.h write_reg_byte(short port, unsigned char reg, unsigned char value) reg 203 drivers/net/ethernet/realtek/atp.h outb(EOC | reg, port + PAR_DATA); /* Reset the address register. */ reg 204 drivers/net/ethernet/realtek/atp.h outval = WrAddr | reg; reg 15 drivers/net/ethernet/realtek/r8169_firmware.h typedef void (*rtl_fw_write_t)(struct rtl8169_private *tp, int reg, int val); reg 16 drivers/net/ethernet/realtek/r8169_firmware.h typedef int (*rtl_fw_read_t)(struct rtl8169_private *tp, int reg); reg 79 drivers/net/ethernet/realtek/r8169_main.c #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) reg 80 drivers/net/ethernet/realtek/r8169_main.c #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) reg 81 drivers/net/ethernet/realtek/r8169_main.c #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) reg 82 drivers/net/ethernet/realtek/r8169_main.c #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) reg 83 drivers/net/ethernet/realtek/r8169_main.c #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) reg 84 drivers/net/ethernet/realtek/r8169_main.c #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) reg 770 drivers/net/ethernet/realtek/r8169_main.c static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) reg 775 drivers/net/ethernet/realtek/r8169_main.c mac[i] = RTL_R8(tp, reg + i); reg 842 drivers/net/ethernet/realtek/r8169_main.c static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) reg 844 drivers/net/ethernet/realtek/r8169_main.c if (reg & 0xffff0001) { reg 845 drivers/net/ethernet/realtek/r8169_main.c netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg); reg 856 drivers/net/ethernet/realtek/r8169_main.c static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) reg 858 drivers/net/ethernet/realtek/r8169_main.c if (rtl_ocp_reg_failure(tp, reg)) reg 861 drivers/net/ethernet/realtek/r8169_main.c RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); reg 866 drivers/net/ethernet/realtek/r8169_main.c static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) reg 868 drivers/net/ethernet/realtek/r8169_main.c if (rtl_ocp_reg_failure(tp, reg)) reg 871 drivers/net/ethernet/realtek/r8169_main.c RTL_W32(tp, GPHY_OCP, reg << 15); reg 877 drivers/net/ethernet/realtek/r8169_main.c static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) reg 879 drivers/net/ethernet/realtek/r8169_main.c if (rtl_ocp_reg_failure(tp, reg)) reg 882 drivers/net/ethernet/realtek/r8169_main.c RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); reg 885 drivers/net/ethernet/realtek/r8169_main.c static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) reg 887 drivers/net/ethernet/realtek/r8169_main.c if (rtl_ocp_reg_failure(tp, reg)) reg 890 drivers/net/ethernet/realtek/r8169_main.c RTL_W32(tp, OCPDR, reg << 15); reg 895 drivers/net/ethernet/realtek/r8169_main.c static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, reg 898 drivers/net/ethernet/realtek/r8169_main.c u16 data = r8168_mac_ocp_read(tp, reg); reg 900 drivers/net/ethernet/realtek/r8169_main.c r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); reg 905 drivers/net/ethernet/realtek/r8169_main.c static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) reg 907 drivers/net/ethernet/realtek/r8169_main.c if (reg == 0x1f) { reg 913 drivers/net/ethernet/realtek/r8169_main.c reg -= 0x10; reg 915 drivers/net/ethernet/realtek/r8169_main.c r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); reg 918 drivers/net/ethernet/realtek/r8169_main.c static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) reg 920 drivers/net/ethernet/realtek/r8169_main.c if (reg == 0x1f) reg 924 drivers/net/ethernet/realtek/r8169_main.c reg -= 0x10; reg 926 drivers/net/ethernet/realtek/r8169_main.c return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); reg 929 drivers/net/ethernet/realtek/r8169_main.c static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) reg 931 drivers/net/ethernet/realtek/r8169_main.c if (reg == 0x1f) { reg 936 drivers/net/ethernet/realtek/r8169_main.c r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); reg 939 drivers/net/ethernet/realtek/r8169_main.c static int mac_mcu_read(struct rtl8169_private *tp, int reg) reg 941 drivers/net/ethernet/realtek/r8169_main.c return r8168_mac_ocp_read(tp, tp->ocp_base + reg); reg 949 drivers/net/ethernet/realtek/r8169_main.c static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) reg 951 drivers/net/ethernet/realtek/r8169_main.c RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); reg 961 drivers/net/ethernet/realtek/r8169_main.c static int r8169_mdio_read(struct rtl8169_private *tp, int reg) reg 965 drivers/net/ethernet/realtek/r8169_main.c RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); reg 984 drivers/net/ethernet/realtek/r8169_main.c static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) reg 986 drivers/net/ethernet/realtek/r8169_main.c RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); reg 993 drivers/net/ethernet/realtek/r8169_main.c static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) reg 995 drivers/net/ethernet/realtek/r8169_main.c r8168dp_1_mdio_access(tp, reg, reg 999 drivers/net/ethernet/realtek/r8169_main.c static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) reg 1001 drivers/net/ethernet/realtek/r8169_main.c r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); reg 1023 drivers/net/ethernet/realtek/r8169_main.c static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) reg 1027 drivers/net/ethernet/realtek/r8169_main.c r8169_mdio_write(tp, reg, value); reg 1032 drivers/net/ethernet/realtek/r8169_main.c static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) reg 1037 drivers/net/ethernet/realtek/r8169_main.c if (reg == MII_PHYSID2) reg 1042 drivers/net/ethernet/realtek/r8169_main.c value = r8169_mdio_read(tp, reg); reg 1174 drivers/net/ethernet/realtek/r8169_main.c static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) reg 1176 drivers/net/ethernet/realtek/r8169_main.c RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); reg 1181 drivers/net/ethernet/realtek/r8169_main.c static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) reg 1183 drivers/net/ethernet/realtek/r8169_main.c return _rtl_eri_read(tp, reg, ERIAR_OOB); reg 1186 drivers/net/ethernet/realtek/r8169_main.c static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, reg 1190 drivers/net/ethernet/realtek/r8169_main.c RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); reg 1194 drivers/net/ethernet/realtek/r8169_main.c static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, reg 1197 drivers/net/ethernet/realtek/r8169_main.c _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, reg 1219 drivers/net/ethernet/realtek/r8169_main.c u16 reg; reg 1221 drivers/net/ethernet/realtek/r8169_main.c reg = rtl8168_get_ocp_reg(tp); reg 1223 drivers/net/ethernet/realtek/r8169_main.c return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800; reg 1313 drivers/net/ethernet/realtek/r8169_main.c u16 reg = rtl8168_get_ocp_reg(tp); reg 1315 drivers/net/ethernet/realtek/r8169_main.c return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000); reg 1460 drivers/net/ethernet/realtek/r8169_main.c u16 reg; reg 1492 drivers/net/ethernet/realtek/r8169_main.c options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; reg 1495 drivers/net/ethernet/realtek/r8169_main.c RTL_W8(tp, cfg[i].reg, options); reg 2227 drivers/net/ethernet/realtek/r8169_main.c u16 reg = RTL_R32(tp, TxConfig) >> 20; reg 2229 drivers/net/ethernet/realtek/r8169_main.c while ((reg & p->mask) != p->val) reg 2234 drivers/net/ethernet/realtek/r8169_main.c dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf); reg 2246 drivers/net/ethernet/realtek/r8169_main.c u16 reg; reg 2254 drivers/net/ethernet/realtek/r8169_main.c rtl_writephy(tp, regs->reg, regs->val); reg 2277 drivers/net/ethernet/realtek/r8169_main.c static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) reg 2279 drivers/net/ethernet/realtek/r8169_main.c if (rtl_readphy(tp, reg) != val) reg 1042 drivers/net/ethernet/renesas/ravb.h static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg) reg 1046 drivers/net/ethernet/renesas/ravb.h return ioread32(priv->addr + reg); reg 1050 drivers/net/ethernet/renesas/ravb.h enum ravb_reg reg) reg 1054 drivers/net/ethernet/renesas/ravb.h iowrite32(data, priv->addr + reg); reg 1057 drivers/net/ethernet/renesas/ravb.h void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, reg 1059 drivers/net/ethernet/renesas/ravb.h int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value); reg 53 drivers/net/ethernet/renesas/ravb_main.c void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, reg 56 drivers/net/ethernet/renesas/ravb_main.c ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); reg 59 drivers/net/ethernet/renesas/ravb_main.c int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) reg 64 drivers/net/ethernet/renesas/ravb_main.c if ((ravb_read(ndev, reg) & mask) == value) reg 2123 drivers/net/ethernet/renesas/sh_eth.c #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32) reg 2124 drivers/net/ethernet/renesas/sh_eth.c #define add_reg_from(reg, read_expr) do { \ reg 2125 drivers/net/ethernet/renesas/sh_eth.c if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ reg 2127 drivers/net/ethernet/renesas/sh_eth.c mark_reg_valid(reg); \ reg 2133 drivers/net/ethernet/renesas/sh_eth.c #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg)) reg 2134 drivers/net/ethernet/renesas/sh_eth.c #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg)) reg 2577 drivers/net/ethernet/renesas/sh_eth.c sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg) reg 2579 drivers/net/ethernet/renesas/sh_eth.c u32 delta = sh_eth_read(ndev, reg); reg 2583 drivers/net/ethernet/renesas/sh_eth.c sh_eth_write(ndev, 0, reg); reg 2690 drivers/net/ethernet/renesas/sh_eth.c int reg = TSU_POST1 + entry / 8; reg 2693 drivers/net/ethernet/renesas/sh_eth.c tmp = sh_eth_tsu_read(mdp, reg); reg 2694 drivers/net/ethernet/renesas/sh_eth.c sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg); reg 2701 drivers/net/ethernet/renesas/sh_eth.c int reg = TSU_POST1 + entry / 8; reg 2707 drivers/net/ethernet/renesas/sh_eth.c tmp = sh_eth_tsu_read(mdp, reg); reg 2708 drivers/net/ethernet/renesas/sh_eth.c sh_eth_tsu_write(mdp, tmp & ~post_mask, reg); reg 113 drivers/net/ethernet/rocker/rocker_main.c #define rocker_write32(rocker, reg, val) \ reg 114 drivers/net/ethernet/rocker/rocker_main.c writel((val), (rocker)->hw_addr + (ROCKER_ ## reg)) reg 115 drivers/net/ethernet/rocker/rocker_main.c #define rocker_read32(rocker, reg) \ reg 116 drivers/net/ethernet/rocker/rocker_main.c readl((rocker)->hw_addr + (ROCKER_ ## reg)) reg 117 drivers/net/ethernet/rocker/rocker_main.c #define rocker_write64(rocker, reg, val) \ reg 118 drivers/net/ethernet/rocker/rocker_main.c writeq((val), (rocker)->hw_addr + (ROCKER_ ## reg)) reg 119 drivers/net/ethernet/rocker/rocker_main.c #define rocker_read64(rocker, reg) \ reg 120 drivers/net/ethernet/rocker/rocker_main.c readq((rocker)->hw_addr + (ROCKER_ ## reg)) reg 165 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h #define SXGBE_ADDR_HIGH(reg) (((reg > 15) ? 0x00000800 : 0x00000040) + \ reg 166 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h (reg * 8)) reg 167 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h #define SXGBE_ADDR_LOW(reg) (((reg > 15) ? 0x00000804 : 0x00000044) + \ reg 168 drivers/net/ethernet/samsung/sxgbe/sxgbe_common.h (reg * 8)) reg 1844 drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c int reg = 1; reg 1887 drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c sxgbe_set_umac_addr(ioaddr, ha->addr, reg); reg 1888 drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c reg++; reg 45 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c u32 reg = phydata; reg 47 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c reg |= (cmd << 16) | SXGBE_SMA_SKIP_ADDRFRM | reg 49 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c writel(reg, sp->ioaddr + sp->hw->mii.data); reg 55 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c u32 reg; reg 58 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c reg = ((phyreg >> 16) & 0x1f) << 21; reg 59 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c reg |= (phyaddr << 16) | (phyreg & 0xffff); reg 60 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c writel(reg, sp->ioaddr + sp->hw->mii.addr); reg 68 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c u32 reg; reg 73 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c reg = (phyaddr << 16) | (phyreg & 0x1f); reg 74 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c writel(reg, sp->ioaddr + sp->hw->mii.addr); reg 148 drivers/net/ethernet/sfc/ef10.c efx_dword_t reg; reg 150 drivers/net/ethernet/sfc/ef10.c efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); reg 151 drivers/net/ethernet/sfc/ef10.c return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? reg 152 drivers/net/ethernet/sfc/ef10.c EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; reg 2254 drivers/net/ethernet/sfc/ef10.c efx_dword_t reg; reg 2258 drivers/net/ethernet/sfc/ef10.c efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); reg 2259 drivers/net/ethernet/sfc/ef10.c queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); reg 2278 drivers/net/ethernet/sfc/ef10.c irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); reg 2311 drivers/net/ethernet/sfc/ef10.c efx_oword_t reg; reg 2314 drivers/net/ethernet/sfc/ef10.c EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); reg 2315 drivers/net/ethernet/sfc/ef10.c reg.qword[0] = *txd; reg 2316 drivers/net/ethernet/sfc/ef10.c efx_writeo_page(tx_queue->efx, ®, reg 2562 drivers/net/ethernet/sfc/ef10.c efx_dword_t reg; reg 2565 drivers/net/ethernet/sfc/ef10.c EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); reg 2566 drivers/net/ethernet/sfc/ef10.c efx_writed_page(tx_queue->efx, ®, reg 3175 drivers/net/ethernet/sfc/ef10.c efx_dword_t reg; reg 3189 drivers/net/ethernet/sfc/ef10.c EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, reg 3191 drivers/net/ethernet/sfc/ef10.c efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, reg 329 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg; reg 331 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AB_GPIO_CTL); reg 332 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state); reg 333 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_GPIO_CTL); reg 339 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg; reg 341 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AB_GPIO_CTL); reg 342 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state); reg 343 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_GPIO_CTL); reg 349 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg; reg 351 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AB_GPIO_CTL); reg 352 drivers/net/ethernet/sfc/falcon/falcon.c return EF4_OWORD_FIELD(reg, FRF_AB_GPIO3_IN); reg 358 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg; reg 360 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AB_GPIO_CTL); reg 361 drivers/net/ethernet/sfc/falcon/falcon.c return EF4_OWORD_FIELD(reg, FRF_AB_GPIO0_IN); reg 424 drivers/net/ethernet/sfc/falcon/falcon.c ef4_dword_t reg; reg 426 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e); reg 427 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writed(efx, ®, FR_AA_INT_ACK_KER); reg 428 drivers/net/ethernet/sfc/falcon/falcon.c ef4_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS); reg 518 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg; reg 519 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AB_EE_SPI_HCMD); reg 520 drivers/net/ethernet/sfc/falcon/falcon.c return EF4_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0; reg 558 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg; reg 572 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address); reg 573 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_EE_SPI_HADR); reg 578 drivers/net/ethernet/sfc/falcon/falcon.c memcpy(®, in, len); reg 579 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_EE_SPI_HDATA); reg 583 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_7(reg, reg 592 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_EE_SPI_HCMD); reg 601 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AB_EE_SPI_HDATA); reg 602 drivers/net/ethernet/sfc/falcon/falcon.c memcpy(out, ®, len); reg 1016 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg; reg 1023 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1); reg 1024 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_XX_PWR_RST); reg 1028 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AB_XX_PWR_RST); reg 1029 drivers/net/ethernet/sfc/falcon/falcon.c if (EF4_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 && reg 1030 drivers/net/ethernet/sfc/falcon/falcon.c EF4_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) { reg 1044 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg; reg 1058 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AB_XM_MGT_INT_MSK); reg 1063 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg; reg 1068 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AB_XX_CORE_STAT); reg 1070 drivers/net/ethernet/sfc/falcon/falcon.c align_done = EF4_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE); reg 1071 drivers/net/ethernet/sfc/falcon/falcon.c sync_status = EF4_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT); reg 1076 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES); reg 1077 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES); reg 1078 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES); reg 1079 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_XX_CORE_STAT); reg 1102 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg; reg 1107 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_3(reg, reg 1111 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_XM_GLB_CFG); reg 1114 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_6(reg, reg 1121 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_XM_TX_CFG); reg 1124 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_5(reg, reg 1130 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_XM_RX_CFG); reg 1134 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len); reg 1135 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_XM_RX_PARAM); reg 1136 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_2(reg, reg 1139 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_XM_TX_PARAM); reg 1141 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_2(reg, reg 1144 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_XM_FC); reg 1147 drivers/net/ethernet/sfc/falcon/falcon.c memcpy(®, &efx->net_dev->dev_addr[0], 4); reg 1148 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_XM_ADR_LO); reg 1149 drivers/net/ethernet/sfc/falcon/falcon.c memcpy(®, &efx->net_dev->dev_addr[4], 2); reg 1150 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_XM_ADR_HI); reg 1155 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg; reg 1163 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AB_XX_CORE_STAT); reg 1164 drivers/net/ethernet/sfc/falcon/falcon.c old_xgxs_loopback = EF4_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN); reg 1165 drivers/net/ethernet/sfc/falcon/falcon.c old_xgmii_loopback = EF4_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN); reg 1167 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AB_XX_SD_CTL); reg 1168 drivers/net/ethernet/sfc/falcon/falcon.c old_xaui_loopback = EF4_OWORD_FIELD(reg, FRF_AB_XX_LPBKA); reg 1176 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AB_XX_CORE_STAT); reg 1177 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG, reg 1180 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback); reg 1181 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback); reg 1182 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_XX_CORE_STAT); reg 1184 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AB_XX_SD_CTL); reg 1185 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback); reg 1186 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback); reg 1187 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback); reg 1188 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback); reg 1189 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_XX_SD_CTL); reg 1273 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg, mac_ctrl; reg 1280 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1); reg 1281 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_XM_GLB_CFG); reg 1284 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AB_XM_GLB_CFG); reg 1285 drivers/net/ethernet/sfc/falcon/falcon.c if (EF4_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) == reg 1302 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AB_GLB_CTL); reg 1303 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1); reg 1304 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1); reg 1305 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1); reg 1306 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_GLB_CTL); reg 1310 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AB_GLB_CTL); reg 1311 drivers/net/ethernet/sfc/falcon/falcon.c if (!EF4_OWORD_FIELD(reg, FRF_AB_RST_XGTX) && reg 1312 drivers/net/ethernet/sfc/falcon/falcon.c !EF4_OWORD_FIELD(reg, FRF_AB_RST_XGRX) && reg 1313 drivers/net/ethernet/sfc/falcon/falcon.c !EF4_OWORD_FIELD(reg, FRF_AB_RST_EM)) { reg 1336 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg; reg 1342 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AB_MAC_CTRL); reg 1344 drivers/net/ethernet/sfc/falcon/falcon.c if (EF4_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN)) reg 1352 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg; reg 1358 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AZ_RX_CFG); reg 1359 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0); reg 1360 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AZ_RX_CFG); reg 1369 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg; reg 1385 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_5(reg, reg 1394 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, reg 1398 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_MAC_CTRL); reg 1403 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AZ_RX_CFG); reg 1406 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1); reg 1409 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate); reg 1410 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AZ_RX_CFG); reg 1416 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg; reg 1426 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_2(reg, reg 1430 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_MAC_STAT_DMA); reg 1577 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg; reg 1592 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); reg 1593 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_MD_PHY_ADR); reg 1595 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, reg 1597 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_MD_ID); reg 1600 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value); reg 1601 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_MD_TXD); reg 1603 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_2(reg, reg 1606 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_MD_CS); reg 1612 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_2(reg, reg 1615 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_MD_CS); reg 1630 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg; reg 1640 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); reg 1641 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_MD_PHY_ADR); reg 1643 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, reg 1645 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_MD_ID); reg 1648 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0); reg 1649 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_MD_CS); reg 1654 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AB_MD_RXD); reg 1655 drivers/net/ethernet/sfc/falcon/falcon.c rc = EF4_OWORD_FIELD(reg, FRF_AB_MD_RXD); reg 1661 drivers/net/ethernet/sfc/falcon/falcon.c EF4_POPULATE_OWORD_2(reg, reg 1664 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AB_MD_CS); reg 2430 drivers/net/ethernet/sfc/falcon/falcon.c ef4_oword_t reg; reg 2432 drivers/net/ethernet/sfc/falcon/falcon.c ef4_reado(efx, ®, FR_AZ_RX_CFG); reg 2440 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0); reg 2441 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE, reg 2443 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, 512 >> 8); reg 2444 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, 2048 >> 8); reg 2445 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr); reg 2446 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr); reg 2449 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0); reg 2450 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE, reg 2453 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, 27648 >> 8); reg 2454 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, 54272 >> 8); reg 2455 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr); reg 2456 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr); reg 2457 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); reg 2462 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1); reg 2463 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1); reg 2464 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1); reg 2468 drivers/net/ethernet/sfc/falcon/falcon.c EF4_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1); reg 2469 drivers/net/ethernet/sfc/falcon/falcon.c ef4_writeo(efx, ®, FR_AZ_RX_CFG); reg 69 drivers/net/ethernet/sfc/falcon/falcon_boards.c u8 reg = *reg_values++; reg 71 drivers/net/ethernet/sfc/falcon/falcon_boards.c int rc = i2c_smbus_write_byte_data(client, reg, value); reg 126 drivers/net/ethernet/sfc/falcon/falcon_boards.c s32 reg; reg 132 drivers/net/ethernet/sfc/falcon/falcon_boards.c reg = i2c_smbus_read_byte_data(client, LM87_REG_ALARMS1); reg 133 drivers/net/ethernet/sfc/falcon/falcon_boards.c if (reg < 0) reg 134 drivers/net/ethernet/sfc/falcon/falcon_boards.c return reg; reg 135 drivers/net/ethernet/sfc/falcon/falcon_boards.c alarms = reg; reg 136 drivers/net/ethernet/sfc/falcon/falcon_boards.c reg = i2c_smbus_read_byte_data(client, LM87_REG_ALARMS2); reg 137 drivers/net/ethernet/sfc/falcon/falcon_boards.c if (reg < 0) reg 138 drivers/net/ethernet/sfc/falcon/falcon_boards.c return reg; reg 139 drivers/net/ethernet/sfc/falcon/falcon_boards.c alarms |= reg << 8; reg 144 drivers/net/ethernet/sfc/falcon/falcon_boards.c reg = i2c_smbus_read_byte_data(client, LM87_REG_TEMP_INT); reg 145 drivers/net/ethernet/sfc/falcon/falcon_boards.c if (reg < 0) reg 146 drivers/net/ethernet/sfc/falcon/falcon_boards.c return reg; reg 147 drivers/net/ethernet/sfc/falcon/falcon_boards.c if (reg > FALCON_BOARD_TEMP_CRIT) reg 151 drivers/net/ethernet/sfc/falcon/falcon_boards.c reg = i2c_smbus_read_byte_data(client, LM87_REG_TEMP_EXT1); reg 152 drivers/net/ethernet/sfc/falcon/falcon_boards.c if (reg < 0) reg 153 drivers/net/ethernet/sfc/falcon/falcon_boards.c return reg; reg 154 drivers/net/ethernet/sfc/falcon/falcon_boards.c if (reg > FALCON_JUNC_TEMP_CRIT) reg 609 drivers/net/ethernet/sfc/falcon/falcon_boards.c int reg; reg 613 drivers/net/ethernet/sfc/falcon/falcon_boards.c reg = QUAKE_LED_OFF; reg 616 drivers/net/ethernet/sfc/falcon/falcon_boards.c reg = QUAKE_LED_ON; reg 619 drivers/net/ethernet/sfc/falcon/falcon_boards.c reg = QUAKE_LED_RXLINK | QUAKE_LED_LINK_STAT; reg 623 drivers/net/ethernet/sfc/falcon/falcon_boards.c falcon_qt202x_set_led(efx, SFN4112F_LINK_LED, reg); reg 104 drivers/net/ethernet/sfc/falcon/farch.c ef4_oword_t mask, imask, original, reg, buf; reg 119 drivers/net/ethernet/sfc/falcon/farch.c EF4_AND_OWORD(reg, original, mask); reg 120 drivers/net/ethernet/sfc/falcon/farch.c EF4_SET_OWORD32(reg, j, j, 1); reg 122 drivers/net/ethernet/sfc/falcon/farch.c ef4_writeo(efx, ®, address); reg 125 drivers/net/ethernet/sfc/falcon/farch.c if (ef4_masked_compare_oword(®, &buf, &mask)) reg 129 drivers/net/ethernet/sfc/falcon/farch.c EF4_OR_OWORD(reg, original, mask); reg 130 drivers/net/ethernet/sfc/falcon/farch.c EF4_SET_OWORD32(reg, j, j, 0); reg 132 drivers/net/ethernet/sfc/falcon/farch.c ef4_writeo(efx, ®, address); reg 135 drivers/net/ethernet/sfc/falcon/farch.c if (ef4_masked_compare_oword(®, &buf, &mask)) reg 147 drivers/net/ethernet/sfc/falcon/farch.c " at address 0x%x mask "EF4_OWORD_FMT"\n", EF4_OWORD_VAL(reg), reg 275 drivers/net/ethernet/sfc/falcon/farch.c ef4_dword_t reg; reg 278 drivers/net/ethernet/sfc/falcon/farch.c EF4_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr); reg 279 drivers/net/ethernet/sfc/falcon/farch.c ef4_writed_page(tx_queue->efx, ®, reg 288 drivers/net/ethernet/sfc/falcon/farch.c ef4_oword_t reg; reg 294 drivers/net/ethernet/sfc/falcon/farch.c EF4_POPULATE_OWORD_2(reg, FRF_AZ_TX_DESC_PUSH_CMD, true, reg 296 drivers/net/ethernet/sfc/falcon/farch.c reg.qword[0] = *txd; reg 297 drivers/net/ethernet/sfc/falcon/farch.c ef4_writeo_page(tx_queue->efx, ®, reg 376 drivers/net/ethernet/sfc/falcon/farch.c ef4_oword_t reg; reg 382 drivers/net/ethernet/sfc/falcon/farch.c EF4_POPULATE_OWORD_10(reg, reg 398 drivers/net/ethernet/sfc/falcon/farch.c EF4_SET_OWORD_FIELD(reg, FRF_BZ_TX_IP_CHKSM_DIS, !csum); reg 399 drivers/net/ethernet/sfc/falcon/farch.c EF4_SET_OWORD_FIELD(reg, FRF_BZ_TX_TCP_CHKSM_DIS, reg 403 drivers/net/ethernet/sfc/falcon/farch.c ef4_writeo_table(efx, ®, efx->type->txd_ptr_tbl_base, reg 410 drivers/net/ethernet/sfc/falcon/farch.c ef4_reado(efx, ®, FR_AA_TX_CHKSM_CFG); reg 412 drivers/net/ethernet/sfc/falcon/farch.c __clear_bit_le(tx_queue->queue, ®); reg 414 drivers/net/ethernet/sfc/falcon/farch.c __set_bit_le(tx_queue->queue, ®); reg 415 drivers/net/ethernet/sfc/falcon/farch.c ef4_writeo(efx, ®, FR_AA_TX_CHKSM_CFG); reg 419 drivers/net/ethernet/sfc/falcon/farch.c EF4_POPULATE_OWORD_1(reg, reg 424 drivers/net/ethernet/sfc/falcon/farch.c ef4_writeo_table(efx, ®, FR_BZ_TX_PACE_TBL, reg 492 drivers/net/ethernet/sfc/falcon/farch.c ef4_dword_t reg; reg 504 drivers/net/ethernet/sfc/falcon/farch.c EF4_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr); reg 505 drivers/net/ethernet/sfc/falcon/farch.c ef4_writed_page(efx, ®, FR_AZ_RX_DESC_UPD_DWORD_P0, reg 780 drivers/net/ethernet/sfc/falcon/farch.c ef4_dword_t reg; reg 783 drivers/net/ethernet/sfc/falcon/farch.c EF4_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, reg 789 drivers/net/ethernet/sfc/falcon/farch.c ef4_writed(efx, ®, reg 1340 drivers/net/ethernet/sfc/falcon/farch.c ef4_oword_t reg; reg 1355 drivers/net/ethernet/sfc/falcon/farch.c EF4_POPULATE_OWORD_3(reg, reg 1359 drivers/net/ethernet/sfc/falcon/farch.c ef4_writeo_table(efx, ®, efx->type->evq_ptr_tbl_base, reg 1367 drivers/net/ethernet/sfc/falcon/farch.c ef4_oword_t reg; reg 1371 drivers/net/ethernet/sfc/falcon/farch.c EF4_ZERO_OWORD(reg); reg 1372 drivers/net/ethernet/sfc/falcon/farch.c ef4_writeo_table(efx, ®, efx->type->evq_ptr_tbl_base, reg 1464 drivers/net/ethernet/sfc/falcon/farch.c ef4_oword_t reg; reg 1465 drivers/net/ethernet/sfc/falcon/farch.c ef4_reado(efx, ®, FR_AZ_MEM_STAT); reg 1468 drivers/net/ethernet/sfc/falcon/farch.c EF4_OWORD_VAL(reg)); reg 1508 drivers/net/ethernet/sfc/falcon/farch.c ef4_dword_t reg; reg 1513 drivers/net/ethernet/sfc/falcon/farch.c ef4_readd(efx, ®, FR_BZ_INT_ISR0); reg 1514 drivers/net/ethernet/sfc/falcon/farch.c queues = EF4_EXTRACT_DWORD(reg, 0, 31); reg 1520 drivers/net/ethernet/sfc/falcon/farch.c if (EF4_DWORD_IS_ALL_ONES(reg) && ef4_try_recovery(efx) && reg 1573 drivers/net/ethernet/sfc/falcon/farch.c irq, raw_smp_processor_id(), EF4_DWORD_VAL(reg)); reg 68 drivers/net/ethernet/sfc/falcon/io.h unsigned int reg) reg 70 drivers/net/ethernet/sfc/falcon/io.h __raw_writeq((__force u64)value, efx->membase + reg); reg 72 drivers/net/ethernet/sfc/falcon/io.h static inline __le64 _ef4_readq(struct ef4_nic *efx, unsigned int reg) reg 74 drivers/net/ethernet/sfc/falcon/io.h return (__force __le64)__raw_readq(efx->membase + reg); reg 79 drivers/net/ethernet/sfc/falcon/io.h unsigned int reg) reg 81 drivers/net/ethernet/sfc/falcon/io.h __raw_writel((__force u32)value, efx->membase + reg); reg 83 drivers/net/ethernet/sfc/falcon/io.h static inline __le32 _ef4_readd(struct ef4_nic *efx, unsigned int reg) reg 85 drivers/net/ethernet/sfc/falcon/io.h return (__force __le32)__raw_readl(efx->membase + reg); reg 90 drivers/net/ethernet/sfc/falcon/io.h unsigned int reg) reg 95 drivers/net/ethernet/sfc/falcon/io.h "writing register %x with " EF4_OWORD_FMT "\n", reg, reg 100 drivers/net/ethernet/sfc/falcon/io.h _ef4_writeq(efx, value->u64[0], reg + 0); reg 101 drivers/net/ethernet/sfc/falcon/io.h _ef4_writeq(efx, value->u64[1], reg + 8); reg 103 drivers/net/ethernet/sfc/falcon/io.h _ef4_writed(efx, value->u32[0], reg + 0); reg 104 drivers/net/ethernet/sfc/falcon/io.h _ef4_writed(efx, value->u32[1], reg + 4); reg 105 drivers/net/ethernet/sfc/falcon/io.h _ef4_writed(efx, value->u32[2], reg + 8); reg 106 drivers/net/ethernet/sfc/falcon/io.h _ef4_writed(efx, value->u32[3], reg + 12); reg 134 drivers/net/ethernet/sfc/falcon/io.h unsigned int reg) reg 138 drivers/net/ethernet/sfc/falcon/io.h reg, EF4_DWORD_VAL(*value)); reg 141 drivers/net/ethernet/sfc/falcon/io.h _ef4_writed(efx, value->u32[0], reg); reg 146 drivers/net/ethernet/sfc/falcon/io.h unsigned int reg) reg 151 drivers/net/ethernet/sfc/falcon/io.h value->u32[0] = _ef4_readd(efx, reg + 0); reg 152 drivers/net/ethernet/sfc/falcon/io.h value->u32[1] = _ef4_readd(efx, reg + 4); reg 153 drivers/net/ethernet/sfc/falcon/io.h value->u32[2] = _ef4_readd(efx, reg + 8); reg 154 drivers/net/ethernet/sfc/falcon/io.h value->u32[3] = _ef4_readd(efx, reg + 12); reg 158 drivers/net/ethernet/sfc/falcon/io.h "read from register %x, got " EF4_OWORD_FMT "\n", reg, reg 185 drivers/net/ethernet/sfc/falcon/io.h unsigned int reg) reg 187 drivers/net/ethernet/sfc/falcon/io.h value->u32[0] = _ef4_readd(efx, reg); reg 190 drivers/net/ethernet/sfc/falcon/io.h reg, EF4_DWORD_VAL(*value)); reg 196 drivers/net/ethernet/sfc/falcon/io.h unsigned int reg, unsigned int index) reg 198 drivers/net/ethernet/sfc/falcon/io.h ef4_writeo(efx, value, reg + index * sizeof(ef4_oword_t)); reg 203 drivers/net/ethernet/sfc/falcon/io.h unsigned int reg, unsigned int index) reg 205 drivers/net/ethernet/sfc/falcon/io.h ef4_reado(efx, value, reg + index * sizeof(ef4_oword_t)); reg 212 drivers/net/ethernet/sfc/falcon/io.h #define EF4_PAGED_REG(page, reg) \ reg 213 drivers/net/ethernet/sfc/falcon/io.h ((page) * EF4_VI_PAGE_SIZE + (reg)) reg 217 drivers/net/ethernet/sfc/falcon/io.h unsigned int reg, unsigned int page) reg 219 drivers/net/ethernet/sfc/falcon/io.h reg = EF4_PAGED_REG(page, reg); reg 222 drivers/net/ethernet/sfc/falcon/io.h "writing register %x with " EF4_OWORD_FMT "\n", reg, reg 226 drivers/net/ethernet/sfc/falcon/io.h _ef4_writeq(efx, value->u64[0], reg + 0); reg 227 drivers/net/ethernet/sfc/falcon/io.h _ef4_writeq(efx, value->u64[1], reg + 8); reg 229 drivers/net/ethernet/sfc/falcon/io.h _ef4_writed(efx, value->u32[0], reg + 0); reg 230 drivers/net/ethernet/sfc/falcon/io.h _ef4_writed(efx, value->u32[1], reg + 4); reg 231 drivers/net/ethernet/sfc/falcon/io.h _ef4_writed(efx, value->u32[2], reg + 8); reg 232 drivers/net/ethernet/sfc/falcon/io.h _ef4_writed(efx, value->u32[3], reg + 12); reg 235 drivers/net/ethernet/sfc/falcon/io.h #define ef4_writeo_page(efx, value, reg, page) \ reg 237 drivers/net/ethernet/sfc/falcon/io.h reg + \ reg 238 drivers/net/ethernet/sfc/falcon/io.h BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \ reg 246 drivers/net/ethernet/sfc/falcon/io.h unsigned int reg, unsigned int page) reg 248 drivers/net/ethernet/sfc/falcon/io.h ef4_writed(efx, value, EF4_PAGED_REG(page, reg)); reg 250 drivers/net/ethernet/sfc/falcon/io.h #define ef4_writed_page(efx, value, reg, page) \ reg 252 drivers/net/ethernet/sfc/falcon/io.h reg + \ reg 253 drivers/net/ethernet/sfc/falcon/io.h BUILD_BUG_ON_ZERO((reg) != 0x400 && \ reg 254 drivers/net/ethernet/sfc/falcon/io.h (reg) != 0x420 && \ reg 255 drivers/net/ethernet/sfc/falcon/io.h (reg) != 0x830 && \ reg 256 drivers/net/ethernet/sfc/falcon/io.h (reg) != 0x83c && \ reg 257 drivers/net/ethernet/sfc/falcon/io.h (reg) != 0xa18 && \ reg 258 drivers/net/ethernet/sfc/falcon/io.h (reg) != 0xa1c), \ reg 267 drivers/net/ethernet/sfc/falcon/io.h unsigned int reg, reg 274 drivers/net/ethernet/sfc/falcon/io.h ef4_writed(efx, value, EF4_PAGED_REG(page, reg)); reg 277 drivers/net/ethernet/sfc/falcon/io.h ef4_writed(efx, value, EF4_PAGED_REG(page, reg)); reg 280 drivers/net/ethernet/sfc/falcon/io.h #define ef4_writed_page_locked(efx, value, reg, page) \ reg 282 drivers/net/ethernet/sfc/falcon/io.h reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \ reg 275 drivers/net/ethernet/sfc/falcon/mdio_10g.c int reg; reg 280 drivers/net/ethernet/sfc/falcon/mdio_10g.c reg = ADVERTISE_CSMA | ADVERTISE_RESV; reg 282 drivers/net/ethernet/sfc/falcon/mdio_10g.c reg |= ADVERTISE_PAUSE_CAP; reg 284 drivers/net/ethernet/sfc/falcon/mdio_10g.c reg |= ADVERTISE_PAUSE_ASYM; reg 285 drivers/net/ethernet/sfc/falcon/mdio_10g.c ef4_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); reg 291 drivers/net/ethernet/sfc/falcon/mdio_10g.c reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1); reg 292 drivers/net/ethernet/sfc/falcon/mdio_10g.c reg |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART | MDIO_AN_CTRL1_XNP; reg 293 drivers/net/ethernet/sfc/falcon/mdio_10g.c ef4_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg); reg 363 drivers/net/ethernet/sfc/falcon/nic.c const struct ef4_nic_reg *reg; reg 367 drivers/net/ethernet/sfc/falcon/nic.c for (reg = ef4_nic_regs; reg 368 drivers/net/ethernet/sfc/falcon/nic.c reg < ef4_nic_regs + ARRAY_SIZE(ef4_nic_regs); reg 369 drivers/net/ethernet/sfc/falcon/nic.c reg++) reg 370 drivers/net/ethernet/sfc/falcon/nic.c if (efx->type->revision >= reg->min_revision && reg 371 drivers/net/ethernet/sfc/falcon/nic.c efx->type->revision <= reg->max_revision) reg 386 drivers/net/ethernet/sfc/falcon/nic.c const struct ef4_nic_reg *reg; reg 389 drivers/net/ethernet/sfc/falcon/nic.c for (reg = ef4_nic_regs; reg 390 drivers/net/ethernet/sfc/falcon/nic.c reg < ef4_nic_regs + ARRAY_SIZE(ef4_nic_regs); reg 391 drivers/net/ethernet/sfc/falcon/nic.c reg++) { reg 392 drivers/net/ethernet/sfc/falcon/nic.c if (efx->type->revision >= reg->min_revision && reg 393 drivers/net/ethernet/sfc/falcon/nic.c efx->type->revision <= reg->max_revision) { reg 394 drivers/net/ethernet/sfc/falcon/nic.c ef4_reado(efx, (ef4_oword_t *)buf, reg->offset); reg 76 drivers/net/ethernet/sfc/falcon/qt202x_phy.c int reg, old_counter = 0; reg 81 drivers/net/ethernet/sfc/falcon/qt202x_phy.c reg = ef4_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG); reg 82 drivers/net/ethernet/sfc/falcon/qt202x_phy.c if (reg < 0) reg 83 drivers/net/ethernet/sfc/falcon/qt202x_phy.c return reg; reg 84 drivers/net/ethernet/sfc/falcon/qt202x_phy.c counter = ((reg >> PCS_FW_HEARTB_LBN) & reg 108 drivers/net/ethernet/sfc/falcon/qt202x_phy.c int reg; reg 112 drivers/net/ethernet/sfc/falcon/qt202x_phy.c reg = ef4_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG); reg 113 drivers/net/ethernet/sfc/falcon/qt202x_phy.c if (reg < 0) reg 114 drivers/net/ethernet/sfc/falcon/qt202x_phy.c return reg; reg 115 drivers/net/ethernet/sfc/falcon/qt202x_phy.c if ((reg & reg 217 drivers/net/ethernet/sfc/falcon/qt202x_phy.c int reg, rc, i; reg 233 drivers/net/ethernet/sfc/falcon/qt202x_phy.c reg = ef4_mdio_read(efx, 1, 0xc319); reg 234 drivers/net/ethernet/sfc/falcon/qt202x_phy.c if ((reg & 0x0038) == phy_op_mode) reg 222 drivers/net/ethernet/sfc/falcon/tenxpress.c int rc, reg; reg 230 drivers/net/ethernet/sfc/falcon/tenxpress.c reg = ef4_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); reg 231 drivers/net/ethernet/sfc/falcon/tenxpress.c reg |= (1 << PMA_PMD_EXT_SSR_LBN); reg 232 drivers/net/ethernet/sfc/falcon/tenxpress.c ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); reg 257 drivers/net/ethernet/sfc/falcon/tenxpress.c int reg; reg 263 drivers/net/ethernet/sfc/falcon/tenxpress.c reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1); reg 264 drivers/net/ethernet/sfc/falcon/tenxpress.c if (!(reg & MDIO_AN_STAT1_LPABLE)) reg 266 drivers/net/ethernet/sfc/falcon/tenxpress.c bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE); reg 278 drivers/net/ethernet/sfc/falcon/tenxpress.c reg = ef4_mdio_read(efx, MDIO_MMD_PMAPMD, reg 280 drivers/net/ethernet/sfc/falcon/tenxpress.c reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN); reg 282 drivers/net/ethernet/sfc/falcon/tenxpress.c reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN; reg 284 drivers/net/ethernet/sfc/falcon/tenxpress.c reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN; reg 292 drivers/net/ethernet/sfc/falcon/tenxpress.c PMA_PMD_LED_OVERR_REG, reg); reg 368 drivers/net/ethernet/sfc/falcon/tenxpress.c int reg; reg 371 drivers/net/ethernet/sfc/falcon/tenxpress.c reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN); reg 372 drivers/net/ethernet/sfc/falcon/tenxpress.c ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); reg 390 drivers/net/ethernet/sfc/falcon/tenxpress.c int reg; reg 394 drivers/net/ethernet/sfc/falcon/tenxpress.c reg = (PMA_PMD_LED_OFF << PMA_PMD_LED_TX_LBN) | reg 399 drivers/net/ethernet/sfc/falcon/tenxpress.c reg = (PMA_PMD_LED_ON << PMA_PMD_LED_TX_LBN) | reg 404 drivers/net/ethernet/sfc/falcon/tenxpress.c reg = SFX7101_PMA_PMD_LED_DEFAULT; reg 408 drivers/net/ethernet/sfc/falcon/tenxpress.c ef4_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg); reg 444 drivers/net/ethernet/sfc/falcon/tenxpress.c int reg; reg 446 drivers/net/ethernet/sfc/falcon/tenxpress.c reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL); reg 447 drivers/net/ethernet/sfc/falcon/tenxpress.c if (reg & MDIO_AN_10GBT_CTRL_ADV10G) reg 449 drivers/net/ethernet/sfc/falcon/tenxpress.c reg = ef4_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); reg 450 drivers/net/ethernet/sfc/falcon/tenxpress.c if (reg & MDIO_AN_10GBT_STAT_LP10G) reg 106 drivers/net/ethernet/sfc/farch.c efx_oword_t mask, imask, original, reg, buf; reg 121 drivers/net/ethernet/sfc/farch.c EFX_AND_OWORD(reg, original, mask); reg 122 drivers/net/ethernet/sfc/farch.c EFX_SET_OWORD32(reg, j, j, 1); reg 124 drivers/net/ethernet/sfc/farch.c efx_writeo(efx, ®, address); reg 127 drivers/net/ethernet/sfc/farch.c if (efx_masked_compare_oword(®, &buf, &mask)) reg 131 drivers/net/ethernet/sfc/farch.c EFX_OR_OWORD(reg, original, mask); reg 132 drivers/net/ethernet/sfc/farch.c EFX_SET_OWORD32(reg, j, j, 0); reg 134 drivers/net/ethernet/sfc/farch.c efx_writeo(efx, ®, address); reg 137 drivers/net/ethernet/sfc/farch.c if (efx_masked_compare_oword(®, &buf, &mask)) reg 149 drivers/net/ethernet/sfc/farch.c " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg), reg 284 drivers/net/ethernet/sfc/farch.c efx_dword_t reg; reg 287 drivers/net/ethernet/sfc/farch.c EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr); reg 288 drivers/net/ethernet/sfc/farch.c efx_writed_page(tx_queue->efx, ®, reg 297 drivers/net/ethernet/sfc/farch.c efx_oword_t reg; reg 303 drivers/net/ethernet/sfc/farch.c EFX_POPULATE_OWORD_2(reg, FRF_AZ_TX_DESC_PUSH_CMD, true, reg 305 drivers/net/ethernet/sfc/farch.c reg.qword[0] = *txd; reg 306 drivers/net/ethernet/sfc/farch.c efx_writeo_page(tx_queue->efx, ®, reg 383 drivers/net/ethernet/sfc/farch.c efx_oword_t reg; reg 389 drivers/net/ethernet/sfc/farch.c EFX_POPULATE_OWORD_10(reg, reg 403 drivers/net/ethernet/sfc/farch.c EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_IP_CHKSM_DIS, !csum); reg 404 drivers/net/ethernet/sfc/farch.c EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_TCP_CHKSM_DIS, !csum); reg 406 drivers/net/ethernet/sfc/farch.c efx_writeo_table(efx, ®, efx->type->txd_ptr_tbl_base, reg 409 drivers/net/ethernet/sfc/farch.c EFX_POPULATE_OWORD_1(reg, reg 414 drivers/net/ethernet/sfc/farch.c efx_writeo_table(efx, ®, FR_BZ_TX_PACE_TBL, tx_queue->queue); reg 480 drivers/net/ethernet/sfc/farch.c efx_dword_t reg; reg 492 drivers/net/ethernet/sfc/farch.c EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr); reg 493 drivers/net/ethernet/sfc/farch.c efx_writed_page(efx, ®, FR_AZ_RX_DESC_UPD_DWORD_P0, reg 773 drivers/net/ethernet/sfc/farch.c efx_dword_t reg; reg 776 drivers/net/ethernet/sfc/farch.c EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, reg 782 drivers/net/ethernet/sfc/farch.c efx_writed(efx, ®, reg 1345 drivers/net/ethernet/sfc/farch.c efx_oword_t reg; reg 1353 drivers/net/ethernet/sfc/farch.c EFX_POPULATE_OWORD_3(reg, reg 1357 drivers/net/ethernet/sfc/farch.c efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, channel->channel); reg 1366 drivers/net/ethernet/sfc/farch.c EFX_POPULATE_OWORD_3(reg, reg 1370 drivers/net/ethernet/sfc/farch.c efx_writeo_table(efx, ®, efx->type->evq_ptr_tbl_base, reg 1378 drivers/net/ethernet/sfc/farch.c efx_oword_t reg; reg 1382 drivers/net/ethernet/sfc/farch.c EFX_ZERO_OWORD(reg); reg 1383 drivers/net/ethernet/sfc/farch.c efx_writeo_table(efx, ®, efx->type->evq_ptr_tbl_base, reg 1385 drivers/net/ethernet/sfc/farch.c efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, channel->channel); reg 1475 drivers/net/ethernet/sfc/farch.c efx_oword_t reg; reg 1476 drivers/net/ethernet/sfc/farch.c efx_reado(efx, ®, FR_AZ_MEM_STAT); reg 1479 drivers/net/ethernet/sfc/farch.c EFX_OWORD_VAL(reg)); reg 1517 drivers/net/ethernet/sfc/farch.c efx_dword_t reg; reg 1522 drivers/net/ethernet/sfc/farch.c efx_readd(efx, ®, FR_BZ_INT_ISR0); reg 1523 drivers/net/ethernet/sfc/farch.c queues = EFX_EXTRACT_DWORD(reg, 0, 31); reg 1529 drivers/net/ethernet/sfc/farch.c if (EFX_DWORD_IS_ALL_ONES(reg) && efx_try_recovery(efx) && reg 1582 drivers/net/ethernet/sfc/farch.c irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); reg 80 drivers/net/ethernet/sfc/io.h unsigned int reg) reg 82 drivers/net/ethernet/sfc/io.h __raw_writeq((__force u64)value, efx->membase + reg); reg 84 drivers/net/ethernet/sfc/io.h static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg) reg 86 drivers/net/ethernet/sfc/io.h return (__force __le64)__raw_readq(efx->membase + reg); reg 91 drivers/net/ethernet/sfc/io.h unsigned int reg) reg 93 drivers/net/ethernet/sfc/io.h __raw_writel((__force u32)value, efx->membase + reg); reg 95 drivers/net/ethernet/sfc/io.h static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg) reg 97 drivers/net/ethernet/sfc/io.h return (__force __le32)__raw_readl(efx->membase + reg); reg 102 drivers/net/ethernet/sfc/io.h unsigned int reg) reg 107 drivers/net/ethernet/sfc/io.h "writing register %x with " EFX_OWORD_FMT "\n", reg, reg 112 drivers/net/ethernet/sfc/io.h _efx_writeq(efx, value->u64[0], reg + 0); reg 113 drivers/net/ethernet/sfc/io.h _efx_writeq(efx, value->u64[1], reg + 8); reg 115 drivers/net/ethernet/sfc/io.h _efx_writed(efx, value->u32[0], reg + 0); reg 116 drivers/net/ethernet/sfc/io.h _efx_writed(efx, value->u32[1], reg + 4); reg 117 drivers/net/ethernet/sfc/io.h _efx_writed(efx, value->u32[2], reg + 8); reg 118 drivers/net/ethernet/sfc/io.h _efx_writed(efx, value->u32[3], reg + 12); reg 146 drivers/net/ethernet/sfc/io.h unsigned int reg) reg 150 drivers/net/ethernet/sfc/io.h reg, EFX_DWORD_VAL(*value)); reg 153 drivers/net/ethernet/sfc/io.h _efx_writed(efx, value->u32[0], reg); reg 158 drivers/net/ethernet/sfc/io.h unsigned int reg) reg 163 drivers/net/ethernet/sfc/io.h value->u32[0] = _efx_readd(efx, reg + 0); reg 164 drivers/net/ethernet/sfc/io.h value->u32[1] = _efx_readd(efx, reg + 4); reg 165 drivers/net/ethernet/sfc/io.h value->u32[2] = _efx_readd(efx, reg + 8); reg 166 drivers/net/ethernet/sfc/io.h value->u32[3] = _efx_readd(efx, reg + 12); reg 170 drivers/net/ethernet/sfc/io.h "read from register %x, got " EFX_OWORD_FMT "\n", reg, reg 197 drivers/net/ethernet/sfc/io.h unsigned int reg) reg 199 drivers/net/ethernet/sfc/io.h value->u32[0] = _efx_readd(efx, reg); reg 202 drivers/net/ethernet/sfc/io.h reg, EFX_DWORD_VAL(*value)); reg 208 drivers/net/ethernet/sfc/io.h unsigned int reg, unsigned int index) reg 210 drivers/net/ethernet/sfc/io.h efx_writeo(efx, value, reg + index * sizeof(efx_oword_t)); reg 215 drivers/net/ethernet/sfc/io.h unsigned int reg, unsigned int index) reg 217 drivers/net/ethernet/sfc/io.h efx_reado(efx, value, reg + index * sizeof(efx_oword_t)); reg 225 drivers/net/ethernet/sfc/io.h unsigned int reg) reg 227 drivers/net/ethernet/sfc/io.h return page * efx->vi_stride + reg; reg 232 drivers/net/ethernet/sfc/io.h unsigned int reg, unsigned int page) reg 234 drivers/net/ethernet/sfc/io.h reg = efx_paged_reg(efx, page, reg); reg 237 drivers/net/ethernet/sfc/io.h "writing register %x with " EFX_OWORD_FMT "\n", reg, reg 241 drivers/net/ethernet/sfc/io.h _efx_writeq(efx, value->u64[0], reg + 0); reg 242 drivers/net/ethernet/sfc/io.h _efx_writeq(efx, value->u64[1], reg + 8); reg 244 drivers/net/ethernet/sfc/io.h _efx_writed(efx, value->u32[0], reg + 0); reg 245 drivers/net/ethernet/sfc/io.h _efx_writed(efx, value->u32[1], reg + 4); reg 246 drivers/net/ethernet/sfc/io.h _efx_writed(efx, value->u32[2], reg + 8); reg 247 drivers/net/ethernet/sfc/io.h _efx_writed(efx, value->u32[3], reg + 12); reg 250 drivers/net/ethernet/sfc/io.h #define efx_writeo_page(efx, value, reg, page) \ reg 252 drivers/net/ethernet/sfc/io.h reg + \ reg 253 drivers/net/ethernet/sfc/io.h BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \ reg 261 drivers/net/ethernet/sfc/io.h unsigned int reg, unsigned int page) reg 263 drivers/net/ethernet/sfc/io.h efx_writed(efx, value, efx_paged_reg(efx, page, reg)); reg 265 drivers/net/ethernet/sfc/io.h #define efx_writed_page(efx, value, reg, page) \ reg 267 drivers/net/ethernet/sfc/io.h reg + \ reg 268 drivers/net/ethernet/sfc/io.h BUILD_BUG_ON_ZERO((reg) != 0x400 && \ reg 269 drivers/net/ethernet/sfc/io.h (reg) != 0x420 && \ reg 270 drivers/net/ethernet/sfc/io.h (reg) != 0x830 && \ reg 271 drivers/net/ethernet/sfc/io.h (reg) != 0x83c && \ reg 272 drivers/net/ethernet/sfc/io.h (reg) != 0xa18 && \ reg 273 drivers/net/ethernet/sfc/io.h (reg) != 0xa1c), \ reg 282 drivers/net/ethernet/sfc/io.h unsigned int reg, reg 289 drivers/net/ethernet/sfc/io.h efx_writed(efx, value, efx_paged_reg(efx, page, reg)); reg 292 drivers/net/ethernet/sfc/io.h efx_writed(efx, value, efx_paged_reg(efx, page, reg)); reg 295 drivers/net/ethernet/sfc/io.h #define efx_writed_page_locked(efx, value, reg, page) \ reg 297 drivers/net/ethernet/sfc/io.h reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \ reg 370 drivers/net/ethernet/sfc/nic.c const struct efx_nic_reg *reg; reg 374 drivers/net/ethernet/sfc/nic.c for (reg = efx_nic_regs; reg 375 drivers/net/ethernet/sfc/nic.c reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs); reg 376 drivers/net/ethernet/sfc/nic.c reg++) reg 377 drivers/net/ethernet/sfc/nic.c if (efx->type->revision >= reg->min_revision && reg 378 drivers/net/ethernet/sfc/nic.c efx->type->revision <= reg->max_revision) reg 393 drivers/net/ethernet/sfc/nic.c const struct efx_nic_reg *reg; reg 396 drivers/net/ethernet/sfc/nic.c for (reg = efx_nic_regs; reg 397 drivers/net/ethernet/sfc/nic.c reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs); reg 398 drivers/net/ethernet/sfc/nic.c reg++) { reg 399 drivers/net/ethernet/sfc/nic.c if (efx->type->revision >= reg->min_revision && reg 400 drivers/net/ethernet/sfc/nic.c efx->type->revision <= reg->max_revision) { reg 401 drivers/net/ethernet/sfc/nic.c efx_reado(efx, (efx_oword_t *)buf, reg->offset); reg 259 drivers/net/ethernet/sfc/siena.c efx_oword_t reg; reg 279 drivers/net/ethernet/sfc/siena.c efx_reado(efx, ®, FR_AZ_CS_DEBUG); reg 280 drivers/net/ethernet/sfc/siena.c efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1; reg 793 drivers/net/ethernet/sfc/siena.c efx_dword_t reg; reg 796 drivers/net/ethernet/sfc/siena.c efx_readd(efx, ®, addr); reg 797 drivers/net/ethernet/sfc/siena.c value = EFX_DWORD_FIELD(reg, EFX_DWORD_0); reg 802 drivers/net/ethernet/sfc/siena.c EFX_ZERO_DWORD(reg); reg 803 drivers/net/ethernet/sfc/siena.c efx_writed(efx, ®, addr); reg 231 drivers/net/ethernet/sfc/siena_sriov.c efx_oword_t reg; reg 233 drivers/net/ethernet/sfc/siena_sriov.c EFX_POPULATE_OWORD_2(reg, reg 236 drivers/net/ethernet/sfc/siena_sriov.c efx_writeo(efx, ®, FR_CZ_USR_EV_CFG); reg 536 drivers/net/ethernet/sfc/siena_sriov.c efx_oword_t reg; reg 549 drivers/net/ethernet/sfc/siena_sriov.c EFX_POPULATE_OWORD_3(reg, reg 553 drivers/net/ethernet/sfc/siena_sriov.c efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, abs_evq); reg 554 drivers/net/ethernet/sfc/siena_sriov.c EFX_POPULATE_OWORD_3(reg, reg 558 drivers/net/ethernet/sfc/siena_sriov.c efx_writeo_table(efx, ®, FR_BZ_EVQ_PTR_TBL, abs_evq); reg 578 drivers/net/ethernet/sfc/siena_sriov.c efx_oword_t reg; reg 595 drivers/net/ethernet/sfc/siena_sriov.c EFX_POPULATE_OWORD_6(reg, reg 604 drivers/net/ethernet/sfc/siena_sriov.c efx_writeo_table(efx, ®, FR_BZ_RX_DESC_PTR_TBL, reg 619 drivers/net/ethernet/sfc/siena_sriov.c efx_oword_t reg; reg 641 drivers/net/ethernet/sfc/siena_sriov.c EFX_POPULATE_OWORD_8(reg, reg 650 drivers/net/ethernet/sfc/siena_sriov.c efx_writeo_table(efx, ®, FR_BZ_TX_DESC_PTR_TBL, reg 679 drivers/net/ethernet/sfc/siena_sriov.c efx_oword_t reg; reg 698 drivers/net/ethernet/sfc/siena_sriov.c EFX_POPULATE_OWORD_2(reg, reg 702 drivers/net/ethernet/sfc/siena_sriov.c efx_writeo(efx, ®, FR_AZ_TX_FLUSH_DESCQ); reg 739 drivers/net/ethernet/sfc/siena_sriov.c EFX_ZERO_OWORD(reg); reg 741 drivers/net/ethernet/sfc/siena_sriov.c efx_writeo_table(efx, ®, FR_BZ_RX_DESC_PTR_TBL, reg 743 drivers/net/ethernet/sfc/siena_sriov.c efx_writeo_table(efx, ®, FR_BZ_TX_DESC_PTR_TBL, reg 745 drivers/net/ethernet/sfc/siena_sriov.c efx_writeo_table(efx, ®, FR_BZ_EVQ_PTR_TBL, reg 747 drivers/net/ethernet/sfc/siena_sriov.c efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, reg 946 drivers/net/ethernet/sfc/siena_sriov.c efx_oword_t reg; reg 991 drivers/net/ethernet/sfc/siena_sriov.c EFX_POPULATE_OWORD_3(reg, reg 995 drivers/net/ethernet/sfc/siena_sriov.c efx_writeo_table(efx, ®, FR_BZ_TIMER_TBL, abs_evq); reg 996 drivers/net/ethernet/sfc/siena_sriov.c EFX_POPULATE_OWORD_3(reg, reg 1000 drivers/net/ethernet/sfc/siena_sriov.c efx_writeo_table(efx, ®, FR_BZ_EVQ_PTR_TBL, abs_evq); reg 316 drivers/net/ethernet/sgi/ioc3-eth.c u64 reg; reg 318 drivers/net/ethernet/sgi/ioc3-eth.c reg = nic_find(mcr, &save); reg 320 drivers/net/ethernet/sgi/ioc3-eth.c switch (reg & 0xff) { reg 337 drivers/net/ethernet/sgi/ioc3-eth.c nic_write_byte(mcr, (reg >> (i << 3)) & 0xff); reg 339 drivers/net/ethernet/sgi/ioc3-eth.c reg >>= 8; /* Shift out type. */ reg 341 drivers/net/ethernet/sgi/ioc3-eth.c serial[i] = reg & 0xff; reg 342 drivers/net/ethernet/sgi/ioc3-eth.c reg >>= 8; reg 344 drivers/net/ethernet/sgi/ioc3-eth.c crc = reg & 0xff; reg 433 drivers/net/ethernet/sgi/ioc3-eth.c static int ioc3_mdio_read(struct net_device *dev, int phy, int reg) reg 440 drivers/net/ethernet/sgi/ioc3-eth.c writel((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG, reg 448 drivers/net/ethernet/sgi/ioc3-eth.c static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data) reg 456 drivers/net/ethernet/sgi/ioc3-eth.c writel((phy << MICR_PHYADDR_SHIFT) | reg, ®s->micr); reg 342 drivers/net/ethernet/silan/sc92031.c static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg) reg 344 drivers/net/ethernet/silan/sc92031.c return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13; reg 347 drivers/net/ethernet/silan/sc92031.c static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val) reg 349 drivers/net/ethernet/silan/sc92031.c _sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11)); reg 74 drivers/net/ethernet/sis/sis190.c #define SIS_W8(reg, val) writeb ((val), ioaddr + (reg)) reg 75 drivers/net/ethernet/sis/sis190.c #define SIS_W16(reg, val) writew ((val), ioaddr + (reg)) reg 76 drivers/net/ethernet/sis/sis190.c #define SIS_W32(reg, val) writel ((val), ioaddr + (reg)) reg 77 drivers/net/ethernet/sis/sis190.c #define SIS_R8(reg) readb (ioaddr + (reg)) reg 78 drivers/net/ethernet/sis/sis190.c #define SIS_R16(reg) readw (ioaddr + (reg)) reg 79 drivers/net/ethernet/sis/sis190.c #define SIS_R32(reg) readl (ioaddr + (reg)) reg 383 drivers/net/ethernet/sis/sis190.c static void mdio_write(void __iomem *ioaddr, int phy_id, int reg, int val) reg 386 drivers/net/ethernet/sis/sis190.c (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift) | reg 390 drivers/net/ethernet/sis/sis190.c static int mdio_read(void __iomem *ioaddr, int phy_id, int reg) reg 393 drivers/net/ethernet/sis/sis190.c (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift)); reg 398 drivers/net/ethernet/sis/sis190.c static void __mdio_write(struct net_device *dev, int phy_id, int reg, int val) reg 402 drivers/net/ethernet/sis/sis190.c mdio_write(tp->mmio_addr, phy_id, reg, val); reg 405 drivers/net/ethernet/sis/sis190.c static int __mdio_read(struct net_device *dev, int phy_id, int reg) reg 409 drivers/net/ethernet/sis/sis190.c return mdio_read(tp->mmio_addr, phy_id, reg); reg 412 drivers/net/ethernet/sis/sis190.c static u16 mdio_read_latched(void __iomem *ioaddr, int phy_id, int reg) reg 414 drivers/net/ethernet/sis/sis190.c mdio_read(ioaddr, phy_id, reg); reg 415 drivers/net/ethernet/sis/sis190.c return mdio_read(ioaddr, phy_id, reg); reg 418 drivers/net/ethernet/sis/sis190.c static u16 sis190_read_eeprom(void __iomem *ioaddr, u32 reg) reg 426 drivers/net/ethernet/sis/sis190.c SIS_W32(ROMInterface, EEREQ | EEROP | (reg << 10)); reg 1358 drivers/net/ethernet/sis/sis190.c u16 reg[2][2] = { reg 1363 drivers/net/ethernet/sis/sis190.c p = (tp->features & F_HAS_RGMII) ? reg[0] : reg[1]; reg 1569 drivers/net/ethernet/sis/sis190.c static void sis190_set_rgmii(struct sis190_private *tp, u8 reg) reg 1571 drivers/net/ethernet/sis/sis190.c tp->features |= (reg & 0x80) ? F_HAS_RGMII : 0; reg 1622 drivers/net/ethernet/sis/sis190.c u8 reg, tmp8; reg 1643 drivers/net/ethernet/sis/sis190.c reg = (tmp8 & ~0x02); reg 1644 drivers/net/ethernet/sis/sis190.c pci_write_config_byte(isa_bridge, 0x48, reg); reg 1646 drivers/net/ethernet/sis/sis190.c pci_read_config_byte(isa_bridge, 0x48, ®); reg 1654 drivers/net/ethernet/sis/sis190.c reg = inb(0x79); reg 1656 drivers/net/ethernet/sis/sis190.c sis190_set_rgmii(tp, reg); reg 1700 drivers/net/ethernet/sis/sis190.c u8 reg; reg 1702 drivers/net/ethernet/sis/sis190.c pci_read_config_byte(pdev, 0x73, ®); reg 1704 drivers/net/ethernet/sis/sis190.c if (reg & 0x00000001) reg 209 drivers/net/ethernet/sis/sis900.c #define sw32(reg, val) iowrite32(val, ioaddr + (reg)) reg 210 drivers/net/ethernet/sis/sis900.c #define sw8(reg, val) iowrite8(val, ioaddr + (reg)) reg 211 drivers/net/ethernet/sis/sis900.c #define sr32(reg) ioread32(ioaddr + (reg)) reg 212 drivers/net/ethernet/sis/sis900.c #define sr16(reg) ioread16(ioaddr + (reg)) reg 293 drivers/net/ethernet/sis/sis900.c u8 reg; reg 304 drivers/net/ethernet/sis/sis900.c pci_read_config_byte(isa_bridge, 0x48, ®); reg 305 drivers/net/ethernet/sis/sis900.c pci_write_config_byte(isa_bridge, 0x48, reg | 0x40); reg 312 drivers/net/ethernet/sis/sis900.c pci_write_config_byte(isa_bridge, 0x48, reg & ~0x40); reg 185 drivers/net/ethernet/smsc/epic100.c #define ew16(reg, val) iowrite16(val, ioaddr + (reg)) reg 186 drivers/net/ethernet/smsc/epic100.c #define ew32(reg, val) iowrite32(val, ioaddr + (reg)) reg 187 drivers/net/ethernet/smsc/epic100.c #define er8(reg) ioread8(ioaddr + (reg)) reg 188 drivers/net/ethernet/smsc/epic100.c #define er16(reg) ioread16(ioaddr + (reg)) reg 189 drivers/net/ethernet/smsc/epic100.c #define er32(reg) ioread32(ioaddr + (reg)) reg 166 drivers/net/ethernet/smsc/smc911x.c unsigned int reg, timeout=0, resets=1, irq_cfg; reg 178 drivers/net/ethernet/smsc/smc911x.c reg = SMC_GET_PMT_CTRL(lp) & PMT_CTRL_READY_; reg 179 drivers/net/ethernet/smsc/smc911x.c } while (--timeout && !reg); reg 196 drivers/net/ethernet/smsc/smc911x.c reg = SMC_GET_HW_CFG(lp); reg 198 drivers/net/ethernet/smsc/smc911x.c if (reg & HW_CFG_SRST_TO_) { reg 203 drivers/net/ethernet/smsc/smc911x.c } while (--timeout && (reg & HW_CFG_SRST_)); reg 337 drivers/net/ethernet/smsc/smc911x.c unsigned int fifo_count, timeout, reg; reg 352 drivers/net/ethernet/smsc/smc911x.c reg = SMC_GET_RX_DP_CTRL(lp) & RX_DP_CTRL_FFWD_BUSY_; reg 353 drivers/net/ethernet/smsc/smc911x.c } while (--timeout && reg); reg 784 drivers/net/ethernet/smsc/smc911x.c unsigned int reg; reg 789 drivers/net/ethernet/smsc/smc911x.c reg = SMC_GET_PMT_CTRL(lp); reg 790 drivers/net/ethernet/smsc/smc911x.c reg &= ~0xfffff030; reg 791 drivers/net/ethernet/smsc/smc911x.c reg |= PMT_CTRL_PHY_RST_; reg 792 drivers/net/ethernet/smsc/smc911x.c SMC_SET_PMT_CTRL(lp, reg); reg 797 drivers/net/ethernet/smsc/smc911x.c reg = SMC_GET_PMT_CTRL(lp); reg 799 drivers/net/ethernet/smsc/smc911x.c if (!(reg & PMT_CTRL_PHY_RST_)) { reg 810 drivers/net/ethernet/smsc/smc911x.c return reg & PMT_CTRL_PHY_RST_; reg 1554 drivers/net/ethernet/smsc/smc911x.c u32 reg,i,j=0; reg 1563 drivers/net/ethernet/smsc/smc911x.c SMC_GET_MAC_CSR(lp, i, reg); reg 1565 drivers/net/ethernet/smsc/smc911x.c data[j++] = reg; reg 1569 drivers/net/ethernet/smsc/smc911x.c SMC_GET_MII(lp, i, lp->mii.phy_id, reg); reg 1571 drivers/net/ethernet/smsc/smc911x.c data[j++] = reg & 0xFFFF; reg 112 drivers/net/ethernet/smsc/smc911x.h static inline unsigned int SMC_inl(struct smc911x_local *lp, int reg) reg 114 drivers/net/ethernet/smsc/smc911x.h void __iomem *ioaddr = lp->base + reg; reg 126 drivers/net/ethernet/smsc/smc911x.h int reg) reg 128 drivers/net/ethernet/smsc/smc911x.h void __iomem *ioaddr = lp->base + reg; reg 144 drivers/net/ethernet/smsc/smc911x.h static inline void SMC_insl(struct smc911x_local *lp, int reg, reg 147 drivers/net/ethernet/smsc/smc911x.h void __iomem *ioaddr = lp->base + reg; reg 162 drivers/net/ethernet/smsc/smc911x.h static inline void SMC_outsl(struct smc911x_local *lp, int reg, reg 165 drivers/net/ethernet/smsc/smc911x.h void __iomem *ioaddr = lp->base + reg; reg 219 drivers/net/ethernet/smsc/smc911x.h int reg, struct dma_chan *dma, u_char *buf, int len) reg 225 drivers/net/ethernet/smsc/smc911x.h *((u32 *)buf) = SMC_inl(lp, reg); reg 251 drivers/net/ethernet/smsc/smc911x.h int reg, struct dma_chan *dma, u_char *buf, int len) reg 257 drivers/net/ethernet/smsc/smc911x.h SMC_outl(*((u32 *)buf), lp, reg); reg 99 drivers/net/ethernet/smsc/smc91x.h static inline void _SMC_outw_align4(u16 val, void __iomem *ioaddr, int reg, reg 104 drivers/net/ethernet/smsc/smc91x.h v |= readl(ioaddr + (reg & ~2)) & 0xffff; reg 105 drivers/net/ethernet/smsc/smc91x.h writel(v, ioaddr + (reg & ~2)); reg 107 drivers/net/ethernet/smsc/smc91x.h writew(val, ioaddr + reg); reg 325 drivers/net/ethernet/smsc/smc91x.h smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, reg 333 drivers/net/ethernet/smsc/smc91x.h readsl(ioaddr + reg, buf, len); reg 339 drivers/net/ethernet/smsc/smc91x.h *((u32 *)buf) = SMC_inl(ioaddr, reg); reg 347 drivers/net/ethernet/smsc/smc91x.h config.src_addr = lp->physaddr + reg; reg 348 drivers/net/ethernet/smsc/smc91x.h config.dst_addr = lp->physaddr + reg; reg 368 drivers/net/ethernet/smsc/smc91x.h smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, reg 376 drivers/net/ethernet/smsc/smc91x.h readsw(ioaddr + reg, buf, len); reg 382 drivers/net/ethernet/smsc/smc91x.h *((u16 *)buf) = SMC_inw(ioaddr, reg); reg 390 drivers/net/ethernet/smsc/smc91x.h config.src_addr = lp->physaddr + reg; reg 391 drivers/net/ethernet/smsc/smc91x.h config.dst_addr = lp->physaddr + reg; reg 417 drivers/net/ethernet/smsc/smc91x.h #define SMC_inl(ioaddr, reg) ({ BUG(); 0; }) reg 418 drivers/net/ethernet/smsc/smc91x.h #define SMC_outl(x, ioaddr, reg) BUG() reg 430 drivers/net/ethernet/smsc/smc91x.h #define SMC_outw(lp, x, ioaddr, reg) SMC_outw_b(x, ioaddr, reg) reg 431 drivers/net/ethernet/smsc/smc91x.h #define SMC_inw(ioaddr, reg) SMC_inw_b(ioaddr, reg) reg 444 drivers/net/ethernet/smsc/smc91x.h #define SMC_inb(ioaddr, reg) ({ BUG(); 0; }) reg 446 drivers/net/ethernet/smsc/smc91x.h #define SMC_outb(x, ioaddr, reg) BUG() reg 846 drivers/net/ethernet/smsc/smc91x.h #define SMC_REG(lp, reg, bank) \ reg 854 drivers/net/ethernet/smsc/smc91x.h reg<<SMC_IO_SHIFT; \ reg 857 drivers/net/ethernet/smsc/smc91x.h #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT) reg 76 drivers/net/ethernet/smsc/smsc911x.c u32 (*reg_read)(struct smsc911x_data *pdata, u32 reg); reg 77 drivers/net/ethernet/smsc/smsc911x.c void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val); reg 146 drivers/net/ethernet/smsc/smsc911x.c #define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift)) reg 148 drivers/net/ethernet/smsc/smsc911x.c static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg) reg 151 drivers/net/ethernet/smsc/smsc911x.c return readl(pdata->ioaddr + reg); reg 154 drivers/net/ethernet/smsc/smsc911x.c return ((readw(pdata->ioaddr + reg) & 0xFFFF) | reg 155 drivers/net/ethernet/smsc/smsc911x.c ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16)); reg 162 drivers/net/ethernet/smsc/smsc911x.c __smsc911x_reg_read_shift(struct smsc911x_data *pdata, u32 reg) reg 165 drivers/net/ethernet/smsc/smsc911x.c return readl(pdata->ioaddr + __smsc_shift(pdata, reg)); reg 169 drivers/net/ethernet/smsc/smsc911x.c __smsc_shift(pdata, reg)) & 0xFFFF) | reg 171 drivers/net/ethernet/smsc/smsc911x.c __smsc_shift(pdata, reg + 2)) & 0xFFFF) << 16); reg 177 drivers/net/ethernet/smsc/smsc911x.c static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg) reg 183 drivers/net/ethernet/smsc/smsc911x.c data = pdata->ops->reg_read(pdata, reg); reg 189 drivers/net/ethernet/smsc/smsc911x.c static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg, reg 193 drivers/net/ethernet/smsc/smsc911x.c writel(val, pdata->ioaddr + reg); reg 198 drivers/net/ethernet/smsc/smsc911x.c writew(val & 0xFFFF, pdata->ioaddr + reg); reg 199 drivers/net/ethernet/smsc/smsc911x.c writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2); reg 207 drivers/net/ethernet/smsc/smsc911x.c __smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val) reg 210 drivers/net/ethernet/smsc/smsc911x.c writel(val, pdata->ioaddr + __smsc_shift(pdata, reg)); reg 216 drivers/net/ethernet/smsc/smsc911x.c pdata->ioaddr + __smsc_shift(pdata, reg)); reg 218 drivers/net/ethernet/smsc/smsc911x.c pdata->ioaddr + __smsc_shift(pdata, reg + 2)); reg 225 drivers/net/ethernet/smsc/smsc911x.c static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg, reg 231 drivers/net/ethernet/smsc/smsc911x.c pdata->ops->reg_write(pdata, reg, val); reg 558 drivers/net/ethernet/smsc/smsc911x.c int i, reg; reg 565 drivers/net/ethernet/smsc/smsc911x.c reg = -EIO; reg 576 drivers/net/ethernet/smsc/smsc911x.c reg = smsc911x_mac_read(pdata, MII_DATA); reg 581 drivers/net/ethernet/smsc/smsc911x.c reg = -EIO; reg 585 drivers/net/ethernet/smsc/smsc911x.c return reg; reg 595 drivers/net/ethernet/smsc/smsc911x.c int i, reg; reg 602 drivers/net/ethernet/smsc/smsc911x.c reg = -EIO; reg 617 drivers/net/ethernet/smsc/smsc911x.c reg = 0; reg 622 drivers/net/ethernet/smsc/smsc911x.c reg = -EIO; reg 626 drivers/net/ethernet/smsc/smsc911x.c return reg; reg 108 drivers/net/ethernet/smsc/smsc9420.c int i, reg = -EIO; reg 127 drivers/net/ethernet/smsc/smsc9420.c reg = (u16)smsc9420_reg_read(pd, MII_DATA); reg 137 drivers/net/ethernet/smsc/smsc9420.c return reg; reg 146 drivers/net/ethernet/smsc/smsc9420.c int i, reg = -EIO; reg 168 drivers/net/ethernet/smsc/smsc9420.c reg = 0; reg 178 drivers/net/ethernet/smsc/smsc9420.c return reg; reg 468 drivers/net/ethernet/socionext/netsec.c int phy_addr, int reg, u16 val) reg 477 drivers/net/ethernet/socionext/netsec.c reg << NETSEC_GMAC_GAR_REG_SHIFT_GR | reg 1327 drivers/net/ethernet/socionext/netsec.c static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg, reg 1339 drivers/net/ethernet/socionext/netsec.c netsec_write(priv, reg, readl(ucode + i * 4)); reg 27 drivers/net/ethernet/stmicro/stmmac/dwmac-anarion.c static uint32_t gmac_read_reg(struct anarion_gmac *gmac, uint8_t reg) reg 29 drivers/net/ethernet/stmicro/stmmac/dwmac-anarion.c return readl((void *)(gmac->ctl_block + reg)); reg 32 drivers/net/ethernet/stmicro/stmmac/dwmac-anarion.c static void gmac_write_reg(struct anarion_gmac *gmac, uint8_t reg, uint32_t val) reg 34 drivers/net/ethernet/stmicro/stmmac/dwmac-anarion.c writel(val, (void *)(gmac->ctl_block + reg)); reg 32 drivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c struct regmap *reg; reg 46 drivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c reg = syscon_regmap_lookup_by_compatible("nxp,lpc1850-creg"); reg 47 drivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c if (IS_ERR(reg)) { reg 49 drivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c ret = PTR_ERR(reg); reg 63 drivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c regmap_update_bits(reg, LPC18XX_CREG_CREG6, reg 22 drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c void __iomem *reg; reg 30 drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c val = readl(dwmac->reg); reg 41 drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c writel(val, dwmac->reg); reg 65 drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c dwmac->reg = devm_platform_ioremap_resource(pdev, 1); reg 66 drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c if (IS_ERR(dwmac->reg)) { reg 67 drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c ret = PTR_ERR(dwmac->reg); reg 72 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, reg 77 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c data = readl(dwmac->regs + reg); reg 81 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c writel(data, dwmac->regs + reg); reg 145 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0; reg 155 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c clk_configs->m250_div.reg = dwmac->regs + PRG_ETH0; reg 177 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c clk_configs->rgmii_tx_en.reg = dwmac->regs + PRG_ETH0; reg 542 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c unsigned int reg; reg 549 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : reg 552 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c regmap_write(bsp_priv->grf, reg, reg 582 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c unsigned int reg; reg 589 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : reg 593 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c regmap_write(bsp_priv->grf, reg, reg 597 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c regmap_write(bsp_priv->grf, reg, reg 164 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c u32 reg = dwmac->ctrl_reg; reg 193 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c regmap_update_bits(dwmac->regmap, reg, STIH4XX_RETIME_SRC_MASK, reg 200 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c u32 reg = dwmac->ctrl_reg; reg 224 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c regmap_update_bits(dwmac->regmap, reg, STID127_RETIME_SRC_MASK, val); reg 231 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c u32 reg = dwmac->ctrl_reg; reg 235 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c regmap_update_bits(regmap, reg, EN_MASK, EN); reg 237 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK, phy_intf_sels[iface]); reg 240 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c regmap_update_bits(regmap, reg, ENMII_MASK, val); reg 177 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c u32 reg = dwmac->mode_reg; reg 214 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c ret = regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET, reg 218 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c return regmap_update_bits(dwmac->regmap, reg, reg 225 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c u32 reg = dwmac->mode_reg; reg 244 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c return regmap_update_bits(dwmac->regmap, reg, reg 82 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c .reg = 0x30, reg 89 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c .reg = 0x164, reg 169 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8) reg 170 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8) reg 816 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c u32 reg, val; reg 821 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c regmap_field_read(gmac->regmap_field, ®); reg 825 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT; reg 831 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN; reg 875 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c u32 reg, val; reg 883 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c reg = gmac->variant->default_syscon_value; reg 884 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c if (reg != val) reg 887 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c val, reg); reg 891 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c reg |= H3_EPHY_LED_POL; reg 893 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c reg &= ~H3_EPHY_LED_POL; reg 896 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c reg |= H3_EPHY_CLK_SEL; reg 906 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c reg |= 1 << H3_EPHY_ADDR_SHIFT; reg 911 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c reg &= ~H3_EPHY_SELECT; reg 922 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c reg &= ~(gmac->variant->tx_delay_max << reg 924 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c reg |= (val << SYSCON_ETXDC_SHIFT); reg 940 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c reg &= ~(gmac->variant->rx_delay_max << reg 942 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c reg |= (val << SYSCON_ERXDC_SHIFT); reg 951 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT); reg 953 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c reg &= ~SYSCON_RMII_EN; reg 963 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII; reg 966 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII; reg 974 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c regmap_field_write(gmac->regmap_field, reg); reg 981 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c u32 reg = gmac->variant->default_syscon_value; reg 983 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c regmap_field_write(gmac->regmap_field, reg); reg 79 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_ADDR_HIGH(reg) (((reg > 15) ? 0x00000800 : 0x00000040) + \ reg 80 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h (reg * 8)) reg 81 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h #define GMAC_ADDR_LOW(reg) (((reg > 15) ? 0x00000804 : 0x00000044) + \ reg 82 drivers/net/ethernet/stmicro/stmmac/dwmac1000.h (reg * 8)) reg 202 drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c int reg = 1; reg 207 drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c GMAC_ADDR_HIGH(reg), reg 208 drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c GMAC_ADDR_LOW(reg)); reg 209 drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c reg++; reg 212 drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c while (reg < perfect_addr_number) { reg 213 drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c writel(0, ioaddr + GMAC_ADDR_HIGH(reg)); reg 214 drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c writel(0, ioaddr + GMAC_ADDR_LOW(reg)); reg 215 drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c reg++; reg 44 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8) reg 45 drivers/net/ethernet/stmicro/stmmac/dwmac4.h #define GMAC_ADDR_LOW(reg) (0x304 + reg * 8) reg 458 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c int reg = 1; reg 461 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c dwmac4_set_umac_addr(hw, ha->addr, reg); reg 462 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c reg++; reg 465 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c while (reg < GMAC_MAX_PERFECT_ADDRESSES) { reg 466 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c writel(0, ioaddr + GMAC_ADDR_HIGH(reg)); reg 467 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c writel(0, ioaddr + GMAC_ADDR_LOW(reg)); reg 468 drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c reg++; reg 99 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c u32 value, reg; reg 101 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c reg = (queue < 4) ? XGMAC_RXQ_CTRL2 : XGMAC_RXQ_CTRL3; reg 105 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c value = readl(ioaddr + reg); reg 109 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c writel(value, ioaddr + reg); reg 116 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c u32 value, reg; reg 118 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c reg = (queue < 4) ? XGMAC_TC_PRTY_MAP0 : XGMAC_TC_PRTY_MAP1; reg 122 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c value = readl(ioaddr + reg); reg 126 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c writel(value, ioaddr + reg); reg 201 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c u32 value, reg; reg 203 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c reg = (queue < 4) ? XGMAC_MTL_RXQ_DMA_MAP0 : XGMAC_MTL_RXQ_DMA_MAP1; reg 207 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c value = readl(ioaddr + reg); reg 211 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c writel(value, ioaddr + reg); reg 480 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c int reg = 1; reg 483 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c dwxgmac2_set_umac_addr(hw, ha->addr, reg); reg 484 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c reg++; reg 487 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c for ( ; reg < XGMAC_ADDR_MAX; reg++) { reg 488 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c writel(0, ioaddr + XGMAC_ADDRx_HIGH(reg)); reg 489 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c writel(0, ioaddr + XGMAC_ADDRx_LOW(reg)); reg 1168 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c u8 reg, u32 *data) reg 1178 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c value = ((filter_no << XGMAC_IDDR_FNUM) | reg) << XGMAC_IDDR_SHIFT; reg 1191 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c u8 reg, u32 data) reg 1203 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c value = ((filter_no << XGMAC_IDDR_FNUM) | reg) << XGMAC_IDDR_SHIFT; reg 13 drivers/net/ethernet/stmicro/stmmac/hwif.c u32 reg = readl(priv->ioaddr + id_reg); reg 15 drivers/net/ethernet/stmicro/stmmac/hwif.c if (!reg) { reg 21 drivers/net/ethernet/stmicro/stmmac/hwif.c (unsigned int)(reg & GENMASK(15, 8)) >> 8, reg 22 drivers/net/ethernet/stmicro/stmmac/hwif.c (unsigned int)(reg & GENMASK(7, 0))); reg 23 drivers/net/ethernet/stmicro/stmmac/hwif.c return reg & GENMASK(7, 0); reg 342 drivers/net/ethernet/stmicro/stmmac/mmc_core.c static void dwxgmac_read_mmc_reg(void __iomem *addr, u32 reg, u32 *dest) reg 346 drivers/net/ethernet/stmicro/stmmac/mmc_core.c tmp += readl(addr + reg); reg 347 drivers/net/ethernet/stmicro/stmmac/mmc_core.c tmp += ((u64 )readl(addr + reg + 0x4)) << 32; reg 56 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h static inline void dwmac_pcs_isr(void __iomem *ioaddr, u32 reg, reg 60 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h u32 val = readl(ioaddr + GMAC_AN_STATUS(reg)); reg 84 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h static inline void dwmac_rane(void __iomem *ioaddr, u32 reg, bool restart) reg 86 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h u32 value = readl(ioaddr + GMAC_AN_CTRL(reg)); reg 91 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h writel(value, ioaddr + GMAC_AN_CTRL(reg)); reg 105 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h static inline void dwmac_ctrl_ane(void __iomem *ioaddr, u32 reg, bool ane, reg 108 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h u32 value = readl(ioaddr + GMAC_AN_CTRL(reg)); reg 123 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h writel(value, ioaddr + GMAC_AN_CTRL(reg)); reg 134 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h static inline void dwmac_get_adv_lp(void __iomem *ioaddr, u32 reg, reg 137 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h u32 value = readl(ioaddr + GMAC_ANE_ADV(reg)); reg 146 drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h value = readl(ioaddr + GMAC_ANE_LPA(reg)); reg 392 drivers/net/ethernet/sun/cassini.c static u16 cas_phy_read(struct cas *cp, int reg) reg 399 drivers/net/ethernet/sun/cassini.c cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg); reg 413 drivers/net/ethernet/sun/cassini.c static int cas_phy_write(struct cas *cp, int reg, u16 val) reg 420 drivers/net/ethernet/sun/cassini.c cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg); reg 51 drivers/net/ethernet/sun/niu.c static u64 readq(void __iomem *reg) reg 53 drivers/net/ethernet/sun/niu.c return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32); reg 56 drivers/net/ethernet/sun/niu.c static void writeq(u64 val, void __iomem *reg) reg 58 drivers/net/ethernet/sun/niu.c writel(val & 0xffffffff, reg); reg 59 drivers/net/ethernet/sun/niu.c writel(val >> 32, reg + 0x4UL); reg 72 drivers/net/ethernet/sun/niu.c #define nr64(reg) readq(np->regs + (reg)) reg 73 drivers/net/ethernet/sun/niu.c #define nw64(reg, val) writeq((val), np->regs + (reg)) reg 75 drivers/net/ethernet/sun/niu.c #define nr64_mac(reg) readq(np->mac_regs + (reg)) reg 76 drivers/net/ethernet/sun/niu.c #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg)) reg 78 drivers/net/ethernet/sun/niu.c #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg)) reg 79 drivers/net/ethernet/sun/niu.c #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg)) reg 81 drivers/net/ethernet/sun/niu.c #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg)) reg 82 drivers/net/ethernet/sun/niu.c #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg)) reg 84 drivers/net/ethernet/sun/niu.c #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg)) reg 85 drivers/net/ethernet/sun/niu.c #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg)) reg 101 drivers/net/ethernet/sun/niu.c static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg, reg 105 drivers/net/ethernet/sun/niu.c u64 val = nr64_mac(reg); reg 116 drivers/net/ethernet/sun/niu.c static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg, reg 122 drivers/net/ethernet/sun/niu.c nw64_mac(reg, bits); reg 123 drivers/net/ethernet/sun/niu.c err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay); reg 127 drivers/net/ethernet/sun/niu.c (unsigned long long)nr64_mac(reg)); reg 136 drivers/net/ethernet/sun/niu.c static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg, reg 140 drivers/net/ethernet/sun/niu.c u64 val = nr64_ipp(reg); reg 151 drivers/net/ethernet/sun/niu.c static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg, reg 158 drivers/net/ethernet/sun/niu.c val = nr64_ipp(reg); reg 160 drivers/net/ethernet/sun/niu.c nw64_ipp(reg, val); reg 162 drivers/net/ethernet/sun/niu.c err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay); reg 166 drivers/net/ethernet/sun/niu.c (unsigned long long)nr64_ipp(reg)); reg 175 drivers/net/ethernet/sun/niu.c static int __niu_wait_bits_clear(struct niu *np, unsigned long reg, reg 179 drivers/net/ethernet/sun/niu.c u64 val = nr64(reg); reg 195 drivers/net/ethernet/sun/niu.c static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg, reg 201 drivers/net/ethernet/sun/niu.c nw64(reg, bits); reg 202 drivers/net/ethernet/sun/niu.c err = __niu_wait_bits_clear(np, reg, bits, limit, delay); reg 206 drivers/net/ethernet/sun/niu.c (unsigned long long)nr64(reg)); reg 313 drivers/net/ethernet/sun/niu.c static int mdio_read(struct niu *np, int port, int dev, int reg) reg 317 drivers/net/ethernet/sun/niu.c nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); reg 326 drivers/net/ethernet/sun/niu.c static int mdio_write(struct niu *np, int port, int dev, int reg, int data) reg 330 drivers/net/ethernet/sun/niu.c nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); reg 343 drivers/net/ethernet/sun/niu.c static int mii_read(struct niu *np, int port, int reg) reg 345 drivers/net/ethernet/sun/niu.c nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg)); reg 349 drivers/net/ethernet/sun/niu.c static int mii_write(struct niu *np, int port, int reg, int data) reg 353 drivers/net/ethernet/sun/niu.c nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data)); reg 1291 drivers/net/ethernet/sun/niu.c static int bcm8704_user_dev3_readback(struct niu *np, int reg) reg 1293 drivers/net/ethernet/sun/niu.c int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg); reg 1296 drivers/net/ethernet/sun/niu.c err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg); reg 2655 drivers/net/ethernet/sun/niu.c unsigned long reg; reg 2662 drivers/net/ethernet/sun/niu.c reg = XMAC_ADDR_CMPEN; reg 2665 drivers/net/ethernet/sun/niu.c reg = BMAC_ADDR_CMPEN; reg 2669 drivers/net/ethernet/sun/niu.c val = nr64_mac(reg); reg 2674 drivers/net/ethernet/sun/niu.c nw64_mac(reg, val); reg 2679 drivers/net/ethernet/sun/niu.c static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg, reg 2682 drivers/net/ethernet/sun/niu.c u64 val = nr64_mac(reg); reg 2687 drivers/net/ethernet/sun/niu.c nw64_mac(reg, val); reg 2694 drivers/net/ethernet/sun/niu.c unsigned long reg; reg 2699 drivers/net/ethernet/sun/niu.c reg = XMAC_HOST_INFO(xmac_index); reg 2701 drivers/net/ethernet/sun/niu.c reg = BMAC_HOST_INFO(bmac_index); reg 2702 drivers/net/ethernet/sun/niu.c __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref); reg 2887 drivers/net/ethernet/sun/niu.c unsigned long reg; reg 2894 drivers/net/ethernet/sun/niu.c reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1); reg 2895 drivers/net/ethernet/sun/niu.c val = nr64(reg); reg 2900 drivers/net/ethernet/sun/niu.c nw64(reg, val); reg 2909 drivers/net/ethernet/sun/niu.c unsigned long reg; reg 2917 drivers/net/ethernet/sun/niu.c reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1); reg 2918 drivers/net/ethernet/sun/niu.c val = nr64(reg); reg 2921 drivers/net/ethernet/sun/niu.c nw64(reg, val); reg 2930 drivers/net/ethernet/sun/niu.c unsigned long reg; reg 2937 drivers/net/ethernet/sun/niu.c reg = L3_CLS(class - CLASS_CODE_USER_PROG1); reg 2938 drivers/net/ethernet/sun/niu.c val = nr64(reg); reg 2943 drivers/net/ethernet/sun/niu.c nw64(reg, val); reg 2952 drivers/net/ethernet/sun/niu.c unsigned long reg; reg 2962 drivers/net/ethernet/sun/niu.c reg = L3_CLS(class - CLASS_CODE_USER_PROG1); reg 2963 drivers/net/ethernet/sun/niu.c val = nr64(reg); reg 2971 drivers/net/ethernet/sun/niu.c nw64(reg, val); reg 3088 drivers/net/ethernet/sun/niu.c unsigned long reg; reg 3096 drivers/net/ethernet/sun/niu.c reg = FLW_PRT_SEL(partition); reg 3098 drivers/net/ethernet/sun/niu.c val = nr64(reg); reg 3104 drivers/net/ethernet/sun/niu.c nw64(reg, val); reg 7832 drivers/net/ethernet/sun/niu.c u64 val, reg, bit; reg 7835 drivers/net/ethernet/sun/niu.c reg = XMAC_CONFIG; reg 7838 drivers/net/ethernet/sun/niu.c reg = BMAC_XIF_CONFIG; reg 7842 drivers/net/ethernet/sun/niu.c val = nr64_mac(reg); reg 7847 drivers/net/ethernet/sun/niu.c nw64_mac(reg, val); reg 10006 drivers/net/ethernet/sun/niu.c const u32 *reg; reg 10011 drivers/net/ethernet/sun/niu.c reg = of_get_property(op->dev.of_node, "reg", NULL); reg 10012 drivers/net/ethernet/sun/niu.c if (!reg) { reg 10019 drivers/net/ethernet/sun/niu.c &niu_phys_ops, reg[0] & 0x1); reg 788 drivers/net/ethernet/sun/niu.h #define MDIO_ADDR_OP(port, dev, reg) \ reg 794 drivers/net/ethernet/sun/niu.h (reg << MIF_FRAME_OUTPUT_DATA_SHIFT)) reg 811 drivers/net/ethernet/sun/niu.h #define MII_READ_OP(port, reg) \ reg 815 drivers/net/ethernet/sun/niu.h (reg << MIF_FRAME_OUTPUT_REG_SHIFT) | \ reg 818 drivers/net/ethernet/sun/niu.h #define MII_WRITE_OP(port, reg, data) \ reg 822 drivers/net/ethernet/sun/niu.h (reg << MIF_FRAME_OUTPUT_REG_SHIFT) | \ reg 349 drivers/net/ethernet/sun/sunbmac.c int reg, unsigned short val) reg 353 drivers/net/ethernet/sun/sunbmac.c reg &= 0xff; reg 375 drivers/net/ethernet/sun/sunbmac.c put_tcvr_byte(bp, tregs, reg); reg 389 drivers/net/ethernet/sun/sunbmac.c int reg) reg 393 drivers/net/ethernet/sun/sunbmac.c reg &= 0xff; reg 414 drivers/net/ethernet/sun/sunbmac.c put_tcvr_byte(bp, tregs, reg); reg 117 drivers/net/ethernet/sun/sungem.c static u16 __sungem_phy_read(struct gem *gp, int phy_addr, int reg) reg 125 drivers/net/ethernet/sun/sungem.c cmd |= (reg << 18) & MIF_FRAME_REGAD; reg 143 drivers/net/ethernet/sun/sungem.c static inline int _sungem_phy_read(struct net_device *dev, int mii_id, int reg) reg 146 drivers/net/ethernet/sun/sungem.c return __sungem_phy_read(gp, mii_id, reg); reg 149 drivers/net/ethernet/sun/sungem.c static inline u16 sungem_phy_read(struct gem *gp, int reg) reg 151 drivers/net/ethernet/sun/sungem.c return __sungem_phy_read(gp, gp->mii_phy_addr, reg); reg 154 drivers/net/ethernet/sun/sungem.c static void __sungem_phy_write(struct gem *gp, int phy_addr, int reg, u16 val) reg 162 drivers/net/ethernet/sun/sungem.c cmd |= (reg << 18) & MIF_FRAME_REGAD; reg 176 drivers/net/ethernet/sun/sungem.c static inline void _sungem_phy_write(struct net_device *dev, int mii_id, int reg, int val) reg 179 drivers/net/ethernet/sun/sungem.c __sungem_phy_write(gp, mii_id, reg, val & 0xffff); reg 182 drivers/net/ethernet/sun/sungem.c static inline void sungem_phy_write(struct gem *gp, int reg, u16 val) reg 184 drivers/net/ethernet/sun/sungem.c __sungem_phy_write(gp, gp->mii_phy_addr, reg, val); reg 187 drivers/net/ethernet/sun/sunhme.c static void sbus_hme_write32(void __iomem *reg, u32 val) reg 189 drivers/net/ethernet/sun/sunhme.c sbus_writel(val, reg); reg 192 drivers/net/ethernet/sun/sunhme.c static u32 sbus_hme_read32(void __iomem *reg) reg 194 drivers/net/ethernet/sun/sunhme.c return sbus_readl(reg); reg 216 drivers/net/ethernet/sun/sunhme.c static void pci_hme_write32(void __iomem *reg, u32 val) reg 218 drivers/net/ethernet/sun/sunhme.c writel(val, reg); reg 221 drivers/net/ethernet/sun/sunhme.c static u32 pci_hme_read32(void __iomem *reg) reg 223 drivers/net/ethernet/sun/sunhme.c return readl(reg); reg 365 drivers/net/ethernet/sun/sunhme.c void __iomem *tregs, int reg) reg 371 drivers/net/ethernet/sun/sunhme.c ASD(("happy_meal_bb_read: reg=%d ", reg)); reg 392 drivers/net/ethernet/sun/sunhme.c tmp = (reg & 0xff); reg 411 drivers/net/ethernet/sun/sunhme.c void __iomem *tregs, int reg, reg 417 drivers/net/ethernet/sun/sunhme.c ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value)); reg 438 drivers/net/ethernet/sun/sunhme.c tmp = (reg & 0xff); reg 456 drivers/net/ethernet/sun/sunhme.c void __iomem *tregs, int reg) reg 461 drivers/net/ethernet/sun/sunhme.c ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg)); reg 469 drivers/net/ethernet/sun/sunhme.c return happy_meal_bb_read(hp, tregs, reg); reg 473 drivers/net/ethernet/sun/sunhme.c (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18))); reg 488 drivers/net/ethernet/sun/sunhme.c void __iomem *tregs, int reg, reg 493 drivers/net/ethernet/sun/sunhme.c ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value)); reg 497 drivers/net/ethernet/sun/sunhme.c happy_meal_bb_write(hp, tregs, reg, value); reg 504 drivers/net/ethernet/sun/sunhme.c ((reg & 0xff) << 18) | (value & 0xffff))); reg 1191 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c unsigned int reg, regval; reg 1205 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c reg = MAC_Q0TFCR; reg 1207 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + reg); reg 1212 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + reg); reg 1214 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c reg += MAC_QTFCR_INC; reg 1223 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c unsigned int reg, regval; reg 1237 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c reg = MAC_Q0TFCR; reg 1239 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + reg); reg 1248 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + reg); reg 1250 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c reg += MAC_QTFCR_INC; reg 1508 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c unsigned int reg, regval; reg 1554 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c reg = MAC_RQC2R; reg 1577 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + reg); reg 1578 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c reg += MAC_RQC2_INC; reg 1585 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c reg = MTL_RQDCM0R; reg 1586 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + reg); reg 1589 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + reg); reg 1591 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c reg += MTL_RQDCM_INC; reg 1592 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + reg); reg 1595 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + reg); reg 1597 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c reg += MTL_RQDCM_INC; reg 1598 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval = readl(pdata->mac_regs + reg); reg 1601 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c writel(regval, pdata->mac_regs + reg); reg 739 drivers/net/ethernet/synopsys/dwc-xlgmac-reg.h #define XLGMAC_MTL_REG(pdata, n, reg) \ reg 740 drivers/net/ethernet/synopsys/dwc-xlgmac-reg.h ((pdata)->mac_regs + MTL_Q_BASE + ((n) * MTL_Q_INC) + (reg)) reg 742 drivers/net/ethernet/synopsys/dwc-xlgmac-reg.h #define XLGMAC_DMA_REG(channel, reg) ((channel)->dma_regs + (reg)) reg 708 drivers/net/ethernet/tehuti/tehuti.c u32 reg, bit, val; reg 716 drivers/net/ethernet/tehuti/tehuti.c reg = regVLAN_0 + (vid / 32) * 4; reg 718 drivers/net/ethernet/tehuti/tehuti.c val = READ_REG(priv, reg); reg 719 drivers/net/ethernet/tehuti/tehuti.c DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit); reg 725 drivers/net/ethernet/tehuti/tehuti.c WRITE_REG(priv, reg, val); reg 792 drivers/net/ethernet/tehuti/tehuti.c u32 reg, val; reg 812 drivers/net/ethernet/tehuti/tehuti.c reg = regRX_MCST_HASH0 + ((hash >> 5) << 2); reg 813 drivers/net/ethernet/tehuti/tehuti.c val = READ_REG(priv, reg); reg 815 drivers/net/ethernet/tehuti/tehuti.c WRITE_REG(priv, reg, val); reg 861 drivers/net/ethernet/tehuti/tehuti.c static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg) reg 865 drivers/net/ethernet/tehuti/tehuti.c val = READ_REG(priv, reg); reg 866 drivers/net/ethernet/tehuti/tehuti.c val |= ((u64) READ_REG(priv, reg + 8)) << 32; reg 97 drivers/net/ethernet/tehuti/tehuti.h #define READ_REG(pp, reg) readl(pp->pBdxRegs + reg) reg 98 drivers/net/ethernet/tehuti/tehuti.h #define WRITE_REG(pp, reg, val) writel(val, pp->pBdxRegs + reg) reg 143 drivers/net/ethernet/ti/cpmac.c #define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg))) reg 144 drivers/net/ethernet/ti/cpmac.c #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \ reg 145 drivers/net/ethernet/ti/cpmac.c (reg))) reg 162 drivers/net/ethernet/ti/cpmac.c #define MDIO_REG(reg) (((reg) & 0x1f) << 21) reg 265 drivers/net/ethernet/ti/cpmac.c static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg) reg 271 drivers/net/ethernet/ti/cpmac.c cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) | reg 280 drivers/net/ethernet/ti/cpmac.c int reg, u16 val) reg 285 drivers/net/ethernet/ti/cpmac.c MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val)); reg 43 drivers/net/ethernet/ti/cpsw-phy-sel.c u32 reg; reg 48 drivers/net/ethernet/ti/cpsw-phy-sel.c reg = readl(priv->gmii_sel); reg 94 drivers/net/ethernet/ti/cpsw-phy-sel.c reg &= ~mask; reg 95 drivers/net/ethernet/ti/cpsw-phy-sel.c reg |= mode; reg 97 drivers/net/ethernet/ti/cpsw-phy-sel.c writel(reg, priv->gmii_sel); reg 103 drivers/net/ethernet/ti/cpsw-phy-sel.c u32 reg; reg 107 drivers/net/ethernet/ti/cpsw-phy-sel.c reg = readl(priv->gmii_sel); reg 147 drivers/net/ethernet/ti/cpsw-phy-sel.c reg &= ~mask; reg 148 drivers/net/ethernet/ti/cpsw-phy-sel.c reg |= mode; reg 150 drivers/net/ethernet/ti/cpsw-phy-sel.c writel(reg, priv->gmii_sel); reg 1005 drivers/net/ethernet/ti/cpsw.c static inline void soft_reset(const char *module, void __iomem *reg) reg 1009 drivers/net/ethernet/ti/cpsw.c writel_relaxed(1, reg); reg 1012 drivers/net/ethernet/ti/cpsw.c } while ((readl_relaxed(reg) & 1) && time_after(timeout, jiffies)); reg 1014 drivers/net/ethernet/ti/cpsw.c WARN(readl_relaxed(reg) & 1, "failed to soft-reset %s\n", module); reg 1293 drivers/net/ethernet/ti/cpsw.c u32 reg; reg 1297 drivers/net/ethernet/ti/cpsw.c reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : reg 1303 drivers/net/ethernet/ti/cpsw.c slave_write(cpsw->slaves + i, vlan, reg); reg 1657 drivers/net/ethernet/ti/cpsw.c u32 reg; reg 1680 drivers/net/ethernet/ti/cpsw.c reg = cpsw->version; reg 1683 drivers/net/ethernet/ti/cpsw.c CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), reg 1684 drivers/net/ethernet/ti/cpsw.c CPSW_RTL_VERSION(reg)); reg 43 drivers/net/ethernet/ti/cpsw_ale.c #define ALE_VLAN_MASK_MUX(reg) (0xc0 + (0x4 * (reg))) reg 347 drivers/net/ethernet/ti/cpsw_ethtool.c u32 *reg = p; reg 353 drivers/net/ethernet/ti/cpsw_ethtool.c cpsw_ale_dump(cpsw->ale, reg); reg 46 drivers/net/ethernet/ti/cpsw_priv.h #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) reg 47 drivers/net/ethernet/ti/cpsw_priv.h #define CPSW_MINOR_VERSION(reg) (reg & 0xff) reg 48 drivers/net/ethernet/ti/cpsw_priv.h #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) reg 189 drivers/net/ethernet/ti/cpsw_sl.c u32 cpsw_sl_reg_read(struct cpsw_sl *sl, enum cpsw_sl_regs reg) reg 193 drivers/net/ethernet/ti/cpsw_sl.c if (sl->regs[reg] == CPSW_SL_REG_NOTUSED) { reg 195 drivers/net/ethernet/ti/cpsw_sl.c sl->regs[reg]); reg 199 drivers/net/ethernet/ti/cpsw_sl.c val = readl(sl->sl_base + sl->regs[reg]); reg 200 drivers/net/ethernet/ti/cpsw_sl.c dev_dbg(sl->dev, "cpsw_sl: reg: %04X r 0x%08X\n", sl->regs[reg], val); reg 204 drivers/net/ethernet/ti/cpsw_sl.c void cpsw_sl_reg_write(struct cpsw_sl *sl, enum cpsw_sl_regs reg, u32 val) reg 206 drivers/net/ethernet/ti/cpsw_sl.c if (sl->regs[reg] == CPSW_SL_REG_NOTUSED) { reg 208 drivers/net/ethernet/ti/cpsw_sl.c sl->regs[reg]); reg 212 drivers/net/ethernet/ti/cpsw_sl.c dev_dbg(sl->dev, "cpsw_sl: reg: %04X w 0x%08X\n", sl->regs[reg], val); reg 213 drivers/net/ethernet/ti/cpsw_sl.c writel(val, sl->sl_base + sl->regs[reg]); reg 70 drivers/net/ethernet/ti/cpsw_sl.h u32 cpsw_sl_reg_read(struct cpsw_sl *sl, enum cpsw_sl_regs reg); reg 71 drivers/net/ethernet/ti/cpsw_sl.h void cpsw_sl_reg_write(struct cpsw_sl *sl, enum cpsw_sl_regs reg, u32 val); reg 29 drivers/net/ethernet/ti/cpts.c #define cpts_read32(c, r) readl_relaxed(&c->reg->r) reg 30 drivers/net/ethernet/ti/cpts.c #define cpts_write32(c, v, r) writel_relaxed(v, &c->reg->r) reg 578 drivers/net/ethernet/ti/cpts.c &cpts->reg->rftclk_sel, 0, 0x1F, reg 645 drivers/net/ethernet/ti/cpts.c cpts->reg = (struct cpsw_cpts __iomem *)regs; reg 101 drivers/net/ethernet/ti/cpts.h struct cpsw_cpts __iomem *reg; reg 129 drivers/net/ethernet/ti/davinci_cpdma.c u32 reg; reg 323 drivers/net/ethernet/ti/davinci_cpdma.c val = dma_reg_read(ctlr, info->reg); reg 326 drivers/net/ethernet/ti/davinci_cpdma.c dma_reg_write(ctlr, info->reg, val); reg 348 drivers/net/ethernet/ti/davinci_cpdma.c ret = (dma_reg_read(ctlr, info->reg) >> info->shift) & info->mask; reg 361 drivers/net/ethernet/ti/davinci_emac.c #define emac_read(reg) ioread32(priv->emac_base + (reg)) reg 362 drivers/net/ethernet/ti/davinci_emac.c #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg)) reg 364 drivers/net/ethernet/ti/davinci_emac.c #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg))) reg 365 drivers/net/ethernet/ti/davinci_emac.c #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg))) reg 181 drivers/net/ethernet/ti/davinci_mdio.c u32 reg; reg 184 drivers/net/ethernet/ti/davinci_mdio.c reg = readl(®s->user[0].access); reg 185 drivers/net/ethernet/ti/davinci_mdio.c if ((reg & USERACCESS_GO) == 0) reg 188 drivers/net/ethernet/ti/davinci_mdio.c reg = readl(®s->control); reg 189 drivers/net/ethernet/ti/davinci_mdio.c if ((reg & CONTROL_IDLE) == 0) { reg 204 drivers/net/ethernet/ti/davinci_mdio.c reg = readl(®s->user[0].access); reg 205 drivers/net/ethernet/ti/davinci_mdio.c if ((reg & USERACCESS_GO) == 0) reg 229 drivers/net/ethernet/ti/davinci_mdio.c u32 reg; reg 241 drivers/net/ethernet/ti/davinci_mdio.c reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) | reg 251 drivers/net/ethernet/ti/davinci_mdio.c writel(reg, &data->regs->user[0].access); reg 259 drivers/net/ethernet/ti/davinci_mdio.c reg = readl(&data->regs->user[0].access); reg 260 drivers/net/ethernet/ti/davinci_mdio.c ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO; reg 273 drivers/net/ethernet/ti/davinci_mdio.c u32 reg; reg 285 drivers/net/ethernet/ti/davinci_mdio.c reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) | reg 295 drivers/net/ethernet/ti/davinci_mdio.c writel(reg, &data->regs->user[0].access); reg 31 drivers/net/ethernet/ti/netcp_ethss.c #define GBE_IDENT(reg) ((reg >> 16) & 0xffff) reg 32 drivers/net/ethernet/ti/netcp_ethss.c #define GBE_MAJOR_VERSION(reg) (reg >> 8 & 0x7) reg 33 drivers/net/ethernet/ti/netcp_ethss.c #define GBE_MINOR_VERSION(reg) (reg & 0xff) reg 34 drivers/net/ethernet/ti/netcp_ethss.c #define GBE_RTL_VERSION(reg) ((reg >> 11) & 0x1f) reg 2903 drivers/net/ethernet/ti/netcp_ethss.c u32 reg, val; reg 2906 drivers/net/ethernet/ti/netcp_ethss.c reg = readl(GBE_REG_ADDR(gbe_dev, switch_regs, id_ver)); reg 2908 drivers/net/ethernet/ti/netcp_ethss.c GBE_MAJOR_VERSION(reg), GBE_MINOR_VERSION(reg), reg 2909 drivers/net/ethernet/ti/netcp_ethss.c GBE_RTL_VERSION(reg), GBE_IDENT(reg)); reg 31 drivers/net/ethernet/ti/netcp_sgmii.c static void sgmii_write_reg(void __iomem *base, int reg, u32 val) reg 33 drivers/net/ethernet/ti/netcp_sgmii.c writel(val, base + reg); reg 36 drivers/net/ethernet/ti/netcp_sgmii.c static u32 sgmii_read_reg(void __iomem *base, int reg) reg 38 drivers/net/ethernet/ti/netcp_sgmii.c return readl(base + reg); reg 41 drivers/net/ethernet/ti/netcp_sgmii.c static void sgmii_write_reg_bit(void __iomem *base, int reg, u32 val) reg 43 drivers/net/ethernet/ti/netcp_sgmii.c writel((readl(base + reg) | val), base + reg); reg 63 drivers/net/ethernet/ti/netcp_sgmii.c u32 reg; reg 67 drivers/net/ethernet/ti/netcp_sgmii.c reg = sgmii_read_reg(sgmii_ofs, SGMII_SRESET_REG(port)); reg 68 drivers/net/ethernet/ti/netcp_sgmii.c oldval = (reg & SGMII_SRESET_RTRESET) != 0x0; reg 70 drivers/net/ethernet/ti/netcp_sgmii.c reg |= SGMII_SRESET_RTRESET; reg 72 drivers/net/ethernet/ti/netcp_sgmii.c reg &= ~SGMII_SRESET_RTRESET; reg 73 drivers/net/ethernet/ti/netcp_sgmii.c sgmii_write_reg(sgmii_ofs, SGMII_SRESET_REG(port), reg); reg 470 drivers/net/ethernet/ti/tlan.c int reg, rc = -ENODEV; reg 510 drivers/net/ethernet/ti/tlan.c for (reg = 0; reg <= 5; reg++) { reg 511 drivers/net/ethernet/ti/tlan.c if (pci_resource_flags(pdev, reg) & IORESOURCE_IO) { reg 512 drivers/net/ethernet/ti/tlan.c pci_io_base = pci_resource_start(pdev, reg); reg 2848 drivers/net/ethernet/ti/tlan.c tlan_mii_read_reg(struct net_device *dev, u16 phy, u16 reg, u16 *val) reg 2874 drivers/net/ethernet/ti/tlan.c tlan_mii_send_data(dev->base_addr, reg, 5); /* register # */ reg 3020 drivers/net/ethernet/ti/tlan.c tlan_mii_write_reg(struct net_device *dev, u16 phy, u16 reg, u16 val) reg 3042 drivers/net/ethernet/ti/tlan.c tlan_mii_send_data(dev->base_addr, reg, 5); /* register # */ reg 78 drivers/net/ethernet/toshiba/spider_net.c spider_net_read_reg(struct spider_net_card *card, u32 reg) reg 84 drivers/net/ethernet/toshiba/spider_net.c return in_be32(card->regs + reg); reg 94 drivers/net/ethernet/toshiba/spider_net.c spider_net_write_reg(struct spider_net_card *card, u32 reg, u32 value) reg 100 drivers/net/ethernet/toshiba/spider_net.c out_be32(card->regs + reg, value); reg 116 drivers/net/ethernet/toshiba/spider_net.c int reg, int val) reg 122 drivers/net/ethernet/toshiba/spider_net.c ((u32)reg << 16) | ((u32)val); reg 139 drivers/net/ethernet/toshiba/spider_net.c spider_net_read_phy(struct net_device *netdev, int mii_id, int reg) reg 144 drivers/net/ethernet/toshiba/spider_net.c readvalue = ((u32)mii_id << 21) | ((u32)reg << 16); reg 591 drivers/net/ethernet/toshiba/spider_net.c u32 reg; reg 615 drivers/net/ethernet/toshiba/spider_net.c reg = 0; reg 617 drivers/net/ethernet/toshiba/spider_net.c reg += 0x08; reg 618 drivers/net/ethernet/toshiba/spider_net.c reg <<= 8; reg 620 drivers/net/ethernet/toshiba/spider_net.c reg += 0x08; reg 621 drivers/net/ethernet/toshiba/spider_net.c reg <<= 8; reg 623 drivers/net/ethernet/toshiba/spider_net.c reg += 0x08; reg 624 drivers/net/ethernet/toshiba/spider_net.c reg <<= 8; reg 626 drivers/net/ethernet/toshiba/spider_net.c reg += 0x08; reg 628 drivers/net/ethernet/toshiba/spider_net.c spider_net_write_reg(card, SPIDER_NET_GMRMHFILnR + i * 4, reg); reg 551 drivers/net/ethernet/toshiba/tc35815.c u32 reg; reg 553 drivers/net/ethernet/toshiba/tc35815.c reg = tc_readl(&tr->MAC_Ctl); reg 554 drivers/net/ethernet/toshiba/tc35815.c reg |= MAC_HaltReq; reg 555 drivers/net/ethernet/toshiba/tc35815.c tc_writel(reg, &tr->MAC_Ctl); reg 557 drivers/net/ethernet/toshiba/tc35815.c reg |= MAC_FullDup; reg 559 drivers/net/ethernet/toshiba/tc35815.c reg &= ~MAC_FullDup; reg 560 drivers/net/ethernet/toshiba/tc35815.c tc_writel(reg, &tr->MAC_Ctl); reg 561 drivers/net/ethernet/toshiba/tc35815.c reg &= ~MAC_HaltReq; reg 562 drivers/net/ethernet/toshiba/tc35815.c tc_writel(reg, &tr->MAC_Ctl); reg 193 drivers/net/ethernet/tundra/tsi108_eth.c static int tsi108_read_mii(struct tsi108_prv_data *data, int reg) reg 199 drivers/net/ethernet/tundra/tsi108_eth.c (reg << TSI108_MAC_MII_ADDR_REG)); reg 216 drivers/net/ethernet/tundra/tsi108_eth.c int reg, u16 val) reg 221 drivers/net/ethernet/tundra/tsi108_eth.c (reg << TSI108_MAC_MII_ADDR_REG)); reg 231 drivers/net/ethernet/tundra/tsi108_eth.c static int tsi108_mdio_read(struct net_device *dev, int addr, int reg) reg 234 drivers/net/ethernet/tundra/tsi108_eth.c return tsi108_read_mii(data, reg); reg 237 drivers/net/ethernet/tundra/tsi108_eth.c static void tsi108_mdio_write(struct net_device *dev, int addr, int reg, int val) reg 240 drivers/net/ethernet/tundra/tsi108_eth.c tsi108_write_mii(data, reg, val); reg 244 drivers/net/ethernet/tundra/tsi108_eth.c int reg, u16 val) reg 249 drivers/net/ethernet/tundra/tsi108_eth.c | (reg << TSI108_MAC_MII_ADDR_REG)); reg 452 drivers/net/ethernet/tundra/tsi108_eth.c tsi108_read_stat(struct tsi108_prv_data * data, int reg, int carry_bit, reg 458 drivers/net/ethernet/tundra/tsi108_eth.c if (reg < 0xb0) reg 464 drivers/net/ethernet/tundra/tsi108_eth.c val = TSI_READ(reg) | *upper; reg 527 drivers/net/ethernet/via/via-rhine.c static void rhine_wait_bit(struct rhine_private *rp, u8 reg, u8 mask, bool low) reg 533 drivers/net/ethernet/via/via-rhine.c bool has_mask_bits = !!(ioread8(ioaddr + reg) & mask); reg 541 drivers/net/ethernet/via/via-rhine.c "count: %04d\n", low ? "low" : "high", reg, mask, i); reg 545 drivers/net/ethernet/via/via-rhine.c static void rhine_wait_bit_high(struct rhine_private *rp, u8 reg, u8 mask) reg 547 drivers/net/ethernet/via/via-rhine.c rhine_wait_bit(rp, reg, mask, false); reg 550 drivers/net/ethernet/via/via-rhine.c static void rhine_wait_bit_low(struct rhine_private *rp, u8 reg, u8 mask) reg 552 drivers/net/ethernet/via/via-rhine.c rhine_wait_bit(rp, reg, mask, true); reg 687 drivers/net/ethernet/via/via-rhine.c int reg = mmio_verify_registers[i++]; reg 688 drivers/net/ethernet/via/via-rhine.c unsigned char a = inb(pioaddr+reg); reg 689 drivers/net/ethernet/via/via-rhine.c unsigned char b = readb(ioaddr+reg); reg 694 drivers/net/ethernet/via/via-rhine.c reg, a, b); reg 352 drivers/net/ethernet/xilinx/ll_temac.h u32 (*dma_in)(struct temac_local *lp, int reg); reg 353 drivers/net/ethernet/xilinx/ll_temac.h void (*dma_out)(struct temac_local *lp, int reg, u32 value); reg 394 drivers/net/ethernet/xilinx/ll_temac.h u32 temac_indirect_in32(struct temac_local *lp, int reg); reg 395 drivers/net/ethernet/xilinx/ll_temac.h u32 temac_indirect_in32_locked(struct temac_local *lp, int reg); reg 396 drivers/net/ethernet/xilinx/ll_temac.h void temac_indirect_out32(struct temac_local *lp, int reg, u32 value); reg 397 drivers/net/ethernet/xilinx/ll_temac.h void temac_indirect_out32_locked(struct temac_local *lp, int reg, u32 value); reg 125 drivers/net/ethernet/xilinx/ll_temac_main.c u32 temac_indirect_in32(struct temac_local *lp, int reg) reg 131 drivers/net/ethernet/xilinx/ll_temac_main.c val = temac_indirect_in32_locked(lp, reg); reg 143 drivers/net/ethernet/xilinx/ll_temac_main.c u32 temac_indirect_in32_locked(struct temac_local *lp, int reg) reg 152 drivers/net/ethernet/xilinx/ll_temac_main.c temac_iow(lp, XTE_CTL0_OFFSET, reg); reg 168 drivers/net/ethernet/xilinx/ll_temac_main.c void temac_indirect_out32(struct temac_local *lp, int reg, u32 value) reg 173 drivers/net/ethernet/xilinx/ll_temac_main.c temac_indirect_out32_locked(lp, reg, value); reg 184 drivers/net/ethernet/xilinx/ll_temac_main.c void temac_indirect_out32_locked(struct temac_local *lp, int reg, u32 value) reg 194 drivers/net/ethernet/xilinx/ll_temac_main.c temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg); reg 208 drivers/net/ethernet/xilinx/ll_temac_main.c static u32 temac_dma_in32_be(struct temac_local *lp, int reg) reg 210 drivers/net/ethernet/xilinx/ll_temac_main.c return ioread32be(lp->sdma_regs + (reg << 2)); reg 213 drivers/net/ethernet/xilinx/ll_temac_main.c static u32 temac_dma_in32_le(struct temac_local *lp, int reg) reg 215 drivers/net/ethernet/xilinx/ll_temac_main.c return ioread32(lp->sdma_regs + (reg << 2)); reg 224 drivers/net/ethernet/xilinx/ll_temac_main.c static void temac_dma_out32_be(struct temac_local *lp, int reg, u32 value) reg 226 drivers/net/ethernet/xilinx/ll_temac_main.c iowrite32be(value, lp->sdma_regs + (reg << 2)); reg 229 drivers/net/ethernet/xilinx/ll_temac_main.c static void temac_dma_out32_le(struct temac_local *lp, int reg, u32 value) reg 231 drivers/net/ethernet/xilinx/ll_temac_main.c iowrite32(value, lp->sdma_regs + (reg << 2)); reg 243 drivers/net/ethernet/xilinx/ll_temac_main.c static u32 temac_dma_dcr_in(struct temac_local *lp, int reg) reg 245 drivers/net/ethernet/xilinx/ll_temac_main.c return dcr_read(lp->sdma_dcrs, reg); reg 251 drivers/net/ethernet/xilinx/ll_temac_main.c static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value) reg 253 drivers/net/ethernet/xilinx/ll_temac_main.c dcr_write(lp->sdma_dcrs, reg, value); reg 515 drivers/net/ethernet/xilinx/ll_temac_main.c u32 reg; reg 522 drivers/net/ethernet/xilinx/ll_temac_main.c .reg = XTE_TXC_OFFSET, reg 527 drivers/net/ethernet/xilinx/ll_temac_main.c .reg = XTE_RXC1_OFFSET, reg 533 drivers/net/ethernet/xilinx/ll_temac_main.c .reg = XTE_TXC_OFFSET, reg 538 drivers/net/ethernet/xilinx/ll_temac_main.c .reg = XTE_RXC1_OFFSET, reg 544 drivers/net/ethernet/xilinx/ll_temac_main.c .reg = XTE_RXC1_OFFSET, reg 550 drivers/net/ethernet/xilinx/ll_temac_main.c .reg = XTE_TXC_OFFSET, reg 556 drivers/net/ethernet/xilinx/ll_temac_main.c .reg = XTE_RXC1_OFFSET, reg 562 drivers/net/ethernet/xilinx/ll_temac_main.c .reg = XTE_FCC_OFFSET, reg 568 drivers/net/ethernet/xilinx/ll_temac_main.c .reg = XTE_FCC_OFFSET, reg 574 drivers/net/ethernet/xilinx/ll_temac_main.c .reg = XTE_AFM_OFFSET, reg 580 drivers/net/ethernet/xilinx/ll_temac_main.c .reg = XTE_TXC_OFFSET, reg 586 drivers/net/ethernet/xilinx/ll_temac_main.c .reg = XTE_RXC1_OFFSET, reg 599 drivers/net/ethernet/xilinx/ll_temac_main.c int reg; reg 604 drivers/net/ethernet/xilinx/ll_temac_main.c reg = temac_indirect_in32_locked(lp, tp->reg) & ~tp->m_or; reg 606 drivers/net/ethernet/xilinx/ll_temac_main.c reg |= tp->m_or; reg 607 drivers/net/ethernet/xilinx/ll_temac_main.c temac_indirect_out32_locked(lp, tp->reg, reg); reg 24 drivers/net/ethernet/xilinx/ll_temac_mdio.c static int temac_mdio_read(struct mii_bus *bus, int phy_id, int reg) reg 34 drivers/net/ethernet/xilinx/ll_temac_mdio.c temac_iow(lp, XTE_LSW0_OFFSET, (phy_id << 5) | reg); reg 39 drivers/net/ethernet/xilinx/ll_temac_mdio.c phy_id, reg, rc); reg 44 drivers/net/ethernet/xilinx/ll_temac_mdio.c static int temac_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val) reg 50 drivers/net/ethernet/xilinx/ll_temac_mdio.c phy_id, reg, val); reg 57 drivers/net/ethernet/xilinx/ll_temac_mdio.c temac_indirect_out32_locked(lp, XTE_MIIMAI_OFFSET, (phy_id << 5) | reg); reg 477 drivers/net/ethernet/xilinx/xilinx_axienet.h u32 reg; reg 71 drivers/net/ethernet/xilinx/xilinx_axienet_main.c .reg = XAE_TC_OFFSET, reg 75 drivers/net/ethernet/xilinx/xilinx_axienet_main.c .reg = XAE_RCW1_OFFSET, reg 79 drivers/net/ethernet/xilinx/xilinx_axienet_main.c .reg = XAE_TC_OFFSET, reg 83 drivers/net/ethernet/xilinx/xilinx_axienet_main.c .reg = XAE_RCW1_OFFSET, reg 87 drivers/net/ethernet/xilinx/xilinx_axienet_main.c .reg = XAE_RCW1_OFFSET, reg 91 drivers/net/ethernet/xilinx/xilinx_axienet_main.c .reg = XAE_TC_OFFSET, reg 95 drivers/net/ethernet/xilinx/xilinx_axienet_main.c .reg = XAE_RCW1_OFFSET, reg 99 drivers/net/ethernet/xilinx/xilinx_axienet_main.c .reg = XAE_FCC_OFFSET, reg 103 drivers/net/ethernet/xilinx/xilinx_axienet_main.c .reg = XAE_FCC_OFFSET, reg 107 drivers/net/ethernet/xilinx/xilinx_axienet_main.c .reg = XAE_FMI_OFFSET, reg 111 drivers/net/ethernet/xilinx/xilinx_axienet_main.c .reg = XAE_TC_OFFSET, reg 115 drivers/net/ethernet/xilinx/xilinx_axienet_main.c .reg = XAE_RCW1_OFFSET, reg 130 drivers/net/ethernet/xilinx/xilinx_axienet_main.c static inline u32 axienet_dma_in32(struct axienet_local *lp, off_t reg) reg 132 drivers/net/ethernet/xilinx/xilinx_axienet_main.c return ioread32(lp->dma_regs + reg); reg 145 drivers/net/ethernet/xilinx/xilinx_axienet_main.c off_t reg, u32 value) reg 147 drivers/net/ethernet/xilinx/xilinx_axienet_main.c iowrite32(value, lp->dma_regs + reg); reg 355 drivers/net/ethernet/xilinx/xilinx_axienet_main.c u32 reg, af0reg, af1reg; reg 365 drivers/net/ethernet/xilinx/xilinx_axienet_main.c reg = axienet_ior(lp, XAE_FMI_OFFSET); reg 366 drivers/net/ethernet/xilinx/xilinx_axienet_main.c reg |= XAE_FMI_PM_MASK; reg 367 drivers/net/ethernet/xilinx/xilinx_axienet_main.c axienet_iow(lp, XAE_FMI_OFFSET, reg); reg 385 drivers/net/ethernet/xilinx/xilinx_axienet_main.c reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00; reg 386 drivers/net/ethernet/xilinx/xilinx_axienet_main.c reg |= i; reg 388 drivers/net/ethernet/xilinx/xilinx_axienet_main.c axienet_iow(lp, XAE_FMI_OFFSET, reg); reg 394 drivers/net/ethernet/xilinx/xilinx_axienet_main.c reg = axienet_ior(lp, XAE_FMI_OFFSET); reg 395 drivers/net/ethernet/xilinx/xilinx_axienet_main.c reg &= ~XAE_FMI_PM_MASK; reg 397 drivers/net/ethernet/xilinx/xilinx_axienet_main.c axienet_iow(lp, XAE_FMI_OFFSET, reg); reg 400 drivers/net/ethernet/xilinx/xilinx_axienet_main.c reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00; reg 401 drivers/net/ethernet/xilinx/xilinx_axienet_main.c reg |= i; reg 403 drivers/net/ethernet/xilinx/xilinx_axienet_main.c axienet_iow(lp, XAE_FMI_OFFSET, reg); reg 425 drivers/net/ethernet/xilinx/xilinx_axienet_main.c int reg; reg 430 drivers/net/ethernet/xilinx/xilinx_axienet_main.c reg = ((axienet_ior(lp, tp->reg)) & ~(tp->m_or)); reg 432 drivers/net/ethernet/xilinx/xilinx_axienet_main.c reg |= tp->m_or; reg 433 drivers/net/ethernet/xilinx/xilinx_axienet_main.c axienet_iow(lp, tp->reg, reg); reg 45 drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c static int axienet_mdio_read(struct mii_bus *bus, int phy_id, int reg) reg 58 drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c ((reg << XAE_MDIO_MCR_REGAD_SHIFT) & reg 70 drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c phy_id, reg, rc); reg 88 drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg, reg 95 drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c phy_id, reg, val); reg 105 drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c ((reg << XAE_MDIO_MCR_REGAD_SHIFT) & reg 737 drivers/net/ethernet/xilinx/xilinx_emaclite.c static int xemaclite_mdio_read(struct mii_bus *bus, int phy_id, int reg) reg 752 drivers/net/ethernet/xilinx/xilinx_emaclite.c ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg), reg 764 drivers/net/ethernet/xilinx/xilinx_emaclite.c phy_id, reg, rc); reg 781 drivers/net/ethernet/xilinx/xilinx_emaclite.c static int xemaclite_mdio_write(struct mii_bus *bus, int phy_id, int reg, reg 789 drivers/net/ethernet/xilinx/xilinx_emaclite.c phy_id, reg, val); reg 801 drivers/net/ethernet/xilinx/xilinx_emaclite.c ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg), reg 308 drivers/net/ethernet/xircom/xirc2ps_cs.c #define GetByte(reg) ((unsigned)inb(ioaddr + (reg))) reg 309 drivers/net/ethernet/xircom/xirc2ps_cs.c #define GetWord(reg) ((unsigned)inw(ioaddr + (reg))) reg 310 drivers/net/ethernet/xircom/xirc2ps_cs.c #define PutByte(reg,value) outb((value), ioaddr+(reg)) reg 311 drivers/net/ethernet/xircom/xirc2ps_cs.c #define PutWord(reg,value) outw((value), ioaddr+(reg)) reg 818 drivers/net/fddi/skfp/h/skfbi.h #define PLC(np,reg) (((np) == PA) ? P2_A(reg) : P1_A(reg)) reg 23 drivers/net/fjes/fjes_hw.c u32 fjes_hw_rd32(struct fjes_hw *hw, u32 reg) reg 28 drivers/net/fjes/fjes_hw.c value = readl(&base[reg]); reg 59 drivers/net/fjes/fjes_hw.c dctl.reg = 0; reg 61 drivers/net/fjes/fjes_hw.c wr32(XSCT_DCTL, dctl.reg); reg 64 drivers/net/fjes/fjes_hw.c dctl.reg = rd32(XSCT_DCTL); reg 67 drivers/net/fjes/fjes_hw.c dctl.reg = rd32(XSCT_DCTL); reg 78 drivers/net/fjes/fjes_hw.c info.reg = rd32(XSCT_MAX_EP); reg 87 drivers/net/fjes/fjes_hw.c info.reg = rd32(XSCT_OWNER_EPID); reg 377 drivers/net/fjes/fjes_hw.c cr.reg = 0; reg 380 drivers/net/fjes/fjes_hw.c wr32(XSCT_CR, cr.reg); reg 381 drivers/net/fjes/fjes_hw.c cr.reg = rd32(XSCT_CR); reg 385 drivers/net/fjes/fjes_hw.c cs.reg = rd32(XSCT_CS); reg 389 drivers/net/fjes/fjes_hw.c cs.reg = rd32(XSCT_CS); reg 50 drivers/net/fjes/fjes_regs.h __le32 reg; reg 58 drivers/net/fjes/fjes_regs.h __le32 reg; reg 68 drivers/net/fjes/fjes_regs.h __le32 reg; reg 79 drivers/net/fjes/fjes_regs.h __le32 reg; reg 89 drivers/net/fjes/fjes_regs.h __le32 reg; reg 98 drivers/net/fjes/fjes_regs.h __le32 reg; reg 117 drivers/net/fjes/fjes_regs.h u32 fjes_hw_rd32(struct fjes_hw *hw, u32 reg); reg 119 drivers/net/fjes/fjes_regs.h #define wr32(reg, val) \ reg 122 drivers/net/fjes/fjes_regs.h writel((val), &base[(reg)]); \ reg 125 drivers/net/fjes/fjes_regs.h #define rd32(reg) (fjes_hw_rd32(hw, reg)) reg 221 drivers/net/hamradio/dmascc.c static void write_scc(struct scc_priv *priv, int reg, int val); reg 223 drivers/net/hamradio/dmascc.c static int read_scc(struct scc_priv *priv, int reg); reg 615 drivers/net/hamradio/dmascc.c static void write_scc(struct scc_priv *priv, int reg, int val) reg 620 drivers/net/hamradio/dmascc.c if (reg) reg 621 drivers/net/hamradio/dmascc.c outb(reg, priv->scc_cmd); reg 625 drivers/net/hamradio/dmascc.c if (reg) reg 626 drivers/net/hamradio/dmascc.c outb_p(reg, priv->scc_cmd); reg 632 drivers/net/hamradio/dmascc.c if (reg) reg 633 drivers/net/hamradio/dmascc.c outb_p(reg, priv->scc_cmd); reg 667 drivers/net/hamradio/dmascc.c static int read_scc(struct scc_priv *priv, int reg) reg 673 drivers/net/hamradio/dmascc.c if (reg) reg 674 drivers/net/hamradio/dmascc.c outb(reg, priv->scc_cmd); reg 677 drivers/net/hamradio/dmascc.c if (reg) reg 678 drivers/net/hamradio/dmascc.c outb_p(reg, priv->scc_cmd); reg 683 drivers/net/hamradio/dmascc.c if (reg) reg 684 drivers/net/hamradio/dmascc.c outb_p(reg, priv->scc_cmd); reg 242 drivers/net/hamradio/scc.c static inline unsigned char InReg(io_port port, unsigned char reg) reg 249 drivers/net/hamradio/scc.c Outb(port, reg); reg 254 drivers/net/hamradio/scc.c Outb(port, reg); reg 261 drivers/net/hamradio/scc.c static inline void OutReg(io_port port, unsigned char reg, unsigned char val) reg 267 drivers/net/hamradio/scc.c Outb(port, reg); udelay(SCC_LDELAY); reg 270 drivers/net/hamradio/scc.c Outb(port, reg); reg 276 drivers/net/hamradio/scc.c static inline void wr(struct scc_channel *scc, unsigned char reg, reg 279 drivers/net/hamradio/scc.c OutReg(scc->ctrl, reg, (scc->wreg[reg] = val)); reg 282 drivers/net/hamradio/scc.c static inline void or(struct scc_channel *scc, unsigned char reg, unsigned char val) reg 284 drivers/net/hamradio/scc.c OutReg(scc->ctrl, reg, (scc->wreg[reg] |= val)); reg 287 drivers/net/hamradio/scc.c static inline void cl(struct scc_channel *scc, unsigned char reg, unsigned char val) reg 289 drivers/net/hamradio/scc.c OutReg(scc->ctrl, reg, (scc->wreg[reg] &= ~val)); reg 2059 drivers/net/hamradio/scc.c int reg; reg 2062 drivers/net/hamradio/scc.c for (reg = 0; reg < 16; reg++) reg 2063 drivers/net/hamradio/scc.c seq_printf(seq, "%2.2x ", scc->wreg[reg]); reg 2067 drivers/net/hamradio/scc.c for (reg = 3; reg < 8; reg++) reg 2068 drivers/net/hamradio/scc.c seq_printf(seq, "%2.2x ", InReg(scc->ctrl, reg)); reg 2070 drivers/net/hamradio/scc.c for (reg = 9; reg < 16; reg++) reg 2071 drivers/net/hamradio/scc.c seq_printf(seq, "%2.2x ", InReg(scc->ctrl, reg)); reg 751 drivers/net/ieee802154/adf7242.c u8 reg; reg 781 drivers/net/ieee802154/adf7242.c adf7242_read_reg(lp, REG_AUTO_CFG, ®); reg 783 drivers/net/ieee802154/adf7242.c reg |= IS_PANCOORD; reg 785 drivers/net/ieee802154/adf7242.c reg &= ~IS_PANCOORD; reg 786 drivers/net/ieee802154/adf7242.c adf7242_write_reg(lp, REG_AUTO_CFG, reg); reg 223 drivers/net/ieee802154/at86rf230.c at86rf230_reg_writeable(struct device *dev, unsigned int reg) reg 225 drivers/net/ieee802154/at86rf230.c switch (reg) { reg 269 drivers/net/ieee802154/at86rf230.c at86rf230_reg_readable(struct device *dev, unsigned int reg) reg 274 drivers/net/ieee802154/at86rf230.c rc = at86rf230_reg_writeable(dev, reg); reg 279 drivers/net/ieee802154/at86rf230.c switch (reg) { reg 294 drivers/net/ieee802154/at86rf230.c at86rf230_reg_volatile(struct device *dev, unsigned int reg) reg 297 drivers/net/ieee802154/at86rf230.c switch (reg) { reg 313 drivers/net/ieee802154/at86rf230.c at86rf230_reg_precious(struct device *dev, unsigned int reg) reg 316 drivers/net/ieee802154/at86rf230.c switch (reg) { reg 372 drivers/net/ieee802154/at86rf230.c at86rf230_async_read_reg(struct at86rf230_local *lp, u8 reg, reg 380 drivers/net/ieee802154/at86rf230.c tx_buf[0] = (reg & CMD_REG_MASK) | CMD_REG; reg 388 drivers/net/ieee802154/at86rf230.c at86rf230_async_write_reg(struct at86rf230_local *lp, u8 reg, u8 val, reg 394 drivers/net/ieee802154/at86rf230.c ctx->buf[0] = (reg & CMD_REG_MASK) | CMD_REG | CMD_WRITE; reg 114 drivers/net/ieee802154/atusb.c static int atusb_write_reg(struct atusb *atusb, u8 reg, u8 value) reg 118 drivers/net/ieee802154/atusb.c dev_dbg(&usb_dev->dev, "%s: 0x%02x <- 0x%02x\n", __func__, reg, value); reg 121 drivers/net/ieee802154/atusb.c value, reg, NULL, 0, 1000); reg 124 drivers/net/ieee802154/atusb.c static int atusb_read_reg(struct atusb *atusb, u8 reg) reg 135 drivers/net/ieee802154/atusb.c dev_dbg(&usb_dev->dev, "%s: reg = 0x%x\n", __func__, reg); reg 138 drivers/net/ieee802154/atusb.c 0, reg, buffer, 1, 1000); reg 150 drivers/net/ieee802154/atusb.c static int atusb_write_subreg(struct atusb *atusb, u8 reg, u8 mask, reg 157 drivers/net/ieee802154/atusb.c dev_dbg(&usb_dev->dev, "%s: 0x%02x <- 0x%02x\n", __func__, reg, value); reg 159 drivers/net/ieee802154/atusb.c orig = atusb_read_reg(atusb, reg); reg 168 drivers/net/ieee802154/atusb.c ret = atusb_write_reg(atusb, reg, tmp); reg 278 drivers/net/ieee802154/cc2520.c cc2520_write_register(struct cc2520_private *priv, u8 reg, u8 value) reg 293 drivers/net/ieee802154/cc2520.c if (reg <= CC2520_FREG_MASK) { reg 294 drivers/net/ieee802154/cc2520.c priv->buf[xfer.len++] = CC2520_CMD_REGISTER_WRITE | reg; reg 298 drivers/net/ieee802154/cc2520.c priv->buf[xfer.len++] = reg; reg 311 drivers/net/ieee802154/cc2520.c cc2520_write_ram(struct cc2520_private *priv, u16 reg, u8 len, u8 *data) reg 328 drivers/net/ieee802154/cc2520.c ((reg >> 8) & 0xff)); reg 329 drivers/net/ieee802154/cc2520.c priv->buf[xfer_head.len++] = reg & 0xff; reg 345 drivers/net/ieee802154/cc2520.c cc2520_read_register(struct cc2520_private *priv, u8 reg, u8 *data) reg 366 drivers/net/ieee802154/cc2520.c priv->buf[xfer1.len++] = reg; reg 140 drivers/net/ieee802154/mcr20a.c #define MCR20A_READSHORT(reg) ((reg) << 1) reg 141 drivers/net/ieee802154/mcr20a.c #define MCR20A_WRITESHORT(reg) ((reg) << 1 | 1) reg 142 drivers/net/ieee802154/mcr20a.c #define MCR20A_READLONG(reg) (1 << 15 | (reg) << 5) reg 143 drivers/net/ieee802154/mcr20a.c #define MCR20A_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4) reg 149 drivers/net/ieee802154/mcr20a.c mcr20a_dar_writeable(struct device *dev, unsigned int reg) reg 151 drivers/net/ieee802154/mcr20a.c switch (reg) { reg 191 drivers/net/ieee802154/mcr20a.c mcr20a_dar_readable(struct device *dev, unsigned int reg) reg 196 drivers/net/ieee802154/mcr20a.c rc = mcr20a_dar_writeable(dev, reg); reg 201 drivers/net/ieee802154/mcr20a.c switch (reg) { reg 220 drivers/net/ieee802154/mcr20a.c mcr20a_dar_volatile(struct device *dev, unsigned int reg) reg 223 drivers/net/ieee802154/mcr20a.c switch (reg) { reg 235 drivers/net/ieee802154/mcr20a.c mcr20a_dar_precious(struct device *dev, unsigned int reg) reg 238 drivers/net/ieee802154/mcr20a.c switch (reg) { reg 264 drivers/net/ieee802154/mcr20a.c mcr20a_iar_writeable(struct device *dev, unsigned int reg) reg 266 drivers/net/ieee802154/mcr20a.c switch (reg) { reg 345 drivers/net/ieee802154/mcr20a.c mcr20a_iar_readable(struct device *dev, unsigned int reg) reg 350 drivers/net/ieee802154/mcr20a.c rc = mcr20a_iar_writeable(dev, reg); reg 355 drivers/net/ieee802154/mcr20a.c switch (reg) { reg 369 drivers/net/ieee802154/mcr20a.c mcr20a_iar_volatile(struct device *dev, unsigned int reg) reg 372 drivers/net/ieee802154/mcr20a.c switch (reg) { reg 248 drivers/net/ieee802154/mrf24j40.c #define MRF24J40_READSHORT(reg) ((reg) << 1) reg 249 drivers/net/ieee802154/mrf24j40.c #define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1) reg 250 drivers/net/ieee802154/mrf24j40.c #define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5) reg 251 drivers/net/ieee802154/mrf24j40.c #define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4) reg 259 drivers/net/ieee802154/mrf24j40.c mrf24j40_short_reg_writeable(struct device *dev, unsigned int reg) reg 261 drivers/net/ieee802154/mrf24j40.c switch (reg) { reg 325 drivers/net/ieee802154/mrf24j40.c mrf24j40_short_reg_readable(struct device *dev, unsigned int reg) reg 330 drivers/net/ieee802154/mrf24j40.c rc = mrf24j40_short_reg_writeable(dev, reg); reg 335 drivers/net/ieee802154/mrf24j40.c switch (reg) { reg 345 drivers/net/ieee802154/mrf24j40.c mrf24j40_short_reg_volatile(struct device *dev, unsigned int reg) reg 348 drivers/net/ieee802154/mrf24j40.c switch (reg) { reg 373 drivers/net/ieee802154/mrf24j40.c mrf24j40_short_reg_precious(struct device *dev, unsigned int reg) reg 376 drivers/net/ieee802154/mrf24j40.c switch (reg) { reg 400 drivers/net/ieee802154/mrf24j40.c mrf24j40_long_reg_writeable(struct device *dev, unsigned int reg) reg 402 drivers/net/ieee802154/mrf24j40.c switch (reg) { reg 453 drivers/net/ieee802154/mrf24j40.c mrf24j40_long_reg_readable(struct device *dev, unsigned int reg) reg 458 drivers/net/ieee802154/mrf24j40.c rc = mrf24j40_long_reg_writeable(dev, reg); reg 463 drivers/net/ieee802154/mrf24j40.c switch (reg) { reg 475 drivers/net/ieee802154/mrf24j40.c mrf24j40_long_reg_volatile(struct device *dev, unsigned int reg) reg 478 drivers/net/ieee802154/mrf24j40.c switch (reg) { reg 525 drivers/net/ieee802154/mrf24j40.c mrf24j40_long_regmap_read(void *context, const void *reg, size_t reg_size, reg 530 drivers/net/ieee802154/mrf24j40.c return spi_write_then_read(spi, reg, reg_size, val, val_size); reg 565 drivers/net/ieee802154/mrf24j40.c static int write_tx_buf(struct mrf24j40 *devrec, u16 reg, reg 577 drivers/net/ieee802154/mrf24j40.c cmd = MRF24J40_WRITELONG(reg); reg 96 drivers/net/mdio.c int devad, reg; reg 100 drivers/net/mdio.c reg = mdio->mdio_read(mdio->dev, mdio->prtad, reg 102 drivers/net/mdio.c return reg >= 0 && !(reg & MDIO_STAT2_RXFAULT); reg 118 drivers/net/mdio.c reg = mdio->mdio_read(mdio->dev, mdio->prtad, reg 120 drivers/net/mdio.c if (reg < 0 || reg 121 drivers/net/mdio.c (reg & (MDIO_STAT1_FAULT | MDIO_STAT1_LSTATUS)) != reg 151 drivers/net/mdio.c int reg; reg 153 drivers/net/mdio.c reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN, addr); reg 154 drivers/net/mdio.c if (reg & ADVERTISE_10HALF) reg 156 drivers/net/mdio.c if (reg & ADVERTISE_10FULL) reg 158 drivers/net/mdio.c if (reg & ADVERTISE_100HALF) reg 160 drivers/net/mdio.c if (reg & ADVERTISE_100FULL) reg 162 drivers/net/mdio.c if (reg & ADVERTISE_PAUSE_CAP) reg 164 drivers/net/mdio.c if (reg & ADVERTISE_PAUSE_ASYM) reg 187 drivers/net/mdio.c int reg; reg 198 drivers/net/mdio.c reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD, reg 200 drivers/net/mdio.c switch (reg & MDIO_PMA_CTRL2_TYPE) { reg 207 drivers/net/mdio.c reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD, reg 209 drivers/net/mdio.c if (reg & MDIO_SPEED_10G) reg 211 drivers/net/mdio.c if (reg & MDIO_PMA_SPEED_1000) reg 214 drivers/net/mdio.c if (reg & MDIO_PMA_SPEED_100) reg 217 drivers/net/mdio.c if (reg & MDIO_PMA_SPEED_10) reg 234 drivers/net/mdio.c reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD, reg 236 drivers/net/mdio.c if (reg & MDIO_PMA_EXTABLE_10GBKX4) reg 238 drivers/net/mdio.c if (reg & MDIO_PMA_EXTABLE_10GBKR) reg 240 drivers/net/mdio.c if (reg & MDIO_PMA_EXTABLE_1000BKX) reg 242 drivers/net/mdio.c reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD, reg 244 drivers/net/mdio.c if (reg & MDIO_PMA_10GBR_FECABLE_ABLE) reg 259 drivers/net/mdio.c reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN, reg 261 drivers/net/mdio.c if (reg & MDIO_AN_CTRL1_ENABLE) { reg 311 drivers/net/mdio.c reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD, reg 313 drivers/net/mdio.c speed = (((reg & MDIO_PMA_CTRL1_SPEED1000) ? 100 : 1) reg 314 drivers/net/mdio.c * ((reg & MDIO_PMA_CTRL1_SPEED100) ? 100 : 10)); reg 315 drivers/net/mdio.c ecmd->duplex = (reg & MDIO_CTRL1_FULLDPLX || reg 359 drivers/net/mdio.c int reg; reg 369 drivers/net/mdio.c reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD, reg 371 drivers/net/mdio.c switch (reg & MDIO_PMA_CTRL2_TYPE) { reg 378 drivers/net/mdio.c reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD, reg 380 drivers/net/mdio.c if (reg & MDIO_SPEED_10G) reg 382 drivers/net/mdio.c if (reg & MDIO_PMA_SPEED_1000) reg 385 drivers/net/mdio.c if (reg & MDIO_PMA_SPEED_100) reg 388 drivers/net/mdio.c if (reg & MDIO_PMA_SPEED_10) reg 405 drivers/net/mdio.c reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD, reg 407 drivers/net/mdio.c if (reg & MDIO_PMA_EXTABLE_10GBKX4) reg 409 drivers/net/mdio.c if (reg & MDIO_PMA_EXTABLE_10GBKR) reg 411 drivers/net/mdio.c if (reg & MDIO_PMA_EXTABLE_1000BKX) reg 413 drivers/net/mdio.c reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD, reg 415 drivers/net/mdio.c if (reg & MDIO_PMA_10GBR_FECABLE_ABLE) reg 430 drivers/net/mdio.c reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_AN, reg 432 drivers/net/mdio.c if (reg & MDIO_AN_CTRL1_ENABLE) { reg 483 drivers/net/mdio.c reg = mdio->mdio_read(mdio->dev, mdio->prtad, MDIO_MMD_PMAPMD, reg 485 drivers/net/mdio.c speed = (((reg & MDIO_PMA_CTRL1_SPEED1000) ? 100 : 1) reg 486 drivers/net/mdio.c * ((reg & MDIO_PMA_CTRL1_SPEED100) ? 100 : 10)); reg 487 drivers/net/mdio.c cmd->base.duplex = (reg & MDIO_CTRL1_FULLDPLX || reg 426 drivers/net/mii.c int reg; reg 428 drivers/net/mii.c reg = mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR); reg 429 drivers/net/mii.c if (reg & BMSR_ESTATEN) { reg 430 drivers/net/mii.c reg = mii->mdio_read(mii->dev, mii->phy_id, MII_ESTATUS); reg 431 drivers/net/mii.c if (reg & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) reg 114 drivers/net/phy/adin.c int reg; reg 189 drivers/net/phy/adin.c return tbl[i].reg; reg 221 drivers/net/phy/adin.c int reg; reg 228 drivers/net/phy/adin.c reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG); reg 229 drivers/net/phy/adin.c if (reg < 0) reg 230 drivers/net/phy/adin.c return reg; reg 232 drivers/net/phy/adin.c reg |= ADIN1300_GE_RGMII_EN; reg 236 drivers/net/phy/adin.c reg |= ADIN1300_GE_RGMII_RXID_EN; reg 241 drivers/net/phy/adin.c reg &= ~ADIN1300_GE_RGMII_RX_MSK; reg 242 drivers/net/phy/adin.c reg |= ADIN1300_GE_RGMII_RX_SEL(val); reg 244 drivers/net/phy/adin.c reg &= ~ADIN1300_GE_RGMII_RXID_EN; reg 249 drivers/net/phy/adin.c reg |= ADIN1300_GE_RGMII_TXID_EN; reg 254 drivers/net/phy/adin.c reg &= ~ADIN1300_GE_RGMII_GTX_MSK; reg 255 drivers/net/phy/adin.c reg |= ADIN1300_GE_RGMII_GTX_SEL(val); reg 257 drivers/net/phy/adin.c reg &= ~ADIN1300_GE_RGMII_TXID_EN; reg 261 drivers/net/phy/adin.c ADIN1300_GE_RGMII_CFG_REG, reg); reg 267 drivers/net/phy/adin.c int reg; reg 274 drivers/net/phy/adin.c reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG); reg 275 drivers/net/phy/adin.c if (reg < 0) reg 276 drivers/net/phy/adin.c return reg; reg 278 drivers/net/phy/adin.c reg |= ADIN1300_GE_RMII_EN; reg 284 drivers/net/phy/adin.c reg &= ~ADIN1300_GE_RMII_FIFO_DEPTH_MSK; reg 285 drivers/net/phy/adin.c reg |= ADIN1300_GE_RMII_FIFO_DEPTH_SEL(val); reg 288 drivers/net/phy/adin.c ADIN1300_GE_RMII_CFG_REG, reg); reg 520 drivers/net/phy/adin.c int reg; reg 537 drivers/net/phy/adin.c reg = phy_read(phydev, ADIN1300_PHY_CTRL1); reg 538 drivers/net/phy/adin.c if (reg < 0) reg 539 drivers/net/phy/adin.c return reg; reg 542 drivers/net/phy/adin.c reg |= ADIN1300_MAN_MDIX_EN; reg 544 drivers/net/phy/adin.c reg &= ~ADIN1300_MAN_MDIX_EN; reg 547 drivers/net/phy/adin.c reg |= ADIN1300_AUTO_MDI_EN; reg 549 drivers/net/phy/adin.c reg &= ~ADIN1300_AUTO_MDI_EN; reg 551 drivers/net/phy/adin.c return phy_write(phydev, ADIN1300_PHY_CTRL1, reg); reg 569 drivers/net/phy/adin.c int reg; reg 571 drivers/net/phy/adin.c reg = phy_read(phydev, ADIN1300_PHY_CTRL1); reg 572 drivers/net/phy/adin.c if (reg < 0) reg 573 drivers/net/phy/adin.c return reg; reg 575 drivers/net/phy/adin.c auto_en = !!(reg & ADIN1300_AUTO_MDI_EN); reg 576 drivers/net/phy/adin.c mdix_en = !!(reg & ADIN1300_MAN_MDIX_EN); reg 592 drivers/net/phy/adin.c reg = phy_read(phydev, ADIN1300_PHY_STATUS1); reg 593 drivers/net/phy/adin.c if (reg < 0) reg 594 drivers/net/phy/adin.c return reg; reg 596 drivers/net/phy/adin.c swapped = !!(reg & ADIN1300_PAIR_01_SWAP); reg 56 drivers/net/phy/aquantia_hwmon.c static int aqr_hwmon_get(struct phy_device *phydev, int reg, long *value) reg 58 drivers/net/phy/aquantia_hwmon.c int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg); reg 69 drivers/net/phy/aquantia_hwmon.c static int aqr_hwmon_set(struct phy_device *phydev, int reg, long value) reg 79 drivers/net/phy/aquantia_hwmon.c return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp); reg 82 drivers/net/phy/aquantia_hwmon.c static int aqr_hwmon_test_bit(struct phy_device *phydev, int reg, int bit) reg 84 drivers/net/phy/aquantia_hwmon.c int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg); reg 108 drivers/net/phy/aquantia_hwmon.c int reg; reg 115 drivers/net/phy/aquantia_hwmon.c reg = aqr_hwmon_test_bit(phydev, VEND1_THERMAL_STAT2, reg 117 drivers/net/phy/aquantia_hwmon.c if (reg < 0) reg 118 drivers/net/phy/aquantia_hwmon.c return reg; reg 119 drivers/net/phy/aquantia_hwmon.c if (!reg) reg 126 drivers/net/phy/aquantia_main.c int reg; reg 171 drivers/net/phy/aquantia_main.c val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); reg 177 drivers/net/phy/aquantia_main.c val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); reg 209 drivers/net/phy/aquantia_main.c u16 reg; reg 224 drivers/net/phy/aquantia_main.c reg = 0; reg 227 drivers/net/phy/aquantia_main.c reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; reg 231 drivers/net/phy/aquantia_main.c reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; reg 235 drivers/net/phy/aquantia_main.c MDIO_AN_VEND_PROV_1000BASET_FULL, reg); reg 266 drivers/net/phy/aquantia_main.c int reg; reg 268 drivers/net/phy/aquantia_main.c reg = phy_read_mmd(phydev, MDIO_MMD_AN, reg 270 drivers/net/phy/aquantia_main.c return (reg < 0) ? reg : 0; reg 87 drivers/net/phy/at803x.c static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) reg 91 drivers/net/phy/at803x.c ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); reg 98 drivers/net/phy/at803x.c static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, reg 104 drivers/net/phy/at803x.c ret = at803x_debug_reg_read(phydev, reg); reg 77 drivers/net/phy/bcm-cygnus.c int reg, rc; reg 79 drivers/net/phy/bcm-cygnus.c reg = phy_read(phydev, MII_BCM54XX_ECR); reg 80 drivers/net/phy/bcm-cygnus.c if (reg < 0) reg 81 drivers/net/phy/bcm-cygnus.c return reg; reg 84 drivers/net/phy/bcm-cygnus.c reg |= MII_BCM54XX_ECR_IM; reg 85 drivers/net/phy/bcm-cygnus.c rc = phy_write(phydev, MII_BCM54XX_ECR, reg); reg 90 drivers/net/phy/bcm-cygnus.c reg = ~(MII_BCM54XX_INT_DUPLEX | reg 93 drivers/net/phy/bcm-cygnus.c rc = phy_write(phydev, MII_BCM54XX_IMR, reg); reg 17 drivers/net/phy/bcm-phy-lib.c int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val) reg 21 drivers/net/phy/bcm-phy-lib.c rc = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg); reg 29 drivers/net/phy/bcm-phy-lib.c int bcm_phy_read_exp(struct phy_device *phydev, u16 reg) reg 33 drivers/net/phy/bcm-phy-lib.c val = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg); reg 64 drivers/net/phy/bcm-phy-lib.c u16 reg, u16 chl, u16 val) reg 80 drivers/net/phy/bcm-phy-lib.c tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg; reg 88 drivers/net/phy/bcm-phy-lib.c u16 reg, u16 chl) reg 104 drivers/net/phy/bcm-phy-lib.c tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg; reg 113 drivers/net/phy/bcm-phy-lib.c int reg; reg 116 drivers/net/phy/bcm-phy-lib.c reg = phy_read(phydev, MII_BCM54XX_ISR); reg 117 drivers/net/phy/bcm-phy-lib.c if (reg < 0) reg 118 drivers/net/phy/bcm-phy-lib.c return reg; reg 126 drivers/net/phy/bcm-phy-lib.c int reg; reg 128 drivers/net/phy/bcm-phy-lib.c reg = phy_read(phydev, MII_BCM54XX_ECR); reg 129 drivers/net/phy/bcm-phy-lib.c if (reg < 0) reg 130 drivers/net/phy/bcm-phy-lib.c return reg; reg 133 drivers/net/phy/bcm-phy-lib.c reg &= ~MII_BCM54XX_ECR_IM; reg 135 drivers/net/phy/bcm-phy-lib.c reg |= MII_BCM54XX_ECR_IM; reg 137 drivers/net/phy/bcm-phy-lib.c return phy_write(phydev, MII_BCM54XX_ECR, reg); reg 311 drivers/net/phy/bcm-phy-lib.c u8 reg; reg 351 drivers/net/phy/bcm-phy-lib.c val = phy_read(phydev, stat.reg); reg 30 drivers/net/phy/bcm-phy-lib.h int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val); reg 31 drivers/net/phy/bcm-phy-lib.h int bcm_phy_read_exp(struct phy_device *phydev, u16 reg); reg 34 drivers/net/phy/bcm-phy-lib.h u16 reg, u16 val) reg 36 drivers/net/phy/bcm-phy-lib.h return bcm_phy_write_exp(phydev, reg | MII_BCM54XX_EXP_SEL_ER, val); reg 43 drivers/net/phy/bcm-phy-lib.h u16 reg, u16 chl, u16 value); reg 45 drivers/net/phy/bcm-phy-lib.h u16 reg, u16 chl); reg 22 drivers/net/phy/bcm63xx.c int reg, err; reg 24 drivers/net/phy/bcm63xx.c reg = phy_read(phydev, MII_BCM63XX_IR); reg 25 drivers/net/phy/bcm63xx.c if (reg < 0) reg 26 drivers/net/phy/bcm63xx.c return reg; reg 29 drivers/net/phy/bcm63xx.c reg &= ~MII_BCM63XX_IR_GMASK; reg 31 drivers/net/phy/bcm63xx.c reg |= MII_BCM63XX_IR_GMASK; reg 33 drivers/net/phy/bcm63xx.c err = phy_write(phydev, MII_BCM63XX_IR, reg); reg 39 drivers/net/phy/bcm63xx.c int reg, err; reg 44 drivers/net/phy/bcm63xx.c reg = phy_read(phydev, MII_BCM63XX_IR); reg 45 drivers/net/phy/bcm63xx.c if (reg < 0) reg 46 drivers/net/phy/bcm63xx.c return reg; reg 49 drivers/net/phy/bcm63xx.c reg |= MII_BCM63XX_IR_GMASK; reg 50 drivers/net/phy/bcm63xx.c err = phy_write(phydev, MII_BCM63XX_IR, reg); reg 55 drivers/net/phy/bcm63xx.c reg = ~(MII_BCM63XX_IR_DUPLEX | reg 59 drivers/net/phy/bcm63xx.c return phy_write(phydev, MII_BCM63XX_IR, reg); reg 445 drivers/net/phy/bcm7xxx.c int reg; reg 459 drivers/net/phy/bcm7xxx.c bcm7xxx_suspend_cfg[i].reg, reg 54 drivers/net/phy/bcm87xx.c u16 reg = be32_to_cpup(paddr++); reg 58 drivers/net/phy/bcm87xx.c u32 regnum = MII_ADDR_C45 | (devid << 16) | reg; reg 140 drivers/net/phy/bcm87xx.c int reg, err; reg 142 drivers/net/phy/bcm87xx.c reg = phy_read(phydev, BCM87XX_LASI_CONTROL); reg 144 drivers/net/phy/bcm87xx.c if (reg < 0) reg 145 drivers/net/phy/bcm87xx.c return reg; reg 148 drivers/net/phy/bcm87xx.c reg |= 1; reg 150 drivers/net/phy/bcm87xx.c reg &= ~1; reg 152 drivers/net/phy/bcm87xx.c err = phy_write(phydev, BCM87XX_LASI_CONTROL, reg); reg 158 drivers/net/phy/bcm87xx.c int reg; reg 160 drivers/net/phy/bcm87xx.c reg = phy_read(phydev, BCM87XX_LASI_STATUS); reg 162 drivers/net/phy/bcm87xx.c if (reg < 0) { reg 165 drivers/net/phy/bcm87xx.c reg); reg 168 drivers/net/phy/bcm87xx.c return (reg & 1) != 0; reg 48 drivers/net/phy/broadcom.c int reg; reg 61 drivers/net/phy/broadcom.c reg = bcm54xx_auxctl_read(phydev, reg 64 drivers/net/phy/broadcom.c reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN; reg 66 drivers/net/phy/broadcom.c reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK; reg 68 drivers/net/phy/broadcom.c MII_BCM54XX_AUXCTL_MISC_WREN | reg); reg 75 drivers/net/phy/broadcom.c reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0); reg 77 drivers/net/phy/broadcom.c BCM54612E_LED4_CLK125OUT_EN | reg); reg 269 drivers/net/phy/broadcom.c int reg, err, val; reg 271 drivers/net/phy/broadcom.c reg = phy_read(phydev, MII_BCM54XX_ECR); reg 272 drivers/net/phy/broadcom.c if (reg < 0) reg 273 drivers/net/phy/broadcom.c return reg; reg 276 drivers/net/phy/broadcom.c reg |= MII_BCM54XX_ECR_IM; reg 277 drivers/net/phy/broadcom.c err = phy_write(phydev, MII_BCM54XX_ECR, reg); reg 282 drivers/net/phy/broadcom.c reg = ~(MII_BCM54XX_INT_DUPLEX | reg 285 drivers/net/phy/broadcom.c err = phy_write(phydev, MII_BCM54XX_IMR, reg); reg 339 drivers/net/phy/broadcom.c int err, reg; reg 347 drivers/net/phy/broadcom.c reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_SSD); reg 349 drivers/net/phy/broadcom.c reg | reg 356 drivers/net/phy/broadcom.c reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD; reg 357 drivers/net/phy/broadcom.c err = bcm_phy_read_exp(phydev, reg); reg 360 drivers/net/phy/broadcom.c err = bcm_phy_write_exp(phydev, reg, err | reg 369 drivers/net/phy/broadcom.c reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD; reg 370 drivers/net/phy/broadcom.c err = bcm_phy_read_exp(phydev, reg); reg 373 drivers/net/phy/broadcom.c err = bcm_phy_write_exp(phydev, reg, reg 381 drivers/net/phy/broadcom.c reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_MODE); reg 383 drivers/net/phy/broadcom.c reg | BCM5482_SHD_MODE_1000BX); reg 462 drivers/net/phy/broadcom.c static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set) reg 466 drivers/net/phy/broadcom.c val = phy_read(phydev, reg); reg 470 drivers/net/phy/broadcom.c return phy_write(phydev, reg, val | set); reg 475 drivers/net/phy/broadcom.c int reg, err, err2, brcmtest; reg 482 drivers/net/phy/broadcom.c reg = phy_read(phydev, MII_BRCM_FET_INTREG); reg 483 drivers/net/phy/broadcom.c if (reg < 0) reg 484 drivers/net/phy/broadcom.c return reg; reg 487 drivers/net/phy/broadcom.c reg = MII_BRCM_FET_IR_DUPLEX_EN | reg 493 drivers/net/phy/broadcom.c err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); reg 502 drivers/net/phy/broadcom.c reg = brcmtest | MII_BRCM_FET_BT_SRE; reg 504 drivers/net/phy/broadcom.c err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); reg 509 drivers/net/phy/broadcom.c reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4); reg 510 drivers/net/phy/broadcom.c if (reg < 0) { reg 511 drivers/net/phy/broadcom.c err = reg; reg 515 drivers/net/phy/broadcom.c reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK; reg 516 drivers/net/phy/broadcom.c reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1; reg 518 drivers/net/phy/broadcom.c err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg); reg 545 drivers/net/phy/broadcom.c int reg; reg 548 drivers/net/phy/broadcom.c reg = phy_read(phydev, MII_BRCM_FET_INTREG); reg 549 drivers/net/phy/broadcom.c if (reg < 0) reg 550 drivers/net/phy/broadcom.c return reg; reg 557 drivers/net/phy/broadcom.c int reg, err; reg 559 drivers/net/phy/broadcom.c reg = phy_read(phydev, MII_BRCM_FET_INTREG); reg 560 drivers/net/phy/broadcom.c if (reg < 0) reg 561 drivers/net/phy/broadcom.c return reg; reg 564 drivers/net/phy/broadcom.c reg &= ~MII_BRCM_FET_IR_MASK; reg 566 drivers/net/phy/broadcom.c reg |= MII_BRCM_FET_IR_MASK; reg 568 drivers/net/phy/broadcom.c err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); reg 191 drivers/net/phy/intel-xway.c int reg, err; reg 195 drivers/net/phy/intel-xway.c reg = phy_read(phydev, MII_CTRL1000); reg 196 drivers/net/phy/intel-xway.c reg |= ADVERTISED_MPD; reg 197 drivers/net/phy/intel-xway.c err = phy_write(phydev, MII_CTRL1000, reg); reg 206 drivers/net/phy/intel-xway.c int reg; reg 208 drivers/net/phy/intel-xway.c reg = phy_read(phydev, XWAY_MDIO_ISTAT); reg 209 drivers/net/phy/intel-xway.c return (reg < 0) ? reg : 0; reg 214 drivers/net/phy/intel-xway.c int reg; reg 216 drivers/net/phy/intel-xway.c reg = phy_read(phydev, XWAY_MDIO_ISTAT); reg 217 drivers/net/phy/intel-xway.c return reg & XWAY_MDIO_INIT_MASK; reg 181 drivers/net/phy/marvell.c u8 reg; reg 241 drivers/net/phy/marvell.c int reg; reg 246 drivers/net/phy/marvell.c reg = phy_read(phydev, MII_M1011_PHY_SCR); reg 247 drivers/net/phy/marvell.c if (reg < 0) reg 248 drivers/net/phy/marvell.c return reg; reg 250 drivers/net/phy/marvell.c val = reg; reg 266 drivers/net/phy/marvell.c if (val != reg) { reg 273 drivers/net/phy/marvell.c return val != reg; reg 279 drivers/net/phy/marvell.c int reg; reg 281 drivers/net/phy/marvell.c reg = phy_read(phydev, MII_M1011_PHY_SCR); reg 282 drivers/net/phy/marvell.c if (reg < 0) reg 283 drivers/net/phy/marvell.c return reg; reg 285 drivers/net/phy/marvell.c reg &= MII_M1011_PHY_SRC_DOWNSHIFT_MASK; reg 286 drivers/net/phy/marvell.c reg |= ((retries - 1) << MII_M1011_PHY_SCR_DOWNSHIFT_SHIFT); reg 288 drivers/net/phy/marvell.c reg |= MII_M1011_PHY_SCR_DOWNSHIFT_EN; reg 290 drivers/net/phy/marvell.c return phy_write(phydev, MII_M1011_PHY_SCR, reg); reg 396 drivers/net/phy/marvell.c u16 reg = be32_to_cpup(paddr + i + 1); reg 410 drivers/net/phy/marvell.c val = __phy_read(phydev, reg); reg 419 drivers/net/phy/marvell.c ret = __phy_write(phydev, reg, val); reg 1616 drivers/net/phy/marvell.c val = phy_read_paged(phydev, stat.page, stat.reg); reg 319 drivers/net/phy/marvell10g.c u16 reg; reg 337 drivers/net/phy/marvell10g.c reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); reg 339 drivers/net/phy/marvell10g.c ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg); reg 66 drivers/net/phy/mdio-bcm-iproc.c static int iproc_mdio_read(struct mii_bus *bus, int phy_id, int reg) reg 78 drivers/net/phy/mdio-bcm-iproc.c (reg << MII_DATA_RA_SHIFT) | reg 95 drivers/net/phy/mdio-bcm-iproc.c int reg, u16 val) reg 107 drivers/net/phy/mdio-bcm-iproc.c (reg << MII_DATA_RA_SHIFT) | reg 71 drivers/net/phy/mdio-bcm-unimac.c u32 reg; reg 73 drivers/net/phy/mdio-bcm-unimac.c reg = unimac_mdio_readl(priv, MDIO_CMD); reg 74 drivers/net/phy/mdio-bcm-unimac.c reg |= MDIO_START_BUSY; reg 75 drivers/net/phy/mdio-bcm-unimac.c unimac_mdio_writel(priv, reg, MDIO_CMD); reg 98 drivers/net/phy/mdio-bcm-unimac.c static int unimac_mdio_read(struct mii_bus *bus, int phy_id, int reg) reg 105 drivers/net/phy/mdio-bcm-unimac.c cmd = MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT); reg 129 drivers/net/phy/mdio-bcm-unimac.c int reg, u16 val) reg 136 drivers/net/phy/mdio-bcm-unimac.c (reg << MDIO_REG_SHIFT) | (0xffff & val); reg 191 drivers/net/phy/mdio-bcm-unimac.c u32 reg, div; reg 211 drivers/net/phy/mdio-bcm-unimac.c reg = unimac_mdio_readl(priv, MDIO_CFG); reg 212 drivers/net/phy/mdio-bcm-unimac.c reg &= ~(MDIO_CLK_DIV_MASK << MDIO_CLK_DIV_SHIFT); reg 213 drivers/net/phy/mdio-bcm-unimac.c reg |= div << MDIO_CLK_DIV_SHIFT; reg 214 drivers/net/phy/mdio-bcm-unimac.c unimac_mdio_writel(priv, reg, MDIO_CFG); reg 94 drivers/net/phy/mdio-bitbang.c static void mdiobb_cmd(struct mdiobb_ctrl *ctrl, int op, u8 phy, u8 reg) reg 125 drivers/net/phy/mdio-bitbang.c mdiobb_send_num(ctrl, reg, 5); reg 137 drivers/net/phy/mdio-bitbang.c unsigned int reg = addr & 0xFFFF; reg 144 drivers/net/phy/mdio-bitbang.c mdiobb_send_num(ctrl, reg, 16); reg 152 drivers/net/phy/mdio-bitbang.c static int mdiobb_read(struct mii_bus *bus, int phy, int reg) reg 157 drivers/net/phy/mdio-bitbang.c if (reg & MII_ADDR_C45) { reg 158 drivers/net/phy/mdio-bitbang.c reg = mdiobb_cmd_addr(ctrl, phy, reg); reg 159 drivers/net/phy/mdio-bitbang.c mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg); reg 161 drivers/net/phy/mdio-bitbang.c mdiobb_cmd(ctrl, MDIO_READ, phy, reg); reg 184 drivers/net/phy/mdio-bitbang.c static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val) reg 188 drivers/net/phy/mdio-bitbang.c if (reg & MII_ADDR_C45) { reg 189 drivers/net/phy/mdio-bitbang.c reg = mdiobb_cmd_addr(ctrl, phy, reg); reg 190 drivers/net/phy/mdio-bitbang.c mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg); reg 192 drivers/net/phy/mdio-bitbang.c mdiobb_cmd(ctrl, MDIO_WRITE, phy, reg); reg 32 drivers/net/phy/mdio-i2c.c static int i2c_mii_read(struct mii_bus *bus, int phy_id, int reg) reg 36 drivers/net/phy/mdio-i2c.c u8 data[2], dev_addr = reg; reg 59 drivers/net/phy/mdio-i2c.c static int i2c_mii_write(struct mii_bus *bus, int phy_id, int reg, u16 val) reg 69 drivers/net/phy/mdio-i2c.c data[0] = reg; reg 108 drivers/net/phy/mdio-mux-bcm-iproc.c u16 phyid, u32 reg, u16 val, u32 op) reg 121 drivers/net/phy/mdio-mux-bcm-iproc.c if (reg & MII_ADDR_C45) reg 126 drivers/net/phy/mdio-mux-bcm-iproc.c writel(reg, base + MDIO_ADDR_OFFSET); reg 140 drivers/net/phy/mdio-mux-bcm-iproc.c static int iproc_mdiomux_read(struct mii_bus *bus, int phyid, int reg) reg 145 drivers/net/phy/mdio-mux-bcm-iproc.c ret = start_miim_ops(md->base, phyid, reg, 0, MDIO_CTRL_READ_OP); reg 153 drivers/net/phy/mdio-mux-bcm-iproc.c int phyid, int reg, u16 val) reg 159 drivers/net/phy/mdio-mux-bcm-iproc.c ret = start_miim_ops(md->base, phyid, reg, val, MDIO_CTRL_WRITE_OP); reg 258 drivers/net/phy/mdio-mux-meson-g12a.c mux->reg = priv->regs + ETH_PLL_CTL0; reg 80 drivers/net/phy/mdio-xgene.c int xgene_mdio_rgmii_read(struct mii_bus *bus, int phy_id, int reg) reg 86 drivers/net/phy/mdio-xgene.c data = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg); reg 106 drivers/net/phy/mdio-xgene.c int xgene_mdio_rgmii_write(struct mii_bus *bus, int phy_id, int reg, u16 data) reg 112 drivers/net/phy/mdio-xgene.c val = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg); reg 212 drivers/net/phy/mdio-xgene.c int reg, u16 data) reg 218 drivers/net/phy/mdio-xgene.c val = SET_VAL(HSTPHYADX, phy_id) | SET_VAL(HSTREGADX, reg) | reg 235 drivers/net/phy/mdio-xgene.c static int xgene_xfi_mdio_read(struct mii_bus *bus, int phy_id, int reg) reg 241 drivers/net/phy/mdio-xgene.c val = SET_VAL(HSTPHYADX, phy_id) | SET_VAL(HSTREGADX, reg); reg 126 drivers/net/phy/mdio-xgene.h int xgene_mdio_rgmii_read(struct mii_bus *bus, int phy_id, int reg); reg 127 drivers/net/phy/mdio-xgene.h int xgene_mdio_rgmii_write(struct mii_bus *bus, int phy_id, int reg, u16 data); reg 73 drivers/net/phy/meson-gxl.c unsigned int bank, unsigned int reg) reg 84 drivers/net/phy/meson-gxl.c FIELD_PREP(TSTCNTL_READ_ADDRESS, reg)); reg 96 drivers/net/phy/meson-gxl.c unsigned int bank, unsigned int reg, reg 112 drivers/net/phy/meson-gxl.c FIELD_PREP(TSTCNTL_WRITE_ADDRESS, reg)); reg 77 drivers/net/phy/micrel.c u8 reg; reg 200 drivers/net/phy/micrel.c static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) reg 204 drivers/net/phy/micrel.c switch (reg) { reg 215 drivers/net/phy/micrel.c temp = phy_read(phydev, reg); reg 223 drivers/net/phy/micrel.c rc = phy_write(phydev, reg, temp); reg 404 drivers/net/phy/micrel.c u16 reg, reg 431 drivers/net/phy/micrel.c newval = kszphy_extended_read(phydev, reg); reg 447 drivers/net/phy/micrel.c return kszphy_extended_write(phydev, reg, newval); reg 503 drivers/net/phy/micrel.c u16 reg, size_t field_sz, reg 521 drivers/net/phy/micrel.c newval = phy_read_mmd(phydev, 2, reg); reg 535 drivers/net/phy/micrel.c return phy_write_mmd(phydev, 2, reg, newval); reg 559 drivers/net/phy/micrel.c int reg; reg 561 drivers/net/phy/micrel.c reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD); reg 562 drivers/net/phy/micrel.c if (reg < 0) reg 563 drivers/net/phy/micrel.c return reg; reg 565 drivers/net/phy/micrel.c reg | MII_KSZ9031RN_EDPD_ENABLE); reg 658 drivers/net/phy/micrel.c u16 reg, size_t field_sz, reg 691 drivers/net/phy/micrel.c newval = phy_read_mmd(phydev, 2, reg); reg 705 drivers/net/phy/micrel.c return phy_write_mmd(phydev, 2, reg, newval); reg 867 drivers/net/phy/micrel.c val = phy_read(phydev, stat.reg); reg 234 drivers/net/phy/microchip.c u32 reg = 0; reg 240 drivers/net/phy/microchip.c reg |= led_modes[i] << (i * 4); reg 243 drivers/net/phy/microchip.c reg |= LAN78XX_FORCE_LED_OFF << (i * 4); reg 244 drivers/net/phy/microchip.c (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg); reg 317 drivers/net/phy/mscc.c u16 reg; reg 323 drivers/net/phy/mscc.c u8 reg; reg 331 drivers/net/phy/mscc.c .reg = MSCC_PHY_ERR_RX_CNT, reg 336 drivers/net/phy/mscc.c .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT, reg 341 drivers/net/phy/mscc.c .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT, reg 346 drivers/net/phy/mscc.c .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT, reg 351 drivers/net/phy/mscc.c .reg = MSCC_PHY_EXT_PHY_CNTL_4, reg 360 drivers/net/phy/mscc.c .reg = MSCC_PHY_ERR_RX_CNT, reg 365 drivers/net/phy/mscc.c .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT, reg 370 drivers/net/phy/mscc.c .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT, reg 375 drivers/net/phy/mscc.c .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT, reg 380 drivers/net/phy/mscc.c .reg = MSCC_PHY_EXT_PHY_CNTL_4, reg 385 drivers/net/phy/mscc.c .reg = MSCC_PHY_SERDES_TX_VALID_CNT, reg 390 drivers/net/phy/mscc.c .reg = MSCC_PHY_SERDES_TX_CRC_ERR_CNT, reg 395 drivers/net/phy/mscc.c .reg = MSCC_PHY_SERDES_RX_VALID_CNT, reg 400 drivers/net/phy/mscc.c .reg = MSCC_PHY_SERDES_RX_CRC_ERR_CNT, reg 474 drivers/net/phy/mscc.c priv->hw_stats[i].reg); reg 931 drivers/net/phy/mscc.c vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val); reg 971 drivers/net/phy/mscc.c vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val); reg 1080 drivers/net/phy/mscc.c u16 reg; reg 1089 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); reg 1090 drivers/net/phy/mscc.c reg &= ~EN_PATCH_RAM_TRAP_ADDR(4); reg 1091 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); reg 1096 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); reg 1097 drivers/net/phy/mscc.c reg |= EN_PATCH_RAM_TRAP_ADDR(4); reg 1098 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); reg 1102 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); reg 1103 drivers/net/phy/mscc.c reg &= ~MICRO_NSOFT_RESET; reg 1104 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg); reg 1110 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); reg 1111 drivers/net/phy/mscc.c reg &= ~EN_PATCH_RAM_TRAP_ADDR(4); reg 1112 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); reg 1186 drivers/net/phy/mscc.c u16 reg; reg 1192 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1)); reg 1193 drivers/net/phy/mscc.c if (reg != 0x3eb7) { reg 1198 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1)); reg 1199 drivers/net/phy/mscc.c if (reg != 0x4012) { reg 1204 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); reg 1205 drivers/net/phy/mscc.c if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) { reg 1210 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); reg 1212 drivers/net/phy/mscc.c MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) { reg 1294 drivers/net/phy/mscc.c u16 crc, reg; reg 1301 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); reg 1302 drivers/net/phy/mscc.c reg |= SMI_BROADCAST_WR_EN; reg 1303 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); reg 1321 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); reg 1322 drivers/net/phy/mscc.c reg |= 0x8000; reg 1323 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); reg 1328 drivers/net/phy/mscc.c vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); reg 1337 drivers/net/phy/mscc.c vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); reg 1341 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); reg 1342 drivers/net/phy/mscc.c reg &= ~0x8000; reg 1343 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); reg 1348 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); reg 1349 drivers/net/phy/mscc.c reg &= ~SMI_BROADCAST_WR_EN; reg 1350 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); reg 1462 drivers/net/phy/mscc.c u16 crc, reg; reg 1468 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); reg 1469 drivers/net/phy/mscc.c reg |= SMI_BROADCAST_WR_EN; reg 1470 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); reg 1474 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL); reg 1475 drivers/net/phy/mscc.c reg |= PARALLEL_DET_IGNORE_ADVERTISED; reg 1476 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg); reg 1491 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); reg 1492 drivers/net/phy/mscc.c reg |= 0x8000; reg 1493 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); reg 1499 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_PHY_TR_MSB); reg 1500 drivers/net/phy/mscc.c reg &= ~0x007f; reg 1501 drivers/net/phy/mscc.c reg |= 0x0019; reg 1502 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_PHY_TR_MSB, reg); reg 1507 drivers/net/phy/mscc.c vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); reg 1516 drivers/net/phy/mscc.c vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); reg 1520 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); reg 1521 drivers/net/phy/mscc.c reg &= ~0x8000; reg 1522 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); reg 1527 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); reg 1528 drivers/net/phy/mscc.c reg &= ~SMI_BROADCAST_WR_EN; reg 1529 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); reg 1812 drivers/net/phy/mscc.c u16 reg; reg 1817 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); reg 1818 drivers/net/phy/mscc.c reg |= SMI_BROADCAST_WR_EN; reg 1819 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); reg 1823 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); reg 1824 drivers/net/phy/mscc.c reg |= BIT(15); reg 1825 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); reg 1830 drivers/net/phy/mscc.c vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); reg 1834 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); reg 1835 drivers/net/phy/mscc.c reg &= ~BIT(15); reg 1836 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); reg 1840 drivers/net/phy/mscc.c reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); reg 1841 drivers/net/phy/mscc.c reg &= ~SMI_BROADCAST_WR_EN; reg 1842 drivers/net/phy/mscc.c phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); reg 1848 drivers/net/phy/mscc.c u32 target, u32 reg) reg 1869 drivers/net/phy/mscc.c MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) | reg 1896 drivers/net/phy/mscc.c u32 target, u32 reg, u32 val) reg 1922 drivers/net/phy/mscc.c MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) | reg 1942 drivers/net/phy/mscc.c static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb, reg 1949 drivers/net/phy/mscc.c ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, reg, reg 1957 drivers/net/phy/mscc.c val = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, reg); reg 1971 drivers/net/phy/mscc.c static int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) reg 1973 drivers/net/phy/mscc.c return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ); reg 1977 drivers/net/phy/mscc.c static int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) reg 1979 drivers/net/phy/mscc.c return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE); reg 1988 drivers/net/phy/mscc.c u32 reg; reg 2091 drivers/net/phy/mscc.c reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, reg 2093 drivers/net/phy/mscc.c if (reg == 0xffffffff) { reg 2098 drivers/net/phy/mscc.c } while (time_before(jiffies, deadline) && (reg & BIT(12))); reg 2100 drivers/net/phy/mscc.c if (reg & BIT(12)) { reg 2118 drivers/net/phy/mscc.c reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, reg 2120 drivers/net/phy/mscc.c if (reg == 0xffffffff) { reg 2125 drivers/net/phy/mscc.c } while (time_before(jiffies, deadline) && !(reg & BIT(8))); reg 2127 drivers/net/phy/mscc.c if (!(reg & BIT(8))) { reg 54 drivers/net/phy/national.c static u8 ns_exp_read(struct phy_device *phydev, u16 reg) reg 56 drivers/net/phy/national.c phy_write(phydev, NS_EXP_MEM_ADD, reg); reg 60 drivers/net/phy/national.c static void ns_exp_write(struct phy_device *phydev, u16 reg, u8 data) reg 62 drivers/net/phy/national.c phy_write(phydev, NS_EXP_MEM_ADD, reg); reg 59 drivers/net/phy/nxp-tja11xx.c u8 reg; reg 73 drivers/net/phy/nxp-tja11xx.c static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set) reg 78 drivers/net/phy/nxp-tja11xx.c ret = phy_read(phydev, reg); reg 91 drivers/net/phy/nxp-tja11xx.c static int phy_modify_check(struct phy_device *phydev, u8 reg, reg 96 drivers/net/phy/nxp-tja11xx.c ret = phy_modify(phydev, reg, mask, set); reg 100 drivers/net/phy/nxp-tja11xx.c return tja11xx_check(phydev, reg, mask, set); reg 263 drivers/net/phy/nxp-tja11xx.c ret = phy_read(phydev, tja11xx_hw_stats[i].reg); reg 1455 drivers/net/phy/phylink.c static int phylink_mii_emul_read(unsigned int reg, reg 1467 drivers/net/phy/phylink.c val = swphy_read_reg(reg, &fs); reg 1468 drivers/net/phy/phylink.c if (reg == MII_BMSR) { reg 1476 drivers/net/phy/phylink.c unsigned int reg) reg 1484 drivers/net/phy/phylink.c devad = MII_ADDR_C45 | devad << 16 | reg; reg 1486 drivers/net/phy/phylink.c switch (reg) { reg 1498 drivers/net/phy/phylink.c if (reg == MII_ADVERTISE) reg 1499 drivers/net/phy/phylink.c reg = MDIO_AN_ADVERTISE; reg 1501 drivers/net/phy/phylink.c reg = MDIO_AN_LPA; reg 1507 drivers/net/phy/phylink.c devad = MII_ADDR_C45 | devad << 16 | reg; reg 1510 drivers/net/phy/phylink.c devad = reg; reg 1516 drivers/net/phy/phylink.c unsigned int reg, unsigned int val) reg 1524 drivers/net/phy/phylink.c devad = MII_ADDR_C45 | devad << 16 | reg; reg 1526 drivers/net/phy/phylink.c switch (reg) { reg 1538 drivers/net/phy/phylink.c if (reg == MII_ADVERTISE) reg 1539 drivers/net/phy/phylink.c reg = MDIO_AN_ADVERTISE; reg 1541 drivers/net/phy/phylink.c reg = MDIO_AN_LPA; reg 1547 drivers/net/phy/phylink.c devad = MII_ADDR_C45 | devad << 16 | reg; reg 1550 drivers/net/phy/phylink.c devad = reg; reg 1557 drivers/net/phy/phylink.c unsigned int reg) reg 1566 drivers/net/phy/phylink.c val = phylink_mii_emul_read(reg, &state); reg 1579 drivers/net/phy/phylink.c val = phylink_mii_emul_read(reg, &state); reg 1588 drivers/net/phy/phylink.c unsigned int reg, unsigned int val) reg 123 drivers/net/phy/rockchip.c int reg, err, val; reg 126 drivers/net/phy/rockchip.c reg = phy_read(phydev, MII_INTERNAL_CTRL_STATUS); reg 127 drivers/net/phy/rockchip.c if (reg < 0) reg 128 drivers/net/phy/rockchip.c return reg; reg 130 drivers/net/phy/rockchip.c reg &= ~MII_AUTO_MDIX_EN; reg 131 drivers/net/phy/rockchip.c val = reg; reg 145 drivers/net/phy/rockchip.c if (val != reg) { reg 508 drivers/net/phy/sfp.c static int sfp_hwmon_read_sensor(struct sfp *sfp, int reg, long *value) reg 513 drivers/net/phy/sfp.c err = sfp_read(sfp, true, reg, &val, sizeof(val)); reg 569 drivers/net/phy/sfp.c static int sfp_hwmon_read_temp(struct sfp *sfp, int reg, long *value) reg 573 drivers/net/phy/sfp.c err = sfp_hwmon_read_sensor(sfp, reg, value); reg 582 drivers/net/phy/sfp.c static int sfp_hwmon_read_vcc(struct sfp *sfp, int reg, long *value) reg 586 drivers/net/phy/sfp.c err = sfp_hwmon_read_sensor(sfp, reg, value); reg 595 drivers/net/phy/sfp.c static int sfp_hwmon_read_bias(struct sfp *sfp, int reg, long *value) reg 599 drivers/net/phy/sfp.c err = sfp_hwmon_read_sensor(sfp, reg, value); reg 608 drivers/net/phy/sfp.c static int sfp_hwmon_read_tx_power(struct sfp *sfp, int reg, long *value) reg 612 drivers/net/phy/sfp.c err = sfp_hwmon_read_sensor(sfp, reg, value); reg 621 drivers/net/phy/sfp.c static int sfp_hwmon_read_rx_power(struct sfp *sfp, int reg, long *value) reg 625 drivers/net/phy/sfp.c err = sfp_hwmon_read_sensor(sfp, reg, value); reg 26 drivers/net/phy/smsc.c u8 reg; reg 173 drivers/net/phy/smsc.c val = phy_read(phydev, stat.reg); reg 115 drivers/net/phy/swphy.c int swphy_read_reg(int reg, const struct fixed_phy_status *state) reg 123 drivers/net/phy/swphy.c if (reg > MII_REGS_NUM) reg 148 drivers/net/phy/swphy.c switch (reg) { reg 8 drivers/net/phy/swphy.h int swphy_read_reg(int reg, const struct fixed_phy_status *state); reg 47 drivers/net/phy/teranetics.c int reg; reg 55 drivers/net/phy/teranetics.c reg = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_LNSTAT); reg 56 drivers/net/phy/teranetics.c if (reg < 0 || reg 57 drivers/net/phy/teranetics.c !((reg & MDIO_PHYXS_LANE_READY) == MDIO_PHYXS_LANE_READY)) { reg 62 drivers/net/phy/teranetics.c reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); reg 63 drivers/net/phy/teranetics.c if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS)) reg 51 drivers/net/sungem_phy.c static inline int __sungem_phy_read(struct mii_phy* phy, int id, int reg) reg 53 drivers/net/sungem_phy.c return phy->mdio_read(phy->dev, id, reg); reg 56 drivers/net/sungem_phy.c static inline void __sungem_phy_write(struct mii_phy* phy, int id, int reg, int val) reg 58 drivers/net/sungem_phy.c phy->mdio_write(phy->dev, id, reg, val); reg 61 drivers/net/sungem_phy.c static inline int sungem_phy_read(struct mii_phy* phy, int reg) reg 63 drivers/net/sungem_phy.c return phy->mdio_read(phy->dev, phy->mii_id, reg); reg 66 drivers/net/sungem_phy.c static inline void sungem_phy_write(struct mii_phy* phy, int reg, int val) reg 68 drivers/net/sungem_phy.c phy->mdio_write(phy->dev, phy->mii_id, reg, val); reg 792 drivers/net/usb/asix_devices.c u16 reg; reg 796 drivers/net/usb/asix_devices.c reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS); reg 797 drivers/net/usb/asix_devices.c netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg); reg 803 drivers/net/usb/asix_devices.c reg = asix_mdio_read(dev->net, dev->mii.phy_id, reg 805 drivers/net/usb/asix_devices.c netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg); reg 807 drivers/net/usb/asix_devices.c reg &= 0xf8ff; reg 808 drivers/net/usb/asix_devices.c reg |= (1 + 0x0100); reg 810 drivers/net/usb/asix_devices.c MII_MARVELL_LED_CTRL, reg); reg 812 drivers/net/usb/asix_devices.c reg = asix_mdio_read(dev->net, dev->mii.phy_id, reg 814 drivers/net/usb/asix_devices.c netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg); reg 815 drivers/net/usb/asix_devices.c reg &= 0xfc0f; reg 844 drivers/net/usb/asix_devices.c u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL); reg 846 drivers/net/usb/asix_devices.c netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg); reg 849 drivers/net/usb/asix_devices.c reg &= 0xfc0f; reg 853 drivers/net/usb/asix_devices.c reg |= 0x03e0; reg 856 drivers/net/usb/asix_devices.c reg |= 0x03b0; reg 859 drivers/net/usb/asix_devices.c reg |= 0x02f0; reg 862 drivers/net/usb/asix_devices.c netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg); reg 863 drivers/net/usb/asix_devices.c asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg); reg 195 drivers/net/usb/catc.c #define catc_set_reg(catc, reg, val) catc_ctrl_msg(catc, USB_DIR_OUT, SetReg, val, reg, NULL, 0) reg 196 drivers/net/usb/catc.c #define catc_get_reg(catc, reg, buf) catc_ctrl_msg(catc, USB_DIR_IN, GetReg, 0, reg, buf, 1) reg 204 drivers/net/usb/catc.c #define catc_set_reg_async(catc, reg, val) catc_ctrl_async(catc, USB_DIR_OUT, SetReg, val, reg, NULL, 0, NULL) reg 205 drivers/net/usb/catc.c #define catc_get_reg_async(catc, reg, cb) catc_ctrl_async(catc, USB_DIR_IN, GetReg, 0, reg, NULL, 1, cb) reg 61 drivers/net/usb/dm9601.c static int dm_read(struct usbnet *dev, u8 reg, u16 length, void *data) reg 66 drivers/net/usb/dm9601.c 0, reg, data, length); reg 72 drivers/net/usb/dm9601.c static int dm_read_reg(struct usbnet *dev, u8 reg, u8 *value) reg 74 drivers/net/usb/dm9601.c return dm_read(dev, reg, 1, value); reg 77 drivers/net/usb/dm9601.c static int dm_write(struct usbnet *dev, u8 reg, u16 length, void *data) reg 82 drivers/net/usb/dm9601.c 0, reg, data, length); reg 89 drivers/net/usb/dm9601.c static int dm_write_reg(struct usbnet *dev, u8 reg, u8 value) reg 93 drivers/net/usb/dm9601.c value, reg, NULL, 0); reg 96 drivers/net/usb/dm9601.c static void dm_write_async(struct usbnet *dev, u8 reg, u16 length, void *data) reg 100 drivers/net/usb/dm9601.c 0, reg, data, length); reg 103 drivers/net/usb/dm9601.c static void dm_write_reg_async(struct usbnet *dev, u8 reg, u8 value) reg 107 drivers/net/usb/dm9601.c value, reg, NULL, 0); reg 110 drivers/net/usb/dm9601.c static int dm_read_shared_word(struct usbnet *dev, int phy, u8 reg, __le16 *value) reg 116 drivers/net/usb/dm9601.c dm_write_reg(dev, DM_SHARED_ADDR, phy ? (reg | 0x40) : reg); reg 142 drivers/net/usb/dm9601.c phy, reg, *value, ret); reg 149 drivers/net/usb/dm9601.c static int dm_write_shared_word(struct usbnet *dev, int phy, u8 reg, __le16 value) reg 159 drivers/net/usb/dm9601.c dm_write_reg(dev, DM_SHARED_ADDR, phy ? (reg | 0x40) : reg); reg 2174 drivers/net/usb/lan78xx.c u32 reg; reg 2182 drivers/net/usb/lan78xx.c lan78xx_read_reg(dev, HW_CFG, ®); reg 2183 drivers/net/usb/lan78xx.c reg &= ~(HW_CFG_LED0_EN_ | reg 2187 drivers/net/usb/lan78xx.c reg |= (len > 0) * HW_CFG_LED0_EN_ | reg 2191 drivers/net/usb/lan78xx.c lan78xx_write_reg(dev, HW_CFG, reg); reg 135 drivers/net/usb/net1080.c u8 reg; reg 142 drivers/net/usb/net1080.c for (reg = 0; reg < 0x20; reg++) { reg 146 drivers/net/usb/net1080.c if (reg >= 0x08 && reg <= 0xf) reg 148 drivers/net/usb/net1080.c if (reg >= 0x12 && reg <= 0x1e) reg 151 drivers/net/usb/net1080.c retval = nc_register_read(dev, reg, vp); reg 154 drivers/net/usb/net1080.c reg, retval); reg 156 drivers/net/usb/net1080.c netdev_dbg(dev->net, "reg [0x%x] = 0x%x\n", reg, *vp); reg 1166 drivers/net/usb/r8152.c static int read_mii_word(struct net_device *netdev, int phy_id, int reg) reg 1177 drivers/net/usb/r8152.c ret = r8152_mdio_read(tp, reg); reg 1183 drivers/net/usb/r8152.c void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) reg 1193 drivers/net/usb/r8152.c r8152_mdio_write(tp, reg, val); reg 3256 drivers/net/usb/r8152.c static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) reg 3259 drivers/net/usb/r8152.c ocp_reg_write(tp, OCP_EEE_DATA, reg); reg 3263 drivers/net/usb/r8152.c static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) reg 3267 drivers/net/usb/r8152.c r8152_mmd_indirect(tp, dev, reg); reg 3274 drivers/net/usb/r8152.c static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) reg 3276 drivers/net/usb/r8152.c r8152_mmd_indirect(tp, dev, reg); reg 198 drivers/net/usb/rtl8150.c static int async_set_registers(rtl8150_t *dev, u16 indx, u16 size, u16 reg) reg 212 drivers/net/usb/rtl8150.c req->rx_creg = cpu_to_le16(reg); reg 230 drivers/net/usb/rtl8150.c static int read_mii_word(rtl8150_t * dev, u8 phy, __u8 indx, u16 * reg) reg 248 drivers/net/usb/rtl8150.c *reg = data[0] | (data[1] << 8); reg 254 drivers/net/usb/rtl8150.c static int write_mii_word(rtl8150_t * dev, u8 phy, __u8 indx, u16 reg) reg 260 drivers/net/usb/rtl8150.c data[1] = reg & 0xff; reg 261 drivers/net/usb/rtl8150.c data[2] = (reg >> 8) & 0xff; reg 26 drivers/net/usb/sr9700.c static int sr_read(struct usbnet *dev, u8 reg, u16 length, void *data) reg 30 drivers/net/usb/sr9700.c err = usbnet_read_cmd(dev, SR_RD_REGS, SR_REQ_RD_REG, 0, reg, data, reg 37 drivers/net/usb/sr9700.c static int sr_write(struct usbnet *dev, u8 reg, u16 length, void *data) reg 41 drivers/net/usb/sr9700.c err = usbnet_write_cmd(dev, SR_WR_REGS, SR_REQ_WR_REG, 0, reg, data, reg 48 drivers/net/usb/sr9700.c static int sr_read_reg(struct usbnet *dev, u8 reg, u8 *value) reg 50 drivers/net/usb/sr9700.c return sr_read(dev, reg, 1, value); reg 53 drivers/net/usb/sr9700.c static int sr_write_reg(struct usbnet *dev, u8 reg, u8 value) reg 56 drivers/net/usb/sr9700.c value, reg, NULL, 0); reg 59 drivers/net/usb/sr9700.c static void sr_write_async(struct usbnet *dev, u8 reg, u16 length, void *data) reg 62 drivers/net/usb/sr9700.c 0, reg, data, length); reg 65 drivers/net/usb/sr9700.c static void sr_write_reg_async(struct usbnet *dev, u8 reg, u8 value) reg 68 drivers/net/usb/sr9700.c value, reg, NULL, 0); reg 94 drivers/net/usb/sr9700.c static int sr_share_read_word(struct usbnet *dev, int phy, u8 reg, reg 101 drivers/net/usb/sr9700.c sr_write_reg(dev, SR_EPAR, phy ? (reg | EPAR_PHY_ADR) : reg); reg 112 drivers/net/usb/sr9700.c phy, reg, *value, ret); reg 119 drivers/net/usb/sr9700.c static int sr_share_write_word(struct usbnet *dev, int phy, u8 reg, reg 130 drivers/net/usb/sr9700.c sr_write_reg(dev, SR_EPAR, phy ? (reg | EPAR_PHY_ADR) : reg); reg 63 drivers/net/vmxnet3/vmxnet3_defs.h #define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF)) reg 394 drivers/net/vmxnet3/vmxnet3_int.h #define VMXNET3_WRITE_BAR0_REG(adapter, reg, val) \ reg 395 drivers/net/vmxnet3/vmxnet3_int.h writel((val), (adapter)->hw_addr0 + (reg)) reg 396 drivers/net/vmxnet3/vmxnet3_int.h #define VMXNET3_READ_BAR0_REG(adapter, reg) \ reg 397 drivers/net/vmxnet3/vmxnet3_int.h readl((adapter)->hw_addr0 + (reg)) reg 399 drivers/net/vmxnet3/vmxnet3_int.h #define VMXNET3_WRITE_BAR1_REG(adapter, reg, val) \ reg 400 drivers/net/vmxnet3/vmxnet3_int.h writel((val), (adapter)->hw_addr1 + (reg)) reg 401 drivers/net/vmxnet3/vmxnet3_int.h #define VMXNET3_READ_BAR1_REG(adapter, reg) \ reg 402 drivers/net/vmxnet3/vmxnet3_int.h readl((adapter)->hw_addr1 + (reg)) reg 83 drivers/net/wan/c101.c #define sca_in(reg, card) readb((card)->win0base + C101_SCA + (reg)) reg 84 drivers/net/wan/c101.c #define sca_out(value, reg, card) writeb(value, (card)->win0base + C101_SCA + (reg)) reg 85 drivers/net/wan/c101.c #define sca_inw(reg, card) readw((card)->win0base + C101_SCA + (reg)) reg 88 drivers/net/wan/c101.c #define sca_outw(value, reg, card) do { \ reg 89 drivers/net/wan/c101.c writeb(value & 0xFF, (card)->win0base + C101_SCA + (reg)); \ reg 90 drivers/net/wan/c101.c writeb((value >> 8 ) & 0xFF, (card)->win0base + C101_SCA + (reg + 1));\ reg 48 drivers/net/wan/hd64572.c #define sca_in(reg, card) readb(card->scabase + (reg)) reg 49 drivers/net/wan/hd64572.c #define sca_out(value, reg, card) writeb(value, card->scabase + (reg)) reg 50 drivers/net/wan/hd64572.c #define sca_inw(reg, card) readw(card->scabase + (reg)) reg 51 drivers/net/wan/hd64572.c #define sca_outw(value, reg, card) writew(value, card->scabase + (reg)) reg 52 drivers/net/wan/hd64572.c #define sca_inl(reg, card) readl(card->scabase + (reg)) reg 53 drivers/net/wan/hd64572.c #define sca_outl(value, reg, card) writel(value, card->scabase + (reg)) reg 46 drivers/net/wan/hd64572.h #define M_REG(reg, chan) (reg + 0x80*chan) /* MSCI */ reg 47 drivers/net/wan/hd64572.h #define DRX_REG(reg, chan) (reg + 0x40*chan) /* DMA Rx */ reg 48 drivers/net/wan/hd64572.h #define DTX_REG(reg, chan) (reg + 0x20*(2*chan + 1)) /* DMA Tx */ reg 49 drivers/net/wan/hd64572.h #define TRX_REG(reg, chan) (reg + 0x20*chan) /* Timer Rx */ reg 50 drivers/net/wan/hd64572.h #define TTX_REG(reg, chan) (reg + 0x10*(2*chan + 1)) /* Timer Tx */ reg 51 drivers/net/wan/hd64572.h #define ST_REG(reg, chan) (reg + 0x80*chan) /* Status Cnt */ reg 1186 drivers/net/wan/ixp4xx_hss.c u32 *best, u32 *best_diff, u32 *reg) reg 1199 drivers/net/wan/ixp4xx_hss.c *reg = (a << 22) | (b << 12) | c; reg 1204 drivers/net/wan/ixp4xx_hss.c static void find_best_clock(u32 rate, u32 *best, u32 *reg) reg 1211 drivers/net/wan/ixp4xx_hss.c check_clock(rate, 0x3FF, 1, 1, best, &diff, reg); reg 1220 drivers/net/wan/ixp4xx_hss.c check_clock(rate, a - 1, 1, 1, best, &diff, reg); reg 1230 drivers/net/wan/ixp4xx_hss.c !check_clock(rate, a - 1, 1, 1, best, &diff, reg)) reg 1232 drivers/net/wan/ixp4xx_hss.c check_clock(rate, a, b, 0xFFF, best, &diff, reg); reg 1235 drivers/net/wan/ixp4xx_hss.c if (!check_clock(rate, a, b, c, best, &diff, reg)) reg 1237 drivers/net/wan/ixp4xx_hss.c if (!check_clock(rate, a, b, c + 1, best, &diff, reg)) reg 44 drivers/net/wan/lmc/lmc_var.h #define LMC_CSR_WRITE(sc, reg, val) \ reg 45 drivers/net/wan/lmc/lmc_var.h outl((val), (sc)->lmc_csrs.reg) reg 132 drivers/net/wan/n2.c #define sca_reg(reg, card) (0x8000 | (card)->io | \ reg 133 drivers/net/wan/n2.c ((reg) & 0x0F) | (((reg) & 0xF0) << 6)) reg 134 drivers/net/wan/n2.c #define sca_in(reg, card) inb(sca_reg(reg, card)) reg 135 drivers/net/wan/n2.c #define sca_out(value, reg, card) outb(value, sca_reg(reg, card)) reg 136 drivers/net/wan/n2.c #define sca_inw(reg, card) inw(sca_reg(reg, card)) reg 137 drivers/net/wan/n2.c #define sca_outw(value, reg, card) outw(value, sca_reg(reg, card)) reg 123 drivers/net/wan/z85230.c static inline u8 read_zsreg(struct z8530_channel *c, u8 reg) reg 125 drivers/net/wan/z85230.c if(reg) reg 126 drivers/net/wan/z85230.c z8530_write_port(c->ctrlio, reg); reg 157 drivers/net/wan/z85230.c static inline void write_zsreg(struct z8530_channel *c, u8 reg, u8 val) reg 159 drivers/net/wan/z85230.c if(reg) reg 160 drivers/net/wan/z85230.c z8530_write_port(c->ctrlio, reg); reg 1386 drivers/net/wan/z85230.c int reg=*rtable++; reg 1387 drivers/net/wan/z85230.c if(reg>0x0F) reg 1389 drivers/net/wan/z85230.c write_zsreg(c, reg&0x0F, *rtable); reg 1390 drivers/net/wan/z85230.c if(reg>0x0F) reg 1392 drivers/net/wan/z85230.c c->regs[reg]=*rtable++; reg 78 drivers/net/wireless/admtek/adm8211.c u32 reg = ADM8211_CSR_READ(SPR); reg 80 drivers/net/wireless/admtek/adm8211.c eeprom->reg_data_in = reg & ADM8211_SPR_SDI; reg 81 drivers/net/wireless/admtek/adm8211.c eeprom->reg_data_out = reg & ADM8211_SPR_SDO; reg 82 drivers/net/wireless/admtek/adm8211.c eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK; reg 83 drivers/net/wireless/admtek/adm8211.c eeprom->reg_chip_select = reg & ADM8211_SPR_SCS; reg 89 drivers/net/wireless/admtek/adm8211.c u32 reg = 0x4000 | ADM8211_SPR_SRS; reg 92 drivers/net/wireless/admtek/adm8211.c reg |= ADM8211_SPR_SDI; reg 94 drivers/net/wireless/admtek/adm8211.c reg |= ADM8211_SPR_SDO; reg 96 drivers/net/wireless/admtek/adm8211.c reg |= ADM8211_SPR_SCLK; reg 98 drivers/net/wireless/admtek/adm8211.c reg |= ADM8211_SPR_SCS; reg 100 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(SPR, reg); reg 262 drivers/net/wireless/admtek/adm8211.c u32 reg = ADM8211_CSR_READ(WEPCTL); reg 278 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(WEPCTL, reg); reg 284 drivers/net/wireless/admtek/adm8211.c u32 reg = ADM8211_CSR_READ(WEPCTL); reg 290 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(WEPCTL, reg); reg 510 drivers/net/wireless/admtek/adm8211.c u32 reg, bitbuf; \ reg 528 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_SYNRF_WRITE_SYNDATA_1; \ reg 530 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_SYNRF_WRITE_SYNDATA_0; \ reg 532 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(SYNRF, reg); \ reg 535 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \ reg 537 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \ reg 542 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0); \ reg 546 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1); \ reg 565 drivers/net/wireless/admtek/adm8211.c u32 reg; reg 569 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(BBPCTL); reg 570 drivers/net/wireless/admtek/adm8211.c if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD))) reg 579 drivers/net/wireless/admtek/adm8211.c addr, data, reg); reg 585 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_BBPCTL_MMISEL; /* three wire interface */ reg 588 drivers/net/wireless/admtek/adm8211.c reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP | reg 592 drivers/net/wireless/admtek/adm8211.c reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP | reg 596 drivers/net/wireless/admtek/adm8211.c reg |= ADM8211_BBPCTL_WR | (addr << 8) | data; reg 598 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(BBPCTL, reg); reg 602 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(BBPCTL); reg 603 drivers/net/wireless/admtek/adm8211.c if (!(reg & ADM8211_BBPCTL_WR)) reg 614 drivers/net/wireless/admtek/adm8211.c addr, data, reg); reg 639 drivers/net/wireless/admtek/adm8211.c u32 reg; reg 693 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(GPIO); reg 694 drivers/net/wireless/admtek/adm8211.c reg &= 0xfffc0000; reg 695 drivers/net/wireless/admtek/adm8211.c reg |= ADM8211_CSR_GPIO_EN0; reg 697 drivers/net/wireless/admtek/adm8211.c reg |= ADM8211_CSR_GPIO_O0; reg 698 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(GPIO, reg); reg 705 drivers/net/wireless/admtek/adm8211.c reg = le16_to_cpu(priv->eeprom->cr49); reg 706 drivers/net/wireless/admtek/adm8211.c reg >>= 13; reg 707 drivers/net/wireless/admtek/adm8211.c reg <<= 15; reg 708 drivers/net/wireless/admtek/adm8211.c reg |= ant_power << 9; reg 709 drivers/net/wireless/admtek/adm8211.c adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg); reg 714 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(PLCPHD); reg 715 drivers/net/wireless/admtek/adm8211.c reg &= 0xff00ffff; reg 716 drivers/net/wireless/admtek/adm8211.c reg |= tx_power << 18; reg 717 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(PLCPHD, reg); reg 745 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(CAP0); reg 746 drivers/net/wireless/admtek/adm8211.c reg &= ~0xF; reg 747 drivers/net/wireless/admtek/adm8211.c reg |= chan; reg 748 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(CAP0, reg); reg 843 drivers/net/wireless/admtek/adm8211.c u32 reg; reg 864 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(BBPCTL); reg 865 drivers/net/wireless/admtek/adm8211.c reg &= ~ADM8211_BBPCTL_TYPE; reg 866 drivers/net/wireless/admtek/adm8211.c reg |= 0x5 << 18; reg 867 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(BBPCTL, reg); reg 883 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(MMIRD1); reg 884 drivers/net/wireless/admtek/adm8211.c reg &= 0x0000FFFF; reg 885 drivers/net/wireless/admtek/adm8211.c reg |= 0x7e100000; reg 886 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(MMIRD1, reg); reg 1044 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(SYNCTL); reg 1045 drivers/net/wireless/admtek/adm8211.c reg |= ADM8211_SYNCTL_SELCAL; reg 1046 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(SYNCTL, reg); reg 1055 drivers/net/wireless/admtek/adm8211.c u32 reg; reg 1076 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */ reg 1077 drivers/net/wireless/admtek/adm8211.c reg |= 1 << 15; /* short preamble */ reg 1078 drivers/net/wireless/admtek/adm8211.c reg |= 110 << 24; reg 1079 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(PLCPHD, reg); reg 1092 drivers/net/wireless/admtek/adm8211.c u32 reg; reg 1095 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(PAR); reg 1096 drivers/net/wireless/admtek/adm8211.c reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME; reg 1097 drivers/net/wireless/admtek/adm8211.c reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL); reg 1100 drivers/net/wireless/admtek/adm8211.c reg |= 0x1 << 24; reg 1105 drivers/net/wireless/admtek/adm8211.c reg |= (0x1 << 14); reg 1108 drivers/net/wireless/admtek/adm8211.c reg |= (0x2 << 14); reg 1111 drivers/net/wireless/admtek/adm8211.c reg |= (0x3 << 14); reg 1114 drivers/net/wireless/admtek/adm8211.c reg |= (0x0 << 14); reg 1119 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(PAR, reg); reg 1121 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(CSR_TEST1); reg 1122 drivers/net/wireless/admtek/adm8211.c reg &= ~(0xF << 28); reg 1123 drivers/net/wireless/admtek/adm8211.c reg |= (1 << 28) | (1 << 31); reg 1124 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(CSR_TEST1, reg); reg 1127 drivers/net/wireless/admtek/adm8211.c reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE; reg 1128 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(WCSR, reg); reg 1132 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(CMDR); reg 1133 drivers/net/wireless/admtek/adm8211.c reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT); reg 1134 drivers/net/wireless/admtek/adm8211.c reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF; reg 1135 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(CMDR, reg); reg 1166 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(CFPP); reg 1167 drivers/net/wireless/admtek/adm8211.c reg &= ~(0xffff << 8); reg 1168 drivers/net/wireless/admtek/adm8211.c reg |= 0x0010 << 8; reg 1169 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(CFPP, reg); reg 1201 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(MACTEST); reg 1202 drivers/net/wireless/admtek/adm8211.c reg &= ~(7 << 20); reg 1203 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(MACTEST, reg); reg 1205 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(WEPCTL); reg 1206 drivers/net/wireless/admtek/adm8211.c reg &= ~ADM8211_WEPCTL_WEPENABLE; reg 1207 drivers/net/wireless/admtek/adm8211.c reg |= ADM8211_WEPCTL_WEPRXBYP; reg 1208 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(WEPCTL, reg); reg 1217 drivers/net/wireless/admtek/adm8211.c u32 reg, tmp; reg 1239 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(CSR_TEST1); reg 1240 drivers/net/wireless/admtek/adm8211.c reg |= (1 << 4) | (1 << 5); reg 1241 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(CSR_TEST1, reg); reg 1243 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(CSR_TEST1); reg 1244 drivers/net/wireless/admtek/adm8211.c reg &= ~((1 << 4) | (1 << 5)); reg 1245 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(CSR_TEST1, reg); reg 1250 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(CSR_TEST0); reg 1251 drivers/net/wireless/admtek/adm8211.c reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */ reg 1252 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(CSR_TEST0, reg); reg 1278 drivers/net/wireless/admtek/adm8211.c u32 reg; reg 1282 drivers/net/wireless/admtek/adm8211.c reg = (bi << 16) | li; reg 1283 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(BPLI, reg); reg 1289 drivers/net/wireless/admtek/adm8211.c u32 reg; reg 1292 drivers/net/wireless/admtek/adm8211.c reg = ADM8211_CSR_READ(ABDA1); reg 1293 drivers/net/wireless/admtek/adm8211.c reg &= 0x0000ffff; reg 1294 drivers/net/wireless/admtek/adm8211.c reg |= (bssid[4] << 16) | (bssid[5] << 24); reg 1295 drivers/net/wireless/admtek/adm8211.c ADM8211_CSR_WRITE(ABDA1, reg); reg 1787 drivers/net/wireless/admtek/adm8211.c u32 reg; reg 1809 drivers/net/wireless/admtek/adm8211.c pci_read_config_dword(pdev, 0x80 /* CR32 */, ®); reg 1810 drivers/net/wireless/admtek/adm8211.c if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) { reg 1812 drivers/net/wireless/admtek/adm8211.c pci_name(pdev), reg); reg 301 drivers/net/wireless/ath/ar5523/ar5523.c static int ar5523_config(struct ar5523 *ar, u32 reg, u32 val) reg 306 drivers/net/wireless/ath/ar5523/ar5523.c write.reg = cpu_to_be32(reg); reg 313 drivers/net/wireless/ath/ar5523/ar5523.c ar5523_err(ar, "could not write register 0x%02x\n", reg); reg 317 drivers/net/wireless/ath/ar5523/ar5523.c static int ar5523_config_multi(struct ar5523 *ar, u32 reg, const void *data, reg 323 drivers/net/wireless/ath/ar5523/ar5523.c write.reg = cpu_to_be32(reg); reg 332 drivers/net/wireless/ath/ar5523/ar5523.c len, reg); reg 183 drivers/net/wireless/ath/ar5523/ar5523_hw.h __be32 reg; reg 2983 drivers/net/wireless/ath/ath10k/pci.c u32 reg; reg 2987 drivers/net/wireless/ath/ath10k/pci.c reg = QCA9887_EEPROM_SELECT_READ | reg 2990 drivers/net/wireless/ath/ath10k/pci.c ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg); reg 3002 drivers/net/wireless/ath/ath10k/pci.c reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET); reg 3003 drivers/net/wireless/ath/ath10k/pci.c if (MS(reg, SI_CS_DONE_INT)) reg 3010 drivers/net/wireless/ath/ath10k/pci.c if (!MS(reg, SI_CS_DONE_INT)) { reg 3017 drivers/net/wireless/ath/ath10k/pci.c ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg); reg 3019 drivers/net/wireless/ath/ath10k/pci.c if (MS(reg, SI_CS_DONE_ERR)) { reg 3025 drivers/net/wireless/ath/ath10k/pci.c reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET); reg 3026 drivers/net/wireless/ath/ath10k/pci.c *out = reg; reg 1352 drivers/net/wireless/ath/ath10k/snoc.c struct regulator *reg; reg 1355 drivers/net/wireless/ath/ath10k/snoc.c reg = devm_regulator_get_optional(dev, vreg_info->name); reg 1357 drivers/net/wireless/ath/ath10k/snoc.c if (IS_ERR(reg)) { reg 1358 drivers/net/wireless/ath/ath10k/snoc.c ret = PTR_ERR(reg); reg 1376 drivers/net/wireless/ath/ath10k/snoc.c vreg_info->reg = reg; reg 1423 drivers/net/wireless/ath/ath10k/snoc.c ret = regulator_set_voltage(vreg_info->reg, vreg_info->min_v, reg 1433 drivers/net/wireless/ath/ath10k/snoc.c ret = regulator_set_load(vreg_info->reg, vreg_info->load_ua); reg 1441 drivers/net/wireless/ath/ath10k/snoc.c ret = regulator_enable(vreg_info->reg); reg 1454 drivers/net/wireless/ath/ath10k/snoc.c regulator_set_load(vreg_info->reg, 0); reg 1456 drivers/net/wireless/ath/ath10k/snoc.c regulator_set_voltage(vreg_info->reg, 0, vreg_info->max_v); reg 1469 drivers/net/wireless/ath/ath10k/snoc.c ret = regulator_disable(vreg_info->reg); reg 1474 drivers/net/wireless/ath/ath10k/snoc.c ret = regulator_set_load(vreg_info->reg, 0); reg 1478 drivers/net/wireless/ath/ath10k/snoc.c ret = regulator_set_voltage(vreg_info->reg, 0, vreg_info->max_v); reg 1495 drivers/net/wireless/ath/ath10k/snoc.c if (!vreg_info->reg) reg 1509 drivers/net/wireless/ath/ath10k/snoc.c if (!vreg_info->reg) reg 1528 drivers/net/wireless/ath/ath10k/snoc.c if (!vreg_info->reg) reg 46 drivers/net/wireless/ath/ath10k/snoc.h struct regulator *reg; reg 1118 drivers/net/wireless/ath/ath10k/wmi-tlv.c const struct hal_reg_capabilities *reg; reg 1136 drivers/net/wireless/ath/ath10k/wmi-tlv.c svc_rdy->reg = ptr; reg 1159 drivers/net/wireless/ath/ath10k/wmi-tlv.c const struct hal_reg_capabilities *reg; reg 1174 drivers/net/wireless/ath/ath10k/wmi-tlv.c reg = svc_rdy.reg; reg 1178 drivers/net/wireless/ath/ath10k/wmi-tlv.c if (!ev || !reg || !svc_bmap || !mem_reqs) reg 1209 drivers/net/wireless/ath/ath10k/wmi-tlv.c arg->eeprom_rd = reg->eeprom_rd; reg 1210 drivers/net/wireless/ath/ath10k/wmi-tlv.c arg->low_5ghz_chan = reg->low_5ghz_chan; reg 1211 drivers/net/wireless/ath/ath10k/wmi-tlv.c arg->high_5ghz_chan = reg->high_5ghz_chan; reg 94 drivers/net/wireless/ath/ath5k/ahb.c u32 reg; reg 141 drivers/net/wireless/ath/ath5k/ahb.c reg = ioread32((void __iomem *) AR5K_AR2315_AHB_ARB_CTL); reg 142 drivers/net/wireless/ath/ath5k/ahb.c reg |= AR5K_AR2315_AHB_ARB_CTL_WLAN; reg 143 drivers/net/wireless/ath/ath5k/ahb.c iowrite32(reg, (void __iomem *) AR5K_AR2315_AHB_ARB_CTL); reg 146 drivers/net/wireless/ath/ath5k/ahb.c reg = ioread32((void __iomem *) AR5K_AR2315_BYTESWAP); reg 147 drivers/net/wireless/ath/ath5k/ahb.c reg |= AR5K_AR2315_BYTESWAP_WMAC; reg 148 drivers/net/wireless/ath/ath5k/ahb.c iowrite32(reg, (void __iomem *) AR5K_AR2315_BYTESWAP); reg 152 drivers/net/wireless/ath/ath5k/ahb.c reg = ioread32((void __iomem *) AR5K_AR5312_ENABLE); reg 154 drivers/net/wireless/ath/ath5k/ahb.c reg |= AR5K_AR5312_ENABLE_WLAN0; reg 156 drivers/net/wireless/ath/ath5k/ahb.c reg |= AR5K_AR5312_ENABLE_WLAN1; reg 157 drivers/net/wireless/ath/ath5k/ahb.c iowrite32(reg, (void __iomem *) AR5K_AR5312_ENABLE); reg 196 drivers/net/wireless/ath/ath5k/ahb.c u32 reg; reg 205 drivers/net/wireless/ath/ath5k/ahb.c reg = ioread32((void __iomem *) AR5K_AR2315_AHB_ARB_CTL); reg 206 drivers/net/wireless/ath/ath5k/ahb.c reg &= ~AR5K_AR2315_AHB_ARB_CTL_WLAN; reg 207 drivers/net/wireless/ath/ath5k/ahb.c iowrite32(reg, (void __iomem *) AR5K_AR2315_AHB_ARB_CTL); reg 210 drivers/net/wireless/ath/ath5k/ahb.c reg = ioread32((void __iomem *) AR5K_AR5312_ENABLE); reg 212 drivers/net/wireless/ath/ath5k/ahb.c reg &= ~AR5K_AR5312_ENABLE_WLAN0; reg 214 drivers/net/wireless/ath/ath5k/ahb.c reg &= ~AR5K_AR5312_ENABLE_WLAN1; reg 215 drivers/net/wireless/ath/ath5k/ahb.c iowrite32(reg, (void __iomem *) AR5K_AR5312_ENABLE); reg 1497 drivers/net/wireless/ath/ath5k/ath5k.h int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, reg 1655 drivers/net/wireless/ath/ath5k/ath5k.h static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg) reg 1659 drivers/net/wireless/ath/ath5k/ath5k.h if (unlikely((reg >= 0x4000) && (reg < 0x5000) && reg 1661 drivers/net/wireless/ath/ath5k/ath5k.h return AR5K_AR2315_PCI_BASE + reg; reg 1663 drivers/net/wireless/ath/ath5k/ath5k.h return ah->iobase + reg; reg 1666 drivers/net/wireless/ath/ath5k/ath5k.h static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) reg 1668 drivers/net/wireless/ath/ath5k/ath5k.h return ioread32(ath5k_ahb_reg(ah, reg)); reg 1671 drivers/net/wireless/ath/ath5k/ath5k.h static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) reg 1673 drivers/net/wireless/ath/ath5k/ath5k.h iowrite32(val, ath5k_ahb_reg(ah, reg)); reg 1678 drivers/net/wireless/ath/ath5k/ath5k.h static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) reg 1680 drivers/net/wireless/ath/ath5k/ath5k.h return ioread32(ah->iobase + reg); reg 1683 drivers/net/wireless/ath/ath5k/ath5k.h static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) reg 1685 drivers/net/wireless/ath/ath5k/ath5k.h iowrite32(val, ah->iobase + reg); reg 88 drivers/net/wireless/ath/ath5k/debug.c static const struct reg regs[] = { reg 158 drivers/net/wireless/ath/ath5k/debug.c struct reg *r = p; reg 286 drivers/net/wireless/ath/ath5k/pcu.c u32 reg; reg 299 drivers/net/wireless/ath/ath5k/pcu.c reg = AR5K_RATE_DUR(rate->hw_value); reg 310 drivers/net/wireless/ath/ath5k/pcu.c ath5k_hw_reg_write(ah, tx_time, reg); reg 317 drivers/net/wireless/ath/ath5k/pcu.c reg + (AR5K_SET_SHORT_PREAMBLE << 2)); reg 3207 drivers/net/wireless/ath/ath5k/phy.c u32 reg; reg 3213 drivers/net/wireless/ath/ath5k/phy.c reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); reg 3214 drivers/net/wireless/ath/ath5k/phy.c reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | reg 3227 drivers/net/wireless/ath/ath5k/phy.c reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); reg 3231 drivers/net/wireless/ath/ath5k/phy.c reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); reg 3234 drivers/net/wireless/ath/ath5k/phy.c reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); reg 3237 drivers/net/wireless/ath/ath5k/phy.c reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); reg 3240 drivers/net/wireless/ath/ath5k/phy.c ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); reg 67 drivers/net/wireless/ath/ath5k/reset.c ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, reg 74 drivers/net/wireless/ath/ath5k/reset.c data = ath5k_hw_reg_read(ah, reg); reg 449 drivers/net/wireless/ath/ath5k/reset.c u32 __iomem *reg; reg 455 drivers/net/wireless/ath/ath5k/reset.c reg = (u32 __iomem *) AR5K_AR2315_RESET; reg 461 drivers/net/wireless/ath/ath5k/reset.c reg = (u32 __iomem *) AR5K_AR5312_RESET; reg 478 drivers/net/wireless/ath/ath5k/reset.c regval = ioread32(reg); reg 479 drivers/net/wireless/ath/ath5k/reset.c iowrite32(regval | val, reg); reg 480 drivers/net/wireless/ath/ath5k/reset.c regval = ioread32(reg); reg 484 drivers/net/wireless/ath/ath5k/reset.c iowrite32(regval & ~val, reg); reg 485 drivers/net/wireless/ath/ath5k/reset.c regval = ioread32(reg); reg 3254 drivers/net/wireless/ath/ath6kl/cfg80211.c u16 frame_type, bool reg) reg 3259 drivers/net/wireless/ath/ath6kl/cfg80211.c __func__, frame_type, reg); reg 3266 drivers/net/wireless/ath/ath6kl/cfg80211.c vif->probe_req_report = reg; reg 734 drivers/net/wireless/ath/ath9k/ar5008_phy.c u32 reg = INI_RA(&ah->iniModes, i, 0); reg 737 drivers/net/wireless/ath/ath9k/ar5008_phy.c if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup) reg 740 drivers/net/wireless/ath/ath9k/ar5008_phy.c REG_WRITE(ah, reg, val); reg 742 drivers/net/wireless/ath/ath9k/ar5008_phy.c if (reg >= 0x7800 && reg < 0x78a0 reg 769 drivers/net/wireless/ath/ath9k/ar5008_phy.c u32 reg = INI_RA(&ah->iniCommon, i, 0); reg 772 drivers/net/wireless/ath/ath9k/ar5008_phy.c REG_WRITE(ah, reg, val); reg 774 drivers/net/wireless/ath/ath9k/ar5008_phy.c if (reg >= 0x7800 && reg < 0x78a0 reg 439 drivers/net/wireless/ath/ath9k/ar9002_hw.c u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0); reg 443 drivers/net/wireless/ath/ath9k/ar9002_hw.c if (reg == AR_PHY_CCK_DETECT) { reg 444 drivers/net/wireless/ath/ath9k/ar9002_hw.c val_orig = REG_READ(ah, reg); reg 448 drivers/net/wireless/ath/ath9k/ar9002_hw.c REG_WRITE(ah, reg, val|val_orig); reg 450 drivers/net/wireless/ath/ath9k/ar9002_hw.c REG_WRITE(ah, reg, val); reg 3800 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c unsigned long reg; reg 3806 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1); reg 3807 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg &= ~0x00ffffc0; reg 3808 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg |= 0x5 << 21; reg 3809 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg |= 0x5 << 18; reg 3810 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg |= 0x5 << 15; reg 3811 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg |= 0x5 << 12; reg 3812 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg |= 0x5 << 9; reg 3813 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg |= 0x5 << 6; reg 3814 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg); reg 3816 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2); reg 3817 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg &= ~0xffffffe0; reg 3818 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg |= 0x5 << 29; reg 3819 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg |= 0x5 << 26; reg 3820 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg |= 0x5 << 23; reg 3821 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg |= 0x5 << 20; reg 3822 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg |= 0x5 << 17; reg 3823 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg |= 0x5 << 14; reg 3824 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg |= 0x5 << 11; reg 3825 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg |= 0x5 << 8; reg 3826 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg |= 0x5 << 5; reg 3827 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg); reg 3829 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4); reg 3830 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg &= ~0xff800000; reg 3831 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg |= 0x5 << 29; reg 3832 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg |= 0x5 << 26; reg 3833 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c reg |= 0x5 << 23; reg 3834 drivers/net/wireless/ath/ath9k/ar9003_eeprom.c REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg); reg 295 drivers/net/wireless/ath/ath9k/ar9003_paprd.c u32 reg = AR_PHY_TXGAIN_TABLE; reg 299 drivers/net/wireless/ath/ath9k/ar9003_paprd.c entry[i] = REG_READ(ah, reg); reg 301 drivers/net/wireless/ath/ath9k/ar9003_paprd.c reg += 4; reg 758 drivers/net/wireless/ath/ath9k/ar9003_paprd.c u32 reg = 0; reg 762 drivers/net/wireless/ath/ath9k/ar9003_paprd.c reg = AR_PHY_PAPRD_MEM_TAB_B0; reg 764 drivers/net/wireless/ath/ath9k/ar9003_paprd.c reg = AR_PHY_PAPRD_MEM_TAB_B1; reg 766 drivers/net/wireless/ath/ath9k/ar9003_paprd.c reg = AR_PHY_PAPRD_MEM_TAB_B2; reg 769 drivers/net/wireless/ath/ath9k/ar9003_paprd.c REG_WRITE(ah, reg, paprd_table_val[i]); reg 770 drivers/net/wireless/ath/ath9k/ar9003_paprd.c reg = reg + 4; reg 774 drivers/net/wireless/ath/ath9k/ar9003_paprd.c reg = AR_PHY_PA_GAIN123_B0; reg 776 drivers/net/wireless/ath/ath9k/ar9003_paprd.c reg = AR_PHY_PA_GAIN123_B1; reg 778 drivers/net/wireless/ath/ath9k/ar9003_paprd.c reg = AR_PHY_PA_GAIN123_B2; reg 780 drivers/net/wireless/ath/ath9k/ar9003_paprd.c REG_RMW_FIELD(ah, reg, AR_PHY_PA_GAIN123_PA_GAIN1, small_signal_gain); reg 924 drivers/net/wireless/ath/ath9k/ar9003_paprd.c u32 reg; reg 938 drivers/net/wireless/ath/ath9k/ar9003_paprd.c reg = AR_PHY_CHAN_INFO_TAB_0; reg 940 drivers/net/wireless/ath/ath9k/ar9003_paprd.c data_L[i] = REG_READ(ah, reg + (i << 2)); reg 946 drivers/net/wireless/ath/ath9k/ar9003_paprd.c data_U[i] = REG_READ(ah, reg + (i << 2)); reg 769 drivers/net/wireless/ath/ath9k/ar9003_phy.c u32 reg = INI_RA(iniArr, i, 0); reg 772 drivers/net/wireless/ath/ath9k/ar9003_phy.c REG_WRITE(ah, reg, val); reg 38 drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c u16 reg; reg 73 drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c (const void *)data <= cal_end && data->reg != (u16)~0; reg 76 drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c u16 reg; reg 78 drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c reg = data->reg; reg 83 drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c reg = swab16(reg); reg 87 drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c iowrite32(val, mem + reg); reg 370 drivers/net/wireless/ath/ath9k/common.c struct ath_regulatory *reg = ath9k_hw_regulatory(ah); reg 372 drivers/net/wireless/ath/ath9k/common.c if (ah->curchan && reg->power_limit != new_txpow) reg 376 drivers/net/wireless/ath/ath9k/common.c *txpower = reg->max_power_level; reg 665 drivers/net/wireless/ath/ath9k/debug.c unsigned int reg; reg 710 drivers/net/wireless/ath/ath9k/debug.c reg = sc->sc_ah->imask; reg 712 drivers/net/wireless/ath/ath9k/debug.c seq_printf(file, "INTERRUPT-MASK: 0x%x", reg); reg 714 drivers/net/wireless/ath/ath9k/debug.c if (reg & ATH9K_INT_SWBA) reg 716 drivers/net/wireless/ath/ath9k/debug.c if (reg & ATH9K_INT_BMISS) reg 718 drivers/net/wireless/ath/ath9k/debug.c if (reg & ATH9K_INT_CST) reg 720 drivers/net/wireless/ath/ath9k/debug.c if (reg & ATH9K_INT_RX) reg 722 drivers/net/wireless/ath/ath9k/debug.c if (reg & ATH9K_INT_RXHP) reg 724 drivers/net/wireless/ath/ath9k/debug.c if (reg & ATH9K_INT_RXLP) reg 726 drivers/net/wireless/ath/ath9k/debug.c if (reg & ATH9K_INT_BB_WATCHDOG) reg 20 drivers/net/wireless/ath/ath9k/eeprom.c void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val) reg 22 drivers/net/wireless/ath/ath9k/eeprom.c REG_WRITE(ah, reg, val); reg 28 drivers/net/wireless/ath/ath9k/eeprom.c void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, reg 31 drivers/net/wireless/ath/ath9k/eeprom.c REG_RMW(ah, reg, ((val << shift) & mask), mask); reg 671 drivers/net/wireless/ath/ath9k/eeprom.h void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val); reg 672 drivers/net/wireless/ath/ath9k/eeprom.h void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, reg 239 drivers/net/wireless/ath/ath9k/htc_drv_init.c __be32 val, reg = cpu_to_be32(reg_offset); reg 243 drivers/net/wireless/ath/ath9k/htc_drv_init.c (u8 *) ®, sizeof(reg), reg 332 drivers/net/wireless/ath/ath9k/htc_drv_init.c priv->wmi->multi_write[priv->wmi->multi_write_idx].reg = reg 395 drivers/net/wireless/ath/ath9k/htc_drv_init.c priv->wmi->multi_rmw[priv->wmi->multi_rmw_idx].reg = reg 475 drivers/net/wireless/ath/ath9k/htc_drv_init.c buf.reg = cpu_to_be32(reg_offset); reg 835 drivers/net/wireless/ath/ath9k/htc_drv_init.c struct ath_regulatory *reg; reg 857 drivers/net/wireless/ath/ath9k/htc_drv_init.c reg = &common->regulatory; reg 883 drivers/net/wireless/ath/ath9k/htc_drv_init.c if (!ath_is_world_regd(reg)) { reg 884 drivers/net/wireless/ath/ath9k/htc_drv_init.c error = regulatory_hint(hw->wiphy, reg->alpha2); reg 77 drivers/net/wireless/ath/ath9k/hw.c bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) reg 84 drivers/net/wireless/ath/ath9k/hw.c if ((REG_READ(ah, reg) & mask) == val) reg 92 drivers/net/wireless/ath/ath9k/hw.c timeout, reg, REG_READ(ah, reg), mask, val); reg 1056 drivers/net/wireless/ath/ath9k/hw.c u32 reg; reg 1103 drivers/net/wireless/ath/ath9k/hw.c reg = AR_USEC_ASYNC_FIFO; reg 1107 drivers/net/wireless/ath/ath9k/hw.c reg = REG_READ(ah, AR_USEC); reg 1109 drivers/net/wireless/ath/ath9k/hw.c rx_lat = MS(reg, AR_USEC_RX_LAT); reg 1110 drivers/net/wireless/ath/ath9k/hw.c tx_lat = MS(reg, AR_USEC_TX_LAT); reg 1177 drivers/net/wireless/ath/ath9k/hw.c u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) reg 1179 drivers/net/wireless/ath/ath9k/hw.c u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); reg 1645 drivers/net/wireless/ath/ath9k/hw.c u32 reg, last_val; reg 1659 drivers/net/wireless/ath/ath9k/hw.c reg = REG_READ(ah, AR_OBS_BUS_1); reg 1660 drivers/net/wireless/ath/ath9k/hw.c if (reg != last_val) reg 1664 drivers/net/wireless/ath/ath9k/hw.c last_val = reg; reg 1665 drivers/net/wireless/ath/ath9k/hw.c if ((reg & 0x7E7FFFEF) == 0x00702400) reg 1668 drivers/net/wireless/ath/ath9k/hw.c switch (reg & 0x7E000B00) { reg 2957 drivers/net/wireless/ath/ath9k/hw.c struct ath_regulatory *reg = ath9k_hw_regulatory(ah); reg 2966 drivers/net/wireless/ath/ath9k/hw.c ctl = ath9k_regd_get_ctl(reg, chan); reg 2970 drivers/net/wireless/ath/ath9k/hw.c new_pwr = min_t(int, chan_pwr, reg->power_limit); reg 2978 drivers/net/wireless/ath/ath9k/hw.c struct ath_regulatory *reg = ath9k_hw_regulatory(ah); reg 2982 drivers/net/wireless/ath/ath9k/hw.c reg->power_limit = min_t(u32, limit, MAX_COMBINED_POWER); reg 2989 drivers/net/wireless/ath/ath9k/hw.c channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); reg 1027 drivers/net/wireless/ath/ath9k/hw.h u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); reg 1041 drivers/net/wireless/ath/ath9k/hw.h bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); reg 256 drivers/net/wireless/ath/ath9k/init.c struct ath_regulatory *reg = ath9k_hw_regulatory(ah); reg 258 drivers/net/wireless/ath/ath9k/init.c ath_reg_notifier_apply(wiphy, request, reg); reg 1024 drivers/net/wireless/ath/ath9k/init.c struct ath_regulatory *reg; reg 1041 drivers/net/wireless/ath/ath9k/init.c reg = &common->regulatory; reg 1074 drivers/net/wireless/ath/ath9k/init.c if (!ath_is_world_regd(reg)) { reg 1075 drivers/net/wireless/ath/ath9k/init.c error = regulatory_hint(hw->wiphy, reg->alpha2); reg 641 drivers/net/wireless/ath/ath9k/mac.c u32 reg; reg 653 drivers/net/wireless/ath/ath9k/mac.c reg = REG_READ(ah, AR_OBS_BUS_1); reg 656 drivers/net/wireless/ath/ath9k/mac.c reg); reg 1208 drivers/net/wireless/ath/ath9k/main.c struct ath_regulatory *reg = ath9k_hw_regulatory(ah); reg 1223 drivers/net/wireless/ath/ath9k/main.c sc->cur_chan->cur_txpower = reg->max_power_level; reg 132 drivers/net/wireless/ath/ath9k/wmi.h __be32 reg; reg 137 drivers/net/wireless/ath/ath9k/wmi.h __be32 reg; reg 43 drivers/net/wireless/ath/carl9170/cmd.c int carl9170_write_reg(struct ar9170 *ar, const u32 reg, const u32 val) reg 46 drivers/net/wireless/ath/carl9170/cmd.c cpu_to_le32(reg), reg 56 drivers/net/wireless/ath/carl9170/cmd.c "(val %#x) failed (%d)\n", reg, val, err); reg 94 drivers/net/wireless/ath/carl9170/cmd.c int carl9170_read_reg(struct ar9170 *ar, u32 reg, u32 *val) reg 96 drivers/net/wireless/ath/carl9170/cmd.c return carl9170_read_mreg(ar, 1, ®, val); reg 45 drivers/net/wireless/ath/carl9170/cmd.h int carl9170_write_reg(struct ar9170 *ar, const u32 reg, const u32 val); reg 46 drivers/net/wireless/ath/carl9170/cmd.h int carl9170_read_reg(struct ar9170 *ar, const u32 reg, u32 *val); reg 468 drivers/net/wireless/ath/carl9170/debug.c __tmp[__i] = name##_regs[__i].reg; \ reg 548 drivers/net/wireless/ath/carl9170/debug.c unsigned int reg, tmp; reg 556 drivers/net/wireless/ath/carl9170/debug.c res = sscanf(buf, "0x%X %d", ®, &n); reg 570 drivers/net/wireless/ath/carl9170/debug.c if ((reg >= 0x280000) || ((reg + (n << 2)) >= 0x280000)) { reg 575 drivers/net/wireless/ath/carl9170/debug.c if (reg & 3) { reg 581 drivers/net/wireless/ath/carl9170/debug.c err = carl9170_read_reg(ar, reg + (i << 2), &tmp); reg 585 drivers/net/wireless/ath/carl9170/debug.c ar->debug.ring[ar->debug.ring_tail].reg = reg + (i << 2); reg 602 drivers/net/wireless/ath/carl9170/debug.c ar->debug.ring[ar->debug.ring_head].reg, reg 725 drivers/net/wireless/ath/carl9170/debug.c u32 reg, val; reg 733 drivers/net/wireless/ath/carl9170/debug.c res = sscanf(buf, "0x%X 0x%X", ®, &val); reg 739 drivers/net/wireless/ath/carl9170/debug.c if (reg <= 0x100000 || reg >= 0x280000) { reg 744 drivers/net/wireless/ath/carl9170/debug.c if (reg & 3) { reg 749 drivers/net/wireless/ath/carl9170/debug.c err = carl9170_write_reg(ar, reg, val); reg 49 drivers/net/wireless/ath/carl9170/debug.h u32 reg; reg 53 drivers/net/wireless/ath/carl9170/debug.h #define STAT_MAC_REG(reg) \ reg 54 drivers/net/wireless/ath/carl9170/debug.h { (AR9170_MAC_REG_##reg), #reg } reg 56 drivers/net/wireless/ath/carl9170/debug.h #define STAT_PTA_REG(reg) \ reg 57 drivers/net/wireless/ath/carl9170/debug.h { (AR9170_PTA_REG_##reg), #reg } reg 59 drivers/net/wireless/ath/carl9170/debug.h #define STAT_USB_REG(reg) \ reg 60 drivers/net/wireless/ath/carl9170/debug.h { (AR9170_USB_REG_##reg), #reg } reg 116 drivers/net/wireless/ath/carl9170/debug.h u32 reg; reg 872 drivers/net/wireless/ath/carl9170/hw.h #define SET_VAL(reg, value, newvalue) \ reg 873 drivers/net/wireless/ath/carl9170/hw.h (value = ((value) & ~reg) | (((newvalue) << reg##_S) & reg)) reg 875 drivers/net/wireless/ath/carl9170/hw.h #define SET_CONSTVAL(reg, newvalue) \ reg 876 drivers/net/wireless/ath/carl9170/hw.h (((newvalue) << reg##_S) & reg) reg 878 drivers/net/wireless/ath/carl9170/hw.h #define MOD_VAL(reg, value, newvalue) \ reg 879 drivers/net/wireless/ath/carl9170/hw.h (((value) & ~reg) | (((newvalue) << reg##_S) & reg)) reg 881 drivers/net/wireless/ath/carl9170/hw.h #define GET_VAL(reg, value) \ reg 882 drivers/net/wireless/ath/carl9170/hw.h (((value) & reg) >> reg##_S) reg 258 drivers/net/wireless/ath/carl9170/mac.c const u32 reg, const u8 *mac) reg 267 drivers/net/wireless/ath/carl9170/mac.c carl9170_regwrite(reg, get_unaligned_le32(mac)); reg 268 drivers/net/wireless/ath/carl9170/mac.c carl9170_regwrite(reg + 4, get_unaligned_le16(mac + 4)); reg 64 drivers/net/wireless/ath/carl9170/phy.c u32 reg, _5ghz_20, _5ghz_40, _2ghz_40, _2ghz_20; reg 406 drivers/net/wireless/ath/carl9170/phy.c static u32 carl9170_def_val(u32 reg, bool is_2ghz, bool is_40mhz) reg 410 drivers/net/wireless/ath/carl9170/phy.c if (ar5416_phy_init[i].reg != reg) reg 565 drivers/net/wireless/ath/carl9170/phy.c carl9170_regwrite(ar5416_phy_init[i].reg, val); reg 590 drivers/net/wireless/ath/carl9170/phy.c u32 reg, _5ghz, _2ghz; reg 679 drivers/net/wireless/ath/carl9170/phy.c carl9170_regwrite(carl9170_rf_initval[i].reg, reg 26 drivers/net/wireless/ath/regd.c static int __ath_regd_init(struct ath_regulatory *reg); reg 117 drivers/net/wireless/ath/regd.c static bool dynamic_country_user_possible(struct ath_regulatory *reg) reg 122 drivers/net/wireless/ath/regd.c switch (reg->country_code) { reg 189 drivers/net/wireless/ath/regd.c static bool ath_reg_dyn_country_user_allow(struct ath_regulatory *reg) reg 193 drivers/net/wireless/ath/regd.c if (!dynamic_country_user_possible(reg)) reg 205 drivers/net/wireless/ath/regd.c static u16 ath_regd_get_eepromRD(struct ath_regulatory *reg) reg 207 drivers/net/wireless/ath/regd.c return reg->current_rd & ~WORLDWIDE_ROAMING_FLAG; reg 210 drivers/net/wireless/ath/regd.c bool ath_is_world_regd(struct ath_regulatory *reg) reg 212 drivers/net/wireless/ath/regd.c return is_wwr_sku(ath_regd_get_eepromRD(reg)); reg 223 drivers/net/wireless/ath/regd.c ieee80211_regdomain *ath_world_regdomain(struct ath_regulatory *reg) reg 225 drivers/net/wireless/ath/regd.c switch (reg->regpair->reg_domain) { reg 258 drivers/net/wireless/ath/regd.c struct ath_regulatory *reg) reg 261 drivers/net/wireless/ath/regd.c if (reg->country_code == CTRY_INDIA) reg 309 drivers/net/wireless/ath/regd.c struct ath_regulatory *reg, reg 313 drivers/net/wireless/ath/regd.c if (ath_is_radar_freq(ch->center_freq, reg) || reg 322 drivers/net/wireless/ath/regd.c if (ath_reg_dyn_country_user_allow(reg)) reg 340 drivers/net/wireless/ath/regd.c struct ath_regulatory *reg, reg 354 drivers/net/wireless/ath/regd.c __ath_reg_apply_beaconing_flags(wiphy, reg, reg 376 drivers/net/wireless/ath/regd.c struct ath_regulatory *reg, reg 391 drivers/net/wireless/ath/regd.c if (!ath_reg_dyn_country_user_allow(reg)) reg 404 drivers/net/wireless/ath/regd.c struct ath_regulatory *reg) reg 417 drivers/net/wireless/ath/regd.c if (!ath_is_radar_freq(ch->center_freq, reg)) reg 437 drivers/net/wireless/ath/regd.c struct ath_regulatory *reg) reg 439 drivers/net/wireless/ath/regd.c switch (reg->regpair->reg_domain) { reg 445 drivers/net/wireless/ath/regd.c ath_reg_apply_beaconing_flags(wiphy, reg, initiator); reg 448 drivers/net/wireless/ath/regd.c ath_reg_apply_beaconing_flags(wiphy, reg, initiator); reg 449 drivers/net/wireless/ath/regd.c ath_reg_apply_ir_flags(wiphy, reg, initiator); reg 452 drivers/net/wireless/ath/regd.c if (ath_reg_dyn_country_user_allow(reg)) reg 453 drivers/net/wireless/ath/regd.c ath_reg_apply_beaconing_flags(wiphy, reg, initiator); reg 471 drivers/net/wireless/ath/regd.c struct ath_regulatory *reg, reg 477 drivers/net/wireless/ath/regd.c !ath_is_world_regd(reg)) reg 484 drivers/net/wireless/ath/regd.c reg->current_rd = COUNTRY_ERD_FLAG; reg 485 drivers/net/wireless/ath/regd.c reg->current_rd |= country_code; reg 487 drivers/net/wireless/ath/regd.c __ath_regd_init(reg); reg 489 drivers/net/wireless/ath/regd.c ath_reg_apply_world_flags(wiphy, request->initiator, reg); reg 495 drivers/net/wireless/ath/regd.c struct ath_regulatory *reg, reg 498 drivers/net/wireless/ath/regd.c if (__ath_reg_dyn_country(wiphy, reg, request)) reg 503 drivers/net/wireless/ath/regd.c reg->current_rd, reg 509 drivers/net/wireless/ath/regd.c struct ath_regulatory *reg) reg 511 drivers/net/wireless/ath/regd.c struct ath_common *common = container_of(reg, struct ath_common, reg 514 drivers/net/wireless/ath/regd.c ath_reg_apply_radar_flags(wiphy, reg); reg 524 drivers/net/wireless/ath/regd.c reg->region = request->dfs_region; reg 534 drivers/net/wireless/ath/regd.c memcpy(reg, &common->reg_world_copy, reg 540 drivers/net/wireless/ath/regd.c if (ath_reg_dyn_country_user_allow(reg)) reg 541 drivers/net/wireless/ath/regd.c ath_reg_dyn_country(wiphy, reg, request); reg 544 drivers/net/wireless/ath/regd.c ath_reg_dyn_country(wiphy, reg, request); reg 550 drivers/net/wireless/ath/regd.c static bool ath_regd_is_eeprom_valid(struct ath_regulatory *reg) reg 552 drivers/net/wireless/ath/regd.c u16 rd = ath_regd_get_eepromRD(reg); reg 634 drivers/net/wireless/ath/regd.c ath_regd_init_wiphy(struct ath_regulatory *reg, reg 645 drivers/net/wireless/ath/regd.c if (ath_is_world_regd(reg)) { reg 650 drivers/net/wireless/ath/regd.c regd = ath_world_regdomain(reg); reg 662 drivers/net/wireless/ath/regd.c ath_reg_apply_radar_flags(wiphy, reg); reg 663 drivers/net/wireless/ath/regd.c ath_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, reg); reg 674 drivers/net/wireless/ath/regd.c static void ath_regd_sanitize(struct ath_regulatory *reg) reg 676 drivers/net/wireless/ath/regd.c if (reg->current_rd != COUNTRY_ERD_FLAG) reg 679 drivers/net/wireless/ath/regd.c reg->current_rd = 0x64; reg 682 drivers/net/wireless/ath/regd.c static int __ath_regd_init(struct ath_regulatory *reg) reg 687 drivers/net/wireless/ath/regd.c if (!reg) reg 690 drivers/net/wireless/ath/regd.c ath_regd_sanitize(reg); reg 692 drivers/net/wireless/ath/regd.c printk(KERN_DEBUG "ath: EEPROM regdomain: 0x%0x\n", reg->current_rd); reg 694 drivers/net/wireless/ath/regd.c if (!ath_regd_is_eeprom_valid(reg)) { reg 699 drivers/net/wireless/ath/regd.c regdmn = ath_regd_get_eepromRD(reg); reg 700 drivers/net/wireless/ath/regd.c reg->country_code = ath_regd_get_default_country(regdmn); reg 702 drivers/net/wireless/ath/regd.c if (reg->country_code == CTRY_DEFAULT && reg 706 drivers/net/wireless/ath/regd.c reg->country_code = CTRY_UNITED_STATES; reg 709 drivers/net/wireless/ath/regd.c if (reg->country_code == CTRY_DEFAULT) { reg 714 drivers/net/wireless/ath/regd.c country = ath_regd_find_country(reg->country_code); reg 719 drivers/net/wireless/ath/regd.c reg->country_code); reg 729 drivers/net/wireless/ath/regd.c reg->regpair = ath_get_regpair(regdmn); reg 731 drivers/net/wireless/ath/regd.c if (!reg->regpair) { reg 741 drivers/net/wireless/ath/regd.c reg->alpha2[0] = country->isoName[0]; reg 742 drivers/net/wireless/ath/regd.c reg->alpha2[1] = country->isoName[1]; reg 744 drivers/net/wireless/ath/regd.c reg->alpha2[0] = '0'; reg 745 drivers/net/wireless/ath/regd.c reg->alpha2[1] = '0'; reg 749 drivers/net/wireless/ath/regd.c reg->alpha2[0], reg->alpha2[1]); reg 751 drivers/net/wireless/ath/regd.c reg->regpair->reg_domain); reg 757 drivers/net/wireless/ath/regd.c ath_regd_init(struct ath_regulatory *reg, reg 762 drivers/net/wireless/ath/regd.c struct ath_common *common = container_of(reg, struct ath_common, reg 766 drivers/net/wireless/ath/regd.c r = __ath_regd_init(reg); reg 770 drivers/net/wireless/ath/regd.c if (ath_is_world_regd(reg)) reg 771 drivers/net/wireless/ath/regd.c memcpy(&common->reg_world_copy, reg, reg 774 drivers/net/wireless/ath/regd.c ath_regd_init_wiphy(reg, wiphy, reg_notifier); reg 780 drivers/net/wireless/ath/regd.c u32 ath_regd_get_band_ctl(struct ath_regulatory *reg, reg 783 drivers/net/wireless/ath/regd.c if (!reg->regpair || reg 784 drivers/net/wireless/ath/regd.c (reg->country_code == CTRY_DEFAULT && reg 785 drivers/net/wireless/ath/regd.c is_wwr_sku(ath_regd_get_eepromRD(reg)))) { reg 789 drivers/net/wireless/ath/regd.c if (ath_regd_get_eepromRD(reg) == CTRY_DEFAULT) { reg 790 drivers/net/wireless/ath/regd.c switch (reg->region) { reg 804 drivers/net/wireless/ath/regd.c return reg->regpair->reg_2ghz_ctl; reg 806 drivers/net/wireless/ath/regd.c return reg->regpair->reg_5ghz_ctl; reg 260 drivers/net/wireless/ath/regd.h bool ath_is_world_regd(struct ath_regulatory *reg); reg 263 drivers/net/wireless/ath/regd.h int ath_regd_init(struct ath_regulatory *reg, struct wiphy *wiphy, reg 266 drivers/net/wireless/ath/regd.h u32 ath_regd_get_band_ctl(struct ath_regulatory *reg, reg 270 drivers/net/wireless/ath/regd.h struct ath_regulatory *reg); reg 1133 drivers/net/wireless/ath/wil6210/wil6210.h static inline u32 wil_r(struct wil6210_priv *wil, u32 reg) reg 1135 drivers/net/wireless/ath/wil6210/wil6210.h return readl(wil->csr + HOSTADDR(reg)); reg 1139 drivers/net/wireless/ath/wil6210/wil6210.h static inline void wil_w(struct wil6210_priv *wil, u32 reg, u32 val) reg 1141 drivers/net/wireless/ath/wil6210/wil6210.h writel(val, wil->csr + HOSTADDR(reg)); reg 1146 drivers/net/wireless/ath/wil6210/wil6210.h static inline void wil_s(struct wil6210_priv *wil, u32 reg, u32 val) reg 1148 drivers/net/wireless/ath/wil6210/wil6210.h wil_w(wil, reg, wil_r(wil, reg) | val); reg 1152 drivers/net/wireless/ath/wil6210/wil6210.h static inline void wil_c(struct wil6210_priv *wil, u32 reg, u32 val) reg 1154 drivers/net/wireless/ath/wil6210/wil6210.h wil_w(wil, reg, wil_r(wil, reg) & ~val); reg 132 drivers/net/wireless/broadcom/b43/lo.c u16 reg, v, padmix; reg 137 drivers/net/wireless/broadcom/b43/lo.c reg = 0x43; reg 140 drivers/net/wireless/broadcom/b43/lo.c reg = 0x52; reg 145 drivers/net/wireless/broadcom/b43/lo.c reg = 0x43; reg 149 drivers/net/wireless/broadcom/b43/lo.c reg = 0x52; reg 159 drivers/net/wireless/broadcom/b43/lo.c return reg; reg 167 drivers/net/wireless/broadcom/b43/lo.c u16 reg, mask; reg 219 drivers/net/wireless/broadcom/b43/lo.c reg = lo_txctl_register_table(dev, &mask, NULL); reg 221 drivers/net/wireless/broadcom/b43/lo.c b43_radio_mask(dev, reg, mask); reg 37 drivers/net/wireless/broadcom/b43/phy_ac.c static void b43_phy_ac_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, reg 40 drivers/net/wireless/broadcom/b43/phy_ac.c b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); reg 45 drivers/net/wireless/broadcom/b43/phy_ac.c static u16 b43_phy_ac_op_radio_read(struct b43_wldev *dev, u16 reg) reg 47 drivers/net/wireless/broadcom/b43/phy_ac.c b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg); reg 51 drivers/net/wireless/broadcom/b43/phy_ac.c static void b43_phy_ac_op_radio_write(struct b43_wldev *dev, u16 reg, reg 54 drivers/net/wireless/broadcom/b43/phy_ac.c b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg); reg 215 drivers/net/wireless/broadcom/b43/phy_common.c u16 b43_radio_read(struct b43_wldev *dev, u16 reg) reg 219 drivers/net/wireless/broadcom/b43/phy_common.c return dev->phy.ops->radio_read(dev, reg); reg 222 drivers/net/wireless/broadcom/b43/phy_common.c void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value) reg 230 drivers/net/wireless/broadcom/b43/phy_common.c dev->phy.ops->radio_write(dev, reg, value); reg 266 drivers/net/wireless/broadcom/b43/phy_common.c u16 b43_phy_read(struct b43_wldev *dev, u16 reg) reg 272 drivers/net/wireless/broadcom/b43/phy_common.c return dev->phy.ops->phy_read(dev, reg); reg 274 drivers/net/wireless/broadcom/b43/phy_common.c b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); reg 278 drivers/net/wireless/broadcom/b43/phy_common.c void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value) reg 288 drivers/net/wireless/broadcom/b43/phy_common.c return dev->phy.ops->phy_write(dev, reg, value); reg 290 drivers/net/wireless/broadcom/b43/phy_common.c b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); reg 18 drivers/net/wireless/broadcom/b43/phy_common.h #define B43_PHY_CCK(reg) ((reg) | B43_PHYROUTE_BASE) reg 20 drivers/net/wireless/broadcom/b43/phy_common.h #define B43_PHY_N(reg) ((reg) | B43_PHYROUTE_BASE) reg 22 drivers/net/wireless/broadcom/b43/phy_common.h #define B43_PHY_N_BMODE(reg) ((reg) | B43_PHYROUTE_N_BMODE) reg 24 drivers/net/wireless/broadcom/b43/phy_common.h #define B43_PHY_OFDM(reg) ((reg) | B43_PHYROUTE_OFDM_GPHY) reg 26 drivers/net/wireless/broadcom/b43/phy_common.h #define B43_PHY_EXTG(reg) ((reg) | B43_PHYROUTE_EXT_GPHY) reg 161 drivers/net/wireless/broadcom/b43/phy_common.h u16 (*phy_read)(struct b43_wldev *dev, u16 reg); reg 162 drivers/net/wireless/broadcom/b43/phy_common.h void (*phy_write)(struct b43_wldev *dev, u16 reg, u16 value); reg 163 drivers/net/wireless/broadcom/b43/phy_common.h void (*phy_maskset)(struct b43_wldev *dev, u16 reg, u16 mask, u16 set); reg 164 drivers/net/wireless/broadcom/b43/phy_common.h u16 (*radio_read)(struct b43_wldev *dev, u16 reg); reg 165 drivers/net/wireless/broadcom/b43/phy_common.h void (*radio_write)(struct b43_wldev *dev, u16 reg, u16 value); reg 305 drivers/net/wireless/broadcom/b43/phy_common.h u16 b43_phy_read(struct b43_wldev *dev, u16 reg); reg 310 drivers/net/wireless/broadcom/b43/phy_common.h void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value); reg 335 drivers/net/wireless/broadcom/b43/phy_common.h u16 b43_radio_read(struct b43_wldev *dev, u16 reg); reg 341 drivers/net/wireless/broadcom/b43/phy_common.h void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value); reg 1081 drivers/net/wireless/broadcom/b43/phy_g.c u16 reg, index, ret; reg 1090 drivers/net/wireless/broadcom/b43/phy_g.c reg = b43_radio_read16(dev, 0x60); reg 1091 drivers/net/wireless/broadcom/b43/phy_g.c index = (reg & 0x001E) >> 1; reg 1093 drivers/net/wireless/broadcom/b43/phy_g.c ret |= (reg & 0x0001); reg 2558 drivers/net/wireless/broadcom/b43/phy_g.c static u16 b43_gphy_op_read(struct b43_wldev *dev, u16 reg) reg 2560 drivers/net/wireless/broadcom/b43/phy_g.c b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); reg 2564 drivers/net/wireless/broadcom/b43/phy_g.c static void b43_gphy_op_write(struct b43_wldev *dev, u16 reg, u16 value) reg 2566 drivers/net/wireless/broadcom/b43/phy_g.c b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); reg 2570 drivers/net/wireless/broadcom/b43/phy_g.c static u16 b43_gphy_op_radio_read(struct b43_wldev *dev, u16 reg) reg 2573 drivers/net/wireless/broadcom/b43/phy_g.c B43_WARN_ON(reg == 1); reg 2575 drivers/net/wireless/broadcom/b43/phy_g.c reg |= 0x80; reg 2577 drivers/net/wireless/broadcom/b43/phy_g.c b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); reg 2581 drivers/net/wireless/broadcom/b43/phy_g.c static void b43_gphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) reg 2584 drivers/net/wireless/broadcom/b43/phy_g.c B43_WARN_ON(reg == 1); reg 2586 drivers/net/wireless/broadcom/b43/phy_g.c b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); reg 1088 drivers/net/wireless/broadcom/b43/phy_ht.c static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, reg 1091 drivers/net/wireless/broadcom/b43/phy_ht.c b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); reg 1096 drivers/net/wireless/broadcom/b43/phy_ht.c static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg) reg 1099 drivers/net/wireless/broadcom/b43/phy_ht.c reg |= 0x200; reg 1101 drivers/net/wireless/broadcom/b43/phy_ht.c b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg); reg 1105 drivers/net/wireless/broadcom/b43/phy_ht.c static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg, reg 1108 drivers/net/wireless/broadcom/b43/phy_ht.c b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg); reg 813 drivers/net/wireless/broadcom/b43/phy_lcn.c static void b43_phy_lcn_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, reg 816 drivers/net/wireless/broadcom/b43/phy_lcn.c b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); reg 821 drivers/net/wireless/broadcom/b43/phy_lcn.c static u16 b43_phy_lcn_op_radio_read(struct b43_wldev *dev, u16 reg) reg 824 drivers/net/wireless/broadcom/b43/phy_lcn.c reg |= 0x200; reg 826 drivers/net/wireless/broadcom/b43/phy_lcn.c b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg); reg 830 drivers/net/wireless/broadcom/b43/phy_lcn.c static void b43_phy_lcn_op_radio_write(struct b43_wldev *dev, u16 reg, reg 833 drivers/net/wireless/broadcom/b43/phy_lcn.c b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg); reg 1965 drivers/net/wireless/broadcom/b43/phy_lp.c static void b43_lpphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, reg 1968 drivers/net/wireless/broadcom/b43/phy_lp.c b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); reg 1973 drivers/net/wireless/broadcom/b43/phy_lp.c static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg) reg 1976 drivers/net/wireless/broadcom/b43/phy_lp.c B43_WARN_ON(reg == 1); reg 1979 drivers/net/wireless/broadcom/b43/phy_lp.c if (reg != 0x4001) reg 1980 drivers/net/wireless/broadcom/b43/phy_lp.c reg |= 0x100; reg 1982 drivers/net/wireless/broadcom/b43/phy_lp.c reg |= 0x200; reg 1984 drivers/net/wireless/broadcom/b43/phy_lp.c b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); reg 1988 drivers/net/wireless/broadcom/b43/phy_lp.c static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) reg 1991 drivers/net/wireless/broadcom/b43/phy_lp.c B43_WARN_ON(reg == 1); reg 1993 drivers/net/wireless/broadcom/b43/phy_lp.c b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); reg 320 drivers/net/wireless/broadcom/b43/phy_n.c u16 reg, tmp, tmp2, val; reg 330 drivers/net/wireless/broadcom/b43/phy_n.c reg = (core == 0) ? B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2; reg 334 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_write(dev, reg, 0); reg 339 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, ~0xC0, value << 6); reg 340 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_set(dev, reg, 0x400); reg 352 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, ~tmp, val); reg 353 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_set(dev, reg, 0x1000); reg 365 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, ~tmp, val); reg 366 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_mask(dev, reg, ~tmp2); reg 378 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, ~tmp, val); reg 379 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_mask(dev, reg, ~tmp2); reg 391 drivers/net/wireless/broadcom/b43/phy_n.c u16 reg, tmp, val; reg 405 drivers/net/wireless/broadcom/b43/phy_n.c reg = (i == 0) ? reg 407 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_set(dev, reg, 0x400); reg 411 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_write(dev, reg, 0); reg 463 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, ~tmp, val); reg 473 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, ~tmp, val); reg 483 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, ~tmp, val); reg 1742 drivers/net/wireless/broadcom/b43/phy_n.c u16 reg, val; reg 1758 drivers/net/wireless/broadcom/b43/phy_n.c reg = (i == 0) ? reg 1760 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, 0xFDFF, 0x0200); reg 1765 drivers/net/wireless/broadcom/b43/phy_n.c reg = (i == 0) ? reg 1768 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, 0xFCFF, 0); reg 1770 drivers/net/wireless/broadcom/b43/phy_n.c reg = (i == 0) ? reg 1773 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, 0xFFC3, 0); reg 1781 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_set(dev, reg, val); reg 1783 drivers/net/wireless/broadcom/b43/phy_n.c reg = (i == 0) ? reg 1786 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_set(dev, reg, 0x0020); reg 1795 drivers/net/wireless/broadcom/b43/phy_n.c reg = (i == 0) ? reg 1799 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, 0xFCFF, val); reg 1800 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, 0xF3FF, val << 2); reg 1812 drivers/net/wireless/broadcom/b43/phy_n.c reg = (i == 0) ? B2056_TX0 : B2056_TX1; reg 1813 drivers/net/wireless/broadcom/b43/phy_n.c reg |= B2056_TX_TX_SSI_MUX; reg 1814 drivers/net/wireless/broadcom/b43/phy_n.c b43_radio_write(dev, reg, val); reg 1817 drivers/net/wireless/broadcom/b43/phy_n.c reg = (i == 0) ? reg 1820 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_set(dev, reg, 0x0200); reg 3832 drivers/net/wireless/broadcom/b43/phy_n.c u16 reg = (i == 0) ? reg 3836 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4); reg 3837 drivers/net/wireless/broadcom/b43/phy_n.c b43_phy_set(dev, reg, 0x4); reg 6560 drivers/net/wireless/broadcom/b43/phy_n.c static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, reg 6563 drivers/net/wireless/broadcom/b43/phy_n.c check_phyreg(dev, reg); reg 6564 drivers/net/wireless/broadcom/b43/phy_n.c b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); reg 6569 drivers/net/wireless/broadcom/b43/phy_n.c static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg) reg 6572 drivers/net/wireless/broadcom/b43/phy_n.c B43_WARN_ON(dev->phy.rev < 7 && reg == 1); reg 6575 drivers/net/wireless/broadcom/b43/phy_n.c reg |= 0x200; /* Radio 0x2057 */ reg 6577 drivers/net/wireless/broadcom/b43/phy_n.c reg |= 0x100; reg 6579 drivers/net/wireless/broadcom/b43/phy_n.c b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); reg 6583 drivers/net/wireless/broadcom/b43/phy_n.c static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) reg 6586 drivers/net/wireless/broadcom/b43/phy_n.c B43_WARN_ON(dev->phy.rev < 7 && reg == 1); reg 6588 drivers/net/wireless/broadcom/b43/phy_n.c b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); reg 48 drivers/net/wireless/broadcom/b43legacy/phy.h #define B43legacy_PHY_BASE(reg) (reg) reg 50 drivers/net/wireless/broadcom/b43legacy/phy.h #define B43legacy_PHY_OFDM(reg) ((reg) | B43legacy_PHYROUTE_OFDM_GPHY) reg 52 drivers/net/wireless/broadcom/b43legacy/phy.h #define B43legacy_PHY_EXTG(reg) ((reg) | B43legacy_PHYROUTE_EXT_GPHY) reg 1368 drivers/net/wireless/broadcom/b43legacy/radio.c u16 reg; reg 1372 drivers/net/wireless/broadcom/b43legacy/radio.c reg = b43legacy_radio_read16(dev, 0x0060); reg 1373 drivers/net/wireless/broadcom/b43legacy/radio.c index = (reg & 0x001E) >> 1; reg 1375 drivers/net/wireless/broadcom/b43legacy/radio.c ret |= (reg & 0x0001); reg 4843 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c u16 frame_type, bool reg) reg 4848 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c brcmf_dbg(TRACE, "Enter, frame_type %04x, reg=%d\n", frame_type, reg); reg 4852 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c if (reg) reg 530 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c static u32 brcmf_chip_core_read32(struct brcmf_core_priv *core, u16 reg) reg 532 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg); reg 536 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c u16 reg, u32 val) reg 538 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val); reg 1326 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c u32 base, addr, reg, pmu_cc3_mask = ~0; reg 1353 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c reg = chip->ops->read32(chip->ctx, addr); reg 1354 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c return (reg & pmu_cc3_mask) != 0; reg 1357 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c reg = chip->ops->read32(chip->ctx, addr); reg 1358 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c return reg != 0; reg 1362 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c reg = chip->ops->read32(chip->ctx, addr); reg 1363 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c return (reg & CC_SR_CTL0_ENABLE_MASK) != 0; reg 1366 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c reg = chip->ops->read32(chip->ctx, addr); reg 1367 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK | reg 1371 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c reg = chip->ops->read32(chip->ctx, addr); reg 1372 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0) reg 1376 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c reg = chip->ops->read32(chip->ctx, addr); reg 1377 drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK | reg 529 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \ reg 530 drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c CHIPCREGOFFS(reg), value) reg 1108 drivers/net/wireless/cisco/airo.c static void OUT4500( struct airo_info *, u16 reg, u16 value ); reg 1109 drivers/net/wireless/cisco/airo.c static unsigned short IN4500( struct airo_info *, u16 reg ); reg 3547 drivers/net/wireless/cisco/airo.c static void OUT4500( struct airo_info *ai, u16 reg, u16 val ) { reg 3549 drivers/net/wireless/cisco/airo.c reg <<= 1; reg 3551 drivers/net/wireless/cisco/airo.c outw( val, ai->dev->base_addr + reg ); reg 3553 drivers/net/wireless/cisco/airo.c outb( val & 0xff, ai->dev->base_addr + reg ); reg 3554 drivers/net/wireless/cisco/airo.c outb( val >> 8, ai->dev->base_addr + reg + 1 ); reg 3558 drivers/net/wireless/cisco/airo.c static u16 IN4500( struct airo_info *ai, u16 reg ) { reg 3562 drivers/net/wireless/cisco/airo.c reg <<= 1; reg 3564 drivers/net/wireless/cisco/airo.c rc = inw( ai->dev->base_addr + reg ); reg 3566 drivers/net/wireless/cisco/airo.c rc = inb( ai->dev->base_addr + reg ); reg 3567 drivers/net/wireless/cisco/airo.c rc += ((int)inb( ai->dev->base_addr + reg + 1 )) << 8; reg 331 drivers/net/wireless/intel/ipw2x00/ipw2100.c static inline void read_register(struct net_device *dev, u32 reg, u32 * val) reg 335 drivers/net/wireless/intel/ipw2x00/ipw2100.c *val = ioread32(priv->ioaddr + reg); reg 336 drivers/net/wireless/intel/ipw2x00/ipw2100.c IPW_DEBUG_IO("r: 0x%08X => 0x%08X\n", reg, *val); reg 339 drivers/net/wireless/intel/ipw2x00/ipw2100.c static inline void write_register(struct net_device *dev, u32 reg, u32 val) reg 343 drivers/net/wireless/intel/ipw2x00/ipw2100.c iowrite32(val, priv->ioaddr + reg); reg 344 drivers/net/wireless/intel/ipw2x00/ipw2100.c IPW_DEBUG_IO("w: 0x%08X <= 0x%08X\n", reg, val); reg 347 drivers/net/wireless/intel/ipw2x00/ipw2100.c static inline void read_register_word(struct net_device *dev, u32 reg, reg 352 drivers/net/wireless/intel/ipw2x00/ipw2100.c *val = ioread16(priv->ioaddr + reg); reg 353 drivers/net/wireless/intel/ipw2x00/ipw2100.c IPW_DEBUG_IO("r: 0x%08X => %04X\n", reg, *val); reg 356 drivers/net/wireless/intel/ipw2x00/ipw2100.c static inline void read_register_byte(struct net_device *dev, u32 reg, u8 * val) reg 360 drivers/net/wireless/intel/ipw2x00/ipw2100.c *val = ioread8(priv->ioaddr + reg); reg 361 drivers/net/wireless/intel/ipw2x00/ipw2100.c IPW_DEBUG_IO("r: 0x%08X => %02X\n", reg, *val); reg 364 drivers/net/wireless/intel/ipw2x00/ipw2100.c static inline void write_register_word(struct net_device *dev, u32 reg, u16 val) reg 368 drivers/net/wireless/intel/ipw2x00/ipw2100.c iowrite16(val, priv->ioaddr + reg); reg 369 drivers/net/wireless/intel/ipw2x00/ipw2100.c IPW_DEBUG_IO("w: 0x%08X <= %04X\n", reg, val); reg 372 drivers/net/wireless/intel/ipw2x00/ipw2100.c static inline void write_register_byte(struct net_device *dev, u32 reg, u8 val) reg 376 drivers/net/wireless/intel/ipw2x00/ipw2100.c iowrite8(val, priv->ioaddr + reg); reg 377 drivers/net/wireless/intel/ipw2x00/ipw2100.c IPW_DEBUG_IO("w: 0x%08X =< %02X\n", reg, val); reg 1142 drivers/net/wireless/intel/ipw2x00/ipw2100.c u32 reg = 0; reg 1147 drivers/net/wireless/intel/ipw2x00/ipw2100.c reg = (IPW_BIT_GPIO_GPIO3_MASK | IPW_BIT_GPIO_GPIO1_ENABLE | reg 1149 drivers/net/wireless/intel/ipw2x00/ipw2100.c write_register(priv->net_dev, IPW_REG_GPIO, reg); reg 1158 drivers/net/wireless/intel/ipw2x00/ipw2100.c u32 reg = 0; reg 1169 drivers/net/wireless/intel/ipw2x00/ipw2100.c read_register(priv->net_dev, IPW_REG_GPIO, ®); reg 1170 drivers/net/wireless/intel/ipw2x00/ipw2100.c value = (value << 1) | ((reg & IPW_BIT_GPIO_RF_KILL) ? 0 : 1); reg 1345 drivers/net/wireless/intel/ipw2x00/ipw2100.c u32 reg; reg 1361 drivers/net/wireless/intel/ipw2x00/ipw2100.c read_register(priv->net_dev, IPW_REG_RESET_REG, ®); reg 1363 drivers/net/wireless/intel/ipw2x00/ipw2100.c if (reg & IPW_AUX_HOST_RESET_REG_MASTER_DISABLED) reg 1484 drivers/net/wireless/intel/ipw2x00/ipw2100.c u32 reg; reg 1560 drivers/net/wireless/intel/ipw2x00/ipw2100.c read_register(priv->net_dev, IPW_REG_RESET_REG, ®); reg 1562 drivers/net/wireless/intel/ipw2x00/ipw2100.c if (reg & IPW_AUX_HOST_RESET_REG_MASTER_DISABLED) reg 2408 drivers/net/wireless/intel/ipw2x00/ipw2100.c u32 match, reg; reg 2422 drivers/net/wireless/intel/ipw2x00/ipw2100.c read_register(priv->net_dev, IPW_REG_RESET_REG, ®); reg 2424 drivers/net/wireless/intel/ipw2x00/ipw2100.c if (reg & IPW_AUX_HOST_RESET_REG_MASTER_DISABLED) reg 8520 drivers/net/wireless/intel/ipw2x00/ipw2100.c void __iomem *reg = priv->ioaddr; reg 8528 drivers/net/wireless/intel/ipw2x00/ipw2100.c readl(reg); reg 8530 drivers/net/wireless/intel/ipw2x00/ipw2100.c readl(reg); reg 8534 drivers/net/wireless/intel/ipw2x00/ipw2100.c readl(reg); reg 8536 drivers/net/wireless/intel/ipw2x00/ipw2100.c readl(reg); reg 8540 drivers/net/wireless/intel/ipw2x00/ipw2100.c readl(reg); reg 8542 drivers/net/wireless/intel/ipw2x00/ipw2100.c readl(reg); reg 8544 drivers/net/wireless/intel/ipw2x00/ipw2100.c readl(reg); reg 8556 drivers/net/wireless/intel/ipw2x00/ipw2100.c readl(reg); reg 8561 drivers/net/wireless/intel/ipw2x00/ipw2100.c readl(reg); reg 8563 drivers/net/wireless/intel/ipw2x00/ipw2100.c readl(reg); reg 8567 drivers/net/wireless/intel/ipw2x00/ipw2100.c readl(reg); reg 8569 drivers/net/wireless/intel/ipw2x00/ipw2100.c readl(reg); reg 8573 drivers/net/wireless/intel/ipw2x00/ipw2100.c readl(reg); reg 8575 drivers/net/wireless/intel/ipw2x00/ipw2100.c readl(reg); reg 8580 drivers/net/wireless/intel/ipw2x00/ipw2100.c readl(reg); reg 291 drivers/net/wireless/intel/ipw2x00/ipw2200.c static u32 _ipw_read_reg32(struct ipw_priv *priv, u32 reg); reg 295 drivers/net/wireless/intel/ipw2x00/ipw2200.c static u8 _ipw_read_reg8(struct ipw_priv *ipw, u32 reg); reg 299 drivers/net/wireless/intel/ipw2x00/ipw2200.c static void _ipw_write_reg8(struct ipw_priv *priv, u32 reg, u8 value); reg 308 drivers/net/wireless/intel/ipw2x00/ipw2200.c static void _ipw_write_reg16(struct ipw_priv *priv, u32 reg, u16 value); reg 317 drivers/net/wireless/intel/ipw2x00/ipw2200.c static void _ipw_write_reg32(struct ipw_priv *priv, u32 reg, u32 value); reg 424 drivers/net/wireless/intel/ipw2x00/ipw2200.c static void _ipw_write_reg32(struct ipw_priv *priv, u32 reg, u32 value) reg 426 drivers/net/wireless/intel/ipw2x00/ipw2200.c IPW_DEBUG_IO(" %p : reg = 0x%8X : value = 0x%8X\n", priv, reg, value); reg 427 drivers/net/wireless/intel/ipw2x00/ipw2200.c _ipw_write32(priv, IPW_INDIRECT_ADDR, reg); reg 432 drivers/net/wireless/intel/ipw2x00/ipw2200.c static void _ipw_write_reg8(struct ipw_priv *priv, u32 reg, u8 value) reg 434 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 aligned_addr = reg & IPW_INDIRECT_ADDR_MASK; /* dword align */ reg 435 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 dif_len = reg - aligned_addr; reg 437 drivers/net/wireless/intel/ipw2x00/ipw2200.c IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", reg, value); reg 443 drivers/net/wireless/intel/ipw2x00/ipw2200.c static void _ipw_write_reg16(struct ipw_priv *priv, u32 reg, u16 value) reg 445 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 aligned_addr = reg & IPW_INDIRECT_ADDR_MASK; /* dword align */ reg 446 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 dif_len = (reg - aligned_addr) & (~0x1ul); reg 448 drivers/net/wireless/intel/ipw2x00/ipw2200.c IPW_DEBUG_IO(" reg = 0x%8X : value = 0x%8X\n", reg, value); reg 454 drivers/net/wireless/intel/ipw2x00/ipw2200.c static u8 _ipw_read_reg8(struct ipw_priv *priv, u32 reg) reg 457 drivers/net/wireless/intel/ipw2x00/ipw2200.c _ipw_write32(priv, IPW_INDIRECT_ADDR, reg & IPW_INDIRECT_ADDR_MASK); reg 458 drivers/net/wireless/intel/ipw2x00/ipw2200.c IPW_DEBUG_IO(" reg = 0x%8X :\n", reg); reg 460 drivers/net/wireless/intel/ipw2x00/ipw2200.c return (word >> ((reg & 0x3) * 8)) & 0xff; reg 464 drivers/net/wireless/intel/ipw2x00/ipw2200.c static u32 _ipw_read_reg32(struct ipw_priv *priv, u32 reg) reg 468 drivers/net/wireless/intel/ipw2x00/ipw2200.c IPW_DEBUG_IO("%p : reg = 0x%08x\n", priv, reg); reg 470 drivers/net/wireless/intel/ipw2x00/ipw2200.c _ipw_write32(priv, IPW_INDIRECT_ADDR, reg); reg 472 drivers/net/wireless/intel/ipw2x00/ipw2200.c IPW_DEBUG_IO(" reg = 0x%4X : value = 0x%4x\n", reg, value); reg 559 drivers/net/wireless/intel/ipw2x00/ipw2200.c static inline void ipw_set_bit(struct ipw_priv *priv, u32 reg, u32 mask) reg 561 drivers/net/wireless/intel/ipw2x00/ipw2200.c ipw_write32(priv, reg, ipw_read32(priv, reg) | mask); reg 565 drivers/net/wireless/intel/ipw2x00/ipw2200.c static inline void ipw_clear_bit(struct ipw_priv *priv, u32 reg, u32 mask) reg 567 drivers/net/wireless/intel/ipw2x00/ipw2200.c ipw_write32(priv, reg, ipw_read32(priv, reg) & ~mask); reg 841 drivers/net/wireless/intel/ipw2x00/ipw2200.c static u32 ipw_register_toggle(u32 reg) reg 843 drivers/net/wireless/intel/ipw2x00/ipw2200.c reg &= ~IPW_START_STANDBY; reg 844 drivers/net/wireless/intel/ipw2x00/ipw2200.c if (reg & IPW_GATE_ODMA) reg 845 drivers/net/wireless/intel/ipw2x00/ipw2200.c reg &= ~IPW_GATE_ODMA; reg 846 drivers/net/wireless/intel/ipw2x00/ipw2200.c if (reg & IPW_GATE_IDMA) reg 847 drivers/net/wireless/intel/ipw2x00/ipw2200.c reg &= ~IPW_GATE_IDMA; reg 848 drivers/net/wireless/intel/ipw2x00/ipw2200.c if (reg & IPW_GATE_ADMA) reg 849 drivers/net/wireless/intel/ipw2x00/ipw2200.c reg &= ~IPW_GATE_ADMA; reg 850 drivers/net/wireless/intel/ipw2x00/ipw2200.c return reg; reg 1622 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 reg = 0; reg 1625 drivers/net/wireless/intel/ipw2x00/ipw2200.c reg = ipw_read_reg32(p, IPW_INTERNAL_CMD_EVENT); reg 1626 drivers/net/wireless/intel/ipw2x00/ipw2200.c return sprintf(buf, "0x%08x\n", reg); reg 1632 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 reg; reg 1635 drivers/net/wireless/intel/ipw2x00/ipw2200.c sscanf(buf, "%x", ®); reg 1636 drivers/net/wireless/intel/ipw2x00/ipw2200.c ipw_write_reg32(p, IPW_INTERNAL_CMD_EVENT, reg); reg 1646 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 reg = 0; reg 1649 drivers/net/wireless/intel/ipw2x00/ipw2200.c reg = ipw_read_reg32(p, 0x301100); reg 1650 drivers/net/wireless/intel/ipw2x00/ipw2200.c return sprintf(buf, "0x%08x\n", reg); reg 1656 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 reg; reg 1659 drivers/net/wireless/intel/ipw2x00/ipw2200.c sscanf(buf, "%x", ®); reg 1660 drivers/net/wireless/intel/ipw2x00/ipw2200.c ipw_write_reg32(p, 0x301100, reg); reg 1669 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 reg = 0; reg 1673 drivers/net/wireless/intel/ipw2x00/ipw2200.c reg = ipw_read_reg32(priv, priv->indirect_dword); reg 1675 drivers/net/wireless/intel/ipw2x00/ipw2200.c reg = 0; reg 1677 drivers/net/wireless/intel/ipw2x00/ipw2200.c return sprintf(buf, "0x%08x\n", reg); reg 1696 drivers/net/wireless/intel/ipw2x00/ipw2200.c u8 reg = 0; reg 1700 drivers/net/wireless/intel/ipw2x00/ipw2200.c reg = ipw_read_reg8(priv, priv->indirect_byte); reg 1702 drivers/net/wireless/intel/ipw2x00/ipw2200.c reg = 0; reg 1704 drivers/net/wireless/intel/ipw2x00/ipw2200.c return sprintf(buf, "0x%02x\n", reg); reg 1723 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 reg = 0; reg 1727 drivers/net/wireless/intel/ipw2x00/ipw2200.c reg = ipw_read32(priv, priv->direct_dword); reg 1729 drivers/net/wireless/intel/ipw2x00/ipw2200.c reg = 0; reg 1731 drivers/net/wireless/intel/ipw2x00/ipw2200.c return sprintf(buf, "0x%08x\n", reg); reg 6071 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 reg; reg 6135 drivers/net/wireless/intel/ipw2x00/ipw2200.c reg = ipw_read32(priv, IPW_MEM_FIXED_OVERRIDE); reg 6136 drivers/net/wireless/intel/ipw2x00/ipw2200.c ipw_write_reg32(priv, reg, *(u32 *) & fr); reg 2472 drivers/net/wireless/intel/iwlegacy/3945.c u32 reg; reg 2479 drivers/net/wireless/intel/iwlegacy/3945.c for (reg = BSM_SRAM_LOWER_BOUND; reg < BSM_SRAM_LOWER_BOUND + len; reg 2480 drivers/net/wireless/intel/iwlegacy/3945.c reg += sizeof(u32), image++) { reg 2481 drivers/net/wireless/intel/iwlegacy/3945.c val = il_rd_prph(il, reg); reg 2485 drivers/net/wireless/intel/iwlegacy/3945.c BSM_SRAM_LOWER_BOUND, reg - BSM_SRAM_LOWER_BOUND, reg 235 drivers/net/wireless/intel/iwlegacy/4965.c u32 reg; reg 237 drivers/net/wireless/intel/iwlegacy/4965.c reg = _il_rd(il, CSR_LED_REG); reg 238 drivers/net/wireless/intel/iwlegacy/4965.c if (reg != (reg & CSR_LED_BSM_CTRL_MSK)) reg 239 drivers/net/wireless/intel/iwlegacy/4965.c _il_wr(il, CSR_LED_REG, reg & CSR_LED_BSM_CTRL_MSK); reg 270 drivers/net/wireless/intel/iwlegacy/4965.c u32 reg; reg 277 drivers/net/wireless/intel/iwlegacy/4965.c for (reg = BSM_SRAM_LOWER_BOUND; reg < BSM_SRAM_LOWER_BOUND + len; reg 278 drivers/net/wireless/intel/iwlegacy/4965.c reg += sizeof(u32), image++) { reg 279 drivers/net/wireless/intel/iwlegacy/4965.c val = il_rd_prph(il, reg); reg 283 drivers/net/wireless/intel/iwlegacy/4965.c BSM_SRAM_LOWER_BOUND, reg - BSM_SRAM_LOWER_BOUND, reg 125 drivers/net/wireless/intel/iwlegacy/common.c il_rd_prph(struct il_priv *il, u32 reg) reg 132 drivers/net/wireless/intel/iwlegacy/common.c val = _il_rd_prph(il, reg); reg 2559 drivers/net/wireless/intel/iwlegacy/common.c u32 reg; reg 2568 drivers/net/wireless/intel/iwlegacy/common.c reg = _il_rd(il, CSR_UCODE_DRV_GP1); reg 2570 drivers/net/wireless/intel/iwlegacy/common.c if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { reg 2572 drivers/net/wireless/intel/iwlegacy/common.c reg); reg 2712 drivers/net/wireless/intel/iwlegacy/common.c u32 reg = 0; reg 2723 drivers/net/wireless/intel/iwlegacy/common.c reg = _il_rd(il, CSR_UCODE_DRV_GP1); reg 2725 drivers/net/wireless/intel/iwlegacy/common.c if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { reg 2727 drivers/net/wireless/intel/iwlegacy/common.c txq_id, reg); reg 1964 drivers/net/wireless/intel/iwlegacy/common.h u32 il_rd_prph(struct il_priv *il, u32 reg); reg 2003 drivers/net/wireless/intel/iwlegacy/common.h _il_clear_bit(struct il_priv *il, u32 reg, u32 mask) reg 2005 drivers/net/wireless/intel/iwlegacy/common.h _il_wr(il, reg, _il_rd(il, reg) & ~mask); reg 2009 drivers/net/wireless/intel/iwlegacy/common.h _il_set_bit(struct il_priv *il, u32 reg, u32 mask) reg 2011 drivers/net/wireless/intel/iwlegacy/common.h _il_wr(il, reg, _il_rd(il, reg) | mask); reg 2021 drivers/net/wireless/intel/iwlegacy/common.h il_rd(struct il_priv *il, u32 reg) reg 2028 drivers/net/wireless/intel/iwlegacy/common.h value = _il_rd(il, reg); reg 2035 drivers/net/wireless/intel/iwlegacy/common.h il_wr(struct il_priv *il, u32 reg, u32 value) reg 2041 drivers/net/wireless/intel/iwlegacy/common.h _il_wr(il, reg, value); reg 2048 drivers/net/wireless/intel/iwlegacy/common.h _il_rd_prph(struct il_priv *il, u32 reg) reg 2050 drivers/net/wireless/intel/iwlegacy/common.h _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); reg 2062 drivers/net/wireless/intel/iwlegacy/common.h il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask) reg 2068 drivers/net/wireless/intel/iwlegacy/common.h _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask)); reg 2075 drivers/net/wireless/intel/iwlegacy/common.h il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask) reg 2081 drivers/net/wireless/intel/iwlegacy/common.h _il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits)); reg 2088 drivers/net/wireless/intel/iwlegacy/common.h il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask) reg 2095 drivers/net/wireless/intel/iwlegacy/common.h val = _il_rd_prph(il, reg); reg 2096 drivers/net/wireless/intel/iwlegacy/common.h _il_wr_prph(il, reg, (val & ~mask)); reg 91 drivers/net/wireless/intel/iwlwifi/dvm/led.c u32 reg; reg 93 drivers/net/wireless/intel/iwlwifi/dvm/led.c reg = iwl_read32(priv->trans, CSR_LED_REG); reg 94 drivers/net/wireless/intel/iwlwifi/dvm/led.c if (reg != (reg & CSR_LED_BSM_CTRL_MSK)) reg 96 drivers/net/wireless/intel/iwlwifi/dvm/led.c reg & CSR_LED_BSM_CTRL_MSK); reg 1059 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg, reg 1065 drivers/net/wireless/intel/iwlwifi/fw/dbg.c u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); reg 1069 drivers/net/wireless/intel/iwlwifi/fw/dbg.c range->range_data_size = reg->internal.range_data_size; reg 1070 drivers/net/wireless/intel/iwlwifi/fw/dbg.c for (i = 0; i < le32_to_cpu(reg->internal.range_data_size); i += 4) { reg 1081 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg, reg 1086 drivers/net/wireless/intel/iwlwifi/fw/dbg.c u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); reg 1090 drivers/net/wireless/intel/iwlwifi/fw/dbg.c range->range_data_size = reg->internal.range_data_size; reg 1091 drivers/net/wireless/intel/iwlwifi/fw/dbg.c for (i = 0; i < le32_to_cpu(reg->internal.range_data_size); i += 4) reg 1098 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg, reg 1102 drivers/net/wireless/intel/iwlwifi/fw/dbg.c u32 addr = le32_to_cpu(reg->start_addr[idx]) + le32_to_cpu(reg->offset); reg 1105 drivers/net/wireless/intel/iwlwifi/fw/dbg.c range->range_data_size = reg->internal.range_data_size; reg 1107 drivers/net/wireless/intel/iwlwifi/fw/dbg.c le32_to_cpu(reg->internal.range_data_size)); reg 1113 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg, reg 1136 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg, reg 1143 drivers/net/wireless/intel/iwlwifi/fw/dbg.c return _iwl_dump_ini_paging_iter(fwrt, reg, range_ptr, idx); reg 1158 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg, void *range_ptr, reg 1178 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg, int idx) reg 1184 drivers/net/wireless/intel/iwlwifi/fw/dbg.c u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid1); reg 1187 drivers/net/wireless/intel/iwlwifi/fw/dbg.c if (le32_to_cpu(reg->offset) && reg 1190 drivers/net/wireless/intel/iwlwifi/fw/dbg.c le32_to_cpu(reg->offset))) reg 1196 drivers/net/wireless/intel/iwlwifi/fw/dbg.c if (le32_to_cpu(reg->offset)) reg 1227 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg, reg 1233 drivers/net/wireless/intel/iwlwifi/fw/dbg.c u32 offs = le32_to_cpu(reg->offset), addr; reg 1235 drivers/net/wireless/intel/iwlwifi/fw/dbg.c le32_to_cpu(reg->fifos.num_of_registers) * sizeof(*reg_dump); reg 1240 drivers/net/wireless/intel/iwlwifi/fw/dbg.c if (!iwl_ini_txf_iter(fwrt, reg, idx)) reg 1247 drivers/net/wireless/intel/iwlwifi/fw/dbg.c range->fifo_hdr.num_of_registers = reg->fifos.num_of_registers; reg 1256 drivers/net/wireless/intel/iwlwifi/fw/dbg.c for (i = 0; i < le32_to_cpu(reg->fifos.num_of_registers); i++) { reg 1257 drivers/net/wireless/intel/iwlwifi/fw/dbg.c addr = le32_to_cpu(reg->start_addr[i]) + offs; reg 1266 drivers/net/wireless/intel/iwlwifi/fw/dbg.c if (reg->fifos.header_only) { reg 1297 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg, reg 1300 drivers/net/wireless/intel/iwlwifi/fw/dbg.c u32 fid1 = le32_to_cpu(reg->fifos.fid1); reg 1301 drivers/net/wireless/intel/iwlwifi/fw/dbg.c u32 fid2 = le32_to_cpu(reg->fifos.fid2); reg 1333 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg, reg 1339 drivers/net/wireless/intel/iwlwifi/fw/dbg.c u32 offs = le32_to_cpu(reg->offset), addr; reg 1341 drivers/net/wireless/intel/iwlwifi/fw/dbg.c le32_to_cpu(reg->fifos.num_of_registers) * sizeof(*reg_dump); reg 1346 drivers/net/wireless/intel/iwlwifi/fw/dbg.c iwl_ini_get_rxf_data(fwrt, reg, &rxf_data); reg 1354 drivers/net/wireless/intel/iwlwifi/fw/dbg.c range->fifo_hdr.num_of_registers = reg->fifos.num_of_registers; reg 1361 drivers/net/wireless/intel/iwlwifi/fw/dbg.c for (i = 0; i < le32_to_cpu(reg->fifos.num_of_registers); i++) { reg 1362 drivers/net/wireless/intel/iwlwifi/fw/dbg.c addr = le32_to_cpu(reg->start_addr[i]) + offs; reg 1371 drivers/net/wireless/intel/iwlwifi/fw/dbg.c if (reg->fifos.header_only) { reg 1399 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg, reg 1411 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg, reg 1438 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg, reg 1458 drivers/net/wireless/intel/iwlwifi/fw/dbg.c return iwl_dump_ini_mon_fill_header(fwrt, reg, mon_dump, write_ptr_addr, reg 1465 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg, reg 1478 drivers/net/wireless/intel/iwlwifi/fw/dbg.c return iwl_dump_ini_mon_fill_header(fwrt, reg, mon_dump, reg 1487 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg) reg 1489 drivers/net/wireless/intel/iwlwifi/fw/dbg.c return le32_to_cpu(reg->internal.num_of_ranges); reg 1493 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg) reg 1502 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg) reg 1508 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg) reg 1512 drivers/net/wireless/intel/iwlwifi/fw/dbg.c while (iwl_ini_txf_iter(fwrt, reg, num_of_fifos)) reg 1519 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg) reg 1528 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg) reg 1531 drivers/net/wireless/intel/iwlwifi/fw/dbg.c iwl_dump_ini_mem_ranges(fwrt, reg) * reg 1533 drivers/net/wireless/intel/iwlwifi/fw/dbg.c le32_to_cpu(reg->internal.range_data_size)); reg 1537 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg) reg 1544 drivers/net/wireless/intel/iwlwifi/fw/dbg.c for (i = 0; i < iwl_dump_ini_paging_ranges(fwrt, reg); i++) reg 1548 drivers/net/wireless/intel/iwlwifi/fw/dbg.c for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg); i++) reg 1557 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg) reg 1569 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg) reg 1572 drivers/net/wireless/intel/iwlwifi/fw/dbg.c iwl_dump_ini_mem_ranges(fwrt, reg) * reg 1574 drivers/net/wireless/intel/iwlwifi/fw/dbg.c le32_to_cpu(reg->internal.range_data_size)); reg 1578 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg) reg 1583 drivers/net/wireless/intel/iwlwifi/fw/dbg.c le32_to_cpu(reg->fifos.num_of_registers) * reg 1586 drivers/net/wireless/intel/iwlwifi/fw/dbg.c while (iwl_ini_txf_iter(fwrt, reg, size)) { reg 1588 drivers/net/wireless/intel/iwlwifi/fw/dbg.c if (!reg->fifos.header_only) reg 1599 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg) reg 1604 drivers/net/wireless/intel/iwlwifi/fw/dbg.c le32_to_cpu(reg->fifos.num_of_registers) * reg 1607 drivers/net/wireless/intel/iwlwifi/fw/dbg.c if (reg->fifos.header_only) reg 1610 drivers/net/wireless/intel/iwlwifi/fw/dbg.c iwl_ini_get_rxf_data(fwrt, reg, &rx_data); reg 1627 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg); reg 1629 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg); reg 1631 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg, void *data); reg 1633 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg, void *range, reg 1649 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg, reg 1655 drivers/net/wireless/intel/iwlwifi/fw/dbg.c u32 num_of_ranges, i, type = le32_to_cpu(reg->region_type), size; reg 1662 drivers/net/wireless/intel/iwlwifi/fw/dbg.c size = ops->get_size(fwrt, reg); reg 1677 drivers/net/wireless/intel/iwlwifi/fw/dbg.c le32_to_cpu(reg->region_id), type); reg 1679 drivers/net/wireless/intel/iwlwifi/fw/dbg.c num_of_ranges = ops->get_num_of_ranges(fwrt, reg); reg 1682 drivers/net/wireless/intel/iwlwifi/fw/dbg.c header->region_id = reg->region_id; reg 1685 drivers/net/wireless/intel/iwlwifi/fw/dbg.c le32_to_cpu(reg->name_len))); reg 1686 drivers/net/wireless/intel/iwlwifi/fw/dbg.c memcpy(header->name, reg->name, le32_to_cpu(header->name_len)); reg 1688 drivers/net/wireless/intel/iwlwifi/fw/dbg.c range = ops->fill_mem_hdr(fwrt, reg, header); reg 1692 drivers/net/wireless/intel/iwlwifi/fw/dbg.c le32_to_cpu(reg->region_id), type); reg 1697 drivers/net/wireless/intel/iwlwifi/fw/dbg.c int range_size = ops->fill_range(fwrt, reg, range, i); reg 1702 drivers/net/wireless/intel/iwlwifi/fw/dbg.c le32_to_cpu(reg->region_id), type); reg 1869 drivers/net/wireless/intel/iwlwifi/fw/dbg.c struct iwl_fw_ini_region_cfg *reg; reg 1874 drivers/net/wireless/intel/iwlwifi/fw/dbg.c reg = fwrt->dump.active_regs[reg_id]; reg 1875 drivers/net/wireless/intel/iwlwifi/fw/dbg.c if (!reg) { reg 1883 drivers/net/wireless/intel/iwlwifi/fw/dbg.c if (le32_to_cpu(reg->domain) != IWL_FW_INI_DBG_DOMAIN_ALWAYS_ON) reg 1886 drivers/net/wireless/intel/iwlwifi/fw/dbg.c reg_type = le32_to_cpu(reg->region_type); reg 1890 drivers/net/wireless/intel/iwlwifi/fw/dbg.c size += iwl_dump_ini_mem(fwrt, list, reg, reg 152 drivers/net/wireless/intel/iwlwifi/iwl-io.c u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg) reg 157 drivers/net/wireless/intel/iwlwifi/iwl-io.c value = iwl_read32(trans, reg); reg 165 drivers/net/wireless/intel/iwlwifi/iwl-io.c void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value) reg 170 drivers/net/wireless/intel/iwlwifi/iwl-io.c iwl_write32(trans, reg, value); reg 176 drivers/net/wireless/intel/iwlwifi/iwl-io.c void iwl_write_direct64(struct iwl_trans *trans, u64 reg, u64 value) reg 181 drivers/net/wireless/intel/iwlwifi/iwl-io.c iwl_write64(trans, reg, value); reg 322 drivers/net/wireless/intel/iwlwifi/iwl-io.c #define IWL_CMD_MQ(arg, reg, q) { if (arg == reg(q)) return #reg; } reg 361 drivers/net/wireless/intel/iwlwifi/iwl-io.c static const struct reg rfh_mq_tbl[] = { reg 69 drivers/net/wireless/intel/iwlwifi/iwl-io.h static inline void iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask) reg 71 drivers/net/wireless/intel/iwlwifi/iwl-io.h iwl_trans_set_bits_mask(trans, reg, mask, mask); reg 74 drivers/net/wireless/intel/iwlwifi/iwl-io.h static inline void iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask) reg 76 drivers/net/wireless/intel/iwlwifi/iwl-io.h iwl_trans_set_bits_mask(trans, reg, mask, 0); reg 84 drivers/net/wireless/intel/iwlwifi/iwl-io.h u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg); reg 85 drivers/net/wireless/intel/iwlwifi/iwl-io.h void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value); reg 86 drivers/net/wireless/intel/iwlwifi/iwl-io.h void iwl_write_direct64(struct iwl_trans *trans, u64 reg, u64 value); reg 604 drivers/net/wireless/intel/iwlwifi/iwl-trans.h void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask, reg 1211 drivers/net/wireless/intel/iwlwifi/iwl-trans.h iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value) reg 1213 drivers/net/wireless/intel/iwlwifi/iwl-trans.h trans->ops->set_bits_mask(trans, reg, mask, value); reg 1024 drivers/net/wireless/intel/iwlwifi/pcie/internal.h u32 reg, u32 mask, u32 value) reg 1032 drivers/net/wireless/intel/iwlwifi/pcie/internal.h v = iwl_read32(trans, reg); reg 1035 drivers/net/wireless/intel/iwlwifi/pcie/internal.h iwl_write32(trans, reg, v); reg 1039 drivers/net/wireless/intel/iwlwifi/pcie/internal.h u32 reg, u32 mask) reg 1041 drivers/net/wireless/intel/iwlwifi/pcie/internal.h __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); reg 1045 drivers/net/wireless/intel/iwlwifi/pcie/internal.h u32 reg, u32 mask) reg 1047 drivers/net/wireless/intel/iwlwifi/pcie/internal.h __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); reg 226 drivers/net/wireless/intel/iwlwifi/pcie/rx.c u32 reg; reg 237 drivers/net/wireless/intel/iwlwifi/pcie/rx.c reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); reg 239 drivers/net/wireless/intel/iwlwifi/pcie/rx.c if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { reg 241 drivers/net/wireless/intel/iwlwifi/pcie/rx.c reg); reg 267 drivers/net/wireless/intel/iwlwifi/pcie/trans.c static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) reg 270 drivers/net/wireless/intel/iwlwifi/pcie/trans.c ((reg & 0x0000ffff) | (2 << 28))); reg 274 drivers/net/wireless/intel/iwlwifi/pcie/trans.c static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) reg 278 drivers/net/wireless/intel/iwlwifi/pcie/trans.c ((reg & 0x0000ffff) | (3 << 28))); reg 1911 drivers/net/wireless/intel/iwlwifi/pcie/trans.c static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) reg 1916 drivers/net/wireless/intel/iwlwifi/pcie/trans.c ((reg & mask) | (3 << 24))); reg 2431 drivers/net/wireless/intel/iwlwifi/pcie/trans.c static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, reg 2438 drivers/net/wireless/intel/iwlwifi/pcie/trans.c __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); reg 284 drivers/net/wireless/intel/iwlwifi/pcie/tx.c u32 reg = 0; reg 303 drivers/net/wireless/intel/iwlwifi/pcie/tx.c reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); reg 305 drivers/net/wireless/intel/iwlwifi/pcie/tx.c if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { reg 307 drivers/net/wireless/intel/iwlwifi/pcie/tx.c txq_id, reg); reg 4 drivers/net/wireless/intersil/hostap/hostap_download.c u16 val, reg; reg 30 drivers/net/wireless/intersil/hostap/hostap_download.c reg = HFA384X_INW(HFA384X_CMD_OFF); reg 33 drivers/net/wireless/intersil/hostap/hostap_download.c dev->name, reg); reg 249 drivers/net/wireless/intersil/hostap/hostap_hw.c u16 reg; reg 279 drivers/net/wireless/intersil/hostap/hostap_hw.c reg = HFA384X_INW(HFA384X_CMD_OFF); reg 282 drivers/net/wireless/intersil/hostap/hostap_hw.c "reg=0x%04x\n", dev->name, reg); reg 434 drivers/net/wireless/intersil/hostap/hostap_hw.c u16 reg = HFA384X_INW(HFA384X_EVSTAT_OFF); reg 438 drivers/net/wireless/intersil/hostap/hostap_hw.c res, entry, entry->type, entry->cmd, entry->param0, reg, reg 440 drivers/net/wireless/intersil/hostap/hostap_hw.c if (reg & HFA384X_EV_CMD) { reg 547 drivers/net/wireless/intersil/hostap/hostap_hw.c u16 reg; reg 557 drivers/net/wireless/intersil/hostap/hostap_hw.c reg = HFA384X_INW(HFA384X_CMD_OFF); reg 560 drivers/net/wireless/intersil/hostap/hostap_hw.c "reg=0x%04x\n", dev->name, io_debug_num, reg); reg 581 drivers/net/wireless/intersil/hostap/hostap_hw.c u16 reg; reg 599 drivers/net/wireless/intersil/hostap/hostap_hw.c reg = HFA384X_INW(HFA384X_EVSTAT_OFF); reg 602 drivers/net/wireless/intersil/hostap/hostap_hw.c "reg=0x%04x\n", dev->name, reg); reg 1893 drivers/net/wireless/intersil/hostap/hostap_hw.c static u16 prism2_read_fid_reg(struct net_device *dev, u16 reg) reg 1900 drivers/net/wireless/intersil/hostap/hostap_hw.c val = HFA384X_INW(reg); reg 1901 drivers/net/wireless/intersil/hostap/hostap_hw.c val2 = HFA384X_INW(reg); reg 1902 drivers/net/wireless/intersil/hostap/hostap_hw.c val3 = HFA384X_INW(reg); reg 1909 drivers/net/wireless/intersil/hostap/hostap_hw.c dev->name, i, reg, val, val2, val3); reg 1916 drivers/net/wireless/intersil/hostap/hostap_hw.c "%04x (%04x %04x %04x)\n", dev->name, reg, val, val2, val3); reg 1919 drivers/net/wireless/intersil/hostap/hostap_hw.c return HFA384X_INW(reg); reg 2890 drivers/net/wireless/intersil/hostap/hostap_hw.c static u16 hfa384x_read_reg(struct net_device *dev, u16 reg) reg 2892 drivers/net/wireless/intersil/hostap/hostap_hw.c return HFA384X_INW(reg); reg 226 drivers/net/wireless/intersil/hostap/hostap_pci.c u16 reg; reg 228 drivers/net/wireless/intersil/hostap/hostap_pci.c reg = HFA384X_INB(HFA384X_PCICOR_OFF); reg 229 drivers/net/wireless/intersil/hostap/hostap_pci.c printk(KERN_DEBUG "%s: Original COR value: 0x%0x\n", dev->name, reg); reg 242 drivers/net/wireless/intersil/hostap/hostap_pci.c HFA384X_OUTW(reg | 0x0080, HFA384X_PCICOR_OFF); reg 245 drivers/net/wireless/intersil/hostap/hostap_pci.c HFA384X_OUTW(reg & ~0x0080, HFA384X_PCICOR_OFF); reg 255 drivers/net/wireless/intersil/hostap/hostap_pci.c HFA384X_OUTW(reg | 0x0080, HFA384X_PCICOR_OFF); reg 257 drivers/net/wireless/intersil/hostap/hostap_pci.c HFA384X_OUTW(reg & ~0x0080, HFA384X_PCICOR_OFF); reg 439 drivers/net/wireless/intersil/hostap/hostap_plx.c u32 reg; reg 474 drivers/net/wireless/intersil/hostap/hostap_plx.c reg = inb(plx_ioaddr); reg 475 drivers/net/wireless/intersil/hostap/hostap_plx.c if (reg != (cor_index | COR_LEVLREQ | COR_ENABLE_FUNC)) { reg 478 drivers/net/wireless/intersil/hostap/hostap_plx.c cor_index | COR_LEVLREQ | COR_ENABLE_FUNC, reg); reg 515 drivers/net/wireless/intersil/hostap/hostap_plx.c reg = inl(plx_ioaddr + PLX_INTCSR); reg 516 drivers/net/wireless/intersil/hostap/hostap_plx.c printk(KERN_DEBUG "PLX_INTCSR=0x%x\n", reg); reg 517 drivers/net/wireless/intersil/hostap/hostap_plx.c if (!(reg & PLX_INTCSR_PCI_INTEN)) { reg 518 drivers/net/wireless/intersil/hostap/hostap_plx.c outl(reg | PLX_INTCSR_PCI_INTEN, reg 528 drivers/net/wireless/intersil/hostap/hostap_plx.c reg = inl(plx_ioaddr + PLX_CNTRL); reg 531 drivers/net/wireless/intersil/hostap/hostap_plx.c reg, (reg & PLX_CNTRL_SERIAL_EEPROM_PRESENT) != 0); reg 976 drivers/net/wireless/intersil/hostap/hostap_wlan.h #define PRISM2_IO_DEBUG_ENTRY(cmd, reg, value) \ reg 977 drivers/net/wireless/intersil/hostap/hostap_wlan.h (((cmd) << 24) | ((reg) << 16) | value) reg 980 drivers/net/wireless/intersil/hostap/hostap_wlan.h int reg, int value) reg 992 drivers/net/wireless/intersil/hostap/hostap_wlan.h PRISM2_IO_DEBUG_ENTRY(cmd, reg, value); reg 1019 drivers/net/wireless/intersil/hostap/hostap_wlan.h int reg, int value) reg 109 drivers/net/wireless/intersil/orinoco/hermes.c u16 reg; reg 112 drivers/net/wireless/intersil/orinoco/hermes.c reg = hermes_read_regn(hw, CMD); reg 113 drivers/net/wireless/intersil/orinoco/hermes.c while ((reg & HERMES_CMD_BUSY) && k) { reg 116 drivers/net/wireless/intersil/orinoco/hermes.c reg = hermes_read_regn(hw, CMD); reg 118 drivers/net/wireless/intersil/orinoco/hermes.c if (reg & HERMES_CMD_BUSY) reg 140 drivers/net/wireless/intersil/orinoco/hermes.c u16 status, reg; reg 146 drivers/net/wireless/intersil/orinoco/hermes.c reg = hermes_read_regn(hw, EVSTAT); reg 148 drivers/net/wireless/intersil/orinoco/hermes.c while ((!(reg & HERMES_EV_CMD)) && k) { reg 151 drivers/net/wireless/intersil/orinoco/hermes.c reg = hermes_read_regn(hw, EVSTAT); reg 163 drivers/net/wireless/intersil/orinoco/hermes.c if (!(reg & HERMES_EV_CMD)) { reg 166 drivers/net/wireless/intersil/orinoco/hermes.c hw->iobase, reg); reg 200 drivers/net/wireless/intersil/orinoco/hermes.c u16 reg; reg 216 drivers/net/wireless/intersil/orinoco/hermes.c reg = hermes_read_regn(hw, CMD); reg 217 drivers/net/wireless/intersil/orinoco/hermes.c while (k && (reg & HERMES_CMD_BUSY)) { reg 218 drivers/net/wireless/intersil/orinoco/hermes.c if (reg == 0xffff) /* Special case - the card has probably been reg 224 drivers/net/wireless/intersil/orinoco/hermes.c reg = hermes_read_regn(hw, CMD); reg 233 drivers/net/wireless/intersil/orinoco/hermes.c reg = hermes_read_regn(hw, EVSTAT); reg 234 drivers/net/wireless/intersil/orinoco/hermes.c hermes_write_regn(hw, EVACK, reg); reg 257 drivers/net/wireless/intersil/orinoco/hermes.c u16 reg; reg 276 drivers/net/wireless/intersil/orinoco/hermes.c reg = hermes_read_regn(hw, EVSTAT); reg 278 drivers/net/wireless/intersil/orinoco/hermes.c while ((!(reg & HERMES_EV_CMD)) && k) { reg 281 drivers/net/wireless/intersil/orinoco/hermes.c reg = hermes_read_regn(hw, EVSTAT); reg 292 drivers/net/wireless/intersil/orinoco/hermes.c if (!(reg & HERMES_EV_CMD)) { reg 320 drivers/net/wireless/intersil/orinoco/hermes.c u16 reg; reg 329 drivers/net/wireless/intersil/orinoco/hermes.c reg = hermes_read_regn(hw, EVSTAT); reg 331 drivers/net/wireless/intersil/orinoco/hermes.c while ((!(reg & HERMES_EV_ALLOC)) && k) { reg 334 drivers/net/wireless/intersil/orinoco/hermes.c reg = hermes_read_regn(hw, EVSTAT); reg 344 drivers/net/wireless/intersil/orinoco/hermes.c if (!(reg & HERMES_EV_ALLOC)) { reg 371 drivers/net/wireless/intersil/orinoco/hermes.c u16 reg; reg 378 drivers/net/wireless/intersil/orinoco/hermes.c reg = hermes_read_reg(hw, oreg); reg 379 drivers/net/wireless/intersil/orinoco/hermes.c while ((reg & HERMES_OFFSET_BUSY) && k) { reg 382 drivers/net/wireless/intersil/orinoco/hermes.c reg = hermes_read_reg(hw, oreg); reg 385 drivers/net/wireless/intersil/orinoco/hermes.c if (reg & HERMES_OFFSET_BUSY) reg 394 drivers/net/wireless/intersil/orinoco/hermes.c reg = hermes_read_reg(hw, oreg); reg 395 drivers/net/wireless/intersil/orinoco/hermes.c while ((reg & (HERMES_OFFSET_BUSY | HERMES_OFFSET_ERR)) && k) { reg 398 drivers/net/wireless/intersil/orinoco/hermes.c reg = hermes_read_reg(hw, oreg); reg 401 drivers/net/wireless/intersil/orinoco/hermes.c if (reg != offset) { reg 404 drivers/net/wireless/intersil/orinoco/hermes.c (reg & HERMES_OFFSET_BUSY) ? "timeout" : "error", reg 405 drivers/net/wireless/intersil/orinoco/hermes.c reg, id, offset); reg 407 drivers/net/wireless/intersil/orinoco/hermes.c if (reg & HERMES_OFFSET_BUSY) reg 93 drivers/net/wireless/intersil/orinoco/orinoco_nortel.c u32 reg; reg 129 drivers/net/wireless/intersil/orinoco/orinoco_nortel.c reg = ioread16(card->attr_io + COR_OFFSET); reg 130 drivers/net/wireless/intersil/orinoco/orinoco_nortel.c if (reg != COR_VALUE) { reg 132 drivers/net/wireless/intersil/orinoco/orinoco_nortel.c reg); reg 86 drivers/net/wireless/intersil/orinoco/orinoco_pci.c u16 reg; reg 98 drivers/net/wireless/intersil/orinoco/orinoco_pci.c reg = hermes_read_regn(hw, CMD); reg 99 drivers/net/wireless/intersil/orinoco/orinoco_pci.c while (time_before(jiffies, timeout) && (reg & HERMES_CMD_BUSY)) { reg 101 drivers/net/wireless/intersil/orinoco/orinoco_pci.c reg = hermes_read_regn(hw, CMD); reg 105 drivers/net/wireless/intersil/orinoco/orinoco_pci.c if (reg & HERMES_CMD_BUSY) { reg 115 drivers/net/wireless/intersil/orinoco/orinoco_plx.c u16 reg; reg 125 drivers/net/wireless/intersil/orinoco/orinoco_plx.c reg = hermes_read_regn(hw, CMD); reg 126 drivers/net/wireless/intersil/orinoco/orinoco_plx.c while (time_before(jiffies, timeout) && (reg & HERMES_CMD_BUSY)) { reg 128 drivers/net/wireless/intersil/orinoco/orinoco_plx.c reg = hermes_read_regn(hw, CMD); reg 132 drivers/net/wireless/intersil/orinoco/orinoco_plx.c if (reg & HERMES_CMD_BUSY) { reg 65 drivers/net/wireless/intersil/orinoco/orinoco_tmd.c u16 reg; reg 75 drivers/net/wireless/intersil/orinoco/orinoco_tmd.c reg = hermes_read_regn(hw, CMD); reg 76 drivers/net/wireless/intersil/orinoco/orinoco_tmd.c while (time_before(jiffies, timeout) && (reg & HERMES_CMD_BUSY)) { reg 78 drivers/net/wireless/intersil/orinoco/orinoco_tmd.c reg = hermes_read_regn(hw, CMD); reg 82 drivers/net/wireless/intersil/orinoco/orinoco_tmd.c if (reg & HERMES_CMD_BUSY) { reg 51 drivers/net/wireless/intersil/p54/p54pci.c __le32 reg; reg 60 drivers/net/wireless/intersil/p54/p54pci.c reg = P54P_READ(ctrl_stat); reg 61 drivers/net/wireless/intersil/p54/p54pci.c reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET); reg 62 drivers/net/wireless/intersil/p54/p54pci.c reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT); reg 63 drivers/net/wireless/intersil/p54/p54pci.c P54P_WRITE(ctrl_stat, reg); reg 67 drivers/net/wireless/intersil/p54/p54pci.c reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET); reg 68 drivers/net/wireless/intersil/p54/p54pci.c P54P_WRITE(ctrl_stat, reg); reg 72 drivers/net/wireless/intersil/p54/p54pci.c reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET); reg 73 drivers/net/wireless/intersil/p54/p54pci.c P54P_WRITE(ctrl_stat, reg); reg 108 drivers/net/wireless/intersil/p54/p54pci.c reg = P54P_READ(ctrl_stat); reg 109 drivers/net/wireless/intersil/p54/p54pci.c reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN); reg 110 drivers/net/wireless/intersil/p54/p54pci.c reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET); reg 111 drivers/net/wireless/intersil/p54/p54pci.c reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT); reg 112 drivers/net/wireless/intersil/p54/p54pci.c P54P_WRITE(ctrl_stat, reg); reg 116 drivers/net/wireless/intersil/p54/p54pci.c reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET); reg 117 drivers/net/wireless/intersil/p54/p54pci.c P54P_WRITE(ctrl_stat, reg); reg 121 drivers/net/wireless/intersil/p54/p54pci.c reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET); reg 122 drivers/net/wireless/intersil/p54/p54pci.c P54P_WRITE(ctrl_stat, reg); reg 305 drivers/net/wireless/intersil/p54/p54pci.c __le32 reg; reg 307 drivers/net/wireless/intersil/p54/p54pci.c reg = P54P_READ(int_ident); reg 308 drivers/net/wireless/intersil/p54/p54pci.c if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) { reg 311 drivers/net/wireless/intersil/p54/p54pci.c P54P_WRITE(int_ack, reg); reg 313 drivers/net/wireless/intersil/p54/p54pci.c reg &= P54P_READ(int_enable); reg 315 drivers/net/wireless/intersil/p54/p54pci.c if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) reg 317 drivers/net/wireless/intersil/p54/p54pci.c else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT)) reg 321 drivers/net/wireless/intersil/p54/p54pci.c return reg ? IRQ_HANDLED : IRQ_NONE; reg 122 drivers/net/wireless/intersil/p54/p54spi.c static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, u32 bits) reg 127 drivers/net/wireless/intersil/p54/p54spi.c u32 buffer = p54spi_read32(priv, reg); reg 328 drivers/net/wireless/intersil/p54/p54usb.c struct net2280_reg_write *reg = NULL; reg 331 drivers/net/wireless/intersil/p54/p54usb.c reg = kmalloc(sizeof(*reg), GFP_ATOMIC); reg 332 drivers/net/wireless/intersil/p54/p54usb.c if (!reg) reg 343 drivers/net/wireless/intersil/p54/p54usb.c reg->port = cpu_to_le16(NET2280_DEV_U32); reg 344 drivers/net/wireless/intersil/p54/p54usb.c reg->addr = cpu_to_le32(P54U_DEV_BASE); reg 345 drivers/net/wireless/intersil/p54/p54usb.c reg->val = cpu_to_le32(ISL38XX_DEV_INT_DATA); reg 352 drivers/net/wireless/intersil/p54/p54usb.c usb_sndbulkpipe(priv->udev, P54U_PIPE_DEV), reg, sizeof(*reg), reg 361 drivers/net/wireless/intersil/p54/p54usb.c reg = NULL; reg 387 drivers/net/wireless/intersil/p54/p54usb.c kfree(reg); reg 417 drivers/net/wireless/intersil/p54/p54usb.c __le32 *reg = buf; reg 435 drivers/net/wireless/intersil/p54/p54usb.c reg, sizeof(*reg), &alen, 1000); reg 439 drivers/net/wireless/intersil/p54/p54usb.c *val = *reg; reg 632 drivers/net/wireless/intersil/p54/p54usb.c __le32 reg; reg 651 drivers/net/wireless/intersil/p54/p54usb.c cpu_to_le32((u32)(unsigned long)addr), ®);\ reg 658 drivers/net/wireless/intersil/p54/p54usb.c reg |= cpu_to_le32(P54U_BRG_POWER_DOWN); reg 659 drivers/net/wireless/intersil/p54/p54usb.c reg &= cpu_to_le32(~P54U_BRG_POWER_UP); reg 660 drivers/net/wireless/intersil/p54/p54usb.c P54U_WRITE(NET2280_BRG_U32, NET2280_GPIOCTL, reg); reg 665 drivers/net/wireless/intersil/p54/p54usb.c reg |= cpu_to_le32(P54U_BRG_POWER_UP); reg 666 drivers/net/wireless/intersil/p54/p54usb.c reg &= cpu_to_le32(~P54U_BRG_POWER_DOWN); reg 667 drivers/net/wireless/intersil/p54/p54usb.c P54U_WRITE(NET2280_BRG_U32, NET2280_GPIOCTL, reg); reg 686 drivers/net/wireless/intersil/p54/p54usb.c reg |= cpu_to_le32(PCI_STATUS_REC_MASTER_ABORT); reg 687 drivers/net/wireless/intersil/p54/p54usb.c P54U_WRITE(NET2280_BRG_CFG_U16, PCI_STATUS, reg); reg 718 drivers/net/wireless/intersil/p54/p54usb.c reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET); reg 719 drivers/net/wireless/intersil/p54/p54usb.c reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT); reg 720 drivers/net/wireless/intersil/p54/p54usb.c reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN); reg 721 drivers/net/wireless/intersil/p54/p54usb.c P54U_WRITE(NET2280_DEV_U32, &devreg->ctrl_stat, reg); reg 725 drivers/net/wireless/intersil/p54/p54usb.c reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET); reg 726 drivers/net/wireless/intersil/p54/p54usb.c P54U_WRITE(NET2280_DEV_U32, &devreg->ctrl_stat, reg); reg 730 drivers/net/wireless/intersil/p54/p54usb.c reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET); reg 731 drivers/net/wireless/intersil/p54/p54usb.c P54U_WRITE(NET2280_DEV_U32, &devreg->ctrl_stat, reg); reg 736 drivers/net/wireless/intersil/p54/p54usb.c P54U_WRITE(NET2280_DEV_U32, &devreg->int_ack, reg); reg 781 drivers/net/wireless/intersil/p54/p54usb.c if (!(reg & cpu_to_le32(ISL38XX_DMA_STATUS_DONE)) || reg 782 drivers/net/wireless/intersil/p54/p54usb.c !(reg & cpu_to_le32(ISL38XX_DMA_STATUS_READY))) { reg 798 drivers/net/wireless/intersil/p54/p54usb.c reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET); reg 799 drivers/net/wireless/intersil/p54/p54usb.c reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN); reg 800 drivers/net/wireless/intersil/p54/p54usb.c reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT); reg 801 drivers/net/wireless/intersil/p54/p54usb.c P54U_WRITE(NET2280_DEV_U32, &devreg->ctrl_stat, reg); reg 805 drivers/net/wireless/intersil/p54/p54usb.c reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET); reg 806 drivers/net/wireless/intersil/p54/p54usb.c P54U_WRITE(NET2280_DEV_U32, &devreg->ctrl_stat, reg); reg 808 drivers/net/wireless/intersil/p54/p54usb.c reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET); reg 809 drivers/net/wireless/intersil/p54/p54usb.c P54U_WRITE(NET2280_DEV_U32, &devreg->ctrl_stat, reg); reg 814 drivers/net/wireless/intersil/p54/p54usb.c P54U_WRITE(NET2280_DEV_U32, &devreg->int_ack, reg); reg 837 drivers/net/wireless/intersil/p54/p54usb.c P54U_WRITE(NET2280_DEV_U32, &devreg->int_ack, reg); reg 839 drivers/net/wireless/intersil/p54/p54usb.c if (!(reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))) reg 101 drivers/net/wireless/intersil/prism54/isl_38xx.c u32 reg; reg 122 drivers/net/wireless/intersil/prism54/isl_38xx.c reg = readl(device_base + ISL38XX_INT_IDENT_REG); reg 123 drivers/net/wireless/intersil/prism54/isl_38xx.c if (reg == 0xabadface) { reg 131 drivers/net/wireless/intersil/prism54/isl_38xx.c while (reg = readl(device_base + ISL38XX_CTRL_STAT_REG), reg 132 drivers/net/wireless/intersil/prism54/isl_38xx.c (reg & ISL38XX_CTRL_STAT_SLEEPMODE) == 0) { reg 159 drivers/net/wireless/intersil/prism54/isl_38xx.c reg = readl(device_base + ISL38XX_CTRL_STAT_REG); reg 162 drivers/net/wireless/intersil/prism54/isl_38xx.c (s64)current_ts64.tv_sec, current_ts64.tv_nsec, reg); reg 203 drivers/net/wireless/intersil/prism54/isl_38xx.c u32 reg; reg 205 drivers/net/wireless/intersil/prism54/isl_38xx.c reg = ISL38XX_INT_IDENT_UPDATE | ISL38XX_INT_IDENT_SLEEP | reg 207 drivers/net/wireless/intersil/prism54/isl_38xx.c isl38xx_w32_flush(device_base, reg, ISL38XX_INT_EN_REG); reg 52 drivers/net/wireless/intersil/prism54/islpci_dev.c u32 reg, rc; reg 56 drivers/net/wireless/intersil/prism54/islpci_dev.c reg = readl(device_base + ISL38XX_CTRL_STAT_REG); reg 57 drivers/net/wireless/intersil/prism54/islpci_dev.c reg &= ~ISL38XX_CTRL_STAT_RESET; reg 58 drivers/net/wireless/intersil/prism54/islpci_dev.c reg &= ~ISL38XX_CTRL_STAT_RAMBOOT; reg 59 drivers/net/wireless/intersil/prism54/islpci_dev.c writel(reg, device_base + ISL38XX_CTRL_STAT_REG); reg 64 drivers/net/wireless/intersil/prism54/islpci_dev.c reg |= ISL38XX_CTRL_STAT_RESET; reg 65 drivers/net/wireless/intersil/prism54/islpci_dev.c writel(reg, device_base + ISL38XX_CTRL_STAT_REG); reg 70 drivers/net/wireless/intersil/prism54/islpci_dev.c reg &= ~ISL38XX_CTRL_STAT_RESET; reg 71 drivers/net/wireless/intersil/prism54/islpci_dev.c writel(reg, device_base + ISL38XX_CTRL_STAT_REG); reg 90 drivers/net/wireless/intersil/prism54/islpci_dev.c reg = ISL38XX_DEV_FIRMWARE_ADDRES; reg 111 drivers/net/wireless/intersil/prism54/islpci_dev.c isl38xx_w32_flush(device_base, reg, reg 116 drivers/net/wireless/intersil/prism54/islpci_dev.c reg += _fw_len; reg 146 drivers/net/wireless/intersil/prism54/islpci_dev.c reg = readl(device_base + ISL38XX_CTRL_STAT_REG); reg 147 drivers/net/wireless/intersil/prism54/islpci_dev.c reg &= ~ISL38XX_CTRL_STAT_CLKRUN; reg 148 drivers/net/wireless/intersil/prism54/islpci_dev.c reg &= ~ISL38XX_CTRL_STAT_RESET; reg 149 drivers/net/wireless/intersil/prism54/islpci_dev.c reg |= ISL38XX_CTRL_STAT_RAMBOOT; reg 150 drivers/net/wireless/intersil/prism54/islpci_dev.c isl38xx_w32_flush(device_base, reg, ISL38XX_CTRL_STAT_REG); reg 156 drivers/net/wireless/intersil/prism54/islpci_dev.c reg |= ISL38XX_CTRL_STAT_RESET; reg 157 drivers/net/wireless/intersil/prism54/islpci_dev.c writel(reg, device_base + ISL38XX_CTRL_STAT_REG); reg 163 drivers/net/wireless/intersil/prism54/islpci_dev.c reg &= ~ISL38XX_CTRL_STAT_RESET; reg 164 drivers/net/wireless/intersil/prism54/islpci_dev.c writel(reg, device_base + ISL38XX_CTRL_STAT_REG); reg 179 drivers/net/wireless/intersil/prism54/islpci_dev.c u32 reg; reg 190 drivers/net/wireless/intersil/prism54/islpci_dev.c reg = readl(device + ISL38XX_CTRL_STAT_REG); reg 191 drivers/net/wireless/intersil/prism54/islpci_dev.c if (reg & ISL38XX_CTRL_STAT_SLEEPMODE) reg 203 drivers/net/wireless/intersil/prism54/islpci_dev.c reg = readl(device + ISL38XX_INT_IDENT_REG); reg 207 drivers/net/wireless/intersil/prism54/islpci_dev.c reg &= readl(device + ISL38XX_INT_EN_REG); reg 208 drivers/net/wireless/intersil/prism54/islpci_dev.c reg &= ISL38XX_INT_SOURCES; reg 210 drivers/net/wireless/intersil/prism54/islpci_dev.c if (reg != 0) { reg 215 drivers/net/wireless/intersil/prism54/islpci_dev.c isl38xx_w32_flush(device, reg, ISL38XX_INT_ACK_REG); reg 219 drivers/net/wireless/intersil/prism54/islpci_dev.c "IRQ: Identification register 0x%p 0x%x\n", device, reg); reg 223 drivers/net/wireless/intersil/prism54/islpci_dev.c if (reg & ISL38XX_INT_IDENT_UPDATE) { reg 313 drivers/net/wireless/intersil/prism54/islpci_dev.c if (reg & ISL38XX_INT_IDENT_INIT) { reg 322 drivers/net/wireless/intersil/prism54/islpci_dev.c if (reg & ISL38XX_INT_IDENT_SLEEP) { reg 332 drivers/net/wireless/intersil/prism54/islpci_dev.c if (reg & ISL38XX_INT_IDENT_WAKEUP) { reg 412 drivers/net/wireless/intersil/prism54/islpci_dev.c u32 reg; reg 425 drivers/net/wireless/intersil/prism54/islpci_dev.c reg = readl(device_base + ISL38XX_CTRL_STAT_REG); reg 426 drivers/net/wireless/intersil/prism54/islpci_dev.c reg &= ~(ISL38XX_CTRL_STAT_RESET | ISL38XX_CTRL_STAT_RAMBOOT); reg 427 drivers/net/wireless/intersil/prism54/islpci_dev.c writel(reg, device_base + ISL38XX_CTRL_STAT_REG); reg 431 drivers/net/wireless/intersil/prism54/islpci_dev.c reg |= ISL38XX_CTRL_STAT_RESET; reg 432 drivers/net/wireless/intersil/prism54/islpci_dev.c writel(reg, device_base + ISL38XX_CTRL_STAT_REG); reg 437 drivers/net/wireless/intersil/prism54/islpci_dev.c reg &= ~ISL38XX_CTRL_STAT_RESET; reg 438 drivers/net/wireless/intersil/prism54/islpci_dev.c writel(reg, device_base + ISL38XX_CTRL_STAT_REG); reg 823 drivers/net/wireless/marvell/libertas/cmd.c int lbs_get_reg(struct lbs_private *priv, u16 reg, u16 offset, u32 *value) reg 835 drivers/net/wireless/marvell/libertas/cmd.c if (reg != CMD_MAC_REG_ACCESS && reg 836 drivers/net/wireless/marvell/libertas/cmd.c reg != CMD_BBP_REG_ACCESS && reg 837 drivers/net/wireless/marvell/libertas/cmd.c reg != CMD_RF_REG_ACCESS) { reg 842 drivers/net/wireless/marvell/libertas/cmd.c ret = lbs_cmd_with_response(priv, reg, &cmd); reg 844 drivers/net/wireless/marvell/libertas/cmd.c if (reg == CMD_BBP_REG_ACCESS || reg == CMD_RF_REG_ACCESS) reg 846 drivers/net/wireless/marvell/libertas/cmd.c else if (reg == CMD_MAC_REG_ACCESS) reg 865 drivers/net/wireless/marvell/libertas/cmd.c int lbs_set_reg(struct lbs_private *priv, u16 reg, u16 offset, u32 value) reg 875 drivers/net/wireless/marvell/libertas/cmd.c if (reg == CMD_BBP_REG_ACCESS || reg == CMD_RF_REG_ACCESS) reg 877 drivers/net/wireless/marvell/libertas/cmd.c else if (reg == CMD_MAC_REG_ACCESS) reg 884 drivers/net/wireless/marvell/libertas/cmd.c ret = lbs_cmd_with_response(priv, reg, &cmd); reg 136 drivers/net/wireless/marvell/libertas/cmd.h int lbs_get_reg(struct lbs_private *priv, u16 reg, u16 offset, u32 *value); reg 138 drivers/net/wireless/marvell/libertas/cmd.h int lbs_set_reg(struct lbs_private *priv, u16 reg, u16 offset, u32 value); reg 96 drivers/net/wireless/marvell/libertas/if_cs.c static inline unsigned int if_cs_read8(struct if_cs_card *card, uint reg) reg 98 drivers/net/wireless/marvell/libertas/if_cs.c unsigned int val = ioread8(card->iobase + reg); reg 100 drivers/net/wireless/marvell/libertas/if_cs.c printk(KERN_INFO "inb %08x<%02x\n", reg, val); reg 103 drivers/net/wireless/marvell/libertas/if_cs.c static inline unsigned int if_cs_read16(struct if_cs_card *card, uint reg) reg 105 drivers/net/wireless/marvell/libertas/if_cs.c unsigned int val = ioread16(card->iobase + reg); reg 107 drivers/net/wireless/marvell/libertas/if_cs.c printk(KERN_INFO "inw %08x<%04x\n", reg, val); reg 112 drivers/net/wireless/marvell/libertas/if_cs.c uint reg, reg 118 drivers/net/wireless/marvell/libertas/if_cs.c reg, count); reg 119 drivers/net/wireless/marvell/libertas/if_cs.c ioread16_rep(card->iobase + reg, buf, count); reg 122 drivers/net/wireless/marvell/libertas/if_cs.c static inline void if_cs_write8(struct if_cs_card *card, uint reg, u8 val) reg 125 drivers/net/wireless/marvell/libertas/if_cs.c printk(KERN_INFO "outb %08x>%02x\n", reg, val); reg 126 drivers/net/wireless/marvell/libertas/if_cs.c iowrite8(val, card->iobase + reg); reg 129 drivers/net/wireless/marvell/libertas/if_cs.c static inline void if_cs_write16(struct if_cs_card *card, uint reg, u16 val) reg 132 drivers/net/wireless/marvell/libertas/if_cs.c printk(KERN_INFO "outw %08x>%04x\n", reg, val); reg 133 drivers/net/wireless/marvell/libertas/if_cs.c iowrite16(val, card->iobase + reg); reg 138 drivers/net/wireless/marvell/libertas/if_cs.c uint reg, reg 144 drivers/net/wireless/marvell/libertas/if_cs.c reg, count); reg 145 drivers/net/wireless/marvell/libertas/if_cs.c iowrite16_rep(card->iobase + reg, buf, count); reg 161 drivers/net/wireless/marvell/libertas/if_cs.c static int if_cs_poll_while_fw_download(struct if_cs_card *card, uint addr, u8 reg) reg 167 drivers/net/wireless/marvell/libertas/if_cs.c if (val == reg) reg 847 drivers/net/wireless/marvell/libertas/if_sdio.c u8 reg; reg 850 drivers/net/wireless/marvell/libertas/if_sdio.c reg = sdio_f0_readb(func, SDIO_CCCR_IF, &ret); reg 854 drivers/net/wireless/marvell/libertas/if_sdio.c reg |= SDIO_BUS_ECSI; reg 855 drivers/net/wireless/marvell/libertas/if_sdio.c sdio_f0_writeb(func, reg, SDIO_CCCR_IF, &ret); reg 149 drivers/net/wireless/marvell/libertas/if_spi.c static int spu_write(struct if_spi_card *card, u16 reg, const u8 *buf, int len) reg 152 drivers/net/wireless/marvell/libertas/if_spi.c __le16 reg_out = cpu_to_le16(reg | IF_SPI_WRITE_OPERATION_MASK); reg 182 drivers/net/wireless/marvell/libertas/if_spi.c static inline int spu_write_u16(struct if_spi_card *card, u16 reg, u16 val) reg 187 drivers/net/wireless/marvell/libertas/if_spi.c return spu_write(card, reg, (u8 *)&buff, sizeof(u16)); reg 190 drivers/net/wireless/marvell/libertas/if_spi.c static inline int spu_reg_is_port_reg(u16 reg) reg 192 drivers/net/wireless/marvell/libertas/if_spi.c switch (reg) { reg 202 drivers/net/wireless/marvell/libertas/if_spi.c static int spu_read(struct if_spi_card *card, u16 reg, u8 *buf, int len) reg 206 drivers/net/wireless/marvell/libertas/if_spi.c __le16 reg_out = cpu_to_le16(reg | IF_SPI_READ_OPERATION_MASK); reg 230 drivers/net/wireless/marvell/libertas/if_spi.c delay = spu_reg_is_port_reg(reg) ? card->spu_port_delay : reg 253 drivers/net/wireless/marvell/libertas/if_spi.c static inline int spu_read_u16(struct if_spi_card *card, u16 reg, u16 *val) reg 258 drivers/net/wireless/marvell/libertas/if_spi.c ret = spu_read(card, reg, (u8 *)&buf, sizeof(buf)); reg 268 drivers/net/wireless/marvell/libertas/if_spi.c static int spu_read_u32(struct if_spi_card *card, u16 reg, u32 *val) reg 273 drivers/net/wireless/marvell/libertas/if_spi.c err = spu_read(card, reg, (u8 *)&buf, sizeof(buf)); reg 288 drivers/net/wireless/marvell/libertas/if_spi.c static int spu_wait_for_u16(struct if_spi_card *card, u16 reg, reg 295 drivers/net/wireless/marvell/libertas/if_spi.c err = spu_read_u16(card, reg, &val); reg 318 drivers/net/wireless/marvell/libertas/if_spi.c static int spu_wait_for_u32(struct if_spi_card *card, u32 reg, u32 target) reg 323 drivers/net/wireless/marvell/libertas/if_spi.c err = spu_read_u32(card, reg, &val); reg 274 drivers/net/wireless/marvell/mwifiex/cfg80211.c u16 frame_type, bool reg) reg 279 drivers/net/wireless/marvell/mwifiex/cfg80211.c if (reg) reg 84 drivers/net/wireless/marvell/mwifiex/pcie.c static int mwifiex_write_reg(struct mwifiex_adapter *adapter, int reg, u32 data) reg 88 drivers/net/wireless/marvell/mwifiex/pcie.c iowrite32(data, card->pci_mmap1 + reg); reg 95 drivers/net/wireless/marvell/mwifiex/pcie.c static int mwifiex_read_reg(struct mwifiex_adapter *adapter, int reg, u32 *data) reg 99 drivers/net/wireless/marvell/mwifiex/pcie.c *data = ioread32(card->pci_mmap1 + reg); reg 108 drivers/net/wireless/marvell/mwifiex/pcie.c int reg, u8 *data) reg 112 drivers/net/wireless/marvell/mwifiex/pcie.c *data = ioread8(card->pci_mmap1 + reg); reg 124 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 126 drivers/net/wireless/marvell/mwifiex/pcie.c if (!reg->sleep_cookie) reg 247 drivers/net/wireless/marvell/mwifiex/pcie.c card->pcie.reg = data->reg; reg 281 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg; reg 293 drivers/net/wireless/marvell/mwifiex/pcie.c reg = card->pcie.reg; reg 294 drivers/net/wireless/marvell/mwifiex/pcie.c if (reg) reg 295 drivers/net/wireless/marvell/mwifiex/pcie.c ret = mwifiex_read_reg(adapter, reg->fw_status, &fw_status); reg 492 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 497 drivers/net/wireless/marvell/mwifiex/pcie.c if (reg->sleep_cookie) reg 501 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_write_reg(adapter, reg->fw_status, FIRMWARE_READY_PCIE)) { reg 507 drivers/net/wireless/marvell/mwifiex/pcie.c if (reg->sleep_cookie) { reg 583 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 590 drivers/net/wireless/marvell/mwifiex/pcie.c if (reg->pfu_enabled) { reg 613 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 644 drivers/net/wireless/marvell/mwifiex/pcie.c if (reg->pfu_enabled) { reg 651 drivers/net/wireless/marvell/mwifiex/pcie.c desc2->flags = reg->ring_flag_eop | reg->ring_flag_sop; reg 721 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 728 drivers/net/wireless/marvell/mwifiex/pcie.c if (reg->pfu_enabled) { reg 760 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 767 drivers/net/wireless/marvell/mwifiex/pcie.c if (reg->pfu_enabled) { reg 822 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 831 drivers/net/wireless/marvell/mwifiex/pcie.c if (reg->pfu_enabled) reg 834 drivers/net/wireless/marvell/mwifiex/pcie.c card->txbd_rdptr |= reg->tx_rollover_ind; reg 838 drivers/net/wireless/marvell/mwifiex/pcie.c if (reg->pfu_enabled) reg 869 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 879 drivers/net/wireless/marvell/mwifiex/pcie.c card->txbd_rdptr = 0 | reg->tx_rollover_ind; reg 892 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 900 drivers/net/wireless/marvell/mwifiex/pcie.c card->rxbd_rdptr = reg->rx_rollover_ind; reg 902 drivers/net/wireless/marvell/mwifiex/pcie.c if (reg->pfu_enabled) reg 937 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 947 drivers/net/wireless/marvell/mwifiex/pcie.c card->rxbd_rdptr = 0 | reg->rx_rollover_ind; reg 960 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 968 drivers/net/wireless/marvell/mwifiex/pcie.c card->evtbd_rdptr = reg->evt_rollover_ind; reg 1001 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 1010 drivers/net/wireless/marvell/mwifiex/pcie.c card->evtbd_rdptr = 0 | reg->evt_rollover_ind; reg 1154 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 1160 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_read_reg(adapter, reg->tx_rdptr, &rdptr)) { reg 1170 drivers/net/wireless/marvell/mwifiex/pcie.c num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr; reg 1172 drivers/net/wireless/marvell/mwifiex/pcie.c while (((card->txbd_rdptr & reg->tx_mask) != reg 1173 drivers/net/wireless/marvell/mwifiex/pcie.c (rdptr & reg->tx_mask)) || reg 1174 drivers/net/wireless/marvell/mwifiex/pcie.c ((card->txbd_rdptr & reg->tx_rollover_ind) != reg 1175 drivers/net/wireless/marvell/mwifiex/pcie.c (rdptr & reg->tx_rollover_ind))) { reg 1176 drivers/net/wireless/marvell/mwifiex/pcie.c wrdoneidx = (card->txbd_rdptr & reg->tx_mask) >> reg 1177 drivers/net/wireless/marvell/mwifiex/pcie.c reg->tx_start_ptr; reg 1200 drivers/net/wireless/marvell/mwifiex/pcie.c if (reg->pfu_enabled) { reg 1213 drivers/net/wireless/marvell/mwifiex/pcie.c card->txbd_rdptr += reg->ring_tx_start_ptr; reg 1218 drivers/net/wireless/marvell/mwifiex/pcie.c if ((card->txbd_rdptr & reg->tx_mask) == num_tx_buffs) reg 1220 drivers/net/wireless/marvell/mwifiex/pcie.c reg->tx_rollover_ind) ^ reg 1221 drivers/net/wireless/marvell/mwifiex/pcie.c reg->tx_rollover_ind); reg 1249 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 1266 drivers/net/wireless/marvell/mwifiex/pcie.c num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr; reg 1282 drivers/net/wireless/marvell/mwifiex/pcie.c wrindx = (card->txbd_wrptr & reg->tx_mask) >> reg->tx_start_ptr; reg 1287 drivers/net/wireless/marvell/mwifiex/pcie.c if (reg->pfu_enabled) { reg 1309 drivers/net/wireless/marvell/mwifiex/pcie.c card->txbd_wrptr += reg->ring_tx_start_ptr; reg 1313 drivers/net/wireless/marvell/mwifiex/pcie.c if ((card->txbd_wrptr & reg->tx_mask) == num_tx_buffs) reg 1315 drivers/net/wireless/marvell/mwifiex/pcie.c reg->tx_rollover_ind) ^ reg 1316 drivers/net/wireless/marvell/mwifiex/pcie.c reg->tx_rollover_ind); reg 1318 drivers/net/wireless/marvell/mwifiex/pcie.c rx_val = card->rxbd_rdptr & reg->rx_wrap_mask; reg 1320 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_write_reg(adapter, reg->tx_wrptr, reg 1364 drivers/net/wireless/marvell/mwifiex/pcie.c if (reg->pfu_enabled) reg 1379 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 1391 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) { reg 1399 drivers/net/wireless/marvell/mwifiex/pcie.c while (((wrptr & reg->rx_mask) != reg 1400 drivers/net/wireless/marvell/mwifiex/pcie.c (card->rxbd_rdptr & reg->rx_mask)) || reg 1401 drivers/net/wireless/marvell/mwifiex/pcie.c ((wrptr & reg->rx_rollover_ind) == reg 1402 drivers/net/wireless/marvell/mwifiex/pcie.c (card->rxbd_rdptr & reg->rx_rollover_ind))) { reg 1406 drivers/net/wireless/marvell/mwifiex/pcie.c rd_index = card->rxbd_rdptr & reg->rx_mask; reg 1463 drivers/net/wireless/marvell/mwifiex/pcie.c if (reg->pfu_enabled) { reg 1469 drivers/net/wireless/marvell/mwifiex/pcie.c desc2->flags = reg->ring_flag_sop | reg->ring_flag_eop; reg 1477 drivers/net/wireless/marvell/mwifiex/pcie.c if ((++card->rxbd_rdptr & reg->rx_mask) == reg 1480 drivers/net/wireless/marvell/mwifiex/pcie.c reg->rx_rollover_ind) ^ reg 1481 drivers/net/wireless/marvell/mwifiex/pcie.c reg->rx_rollover_ind); reg 1487 drivers/net/wireless/marvell/mwifiex/pcie.c tx_val = card->txbd_wrptr & reg->tx_wrap_mask; reg 1489 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_write_reg(adapter, reg->rx_rdptr, reg 1498 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) { reg 1521 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 1538 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, (u32)buf_pa)) { reg 1549 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_write_reg(adapter, reg->cmd_addr_hi, reg 1559 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_write_reg(adapter, reg->cmd_size, skb->len)) { reg 1585 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 1586 drivers/net/wireless/marvell/mwifiex/pcie.c int tx_wrap = card->txbd_wrptr & reg->tx_wrap_mask; reg 1589 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_write_reg(adapter, reg->rx_rdptr, card->rxbd_rdptr | reg 1604 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 1655 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, reg 1664 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, reg 1675 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, reg 1683 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_write_reg(adapter, reg->cmd_addr_hi, reg 1692 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_write_reg(adapter, reg->cmd_size, reg 1722 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 1768 drivers/net/wireless/marvell/mwifiex/pcie.c while (reg->sleep_cookie && (count++ < 10) && reg 1795 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 0)) { reg 1802 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 0)) { reg 1837 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 1859 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) { reg 1870 drivers/net/wireless/marvell/mwifiex/pcie.c ((wrptr & reg->evt_rollover_ind) == reg 1871 drivers/net/wireless/marvell/mwifiex/pcie.c (card->evtbd_rdptr & reg->evt_rollover_ind))) { reg 1931 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 1948 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) { reg 1975 drivers/net/wireless/marvell/mwifiex/pcie.c reg->evt_rollover_ind) ^ reg 1976 drivers/net/wireless/marvell/mwifiex/pcie.c reg->evt_rollover_ind); reg 1984 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_write_reg(adapter, reg->evt_rdptr, reg 2116 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 2167 drivers/net/wireless/marvell/mwifiex/pcie.c ret = mwifiex_read_reg(adapter, reg->cmd_size, reg 2282 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 2295 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_write_reg(adapter, reg->drv_rdy, reg 2304 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_read_reg(adapter, reg->fw_status, reg 2335 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 2337 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_read_reg(adapter, reg->fw_status, &winner)) { reg 2581 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 2591 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_read_reg(adapter, reg->fw_status, &value)) { reg 2620 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 2622 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_read_reg(adapter, reg->fw_status, &fw_status)) reg 2625 drivers/net/wireless/marvell/mwifiex/pcie.c ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl, reg 2626 drivers/net/wireless/marvell/mwifiex/pcie.c reg->fw_dump_host_ready); reg 2634 drivers/net/wireless/marvell/mwifiex/pcie.c mwifiex_read_reg_byte(adapter, reg->fw_dump_ctrl, &ctrl_data); reg 2639 drivers/net/wireless/marvell/mwifiex/pcie.c if (ctrl_data != reg->fw_dump_host_ready) { reg 2642 drivers/net/wireless/marvell/mwifiex/pcie.c ret = mwifiex_write_reg(adapter, reg->fw_dump_ctrl, reg 2643 drivers/net/wireless/marvell/mwifiex/pcie.c reg->fw_dump_host_ready); reg 2661 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *creg = card->pcie.reg; reg 2662 drivers/net/wireless/marvell/mwifiex/pcie.c unsigned int reg, reg_start, reg_end; reg 2690 drivers/net/wireless/marvell/mwifiex/pcie.c reg = creg->fw_dump_start; reg 2691 drivers/net/wireless/marvell/mwifiex/pcie.c mwifiex_read_reg_byte(adapter, reg, &fw_dump_num); reg 2709 drivers/net/wireless/marvell/mwifiex/pcie.c reg = creg->fw_dump_start; reg 2711 drivers/net/wireless/marvell/mwifiex/pcie.c mwifiex_read_reg_byte(adapter, reg, &read_reg); reg 2713 drivers/net/wireless/marvell/mwifiex/pcie.c reg++; reg 2753 drivers/net/wireless/marvell/mwifiex/pcie.c for (reg = reg_start; reg <= reg_end; reg++) { reg 2754 drivers/net/wireless/marvell/mwifiex/pcie.c mwifiex_read_reg_byte(adapter, reg, dbg_ptr); reg 2845 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 2873 drivers/net/wireless/marvell/mwifiex/pcie.c if (reg->sleep_cookie) { reg 2900 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 2902 drivers/net/wireless/marvell/mwifiex/pcie.c if (reg->sleep_cookie) reg 2994 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 3000 drivers/net/wireless/marvell/mwifiex/pcie.c ret = mwifiex_read_reg(adapter, reg->fw_status, &fw_status); reg 3004 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000)) reg 3025 drivers/net/wireless/marvell/mwifiex/pcie.c if (card->pcie.reg->msix_support) { reg 3208 drivers/net/wireless/marvell/mwifiex/pcie.c const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 3211 drivers/net/wireless/marvell/mwifiex/pcie.c if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000)) reg 283 drivers/net/wireless/marvell/mwifiex/pcie.h const struct mwifiex_pcie_card_reg *reg; reg 293 drivers/net/wireless/marvell/mwifiex/pcie.h .reg = &mwifiex_reg_8766, reg 301 drivers/net/wireless/marvell/mwifiex/pcie.h .reg = &mwifiex_reg_8897, reg 311 drivers/net/wireless/marvell/mwifiex/pcie.h .reg = &mwifiex_reg_8997, reg 399 drivers/net/wireless/marvell/mwifiex/pcie.h const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 403 drivers/net/wireless/marvell/mwifiex/pcie.h if (((card->txbd_wrptr & reg->tx_mask) == reg 404 drivers/net/wireless/marvell/mwifiex/pcie.h (rdptr & reg->tx_mask)) && reg 405 drivers/net/wireless/marvell/mwifiex/pcie.h ((card->txbd_wrptr & reg->tx_rollover_ind) != reg 406 drivers/net/wireless/marvell/mwifiex/pcie.h (rdptr & reg->tx_rollover_ind))) reg 411 drivers/net/wireless/marvell/mwifiex/pcie.h if (((card->txbd_wrptr & reg->tx_mask) == reg 412 drivers/net/wireless/marvell/mwifiex/pcie.h (rdptr & reg->tx_mask)) && reg 413 drivers/net/wireless/marvell/mwifiex/pcie.h ((card->txbd_wrptr & reg->tx_rollover_ind) == reg 414 drivers/net/wireless/marvell/mwifiex/pcie.h (rdptr & reg->tx_rollover_ind))) reg 425 drivers/net/wireless/marvell/mwifiex/pcie.h const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; reg 429 drivers/net/wireless/marvell/mwifiex/pcie.h if (((card->txbd_wrptr & reg->tx_mask) != reg 430 drivers/net/wireless/marvell/mwifiex/pcie.h (card->txbd_rdptr & reg->tx_mask)) || reg 431 drivers/net/wireless/marvell/mwifiex/pcie.h ((card->txbd_wrptr & reg->tx_rollover_ind) != reg 432 drivers/net/wireless/marvell/mwifiex/pcie.h (card->txbd_rdptr & reg->tx_rollover_ind))) reg 437 drivers/net/wireless/marvell/mwifiex/pcie.h if (((card->txbd_wrptr & reg->tx_mask) != reg 438 drivers/net/wireless/marvell/mwifiex/pcie.h (card->txbd_rdptr & reg->tx_mask)) || reg 439 drivers/net/wireless/marvell/mwifiex/pcie.h ((card->txbd_wrptr & reg->tx_rollover_ind) == reg 440 drivers/net/wireless/marvell/mwifiex/pcie.h (card->txbd_rdptr & reg->tx_rollover_ind))) reg 112 drivers/net/wireless/marvell/mwifiex/sdio.c card->reg = data->reg; reg 203 drivers/net/wireless/marvell/mwifiex/sdio.c mwifiex_write_reg_locked(struct sdio_func *func, u32 reg, u8 data) reg 207 drivers/net/wireless/marvell/mwifiex/sdio.c sdio_writeb(func, data, reg, &ret); reg 214 drivers/net/wireless/marvell/mwifiex/sdio.c mwifiex_write_reg(struct mwifiex_adapter *adapter, u32 reg, u8 data) reg 220 drivers/net/wireless/marvell/mwifiex/sdio.c ret = mwifiex_write_reg_locked(card->func, reg, data); reg 229 drivers/net/wireless/marvell/mwifiex/sdio.c mwifiex_read_reg(struct mwifiex_adapter *adapter, u32 reg, u8 *data) reg 236 drivers/net/wireless/marvell/mwifiex/sdio.c val = sdio_readb(card->func, reg, &ret); reg 309 drivers/net/wireless/marvell/mwifiex/sdio.c const struct mwifiex_sdio_card_reg *reg = card->reg; reg 312 drivers/net/wireless/marvell/mwifiex/sdio.c if (mwifiex_read_reg(adapter, reg->status_reg_0, &fws0)) reg 315 drivers/net/wireless/marvell/mwifiex/sdio.c if (mwifiex_read_reg(adapter, reg->status_reg_1, &fws1)) reg 355 drivers/net/wireless/marvell/mwifiex/sdio.c if (mwifiex_read_reg(adapter, card->reg->status_reg_0, &winner)) reg 591 drivers/net/wireless/marvell/mwifiex/sdio.c u8 reg; reg 597 drivers/net/wireless/marvell/mwifiex/sdio.c if (mwifiex_read_reg(adapter, card->reg->card_cfg_2_1_reg, ®)) reg 599 drivers/net/wireless/marvell/mwifiex/sdio.c if (mwifiex_write_reg(adapter, card->reg->card_cfg_2_1_reg, reg 600 drivers/net/wireless/marvell/mwifiex/sdio.c reg | CMD53_NEW_MODE)) reg 604 drivers/net/wireless/marvell/mwifiex/sdio.c if (mwifiex_read_reg(adapter, card->reg->cmd_cfg_0, ®)) reg 606 drivers/net/wireless/marvell/mwifiex/sdio.c if (mwifiex_write_reg(adapter, card->reg->cmd_cfg_0, reg 607 drivers/net/wireless/marvell/mwifiex/sdio.c reg | CMD_PORT_RD_LEN_EN)) reg 613 drivers/net/wireless/marvell/mwifiex/sdio.c if (mwifiex_read_reg(adapter, card->reg->cmd_cfg_1, ®)) reg 615 drivers/net/wireless/marvell/mwifiex/sdio.c if (mwifiex_write_reg(adapter, card->reg->cmd_cfg_1, reg 616 drivers/net/wireless/marvell/mwifiex/sdio.c reg | CMD_PORT_AUTO_EN)) reg 631 drivers/net/wireless/marvell/mwifiex/sdio.c u8 reg; reg 643 drivers/net/wireless/marvell/mwifiex/sdio.c if (!mwifiex_read_reg(adapter, card->reg->io_port_0_reg, ®)) reg 644 drivers/net/wireless/marvell/mwifiex/sdio.c adapter->ioport |= (reg & 0xff); reg 648 drivers/net/wireless/marvell/mwifiex/sdio.c if (!mwifiex_read_reg(adapter, card->reg->io_port_1_reg, ®)) reg 649 drivers/net/wireless/marvell/mwifiex/sdio.c adapter->ioport |= ((reg & 0xff) << 8); reg 653 drivers/net/wireless/marvell/mwifiex/sdio.c if (!mwifiex_read_reg(adapter, card->reg->io_port_2_reg, ®)) reg 654 drivers/net/wireless/marvell/mwifiex/sdio.c adapter->ioport |= ((reg & 0xff) << 16); reg 662 drivers/net/wireless/marvell/mwifiex/sdio.c if (!mwifiex_read_reg(adapter, card->reg->host_int_rsr_reg, ®)) reg 663 drivers/net/wireless/marvell/mwifiex/sdio.c mwifiex_write_reg(adapter, card->reg->host_int_rsr_reg, reg 664 drivers/net/wireless/marvell/mwifiex/sdio.c reg | card->reg->sdio_int_mask); reg 669 drivers/net/wireless/marvell/mwifiex/sdio.c if (!mwifiex_read_reg(adapter, card->reg->card_misc_cfg_reg, ®)) reg 670 drivers/net/wireless/marvell/mwifiex/sdio.c mwifiex_write_reg(adapter, card->reg->card_misc_cfg_reg, reg 671 drivers/net/wireless/marvell/mwifiex/sdio.c reg | AUTO_RE_ENABLE_INT); reg 718 drivers/net/wireless/marvell/mwifiex/sdio.c const struct mwifiex_sdio_card_reg *reg = card->reg; reg 725 drivers/net/wireless/marvell/mwifiex/sdio.c if (!(rd_bitmap & reg->data_port_mask)) reg 728 drivers/net/wireless/marvell/mwifiex/sdio.c if (!(rd_bitmap & (CTRL_PORT_MASK | reg->data_port_mask))) reg 750 drivers/net/wireless/marvell/mwifiex/sdio.c card->curr_rd_port = reg->start_rd_port; reg 769 drivers/net/wireless/marvell/mwifiex/sdio.c const struct mwifiex_sdio_card_reg *reg = card->reg; reg 784 drivers/net/wireless/marvell/mwifiex/sdio.c card->curr_wr_port = reg->start_wr_port; reg 816 drivers/net/wireless/marvell/mwifiex/sdio.c if (mwifiex_read_reg(adapter, card->reg->poll_reg, &cs)) reg 842 drivers/net/wireless/marvell/mwifiex/sdio.c mwifiex_write_reg_locked(func, card->reg->host_int_mask_reg, 0); reg 857 drivers/net/wireless/marvell/mwifiex/sdio.c card->reg->max_mp_regs, reg 863 drivers/net/wireless/marvell/mwifiex/sdio.c sdio_ireg = card->mp_regs[card->reg->host_int_status_reg]; reg 930 drivers/net/wireless/marvell/mwifiex/sdio.c ret = mwifiex_write_reg_locked(func, card->reg->host_int_mask_reg, reg 931 drivers/net/wireless/marvell/mwifiex/sdio.c card->reg->host_int_enable); reg 992 drivers/net/wireless/marvell/mwifiex/sdio.c const struct mwifiex_sdio_card_reg *reg = card->reg; reg 1038 drivers/net/wireless/marvell/mwifiex/sdio.c ret = mwifiex_read_reg(adapter, reg->base_0_reg, reg 1047 drivers/net/wireless/marvell/mwifiex/sdio.c ret = mwifiex_read_reg(adapter, reg->base_1_reg, reg 1327 drivers/net/wireless/marvell/mwifiex/sdio.c card->reg->data_port_mask)) || reg 1532 drivers/net/wireless/marvell/mwifiex/sdio.c const struct mwifiex_sdio_card_reg *reg = card->reg; reg 1561 drivers/net/wireless/marvell/mwifiex/sdio.c rx_len = card->mp_regs[reg->cmd_rd_len_1] << 8; reg 1562 drivers/net/wireless/marvell/mwifiex/sdio.c rx_len |= (u16)card->mp_regs[reg->cmd_rd_len_0]; reg 1596 drivers/net/wireless/marvell/mwifiex/sdio.c bitmap = (u32) card->mp_regs[reg->wr_bitmap_l]; reg 1597 drivers/net/wireless/marvell/mwifiex/sdio.c bitmap |= ((u32) card->mp_regs[reg->wr_bitmap_u]) << 8; reg 1600 drivers/net/wireless/marvell/mwifiex/sdio.c ((u32) card->mp_regs[reg->wr_bitmap_1l]) << 16; reg 1602 drivers/net/wireless/marvell/mwifiex/sdio.c ((u32) card->mp_regs[reg->wr_bitmap_1u]) << 24; reg 1624 drivers/net/wireless/marvell/mwifiex/sdio.c (u32) card->mp_regs[reg->wr_bitmap_l] & CTRL_PORT_MASK; reg 1632 drivers/net/wireless/marvell/mwifiex/sdio.c bitmap = (u32) card->mp_regs[reg->rd_bitmap_l]; reg 1633 drivers/net/wireless/marvell/mwifiex/sdio.c bitmap |= ((u32) card->mp_regs[reg->rd_bitmap_u]) << 8; reg 1636 drivers/net/wireless/marvell/mwifiex/sdio.c ((u32) card->mp_regs[reg->rd_bitmap_1l]) << 16; reg 1638 drivers/net/wireless/marvell/mwifiex/sdio.c ((u32) card->mp_regs[reg->rd_bitmap_1u]) << 24; reg 1652 drivers/net/wireless/marvell/mwifiex/sdio.c len_reg_l = reg->rd_len_p0_l + (port << 1); reg 1653 drivers/net/wireless/marvell/mwifiex/sdio.c len_reg_u = reg->rd_len_p0_u + (port << 1); reg 2076 drivers/net/wireless/marvell/mwifiex/sdio.c const struct mwifiex_sdio_card_reg *reg = card->reg; reg 2087 drivers/net/wireless/marvell/mwifiex/sdio.c mwifiex_read_reg(adapter, card->reg->host_int_status_reg, &sdio_ireg); reg 2095 drivers/net/wireless/marvell/mwifiex/sdio.c card->curr_rd_port = reg->start_rd_port; reg 2096 drivers/net/wireless/marvell/mwifiex/sdio.c card->curr_wr_port = reg->start_wr_port; reg 2098 drivers/net/wireless/marvell/mwifiex/sdio.c card->mp_data_port_mask = reg->data_port_mask; reg 2115 drivers/net/wireless/marvell/mwifiex/sdio.c card->mp_regs = kzalloc(reg->max_mp_regs, GFP_KERNEL); reg 2200 drivers/net/wireless/marvell/mwifiex/sdio.c const struct mwifiex_sdio_card_reg *reg = card->reg; reg 2205 drivers/net/wireless/marvell/mwifiex/sdio.c card->mp_data_port_mask = reg->data_port_mask; reg 2207 drivers/net/wireless/marvell/mwifiex/sdio.c if (reg->start_wr_port) { reg 2213 drivers/net/wireless/marvell/mwifiex/sdio.c card->curr_wr_port = reg->start_wr_port; reg 2261 drivers/net/wireless/marvell/mwifiex/sdio.c sdio_writeb(card->func, card->reg->fw_dump_host_ready, reg 2262 drivers/net/wireless/marvell/mwifiex/sdio.c card->reg->fw_dump_ctrl, &ret); reg 2268 drivers/net/wireless/marvell/mwifiex/sdio.c ctrl_data = sdio_readb(card->func, card->reg->fw_dump_ctrl, reg 2278 drivers/net/wireless/marvell/mwifiex/sdio.c if (ctrl_data != card->reg->fw_dump_host_ready) { reg 2281 drivers/net/wireless/marvell/mwifiex/sdio.c sdio_writeb(card->func, card->reg->fw_dump_host_ready, reg 2282 drivers/net/wireless/marvell/mwifiex/sdio.c card->reg->fw_dump_ctrl, &ret); reg 2290 drivers/net/wireless/marvell/mwifiex/sdio.c if (ctrl_data == card->reg->fw_dump_host_ready) { reg 2304 drivers/net/wireless/marvell/mwifiex/sdio.c unsigned int reg, reg_start, reg_end; reg 2331 drivers/net/wireless/marvell/mwifiex/sdio.c reg = card->reg->fw_dump_start; reg 2333 drivers/net/wireless/marvell/mwifiex/sdio.c dump_num = sdio_readb(card->func, reg, &ret); reg 2348 drivers/net/wireless/marvell/mwifiex/sdio.c reg = card->reg->fw_dump_start; reg 2350 drivers/net/wireless/marvell/mwifiex/sdio.c read_reg = sdio_readb(card->func, reg, &ret); reg 2356 drivers/net/wireless/marvell/mwifiex/sdio.c reg++; reg 2362 drivers/net/wireless/marvell/mwifiex/sdio.c card->reg->fw_dump_ctrl, reg 2393 drivers/net/wireless/marvell/mwifiex/sdio.c reg_start = card->reg->fw_dump_start; reg 2394 drivers/net/wireless/marvell/mwifiex/sdio.c reg_end = card->reg->fw_dump_end; reg 2395 drivers/net/wireless/marvell/mwifiex/sdio.c for (reg = reg_start; reg <= reg_end; reg++) { reg 2396 drivers/net/wireless/marvell/mwifiex/sdio.c *dbg_ptr = sdio_readb(card->func, reg, &ret); reg 2427 drivers/net/wireless/marvell/mwifiex/sdio.c unsigned int reg, reg_start, reg_end; reg 2451 drivers/net/wireless/marvell/mwifiex/sdio.c reg_start = card->reg->fw_dump_start; reg 2452 drivers/net/wireless/marvell/mwifiex/sdio.c reg_end = card->reg->fw_dump_end; reg 2453 drivers/net/wireless/marvell/mwifiex/sdio.c for (reg = reg_start; reg <= reg_end; reg++) { reg 2455 drivers/net/wireless/marvell/mwifiex/sdio.c start_flag = sdio_readb(card->func, reg, &ret); reg 2490 drivers/net/wireless/marvell/mwifiex/sdio.c for (reg = reg_start; reg <= reg_end; reg++) { reg 2491 drivers/net/wireless/marvell/mwifiex/sdio.c *dbg_ptr = sdio_readb(card->func, reg, &ret); reg 2599 drivers/net/wireless/marvell/mwifiex/sdio.c u8 reg, reg_start, reg_end; reg 2625 drivers/net/wireless/marvell/mwifiex/sdio.c reg_start = cardp->reg->func1_dump_reg_start; reg 2626 drivers/net/wireless/marvell/mwifiex/sdio.c reg_end = cardp->reg->func1_dump_reg_end; reg 2631 drivers/net/wireless/marvell/mwifiex/sdio.c reg_start = cardp->reg->func1_spec_reg_table[index++]; reg 2632 drivers/net/wireless/marvell/mwifiex/sdio.c size = cardp->reg->func1_spec_reg_num; reg 2633 drivers/net/wireless/marvell/mwifiex/sdio.c reg_end = cardp->reg->func1_spec_reg_table[size-1]; reg 2640 drivers/net/wireless/marvell/mwifiex/sdio.c reg_start = cardp->reg->func1_scratch_reg; reg 2650 drivers/net/wireless/marvell/mwifiex/sdio.c for (reg = reg_start; reg <= reg_end;) { reg 2652 drivers/net/wireless/marvell/mwifiex/sdio.c data = sdio_f0_readb(cardp->func, reg, &ret); reg 2654 drivers/net/wireless/marvell/mwifiex/sdio.c data = sdio_readb(cardp->func, reg, &ret); reg 2657 drivers/net/wireless/marvell/mwifiex/sdio.c ptr += sprintf(ptr, "(%#x) ", reg); reg 2665 drivers/net/wireless/marvell/mwifiex/sdio.c if (count == 2 && reg < reg_end) reg 2666 drivers/net/wireless/marvell/mwifiex/sdio.c reg = cardp->reg->func1_spec_reg_table[index++]; reg 2668 drivers/net/wireless/marvell/mwifiex/sdio.c reg++; reg 2704 drivers/net/wireless/marvell/mwifiex/sdio.c mwifiex_read_reg(adapter, card->reg->host_int_status_reg, &sdio_ireg); reg 246 drivers/net/wireless/marvell/mwifiex/sdio.h const struct mwifiex_sdio_card_reg *reg; reg 279 drivers/net/wireless/marvell/mwifiex/sdio.h const struct mwifiex_sdio_card_reg *reg; reg 584 drivers/net/wireless/marvell/mwifiex/sdio.h .reg = &mwifiex_reg_sd87xx, reg 599 drivers/net/wireless/marvell/mwifiex/sdio.h .reg = &mwifiex_reg_sd87xx, reg 614 drivers/net/wireless/marvell/mwifiex/sdio.h .reg = &mwifiex_reg_sd87xx, reg 629 drivers/net/wireless/marvell/mwifiex/sdio.h .reg = &mwifiex_reg_sd8897, reg 644 drivers/net/wireless/marvell/mwifiex/sdio.h .reg = &mwifiex_reg_sd8977, reg 660 drivers/net/wireless/marvell/mwifiex/sdio.h .reg = &mwifiex_reg_sd8997, reg 676 drivers/net/wireless/marvell/mwifiex/sdio.h .reg = &mwifiex_reg_sd8887, reg 691 drivers/net/wireless/marvell/mwifiex/sdio.h .reg = &mwifiex_reg_sd8987, reg 707 drivers/net/wireless/marvell/mwifiex/sdio.h .reg = &mwifiex_reg_sd87xx, reg 1620 drivers/net/wireless/marvell/mwifiex/sta_cmd.c struct host_cmd_ds_chan_region_cfg *reg = &cmd->params.reg_cfg; reg 1623 drivers/net/wireless/marvell/mwifiex/sta_cmd.c cmd->size = cpu_to_le16(sizeof(*reg) + S_DS_GEN); reg 1626 drivers/net/wireless/marvell/mwifiex/sta_cmd.c reg->action = cpu_to_le16(cmd_action); reg 1108 drivers/net/wireless/marvell/mwifiex/sta_cmdresp.c struct host_cmd_ds_chan_region_cfg *reg = &resp->params.reg_cfg; reg 1109 drivers/net/wireless/marvell/mwifiex/sta_cmdresp.c u16 action = le16_to_cpu(reg->action); reg 1118 drivers/net/wireless/marvell/mwifiex/sta_cmdresp.c tlv_buf = (u8 *)reg + sizeof(*reg); reg 1119 drivers/net/wireless/marvell/mwifiex/sta_cmdresp.c tlv_buf_left = le16_to_cpu(resp->size) - S_DS_GEN - sizeof(*reg); reg 48 drivers/net/wireless/mediatek/mt76/mmio.c mt76_mmio_wr(dev, data->reg, data->value); reg 60 drivers/net/wireless/mediatek/mt76/mmio.c data->value = mt76_mmio_rr(dev, data->reg); reg 28 drivers/net/wireless/mediatek/mt76/mt76.h u32 reg; reg 119 drivers/net/wireless/mediatek/mt76/mt76x0/init.c mt76_wr(dev, pair->reg, pair->value); reg 24 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u8 bank, reg; reg 30 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c reg = MT_RF_REG(offset); reg 32 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank > 8)) reg 45 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) | reg 54 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c bank, reg, ret); reg 63 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u8 bank, reg; reg 69 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c reg = MT_RF_REG(offset); reg 71 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank > 8)) reg 81 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) | reg 88 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c if (FIELD_GET(MT_RF_CSR_CFG_REG_ID, val) == reg && reg 97 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c bank, reg, ret); reg 107 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c .reg = offset, reg 126 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c .reg = offset, reg 173 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76x0_rf_csr_wr(dev, data->reg, data->value); reg 411 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c if (pair->reg == MT_BBP(AGC, 8)) { reg 419 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_wr(dev, pair->reg, val); reg 421 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76_wr(dev, pair->reg, pair->value); reg 579 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u32 val, reg; reg 581 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c reg = (index == 1) ? MT_RF_PA_MODE_CFG1 : MT_RF_PA_MODE_CFG0; reg 582 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val = mt76_rr(dev, reg); reg 1121 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c u32 reg = rp[i].reg; reg 1124 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c switch (reg) { reg 1152 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76x0_rf_wr(dev, reg, val); reg 21 drivers/net/wireless/mediatek/mt76/mt76x0/phy.h #define MT_RF(bank, reg) ((bank) << 16 | (reg)) reg 24 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c u32 reg, val; reg 30 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c reg = usb->mcu.rp[0].reg - usb->mcu.base; reg 33 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c usb->mcu.rp[i].reg = reg++; reg 40 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c reg = get_unaligned_le32(data + 8 * i) - reg 44 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c WARN_ON_ONCE(usb->mcu.rp[i].reg != reg); reg 163 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c skb_put_le32(skb, base + data[i].reg); reg 199 drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c skb_put_le32(skb, base + data[i].reg); reg 13 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c mt76x2_adjust_high_lna_gain(struct mt76x02_dev *dev, int reg, s8 offset) reg 18 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c mt76_rr(dev, MT_BBP(AGC, reg))); reg 20 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_LNA_HIGH_GAIN, gain); reg 24 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c mt76x2_adjust_agc_gain(struct mt76x02_dev *dev, int reg, s8 offset) reg 28 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c gain = FIELD_GET(MT_BBP_AGC_GAIN, mt76_rr(dev, MT_BBP(AGC, reg))); reg 30 drivers/net/wireless/mediatek/mt76/mt76x2/phy.c mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_GAIN, gain); reg 22 drivers/net/wireless/mediatek/mt76/trace.h #define REG_ENTRY __field(u32, reg) __field(u32, val) reg 23 drivers/net/wireless/mediatek/mt76/trace.h #define REG_ASSIGN __entry->reg = reg; __entry->val = val reg 25 drivers/net/wireless/mediatek/mt76/trace.h #define REG_PR_ARG __entry->reg, __entry->val reg 28 drivers/net/wireless/mediatek/mt76/trace.h TP_PROTO(struct mt76_dev *dev, u32 reg, u32 val), reg 29 drivers/net/wireless/mediatek/mt76/trace.h TP_ARGS(dev, reg, val), reg 45 drivers/net/wireless/mediatek/mt76/trace.h TP_PROTO(struct mt76_dev *dev, u32 reg, u32 val), reg 46 drivers/net/wireless/mediatek/mt76/trace.h TP_ARGS(dev, reg, val) reg 50 drivers/net/wireless/mediatek/mt76/trace.h TP_PROTO(struct mt76_dev *dev, u32 reg, u32 val), reg 51 drivers/net/wireless/mediatek/mt76/trace.h TP_ARGS(dev, reg, val) reg 191 drivers/net/wireless/mediatek/mt76/usb.c __mt76u_wr(dev, base + data->reg, data->value); reg 218 drivers/net/wireless/mediatek/mt76/usb.c data->value = __mt76u_rr(dev, base + data->reg); reg 22 drivers/net/wireless/mediatek/mt76/usb_trace.h #define REG_ENTRY __field(u32, reg) __field(u32, val) reg 23 drivers/net/wireless/mediatek/mt76/usb_trace.h #define REG_ASSIGN __entry->reg = reg; __entry->val = val reg 25 drivers/net/wireless/mediatek/mt76/usb_trace.h #define REG_PR_ARG __entry->reg, __entry->val reg 28 drivers/net/wireless/mediatek/mt76/usb_trace.h TP_PROTO(struct mt76_dev *dev, u32 reg, u32 val), reg 29 drivers/net/wireless/mediatek/mt76/usb_trace.h TP_ARGS(dev, reg, val), reg 45 drivers/net/wireless/mediatek/mt76/usb_trace.h TP_PROTO(struct mt76_dev *dev, u32 reg, u32 val), reg 46 drivers/net/wireless/mediatek/mt76/usb_trace.h TP_ARGS(dev, reg, val) reg 50 drivers/net/wireless/mediatek/mt76/usb_trace.h TP_PROTO(struct mt76_dev *dev, u32 reg, u32 val), reg 51 drivers/net/wireless/mediatek/mt76/usb_trace.h TP_ARGS(dev, reg, val) reg 102 drivers/net/wireless/mediatek/mt7601u/debugfs.c seq_printf(file, "Reg channels: %hhu-%hhu\n", dev->ee->reg.start, reg 103 drivers/net/wireless/mediatek/mt7601u/debugfs.c dev->ee->reg.start + dev->ee->reg.num - 1); reg 197 drivers/net/wireless/mediatek/mt7601u/eeprom.c dev->ee->reg = chan_bounds[idx]; reg 111 drivers/net/wireless/mediatek/mt7601u/eeprom.h struct reg_channel_bounds reg; reg 116 drivers/net/wireless/mediatek/mt7601u/eeprom.h static inline u32 s6_validate(u32 reg) reg 118 drivers/net/wireless/mediatek/mt7601u/eeprom.h WARN_ON(reg & ~GENMASK(5, 0)); reg 119 drivers/net/wireless/mediatek/mt7601u/eeprom.h return reg & GENMASK(5, 0); reg 122 drivers/net/wireless/mediatek/mt7601u/eeprom.h static inline int s6_to_int(u32 reg) reg 126 drivers/net/wireless/mediatek/mt7601u/eeprom.h s6 = s6_validate(reg); reg 565 drivers/net/wireless/mediatek/mt7601u/init.c WARN_ON(dev->ee->reg.start - 1 + dev->ee->reg.num > reg 569 drivers/net/wireless/mediatek/mt7601u/init.c &mt76_channels_2ghz[dev->ee->reg.start - 1], reg 570 drivers/net/wireless/mediatek/mt7601u/init.c dev->ee->reg.num, reg 10 drivers/net/wireless/mediatek/mt7601u/initvals_phy.h #define RF_REG_PAIR(bank, reg, value) \ reg 11 drivers/net/wireless/mediatek/mt7601u/initvals_phy.h { MT_MCU_MEMMAP_RF | (bank) << 16 | (reg), value } reg 226 drivers/net/wireless/mediatek/mt7601u/mcu.c skb_put_le32(skb, base + data[i].reg); reg 287 drivers/net/wireless/mediatek/mt7601u/mcu.c __le32 reg; reg 291 drivers/net/wireless/mediatek/mt7601u/mcu.c reg = cpu_to_le32(FIELD_PREP(MT_TXD_INFO_TYPE, DMA_PACKET) | reg 294 drivers/net/wireless/mediatek/mt7601u/mcu.c memcpy(buf.buf, ®, sizeof(reg)); reg 295 drivers/net/wireless/mediatek/mt7601u/mcu.c memcpy(buf.buf + sizeof(reg), data, len); reg 296 drivers/net/wireless/mediatek/mt7601u/mcu.c memset(buf.buf + sizeof(reg) + len, 0, 8); reg 273 drivers/net/wireless/mediatek/mt7601u/mt7601u.h u32 reg; reg 484 drivers/net/wireless/mediatek/mt7601u/phy.c static u8 mt7601u_bbp_r47_get(struct mt7601u_dev *dev, u8 reg, u8 flag) reg 486 drivers/net/wireless/mediatek/mt7601u/phy.c flag |= reg & ~BBP_R47_FLAG; reg 785 drivers/net/wireless/mediatek/mt7601u/phy.c u32 reg; reg 792 drivers/net/wireless/mediatek/mt7601u/phy.c reg = dev->rf_pa_mode[0]; reg 795 drivers/net/wireless/mediatek/mt7601u/phy.c reg = dev->rf_pa_mode[1]; reg 799 drivers/net/wireless/mediatek/mt7601u/phy.c return decode_tb[(reg >> (tx_rate * 2)) & 0x3]; reg 24 drivers/net/wireless/mediatek/mt7601u/trace.h #define REG_ENTRY __field(u32, reg) __field(u32, val) reg 25 drivers/net/wireless/mediatek/mt7601u/trace.h #define REG_ASSIGN __entry->reg = reg; __entry->val = val reg 27 drivers/net/wireless/mediatek/mt7601u/trace.h #define REG_PR_ARG __entry->reg, __entry->val reg 30 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u32 reg, u32 val), reg 31 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, reg, val), reg 47 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u32 reg, u32 val), reg 48 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, reg, val) reg 52 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u32 reg, u32 val), reg 53 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, reg, val) reg 142 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 bank, u8 reg, u8 val), reg 143 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, bank, reg, val), reg 147 drivers/net/wireless/mediatek/mt7601u/trace.h __field(u8, reg) reg 157 drivers/net/wireless/mediatek/mt7601u/trace.h DEV_PR_ARG, __entry->bank, __entry->reg, __entry->val reg 162 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 bank, u8 reg, u8 val), reg 163 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, bank, reg, val) reg 167 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 bank, u8 reg, u8 val), reg 168 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, bank, reg, val) reg 172 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 reg, u8 val), reg 173 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, reg, val), reg 176 drivers/net/wireless/mediatek/mt7601u/trace.h __field(u8, reg) reg 185 drivers/net/wireless/mediatek/mt7601u/trace.h DEV_PR_ARG, __entry->reg, __entry->val reg 190 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 reg, u8 val), reg 191 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, reg, val) reg 195 drivers/net/wireless/mediatek/mt7601u/trace.h TP_PROTO(struct mt7601u_dev *dev, u8 reg, u8 val), reg 196 drivers/net/wireless/mediatek/mt7601u/trace.h TP_ARGS(dev, reg, val) reg 199 drivers/net/wireless/mediatek/mt7601u/usb.c u32 reg; reg 202 drivers/net/wireless/mediatek/mt7601u/usb.c reg = __mt7601u_rr(dev, offset); reg 203 drivers/net/wireless/mediatek/mt7601u/usb.c val |= reg & ~mask; reg 204 drivers/net/wireless/mediatek/mt7601u/usb.c if (reg != val) reg 370 drivers/net/wireless/quantenna/qtnfmac/cfg80211.c u16 frame_type, bool reg) reg 379 drivers/net/wireless/quantenna/qtnfmac/cfg80211.c if (reg) reg 408 drivers/net/wireless/quantenna/qtnfmac/cfg80211.c if (qtnf_cmd_send_register_mgmt(vif, qlink_frame_type, reg)) { reg 410 drivers/net/wireless/quantenna/qtnfmac/cfg80211.c vif->mac->macid, vif->vifid, reg ? "" : "un", reg 417 drivers/net/wireless/quantenna/qtnfmac/cfg80211.c vif->mac->macid, vif->vifid, reg ? "" : "un", frame_type); reg 358 drivers/net/wireless/quantenna/qtnfmac/commands.c int qtnf_cmd_send_register_mgmt(struct qtnf_vif *vif, u16 frame_type, bool reg) reg 374 drivers/net/wireless/quantenna/qtnfmac/commands.c cmd->do_register = reg; reg 29 drivers/net/wireless/quantenna/qtnfmac/commands.h int qtnf_cmd_send_register_mgmt(struct qtnf_vif *vif, u16 frame_type, bool reg); reg 168 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c void __iomem *reg = ps->base.sysctl_bar + PEARL_PCIE_CFG0_OFFSET; reg 171 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c cfg = readl(reg); reg 173 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c qtnf_non_posted_write(cfg, reg); reg 179 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c void __iomem *reg = ps->base.sysctl_bar + reg 182 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c qtnf_non_posted_write(data, reg); reg 191 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c void __iomem *reg = ps->base.sysctl_bar + reg 194 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c qtnf_non_posted_write(data, reg); reg 197 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c static int qtnf_is_state(__le32 __iomem *reg, u32 state) reg 199 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c u32 s = readl(reg); reg 204 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c static void qtnf_set_state(__le32 __iomem *reg, u32 state) reg 206 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c u32 s = readl(reg); reg 208 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c qtnf_non_posted_write(state | s, reg); reg 211 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c static void qtnf_clear_state(__le32 __iomem *reg, u32 state) reg 213 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c u32 s = readl(reg); reg 215 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c qtnf_non_posted_write(s & ~state, reg); reg 218 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c static int qtnf_poll_state(__le32 __iomem *reg, u32 state, u32 delay_in_ms) reg 222 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c while ((qtnf_is_state(reg, state) == 0)) { reg 813 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c u32 reg = readl(PCIE_HDP_INT_EN(ps->pcie_reg_base)); reg 818 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c status = reg & PCIE_HDP_INT_TX_BITS; reg 822 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c status = reg & PCIE_HDP_INT_RX_BITS; reg 826 drivers/net/wireless/quantenna/qtnfmac/pcie/pearl_pcie.c status = reg & PCIE_HDP_INT_HHBM_UF; reg 104 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c void __iomem *reg = ts->base.sysctl_bar + TOPAZ_PCIE_CFG0_OFFSET; reg 107 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c cfg = readl(reg); reg 109 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c qtnf_non_posted_write(cfg, reg); reg 114 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c void __iomem *reg = ts->base.sysctl_bar + TOPAZ_PCIE_CFG0_OFFSET; reg 115 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c u32 cfg = readl(reg); reg 130 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c void __iomem *reg = PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(ts->base.dmareg_bar); reg 132 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c ts->dma_msi_imwr = readl(reg); reg 137 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c void __iomem *reg = PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(ts->base.dmareg_bar); reg 139 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c qtnf_non_posted_write(ts->dma_msi_imwr, reg); reg 144 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c void __iomem *reg = PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(ts->base.dmareg_bar); reg 146 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c qtnf_non_posted_write(QTN_HOST_LO32(ts->dma_msi_dummy), reg); reg 157 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c static int qtnf_is_state(__le32 __iomem *reg, u32 state) reg 159 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c u32 s = readl(reg); reg 164 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c static void qtnf_set_state(__le32 __iomem *reg, u32 state) reg 166 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c qtnf_non_posted_write(state, reg); reg 169 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c static int qtnf_poll_state(__le32 __iomem *reg, u32 state, u32 delay_in_ms) reg 173 drivers/net/wireless/quantenna/qtnfmac/pcie/topaz_pcie.c while ((qtnf_is_state(reg, state) == 0)) { reg 48 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 56 drivers/net/wireless/ralink/rt2x00/rt2400pci.c if (WAIT_FOR_BBP(rt2x00dev, ®)) { reg 57 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = 0; reg 58 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, BBPCSR_VALUE, value); reg 59 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, BBPCSR_REGNUM, word); reg 60 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, BBPCSR_BUSY, 1); reg 61 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); reg 63 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); reg 72 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 85 drivers/net/wireless/ralink/rt2x00/rt2400pci.c if (WAIT_FOR_BBP(rt2x00dev, ®)) { reg 86 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = 0; reg 87 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, BBPCSR_REGNUM, word); reg 88 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, BBPCSR_BUSY, 1); reg 89 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); reg 91 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); reg 93 drivers/net/wireless/ralink/rt2x00/rt2400pci.c WAIT_FOR_BBP(rt2x00dev, ®); reg 96 drivers/net/wireless/ralink/rt2x00/rt2400pci.c value = rt2x00_get_field32(reg, BBPCSR_VALUE); reg 106 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 114 drivers/net/wireless/ralink/rt2x00/rt2400pci.c if (WAIT_FOR_RF(rt2x00dev, ®)) { reg 115 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = 0; reg 116 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RFCSR_VALUE, value); reg 117 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20); reg 118 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RFCSR_IF_SELECT, 0); reg 119 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RFCSR_BUSY, 1); reg 121 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, RFCSR, reg); reg 131 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 133 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR21); reg 135 drivers/net/wireless/ralink/rt2x00/rt2400pci.c eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN); reg 136 drivers/net/wireless/ralink/rt2x00/rt2400pci.c eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT); reg 138 drivers/net/wireless/ralink/rt2x00/rt2400pci.c !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK); reg 140 drivers/net/wireless/ralink/rt2x00/rt2400pci.c !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT); reg 146 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg = 0; reg 148 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); reg 149 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); reg 150 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK, reg 152 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT, reg 155 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR21, reg); reg 195 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 197 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR); reg 198 drivers/net/wireless/ralink/rt2x00/rt2400pci.c return rt2x00_get_field32(reg, GPIOCSR_VAL0); reg 208 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 210 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR); reg 213 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, LEDCSR_LINK, enabled); reg 215 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled); reg 217 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); reg 226 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 228 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR); reg 229 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on); reg 230 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off); reg 231 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); reg 254 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 261 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); reg 262 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RXCSR0_DROP_CRC, reg 264 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, reg 266 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, reg 268 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, reg 270 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RXCSR0_DROP_TODS, reg 273 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); reg 274 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); reg 283 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 290 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, BCNCSR1); reg 291 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload); reg 292 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg); reg 297 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR14); reg 298 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync); reg 299 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR14, reg); reg 317 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 325 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR1); reg 326 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x1ff); reg 327 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0x13a); reg 328 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); reg 329 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1); reg 330 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg); reg 332 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, ARCSR2); reg 333 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); reg 334 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); reg 335 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, ARCSR2_LENGTH, reg 337 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg); reg 339 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, ARCSR3); reg 340 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); reg 341 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); reg 342 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, ARCSR2_LENGTH, reg 344 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg); reg 346 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, ARCSR4); reg 347 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); reg 348 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); reg 349 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, ARCSR2_LENGTH, reg 351 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg); reg 353 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, ARCSR5); reg 354 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); reg 355 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); reg 356 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, ARCSR2_LENGTH, reg 358 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg); reg 365 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR11); reg 366 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time); reg 367 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR11, reg); reg 369 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR18); reg 370 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR18_SIFS, erp->sifs); reg 371 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR18_PIFS, erp->pifs); reg 372 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR18, reg); reg 374 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR19); reg 375 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR19_DIFS, erp->difs); reg 376 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR19_EIFS, erp->eifs); reg 377 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR19, reg); reg 381 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR12); reg 382 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, reg 384 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, reg 386 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR12, reg); reg 501 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 503 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR11); reg 504 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR11_LONG_RETRY, reg 506 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR11_SHORT_RETRY, reg 508 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR11, reg); reg 517 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 520 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR20); reg 521 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN, reg 523 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP, reg 527 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); reg 528 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR20, reg); reg 530 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR20_AUTOWAKE, 1); reg 531 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR20, reg); reg 533 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR20); reg 534 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); reg 535 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR20, reg); reg 559 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 561 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR11); reg 562 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR11_CWMIN, cw_min); reg 563 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR11_CWMAX, cw_max); reg 564 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR11, reg); reg 573 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 579 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CNT0); reg 580 drivers/net/wireless/ralink/rt2x00/rt2400pci.c qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR); reg 630 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 634 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); reg 635 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0); reg 636 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); reg 639 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR14); reg 640 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); reg 641 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR14_TBCN, 1); reg 642 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); reg 643 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR14, reg); reg 653 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 657 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); reg 658 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1); reg 659 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); reg 662 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); reg 663 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TXCSR0_KICK_TX, 1); reg 664 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); reg 667 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); reg 668 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1); reg 669 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); reg 679 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 685 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); reg 686 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TXCSR0_ABORT, 1); reg 687 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); reg 690 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); reg 691 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1); reg 692 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); reg 695 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR14); reg 696 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); reg 697 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR14_TBCN, 0); reg 698 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); reg 699 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR14, reg); reg 760 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 765 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR2); reg 766 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); reg 767 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); reg 768 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); reg 769 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); reg 770 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg); reg 773 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR3); reg 774 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, reg 776 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg); reg 779 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR5); reg 780 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, reg 782 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg); reg 785 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR4); reg 786 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, reg 788 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg); reg 791 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR6); reg 792 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, reg 794 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg); reg 796 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, RXCSR1); reg 797 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); reg 798 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); reg 799 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg); reg 802 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, RXCSR2); reg 803 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, reg 805 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg); reg 812 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 819 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, TIMECSR); reg 820 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TIMECSR_US_COUNT, 33); reg 821 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63); reg 822 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0); reg 823 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg); reg 825 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR9); reg 826 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT, reg 828 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR9, reg); reg 830 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR14); reg 831 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); reg 832 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR14_TSF_SYNC, 0); reg 833 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR14_TBCN, 0); reg 834 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR14_TCFP, 0); reg 835 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR14_TATIMW, 0); reg 836 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); reg 837 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0); reg 838 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0); reg 839 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR14, reg); reg 843 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, ARCSR0); reg 844 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133); reg 845 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134); reg 846 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136); reg 847 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135); reg 848 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg); reg 850 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, RXCSR3); reg 851 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); /* Tx power.*/ reg 852 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1); reg 853 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); /* Signal */ reg 854 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1); reg 855 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); /* Rssi */ reg 856 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1); reg 857 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg); reg 867 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, MACCSR2); reg 868 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, MACCSR2_DELAY, 64); reg 869 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg); reg 871 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, RALINKCSR); reg 872 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17); reg 873 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154); reg 874 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0); reg 875 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 154); reg 876 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg); reg 878 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR1); reg 879 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR1_SOFT_RESET, 1); reg 880 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR1_BBP_RESET, 0); reg 881 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR1_HOST_READY, 0); reg 882 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR1, reg); reg 884 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR1); reg 885 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR1_SOFT_RESET, 0); reg 886 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR1_HOST_READY, 1); reg 887 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR1, reg); reg 894 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CNT0); reg 895 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CNT4); reg 961 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 969 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR7); reg 970 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR7, reg); reg 979 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR8); reg 980 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); reg 981 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); reg 982 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); reg 983 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); reg 984 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR8_RXDONE, mask); reg 985 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR8, reg); reg 1024 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg, reg2; reg 1032 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, PWRCSR1); reg 1033 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1); reg 1034 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state); reg 1035 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state); reg 1036 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); reg 1037 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); reg 1050 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); reg 1169 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 1175 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR14); reg 1176 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); reg 1177 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR14, reg); reg 1186 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); reg 1200 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); reg 1201 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR14, reg); reg 1307 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 1315 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR8); reg 1316 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, irq_field, 0); reg 1317 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR8, reg); reg 1325 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 1340 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR8); reg 1341 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0); reg 1342 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0); reg 1343 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0); reg 1344 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR8, reg); reg 1370 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg, mask; reg 1376 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR7); reg 1377 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR7, reg); reg 1379 drivers/net/wireless/ralink/rt2x00/rt2400pci.c if (!reg) reg 1385 drivers/net/wireless/ralink/rt2x00/rt2400pci.c mask = reg; reg 1390 drivers/net/wireless/ralink/rt2x00/rt2400pci.c if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) reg 1393 drivers/net/wireless/ralink/rt2x00/rt2400pci.c if (rt2x00_get_field32(reg, CSR7_RXDONE)) reg 1396 drivers/net/wireless/ralink/rt2x00/rt2400pci.c if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) || reg 1397 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) || reg 1398 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) { reg 1414 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR8); reg 1415 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg |= mask; reg 1416 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, CSR8, reg); reg 1431 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 1435 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR21); reg 1440 drivers/net/wireless/ralink/rt2x00/rt2400pci.c eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ? reg 1467 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 1480 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR0); reg 1482 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_get_field32(reg, CSR0_REVISION)); reg 1608 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 1625 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR); reg 1626 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, GPIOCSR_DIR0, 1); reg 1627 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg); reg 1685 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 1687 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR17); reg 1688 drivers/net/wireless/ralink/rt2x00/rt2400pci.c tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32; reg 1689 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR16); reg 1690 drivers/net/wireless/ralink/rt2x00/rt2400pci.c tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER); reg 1698 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg; reg 1700 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR15); reg 1701 drivers/net/wireless/ralink/rt2x00/rt2400pci.c return rt2x00_get_field32(reg, CSR15_BEACON_SENT); reg 48 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 56 drivers/net/wireless/ralink/rt2x00/rt2500pci.c if (WAIT_FOR_BBP(rt2x00dev, ®)) { reg 57 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = 0; reg 58 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, BBPCSR_VALUE, value); reg 59 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, BBPCSR_REGNUM, word); reg 60 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, BBPCSR_BUSY, 1); reg 61 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); reg 63 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); reg 72 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 85 drivers/net/wireless/ralink/rt2x00/rt2500pci.c if (WAIT_FOR_BBP(rt2x00dev, ®)) { reg 86 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = 0; reg 87 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, BBPCSR_REGNUM, word); reg 88 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, BBPCSR_BUSY, 1); reg 89 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); reg 91 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); reg 93 drivers/net/wireless/ralink/rt2x00/rt2500pci.c WAIT_FOR_BBP(rt2x00dev, ®); reg 96 drivers/net/wireless/ralink/rt2x00/rt2500pci.c value = rt2x00_get_field32(reg, BBPCSR_VALUE); reg 106 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 114 drivers/net/wireless/ralink/rt2x00/rt2500pci.c if (WAIT_FOR_RF(rt2x00dev, ®)) { reg 115 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = 0; reg 116 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RFCSR_VALUE, value); reg 117 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20); reg 118 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RFCSR_IF_SELECT, 0); reg 119 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RFCSR_BUSY, 1); reg 121 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, RFCSR, reg); reg 131 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 133 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR21); reg 135 drivers/net/wireless/ralink/rt2x00/rt2500pci.c eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN); reg 136 drivers/net/wireless/ralink/rt2x00/rt2500pci.c eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT); reg 138 drivers/net/wireless/ralink/rt2x00/rt2500pci.c !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK); reg 140 drivers/net/wireless/ralink/rt2x00/rt2500pci.c !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT); reg 146 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg = 0; reg 148 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); reg 149 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); reg 150 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK, reg 152 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT, reg 155 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR21, reg); reg 195 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 197 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR); reg 198 drivers/net/wireless/ralink/rt2x00/rt2500pci.c return rt2x00_get_field32(reg, GPIOCSR_VAL0); reg 208 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 210 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR); reg 213 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, LEDCSR_LINK, enabled); reg 215 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled); reg 217 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); reg 226 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 228 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR); reg 229 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on); reg 230 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off); reg 231 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); reg 254 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 262 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); reg 263 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR0_DROP_CRC, reg 265 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, reg 267 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, reg 269 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, reg 271 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR0_DROP_TODS, reg 274 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); reg 275 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR0_DROP_MCAST, reg 277 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR0_DROP_BCAST, 0); reg 278 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); reg 288 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 295 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, BCNCSR1); reg 296 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload); reg 297 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN, queue->cw_min); reg 298 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg); reg 303 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR14); reg 304 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync); reg 305 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR14, reg); reg 322 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 330 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR1); reg 331 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x162); reg 332 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0xa2); reg 333 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); reg 334 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1); reg 335 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg); reg 337 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, ARCSR2); reg 338 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); reg 339 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); reg 340 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARCSR2_LENGTH, reg 342 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg); reg 344 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, ARCSR3); reg 345 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); reg 346 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); reg 347 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARCSR2_LENGTH, reg 349 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg); reg 351 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, ARCSR4); reg 352 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); reg 353 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); reg 354 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARCSR2_LENGTH, reg 356 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg); reg 358 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, ARCSR5); reg 359 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); reg 360 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); reg 361 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARCSR2_LENGTH, reg 363 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg); reg 370 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR11); reg 371 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time); reg 372 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR11, reg); reg 374 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR18); reg 375 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR18_SIFS, erp->sifs); reg 376 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR18_PIFS, erp->pifs); reg 377 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR18, reg); reg 379 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR19); reg 380 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR19_DIFS, erp->difs); reg 381 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR19_EIFS, erp->eifs); reg 382 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR19, reg); reg 386 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR12); reg 387 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, reg 389 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, reg 391 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR12, reg); reg 399 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 410 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, BBPCSR1); reg 420 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, BBPCSR1_CCK, 0); reg 421 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, BBPCSR1_OFDM, 0); reg 426 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, BBPCSR1_CCK, 2); reg 427 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, BBPCSR1_OFDM, 2); reg 449 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 1); reg 450 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 1); reg 458 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 0); reg 459 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 0); reg 462 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, BBPCSR1, reg); reg 549 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 551 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR11); reg 552 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR11_LONG_RETRY, reg 554 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR11_SHORT_RETRY, reg 556 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR11, reg); reg 565 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 568 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR20); reg 569 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN, reg 571 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP, reg 575 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); reg 576 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR20, reg); reg 578 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR20_AUTOWAKE, 1); reg 579 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR20, reg); reg 581 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR20); reg 582 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); reg 583 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR20, reg); reg 612 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 617 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CNT0); reg 618 drivers/net/wireless/ralink/rt2x00/rt2500pci.c qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR); reg 623 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CNT3); reg 624 drivers/net/wireless/ralink/rt2x00/rt2500pci.c qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA); reg 719 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 723 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); reg 724 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0); reg 725 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); reg 728 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR14); reg 729 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); reg 730 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR14_TBCN, 1); reg 731 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); reg 732 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR14, reg); reg 742 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 746 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); reg 747 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1); reg 748 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); reg 751 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); reg 752 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR0_KICK_TX, 1); reg 753 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); reg 756 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); reg 757 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1); reg 758 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); reg 768 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 774 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); reg 775 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR0_ABORT, 1); reg 776 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); reg 779 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); reg 780 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1); reg 781 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); reg 784 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR14); reg 785 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); reg 786 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR14_TBCN, 0); reg 787 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); reg 788 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR14, reg); reg 845 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 850 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR2); reg 851 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); reg 852 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); reg 853 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); reg 854 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); reg 855 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg); reg 858 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR3); reg 859 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, reg 861 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg); reg 864 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR5); reg 865 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, reg 867 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg); reg 870 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR4); reg 871 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, reg 873 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg); reg 876 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR6); reg 877 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, reg 879 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg); reg 881 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, RXCSR1); reg 882 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); reg 883 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); reg 884 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg); reg 887 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, RXCSR2); reg 888 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, reg 890 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg); reg 897 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 904 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, TIMECSR); reg 905 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TIMECSR_US_COUNT, 33); reg 906 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63); reg 907 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0); reg 908 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg); reg 910 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR9); reg 911 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT, reg 913 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR9, reg); reg 918 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR11); reg 919 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR11_CW_SELECT, 0); reg 920 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR11, reg); reg 922 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR14); reg 923 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); reg 924 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR14_TSF_SYNC, 0); reg 925 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR14_TBCN, 0); reg 926 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR14_TCFP, 0); reg 927 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR14_TATIMW, 0); reg 928 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); reg 929 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0); reg 930 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0); reg 931 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR14, reg); reg 935 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXCSR8); reg 936 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR8_BBP_ID0, 10); reg 937 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR8_BBP_ID0_VALID, 1); reg 938 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR8_BBP_ID1, 11); reg 939 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR8_BBP_ID1_VALID, 1); reg 940 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR8_BBP_ID2, 13); reg 941 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR8_BBP_ID2_VALID, 1); reg 942 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR8_BBP_ID3, 12); reg 943 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, TXCSR8_BBP_ID3_VALID, 1); reg 944 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, TXCSR8, reg); reg 946 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, ARTCSR0); reg 947 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARTCSR0_ACK_CTS_1MBS, 112); reg 948 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARTCSR0_ACK_CTS_2MBS, 56); reg 949 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARTCSR0_ACK_CTS_5_5MBS, 20); reg 950 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARTCSR0_ACK_CTS_11MBS, 10); reg 951 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, ARTCSR0, reg); reg 953 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, ARTCSR1); reg 954 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARTCSR1_ACK_CTS_6MBS, 45); reg 955 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARTCSR1_ACK_CTS_9MBS, 37); reg 956 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARTCSR1_ACK_CTS_12MBS, 33); reg 957 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARTCSR1_ACK_CTS_18MBS, 29); reg 958 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, ARTCSR1, reg); reg 960 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, ARTCSR2); reg 961 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARTCSR2_ACK_CTS_24MBS, 29); reg 962 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARTCSR2_ACK_CTS_36MBS, 25); reg 963 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARTCSR2_ACK_CTS_48MBS, 25); reg 964 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, ARTCSR2_ACK_CTS_54MBS, 25); reg 965 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, ARTCSR2, reg); reg 967 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, RXCSR3); reg 968 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR3_BBP_ID0, 47); /* CCK Signal */ reg 969 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1); reg 970 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR3_BBP_ID1, 51); /* Rssi */ reg 971 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1); reg 972 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR3_BBP_ID2, 42); /* OFDM Rate */ reg 973 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1); reg 974 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR3_BBP_ID3, 51); /* RSSI */ reg 975 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RXCSR3_BBP_ID3_VALID, 1); reg 976 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg); reg 978 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, PCICSR); reg 979 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0); reg 980 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0); reg 981 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, PCICSR_TX_TRESHOLD, 3); reg 982 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, PCICSR_BURST_LENTH, 1); reg 983 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, PCICSR_ENABLE_CLK, 1); reg 984 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, PCICSR_READ_MULTIPLE, 1); reg 985 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, PCICSR_WRITE_INVALID, 1); reg 986 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, PCICSR, reg); reg 999 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, MACCSR2); reg 1000 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, MACCSR2_DELAY, 64); reg 1001 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg); reg 1003 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, RALINKCSR); reg 1004 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17); reg 1005 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 26); reg 1006 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID0, 1); reg 1007 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0); reg 1008 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 26); reg 1009 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID1, 1); reg 1010 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg); reg 1016 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR1); reg 1017 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR1_SOFT_RESET, 1); reg 1018 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR1_BBP_RESET, 0); reg 1019 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR1_HOST_READY, 0); reg 1020 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR1, reg); reg 1022 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR1); reg 1023 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR1_SOFT_RESET, 0); reg 1024 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR1_HOST_READY, 1); reg 1025 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR1, reg); reg 1032 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CNT0); reg 1033 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CNT4); reg 1115 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 1123 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR7); reg 1124 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR7, reg); reg 1133 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR8); reg 1134 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); reg 1135 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); reg 1136 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); reg 1137 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); reg 1138 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR8_RXDONE, mask); reg 1139 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR8, reg); reg 1177 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg, reg2; reg 1185 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, PWRCSR1); reg 1186 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1); reg 1187 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state); reg 1188 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state); reg 1189 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); reg 1190 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); reg 1203 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); reg 1321 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 1327 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR14); reg 1328 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); reg 1329 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR14, reg); reg 1349 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); reg 1350 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR14, reg); reg 1435 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 1443 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR8); reg 1444 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, irq_field, 0); reg 1445 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR8, reg); reg 1453 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 1468 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR8); reg 1469 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0); reg 1470 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0); reg 1471 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0); reg 1472 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR8, reg); reg 1498 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg, mask; reg 1504 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR7); reg 1505 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR7, reg); reg 1507 drivers/net/wireless/ralink/rt2x00/rt2500pci.c if (!reg) reg 1513 drivers/net/wireless/ralink/rt2x00/rt2500pci.c mask = reg; reg 1518 drivers/net/wireless/ralink/rt2x00/rt2500pci.c if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) reg 1521 drivers/net/wireless/ralink/rt2x00/rt2500pci.c if (rt2x00_get_field32(reg, CSR7_RXDONE)) reg 1524 drivers/net/wireless/ralink/rt2x00/rt2500pci.c if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) || reg 1525 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) || reg 1526 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) { reg 1542 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR8); reg 1543 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg |= mask; reg 1544 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, CSR8, reg); reg 1557 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 1561 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR21); reg 1566 drivers/net/wireless/ralink/rt2x00/rt2500pci.c eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ? reg 1621 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 1634 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR0); reg 1636 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_get_field32(reg, CSR0_REVISION)); reg 1933 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 1950 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR); reg 1951 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, GPIOCSR_DIR0, 1); reg 1952 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg); reg 1984 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 1986 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR17); reg 1987 drivers/net/wireless/ralink/rt2x00/rt2500pci.c tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32; reg 1988 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR16); reg 1989 drivers/net/wireless/ralink/rt2x00/rt2500pci.c tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER); reg 1997 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg; reg 1999 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg = rt2x00mmio_register_read(rt2x00dev, CSR15); reg 2000 drivers/net/wireless/ralink/rt2x00/rt2500pci.c return rt2x00_get_field32(reg, CSR15_BEACON_SENT); reg 50 drivers/net/wireless/ralink/rt2x00/rt2500usb.c __le16 reg; reg 53 drivers/net/wireless/ralink/rt2x00/rt2500usb.c ®, sizeof(reg)); reg 54 drivers/net/wireless/ralink/rt2x00/rt2500usb.c return le16_to_cpu(reg); reg 60 drivers/net/wireless/ralink/rt2x00/rt2500usb.c __le16 reg; reg 63 drivers/net/wireless/ralink/rt2x00/rt2500usb.c ®, sizeof(reg), REGISTER_TIMEOUT); reg 64 drivers/net/wireless/ralink/rt2x00/rt2500usb.c return le16_to_cpu(reg); reg 71 drivers/net/wireless/ralink/rt2x00/rt2500usb.c __le16 reg = cpu_to_le16(value); reg 74 drivers/net/wireless/ralink/rt2x00/rt2500usb.c ®, sizeof(reg)); reg 81 drivers/net/wireless/ralink/rt2x00/rt2500usb.c __le16 reg = cpu_to_le16(value); reg 84 drivers/net/wireless/ralink/rt2x00/rt2500usb.c ®, sizeof(reg), REGISTER_TIMEOUT); reg 99 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 *reg) reg 104 drivers/net/wireless/ralink/rt2x00/rt2500usb.c *reg = rt2500usb_register_read_lock(rt2x00dev, offset); reg 105 drivers/net/wireless/ralink/rt2x00/rt2500usb.c if (!rt2x00_get_field16(*reg, field)) reg 111 drivers/net/wireless/ralink/rt2x00/rt2500usb.c offset, *reg); reg 112 drivers/net/wireless/ralink/rt2x00/rt2500usb.c *reg = ~0; reg 125 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg; reg 133 drivers/net/wireless/ralink/rt2x00/rt2500usb.c if (WAIT_FOR_BBP(rt2x00dev, ®)) { reg 134 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = 0; reg 135 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, PHY_CSR7_DATA, value); reg 136 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, PHY_CSR7_REG_ID, word); reg 137 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, PHY_CSR7_READ_CONTROL, 0); reg 139 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write_lock(rt2x00dev, PHY_CSR7, reg); reg 148 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg; reg 161 drivers/net/wireless/ralink/rt2x00/rt2500usb.c if (WAIT_FOR_BBP(rt2x00dev, ®)) { reg 162 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = 0; reg 163 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, PHY_CSR7_REG_ID, word); reg 164 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, PHY_CSR7_READ_CONTROL, 1); reg 166 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write_lock(rt2x00dev, PHY_CSR7, reg); reg 168 drivers/net/wireless/ralink/rt2x00/rt2500usb.c if (WAIT_FOR_BBP(rt2x00dev, ®)) reg 169 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read_lock(rt2x00dev, PHY_CSR7); reg 172 drivers/net/wireless/ralink/rt2x00/rt2500usb.c value = rt2x00_get_field16(reg, PHY_CSR7_DATA); reg 182 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg; reg 190 drivers/net/wireless/ralink/rt2x00/rt2500usb.c if (WAIT_FOR_RF(rt2x00dev, ®)) { reg 191 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = 0; reg 192 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, PHY_CSR9_RF_VALUE, value); reg 193 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write_lock(rt2x00dev, PHY_CSR9, reg); reg 195 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = 0; reg 196 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, PHY_CSR10_RF_VALUE, value >> 16); reg 197 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, PHY_CSR10_RF_NUMBER_OF_BITS, 20); reg 198 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, PHY_CSR10_RF_IF_SELECT, 0); reg 199 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, PHY_CSR10_RF_BUSY, 1); reg 201 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write_lock(rt2x00dev, PHY_CSR10, reg); reg 258 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg; reg 260 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, MAC_CSR19); reg 261 drivers/net/wireless/ralink/rt2x00/rt2500usb.c return rt2x00_get_field16(reg, MAC_CSR19_VAL7); reg 271 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg; reg 273 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(led->rt2x00dev, MAC_CSR20); reg 276 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR20_LINK, enabled); reg 278 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR20_ACTIVITY, enabled); reg 280 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(led->rt2x00dev, MAC_CSR20, reg); reg 289 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg; reg 291 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(led->rt2x00dev, MAC_CSR21); reg 292 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR21_ON_PERIOD, *delay_on); reg 293 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR21_OFF_PERIOD, *delay_off); reg 294 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(led->rt2x00dev, MAC_CSR21, reg); reg 324 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg; reg 345 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR0); reg 346 drivers/net/wireless/ralink/rt2x00/rt2500usb.c curr_cipher = rt2x00_get_field16(reg, TXRX_CSR0_ALGORITHM); reg 347 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg &= mask; reg 349 drivers/net/wireless/ralink/rt2x00/rt2500usb.c if (reg && reg == mask) reg 352 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2x00_get_field16(reg, TXRX_CSR0_KEY_ID); reg 354 drivers/net/wireless/ralink/rt2x00/rt2500usb.c key->hw_key_idx += reg ? ffz(reg) : 0; reg 384 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR0); reg 385 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR0_ALGORITHM, crypto->cipher); reg 386 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER); reg 388 drivers/net/wireless/ralink/rt2x00/rt2500usb.c mask = rt2x00_get_field16(reg, TXRX_CSR0_KEY_ID); reg 393 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR0_KEY_ID, mask); reg 394 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR0, reg); reg 402 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg; reg 410 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR2); reg 411 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR2_DROP_CRC, reg 413 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR2_DROP_PHYSICAL, reg 415 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR2_DROP_CONTROL, reg 417 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR2_DROP_NOT_TO_ME, reg 419 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR2_DROP_TODS, reg 422 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR2_DROP_VERSION_ERROR, 1); reg 423 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR2_DROP_MULTICAST, reg 425 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR2_DROP_BROADCAST, 0); reg 426 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg); reg 435 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg; reg 442 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR20); reg 443 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR20_OFFSET, bcn_preload >> 6); reg 444 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR20_BCN_EXPECT_WINDOW, reg 446 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR20, reg); reg 451 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR18); reg 452 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR18_OFFSET, 0); reg 453 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg); reg 455 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR19); reg 456 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR19_TSF_SYNC, conf->sync); reg 457 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); reg 473 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg; reg 476 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR10); reg 477 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR10_AUTORESPOND_PREAMBLE, reg 479 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR10, reg); reg 487 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR18); reg 488 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR18_INTERVAL, reg 490 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg); reg 629 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg; reg 632 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, MAC_CSR18); reg 633 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR18_DELAY_AFTER_BEACON, reg 635 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR18_BEACONS_BEFORE_WAKEUP, reg 639 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR18_AUTO_WAKE, 0); reg 640 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg); reg 642 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR18_AUTO_WAKE, 1); reg 643 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg); reg 645 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, MAC_CSR18); reg 646 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR18_AUTO_WAKE, 0); reg 647 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg); reg 674 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg; reg 679 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, STA_CSR0); reg 680 drivers/net/wireless/ralink/rt2x00/rt2500usb.c qual->rx_failed = rt2x00_get_field16(reg, STA_CSR0_FCS_ERROR); reg 685 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, STA_CSR3); reg 686 drivers/net/wireless/ralink/rt2x00/rt2500usb.c qual->false_cca = rt2x00_get_field16(reg, STA_CSR3_FALSE_CCA_ERROR); reg 720 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg; reg 724 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR2); reg 725 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR2_DISABLE_RX, 0); reg 726 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg); reg 729 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR19); reg 730 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR19_TSF_COUNT, 1); reg 731 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR19_TBCN, 1); reg 732 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR19_BEACON_GEN, 1); reg 733 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); reg 743 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg; reg 747 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR2); reg 748 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR2_DISABLE_RX, 1); reg 749 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg); reg 752 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR19); reg 753 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR19_TSF_COUNT, 0); reg 754 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR19_TBCN, 0); reg 755 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR19_BEACON_GEN, 0); reg 756 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); reg 768 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg; reg 775 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR2); reg 776 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR2_DISABLE_RX, 1); reg 777 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg); reg 782 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, MAC_CSR1); reg 783 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR1_SOFT_RESET, 1); reg 784 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR1_BBP_RESET, 1); reg 785 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR1_HOST_READY, 0); reg 786 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg); reg 788 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, MAC_CSR1); reg 789 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR1_SOFT_RESET, 0); reg 790 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR1_BBP_RESET, 0); reg 791 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR1_HOST_READY, 0); reg 792 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg); reg 794 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR5); reg 795 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR5_BBP_ID0, 13); reg 796 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR5_BBP_ID0_VALID, 1); reg 797 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR5_BBP_ID1, 12); reg 798 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR5_BBP_ID1_VALID, 1); reg 799 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR5, reg); reg 801 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR6); reg 802 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR6_BBP_ID0, 10); reg 803 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR6_BBP_ID0_VALID, 1); reg 804 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR6_BBP_ID1, 11); reg 805 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR6_BBP_ID1_VALID, 1); reg 806 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR6, reg); reg 808 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR7); reg 809 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR7_BBP_ID0, 7); reg 810 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR7_BBP_ID0_VALID, 1); reg 811 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR7_BBP_ID1, 6); reg 812 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR7_BBP_ID1_VALID, 1); reg 813 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR7, reg); reg 815 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR8); reg 816 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR8_BBP_ID0, 5); reg 817 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR8_BBP_ID0_VALID, 1); reg 818 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR8_BBP_ID1, 0); reg 819 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR8_BBP_ID1_VALID, 0); reg 820 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR8, reg); reg 822 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR19); reg 823 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR19_TSF_COUNT, 0); reg 824 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR19_TSF_SYNC, 0); reg 825 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR19_TBCN, 0); reg 826 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR19_BEACON_GEN, 0); reg 827 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); reg 835 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, MAC_CSR1); reg 836 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR1_SOFT_RESET, 0); reg 837 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR1_BBP_RESET, 0); reg 838 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR1_HOST_READY, 1); reg 839 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg); reg 842 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, PHY_CSR2); reg 843 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, PHY_CSR2_LNA, 0); reg 845 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = 0; reg 846 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, PHY_CSR2_LNA, 1); reg 847 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, PHY_CSR2_LNA_MODE, 3); reg 849 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, PHY_CSR2, reg); reg 856 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, MAC_CSR8); reg 857 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR8_MAX_FRAME_UNIT, reg 859 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, MAC_CSR8, reg); reg 861 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR0); reg 862 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR0_ALGORITHM, CIPHER_NONE); reg 863 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER); reg 864 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR0_KEY_ID, 0); reg 865 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR0, reg); reg 867 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, MAC_CSR18); reg 868 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR18_DELAY_AFTER_BEACON, 90); reg 869 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg); reg 871 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, PHY_CSR4); reg 872 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, PHY_CSR4_LOW_RF_LE, 1); reg 873 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, PHY_CSR4, reg); reg 875 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR1); reg 876 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR1_AUTO_SEQUENCE, 1); reg 877 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR1, reg); reg 984 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg; reg 993 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = 0; reg 994 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR17_BBP_DESIRE_STATE, state); reg 995 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR17_RF_DESIRE_STATE, state); reg 996 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR17_PUT_TO_SLEEP, put_to_sleep); reg 997 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg); reg 998 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR17_SET_STATE, 1); reg 999 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg); reg 1012 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg); reg 1126 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg, reg0; reg 1132 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, TXRX_CSR19); reg 1133 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR19_BEACON_GEN, 0); reg 1134 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); reg 1181 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR19_TSF_COUNT, 1); reg 1182 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR19_TBCN, 1); reg 1183 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg0 = reg; reg 1184 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR19_BEACON_GEN, 1); reg 1192 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); reg 1194 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); reg 1196 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); reg 1427 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg; reg 1440 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, MAC_CSR0); reg 1441 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_chip(rt2x00dev, RT2570, value, reg); reg 1443 drivers/net/wireless/ralink/rt2x00/rt2500usb.c if (((reg & 0xfff0) != 0) || ((reg & 0x0000000f) == 0)) { reg 1748 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg; reg 1765 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg = rt2500usb_register_read(rt2x00dev, MAC_CSR19); reg 1766 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, MAC_CSR19_DIR0, 0); reg 1767 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2500usb_register_write(rt2x00dev, MAC_CSR19, reg); reg 84 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 92 drivers/net/wireless/ralink/rt2x00/rt2800lib.c if (WAIT_FOR_BBP(rt2x00dev, ®)) { reg 93 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = 0; reg 94 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); reg 95 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); reg 96 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); reg 97 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); reg 98 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); reg 100 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); reg 108 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 121 drivers/net/wireless/ralink/rt2x00/rt2800lib.c if (WAIT_FOR_BBP(rt2x00dev, ®)) { reg 122 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = 0; reg 123 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); reg 124 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); reg 125 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); reg 126 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); reg 128 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); reg 130 drivers/net/wireless/ralink/rt2x00/rt2800lib.c WAIT_FOR_BBP(rt2x00dev, ®); reg 133 drivers/net/wireless/ralink/rt2x00/rt2800lib.c value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); reg 143 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 153 drivers/net/wireless/ralink/rt2x00/rt2800lib.c if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { reg 154 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = 0; reg 155 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value); reg 156 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, reg 158 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 1); reg 159 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); reg 161 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); reg 166 drivers/net/wireless/ralink/rt2x00/rt2800lib.c if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { reg 167 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = 0; reg 168 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); reg 169 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); reg 170 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); reg 171 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); reg 173 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); reg 182 drivers/net/wireless/ralink/rt2x00/rt2800lib.c const unsigned int reg, const u8 value) reg 184 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value); reg 188 drivers/net/wireless/ralink/rt2x00/rt2800lib.c const unsigned int reg, const u8 value) reg 190 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value); reg 191 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value); reg 195 drivers/net/wireless/ralink/rt2x00/rt2800lib.c const unsigned int reg, const u8 value) reg 197 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value); reg 198 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value); reg 204 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 219 drivers/net/wireless/ralink/rt2x00/rt2800lib.c if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { reg 220 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = 0; reg 221 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, reg 223 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 0); reg 224 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); reg 226 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); reg 228 drivers/net/wireless/ralink/rt2x00/rt2800lib.c WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®); reg 231 drivers/net/wireless/ralink/rt2x00/rt2800lib.c value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620); reg 235 drivers/net/wireless/ralink/rt2x00/rt2800lib.c if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { reg 236 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = 0; reg 237 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); reg 238 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); reg 239 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); reg 241 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); reg 243 drivers/net/wireless/ralink/rt2x00/rt2800lib.c WAIT_FOR_RFCSR(rt2x00dev, ®); reg 246 drivers/net/wireless/ralink/rt2x00/rt2800lib.c value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); reg 256 drivers/net/wireless/ralink/rt2x00/rt2800lib.c const unsigned int reg) reg 258 drivers/net/wireless/ralink/rt2x00/rt2800lib.c return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6))); reg 264 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 272 drivers/net/wireless/ralink/rt2x00/rt2800lib.c if (WAIT_FOR_RF(rt2x00dev, ®)) { reg 273 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = 0; reg 274 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); reg 275 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); reg 276 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); reg 277 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); reg 279 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); reg 437 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 440 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); reg 441 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); reg 442 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); reg 443 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WLAN_CLK_EN, 0); reg 444 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WLAN_EN, 1); reg 445 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); reg 455 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, CMB_CTRL); reg 456 drivers/net/wireless/ralink/rt2x00/rt2800lib.c if (rt2x00_get_field32(reg, PLL_LD) && reg 457 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_get_field32(reg, XTAL_RDY)) reg 478 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); reg 479 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); reg 480 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WLAN_CLK_EN, 1); reg 481 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WLAN_RESET, 1); reg 482 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); reg 484 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WLAN_RESET, 0); reg 485 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); reg 497 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 511 drivers/net/wireless/ralink/rt2x00/rt2800lib.c if (WAIT_FOR_MCU(rt2x00dev, ®)) { reg 512 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); reg 513 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); reg 514 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); reg 515 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); reg 516 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); reg 518 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = 0; reg 519 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); reg 520 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); reg 530 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 533 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, MAC_CSR0); reg 534 drivers/net/wireless/ralink/rt2x00/rt2800lib.c if (reg && reg != ~0) reg 547 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 554 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); reg 555 drivers/net/wireless/ralink/rt2x00/rt2800lib.c if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && reg 556 drivers/net/wireless/ralink/rt2x00/rt2800lib.c !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) reg 562 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); reg 569 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 571 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); reg 572 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); reg 573 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); reg 574 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); reg 575 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); reg 576 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); reg 577 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); reg 696 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 722 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, AUX_CTRL); reg 723 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); reg 724 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); reg 725 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, AUX_CTRL, reg); reg 741 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL); reg 742 drivers/net/wireless/ralink/rt2x00/rt2800lib.c if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) reg 955 drivers/net/wireless/ralink/rt2x00/rt2800lib.c static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg) reg 970 drivers/net/wireless/ralink/rt2x00/rt2800lib.c wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID); reg 971 drivers/net/wireless/ralink/rt2x00/rt2800lib.c ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED); reg 972 drivers/net/wireless/ralink/rt2x00/rt2800lib.c pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE); reg 973 drivers/net/wireless/ralink/rt2x00/rt2800lib.c is_agg = rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE); reg 1102 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 1106 drivers/net/wireless/ralink/rt2x00/rt2800lib.c while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, ®)) { reg 1111 drivers/net/wireless/ralink/rt2x00/rt2800lib.c qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE); reg 1129 drivers/net/wireless/ralink/rt2x00/rt2800lib.c match = rt2800_txdone_entry_check(entry, reg); reg 1130 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match); reg 1293 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u64 off, reg = 0; reg 1304 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg |= off << (8 * bcn_num); reg 1308 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); reg 1309 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); reg 1326 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 orig_reg, reg; reg 1333 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); reg 1334 drivers/net/wireless/ralink/rt2x00/rt2800lib.c orig_reg = reg; reg 1335 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); reg 1336 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); reg 1417 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 orig_reg, reg; reg 1424 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = orig_reg; reg 1425 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); reg 1426 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); reg 1493 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 1496 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); reg 1497 drivers/net/wireless/ralink/rt2x00/rt2800lib.c return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); reg 1499 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); reg 1500 drivers/net/wireless/ralink/rt2x00/rt2800lib.c return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); reg 1520 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 1524 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(led->rt2x00dev, LED_CFG); reg 1527 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); reg 1531 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LED_CFG_G_LED_MODE, reg 1534 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, reg 1537 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LED_CFG_R_LED_MODE, reg 1541 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(led->rt2x00dev, LED_CFG, reg); reg 1607 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 1613 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, offset); reg 1614 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); reg 1615 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, reg 1617 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, offset, reg); reg 1626 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 1631 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, offset); reg 1632 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, reg 1639 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, reg 1641 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, reg 1643 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); reg 1644 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, offset, reg); reg 1647 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, offset); reg 1648 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); reg 1649 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); reg 1650 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); reg 1651 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); reg 1652 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, offset, reg); reg 1680 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 1709 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, offset); reg 1710 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, field, reg 1712 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, offset, reg); reg 1766 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 1775 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); reg 1776 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); reg 1777 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); reg 1881 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 1889 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG); reg 1890 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, reg 1892 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, reg 1894 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, reg 1896 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); reg 1897 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); reg 1898 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, reg 1900 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); reg 1901 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); reg 1902 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, reg 1904 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, reg 1906 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, reg 1908 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, reg 1910 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, reg 1912 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, reg 1914 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); reg 1915 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, reg 1917 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, reg 1919 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); reg 1926 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 1933 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); reg 1934 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); reg 1935 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); reg 1941 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); reg 1942 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); reg 1943 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); reg 1944 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); reg 1945 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); reg 1946 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); reg 1948 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); reg 1949 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); reg 1950 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); reg 1951 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); reg 1952 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); reg 1953 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); reg 1969 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = le32_to_cpu(conf->mac[1]); reg 1970 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); reg 1971 drivers/net/wireless/ralink/rt2x00/rt2800lib.c conf->mac[1] = cpu_to_le32(reg); reg 1980 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = le32_to_cpu(conf->bssid[1]); reg 1981 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); reg 1982 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); reg 1983 drivers/net/wireless/ralink/rt2x00/rt2800lib.c conf->bssid[1] = cpu_to_le32(reg); reg 2000 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 2067 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); reg 2068 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); reg 2069 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); reg 2070 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); reg 2072 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); reg 2073 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); reg 2074 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); reg 2075 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); reg 2077 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); reg 2078 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); reg 2079 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); reg 2080 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); reg 2082 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); reg 2083 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); reg 2084 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); reg 2085 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); reg 2091 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 2094 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); reg 2095 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, reg 2097 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); reg 2101 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); reg 2102 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, reg 2104 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); reg 2114 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); reg 2115 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, reg 2117 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); reg 2119 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); reg 2120 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); reg 2121 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); reg 2125 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); reg 2126 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, reg 2128 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); reg 2138 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 2142 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); reg 2144 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_SWITCH_0, 1); reg 2145 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_SWITCH_1, 1); reg 2147 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_SWITCH_0, 0); reg 2148 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_SWITCH_1, 0); reg 2150 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); reg 2152 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, LED_CFG); reg 2153 drivers/net/wireless/ralink/rt2x00/rt2800lib.c led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; reg 2154 drivers/net/wireless/ralink/rt2x00/rt2800lib.c led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; reg 2155 drivers/net/wireless/ralink/rt2x00/rt2800lib.c if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || reg 2156 drivers/net/wireless/ralink/rt2x00/rt2800lib.c led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { reg 2160 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); reg 2161 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); reg 2162 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, LED_CFG, reg); reg 2173 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 2178 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, E2PROM_CSR); reg 2179 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); reg 2180 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); reg 2185 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); reg 2186 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); reg 2187 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); reg 2188 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); reg 2501 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 2653 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); reg 2654 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); reg 2656 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); reg 2658 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); reg 2659 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); reg 3360 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 3367 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, LDO_CFG0); reg 3368 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, reg 3370 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, LDO_CFG0, reg); reg 3793 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 3806 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0); reg 3807 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, power_level); reg 3808 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, power_level); reg 3809 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, max_power); reg 3810 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, max_power); reg 3817 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, target_power); reg 3818 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, target_power); reg 3820 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg); reg 3822 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); reg 3823 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0); reg 3824 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); reg 3870 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u8 chain, reg; reg 3873 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_bbp_read(rt2x00dev, 27); reg 3874 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); reg 3875 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_bbp_write(rt2x00dev, 27, reg); reg 4021 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 4199 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG); reg 4200 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); reg 4201 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); reg 4202 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); reg 4203 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); reg 4270 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = 0x1c + (2 * rt2x00dev->lna_gain); reg 4272 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); reg 4274 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); reg 4278 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); reg 4284 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); reg 4286 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); reg 4288 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); reg 4296 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); reg 4297 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); reg 4299 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); reg 4300 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); reg 4303 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); reg 4304 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); reg 4307 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); reg 4311 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = 0x1c + 2 * rt2x00dev->lna_gain; reg 4313 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); reg 4315 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); reg 4328 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = 0x2e + rt2x00dev->lna_gain; reg 4330 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3); reg 4332 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); reg 4338 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = 0x10; reg 4342 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg |= 0x5; reg 4344 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg |= 0xa; reg 4348 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_bbp_write(rt2x00dev, 196, reg); reg 4355 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain; reg 4356 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); reg 4386 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA); reg 4387 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA); reg 4388 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); reg 5044 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg, pwreg; reg 5135 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1); reg 5136 drivers/net/wireless/ralink/rt2x00/rt2800lib.c t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS); reg 5140 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2); reg 5141 drivers/net/wireless/ralink/rt2x00/rt2800lib.c t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7); reg 5147 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3); reg 5148 drivers/net/wireless/ralink/rt2x00/rt2800lib.c t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14); reg 5154 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4); reg 5155 drivers/net/wireless/ralink/rt2x00/rt2800lib.c t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6); reg 5179 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg, offset; reg 5247 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, offset); reg 5264 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); reg 5275 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); reg 5286 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); reg 5297 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); reg 5314 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); reg 5325 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); reg 5336 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); reg 5347 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); reg 5349 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, offset, reg); reg 5511 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 5513 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); reg 5514 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, reg 5516 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, reg 5518 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); reg 5527 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 5532 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); reg 5533 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); reg 5534 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, reg 5536 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); reg 5537 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); reg 5541 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); reg 5542 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); reg 5543 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); reg 5544 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); reg 5545 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); reg 5579 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 5584 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); reg 5585 drivers/net/wireless/ralink/rt2x00/rt2800lib.c qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); reg 5704 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 5720 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); reg 5721 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); reg 5722 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); reg 5723 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); reg 5724 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); reg 5725 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); reg 5726 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); reg 5727 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); reg 5731 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); reg 5732 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); reg 5733 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); reg 5734 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); reg 5737 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); reg 5738 drivers/net/wireless/ralink/rt2x00/rt2800lib.c if (rt2x00_get_field32(reg, WLAN_EN) == 1) { reg 5739 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); reg 5740 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); reg 5743 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, CMB_CTRL); reg 5744 drivers/net/wireless/ralink/rt2x00/rt2800lib.c if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { reg 5745 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LDO0_EN, 1); reg 5746 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LDO_BGSEL, 3); reg 5747 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, CMB_CTRL, reg); reg 5750 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, OSC_CTRL); reg 5751 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, OSC_ROSC_EN, 1); reg 5752 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, OSC_CAL_REQ, 1); reg 5753 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); reg 5754 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, OSC_CTRL, reg); reg 5756 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, COEX_CFG0); reg 5757 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); reg 5758 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, COEX_CFG0, reg); reg 5760 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, COEX_CFG2); reg 5761 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); reg 5762 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); reg 5763 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); reg 5764 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); reg 5765 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, COEX_CFG2, reg); reg 5767 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, PLL_CTRL); reg 5768 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, PLL_CONTROL, 1); reg 5769 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, PLL_CTRL, reg); reg 5865 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); reg 5866 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); reg 5867 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); reg 5873 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG); reg 5874 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); reg 5875 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); reg 5876 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); reg 5877 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); reg 5878 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); reg 5879 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); reg 5880 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); reg 5881 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); reg 5882 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); reg 5884 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG); reg 5885 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); reg 5886 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); reg 5887 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); reg 5888 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); reg 5890 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); reg 5891 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); reg 5901 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu); reg 5902 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); reg 5903 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); reg 5904 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); reg 5906 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, LED_CFG); reg 5907 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); reg 5908 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); reg 5909 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); reg 5910 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); reg 5911 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); reg 5912 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); reg 5913 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); reg 5914 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, LED_CFG, reg); reg 5918 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); reg 5919 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2); reg 5920 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2); reg 5921 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); reg 5922 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); reg 5923 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); reg 5924 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); reg 5925 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); reg 5927 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); reg 5928 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); reg 5929 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); reg 5930 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); reg 5931 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); reg 5932 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0); reg 5933 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); reg 5934 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); reg 5935 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); reg 5937 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); reg 5938 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); reg 5939 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); reg 5940 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); reg 5941 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); reg 5942 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); reg 5943 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); reg 5944 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); reg 5945 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); reg 5946 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); reg 5947 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); reg 5948 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); reg 5950 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); reg 5951 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); reg 5952 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); reg 5953 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); reg 5954 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); reg 5955 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); reg 5956 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); reg 5957 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); reg 5958 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); reg 5959 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); reg 5960 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); reg 5961 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); reg 5963 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); reg 5964 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); reg 5965 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); reg 5966 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); reg 5967 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0); reg 5968 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); reg 5969 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); reg 5970 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); reg 5971 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); reg 5972 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); reg 5973 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); reg 5974 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); reg 5976 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); reg 5977 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); reg 5978 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); reg 5979 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); reg 5980 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0); reg 5981 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); reg 5982 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); reg 5983 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); reg 5984 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); reg 5985 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); reg 5986 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); reg 5987 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); reg 5989 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); reg 5990 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); reg 5991 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); reg 5992 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); reg 5993 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0); reg 5994 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); reg 5995 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); reg 5996 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); reg 5997 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); reg 5998 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); reg 5999 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); reg 6000 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); reg 6002 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); reg 6003 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); reg 6004 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); reg 6005 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); reg 6006 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0); reg 6007 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); reg 6008 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); reg 6009 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); reg 6010 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); reg 6011 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); reg 6012 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); reg 6013 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); reg 6018 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); reg 6019 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); reg 6020 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); reg 6021 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); reg 6022 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); reg 6023 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); reg 6024 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); reg 6025 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); reg 6026 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); reg 6027 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); reg 6028 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); reg 6035 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG); reg 6036 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); reg 6037 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); reg 6038 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); reg 6039 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); reg 6040 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); reg 6041 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); reg 6042 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); reg 6043 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); reg 6044 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); reg 6045 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); reg 6046 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); reg 6048 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; reg 6049 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); reg 6056 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); reg 6057 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7); reg 6058 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, reg 6060 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1); reg 6061 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); reg 6072 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); reg 6073 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); reg 6074 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); reg 6075 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); reg 6076 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); reg 6077 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); reg 6078 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); reg 6109 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); reg 6110 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); reg 6111 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); reg 6113 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); reg 6114 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); reg 6115 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); reg 6118 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0); reg 6119 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); reg 6120 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); reg 6121 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); reg 6122 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); reg 6123 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); reg 6124 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); reg 6125 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); reg 6126 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); reg 6127 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); reg 6129 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1); reg 6130 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); reg 6131 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); reg 6132 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); reg 6133 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); reg 6134 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); reg 6135 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); reg 6136 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); reg 6137 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); reg 6138 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); reg 6140 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0); reg 6141 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); reg 6142 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); reg 6143 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); reg 6144 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); reg 6145 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); reg 6146 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); reg 6147 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); reg 6148 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); reg 6149 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); reg 6151 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1); reg 6152 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); reg 6153 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); reg 6154 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); reg 6155 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); reg 6156 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); reg 6161 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE); reg 6162 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); reg 6163 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); reg 6164 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); reg 6171 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); reg 6172 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1); reg 6173 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2); reg 6174 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0); reg 6175 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1); reg 6176 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2); reg 6181 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG); reg 6182 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); reg 6183 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); reg 6188 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG); reg 6189 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); reg 6190 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); reg 6191 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); reg 6192 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); reg 6193 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); reg 6194 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); reg 6202 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 6205 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); reg 6206 drivers/net/wireless/ralink/rt2x00/rt2800lib.c if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) reg 6797 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 6799 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); reg 6800 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); reg 6801 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); reg 6802 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); reg 6803 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); reg 6805 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); reg 6807 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); reg 6808 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); reg 6904 drivers/net/wireless/ralink/rt2x00/rt2800lib.c const u8 reg, const u8 value) reg 6906 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_bbp_write(rt2x00dev, 195, reg); reg 6911 drivers/net/wireless/ralink/rt2x00/rt2800lib.c const u8 reg, const u8 value) reg 6913 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_bbp_write(rt2x00dev, 158, reg); reg 6917 drivers/net/wireless/ralink/rt2x00/rt2800lib.c static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg) reg 6919 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_bbp_write(rt2x00dev, 158, reg); reg 7193 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 7195 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, OPT_14_CSR); reg 7196 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); reg 7197 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); reg 7433 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u8 reg; reg 7437 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_bbp_read(rt2x00dev, 138); reg 7440 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field8(®, BBP138_RX_ADC1, 0); reg 7442 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field8(®, BBP138_TX_DAC1, 1); reg 7443 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_bbp_write(rt2x00dev, 138, reg); reg 7445 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_rfcsr_read(rt2x00dev, 38); reg 7446 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); reg 7447 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_rfcsr_write(rt2x00dev, 38, reg); reg 7449 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_rfcsr_read(rt2x00dev, 39); reg 7450 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); reg 7451 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_rfcsr_write(rt2x00dev, 39, reg); reg 7455 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_rfcsr_read(rt2x00dev, 30); reg 7456 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); reg 7457 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_rfcsr_write(rt2x00dev, 30, reg); reg 7502 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 7528 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, LDO_CFG0); reg 7529 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); reg 7530 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); reg 7531 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, LDO_CFG0, reg); reg 7540 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, LDO_CFG0); reg 7541 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); reg 7546 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); reg 7548 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); reg 7550 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, LDO_CFG0, reg); reg 7552 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); reg 7553 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_SWITCH_5, 0); reg 7554 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); reg 7730 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 7767 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); reg 7768 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_SWITCH_5, 0); reg 7769 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); reg 7783 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 7823 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, LDO_CFG0); reg 7824 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); reg 7825 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); reg 7826 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, LDO_CFG0, reg); reg 7828 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, LDO_CFG0); reg 7829 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); reg 7830 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); reg 7831 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, LDO_CFG0, reg); reg 7888 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 7892 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); reg 7893 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_SWITCH_4, 0); reg 7894 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_SWITCH_7, 0); reg 7895 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); reg 7943 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, LDO_CFG0); reg 7944 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); reg 7945 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); reg 7946 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, LDO_CFG0, reg); reg 7948 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, LDO_CFG0); reg 7949 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); reg 7950 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, LDO_CFG0, reg); reg 9047 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 9097 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); reg 9098 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); reg 9099 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); reg 9100 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); reg 9104 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); reg 9105 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); reg 9106 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); reg 9107 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); reg 9108 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); reg 9110 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); reg 9111 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); reg 9112 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); reg 9113 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); reg 9136 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 9143 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); reg 9144 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); reg 9145 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); reg 9146 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); reg 9152 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 9160 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg); reg 9161 drivers/net/wireless/ralink/rt2x00/rt2800lib.c return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); reg 9167 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 9189 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg); reg 9190 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); reg 9191 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); reg 9192 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); reg 9193 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); reg 9196 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); reg 9198 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg); reg 9200 drivers/net/wireless/ralink/rt2x00/rt2800lib.c *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); reg 9201 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg); reg 9202 drivers/net/wireless/ralink/rt2x00/rt2800lib.c *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); reg 9203 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg); reg 9204 drivers/net/wireless/ralink/rt2x00/rt2800lib.c *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); reg 9205 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg); reg 9206 drivers/net/wireless/ralink/rt2x00/rt2800lib.c *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); reg 9944 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 10056 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX); reg 10057 drivers/net/wireless/ralink/rt2x00/rt2800lib.c if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { reg 10193 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 10198 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290); reg 10200 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, MAC_CSR0); reg 10202 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); reg 10203 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); reg 10240 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 10261 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); reg 10262 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); reg 10263 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); reg 10340 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 10343 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); reg 10344 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); reg 10345 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); reg 10347 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); reg 10348 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); reg 10349 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); reg 10351 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); reg 10352 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); reg 10353 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); reg 10355 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); reg 10356 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); reg 10357 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); reg 10359 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); reg 10360 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); reg 10361 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); reg 10363 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); reg 10364 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); reg 10365 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); reg 10367 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); reg 10368 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); reg 10369 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); reg 10383 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 10410 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, offset); reg 10411 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, field, queue->txop); reg 10412 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, offset, reg); reg 10418 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG); reg 10419 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, field, queue->aifs); reg 10420 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); reg 10422 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG); reg 10423 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, field, queue->cw_min); reg 10424 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); reg 10426 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG); reg 10427 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, field, queue->cw_max); reg 10428 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); reg 10433 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, offset); reg 10434 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); reg 10435 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); reg 10436 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); reg 10437 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); reg 10438 drivers/net/wireless/ralink/rt2x00/rt2800lib.c rt2800_register_write(rt2x00dev, offset, reg); reg 10448 drivers/net/wireless/ralink/rt2x00/rt2800lib.c u32 reg; reg 10450 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1); reg 10451 drivers/net/wireless/ralink/rt2x00/rt2800lib.c tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; reg 10452 drivers/net/wireless/ralink/rt2x00/rt2800lib.c reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0); reg 10453 drivers/net/wireless/ralink/rt2x00/rt2800lib.c tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); reg 59 drivers/net/wireless/ralink/rt2x00/rt2800lib.h const struct rt2x00_field32 field, u32 *reg); reg 127 drivers/net/wireless/ralink/rt2x00/rt2800lib.h u32 *reg) reg 131 drivers/net/wireless/ralink/rt2x00/rt2800lib.h return rt2800ops->regbusy_read(rt2x00dev, offset, field, reg); reg 200 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c u32 reg; reg 207 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); reg 208 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, irq_field, 1); reg 209 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); reg 226 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c u32 reg; reg 238 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG); reg 239 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, reg 241 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg); reg 243 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG); reg 244 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, reg 246 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg); reg 325 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c u32 reg, mask; reg 328 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR); reg 329 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); reg 331 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c if (!reg) reg 342 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c mask = ~reg; reg 344 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) { reg 351 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT)) reg 354 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT)) reg 357 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE)) reg 360 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP)) reg 368 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); reg 369 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c reg &= mask; reg 370 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); reg 380 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c u32 reg; reg 388 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR); reg 389 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); reg 393 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c reg = 0; reg 395 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, 1); reg 396 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, INT_MASK_CSR_TBTT, 1); reg 397 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, 1); reg 398 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, 1); reg 399 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, 1); reg 401 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); reg 423 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c u32 reg; reg 427 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c reg = rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL); reg 428 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); reg 429 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg); reg 432 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG); reg 433 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1); reg 434 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1); reg 435 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1); reg 436 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg); reg 438 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c reg = rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN); reg 439 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 1); reg 440 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg); reg 526 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c u32 reg; reg 530 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c reg = rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL); reg 531 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); reg 532 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg); reg 535 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG); reg 536 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); reg 537 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); reg 538 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); reg 539 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg); reg 541 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c reg = rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN); reg 542 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 0); reg 543 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg); reg 726 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c u32 reg; reg 731 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c reg = rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX); reg 732 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1); reg 733 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1); reg 734 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1); reg 735 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1); reg 736 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1); reg 737 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1); reg 738 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1); reg 739 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00mmio_register_write(rt2x00dev, WPDMA_RST_IDX, reg); reg 752 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c reg = rt2x00mmio_register_read(rt2x00dev, AUX_CTRL); reg 753 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); reg 754 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); reg 755 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00mmio_register_write(rt2x00dev, AUX_CTRL, reg); reg 760 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c reg = 0; reg 761 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1); reg 762 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1); reg 763 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg); reg 52 drivers/net/wireless/ralink/rt2x00/rt2800pci.c u32 reg; reg 61 drivers/net/wireless/ralink/rt2x00/rt2800pci.c reg = rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID); reg 63 drivers/net/wireless/ralink/rt2x00/rt2800pci.c if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) || reg 64 drivers/net/wireless/ralink/rt2x00/rt2800pci.c (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) || reg 65 drivers/net/wireless/ralink/rt2x00/rt2800pci.c (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) || reg 66 drivers/net/wireless/ralink/rt2x00/rt2800pci.c (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token)) reg 82 drivers/net/wireless/ralink/rt2x00/rt2800pci.c u32 reg; reg 84 drivers/net/wireless/ralink/rt2x00/rt2800pci.c reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR); reg 86 drivers/net/wireless/ralink/rt2x00/rt2800pci.c eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); reg 87 drivers/net/wireless/ralink/rt2x00/rt2800pci.c eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); reg 89 drivers/net/wireless/ralink/rt2x00/rt2800pci.c !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK); reg 91 drivers/net/wireless/ralink/rt2x00/rt2800pci.c !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT); reg 97 drivers/net/wireless/ralink/rt2x00/rt2800pci.c u32 reg = 0; reg 99 drivers/net/wireless/ralink/rt2x00/rt2800pci.c rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in); reg 100 drivers/net/wireless/ralink/rt2x00/rt2800pci.c rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out); reg 101 drivers/net/wireless/ralink/rt2x00/rt2800pci.c rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, reg 103 drivers/net/wireless/ralink/rt2x00/rt2800pci.c rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT, reg 106 drivers/net/wireless/ralink/rt2x00/rt2800pci.c rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg); reg 112 drivers/net/wireless/ralink/rt2x00/rt2800pci.c u32 reg; reg 114 drivers/net/wireless/ralink/rt2x00/rt2800pci.c reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR); reg 119 drivers/net/wireless/ralink/rt2x00/rt2800pci.c switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE)) reg 169 drivers/net/wireless/ralink/rt2x00/rt2800pci.c u32 reg; reg 174 drivers/net/wireless/ralink/rt2x00/rt2800pci.c reg = 0; reg 175 drivers/net/wireless/ralink/rt2x00/rt2800pci.c rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1); reg 176 drivers/net/wireless/ralink/rt2x00/rt2800pci.c rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg); reg 42 drivers/net/wireless/ralink/rt2x00/rt2800soc.c u32 reg; reg 47 drivers/net/wireless/ralink/rt2x00/rt2800soc.c reg = 0; reg 49 drivers/net/wireless/ralink/rt2x00/rt2800soc.c rt2x00_set_field32(®, TX_PIN_CFG_RFTR_EN, 1); reg 51 drivers/net/wireless/ralink/rt2x00/rt2800soc.c rt2x00mmio_register_write(rt2x00dev, TX_PIN_CFG, reg); reg 49 drivers/net/wireless/ralink/rt2x00/rt2800usb.c u32 reg; reg 53 drivers/net/wireless/ralink/rt2x00/rt2800usb.c reg = rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL); reg 54 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); reg 55 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg); reg 58 drivers/net/wireless/ralink/rt2x00/rt2800usb.c reg = rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG); reg 59 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1); reg 60 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1); reg 61 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1); reg 62 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg); reg 72 drivers/net/wireless/ralink/rt2x00/rt2800usb.c u32 reg; reg 76 drivers/net/wireless/ralink/rt2x00/rt2800usb.c reg = rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL); reg 77 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); reg 78 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg); reg 81 drivers/net/wireless/ralink/rt2x00/rt2800usb.c reg = rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG); reg 82 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); reg 83 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); reg 84 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); reg 85 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg); reg 178 drivers/net/wireless/ralink/rt2x00/rt2800usb.c __le32 *reg; reg 182 drivers/net/wireless/ralink/rt2x00/rt2800usb.c reg = kmalloc(sizeof(*reg), GFP_KERNEL); reg 183 drivers/net/wireless/ralink/rt2x00/rt2800usb.c if (reg == NULL) reg 192 drivers/net/wireless/ralink/rt2x00/rt2800usb.c USB_MODE_AUTORUN, reg, sizeof(*reg), reg 194 drivers/net/wireless/ralink/rt2x00/rt2800usb.c fw_mode = le32_to_cpu(*reg); reg 195 drivers/net/wireless/ralink/rt2x00/rt2800usb.c kfree(reg); reg 272 drivers/net/wireless/ralink/rt2x00/rt2800usb.c u32 reg; reg 280 drivers/net/wireless/ralink/rt2x00/rt2800usb.c reg = rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL); reg 281 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000); reg 283 drivers/net/wireless/ralink/rt2x00/rt2800usb.c reg = 0; reg 284 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1); reg 285 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1); reg 286 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg); reg 298 drivers/net/wireless/ralink/rt2x00/rt2800usb.c u32 reg = 0; reg 303 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00_set_field32(®, USB_DMA_CFG_PHY_CLEAR, 0); reg 304 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00_set_field32(®, USB_DMA_CFG_RX_BULK_AGG_EN, 0); reg 305 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00_set_field32(®, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128); reg 310 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00_set_field32(®, USB_DMA_CFG_RX_BULK_AGG_LIMIT, reg 313 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00_set_field32(®, USB_DMA_CFG_RX_BULK_EN, 1); reg 314 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00_set_field32(®, USB_DMA_CFG_TX_BULK_EN, 1); reg 315 drivers/net/wireless/ralink/rt2x00/rt2800usb.c rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg); reg 29 drivers/net/wireless/ralink/rt2x00/rt2x00debug.h struct reg##__name { \ reg 27 drivers/net/wireless/ralink/rt2x00/rt2x00mmio.c u32 *reg) reg 35 drivers/net/wireless/ralink/rt2x00/rt2x00mmio.c *reg = rt2x00mmio_register_read(rt2x00dev, offset); reg 36 drivers/net/wireless/ralink/rt2x00/rt2x00mmio.c if (!rt2x00_get_field32(*reg, field)) reg 42 drivers/net/wireless/ralink/rt2x00/rt2x00mmio.c "offset=0x%.08x, value=0x%.08x\n", __func__, offset, *reg); reg 43 drivers/net/wireless/ralink/rt2x00/rt2x00mmio.c *reg = ~0; reg 65 drivers/net/wireless/ralink/rt2x00/rt2x00mmio.h u32 *reg); reg 145 drivers/net/wireless/ralink/rt2x00/rt2x00usb.c u32 *reg) reg 153 drivers/net/wireless/ralink/rt2x00/rt2x00usb.c *reg = rt2x00usb_register_read_lock(rt2x00dev, offset); reg 154 drivers/net/wireless/ralink/rt2x00/rt2x00usb.c if (!rt2x00_get_field32(*reg, field)) reg 160 drivers/net/wireless/ralink/rt2x00/rt2x00usb.c offset, *reg); reg 161 drivers/net/wireless/ralink/rt2x00/rt2x00usb.c *reg = ~0; reg 169 drivers/net/wireless/ralink/rt2x00/rt2x00usb.c __le32 reg; reg 178 drivers/net/wireless/ralink/rt2x00/rt2x00usb.c if (rd->callback(rd->rt2x00dev, urb->status, le32_to_cpu(rd->reg))) { reg 215 drivers/net/wireless/ralink/rt2x00/rt2x00usb.c (unsigned char *)(&rd->cr), &rd->reg, sizeof(rd->reg), reg 189 drivers/net/wireless/ralink/rt2x00/rt2x00usb.h __le32 reg = 0; reg 192 drivers/net/wireless/ralink/rt2x00/rt2x00usb.h ®, sizeof(reg)); reg 193 drivers/net/wireless/ralink/rt2x00/rt2x00usb.h return le32_to_cpu(reg); reg 207 drivers/net/wireless/ralink/rt2x00/rt2x00usb.h __le32 reg = 0; reg 210 drivers/net/wireless/ralink/rt2x00/rt2x00usb.h ®, sizeof(reg), REGISTER_TIMEOUT); reg 211 drivers/net/wireless/ralink/rt2x00/rt2x00usb.h return le32_to_cpu(reg); reg 246 drivers/net/wireless/ralink/rt2x00/rt2x00usb.h __le32 reg = cpu_to_le32(value); reg 249 drivers/net/wireless/ralink/rt2x00/rt2x00usb.h ®, sizeof(reg)); reg 265 drivers/net/wireless/ralink/rt2x00/rt2x00usb.h __le32 reg = cpu_to_le32(value); reg 268 drivers/net/wireless/ralink/rt2x00/rt2x00usb.h ®, sizeof(reg), REGISTER_TIMEOUT); reg 307 drivers/net/wireless/ralink/rt2x00/rt2x00usb.h u32 *reg); reg 57 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 65 drivers/net/wireless/ralink/rt2x00/rt61pci.c if (WAIT_FOR_BBP(rt2x00dev, ®)) { reg 66 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = 0; reg 67 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, PHY_CSR3_VALUE, value); reg 68 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); reg 69 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); reg 70 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); reg 72 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); reg 81 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 94 drivers/net/wireless/ralink/rt2x00/rt61pci.c if (WAIT_FOR_BBP(rt2x00dev, ®)) { reg 95 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = 0; reg 96 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); reg 97 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); reg 98 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1); reg 100 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); reg 102 drivers/net/wireless/ralink/rt2x00/rt61pci.c WAIT_FOR_BBP(rt2x00dev, ®); reg 105 drivers/net/wireless/ralink/rt2x00/rt61pci.c value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); reg 115 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 123 drivers/net/wireless/ralink/rt2x00/rt61pci.c if (WAIT_FOR_RF(rt2x00dev, ®)) { reg 124 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = 0; reg 125 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, PHY_CSR4_VALUE, value); reg 126 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21); reg 127 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0); reg 128 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, PHY_CSR4_BUSY, 1); reg 130 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, PHY_CSR4, reg); reg 141 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 149 drivers/net/wireless/ralink/rt2x00/rt61pci.c if (WAIT_FOR_MCU(rt2x00dev, ®)) { reg 150 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); reg 151 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); reg 152 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); reg 153 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); reg 154 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); reg 156 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR); reg 157 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); reg 158 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1); reg 159 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, reg); reg 169 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 171 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR); reg 173 drivers/net/wireless/ralink/rt2x00/rt61pci.c eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); reg 174 drivers/net/wireless/ralink/rt2x00/rt61pci.c eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); reg 176 drivers/net/wireless/ralink/rt2x00/rt61pci.c !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK); reg 178 drivers/net/wireless/ralink/rt2x00/rt61pci.c !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT); reg 184 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg = 0; reg 186 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in); reg 187 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out); reg 188 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, reg 190 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT, reg 193 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg); reg 233 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 235 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13); reg 236 drivers/net/wireless/ralink/rt2x00/rt61pci.c return rt2x00_get_field32(reg, MAC_CSR13_VAL5); reg 284 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 286 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14); reg 287 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on); reg 288 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off); reg 289 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg); reg 328 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 340 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR2); reg 341 drivers/net/wireless/ralink/rt2x00/rt61pci.c if (reg && reg == ~0) { reg 343 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR3); reg 344 drivers/net/wireless/ralink/rt2x00/rt61pci.c if (reg && reg == ~0) reg 348 drivers/net/wireless/ralink/rt2x00/rt61pci.c key->hw_key_idx += reg ? ffz(reg) : 0; reg 364 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx); reg 365 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_multiwrite(rt2x00dev, reg, reg 368 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); reg 369 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_multiwrite(rt2x00dev, reg, reg 377 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR4); reg 378 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg |= (1 << crypto->bssidx); reg 379 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, SEC_CSR4, reg); reg 402 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR2); reg 404 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg |= mask; reg 406 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg &= ~mask; reg 407 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, SEC_CSR2, reg); reg 411 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR3); reg 413 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg |= mask; reg 415 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg &= ~mask; reg 416 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, SEC_CSR3, reg); reg 425 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 433 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); reg 434 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, reg 436 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, reg 438 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL, reg 440 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME, reg 442 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS, reg 445 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1); reg 446 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST, reg 448 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0); reg 449 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, reg 451 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); reg 459 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 465 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); reg 466 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); reg 467 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); reg 471 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = le32_to_cpu(conf->mac[1]); reg 472 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); reg 473 drivers/net/wireless/ralink/rt2x00/rt61pci.c conf->mac[1] = cpu_to_le32(reg); reg 480 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = le32_to_cpu(conf->bssid[1]); reg 481 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3); reg 482 drivers/net/wireless/ralink/rt2x00/rt61pci.c conf->bssid[1] = cpu_to_le32(reg); reg 494 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 496 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); reg 497 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32); reg 498 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); reg 499 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); reg 502 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4); reg 503 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); reg 504 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, reg 506 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); reg 514 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); reg 515 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, reg 517 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); reg 521 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR9); reg 522 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time); reg 523 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); reg 525 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR8); reg 526 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs); reg 527 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); reg 528 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs); reg 529 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MAC_CSR8, reg); reg 620 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 622 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13); reg 624 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR13_DIR4, 0); reg 625 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR13_VAL4, p1); reg 627 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR13_DIR3, 0); reg 628 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR13_VAL3, !p2); reg 630 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); reg 709 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 729 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, PHY_CSR0); reg 731 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, reg 733 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, reg 736 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, PHY_CSR0, reg); reg 834 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 836 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4); reg 837 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1); reg 838 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0); reg 839 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0); reg 840 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, reg 842 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, reg 844 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); reg 853 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 856 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR11); reg 857 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, reg 859 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, reg 861 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 5); reg 864 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); reg 865 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); reg 867 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 1); reg 868 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); reg 877 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR11); reg 878 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0); reg 879 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); reg 880 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); reg 881 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 0); reg 882 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); reg 918 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 923 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR0); reg 924 drivers/net/wireless/ralink/rt2x00/rt61pci.c qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); reg 929 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR1); reg 930 drivers/net/wireless/ralink/rt2x00/rt61pci.c qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); reg 1044 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 1048 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); reg 1049 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); reg 1050 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); reg 1053 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); reg 1054 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); reg 1055 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); reg 1056 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); reg 1057 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); reg 1067 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 1071 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); reg 1072 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, 1); reg 1073 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); reg 1076 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); reg 1077 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, 1); reg 1078 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); reg 1081 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); reg 1082 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, 1); reg 1083 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); reg 1086 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); reg 1087 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, 1); reg 1088 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); reg 1098 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 1102 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); reg 1103 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1); reg 1104 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); reg 1107 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); reg 1108 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1); reg 1109 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); reg 1112 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); reg 1113 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1); reg 1114 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); reg 1117 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); reg 1118 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1); reg 1119 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); reg 1122 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); reg 1123 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 1); reg 1124 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); reg 1127 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); reg 1128 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); reg 1129 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); reg 1130 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); reg 1131 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); reg 1203 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 1209 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR0); reg 1210 drivers/net/wireless/ralink/rt2x00/rt61pci.c if (reg) reg 1215 drivers/net/wireless/ralink/rt2x00/rt61pci.c if (!reg) { reg 1223 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = 0; reg 1224 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); reg 1225 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); reg 1233 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = 0; reg 1234 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); reg 1235 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1); reg 1236 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); reg 1241 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0); reg 1242 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); reg 1244 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0); reg 1245 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); reg 1248 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR); reg 1249 drivers/net/wireless/ralink/rt2x00/rt61pci.c if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY)) reg 1267 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = 0; reg 1268 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); reg 1269 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); reg 1270 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); reg 1272 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); reg 1273 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); reg 1274 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); reg 1275 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); reg 1277 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); reg 1278 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); reg 1279 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); reg 1330 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 1335 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0); reg 1336 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE, reg 1338 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE, reg 1340 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE, reg 1342 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE, reg 1344 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR0, reg); reg 1346 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1); reg 1347 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE, reg 1349 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR1, reg); reg 1352 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR); reg 1353 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER, reg 1355 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, AC0_BASE_CSR, reg); reg 1358 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR); reg 1359 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER, reg 1361 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, AC1_BASE_CSR, reg); reg 1364 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR); reg 1365 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER, reg 1367 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, AC2_BASE_CSR, reg); reg 1370 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR); reg 1371 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER, reg 1373 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, AC3_BASE_CSR, reg); reg 1375 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR); reg 1376 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit); reg 1377 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE, reg 1379 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4); reg 1380 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, RX_RING_CSR, reg); reg 1383 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR); reg 1384 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER, reg 1386 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, RX_BASE_CSR, reg); reg 1388 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR); reg 1389 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2); reg 1390 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2); reg 1391 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2); reg 1392 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2); reg 1393 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TX_DMA_DST_CSR, reg); reg 1395 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR); reg 1396 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1); reg 1397 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1); reg 1398 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1); reg 1399 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1); reg 1400 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); reg 1402 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR); reg 1403 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1); reg 1404 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); reg 1411 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 1413 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); reg 1414 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); reg 1415 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); reg 1416 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); reg 1417 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); reg 1419 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1); reg 1420 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ reg 1421 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); reg 1422 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ reg 1423 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1); reg 1424 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ reg 1425 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1); reg 1426 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ reg 1427 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1); reg 1428 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR1, reg); reg 1433 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2); reg 1434 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); reg 1435 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); reg 1436 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); reg 1437 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1); reg 1438 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11); reg 1439 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1); reg 1440 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10); reg 1441 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1); reg 1442 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR2, reg); reg 1447 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3); reg 1448 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); reg 1449 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); reg 1450 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); reg 1451 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1); reg 1452 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5); reg 1453 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); reg 1454 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR3, reg); reg 1456 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7); reg 1457 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); reg 1458 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); reg 1459 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); reg 1460 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); reg 1461 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR7, reg); reg 1463 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8); reg 1464 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); reg 1465 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); reg 1466 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); reg 1467 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); reg 1468 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR8, reg); reg 1470 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); reg 1471 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0); reg 1472 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); reg 1473 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0); reg 1474 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); reg 1475 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); reg 1476 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); reg 1477 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); reg 1483 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR9); reg 1484 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); reg 1485 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); reg 1529 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR0); reg 1530 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR1); reg 1531 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR2); reg 1536 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); reg 1537 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); reg 1538 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); reg 1539 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); reg 1541 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); reg 1542 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); reg 1543 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); reg 1544 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); reg 1546 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); reg 1547 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); reg 1548 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); reg 1624 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 1632 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR); reg 1633 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); reg 1635 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR); reg 1636 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); reg 1645 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); reg 1646 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask); reg 1647 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask); reg 1648 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, INT_MASK_CSR_BEACON_DONE, mask); reg 1649 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask); reg 1650 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff); reg 1651 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); reg 1653 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR); reg 1654 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask); reg 1655 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask); reg 1656 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask); reg 1657 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask); reg 1658 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask); reg 1659 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask); reg 1660 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask); reg 1661 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask); reg 1662 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_INT_MASK_CSR_TWAKEUP, mask); reg 1663 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); reg 1680 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 1693 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR); reg 1694 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1); reg 1695 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); reg 1710 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg, reg2; reg 1716 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR12); reg 1717 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); reg 1718 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); reg 1719 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); reg 1731 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); reg 1879 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 orig_reg, reg; reg 1885 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); reg 1886 drivers/net/wireless/ralink/rt2x00/rt61pci.c orig_reg = reg; reg 1887 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); reg 1888 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); reg 1927 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); reg 1928 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); reg 1940 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 orig_reg, reg; reg 1947 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = orig_reg; reg 1948 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); reg 1949 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); reg 2067 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 2082 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR4); reg 2083 drivers/net/wireless/ralink/rt2x00/rt61pci.c if (!rt2x00_get_field32(reg, STA_CSR4_VALID)) reg 2090 drivers/net/wireless/ralink/rt2x00/rt61pci.c type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE); reg 2099 drivers/net/wireless/ralink/rt2x00/rt61pci.c index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE); reg 2127 drivers/net/wireless/ralink/rt2x00/rt61pci.c switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) { reg 2137 drivers/net/wireless/ralink/rt2x00/rt61pci.c txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT); reg 2160 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 2168 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); reg 2169 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, irq_field, 0); reg 2170 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); reg 2178 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 2186 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR); reg 2187 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, irq_field, 0); reg 2188 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); reg 2232 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg, mask; reg 2241 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR); reg 2242 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); reg 2244 drivers/net/wireless/ralink/rt2x00/rt61pci.c if (!reg && !reg_mcu) reg 2253 drivers/net/wireless/ralink/rt2x00/rt61pci.c if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE)) reg 2256 drivers/net/wireless/ralink/rt2x00/rt61pci.c if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE)) reg 2259 drivers/net/wireless/ralink/rt2x00/rt61pci.c if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE)) reg 2270 drivers/net/wireless/ralink/rt2x00/rt61pci.c mask = reg; reg 2279 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); reg 2280 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg |= mask; reg 2281 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); reg 2283 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR); reg 2284 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg |= mask_mcu; reg 2285 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); reg 2298 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 2303 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR); reg 2308 drivers/net/wireless/ralink/rt2x00/rt61pci.c eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ? reg 2405 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 2418 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR0); reg 2419 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), reg 2420 drivers/net/wireless/ralink/rt2x00/rt61pci.c value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); reg 2738 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 2760 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13); reg 2761 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MAC_CSR13_DIR5, 1); reg 2762 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); reg 2805 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 2832 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, offset); reg 2833 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, field, queue->txop); reg 2834 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, offset, reg); reg 2840 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR); reg 2841 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, field, queue->aifs); reg 2842 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, AIFSN_CSR, reg); reg 2844 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR); reg 2845 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, field, queue->cw_min); reg 2846 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, CWMIN_CSR, reg); reg 2848 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR); reg 2849 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, field, queue->cw_max); reg 2850 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00mmio_register_write(rt2x00dev, CWMAX_CSR, reg); reg 2859 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg; reg 2861 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13); reg 2862 drivers/net/wireless/ralink/rt2x00/rt61pci.c tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; reg 2863 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12); reg 2864 drivers/net/wireless/ralink/rt2x00/rt61pci.c tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); reg 55 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 63 drivers/net/wireless/ralink/rt2x00/rt73usb.c if (WAIT_FOR_BBP(rt2x00dev, ®)) { reg 64 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = 0; reg 65 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, PHY_CSR3_VALUE, value); reg 66 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); reg 67 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); reg 68 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); reg 70 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); reg 79 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 92 drivers/net/wireless/ralink/rt2x00/rt73usb.c if (WAIT_FOR_BBP(rt2x00dev, ®)) { reg 93 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = 0; reg 94 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); reg 95 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); reg 96 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1); reg 98 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); reg 100 drivers/net/wireless/ralink/rt2x00/rt73usb.c WAIT_FOR_BBP(rt2x00dev, ®); reg 103 drivers/net/wireless/ralink/rt2x00/rt73usb.c value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); reg 113 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 121 drivers/net/wireless/ralink/rt2x00/rt73usb.c if (WAIT_FOR_RF(rt2x00dev, ®)) { reg 122 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = 0; reg 123 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, PHY_CSR4_VALUE, value); reg 128 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, reg 131 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0); reg 132 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, PHY_CSR4_BUSY, 1); reg 134 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg); reg 178 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 180 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR13); reg 181 drivers/net/wireless/ralink/rt2x00/rt73usb.c return rt2x00_get_field32(reg, MAC_CSR13_VAL7); reg 231 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 233 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14); reg 234 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on); reg 235 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off); reg 236 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg); reg 263 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 278 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR0); reg 279 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg &= mask; reg 281 drivers/net/wireless/ralink/rt2x00/rt73usb.c if (reg && reg == mask) reg 284 drivers/net/wireless/ralink/rt2x00/rt73usb.c key->hw_key_idx += reg ? ffz(reg) : 0; reg 296 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = SHARED_KEY_ENTRY(key->hw_key_idx); reg 297 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_multiwrite(rt2x00dev, reg, reg 311 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR1); reg 312 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, field, crypto->cipher); reg 313 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg); reg 318 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR5); reg 319 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, field, crypto->cipher); reg 320 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg); reg 343 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR0); reg 345 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg |= mask; reg 347 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg &= ~mask; reg 348 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg); reg 360 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 372 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR2); reg 373 drivers/net/wireless/ralink/rt2x00/rt73usb.c if (reg && reg == ~0) { reg 375 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR3); reg 376 drivers/net/wireless/ralink/rt2x00/rt73usb.c if (reg && reg == ~0) reg 380 drivers/net/wireless/ralink/rt2x00/rt73usb.c key->hw_key_idx += reg ? ffz(reg) : 0; reg 392 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx); reg 393 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_multiwrite(rt2x00dev, reg, reg 403 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); reg 404 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_multiwrite(rt2x00dev, reg, reg 412 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR4); reg 413 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg |= (1 << crypto->bssidx); reg 414 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg); reg 437 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR2); reg 439 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg |= mask; reg 441 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg &= ~mask; reg 442 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg); reg 446 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, SEC_CSR3); reg 448 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg |= mask; reg 450 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg &= ~mask; reg 451 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg); reg 460 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 468 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR0); reg 469 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, reg 471 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, reg 473 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL, reg 475 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME, reg 477 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS, reg 480 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1); reg 481 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST, reg 483 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0); reg 484 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, reg 486 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); reg 494 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 500 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9); reg 501 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); reg 502 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); reg 506 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = le32_to_cpu(conf->mac[1]); reg 507 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); reg 508 drivers/net/wireless/ralink/rt2x00/rt73usb.c conf->mac[1] = cpu_to_le32(reg); reg 515 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = le32_to_cpu(conf->bssid[1]); reg 516 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3); reg 517 drivers/net/wireless/ralink/rt2x00/rt73usb.c conf->bssid[1] = cpu_to_le32(reg); reg 528 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 530 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR0); reg 531 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32); reg 532 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); reg 533 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); reg 536 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR4); reg 537 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); reg 538 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, reg 540 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg); reg 548 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9); reg 549 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, reg 551 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); reg 555 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR9); reg 556 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time); reg 557 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg); reg 559 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR8); reg 560 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs); reg 561 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); reg 562 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs); reg 563 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg); reg 690 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 710 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, PHY_CSR0); reg 712 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, reg 714 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, reg 717 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg); reg 802 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 804 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR4); reg 805 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1); reg 806 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0); reg 807 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0); reg 808 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, reg 810 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, reg 812 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg); reg 821 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 824 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR11); reg 825 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, reg 827 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, reg 829 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 5); reg 832 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); reg 833 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); reg 835 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 1); reg 836 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); reg 841 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR11); reg 842 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0); reg 843 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); reg 844 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); reg 845 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 0); reg 846 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); reg 878 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 883 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, STA_CSR0); reg 884 drivers/net/wireless/ralink/rt2x00/rt73usb.c qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); reg 889 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, STA_CSR1); reg 890 drivers/net/wireless/ralink/rt2x00/rt73usb.c qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); reg 1016 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 1020 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR0); reg 1021 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); reg 1022 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); reg 1025 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9); reg 1026 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); reg 1027 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); reg 1028 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); reg 1029 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); reg 1039 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 1043 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR0); reg 1044 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 1); reg 1045 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); reg 1048 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9); reg 1049 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); reg 1050 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); reg 1051 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); reg 1052 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); reg 1101 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 1107 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR0); reg 1108 drivers/net/wireless/ralink/rt2x00/rt73usb.c if (reg) reg 1113 drivers/net/wireless/ralink/rt2x00/rt73usb.c if (!reg) { reg 1143 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 1145 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR0); reg 1146 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); reg 1147 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); reg 1148 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); reg 1149 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); reg 1151 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR1); reg 1152 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ reg 1153 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); reg 1154 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ reg 1155 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1); reg 1156 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ reg 1157 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1); reg 1158 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ reg 1159 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1); reg 1160 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg); reg 1165 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR2); reg 1166 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); reg 1167 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); reg 1168 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); reg 1169 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1); reg 1170 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11); reg 1171 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1); reg 1172 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10); reg 1173 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1); reg 1174 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg); reg 1179 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR3); reg 1180 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); reg 1181 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); reg 1182 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); reg 1183 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1); reg 1184 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5); reg 1185 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); reg 1186 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg); reg 1188 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR7); reg 1189 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); reg 1190 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); reg 1191 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); reg 1192 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); reg 1193 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg); reg 1195 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR8); reg 1196 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); reg 1197 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); reg 1198 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); reg 1199 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); reg 1200 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg); reg 1202 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9); reg 1203 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0); reg 1204 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); reg 1205 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0); reg 1206 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); reg 1207 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); reg 1208 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); reg 1209 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); reg 1213 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR6); reg 1214 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR6_MAX_FRAME_UNIT, 0xfff); reg 1215 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg); reg 1232 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = 0x000023b0; reg 1234 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, PHY_CSR1_RF_RPI, 1); reg 1235 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg); reg 1241 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR9); reg 1242 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); reg 1243 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg); reg 1261 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, STA_CSR0); reg 1262 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, STA_CSR1); reg 1263 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, STA_CSR2); reg 1268 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR1); reg 1269 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); reg 1270 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); reg 1271 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); reg 1273 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR1); reg 1274 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); reg 1275 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); reg 1276 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); reg 1278 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR1); reg 1279 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); reg 1280 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); reg 1379 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg, reg2; reg 1385 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR12); reg 1386 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); reg 1387 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); reg 1388 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg); reg 1400 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg); reg 1527 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 orig_reg, reg; reg 1533 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR9); reg 1534 drivers/net/wireless/ralink/rt2x00/rt73usb.c orig_reg = reg; reg 1535 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); reg 1536 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); reg 1578 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); reg 1579 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); reg 1592 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 orig_reg, reg; reg 1599 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = orig_reg; reg 1600 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); reg 1601 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); reg 1846 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 1859 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR0); reg 1860 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), reg 1861 drivers/net/wireless/ralink/rt2x00/rt73usb.c value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); reg 2166 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 2183 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, MAC_CSR13); reg 2184 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, MAC_CSR13_DIR7, 0); reg 2185 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, MAC_CSR13, reg); reg 2228 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 2255 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, offset); reg 2256 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, field, queue->txop); reg 2257 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, offset, reg); reg 2263 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, AIFSN_CSR); reg 2264 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, field, queue->aifs); reg 2265 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg); reg 2267 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, CWMIN_CSR); reg 2268 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, field, queue->cw_min); reg 2269 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg); reg 2271 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, CWMAX_CSR); reg 2272 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00_set_field32(®, field, queue->cw_max); reg 2273 drivers/net/wireless/ralink/rt2x00/rt73usb.c rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg); reg 2282 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg; reg 2284 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR13); reg 2285 drivers/net/wireless/ralink/rt2x00/rt73usb.c tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; reg 2286 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg = rt2x00usb_register_read(rt2x00dev, TXRX_CSR12); reg 2287 drivers/net/wireless/ralink/rt2x00/rt73usb.c tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); reg 96 drivers/net/wireless/ray_cs.c static irqreturn_t ray_interrupt(int reg, void *dev_id); reg 380 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c u32 reg; reg 386 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread32(priv, &priv->map->INT_STATUS_SE); reg 387 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c if (unlikely(reg == 0xFFFFFFFF)) { reg 392 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite32(priv, &priv->map->INT_STATUS_SE, reg); reg 394 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c if (reg & IMR_TIMEOUT1) reg 397 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c if (reg & (IMR_TBDOK | IMR_TBDER)) reg 400 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c if (reg & (IMR_TVODOK | IMR_TVODER)) reg 403 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c if (reg & (IMR_TVIDOK | IMR_TVIDER)) reg 406 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c if (reg & (IMR_TBEDOK | IMR_TBEDER)) reg 409 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c if (reg & (IMR_TBKDOK | IMR_TBKDER)) reg 412 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c if (reg & (IMR_ROK | IMR_RER | RTL818X_INT_SE_RX_DU | IMR_RQOSOK)) reg 417 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c if ((reg & RTL818X_INT_SE_RX_DU) && desc_err++ > 2) reg 429 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c u16 reg; reg 432 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS); reg 433 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c if (unlikely(reg == 0xFFFF)) { reg 438 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg); reg 440 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR)) reg 443 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR)) reg 446 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR)) reg 594 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c u8 reg; reg 599 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); reg 601 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg | RTL818X_CONFIG3_ANAPARAM_WRITE); reg 606 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); reg 614 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c u8 reg; reg 619 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); reg 621 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg | RTL818X_CONFIG3_ANAPARAM_WRITE); reg 626 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); reg 634 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c u8 reg; reg 637 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); reg 639 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg | RTL818X_CONFIG3_ANAPARAM_WRITE); reg 642 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); reg 649 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c u8 reg; reg 658 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread8(priv, &priv->map->PHY_PR); reg 659 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite8(priv, &priv->map->PHY_PR, reg | 0x04); reg 748 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c u16 reg; reg 768 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread16(priv, &priv->map->BRSR); reg 769 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg &= ~3; reg 770 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg |= basic_max; reg 771 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite16(priv, &priv->map->BRSR, reg); reg 815 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c u16 reg; reg 826 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread8(priv, &priv->map->CMD); reg 827 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg &= (1 << 1); reg 828 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg |= RTL818X_CMD_RESET; reg 880 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread8(priv, &priv->map->CONFIG2); reg 881 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3)); reg 883 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread8(priv, &priv->map->CONFIG2); reg 884 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4)); reg 906 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE); reg 907 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6)); reg 909 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); reg 910 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2)); reg 914 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c u8 reg; reg 916 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread8(priv, &priv->map->PGSELECT); reg 917 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1); reg 919 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg); reg 1121 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c u32 reg; reg 1158 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = RTL818X_RX_CONF_ONLYERLPKT | reg 1167 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2; reg 1169 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1) reg 1171 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2) reg 1174 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg &= ~(RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2); reg 1177 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c priv->rx_conf = reg; reg 1178 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg); reg 1181 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread8(priv, &priv->map->CW_CONF); reg 1187 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg &= ~RTL818X_CW_CONF_PERPACKET_CW; reg 1192 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg |= RTL818X_CW_CONF_PERPACKET_RETRY; reg 1193 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg); reg 1195 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL); reg 1200 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN; reg 1201 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL; reg 1202 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT; reg 1203 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg); reg 1209 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); reg 1210 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg |= (6 << 21 /* MAX TX DMA */) | reg 1214 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg |= 1<<30; /* "duration procedure mode" */ reg 1217 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg &= ~RTL818X_TX_CONF_PROBE_DTS; reg 1219 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg &= ~RTL818X_TX_CONF_HW_SEQNUM; reg 1221 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg &= ~RTL818X_TX_CONF_DISCW; reg 1224 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg &= ~RTL818X_TX_CONF_SAT_HWPLCP; reg 1226 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg); reg 1228 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread8(priv, &priv->map->CMD); reg 1229 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg |= RTL818X_CMD_RX_ENABLE; reg 1230 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg |= RTL818X_CMD_TX_ENABLE; reg 1231 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite8(priv, &priv->map->CMD, reg); reg 1247 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c u8 reg; reg 1252 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread8(priv, &priv->map->CMD); reg 1253 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg &= ~RTL818X_CMD_TX_ENABLE; reg 1254 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg &= ~RTL818X_CMD_RX_ENABLE; reg 1255 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite8(priv, &priv->map->CMD, reg); reg 1260 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread8(priv, &priv->map->CONFIG4); reg 1261 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF); reg 1500 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c u8 reg; reg 1512 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = RTL818X_MSR_ADHOC; reg 1514 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = RTL818X_MSR_INFRA; reg 1516 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = RTL818X_MSR_NO_LINK; reg 1519 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg |= RTL818X_MSR_ENEDCA; reg 1521 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite8(priv, &priv->map->MSR, reg); reg 1617 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); reg 1619 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE; reg 1620 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ; reg 1621 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK; reg 1622 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS; reg 1628 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c u8 reg = 2 << 6; reg 1631 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg |= RTL818X_EEPROM_CMD_WRITE; reg 1633 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg |= RTL818X_EEPROM_CMD_READ; reg 1635 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg |= RTL818X_EEPROM_CMD_CK; reg 1637 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg |= RTL818X_EEPROM_CMD_CS; reg 1639 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg); reg 1730 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c u32 reg; reg 1815 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); reg 1816 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c reg &= RTL818X_TX_CONF_HWVER_MASK; reg 1817 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c switch (reg) { reg 1851 drivers/net/wireless/realtek/rtl818x/rtl8180/dev.c pci_name(pdev), reg >> 25); reg 49 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c u16 reg = reg80; reg 52 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c reg |= 1; reg 55 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg); reg 57 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg | (1 << 1)); reg 58 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg | (1 << 1)); reg 61 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg); reg 96 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c u16 reg = reg80 | ((addr >> i) & 1); reg 99 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg); reg 105 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c reg | (1 << 1)); reg 109 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c reg | (1 << 1)); reg 114 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg); reg 260 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c u32 reg; reg 285 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); reg 286 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | RTL818X_CONFIG3_ANAPARAM_WRITE); reg 288 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); reg 702 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c u8 reg; reg 707 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); reg 708 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | RTL818X_CONFIG3_ANAPARAM_WRITE); reg 711 drivers/net/wireless/realtek/rtl818x/rtl8180/rtl8225.c rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); reg 573 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c u8 anaparam3, reg; reg 597 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); reg 598 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg |= RTL818X_CONFIG3_ANAPARAM_WRITE; reg 599 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg); reg 604 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE; reg 605 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg); reg 613 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c u8 reg; reg 616 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = rtl818x_ioread8(priv, &priv->map->CMD); reg 617 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg &= (1 << 1); reg 618 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg |= RTL818X_CMD_RESET; reg 619 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->CMD, reg); reg 656 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c u8 reg; reg 687 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = rtl818x_ioread8(priv, &priv->map->CONFIG1); reg 688 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg &= 0x3F; reg 689 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg |= 0x80; reg 690 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg); reg 705 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = rtl818x_ioread8(priv, (u8 *)0xFE53); reg 706 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7)); reg 729 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1; reg 730 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1); reg 734 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg); reg 773 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c u8 reg; reg 780 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = rtl818x_ioread8(priv, (u8 *)0xFF62); reg 781 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5)); reg 782 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5)); reg 795 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = rtl818x_ioread8(priv, &priv->map->CW_CONF); reg 796 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg |= RTL818X_CW_CONF_PERPACKET_RETRY; reg 797 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg); reg 807 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = rtl818x_ioread8(priv, &priv->map->CONFIG1); reg 808 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80); reg 840 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE; reg 841 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->CMD, reg); reg 852 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = rtl818x_ioread8(priv, (u8 *)0xFFDB); reg 853 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2)); reg 926 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c u32 reg; reg 940 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = RTL818X_RX_CONF_MGMT | reg 949 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c priv->rx_conf = reg; reg 950 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg); reg 952 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL); reg 953 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN; reg 954 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL; reg 955 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT; reg 956 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg); reg 982 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = RTL818X_RX_CONF_ONLYERLPKT | reg 992 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c priv->rx_conf = reg; reg 993 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg); reg 995 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = rtl818x_ioread8(priv, &priv->map->CW_CONF); reg 996 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg &= ~RTL818X_CW_CONF_PERPACKET_CW; reg 997 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg |= RTL818X_CW_CONF_PERPACKET_RETRY; reg 998 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg); reg 1000 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL); reg 1001 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN; reg 1002 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL; reg 1003 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT; reg 1004 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg); reg 1006 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = RTL818X_TX_CONF_CW_MIN | reg 1009 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg); reg 1011 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = rtl818x_ioread8(priv, &priv->map->CMD); reg 1012 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg |= RTL818X_CMD_TX_ENABLE; reg 1013 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg |= RTL818X_CMD_RX_ENABLE; reg 1014 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->CMD, reg); reg 1026 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c u32 reg; reg 1031 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = rtl818x_ioread8(priv, &priv->map->CMD); reg 1032 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg &= ~RTL818X_CMD_TX_ENABLE; reg 1033 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg &= ~RTL818X_CMD_RX_ENABLE; reg 1034 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->CMD, reg); reg 1040 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = rtl818x_ioread8(priv, &priv->map->CONFIG4); reg 1041 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF); reg 1158 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c u32 reg; reg 1161 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); reg 1167 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg | RTL818X_TX_CONF_LOOPBACK_MAC); reg 1170 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg); reg 1259 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c u8 reg; reg 1270 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = RTL818X_MSR_ENEDCA; reg 1272 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = 0; reg 1276 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg |= RTL818X_MSR_ADHOC; reg 1278 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg |= RTL818X_MSR_INFRA; reg 1281 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg |= RTL818X_MSR_NO_LINK; reg 1283 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->MSR, reg); reg 1397 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); reg 1399 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE; reg 1400 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ; reg 1401 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK; reg 1402 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS; reg 1409 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c u8 reg = RTL818X_EEPROM_CMD_PROGRAM; reg 1412 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg |= RTL818X_EEPROM_CMD_WRITE; reg 1414 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg |= RTL818X_EEPROM_CMD_READ; reg 1416 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg |= RTL818X_EEPROM_CMD_CK; reg 1418 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg |= RTL818X_EEPROM_CMD_CS; reg 1420 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg); reg 1433 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c u16 txpwr, reg; reg 1523 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1; reg 1524 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1); reg 1529 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg); reg 1602 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_SELECT_GPIO, ®); reg 1603 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c if (reg & 0xFF00) reg 1637 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c eeprom_93cx6_read(&eeprom, 0x3F, ®); reg 1638 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c reg &= 0xFF; reg 1639 drivers/net/wireless/realtek/rtl818x/rtl8187/dev.c rtl8187_leds_init(dev, reg); reg 27 drivers/net/wireless/realtek/rtl818x/rtl8187/leds.c u8 reg; reg 46 drivers/net/wireless/realtek/rtl818x/rtl8187/leds.c reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~(1 << 4); reg 47 drivers/net/wireless/realtek/rtl818x/rtl8187/leds.c rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg); reg 50 drivers/net/wireless/realtek/rtl818x/rtl8187/leds.c reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~(1 << 5); reg 51 drivers/net/wireless/realtek/rtl818x/rtl8187/leds.c rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg); reg 65 drivers/net/wireless/realtek/rtl818x/rtl8187/leds.c u8 reg; reg 84 drivers/net/wireless/realtek/rtl818x/rtl8187/leds.c reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) | (1 << 4); reg 85 drivers/net/wireless/realtek/rtl818x/rtl8187/leds.c rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg); reg 88 drivers/net/wireless/realtek/rtl818x/rtl8187/leds.c reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) | (1 << 5); reg 89 drivers/net/wireless/realtek/rtl818x/rtl8187/leds.c rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg); reg 139 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c u16 reg = reg80 | (bangdata & (1 << i)) >> i; reg 142 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg); reg 144 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg | (1 << 1)); reg 145 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg | (1 << 1)); reg 148 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg); reg 228 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c u16 reg = reg80 | ((addr >> i) & 1); reg 231 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg); reg 236 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c reg | (1 << 1)); reg 239 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c reg | (1 << 1)); reg 243 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, reg); reg 376 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c u32 reg; reg 403 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); reg 405 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c reg | RTL818X_CONFIG3_ANAPARAM_WRITE); reg 409 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); reg 627 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c u32 reg; reg 658 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); reg 660 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c reg | RTL818X_CONFIG3_ANAPARAM_WRITE); reg 664 drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8225.c reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); reg 868 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h u16 reg; reg 873 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h u16 reg; reg 878 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h u8 reg; reg 1370 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h enum rtl8xxxu_rfpath path, u8 reg); reg 1372 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h enum rtl8xxxu_rfpath path, u8 reg, u32 data); reg 1378 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h const u32 *reg, u32 *backup); reg 1380 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h const u32 *reg, u32 *backup); reg 307 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data) reg 324 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c h2c.bt_mp_oper.addr = reg; reg 808 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c enum rtl8xxxu_rfpath path, u8 reg) reg 819 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT); reg 843 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c __func__, reg, retval); reg 853 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c enum rtl8xxxu_rfpath path, u8 reg, u32 data) reg 860 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c __func__, reg, data); reg 863 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data; reg 2147 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c u16 reg; reg 2151 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c reg = array[i].reg; reg 2154 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c if (reg == 0xffff && val == 0xff) reg 2157 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c ret = rtl8xxxu_write8(priv, reg, val); reg 2161 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c "(reg: %04x, val %02x)\n", reg, val); reg 2176 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c u16 reg; reg 2180 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c reg = array[i].reg; reg 2183 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c if (reg == 0xffff && val == 0xffffffff) reg 2186 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c ret = rtl8xxxu_write32(priv, reg, val); reg 2342 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c u8 reg; reg 2346 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c reg = array[i].reg; reg 2349 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c if (reg == 0xff && val == 0xffffffff) reg 2352 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c switch (reg) { reg 2373 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c ret = rtl8xxxu_write_rfreg(priv, path, reg, val); reg 2652 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c u32 oldval, x, tx0_a, reg; reg 2704 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c reg = result[candidate][2]; reg 2708 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= (reg & 0x3ff); reg 2711 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c reg = result[candidate][3] & 0x3F; reg 2715 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= ((reg << 10) & 0xfc00); reg 2718 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c reg = (result[candidate][3] >> 6) & 0xF; reg 2722 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= (reg << 28); reg 2729 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c u32 oldval, x, tx1_a, reg; reg 2781 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c reg = result[candidate][6]; reg 2785 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= (reg & 0x3ff); reg 2788 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c reg = result[candidate][7] & 0x3f; reg 2792 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= ((reg << 10) & 0xfc00); reg 2795 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c reg = (result[candidate][7] >> 6) & 0xf; reg 2799 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c val32 |= (reg << 12); reg 2945 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup) reg 2950 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c backup[i] = rtl8xxxu_read8(priv, reg[i]); reg 2952 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c backup[i] = rtl8xxxu_read32(priv, reg[i]); reg 2956 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c const u32 *reg, u32 *backup) reg 2961 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c rtl8xxxu_write8(priv, reg[i], backup[i]); reg 2963 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c rtl8xxxu_write32(priv, reg[i], backup[i]); reg 3490 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c u16 reg; reg 3492 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c reg = REG_MACID; reg 3495 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]); reg 3503 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c u16 reg; reg 3507 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c reg = REG_BSSID; reg 3510 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c rtl8xxxu_write8(priv, reg + i, bssid[i]); reg 1720 drivers/net/wireless/realtek/rtlwifi/base.c u32 reg = 0; reg 1741 drivers/net/wireless/realtek/rtlwifi/base.c reg |= (param->txop & 0x7FF) << 16; reg 1742 drivers/net/wireless/realtek/rtlwifi/base.c reg |= (fls(param->cw_max) & 0xF) << 12; reg 1743 drivers/net/wireless/realtek/rtlwifi/base.c reg |= (fls(param->cw_min) & 0xF) << 8; reg 1744 drivers/net/wireless/realtek/rtlwifi/base.c reg |= (param->aifs & 0x0F) * slottime + sifstime; reg 1746 drivers/net/wireless/realtek/rtlwifi/base.c return reg; reg 272 drivers/net/wireless/realtek/rtlwifi/regd.c struct rtl_regulatory *reg) reg 281 drivers/net/wireless/realtek/rtlwifi/regd.c struct rtl_regulatory *reg) reg 292 drivers/net/wireless/realtek/rtlwifi/regd.c _rtl_reg_apply_world_flags(wiphy, request->initiator, reg); reg 300 drivers/net/wireless/realtek/rtlwifi/regd.c struct rtl_regulatory *reg) reg 302 drivers/net/wireless/realtek/rtlwifi/regd.c switch (reg->country_code) { reg 329 drivers/net/wireless/realtek/rtlwifi/regd.c static int _rtl_regd_init_wiphy(struct rtl_regulatory *reg, reg 342 drivers/net/wireless/realtek/rtlwifi/regd.c regd = _rtl_regdomain_select(reg); reg 345 drivers/net/wireless/realtek/rtlwifi/regd.c _rtl_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, reg); reg 1506 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c u32 oldval_0, x, tx0_a, reg; reg 1533 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c reg = result[final_candidate][2]; reg 1534 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); reg 1535 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c reg = result[final_candidate][3] & 0x3F; reg 1536 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); reg 1537 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c reg = (result[final_candidate][3] >> 6) & 0xF; reg 1538 drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); reg 981 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c u32 oldval_0, x, tx0_a, reg; reg 1008 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c reg = result[final_candidate][2]; reg 1009 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); reg 1010 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c reg = result[final_candidate][3] & 0x3F; reg 1011 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); reg 1012 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c reg = (result[final_candidate][3] >> 6) & 0xF; reg 1013 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); reg 1021 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c u32 oldval_1, x, tx1_a, reg; reg 1048 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c reg = result[final_candidate][6]; reg 1049 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); reg 1050 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c reg = result[final_candidate][7] & 0x3F; reg 1051 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); reg 1052 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c reg = (result[final_candidate][7] >> 6) & 0xF; reg 1053 drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); reg 2136 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c u32 oldval_0, val_x, tx0_a, reg; reg 2183 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c reg = result[final_candidate][2]; reg 2184 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); reg 2185 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c reg = result[final_candidate][3] & 0x3F; reg 2186 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); reg 2187 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c reg = (result[final_candidate][3] >> 6) & 0xF; reg 2188 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); reg 2197 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c u32 oldval_1, val_x, tx1_a, reg; reg 2232 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c reg = result[final_candidate][6]; reg 2233 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); reg 2234 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c reg = result[final_candidate][7] & 0x3F; reg 2235 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); reg 2236 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c reg = (result[final_candidate][7] >> 6) & 0xF; reg 2237 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); reg 477 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c u8 *reg = NULL; reg 480 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c reg = regtoset_normal; reg 488 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if ((reg[i] & 0xf0) > (fac << 4)) reg 489 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c reg[i] = (reg[i] & 0x0f) | reg 491 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c if ((reg[i] & 0x0f) > fac) reg 492 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c reg[i] = (reg[i] & 0xf0) | fac; reg 495 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c reg[i]); reg 2264 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c u32 oldval_0, x, tx0_a, reg; reg 2293 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c reg = result[final_candidate][2]; reg 2294 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); reg 2296 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c reg = result[final_candidate][3] & 0x3F; reg 2297 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); reg 2299 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c reg = (result[final_candidate][3] >> 6) & 0xF; reg 2300 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg); reg 2309 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c u32 oldval_1, x, tx1_a, reg; reg 2338 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c reg = result[final_candidate][6]; reg 2339 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); reg 2341 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c reg = result[final_candidate][7] & 0x3F; reg 2342 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); reg 2344 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c reg = (result[final_candidate][7] >> 6) & 0xF; reg 2345 drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0xF0000000, reg); reg 1890 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c u32 oldval_1, x, tx1_a, reg; reg 1917 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c reg = result[final_candidate][6]; reg 1918 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); reg 1919 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c reg = result[final_candidate][7] & 0x3F; reg 1920 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); reg 1921 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c reg = (result[final_candidate][7] >> 6) & 0xF; reg 286 drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c u32 oldval_0, x, tx0_a, reg; reg 313 drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c reg = result[final_candidate][2]; reg 314 drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); reg 315 drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c reg = result[final_candidate][3] & 0x3F; reg 316 drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); reg 317 drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c reg = (result[final_candidate][3] >> 6) & 0xF; reg 318 drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); reg 362 drivers/net/wireless/realtek/rtw88/mac.c bckp[bckp_idx].reg = REG_TXDMA_PQ_MAP + 1; reg 370 drivers/net/wireless/realtek/rtw88/mac.c bckp[bckp_idx].reg = REG_CR; reg 374 drivers/net/wireless/realtek/rtw88/mac.c bckp[bckp_idx].reg = REG_H2CQ_CSR; reg 383 drivers/net/wireless/realtek/rtw88/mac.c bckp[bckp_idx].reg = REG_FIFOPAGE_INFO_1; reg 387 drivers/net/wireless/realtek/rtw88/mac.c bckp[bckp_idx].reg = REG_RQPN_CTRL_2; reg 396 drivers/net/wireless/realtek/rtw88/mac.c bckp[bckp_idx].reg = REG_BCN_CTRL; reg 439 drivers/net/wireless/realtek/rtw88/main.h u32 reg; reg 355 drivers/net/wireless/realtek/rtw88/regd.c rtw_regd_init_wiphy(struct rtw_regulatory *reg, struct wiphy *wiphy, reg 78 drivers/net/wireless/realtek/rtw88/rtw8822c.c u32 reg; reg 87 drivers/net/wireless/realtek/rtw88/rtw8822c.c backup[i].reg = addrs[i]; reg 93 drivers/net/wireless/realtek/rtw88/rtw8822c.c reg = rf_addr[i]; reg 94 drivers/net/wireless/realtek/rtw88/rtw8822c.c val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK); reg 95 drivers/net/wireless/realtek/rtw88/rtw8822c.c backup_rf[path * i + i].reg = reg; reg 107 drivers/net/wireless/realtek/rtw88/rtw8822c.c u32 reg; reg 114 drivers/net/wireless/realtek/rtw88/rtw8822c.c reg = backup_rf[path * i + i].reg; reg 115 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val); reg 2100 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw8822c_dpk_backup_registers(struct rtw_dev *rtwdev, u32 *reg, reg 2107 drivers/net/wireless/realtek/rtw88/rtw8822c.c bckp[i].reg = reg[i]; reg 2108 drivers/net/wireless/realtek/rtw88/rtw8822c.c bckp[i].val = rtw_read32(rtwdev, reg[i]); reg 2143 drivers/net/wireless/realtek/rtw88/rtw8822c.c u32 reg; reg 2146 drivers/net/wireless/realtek/rtw88/rtw8822c.c reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); reg 2148 drivers/net/wireless/realtek/rtw88/rtw8822c.c band_shift = FIELD_GET(BIT(16), reg); reg 2150 drivers/net/wireless/realtek/rtw88/rtw8822c.c dpk_info->dpk_ch = FIELD_GET(0xff, reg); reg 2151 drivers/net/wireless/realtek/rtw88/rtw8822c.c dpk_info->dpk_bw = FIELD_GET(0x3000, reg); reg 2613 drivers/net/wireless/realtek/rtw88/rtw8822c.c u32 reg = 0; reg 2616 drivers/net/wireless/realtek/rtw88/rtw8822c.c reg = rtw_read32(rtwdev, REG_STAT_RPT); reg 2623 drivers/net/wireless/realtek/rtw88/rtw8822c.c reg = (coef_i << 16) | coef_q; reg 2625 drivers/net/wireless/realtek/rtw88/rtw8822c.c return reg; reg 2683 drivers/net/wireless/realtek/rtw88/rtw8822c.c u16 reg[DPK_RF_PATH_NUM] = {0x1b0c, 0x1b64}; reg 2699 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32(rtwdev, reg[path] + addr * 4, coef); reg 49 drivers/net/wireless/realtek/rtw88/util.c u32 reg; reg 55 drivers/net/wireless/realtek/rtw88/util.c reg = bckp->reg; reg 60 drivers/net/wireless/realtek/rtw88/util.c rtw_write8(rtwdev, reg, (u8)val); reg 63 drivers/net/wireless/realtek/rtw88/util.c rtw_write16(rtwdev, reg, (u16)val); reg 66 drivers/net/wireless/realtek/rtw88/util.c rtw_write32(rtwdev, reg, (u32)val); reg 171 drivers/net/wireless/rsi/rsi_91x_usb.c u32 reg, reg 189 drivers/net/wireless/rsi/rsi_91x_usb.c ((reg & 0xffff0000) >> 16), (reg & 0xffff), reg 216 drivers/net/wireless/rsi/rsi_91x_usb.c u32 reg, reg 239 drivers/net/wireless/rsi/rsi_91x_usb.c ((cpu_to_le32(reg) & 0xffff0000) >> 16), reg 240 drivers/net/wireless/rsi/rsi_91x_usb.c (cpu_to_le32(reg) & 0xffff), reg 465 drivers/net/wireless/rsi/rsi_91x_usb.c static int rsi_usb_master_reg_read(struct rsi_hw *adapter, u32 reg, reg 473 drivers/net/wireless/rsi/rsi_91x_usb.c ret = rsi_usb_reg_read(usbdev, reg, &temp, len); reg 482 drivers/net/wireless/rsi/rsi_91x_usb.c unsigned long reg, reg 488 drivers/net/wireless/rsi/rsi_91x_usb.c return rsi_usb_reg_write(usbdev, reg, value, len); reg 62 drivers/net/wireless/st/cw1200/fwio.c #define APB_WRITE(reg, val) \ reg 64 drivers/net/wireless/st/cw1200/fwio.c ret = cw1200_apb_write_32(priv, CW1200_APB(reg), (val)); \ reg 68 drivers/net/wireless/st/cw1200/fwio.c #define APB_WRITE2(reg, val) \ reg 70 drivers/net/wireless/st/cw1200/fwio.c ret = cw1200_apb_write_32(priv, CW1200_APB(reg), (val)); \ reg 74 drivers/net/wireless/st/cw1200/fwio.c #define APB_READ(reg, val) \ reg 76 drivers/net/wireless/st/cw1200/fwio.c ret = cw1200_apb_read_32(priv, CW1200_APB(reg), &(val)); \ reg 80 drivers/net/wireless/st/cw1200/fwio.c #define REG_WRITE(reg, val) \ reg 82 drivers/net/wireless/st/cw1200/fwio.c ret = cw1200_reg_write_32(priv, (reg), (val)); \ reg 86 drivers/net/wireless/st/cw1200/fwio.c #define REG_READ(reg, val) \ reg 88 drivers/net/wireless/st/cw1200/fwio.c ret = cw1200_reg_read_32(priv, (reg), &(val)); \ reg 1245 drivers/net/wireless/st/cw1200/wsm.c u32 reg[18]; reg 1260 drivers/net/wireless/st/cw1200/wsm.c for (i = 0; i < ARRAY_SIZE(reg); ++i) reg 1261 drivers/net/wireless/st/cw1200/wsm.c reg[i] = WSM_GET32(&buf); reg 1271 drivers/net/wireless/st/cw1200/wsm.c (int) sizeof(fname), fname, reg[1]); reg 1276 drivers/net/wireless/st/cw1200/wsm.c i + 0, reg[i + 0], i + 1, reg[i + 1], reg 1277 drivers/net/wireless/st/cw1200/wsm.c i + 2, reg[i + 2], i + 3, reg[i + 3]); reg 1280 drivers/net/wireless/st/cw1200/wsm.c reg[i + 0], reg[i + 1], reg[i + 2], reg[i + 3]); reg 1284 drivers/net/wireless/st/cw1200/wsm.c reg[i + 0], reg[i + 1]); reg 132 drivers/net/wireless/ti/wl1251/wl1251.h struct wl1251_partition reg; reg 495 drivers/net/wireless/ti/wl12xx/main.c .reg = { reg 515 drivers/net/wireless/ti/wl12xx/main.c .reg = { reg 534 drivers/net/wireless/ti/wl12xx/main.c .reg = { reg 553 drivers/net/wireless/ti/wl12xx/main.c .reg = { reg 583 drivers/net/wireless/ti/wl18xx/main.c .reg = { .start = 0x00807000, .size = 0x00005000 }, reg 589 drivers/net/wireless/ti/wl18xx/main.c .reg = { .start = 0x00810000, .size = 0x0000BFFF }, reg 595 drivers/net/wireless/ti/wl18xx/main.c .reg = { .start = 0x00802000, .size = 0x00014578 }, reg 601 drivers/net/wireless/ti/wl18xx/main.c .reg = { .start = 0x00B00404, .size = 0x00001000 }, reg 608 drivers/net/wireless/ti/wl18xx/main.c .reg = { .start = 0x00000000, .size = 0x00000000 }, reg 365 drivers/net/wireless/ti/wlcore/boot.c dest_addr += wl->curr_part.reg.start; reg 72 drivers/net/wireless/ti/wlcore/io.c else if ((addr >= part->reg.start) && reg 73 drivers/net/wireless/ti/wlcore/io.c (addr < part->reg.start + part->reg.size)) reg 74 drivers/net/wireless/ti/wlcore/io.c return addr - part->reg.start + part->mem.size; reg 78 drivers/net/wireless/ti/wlcore/io.c part->reg.size; reg 82 drivers/net/wireless/ti/wlcore/io.c part->reg.size + part->mem2.size; reg 134 drivers/net/wireless/ti/wlcore/io.c p->reg.start, p->reg.size); reg 148 drivers/net/wireless/ti/wlcore/io.c ret = wlcore_raw_write32(wl, HW_PART1_START_ADDR, p->reg.start); reg 152 drivers/net/wireless/ti/wlcore/io.c ret = wlcore_raw_write32(wl, HW_PART1_SIZE_ADDR, p->reg.size); reg 80 drivers/net/wireless/ti/wlcore/io.h static inline int __must_check wlcore_raw_read_data(struct wl1271 *wl, int reg, reg 84 drivers/net/wireless/ti/wlcore/io.h return wlcore_raw_read(wl, wl->rtable[reg], buf, len, fixed); reg 87 drivers/net/wireless/ti/wlcore/io.h static inline int __must_check wlcore_raw_write_data(struct wl1271 *wl, int reg, reg 91 drivers/net/wireless/ti/wlcore/io.h return wlcore_raw_write(wl, wl->rtable[reg], buf, len, fixed); reg 138 drivers/net/wireless/ti/wlcore/io.h static inline int __must_check wlcore_write_data(struct wl1271 *wl, int reg, reg 142 drivers/net/wireless/ti/wlcore/io.h return wlcore_write(wl, wl->rtable[reg], buf, len, fixed); reg 145 drivers/net/wireless/ti/wlcore/io.h static inline int __must_check wlcore_read_data(struct wl1271 *wl, int reg, reg 149 drivers/net/wireless/ti/wlcore/io.h return wlcore_read(wl, wl->rtable[reg], buf, len, fixed); reg 179 drivers/net/wireless/ti/wlcore/io.h static inline int __must_check wlcore_read_reg(struct wl1271 *wl, int reg, reg 183 drivers/net/wireless/ti/wlcore/io.h wlcore_translate_addr(wl, wl->rtable[reg]), reg 187 drivers/net/wireless/ti/wlcore/io.h static inline int __must_check wlcore_write_reg(struct wl1271 *wl, int reg, reg 191 drivers/net/wireless/ti/wlcore/io.h wlcore_translate_addr(wl, wl->rtable[reg]), reg 87 drivers/net/wireless/ti/wlcore/spi.c struct regulator *reg; /* Power regulator */ reg 378 drivers/net/wireless/ti/wlcore/spi.c WARN_ON(!glue->reg); reg 382 drivers/net/wireless/ti/wlcore/spi.c ret = regulator_enable(glue->reg); reg 386 drivers/net/wireless/ti/wlcore/spi.c ret = regulator_disable(glue->reg); reg 491 drivers/net/wireless/ti/wlcore/spi.c glue->reg = devm_regulator_get(&spi->dev, "vwlan"); reg 492 drivers/net/wireless/ti/wlcore/spi.c if (PTR_ERR(glue->reg) == -EPROBE_DEFER) reg 494 drivers/net/wireless/ti/wlcore/spi.c if (IS_ERR(glue->reg)) { reg 496 drivers/net/wireless/ti/wlcore/spi.c return PTR_ERR(glue->reg); reg 138 drivers/net/wireless/ti/wlcore/wlcore.h struct wlcore_partition reg; reg 23 drivers/net/wireless/zydas/zd1211rw/zd_mac.c u32 reg; reg 141 drivers/net/wireless/zydas/zd1211rw/zd_mac.c if (regdomain == reg_map->reg) { reg 46 drivers/net/wireless/zydas/zd1211rw/zd_rf_rf2959.c int reg = bits(rw, 18, 22); reg 48 drivers/net/wireless/zydas/zd1211rw/zd_rf_rf2959.c PDEBUG("rf2959 %#010x reg %d rw %d", rw, reg, rw_flag); reg 50 drivers/net/wireless/zydas/zd1211rw/zd_rf_rf2959.c switch (reg) { reg 22 drivers/net/wireless/zydas/zd1211rw/zd_rf_uw2453.c #define UW2453_REGWRITE(reg, val) ((((reg) & 0xf) << 20) | ((val) & 0xfffff)) reg 470 drivers/nfc/trf7970a.c static int trf7970a_read(struct trf7970a *trf, u8 reg, u8 *val) reg 472 drivers/nfc/trf7970a.c u8 addr = TRF7970A_CMD_BIT_RW | reg; reg 485 drivers/nfc/trf7970a.c static int trf7970a_read_cont(struct trf7970a *trf, u8 reg, u8 *buf, reg 488 drivers/nfc/trf7970a.c u8 addr = reg | TRF7970A_CMD_BIT_RW | TRF7970A_CMD_BIT_CONTINUOUS; reg 514 drivers/nfc/trf7970a.c static int trf7970a_write(struct trf7970a *trf, u8 reg, u8 val) reg 516 drivers/nfc/trf7970a.c u8 buf[2] = { reg, val }; reg 519 drivers/nfc/trf7970a.c dev_dbg(trf->dev, "write(0x%x): 0x%x\n", reg, val); reg 491 drivers/ntb/hw/amd/ntb_hw_amd.c int reg; reg 493 drivers/ntb/hw/amd/ntb_hw_amd.c reg = readl(mmio + AMD_SMUACK_OFFSET); reg 494 drivers/ntb/hw/amd/ntb_hw_amd.c reg |= bit; reg 495 drivers/ntb/hw/amd/ntb_hw_amd.c writel(reg, mmio + AMD_SMUACK_OFFSET); reg 845 drivers/ntb/hw/amd/ntb_hw_amd.c u32 reg, stat; reg 848 drivers/ntb/hw/amd/ntb_hw_amd.c reg = readl(mmio + AMD_SIDEINFO_OFFSET); reg 849 drivers/ntb/hw/amd/ntb_hw_amd.c reg &= NTB_LIN_STA_ACTIVE_BIT; reg 851 drivers/ntb/hw/amd/ntb_hw_amd.c dev_dbg(&ndev->ntb.pdev->dev, "%s: reg_val = 0x%x.\n", __func__, reg); reg 853 drivers/ntb/hw/amd/ntb_hw_amd.c if (reg == ndev->cntl_sta) reg 856 drivers/ntb/hw/amd/ntb_hw_amd.c ndev->cntl_sta = reg; reg 886 drivers/ntb/hw/amd/ntb_hw_amd.c unsigned int reg; reg 888 drivers/ntb/hw/amd/ntb_hw_amd.c reg = readl(mmio + AMD_SIDEINFO_OFFSET); reg 889 drivers/ntb/hw/amd/ntb_hw_amd.c if (!(reg & AMD_SIDE_READY)) { reg 890 drivers/ntb/hw/amd/ntb_hw_amd.c reg |= AMD_SIDE_READY; reg 891 drivers/ntb/hw/amd/ntb_hw_amd.c writel(reg, mmio + AMD_SIDEINFO_OFFSET); reg 898 drivers/ntb/hw/amd/ntb_hw_amd.c unsigned int reg; reg 900 drivers/ntb/hw/amd/ntb_hw_amd.c reg = readl(mmio + AMD_SIDEINFO_OFFSET); reg 901 drivers/ntb/hw/amd/ntb_hw_amd.c if (reg & AMD_SIDE_READY) { reg 902 drivers/ntb/hw/amd/ntb_hw_amd.c reg &= ~AMD_SIDE_READY; reg 903 drivers/ntb/hw/amd/ntb_hw_amd.c writel(reg, mmio + AMD_SIDEINFO_OFFSET); reg 300 drivers/ntb/hw/idt/ntb_hw_idt.c const unsigned int reg, const u32 data) reg 306 drivers/ntb/hw/idt/ntb_hw_idt.c if (WARN_ON(reg > IDT_REG_PCI_MAX || !IS_ALIGNED(reg, IDT_REG_ALIGN))) reg 310 drivers/ntb/hw/idt/ntb_hw_idt.c iowrite32(data, ndev->cfgspc + (ptrdiff_t)reg); reg 322 drivers/ntb/hw/idt/ntb_hw_idt.c static u32 idt_nt_read(struct idt_ntb_dev *ndev, const unsigned int reg) reg 328 drivers/ntb/hw/idt/ntb_hw_idt.c if (WARN_ON(reg > IDT_REG_PCI_MAX || !IS_ALIGNED(reg, IDT_REG_ALIGN))) reg 332 drivers/ntb/hw/idt/ntb_hw_idt.c return ioread32(ndev->cfgspc + (ptrdiff_t)reg); reg 344 drivers/ntb/hw/idt/ntb_hw_idt.c const unsigned int reg, const u32 data) reg 352 drivers/ntb/hw/idt/ntb_hw_idt.c if (WARN_ON(reg > IDT_REG_SW_MAX || !IS_ALIGNED(reg, IDT_REG_ALIGN))) reg 358 drivers/ntb/hw/idt/ntb_hw_idt.c iowrite32((u32)reg, ndev->cfgspc + (ptrdiff_t)IDT_NT_GASAADDR); reg 374 drivers/ntb/hw/idt/ntb_hw_idt.c static u32 idt_sw_read(struct idt_ntb_dev *ndev, const unsigned int reg) reg 383 drivers/ntb/hw/idt/ntb_hw_idt.c if (WARN_ON(reg > IDT_REG_SW_MAX || !IS_ALIGNED(reg, IDT_REG_ALIGN))) reg 389 drivers/ntb/hw/idt/ntb_hw_idt.c iowrite32((u32)reg, ndev->cfgspc + (ptrdiff_t)IDT_NT_GASAADDR); reg 414 drivers/ntb/hw/idt/ntb_hw_idt.c static inline int idt_reg_set_bits(struct idt_ntb_dev *ndev, unsigned int reg, reg 426 drivers/ntb/hw/idt/ntb_hw_idt.c data = idt_nt_read(ndev, reg) | (u32)set_bits; reg 427 drivers/ntb/hw/idt/ntb_hw_idt.c idt_nt_write(ndev, reg, data); reg 451 drivers/ntb/hw/idt/ntb_hw_idt.c unsigned int reg, spinlock_t *reg_lock, reg 459 drivers/ntb/hw/idt/ntb_hw_idt.c data = idt_nt_read(ndev, reg) & ~(u32)clear_bits; reg 460 drivers/ntb/hw/idt/ntb_hw_idt.c idt_nt_write(ndev, reg, data); reg 1933 drivers/ntb/hw/idt/ntb_hw_idt.c unsigned int reg; reg 1943 drivers/ntb/hw/idt/ntb_hw_idt.c reg = IDT_SW_TMPALARM; reg 1944 drivers/ntb/hw/idt/ntb_hw_idt.c data = SET_FIELD(TMPALARM_LTEMP, idt_sw_read(ndev, reg), fmt) & reg 1948 drivers/ntb/hw/idt/ntb_hw_idt.c reg = IDT_SW_TMPALARM; reg 1949 drivers/ntb/hw/idt/ntb_hw_idt.c data = SET_FIELD(TMPALARM_HTEMP, idt_sw_read(ndev, reg), fmt) & reg 1953 drivers/ntb/hw/idt/ntb_hw_idt.c reg = IDT_SW_TMPADJ; reg 1954 drivers/ntb/hw/idt/ntb_hw_idt.c data = SET_FIELD(TMPADJ_OFFSET, idt_sw_read(ndev, reg), fmt); reg 1960 drivers/ntb/hw/idt/ntb_hw_idt.c idt_sw_write(ndev, reg, data); reg 180 drivers/ntb/hw/intel/ntb_hw_gen1.c return ndev->reg->mw_bar[idx]; reg 185 drivers/ntb/hw/intel/ntb_hw_gen1.c phys_addr_t reg_addr, unsigned long reg) reg 191 drivers/ntb/hw/intel/ntb_hw_gen1.c *db_addr = reg_addr + reg; reg 196 drivers/ntb/hw/intel/ntb_hw_gen1.c *db_size = ndev->reg->db_size; reg 207 drivers/ntb/hw/intel/ntb_hw_gen1.c return ndev->reg->db_ioread(mmio); reg 219 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->reg->db_iowrite(db_bits, mmio); reg 238 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->reg->db_iowrite(ndev->db_mask, mmio); reg 259 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->reg->db_iowrite(ndev->db_mask, mmio); reg 278 drivers/ntb/hw/intel/ntb_hw_gen1.c unsigned long reg) reg 287 drivers/ntb/hw/intel/ntb_hw_gen1.c *spad_addr = reg_addr + reg + (idx << 2); reg 335 drivers/ntb/hw/intel/ntb_hw_gen1.c if (ndev->reg->poll_link(ndev)) reg 375 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->reg->db_iowrite(ndev->db_mask, reg 472 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->reg->db_iowrite(ndev->db_mask, reg 536 drivers/ntb/hw/intel/ntb_hw_gen1.c if (!ndev->reg->link_is_up(ndev)) { reg 945 drivers/ntb/hw/intel/ntb_hw_gen1.c if (ndev->reg->link_is_up(ndev)) { reg 982 drivers/ntb/hw/intel/ntb_hw_gen1.c ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl); reg 988 drivers/ntb/hw/intel/ntb_hw_gen1.c iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl); reg 1006 drivers/ntb/hw/intel/ntb_hw_gen1.c ntb_cntl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl); reg 1012 drivers/ntb/hw/intel/ntb_hw_gen1.c iowrite32(ntb_cntl, ndev->self_mmio + ndev->reg->ntb_ctl); reg 1220 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->reg->db_iowrite(ndev->db_link_mask, reg 1557 drivers/ntb/hw/intel/ntb_hw_gen1.c ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl); reg 1559 drivers/ntb/hw/intel/ntb_hw_gen1.c iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl); reg 1633 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->reg->db_iowrite(ndev->db_valid_mask, reg 1715 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->reg = &xeon_reg; reg 1904 drivers/ntb/hw/intel/ntb_hw_gen1.c ndev->reg->poll_link(ndev); reg 152 drivers/ntb/hw/intel/ntb_hw_gen1.h phys_addr_t reg_addr, unsigned long reg); reg 98 drivers/ntb/hw/intel/ntb_hw_gen3.c ndev->reg->db_iowrite(ndev->db_link_mask, reg 219 drivers/ntb/hw/intel/ntb_hw_gen3.c ndev->reg->db_iowrite(ndev->db_valid_mask, reg 234 drivers/ntb/hw/intel/ntb_hw_gen3.c ndev->reg = &gen3_reg; reg 288 drivers/ntb/hw/intel/ntb_hw_gen3.c if (!ndev->reg->link_is_up(ndev)) reg 436 drivers/ntb/hw/intel/ntb_hw_gen3.c ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl); reg 440 drivers/ntb/hw/intel/ntb_hw_gen3.c iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl); reg 168 drivers/ntb/hw/intel/ntb_hw_intel.h const struct intel_ntb_reg *reg; reg 46 drivers/nvmem/imx-iim.c int reg = i & 0x1f; reg 48 drivers/nvmem/imx-iim.c *buf8++ = readl(iim->base + IIM_BANK_BASE(bank) + reg * 4); reg 55 drivers/nvmem/lpc18xx_eeprom.c u32 reg, u32 val) reg 57 drivers/nvmem/lpc18xx_eeprom.c writel(val, eeprom->reg_base + reg); reg 61 drivers/nvmem/lpc18xx_eeprom.c u32 reg) reg 63 drivers/nvmem/lpc18xx_eeprom.c return readl(eeprom->reg_base + reg); reg 90 drivers/nvmem/lpc18xx_eeprom.c static int lpc18xx_eeprom_gather_write(void *context, unsigned int reg, reg 94 drivers/nvmem/lpc18xx_eeprom.c unsigned int offset = reg; reg 101 drivers/nvmem/lpc18xx_eeprom.c if ((reg > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE) || reg 102 drivers/nvmem/lpc18xx_eeprom.c (reg + bytes > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE)) reg 51 drivers/nvmem/meson-mx-efuse.c static void meson_mx_efuse_mask_bits(struct meson_mx_efuse *efuse, u32 reg, reg 56 drivers/nvmem/meson-mx-efuse.c data = readl(efuse->base + reg); reg 60 drivers/nvmem/meson-mx-efuse.c writel(data, efuse->base + reg); reg 19 drivers/nvmem/mtk-efuse.c unsigned int reg, void *_val, size_t bytes) reg 26 drivers/nvmem/mtk-efuse.c *val++ = readl(priv->base + reg + (i++ * 4)); reg 32 drivers/nvmem/mtk-efuse.c unsigned int reg, void *_val, size_t bytes) reg 39 drivers/nvmem/mtk-efuse.c writel(*val++, priv->base + reg + (i++ * 4)); reg 18 drivers/nvmem/qfprom.c unsigned int reg, void *_val, size_t bytes) reg 25 drivers/nvmem/qfprom.c *val++ = readb(priv->base + reg + i++); reg 295 drivers/nvmem/rave-sp-eeprom.c u32 reg[2], size; reg 297 drivers/nvmem/rave-sp-eeprom.c if (of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg))) { reg 302 drivers/nvmem/rave-sp-eeprom.c size = reg[1]; reg 316 drivers/nvmem/rave-sp-eeprom.c eeprom->address = reg[0]; reg 20 drivers/nvmem/uniphier-efuse.c unsigned int reg, void *_val, size_t bytes) reg 27 drivers/nvmem/uniphier-efuse.c *val++ = readb(priv->base + reg + offs); reg 151 drivers/nvmem/vf610-ocotp.c u32 reg, *buf = val; reg 163 drivers/nvmem/vf610-ocotp.c reg = readl(base + OCOTP_CTRL_REG); reg 164 drivers/nvmem/vf610-ocotp.c reg &= ~OCOTP_CTRL_ADDR_MASK; reg 165 drivers/nvmem/vf610-ocotp.c reg &= ~OCOTP_CTRL_WR_UNLOCK_MASK; reg 166 drivers/nvmem/vf610-ocotp.c reg |= BF(fuse_addr, OCOTP_CTRL_ADDR); reg 167 drivers/nvmem/vf610-ocotp.c writel(reg, base + OCOTP_CTRL_REG); reg 1000 drivers/of/fdt.c const __be32 *reg, *endp; reg 1008 drivers/of/fdt.c reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l); reg 1009 drivers/of/fdt.c if (reg == NULL) reg 1010 drivers/of/fdt.c reg = of_get_flat_dt_prop(node, "reg", &l); reg 1011 drivers/of/fdt.c if (reg == NULL) reg 1014 drivers/of/fdt.c endp = reg + (l / sizeof(__be32)); reg 1019 drivers/of/fdt.c while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) { reg 1022 drivers/of/fdt.c base = dt_mem_next_cell(dt_root_addr_cells, ®); reg 1023 drivers/of/fdt.c size = dt_mem_next_cell(dt_root_size_cells, ®); reg 167 drivers/of/fdt_address.c const __be32 *reg; reg 175 drivers/of/fdt_address.c reg = fdt_getprop(blob, node_offset, "reg", &len); reg 176 drivers/of/fdt_address.c if (!reg) { reg 195 drivers/of/fdt_address.c memcpy(addr, reg, na * 4); reg 78 drivers/of/platform.c const __be32 *reg; reg 87 drivers/of/platform.c reg = of_get_property(node, "reg", NULL); reg 88 drivers/of/platform.c if (reg && (addr = of_translate_address(node, reg)) != OF_BAD_ADDR) { reg 665 drivers/of/property.c const struct device_node *parent, int port_reg, int reg) reg 673 drivers/of/property.c ((reg == -1) || (endpoint.id == reg))) reg 1964 drivers/of/unittest.c u32 reg, max_reg; reg 1975 drivers/of/unittest.c if (of_property_read_u32(child, "reg", ®)) reg 1977 drivers/of/unittest.c if (max_reg == (u32)-1 || reg > max_reg) reg 1978 drivers/of/unittest.c max_reg = reg; reg 202 drivers/opp/core.c struct regulator *reg; reg 248 drivers/opp/core.c reg = opp_table->regulators[i]; reg 249 drivers/opp/core.c ret = regulator_set_voltage_time(reg, uV[i].min, uV[i].max); reg 628 drivers/opp/core.c static int _set_opp_voltage(struct device *dev, struct regulator *reg, reg 634 drivers/opp/core.c if (IS_ERR(reg)) { reg 636 drivers/opp/core.c PTR_ERR(reg)); reg 643 drivers/opp/core.c ret = regulator_set_voltage_triplet(reg, supply->u_volt_min, reg 674 drivers/opp/core.c struct regulator *reg = opp_table->regulators[0]; reg 685 drivers/opp/core.c ret = _set_opp_voltage(dev, reg, new_supply); reg 697 drivers/opp/core.c ret = _set_opp_voltage(dev, reg, new_supply); reg 711 drivers/opp/core.c _set_opp_voltage(dev, reg, old_supply); reg 1263 drivers/opp/core.c struct regulator *reg; reg 1270 drivers/opp/core.c reg = opp_table->regulators[i]; reg 1272 drivers/opp/core.c if (!regulator_is_supported_voltage(reg, reg 1594 drivers/opp/core.c struct regulator *reg; reg 1620 drivers/opp/core.c reg = regulator_get_optional(dev, names[i]); reg 1621 drivers/opp/core.c if (IS_ERR(reg)) { reg 1622 drivers/opp/core.c ret = PTR_ERR(reg); reg 1629 drivers/opp/core.c opp_table->regulators[i] = reg; reg 218 drivers/opp/ti-opp-supply.c int new_target_uv, struct regulator *reg, reg 255 drivers/opp/ti-opp-supply.c ret = regulator_set_voltage_triplet(reg, reg 173 drivers/parisc/iosapic.c static inline unsigned int iosapic_read(void __iomem *iosapic, unsigned int reg) reg 175 drivers/parisc/iosapic.c writel(reg, iosapic + IOSAPIC_REG_SELECT); reg 179 drivers/parisc/iosapic.c static inline void iosapic_write(void __iomem *iosapic, unsigned int reg, u32 val) reg 181 drivers/parisc/iosapic.c writel(reg, iosapic + IOSAPIC_REG_SELECT); reg 337 drivers/parisc/lba_pci.c lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size) reg 351 drivers/parisc/lba_pci.c LBA_CFG_ADDR_SETUP(d, tok | reg); reg 353 drivers/parisc/lba_pci.c case 1: data = (u32) READ_REG8(data_reg + (reg & 3)); break; reg 354 drivers/parisc/lba_pci.c case 2: data = (u32) READ_REG16(data_reg+ (reg & 2)); break; reg 405 drivers/parisc/lba_pci.c lba_wr_cfg(struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size) reg 414 drivers/parisc/lba_pci.c LBA_CFG_ADDR_SETUP(d, tok | reg); reg 416 drivers/parisc/lba_pci.c case 1: WRITE_REG8 (data, data_reg + (reg & 3)); break; reg 417 drivers/parisc/lba_pci.c case 2: WRITE_REG16(data, data_reg + (reg & 2)); break; reg 2027 drivers/parisc/sba_iommu.c void __iomem *reg = sba->sba_hpa + i*0x18; reg 2029 drivers/parisc/sba_iommu.c base = READ_REG32(reg + LMMIO_DIRECT0_BASE); reg 2033 drivers/parisc/sba_iommu.c size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE); reg 2039 drivers/parisc/sba_iommu.c size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK); reg 125 drivers/pci/controller/dwc/pci-dra7xx.c u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS); reg 127 drivers/pci/controller/dwc/pci-dra7xx.c return !!(reg & LINK_UP); reg 133 drivers/pci/controller/dwc/pci-dra7xx.c u32 reg; reg 135 drivers/pci/controller/dwc/pci-dra7xx.c reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); reg 136 drivers/pci/controller/dwc/pci-dra7xx.c reg &= ~LTSSM_EN; reg 137 drivers/pci/controller/dwc/pci-dra7xx.c dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); reg 144 drivers/pci/controller/dwc/pci-dra7xx.c u32 reg; reg 154 drivers/pci/controller/dwc/pci-dra7xx.c 4, ®); reg 155 drivers/pci/controller/dwc/pci-dra7xx.c if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { reg 156 drivers/pci/controller/dwc/pci-dra7xx.c reg &= ~((u32)PCI_EXP_LNKCAP_SLS); reg 157 drivers/pci/controller/dwc/pci-dra7xx.c reg |= PCI_EXP_LNKCAP_SLS_2_5GB; reg 159 drivers/pci/controller/dwc/pci-dra7xx.c PCI_EXP_LNKCAP, 4, reg); reg 163 drivers/pci/controller/dwc/pci-dra7xx.c 2, ®); reg 164 drivers/pci/controller/dwc/pci-dra7xx.c if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { reg 165 drivers/pci/controller/dwc/pci-dra7xx.c reg &= ~((u32)PCI_EXP_LNKCAP_SLS); reg 166 drivers/pci/controller/dwc/pci-dra7xx.c reg |= PCI_EXP_LNKCAP_SLS_2_5GB; reg 168 drivers/pci/controller/dwc/pci-dra7xx.c PCI_EXP_LNKCTL2, 2, reg); reg 172 drivers/pci/controller/dwc/pci-dra7xx.c reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); reg 173 drivers/pci/controller/dwc/pci-dra7xx.c reg |= LTSSM_EN; reg 174 drivers/pci/controller/dwc/pci-dra7xx.c dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); reg 265 drivers/pci/controller/dwc/pci-dra7xx.c unsigned long reg; reg 268 drivers/pci/controller/dwc/pci-dra7xx.c reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI); reg 270 drivers/pci/controller/dwc/pci-dra7xx.c switch (reg) { reg 278 drivers/pci/controller/dwc/pci-dra7xx.c for_each_set_bit(bit, ®, PCI_NUM_INTX) { reg 286 drivers/pci/controller/dwc/pci-dra7xx.c dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg); reg 297 drivers/pci/controller/dwc/pci-dra7xx.c u32 reg; reg 299 drivers/pci/controller/dwc/pci-dra7xx.c reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN); reg 301 drivers/pci/controller/dwc/pci-dra7xx.c if (reg & ERR_SYS) reg 304 drivers/pci/controller/dwc/pci-dra7xx.c if (reg & ERR_FATAL) reg 307 drivers/pci/controller/dwc/pci-dra7xx.c if (reg & ERR_NONFATAL) reg 310 drivers/pci/controller/dwc/pci-dra7xx.c if (reg & ERR_COR) reg 313 drivers/pci/controller/dwc/pci-dra7xx.c if (reg & ERR_AXI) reg 316 drivers/pci/controller/dwc/pci-dra7xx.c if (reg & ERR_ECRC) reg 319 drivers/pci/controller/dwc/pci-dra7xx.c if (reg & PME_TURN_OFF) reg 323 drivers/pci/controller/dwc/pci-dra7xx.c if (reg & PME_TO_ACK) reg 327 drivers/pci/controller/dwc/pci-dra7xx.c if (reg & PM_PME) reg 330 drivers/pci/controller/dwc/pci-dra7xx.c if (reg & LINK_REQ_RST) reg 333 drivers/pci/controller/dwc/pci-dra7xx.c if (reg & LINK_UP_EVT) { reg 339 drivers/pci/controller/dwc/pci-dra7xx.c if (reg & CFG_BME_EVT) reg 342 drivers/pci/controller/dwc/pci-dra7xx.c if (reg & CFG_MSE_EVT) reg 345 drivers/pci/controller/dwc/pci-dra7xx.c dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg); reg 372 drivers/pci/controller/dwc/pci-dra7xx.c u32 reg; reg 374 drivers/pci/controller/dwc/pci-dra7xx.c reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT; reg 375 drivers/pci/controller/dwc/pci-dra7xx.c reg |= MSI_REQ_GRANT; reg 376 drivers/pci/controller/dwc/pci-dra7xx.c dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg); reg 676 drivers/pci/controller/dwc/pci-dra7xx.c u32 reg; reg 786 drivers/pci/controller/dwc/pci-dra7xx.c reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); reg 787 drivers/pci/controller/dwc/pci-dra7xx.c reg &= ~LTSSM_EN; reg 788 drivers/pci/controller/dwc/pci-dra7xx.c dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); reg 164 drivers/pci/controller/dwc/pci-exynos.c static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) reg 166 drivers/pci/controller/dwc/pci-exynos.c writel(val, base + reg); reg 169 drivers/pci/controller/dwc/pci-exynos.c static u32 exynos_pcie_readl(void __iomem *base, u32 reg) reg 171 drivers/pci/controller/dwc/pci-exynos.c return readl(base + reg); reg 320 drivers/pci/controller/dwc/pci-exynos.c u32 reg, size_t size) reg 326 drivers/pci/controller/dwc/pci-exynos.c dw_pcie_read(base + reg, size, &val); reg 332 drivers/pci/controller/dwc/pci-exynos.c u32 reg, size_t size, u32 val) reg 337 drivers/pci/controller/dwc/pci-exynos.c dw_pcie_write(base + reg, size, val); reg 308 drivers/pci/controller/dwc/pci-imx6.c int reg = (instr >> 12) & 15; reg 322 drivers/pci/controller/dwc/pci-imx6.c regs->uregs[reg] = val; reg 328 drivers/pci/controller/dwc/pci-imx6.c regs->uregs[reg] = -1; reg 293 drivers/pci/controller/dwc/pci-keystone.c u32 reg; reg 296 drivers/pci/controller/dwc/pci-keystone.c reg = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS); reg 297 drivers/pci/controller/dwc/pci-keystone.c if (!reg) reg 300 drivers/pci/controller/dwc/pci-keystone.c if (reg & ERR_SYS) reg 303 drivers/pci/controller/dwc/pci-keystone.c if (reg & ERR_FATAL) reg 306 drivers/pci/controller/dwc/pci-keystone.c if (reg & ERR_NONFATAL) reg 309 drivers/pci/controller/dwc/pci-keystone.c if (reg & ERR_CORR) reg 312 drivers/pci/controller/dwc/pci-keystone.c if (!ks_pcie->is_am6 && (reg & ERR_AXI)) reg 315 drivers/pci/controller/dwc/pci-keystone.c if (reg & ERR_AER || (ks_pcie->is_am6 && (reg & AM6_ERR_AER))) reg 318 drivers/pci/controller/dwc/pci-keystone.c ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, reg); reg 439 drivers/pci/controller/dwc/pci-keystone.c u32 reg; reg 441 drivers/pci/controller/dwc/pci-keystone.c reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | reg 444 drivers/pci/controller/dwc/pci-keystone.c reg |= CFG_TYPE1; reg 445 drivers/pci/controller/dwc/pci-keystone.c ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg); reg 456 drivers/pci/controller/dwc/pci-keystone.c u32 reg; reg 458 drivers/pci/controller/dwc/pci-keystone.c reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | reg 461 drivers/pci/controller/dwc/pci-keystone.c reg |= CFG_TYPE1; reg 462 drivers/pci/controller/dwc/pci-keystone.c ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg); reg 586 drivers/pci/controller/dwc/pci-keystone.c u32 vector, virq, reg, pos; reg 597 drivers/pci/controller/dwc/pci-keystone.c reg = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset)); reg 603 drivers/pci/controller/dwc/pci-keystone.c if (!(reg & BIT(pos))) reg 769 drivers/pci/controller/dwc/pci-keystone.c int reg = (instr >> 12) & 15; reg 771 drivers/pci/controller/dwc/pci-keystone.c regs->uregs[reg] = -1; reg 890 drivers/pci/controller/dwc/pci-keystone.c u32 reg, size_t size) reg 896 drivers/pci/controller/dwc/pci-keystone.c dw_pcie_read(base + reg, size, &val); reg 902 drivers/pci/controller/dwc/pci-keystone.c u32 reg, size_t size, u32 val) reg 907 drivers/pci/controller/dwc/pci-keystone.c dw_pcie_write(base + reg, size, val); reg 268 drivers/pci/controller/dwc/pci-meson.c static inline void meson_elb_writel(struct meson_pcie *mp, u32 val, u32 reg) reg 270 drivers/pci/controller/dwc/pci-meson.c writel(val, mp->mem_res.elbi_base + reg); reg 273 drivers/pci/controller/dwc/pci-meson.c static inline u32 meson_elb_readl(struct meson_pcie *mp, u32 reg) reg 275 drivers/pci/controller/dwc/pci-meson.c return readl(mp->mem_res.elbi_base + reg); reg 278 drivers/pci/controller/dwc/pci-meson.c static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg) reg 280 drivers/pci/controller/dwc/pci-meson.c return readl(mp->mem_res.cfg_base + reg); reg 283 drivers/pci/controller/dwc/pci-meson.c static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg) reg 285 drivers/pci/controller/dwc/pci-meson.c writel(val, mp->mem_res.cfg_base + reg); reg 215 drivers/pci/controller/dwc/pcie-al.c u32 reg; reg 217 drivers/pci/controller/dwc/pcie-al.c reg = FIELD_PREP(CFG_TARGET_BUS_MASK_MASK, mask_target_bus) | reg 222 drivers/pci/controller/dwc/pcie-al.c reg); reg 304 drivers/pci/controller/dwc/pcie-al.c u32 reg; reg 332 drivers/pci/controller/dwc/pcie-al.c reg = cfg_control & reg 335 drivers/pci/controller/dwc/pcie-al.c reg |= FIELD_PREP(CFG_CONTROL_SUBBUS_MASK, subordinate_bus) | reg 338 drivers/pci/controller/dwc/pcie-al.c al_pcie_controller_writel(pcie, cfg_control_offset, reg); reg 145 drivers/pci/controller/dwc/pcie-armada8k.c u32 reg; reg 148 drivers/pci/controller/dwc/pcie-armada8k.c reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG); reg 150 drivers/pci/controller/dwc/pcie-armada8k.c if ((reg & mask) == mask) reg 153 drivers/pci/controller/dwc/pcie-armada8k.c dev_dbg(pci->dev, "No link detected (Global-Status: 0x%08x).\n", reg); reg 160 drivers/pci/controller/dwc/pcie-armada8k.c u32 reg; reg 164 drivers/pci/controller/dwc/pcie-armada8k.c reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); reg 165 drivers/pci/controller/dwc/pcie-armada8k.c reg &= ~(PCIE_APP_LTSSM_EN); reg 166 drivers/pci/controller/dwc/pcie-armada8k.c dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); reg 170 drivers/pci/controller/dwc/pcie-armada8k.c reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); reg 171 drivers/pci/controller/dwc/pcie-armada8k.c reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT); reg 172 drivers/pci/controller/dwc/pcie-armada8k.c reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT; reg 173 drivers/pci/controller/dwc/pcie-armada8k.c dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); reg 180 drivers/pci/controller/dwc/pcie-armada8k.c reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG); reg 181 drivers/pci/controller/dwc/pcie-armada8k.c reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); reg 182 drivers/pci/controller/dwc/pcie-armada8k.c reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; reg 183 drivers/pci/controller/dwc/pcie-armada8k.c dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg); reg 185 drivers/pci/controller/dwc/pcie-armada8k.c reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG); reg 186 drivers/pci/controller/dwc/pcie-armada8k.c reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); reg 187 drivers/pci/controller/dwc/pcie-armada8k.c reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; reg 188 drivers/pci/controller/dwc/pcie-armada8k.c dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg); reg 191 drivers/pci/controller/dwc/pcie-armada8k.c reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG); reg 192 drivers/pci/controller/dwc/pcie-armada8k.c reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | reg 194 drivers/pci/controller/dwc/pcie-armada8k.c dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); reg 198 drivers/pci/controller/dwc/pcie-armada8k.c reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); reg 199 drivers/pci/controller/dwc/pcie-armada8k.c reg |= PCIE_APP_LTSSM_EN; reg 200 drivers/pci/controller/dwc/pcie-armada8k.c dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg); reg 25 drivers/pci/controller/dwc/pcie-designware-ep.c u32 reg; reg 27 drivers/pci/controller/dwc/pcie-designware-ep.c reg = PCI_BASE_ADDRESS_0 + (4 * bar); reg 29 drivers/pci/controller/dwc/pcie-designware-ep.c dw_pcie_writel_dbi2(pci, reg, 0x0); reg 30 drivers/pci/controller/dwc/pcie-designware-ep.c dw_pcie_writel_dbi(pci, reg, 0x0); reg 32 drivers/pci/controller/dwc/pcie-designware-ep.c dw_pcie_writel_dbi2(pci, reg + 4, 0x0); reg 33 drivers/pci/controller/dwc/pcie-designware-ep.c dw_pcie_writel_dbi(pci, reg + 4, 0x0); reg 140 drivers/pci/controller/dwc/pcie-designware-ep.c u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar); reg 153 drivers/pci/controller/dwc/pcie-designware-ep.c dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1)); reg 154 drivers/pci/controller/dwc/pcie-designware-ep.c dw_pcie_writel_dbi(pci, reg, flags); reg 157 drivers/pci/controller/dwc/pcie-designware-ep.c dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1)); reg 158 drivers/pci/controller/dwc/pcie-designware-ep.c dw_pcie_writel_dbi(pci, reg + 4, 0); reg 218 drivers/pci/controller/dwc/pcie-designware-ep.c u32 val, reg; reg 223 drivers/pci/controller/dwc/pcie-designware-ep.c reg = ep->msi_cap + PCI_MSI_FLAGS; reg 224 drivers/pci/controller/dwc/pcie-designware-ep.c val = dw_pcie_readw_dbi(pci, reg); reg 237 drivers/pci/controller/dwc/pcie-designware-ep.c u32 val, reg; reg 242 drivers/pci/controller/dwc/pcie-designware-ep.c reg = ep->msi_cap + PCI_MSI_FLAGS; reg 243 drivers/pci/controller/dwc/pcie-designware-ep.c val = dw_pcie_readw_dbi(pci, reg); reg 247 drivers/pci/controller/dwc/pcie-designware-ep.c dw_pcie_writew_dbi(pci, reg, val); reg 257 drivers/pci/controller/dwc/pcie-designware-ep.c u32 val, reg; reg 262 drivers/pci/controller/dwc/pcie-designware-ep.c reg = ep->msix_cap + PCI_MSIX_FLAGS; reg 263 drivers/pci/controller/dwc/pcie-designware-ep.c val = dw_pcie_readw_dbi(pci, reg); reg 276 drivers/pci/controller/dwc/pcie-designware-ep.c u32 val, reg; reg 281 drivers/pci/controller/dwc/pcie-designware-ep.c reg = ep->msix_cap + PCI_MSIX_FLAGS; reg 282 drivers/pci/controller/dwc/pcie-designware-ep.c val = dw_pcie_readw_dbi(pci, reg); reg 286 drivers/pci/controller/dwc/pcie-designware-ep.c dw_pcie_writew_dbi(pci, reg, val); reg 369 drivers/pci/controller/dwc/pcie-designware-ep.c u32 msg_addr_lower, msg_addr_upper, reg; reg 378 drivers/pci/controller/dwc/pcie-designware-ep.c reg = ep->msi_cap + PCI_MSI_FLAGS; reg 379 drivers/pci/controller/dwc/pcie-designware-ep.c msg_ctrl = dw_pcie_readw_dbi(pci, reg); reg 381 drivers/pci/controller/dwc/pcie-designware-ep.c reg = ep->msi_cap + PCI_MSI_ADDRESS_LO; reg 382 drivers/pci/controller/dwc/pcie-designware-ep.c msg_addr_lower = dw_pcie_readl_dbi(pci, reg); reg 384 drivers/pci/controller/dwc/pcie-designware-ep.c reg = ep->msi_cap + PCI_MSI_ADDRESS_HI; reg 385 drivers/pci/controller/dwc/pcie-designware-ep.c msg_addr_upper = dw_pcie_readl_dbi(pci, reg); reg 386 drivers/pci/controller/dwc/pcie-designware-ep.c reg = ep->msi_cap + PCI_MSI_DATA_64; reg 387 drivers/pci/controller/dwc/pcie-designware-ep.c msg_data = dw_pcie_readw_dbi(pci, reg); reg 390 drivers/pci/controller/dwc/pcie-designware-ep.c reg = ep->msi_cap + PCI_MSI_DATA_32; reg 391 drivers/pci/controller/dwc/pcie-designware-ep.c msg_data = dw_pcie_readw_dbi(pci, reg); reg 416 drivers/pci/controller/dwc/pcie-designware-ep.c u32 reg, msg_data, vec_ctrl; reg 421 drivers/pci/controller/dwc/pcie-designware-ep.c reg = ep->msix_cap + PCI_MSIX_TABLE; reg 422 drivers/pci/controller/dwc/pcie-designware-ep.c tbl_offset = dw_pcie_readl_dbi(pci, reg); reg 426 drivers/pci/controller/dwc/pcie-designware-ep.c reg = PCI_BASE_ADDRESS_0 + (4 * bir); reg 428 drivers/pci/controller/dwc/pcie-designware-ep.c bar_addr_lower = dw_pcie_readl_dbi(pci, reg); reg 431 drivers/pci/controller/dwc/pcie-designware-ep.c bar_addr_upper = dw_pcie_readl_dbi(pci, reg + 4); reg 499 drivers/pci/controller/dwc/pcie-designware-ep.c u32 reg; reg 596 drivers/pci/controller/dwc/pcie-designware-ep.c reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); reg 597 drivers/pci/controller/dwc/pcie-designware-ep.c nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> reg 26 drivers/pci/controller/dwc/pcie-designware.c u16 reg; reg 31 drivers/pci/controller/dwc/pcie-designware.c reg = dw_pcie_readw_dbi(pci, cap_ptr); reg 32 drivers/pci/controller/dwc/pcie-designware.c cap_id = (reg & 0x00ff); reg 40 drivers/pci/controller/dwc/pcie-designware.c next_cap_ptr = (reg & 0xff00) >> 8; reg 47 drivers/pci/controller/dwc/pcie-designware.c u16 reg; reg 49 drivers/pci/controller/dwc/pcie-designware.c reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); reg 50 drivers/pci/controller/dwc/pcie-designware.c next_cap_ptr = (reg & 0x00ff); reg 137 drivers/pci/controller/dwc/pcie-designware.c u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size) reg 143 drivers/pci/controller/dwc/pcie-designware.c return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); reg 145 drivers/pci/controller/dwc/pcie-designware.c ret = dw_pcie_read(pci->dbi_base + reg, size, &val); reg 153 drivers/pci/controller/dwc/pcie-designware.c void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val) reg 158 drivers/pci/controller/dwc/pcie-designware.c pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); reg 162 drivers/pci/controller/dwc/pcie-designware.c ret = dw_pcie_write(pci->dbi_base + reg, size, val); reg 168 drivers/pci/controller/dwc/pcie-designware.c u32 dw_pcie_read_dbi2(struct dw_pcie *pci, u32 reg, size_t size) reg 174 drivers/pci/controller/dwc/pcie-designware.c return pci->ops->read_dbi2(pci, pci->dbi_base2, reg, size); reg 176 drivers/pci/controller/dwc/pcie-designware.c ret = dw_pcie_read(pci->dbi_base2 + reg, size, &val); reg 183 drivers/pci/controller/dwc/pcie-designware.c void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) reg 188 drivers/pci/controller/dwc/pcie-designware.c pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); reg 192 drivers/pci/controller/dwc/pcie-designware.c ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); reg 197 drivers/pci/controller/dwc/pcie-designware.c u32 dw_pcie_read_atu(struct dw_pcie *pci, u32 reg, size_t size) reg 203 drivers/pci/controller/dwc/pcie-designware.c return pci->ops->read_dbi(pci, pci->atu_base, reg, size); reg 205 drivers/pci/controller/dwc/pcie-designware.c ret = dw_pcie_read(pci->atu_base + reg, size, &val); reg 212 drivers/pci/controller/dwc/pcie-designware.c void dw_pcie_write_atu(struct dw_pcie *pci, u32 reg, size_t size, u32 val) reg 217 drivers/pci/controller/dwc/pcie-designware.c pci->ops->write_dbi(pci, pci->atu_base, reg, size, val); reg 221 drivers/pci/controller/dwc/pcie-designware.c ret = dw_pcie_write(pci->atu_base + reg, size, val); reg 226 drivers/pci/controller/dwc/pcie-designware.c static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg) reg 230 drivers/pci/controller/dwc/pcie-designware.c return dw_pcie_readl_atu(pci, offset + reg); reg 233 drivers/pci/controller/dwc/pcie-designware.c static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg, reg 238 drivers/pci/controller/dwc/pcie-designware.c dw_pcie_writel_atu(pci, offset + reg, val); reg 320 drivers/pci/controller/dwc/pcie-designware.c static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg) reg 324 drivers/pci/controller/dwc/pcie-designware.c return dw_pcie_readl_atu(pci, offset + reg); reg 327 drivers/pci/controller/dwc/pcie-designware.c static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg, reg 332 drivers/pci/controller/dwc/pcie-designware.c dw_pcie_writel_atu(pci, offset + reg, val); reg 231 drivers/pci/controller/dwc/pcie-designware.h u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, reg 233 drivers/pci/controller/dwc/pcie-designware.h void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, reg 235 drivers/pci/controller/dwc/pcie-designware.h u32 (*read_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, reg 237 drivers/pci/controller/dwc/pcie-designware.h void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, reg 269 drivers/pci/controller/dwc/pcie-designware.h u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size); reg 270 drivers/pci/controller/dwc/pcie-designware.h void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val); reg 271 drivers/pci/controller/dwc/pcie-designware.h u32 dw_pcie_read_dbi2(struct dw_pcie *pci, u32 reg, size_t size); reg 272 drivers/pci/controller/dwc/pcie-designware.h void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val); reg 273 drivers/pci/controller/dwc/pcie-designware.h u32 dw_pcie_read_atu(struct dw_pcie *pci, u32 reg, size_t size); reg 274 drivers/pci/controller/dwc/pcie-designware.h void dw_pcie_write_atu(struct dw_pcie *pci, u32 reg, size_t size, u32 val); reg 286 drivers/pci/controller/dwc/pcie-designware.h static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) reg 288 drivers/pci/controller/dwc/pcie-designware.h dw_pcie_write_dbi(pci, reg, 0x4, val); reg 291 drivers/pci/controller/dwc/pcie-designware.h static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg) reg 293 drivers/pci/controller/dwc/pcie-designware.h return dw_pcie_read_dbi(pci, reg, 0x4); reg 296 drivers/pci/controller/dwc/pcie-designware.h static inline void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val) reg 298 drivers/pci/controller/dwc/pcie-designware.h dw_pcie_write_dbi(pci, reg, 0x2, val); reg 301 drivers/pci/controller/dwc/pcie-designware.h static inline u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg) reg 303 drivers/pci/controller/dwc/pcie-designware.h return dw_pcie_read_dbi(pci, reg, 0x2); reg 306 drivers/pci/controller/dwc/pcie-designware.h static inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val) reg 308 drivers/pci/controller/dwc/pcie-designware.h dw_pcie_write_dbi(pci, reg, 0x1, val); reg 311 drivers/pci/controller/dwc/pcie-designware.h static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg) reg 313 drivers/pci/controller/dwc/pcie-designware.h return dw_pcie_read_dbi(pci, reg, 0x1); reg 316 drivers/pci/controller/dwc/pcie-designware.h static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val) reg 318 drivers/pci/controller/dwc/pcie-designware.h dw_pcie_write_dbi2(pci, reg, 0x4, val); reg 321 drivers/pci/controller/dwc/pcie-designware.h static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg) reg 323 drivers/pci/controller/dwc/pcie-designware.h return dw_pcie_read_dbi2(pci, reg, 0x4); reg 326 drivers/pci/controller/dwc/pcie-designware.h static inline void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val) reg 328 drivers/pci/controller/dwc/pcie-designware.h dw_pcie_write_atu(pci, reg, 0x4, val); reg 331 drivers/pci/controller/dwc/pcie-designware.h static inline u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg) reg 333 drivers/pci/controller/dwc/pcie-designware.h return dw_pcie_read_atu(pci, reg, 0x4); reg 338 drivers/pci/controller/dwc/pcie-designware.h u32 reg; reg 341 drivers/pci/controller/dwc/pcie-designware.h reg = PCIE_MISC_CONTROL_1_OFF; reg 342 drivers/pci/controller/dwc/pcie-designware.h val = dw_pcie_readl_dbi(pci, reg); reg 344 drivers/pci/controller/dwc/pcie-designware.h dw_pcie_writel_dbi(pci, reg, val); reg 349 drivers/pci/controller/dwc/pcie-designware.h u32 reg; reg 352 drivers/pci/controller/dwc/pcie-designware.h reg = PCIE_MISC_CONTROL_1_OFF; reg 353 drivers/pci/controller/dwc/pcie-designware.h val = dw_pcie_readl_dbi(pci, reg); reg 355 drivers/pci/controller/dwc/pcie-designware.h dw_pcie_writel_dbi(pci, reg, val); reg 148 drivers/pci/controller/dwc/pcie-hisi.c u32 reg; reg 154 drivers/pci/controller/dwc/pcie-hisi.c reg = where & ~0x3; reg 155 drivers/pci/controller/dwc/pcie-hisi.c reg_val = dw_pcie_readl_dbi(pci, reg); reg 174 drivers/pci/controller/dwc/pcie-hisi.c u32 reg; reg 179 drivers/pci/controller/dwc/pcie-hisi.c reg = where & ~0x3; reg 181 drivers/pci/controller/dwc/pcie-hisi.c dw_pcie_writel_dbi(pci, reg, val); reg 183 drivers/pci/controller/dwc/pcie-hisi.c reg_val = dw_pcie_readl_dbi(pci, reg); reg 185 drivers/pci/controller/dwc/pcie-hisi.c dw_pcie_writel_dbi(pci, reg, reg_val); reg 187 drivers/pci/controller/dwc/pcie-hisi.c reg_val = dw_pcie_readl_dbi(pci, reg); reg 189 drivers/pci/controller/dwc/pcie-hisi.c dw_pcie_writel_dbi(pci, reg, reg_val); reg 267 drivers/pci/controller/dwc/pcie-hisi.c struct resource *reg; reg 292 drivers/pci/controller/dwc/pcie-hisi.c reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi"); reg 293 drivers/pci/controller/dwc/pcie-hisi.c pci->dbi_base = devm_pci_remap_cfg_resource(dev, reg); reg 67 drivers/pci/controller/dwc/pcie-histb.c static u32 histb_pcie_readl(struct histb_pcie *histb_pcie, u32 reg) reg 69 drivers/pci/controller/dwc/pcie-histb.c return readl(histb_pcie->ctrl + reg); reg 72 drivers/pci/controller/dwc/pcie-histb.c static void histb_pcie_writel(struct histb_pcie *histb_pcie, u32 reg, u32 val) reg 74 drivers/pci/controller/dwc/pcie-histb.c writel(val, histb_pcie->ctrl + reg); reg 106 drivers/pci/controller/dwc/pcie-histb.c u32 reg, size_t size) reg 111 drivers/pci/controller/dwc/pcie-histb.c dw_pcie_read(base + reg, size, &val); reg 118 drivers/pci/controller/dwc/pcie-histb.c u32 reg, size_t size, u32 val) reg 121 drivers/pci/controller/dwc/pcie-histb.c dw_pcie_write(base + reg, size, val); reg 97 drivers/pci/controller/dwc/pcie-kirin.c u32 val, u32 reg) reg 99 drivers/pci/controller/dwc/pcie-kirin.c writel(val, kirin_pcie->apb_base + reg); reg 102 drivers/pci/controller/dwc/pcie-kirin.c static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg) reg 104 drivers/pci/controller/dwc/pcie-kirin.c return readl(kirin_pcie->apb_base + reg); reg 109 drivers/pci/controller/dwc/pcie-kirin.c u32 val, u32 reg) reg 111 drivers/pci/controller/dwc/pcie-kirin.c writel(val, kirin_pcie->phy_base + reg); reg 114 drivers/pci/controller/dwc/pcie-kirin.c static inline u32 kirin_apb_phy_readl(struct kirin_pcie *kirin_pcie, u32 reg) reg 116 drivers/pci/controller/dwc/pcie-kirin.c return readl(kirin_pcie->phy_base + reg); reg 367 drivers/pci/controller/dwc/pcie-kirin.c u32 reg, size_t size) reg 373 drivers/pci/controller/dwc/pcie-kirin.c dw_pcie_read(base + reg, size, &ret); reg 380 drivers/pci/controller/dwc/pcie-kirin.c u32 reg, size_t size, u32 val) reg 385 drivers/pci/controller/dwc/pcie-kirin.c dw_pcie_write(base + reg, size, val); reg 296 drivers/pci/controller/dwc/pcie-tegra194.c const u32 reg) reg 298 drivers/pci/controller/dwc/pcie-tegra194.c writel_relaxed(value, pcie->appl_base + reg); reg 301 drivers/pci/controller/dwc/pcie-tegra194.c static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg) reg 303 drivers/pci/controller/dwc/pcie-tegra194.c return readl_relaxed(pcie->appl_base + reg); reg 236 drivers/pci/controller/dwc/pcie-uniphier.c unsigned long reg; reg 257 drivers/pci/controller/dwc/pcie-uniphier.c reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val); reg 259 drivers/pci/controller/dwc/pcie-uniphier.c for_each_set_bit(bit, ®, PCI_NUM_INTX) { reg 173 drivers/pci/controller/pci-aardvark.c #define PCIE_CONF_REG(reg) ((reg) & 0xffc) reg 206 drivers/pci/controller/pci-aardvark.c static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) reg 208 drivers/pci/controller/pci-aardvark.c writel(val, pcie->base + reg); reg 211 drivers/pci/controller/pci-aardvark.c static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) reg 213 drivers/pci/controller/pci-aardvark.c return readl(pcie->base + reg); reg 257 drivers/pci/controller/pci-aardvark.c u32 reg; reg 260 drivers/pci/controller/pci-aardvark.c reg = advk_readl(pcie, CTRL_CONFIG_REG); reg 261 drivers/pci/controller/pci-aardvark.c reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); reg 262 drivers/pci/controller/pci-aardvark.c reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT); reg 263 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, CTRL_CONFIG_REG); reg 266 drivers/pci/controller/pci-aardvark.c reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); reg 267 drivers/pci/controller/pci-aardvark.c reg |= (IS_RC_MSK << IS_RC_SHIFT); reg 268 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); reg 271 drivers/pci/controller/pci-aardvark.c reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | reg 275 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); reg 278 drivers/pci/controller/pci-aardvark.c reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | reg 283 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); reg 286 drivers/pci/controller/pci-aardvark.c reg = PCIE_CORE_CTRL2_RESERVED | reg 288 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); reg 291 drivers/pci/controller/pci-aardvark.c reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); reg 292 drivers/pci/controller/pci-aardvark.c reg &= ~PCIE_GEN_SEL_MSK; reg 293 drivers/pci/controller/pci-aardvark.c reg |= SPEED_GEN_2; reg 294 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); reg 297 drivers/pci/controller/pci-aardvark.c reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); reg 298 drivers/pci/controller/pci-aardvark.c reg &= ~LANE_CNT_MSK; reg 299 drivers/pci/controller/pci-aardvark.c reg |= LANE_COUNT_1; reg 300 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); reg 303 drivers/pci/controller/pci-aardvark.c reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); reg 304 drivers/pci/controller/pci-aardvark.c reg |= LINK_TRAINING_EN; reg 305 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); reg 308 drivers/pci/controller/pci-aardvark.c reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); reg 309 drivers/pci/controller/pci-aardvark.c reg |= PCIE_CORE_CTRL2_MSI_ENABLE; reg 310 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); reg 318 drivers/pci/controller/pci-aardvark.c reg = PCIE_ISR0_ALL_MASK; reg 319 drivers/pci/controller/pci-aardvark.c reg &= ~PCIE_ISR0_MSI_INT_PENDING; reg 320 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); reg 328 drivers/pci/controller/pci-aardvark.c reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); reg 329 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); reg 331 drivers/pci/controller/pci-aardvark.c reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); reg 332 drivers/pci/controller/pci-aardvark.c reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE; reg 333 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); reg 336 drivers/pci/controller/pci-aardvark.c reg = advk_readl(pcie, PIO_CTRL); reg 337 drivers/pci/controller/pci-aardvark.c reg |= PIO_CTRL_ADDR_WIN_DISABLE; reg 338 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PIO_CTRL); reg 341 drivers/pci/controller/pci-aardvark.c reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); reg 342 drivers/pci/controller/pci-aardvark.c reg |= PCIE_CORE_LINK_TRAINING; reg 343 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); reg 347 drivers/pci/controller/pci-aardvark.c reg = PCIE_CORE_LINK_L0S_ENTRY | reg 349 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); reg 351 drivers/pci/controller/pci-aardvark.c reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); reg 352 drivers/pci/controller/pci-aardvark.c reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | reg 355 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); reg 361 drivers/pci/controller/pci-aardvark.c u32 reg; reg 365 drivers/pci/controller/pci-aardvark.c reg = advk_readl(pcie, PIO_STAT); reg 366 drivers/pci/controller/pci-aardvark.c status = (reg & PIO_COMPLETION_STATUS_MASK) >> reg 387 drivers/pci/controller/pci-aardvark.c if (reg & PIO_NON_POSTED_REQ) reg 393 drivers/pci/controller/pci-aardvark.c str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); reg 419 drivers/pci/controller/pci-aardvark.c int reg, u32 *value) reg 424 drivers/pci/controller/pci-aardvark.c switch (reg) { reg 444 drivers/pci/controller/pci-aardvark.c u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & reg 456 drivers/pci/controller/pci-aardvark.c *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); reg 466 drivers/pci/controller/pci-aardvark.c int reg, u32 old, u32 new, u32 mask) reg 470 drivers/pci/controller/pci-aardvark.c switch (reg) { reg 472 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); reg 476 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); reg 551 drivers/pci/controller/pci-aardvark.c u32 reg; reg 568 drivers/pci/controller/pci-aardvark.c reg = advk_readl(pcie, PIO_CTRL); reg 569 drivers/pci/controller/pci-aardvark.c reg &= ~PIO_CTRL_TYPE_MASK; reg 571 drivers/pci/controller/pci-aardvark.c reg |= PCIE_CONFIG_RD_TYPE0; reg 573 drivers/pci/controller/pci-aardvark.c reg |= PCIE_CONFIG_RD_TYPE1; reg 574 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PIO_CTRL); reg 577 drivers/pci/controller/pci-aardvark.c reg = PCIE_CONF_ADDR(bus->number, devfn, where); reg 578 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PIO_ADDR_LS); reg 607 drivers/pci/controller/pci-aardvark.c u32 reg; reg 627 drivers/pci/controller/pci-aardvark.c reg = advk_readl(pcie, PIO_CTRL); reg 628 drivers/pci/controller/pci-aardvark.c reg &= ~PIO_CTRL_TYPE_MASK; reg 630 drivers/pci/controller/pci-aardvark.c reg |= PCIE_CONFIG_WR_TYPE0; reg 632 drivers/pci/controller/pci-aardvark.c reg |= PCIE_CONFIG_WR_TYPE1; reg 633 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PIO_CTRL); reg 636 drivers/pci/controller/pci-aardvark.c reg = PCIE_CONF_ADDR(bus->number, devfn, where); reg 637 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PIO_ADDR_LS); reg 642 drivers/pci/controller/pci-aardvark.c reg = val << (8 * offset); reg 646 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, reg, PIO_WR_DATA); reg 273 drivers/pci/controller/pci-ftpci100.c unsigned int reg; reg 275 drivers/pci/controller/pci-ftpci100.c faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®); reg 276 drivers/pci/controller/pci-ftpci100.c reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT); reg 277 drivers/pci/controller/pci-ftpci100.c reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTSTS_SHIFT); reg 278 drivers/pci/controller/pci-ftpci100.c faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg); reg 284 drivers/pci/controller/pci-ftpci100.c unsigned int reg; reg 286 drivers/pci/controller/pci-ftpci100.c faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®); reg 287 drivers/pci/controller/pci-ftpci100.c reg &= ~((0xF << PCI_CTRL2_INTSTS_SHIFT) reg 289 drivers/pci/controller/pci-ftpci100.c faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg); reg 295 drivers/pci/controller/pci-ftpci100.c unsigned int reg; reg 297 drivers/pci/controller/pci-ftpci100.c faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®); reg 298 drivers/pci/controller/pci-ftpci100.c reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT); reg 299 drivers/pci/controller/pci-ftpci100.c reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT); reg 300 drivers/pci/controller/pci-ftpci100.c faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg); reg 307 drivers/pci/controller/pci-ftpci100.c unsigned int irq_stat, reg, i; reg 309 drivers/pci/controller/pci-ftpci100.c faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®); reg 310 drivers/pci/controller/pci-ftpci100.c irq_stat = reg >> PCI_CTRL2_INTSTS_SHIFT; reg 110 drivers/pci/controller/pci-mvebu.c static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg) reg 112 drivers/pci/controller/pci-mvebu.c writel(val, port->base + reg); reg 115 drivers/pci/controller/pci-mvebu.c static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg) reg 117 drivers/pci/controller/pci-mvebu.c return readl(port->base + reg); reg 429 drivers/pci/controller/pci-mvebu.c int reg, u32 *value) reg 433 drivers/pci/controller/pci-mvebu.c switch (reg) { reg 474 drivers/pci/controller/pci-mvebu.c int reg, u32 old, u32 new, u32 mask) reg 479 drivers/pci/controller/pci-mvebu.c switch (reg) { reg 523 drivers/pci/controller/pci-mvebu.c int reg, u32 old, u32 new, u32 mask) reg 527 drivers/pci/controller/pci-mvebu.c switch (reg) { reg 98 drivers/pci/controller/pci-rcar-gen2.c void __iomem *reg; reg 131 drivers/pci/controller/pci-rcar-gen2.c iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG); reg 132 drivers/pci/controller/pci-rcar-gen2.c return priv->reg + (slot >> 1) * 0x100 + where; reg 156 drivers/pci/controller/pci-rcar-gen2.c u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG); reg 163 drivers/pci/controller/pci-rcar-gen2.c priv->reg + RCAR_PCI_INT_STATUS_REG); reg 183 drivers/pci/controller/pci-rcar-gen2.c val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG); reg 185 drivers/pci/controller/pci-rcar-gen2.c iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG); reg 196 drivers/pci/controller/pci-rcar-gen2.c void __iomem *reg = priv->reg; reg 203 drivers/pci/controller/pci-rcar-gen2.c val = ioread32(reg + RCAR_PCI_UNIT_REV_REG); reg 207 drivers/pci/controller/pci-rcar-gen2.c val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD; reg 209 drivers/pci/controller/pci-rcar-gen2.c iowrite32(val, reg + RCAR_USBCTR_REG); reg 236 drivers/pci/controller/pci-rcar-gen2.c iowrite32(val, reg + RCAR_USBCTR_REG); reg 239 drivers/pci/controller/pci-rcar-gen2.c iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG); reg 242 drivers/pci/controller/pci-rcar-gen2.c val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG); reg 245 drivers/pci/controller/pci-rcar-gen2.c iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG); reg 249 drivers/pci/controller/pci-rcar-gen2.c reg + RCAR_PCIAHB_WIN1_CTR_REG); reg 253 drivers/pci/controller/pci-rcar-gen2.c iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG); reg 257 drivers/pci/controller/pci-rcar-gen2.c reg + RCAR_AHBPCI_WIN1_CTR_REG); reg 260 drivers/pci/controller/pci-rcar-gen2.c reg + PCI_BASE_ADDRESS_1); reg 263 drivers/pci/controller/pci-rcar-gen2.c iowrite32(val, reg + PCI_BASE_ADDRESS_0); reg 265 drivers/pci/controller/pci-rcar-gen2.c val = ioread32(reg + PCI_COMMAND); reg 268 drivers/pci/controller/pci-rcar-gen2.c iowrite32(val, reg + PCI_COMMAND); reg 272 drivers/pci/controller/pci-rcar-gen2.c reg + RCAR_PCI_INT_ENABLE_REG); reg 340 drivers/pci/controller/pci-rcar-gen2.c void __iomem *reg; reg 345 drivers/pci/controller/pci-rcar-gen2.c reg = devm_ioremap_resource(dev, cfg_res); reg 346 drivers/pci/controller/pci-rcar-gen2.c if (IS_ERR(reg)) reg 347 drivers/pci/controller/pci-rcar-gen2.c return PTR_ERR(reg); reg 364 drivers/pci/controller/pci-rcar-gen2.c priv->reg = reg; reg 1651 drivers/pci/controller/pci-tegra.c unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4); reg 1653 drivers/pci/controller/pci-tegra.c while (reg) { reg 1654 drivers/pci/controller/pci-tegra.c unsigned int offset = find_first_bit(®, 32); reg 1676 drivers/pci/controller/pci-tegra.c reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4); reg 1818 drivers/pci/controller/pci-tegra.c u32 reg; reg 1836 drivers/pci/controller/pci-tegra.c reg = afi_readl(pcie, AFI_INTR_MASK); reg 1837 drivers/pci/controller/pci-tegra.c reg |= AFI_INTR_MASK_MSI_MASK; reg 1838 drivers/pci/controller/pci-tegra.c afi_writel(pcie, reg, AFI_INTR_MASK); reg 75 drivers/pci/controller/pci-xgene.c static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg) reg 77 drivers/pci/controller/pci-xgene.c return readl(port->csr_base + reg); reg 80 drivers/pci/controller/pci-xgene.c static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val) reg 82 drivers/pci/controller/pci-xgene.c writel(val, port->csr_base + reg); reg 42 drivers/pci/controller/pcie-altera-msi.c const u32 reg) reg 44 drivers/pci/controller/pcie-altera-msi.c writel_relaxed(value, msi->csr_base + reg); reg 47 drivers/pci/controller/pcie-altera-msi.c static inline u32 msi_readl(struct altera_msi *msi, const u32 reg) reg 49 drivers/pci/controller/pcie-altera-msi.c return readl_relaxed(msi->csr_base + reg); reg 45 drivers/pci/controller/pcie-altera.c #define S10_RP_CFG_ADDR(pcie, reg) \ reg 46 drivers/pci/controller/pcie-altera.c (((pcie)->hip_base) + (reg) + (1 << 20)) reg 127 drivers/pci/controller/pcie-altera.c const u32 reg) reg 129 drivers/pci/controller/pcie-altera.c writel_relaxed(value, pcie->cra_base + reg); reg 132 drivers/pci/controller/pcie-altera.c static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg) reg 134 drivers/pci/controller/pcie-altera.c return readl_relaxed(pcie->cra_base + reg); reg 88 drivers/pci/controller/pcie-cadence-ep.c u32 addr0, addr1, reg, cfg, b, aperture, ctrl; reg 130 drivers/pci/controller/pcie-cadence-ep.c reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn); reg 133 drivers/pci/controller/pcie-cadence-ep.c reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn); reg 137 drivers/pci/controller/pcie-cadence-ep.c cfg = cdns_pcie_readl(pcie, reg); reg 142 drivers/pci/controller/pcie-cadence-ep.c cdns_pcie_writel(pcie, reg, cfg); reg 153 drivers/pci/controller/pcie-cadence-ep.c u32 reg, cfg, b, ctrl; reg 156 drivers/pci/controller/pcie-cadence-ep.c reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn); reg 159 drivers/pci/controller/pcie-cadence-ep.c reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn); reg 164 drivers/pci/controller/pcie-cadence-ep.c cfg = cdns_pcie_readl(pcie, reg); reg 168 drivers/pci/controller/pcie-cadence-ep.c cdns_pcie_writel(pcie, reg, cfg); reg 242 drivers/pci/controller/pcie-cadence.h static inline void cdns_pcie_writeb(struct cdns_pcie *pcie, u32 reg, u8 value) reg 244 drivers/pci/controller/pcie-cadence.h writeb(value, pcie->reg_base + reg); reg 247 drivers/pci/controller/pcie-cadence.h static inline void cdns_pcie_writew(struct cdns_pcie *pcie, u32 reg, u16 value) reg 249 drivers/pci/controller/pcie-cadence.h writew(value, pcie->reg_base + reg); reg 252 drivers/pci/controller/pcie-cadence.h static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) reg 254 drivers/pci/controller/pcie-cadence.h writel(value, pcie->reg_base + reg); reg 257 drivers/pci/controller/pcie-cadence.h static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) reg 259 drivers/pci/controller/pcie-cadence.h return readl(pcie->reg_base + reg); reg 264 drivers/pci/controller/pcie-cadence.h u32 reg, u8 value) reg 266 drivers/pci/controller/pcie-cadence.h writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); reg 270 drivers/pci/controller/pcie-cadence.h u32 reg, u16 value) reg 272 drivers/pci/controller/pcie-cadence.h writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); reg 277 drivers/pci/controller/pcie-cadence.h u32 reg, u8 value) reg 279 drivers/pci/controller/pcie-cadence.h writeb(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); reg 283 drivers/pci/controller/pcie-cadence.h u32 reg, u16 value) reg 285 drivers/pci/controller/pcie-cadence.h writew(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); reg 289 drivers/pci/controller/pcie-cadence.h u32 reg, u32 value) reg 291 drivers/pci/controller/pcie-cadence.h writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); reg 294 drivers/pci/controller/pcie-cadence.h static inline u8 cdns_pcie_ep_fn_readb(struct cdns_pcie *pcie, u8 fn, u32 reg) reg 296 drivers/pci/controller/pcie-cadence.h return readb(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); reg 299 drivers/pci/controller/pcie-cadence.h static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg) reg 301 drivers/pci/controller/pcie-cadence.h return readw(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); reg 304 drivers/pci/controller/pcie-cadence.h static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) reg 306 drivers/pci/controller/pcie-cadence.h return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); reg 129 drivers/pci/controller/pcie-iproc-msi.c enum iproc_msi_reg reg, reg 134 drivers/pci/controller/pcie-iproc-msi.c return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]); reg 138 drivers/pci/controller/pcie-iproc-msi.c enum iproc_msi_reg reg, reg 143 drivers/pci/controller/pcie-iproc-msi.c writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]); reg 45 drivers/pci/controller/pcie-iproc-platform.c struct resource reg; reg 60 drivers/pci/controller/pcie-iproc-platform.c ret = of_address_to_resource(np, 0, ®); reg 66 drivers/pci/controller/pcie-iproc-platform.c pcie->base = devm_pci_remap_cfgspace(dev, reg.start, reg 67 drivers/pci/controller/pcie-iproc-platform.c resource_size(®)); reg 72 drivers/pci/controller/pcie-iproc-platform.c pcie->base_addr = reg.start; reg 411 drivers/pci/controller/pcie-iproc.c enum iproc_pcie_reg reg) reg 413 drivers/pci/controller/pcie-iproc.c return pcie->reg_offsets[reg]; reg 417 drivers/pci/controller/pcie-iproc.c enum iproc_pcie_reg reg) reg 419 drivers/pci/controller/pcie-iproc.c u16 offset = iproc_pcie_reg_offset(pcie, reg); reg 428 drivers/pci/controller/pcie-iproc.c enum iproc_pcie_reg reg, u32 val) reg 430 drivers/pci/controller/pcie-iproc.c u16 offset = iproc_pcie_reg_offset(pcie, reg); reg 161 drivers/pci/controller/pcie-rcar.c unsigned int reg) reg 163 drivers/pci/controller/pcie-rcar.c writel(val, pcie->base + reg); reg 166 drivers/pci/controller/pcie-rcar.c static u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg) reg 168 drivers/pci/controller/pcie-rcar.c return readl(pcie->base + reg); reg 199 drivers/pci/controller/pcie-rcar.c unsigned int dev, func, reg, index; reg 203 drivers/pci/controller/pcie-rcar.c reg = where & ~3; reg 204 drivers/pci/controller/pcie-rcar.c index = reg / 4; reg 229 drivers/pci/controller/pcie-rcar.c if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS)) reg 246 drivers/pci/controller/pcie-rcar.c PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR); reg 738 drivers/pci/controller/pcie-rcar.c unsigned long reg; reg 740 drivers/pci/controller/pcie-rcar.c reg = rcar_pci_read_reg(pcie, PCIEMSIFR); reg 743 drivers/pci/controller/pcie-rcar.c if (!reg) reg 746 drivers/pci/controller/pcie-rcar.c while (reg) { reg 747 drivers/pci/controller/pcie-rcar.c unsigned int index = find_first_bit(®, 32); reg 765 drivers/pci/controller/pcie-rcar.c reg = rcar_pci_read_reg(pcie, PCIEMSIFR); reg 169 drivers/pci/controller/pcie-rockchip-ep.c u32 addr0, addr1, reg, cfg, b, aperture, ctrl; reg 204 drivers/pci/controller/pcie-rockchip-ep.c reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn); reg 207 drivers/pci/controller/pcie-rockchip-ep.c reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn); reg 214 drivers/pci/controller/pcie-rockchip-ep.c cfg = rockchip_pcie_read(rockchip, reg); reg 220 drivers/pci/controller/pcie-rockchip-ep.c rockchip_pcie_write(rockchip, cfg, reg); reg 234 drivers/pci/controller/pcie-rockchip-ep.c u32 reg, cfg, b, ctrl; reg 238 drivers/pci/controller/pcie-rockchip-ep.c reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn); reg 241 drivers/pci/controller/pcie-rockchip-ep.c reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn); reg 246 drivers/pci/controller/pcie-rockchip-ep.c cfg = rockchip_pcie_read(rockchip, reg); reg 251 drivers/pci/controller/pcie-rockchip-ep.c rockchip_pcie_write(rockchip, cfg, reg); reg 413 drivers/pci/controller/pcie-rockchip-host.c u32 reg; reg 416 drivers/pci/controller/pcie-rockchip-host.c reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS); reg 417 drivers/pci/controller/pcie-rockchip-host.c if (reg & PCIE_CLIENT_INT_LOCAL) { reg 463 drivers/pci/controller/pcie-rockchip-host.c } else if (reg & PCIE_CLIENT_INT_PHY) { reg 469 drivers/pci/controller/pcie-rockchip-host.c rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL, reg 479 drivers/pci/controller/pcie-rockchip-host.c u32 reg; reg 481 drivers/pci/controller/pcie-rockchip-host.c reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS); reg 482 drivers/pci/controller/pcie-rockchip-host.c if (reg & PCIE_CLIENT_INT_LEGACY_DONE) reg 485 drivers/pci/controller/pcie-rockchip-host.c if (reg & PCIE_CLIENT_INT_MSG) reg 488 drivers/pci/controller/pcie-rockchip-host.c if (reg & PCIE_CLIENT_INT_HOT_RST) reg 491 drivers/pci/controller/pcie-rockchip-host.c if (reg & PCIE_CLIENT_INT_DPA) reg 494 drivers/pci/controller/pcie-rockchip-host.c if (reg & PCIE_CLIENT_INT_FATAL_ERR) reg 497 drivers/pci/controller/pcie-rockchip-host.c if (reg & PCIE_CLIENT_INT_NFATAL_ERR) reg 500 drivers/pci/controller/pcie-rockchip-host.c if (reg & PCIE_CLIENT_INT_CORR_ERR) reg 503 drivers/pci/controller/pcie-rockchip-host.c if (reg & PCIE_CLIENT_INT_PHY) reg 506 drivers/pci/controller/pcie-rockchip-host.c rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE | reg 522 drivers/pci/controller/pcie-rockchip-host.c u32 reg; reg 528 drivers/pci/controller/pcie-rockchip-host.c reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS); reg 529 drivers/pci/controller/pcie-rockchip-host.c reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT; reg 531 drivers/pci/controller/pcie-rockchip-host.c while (reg) { reg 532 drivers/pci/controller/pcie-rockchip-host.c hwirq = ffs(reg) - 1; reg 533 drivers/pci/controller/pcie-rockchip-host.c reg &= ~BIT(hwirq); reg 185 drivers/pci/controller/pcie-rockchip.h #define PCIE_ECAM_ADDR(bus, dev, func, reg) \ reg 187 drivers/pci/controller/pcie-rockchip.h PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg)) reg 318 drivers/pci/controller/pcie-rockchip.h static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg) reg 320 drivers/pci/controller/pcie-rockchip.h return readl(rockchip->apb_base + reg); reg 324 drivers/pci/controller/pcie-rockchip.h u32 reg) reg 326 drivers/pci/controller/pcie-rockchip.h writel(val, rockchip->apb_base + reg); reg 120 drivers/pci/controller/pcie-xilinx.c static inline u32 pcie_read(struct xilinx_pcie_port *port, u32 reg) reg 122 drivers/pci/controller/pcie-xilinx.c return readl(port->reg_base + reg); reg 125 drivers/pci/controller/pcie-xilinx.c static inline void pcie_write(struct xilinx_pcie_port *port, u32 val, u32 reg) reg 127 drivers/pci/controller/pcie-xilinx.c writel(val, port->reg_base + reg); reg 444 drivers/pci/controller/vmd.c unsigned int devfn, int reg, int len) reg 448 drivers/pci/controller/vmd.c (devfn << 12) + reg; reg 461 drivers/pci/controller/vmd.c static int vmd_pci_read(struct pci_bus *bus, unsigned int devfn, int reg, reg 465 drivers/pci/controller/vmd.c char __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); reg 496 drivers/pci/controller/vmd.c static int vmd_pci_write(struct pci_bus *bus, unsigned int devfn, int reg, reg 500 drivers/pci/controller/vmd.c char __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); reg 47 drivers/pci/endpoint/functions/pci-epf-test.c void *reg[6]; reg 86 drivers/pci/endpoint/functions/pci-epf-test.c struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; reg 88 drivers/pci/endpoint/functions/pci-epf-test.c src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, reg->size); reg 91 drivers/pci/endpoint/functions/pci-epf-test.c reg->status = STATUS_SRC_ADDR_INVALID; reg 96 drivers/pci/endpoint/functions/pci-epf-test.c ret = pci_epc_map_addr(epc, epf->func_no, src_phys_addr, reg->src_addr, reg 97 drivers/pci/endpoint/functions/pci-epf-test.c reg->size); reg 100 drivers/pci/endpoint/functions/pci-epf-test.c reg->status = STATUS_SRC_ADDR_INVALID; reg 104 drivers/pci/endpoint/functions/pci-epf-test.c dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, reg->size); reg 107 drivers/pci/endpoint/functions/pci-epf-test.c reg->status = STATUS_DST_ADDR_INVALID; reg 112 drivers/pci/endpoint/functions/pci-epf-test.c ret = pci_epc_map_addr(epc, epf->func_no, dst_phys_addr, reg->dst_addr, reg 113 drivers/pci/endpoint/functions/pci-epf-test.c reg->size); reg 116 drivers/pci/endpoint/functions/pci-epf-test.c reg->status = STATUS_DST_ADDR_INVALID; reg 120 drivers/pci/endpoint/functions/pci-epf-test.c memcpy(dst_addr, src_addr, reg->size); reg 125 drivers/pci/endpoint/functions/pci-epf-test.c pci_epc_mem_free_addr(epc, dst_phys_addr, dst_addr, reg->size); reg 131 drivers/pci/endpoint/functions/pci-epf-test.c pci_epc_mem_free_addr(epc, src_phys_addr, src_addr, reg->size); reg 148 drivers/pci/endpoint/functions/pci-epf-test.c struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; reg 150 drivers/pci/endpoint/functions/pci-epf-test.c src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size); reg 153 drivers/pci/endpoint/functions/pci-epf-test.c reg->status = STATUS_SRC_ADDR_INVALID; reg 158 drivers/pci/endpoint/functions/pci-epf-test.c ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->src_addr, reg 159 drivers/pci/endpoint/functions/pci-epf-test.c reg->size); reg 162 drivers/pci/endpoint/functions/pci-epf-test.c reg->status = STATUS_SRC_ADDR_INVALID; reg 166 drivers/pci/endpoint/functions/pci-epf-test.c buf = kzalloc(reg->size, GFP_KERNEL); reg 172 drivers/pci/endpoint/functions/pci-epf-test.c memcpy_fromio(buf, src_addr, reg->size); reg 174 drivers/pci/endpoint/functions/pci-epf-test.c crc32 = crc32_le(~0, buf, reg->size); reg 175 drivers/pci/endpoint/functions/pci-epf-test.c if (crc32 != reg->checksum) reg 184 drivers/pci/endpoint/functions/pci-epf-test.c pci_epc_mem_free_addr(epc, phys_addr, src_addr, reg->size); reg 200 drivers/pci/endpoint/functions/pci-epf-test.c struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; reg 202 drivers/pci/endpoint/functions/pci-epf-test.c dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size); reg 205 drivers/pci/endpoint/functions/pci-epf-test.c reg->status = STATUS_DST_ADDR_INVALID; reg 210 drivers/pci/endpoint/functions/pci-epf-test.c ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->dst_addr, reg 211 drivers/pci/endpoint/functions/pci-epf-test.c reg->size); reg 214 drivers/pci/endpoint/functions/pci-epf-test.c reg->status = STATUS_DST_ADDR_INVALID; reg 218 drivers/pci/endpoint/functions/pci-epf-test.c buf = kzalloc(reg->size, GFP_KERNEL); reg 224 drivers/pci/endpoint/functions/pci-epf-test.c get_random_bytes(buf, reg->size); reg 225 drivers/pci/endpoint/functions/pci-epf-test.c reg->checksum = crc32_le(~0, buf, reg->size); reg 227 drivers/pci/endpoint/functions/pci-epf-test.c memcpy_toio(dst_addr, buf, reg->size); reg 241 drivers/pci/endpoint/functions/pci-epf-test.c pci_epc_mem_free_addr(epc, phys_addr, dst_addr, reg->size); reg 254 drivers/pci/endpoint/functions/pci-epf-test.c struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; reg 256 drivers/pci/endpoint/functions/pci-epf-test.c reg->status |= STATUS_IRQ_RAISED; reg 285 drivers/pci/endpoint/functions/pci-epf-test.c struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar]; reg 287 drivers/pci/endpoint/functions/pci-epf-test.c command = reg->command; reg 291 drivers/pci/endpoint/functions/pci-epf-test.c reg->command = 0; reg 292 drivers/pci/endpoint/functions/pci-epf-test.c reg->status = 0; reg 294 drivers/pci/endpoint/functions/pci-epf-test.c if (reg->irq_type > IRQ_TYPE_MSIX) { reg 300 drivers/pci/endpoint/functions/pci-epf-test.c reg->status = STATUS_IRQ_RAISED; reg 308 drivers/pci/endpoint/functions/pci-epf-test.c reg->status |= STATUS_WRITE_FAIL; reg 310 drivers/pci/endpoint/functions/pci-epf-test.c reg->status |= STATUS_WRITE_SUCCESS; reg 311 drivers/pci/endpoint/functions/pci-epf-test.c pci_epf_test_raise_irq(epf_test, reg->irq_type, reg 312 drivers/pci/endpoint/functions/pci-epf-test.c reg->irq_number); reg 319 drivers/pci/endpoint/functions/pci-epf-test.c reg->status |= STATUS_READ_SUCCESS; reg 321 drivers/pci/endpoint/functions/pci-epf-test.c reg->status |= STATUS_READ_FAIL; reg 322 drivers/pci/endpoint/functions/pci-epf-test.c pci_epf_test_raise_irq(epf_test, reg->irq_type, reg 323 drivers/pci/endpoint/functions/pci-epf-test.c reg->irq_number); reg 330 drivers/pci/endpoint/functions/pci-epf-test.c reg->status |= STATUS_COPY_SUCCESS; reg 332 drivers/pci/endpoint/functions/pci-epf-test.c reg->status |= STATUS_COPY_FAIL; reg 333 drivers/pci/endpoint/functions/pci-epf-test.c pci_epf_test_raise_irq(epf_test, reg->irq_type, reg 334 drivers/pci/endpoint/functions/pci-epf-test.c reg->irq_number); reg 340 drivers/pci/endpoint/functions/pci-epf-test.c if (reg->irq_number > count || count <= 0) reg 342 drivers/pci/endpoint/functions/pci-epf-test.c reg->status = STATUS_IRQ_RAISED; reg 344 drivers/pci/endpoint/functions/pci-epf-test.c reg->irq_number); reg 350 drivers/pci/endpoint/functions/pci-epf-test.c if (reg->irq_number > count || count <= 0) reg 352 drivers/pci/endpoint/functions/pci-epf-test.c reg->status = STATUS_IRQ_RAISED; reg 354 drivers/pci/endpoint/functions/pci-epf-test.c reg->irq_number); reg 383 drivers/pci/endpoint/functions/pci-epf-test.c if (epf_test->reg[bar]) { reg 385 drivers/pci/endpoint/functions/pci-epf-test.c pci_epf_free_space(epf, epf_test->reg[bar], bar); reg 417 drivers/pci/endpoint/functions/pci-epf-test.c pci_epf_free_space(epf, epf_test->reg[bar], bar); reg 451 drivers/pci/endpoint/functions/pci-epf-test.c epf_test->reg[test_reg_bar] = base; reg 468 drivers/pci/endpoint/functions/pci-epf-test.c epf_test->reg[bar] = base; reg 151 drivers/pci/hotplug/cpcihp_zt5550.c u8 reg; reg 155 drivers/pci/hotplug/cpcihp_zt5550.c reg = readb(csr_int_status); reg 156 drivers/pci/hotplug/cpcihp_zt5550.c if (reg) reg 164 drivers/pci/hotplug/cpcihp_zt5550.c u8 reg; reg 169 drivers/pci/hotplug/cpcihp_zt5550.c reg = readb(csr_int_mask); reg 170 drivers/pci/hotplug/cpcihp_zt5550.c reg = reg & ~ENUM_INT_MASK; reg 171 drivers/pci/hotplug/cpcihp_zt5550.c writeb(reg, csr_int_mask); reg 177 drivers/pci/hotplug/cpcihp_zt5550.c u8 reg; reg 182 drivers/pci/hotplug/cpcihp_zt5550.c reg = readb(csr_int_mask); reg 183 drivers/pci/hotplug/cpcihp_zt5550.c reg = reg | ENUM_INT_MASK; reg 184 drivers/pci/hotplug/cpcihp_zt5550.c writeb(reg, csr_int_mask); reg 1119 drivers/pci/hotplug/cpqphp_ctrl.c u8 reg; reg 1171 drivers/pci/hotplug/cpqphp_ctrl.c reg = 0xF5; reg 1173 drivers/pci/hotplug/cpqphp_ctrl.c reg = 0xF4; reg 1174 drivers/pci/hotplug/cpqphp_ctrl.c pci_write_config_byte(ctrl->pci_dev, 0x41, reg); reg 1180 drivers/pci/hotplug/cpqphp_ctrl.c reg = 0x75; reg 1184 drivers/pci/hotplug/cpqphp_ctrl.c reg = 0x74; reg 1188 drivers/pci/hotplug/cpqphp_ctrl.c reg = 0x73; reg 1192 drivers/pci/hotplug/cpqphp_ctrl.c reg = 0x73; reg 1196 drivers/pci/hotplug/cpqphp_ctrl.c reg = 0x71; reg 1208 drivers/pci/hotplug/cpqphp_ctrl.c pci_write_config_byte(ctrl->pci_dev, 0x41, reg); reg 1211 drivers/pci/hotplug/cpqphp_ctrl.c reg = ~0xF; reg 1212 drivers/pci/hotplug/cpqphp_ctrl.c pci_read_config_byte(ctrl->pci_dev, 0x43, ®); reg 1213 drivers/pci/hotplug/cpqphp_ctrl.c pci_write_config_byte(ctrl->pci_dev, 0x43, reg); reg 172 drivers/pci/hotplug/shpchp_hpc.c static inline u8 shpc_readb(struct controller *ctrl, int reg) reg 174 drivers/pci/hotplug/shpchp_hpc.c return readb(ctrl->creg + reg); reg 177 drivers/pci/hotplug/shpchp_hpc.c static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) reg 179 drivers/pci/hotplug/shpchp_hpc.c writeb(val, ctrl->creg + reg); reg 182 drivers/pci/hotplug/shpchp_hpc.c static inline u16 shpc_readw(struct controller *ctrl, int reg) reg 184 drivers/pci/hotplug/shpchp_hpc.c return readw(ctrl->creg + reg); reg 187 drivers/pci/hotplug/shpchp_hpc.c static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) reg 189 drivers/pci/hotplug/shpchp_hpc.c writew(val, ctrl->creg + reg); reg 192 drivers/pci/hotplug/shpchp_hpc.c static inline u32 shpc_readl(struct controller *ctrl, int reg) reg 194 drivers/pci/hotplug/shpchp_hpc.c return readl(ctrl->creg + reg); reg 197 drivers/pci/hotplug/shpchp_hpc.c static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) reg 199 drivers/pci/hotplug/shpchp_hpc.c writel(val, ctrl->creg + reg); reg 797 drivers/pci/iov.c int reg; reg 832 drivers/pci/iov.c reg = iov->pos + PCI_SRIOV_BAR + 4 * vf_bar; reg 833 drivers/pci/iov.c pci_write_config_dword(dev, reg, new); reg 836 drivers/pci/iov.c pci_write_config_dword(dev, reg + 4, new); reg 155 drivers/pci/of.c u32 reg[5]; reg 158 drivers/pci/of.c error = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg)); reg 162 drivers/pci/of.c return (reg[0] >> 8) & 0xff; reg 498 drivers/pci/pci-acpi.c const struct hpx_type3 *reg) reg 503 drivers/pci/pci-acpi.c if (!(hpx3_device_type(dev) & reg->device_type)) reg 506 drivers/pci/pci-acpi.c if (!(hpx3_function_type(dev) & reg->function_type)) reg 509 drivers/pci/pci-acpi.c switch (reg->config_space_location) { reg 514 drivers/pci/pci-acpi.c pos = pci_find_capability(dev, reg->pci_exp_cap_id); reg 520 drivers/pci/pci-acpi.c pos = pci_find_ext_capability(dev, reg->pci_exp_cap_id); reg 526 drivers/pci/pci-acpi.c reg->pci_exp_cap_ver)) reg 537 drivers/pci/pci-acpi.c pci_read_config_dword(dev, pos + reg->match_offset, &match_reg); reg 539 drivers/pci/pci-acpi.c if ((match_reg & reg->match_mask_and) != reg->match_value) reg 542 drivers/pci/pci-acpi.c pci_read_config_dword(dev, pos + reg->reg_offset, &write_reg); reg 544 drivers/pci/pci-acpi.c write_reg &= reg->reg_mask_and; reg 545 drivers/pci/pci-acpi.c write_reg |= reg->reg_mask_or; reg 550 drivers/pci/pci-acpi.c pci_write_config_dword(dev, pos + reg->reg_offset, write_reg); reg 327 drivers/pci/pci-bridge-emul.c int reg = where & ~3; reg 329 drivers/pci/pci-bridge-emul.c int reg, u32 *value); reg 333 drivers/pci/pci-bridge-emul.c if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) { reg 338 drivers/pci/pci-bridge-emul.c if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) { reg 343 drivers/pci/pci-bridge-emul.c if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { reg 344 drivers/pci/pci-bridge-emul.c reg -= PCI_CAP_PCIE_START; reg 355 drivers/pci/pci-bridge-emul.c ret = read_op(bridge, reg, value); reg 360 drivers/pci/pci-bridge-emul.c *value = cfgspace[reg / 4]; reg 366 drivers/pci/pci-bridge-emul.c *value &= ~behavior[reg / 4].rsvd; reg 386 drivers/pci/pci-bridge-emul.c int reg = where & ~3; reg 388 drivers/pci/pci-bridge-emul.c void (*write_op)(struct pci_bridge_emul *bridge, int reg, reg 393 drivers/pci/pci-bridge-emul.c if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) reg 396 drivers/pci/pci-bridge-emul.c if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) reg 410 drivers/pci/pci-bridge-emul.c ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old); reg 414 drivers/pci/pci-bridge-emul.c if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { reg 415 drivers/pci/pci-bridge-emul.c reg -= PCI_CAP_PCIE_START; reg 426 drivers/pci/pci-bridge-emul.c new = old & (~mask | ~behavior[reg / 4].rw); reg 429 drivers/pci/pci-bridge-emul.c new |= (value << shift) & (behavior[reg / 4].rw & mask); reg 432 drivers/pci/pci-bridge-emul.c new &= ~((value << shift) & (behavior[reg / 4].w1c & mask)); reg 434 drivers/pci/pci-bridge-emul.c cfgspace[reg / 4] = new; reg 437 drivers/pci/pci-bridge-emul.c write_op(bridge, reg, old, new, mask); reg 85 drivers/pci/pci-bridge-emul.h int reg, u32 *value); reg 92 drivers/pci/pci-bridge-emul.h int reg, u32 *value); reg 99 drivers/pci/pci-bridge-emul.h void (*write_base)(struct pci_bridge_emul *bridge, int reg, reg 106 drivers/pci/pci-bridge-emul.h void (*write_pcie)(struct pci_bridge_emul *bridge, int reg, reg 279 drivers/pci/pci.h struct resource *res, unsigned int reg); reg 322 drivers/pci/probe.c unsigned int pos, reg; reg 333 drivers/pci/probe.c reg = PCI_BASE_ADDRESS_0 + (pos << 2); reg 334 drivers/pci/probe.c pos += __pci_read_base(dev, pci_bar_unknown, res, reg); reg 813 drivers/pci/quirks.c static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, reg 819 drivers/pci/quirks.c pci_read_config_dword(dev, reg, &val); reg 857 drivers/pci/quirks.c static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, reg 863 drivers/pci/quirks.c pci_read_config_dword(dev, reg, &val); reg 1251 drivers/pci/quirks.c u8 reg; reg 1253 drivers/pci/quirks.c pci_read_config_byte(dev, 0x41, ®); reg 1254 drivers/pci/quirks.c if (reg & 2) { reg 1255 drivers/pci/quirks.c reg &= ~2; reg 1257 drivers/pci/quirks.c reg); reg 1258 drivers/pci/quirks.c pci_write_config_byte(dev, 0x41, reg); reg 1645 drivers/pci/quirks.c u8 reg; reg 1648 drivers/pci/quirks.c pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); reg 1649 drivers/pci/quirks.c pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); reg 1652 drivers/pci/quirks.c pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); reg 2479 drivers/pci/quirks.c u8 reg; reg 2481 drivers/pci/quirks.c if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { reg 2483 drivers/pci/quirks.c pci_write_config_byte(dev, 0xF4, reg | 0x02); reg 31 drivers/pci/setup-res.c int reg; reg 70 drivers/pci/setup-res.c reg = PCI_BASE_ADDRESS_0 + 4 * resno; reg 81 drivers/pci/setup-res.c reg = dev->rom_base_reg; reg 98 drivers/pci/setup-res.c pci_write_config_dword(dev, reg, new); reg 99 drivers/pci/setup-res.c pci_read_config_dword(dev, reg, &check); reg 108 drivers/pci/setup-res.c pci_write_config_dword(dev, reg + 4, new); reg 109 drivers/pci/setup-res.c pci_read_config_dword(dev, reg + 4, &check); reg 670 drivers/pci/switch/switchtec.c u32 reg; reg 682 drivers/pci/switch/switchtec.c reg = ioread32(&stdev->mmio_part_cfg_all[i].part_event_summary); reg 683 drivers/pci/switch/switchtec.c s->part[i] = reg; reg 687 drivers/pci/switch/switchtec.c reg = ioread16(&stdev->mmio_pff_csr[i].vendor_id); reg 688 drivers/pci/switch/switchtec.c if (reg != PCI_VENDOR_ID_MICROSEMI) reg 691 drivers/pci/switch/switchtec.c reg = ioread32(&stdev->mmio_pff_csr[i].pff_event_summary); reg 692 drivers/pci/switch/switchtec.c s->pff[i] = reg; reg 795 drivers/pci/switch/switchtec.c u32 __iomem *reg; reg 798 drivers/pci/switch/switchtec.c reg = event_hdr_addr(stdev, ctl->event_id, ctl->index); reg 799 drivers/pci/switch/switchtec.c if (IS_ERR(reg)) reg 800 drivers/pci/switch/switchtec.c return PTR_ERR(reg); reg 802 drivers/pci/switch/switchtec.c hdr = ioread32(reg); reg 804 drivers/pci/switch/switchtec.c ctl->data[i] = ioread32(®[i + 1]); reg 829 drivers/pci/switch/switchtec.c iowrite32(hdr, reg); reg 894 drivers/pci/switch/switchtec.c u32 reg; reg 906 drivers/pci/switch/switchtec.c reg = ioread32(&pcfg->usp_pff_inst_id); reg 907 drivers/pci/switch/switchtec.c if (reg == p.pff) { reg 912 drivers/pci/switch/switchtec.c reg = ioread32(&pcfg->vep_pff_inst_id); reg 913 drivers/pci/switch/switchtec.c if (reg == p.pff) { reg 919 drivers/pci/switch/switchtec.c reg = ioread32(&pcfg->dsp_pff_inst_id[i]); reg 920 drivers/pci/switch/switchtec.c if (reg != p.pff) reg 1044 drivers/pci/switch/switchtec.c u32 reg; reg 1049 drivers/pci/switch/switchtec.c reg = ioread32(&stdev->mmio_pff_csr[idx].link_state_hdr); reg 1050 drivers/pci/switch/switchtec.c dev_dbg(&stdev->dev, "link_state: %d->%08x\n", idx, reg); reg 1051 drivers/pci/switch/switchtec.c count = (reg >> 5) & 0xFF; reg 1220 drivers/pci/switch/switchtec.c u32 reg; reg 1224 drivers/pci/switch/switchtec.c reg = ioread32(&stdev->mmio_part_cfg->mrpc_comp_hdr); reg 1225 drivers/pci/switch/switchtec.c if (reg & SWITCHTEC_EVENT_OCCURRED) { reg 1229 drivers/pci/switch/switchtec.c iowrite32(reg, &stdev->mmio_part_cfg->mrpc_comp_hdr); reg 1315 drivers/pci/switch/switchtec.c u32 reg; reg 1319 drivers/pci/switch/switchtec.c reg = ioread16(&stdev->mmio_pff_csr[i].vendor_id); reg 1320 drivers/pci/switch/switchtec.c if (reg != PCI_VENDOR_ID_MICROSEMI) reg 1326 drivers/pci/switch/switchtec.c reg = ioread32(&pcfg->usp_pff_inst_id); reg 1327 drivers/pci/switch/switchtec.c if (reg < SWITCHTEC_MAX_PFF_CSR) reg 1328 drivers/pci/switch/switchtec.c stdev->pff_local[reg] = 1; reg 1330 drivers/pci/switch/switchtec.c reg = ioread32(&pcfg->vep_pff_inst_id); reg 1331 drivers/pci/switch/switchtec.c if (reg < SWITCHTEC_MAX_PFF_CSR) reg 1332 drivers/pci/switch/switchtec.c stdev->pff_local[reg] = 1; reg 1335 drivers/pci/switch/switchtec.c reg = ioread32(&pcfg->dsp_pff_inst_id[i]); reg 1336 drivers/pci/switch/switchtec.c if (reg < SWITCHTEC_MAX_PFF_CSR) reg 1337 drivers/pci/switch/switchtec.c stdev->pff_local[reg] = 1; reg 182 drivers/pcmcia/i82092.c static unsigned char indirect_read(int socket, unsigned short reg) reg 188 drivers/pcmcia/i82092.c reg += socket * 0x40; reg 190 drivers/pcmcia/i82092.c outb(reg,port); reg 197 drivers/pcmcia/i82092.c static unsigned short indirect_read16(int socket, unsigned short reg) reg 203 drivers/pcmcia/i82092.c reg = reg + socket * 0x40; reg 205 drivers/pcmcia/i82092.c outb(reg,port); reg 207 drivers/pcmcia/i82092.c reg++; reg 208 drivers/pcmcia/i82092.c outb(reg,port); reg 215 drivers/pcmcia/i82092.c static void indirect_write(int socket, unsigned short reg, unsigned char value) reg 220 drivers/pcmcia/i82092.c reg = reg + socket * 0x40; reg 222 drivers/pcmcia/i82092.c outb(reg,port); reg 227 drivers/pcmcia/i82092.c static void indirect_setbit(int socket, unsigned short reg, unsigned char mask) reg 233 drivers/pcmcia/i82092.c reg = reg + socket * 0x40; reg 235 drivers/pcmcia/i82092.c outb(reg,port); reg 238 drivers/pcmcia/i82092.c outb(reg,port); reg 244 drivers/pcmcia/i82092.c static void indirect_resetbit(int socket, unsigned short reg, unsigned char mask) reg 250 drivers/pcmcia/i82092.c reg = reg + socket * 0x40; reg 252 drivers/pcmcia/i82092.c outb(reg,port); reg 255 drivers/pcmcia/i82092.c outb(reg,port); reg 260 drivers/pcmcia/i82092.c static void indirect_write16(int socket, unsigned short reg, unsigned short value) reg 266 drivers/pcmcia/i82092.c reg = reg + socket * 0x40; reg 269 drivers/pcmcia/i82092.c outb(reg,port); reg 273 drivers/pcmcia/i82092.c reg++; reg 275 drivers/pcmcia/i82092.c outb(reg,port); reg 464 drivers/pcmcia/i82092.c unsigned char reg; reg 474 drivers/pcmcia/i82092.c reg = 0; reg 476 drivers/pcmcia/i82092.c reg = reg | I365_PC_RESET; reg 478 drivers/pcmcia/i82092.c reg = reg | I365_PC_IOCARD; reg 480 drivers/pcmcia/i82092.c indirect_write(sock,I365_INTCTL,reg); /* IGENC, Interrupt and General Control Register */ reg 484 drivers/pcmcia/i82092.c reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */ reg 488 drivers/pcmcia/i82092.c reg |= I365_PWR_AUTO; /* automatic power mngmnt */ reg 492 drivers/pcmcia/i82092.c reg |= I365_PWR_OUT; /* enable power */ reg 500 drivers/pcmcia/i82092.c reg |= I365_VCC_5V; reg 515 drivers/pcmcia/i82092.c reg |= I365_VPP1_5V | I365_VPP2_5V; reg 519 drivers/pcmcia/i82092.c reg |= I365_VPP1_12V | I365_VPP2_12V; reg 527 drivers/pcmcia/i82092.c if (reg != indirect_read(sock,I365_POWER)) /* only write if changed */ reg 528 drivers/pcmcia/i82092.c indirect_write(sock,I365_POWER,reg); reg 532 drivers/pcmcia/i82092.c reg = 0x00; reg 534 drivers/pcmcia/i82092.c reg |= I365_CSC_DETECT; reg 538 drivers/pcmcia/i82092.c reg |= I365_CSC_STSCHG; reg 541 drivers/pcmcia/i82092.c reg |= I365_CSC_BVD1; reg 543 drivers/pcmcia/i82092.c reg |= I365_CSC_BVD2; reg 545 drivers/pcmcia/i82092.c reg |= I365_CSC_READY; reg 551 drivers/pcmcia/i82092.c indirect_write(sock,I365_CSCINT,reg); reg 217 drivers/pcmcia/i82365.c static u_char i365_get(u_short sock, u_short reg) reg 224 drivers/pcmcia/i82365.c reg = I365_REG(socket[sock].psock, reg); reg 225 drivers/pcmcia/i82365.c outb(reg, port); val = inb(port+1); reg 231 drivers/pcmcia/i82365.c static void i365_set(u_short sock, u_short reg, u_char data) reg 237 drivers/pcmcia/i82365.c u_char val = I365_REG(socket[sock].psock, reg); reg 243 drivers/pcmcia/i82365.c static void i365_bset(u_short sock, u_short reg, u_char mask) reg 245 drivers/pcmcia/i82365.c u_char d = i365_get(sock, reg); reg 247 drivers/pcmcia/i82365.c i365_set(sock, reg, d); reg 250 drivers/pcmcia/i82365.c static void i365_bclr(u_short sock, u_short reg, u_char mask) reg 252 drivers/pcmcia/i82365.c u_char d = i365_get(sock, reg); reg 254 drivers/pcmcia/i82365.c i365_set(sock, reg, d); reg 257 drivers/pcmcia/i82365.c static void i365_bflip(u_short sock, u_short reg, u_char mask, int b) reg 259 drivers/pcmcia/i82365.c u_char d = i365_get(sock, reg); reg 264 drivers/pcmcia/i82365.c i365_set(sock, reg, d); reg 267 drivers/pcmcia/i82365.c static u_short i365_get_pair(u_short sock, u_short reg) reg 270 drivers/pcmcia/i82365.c a = i365_get(sock, reg); reg 271 drivers/pcmcia/i82365.c b = i365_get(sock, reg+1); reg 275 drivers/pcmcia/i82365.c static void i365_set_pair(u_short sock, u_short reg, u_short data) reg 277 drivers/pcmcia/i82365.c i365_set(sock, reg, data & 0xff); reg 278 drivers/pcmcia/i82365.c i365_set(sock, reg+1, data >> 8); reg 925 drivers/pcmcia/i82365.c u_char reg; reg 935 drivers/pcmcia/i82365.c reg = t->intr; reg 936 drivers/pcmcia/i82365.c reg |= state->io_irq; reg 937 drivers/pcmcia/i82365.c reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET; reg 938 drivers/pcmcia/i82365.c reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0; reg 939 drivers/pcmcia/i82365.c i365_set(sock, I365_INTCTL, reg); reg 941 drivers/pcmcia/i82365.c reg = I365_PWR_NORESET; reg 942 drivers/pcmcia/i82365.c if (state->flags & SS_PWR_AUTO) reg |= I365_PWR_AUTO; reg 943 drivers/pcmcia/i82365.c if (state->flags & SS_OUTPUT_ENA) reg |= I365_PWR_OUT; reg 948 drivers/pcmcia/i82365.c reg |= I365_VPP1_12V; reg 950 drivers/pcmcia/i82365.c reg |= I365_VPP1_5V; reg 954 drivers/pcmcia/i82365.c reg |= I365_VCC_5V; reg 964 drivers/pcmcia/i82365.c reg |= I365_VPP1_12V; reg 966 drivers/pcmcia/i82365.c reg |= I365_VPP1_5V; reg 970 drivers/pcmcia/i82365.c reg |= I365_VCC_5V; reg 980 drivers/pcmcia/i82365.c case 33: reg |= I365_VCC_3V; break; reg 981 drivers/pcmcia/i82365.c case 50: reg |= I365_VCC_5V; break; reg 986 drivers/pcmcia/i82365.c case 50: reg |= I365_VPP1_5V; break; reg 987 drivers/pcmcia/i82365.c case 120: reg |= I365_VPP1_12V; break; reg 993 drivers/pcmcia/i82365.c case 50: reg |= I365_VCC_5V; break; reg 998 drivers/pcmcia/i82365.c case 50: reg |= I365_VPP1_5V | I365_VPP2_5V; break; reg 999 drivers/pcmcia/i82365.c case 120: reg |= I365_VPP1_12V | I365_VPP2_12V; break; reg 1004 drivers/pcmcia/i82365.c if (reg != i365_get(sock, I365_POWER)) reg 1005 drivers/pcmcia/i82365.c i365_set(sock, I365_POWER, reg); reg 1015 drivers/pcmcia/i82365.c reg = t->cs_irq << 4; reg 1016 drivers/pcmcia/i82365.c if (state->csc_mask & SS_DETECT) reg |= I365_CSC_DETECT; reg 1018 drivers/pcmcia/i82365.c if (state->csc_mask & SS_STSCHG) reg |= I365_CSC_STSCHG; reg 1020 drivers/pcmcia/i82365.c if (state->csc_mask & SS_BATDEAD) reg |= I365_CSC_BVD1; reg 1021 drivers/pcmcia/i82365.c if (state->csc_mask & SS_BATWARN) reg |= I365_CSC_BVD2; reg 1022 drivers/pcmcia/i82365.c if (state->csc_mask & SS_READY) reg |= I365_CSC_READY; reg 1024 drivers/pcmcia/i82365.c i365_set(sock, I365_CSCINT, reg); reg 134 drivers/pcmcia/i82365.h #define I365_REG(slot, reg) (((slot) << 6) + reg) reg 62 drivers/pcmcia/pd6729.c unsigned short reg) reg 69 drivers/pcmcia/pd6729.c reg += socket->number * 0x40; reg 71 drivers/pcmcia/pd6729.c outb(reg, port); reg 79 drivers/pcmcia/pd6729.c unsigned short reg) reg 86 drivers/pcmcia/pd6729.c reg = reg + socket->number * 0x40; reg 88 drivers/pcmcia/pd6729.c outb(reg, port); reg 90 drivers/pcmcia/pd6729.c reg++; reg 91 drivers/pcmcia/pd6729.c outb(reg, port); reg 98 drivers/pcmcia/pd6729.c static void indirect_write(struct pd6729_socket *socket, unsigned short reg, reg 105 drivers/pcmcia/pd6729.c reg = reg + socket->number * 0x40; reg 107 drivers/pcmcia/pd6729.c outb(reg, port); reg 112 drivers/pcmcia/pd6729.c static void indirect_setbit(struct pd6729_socket *socket, unsigned short reg, reg 120 drivers/pcmcia/pd6729.c reg = reg + socket->number * 0x40; reg 122 drivers/pcmcia/pd6729.c outb(reg, port); reg 125 drivers/pcmcia/pd6729.c outb(reg, port); reg 130 drivers/pcmcia/pd6729.c static void indirect_resetbit(struct pd6729_socket *socket, unsigned short reg, reg 138 drivers/pcmcia/pd6729.c reg = reg + socket->number * 0x40; reg 140 drivers/pcmcia/pd6729.c outb(reg, port); reg 143 drivers/pcmcia/pd6729.c outb(reg, port); reg 148 drivers/pcmcia/pd6729.c static void indirect_write16(struct pd6729_socket *socket, unsigned short reg, reg 156 drivers/pcmcia/pd6729.c reg = reg + socket->number * 0x40; reg 159 drivers/pcmcia/pd6729.c outb(reg, port); reg 163 drivers/pcmcia/pd6729.c reg++; reg 165 drivers/pcmcia/pd6729.c outb(reg, port); reg 298 drivers/pcmcia/pd6729.c unsigned char reg, data; reg 307 drivers/pcmcia/pd6729.c reg = 0; reg 310 drivers/pcmcia/pd6729.c reg |= I365_PC_RESET; reg 312 drivers/pcmcia/pd6729.c reg |= I365_PC_IOCARD; reg 315 drivers/pcmcia/pd6729.c indirect_write(socket, I365_INTCTL, reg); reg 319 drivers/pcmcia/pd6729.c reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */ reg 323 drivers/pcmcia/pd6729.c reg |= I365_PWR_AUTO; /* automatic power mngmnt */ reg 327 drivers/pcmcia/pd6729.c reg |= I365_PWR_OUT; /* enable power */ reg 337 drivers/pcmcia/pd6729.c reg |= I365_VCC_5V; reg 344 drivers/pcmcia/pd6729.c reg |= I365_VCC_5V; reg 363 drivers/pcmcia/pd6729.c reg |= I365_VPP1_5V; reg 367 drivers/pcmcia/pd6729.c reg |= I365_VPP1_12V; reg 376 drivers/pcmcia/pd6729.c if (reg != indirect_read(socket, I365_POWER)) reg 377 drivers/pcmcia/pd6729.c indirect_write(socket, I365_POWER, reg); reg 390 drivers/pcmcia/pd6729.c reg = 0x00; reg 392 drivers/pcmcia/pd6729.c reg |= I365_CSC_DETECT; reg 396 drivers/pcmcia/pd6729.c reg |= I365_CSC_STSCHG; reg 399 drivers/pcmcia/pd6729.c reg |= I365_CSC_BVD1; reg 401 drivers/pcmcia/pd6729.c reg |= I365_CSC_BVD2; reg 403 drivers/pcmcia/pd6729.c reg |= I365_CSC_READY; reg 406 drivers/pcmcia/pd6729.c reg |= 0x30; /* management IRQ: PCI INTA# = "irq 3" */ reg 407 drivers/pcmcia/pd6729.c indirect_write(socket, I365_CSCINT, reg); reg 409 drivers/pcmcia/pd6729.c reg = indirect_read(socket, I365_INTCTL); reg 411 drivers/pcmcia/pd6729.c reg |= 0x03; /* card IRQ: PCI INTA# = "irq 3" */ reg 413 drivers/pcmcia/pd6729.c reg |= socket->card_irq; reg 414 drivers/pcmcia/pd6729.c indirect_write(socket, I365_INTCTL, reg); reg 136 drivers/pcmcia/ricoh.h u8 reg; reg 139 drivers/pcmcia/ricoh.h reg = config_readb(socket, RL5C4XX_MISC_CONTROL); reg 142 drivers/pcmcia/ricoh.h reg |= RL5C4XX_ZV_ENABLE; reg 144 drivers/pcmcia/ricoh.h reg &= ~RL5C4XX_ZV_ENABLE; reg 146 drivers/pcmcia/ricoh.h config_writeb(socket, RL5C4XX_MISC_CONTROL, reg); reg 67 drivers/pcmcia/sa1100_generic.c skt->vcc.reg = devm_regulator_get_optional(dev, "vcc"); reg 68 drivers/pcmcia/sa1100_generic.c if (IS_ERR(skt->vcc.reg)) reg 69 drivers/pcmcia/sa1100_generic.c return PTR_ERR(skt->vcc.reg); reg 71 drivers/pcmcia/sa1100_generic.c if (!skt->vcc.reg) reg 90 drivers/pcmcia/soc_common.c if (!r->reg) reg 98 drivers/pcmcia/soc_common.c ret = regulator_set_voltage(r->reg, v * 100000, v * 100000); reg 100 drivers/pcmcia/soc_common.c int vout = regulator_get_voltage(r->reg) / 100000; reg 108 drivers/pcmcia/soc_common.c ret = regulator_enable(r->reg); reg 110 drivers/pcmcia/soc_common.c ret = regulator_disable(r->reg); reg 26 drivers/pcmcia/soc_common.h struct regulator *reg; reg 124 drivers/pcmcia/tcic.c static u_char tcic_getb(u_char reg) reg 126 drivers/pcmcia/tcic.c u_char val = inb(tcic_base+reg); reg 127 drivers/pcmcia/tcic.c printk(KERN_DEBUG "tcic_getb(%#lx) = %#x\n", tcic_base+reg, val); reg 131 drivers/pcmcia/tcic.c static u_short tcic_getw(u_char reg) reg 133 drivers/pcmcia/tcic.c u_short val = inw(tcic_base+reg); reg 134 drivers/pcmcia/tcic.c printk(KERN_DEBUG "tcic_getw(%#lx) = %#x\n", tcic_base+reg, val); reg 138 drivers/pcmcia/tcic.c static void tcic_setb(u_char reg, u_char data) reg 140 drivers/pcmcia/tcic.c printk(KERN_DEBUG "tcic_setb(%#lx, %#x)\n", tcic_base+reg, data); reg 141 drivers/pcmcia/tcic.c outb(data, tcic_base+reg); reg 144 drivers/pcmcia/tcic.c static void tcic_setw(u_char reg, u_short data) reg 146 drivers/pcmcia/tcic.c printk(KERN_DEBUG "tcic_setw(%#lx, %#x)\n", tcic_base+reg, data); reg 147 drivers/pcmcia/tcic.c outw(data, tcic_base+reg); reg 150 drivers/pcmcia/tcic.c #define tcic_getb(reg) inb(tcic_base+reg) reg 151 drivers/pcmcia/tcic.c #define tcic_getw(reg) inw(tcic_base+reg) reg 152 drivers/pcmcia/tcic.c #define tcic_setb(reg, data) outb(data, tcic_base+reg) reg 153 drivers/pcmcia/tcic.c #define tcic_setw(reg, data) outw(data, tcic_base+reg) reg 156 drivers/pcmcia/tcic.c static void tcic_setl(u_char reg, u_int data) reg 159 drivers/pcmcia/tcic.c printk(KERN_DEBUG "tcic_setl(%#x, %#lx)\n", tcic_base+reg, data); reg 161 drivers/pcmcia/tcic.c outw(data & 0xffff, tcic_base+reg); reg 162 drivers/pcmcia/tcic.c outw(data >> 16, tcic_base+reg+2); reg 165 drivers/pcmcia/tcic.c static void tcic_aux_setb(u_short reg, u_char data) reg 167 drivers/pcmcia/tcic.c u_char mode = (tcic_getb(TCIC_MODE) & TCIC_MODE_PGMMASK) | reg; reg 172 drivers/pcmcia/tcic.c static u_short tcic_aux_getw(u_short reg) reg 174 drivers/pcmcia/tcic.c u_char mode = (tcic_getb(TCIC_MODE) & TCIC_MODE_PGMMASK) | reg; reg 179 drivers/pcmcia/tcic.c static void tcic_aux_setw(u_short reg, u_short data) reg 181 drivers/pcmcia/tcic.c u_char mode = (tcic_getb(TCIC_MODE) & TCIC_MODE_PGMMASK) | reg; reg 596 drivers/pcmcia/tcic.c u_char reg; reg 600 drivers/pcmcia/tcic.c reg = tcic_getb(TCIC_SSTAT); reg 601 drivers/pcmcia/tcic.c *value = (reg & TCIC_SSTAT_CD) ? SS_DETECT : 0; reg 602 drivers/pcmcia/tcic.c *value |= (reg & TCIC_SSTAT_WP) ? SS_WRPROT : 0; reg 604 drivers/pcmcia/tcic.c *value |= (reg & TCIC_SSTAT_LBAT1) ? SS_STSCHG : 0; reg 606 drivers/pcmcia/tcic.c *value |= (reg & TCIC_SSTAT_RDY) ? SS_READY : 0; reg 607 drivers/pcmcia/tcic.c *value |= (reg & TCIC_SSTAT_LBAT1) ? SS_BATDEAD : 0; reg 608 drivers/pcmcia/tcic.c *value |= (reg & TCIC_SSTAT_LBAT2) ? SS_BATWARN : 0; reg 610 drivers/pcmcia/tcic.c reg = tcic_getb(TCIC_PWR); reg 611 drivers/pcmcia/tcic.c if (reg & (TCIC_PWR_VCC(psock)|TCIC_PWR_VPP(psock))) reg 622 drivers/pcmcia/tcic.c u_char reg; reg 630 drivers/pcmcia/tcic.c reg = tcic_getb(TCIC_PWR); reg 631 drivers/pcmcia/tcic.c reg &= ~(TCIC_PWR_VCC(psock) | TCIC_PWR_VPP(psock)); reg 635 drivers/pcmcia/tcic.c case 0: reg |= TCIC_PWR_VCC(psock) | TCIC_PWR_VPP(psock); break; reg 636 drivers/pcmcia/tcic.c case 50: reg |= TCIC_PWR_VCC(psock); break; reg 637 drivers/pcmcia/tcic.c case 120: reg |= TCIC_PWR_VPP(psock); break; reg 643 drivers/pcmcia/tcic.c if (reg != tcic_getb(TCIC_PWR)) reg 644 drivers/pcmcia/tcic.c tcic_setb(TCIC_PWR, reg); reg 646 drivers/pcmcia/tcic.c reg = TCIC_ILOCK_HOLD_CCLK | TCIC_ILOCK_CWAIT; reg 649 drivers/pcmcia/tcic.c reg |= TCIC_ILOCK_CRESENA; reg 653 drivers/pcmcia/tcic.c reg |= TCIC_ILOCK_CRESET; reg 654 drivers/pcmcia/tcic.c tcic_aux_setb(TCIC_AUX_ILOCK, reg); reg 669 drivers/pcmcia/tcic.c reg = TCIC_WAIT_ASYNC | TCIC_WAIT_SENSE | to_cycles(250); reg 670 drivers/pcmcia/tcic.c tcic_aux_setb(TCIC_AUX_WCTL, reg); reg 679 drivers/pcmcia/tcic.c if (state->csc_mask & SS_STSCHG) reg &= ~TCIC_SCF2_MLBAT1; reg 681 drivers/pcmcia/tcic.c if (state->csc_mask & SS_BATDEAD) reg &= ~TCIC_SCF2_MLBAT1; reg 682 drivers/pcmcia/tcic.c if (state->csc_mask & SS_BATWARN) reg &= ~TCIC_SCF2_MLBAT2; reg 683 drivers/pcmcia/tcic.c if (state->csc_mask & SS_READY) reg &= ~TCIC_SCF2_MRDY; reg 206 drivers/pcmcia/ti113x.h u8 reg; reg 211 drivers/pcmcia/ti113x.h reg = config_readb(socket, TI113X_CARD_CONTROL); reg 214 drivers/pcmcia/ti113x.h reg |= TI113X_CCR_ZVENABLE; reg 216 drivers/pcmcia/ti113x.h reg &= ~TI113X_CCR_ZVENABLE; reg 217 drivers/pcmcia/ti113x.h config_writeb(socket, TI113X_CARD_CONTROL, reg); reg 233 drivers/pcmcia/ti113x.h u8 reg; reg 237 drivers/pcmcia/ti113x.h reg = config_readb(socket, TI1250_MULTIMEDIA_CTL); reg 238 drivers/pcmcia/ti113x.h reg |= TI1250_MMC_ZVOUTEN; /* ZV bus enable */ reg 245 drivers/pcmcia/ti113x.h reg &= ~(1<<6); /* Clear select bit */ reg 246 drivers/pcmcia/ti113x.h reg |= shift<<6; /* Favour our socket */ reg 247 drivers/pcmcia/ti113x.h reg |= 1<<shift; /* Socket zoom video on */ reg 251 drivers/pcmcia/ti113x.h reg &= ~(1<<6); /* Clear select bit */ reg 252 drivers/pcmcia/ti113x.h reg |= (1^shift)<<6; /* Favour other socket */ reg 253 drivers/pcmcia/ti113x.h reg &= ~(1<<shift); /* Socket zoon video off */ reg 256 drivers/pcmcia/ti113x.h config_writeb(socket, TI1250_MULTIMEDIA_CTL, reg); reg 296 drivers/pcmcia/ti113x.h u8 new, reg = exca_readb(socket, I365_INTCTL); reg 298 drivers/pcmcia/ti113x.h new = reg & ~I365_INTR_ENA; reg 301 drivers/pcmcia/ti113x.h if (new != reg) reg 308 drivers/pcmcia/ti113x.h u8 new, reg = exca_readb(socket, I365_INTCTL); reg 310 drivers/pcmcia/ti113x.h new = reg & ~I365_INTR_ENA; reg 311 drivers/pcmcia/ti113x.h if (new != reg) reg 113 drivers/pcmcia/topic.h u8 reg_zv, reg; reg 120 drivers/pcmcia/topic.h reg = config_readb(socket, TOPIC97_AUDIO_VIDEO_SWITCH); reg 121 drivers/pcmcia/topic.h reg |= TOPIC97_AVS_AUDIO_CONTROL | TOPIC97_AVS_VIDEO_CONTROL; reg 122 drivers/pcmcia/topic.h config_writeb(socket, TOPIC97_AUDIO_VIDEO_SWITCH, reg); reg 127 drivers/pcmcia/topic.h reg = config_readb(socket, TOPIC97_AUDIO_VIDEO_SWITCH); reg 128 drivers/pcmcia/topic.h reg &= ~(TOPIC97_AVS_AUDIO_CONTROL | TOPIC97_AVS_VIDEO_CONTROL); reg 129 drivers/pcmcia/topic.h config_writeb(socket, TOPIC97_AUDIO_VIDEO_SWITCH, reg); reg 84 drivers/pcmcia/yenta_socket.c static inline u32 cb_readl(struct yenta_socket *socket, unsigned reg) reg 86 drivers/pcmcia/yenta_socket.c u32 val = readl(socket->base + reg); reg 87 drivers/pcmcia/yenta_socket.c debug("%04x %08x\n", socket, reg, val); reg 91 drivers/pcmcia/yenta_socket.c static inline void cb_writel(struct yenta_socket *socket, unsigned reg, u32 val) reg 93 drivers/pcmcia/yenta_socket.c debug("%04x %08x\n", socket, reg, val); reg 94 drivers/pcmcia/yenta_socket.c writel(val, socket->base + reg); reg 95 drivers/pcmcia/yenta_socket.c readl(socket->base + reg); /* avoid problems with PCI write posting */ reg 140 drivers/pcmcia/yenta_socket.c static inline u8 exca_readb(struct yenta_socket *socket, unsigned reg) reg 142 drivers/pcmcia/yenta_socket.c u8 val = readb(socket->base + 0x800 + reg); reg 143 drivers/pcmcia/yenta_socket.c debug("%04x %02x\n", socket, reg, val); reg 147 drivers/pcmcia/yenta_socket.c static inline u8 exca_readw(struct yenta_socket *socket, unsigned reg) reg 150 drivers/pcmcia/yenta_socket.c val = readb(socket->base + 0x800 + reg); reg 151 drivers/pcmcia/yenta_socket.c val |= readb(socket->base + 0x800 + reg + 1) << 8; reg 152 drivers/pcmcia/yenta_socket.c debug("%04x %04x\n", socket, reg, val); reg 156 drivers/pcmcia/yenta_socket.c static inline void exca_writeb(struct yenta_socket *socket, unsigned reg, u8 val) reg 158 drivers/pcmcia/yenta_socket.c debug("%04x %02x\n", socket, reg, val); reg 159 drivers/pcmcia/yenta_socket.c writeb(val, socket->base + 0x800 + reg); reg 160 drivers/pcmcia/yenta_socket.c readb(socket->base + 0x800 + reg); /* PCI write posting... */ reg 163 drivers/pcmcia/yenta_socket.c static void exca_writew(struct yenta_socket *socket, unsigned reg, u16 val) reg 165 drivers/pcmcia/yenta_socket.c debug("%04x %04x\n", socket, reg, val); reg 166 drivers/pcmcia/yenta_socket.c writeb(val, socket->base + 0x800 + reg); reg 167 drivers/pcmcia/yenta_socket.c writeb(val >> 8, socket->base + 0x800 + reg + 1); reg 170 drivers/pcmcia/yenta_socket.c readb(socket->base + 0x800 + reg); reg 171 drivers/pcmcia/yenta_socket.c readb(socket->base + 0x800 + reg + 1); reg 252 drivers/pcmcia/yenta_socket.c u8 reg, old; reg 253 drivers/pcmcia/yenta_socket.c reg = old = exca_readb(socket, I365_POWER); reg 254 drivers/pcmcia/yenta_socket.c reg &= ~(I365_VCC_MASK | I365_VPP1_MASK | I365_VPP2_MASK); reg 260 drivers/pcmcia/yenta_socket.c reg |= I365_VCC_3V; reg 263 drivers/pcmcia/yenta_socket.c reg |= I365_VCC_5V; reg 266 drivers/pcmcia/yenta_socket.c reg = 0; reg 272 drivers/pcmcia/yenta_socket.c reg |= I365_VPP1_5V; reg 275 drivers/pcmcia/yenta_socket.c reg |= I365_VPP1_12V; reg 282 drivers/pcmcia/yenta_socket.c reg |= I365_VCC_5V; reg 285 drivers/pcmcia/yenta_socket.c reg = 0; reg 290 drivers/pcmcia/yenta_socket.c reg |= I365_VPP1_5V | I365_VPP2_5V; reg 293 drivers/pcmcia/yenta_socket.c reg |= I365_VPP1_12V | I365_VPP2_12V; reg 298 drivers/pcmcia/yenta_socket.c if (reg != old) reg 299 drivers/pcmcia/yenta_socket.c exca_writeb(socket, I365_POWER, reg); reg 301 drivers/pcmcia/yenta_socket.c u32 reg = 0; /* CB_SC_STPCLK? */ reg 304 drivers/pcmcia/yenta_socket.c reg = CB_SC_VCC_3V; reg 307 drivers/pcmcia/yenta_socket.c reg = CB_SC_VCC_5V; reg 310 drivers/pcmcia/yenta_socket.c reg = 0; reg 315 drivers/pcmcia/yenta_socket.c reg |= CB_SC_VPP_3V; reg 318 drivers/pcmcia/yenta_socket.c reg |= CB_SC_VPP_5V; reg 321 drivers/pcmcia/yenta_socket.c reg |= CB_SC_VPP_12V; reg 324 drivers/pcmcia/yenta_socket.c if (reg != cb_readl(socket, CB_SOCKET_CONTROL)) reg 325 drivers/pcmcia/yenta_socket.c cb_writel(socket, CB_SOCKET_CONTROL, reg); reg 353 drivers/pcmcia/yenta_socket.c u8 reg; reg 355 drivers/pcmcia/yenta_socket.c reg = exca_readb(socket, I365_INTCTL) & (I365_RING_ENA | I365_INTR_ENA); reg 356 drivers/pcmcia/yenta_socket.c reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET; reg 357 drivers/pcmcia/yenta_socket.c reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0; reg 359 drivers/pcmcia/yenta_socket.c reg |= state->io_irq; reg 362 drivers/pcmcia/yenta_socket.c exca_writeb(socket, I365_INTCTL, reg); reg 364 drivers/pcmcia/yenta_socket.c reg = exca_readb(socket, I365_POWER) & (I365_VCC_MASK|I365_VPP1_MASK); reg 365 drivers/pcmcia/yenta_socket.c reg |= I365_PWR_NORESET; reg 367 drivers/pcmcia/yenta_socket.c reg |= I365_PWR_AUTO; reg 369 drivers/pcmcia/yenta_socket.c reg |= I365_PWR_OUT; reg 370 drivers/pcmcia/yenta_socket.c if (exca_readb(socket, I365_POWER) != reg) reg 371 drivers/pcmcia/yenta_socket.c exca_writeb(socket, I365_POWER, reg); reg 374 drivers/pcmcia/yenta_socket.c reg = exca_readb(socket, I365_CSCINT); reg 375 drivers/pcmcia/yenta_socket.c reg &= I365_CSC_IRQ_MASK; reg 376 drivers/pcmcia/yenta_socket.c reg |= I365_CSC_DETECT; reg 379 drivers/pcmcia/yenta_socket.c reg |= I365_CSC_STSCHG; reg 382 drivers/pcmcia/yenta_socket.c reg |= I365_CSC_BVD1; reg 384 drivers/pcmcia/yenta_socket.c reg |= I365_CSC_BVD2; reg 386 drivers/pcmcia/yenta_socket.c reg |= I365_CSC_READY; reg 388 drivers/pcmcia/yenta_socket.c exca_writeb(socket, I365_CSCINT, reg); reg 918 drivers/pcmcia/yenta_socket.c u8 reg; reg 926 drivers/pcmcia/yenta_socket.c reg = exca_readb(socket, I365_CSCINT); reg 938 drivers/pcmcia/yenta_socket.c exca_writeb(socket, I365_CSCINT, reg); reg 975 drivers/pcmcia/yenta_socket.c u8 reg = 0; reg 990 drivers/pcmcia/yenta_socket.c reg = exca_readb(socket, I365_CSCINT); reg 991 drivers/pcmcia/yenta_socket.c exca_writeb(socket, I365_CSCINT, reg | I365_CSC_STSCHG); reg 1000 drivers/pcmcia/yenta_socket.c exca_writeb(socket, I365_CSCINT, reg); reg 265 drivers/perf/arm_spe_pmu.c u64 reg = 0; reg 267 drivers/perf/arm_spe_pmu.c reg |= ATTR_CFG_GET_FLD(attr, ts_enable) << SYS_PMSCR_EL1_TS_SHIFT; reg 268 drivers/perf/arm_spe_pmu.c reg |= ATTR_CFG_GET_FLD(attr, pa_enable) << SYS_PMSCR_EL1_PA_SHIFT; reg 269 drivers/perf/arm_spe_pmu.c reg |= ATTR_CFG_GET_FLD(attr, pct_enable) << SYS_PMSCR_EL1_PCT_SHIFT; reg 272 drivers/perf/arm_spe_pmu.c reg |= BIT(SYS_PMSCR_EL1_E0SPE_SHIFT); reg 275 drivers/perf/arm_spe_pmu.c reg |= BIT(SYS_PMSCR_EL1_E1SPE_SHIFT); reg 278 drivers/perf/arm_spe_pmu.c reg |= BIT(SYS_PMSCR_EL1_CX_SHIFT); reg 280 drivers/perf/arm_spe_pmu.c return reg; reg 303 drivers/perf/arm_spe_pmu.c u64 reg = 0; reg 307 drivers/perf/arm_spe_pmu.c reg |= ATTR_CFG_GET_FLD(attr, jitter) << SYS_PMSIRR_EL1_RND_SHIFT; reg 308 drivers/perf/arm_spe_pmu.c reg |= event->hw.sample_period; reg 310 drivers/perf/arm_spe_pmu.c return reg; reg 316 drivers/perf/arm_spe_pmu.c u64 reg = 0; reg 318 drivers/perf/arm_spe_pmu.c reg |= ATTR_CFG_GET_FLD(attr, load_filter) << SYS_PMSFCR_EL1_LD_SHIFT; reg 319 drivers/perf/arm_spe_pmu.c reg |= ATTR_CFG_GET_FLD(attr, store_filter) << SYS_PMSFCR_EL1_ST_SHIFT; reg 320 drivers/perf/arm_spe_pmu.c reg |= ATTR_CFG_GET_FLD(attr, branch_filter) << SYS_PMSFCR_EL1_B_SHIFT; reg 322 drivers/perf/arm_spe_pmu.c if (reg) reg 323 drivers/perf/arm_spe_pmu.c reg |= BIT(SYS_PMSFCR_EL1_FT_SHIFT); reg 326 drivers/perf/arm_spe_pmu.c reg |= BIT(SYS_PMSFCR_EL1_FE_SHIFT); reg 329 drivers/perf/arm_spe_pmu.c reg |= BIT(SYS_PMSFCR_EL1_FL_SHIFT); reg 331 drivers/perf/arm_spe_pmu.c return reg; reg 661 drivers/perf/arm_spe_pmu.c u64 reg; reg 689 drivers/perf/arm_spe_pmu.c reg = arm_spe_event_to_pmsfcr(event); reg 690 drivers/perf/arm_spe_pmu.c if ((reg & BIT(SYS_PMSFCR_EL1_FE_SHIFT)) && reg 694 drivers/perf/arm_spe_pmu.c if ((reg & BIT(SYS_PMSFCR_EL1_FT_SHIFT)) && reg 698 drivers/perf/arm_spe_pmu.c if ((reg & BIT(SYS_PMSFCR_EL1_FL_SHIFT)) && reg 702 drivers/perf/arm_spe_pmu.c reg = arm_spe_event_to_pmscr(event); reg 704 drivers/perf/arm_spe_pmu.c (reg & (BIT(SYS_PMSCR_EL1_PA_SHIFT) | reg 714 drivers/perf/arm_spe_pmu.c u64 reg; reg 724 drivers/perf/arm_spe_pmu.c reg = arm_spe_event_to_pmsfcr(event); reg 725 drivers/perf/arm_spe_pmu.c write_sysreg_s(reg, SYS_PMSFCR_EL1); reg 727 drivers/perf/arm_spe_pmu.c reg = arm_spe_event_to_pmsevfr(event); reg 728 drivers/perf/arm_spe_pmu.c write_sysreg_s(reg, SYS_PMSEVFR_EL1); reg 730 drivers/perf/arm_spe_pmu.c reg = arm_spe_event_to_pmslatfr(event); reg 731 drivers/perf/arm_spe_pmu.c write_sysreg_s(reg, SYS_PMSLATFR_EL1); reg 734 drivers/perf/arm_spe_pmu.c reg = arm_spe_event_to_pmsirr(event); reg 735 drivers/perf/arm_spe_pmu.c write_sysreg_s(reg, SYS_PMSIRR_EL1); reg 737 drivers/perf/arm_spe_pmu.c reg = local64_read(&hwc->period_left); reg 738 drivers/perf/arm_spe_pmu.c write_sysreg_s(reg, SYS_PMSICR_EL1); reg 741 drivers/perf/arm_spe_pmu.c reg = arm_spe_event_to_pmscr(event); reg 743 drivers/perf/arm_spe_pmu.c write_sysreg_s(reg, SYS_PMSCR_EL1); reg 928 drivers/perf/arm_spe_pmu.c u64 reg; reg 942 drivers/perf/arm_spe_pmu.c reg = read_sysreg_s(SYS_PMBIDR_EL1); reg 943 drivers/perf/arm_spe_pmu.c if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) { reg 950 drivers/perf/arm_spe_pmu.c fld = reg >> SYS_PMBIDR_EL1_ALIGN_SHIFT & SYS_PMBIDR_EL1_ALIGN_MASK; reg 959 drivers/perf/arm_spe_pmu.c reg = read_sysreg_s(SYS_PMSIDR_EL1); reg 960 drivers/perf/arm_spe_pmu.c if (reg & BIT(SYS_PMSIDR_EL1_FE_SHIFT)) reg 963 drivers/perf/arm_spe_pmu.c if (reg & BIT(SYS_PMSIDR_EL1_FT_SHIFT)) reg 966 drivers/perf/arm_spe_pmu.c if (reg & BIT(SYS_PMSIDR_EL1_FL_SHIFT)) reg 969 drivers/perf/arm_spe_pmu.c if (reg & BIT(SYS_PMSIDR_EL1_ARCHINST_SHIFT)) reg 972 drivers/perf/arm_spe_pmu.c if (reg & BIT(SYS_PMSIDR_EL1_LDS_SHIFT)) reg 975 drivers/perf/arm_spe_pmu.c if (reg & BIT(SYS_PMSIDR_EL1_ERND_SHIFT)) reg 979 drivers/perf/arm_spe_pmu.c fld = reg >> SYS_PMSIDR_EL1_INTERVAL_SHIFT & SYS_PMSIDR_EL1_INTERVAL_MASK; reg 1011 drivers/perf/arm_spe_pmu.c fld = reg >> SYS_PMSIDR_EL1_MAXSIZE_SHIFT & SYS_PMSIDR_EL1_MAXSIZE_MASK; reg 1019 drivers/perf/arm_spe_pmu.c fld = reg >> SYS_PMSIDR_EL1_COUNTSIZE_SHIFT & SYS_PMSIDR_EL1_COUNTSIZE_MASK; reg 325 drivers/perf/fsl_imx8_ddr_perf.c u8 reg = counter * 4 + COUNTER_CNTL; reg 335 drivers/perf/fsl_imx8_ddr_perf.c writel(0, pmu->base + reg); reg 338 drivers/perf/fsl_imx8_ddr_perf.c writel(val, pmu->base + reg); reg 341 drivers/perf/fsl_imx8_ddr_perf.c val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK; reg 342 drivers/perf/fsl_imx8_ddr_perf.c writel(val, pmu->base + reg); reg 81 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c u32 reg, reg_idx, shift, val; reg 90 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c reg = HHA_EVENT_TYPE0 + 4 * (idx / 4); reg 95 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c val = readl(hha_pmu->base + reg); reg 98 drivers/perf/hisilicon/hisi_uncore_hha_pmu.c writel(val, hha_pmu->base + reg); reg 80 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c u32 reg, reg_idx, shift, val; reg 89 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c reg = L3C_EVENT_TYPE0 + (idx / 4) * 4; reg 94 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c val = readl(l3c_pmu->base + reg); reg 97 drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c writel(val, l3c_pmu->base + reg); reg 85 drivers/perf/qcom_l2_pmu.c #define reg_idx(reg, i) (((i) * IA_L2_REG_OFFSET) + reg##_BASE) reg 112 drivers/perf/qcom_l2_pmu.c static void set_l2_indirect_reg(u64 reg, u64 val) reg 117 drivers/perf/qcom_l2_pmu.c write_sysreg_s(reg, L2CPUSRSELR_EL1); reg 131 drivers/perf/qcom_l2_pmu.c static u64 get_l2_indirect_reg(u64 reg) reg 137 drivers/perf/qcom_l2_pmu.c write_sysreg_s(reg, L2CPUSRSELR_EL1); reg 1286 drivers/perf/xgene_pmu.c unsigned int reg; reg 1311 drivers/perf/xgene_pmu.c reg = readl(csw_csr + CSW_CSWCR); reg 1312 drivers/perf/xgene_pmu.c if (reg & CSW_CSWCR_DUALMCB_MASK) { reg 1316 drivers/perf/xgene_pmu.c reg = readl(mcbb_csr + CSW_CSWCR); reg 1318 drivers/perf/xgene_pmu.c (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5; reg 1323 drivers/perf/xgene_pmu.c reg = readl(mcba_csr + CSW_CSWCR); reg 1325 drivers/perf/xgene_pmu.c (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1; reg 1336 drivers/perf/xgene_pmu.c unsigned int reg; reg 1347 drivers/perf/xgene_pmu.c reg = readl(csw_csr + CSW_CSWCR); reg 1348 drivers/perf/xgene_pmu.c mcb0routing = CSW_CSWCR_MCB0_ROUTING(reg); reg 1349 drivers/perf/xgene_pmu.c mcb1routing = CSW_CSWCR_MCB1_ROUTING(reg); reg 1350 drivers/perf/xgene_pmu.c if (reg & CSW_CSWCR_DUALMCB_MASK) { reg 1384 drivers/perf/xgene_pmu.c unsigned int reg; reg 1405 drivers/perf/xgene_pmu.c if (regmap_read(csw_map, CSW_CSWCR, ®)) reg 1408 drivers/perf/xgene_pmu.c if (reg & CSW_CSWCR_DUALMCB_MASK) { reg 1412 drivers/perf/xgene_pmu.c if (regmap_read(mcbb_map, MCBADDRMR, ®)) reg 1415 drivers/perf/xgene_pmu.c (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5; reg 1420 drivers/perf/xgene_pmu.c if (regmap_read(mcba_map, MCBADDRMR, ®)) reg 1423 drivers/perf/xgene_pmu.c (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1; reg 72 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c unsigned int val, reg; reg 75 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, addr); reg 77 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c regmap_write(priv->regmap, PHY_R4, reg); reg 78 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c regmap_write(priv->regmap, PHY_R4, reg); reg 80 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR); reg 88 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c regmap_write(priv->regmap, PHY_R4, reg); reg 136 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c unsigned int val, reg; reg 143 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, data); reg 145 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c regmap_write(priv->regmap, PHY_R4, reg); reg 146 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c regmap_write(priv->regmap, PHY_R4, reg); reg 148 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_DATA); reg 156 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c regmap_write(priv->regmap, PHY_R4, reg); reg 164 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c regmap_write(priv->regmap, PHY_R4, reg); reg 166 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_WRITE); reg 174 drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c regmap_write(priv->regmap, PHY_R4, reg); reg 116 drivers/phy/amlogic/phy-meson8b-usb2.c u32 reg) reg 118 drivers/phy/amlogic/phy-meson8b-usb2.c return readl(phy_priv->regs + reg); reg 122 drivers/phy/amlogic/phy-meson8b-usb2.c u32 reg, u32 mask, u32 value) reg 126 drivers/phy/amlogic/phy-meson8b-usb2.c data = phy_meson8b_usb2_read(phy_priv, reg); reg 130 drivers/phy/amlogic/phy-meson8b-usb2.c writel(data, phy_priv->regs + reg); reg 57 drivers/phy/broadcom/phy-bcm-ns-usb3.c int (*phy_write)(struct bcm_ns_usb3 *usb3, u16 reg, u16 value); reg 73 drivers/phy/broadcom/phy-bcm-ns-usb3.c static int bcm_ns_usb3_mdio_phy_write(struct bcm_ns_usb3 *usb3, u16 reg, reg 76 drivers/phy/broadcom/phy-bcm-ns-usb3.c return usb3->phy_write(usb3, reg, value); reg 189 drivers/phy/broadcom/phy-bcm-ns-usb3.c static int bcm_ns_usb3_mdiodev_phy_write(struct bcm_ns_usb3 *usb3, u16 reg, reg 194 drivers/phy/broadcom/phy-bcm-ns-usb3.c return mdiobus_write(mdiodev->bus, mdiodev->addr, reg, value); reg 286 drivers/phy/broadcom/phy-bcm-ns-usb3.c static int bcm_ns_usb3_platform_phy_write(struct bcm_ns_usb3 *usb3, u16 reg, reg 300 drivers/phy/broadcom/phy-bcm-ns-usb3.c tmp |= reg << 18; reg 257 drivers/phy/broadcom/phy-brcm-sata.c u32 tmp = 0, reg = 0; reg 264 drivers/phy/broadcom/phy-brcm-sata.c reg = AEQ_CONTROL1; reg 269 drivers/phy/broadcom/phy-brcm-sata.c reg = AEQ_FRC_EQ; reg 277 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, AEQRX_REG_BANK_0, reg, ~tmp, tmp); reg 278 drivers/phy/broadcom/phy-brcm-sata.c brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, reg, ~tmp, tmp); reg 129 drivers/phy/broadcom/phy-brcm-usb-init.c #define USB_CTRL_REG(base, reg) ((void *)base + USB_CTRL_##reg) reg 130 drivers/phy/broadcom/phy-brcm-usb-init.c #define USB_XHCI_EC_REG(base, reg) ((void *)base + USB_XHCI_EC_##reg) reg 131 drivers/phy/broadcom/phy-brcm-usb-init.c #define USB_CTRL_MASK(reg, field) \ reg 132 drivers/phy/broadcom/phy-brcm-usb-init.c USB_CTRL_##reg##_##field##_MASK reg 133 drivers/phy/broadcom/phy-brcm-usb-init.c #define USB_CTRL_MASK_FAMILY(params, reg, field) \ reg 134 drivers/phy/broadcom/phy-brcm-usb-init.c (params->usb_reg_bits_map[USB_CTRL_##reg##_##field##_SELECTOR]) reg 136 drivers/phy/broadcom/phy-brcm-usb-init.c #define USB_CTRL_SET_FAMILY(params, reg, field) \ reg 137 drivers/phy/broadcom/phy-brcm-usb-init.c usb_ctrl_set_family(params, USB_CTRL_##reg, \ reg 138 drivers/phy/broadcom/phy-brcm-usb-init.c USB_CTRL_##reg##_##field##_SELECTOR) reg 139 drivers/phy/broadcom/phy-brcm-usb-init.c #define USB_CTRL_UNSET_FAMILY(params, reg, field) \ reg 140 drivers/phy/broadcom/phy-brcm-usb-init.c usb_ctrl_unset_family(params, USB_CTRL_##reg, \ reg 141 drivers/phy/broadcom/phy-brcm-usb-init.c USB_CTRL_##reg##_##field##_SELECTOR) reg 143 drivers/phy/broadcom/phy-brcm-usb-init.c #define USB_CTRL_SET(base, reg, field) \ reg 144 drivers/phy/broadcom/phy-brcm-usb-init.c usb_ctrl_set(USB_CTRL_REG(base, reg), \ reg 145 drivers/phy/broadcom/phy-brcm-usb-init.c USB_CTRL_##reg##_##field##_MASK) reg 146 drivers/phy/broadcom/phy-brcm-usb-init.c #define USB_CTRL_UNSET(base, reg, field) \ reg 147 drivers/phy/broadcom/phy-brcm-usb-init.c usb_ctrl_unset(USB_CTRL_REG(base, reg), \ reg 148 drivers/phy/broadcom/phy-brcm-usb-init.c USB_CTRL_##reg##_##field##_MASK) reg 419 drivers/phy/broadcom/phy-brcm-usb-init.c void *reg; reg 422 drivers/phy/broadcom/phy-brcm-usb-init.c reg = params->ctrl_regs + reg_offset; reg 423 drivers/phy/broadcom/phy-brcm-usb-init.c brcmusb_writel(brcmusb_readl(reg) & ~mask, reg); reg 431 drivers/phy/broadcom/phy-brcm-usb-init.c void *reg; reg 434 drivers/phy/broadcom/phy-brcm-usb-init.c reg = params->ctrl_regs + reg_offset; reg 435 drivers/phy/broadcom/phy-brcm-usb-init.c brcmusb_writel(brcmusb_readl(reg) | mask, reg); reg 438 drivers/phy/broadcom/phy-brcm-usb-init.c static inline void usb_ctrl_set(void __iomem *reg, u32 field) reg 442 drivers/phy/broadcom/phy-brcm-usb-init.c value = brcmusb_readl(reg); reg 443 drivers/phy/broadcom/phy-brcm-usb-init.c brcmusb_writel(value | field, reg); reg 446 drivers/phy/broadcom/phy-brcm-usb-init.c static inline void usb_ctrl_unset(void __iomem *reg, u32 field) reg 450 drivers/phy/broadcom/phy-brcm-usb-init.c value = brcmusb_readl(reg); reg 451 drivers/phy/broadcom/phy-brcm-usb-init.c brcmusb_writel(value & ~field, reg); reg 454 drivers/phy/broadcom/phy-brcm-usb-init.c static u32 brcmusb_usb_mdio_read(void __iomem *ctrl_base, u32 reg, int mode) reg 458 drivers/phy/broadcom/phy-brcm-usb-init.c data = (reg << 16) | mode; reg 472 drivers/phy/broadcom/phy-brcm-usb-init.c static void brcmusb_usb_mdio_write(void __iomem *ctrl_base, u32 reg, reg 477 drivers/phy/broadcom/phy-brcm-usb-init.c data = (reg << 16) | val | mode; reg 781 drivers/phy/broadcom/phy-brcm-usb-init.c u32 reg; reg 794 drivers/phy/broadcom/phy-brcm-usb-init.c reg = brcmusb_readl(USB_CTRL_REG(ctrl, SETUP)); reg 795 drivers/phy/broadcom/phy-brcm-usb-init.c orig_reg = reg; reg 798 drivers/phy/broadcom/phy-brcm-usb-init.c reg &= ~(USB_CTRL_MASK_FAMILY(params, reg 804 drivers/phy/broadcom/phy-brcm-usb-init.c reg &= ~(USB_CTRL_MASK_FAMILY(params, SETUP, reg 808 drivers/phy/broadcom/phy-brcm-usb-init.c reg &= ~(USB_CTRL_MASK(SETUP, IPP) | USB_CTRL_MASK(SETUP, IOC)); reg 810 drivers/phy/broadcom/phy-brcm-usb-init.c reg |= USB_CTRL_MASK(SETUP, IOC); reg 811 drivers/phy/broadcom/phy-brcm-usb-init.c if (params->ipp == 1 && ((reg & USB_CTRL_MASK(SETUP, IPP)) == 0)) reg 812 drivers/phy/broadcom/phy-brcm-usb-init.c reg |= USB_CTRL_MASK(SETUP, IPP); reg 813 drivers/phy/broadcom/phy-brcm-usb-init.c brcmusb_writel(reg, USB_CTRL_REG(ctrl, SETUP)); reg 819 drivers/phy/broadcom/phy-brcm-usb-init.c if (reg != orig_reg) reg 826 drivers/phy/broadcom/phy-brcm-usb-init.c u32 reg = 0; reg 829 drivers/phy/broadcom/phy-brcm-usb-init.c reg = brcmusb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); reg 830 drivers/phy/broadcom/phy-brcm-usb-init.c reg &= USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, reg 833 drivers/phy/broadcom/phy-brcm-usb-init.c return reg; reg 840 drivers/phy/broadcom/phy-brcm-usb-init.c u32 reg; reg 843 drivers/phy/broadcom/phy-brcm-usb-init.c reg = brcmusb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); reg 844 drivers/phy/broadcom/phy-brcm-usb-init.c reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, reg 846 drivers/phy/broadcom/phy-brcm-usb-init.c reg |= mode; reg 847 drivers/phy/broadcom/phy-brcm-usb-init.c brcmusb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); reg 853 drivers/phy/broadcom/phy-brcm-usb-init.c u32 reg; reg 880 drivers/phy/broadcom/phy-brcm-usb-init.c reg = brcmusb_readl(USB_CTRL_REG(ctrl, SETUP)); reg 883 drivers/phy/broadcom/phy-brcm-usb-init.c reg |= USB_CTRL_MASK_FAMILY(params, SETUP, OC3_DISABLE); reg 893 drivers/phy/broadcom/phy-brcm-usb-init.c reg |= USB_CTRL_MASK_FAMILY(params, SETUP, SCB1_EN); reg 895 drivers/phy/broadcom/phy-brcm-usb-init.c reg |= USB_CTRL_MASK_FAMILY(params, SETUP, SCB2_EN); reg 896 drivers/phy/broadcom/phy-brcm-usb-init.c brcmusb_writel(reg, USB_CTRL_REG(ctrl, SETUP)); reg 901 drivers/phy/broadcom/phy-brcm-usb-init.c reg = brcmusb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); reg 902 drivers/phy/broadcom/phy-brcm-usb-init.c reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, reg 904 drivers/phy/broadcom/phy-brcm-usb-init.c reg |= params->mode; reg 905 drivers/phy/broadcom/phy-brcm-usb-init.c brcmusb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1)); reg 929 drivers/phy/broadcom/phy-brcm-usb-init.c u32 reg; reg 943 drivers/phy/broadcom/phy-brcm-usb-init.c reg = brcmusb_readl(USB_CTRL_REG(ctrl, SETUP)); reg 944 drivers/phy/broadcom/phy-brcm-usb-init.c reg &= ~USB_CTRL_SETUP_ENDIAN_BITS; reg 945 drivers/phy/broadcom/phy-brcm-usb-init.c reg |= USB_CTRL_MASK_FAMILY(params, SETUP, ENDIAN); reg 946 drivers/phy/broadcom/phy-brcm-usb-init.c brcmusb_writel(reg, USB_CTRL_REG(ctrl, SETUP)); reg 22 drivers/phy/cadence/cdns-dphy.c #define DPHY_PMA_CMN(reg) (reg) reg 23 drivers/phy/cadence/cdns-dphy.c #define DPHY_PMA_LCLK(reg) (0x100 + (reg)) reg 24 drivers/phy/cadence/cdns-dphy.c #define DPHY_PMA_LDATA(lane, reg) (0x200 + ((lane) * 0x100) + (reg)) reg 25 drivers/phy/cadence/cdns-dphy.c #define DPHY_PMA_RCLK(reg) (0x600 + (reg)) reg 26 drivers/phy/cadence/cdns-dphy.c #define DPHY_PMA_RDATA(lane, reg) (0x700 + ((lane) * 0x100) + (reg)) reg 27 drivers/phy/cadence/cdns-dphy.c #define DPHY_PCS(reg) (0xb00 + (reg)) reg 207 drivers/phy/cadence/phy-cadence-dp.c unsigned int reg; reg 210 drivers/phy/cadence/phy-cadence-dp.c ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_CMN_READY, reg, reg 211 drivers/phy/cadence/phy-cadence-dp.c reg & 1, 0, 500); reg 110 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c static int phy_write(struct phy *phy, u32 value, unsigned int reg) reg 115 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c ret = regmap_write(priv->regmap, reg, value); reg 117 drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c dev_err(&phy->dev, "Failed to write DPHY reg %d: %d\n", reg, reg 44 drivers/phy/hisilicon/phy-hi6220-usb.c struct regmap *reg; reg 50 drivers/phy/hisilicon/phy-hi6220-usb.c struct regmap *reg = priv->reg; reg 56 drivers/phy/hisilicon/phy-hi6220-usb.c regmap_update_bits(reg, SC_PERIPH_RSTEN0, mask, val); reg 57 drivers/phy/hisilicon/phy-hi6220-usb.c regmap_update_bits(reg, SC_PERIPH_RSTDIS0, mask, val); reg 62 drivers/phy/hisilicon/phy-hi6220-usb.c struct regmap *reg = priv->reg; reg 69 drivers/phy/hisilicon/phy-hi6220-usb.c ret = regmap_update_bits(reg, SC_PERIPH_CTRL5, mask, val); reg 76 drivers/phy/hisilicon/phy-hi6220-usb.c ret = regmap_update_bits(reg, SC_PERIPH_CTRL4, mask, val); reg 80 drivers/phy/hisilicon/phy-hi6220-usb.c ret = regmap_write(reg, SC_PERIPH_CTRL8, EYE_PATTERN_PARA); reg 86 drivers/phy/hisilicon/phy-hi6220-usb.c ret = regmap_update_bits(reg, SC_PERIPH_CTRL4, mask, val); reg 129 drivers/phy/hisilicon/phy-hi6220-usb.c priv->reg = syscon_regmap_lookup_by_phandle(dev->of_node, reg 131 drivers/phy/hisilicon/phy-hi6220-usb.c if (IS_ERR(priv->reg)) { reg 133 drivers/phy/hisilicon/phy-hi6220-usb.c return PTR_ERR(priv->reg); reg 46 drivers/phy/hisilicon/phy-hisi-inno-usb2.c void __iomem *reg = priv->mmio; reg 53 drivers/phy/hisilicon/phy-hisi-inno-usb2.c writel(val, reg); reg 56 drivers/phy/hisilicon/phy-hisi-inno-usb2.c writel(val, reg); reg 59 drivers/phy/hisilicon/phy-hisi-inno-usb2.c writel(val, reg); reg 38 drivers/phy/hisilicon/phy-histb-combphy.c u32 reg; reg 55 drivers/phy/hisilicon/phy-histb-combphy.c void __iomem *reg = priv->mmio + COMBPHY_CFG_REG; reg 59 drivers/phy/hisilicon/phy-histb-combphy.c val = readl(reg); reg 64 drivers/phy/hisilicon/phy-histb-combphy.c writel(val, reg); reg 68 drivers/phy/hisilicon/phy-histb-combphy.c writel(val, reg); reg 70 drivers/phy/hisilicon/phy-histb-combphy.c writel(val, reg); reg 101 drivers/phy/hisilicon/phy-histb-combphy.c return regmap_update_bits(syscon, mode->reg, mode->mask, reg 234 drivers/phy/hisilicon/phy-histb-combphy.c mode->reg = vals[0]; reg 204 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c .reg = PCIE_PHY_TX1_CTRL1, reg 208 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c .reg = PCIE_PHY_TX2_CTRL1, reg 212 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c .reg = PCIE_PHY_RX1_CTRL1, reg 220 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c regmap_update_bits(priv->phy_regmap, slices[i].reg, reg 226 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c regmap_update_bits(priv->phy_regmap, slices[i].reg, reg 26 drivers/phy/marvell/phy-armada375-usb2.c void __iomem *reg; reg 34 drivers/phy/marvell/phy-armada375-usb2.c u32 reg; reg 40 drivers/phy/marvell/phy-armada375-usb2.c reg = readl(cluster_phy->reg); reg 42 drivers/phy/marvell/phy-armada375-usb2.c reg |= USB2_PHY_CONFIG_DISABLE; reg 44 drivers/phy/marvell/phy-armada375-usb2.c reg &= ~USB2_PHY_CONFIG_DISABLE; reg 45 drivers/phy/marvell/phy-armada375-usb2.c writel(reg, cluster_phy->reg); reg 127 drivers/phy/marvell/phy-armada375-usb2.c cluster_phy->reg = usb_cluster_base; reg 66 drivers/phy/marvell/phy-berlin-sata.c u32 phy_base, u32 reg, u32 mask, u32 val) reg 71 drivers/phy/marvell/phy-berlin-sata.c writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR); reg 92 drivers/phy/marvell/phy-mvebu-a3700-utmi.c u32 reg; reg 98 drivers/phy/marvell/phy-mvebu-a3700-utmi.c reg = readl(utmi->regs + USB2_PHY_PLL_CTRL_REG0); reg 99 drivers/phy/marvell/phy-mvebu-a3700-utmi.c reg &= ~(PLL_REF_DIV_MASK | PLL_FB_DIV_MASK | PLL_SEL_LPFR_MASK); reg 100 drivers/phy/marvell/phy-mvebu-a3700-utmi.c reg |= (PLL_REF_DIV_5 << PLL_REF_DIV_OFF) | reg 102 drivers/phy/marvell/phy-mvebu-a3700-utmi.c writel(reg, utmi->regs + USB2_PHY_PLL_CTRL_REG0); reg 111 drivers/phy/marvell/phy-mvebu-a3700-utmi.c reg = readl(utmi->regs + USB2_PHY_OTG_CTRL); reg 112 drivers/phy/marvell/phy-mvebu-a3700-utmi.c reg |= PHY_PU_OTG; reg 113 drivers/phy/marvell/phy-mvebu-a3700-utmi.c writel(reg, utmi->regs + USB2_PHY_OTG_CTRL); reg 116 drivers/phy/marvell/phy-mvebu-a3700-utmi.c reg = readl(utmi->regs + USB2_PHY_CHRGR_DETECT); reg 117 drivers/phy/marvell/phy-mvebu-a3700-utmi.c reg &= ~(PHY_CDP_EN | PHY_DCP_EN | PHY_PD_EN | PHY_PU_CHRG_DTC | reg 119 drivers/phy/marvell/phy-mvebu-a3700-utmi.c writel(reg, utmi->regs + USB2_PHY_CHRGR_DETECT); reg 128 drivers/phy/marvell/phy-mvebu-a3700-utmi.c ret = readl_poll_timeout(utmi->regs + USB2_PHY_CAL_CTRL, reg, reg 129 drivers/phy/marvell/phy-mvebu-a3700-utmi.c reg & PHY_PLLCAL_DONE, reg 137 drivers/phy/marvell/phy-mvebu-a3700-utmi.c ret = readl_poll_timeout(utmi->regs + USB2_PHY_CAL_CTRL, reg, reg 138 drivers/phy/marvell/phy-mvebu-a3700-utmi.c reg & PHY_IMPCAL_DONE, reg 146 drivers/phy/marvell/phy-mvebu-a3700-utmi.c ret = readl_poll_timeout(utmi->regs + USB2_RX_CHAN_CTRL1, reg, reg 147 drivers/phy/marvell/phy-mvebu-a3700-utmi.c reg & USB2PHY_SQCAL_DONE, reg 155 drivers/phy/marvell/phy-mvebu-a3700-utmi.c ret = readl_poll_timeout(utmi->regs + USB2_PHY_PLL_CTRL_REG0, reg, reg 156 drivers/phy/marvell/phy-mvebu-a3700-utmi.c reg & PLL_READY, reg 168 drivers/phy/marvell/phy-mvebu-a3700-utmi.c u32 reg; reg 171 drivers/phy/marvell/phy-mvebu-a3700-utmi.c reg = readl(utmi->regs + USB2_PHY_CTRL(usb32)); reg 172 drivers/phy/marvell/phy-mvebu-a3700-utmi.c reg &= ~(RB_USB2PHY_PU | RB_USB2PHY_SUSPM(usb32)); reg 173 drivers/phy/marvell/phy-mvebu-a3700-utmi.c writel(reg, utmi->regs + USB2_PHY_CTRL(usb32)); reg 177 drivers/phy/marvell/phy-mvebu-a3700-utmi.c reg = readl(utmi->regs + USB2_PHY_OTG_CTRL); reg 178 drivers/phy/marvell/phy-mvebu-a3700-utmi.c reg &= ~PHY_PU_OTG; reg 179 drivers/phy/marvell/phy-mvebu-a3700-utmi.c writel(reg, utmi->regs + USB2_PHY_OTG_CTRL); reg 31 drivers/phy/marvell/phy-mvebu-sata.c u32 reg; reg 36 drivers/phy/marvell/phy-mvebu-sata.c reg = readl(priv->base + SATA_PHY_MODE_2); reg 37 drivers/phy/marvell/phy-mvebu-sata.c reg |= (MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX | reg 39 drivers/phy/marvell/phy-mvebu-sata.c writel(reg , priv->base + SATA_PHY_MODE_2); reg 42 drivers/phy/marvell/phy-mvebu-sata.c reg = readl(priv->base + SATA_IF_CTRL); reg 43 drivers/phy/marvell/phy-mvebu-sata.c reg &= ~CTRL_PHY_SHUTDOWN; reg 44 drivers/phy/marvell/phy-mvebu-sata.c writel(reg, priv->base + SATA_IF_CTRL); reg 54 drivers/phy/marvell/phy-mvebu-sata.c u32 reg; reg 59 drivers/phy/marvell/phy-mvebu-sata.c reg = readl(priv->base + SATA_PHY_MODE_2); reg 60 drivers/phy/marvell/phy-mvebu-sata.c reg &= ~(MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX | reg 62 drivers/phy/marvell/phy-mvebu-sata.c writel(reg, priv->base + SATA_PHY_MODE_2); reg 65 drivers/phy/marvell/phy-mvebu-sata.c reg = readl(priv->base + SATA_IF_CTRL); reg 66 drivers/phy/marvell/phy-mvebu-sata.c reg |= CTRL_PHY_SHUTDOWN; reg 67 drivers/phy/marvell/phy-mvebu-sata.c writel(reg, priv->base + SATA_IF_CTRL); reg 47 drivers/phy/marvell/phy-pxa-28nm-hsic.c static bool wait_for_reg(void __iomem *reg, u32 mask, unsigned long timeout) reg 51 drivers/phy/marvell/phy-pxa-28nm-hsic.c if ((readl(reg) & mask) == mask) reg 93 drivers/phy/marvell/phy-pxa-28nm-hsic.c u32 reg; reg 95 drivers/phy/marvell/phy-pxa-28nm-hsic.c reg = readl(base + PHY_28NM_HSIC_CTRL); reg 97 drivers/phy/marvell/phy-pxa-28nm-hsic.c reg &= ~S2H_DRV_SE0_4RESUME; reg 98 drivers/phy/marvell/phy-pxa-28nm-hsic.c reg |= PHY_28NM_HSIC_S2H_HSIC_EN; /* Enable HSIC PHY */ reg 99 drivers/phy/marvell/phy-pxa-28nm-hsic.c writel(reg, base + PHY_28NM_HSIC_CTRL); reg 141 drivers/phy/marvell/phy-pxa-28nm-usb2.c static bool wait_for_reg(void __iomem *reg, u32 mask, unsigned long timeout) reg 145 drivers/phy/marvell/phy-pxa-28nm-usb2.c if ((readl(reg) & mask) == mask) reg 157 drivers/phy/marvell/phy-pxa-28nm-usb2.c u32 reg; reg 163 drivers/phy/marvell/phy-pxa-28nm-usb2.c reg = readl(base + PHY_28NM_PLL_REG0) & reg 166 drivers/phy/marvell/phy-pxa-28nm-usb2.c writel(reg | (0x1 << PHY_28NM_PLL_SELLPFR_SHIFT reg 173 drivers/phy/marvell/phy-pxa-28nm-usb2.c reg = readl(base + PHY_28NM_PLL_REG1); reg 174 drivers/phy/marvell/phy-pxa-28nm-usb2.c writel(reg | PHY_28NM_PLL_PU_PLL | PHY_28NM_PLL_PU_BY_REG, reg 178 drivers/phy/marvell/phy-pxa-28nm-usb2.c reg = readl(base + PHY_28NM_TX_REG0) & ~PHY_28NM_TX_AMP_MASK; reg 179 drivers/phy/marvell/phy-pxa-28nm-usb2.c writel(reg | PHY_28NM_TX_PU_BY_REG | 0x3 << PHY_28NM_TX_AMP_SHIFT | reg 184 drivers/phy/marvell/phy-pxa-28nm-usb2.c reg = readl(base + PHY_28NM_RX_REG0) & ~PHY_28NM_RX_SQ_THRESH_MASK; reg 185 drivers/phy/marvell/phy-pxa-28nm-usb2.c writel(reg | 0xa << PHY_28NM_RX_SQ_THRESH_SHIFT, reg 189 drivers/phy/marvell/phy-pxa-28nm-usb2.c reg = readl(base + PHY_28NM_DIG_REG0) & reg 193 drivers/phy/marvell/phy-pxa-28nm-usb2.c writel(reg | (0x1 << PHY_28NM_DIG_SYNC_NUM_SHIFT | reg 198 drivers/phy/marvell/phy-pxa-28nm-usb2.c reg = readl(base + PHY_28NM_OTG_REG) | PHY_28NM_OTG_PU_OTG; reg 199 drivers/phy/marvell/phy-pxa-28nm-usb2.c writel(reg & ~PHY_28NM_OTG_CONTROL_BY_PIN, base + PHY_28NM_OTG_REG); reg 133 drivers/phy/marvell/phy-pxa-usb.c u32 reg; reg 135 drivers/phy/marvell/phy-pxa-usb.c reg = readl_relaxed(base + offset); reg 136 drivers/phy/marvell/phy-pxa-usb.c reg |= value; reg 137 drivers/phy/marvell/phy-pxa-usb.c writel_relaxed(reg, base + offset); reg 144 drivers/phy/marvell/phy-pxa-usb.c u32 reg; reg 146 drivers/phy/marvell/phy-pxa-usb.c reg = readl_relaxed(base + offset); reg 147 drivers/phy/marvell/phy-pxa-usb.c reg &= ~value; reg 148 drivers/phy/marvell/phy-pxa-usb.c writel_relaxed(reg, base + offset); reg 41 drivers/phy/mediatek/phy-mtk-ufs.c static inline u32 mphy_readl(struct ufs_mtk_phy *phy, u32 reg) reg 43 drivers/phy/mediatek/phy-mtk-ufs.c return readl(phy->mmio + reg); reg 46 drivers/phy/mediatek/phy-mtk-ufs.c static inline void mphy_writel(struct ufs_mtk_phy *phy, u32 val, u32 reg) reg 48 drivers/phy/mediatek/phy-mtk-ufs.c writel(val, phy->mmio + reg); reg 51 drivers/phy/mediatek/phy-mtk-ufs.c static void mphy_set_bit(struct ufs_mtk_phy *phy, u32 reg, u32 bit) reg 55 drivers/phy/mediatek/phy-mtk-ufs.c val = mphy_readl(phy, reg); reg 57 drivers/phy/mediatek/phy-mtk-ufs.c mphy_writel(phy, val, reg); reg 60 drivers/phy/mediatek/phy-mtk-ufs.c static void mphy_clr_bit(struct ufs_mtk_phy *phy, u32 reg, u32 bit) reg 64 drivers/phy/mediatek/phy-mtk-ufs.c val = mphy_readl(phy, reg); reg 66 drivers/phy/mediatek/phy-mtk-ufs.c mphy_writel(phy, val, reg); reg 123 drivers/phy/motorola/phy-cpcap-usb.c struct regmap *reg; reg 180 drivers/phy/motorola/phy-cpcap-usb.c error = regmap_read(ddata->reg, CPCAP_REG_INTS1, &val); reg 188 drivers/phy/motorola/phy-cpcap-usb.c error = regmap_read(ddata->reg, CPCAP_REG_INTS2, &val); reg 197 drivers/phy/motorola/phy-cpcap-usb.c error = regmap_read(ddata->reg, CPCAP_REG_INTS4, &val); reg 244 drivers/phy/motorola/phy-cpcap-usb.c error = regmap_update_bits(ddata->reg, CPCAP_REG_USBC3, reg 254 drivers/phy/motorola/phy-cpcap-usb.c error = regmap_update_bits(ddata->reg, CPCAP_REG_USBC3, reg 395 drivers/phy/motorola/phy-cpcap-usb.c error = regmap_update_bits(ddata->reg, CPCAP_REG_USBC1, reg 401 drivers/phy/motorola/phy-cpcap-usb.c error = regmap_update_bits(ddata->reg, CPCAP_REG_USBC2, reg 407 drivers/phy/motorola/phy-cpcap-usb.c error = regmap_update_bits(ddata->reg, CPCAP_REG_USBC3, 0x7fff, reg 444 drivers/phy/motorola/phy-cpcap-usb.c error = regmap_update_bits(ddata->reg, CPCAP_REG_USBC1, reg 449 drivers/phy/motorola/phy-cpcap-usb.c error = regmap_update_bits(ddata->reg, CPCAP_REG_USBC2, reg 455 drivers/phy/motorola/phy-cpcap-usb.c error = regmap_update_bits(ddata->reg, CPCAP_REG_USBC3, reg 464 drivers/phy/motorola/phy-cpcap-usb.c error = regmap_update_bits(ddata->reg, CPCAP_REG_USBC2, reg 598 drivers/phy/motorola/phy-cpcap-usb.c ddata->reg = dev_get_regmap(pdev->dev.parent, NULL); reg 599 drivers/phy/motorola/phy-cpcap-usb.c if (!ddata->reg) reg 24 drivers/phy/phy-lpc18xx-usb-otg.c struct regmap *reg; reg 59 drivers/phy/phy-lpc18xx-usb-otg.c ret = regmap_update_bits(lpc->reg, LPC18XX_CREG_CREG0, reg 74 drivers/phy/phy-lpc18xx-usb-otg.c ret = regmap_update_bits(lpc->reg, LPC18XX_CREG_CREG0, reg 102 drivers/phy/phy-lpc18xx-usb-otg.c lpc->reg = syscon_node_to_regmap(pdev->dev.of_node->parent); reg 103 drivers/phy/phy-lpc18xx-usb-otg.c if (IS_ERR(lpc->reg)) { reg 105 drivers/phy/phy-lpc18xx-usb-otg.c return PTR_ERR(lpc->reg); reg 594 drivers/phy/phy-xgene.c u32 reg, u32 data) reg 600 drivers/phy/phy-xgene.c reg += SERDES_PLL_REF_INDIRECT_OFFSET; reg 602 drivers/phy/phy-xgene.c reg += SERDES_PLL_INDIRECT_OFFSET; reg 604 drivers/phy/phy-xgene.c SATA_ENET_SDS_IND_WDATA_REG, reg, data); reg 606 drivers/phy/phy-xgene.c SATA_ENET_SDS_IND_RDATA_REG, reg, &val); reg 607 drivers/phy/phy-xgene.c pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val); reg 611 drivers/phy/phy-xgene.c u32 reg, u32 *data) reg 616 drivers/phy/phy-xgene.c reg += SERDES_PLL_REF_INDIRECT_OFFSET; reg 618 drivers/phy/phy-xgene.c reg += SERDES_PLL_INDIRECT_OFFSET; reg 620 drivers/phy/phy-xgene.c SATA_ENET_SDS_IND_RDATA_REG, reg, data); reg 621 drivers/phy/phy-xgene.c pr_debug("CMU RD addr 0x%X value 0x%08X\n", reg, *data); reg 625 drivers/phy/phy-xgene.c u32 reg, u32 bits) reg 629 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, reg, &val); reg 631 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, reg, val); reg 632 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, reg, &val); reg 634 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, reg, val); reg 638 drivers/phy/phy-xgene.c u32 reg, u32 bits) reg 642 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, reg, &val); reg 644 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, reg, val); reg 648 drivers/phy/phy-xgene.c u32 reg, u32 bits) reg 652 drivers/phy/phy-xgene.c cmu_rd(ctx, cmu_type, reg, &val); reg 654 drivers/phy/phy-xgene.c cmu_wr(ctx, cmu_type, reg, val); reg 657 drivers/phy/phy-xgene.c static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) reg 662 drivers/phy/phy-xgene.c reg += SERDES_INDIRECT_OFFSET; reg 663 drivers/phy/phy-xgene.c reg += lane * SERDES_LANE_STRIDE; reg 665 drivers/phy/phy-xgene.c SATA_ENET_SDS_IND_WDATA_REG, reg, data); reg 667 drivers/phy/phy-xgene.c SATA_ENET_SDS_IND_RDATA_REG, reg, &val); reg 668 drivers/phy/phy-xgene.c pr_debug("SERDES WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, reg 672 drivers/phy/phy-xgene.c static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) reg 676 drivers/phy/phy-xgene.c reg += SERDES_INDIRECT_OFFSET; reg 677 drivers/phy/phy-xgene.c reg += lane * SERDES_LANE_STRIDE; reg 679 drivers/phy/phy-xgene.c SATA_ENET_SDS_IND_RDATA_REG, reg, data); reg 680 drivers/phy/phy-xgene.c pr_debug("SERDES RD addr 0x%X value 0x%08X\n", reg, *data); reg 683 drivers/phy/phy-xgene.c static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, reg 688 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, reg, &val); reg 690 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, reg, val); reg 693 drivers/phy/phy-xgene.c static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, reg 698 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, reg, &val); reg 700 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, reg, val); reg 941 drivers/phy/phy-xgene.c u32 reg; reg 1058 drivers/phy/phy-xgene.c reg = RXTX_REG81 + i * 2; reg 1059 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, reg, &val); reg 1063 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, reg, val); reg 1068 drivers/phy/phy-xgene.c reg = RXTX_REG96 + i * 2; reg 1069 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, reg, &val); reg 1073 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, reg, val); reg 1078 drivers/phy/phy-xgene.c reg = RXTX_REG99 + i * 2; reg 1079 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, reg, &val); reg 1083 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, reg, val); reg 1127 drivers/phy/phy-xgene.c reg = RXTX_REG148 + i * 2; reg 1128 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, reg, 0xFFFF); reg 1346 drivers/phy/phy-xgene.c u32 reg; reg 1404 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, serdes_reg[i].reg, reg 56 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c u32 reg; reg 59 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3); reg 60 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c reg = reg | SATA_PHY_SSC_EN; reg 61 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3); reg 63 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) & reg 67 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c reg |= SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(0xf); reg 68 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0); reg 70 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) & reg 74 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c reg |= SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(0x55) | reg 77 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1); reg 79 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM2) & reg 81 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c reg |= SATA_PHY_P0_PARAM2_RX_EQ(0x3); reg 82 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM2); reg 85 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); reg 86 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c reg = reg | SATA_PHY_RESET; reg 87 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); reg 90 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); reg 91 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c reg = reg | SATA_PHY_REF_SSP_EN | SATA_PHY_RESET; reg 92 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); reg 101 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); reg 102 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c reg = reg & ~SATA_PHY_RESET; reg 103 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); reg 111 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c u32 reg; reg 114 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); reg 115 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c reg = reg | SATA_PHY_RESET; reg 116 drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); reg 1006 drivers/phy/qualcomm/phy-qcom-qmp.c u32 reg; reg 1008 drivers/phy/qualcomm/phy-qcom-qmp.c reg = readl(base + offset); reg 1009 drivers/phy/qualcomm/phy-qcom-qmp.c reg |= val; reg 1010 drivers/phy/qualcomm/phy-qcom-qmp.c writel(reg, base + offset); reg 1018 drivers/phy/qualcomm/phy-qcom-qmp.c u32 reg; reg 1020 drivers/phy/qualcomm/phy-qcom-qmp.c reg = readl(base + offset); reg 1021 drivers/phy/qualcomm/phy-qcom-qmp.c reg &= ~val; reg 1022 drivers/phy/qualcomm/phy-qcom-qmp.c writel(reg, base + offset); reg 340 drivers/phy/qualcomm/phy-qcom-qusb2.c u32 reg; reg 342 drivers/phy/qualcomm/phy-qcom-qusb2.c reg = readl(base + offset); reg 343 drivers/phy/qualcomm/phy-qcom-qusb2.c reg &= ~mask; reg 344 drivers/phy/qualcomm/phy-qcom-qusb2.c reg |= val & mask; reg 345 drivers/phy/qualcomm/phy-qcom-qusb2.c writel(reg, base + offset); reg 353 drivers/phy/qualcomm/phy-qcom-qusb2.c u32 reg; reg 355 drivers/phy/qualcomm/phy-qcom-qusb2.c reg = readl(base + offset); reg 356 drivers/phy/qualcomm/phy-qcom-qusb2.c reg |= val; reg 357 drivers/phy/qualcomm/phy-qcom-qusb2.c writel(reg, base + offset); reg 365 drivers/phy/qualcomm/phy-qcom-qusb2.c u32 reg; reg 367 drivers/phy/qualcomm/phy-qcom-qusb2.c reg = readl(base + offset); reg 368 drivers/phy/qualcomm/phy-qcom-qusb2.c reg &= ~val; reg 369 drivers/phy/qualcomm/phy-qcom-qusb2.c writel(reg, base + offset); reg 20 drivers/phy/qualcomm/phy-qcom-ufs-i.h #define UFS_QCOM_PHY_CAL_ENTRY(reg, val) \ reg 22 drivers/phy/qualcomm/phy-qcom-ufs-i.h .reg_offset = reg, \ reg 50 drivers/phy/qualcomm/phy-qcom-ufs-i.h struct regulator *reg; reg 228 drivers/phy/qualcomm/phy-qcom-ufs.c vreg->reg = devm_regulator_get(dev, name); reg 229 drivers/phy/qualcomm/phy-qcom-ufs.c if (IS_ERR(vreg->reg)) { reg 230 drivers/phy/qualcomm/phy-qcom-ufs.c err = PTR_ERR(vreg->reg); reg 244 drivers/phy/qualcomm/phy-qcom-ufs.c if (regulator_count_voltages(vreg->reg) > 0) { reg 295 drivers/phy/qualcomm/phy-qcom-ufs.c struct regulator *reg = vreg->reg; reg 300 drivers/phy/qualcomm/phy-qcom-ufs.c if (regulator_count_voltages(reg) > 0) { reg 302 drivers/phy/qualcomm/phy-qcom-ufs.c ret = regulator_set_voltage(reg, min_uV, vreg->max_uV); reg 309 drivers/phy/qualcomm/phy-qcom-ufs.c ret = regulator_set_load(reg, uA_load); reg 341 drivers/phy/qualcomm/phy-qcom-ufs.c ret = regulator_enable(vreg->reg); reg 411 drivers/phy/qualcomm/phy-qcom-ufs.c ret = regulator_disable(vreg->reg); reg 601 drivers/phy/qualcomm/phy-qcom-ufs.c if (phy_common->vddp_ref_clk.reg) { reg 632 drivers/phy/qualcomm/phy-qcom-ufs.c if (phy_common->vddp_ref_clk.reg) reg 206 drivers/phy/qualcomm/phy-qcom-usb-hs.c struct regulator *reg; reg 239 drivers/phy/qualcomm/phy-qcom-usb-hs.c uphy->v1p8 = reg = devm_regulator_get(&ulpi->dev, "v1p8"); reg 240 drivers/phy/qualcomm/phy-qcom-usb-hs.c if (IS_ERR(reg)) reg 241 drivers/phy/qualcomm/phy-qcom-usb-hs.c return PTR_ERR(reg); reg 243 drivers/phy/qualcomm/phy-qcom-usb-hs.c uphy->v3p3 = reg = devm_regulator_get(&ulpi->dev, "v3p3"); reg 244 drivers/phy/qualcomm/phy-qcom-usb-hs.c if (IS_ERR(reg)) reg 245 drivers/phy/qualcomm/phy-qcom-usb-hs.c return PTR_ERR(reg); reg 61 drivers/phy/ralink/phy-ralink-usb.c static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg) reg 63 drivers/phy/ralink/phy-ralink-usb.c writel(val, phy->base + reg); reg 66 drivers/phy/ralink/phy-ralink-usb.c static u32 u2_phy_r32(struct ralink_usb_phy *phy, u32 reg) reg 68 drivers/phy/ralink/phy-ralink-usb.c return readl(phy->base + reg); reg 28 drivers/phy/renesas/phy-rcar-gen3-pcie.c static void rcar_gen3_phy_pcie_modify_reg(struct phy *p, unsigned int reg, reg 38 drivers/phy/renesas/phy-rcar-gen3-pcie.c value = readl(base + reg); reg 41 drivers/phy/renesas/phy-rcar-gen3-pcie.c writel(value, base + reg); reg 382 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val) reg 384 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c regmap_write(inno->regmap, reg * 4, val); reg 387 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg) reg 391 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c regmap_read(inno->regmap, reg * 4, &val); reg 396 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg, reg 399 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c regmap_update_bits(inno->regmap, reg * 4, mask, val); reg 402 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c #define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) \ reg 403 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c regmap_read_poll_timeout((inno)->regmap, (reg) * 4, val, cond, \ reg 150 drivers/phy/rockchip/phy-rockchip-inno-usb2.c unsigned int reg; reg 231 drivers/phy/rockchip/phy-rockchip-inno-usb2.c const struct usb2phy_reg *reg, bool en) reg 235 drivers/phy/rockchip/phy-rockchip-inno-usb2.c tmp = en ? reg->enable : reg->disable; reg 236 drivers/phy/rockchip/phy-rockchip-inno-usb2.c mask = GENMASK(reg->bitend, reg->bitstart); reg 237 drivers/phy/rockchip/phy-rockchip-inno-usb2.c val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); reg 239 drivers/phy/rockchip/phy-rockchip-inno-usb2.c return regmap_write(base, reg->offset, val); reg 243 drivers/phy/rockchip/phy-rockchip-inno-usb2.c const struct usb2phy_reg *reg) reg 247 drivers/phy/rockchip/phy-rockchip-inno-usb2.c unsigned int mask = GENMASK(reg->bitend, reg->bitstart); reg 249 drivers/phy/rockchip/phy-rockchip-inno-usb2.c ret = regmap_read(base, reg->offset, &orig); reg 253 drivers/phy/rockchip/phy-rockchip-inno-usb2.c tmp = (orig & mask) >> reg->bitstart; reg 254 drivers/phy/rockchip/phy-rockchip-inno-usb2.c return tmp == reg->enable; reg 1071 drivers/phy/rockchip/phy-rockchip-inno-usb2.c unsigned int reg; reg 1101 drivers/phy/rockchip/phy-rockchip-inno-usb2.c if (of_property_read_u32(np, "reg", ®)) { reg 1119 drivers/phy/rockchip/phy-rockchip-inno-usb2.c while (phy_cfgs[index].reg) { reg 1120 drivers/phy/rockchip/phy-rockchip-inno-usb2.c if (phy_cfgs[index].reg == reg) { reg 1202 drivers/phy/rockchip/phy-rockchip-inno-usb2.c .reg = 0x760, reg 1238 drivers/phy/rockchip/phy-rockchip-inno-usb2.c .reg = 0x800, reg 1261 drivers/phy/rockchip/phy-rockchip-inno-usb2.c .reg = 0x100, reg 1304 drivers/phy/rockchip/phy-rockchip-inno-usb2.c .reg = 0x700, reg 1323 drivers/phy/rockchip/phy-rockchip-inno-usb2.c .reg = 0xe450, reg 1358 drivers/phy/rockchip/phy-rockchip-inno-usb2.c .reg = 0xe460, reg 1385 drivers/phy/rockchip/phy-rockchip-inno-usb2.c .reg = 0x100, reg 361 drivers/phy/rockchip/phy-rockchip-typec.c unsigned int reg; reg 435 drivers/phy/rockchip/phy-rockchip-typec.c .reg = 0xff7c0000, reg 445 drivers/phy/rockchip/phy-rockchip-typec.c .reg = 0xff800000, reg 561 drivers/phy/rockchip/phy-rockchip-typec.c const struct usb3phy_reg *reg, bool en) reg 563 drivers/phy/rockchip/phy-rockchip-typec.c u32 mask = 1 << reg->write_enable; reg 564 drivers/phy/rockchip/phy-rockchip-typec.c u32 val = en << reg->enable_bit; reg 566 drivers/phy/rockchip/phy-rockchip-typec.c return regmap_write(tcphy->grf_regs, reg->offset, val | mask); reg 870 drivers/phy/rockchip/phy-rockchip-typec.c const struct usb3phy_reg *reg = &cfg->pipe_status; reg 899 drivers/phy/rockchip/phy-rockchip-typec.c regmap_read(tcphy->grf_regs, reg->offset, &val); reg 900 drivers/phy/rockchip/phy-rockchip-typec.c if (!(val & BIT(reg->enable_bit))) { reg 1129 drivers/phy/rockchip/phy-rockchip-typec.c while (phy_cfgs[index].reg) { reg 1130 drivers/phy/rockchip/phy-rockchip-typec.c if (phy_cfgs[index].reg == res->start) { reg 49 drivers/phy/rockchip/phy-rockchip-usb.c int reg; reg 236 drivers/phy/rockchip/phy-rockchip-usb.c while (base->pdata->phys[i].reg) { reg 237 drivers/phy/rockchip/phy-rockchip-usb.c if (base->pdata->phys[i].reg == reg_offset) { reg 318 drivers/phy/rockchip/phy-rockchip-usb.c { .reg = 0x17c, .pll_name = "sclk_otgphy0_480m" }, reg 319 drivers/phy/rockchip/phy-rockchip-usb.c { .reg = 0x188, .pll_name = "sclk_otgphy1_480m" }, reg 327 drivers/phy/rockchip/phy-rockchip-usb.c int regoffs = pdata->phys[pdata->usb_uart_phy].reg; reg 397 drivers/phy/rockchip/phy-rockchip-usb.c { .reg = 0x10c, .pll_name = "sclk_otgphy0_480m" }, reg 398 drivers/phy/rockchip/phy-rockchip-usb.c { .reg = 0x11c, .pll_name = "sclk_otgphy1_480m" }, reg 447 drivers/phy/rockchip/phy-rockchip-usb.c { .reg = 0x320, .pll_name = "sclk_otgphy0_480m" }, reg 448 drivers/phy/rockchip/phy-rockchip-usb.c { .reg = 0x334, .pll_name = "sclk_otgphy1_480m" }, reg 449 drivers/phy/rockchip/phy-rockchip-usb.c { .reg = 0x348, .pll_name = "sclk_otgphy2_480m" }, reg 105 drivers/phy/samsung/phy-exynos4210-usb2.c static int exynos4210_rate_to_clk(unsigned long rate, u32 *reg) reg 109 drivers/phy/samsung/phy-exynos4210-usb2.c *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ; reg 112 drivers/phy/samsung/phy-exynos4210-usb2.c *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ; reg 115 drivers/phy/samsung/phy-exynos4210-usb2.c *reg = EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ; reg 132 drivers/phy/samsung/phy-exynos4x12-usb2.c static int exynos4x12_rate_to_clk(unsigned long rate, u32 *reg) reg 138 drivers/phy/samsung/phy-exynos4x12-usb2.c *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_9MHZ6; reg 141 drivers/phy/samsung/phy-exynos4x12-usb2.c *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_10MHZ; reg 144 drivers/phy/samsung/phy-exynos4x12-usb2.c *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_12MHZ; reg 147 drivers/phy/samsung/phy-exynos4x12-usb2.c *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_19MHZ2; reg 150 drivers/phy/samsung/phy-exynos4x12-usb2.c *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_20MHZ; reg 153 drivers/phy/samsung/phy-exynos4x12-usb2.c *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_24MHZ; reg 156 drivers/phy/samsung/phy-exynos4x12-usb2.c *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_50MHZ; reg 224 drivers/phy/samsung/phy-exynos5-usbdrd.c static unsigned int exynos5_rate_to_clk(unsigned long rate, u32 *reg) reg 230 drivers/phy/samsung/phy-exynos5-usbdrd.c *reg = EXYNOS5_FSEL_9MHZ6; reg 233 drivers/phy/samsung/phy-exynos5-usbdrd.c *reg = EXYNOS5_FSEL_10MHZ; reg 236 drivers/phy/samsung/phy-exynos5-usbdrd.c *reg = EXYNOS5_FSEL_12MHZ; reg 239 drivers/phy/samsung/phy-exynos5-usbdrd.c *reg = EXYNOS5_FSEL_19MHZ2; reg 242 drivers/phy/samsung/phy-exynos5-usbdrd.c *reg = EXYNOS5_FSEL_20MHZ; reg 245 drivers/phy/samsung/phy-exynos5-usbdrd.c *reg = EXYNOS5_FSEL_24MHZ; reg 248 drivers/phy/samsung/phy-exynos5-usbdrd.c *reg = EXYNOS5_FSEL_50MHZ; reg 279 drivers/phy/samsung/phy-exynos5-usbdrd.c u32 reg; reg 283 drivers/phy/samsung/phy-exynos5-usbdrd.c reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); reg 286 drivers/phy/samsung/phy-exynos5-usbdrd.c reg &= ~PHYCLKRST_REFCLKSEL_MASK; reg 287 drivers/phy/samsung/phy-exynos5-usbdrd.c reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK; reg 290 drivers/phy/samsung/phy-exynos5-usbdrd.c reg &= ~PHYCLKRST_FSEL_PIPE_MASK | reg 295 drivers/phy/samsung/phy-exynos5-usbdrd.c reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF | reg 299 drivers/phy/samsung/phy-exynos5-usbdrd.c reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF | reg 303 drivers/phy/samsung/phy-exynos5-usbdrd.c reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF | reg 307 drivers/phy/samsung/phy-exynos5-usbdrd.c reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF | reg 315 drivers/phy/samsung/phy-exynos5-usbdrd.c return reg; reg 325 drivers/phy/samsung/phy-exynos5-usbdrd.c u32 reg; reg 329 drivers/phy/samsung/phy-exynos5-usbdrd.c reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); reg 331 drivers/phy/samsung/phy-exynos5-usbdrd.c reg &= ~PHYCLKRST_REFCLKSEL_MASK; reg 332 drivers/phy/samsung/phy-exynos5-usbdrd.c reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK; reg 334 drivers/phy/samsung/phy-exynos5-usbdrd.c reg &= ~PHYCLKRST_FSEL_UTMI_MASK | reg 337 drivers/phy/samsung/phy-exynos5-usbdrd.c reg |= PHYCLKRST_FSEL(phy_drd->extrefclk); reg 339 drivers/phy/samsung/phy-exynos5-usbdrd.c return reg; reg 344 drivers/phy/samsung/phy-exynos5-usbdrd.c u32 reg; reg 346 drivers/phy/samsung/phy-exynos5-usbdrd.c reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); reg 348 drivers/phy/samsung/phy-exynos5-usbdrd.c reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK; reg 349 drivers/phy/samsung/phy-exynos5-usbdrd.c reg |= PHYPARAM1_PCS_TXDEEMPH; reg 350 drivers/phy/samsung/phy-exynos5-usbdrd.c writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); reg 352 drivers/phy/samsung/phy-exynos5-usbdrd.c reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); reg 353 drivers/phy/samsung/phy-exynos5-usbdrd.c reg &= ~PHYTEST_POWERDOWN_SSP; reg 354 drivers/phy/samsung/phy-exynos5-usbdrd.c writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); reg 359 drivers/phy/samsung/phy-exynos5-usbdrd.c u32 reg; reg 361 drivers/phy/samsung/phy-exynos5-usbdrd.c reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); reg 363 drivers/phy/samsung/phy-exynos5-usbdrd.c reg &= ~PHYPARAM0_REF_LOSLEVEL_MASK; reg 364 drivers/phy/samsung/phy-exynos5-usbdrd.c reg |= PHYPARAM0_REF_LOSLEVEL; reg 365 drivers/phy/samsung/phy-exynos5-usbdrd.c writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); reg 367 drivers/phy/samsung/phy-exynos5-usbdrd.c reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); reg 369 drivers/phy/samsung/phy-exynos5-usbdrd.c reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK; reg 370 drivers/phy/samsung/phy-exynos5-usbdrd.c reg |= PHYPARAM1_PCS_TXDEEMPH; reg 371 drivers/phy/samsung/phy-exynos5-usbdrd.c writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); reg 376 drivers/phy/samsung/phy-exynos5-usbdrd.c reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); reg 377 drivers/phy/samsung/phy-exynos5-usbdrd.c reg &= ~PHYTEST_POWERDOWN_HSP; reg 378 drivers/phy/samsung/phy-exynos5-usbdrd.c writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); reg 384 drivers/phy/samsung/phy-exynos5-usbdrd.c u32 reg; reg 400 drivers/phy/samsung/phy-exynos5-usbdrd.c reg = LINKSYSTEM_XHCI_VERSION_CONTROL | reg 402 drivers/phy/samsung/phy-exynos5-usbdrd.c writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); reg 404 drivers/phy/samsung/phy-exynos5-usbdrd.c reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); reg 406 drivers/phy/samsung/phy-exynos5-usbdrd.c reg &= ~PHYPARAM0_REF_USE_PAD; reg 407 drivers/phy/samsung/phy-exynos5-usbdrd.c writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); reg 410 drivers/phy/samsung/phy-exynos5-usbdrd.c reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL); reg 411 drivers/phy/samsung/phy-exynos5-usbdrd.c reg |= PHYUTMICLKSEL_UTMI_CLKSEL; reg 412 drivers/phy/samsung/phy-exynos5-usbdrd.c writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL); reg 418 drivers/phy/samsung/phy-exynos5-usbdrd.c reg = inst->phy_cfg->set_refclk(inst); reg 421 drivers/phy/samsung/phy-exynos5-usbdrd.c reg |= PHYCLKRST_RETENABLEN | reg 431 drivers/phy/samsung/phy-exynos5-usbdrd.c writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); reg 435 drivers/phy/samsung/phy-exynos5-usbdrd.c reg &= ~PHYCLKRST_PORTRESET; reg 436 drivers/phy/samsung/phy-exynos5-usbdrd.c writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); reg 446 drivers/phy/samsung/phy-exynos5-usbdrd.c u32 reg; reg 454 drivers/phy/samsung/phy-exynos5-usbdrd.c reg = PHYUTMI_OTGDISABLE | reg 457 drivers/phy/samsung/phy-exynos5-usbdrd.c writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); reg 460 drivers/phy/samsung/phy-exynos5-usbdrd.c reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); reg 461 drivers/phy/samsung/phy-exynos5-usbdrd.c reg &= ~(PHYCLKRST_REF_SSP_EN | reg 464 drivers/phy/samsung/phy-exynos5-usbdrd.c writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); reg 467 drivers/phy/samsung/phy-exynos5-usbdrd.c reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); reg 468 drivers/phy/samsung/phy-exynos5-usbdrd.c reg |= PHYTEST_POWERDOWN_SSP | reg 470 drivers/phy/samsung/phy-exynos5-usbdrd.c writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); reg 56 drivers/phy/samsung/phy-exynos5250-sata.c static int wait_for_reg_status(void __iomem *base, u32 reg, u32 checkbit, reg 62 drivers/phy/samsung/phy-exynos5250-sata.c if ((readl(base + reg) & checkbit) == status) reg 142 drivers/phy/samsung/phy-exynos5250-usb2.c static int exynos5250_rate_to_clk(unsigned long rate, u32 *reg) reg 148 drivers/phy/samsung/phy-exynos5250-usb2.c *reg = EXYNOS_5250_FSEL_9MHZ6; reg 151 drivers/phy/samsung/phy-exynos5250-usb2.c *reg = EXYNOS_5250_FSEL_10MHZ; reg 154 drivers/phy/samsung/phy-exynos5250-usb2.c *reg = EXYNOS_5250_FSEL_12MHZ; reg 157 drivers/phy/samsung/phy-exynos5250-usb2.c *reg = EXYNOS_5250_FSEL_19MHZ2; reg 160 drivers/phy/samsung/phy-exynos5250-usb2.c *reg = EXYNOS_5250_FSEL_20MHZ; reg 163 drivers/phy/samsung/phy-exynos5250-usb2.c *reg = EXYNOS_5250_FSEL_24MHZ; reg 166 drivers/phy/samsung/phy-exynos5250-usb2.c *reg = EXYNOS_5250_FSEL_50MHZ; reg 70 drivers/phy/samsung/phy-s5pv210-usb2.c static int s5pv210_rate_to_clk(unsigned long rate, u32 *reg) reg 74 drivers/phy/samsung/phy-s5pv210-usb2.c *reg = S5PV210_UPHYCLK_PHYFSEL_12MHZ; reg 77 drivers/phy/samsung/phy-s5pv210-usb2.c *reg = S5PV210_UPHYCLK_PHYFSEL_24MHZ; reg 80 drivers/phy/samsung/phy-s5pv210-usb2.c *reg = S5PV210_UPHYCLK_PHYFSEL_48MHZ; reg 67 drivers/phy/socionext/phy-uniphier-pcie.c u32 reg, u32 mask, u32 param) reg 73 drivers/phy/socionext/phy-uniphier-pcie.c val |= FIELD_PREP(TESTI_ADR_MASK, reg); reg 80 drivers/phy/socionext/phy-uniphier-pcie.c val |= FIELD_PREP(TESTI_ADR_MASK, reg); reg 87 drivers/phy/socionext/phy-uniphier-pcie.c val |= FIELD_PREP(TESTI_ADR_MASK, reg); reg 231 drivers/phy/st/phy-miphy28lp.c u16 reg; reg 76 drivers/phy/st/phy-stm32-usbphyc.c static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits) reg 78 drivers/phy/st/phy-stm32-usbphyc.c writel_relaxed(readl_relaxed(reg) | bits, reg); reg 81 drivers/phy/st/phy-stm32-usbphyc.c static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits) reg 83 drivers/phy/st/phy-stm32-usbphyc.c writel_relaxed(readl_relaxed(reg) & ~bits, reg); reg 32 drivers/phy/tegra/phy-tegra194-p2u.c const u32 reg) reg 34 drivers/phy/tegra/phy-tegra194-p2u.c writel_relaxed(value, phy->base + reg); reg 37 drivers/phy/tegra/phy-tegra194-p2u.c static inline u32 p2u_readl(struct tegra_p2u *phy, const u32 reg) reg 39 drivers/phy/tegra/phy-tegra194-p2u.c return readl_relaxed(phy->base + reg); reg 67 drivers/phy/ti/phy-am654-serdes.c unsigned int reg; reg 324 drivers/phy/ti/phy-am654-serdes.c unsigned int reg = mux->reg; reg 327 drivers/phy/ti/phy-am654-serdes.c regmap_read(regmap, reg, &val); reg 339 drivers/phy/ti/phy-am654-serdes.c unsigned int reg = mux->reg; reg 348 drivers/phy/ti/phy-am654-serdes.c regmap_read(regmap, reg, &val); reg 383 drivers/phy/ti/phy-am654-serdes.c ret = regmap_update_bits(regmap, reg, AM654_SERDES_CTRL_CLKSEL_MASK, reg 406 drivers/phy/ti/phy-am654-serdes.c unsigned int reg; reg 452 drivers/phy/ti/phy-am654-serdes.c reg = be32_to_cpu(*addr); reg 461 drivers/phy/ti/phy-am654-serdes.c mux->reg = reg; reg 250 drivers/phy/ti/phy-gmii-sel.c field->reg, field->msb, field->lsb); reg 258 drivers/phy/ti/phy-gmii-sel.c if (field->reg != (~0)) { reg 269 drivers/phy/ti/phy-gmii-sel.c if (field->reg != (~0)) { reg 96 drivers/phy/ti/phy-tusb1210.c u8 val, reg; reg 123 drivers/phy/ti/phy-tusb1210.c reg = val << TUSB1210_VENDOR_SPECIFIC2_IHSTX_SHIFT; reg 127 drivers/phy/ti/phy-tusb1210.c reg |= val << TUSB1210_VENDOR_SPECIFIC2_ZHSDRV_SHIFT; reg 131 drivers/phy/ti/phy-tusb1210.c reg |= val << TUSB1210_VENDOR_SPECIFIC2_DP_SHIFT; reg 133 drivers/phy/ti/phy-tusb1210.c if (reg) { reg 134 drivers/phy/ti/phy-tusb1210.c ulpi_write(ulpi, TUSB1210_VENDOR_SPECIFIC2, reg); reg 135 drivers/phy/ti/phy-tusb1210.c tusb->vendor_specific2 = reg; reg 237 drivers/phy/ti/phy-twl4030-usb.c twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits) reg 239 drivers/phy/ti/phy-twl4030-usb.c return twl4030_usb_write(twl, ULPI_SET(reg), bits); reg 243 drivers/phy/ti/phy-twl4030-usb.c twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits) reg 245 drivers/phy/ti/phy-twl4030-usb.c return twl4030_usb_write(twl, ULPI_CLR(reg), bits); reg 65 drivers/pinctrl/actions/pinctrl-owl.c static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg, reg 70 drivers/pinctrl/actions/pinctrl-owl.c tmp = readl_relaxed(pctrl->base + reg); reg 76 drivers/pinctrl/actions/pinctrl-owl.c static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg, reg 84 drivers/pinctrl/actions/pinctrl-owl.c owl_update_bits(pctrl->base + reg, mask, (arg << bit)); reg 220 drivers/pinctrl/actions/pinctrl-owl.c u32 *reg, reg 231 drivers/pinctrl/actions/pinctrl-owl.c *reg = info->pullctl->reg; reg 238 drivers/pinctrl/actions/pinctrl-owl.c *reg = info->st->reg; reg 257 drivers/pinctrl/actions/pinctrl-owl.c u32 reg, bit, width, arg; reg 261 drivers/pinctrl/actions/pinctrl-owl.c ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width); reg 265 drivers/pinctrl/actions/pinctrl-owl.c arg = owl_read_field(pctrl, reg, bit, width); reg 288 drivers/pinctrl/actions/pinctrl-owl.c u32 reg, bit, width, arg; reg 297 drivers/pinctrl/actions/pinctrl-owl.c ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width); reg 310 drivers/pinctrl/actions/pinctrl-owl.c owl_write_field(pctrl, reg, arg, bit, width); reg 320 drivers/pinctrl/actions/pinctrl-owl.c u32 *reg, reg 328 drivers/pinctrl/actions/pinctrl-owl.c *reg = g->drv_reg; reg 335 drivers/pinctrl/actions/pinctrl-owl.c *reg = g->sr_reg; reg 425 drivers/pinctrl/actions/pinctrl-owl.c u32 reg, bit, width, arg; reg 430 drivers/pinctrl/actions/pinctrl-owl.c ret = owl_group_pinconf_reg(g, param, ®, &bit, &width); reg 434 drivers/pinctrl/actions/pinctrl-owl.c arg = owl_read_field(pctrl, reg, bit, width); reg 455 drivers/pinctrl/actions/pinctrl-owl.c u32 reg, bit, width, arg; reg 464 drivers/pinctrl/actions/pinctrl-owl.c ret = owl_group_pinconf_reg(g, param, ®, &bit, &width); reg 475 drivers/pinctrl/actions/pinctrl-owl.c owl_write_field(pctrl, reg, arg, bit, width); reg 18 drivers/pinctrl/actions/pinctrl-owl.h #define MUX_PG(group_name, reg, shift, width) \ reg 25 drivers/pinctrl/actions/pinctrl-owl.h .mfpctl_reg = MFCTL##reg, \ reg 36 drivers/pinctrl/actions/pinctrl-owl.h #define DRV_PG(group_name, reg, shift, width) \ reg 44 drivers/pinctrl/actions/pinctrl-owl.h .drv_reg = PAD_DRV##reg, \ reg 52 drivers/pinctrl/actions/pinctrl-owl.h #define SR_PG(group_name, reg, shift, width) \ reg 63 drivers/pinctrl/actions/pinctrl-owl.h .sr_reg = PAD_SR##reg, \ reg 78 drivers/pinctrl/actions/pinctrl-owl.h .reg = PAD_PULLCTL##pull_reg, \ reg 89 drivers/pinctrl/actions/pinctrl-owl.h .reg = PAD_ST##st_reg, \ reg 174 drivers/pinctrl/actions/pinctrl-owl.h int reg; reg 186 drivers/pinctrl/actions/pinctrl-owl.h int reg; reg 2573 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 && reg 2577 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2) reg 2580 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg, reg 2747 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 && reg 2751 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2) reg 2755 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1) { reg 2766 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg, reg 2263 drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c is_strap = desc->reg == SCU500 || desc->reg == SCU510; reg 2277 drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c u32 w1c = desc->reg + 4; reg 2285 drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg, reg 490 drivers/pinctrl/aspeed/pinctrl-aspeed.c rc = regmap_read(pdata->scu, pconf->reg, &val); reg 545 drivers/pinctrl/aspeed/pinctrl-aspeed.c rc = regmap_update_bits(pdata->scu, pconf->reg, reg 552 drivers/pinctrl/aspeed/pinctrl-aspeed.c __func__, pconf->reg, pconf->bit, pmap->val, reg 26 drivers/pinctrl/aspeed/pinctrl-aspeed.h unsigned int reg; reg 18 drivers/pinctrl/aspeed/pinmux-aspeed.c aspeed_pinmux_ips[desc->ip], desc->reg, reg 50 drivers/pinctrl/aspeed/pinmux-aspeed.c ret = regmap_read(map, desc->reg, &raw); reg 444 drivers/pinctrl/aspeed/pinmux-aspeed.h unsigned int reg; reg 487 drivers/pinctrl/aspeed/pinmux-aspeed.h #define SIG_DESC_IP_BIT(ip, reg, idx, val) \ reg 488 drivers/pinctrl/aspeed/pinmux-aspeed.h { ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) } reg 498 drivers/pinctrl/aspeed/pinmux-aspeed.h #define SIG_DESC_BIT(reg, idx, val) \ reg 499 drivers/pinctrl/aspeed/pinmux-aspeed.h SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val) reg 501 drivers/pinctrl/aspeed/pinmux-aspeed.h #define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1) reg 510 drivers/pinctrl/aspeed/pinmux-aspeed.h #define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1) reg 511 drivers/pinctrl/aspeed/pinmux-aspeed.h #define SIG_DESC_CLEAR(reg, idx) { ASPEED_IP_SCU, reg, BIT_MASK(idx), 0, 0 } reg 235 drivers/pinctrl/bcm/pinctrl-bcm2835.c static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg) reg 237 drivers/pinctrl/bcm/pinctrl-bcm2835.c return readl(pc->base + reg); reg 240 drivers/pinctrl/bcm/pinctrl-bcm2835.c static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg, reg 243 drivers/pinctrl/bcm/pinctrl-bcm2835.c writel(val, pc->base + reg); reg 246 drivers/pinctrl/bcm/pinctrl-bcm2835.c static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg, reg 249 drivers/pinctrl/bcm/pinctrl-bcm2835.c reg += GPIO_REG_OFFSET(bit) * 4; reg 250 drivers/pinctrl/bcm/pinctrl-bcm2835.c return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1; reg 255 drivers/pinctrl/bcm/pinctrl-bcm2835.c unsigned reg, unsigned bit) reg 257 drivers/pinctrl/bcm/pinctrl-bcm2835.c reg += GPIO_REG_OFFSET(bit) * 4; reg 258 drivers/pinctrl/bcm/pinctrl-bcm2835.c bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit))); reg 413 drivers/pinctrl/bcm/pinctrl-bcm2835.c unsigned reg, unsigned offset, bool enable) reg 416 drivers/pinctrl/bcm/pinctrl-bcm2835.c reg += GPIO_REG_OFFSET(offset) * 4; reg 417 drivers/pinctrl/bcm/pinctrl-bcm2835.c value = bcm2835_gpio_rd(pc, reg); reg 422 drivers/pinctrl/bcm/pinctrl-bcm2835.c bcm2835_gpio_wr(pc, reg, value); reg 60 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c #define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg)) reg 139 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg, reg 142 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c unsigned int offset = IPROC_GPIO_REG(gpio, reg); reg 154 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg, reg 157 drivers/pinctrl/bcm/pinctrl-iproc-gpio.c unsigned int offset = IPROC_GPIO_REG(gpio, reg); reg 105 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c unsigned int reg, unsigned gpio, bool set) reg 115 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c val = readl(base_address + reg); reg 121 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c writel(val, base_address + reg); reg 129 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c unsigned int reg, unsigned gpio) reg 132 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c return !!(readl(chip->io_ctrl + reg) & BIT(gpio)); reg 134 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c return !!(readl(chip->base + reg) & BIT(gpio)); reg 52 drivers/pinctrl/cirrus/pinctrl-lochnagar.c .name = NAME, .type = LN_PTYPE_GPIO, .reg = LOCHNAGAR##REV##_##REG, \ reg 71 drivers/pinctrl/cirrus/pinctrl-lochnagar.c { .name = NAME, .type = LN_PTYPE_MUX, .reg = LOCHNAGAR1_##ID, } reg 80 drivers/pinctrl/cirrus/pinctrl-lochnagar.c { .name = NAME, .type = LN_PTYPE_MUX, .reg = LOCHNAGAR2_GPIO_##ID, } reg 195 drivers/pinctrl/cirrus/pinctrl-lochnagar.c unsigned int reg; reg 854 drivers/pinctrl/cirrus/pinctrl-lochnagar.c ret = regmap_write(priv->lochnagar->regmap, pin->reg, op); reg 894 drivers/pinctrl/cirrus/pinctrl-lochnagar.c ret = regmap_update_bits(regmap, pin->reg, reg 1081 drivers/pinctrl/cirrus/pinctrl-lochnagar.c ret = regmap_update_bits(lochnagar->regmap, pin->reg, reg 518 drivers/pinctrl/cirrus/pinctrl-madera-core.c unsigned int reg = MADERA_GPIO1_CTRL_1 + (2 * pin); reg 522 drivers/pinctrl/cirrus/pinctrl-madera-core.c ret = regmap_read(priv->madera->regmap, reg, &conf[0]); reg 526 drivers/pinctrl/cirrus/pinctrl-madera-core.c ret = regmap_read(priv->madera->regmap, reg + 1, &conf[1]); reg 617 drivers/pinctrl/cirrus/pinctrl-madera-core.c unsigned int reg; reg 637 drivers/pinctrl/cirrus/pinctrl-madera-core.c reg = MADERA_GPIO1_CTRL_1 + (2 * pin_group->pins[i]); reg 640 drivers/pinctrl/cirrus/pinctrl-madera-core.c __func__, reg); reg 642 drivers/pinctrl/cirrus/pinctrl-madera-core.c ret = regmap_update_bits(madera->regmap, reg, reg 655 drivers/pinctrl/cirrus/pinctrl-madera-core.c reg = MADERA_GPIO1_CTRL_1 + (2 * group); reg 658 drivers/pinctrl/cirrus/pinctrl-madera-core.c __func__, reg, madera_mux_funcs[selector].func); reg 661 drivers/pinctrl/cirrus/pinctrl-madera-core.c reg, reg 667 drivers/pinctrl/cirrus/pinctrl-madera-core.c dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret); reg 679 drivers/pinctrl/cirrus/pinctrl-madera-core.c unsigned int reg = MADERA_GPIO1_CTRL_2 + (2 * offset); reg 688 drivers/pinctrl/cirrus/pinctrl-madera-core.c ret = regmap_update_bits(madera->regmap, reg, MADERA_GP1_DIR_MASK, val); reg 690 drivers/pinctrl/cirrus/pinctrl-madera-core.c dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret); reg 701 drivers/pinctrl/cirrus/pinctrl-madera-core.c unsigned int reg = MADERA_GPIO1_CTRL_1 + (2 * offset); reg 705 drivers/pinctrl/cirrus/pinctrl-madera-core.c ret = regmap_update_bits(madera->regmap, reg, MADERA_GP1_FN_MASK, 1); reg 707 drivers/pinctrl/cirrus/pinctrl-madera-core.c dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret); reg 718 drivers/pinctrl/cirrus/pinctrl-madera-core.c unsigned int reg = MADERA_GPIO1_CTRL_1 + (2 * offset); reg 724 drivers/pinctrl/cirrus/pinctrl-madera-core.c ret = regmap_update_bits(madera->regmap, reg, MADERA_GP1_FN_MASK, 1); reg 726 drivers/pinctrl/cirrus/pinctrl-madera-core.c dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret); reg 746 drivers/pinctrl/cirrus/pinctrl-madera-core.c unsigned int reg = MADERA_GPIO1_CTRL_1 + (2 * pin); reg 750 drivers/pinctrl/cirrus/pinctrl-madera-core.c ret = regmap_read(priv->madera->regmap, reg, &conf[0]); reg 752 drivers/pinctrl/cirrus/pinctrl-madera-core.c ret = regmap_read(priv->madera->regmap, reg + 1, &conf[1]); reg 825 drivers/pinctrl/cirrus/pinctrl-madera-core.c unsigned int reg = MADERA_GPIO1_CTRL_1 + (2 * pin); reg 924 drivers/pinctrl/cirrus/pinctrl-madera-core.c __func__, pin + 1, reg, conf[0], reg + 1, conf[1]); reg 926 drivers/pinctrl/cirrus/pinctrl-madera-core.c ret = regmap_update_bits(priv->madera->regmap, reg, mask[0], conf[0]); reg 930 drivers/pinctrl/cirrus/pinctrl-madera-core.c ++reg; reg 931 drivers/pinctrl/cirrus/pinctrl-madera-core.c ret = regmap_update_bits(priv->madera->regmap, reg, mask[1], conf[1]); reg 940 drivers/pinctrl/cirrus/pinctrl-madera-core.c pin + 1, ret, reg); reg 180 drivers/pinctrl/freescale/pinctrl-imx.c u32 reg; reg 182 drivers/pinctrl/freescale/pinctrl-imx.c reg = readl(ipctl->base + pin_reg->mux_reg); reg 183 drivers/pinctrl/freescale/pinctrl-imx.c reg &= ~info->mux_mask; reg 184 drivers/pinctrl/freescale/pinctrl-imx.c reg |= (pin_mmio->mux_mode << info->mux_shift); reg 185 drivers/pinctrl/freescale/pinctrl-imx.c writel(reg, ipctl->base + pin_reg->mux_reg); reg 187 drivers/pinctrl/freescale/pinctrl-imx.c pin_reg->mux_reg, reg); reg 401 drivers/pinctrl/freescale/pinctrl-imx.c u32 reg; reg 402 drivers/pinctrl/freescale/pinctrl-imx.c reg = readl(ipctl->base + pin_reg->conf_reg); reg 403 drivers/pinctrl/freescale/pinctrl-imx.c reg &= info->mux_mask; reg 404 drivers/pinctrl/freescale/pinctrl-imx.c reg |= configs[i]; reg 405 drivers/pinctrl/freescale/pinctrl-imx.c writel(reg, ipctl->base + pin_reg->conf_reg); reg 407 drivers/pinctrl/freescale/pinctrl-imx.c pin_reg->conf_reg, reg); reg 88 drivers/pinctrl/freescale/pinctrl-imx1-core.c void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; reg 96 drivers/pinctrl/freescale/pinctrl-imx1-core.c reg += 0x04; reg 99 drivers/pinctrl/freescale/pinctrl-imx1-core.c reg, offset, value); reg 102 drivers/pinctrl/freescale/pinctrl-imx1-core.c old_val = readl(reg); reg 109 drivers/pinctrl/freescale/pinctrl-imx1-core.c writel(new_val, reg); reg 115 drivers/pinctrl/freescale/pinctrl-imx1-core.c void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; reg 122 drivers/pinctrl/freescale/pinctrl-imx1-core.c old_val = readl(reg); reg 129 drivers/pinctrl/freescale/pinctrl-imx1-core.c writel(new_val, reg); reg 135 drivers/pinctrl/freescale/pinctrl-imx1-core.c void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; reg 140 drivers/pinctrl/freescale/pinctrl-imx1-core.c reg += 0x04; reg 142 drivers/pinctrl/freescale/pinctrl-imx1-core.c return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset; reg 148 drivers/pinctrl/freescale/pinctrl-imx1-core.c void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; reg 151 drivers/pinctrl/freescale/pinctrl-imx1-core.c return !!(readl(reg) & BIT(offset)); reg 268 drivers/pinctrl/freescale/pinctrl-imx7ulp.c u32 reg; reg 274 drivers/pinctrl/freescale/pinctrl-imx7ulp.c reg = readl(ipctl->base + pin_reg->mux_reg); reg 276 drivers/pinctrl/freescale/pinctrl-imx7ulp.c reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED; reg 278 drivers/pinctrl/freescale/pinctrl-imx7ulp.c reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED; reg 279 drivers/pinctrl/freescale/pinctrl-imx7ulp.c writel(reg, ipctl->base + pin_reg->mux_reg); reg 71 drivers/pinctrl/freescale/pinctrl-mxs.c u32 val, reg; reg 75 drivers/pinctrl/freescale/pinctrl-mxs.c if (of_property_read_u32(np, "reg", ®)) reg 106 drivers/pinctrl/freescale/pinctrl-mxs.c snprintf(group, length, "%s.%d", np->name, reg); reg 190 drivers/pinctrl/freescale/pinctrl-mxs.c static void mxs_pinctrl_rmwl(u32 value, u32 mask, u8 shift, void __iomem *reg) reg 194 drivers/pinctrl/freescale/pinctrl-mxs.c tmp = readl(reg); reg 197 drivers/pinctrl/freescale/pinctrl-mxs.c writel(tmp, reg); reg 205 drivers/pinctrl/freescale/pinctrl-mxs.c void __iomem *reg; reg 213 drivers/pinctrl/freescale/pinctrl-mxs.c reg = d->base + d->soc->regs->muxsel; reg 214 drivers/pinctrl/freescale/pinctrl-mxs.c reg += bank * 0x20 + pin / 16 * 0x10; reg 217 drivers/pinctrl/freescale/pinctrl-mxs.c mxs_pinctrl_rmwl(g->muxsel[i], 0x3, shift, reg); reg 259 drivers/pinctrl/freescale/pinctrl-mxs.c void __iomem *reg; reg 278 drivers/pinctrl/freescale/pinctrl-mxs.c reg = d->base + d->soc->regs->drive; reg 279 drivers/pinctrl/freescale/pinctrl-mxs.c reg += bank * 0x40 + pin / 8 * 0x10; reg 284 drivers/pinctrl/freescale/pinctrl-mxs.c mxs_pinctrl_rmwl(ma, 0x3, shift, reg); reg 291 drivers/pinctrl/freescale/pinctrl-mxs.c writel(1 << shift, reg + SET); reg 293 drivers/pinctrl/freescale/pinctrl-mxs.c writel(1 << shift, reg + CLR); reg 298 drivers/pinctrl/freescale/pinctrl-mxs.c reg = d->base + d->soc->regs->pull; reg 299 drivers/pinctrl/freescale/pinctrl-mxs.c reg += bank * 0x10; reg 302 drivers/pinctrl/freescale/pinctrl-mxs.c writel(1 << shift, reg + SET); reg 304 drivers/pinctrl/freescale/pinctrl-mxs.c writel(1 << shift, reg + CLR); reg 299 drivers/pinctrl/freescale/pinctrl-vf610.c u32 reg; reg 306 drivers/pinctrl/freescale/pinctrl-vf610.c reg = readl(ipctl->base + pin_reg->mux_reg); reg 308 drivers/pinctrl/freescale/pinctrl-vf610.c reg &= ~0x2; reg 310 drivers/pinctrl/freescale/pinctrl-vf610.c reg |= 0x2; reg 311 drivers/pinctrl/freescale/pinctrl-vf610.c writel(reg, ipctl->base + pin_reg->mux_reg); reg 569 drivers/pinctrl/intel/pinctrl-baytrail.c int reg) reg 578 drivers/pinctrl/intel/pinctrl-baytrail.c switch (reg) { reg 590 drivers/pinctrl/intel/pinctrl-baytrail.c return comm->pad_regs + reg_offset + reg; reg 749 drivers/pinctrl/intel/pinctrl-baytrail.c void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); reg 754 drivers/pinctrl/intel/pinctrl-baytrail.c value = readl(reg); reg 762 drivers/pinctrl/intel/pinctrl-baytrail.c writel(value, reg); reg 771 drivers/pinctrl/intel/pinctrl-baytrail.c void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); reg 786 drivers/pinctrl/intel/pinctrl-baytrail.c value = readl(reg) & BYT_PIN_MUX; reg 789 drivers/pinctrl/intel/pinctrl-baytrail.c value = readl(reg) & ~BYT_PIN_MUX; reg 791 drivers/pinctrl/intel/pinctrl-baytrail.c writel(value, reg); reg 857 drivers/pinctrl/intel/pinctrl-baytrail.c static void byt_get_pull_strength(u32 reg, u16 *strength) reg 859 drivers/pinctrl/intel/pinctrl-baytrail.c switch (reg & BYT_PULL_STR_MASK) { reg 875 drivers/pinctrl/intel/pinctrl-baytrail.c static int byt_set_pull_strength(u32 *reg, u16 strength) reg 877 drivers/pinctrl/intel/pinctrl-baytrail.c *reg &= ~BYT_PULL_STR_MASK; reg 881 drivers/pinctrl/intel/pinctrl-baytrail.c *reg |= BYT_PULL_STR_2K; reg 884 drivers/pinctrl/intel/pinctrl-baytrail.c *reg |= BYT_PULL_STR_10K; reg 887 drivers/pinctrl/intel/pinctrl-baytrail.c *reg |= BYT_PULL_STR_20K; reg 890 drivers/pinctrl/intel/pinctrl-baytrail.c *reg |= BYT_PULL_STR_40K; reg 1125 drivers/pinctrl/intel/pinctrl-baytrail.c void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); reg 1130 drivers/pinctrl/intel/pinctrl-baytrail.c val = readl(reg); reg 1139 drivers/pinctrl/intel/pinctrl-baytrail.c void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); reg 1143 drivers/pinctrl/intel/pinctrl-baytrail.c if (!reg) reg 1147 drivers/pinctrl/intel/pinctrl-baytrail.c old_val = readl(reg); reg 1149 drivers/pinctrl/intel/pinctrl-baytrail.c writel(old_val | BYT_LEVEL, reg); reg 1151 drivers/pinctrl/intel/pinctrl-baytrail.c writel(old_val & ~BYT_LEVEL, reg); reg 1158 drivers/pinctrl/intel/pinctrl-baytrail.c void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); reg 1162 drivers/pinctrl/intel/pinctrl-baytrail.c if (!reg) reg 1166 drivers/pinctrl/intel/pinctrl-baytrail.c value = readl(reg); reg 1205 drivers/pinctrl/intel/pinctrl-baytrail.c void __iomem *reg; reg 1212 drivers/pinctrl/intel/pinctrl-baytrail.c reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); reg 1213 drivers/pinctrl/intel/pinctrl-baytrail.c if (!reg) { reg 1220 drivers/pinctrl/intel/pinctrl-baytrail.c conf0 = readl(reg); reg 1222 drivers/pinctrl/intel/pinctrl-baytrail.c reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); reg 1223 drivers/pinctrl/intel/pinctrl-baytrail.c if (!reg) { reg 1229 drivers/pinctrl/intel/pinctrl-baytrail.c val = readl(reg); reg 1309 drivers/pinctrl/intel/pinctrl-baytrail.c void __iomem *reg; reg 1311 drivers/pinctrl/intel/pinctrl-baytrail.c reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG); reg 1312 drivers/pinctrl/intel/pinctrl-baytrail.c if (!reg) reg 1316 drivers/pinctrl/intel/pinctrl-baytrail.c writel(BIT(offset % 32), reg); reg 1334 drivers/pinctrl/intel/pinctrl-baytrail.c void __iomem *reg; reg 1337 drivers/pinctrl/intel/pinctrl-baytrail.c reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); reg 1338 drivers/pinctrl/intel/pinctrl-baytrail.c if (!reg) reg 1342 drivers/pinctrl/intel/pinctrl-baytrail.c value = readl(reg); reg 1362 drivers/pinctrl/intel/pinctrl-baytrail.c writel(value, reg); reg 1373 drivers/pinctrl/intel/pinctrl-baytrail.c void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); reg 1375 drivers/pinctrl/intel/pinctrl-baytrail.c if (!reg || offset >= vg->chip.ngpio) reg 1379 drivers/pinctrl/intel/pinctrl-baytrail.c value = readl(reg); reg 1393 drivers/pinctrl/intel/pinctrl-baytrail.c writel(value, reg); reg 1421 drivers/pinctrl/intel/pinctrl-baytrail.c void __iomem *reg; reg 1427 drivers/pinctrl/intel/pinctrl-baytrail.c reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); reg 1429 drivers/pinctrl/intel/pinctrl-baytrail.c if (!reg) { reg 1437 drivers/pinctrl/intel/pinctrl-baytrail.c pending = readl(reg); reg 1465 drivers/pinctrl/intel/pinctrl-baytrail.c void __iomem *reg; reg 1477 drivers/pinctrl/intel/pinctrl-baytrail.c reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); reg 1478 drivers/pinctrl/intel/pinctrl-baytrail.c if (!reg) { reg 1485 drivers/pinctrl/intel/pinctrl-baytrail.c value = readl(reg); reg 1497 drivers/pinctrl/intel/pinctrl-baytrail.c reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); reg 1499 drivers/pinctrl/intel/pinctrl-baytrail.c if (!reg) { reg 1506 drivers/pinctrl/intel/pinctrl-baytrail.c writel(0xffffffff, reg); reg 1509 drivers/pinctrl/intel/pinctrl-baytrail.c value = readl(reg); reg 1669 drivers/pinctrl/intel/pinctrl-baytrail.c void __iomem *reg; reg 1673 drivers/pinctrl/intel/pinctrl-baytrail.c reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); reg 1674 drivers/pinctrl/intel/pinctrl-baytrail.c if (!reg) { reg 1680 drivers/pinctrl/intel/pinctrl-baytrail.c value = readl(reg) & BYT_CONF0_RESTORE_MASK; reg 1683 drivers/pinctrl/intel/pinctrl-baytrail.c reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); reg 1684 drivers/pinctrl/intel/pinctrl-baytrail.c value = readl(reg) & BYT_VAL_RESTORE_MASK; reg 1701 drivers/pinctrl/intel/pinctrl-baytrail.c void __iomem *reg; reg 1705 drivers/pinctrl/intel/pinctrl-baytrail.c reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); reg 1706 drivers/pinctrl/intel/pinctrl-baytrail.c if (!reg) { reg 1712 drivers/pinctrl/intel/pinctrl-baytrail.c value = readl(reg); reg 1717 drivers/pinctrl/intel/pinctrl-baytrail.c writel(value, reg); reg 1721 drivers/pinctrl/intel/pinctrl-baytrail.c reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); reg 1722 drivers/pinctrl/intel/pinctrl-baytrail.c value = readl(reg); reg 1730 drivers/pinctrl/intel/pinctrl-baytrail.c writel(v, reg); reg 667 drivers/pinctrl/intel/pinctrl-cherryview.c unsigned int reg) reg 675 drivers/pinctrl/intel/pinctrl-cherryview.c return pctrl->regs + offset + reg; reg 678 drivers/pinctrl/intel/pinctrl-cherryview.c static void chv_writel(u32 value, void __iomem *reg) reg 680 drivers/pinctrl/intel/pinctrl-cherryview.c writel(value, reg); reg 682 drivers/pinctrl/intel/pinctrl-cherryview.c readl(reg); reg 688 drivers/pinctrl/intel/pinctrl-cherryview.c void __iomem *reg; reg 690 drivers/pinctrl/intel/pinctrl-cherryview.c reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); reg 691 drivers/pinctrl/intel/pinctrl-cherryview.c return readl(reg) & CHV_PADCTRL1_CFGLOCK; reg 811 drivers/pinctrl/intel/pinctrl-cherryview.c void __iomem *reg; reg 826 drivers/pinctrl/intel/pinctrl-cherryview.c reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); reg 827 drivers/pinctrl/intel/pinctrl-cherryview.c value = readl(reg); reg 833 drivers/pinctrl/intel/pinctrl-cherryview.c chv_writel(value, reg); reg 836 drivers/pinctrl/intel/pinctrl-cherryview.c reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); reg 837 drivers/pinctrl/intel/pinctrl-cherryview.c value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK; reg 840 drivers/pinctrl/intel/pinctrl-cherryview.c chv_writel(value, reg); reg 854 drivers/pinctrl/intel/pinctrl-cherryview.c void __iomem *reg; reg 857 drivers/pinctrl/intel/pinctrl-cherryview.c reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); reg 858 drivers/pinctrl/intel/pinctrl-cherryview.c value = readl(reg); reg 861 drivers/pinctrl/intel/pinctrl-cherryview.c chv_writel(value, reg); reg 870 drivers/pinctrl/intel/pinctrl-cherryview.c void __iomem *reg; reg 896 drivers/pinctrl/intel/pinctrl-cherryview.c reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); reg 897 drivers/pinctrl/intel/pinctrl-cherryview.c value = readl(reg); reg 912 drivers/pinctrl/intel/pinctrl-cherryview.c chv_writel(value, reg); reg 940 drivers/pinctrl/intel/pinctrl-cherryview.c void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); reg 946 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK; reg 951 drivers/pinctrl/intel/pinctrl-cherryview.c chv_writel(ctrl0, reg); reg 1051 drivers/pinctrl/intel/pinctrl-cherryview.c void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); reg 1056 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 = readl(reg); reg 1108 drivers/pinctrl/intel/pinctrl-cherryview.c chv_writel(ctrl0, reg); reg 1117 drivers/pinctrl/intel/pinctrl-cherryview.c void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); reg 1122 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl1 = readl(reg); reg 1129 drivers/pinctrl/intel/pinctrl-cherryview.c chv_writel(ctrl1, reg); reg 1259 drivers/pinctrl/intel/pinctrl-cherryview.c void __iomem *reg; reg 1264 drivers/pinctrl/intel/pinctrl-cherryview.c reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); reg 1265 drivers/pinctrl/intel/pinctrl-cherryview.c ctrl0 = readl(reg); reg 1272 drivers/pinctrl/intel/pinctrl-cherryview.c chv_writel(ctrl0, reg); reg 1433 drivers/pinctrl/intel/pinctrl-cherryview.c void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); reg 1435 drivers/pinctrl/intel/pinctrl-cherryview.c value = readl(reg); reg 1452 drivers/pinctrl/intel/pinctrl-cherryview.c chv_writel(value, reg); reg 1770 drivers/pinctrl/intel/pinctrl-cherryview.c void __iomem *reg; reg 1778 drivers/pinctrl/intel/pinctrl-cherryview.c reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); reg 1779 drivers/pinctrl/intel/pinctrl-cherryview.c ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; reg 1781 drivers/pinctrl/intel/pinctrl-cherryview.c reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); reg 1782 drivers/pinctrl/intel/pinctrl-cherryview.c ctx->padctrl1 = readl(reg); reg 1808 drivers/pinctrl/intel/pinctrl-cherryview.c void __iomem *reg; reg 1818 drivers/pinctrl/intel/pinctrl-cherryview.c reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); reg 1819 drivers/pinctrl/intel/pinctrl-cherryview.c val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; reg 1821 drivers/pinctrl/intel/pinctrl-cherryview.c chv_writel(ctx->padctrl0, reg); reg 1823 drivers/pinctrl/intel/pinctrl-cherryview.c desc->number, readl(reg)); reg 1826 drivers/pinctrl/intel/pinctrl-cherryview.c reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); reg 1827 drivers/pinctrl/intel/pinctrl-cherryview.c val = readl(reg); reg 1829 drivers/pinctrl/intel/pinctrl-cherryview.c chv_writel(ctx->padctrl1, reg); reg 1831 drivers/pinctrl/intel/pinctrl-cherryview.c desc->number, readl(reg)); reg 158 drivers/pinctrl/intel/pinctrl-intel.c unsigned int pin, unsigned int reg) reg 171 drivers/pinctrl/intel/pinctrl-intel.c if (reg >= nregs * 4) reg 174 drivers/pinctrl/intel/pinctrl-intel.c return community->pad_regs + reg + padno * nregs * 4; reg 881 drivers/pinctrl/intel/pinctrl-intel.c void __iomem *reg; reg 889 drivers/pinctrl/intel/pinctrl-intel.c reg = intel_get_padcfg(pctrl, pin, PADCFG0); reg 890 drivers/pinctrl/intel/pinctrl-intel.c if (!reg) reg 893 drivers/pinctrl/intel/pinctrl-intel.c padcfg0 = readl(reg); reg 905 drivers/pinctrl/intel/pinctrl-intel.c void __iomem *reg; reg 913 drivers/pinctrl/intel/pinctrl-intel.c reg = intel_get_padcfg(pctrl, pin, PADCFG0); reg 914 drivers/pinctrl/intel/pinctrl-intel.c if (!reg) reg 918 drivers/pinctrl/intel/pinctrl-intel.c padcfg0 = readl(reg); reg 923 drivers/pinctrl/intel/pinctrl-intel.c writel(padcfg0, reg); reg 930 drivers/pinctrl/intel/pinctrl-intel.c void __iomem *reg; reg 938 drivers/pinctrl/intel/pinctrl-intel.c reg = intel_get_padcfg(pctrl, pin, PADCFG0); reg 939 drivers/pinctrl/intel/pinctrl-intel.c if (!reg) reg 942 drivers/pinctrl/intel/pinctrl-intel.c padcfg0 = readl(reg); reg 1008 drivers/pinctrl/intel/pinctrl-intel.c void __iomem *reg, *is; reg 1014 drivers/pinctrl/intel/pinctrl-intel.c reg = community->regs + community->ie_offset + gpp * 4; reg 1022 drivers/pinctrl/intel/pinctrl-intel.c value = readl(reg); reg 1027 drivers/pinctrl/intel/pinctrl-intel.c writel(value, reg); reg 1048 drivers/pinctrl/intel/pinctrl-intel.c void __iomem *reg; reg 1051 drivers/pinctrl/intel/pinctrl-intel.c reg = intel_get_padcfg(pctrl, pin, PADCFG0); reg 1052 drivers/pinctrl/intel/pinctrl-intel.c if (!reg) reg 1067 drivers/pinctrl/intel/pinctrl-intel.c intel_gpio_set_gpio_mode(reg); reg 1069 drivers/pinctrl/intel/pinctrl-intel.c value = readl(reg); reg 1087 drivers/pinctrl/intel/pinctrl-intel.c writel(value, reg); reg 55 drivers/pinctrl/mediatek/mtk-eint.c void __iomem *reg; reg 60 drivers/pinctrl/mediatek/mtk-eint.c reg = eint->base + offset + ((eint_num - eint_base) / 32) * 4; reg 62 drivers/pinctrl/mediatek/mtk-eint.c return reg; reg 70 drivers/pinctrl/mediatek/mtk-eint.c void __iomem *reg = mtk_eint_get_offset(eint, eint_num, reg 73 drivers/pinctrl/mediatek/mtk-eint.c if (readl(reg) & bit) reg 90 drivers/pinctrl/mediatek/mtk-eint.c void __iomem *reg = eint->base + (port << 2); reg 100 drivers/pinctrl/mediatek/mtk-eint.c writel(mask, reg + reg_offset); reg 113 drivers/pinctrl/mediatek/mtk-eint.c void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, reg 118 drivers/pinctrl/mediatek/mtk-eint.c writel(mask, reg); reg 125 drivers/pinctrl/mediatek/mtk-eint.c void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, reg 130 drivers/pinctrl/mediatek/mtk-eint.c writel(mask, reg); reg 140 drivers/pinctrl/mediatek/mtk-eint.c void __iomem *reg = mtk_eint_get_offset(eint, eint_num, reg 143 drivers/pinctrl/mediatek/mtk-eint.c return !!(readl(reg) & bit); reg 150 drivers/pinctrl/mediatek/mtk-eint.c void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq, reg 153 drivers/pinctrl/mediatek/mtk-eint.c writel(mask, reg); reg 160 drivers/pinctrl/mediatek/mtk-eint.c void __iomem *reg; reg 176 drivers/pinctrl/mediatek/mtk-eint.c reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr); reg 177 drivers/pinctrl/mediatek/mtk-eint.c writel(mask, reg); reg 179 drivers/pinctrl/mediatek/mtk-eint.c reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_set); reg 180 drivers/pinctrl/mediatek/mtk-eint.c writel(mask, reg); reg 184 drivers/pinctrl/mediatek/mtk-eint.c reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr); reg 185 drivers/pinctrl/mediatek/mtk-eint.c writel(mask, reg); reg 187 drivers/pinctrl/mediatek/mtk-eint.c reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_set); reg 188 drivers/pinctrl/mediatek/mtk-eint.c writel(mask, reg); reg 201 drivers/pinctrl/mediatek/mtk-eint.c int reg = d->hwirq >> 5; reg 204 drivers/pinctrl/mediatek/mtk-eint.c eint->wake_mask[reg] |= BIT(shift); reg 206 drivers/pinctrl/mediatek/mtk-eint.c eint->wake_mask[reg] &= ~BIT(shift); reg 215 drivers/pinctrl/mediatek/mtk-eint.c void __iomem *reg; reg 218 drivers/pinctrl/mediatek/mtk-eint.c reg = base + (port << 2); reg 219 drivers/pinctrl/mediatek/mtk-eint.c writel_relaxed(~buf[port], reg + eint->regs->mask_set); reg 220 drivers/pinctrl/mediatek/mtk-eint.c writel_relaxed(buf[port], reg + eint->regs->mask_clr); reg 280 drivers/pinctrl/mediatek/mtk-eint.c void __iomem *reg = eint->base + eint->regs->dom_en; reg 284 drivers/pinctrl/mediatek/mtk-eint.c writel(0xffffffff, reg); reg 285 drivers/pinctrl/mediatek/mtk-eint.c reg += 4; reg 313 drivers/pinctrl/mediatek/mtk-eint.c void __iomem *reg = mtk_eint_get_offset(eint, 0, eint->regs->stat); reg 318 drivers/pinctrl/mediatek/mtk-eint.c reg += 4) { reg 319 drivers/pinctrl/mediatek/mtk-eint.c status = readl(reg); reg 335 drivers/pinctrl/mediatek/mtk-eint.c writel_relaxed(BIT(offset), reg - reg 346 drivers/pinctrl/mediatek/mtk-eint.c writel(BIT(offset), reg - eint->regs->stat + reg 364 drivers/pinctrl/mediatek/mtk-eint.c writel(BIT(offset), reg - reg 102 drivers/pinctrl/mediatek/pinctrl-moore.c int val, val2, err, reg, ret = 1; reg 180 drivers/pinctrl/mediatek/pinctrl-moore.c reg = (param == MTK_PIN_CONFIG_TDSEL) ? reg 183 drivers/pinctrl/mediatek/pinctrl-moore.c err = mtk_hw_get_value(hw, desc, reg, &val); reg 217 drivers/pinctrl/mediatek/pinctrl-moore.c u32 reg, param, arg; reg 321 drivers/pinctrl/mediatek/pinctrl-moore.c reg = (param == MTK_PIN_CONFIG_TDSEL) ? reg 324 drivers/pinctrl/mediatek/pinctrl-moore.c err = mtk_hw_set_value(hw, desc, reg, arg); reg 474 drivers/pinctrl/mediatek/pinctrl-mt2701.c static void mt2701_spec_pinmux_set(struct regmap *reg, unsigned int pin, reg 495 drivers/pinctrl/mediatek/pinctrl-mt2701.c regmap_update_bits(reg, mt2701_spec_pinmux[i].offset, mask, value); reg 45 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val) reg 47 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c writel_relaxed(val, pctl->base[i] + reg); reg 50 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg) reg 52 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c return readl_relaxed(pctl->base[i] + reg); reg 55 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set) reg 59 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c val = mtk_r32(pctl, i, reg); reg 62 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c mtk_w32(pctl, i, reg, val); reg 414 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c int reg, err, v; reg 416 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c reg = pullup ? PINCTRL_PIN_REG_PU : PINCTRL_PIN_REG_PD; reg 418 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c err = mtk_hw_get_value(hw, desc, reg, &v); reg 251 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set); reg 234 drivers/pinctrl/mediatek/pinctrl-mtk-common.h int (*spec_pull_set)(struct regmap *reg, unsigned int pin, reg 236 drivers/pinctrl/mediatek/pinctrl-mtk-common.h int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin, reg 238 drivers/pinctrl/mediatek/pinctrl-mtk-common.h void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin, reg 81 drivers/pinctrl/mediatek/pinctrl-paris.c int val, val2, err, reg, ret = 1; reg 159 drivers/pinctrl/mediatek/pinctrl-paris.c reg = (param == MTK_PIN_CONFIG_TDSEL) ? reg 162 drivers/pinctrl/mediatek/pinctrl-paris.c err = mtk_hw_get_value(hw, desc, reg, &val); reg 207 drivers/pinctrl/mediatek/pinctrl-paris.c u32 reg; reg 305 drivers/pinctrl/mediatek/pinctrl-paris.c reg = (param == MTK_PIN_CONFIG_TDSEL) ? reg 308 drivers/pinctrl/mediatek/pinctrl-paris.c err = mtk_hw_set_value(hw, desc, reg, arg); reg 47 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c unsigned int pin, unsigned int *reg, reg 54 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c *reg = bank->reg + (bank->offset + (shift << 2)) / 32; reg 64 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c int reg; reg 72 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c meson_pmx_calc_reg_and_offset(bank, pin, ®, &offset); reg 74 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c ret = regmap_update_bits(pc->reg_mux, reg << 2, reg 15 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h unsigned int reg; reg 29 drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h .reg = r, \ reg 95 drivers/pinctrl/meson/pinctrl-meson.c unsigned int *reg, unsigned int *bit) reg 99 drivers/pinctrl/meson/pinctrl-meson.c *reg = desc->reg * 4; reg 177 drivers/pinctrl/meson/pinctrl-meson.c unsigned int reg, bit; reg 184 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, pin, reg_type, ®, &bit); reg 185 drivers/pinctrl/meson/pinctrl-meson.c return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), reg 194 drivers/pinctrl/meson/pinctrl-meson.c unsigned int reg, bit, val; reg 201 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, pin, reg_type, ®, &bit); reg 202 drivers/pinctrl/meson/pinctrl-meson.c ret = regmap_read(pc->reg_gpio, reg, &val); reg 257 drivers/pinctrl/meson/pinctrl-meson.c unsigned int reg, bit = 0; reg 264 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); reg 265 drivers/pinctrl/meson/pinctrl-meson.c ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), 0); reg 276 drivers/pinctrl/meson/pinctrl-meson.c unsigned int reg, bit, val = 0; reg 283 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); reg 287 drivers/pinctrl/meson/pinctrl-meson.c ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), val); reg 291 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); reg 292 drivers/pinctrl/meson/pinctrl-meson.c ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit)); reg 304 drivers/pinctrl/meson/pinctrl-meson.c unsigned int reg, bit, ds_val; reg 316 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit); reg 334 drivers/pinctrl/meson/pinctrl-meson.c ret = regmap_update_bits(pc->reg_ds, reg, 0x3 << bit, ds_val << bit); reg 396 drivers/pinctrl/meson/pinctrl-meson.c unsigned int reg, bit, val; reg 403 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); reg 405 drivers/pinctrl/meson/pinctrl-meson.c ret = regmap_read(pc->reg_pullen, reg, &val); reg 412 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); reg 414 drivers/pinctrl/meson/pinctrl-meson.c ret = regmap_read(pc->reg_pull, reg, &val); reg 432 drivers/pinctrl/meson/pinctrl-meson.c unsigned int reg, bit; reg 443 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, pin, REG_DS, ®, &bit); reg 446 drivers/pinctrl/meson/pinctrl-meson.c ret = regmap_read(pc->reg_ds, reg, &val); reg 572 drivers/pinctrl/meson/pinctrl-meson.c unsigned int reg, bit, val; reg 580 drivers/pinctrl/meson/pinctrl-meson.c meson_calc_reg_and_bit(bank, gpio, REG_IN, ®, &bit); reg 581 drivers/pinctrl/meson/pinctrl-meson.c regmap_read(pc->reg_gpio, reg, &val); reg 55 drivers/pinctrl/meson/pinctrl-meson.h unsigned int reg; reg 49 drivers/pinctrl/meson/pinctrl-meson8-pmx.c pmx_data->reg * 4, reg 78 drivers/pinctrl/meson/pinctrl-meson8-pmx.c ret = regmap_update_bits(pc->reg_mux, pmx_data->reg * 4, reg 11 drivers/pinctrl/meson/pinctrl-meson8-pmx.h unsigned int reg; reg 17 drivers/pinctrl/meson/pinctrl-meson8-pmx.h .reg = r, \ reg 223 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c static inline void armada_37xx_update_reg(unsigned int *reg, reg 229 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c *reg += sizeof(u32); reg 344 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c unsigned int reg = SELECTION; reg 357 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c regmap_update_bits(info->regmap, reg, mask, val); reg 374 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c static inline void armada_37xx_irq_update_reg(unsigned int *reg, reg 379 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c armada_37xx_update_reg(reg, &offset); reg 386 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c unsigned int reg = OUTPUT_EN; reg 389 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c armada_37xx_update_reg(®, &offset); reg 392 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c return regmap_update_bits(info->regmap, reg, mask, 0); reg 399 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c unsigned int reg = OUTPUT_EN; reg 402 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c armada_37xx_update_reg(®, &offset); reg 404 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c regmap_read(info->regmap, reg, &val); reg 413 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c unsigned int reg = OUTPUT_EN; reg 416 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c armada_37xx_update_reg(®, &offset); reg 419 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c ret = regmap_update_bits(info->regmap, reg, mask, mask); reg 424 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c reg = OUTPUT_VAL; reg 426 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c regmap_update_bits(info->regmap, reg, mask, val); reg 434 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c unsigned int reg = INPUT_VAL; reg 437 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c armada_37xx_update_reg(®, &offset); reg 440 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c regmap_read(info->regmap, reg, &val); reg 449 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c unsigned int reg = OUTPUT_VAL; reg 452 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c armada_37xx_update_reg(®, &offset); reg 456 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c regmap_update_bits(info->regmap, reg, mask, val); reg 517 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c u32 reg = IRQ_STATUS; reg 520 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c armada_37xx_irq_update_reg(®, d); reg 522 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(d->mask, info->base + reg); reg 530 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c u32 val, reg = IRQ_EN; reg 533 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c armada_37xx_irq_update_reg(®, d); reg 535 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val = readl(info->base + reg); reg 536 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(val & ~d->mask, info->base + reg); reg 544 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c u32 val, reg = IRQ_EN; reg 547 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c armada_37xx_irq_update_reg(®, d); reg 549 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val = readl(info->base + reg); reg 550 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(val | d->mask, info->base + reg); reg 558 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c u32 val, reg = IRQ_WKUP; reg 561 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c armada_37xx_irq_update_reg(®, d); reg 563 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val = readl(info->base + reg); reg 568 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(val, info->base + reg); reg 578 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c u32 val, reg = IRQ_POL; reg 582 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c armada_37xx_irq_update_reg(®, d); reg 583 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val = readl(info->base + reg); reg 608 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(val, info->base + reg); reg 74 drivers/pinctrl/mvebu/pinctrl-mvebu.c unsigned long reg; reg 76 drivers/pinctrl/mvebu/pinctrl-mvebu.c reg = readl(data->base + off) & ~(MVEBU_MPP_MASK << shift); reg 77 drivers/pinctrl/mvebu/pinctrl-mvebu.c writel(reg | (config << shift), data->base + off); reg 53 drivers/pinctrl/mvebu/pinctrl-orion.c u32 reg = readl(mpp_base + off) & ~(MVEBU_MPP_MASK << shift); reg 54 drivers/pinctrl/mvebu/pinctrl-orion.c writel(reg | (config << shift), mpp_base + off); reg 57 drivers/pinctrl/mvebu/pinctrl-orion.c u32 reg = readl(high_mpp_base) & ~(MVEBU_MPP_MASK << shift); reg 58 drivers/pinctrl/mvebu/pinctrl-orion.c writel(reg | (config << shift), high_mpp_base); reg 89 drivers/pinctrl/nomadik/pinctrl-abx500.c static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg, reg 97 drivers/pinctrl/nomadik/pinctrl-abx500.c reg += offset / 8; reg 99 drivers/pinctrl/nomadik/pinctrl-abx500.c AB8500_MISC, reg, &val); reg 103 drivers/pinctrl/nomadik/pinctrl-abx500.c __func__, reg, offset, ret); reg 112 drivers/pinctrl/nomadik/pinctrl-abx500.c static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg, reg 119 drivers/pinctrl/nomadik/pinctrl-abx500.c reg += offset / 8; reg 121 drivers/pinctrl/nomadik/pinctrl-abx500.c AB8500_MISC, reg, BIT(pos), val << pos); reg 124 drivers/pinctrl/nomadik/pinctrl-abx500.c __func__, reg, offset, ret); reg 437 drivers/pinctrl/nomadik/pinctrl-nomadik.c static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) reg 441 drivers/pinctrl/nomadik/pinctrl-nomadik.c val = readl(reg); reg 443 drivers/pinctrl/nomadik/pinctrl-nomadik.c writel(val, reg); reg 450 drivers/pinctrl/nomadik/pinctrl-nomadik.c u16 reg; reg 485 drivers/pinctrl/nomadik/pinctrl-nomadik.c reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; reg 487 drivers/pinctrl/nomadik/pinctrl-nomadik.c if (readl(npct->prcm_base + reg) & BIT(bit)) { reg 488 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); reg 514 drivers/pinctrl/nomadik/pinctrl-nomadik.c reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; reg 516 drivers/pinctrl/nomadik/pinctrl-nomadik.c if (readl(npct->prcm_base + reg) & BIT(bit)) { reg 517 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); reg 525 drivers/pinctrl/nomadik/pinctrl-nomadik.c reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; reg 529 drivers/pinctrl/nomadik/pinctrl-nomadik.c nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); reg 581 drivers/pinctrl/nomadik/pinctrl-nomadik.c u16 reg; reg 601 drivers/pinctrl/nomadik/pinctrl-nomadik.c reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; reg 603 drivers/pinctrl/nomadik/pinctrl-nomadik.c if (readl(npct->prcm_base + reg) & BIT(bit)) reg 102 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg, reg 110 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c val = ioread32(reg) | pinmask; reg 111 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(val, reg); reg 116 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg, reg 124 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c val = ioread32(reg) & ~pinmask; reg 125 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c iowrite32(val, reg); reg 401 drivers/pinctrl/pinctrl-amd.c u32 reg; reg 407 drivers/pinctrl/pinctrl-amd.c reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); reg 408 drivers/pinctrl/pinctrl-amd.c reg |= EOI_MASK; reg 409 drivers/pinctrl/pinctrl-amd.c writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); reg 658 drivers/pinctrl/pinctrl-artpec6.c unsigned int reg; reg 682 drivers/pinctrl/pinctrl-artpec6.c reg = artpec6_pmx_reg_offset(artpec6_pin_groups[group].pins[i]); reg 684 drivers/pinctrl/pinctrl-artpec6.c regval = readl(pmx->base + reg); reg 687 drivers/pinctrl/pinctrl-artpec6.c writel(regval, pmx->base + reg); reg 711 drivers/pinctrl/pinctrl-artpec6.c unsigned int reg = artpec6_pmx_reg_offset(pin); reg 717 drivers/pinctrl/pinctrl-artpec6.c val = readl_relaxed(pmx->base + reg); reg 720 drivers/pinctrl/pinctrl-artpec6.c writel_relaxed(val, pmx->base + reg); reg 801 drivers/pinctrl/pinctrl-artpec6.c unsigned int *reg; reg 814 drivers/pinctrl/pinctrl-artpec6.c reg = pmx->base + artpec6_pmx_reg_offset(pin); reg 825 drivers/pinctrl/pinctrl-artpec6.c regval = readl(reg); reg 827 drivers/pinctrl/pinctrl-artpec6.c writel(regval, reg); reg 837 drivers/pinctrl/pinctrl-artpec6.c regval = readl(reg); reg 840 drivers/pinctrl/pinctrl-artpec6.c writel(regval, reg); reg 850 drivers/pinctrl/pinctrl-artpec6.c regval = readl(reg); reg 853 drivers/pinctrl/pinctrl-artpec6.c writel(regval, reg); reg 864 drivers/pinctrl/pinctrl-artpec6.c regval = readl(reg); reg 867 drivers/pinctrl/pinctrl-artpec6.c writel(regval, reg); reg 444 drivers/pinctrl/pinctrl-as3722.c u32 reg; reg 465 drivers/pinctrl/pinctrl-as3722.c reg = AS3722_GPIO_SIGNAL_IN_REG; reg 469 drivers/pinctrl/pinctrl-as3722.c reg = AS3722_GPIO_SIGNAL_OUT_REG; reg 475 drivers/pinctrl/pinctrl-as3722.c ret = as3722_read(as3722, reg, &val); reg 144 drivers/pinctrl/pinctrl-at91-pio4.c unsigned int bank, unsigned int reg) reg 147 drivers/pinctrl/pinctrl-at91-pio4.c + ATMEL_PIO_BANK_OFFSET * bank + reg); reg 151 drivers/pinctrl/pinctrl-at91-pio4.c unsigned int bank, unsigned int reg, reg 155 drivers/pinctrl/pinctrl-at91-pio4.c + ATMEL_PIO_BANK_OFFSET * bank + reg); reg 170 drivers/pinctrl/pinctrl-at91-pio4.c unsigned reg; reg 174 drivers/pinctrl/pinctrl-at91-pio4.c reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); reg 175 drivers/pinctrl/pinctrl-at91-pio4.c reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK); reg 180 drivers/pinctrl/pinctrl-at91-pio4.c reg |= ATMEL_PIO_CFGR_EVTSEL_RISING; reg 184 drivers/pinctrl/pinctrl-at91-pio4.c reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING; reg 188 drivers/pinctrl/pinctrl-at91-pio4.c reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH; reg 192 drivers/pinctrl/pinctrl-at91-pio4.c reg |= ATMEL_PIO_CFGR_EVTSEL_LOW; reg 196 drivers/pinctrl/pinctrl-at91-pio4.c reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH; reg 203 drivers/pinctrl/pinctrl-at91-pio4.c atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); reg 309 drivers/pinctrl/pinctrl-at91-pio4.c unsigned reg; reg 313 drivers/pinctrl/pinctrl-at91-pio4.c reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); reg 314 drivers/pinctrl/pinctrl-at91-pio4.c reg &= ~ATMEL_PIO_DIR_MASK; reg 315 drivers/pinctrl/pinctrl-at91-pio4.c atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); reg 324 drivers/pinctrl/pinctrl-at91-pio4.c unsigned reg; reg 326 drivers/pinctrl/pinctrl-at91-pio4.c reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR); reg 328 drivers/pinctrl/pinctrl-at91-pio4.c return !!(reg & BIT(pin->line)); reg 336 drivers/pinctrl/pinctrl-at91-pio4.c unsigned reg; reg 344 drivers/pinctrl/pinctrl-at91-pio4.c reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR); reg 345 drivers/pinctrl/pinctrl-at91-pio4.c reg |= ATMEL_PIO_DIR_MASK; reg 346 drivers/pinctrl/pinctrl-at91-pio4.c atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg); reg 552 drivers/pinctrl/pinctrl-at91.c static inline u32 read_drive_strength(void __iomem *reg, unsigned pin) reg 554 drivers/pinctrl/pinctrl-at91.c unsigned tmp = readl_relaxed(reg); reg 609 drivers/pinctrl/pinctrl-at91.c static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength) reg 611 drivers/pinctrl/pinctrl-at91.c unsigned tmp = readl_relaxed(reg); reg 617 drivers/pinctrl/pinctrl-at91.c writel_relaxed(tmp, reg); reg 136 drivers/pinctrl/pinctrl-axp209.c int reg, ret; reg 138 drivers/pinctrl/pinctrl-axp209.c reg = axp20x_gpio_get_reg(offset); reg 139 drivers/pinctrl/pinctrl-axp209.c if (reg < 0) reg 140 drivers/pinctrl/pinctrl-axp209.c return reg; reg 142 drivers/pinctrl/pinctrl-axp209.c ret = regmap_read(pctl->regmap, reg, &val); reg 173 drivers/pinctrl/pinctrl-axp209.c int reg; reg 175 drivers/pinctrl/pinctrl-axp209.c reg = axp20x_gpio_get_reg(offset); reg 176 drivers/pinctrl/pinctrl-axp209.c if (reg < 0) reg 179 drivers/pinctrl/pinctrl-axp209.c regmap_update_bits(pctl->regmap, reg, reg 189 drivers/pinctrl/pinctrl-axp209.c int reg; reg 191 drivers/pinctrl/pinctrl-axp209.c reg = axp20x_gpio_get_reg(offset); reg 192 drivers/pinctrl/pinctrl-axp209.c if (reg < 0) reg 193 drivers/pinctrl/pinctrl-axp209.c return reg; reg 195 drivers/pinctrl/pinctrl-axp209.c return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS, reg 93 drivers/pinctrl/pinctrl-coh901.c #define U300_PIN_REG(pin, reg) \ reg 94 drivers/pinctrl/pinctrl-coh901.c (gpio->base + (pin >> 3) * gpio->stride + gpio->reg) reg 114 drivers/pinctrl/pinctrl-digicolor.c static void dc_client_sel(int pin_num, int *reg, int *bit) reg 117 drivers/pinctrl/pinctrl-digicolor.c *reg = GP_CLIENTSEL(pin_num/PINS_PER_COLLECTION); reg 121 drivers/pinctrl/pinctrl-digicolor.c *reg += 1; reg 130 drivers/pinctrl/pinctrl-digicolor.c u8 reg; reg 134 drivers/pinctrl/pinctrl-digicolor.c reg = readb_relaxed(pmap->regs + reg_off); reg 135 drivers/pinctrl/pinctrl-digicolor.c reg &= ~(3 << bit_off); reg 136 drivers/pinctrl/pinctrl-digicolor.c reg |= (selector << bit_off); reg 137 drivers/pinctrl/pinctrl-digicolor.c writeb_relaxed(reg, pmap->regs + reg_off); reg 148 drivers/pinctrl/pinctrl-digicolor.c u8 reg; reg 152 drivers/pinctrl/pinctrl-digicolor.c reg = readb_relaxed(pmap->regs + reg_off); reg 153 drivers/pinctrl/pinctrl-digicolor.c if ((reg & (3 << bit_off)) != 0) reg 39 drivers/pinctrl/pinctrl-falcon.c #define pad_r32(p, reg) ltq_r32(p + reg) reg 40 drivers/pinctrl/pinctrl-falcon.c #define pad_w32(p, val, reg) ltq_w32(val, p + reg) reg 41 drivers/pinctrl/pinctrl-falcon.c #define pad_w32_mask(c, clear, set, reg) \ reg 42 drivers/pinctrl/pinctrl-falcon.c pad_w32(c, (pad_r32(c, reg) & ~(clear)) | (set), reg) reg 284 drivers/pinctrl/pinctrl-falcon.c u32 reg; reg 293 drivers/pinctrl/pinctrl-falcon.c reg = LTQ_PADC_DCC; reg 297 drivers/pinctrl/pinctrl-falcon.c reg = LTQ_PADC_SRC; reg 302 drivers/pinctrl/pinctrl-falcon.c reg = LTQ_PADC_PDEN; reg 304 drivers/pinctrl/pinctrl-falcon.c reg = LTQ_PADC_PUEN; reg 313 drivers/pinctrl/pinctrl-falcon.c pad_w32(mem, BIT(PORT_PIN(pin)), reg); reg 314 drivers/pinctrl/pinctrl-falcon.c if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin)))) reg 34 drivers/pinctrl/pinctrl-gemini.c u32 reg; reg 2305 drivers/pinctrl/pinctrl-gemini.c .reg = _r, \ reg 2390 drivers/pinctrl/pinctrl-gemini.c regmap_read(pmx->map, conf->reg, &val); reg 2430 drivers/pinctrl/pinctrl-gemini.c regmap_update_bits(pmx->map, conf->reg, conf->mask, arg); reg 1333 drivers/pinctrl/pinctrl-ingenic.c static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) reg 1337 drivers/pinctrl/pinctrl-ingenic.c regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val); reg 1343 drivers/pinctrl/pinctrl-ingenic.c u8 reg, u8 offset, bool set) reg 1346 drivers/pinctrl/pinctrl-ingenic.c reg = REG_SET(reg); reg 1348 drivers/pinctrl/pinctrl-ingenic.c reg = REG_CLEAR(reg); reg 1350 drivers/pinctrl/pinctrl-ingenic.c regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); reg 1354 drivers/pinctrl/pinctrl-ingenic.c u8 reg, u8 offset, bool set) reg 1357 drivers/pinctrl/pinctrl-ingenic.c reg = REG_SET(reg); reg 1359 drivers/pinctrl/pinctrl-ingenic.c reg = REG_CLEAR(reg); reg 1361 drivers/pinctrl/pinctrl-ingenic.c regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_BASE + reg, BIT(offset)); reg 1604 drivers/pinctrl/pinctrl-ingenic.c unsigned int pin, u8 reg, bool set) reg 1610 drivers/pinctrl/pinctrl-ingenic.c (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); reg 1614 drivers/pinctrl/pinctrl-ingenic.c unsigned int pin, u8 reg, bool set) reg 1619 drivers/pinctrl/pinctrl-ingenic.c (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); reg 1629 drivers/pinctrl/pinctrl-ingenic.c unsigned int pin, u8 reg) reg 1635 drivers/pinctrl/pinctrl-ingenic.c regmap_read(jzpc->map, offt * 0x100 + reg, &val); reg 646 drivers/pinctrl/pinctrl-lpc18xx.c static int lpc18xx_pconf_get_usb1(enum pin_config_param param, int *arg, u32 reg) reg 650 drivers/pinctrl/pinctrl-lpc18xx.c if (reg & LPC18XX_SCU_USB1_EPWR) reg 657 drivers/pinctrl/pinctrl-lpc18xx.c if (reg & LPC18XX_SCU_USB1_EPD) reg 662 drivers/pinctrl/pinctrl-lpc18xx.c if (reg & LPC18XX_SCU_USB1_EPD) reg 675 drivers/pinctrl/pinctrl-lpc18xx.c static int lpc18xx_pconf_get_i2c0(enum pin_config_param param, int *arg, u32 reg, reg 687 drivers/pinctrl/pinctrl-lpc18xx.c if (reg & (LPC18XX_SCU_I2C0_EZI << shift)) reg 694 drivers/pinctrl/pinctrl-lpc18xx.c if (reg & (LPC18XX_SCU_I2C0_EHD << shift)) reg 701 drivers/pinctrl/pinctrl-lpc18xx.c if (reg & (LPC18XX_SCU_I2C0_EFP << shift)) reg 708 drivers/pinctrl/pinctrl-lpc18xx.c if (reg & (LPC18XX_SCU_I2C0_ZIF << shift)) reg 785 drivers/pinctrl/pinctrl-lpc18xx.c int *arg, u32 reg, unsigned pin, reg 790 drivers/pinctrl/pinctrl-lpc18xx.c if ((!(reg & LPC18XX_SCU_PIN_EPD)) && (reg & LPC18XX_SCU_PIN_EPUN)) reg 797 drivers/pinctrl/pinctrl-lpc18xx.c if (reg & LPC18XX_SCU_PIN_EPUN) reg 804 drivers/pinctrl/pinctrl-lpc18xx.c if (reg & LPC18XX_SCU_PIN_EPD) reg 811 drivers/pinctrl/pinctrl-lpc18xx.c if (reg & LPC18XX_SCU_PIN_EZI) reg 821 drivers/pinctrl/pinctrl-lpc18xx.c if (reg & LPC18XX_SCU_PIN_EHS) reg 828 drivers/pinctrl/pinctrl-lpc18xx.c if (reg & LPC18XX_SCU_PIN_ZIF) reg 838 drivers/pinctrl/pinctrl-lpc18xx.c *arg = (reg & LPC18XX_SCU_PIN_EHD_MASK) >> LPC18XX_SCU_PIN_EHD_POS; reg 879 drivers/pinctrl/pinctrl-lpc18xx.c u32 reg; reg 885 drivers/pinctrl/pinctrl-lpc18xx.c reg = readl(scu->base + pin_cap->offset); reg 888 drivers/pinctrl/pinctrl-lpc18xx.c ret = lpc18xx_pconf_get_i2c0(param, &arg, reg, pin); reg 890 drivers/pinctrl/pinctrl-lpc18xx.c ret = lpc18xx_pconf_get_usb1(param, &arg, reg); reg 892 drivers/pinctrl/pinctrl-lpc18xx.c ret = lpc18xx_pconf_get_pin(pctldev, param, &arg, reg, pin, pin_cap); reg 904 drivers/pinctrl/pinctrl-lpc18xx.c u32 param_val, u32 *reg) reg 909 drivers/pinctrl/pinctrl-lpc18xx.c *reg &= ~LPC18XX_SCU_USB1_EPWR; reg 911 drivers/pinctrl/pinctrl-lpc18xx.c *reg |= LPC18XX_SCU_USB1_EPWR; reg 915 drivers/pinctrl/pinctrl-lpc18xx.c *reg &= ~LPC18XX_SCU_USB1_EPD; reg 919 drivers/pinctrl/pinctrl-lpc18xx.c *reg |= LPC18XX_SCU_USB1_EPD; reg 932 drivers/pinctrl/pinctrl-lpc18xx.c u32 param_val, u32 *reg, reg 945 drivers/pinctrl/pinctrl-lpc18xx.c *reg |= (LPC18XX_SCU_I2C0_EZI << shift); reg 947 drivers/pinctrl/pinctrl-lpc18xx.c *reg &= ~(LPC18XX_SCU_I2C0_EZI << shift); reg 952 drivers/pinctrl/pinctrl-lpc18xx.c *reg |= (LPC18XX_SCU_I2C0_EHD << shift); reg 954 drivers/pinctrl/pinctrl-lpc18xx.c *reg &= ~(LPC18XX_SCU_I2C0_EHD << shift); reg 959 drivers/pinctrl/pinctrl-lpc18xx.c *reg |= (LPC18XX_SCU_I2C0_EFP << shift); reg 961 drivers/pinctrl/pinctrl-lpc18xx.c *reg &= ~(LPC18XX_SCU_I2C0_EFP << shift); reg 968 drivers/pinctrl/pinctrl-lpc18xx.c *reg &= ~(LPC18XX_SCU_I2C0_ZIF << shift); reg 970 drivers/pinctrl/pinctrl-lpc18xx.c *reg |= (LPC18XX_SCU_I2C0_ZIF << shift); reg 1008 drivers/pinctrl/pinctrl-lpc18xx.c u32 param_val, u32 *reg, unsigned pin, reg 1013 drivers/pinctrl/pinctrl-lpc18xx.c *reg &= ~LPC18XX_SCU_PIN_EPD; reg 1014 drivers/pinctrl/pinctrl-lpc18xx.c *reg |= LPC18XX_SCU_PIN_EPUN; reg 1018 drivers/pinctrl/pinctrl-lpc18xx.c *reg &= ~LPC18XX_SCU_PIN_EPUN; reg 1022 drivers/pinctrl/pinctrl-lpc18xx.c *reg |= LPC18XX_SCU_PIN_EPD; reg 1027 drivers/pinctrl/pinctrl-lpc18xx.c *reg |= LPC18XX_SCU_PIN_EZI; reg 1029 drivers/pinctrl/pinctrl-lpc18xx.c *reg &= ~LPC18XX_SCU_PIN_EZI; reg 1039 drivers/pinctrl/pinctrl-lpc18xx.c *reg &= ~LPC18XX_SCU_PIN_EHS; reg 1041 drivers/pinctrl/pinctrl-lpc18xx.c *reg |= LPC18XX_SCU_PIN_EHS; reg 1046 drivers/pinctrl/pinctrl-lpc18xx.c *reg &= ~LPC18XX_SCU_PIN_ZIF; reg 1048 drivers/pinctrl/pinctrl-lpc18xx.c *reg |= LPC18XX_SCU_PIN_ZIF; reg 1056 drivers/pinctrl/pinctrl-lpc18xx.c *reg &= ~LPC18XX_SCU_PIN_EHD_MASK; reg 1071 drivers/pinctrl/pinctrl-lpc18xx.c *reg |= param_val << LPC18XX_SCU_PIN_EHD_POS; reg 1092 drivers/pinctrl/pinctrl-lpc18xx.c u32 reg; reg 1100 drivers/pinctrl/pinctrl-lpc18xx.c reg = readl(scu->base + pin_cap->offset); reg 1107 drivers/pinctrl/pinctrl-lpc18xx.c ret = lpc18xx_pconf_set_i2c0(pctldev, param, param_val, ®, pin); reg 1109 drivers/pinctrl/pinctrl-lpc18xx.c ret = lpc18xx_pconf_set_usb1(pctldev, param, param_val, ®); reg 1111 drivers/pinctrl/pinctrl-lpc18xx.c ret = lpc18xx_pconf_set_pin(pctldev, param, param_val, ®, pin, pin_cap); reg 1117 drivers/pinctrl/pinctrl-lpc18xx.c writel(reg, scu->base + pin_cap->offset); reg 1158 drivers/pinctrl/pinctrl-lpc18xx.c u32 reg; reg 1185 drivers/pinctrl/pinctrl-lpc18xx.c reg = readl(scu->base + offset); reg 1186 drivers/pinctrl/pinctrl-lpc18xx.c reg |= pin->analog & LPC18XX_ANALOG_BIT_MASK; reg 1187 drivers/pinctrl/pinctrl-lpc18xx.c writel(reg, scu->base + offset); reg 1195 drivers/pinctrl/pinctrl-lpc18xx.c reg = readl(scu->base + LPC18XX_SCU_REG_ENAIO2); reg 1196 drivers/pinctrl/pinctrl-lpc18xx.c reg |= LPC18XX_SCU_REG_ENAIO2_DAC; reg 1197 drivers/pinctrl/pinctrl-lpc18xx.c writel(reg, scu->base + LPC18XX_SCU_REG_ENAIO2); reg 1210 drivers/pinctrl/pinctrl-lpc18xx.c reg = readl(scu->base + pin->offset); reg 1211 drivers/pinctrl/pinctrl-lpc18xx.c reg &= ~LPC18XX_SCU_PIN_MODE_MASK; reg 1212 drivers/pinctrl/pinctrl-lpc18xx.c writel(reg | func, scu->base + pin->offset); reg 82 drivers/pinctrl/pinctrl-mcp23s08.c {.reg = MCP_IODIR, .def = 0xff}, reg 83 drivers/pinctrl/pinctrl-mcp23s08.c {.reg = MCP_IPOL, .def = 0x00}, reg 84 drivers/pinctrl/pinctrl-mcp23s08.c {.reg = MCP_GPINTEN, .def = 0x00}, reg 85 drivers/pinctrl/pinctrl-mcp23s08.c {.reg = MCP_DEFVAL, .def = 0x00}, reg 86 drivers/pinctrl/pinctrl-mcp23s08.c {.reg = MCP_INTCON, .def = 0x00}, reg 87 drivers/pinctrl/pinctrl-mcp23s08.c {.reg = MCP_IOCON, .def = 0x00}, reg 88 drivers/pinctrl/pinctrl-mcp23s08.c {.reg = MCP_GPPU, .def = 0x00}, reg 89 drivers/pinctrl/pinctrl-mcp23s08.c {.reg = MCP_OLAT, .def = 0x00}, reg 126 drivers/pinctrl/pinctrl-mcp23s08.c {.reg = MCP_IODIR << 1, .def = 0xffff}, reg 127 drivers/pinctrl/pinctrl-mcp23s08.c {.reg = MCP_IPOL << 1, .def = 0x0000}, reg 128 drivers/pinctrl/pinctrl-mcp23s08.c {.reg = MCP_GPINTEN << 1, .def = 0x0000}, reg 129 drivers/pinctrl/pinctrl-mcp23s08.c {.reg = MCP_DEFVAL << 1, .def = 0x0000}, reg 130 drivers/pinctrl/pinctrl-mcp23s08.c {.reg = MCP_INTCON << 1, .def = 0x0000}, reg 131 drivers/pinctrl/pinctrl-mcp23s08.c {.reg = MCP_IOCON << 1, .def = 0x0000}, reg 132 drivers/pinctrl/pinctrl-mcp23s08.c {.reg = MCP_GPPU << 1, .def = 0x0000}, reg 133 drivers/pinctrl/pinctrl-mcp23s08.c {.reg = MCP_OLAT << 1, .def = 0x0000}, reg 170 drivers/pinctrl/pinctrl-mcp23s08.c static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val) reg 172 drivers/pinctrl/pinctrl-mcp23s08.c return regmap_read(mcp->regmap, reg << mcp->reg_shift, val); reg 175 drivers/pinctrl/pinctrl-mcp23s08.c static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val) reg 177 drivers/pinctrl/pinctrl-mcp23s08.c return regmap_write(mcp->regmap, reg << mcp->reg_shift, val); reg 180 drivers/pinctrl/pinctrl-mcp23s08.c static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg, reg 184 drivers/pinctrl/pinctrl-mcp23s08.c return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift, reg 188 drivers/pinctrl/pinctrl-mcp23s08.c static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg, reg 192 drivers/pinctrl/pinctrl-mcp23s08.c return mcp_set_mask(mcp, reg, mask, enabled); reg 330 drivers/pinctrl/pinctrl-mcp23s08.c const void *reg, size_t reg_size, reg 337 drivers/pinctrl/pinctrl-mcp23s08.c { .tx_buf = reg, .len = reg_size, }, reg 348 drivers/pinctrl/pinctrl-mcp23s08.c static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size, reg 359 drivers/pinctrl/pinctrl-mcp23s08.c tx[1] = *((u8 *) reg); reg 714 drivers/pinctrl/pinctrl-ocelot.c unsigned int reg = 0, irq, i; reg 718 drivers/pinctrl/pinctrl-ocelot.c regmap_read(info->map, OCELOT_GPIO_INTR_IDENT + 4 * i, ®); reg 719 drivers/pinctrl/pinctrl-ocelot.c if (!reg) reg 724 drivers/pinctrl/pinctrl-ocelot.c irqs = reg; reg 506 drivers/pinctrl/pinctrl-palmas.c #define PALMAS_PINGROUP(pg_name, pin_id, base, reg, _mask, _bshift, o0, o1, o2, o3) \ reg 512 drivers/pinctrl/pinctrl-palmas.c .mux_reg_add = PALMAS_PRIMARY_SECONDARY_##reg, \ reg 831 drivers/pinctrl/pinctrl-pistachio.c static inline u32 pctl_readl(struct pistachio_pinctrl *pctl, u32 reg) reg 833 drivers/pinctrl/pinctrl-pistachio.c return readl(pctl->base + reg); reg 836 drivers/pinctrl/pinctrl-pistachio.c static inline void pctl_writel(struct pistachio_pinctrl *pctl, u32 val, u32 reg) reg 838 drivers/pinctrl/pinctrl-pistachio.c writel(val, pctl->base + reg); reg 846 drivers/pinctrl/pinctrl-pistachio.c static inline u32 gpio_readl(struct pistachio_gpio_bank *bank, u32 reg) reg 848 drivers/pinctrl/pinctrl-pistachio.c return readl(bank->base + reg); reg 852 drivers/pinctrl/pinctrl-pistachio.c u32 reg) reg 854 drivers/pinctrl/pinctrl-pistachio.c writel(val, bank->base + reg); reg 858 drivers/pinctrl/pinctrl-pistachio.c u32 reg, unsigned int bit, u32 val) reg 864 drivers/pinctrl/pinctrl-pistachio.c gpio_writel(bank, (0x10000 | val) << bit, reg); reg 1175 drivers/pinctrl/pinctrl-pistachio.c u32 reg; reg 1178 drivers/pinctrl/pinctrl-pistachio.c reg = GPIO_OUTPUT; reg 1180 drivers/pinctrl/pinctrl-pistachio.c reg = GPIO_INPUT; reg 1182 drivers/pinctrl/pinctrl-pistachio.c return !!(gpio_readl(bank, reg) & BIT(offset)); reg 58 drivers/pinctrl/pinctrl-rk805.c u8 reg; reg 126 drivers/pinctrl/pinctrl-rk805.c .reg = RK805_OUT_REG, reg 130 drivers/pinctrl/pinctrl-rk805.c .reg = RK805_OUT_REG, reg 141 drivers/pinctrl/pinctrl-rk805.c ret = regmap_read(pci->rk808->regmap, pci->pin_cfg[offset].reg, &val); reg 158 drivers/pinctrl/pinctrl-rk805.c pci->pin_cfg[offset].reg, reg 190 drivers/pinctrl/pinctrl-rk805.c pci->pin_cfg[offset].reg, reg 291 drivers/pinctrl/pinctrl-rk805.c pci->pin_cfg[offset].reg, reg 336 drivers/pinctrl/pinctrl-rk805.c pci->pin_cfg[offset].reg, reg 297 drivers/pinctrl/pinctrl-rockchip.c u32 reg; reg 344 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit); reg 347 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit); reg 350 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit); reg 565 drivers/pinctrl/pinctrl-rockchip.c .reg = 0x418, reg 571 drivers/pinctrl/pinctrl-rockchip.c .reg = 0x418, reg 577 drivers/pinctrl/pinctrl-rockchip.c .reg = 0x418, reg 583 drivers/pinctrl/pinctrl-rockchip.c .reg = 0x418, reg 589 drivers/pinctrl/pinctrl-rockchip.c .reg = 0x418, reg 595 drivers/pinctrl/pinctrl-rockchip.c .reg = 0x418, reg 601 drivers/pinctrl/pinctrl-rockchip.c .reg = 0x418, reg 607 drivers/pinctrl/pinctrl-rockchip.c .reg = 0x418, reg 613 drivers/pinctrl/pinctrl-rockchip.c .reg = 0x41c, reg 619 drivers/pinctrl/pinctrl-rockchip.c .reg = 0x41c, reg 629 drivers/pinctrl/pinctrl-rockchip.c .reg = 0xe8, reg 635 drivers/pinctrl/pinctrl-rockchip.c .reg = 0xe8, reg 641 drivers/pinctrl/pinctrl-rockchip.c .reg = 0xe8, reg 647 drivers/pinctrl/pinctrl-rockchip.c .reg = 0xe8, reg 653 drivers/pinctrl/pinctrl-rockchip.c .reg = 0xd4, reg 663 drivers/pinctrl/pinctrl-rockchip.c .reg = 0x24, reg 669 drivers/pinctrl/pinctrl-rockchip.c .reg = 0x28, reg 675 drivers/pinctrl/pinctrl-rockchip.c .reg = 0x30, reg 682 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit, int *mask) reg 699 drivers/pinctrl/pinctrl-rockchip.c *reg = data->reg; reg 1113 drivers/pinctrl/pinctrl-rockchip.c int mux, u32 *loc, u32 *reg, u32 *value) reg 1131 drivers/pinctrl/pinctrl-rockchip.c *reg = data->route_offset; reg 1143 drivers/pinctrl/pinctrl-rockchip.c int reg, ret, mask, mux_type; reg 1162 drivers/pinctrl/pinctrl-rockchip.c reg = bank->iomux[iomux_num].offset; reg 1165 drivers/pinctrl/pinctrl-rockchip.c reg += 0x4; reg 1170 drivers/pinctrl/pinctrl-rockchip.c reg += 0x4; reg 1179 drivers/pinctrl/pinctrl-rockchip.c rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); reg 1181 drivers/pinctrl/pinctrl-rockchip.c ret = regmap_read(regmap, reg, &val); reg 1231 drivers/pinctrl/pinctrl-rockchip.c int reg, ret, mask, mux_type; reg 1250 drivers/pinctrl/pinctrl-rockchip.c reg = bank->iomux[iomux_num].offset; reg 1253 drivers/pinctrl/pinctrl-rockchip.c reg += 0x4; reg 1258 drivers/pinctrl/pinctrl-rockchip.c reg += 0x4; reg 1267 drivers/pinctrl/pinctrl-rockchip.c rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); reg 1293 drivers/pinctrl/pinctrl-rockchip.c ret = regmap_update_bits(regmap, reg, rmask, data); reg 1306 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit) reg 1313 drivers/pinctrl/pinctrl-rockchip.c *reg = PX30_PULL_PMU_OFFSET; reg 1316 drivers/pinctrl/pinctrl-rockchip.c *reg = PX30_PULL_GRF_OFFSET; reg 1319 drivers/pinctrl/pinctrl-rockchip.c *reg -= 0x10; reg 1320 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; reg 1323 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); reg 1336 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit) reg 1343 drivers/pinctrl/pinctrl-rockchip.c *reg = PX30_DRV_PMU_OFFSET; reg 1346 drivers/pinctrl/pinctrl-rockchip.c *reg = PX30_DRV_GRF_OFFSET; reg 1349 drivers/pinctrl/pinctrl-rockchip.c *reg -= 0x10; reg 1350 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; reg 1353 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); reg 1367 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit) reg 1374 drivers/pinctrl/pinctrl-rockchip.c *reg = PX30_SCHMITT_PMU_OFFSET; reg 1378 drivers/pinctrl/pinctrl-rockchip.c *reg = PX30_SCHMITT_GRF_OFFSET; reg 1380 drivers/pinctrl/pinctrl-rockchip.c *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; reg 1383 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / pins_per_reg) * 4); reg 1397 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit) reg 1404 drivers/pinctrl/pinctrl-rockchip.c *reg = RV1108_PULL_PMU_OFFSET; reg 1406 drivers/pinctrl/pinctrl-rockchip.c *reg = RV1108_PULL_OFFSET; reg 1409 drivers/pinctrl/pinctrl-rockchip.c *reg -= 0x10; reg 1410 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; reg 1413 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); reg 1426 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit) reg 1433 drivers/pinctrl/pinctrl-rockchip.c *reg = RV1108_DRV_PMU_OFFSET; reg 1436 drivers/pinctrl/pinctrl-rockchip.c *reg = RV1108_DRV_GRF_OFFSET; reg 1439 drivers/pinctrl/pinctrl-rockchip.c *reg -= 0x10; reg 1440 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; reg 1443 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); reg 1457 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit) reg 1464 drivers/pinctrl/pinctrl-rockchip.c *reg = RV1108_SCHMITT_PMU_OFFSET; reg 1468 drivers/pinctrl/pinctrl-rockchip.c *reg = RV1108_SCHMITT_GRF_OFFSET; reg 1470 drivers/pinctrl/pinctrl-rockchip.c *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; reg 1472 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / pins_per_reg) * 4); reg 1484 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit) reg 1489 drivers/pinctrl/pinctrl-rockchip.c *reg = RK2928_PULL_OFFSET; reg 1490 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; reg 1491 drivers/pinctrl/pinctrl-rockchip.c *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; reg 1500 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit) reg 1505 drivers/pinctrl/pinctrl-rockchip.c *reg = RK3128_PULL_OFFSET; reg 1506 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; reg 1507 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); reg 1520 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit) reg 1528 drivers/pinctrl/pinctrl-rockchip.c *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; reg 1529 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); reg 1535 drivers/pinctrl/pinctrl-rockchip.c *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; reg 1538 drivers/pinctrl/pinctrl-rockchip.c *reg -= 4; reg 1539 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; reg 1540 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); reg 1555 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit) reg 1562 drivers/pinctrl/pinctrl-rockchip.c *reg = RK3188_PULL_PMU_OFFSET; reg 1564 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); reg 1569 drivers/pinctrl/pinctrl-rockchip.c *reg = RK3288_PULL_OFFSET; reg 1572 drivers/pinctrl/pinctrl-rockchip.c *reg -= 0x10; reg 1573 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; reg 1574 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); reg 1589 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit) reg 1596 drivers/pinctrl/pinctrl-rockchip.c *reg = RK3288_DRV_PMU_OFFSET; reg 1598 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); reg 1603 drivers/pinctrl/pinctrl-rockchip.c *reg = RK3288_DRV_GRF_OFFSET; reg 1606 drivers/pinctrl/pinctrl-rockchip.c *reg -= 0x10; reg 1607 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; reg 1608 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); reg 1619 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit) reg 1624 drivers/pinctrl/pinctrl-rockchip.c *reg = RK3228_PULL_OFFSET; reg 1625 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; reg 1626 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); reg 1636 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit) reg 1641 drivers/pinctrl/pinctrl-rockchip.c *reg = RK3228_DRV_GRF_OFFSET; reg 1642 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; reg 1643 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); reg 1654 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit) reg 1661 drivers/pinctrl/pinctrl-rockchip.c *reg = RK3368_PULL_PMU_OFFSET; reg 1663 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); reg 1668 drivers/pinctrl/pinctrl-rockchip.c *reg = RK3368_PULL_GRF_OFFSET; reg 1671 drivers/pinctrl/pinctrl-rockchip.c *reg -= 0x10; reg 1672 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; reg 1673 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); reg 1685 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit) reg 1692 drivers/pinctrl/pinctrl-rockchip.c *reg = RK3368_DRV_PMU_OFFSET; reg 1694 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); reg 1699 drivers/pinctrl/pinctrl-rockchip.c *reg = RK3368_DRV_GRF_OFFSET; reg 1702 drivers/pinctrl/pinctrl-rockchip.c *reg -= 0x10; reg 1703 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; reg 1704 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); reg 1717 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit) reg 1724 drivers/pinctrl/pinctrl-rockchip.c *reg = RK3399_PULL_PMU_OFFSET; reg 1726 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; reg 1728 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); reg 1733 drivers/pinctrl/pinctrl-rockchip.c *reg = RK3399_PULL_GRF_OFFSET; reg 1736 drivers/pinctrl/pinctrl-rockchip.c *reg -= 0x20; reg 1737 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; reg 1738 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); reg 1747 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit) reg 1758 drivers/pinctrl/pinctrl-rockchip.c *reg = bank->drv[drv_num].offset; reg 1780 drivers/pinctrl/pinctrl-rockchip.c int reg, ret; reg 1785 drivers/pinctrl/pinctrl-rockchip.c ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); reg 1800 drivers/pinctrl/pinctrl-rockchip.c ret = regmap_read(regmap, reg, &data); reg 1804 drivers/pinctrl/pinctrl-rockchip.c ret = regmap_read(regmap, reg + 0x4, &temp); reg 1820 drivers/pinctrl/pinctrl-rockchip.c reg += 4; reg 1841 drivers/pinctrl/pinctrl-rockchip.c ret = regmap_read(regmap, reg, &data); reg 1857 drivers/pinctrl/pinctrl-rockchip.c int reg, ret, i; reg 1865 drivers/pinctrl/pinctrl-rockchip.c ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); reg 1903 drivers/pinctrl/pinctrl-rockchip.c ret = regmap_update_bits(regmap, reg, rmask, data); reg 1909 drivers/pinctrl/pinctrl-rockchip.c reg += 0x4; reg 1910 drivers/pinctrl/pinctrl-rockchip.c ret = regmap_update_bits(regmap, reg, rmask, temp); reg 1915 drivers/pinctrl/pinctrl-rockchip.c reg += 4; reg 1940 drivers/pinctrl/pinctrl-rockchip.c ret = regmap_update_bits(regmap, reg, rmask, data); reg 1965 drivers/pinctrl/pinctrl-rockchip.c int reg, ret, pull_type; reg 1973 drivers/pinctrl/pinctrl-rockchip.c ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); reg 1975 drivers/pinctrl/pinctrl-rockchip.c ret = regmap_read(regmap, reg, &data); reg 2008 drivers/pinctrl/pinctrl-rockchip.c int reg, ret, i, pull_type; reg 2019 drivers/pinctrl/pinctrl-rockchip.c ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); reg 2027 drivers/pinctrl/pinctrl-rockchip.c ret = regmap_write(regmap, reg, data); reg 2056 drivers/pinctrl/pinctrl-rockchip.c ret = regmap_update_bits(regmap, reg, rmask, data); reg 2074 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit) reg 2079 drivers/pinctrl/pinctrl-rockchip.c *reg = RK3328_SCHMITT_GRF_OFFSET; reg 2081 drivers/pinctrl/pinctrl-rockchip.c *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; reg 2082 drivers/pinctrl/pinctrl-rockchip.c *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); reg 2093 drivers/pinctrl/pinctrl-rockchip.c int reg, ret; reg 2097 drivers/pinctrl/pinctrl-rockchip.c ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); reg 2101 drivers/pinctrl/pinctrl-rockchip.c ret = regmap_read(regmap, reg, &data); reg 2115 drivers/pinctrl/pinctrl-rockchip.c int reg, ret; reg 2122 drivers/pinctrl/pinctrl-rockchip.c ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); reg 2130 drivers/pinctrl/pinctrl-rockchip.c return regmap_update_bits(regmap, reg, rmask, data); reg 2693 drivers/pinctrl/pinctrl-rockchip.c void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; reg 2700 drivers/pinctrl/pinctrl-rockchip.c data = readl(reg); reg 2704 drivers/pinctrl/pinctrl-rockchip.c writel(data, reg); reg 2753 drivers/pinctrl/pinctrl-rockchip.c void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; reg 2760 drivers/pinctrl/pinctrl-rockchip.c data = readl(reg); reg 2765 drivers/pinctrl/pinctrl-rockchip.c writel(data, reg); reg 47 drivers/pinctrl/pinctrl-rza1.c #define RZA1_ADDR(mem, reg, port) ((mem) + (reg) + ((port) * 4)) reg 573 drivers/pinctrl/pinctrl-rza1.c static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg, reg 576 drivers/pinctrl/pinctrl-rza1.c void __iomem *mem = RZA1_ADDR(port->base, reg, port->id); reg 588 drivers/pinctrl/pinctrl-rza1.c unsigned int reg, unsigned int bit) reg 590 drivers/pinctrl/pinctrl-rza1.c void __iomem *mem = RZA1_ADDR(port->base, reg, port->id); reg 47 drivers/pinctrl/pinctrl-single.c void __iomem *reg; reg 203 drivers/pinctrl/pinctrl-single.c unsigned (*read)(void __iomem *reg); reg 204 drivers/pinctrl/pinctrl-single.c void (*write)(unsigned val, void __iomem *reg); reg 240 drivers/pinctrl/pinctrl-single.c static unsigned __maybe_unused pcs_readb(void __iomem *reg) reg 242 drivers/pinctrl/pinctrl-single.c return readb(reg); reg 245 drivers/pinctrl/pinctrl-single.c static unsigned __maybe_unused pcs_readw(void __iomem *reg) reg 247 drivers/pinctrl/pinctrl-single.c return readw(reg); reg 250 drivers/pinctrl/pinctrl-single.c static unsigned __maybe_unused pcs_readl(void __iomem *reg) reg 252 drivers/pinctrl/pinctrl-single.c return readl(reg); reg 255 drivers/pinctrl/pinctrl-single.c static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg) reg 257 drivers/pinctrl/pinctrl-single.c writeb(val, reg); reg 260 drivers/pinctrl/pinctrl-single.c static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg) reg 262 drivers/pinctrl/pinctrl-single.c writew(val, reg); reg 265 drivers/pinctrl/pinctrl-single.c static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg) reg 267 drivers/pinctrl/pinctrl-single.c writel(val, reg); reg 362 drivers/pinctrl/pinctrl-single.c val = pcs->read(vals->reg); reg 371 drivers/pinctrl/pinctrl-single.c pcs->write(val, vals->reg); reg 1022 drivers/pinctrl/pinctrl-single.c vals[found].reg = pcs->base + offset; reg 1166 drivers/pinctrl/pinctrl-single.c vals[found].reg = pcs->base + offset; reg 1353 drivers/pinctrl/pinctrl-single.c void __iomem *reg; reg 1383 drivers/pinctrl/pinctrl-single.c mask = pcs->read(pcswi->reg); reg 1388 drivers/pinctrl/pinctrl-single.c pcs->write(mask, pcswi->reg); reg 1391 drivers/pinctrl/pinctrl-single.c mask = pcs->read(pcswi->reg); reg 1460 drivers/pinctrl/pinctrl-single.c mask = pcs->read(pcswi->reg); reg 1519 drivers/pinctrl/pinctrl-single.c pcswi->reg = pcs->base + hwirq; reg 64 drivers/pinctrl/pinctrl-st.c #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7) reg 65 drivers/pinctrl/pinctrl-st.c #define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23) reg 66 drivers/pinctrl/pinctrl-st.c #define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31) reg 67 drivers/pinctrl/pinctrl-st.c #define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7) reg 68 drivers/pinctrl/pinctrl-st.c #define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15) reg 69 drivers/pinctrl/pinctrl-st.c #define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23) reg 70 drivers/pinctrl/pinctrl-st.c #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31) reg 1053 drivers/pinctrl/pinctrl-st.c int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4; reg 1056 drivers/pinctrl/pinctrl-st.c struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg); reg 1057 drivers/pinctrl/pinctrl-st.c struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg); reg 1058 drivers/pinctrl/pinctrl-st.c struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg); reg 1060 drivers/pinctrl/pinctrl-st.c struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4); reg 1061 drivers/pinctrl/pinctrl-st.c struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4); reg 1062 drivers/pinctrl/pinctrl-st.c struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4); reg 1063 drivers/pinctrl/pinctrl-st.c struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4); reg 1096 drivers/pinctrl/pinctrl-st.c struct reg_field reg = REG_FIELD(reg_offset, 0, 31); reg 1097 drivers/pinctrl/pinctrl-st.c rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg); reg 1123 drivers/pinctrl/pinctrl-st.c struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb); reg 1128 drivers/pinctrl/pinctrl-st.c return devm_regmap_field_alloc(dev, regmap, reg); reg 106 drivers/pinctrl/pinctrl-stmfx.c u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset); reg 111 drivers/pinctrl/pinctrl-stmfx.c ret = regmap_read(pctl->stmfx->map, reg, &value); reg 119 drivers/pinctrl/pinctrl-stmfx.c u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR; reg 122 drivers/pinctrl/pinctrl-stmfx.c regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset), reg 129 drivers/pinctrl/pinctrl-stmfx.c u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); reg 134 drivers/pinctrl/pinctrl-stmfx.c ret = regmap_read(pctl->stmfx->map, reg, &val); reg 146 drivers/pinctrl/pinctrl-stmfx.c u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); reg 149 drivers/pinctrl/pinctrl-stmfx.c return regmap_write_bits(pctl->stmfx->map, reg, mask, 0); reg 156 drivers/pinctrl/pinctrl-stmfx.c u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset); reg 161 drivers/pinctrl/pinctrl-stmfx.c return regmap_write_bits(pctl->stmfx->map, reg, mask, mask); reg 167 drivers/pinctrl/pinctrl-stmfx.c u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset); reg 171 drivers/pinctrl/pinctrl-stmfx.c ret = regmap_read(pctl->stmfx->map, reg, &pupd); reg 181 drivers/pinctrl/pinctrl-stmfx.c u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset); reg 184 drivers/pinctrl/pinctrl-stmfx.c return regmap_write_bits(pctl->stmfx->map, reg, mask, pupd ? mask : 0); reg 190 drivers/pinctrl/pinctrl-stmfx.c u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset); reg 194 drivers/pinctrl/pinctrl-stmfx.c ret = regmap_read(pctl->stmfx->map, reg, &type); reg 204 drivers/pinctrl/pinctrl-stmfx.c u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset); reg 207 drivers/pinctrl/pinctrl-stmfx.c return regmap_write_bits(pctl->stmfx->map, reg, mask, type ? mask : 0); reg 417 drivers/pinctrl/pinctrl-stmfx.c u32 reg = get_reg(data->hwirq); reg 420 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_src[reg] &= ~mask; reg 427 drivers/pinctrl/pinctrl-stmfx.c u32 reg = get_reg(data->hwirq); reg 430 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_src[reg] |= mask; reg 437 drivers/pinctrl/pinctrl-stmfx.c u32 reg = get_reg(data->hwirq); reg 444 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_evt[reg] |= mask; reg 447 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_evt[reg] &= ~mask; reg 452 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_type[reg] |= mask; reg 454 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_type[reg] &= ~mask; reg 464 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_toggle_edge[reg] |= mask; reg 466 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_toggle_edge[reg] &= mask; reg 483 drivers/pinctrl/pinctrl-stmfx.c u32 reg = get_reg(data->hwirq); reg 491 drivers/pinctrl/pinctrl-stmfx.c if (pctl->irq_toggle_edge[reg] & mask) { reg 493 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_type[reg] &= ~mask; reg 495 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_type[reg] |= mask; reg 511 drivers/pinctrl/pinctrl-stmfx.c u32 reg = get_reg(offset); reg 515 drivers/pinctrl/pinctrl-stmfx.c if (!(pctl->irq_toggle_edge[reg] & mask)) reg 523 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_type[reg] &= mask; reg 525 drivers/pinctrl/pinctrl-stmfx.c STMFX_REG_IRQ_GPI_TYPE + reg, reg 529 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_type[reg] |= mask; reg 531 drivers/pinctrl/pinctrl-stmfx.c STMFX_REG_IRQ_GPI_TYPE + reg, reg 862 drivers/pinctrl/pinctrl-sx150x.c u8 reg, value; reg 866 drivers/pinctrl/pinctrl-sx150x.c reg = pctl->data->pri.x789.reg_misc; reg 870 drivers/pinctrl/pinctrl-sx150x.c reg = pctl->data->pri.x456.reg_advanced; reg 877 drivers/pinctrl/pinctrl-sx150x.c if (!reg) reg 881 drivers/pinctrl/pinctrl-sx150x.c reg = pctl->data->pri.x123.reg_advanced; reg 889 drivers/pinctrl/pinctrl-sx150x.c return regmap_write(pctl->regmap, reg, value); reg 894 drivers/pinctrl/pinctrl-sx150x.c const u8 reg[] = { reg 913 drivers/pinctrl/pinctrl-sx150x.c return regmap_write(pctl->regmap, reg[pctl->data->model], 0); reg 917 drivers/pinctrl/pinctrl-sx150x.c unsigned int reg) reg 921 drivers/pinctrl/pinctrl-sx150x.c if (reg == data->reg_sense) { reg 929 drivers/pinctrl/pinctrl-sx150x.c (reg == data->pri.x789.reg_misc || reg 930 drivers/pinctrl/pinctrl-sx150x.c reg == data->pri.x789.reg_clock || reg 931 drivers/pinctrl/pinctrl-sx150x.c reg == data->pri.x789.reg_reset)) reg 934 drivers/pinctrl/pinctrl-sx150x.c reg == data->pri.x123.reg_advanced) reg 938 drivers/pinctrl/pinctrl-sx150x.c reg == data->pri.x456.reg_advanced)) { reg 946 drivers/pinctrl/pinctrl-sx150x.c unsigned int reg, unsigned int val) reg 970 drivers/pinctrl/pinctrl-sx150x.c if (reg == data->reg_sense && reg 997 drivers/pinctrl/pinctrl-sx150x.c static int sx150x_regmap_reg_read(void *context, unsigned int reg, reg 1003 drivers/pinctrl/pinctrl-sx150x.c const int width = sx150x_regmap_reg_width(pctl, reg); reg 1035 drivers/pinctrl/pinctrl-sx150x.c for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) { reg 1045 drivers/pinctrl/pinctrl-sx150x.c *result = sx150x_maybe_swizzle(pctl, reg, val); reg 1050 drivers/pinctrl/pinctrl-sx150x.c static int sx150x_regmap_reg_write(void *context, unsigned int reg, reg 1056 drivers/pinctrl/pinctrl-sx150x.c const int width = sx150x_regmap_reg_width(pctl, reg); reg 1058 drivers/pinctrl/pinctrl-sx150x.c val = sx150x_maybe_swizzle(pctl, reg, val); reg 1064 drivers/pinctrl/pinctrl-sx150x.c ret = i2c_smbus_write_byte_data(i2c, reg, byte); reg 1068 drivers/pinctrl/pinctrl-sx150x.c reg++; reg 1075 drivers/pinctrl/pinctrl-sx150x.c static bool sx150x_reg_volatile(struct device *dev, unsigned int reg) reg 1079 drivers/pinctrl/pinctrl-sx150x.c return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data; reg 1340 drivers/pinctrl/pinctrl-xway.c u32 reg; reg 1345 drivers/pinctrl/pinctrl-xway.c reg = GPIO3_OD; reg 1347 drivers/pinctrl/pinctrl-xway.c reg = GPIO_OD(pin); reg 1349 drivers/pinctrl/pinctrl-xway.c !gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); reg 1354 drivers/pinctrl/pinctrl-xway.c reg = GPIO3_PUDEN; reg 1356 drivers/pinctrl/pinctrl-xway.c reg = GPIO_PUDEN(pin); reg 1357 drivers/pinctrl/pinctrl-xway.c if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) { reg 1363 drivers/pinctrl/pinctrl-xway.c reg = GPIO3_PUDSEL; reg 1365 drivers/pinctrl/pinctrl-xway.c reg = GPIO_PUDSEL(pin); reg 1366 drivers/pinctrl/pinctrl-xway.c if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) reg 1373 drivers/pinctrl/pinctrl-xway.c reg = GPIO_DIR(pin); reg 1375 drivers/pinctrl/pinctrl-xway.c gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); reg 1393 drivers/pinctrl/pinctrl-xway.c u32 reg; reg 1403 drivers/pinctrl/pinctrl-xway.c reg = GPIO3_OD; reg 1405 drivers/pinctrl/pinctrl-xway.c reg = GPIO_OD(pin); reg 1408 drivers/pinctrl/pinctrl-xway.c reg, reg 1412 drivers/pinctrl/pinctrl-xway.c reg, reg 1418 drivers/pinctrl/pinctrl-xway.c reg = GPIO3_PUDEN; reg 1420 drivers/pinctrl/pinctrl-xway.c reg = GPIO_PUDEN(pin); reg 1423 drivers/pinctrl/pinctrl-xway.c reg, reg 1427 drivers/pinctrl/pinctrl-xway.c gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); reg 1430 drivers/pinctrl/pinctrl-xway.c reg = GPIO3_PUDSEL; reg 1432 drivers/pinctrl/pinctrl-xway.c reg = GPIO_PUDSEL(pin); reg 1435 drivers/pinctrl/pinctrl-xway.c reg, reg 1439 drivers/pinctrl/pinctrl-xway.c reg, reg 1447 drivers/pinctrl/pinctrl-xway.c reg = GPIO_DIR(pin); reg 1450 drivers/pinctrl/pinctrl-xway.c reg, reg 1454 drivers/pinctrl/pinctrl-xway.c reg, reg 904 drivers/pinctrl/pinctrl-zynq.c u32 reg; reg 907 drivers/pinctrl/pinctrl-zynq.c pctrl->pctrl_offset + func->mux, ®); reg 911 drivers/pinctrl/pinctrl-zynq.c reg &= ~func->mux_mask; reg 912 drivers/pinctrl/pinctrl-zynq.c reg |= pgrp->pins[0] << func->mux_shift; reg 914 drivers/pinctrl/pinctrl-zynq.c pctrl->pctrl_offset + func->mux, reg); reg 920 drivers/pinctrl/pinctrl-zynq.c u32 reg, addr = pctrl->pctrl_offset + (4 * pin); reg 922 drivers/pinctrl/pinctrl-zynq.c ret = regmap_read(pctrl->syscon, addr, ®); reg 926 drivers/pinctrl/pinctrl-zynq.c reg &= ~ZYNQ_PINMUX_MUX_MASK; reg 927 drivers/pinctrl/pinctrl-zynq.c reg |= func->mux_val << ZYNQ_PINMUX_MUX_SHIFT; reg 928 drivers/pinctrl/pinctrl-zynq.c ret = regmap_write(pctrl->syscon, addr, reg); reg 979 drivers/pinctrl/pinctrl-zynq.c static unsigned int zynq_pinconf_iostd_get(u32 reg) reg 981 drivers/pinctrl/pinctrl-zynq.c return (reg & ZYNQ_PINCONF_IOTYPE_MASK) >> ZYNQ_PINCONF_IOTYPE_SHIFT; reg 988 drivers/pinctrl/pinctrl-zynq.c u32 reg; reg 997 drivers/pinctrl/pinctrl-zynq.c ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), ®); reg 1003 drivers/pinctrl/pinctrl-zynq.c if (!(reg & ZYNQ_PINCONF_PULLUP)) reg 1008 drivers/pinctrl/pinctrl-zynq.c if (!(reg & ZYNQ_PINCONF_TRISTATE)) reg 1013 drivers/pinctrl/pinctrl-zynq.c if (reg & ZYNQ_PINCONF_PULLUP || reg & ZYNQ_PINCONF_TRISTATE) reg 1017 drivers/pinctrl/pinctrl-zynq.c arg = !!(reg & ZYNQ_PINCONF_SPEED); reg 1021 drivers/pinctrl/pinctrl-zynq.c enum zynq_io_standards iostd = zynq_pinconf_iostd_get(reg); reg 1025 drivers/pinctrl/pinctrl-zynq.c if (!(reg & ZYNQ_PINCONF_DISABLE_RECVR)) reg 1027 drivers/pinctrl/pinctrl-zynq.c arg = !!(reg & ZYNQ_PINCONF_DISABLE_RECVR); reg 1031 drivers/pinctrl/pinctrl-zynq.c arg = zynq_pinconf_iostd_get(reg); reg 1047 drivers/pinctrl/pinctrl-zynq.c u32 reg; reg 1055 drivers/pinctrl/pinctrl-zynq.c ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), ®); reg 1071 drivers/pinctrl/pinctrl-zynq.c reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE); reg 1075 drivers/pinctrl/pinctrl-zynq.c reg |= ZYNQ_PINCONF_SPEED; reg 1077 drivers/pinctrl/pinctrl-zynq.c reg &= ~ZYNQ_PINCONF_SPEED; reg 1087 drivers/pinctrl/pinctrl-zynq.c reg &= ~ZYNQ_PINCONF_IOTYPE_MASK; reg 1088 drivers/pinctrl/pinctrl-zynq.c reg |= arg << ZYNQ_PINCONF_IOTYPE_SHIFT; reg 1092 drivers/pinctrl/pinctrl-zynq.c reg |= ZYNQ_PINCONF_DISABLE_RECVR; reg 1094 drivers/pinctrl/pinctrl-zynq.c reg &= ~ZYNQ_PINCONF_DISABLE_RECVR; reg 1106 drivers/pinctrl/pinctrl-zynq.c reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE); reg 1107 drivers/pinctrl/pinctrl-zynq.c reg |= tristate | pullup; reg 1110 drivers/pinctrl/pinctrl-zynq.c ret = regmap_write(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), reg); reg 978 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c u32 reg; reg 980 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c ret = of_property_read_u32(dev->of_node, "reg", ®); reg 1028 drivers/pinctrl/qcom/pinctrl-spmi-gpio.c pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE; reg 807 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c u32 reg; reg 809 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c ret = of_property_read_u32(dev->of_node, "reg", ®); reg 868 drivers/pinctrl/qcom/pinctrl-spmi-mpp.c pad->base = reg + i * PMIC_MPP_ADDRESS_RANGE; reg 74 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c unsigned reg; reg 136 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c ret = regmap_write(pctrl->regmap, pin->reg, val); reg 142 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c ret = regmap_read(pctrl->regmap, pin->reg, &val); reg 161 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c ret = regmap_write(pctrl->regmap, pin->reg, val); reg 802 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c pin_data[i].reg = SSBI_REG_ADDR_GPIO(i); reg 105 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c unsigned reg; reg 233 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c ret = regmap_write(pctrl->regmap, pin->reg, val); reg 658 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c ret = regmap_read(pctrl->regmap, pin->reg, &val); reg 792 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c pin_data[i].reg = SSBI_REG_ADDR_MPP(i); reg 51 drivers/pinctrl/samsung/pinctrl-exynos.h #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ reg 54 drivers/pinctrl/samsung/pinctrl-exynos.h .pctl_offset = reg, \ reg 60 drivers/pinctrl/samsung/pinctrl-exynos.h #define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \ reg 63 drivers/pinctrl/samsung/pinctrl-exynos.h .pctl_offset = reg, \ reg 70 drivers/pinctrl/samsung/pinctrl-exynos.h #define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \ reg 73 drivers/pinctrl/samsung/pinctrl-exynos.h .pctl_offset = reg, \ reg 80 drivers/pinctrl/samsung/pinctrl-exynos.h #define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \ reg 83 drivers/pinctrl/samsung/pinctrl-exynos.h .pctl_offset = reg, \ reg 90 drivers/pinctrl/samsung/pinctrl-exynos.h #define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \ reg 93 drivers/pinctrl/samsung/pinctrl-exynos.h .pctl_offset = reg, \ reg 100 drivers/pinctrl/samsung/pinctrl-exynos.h #define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \ reg 103 drivers/pinctrl/samsung/pinctrl-exynos.h .pctl_offset = reg, \ reg 52 drivers/pinctrl/samsung/pinctrl-s3c24xx.c #define PIN_BANK_A(pins, reg, id) \ reg 55 drivers/pinctrl/samsung/pinctrl-s3c24xx.c .pctl_offset = reg, \ reg 61 drivers/pinctrl/samsung/pinctrl-s3c24xx.c #define PIN_BANK_2BIT(pins, reg, id) \ reg 64 drivers/pinctrl/samsung/pinctrl-s3c24xx.c .pctl_offset = reg, \ reg 70 drivers/pinctrl/samsung/pinctrl-s3c24xx.c #define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs, emask)\ reg 73 drivers/pinctrl/samsung/pinctrl-s3c24xx.c .pctl_offset = reg, \ reg 143 drivers/pinctrl/samsung/pinctrl-s3c24xx.c void __iomem *reg; reg 149 drivers/pinctrl/samsung/pinctrl-s3c24xx.c reg = d->virt_base + bank->pctl_offset; reg 155 drivers/pinctrl/samsung/pinctrl-s3c24xx.c val = readl(reg); reg 158 drivers/pinctrl/samsung/pinctrl-s3c24xx.c writel(val, reg); reg 168 drivers/pinctrl/samsung/pinctrl-s3c24xx.c void __iomem *reg; reg 182 drivers/pinctrl/samsung/pinctrl-s3c24xx.c reg = d->virt_base + EINT_REG(index); reg 185 drivers/pinctrl/samsung/pinctrl-s3c24xx.c val = readl(reg); reg 188 drivers/pinctrl/samsung/pinctrl-s3c24xx.c writel(val, reg); reg 96 drivers/pinctrl/samsung/pinctrl-s3c64xx.c #define PIN_BANK_4BIT(pins, reg, id) \ reg 99 drivers/pinctrl/samsung/pinctrl-s3c64xx.c .pctl_offset = reg, \ reg 105 drivers/pinctrl/samsung/pinctrl-s3c64xx.c #define PIN_BANK_4BIT_EINTG(pins, reg, id, eoffs) \ reg 108 drivers/pinctrl/samsung/pinctrl-s3c64xx.c .pctl_offset = reg, \ reg 117 drivers/pinctrl/samsung/pinctrl-s3c64xx.c #define PIN_BANK_4BIT_EINTW(pins, reg, id, eoffs, emask) \ reg 120 drivers/pinctrl/samsung/pinctrl-s3c64xx.c .pctl_offset = reg, \ reg 129 drivers/pinctrl/samsung/pinctrl-s3c64xx.c #define PIN_BANK_4BIT2_EINTG(pins, reg, id, eoffs) \ reg 132 drivers/pinctrl/samsung/pinctrl-s3c64xx.c .pctl_offset = reg, \ reg 141 drivers/pinctrl/samsung/pinctrl-s3c64xx.c #define PIN_BANK_4BIT2_EINTW(pins, reg, id, eoffs, emask) \ reg 144 drivers/pinctrl/samsung/pinctrl-s3c64xx.c .pctl_offset = reg, \ reg 153 drivers/pinctrl/samsung/pinctrl-s3c64xx.c #define PIN_BANK_4BIT2_ALIVE(pins, reg, id) \ reg 156 drivers/pinctrl/samsung/pinctrl-s3c64xx.c .pctl_offset = reg, \ reg 162 drivers/pinctrl/samsung/pinctrl-s3c64xx.c #define PIN_BANK_2BIT(pins, reg, id) \ reg 165 drivers/pinctrl/samsung/pinctrl-s3c64xx.c .pctl_offset = reg, \ reg 171 drivers/pinctrl/samsung/pinctrl-s3c64xx.c #define PIN_BANK_2BIT_EINTG(pins, reg, id, eoffs, emask) \ reg 174 drivers/pinctrl/samsung/pinctrl-s3c64xx.c .pctl_offset = reg, \ reg 183 drivers/pinctrl/samsung/pinctrl-s3c64xx.c #define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs) \ reg 186 drivers/pinctrl/samsung/pinctrl-s3c64xx.c .pctl_offset = reg, \ reg 272 drivers/pinctrl/samsung/pinctrl-s3c64xx.c void __iomem *reg; reg 278 drivers/pinctrl/samsung/pinctrl-s3c64xx.c reg = d->virt_base + bank->pctl_offset; reg 282 drivers/pinctrl/samsung/pinctrl-s3c64xx.c reg += 4; reg 291 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val = readl(reg); reg 294 drivers/pinctrl/samsung/pinctrl-s3c64xx.c writel(val, reg); reg 308 drivers/pinctrl/samsung/pinctrl-s3c64xx.c void __iomem *reg = d->virt_base + EINTMASK_REG(bank->eint_offset); reg 311 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val = readl(reg); reg 316 drivers/pinctrl/samsung/pinctrl-s3c64xx.c writel(val, reg); reg 334 drivers/pinctrl/samsung/pinctrl-s3c64xx.c void __iomem *reg = d->virt_base + EINTPEND_REG(bank->eint_offset); reg 336 drivers/pinctrl/samsung/pinctrl-s3c64xx.c writel(1 << index, reg); reg 343 drivers/pinctrl/samsung/pinctrl-s3c64xx.c void __iomem *reg; reg 357 drivers/pinctrl/samsung/pinctrl-s3c64xx.c reg = d->virt_base + EINTCON_REG(bank->eint_offset); reg 361 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val = readl(reg); reg 364 drivers/pinctrl/samsung/pinctrl-s3c64xx.c writel(val, reg); reg 551 drivers/pinctrl/samsung/pinctrl-s3c64xx.c void __iomem *reg; reg 565 drivers/pinctrl/samsung/pinctrl-s3c64xx.c reg = d->virt_base + EINT0CON0_REG; reg 568 drivers/pinctrl/samsung/pinctrl-s3c64xx.c reg += 4; reg 573 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val = readl(reg); reg 576 drivers/pinctrl/samsung/pinctrl-s3c64xx.c writel(val, reg); reg 358 drivers/pinctrl/samsung/pinctrl-samsung.c unsigned pin, void __iomem **reg, u32 *offset, reg 369 drivers/pinctrl/samsung/pinctrl-samsung.c *reg = b->pctl_base + b->pctl_offset; reg 382 drivers/pinctrl/samsung/pinctrl-samsung.c void __iomem *reg; reg 393 drivers/pinctrl/samsung/pinctrl-samsung.c ®, &pin_offset, &bank); reg 400 drivers/pinctrl/samsung/pinctrl-samsung.c reg += 4; reg 405 drivers/pinctrl/samsung/pinctrl-samsung.c data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]); reg 408 drivers/pinctrl/samsung/pinctrl-samsung.c writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]); reg 546 drivers/pinctrl/samsung/pinctrl-samsung.c void __iomem *reg; reg 549 drivers/pinctrl/samsung/pinctrl-samsung.c reg = bank->pctl_base + bank->pctl_offset; reg 551 drivers/pinctrl/samsung/pinctrl-samsung.c data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); reg 555 drivers/pinctrl/samsung/pinctrl-samsung.c writel(data, reg + type->reg_offset[PINCFG_TYPE_DAT]); reg 572 drivers/pinctrl/samsung/pinctrl-samsung.c void __iomem *reg; reg 577 drivers/pinctrl/samsung/pinctrl-samsung.c reg = bank->pctl_base + bank->pctl_offset; reg 579 drivers/pinctrl/samsung/pinctrl-samsung.c data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); reg 596 drivers/pinctrl/samsung/pinctrl-samsung.c void __iomem *reg; reg 602 drivers/pinctrl/samsung/pinctrl-samsung.c reg = bank->pctl_base + bank->pctl_offset reg 610 drivers/pinctrl/samsung/pinctrl-samsung.c reg += 4; reg 613 drivers/pinctrl/samsung/pinctrl-samsung.c data = readl(reg); reg 617 drivers/pinctrl/samsung/pinctrl-samsung.c writel(data, reg); reg 1155 drivers/pinctrl/samsung/pinctrl-samsung.c void __iomem *reg = bank->pctl_base + bank->pctl_offset; reg 1166 drivers/pinctrl/samsung/pinctrl-samsung.c bank->pm_save[type] = readl(reg + offs[type]); reg 1171 drivers/pinctrl/samsung/pinctrl-samsung.c readl(reg + offs[PINCFG_TYPE_FUNC] + 4); reg 1173 drivers/pinctrl/samsung/pinctrl-samsung.c bank->name, reg, reg 1178 drivers/pinctrl/samsung/pinctrl-samsung.c reg, bank->pm_save[PINCFG_TYPE_FUNC]); reg 1208 drivers/pinctrl/samsung/pinctrl-samsung.c void __iomem *reg = bank->pctl_base + bank->pctl_offset; reg 1220 drivers/pinctrl/samsung/pinctrl-samsung.c bank->name, reg, reg 1221 drivers/pinctrl/samsung/pinctrl-samsung.c readl(reg + offs[PINCFG_TYPE_FUNC]), reg 1222 drivers/pinctrl/samsung/pinctrl-samsung.c readl(reg + offs[PINCFG_TYPE_FUNC] + 4), reg 1226 drivers/pinctrl/samsung/pinctrl-samsung.c reg + offs[PINCFG_TYPE_FUNC] + 4); reg 1229 drivers/pinctrl/samsung/pinctrl-samsung.c reg, readl(reg + offs[PINCFG_TYPE_FUNC]), reg 1234 drivers/pinctrl/samsung/pinctrl-samsung.c writel(bank->pm_save[type], reg + offs[type]); reg 87 drivers/pinctrl/sh-pfc/core.c static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg) reg 90 drivers/pinctrl/sh-pfc/core.c phys_addr_t address = reg; reg 172 drivers/pinctrl/sh-pfc/core.c u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg) reg 174 drivers/pinctrl/sh-pfc/core.c return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32); reg 177 drivers/pinctrl/sh-pfc/core.c void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data) reg 184 drivers/pinctrl/sh-pfc/core.c sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data); reg 195 drivers/pinctrl/sh-pfc/core.c *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg); reg 220 drivers/pinctrl/sh-pfc/core.c crp->reg, value, field, crp->reg_width, hweight32(mask)); reg 625 drivers/pinctrl/sh-pfc/core.c static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) reg 629 drivers/pinctrl/sh-pfc/core.c static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) reg 631 drivers/pinctrl/sh-pfc/core.c pfc->saved_regs[idx] = sh_pfc_read(pfc, reg); reg 634 drivers/pinctrl/sh-pfc/core.c static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) reg 636 drivers/pinctrl/sh-pfc/core.c sh_pfc_write(pfc, reg, pfc->saved_regs[idx]); reg 640 drivers/pinctrl/sh-pfc/core.c void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx)) reg 645 drivers/pinctrl/sh-pfc/core.c for (i = 0; pfc->info->cfg_regs[i].reg; i++) reg 646 drivers/pinctrl/sh-pfc/core.c do_reg(pfc, pfc->info->cfg_regs[i].reg, n++); reg 649 drivers/pinctrl/sh-pfc/core.c for (i = 0; pfc->info->drive_regs[i].reg; i++) reg 650 drivers/pinctrl/sh-pfc/core.c do_reg(pfc, pfc->info->drive_regs[i].reg, n++); reg 660 drivers/pinctrl/sh-pfc/core.c for (i = 0; pfc->info->ioctrl_regs[i].reg; i++) reg 661 drivers/pinctrl/sh-pfc/core.c do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++); reg 743 drivers/pinctrl/sh-pfc/core.c drvname, cfg_reg->reg, rw, rw + fw - 1); reg 752 drivers/pinctrl/sh-pfc/core.c drvname, cfg_reg->reg, rw, cfg_reg->reg_width); reg 758 drivers/pinctrl/sh-pfc/core.c drvname, cfg_reg->reg, cfg_reg->nr_enum_ids, n); reg 851 drivers/pinctrl/sh-pfc/core.c for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++) reg 26 drivers/pinctrl/sh-pfc/core.h u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg); reg 27 drivers/pinctrl/sh-pfc/core.h void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data); reg 45 drivers/pinctrl/sh-pfc/gpio.c struct sh_pfc_gpio_data_reg **reg, reg 51 drivers/pinctrl/sh-pfc/gpio.c *reg = &chip->regs[gpio_pin->dreg]; reg 58 drivers/pinctrl/sh-pfc/gpio.c phys_addr_t address = dreg->reg; reg 67 drivers/pinctrl/sh-pfc/gpio.c phys_addr_t address = dreg->reg; reg 150 drivers/pinctrl/sh-pfc/gpio.c struct sh_pfc_gpio_data_reg *reg; reg 154 drivers/pinctrl/sh-pfc/gpio.c gpio_get_data_reg(chip, offset, ®, &bit); reg 156 drivers/pinctrl/sh-pfc/gpio.c pos = reg->info->reg_width - (bit + 1); reg 159 drivers/pinctrl/sh-pfc/gpio.c reg->shadow |= BIT(pos); reg 161 drivers/pinctrl/sh-pfc/gpio.c reg->shadow &= ~BIT(pos); reg 163 drivers/pinctrl/sh-pfc/gpio.c gpio_write_data_reg(chip, reg->info, reg->shadow); reg 182 drivers/pinctrl/sh-pfc/gpio.c struct sh_pfc_gpio_data_reg *reg; reg 186 drivers/pinctrl/sh-pfc/gpio.c gpio_get_data_reg(chip, offset, ®, &bit); reg 188 drivers/pinctrl/sh-pfc/gpio.c pos = reg->info->reg_width - (bit + 1); reg 190 drivers/pinctrl/sh-pfc/gpio.c return (gpio_read_data_reg(chip, reg->info) >> pos) & 1; reg 339 drivers/pinctrl/sh-pfc/gpio.c address = pfc->info->data_regs[0].reg; reg 3122 drivers/pinctrl/sh-pfc/pfc-r8a7778.c const struct pinmux_bias_reg *reg; reg 3126 drivers/pinctrl/sh-pfc/pfc-r8a7778.c reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); reg 3127 drivers/pinctrl/sh-pfc/pfc-r8a7778.c if (!reg) reg 3130 drivers/pinctrl/sh-pfc/pfc-r8a7778.c addr = pfc->windows->virt + reg->puen; reg 3141 drivers/pinctrl/sh-pfc/pfc-r8a7778.c const struct pinmux_bias_reg *reg; reg 3146 drivers/pinctrl/sh-pfc/pfc-r8a7778.c reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); reg 3147 drivers/pinctrl/sh-pfc/pfc-r8a7778.c if (!reg) reg 3150 drivers/pinctrl/sh-pfc/pfc-r8a7778.c addr = pfc->windows->virt + reg->puen; reg 5570 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; reg 5826 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c const struct pinmux_bias_reg *reg; reg 5829 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); reg 5830 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c if (!reg) reg 5833 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) reg 5835 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) reg 5844 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c const struct pinmux_bias_reg *reg; reg 5848 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); reg 5849 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c if (!reg) reg 5852 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); reg 5856 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); reg 5860 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c sh_pfc_write(pfc, reg->pud, updown); reg 5861 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c sh_pfc_write(pfc, reg->puen, enable); reg 5922 drivers/pinctrl/sh-pfc/pfc-r8a7795.c *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; reg 6178 drivers/pinctrl/sh-pfc/pfc-r8a7795.c const struct pinmux_bias_reg *reg; reg 6181 drivers/pinctrl/sh-pfc/pfc-r8a7795.c reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); reg 6182 drivers/pinctrl/sh-pfc/pfc-r8a7795.c if (!reg) reg 6185 drivers/pinctrl/sh-pfc/pfc-r8a7795.c if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) reg 6187 drivers/pinctrl/sh-pfc/pfc-r8a7795.c else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) reg 6196 drivers/pinctrl/sh-pfc/pfc-r8a7795.c const struct pinmux_bias_reg *reg; reg 6200 drivers/pinctrl/sh-pfc/pfc-r8a7795.c reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); reg 6201 drivers/pinctrl/sh-pfc/pfc-r8a7795.c if (!reg) reg 6204 drivers/pinctrl/sh-pfc/pfc-r8a7795.c enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); reg 6208 drivers/pinctrl/sh-pfc/pfc-r8a7795.c updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); reg 6212 drivers/pinctrl/sh-pfc/pfc-r8a7795.c sh_pfc_write(pfc, reg->pud, updown); reg 6213 drivers/pinctrl/sh-pfc/pfc-r8a7795.c sh_pfc_write(pfc, reg->puen, enable); reg 5888 drivers/pinctrl/sh-pfc/pfc-r8a7796.c *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; reg 6144 drivers/pinctrl/sh-pfc/pfc-r8a7796.c const struct pinmux_bias_reg *reg; reg 6147 drivers/pinctrl/sh-pfc/pfc-r8a7796.c reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); reg 6148 drivers/pinctrl/sh-pfc/pfc-r8a7796.c if (!reg) reg 6151 drivers/pinctrl/sh-pfc/pfc-r8a7796.c if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) reg 6153 drivers/pinctrl/sh-pfc/pfc-r8a7796.c else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) reg 6162 drivers/pinctrl/sh-pfc/pfc-r8a7796.c const struct pinmux_bias_reg *reg; reg 6166 drivers/pinctrl/sh-pfc/pfc-r8a7796.c reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); reg 6167 drivers/pinctrl/sh-pfc/pfc-r8a7796.c if (!reg) reg 6170 drivers/pinctrl/sh-pfc/pfc-r8a7796.c enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); reg 6174 drivers/pinctrl/sh-pfc/pfc-r8a7796.c updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); reg 6178 drivers/pinctrl/sh-pfc/pfc-r8a7796.c sh_pfc_write(pfc, reg->pud, updown); reg 6179 drivers/pinctrl/sh-pfc/pfc-r8a7796.c sh_pfc_write(pfc, reg->puen, enable); reg 6128 drivers/pinctrl/sh-pfc/pfc-r8a77965.c *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; reg 6384 drivers/pinctrl/sh-pfc/pfc-r8a77965.c const struct pinmux_bias_reg *reg; reg 6387 drivers/pinctrl/sh-pfc/pfc-r8a77965.c reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); reg 6388 drivers/pinctrl/sh-pfc/pfc-r8a77965.c if (!reg) reg 6391 drivers/pinctrl/sh-pfc/pfc-r8a77965.c if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) reg 6393 drivers/pinctrl/sh-pfc/pfc-r8a77965.c else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) reg 6402 drivers/pinctrl/sh-pfc/pfc-r8a77965.c const struct pinmux_bias_reg *reg; reg 6406 drivers/pinctrl/sh-pfc/pfc-r8a77965.c reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); reg 6407 drivers/pinctrl/sh-pfc/pfc-r8a77965.c if (!reg) reg 6410 drivers/pinctrl/sh-pfc/pfc-r8a77965.c enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); reg 6414 drivers/pinctrl/sh-pfc/pfc-r8a77965.c updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); reg 6418 drivers/pinctrl/sh-pfc/pfc-r8a77965.c sh_pfc_write(pfc, reg->pud, updown); reg 6419 drivers/pinctrl/sh-pfc/pfc-r8a77965.c sh_pfc_write(pfc, reg->puen, enable); reg 2409 drivers/pinctrl/sh-pfc/pfc-r8a77970.c *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; reg 2415 drivers/pinctrl/sh-pfc/pfc-r8a77970.c *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; reg 2853 drivers/pinctrl/sh-pfc/pfc-r8a77980.c *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; reg 2859 drivers/pinctrl/sh-pfc/pfc-r8a77980.c *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; reg 2866 drivers/pinctrl/sh-pfc/pfc-r8a77980.c *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg; reg 5009 drivers/pinctrl/sh-pfc/pfc-r8a77990.c *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; reg 5231 drivers/pinctrl/sh-pfc/pfc-r8a77990.c const struct pinmux_bias_reg *reg; reg 5234 drivers/pinctrl/sh-pfc/pfc-r8a77990.c reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); reg 5235 drivers/pinctrl/sh-pfc/pfc-r8a77990.c if (!reg) reg 5238 drivers/pinctrl/sh-pfc/pfc-r8a77990.c if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) reg 5240 drivers/pinctrl/sh-pfc/pfc-r8a77990.c else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) reg 5249 drivers/pinctrl/sh-pfc/pfc-r8a77990.c const struct pinmux_bias_reg *reg; reg 5253 drivers/pinctrl/sh-pfc/pfc-r8a77990.c reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); reg 5254 drivers/pinctrl/sh-pfc/pfc-r8a77990.c if (!reg) reg 5257 drivers/pinctrl/sh-pfc/pfc-r8a77990.c enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); reg 5261 drivers/pinctrl/sh-pfc/pfc-r8a77990.c updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); reg 5265 drivers/pinctrl/sh-pfc/pfc-r8a77990.c sh_pfc_write(pfc, reg->pud, updown); reg 5266 drivers/pinctrl/sh-pfc/pfc-r8a77990.c sh_pfc_write(pfc, reg->puen, enable); reg 4230 drivers/pinctrl/sh-pfc/pfc-sh73a0.c static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable) reg 4232 drivers/pinctrl/sh-pfc/pfc-sh73a0.c struct sh_pfc *pfc = reg->reg_data; reg 4251 drivers/pinctrl/sh-pfc/pfc-sh73a0.c static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg) reg 4253 drivers/pinctrl/sh-pfc/pfc-sh73a0.c sh73a0_vccq_mc0_endisable(reg, true); reg 4257 drivers/pinctrl/sh-pfc/pfc-sh73a0.c static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg) reg 4259 drivers/pinctrl/sh-pfc/pfc-sh73a0.c sh73a0_vccq_mc0_endisable(reg, false); reg 4263 drivers/pinctrl/sh-pfc/pfc-sh73a0.c static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg) reg 4265 drivers/pinctrl/sh-pfc/pfc-sh73a0.c struct sh_pfc *pfc = reg->reg_data; reg 4277 drivers/pinctrl/sh-pfc/pfc-sh73a0.c static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg) reg 487 drivers/pinctrl/sh-pfc/pinctrl.c const struct pinmux_drive_reg *reg; reg 490 drivers/pinctrl/sh-pfc/pinctrl.c for (reg = pfc->info->drive_regs; reg->reg; ++reg) { reg 491 drivers/pinctrl/sh-pfc/pinctrl.c for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) { reg 492 drivers/pinctrl/sh-pfc/pinctrl.c field = ®->fields[i]; reg 498 drivers/pinctrl/sh-pfc/pinctrl.c return reg->reg; reg 512 drivers/pinctrl/sh-pfc/pinctrl.c u32 reg; reg 515 drivers/pinctrl/sh-pfc/pinctrl.c reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); reg 516 drivers/pinctrl/sh-pfc/pinctrl.c if (!reg) reg 520 drivers/pinctrl/sh-pfc/pinctrl.c val = sh_pfc_read(pfc, reg); reg 538 drivers/pinctrl/sh-pfc/pinctrl.c u32 reg; reg 541 drivers/pinctrl/sh-pfc/pinctrl.c reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); reg 542 drivers/pinctrl/sh-pfc/pinctrl.c if (!reg) reg 557 drivers/pinctrl/sh-pfc/pinctrl.c val = sh_pfc_read(pfc, reg); reg 561 drivers/pinctrl/sh-pfc/pinctrl.c sh_pfc_write(pfc, reg, val); reg 116 drivers/pinctrl/sh-pfc/sh_pfc.h u32 reg; reg 142 drivers/pinctrl/sh-pfc/sh_pfc.h .reg = r, .reg_width = r_width, \ reg 162 drivers/pinctrl/sh-pfc/sh_pfc.h .reg = r, .reg_width = r_width, \ reg 174 drivers/pinctrl/sh-pfc/sh_pfc.h u32 reg; reg 179 drivers/pinctrl/sh-pfc/sh_pfc.h .reg = r, \ reg 194 drivers/pinctrl/sh-pfc/sh_pfc.h u32 reg; reg 198 drivers/pinctrl/sh-pfc/sh_pfc.h u32 reg; reg 212 drivers/pinctrl/sh-pfc/sh_pfc.h .reg = r, .reg_width = r_width + \ reg 728 drivers/pinctrl/sh-pfc/sh_pfc.h #define PORTCR(nr, reg) \ reg 730 drivers/pinctrl/sh-pfc/sh_pfc.h PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \ reg 324 drivers/pinctrl/sirf/pinctrl-atlas7.c #define ATLAS7_GPIO_BASE(g, b) ((g)->reg + 0x100 * (b)) reg 350 drivers/pinctrl/sirf/pinctrl-atlas7.c void __iomem *reg; reg 6026 drivers/pinctrl/sirf/pinctrl-atlas7.c a7gc->reg = of_iomap(np, 0); reg 6027 drivers/pinctrl/sirf/pinctrl-atlas7.c if (!a7gc->reg) { reg 26 drivers/pinctrl/spear/pinctrl-plgpio.c #define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \ reg 80 drivers/pinctrl/spear/pinctrl-plgpio.c static inline u32 is_plgpio_set(void __iomem *base, u32 pin, u32 reg) reg 83 drivers/pinctrl/spear/pinctrl-plgpio.c void __iomem *reg_off = REG_OFFSET(base, reg, pin); reg 89 drivers/pinctrl/spear/pinctrl-plgpio.c static inline void plgpio_reg_set(void __iomem *base, u32 pin, u32 reg) reg 92 drivers/pinctrl/spear/pinctrl-plgpio.c void __iomem *reg_off = REG_OFFSET(base, reg, pin); reg 98 drivers/pinctrl/spear/pinctrl-plgpio.c static inline void plgpio_reg_reset(void __iomem *base, u32 pin, u32 reg) reg 101 drivers/pinctrl/spear/pinctrl-plgpio.c void __iomem *reg_off = REG_OFFSET(base, reg, pin); reg 40 drivers/pinctrl/spear/pinctrl-spear.c val = pmx_readl(pmx, muxreg->reg); reg 49 drivers/pinctrl/spear/pinctrl-spear.c pmx_writel(pmx, val, muxreg->reg); reg 72 drivers/pinctrl/spear/pinctrl-spear.c val = pmx_readl(pmx, pmx_mode->reg); reg 75 drivers/pinctrl/spear/pinctrl-spear.c pmx_writel(pmx, val, pmx_mode->reg); reg 80 drivers/pinctrl/spear/pinctrl-spear.c pmx_mode->reg); reg 86 drivers/pinctrl/spear/pinctrl-spear.c unsigned count, u16 reg) reg 92 drivers/pinctrl/spear/pinctrl-spear.c gpio_pingroup[i].muxregs[j].reg = reg; reg 95 drivers/pinctrl/spear/pinctrl-spear.c void pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg) reg 108 drivers/pinctrl/spear/pinctrl-spear.c if (modemux->muxregs[j].reg == 0xFFFF) reg 109 drivers/pinctrl/spear/pinctrl-spear.c modemux->muxregs[j].reg = reg; reg 35 drivers/pinctrl/spear/pinctrl-spear.h u16 reg; reg 47 drivers/pinctrl/spear/pinctrl-spear.h u16 reg; reg 63 drivers/pinctrl/spear/pinctrl-spear.h .reg = __muxreg, \ reg 72 drivers/pinctrl/spear/pinctrl-spear.h .reg = __muxreg1, \ reg 76 drivers/pinctrl/spear/pinctrl-spear.h .reg = __muxreg2, \ reg 185 drivers/pinctrl/spear/pinctrl-spear.h static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg) reg 187 drivers/pinctrl/spear/pinctrl-spear.h return readl_relaxed(pmx->vbase + reg); reg 190 drivers/pinctrl/spear/pinctrl-spear.h static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg) reg 192 drivers/pinctrl/spear/pinctrl-spear.h writel_relaxed(val, pmx->vbase + reg); reg 195 drivers/pinctrl/spear/pinctrl-spear.h void pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg); reg 197 drivers/pinctrl/spear/pinctrl-spear.h unsigned count, u16 reg); reg 240 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 244 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 276 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 280 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 305 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_2, reg 309 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_2, reg 334 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_2, reg 338 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_2, reg 371 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 375 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 407 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 411 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 445 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 449 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 474 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 478 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 510 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 514 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 518 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 522 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 554 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 558 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 582 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 586 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 590 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 594 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 628 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 632 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 666 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 670 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 674 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_2, reg 678 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 682 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 686 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_2, reg 720 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 724 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 756 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 760 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 796 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 800 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 804 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 808 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 834 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 838 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 863 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 867 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 901 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 928 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 932 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 965 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 969 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 994 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 998 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 1030 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 1034 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 1059 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 1063 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 1095 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 1099 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 1124 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 1128 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 1163 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, \ reg 1167 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, \ reg 1172 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_2, \ reg 1176 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, \ reg 1180 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, \ reg 1186 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_2, \ reg 1195 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PERIP_CFG, reg 1227 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PERIP_CFG, reg 1259 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PERIP_CFG, reg 1291 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_2, reg 1295 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_2, reg 1328 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 1332 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 1357 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 1362 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 1397 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 1401 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 1433 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 1437 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 1469 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 1473 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 1507 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 1511 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 1543 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 1547 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 1580 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 1584 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 1610 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 1614 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 1648 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 1652 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 1678 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 1682 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_2, reg 1686 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 1690 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_2, reg 1716 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_2, reg 1721 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_2, reg 1757 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 1761 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 1787 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_2, reg 1792 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_2, reg 1819 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_2, reg 1824 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_2, reg 1860 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 1864 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 1868 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 1872 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 1898 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_2, reg 1902 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_2, reg 1936 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_2, reg 1940 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_2, reg 1966 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 1970 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 2007 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_0, reg 2011 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 2015 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_2, reg 2019 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_0, reg 2023 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 2027 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_2, reg 2058 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PCIE_SATA_CFG, reg 2080 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PCIE_SATA_CFG, reg 2102 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PCIE_SATA_CFG, reg 2132 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PCIE_SATA_CFG, reg 2154 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PCIE_SATA_CFG, reg 2176 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PCIE_SATA_CFG, reg 2207 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_1, reg 2213 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_1, reg 2242 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_2, reg 2247 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_2, reg 2282 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_FUNCTION_EN_2, reg 2287 drivers/pinctrl/spear/pinctrl-spear1310.c .reg = PAD_DIRECTION_SEL_2, reg 218 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_1, reg 222 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_2, reg 226 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_3, reg 230 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_4, reg 234 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_5, reg 238 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_6, reg 242 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_7, reg 246 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_8, reg 279 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_8, reg 304 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 308 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_1, reg 335 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 339 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_7, reg 373 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 377 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_1, reg 402 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 406 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_1, reg 439 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_1, reg 471 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_5, reg 475 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PERIP_CFG, reg 507 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 511 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_1, reg 547 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 551 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_1, reg 576 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 580 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_1, reg 605 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 609 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_1, reg 634 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 638 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_1, reg 671 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_2, reg 697 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 701 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_3, reg 727 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 731 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_2, reg 735 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_3, reg 761 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 765 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_2, reg 791 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 795 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_1, reg 799 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_2, reg 833 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 837 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_3, reg 870 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 874 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_2, reg 878 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_3, reg 911 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 915 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_2, reg 948 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 952 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_1, reg 956 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_2, reg 988 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_3, reg 1020 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_3, reg 1045 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 1049 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_1, reg 1074 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 1078 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_3, reg 1103 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_5, reg 1136 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_3, reg 1161 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 1165 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_1, reg 1197 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_3, reg 1229 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_3, reg 1233 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_4, reg 1258 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_4, reg 1292 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_4, \ reg 1296 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_5, \ reg 1305 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = GMAC_CLK_CFG, reg 1330 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = GMAC_CLK_CFG, reg 1355 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = GMAC_CLK_CFG, reg 1380 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = GMAC_CLK_CFG, reg 1413 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_5, reg 1445 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_1, reg 1477 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_5, reg 1509 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_5, reg 1544 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, \ reg 1548 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_7, \ reg 1552 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_8, \ reg 1561 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PERIP_CFG, reg 1593 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PERIP_CFG, reg 1625 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PERIP_CFG, reg 1661 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 1665 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_5, reg 1669 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_6, reg 1673 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_7, reg 1697 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 1701 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_5, reg 1705 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_6, reg 1709 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_7, reg 1744 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 1748 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_5, reg 1752 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_6, reg 1756 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_7, reg 1790 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_SHARED_IP_EN_1, reg 1794 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PAD_FUNCTION_EN_5, reg 1826 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PCIE_SATA_CFG, reg 1858 drivers/pinctrl/spear/pinctrl-spear1340.c .reg = PCIE_SATA_CFG, reg 42 drivers/pinctrl/spear/pinctrl-spear300.c .reg = MODE_CONFIG_REG, reg 50 drivers/pinctrl/spear/pinctrl-spear300.c .reg = MODE_CONFIG_REG, reg 58 drivers/pinctrl/spear/pinctrl-spear300.c .reg = MODE_CONFIG_REG, reg 66 drivers/pinctrl/spear/pinctrl-spear300.c .reg = MODE_CONFIG_REG, reg 74 drivers/pinctrl/spear/pinctrl-spear300.c .reg = MODE_CONFIG_REG, reg 82 drivers/pinctrl/spear/pinctrl-spear300.c .reg = MODE_CONFIG_REG, reg 90 drivers/pinctrl/spear/pinctrl-spear300.c .reg = MODE_CONFIG_REG, reg 98 drivers/pinctrl/spear/pinctrl-spear300.c .reg = MODE_CONFIG_REG, reg 106 drivers/pinctrl/spear/pinctrl-spear300.c .reg = MODE_CONFIG_REG, reg 114 drivers/pinctrl/spear/pinctrl-spear300.c .reg = MODE_CONFIG_REG, reg 122 drivers/pinctrl/spear/pinctrl-spear300.c .reg = MODE_CONFIG_REG, reg 130 drivers/pinctrl/spear/pinctrl-spear300.c .reg = MODE_CONFIG_REG, reg 138 drivers/pinctrl/spear/pinctrl-spear300.c .reg = MODE_CONFIG_REG, reg 163 drivers/pinctrl/spear/pinctrl-spear300.c .reg = PMX_CONFIG_REG, reg 190 drivers/pinctrl/spear/pinctrl-spear300.c .reg = PMX_CONFIG_REG, reg 225 drivers/pinctrl/spear/pinctrl-spear300.c .reg = PMX_CONFIG_REG, reg 252 drivers/pinctrl/spear/pinctrl-spear300.c .reg = PMX_CONFIG_REG, reg 286 drivers/pinctrl/spear/pinctrl-spear300.c .reg = PMX_CONFIG_REG, reg 323 drivers/pinctrl/spear/pinctrl-spear300.c .reg = PMX_CONFIG_REG, reg 359 drivers/pinctrl/spear/pinctrl-spear300.c .reg = PMX_CONFIG_REG, reg 385 drivers/pinctrl/spear/pinctrl-spear300.c .reg = PMX_CONFIG_REG, reg 418 drivers/pinctrl/spear/pinctrl-spear300.c .reg = PMX_CONFIG_REG, reg 452 drivers/pinctrl/spear/pinctrl-spear300.c .reg = PMX_CONFIG_REG, reg 488 drivers/pinctrl/spear/pinctrl-spear300.c .reg = PMX_CONFIG_REG, reg 520 drivers/pinctrl/spear/pinctrl-spear300.c .reg = PMX_CONFIG_REG, reg 558 drivers/pinctrl/spear/pinctrl-spear300.c .reg = PMX_CONFIG_REG, reg 585 drivers/pinctrl/spear/pinctrl-spear300.c .reg = PMX_CONFIG_REG, reg 27 drivers/pinctrl/spear/pinctrl-spear310.c .reg = PMX_CONFIG_REG, reg 59 drivers/pinctrl/spear/pinctrl-spear310.c .reg = PMX_CONFIG_REG, reg 91 drivers/pinctrl/spear/pinctrl-spear310.c .reg = PMX_CONFIG_REG, reg 123 drivers/pinctrl/spear/pinctrl-spear310.c .reg = PMX_CONFIG_REG, reg 155 drivers/pinctrl/spear/pinctrl-spear310.c .reg = PMX_CONFIG_REG, reg 187 drivers/pinctrl/spear/pinctrl-spear310.c .reg = PMX_CONFIG_REG, reg 219 drivers/pinctrl/spear/pinctrl-spear310.c .reg = PMX_CONFIG_REG, reg 251 drivers/pinctrl/spear/pinctrl-spear310.c .reg = PMX_CONFIG_REG, reg 283 drivers/pinctrl/spear/pinctrl-spear310.c .reg = PMX_CONFIG_REG, reg 315 drivers/pinctrl/spear/pinctrl-spear310.c .reg = PMX_CONFIG_REG, reg 35 drivers/pinctrl/spear/pinctrl-spear320.c .reg = MODE_CONFIG_REG, reg 43 drivers/pinctrl/spear/pinctrl-spear320.c .reg = MODE_CONFIG_REG, reg 51 drivers/pinctrl/spear/pinctrl-spear320.c .reg = MODE_CONFIG_REG, reg 59 drivers/pinctrl/spear/pinctrl-spear320.c .reg = MODE_CONFIG_REG, reg 67 drivers/pinctrl/spear/pinctrl-spear320.c .reg = MODE_EXT_CONFIG_REG, reg 464 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_60_69_REG, reg 468 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_70_79_REG, reg 476 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_80_89_REG, reg 482 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_90_99_REG, reg 521 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 529 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_40_49_REG, reg 533 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_50_59_REG, reg 540 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_60_69_REG, reg 544 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_70_79_REG, reg 552 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_80_89_REG, reg 558 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_90_99_REG, reg 564 drivers/pinctrl/spear/pinctrl-spear320.c .reg = EXT_CTRL_REG, reg 602 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_50_59_REG, reg 608 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_60_69_REG, reg 614 drivers/pinctrl/spear/pinctrl-spear320.c .reg = EXT_CTRL_REG, reg 640 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 648 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_40_49_REG, reg 652 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_70_79_REG, reg 695 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_60_69_REG, reg 699 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_70_79_REG, reg 707 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_80_89_REG, reg 740 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 748 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_30_39_REG, reg 780 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 788 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_40_49_REG, reg 794 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_50_59_REG, reg 798 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_90_99_REG, reg 802 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 810 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 814 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_10_19_REG, reg 818 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 826 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_50_59_REG, reg 830 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 897 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 901 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 909 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_30_39_REG, reg 913 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_40_49_REG, reg 950 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 958 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_20_29_REG, reg 1000 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 1004 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_0_9_REG, reg 1009 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1017 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 1026 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_30_39_REG, reg 1033 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1041 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 1050 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_30_39_REG, reg 1055 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_40_49_REG, reg 1059 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1067 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_80_89_REG, reg 1071 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_40_49_REG, reg 1075 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1162 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 1170 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_0_9_REG, reg 1210 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 1214 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_0_9_REG, reg 1218 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1226 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 1230 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_10_19_REG, reg 1234 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1242 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 1246 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_40_49_REG, reg 1250 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1258 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_50_59_REG, reg 1262 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1270 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_70_79_REG, reg 1274 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1282 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_90_99_REG, reg 1286 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1294 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_90_99_REG, reg 1298 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1419 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 1423 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_0_9_REG, reg 1427 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1435 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 1439 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_10_19_REG, reg 1443 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1451 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 1455 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_30_39_REG, reg 1459 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_40_49_REG, reg 1463 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1471 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_70_79_REG, reg 1475 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1483 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_90_99_REG, reg 1487 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1495 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1605 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 1609 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_0_9_REG, reg 1613 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1621 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 1625 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_30_39_REG, reg 1629 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1637 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_60_69_REG, reg 1641 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_70_79_REG, reg 1645 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1653 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_90_99_REG, reg 1657 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1735 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 1739 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_0_9_REG, reg 1743 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1751 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_80_89_REG, reg 1755 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 1806 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_70_79_REG, reg 1839 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 1847 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_0_9_REG, reg 1851 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_30_39_REG, reg 1888 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 1896 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_30_39_REG, reg 1933 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 1941 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_30_39_REG, reg 1981 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 1985 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_0_9_REG, reg 1993 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2001 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_10_19_REG, reg 2009 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2013 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_30_39_REG, reg 2021 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2029 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_30_39_REG, reg 2037 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2041 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_40_49_REG, reg 2050 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_50_59_REG, reg 2054 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_60_69_REG, reg 2062 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_80_89_REG, reg 2194 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2202 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_0_9_REG, reg 2210 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2218 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_10_19_REG, reg 2226 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2230 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_20_29_REG, reg 2238 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2242 drivers/pinctrl/spear/pinctrl-spear320.c .reg = MODE_CONFIG_REG, reg 2246 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_30_39_REG, reg 2254 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2258 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_40_49_REG, reg 2266 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_50_59_REG, reg 2274 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_80_89_REG, reg 2401 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2405 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_0_9_REG, reg 2413 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2421 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_10_19_REG, reg 2429 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2433 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_20_29_REG, reg 2441 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2445 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_40_49_REG, reg 2453 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_50_59_REG, reg 2461 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_80_89_REG, reg 2574 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2582 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_10_19_REG, reg 2586 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_20_29_REG, reg 2590 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 2598 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2602 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_30_39_REG, reg 2607 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 2615 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2619 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_40_49_REG, reg 2623 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_50_59_REG, reg 2627 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 2635 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_60_69_REG, reg 2639 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 2647 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_90_99_REG, reg 2651 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 2749 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2757 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_10_19_REG, reg 2761 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 2769 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2774 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_30_39_REG, reg 2779 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 2787 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2791 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_40_49_REG, reg 2795 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 2803 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_60_69_REG, reg 2807 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 2815 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_90_99_REG, reg 2819 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 2916 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_80_89_REG, reg 2922 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_90_99_REG, reg 2928 drivers/pinctrl/spear/pinctrl-spear320.c .reg = EXT_CTRL_REG, reg 2967 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 2975 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_10_19_REG, reg 2979 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_20_29_REG, reg 2983 drivers/pinctrl/spear/pinctrl-spear320.c .reg = EXT_CTRL_REG, reg 2995 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_10_19_REG, reg 3002 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_20_29_REG, reg 3006 drivers/pinctrl/spear/pinctrl-spear320.c .reg = EXT_CTRL_REG, reg 3071 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 3075 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_0_9_REG, reg 3079 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 3087 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_90_99_REG, reg 3091 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 3143 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 3147 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_0_9_REG, reg 3151 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 3159 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 3163 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_0_9_REG, reg 3167 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 3175 drivers/pinctrl/spear/pinctrl-spear320.c .reg = PMX_CONFIG_REG, reg 3179 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_10_19_REG, reg 3183 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_20_29_REG, reg 3187 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 3195 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_70_79_REG, reg 3199 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 3207 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_PAD_90_99_REG, reg 3211 drivers/pinctrl/spear/pinctrl-spear320.c .reg = IP_SEL_MIX_PAD_REG, reg 25 drivers/pinctrl/spear/pinctrl-spear3xx.c .reg = -1, reg 58 drivers/pinctrl/spear/pinctrl-spear3xx.c .reg = -1, reg 91 drivers/pinctrl/spear/pinctrl-spear3xx.c .reg = -1, reg 124 drivers/pinctrl/spear/pinctrl-spear3xx.c .reg = -1, reg 158 drivers/pinctrl/spear/pinctrl-spear3xx.c .reg = -1, reg 191 drivers/pinctrl/spear/pinctrl-spear3xx.c .reg = -1, reg 217 drivers/pinctrl/spear/pinctrl-spear3xx.c .reg = -1, reg 243 drivers/pinctrl/spear/pinctrl-spear3xx.c .reg = -1, reg 269 drivers/pinctrl/spear/pinctrl-spear3xx.c .reg = -1, reg 295 drivers/pinctrl/spear/pinctrl-spear3xx.c .reg = -1, reg 321 drivers/pinctrl/spear/pinctrl-spear3xx.c .reg = -1, reg 356 drivers/pinctrl/spear/pinctrl-spear3xx.c .reg = -1, reg 389 drivers/pinctrl/spear/pinctrl-spear3xx.c .reg = -1, reg 422 drivers/pinctrl/spear/pinctrl-spear3xx.c .reg = -1, reg 455 drivers/pinctrl/spear/pinctrl-spear3xx.c .reg = -1, reg 107 drivers/pinctrl/sprd/pinctrl-sprd.c unsigned long reg; reg 390 drivers/pinctrl/sprd/pinctrl-sprd.c unsigned long reg; reg 420 drivers/pinctrl/sprd/pinctrl-sprd.c reg = readl((void __iomem *)pin->reg); reg 421 drivers/pinctrl/sprd/pinctrl-sprd.c reg &= ~PIN_FUNC_MASK; reg 422 drivers/pinctrl/sprd/pinctrl-sprd.c reg |= val; reg 423 drivers/pinctrl/sprd/pinctrl-sprd.c writel(reg, (void __iomem *)pin->reg); reg 442 drivers/pinctrl/sprd/pinctrl-sprd.c unsigned int reg, arg; reg 448 drivers/pinctrl/sprd/pinctrl-sprd.c reg = (readl((void __iomem *)pin->reg) >> reg 451 drivers/pinctrl/sprd/pinctrl-sprd.c reg = readl((void __iomem *)pin->reg); reg 456 drivers/pinctrl/sprd/pinctrl-sprd.c arg = reg; reg 460 drivers/pinctrl/sprd/pinctrl-sprd.c arg = (reg >> SLEEP_MODE_SHIFT) & SLEEP_MODE_MASK; reg 463 drivers/pinctrl/sprd/pinctrl-sprd.c arg = (reg >> SLEEP_INPUT_SHIFT) & SLEEP_INPUT_MASK; reg 466 drivers/pinctrl/sprd/pinctrl-sprd.c arg = reg & SLEEP_OUTPUT_MASK; reg 469 drivers/pinctrl/sprd/pinctrl-sprd.c arg = (reg >> DRIVE_STRENGTH_SHIFT) & reg 474 drivers/pinctrl/sprd/pinctrl-sprd.c arg = ((reg >> SLEEP_PULL_DOWN_SHIFT) & reg 476 drivers/pinctrl/sprd/pinctrl-sprd.c arg |= (reg >> PULL_DOWN_SHIFT) & PULL_DOWN_MASK; reg 479 drivers/pinctrl/sprd/pinctrl-sprd.c arg = (reg >> INPUT_SCHMITT_SHIFT) & INPUT_SCHMITT_MASK; reg 483 drivers/pinctrl/sprd/pinctrl-sprd.c arg = ((reg >> SLEEP_PULL_UP_SHIFT) & reg 485 drivers/pinctrl/sprd/pinctrl-sprd.c arg |= (reg >> PULL_UP_SHIFT) & PULL_UP_MASK; reg 581 drivers/pinctrl/sprd/pinctrl-sprd.c unsigned long reg; reg 687 drivers/pinctrl/sprd/pinctrl-sprd.c reg = readl((void __iomem *)pin->reg); reg 688 drivers/pinctrl/sprd/pinctrl-sprd.c reg &= ~(PINCTRL_BIT_MASK(pin->bit_width) reg 690 drivers/pinctrl/sprd/pinctrl-sprd.c reg |= (val & PINCTRL_BIT_MASK(pin->bit_width)) reg 692 drivers/pinctrl/sprd/pinctrl-sprd.c writel(reg, (void __iomem *)pin->reg); reg 694 drivers/pinctrl/sprd/pinctrl-sprd.c reg = readl((void __iomem *)pin->reg); reg 695 drivers/pinctrl/sprd/pinctrl-sprd.c reg &= ~(mask << shift); reg 696 drivers/pinctrl/sprd/pinctrl-sprd.c reg |= val; reg 697 drivers/pinctrl/sprd/pinctrl-sprd.c writel(reg, (void __iomem *)pin->reg); reg 758 drivers/pinctrl/sprd/pinctrl-sprd.c *config = (readl((void __iomem *)pin->reg) >> reg 761 drivers/pinctrl/sprd/pinctrl-sprd.c *config = readl((void __iomem *)pin->reg); reg 972 drivers/pinctrl/sprd/pinctrl-sprd.c unsigned int reg; reg 977 drivers/pinctrl/sprd/pinctrl-sprd.c reg = sprd_soc_pin_info[i].reg; reg 979 drivers/pinctrl/sprd/pinctrl-sprd.c pin->reg = (unsigned long)sprd_pctl->base + reg 980 drivers/pinctrl/sprd/pinctrl-sprd.c PINCTRL_REG_LEN * reg; reg 985 drivers/pinctrl/sprd/pinctrl-sprd.c pin->reg = (unsigned long)sprd_pctl->base + reg 990 drivers/pinctrl/sprd/pinctrl-sprd.c pin->reg = (unsigned long)sprd_pctl->base + reg 1000 drivers/pinctrl/sprd/pinctrl-sprd.c pin->bit_offset, pin->bit_width, pin->reg); reg 17 drivers/pinctrl/sprd/pinctrl-sprd.h #define SPRD_PIN_INFO(num, type, offset, width, reg) \ reg 22 drivers/pinctrl/sprd/pinctrl-sprd.h ((reg) & 0xF)) reg 33 drivers/pinctrl/sprd/pinctrl-sprd.h .reg = ((a) & 0xf) \ reg 50 drivers/pinctrl/sprd/pinctrl-sprd.h unsigned int reg; reg 1281 drivers/pinctrl/stm32/pinctrl-stm32.c mux.reg = offset + (i / 4) * 4; reg 1286 drivers/pinctrl/stm32/pinctrl-stm32.c i, mux.reg, mux.lsb, mux.msb); reg 542 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 offset, shift, mask, reg; reg 586 drivers/pinctrl/sunxi/pinctrl-sunxi.c reg = readl(pctl->membase + offset); reg 587 drivers/pinctrl/sunxi/pinctrl-sunxi.c reg &= ~(mask << shift); reg 588 drivers/pinctrl/sunxi/pinctrl-sunxi.c writel(reg | val << shift, pctl->membase + offset); reg 619 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 val, reg; reg 652 drivers/pinctrl/sunxi/pinctrl-sunxi.c reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); reg 653 drivers/pinctrl/sunxi/pinctrl-sunxi.c reg &= ~IO_BIAS_MASK; reg 654 drivers/pinctrl/sunxi/pinctrl-sunxi.c writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); reg 660 drivers/pinctrl/sunxi/pinctrl-sunxi.c reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG); reg 661 drivers/pinctrl/sunxi/pinctrl-sunxi.c reg &= ~(1 << bank); reg 662 drivers/pinctrl/sunxi/pinctrl-sunxi.c writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG); reg 768 drivers/pinctrl/sunxi/pinctrl-sunxi.c struct regulator *reg = s_reg->regulator; reg 772 drivers/pinctrl/sunxi/pinctrl-sunxi.c if (reg) { reg 778 drivers/pinctrl/sunxi/pinctrl-sunxi.c reg = regulator_get(pctl->dev, supply); reg 779 drivers/pinctrl/sunxi/pinctrl-sunxi.c if (IS_ERR(reg)) { reg 782 drivers/pinctrl/sunxi/pinctrl-sunxi.c return PTR_ERR(reg); reg 785 drivers/pinctrl/sunxi/pinctrl-sunxi.c ret = regulator_enable(reg); reg 792 drivers/pinctrl/sunxi/pinctrl-sunxi.c sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg); reg 794 drivers/pinctrl/sunxi/pinctrl-sunxi.c s_reg->regulator = reg; reg 843 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 reg = sunxi_data_reg(offset); reg 853 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; reg 865 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 reg = sunxi_data_reg(offset); reg 872 drivers/pinctrl/sunxi/pinctrl-sunxi.c regval = readl(pctl->membase + reg); reg 879 drivers/pinctrl/sunxi/pinctrl-sunxi.c writel(regval, pctl->membase + reg); reg 967 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq); reg 1002 drivers/pinctrl/sunxi/pinctrl-sunxi.c regval = readl(pctl->membase + reg); reg 1004 drivers/pinctrl/sunxi/pinctrl-sunxi.c writel(regval | (mode << index), pctl->membase + reg); reg 1024 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); reg 1032 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = readl(pctl->membase + reg); reg 1033 drivers/pinctrl/sunxi/pinctrl-sunxi.c writel(val & ~(1 << idx), pctl->membase + reg); reg 1041 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); reg 1049 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = readl(pctl->membase + reg); reg 1050 drivers/pinctrl/sunxi/pinctrl-sunxi.c writel(val | (1 << idx), pctl->membase + reg); reg 1124 drivers/pinctrl/sunxi/pinctrl-sunxi.c unsigned long bank, reg, val; reg 1133 drivers/pinctrl/sunxi/pinctrl-sunxi.c reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank); reg 1134 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = readl(pctl->membase + reg); reg 307 drivers/pinctrl/sunxi/pinctrl-sunxi.h u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04; reg 310 drivers/pinctrl/sunxi/pinctrl-sunxi.h sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg; reg 28 drivers/pinctrl/tegra/pinctrl-tegra.c static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) reg 30 drivers/pinctrl/tegra/pinctrl-tegra.c return readl(pmx->regs[bank] + reg); reg 33 drivers/pinctrl/tegra/pinctrl-tegra.c static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) reg 35 drivers/pinctrl/tegra/pinctrl-tegra.c writel_relaxed(val, pmx->regs[bank] + reg); reg 37 drivers/pinctrl/tegra/pinctrl-tegra.c pmx_readl(pmx, bank, reg); reg 289 drivers/pinctrl/tegra/pinctrl-tegra.c s8 *bank, s32 *reg, s8 *bit, s8 *width) reg 294 drivers/pinctrl/tegra/pinctrl-tegra.c *reg = g->pupd_reg; reg 300 drivers/pinctrl/tegra/pinctrl-tegra.c *reg = g->tri_reg; reg 306 drivers/pinctrl/tegra/pinctrl-tegra.c *reg = g->mux_reg; reg 312 drivers/pinctrl/tegra/pinctrl-tegra.c *reg = g->mux_reg; reg 318 drivers/pinctrl/tegra/pinctrl-tegra.c *reg = g->mux_reg; reg 324 drivers/pinctrl/tegra/pinctrl-tegra.c *reg = g->mux_reg; reg 330 drivers/pinctrl/tegra/pinctrl-tegra.c *reg = g->mux_reg; reg 337 drivers/pinctrl/tegra/pinctrl-tegra.c *reg = g->mux_reg; reg 340 drivers/pinctrl/tegra/pinctrl-tegra.c *reg = g->drv_reg; reg 348 drivers/pinctrl/tegra/pinctrl-tegra.c *reg = g->mux_reg; reg 351 drivers/pinctrl/tegra/pinctrl-tegra.c *reg = g->drv_reg; reg 358 drivers/pinctrl/tegra/pinctrl-tegra.c *reg = g->drv_reg; reg 364 drivers/pinctrl/tegra/pinctrl-tegra.c *reg = g->drv_reg; reg 370 drivers/pinctrl/tegra/pinctrl-tegra.c *reg = g->drv_reg; reg 376 drivers/pinctrl/tegra/pinctrl-tegra.c *reg = g->drv_reg; reg 382 drivers/pinctrl/tegra/pinctrl-tegra.c *reg = g->drv_reg; reg 389 drivers/pinctrl/tegra/pinctrl-tegra.c *reg = g->mux_reg; reg 392 drivers/pinctrl/tegra/pinctrl-tegra.c *reg = g->drv_reg; reg 402 drivers/pinctrl/tegra/pinctrl-tegra.c if (*reg < 0 || *bit < 0) { reg 448 drivers/pinctrl/tegra/pinctrl-tegra.c s32 reg; reg 453 drivers/pinctrl/tegra/pinctrl-tegra.c ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, reg 458 drivers/pinctrl/tegra/pinctrl-tegra.c val = pmx_readl(pmx, bank, reg); reg 477 drivers/pinctrl/tegra/pinctrl-tegra.c s32 reg; reg 486 drivers/pinctrl/tegra/pinctrl-tegra.c ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, reg 491 drivers/pinctrl/tegra/pinctrl-tegra.c val = pmx_readl(pmx, bank, reg); reg 517 drivers/pinctrl/tegra/pinctrl-tegra.c pmx_writel(pmx, val, bank, reg); reg 545 drivers/pinctrl/tegra/pinctrl-tegra.c s32 reg; reg 552 drivers/pinctrl/tegra/pinctrl-tegra.c &bank, ®, &bit, &width); reg 556 drivers/pinctrl/tegra/pinctrl-tegra.c val = pmx_readl(pmx, bank, reg); reg 619 drivers/pinctrl/tegra/pinctrl-tegra.c unsigned int bank, reg; reg 623 drivers/pinctrl/tegra/pinctrl-tegra.c reg = g->mux_reg; reg 626 drivers/pinctrl/tegra/pinctrl-tegra.c reg = g->drv_reg; reg 629 drivers/pinctrl/tegra/pinctrl-tegra.c val = pmx_readl(pmx, bank, reg); reg 631 drivers/pinctrl/tegra/pinctrl-tegra.c pmx_writel(pmx, val, bank, reg); reg 209 drivers/pinctrl/ti/pinctrl-ti-iodelay.c const struct ti_iodelay_reg_data *reg = iod->reg_data; reg 235 drivers/pinctrl/ti/pinctrl-ti-iodelay.c reg_mask = reg->signature_mask; reg 236 drivers/pinctrl/ti/pinctrl-ti-iodelay.c reg_val = reg->signature_value << __ffs(reg->signature_mask); reg 238 drivers/pinctrl/ti/pinctrl-ti-iodelay.c reg_mask |= reg->binary_data_coarse_mask; reg 239 drivers/pinctrl/ti/pinctrl-ti-iodelay.c tmp_val = c_elements << __ffs(reg->binary_data_coarse_mask); reg 240 drivers/pinctrl/ti/pinctrl-ti-iodelay.c if (tmp_val & ~reg->binary_data_coarse_mask) { reg 243 drivers/pinctrl/ti/pinctrl-ti-iodelay.c tmp_val &= reg->binary_data_coarse_mask; reg 247 drivers/pinctrl/ti/pinctrl-ti-iodelay.c reg_mask |= reg->binary_data_fine_mask; reg 248 drivers/pinctrl/ti/pinctrl-ti-iodelay.c tmp_val = f_elements << __ffs(reg->binary_data_fine_mask); reg 249 drivers/pinctrl/ti/pinctrl-ti-iodelay.c if (tmp_val & ~reg->binary_data_fine_mask) { reg 252 drivers/pinctrl/ti/pinctrl-ti-iodelay.c tmp_val &= reg->binary_data_fine_mask; reg 262 drivers/pinctrl/ti/pinctrl-ti-iodelay.c reg_mask |= reg->lock_mask; reg 263 drivers/pinctrl/ti/pinctrl-ti-iodelay.c reg_val |= reg->unlock_val << __ffs(reg->lock_mask); reg 283 drivers/pinctrl/ti/pinctrl-ti-iodelay.c const struct ti_iodelay_reg_data *reg = iod->reg_data; reg 290 drivers/pinctrl/ti/pinctrl-ti-iodelay.c r = regmap_update_bits(iod->regmap, reg->reg_global_lock_offset, reg 291 drivers/pinctrl/ti/pinctrl-ti-iodelay.c reg->global_lock_mask, reg->global_unlock_val); reg 296 drivers/pinctrl/ti/pinctrl-ti-iodelay.c r = regmap_read(iod->regmap, reg->reg_refclk_offset, &val); reg 299 drivers/pinctrl/ti/pinctrl-ti-iodelay.c ival->ref_clk_period = ti_iodelay_extract(val, reg->refclk_period_mask); reg 302 drivers/pinctrl/ti/pinctrl-ti-iodelay.c r = regmap_read(iod->regmap, reg->reg_coarse_offset, &val); reg 306 drivers/pinctrl/ti/pinctrl-ti-iodelay.c ti_iodelay_extract(val, reg->coarse_ref_count_mask); reg 308 drivers/pinctrl/ti/pinctrl-ti-iodelay.c ti_iodelay_extract(val, reg->coarse_delay_count_mask); reg 326 drivers/pinctrl/ti/pinctrl-ti-iodelay.c r = regmap_read(iod->regmap, reg->reg_fine_offset, &val); reg 330 drivers/pinctrl/ti/pinctrl-ti-iodelay.c ti_iodelay_extract(val, reg->fine_ref_count_mask); reg 332 drivers/pinctrl/ti/pinctrl-ti-iodelay.c ti_iodelay_extract(val, reg->fine_delay_count_mask); reg 361 drivers/pinctrl/ti/pinctrl-ti-iodelay.c const struct ti_iodelay_reg_data *reg = iod->reg_data; reg 364 drivers/pinctrl/ti/pinctrl-ti-iodelay.c regmap_update_bits(iod->regmap, reg->reg_global_lock_offset, reg 365 drivers/pinctrl/ti/pinctrl-ti-iodelay.c reg->global_lock_mask, reg->global_lock_val); reg 704 drivers/pinctrl/ti/pinctrl-ti-iodelay.c u32 reg = 0; reg 707 drivers/pinctrl/ti/pinctrl-ti-iodelay.c regmap_read(iod->regmap, cfg->offset, ®), reg 709 drivers/pinctrl/ti/pinctrl-ti-iodelay.c cfg->offset, reg, cfg->a_delay, reg 148 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int pin, unsigned int *reg, reg 197 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c *reg = base + drvctrl / 32 * 4; reg 212 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int pupdctrl, reg, shift, val; reg 243 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pupdctrl / 32 * 4; reg 246 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c ret = regmap_read(priv->regmap, reg, &val); reg 259 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int reg, shift, mask, val; reg 263 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c ret = uniphier_conf_get_drvctrl_data(pctldev, pin, ®, &shift, reg 269 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c ret = regmap_read(priv->regmap, reg, &val); reg 287 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int reg, mask, val; reg 297 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4; reg 300 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c ret = regmap_read(priv->regmap, reg, &val); reg 349 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int pupdctrl, reg, shift; reg 410 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pupdctrl / 32 * 4; reg 413 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c return regmap_update_bits(priv->regmap, reg, 1 << shift, val << shift); reg 421 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int reg, shift, mask, val; reg 425 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c ret = uniphier_conf_get_drvctrl_data(pctldev, pin, ®, &shift, reg 450 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c return regmap_update_bits(priv->regmap, reg, reg 460 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int reg, mask; reg 477 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c reg = UNIPHIER_PINCTRL_IECTRL_BASE + iectrl / 32 * 4; reg 480 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c return regmap_update_bits(priv->regmap, reg, mask, enable ? mask : 0); reg 582 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int mux_bits, reg_stride, reg, reg_end, shift, mask; reg 614 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride; reg 615 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c reg_end = reg + reg_stride; reg 623 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c for (; reg < reg_end; reg += 4) { reg 624 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c ret = regmap_update_bits(priv->regmap, reg, reg 26 drivers/pinctrl/vt8500/pinctrl-wmt.c static inline void wmt_setbits(struct wmt_pinctrl_data *data, u32 reg, reg 31 drivers/pinctrl/vt8500/pinctrl-wmt.c val = readl_relaxed(data->base + reg); reg 33 drivers/pinctrl/vt8500/pinctrl-wmt.c writel_relaxed(val, data->base + reg); reg 36 drivers/pinctrl/vt8500/pinctrl-wmt.c static inline void wmt_clearbits(struct wmt_pinctrl_data *data, u32 reg, reg 41 drivers/pinctrl/vt8500/pinctrl-wmt.c val = readl_relaxed(data->base + reg); reg 43 drivers/pinctrl/vt8500/pinctrl-wmt.c writel_relaxed(val, data->base + reg); reg 174 drivers/platform/mellanox/mlxreg-hotplug.c ret = regmap_read(priv->regmap, data->reg, ®val); reg 264 drivers/platform/mellanox/mlxreg-hotplug.c item->reg, item->mask); reg 270 drivers/platform/mellanox/mlxreg-hotplug.c ret = regmap_write(priv->regmap, item->reg + MLXREG_HOTPLUG_MASK_OFF, reg 276 drivers/platform/mellanox/mlxreg-hotplug.c ret = regmap_read(priv->regmap, item->reg, ®val); reg 301 drivers/platform/mellanox/mlxreg-hotplug.c ret = regmap_write(priv->regmap, item->reg + MLXREG_HOTPLUG_EVENT_OFF, reg 307 drivers/platform/mellanox/mlxreg-hotplug.c ret = regmap_write(priv->regmap, item->reg + MLXREG_HOTPLUG_MASK_OFF, reg 325 drivers/platform/mellanox/mlxreg-hotplug.c ret = regmap_write(priv->regmap, data->reg + reg 331 drivers/platform/mellanox/mlxreg-hotplug.c ret = regmap_read(priv->regmap, data->reg, ®val); reg 371 drivers/platform/mellanox/mlxreg-hotplug.c ret = regmap_write(priv->regmap, data->reg + reg 377 drivers/platform/mellanox/mlxreg-hotplug.c ret = regmap_write(priv->regmap, data->reg + reg 508 drivers/platform/mellanox/mlxreg-hotplug.c ret = regmap_write(priv->regmap, item->reg + reg 535 drivers/platform/mellanox/mlxreg-hotplug.c ret = regmap_write(priv->regmap, item->reg + reg 593 drivers/platform/mellanox/mlxreg-hotplug.c regmap_write(priv->regmap, data->reg + MLXREG_HOTPLUG_MASK_OFF, reg 596 drivers/platform/mellanox/mlxreg-hotplug.c regmap_write(priv->regmap, data->reg + reg 50 drivers/platform/mellanox/mlxreg-io.c ret = regmap_read(regmap, data->reg, regval); reg 135 drivers/platform/mellanox/mlxreg-io.c ret = regmap_write(priv->pdata->regmap, data->reg, regval); reg 21 drivers/platform/mips/cpu_hwmon.c u32 reg, prid_rev; reg 23 drivers/platform/mips/cpu_hwmon.c reg = LOONGSON_CHIPTEMP(cpu); reg 27 drivers/platform/mips/cpu_hwmon.c reg = (reg >> 8) & 0xff; reg 33 drivers/platform/mips/cpu_hwmon.c reg = ((reg >> 8) & 0xff) - 100; reg 37 drivers/platform/mips/cpu_hwmon.c reg = (reg & 0xffff)*731/0x4000 - 273; reg 40 drivers/platform/mips/cpu_hwmon.c return (int)reg * 1000; reg 106 drivers/platform/x86/hp_accel.c static int lis3lv02d_acpi_read(struct lis3lv02d *lis3, int reg, u8 *ret) reg 114 drivers/platform/x86/hp_accel.c arg0.integer.value = reg; reg 131 drivers/platform/x86/hp_accel.c static int lis3lv02d_acpi_write(struct lis3lv02d *lis3, int reg, u8 val) reg 139 drivers/platform/x86/hp_accel.c in_obj[0].integer.value = reg; reg 859 drivers/platform/x86/intel_ips.c int reg = cpu ? THM_CTV2 : THM_CTV1; reg 862 drivers/platform/x86/intel_ips.c val = thm_readw(reg); reg 1109 drivers/platform/x86/intel_ips.c #define THM_DUMPW(reg) \ reg 1111 drivers/platform/x86/intel_ips.c u16 val = thm_readw(reg); \ reg 1112 drivers/platform/x86/intel_ips.c dev_dbg(ips->dev, #reg ": 0x%04x\n", val); \ reg 1114 drivers/platform/x86/intel_ips.c #define THM_DUMPL(reg) \ reg 1116 drivers/platform/x86/intel_ips.c u32 val = thm_readl(reg); \ reg 1117 drivers/platform/x86/intel_ips.c dev_dbg(ips->dev, #reg ": 0x%08x\n", val); \ reg 1119 drivers/platform/x86/intel_ips.c #define THM_DUMPQ(reg) \ reg 1121 drivers/platform/x86/intel_ips.c u64 val = thm_readq(reg); \ reg 1122 drivers/platform/x86/intel_ips.c dev_dbg(ips->dev, #reg ": 0x%016x\n", val); \ reg 42 drivers/platform/x86/intel_speed_select_if/isst_if_mmio.c if (io_reg->reg < 0x04 || io_reg->reg > 0xD0) reg 62 drivers/platform/x86/intel_speed_select_if/isst_if_mmio.c writel(io_reg->value, punit_dev->punit_mmio+io_reg->reg); reg 65 drivers/platform/x86/intel_speed_select_if/isst_if_mmio.c io_reg->value = readl(punit_dev->punit_mmio+io_reg->reg); reg 221 drivers/platform/x86/mlx-platform.c .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, reg 229 drivers/platform/x86/mlx-platform.c .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, reg 283 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, reg 290 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, reg 300 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, reg 307 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, reg 317 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, reg 324 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, reg 331 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, reg 338 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, reg 348 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, reg 358 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, reg 367 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, reg 376 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, reg 385 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, reg 406 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, reg 412 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, reg 423 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, reg 432 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, reg 454 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, reg 461 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, reg 471 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, reg 478 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, reg 488 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, reg 494 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, reg 500 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, reg 506 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, reg 516 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, reg 525 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, reg 534 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, reg 543 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, reg 565 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, reg 571 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, reg 581 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, reg 590 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, reg 612 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, reg 619 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, reg 629 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, reg 637 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, reg 645 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, reg 653 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, reg 661 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, reg 669 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, reg 681 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, reg 690 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, reg 699 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, reg 708 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, reg 730 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, reg 735 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, reg 740 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, reg 745 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, reg 750 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, reg 755 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, reg 760 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, reg 765 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, reg 770 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, reg 775 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, reg 780 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, reg 785 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, reg 799 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, reg 804 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, reg 809 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, reg 814 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, reg 819 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, reg 824 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, reg 829 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, reg 834 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, reg 839 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, reg 853 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, reg 858 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, reg 863 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, reg 868 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, reg 873 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, reg 880 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, reg 887 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, reg 894 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, reg 901 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, reg 908 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, reg 915 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, reg 922 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, reg 929 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, reg 936 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, reg 943 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, reg 950 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, reg 957 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, reg 971 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, reg 977 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, reg 983 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 989 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 995 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1001 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1007 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1013 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1019 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1025 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1031 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, reg 1037 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, reg 1043 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, reg 1049 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, reg 1055 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, reg 1061 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, reg 1077 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, reg 1083 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, reg 1089 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1095 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1101 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1107 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1113 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1119 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1125 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1131 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, reg 1137 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, reg 1143 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, reg 1149 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, reg 1155 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, reg 1161 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, reg 1177 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, reg 1183 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, reg 1189 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, reg 1195 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, reg 1201 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1207 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1213 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1219 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1225 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1231 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1237 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1243 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, reg 1249 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, reg 1255 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, reg 1261 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, reg 1267 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, reg 1273 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, reg 1279 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, reg 1285 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, reg 1291 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, reg 1297 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, reg 1303 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, reg 1309 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, reg 1316 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, reg 1331 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, reg 1335 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, reg 1342 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, reg 1349 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, reg 1356 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, reg 1363 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, reg 1370 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, reg 1377 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, reg 1384 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, reg 1391 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, reg 1398 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET, reg 1405 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET, reg 1412 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET, reg 1434 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, reg 1440 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET, reg 1446 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, reg 1452 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1461 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, reg 1467 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, reg 1473 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, reg 1500 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, reg 1506 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, reg 1512 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET, reg 1517 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, reg 1523 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, reg 1532 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, reg 1538 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, reg 1544 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET, reg 1549 drivers/platform/x86/mlx-platform.c .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, reg 1570 drivers/platform/x86/mlx-platform.c static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) reg 1572 drivers/platform/x86/mlx-platform.c switch (reg) { reg 1608 drivers/platform/x86/mlx-platform.c static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) reg 1610 drivers/platform/x86/mlx-platform.c switch (reg) { reg 1679 drivers/platform/x86/mlx-platform.c static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) reg 1681 drivers/platform/x86/mlx-platform.c switch (reg) { reg 1761 drivers/platform/x86/mlx-platform.c mlxplat_mlxcpld_reg_read(void *context, unsigned int reg, unsigned int *val) reg 1765 drivers/platform/x86/mlx-platform.c *val = ioread8(ctx->base + reg); reg 1770 drivers/platform/x86/mlx-platform.c mlxplat_mlxcpld_reg_write(void *context, unsigned int reg, unsigned int val) reg 1774 drivers/platform/x86/mlx-platform.c iowrite8(val, ctx->base + reg); reg 2162 drivers/platform/x86/mlx-platform.c mlxplat_regmap_config->reg_defaults[j].reg, reg 347 drivers/platform/x86/toshiba_acpi.c static u32 hci_write(struct toshiba_acpi_dev *dev, u32 reg, u32 in1) reg 349 drivers/platform/x86/toshiba_acpi.c u32 in[TCI_WORDS] = { HCI_SET, reg, in1, 0, 0, 0 }; reg 356 drivers/platform/x86/toshiba_acpi.c static u32 hci_read(struct toshiba_acpi_dev *dev, u32 reg, u32 *out1) reg 358 drivers/platform/x86/toshiba_acpi.c u32 in[TCI_WORDS] = { HCI_GET, reg, 0, 0, 0, 0 }; reg 430 drivers/platform/x86/toshiba_acpi.c static u32 sci_read(struct toshiba_acpi_dev *dev, u32 reg, u32 *out1) reg 432 drivers/platform/x86/toshiba_acpi.c u32 in[TCI_WORDS] = { SCI_GET, reg, 0, 0, 0, 0 }; reg 444 drivers/platform/x86/toshiba_acpi.c static u32 sci_write(struct toshiba_acpi_dev *dev, u32 reg, u32 in1) reg 446 drivers/platform/x86/toshiba_acpi.c u32 in[TCI_WORDS] = { SCI_SET, reg, in1, 0, 0, 0 }; reg 67 drivers/power/avs/rockchip-io-domain.c struct regulator *reg; reg 156 drivers/power/avs/rockchip-io-domain.c if (!iod->supplies[PX30_IO_VSEL_VCCIO6_SUPPLY_NUM].reg) reg 175 drivers/power/avs/rockchip-io-domain.c if (!iod->supplies[RK3288_SOC_FLASH_SUPPLY_NUM].reg) reg 194 drivers/power/avs/rockchip-io-domain.c if (!iod->supplies[RK3328_SOC_VCCIO2_SUPPLY_NUM].reg) reg 213 drivers/power/avs/rockchip-io-domain.c if (!iod->supplies[RK3368_SOC_FLASH_SUPPLY_NUM].reg) reg 232 drivers/power/avs/rockchip-io-domain.c if (!iod->supplies[RK3399_PMUGRF_VSEL_SUPPLY_NUM].reg) reg 524 drivers/power/avs/rockchip-io-domain.c struct regulator *reg; reg 530 drivers/power/avs/rockchip-io-domain.c reg = devm_regulator_get_optional(iod->dev, supply_name); reg 531 drivers/power/avs/rockchip-io-domain.c if (IS_ERR(reg)) { reg 532 drivers/power/avs/rockchip-io-domain.c ret = PTR_ERR(reg); reg 544 drivers/power/avs/rockchip-io-domain.c uV = regulator_get_voltage(reg); reg 564 drivers/power/avs/rockchip-io-domain.c supply->reg = reg; reg 569 drivers/power/avs/rockchip-io-domain.c supply->reg = NULL; reg 574 drivers/power/avs/rockchip-io-domain.c ret = regulator_register_notifier(reg, &supply->nb); reg 578 drivers/power/avs/rockchip-io-domain.c supply->reg = NULL; reg 592 drivers/power/avs/rockchip-io-domain.c if (io_supply->reg) reg 593 drivers/power/avs/rockchip-io-domain.c regulator_unregister_notifier(io_supply->reg, reg 608 drivers/power/avs/rockchip-io-domain.c if (io_supply->reg) reg 609 drivers/power/avs/rockchip-io-domain.c regulator_unregister_notifier(io_supply->reg, reg 63 drivers/power/reset/at91-poweroff.c u32 reg = readl(at91_shdwc.shdwc_base + AT91_SHDW_SR); reg 66 drivers/power/reset/at91-poweroff.c if (!reg) reg 69 drivers/power/reset/at91-poweroff.c if (reg & AT91_SHDW_RTTWK) reg 71 drivers/power/reset/at91-poweroff.c else if (reg & AT91_SHDW_RTCWK) reg 152 drivers/power/reset/at91-reset.c u32 reg = readl(at91_rstc_base + AT91_RSTC_SR); reg 154 drivers/power/reset/at91-reset.c switch ((reg & AT91_RSTC_RSTTYP) >> 8) { reg 58 drivers/power/reset/at91-sama5d2_shdwc.c #define SHDW_WK_PIN(reg, cfg) ((reg) & AT91_SHDW_WKUPIS((cfg)->wkup_pin_input)) reg 59 drivers/power/reset/at91-sama5d2_shdwc.c #define SHDW_RTCWK(reg, cfg) (((reg) >> ((cfg)->sr_rtcwk_shift)) & 0x1) reg 60 drivers/power/reset/at91-sama5d2_shdwc.c #define SHDW_RTTWK(reg, cfg) (((reg) >> ((cfg)->sr_rttwk_shift)) & 0x1) reg 98 drivers/power/reset/at91-sama5d2_shdwc.c u32 reg; reg 101 drivers/power/reset/at91-sama5d2_shdwc.c reg = readl(shdw->shdwc_base + AT91_SHDW_SR); reg 103 drivers/power/reset/at91-sama5d2_shdwc.c dev_dbg(&pdev->dev, "%s: status = %#x\n", __func__, reg); reg 106 drivers/power/reset/at91-sama5d2_shdwc.c if (!reg) reg 109 drivers/power/reset/at91-sama5d2_shdwc.c if (SHDW_WK_PIN(reg, shdw->cfg)) reg 111 drivers/power/reset/at91-sama5d2_shdwc.c else if (SHDW_RTCWK(reg, shdw->cfg)) reg 113 drivers/power/reset/at91-sama5d2_shdwc.c else if (SHDW_RTTWK(reg, shdw->cfg)) reg 19 drivers/power/reset/vexpress-poweroff.c struct regmap *reg = dev_get_drvdata(dev); reg 21 drivers/power/reset/vexpress-poweroff.c if (reg) { reg 22 drivers/power/reset/vexpress-poweroff.c err = regmap_write(reg, 0, 0); reg 346 drivers/power/supply/ab8500_charger.c u8 reg; reg 355 drivers/power/supply/ab8500_charger.c reg = 0x0; reg 359 drivers/power/supply/ab8500_charger.c reg = AB8500_SW_CONTROL_FALLBACK; reg 364 drivers/power/supply/ab8500_charger.c ret = abx500_get_register_interruptible(di->dev, bank, reg, &val); reg 385 drivers/power/supply/ab8500_charger.c ret = abx500_set_register_interruptible(di->dev, bank, reg, val); reg 1091 drivers/power/supply/ab8500_charger.c int reg) reg 1093 drivers/power/supply/ab8500_charger.c if (reg == AB8500_USBCH_IPT_CRNTLVL_REG) reg 1113 drivers/power/supply/ab8500_charger.c int ich, int reg) reg 1124 drivers/power/supply/ab8500_charger.c reg, ®_value); reg 1130 drivers/power/supply/ab8500_charger.c switch (reg) { reg 1175 drivers/power/supply/ab8500_charger.c __func__, reg); reg 1181 drivers/power/supply/ab8500_charger.c __func__, ich, reg); reg 1185 drivers/power/supply/ab8500_charger.c reg, (u8)curr_index << shift_value); reg 1191 drivers/power/supply/ab8500_charger.c (u8) i << shift_value, reg); reg 1193 drivers/power/supply/ab8500_charger.c AB8500_CHARGER, reg, (u8)i << shift_value); reg 1205 drivers/power/supply/ab8500_charger.c (u8)i << shift_value, reg); reg 1207 drivers/power/supply/ab8500_charger.c AB8500_CHARGER, reg, (u8)i << shift_value); reg 1215 drivers/power/supply/ab8500_charger.c allow = ab8500_charger_check_continue_stepping(di, reg); reg 62 drivers/power/supply/axp20x_ac_power.c int ret, reg; reg 66 drivers/power/supply/axp20x_ac_power.c ret = regmap_read(power->regmap, AXP20X_PWR_INPUT_STATUS, ®); reg 70 drivers/power/supply/axp20x_ac_power.c if (reg & AXP20X_PWR_STATUS_ACIN_PRESENT) { reg 79 drivers/power/supply/axp20x_ac_power.c ret = regmap_read(power->regmap, AXP20X_PWR_INPUT_STATUS, ®); reg 83 drivers/power/supply/axp20x_ac_power.c val->intval = !!(reg & AXP20X_PWR_STATUS_ACIN_PRESENT); reg 87 drivers/power/supply/axp20x_ac_power.c ret = regmap_read(power->regmap, AXP20X_PWR_INPUT_STATUS, ®); reg 91 drivers/power/supply/axp20x_ac_power.c val->intval = !!(reg & AXP20X_PWR_STATUS_ACIN_AVAIL); reg 96 drivers/power/supply/axp20x_ac_power.c ®); reg 100 drivers/power/supply/axp20x_ac_power.c val->intval = !!(reg & AXP813_ACIN_PATH_SEL); reg 126 drivers/power/supply/axp20x_ac_power.c ret = regmap_read(power->regmap, AXP813_ACIN_PATH_CTRL, ®); reg 130 drivers/power/supply/axp20x_ac_power.c val->intval = AXP813_VHOLD_REG_TO_UV(reg); reg 135 drivers/power/supply/axp20x_ac_power.c ret = regmap_read(power->regmap, AXP813_ACIN_PATH_CTRL, ®); reg 139 drivers/power/supply/axp20x_ac_power.c val->intval = AXP813_CURR_LIMIT_REG_TO_UA(reg); reg 83 drivers/power/supply/axp20x_battery.c int ret, reg; reg 85 drivers/power/supply/axp20x_battery.c ret = regmap_read(axp20x_batt->regmap, AXP20X_CHRG_CTRL1, ®); reg 89 drivers/power/supply/axp20x_battery.c switch (reg & AXP20X_CHRG_CTRL1_TGT_VOLT) { reg 112 drivers/power/supply/axp20x_battery.c int ret, reg; reg 114 drivers/power/supply/axp20x_battery.c ret = regmap_read(axp20x_batt->regmap, AXP20X_CHRG_CTRL1, ®); reg 118 drivers/power/supply/axp20x_battery.c switch (reg & AXP20X_CHRG_CTRL1_TGT_VOLT) { reg 141 drivers/power/supply/axp20x_battery.c int ret, reg; reg 143 drivers/power/supply/axp20x_battery.c ret = regmap_read(axp20x_batt->regmap, AXP20X_CHRG_CTRL1, ®); reg 147 drivers/power/supply/axp20x_battery.c switch (reg & AXP20X_CHRG_CTRL1_TGT_VOLT) { reg 189 drivers/power/supply/axp20x_battery.c int ret = 0, reg, val1; reg 195 drivers/power/supply/axp20x_battery.c ®); reg 199 drivers/power/supply/axp20x_battery.c val->intval = !!(reg & AXP20X_PWR_OP_BATT_PRESENT); reg 204 drivers/power/supply/axp20x_battery.c ®); reg 208 drivers/power/supply/axp20x_battery.c if (reg & AXP20X_PWR_STATUS_BAT_CHARGING) { reg 264 drivers/power/supply/axp20x_battery.c ®); reg 268 drivers/power/supply/axp20x_battery.c if (reg & AXP20X_PWR_STATUS_BAT_CHARGING) reg 284 drivers/power/supply/axp20x_battery.c ®); reg 288 drivers/power/supply/axp20x_battery.c if (!(reg & AXP20X_PWR_OP_BATT_PRESENT)) { reg 293 drivers/power/supply/axp20x_battery.c ret = regmap_read(axp20x_batt->regmap, AXP20X_FG_RES, ®); reg 297 drivers/power/supply/axp20x_battery.c if (axp20x_batt->data->has_fg_valid && !(reg & AXP22X_FG_VALID)) reg 304 drivers/power/supply/axp20x_battery.c val->intval = reg & AXP209_FG_PERCENT; reg 312 drivers/power/supply/axp20x_battery.c ret = regmap_read(axp20x_batt->regmap, AXP20X_V_OFF, ®); reg 316 drivers/power/supply/axp20x_battery.c val->intval = 2600000 + 100000 * (reg & AXP20X_V_OFF_MASK); reg 138 drivers/power/supply/axp288_fuel_gauge.c static int fuel_gauge_reg_readb(struct axp288_fg_info *info, int reg) reg 144 drivers/power/supply/axp288_fuel_gauge.c ret = regmap_read(info->regmap, reg, &val); reg 159 drivers/power/supply/axp288_fuel_gauge.c static int fuel_gauge_reg_writeb(struct axp288_fg_info *info, int reg, u8 val) reg 163 drivers/power/supply/axp288_fuel_gauge.c ret = regmap_write(info->regmap, reg, (unsigned int)val); reg 171 drivers/power/supply/axp288_fuel_gauge.c static int fuel_gauge_read_15bit_word(struct axp288_fg_info *info, int reg) reg 176 drivers/power/supply/axp288_fuel_gauge.c ret = regmap_bulk_read(info->regmap, reg, buf, 2); reg 179 drivers/power/supply/axp288_fuel_gauge.c reg, ret); reg 186 drivers/power/supply/axp288_fuel_gauge.c reg); reg 193 drivers/power/supply/axp288_fuel_gauge.c static int fuel_gauge_read_12bit_word(struct axp288_fg_info *info, int reg) reg 198 drivers/power/supply/axp288_fuel_gauge.c ret = regmap_bulk_read(info->regmap, reg, buf, 2); reg 201 drivers/power/supply/axp288_fuel_gauge.c reg, ret); reg 571 drivers/power/supply/bd70528-charger.c unsigned int reg; reg 579 drivers/power/supply/bd70528-charger.c reg = MAX_WARM_CHG_CURR_SEL; reg 586 drivers/power/supply/bd70528-charger.c reg = MIN_CHG_CURR_SEL; reg 593 drivers/power/supply/bd70528-charger.c ®, &found); reg 595 drivers/power/supply/bd70528-charger.c reg = MIN_CHG_CURR_SEL; reg 607 drivers/power/supply/bd70528-charger.c BD70528_MASK_CHG_CHG_CURR, reg); reg 612 drivers/power/supply/bd70528-charger.c if (reg > MAX_COLD_CHG_CURR_SEL) reg 613 drivers/power/supply/bd70528-charger.c reg = MAX_COLD_CHG_CURR_SEL; reg 618 drivers/power/supply/bd70528-charger.c BD70528_MASK_CHG_CHG_CURR, reg); reg 631 drivers/power/supply/bd70528-charger.c unsigned int reg; reg 639 drivers/power/supply/bd70528-charger.c reg = MAX_CURR_LIMIT_SEL; reg 646 drivers/power/supply/bd70528-charger.c reg = MIN_CURR_LIMIT_SEL; reg 653 drivers/power/supply/bd70528-charger.c ®, &found); reg 655 drivers/power/supply/bd70528-charger.c reg = MIN_CURR_LIMIT_SEL; reg 667 drivers/power/supply/bd70528-charger.c BD70528_MASK_CHG_DCIN_ILIM, reg); reg 187 drivers/power/supply/bq2415x_charger.c static int bq2415x_i2c_read(struct bq2415x_device *bq, u8 reg) reg 199 drivers/power/supply/bq2415x_charger.c msg[0].buf = ® reg 200 drivers/power/supply/bq2415x_charger.c msg[0].len = sizeof(reg); reg 217 drivers/power/supply/bq2415x_charger.c static int bq2415x_i2c_read_mask(struct bq2415x_device *bq, u8 reg, reg 225 drivers/power/supply/bq2415x_charger.c ret = bq2415x_i2c_read(bq, reg); reg 232 drivers/power/supply/bq2415x_charger.c static int bq2415x_i2c_read_bit(struct bq2415x_device *bq, u8 reg, u8 bit) reg 236 drivers/power/supply/bq2415x_charger.c return bq2415x_i2c_read_mask(bq, reg, BIT(bit), bit); reg 242 drivers/power/supply/bq2415x_charger.c static int bq2415x_i2c_write(struct bq2415x_device *bq, u8 reg, u8 val) reg 249 drivers/power/supply/bq2415x_charger.c data[0] = reg; reg 271 drivers/power/supply/bq2415x_charger.c static int bq2415x_i2c_write_mask(struct bq2415x_device *bq, u8 reg, u8 val, reg 279 drivers/power/supply/bq2415x_charger.c ret = bq2415x_i2c_read(bq, reg); reg 286 drivers/power/supply/bq2415x_charger.c return bq2415x_i2c_write(bq, reg, ret); reg 290 drivers/power/supply/bq2415x_charger.c static int bq2415x_i2c_write_bit(struct bq2415x_device *bq, u8 reg, reg 295 drivers/power/supply/bq2415x_charger.c return bq2415x_i2c_write_mask(bq, reg, val, BIT(bit), bit); reg 1241 drivers/power/supply/bq2415x_charger.c unsigned int reg; reg 1244 drivers/power/supply/bq2415x_charger.c if (sscanf(buf, "%x %x", ®, &val) != 2) reg 1247 drivers/power/supply/bq2415x_charger.c if (reg > 4 || val > 255) reg 1250 drivers/power/supply/bq2415x_charger.c ret = bq2415x_i2c_write(bq, reg, val); reg 1258 drivers/power/supply/bq2415x_charger.c u8 reg, reg 1261 drivers/power/supply/bq2415x_charger.c int ret = bq2415x_i2c_read(bq, reg); reg 1264 drivers/power/supply/bq2415x_charger.c return sprintf(buf, "%#.2x=error %d\n", reg, ret); reg 1265 drivers/power/supply/bq2415x_charger.c return sprintf(buf, "%#.2x=%#.2x\n", reg, ret); reg 242 drivers/power/supply/bq24190_charger.c static int bq24190_read(struct bq24190_dev_info *bdi, u8 reg, u8 *data) reg 246 drivers/power/supply/bq24190_charger.c ret = i2c_smbus_read_byte_data(bdi->client, reg); reg 254 drivers/power/supply/bq24190_charger.c static int bq24190_write(struct bq24190_dev_info *bdi, u8 reg, u8 data) reg 256 drivers/power/supply/bq24190_charger.c return i2c_smbus_write_byte_data(bdi->client, reg, data); reg 259 drivers/power/supply/bq24190_charger.c static int bq24190_read_mask(struct bq24190_dev_info *bdi, u8 reg, reg 265 drivers/power/supply/bq24190_charger.c ret = bq24190_read(bdi, reg, &v); reg 276 drivers/power/supply/bq24190_charger.c static int bq24190_write_mask(struct bq24190_dev_info *bdi, u8 reg, reg 282 drivers/power/supply/bq24190_charger.c ret = bq24190_read(bdi, reg, &v); reg 289 drivers/power/supply/bq24190_charger.c return bq24190_write(bdi, reg, v); reg 293 drivers/power/supply/bq24190_charger.c u8 reg, u8 mask, u8 shift, reg 300 drivers/power/supply/bq24190_charger.c ret = bq24190_read_mask(bdi, reg, mask, shift, &v); reg 311 drivers/power/supply/bq24190_charger.c u8 reg, u8 mask, u8 shift, reg 319 drivers/power/supply/bq24190_charger.c return bq24190_write_mask(bdi, reg, mask, shift, idx); reg 334 drivers/power/supply/bq24190_charger.c .reg = BQ24190_REG_##r, \ reg 353 drivers/power/supply/bq24190_charger.c u8 reg; reg 454 drivers/power/supply/bq24190_charger.c ret = bq24190_read_mask(bdi, info->reg, info->mask, info->shift, &v); reg 487 drivers/power/supply/bq24190_charger.c ret = bq24190_write_mask(bdi, info->reg, info->mask, info->shift, v); reg 580 drivers/power/supply/bq24190_charger.c struct regulator_dev *reg; reg 589 drivers/power/supply/bq24190_charger.c reg = devm_regulator_register(bdi->dev, &bq24190_vbus_desc, &cfg); reg 590 drivers/power/supply/bq24190_charger.c if (IS_ERR(reg)) { reg 591 drivers/power/supply/bq24190_charger.c ret = PTR_ERR(reg); reg 104 drivers/power/supply/bq24257_charger.c static bool bq24257_is_volatile_reg(struct device *dev, unsigned int reg) reg 106 drivers/power/supply/bq24257_charger.c switch (reg) { reg 81 drivers/power/supply/bq24735-charger.c static inline int bq24735_write_word(struct i2c_client *client, u8 reg, reg 84 drivers/power/supply/bq24735-charger.c return i2c_smbus_write_word_data(client, reg, value); reg 87 drivers/power/supply/bq24735-charger.c static inline int bq24735_read_word(struct i2c_client *client, u8 reg) reg 89 drivers/power/supply/bq24735-charger.c return i2c_smbus_read_word_data(client, reg); reg 92 drivers/power/supply/bq24735-charger.c static int bq24735_update_word(struct i2c_client *client, u8 reg, reg 98 drivers/power/supply/bq24735-charger.c ret = bq24735_read_word(client, reg); reg 105 drivers/power/supply/bq24735-charger.c return bq24735_write_word(client, reg, tmp); reg 851 drivers/power/supply/bq27xxx_battery.c struct bq27xxx_dm_reg *reg) reg 853 drivers/power/supply/bq27xxx_battery.c if (buf->class == reg->subclass_id && reg 854 drivers/power/supply/bq27xxx_battery.c buf->block == reg->offset / BQ27XXX_DM_SZ) reg 855 drivers/power/supply/bq27xxx_battery.c return (u16 *) (buf->data + reg->offset % BQ27XXX_DM_SZ); reg 1079 drivers/power/supply/bq27xxx_battery.c struct bq27xxx_dm_reg *reg = &di->dm_regs[reg_id]; reg 1081 drivers/power/supply/bq27xxx_battery.c u16 *prev = bq27xxx_dm_reg_ptr(buf, reg); reg 1088 drivers/power/supply/bq27xxx_battery.c if (reg->bytes != 2) { reg 1353 drivers/power/supply/bq27xxx_battery.c static int bq27xxx_battery_read_charge(struct bq27xxx_device_info *di, u8 reg) reg 1357 drivers/power/supply/bq27xxx_battery.c charge = bq27xxx_read(di, reg, false); reg 1360 drivers/power/supply/bq27xxx_battery.c reg, charge); reg 1485 drivers/power/supply/bq27xxx_battery.c static int bq27xxx_battery_read_time(struct bq27xxx_device_info *di, u8 reg) reg 1489 drivers/power/supply/bq27xxx_battery.c tval = bq27xxx_read(di, reg, false); reg 1492 drivers/power/supply/bq27xxx_battery.c reg, tval); reg 35 drivers/power/supply/bq27xxx_battery_hdq.c static int w1_bq27000_read(struct w1_slave *sl, unsigned int reg) reg 40 drivers/power/supply/bq27xxx_battery_hdq.c w1_write_8(sl->master, HDQ_CMD_READ | reg); reg 47 drivers/power/supply/bq27xxx_battery_hdq.c static int bq27xxx_battery_hdq_read(struct bq27xxx_device_info *di, u8 reg, reg 60 drivers/power/supply/bq27xxx_battery_hdq.c upper = w1_bq27000_read(sl, reg + 1); reg 66 drivers/power/supply/bq27xxx_battery_hdq.c lower = w1_bq27000_read(sl, reg); reg 70 drivers/power/supply/bq27xxx_battery_hdq.c upper = w1_bq27000_read(sl, reg + 1); reg 79 drivers/power/supply/bq27xxx_battery_hdq.c return w1_bq27000_read(sl, reg); reg 36 drivers/power/supply/bq27xxx_battery_i2c.c static int bq27xxx_battery_i2c_read(struct bq27xxx_device_info *di, u8 reg, reg 49 drivers/power/supply/bq27xxx_battery_i2c.c msg[0].buf = ® reg 50 drivers/power/supply/bq27xxx_battery_i2c.c msg[0].len = sizeof(reg); reg 71 drivers/power/supply/bq27xxx_battery_i2c.c static int bq27xxx_battery_i2c_write(struct bq27xxx_device_info *di, u8 reg, reg 82 drivers/power/supply/bq27xxx_battery_i2c.c data[0] = reg; reg 103 drivers/power/supply/bq27xxx_battery_i2c.c static int bq27xxx_battery_i2c_bulk_read(struct bq27xxx_device_info *di, u8 reg, reg 112 drivers/power/supply/bq27xxx_battery_i2c.c ret = i2c_smbus_read_i2c_block_data(client, reg, len, data); reg 121 drivers/power/supply/bq27xxx_battery_i2c.c u8 reg, u8 *data, int len) reg 131 drivers/power/supply/bq27xxx_battery_i2c.c buf[0] = reg; reg 107 drivers/power/supply/cpcap-battery.c struct regmap *reg; reg 304 drivers/power/supply/cpcap-battery.c error = regmap_bulk_read(ddata->reg, CPCAP_REG_CCS1, reg 346 drivers/power/supply/cpcap-battery.c error = regmap_read(ddata->reg, CPCAP_REG_CCI, &value); reg 356 drivers/power/supply/cpcap-battery.c error = regmap_read(ddata->reg, CPCAP_REG_CCM, &value); reg 641 drivers/power/supply/cpcap-battery.c error = regmap_update_bits(ddata->reg, CPCAP_REG_BPEOL, reg 738 drivers/power/supply/cpcap-battery.c ddata->reg = dev_get_regmap(ddata->dev->parent, NULL); reg 739 drivers/power/supply/cpcap-battery.c if (!ddata->reg) reg 742 drivers/power/supply/cpcap-battery.c error = cpcap_get_vendor(ddata->dev, ddata->reg, &ddata->vendor); reg 748 drivers/power/supply/cpcap-battery.c error = regmap_update_bits(ddata->reg, CPCAP_REG_CCM, reg 793 drivers/power/supply/cpcap-battery.c error = regmap_update_bits(ddata->reg, CPCAP_REG_BPEOL, reg 125 drivers/power/supply/cpcap-charger.c struct regmap *reg; reg 280 drivers/power/supply/cpcap-charger.c error = regmap_update_bits(ddata->reg, CPCAP_REG_CRM, reg 294 drivers/power/supply/cpcap-charger.c error = regmap_update_bits(ddata->reg, CPCAP_REG_CRM, 0x3fff, reg 357 drivers/power/supply/cpcap-charger.c error = regmap_update_bits(ddata->reg, CPCAP_REG_VUSBC, reg 363 drivers/power/supply/cpcap-charger.c error = regmap_update_bits(ddata->reg, CPCAP_REG_CRM, reg 369 drivers/power/supply/cpcap-charger.c error = regmap_update_bits(ddata->reg, CPCAP_REG_VUSBC, reg 374 drivers/power/supply/cpcap-charger.c error = regmap_update_bits(ddata->reg, CPCAP_REG_CRM, reg 411 drivers/power/supply/cpcap-charger.c error = regmap_read(ddata->reg, CPCAP_REG_INTS1, &val); reg 419 drivers/power/supply/cpcap-charger.c error = regmap_read(ddata->reg, CPCAP_REG_INTS2, &val); reg 428 drivers/power/supply/cpcap-charger.c error = regmap_read(ddata->reg, CPCAP_REG_INTS4, &val); reg 629 drivers/power/supply/cpcap-charger.c ddata->reg = dev_get_regmap(ddata->dev->parent, NULL); reg 630 drivers/power/supply/cpcap-charger.c if (!ddata->reg) reg 121 drivers/power/supply/da9030_battery.c static inline int da9030_reg_to_mV(int reg) reg 123 drivers/power/supply/da9030_battery.c return ((reg * 2650) >> 8) + 2650; reg 131 drivers/power/supply/da9030_battery.c static inline int da9030_reg_to_mA(int reg) reg 133 drivers/power/supply/da9030_battery.c return ((reg * 24000) >> 8) / 15; reg 141 drivers/power/supply/da9150-charger.c u8 reg; reg 144 drivers/power/supply/da9150-charger.c reg = da9150_reg_read(charger->da9150, DA9150_STATUS_H); reg 146 drivers/power/supply/da9150-charger.c if (((reg & DA9150_VBUS_STAT_MASK) == DA9150_VBUS_STAT_OFF) || reg 147 drivers/power/supply/da9150-charger.c ((reg & DA9150_VBUS_STAT_MASK) == DA9150_VBUS_STAT_WAIT)) { reg 153 drivers/power/supply/da9150-charger.c reg = da9150_reg_read(charger->da9150, DA9150_STATUS_J); reg 156 drivers/power/supply/da9150-charger.c switch (reg & DA9150_CHG_STAT_MASK) { reg 184 drivers/power/supply/da9150-charger.c u8 reg; reg 186 drivers/power/supply/da9150-charger.c reg = da9150_reg_read(charger->da9150, DA9150_STATUS_J); reg 189 drivers/power/supply/da9150-charger.c switch (reg & DA9150_CHG_TEMP_MASK) { reg 201 drivers/power/supply/da9150-charger.c switch (reg & DA9150_CHG_STAT_MASK) { reg 220 drivers/power/supply/da9150-charger.c u8 reg; reg 223 drivers/power/supply/da9150-charger.c reg = da9150_reg_read(charger->da9150, DA9150_STATUS_J); reg 224 drivers/power/supply/da9150-charger.c if ((reg & DA9150_CHG_STAT_MASK) == DA9150_CHG_STAT_BAT) reg 235 drivers/power/supply/da9150-charger.c u8 reg; reg 237 drivers/power/supply/da9150-charger.c reg = da9150_reg_read(charger->da9150, DA9150_STATUS_J); reg 239 drivers/power/supply/da9150-charger.c switch (reg & DA9150_CHG_STAT_MASK) { reg 259 drivers/power/supply/da9150-charger.c u8 reg; reg 261 drivers/power/supply/da9150-charger.c reg = da9150_reg_read(charger->da9150, DA9150_PPR_CHGCTRL_C); reg 264 drivers/power/supply/da9150-charger.c val->intval = ((reg & DA9150_CHG_VFAULT_MASK) * 50000) + 2500000; reg 287 drivers/power/supply/da9150-charger.c int reg; reg 289 drivers/power/supply/da9150-charger.c reg = da9150_reg_read(charger->da9150, DA9150_PPR_CHGCTRL_D); reg 292 drivers/power/supply/da9150-charger.c val->intval = reg * 25000; reg 300 drivers/power/supply/da9150-charger.c u8 reg; reg 302 drivers/power/supply/da9150-charger.c reg = da9150_reg_read(charger->da9150, DA9150_PPR_CHGCTRL_B); reg 305 drivers/power/supply/da9150-charger.c val->intval = ((reg & DA9150_CHG_VBAT_MASK) * 25000) + 3650000; reg 399 drivers/power/supply/da9150-charger.c u8 reg; reg 401 drivers/power/supply/da9150-charger.c reg = da9150_reg_read(charger->da9150, DA9150_STATUS_H); reg 404 drivers/power/supply/da9150-charger.c switch (reg & DA9150_VBUS_STAT_MASK) { reg 414 drivers/power/supply/da9150-charger.c reg); reg 519 drivers/power/supply/da9150-charger.c u8 reg; reg 569 drivers/power/supply/da9150-charger.c reg = da9150_reg_read(da9150, DA9150_STATUS_H); reg 571 drivers/power/supply/da9150-charger.c switch (reg & DA9150_VBUS_STAT_MASK) { reg 580 drivers/power/supply/da9150-charger.c dev_warn(dev, "Unknown VBUS state - reg = 0x%x\n", reg); reg 104 drivers/power/supply/ds2780_battery.c static int ds2780_save_eeprom(struct ds2780_device_info *dev_info, int reg) reg 108 drivers/power/supply/ds2780_battery.c ret = ds2780_store_eeprom(dev_info->w1_dev, reg); reg 112 drivers/power/supply/ds2780_battery.c ret = ds2780_recall_eeprom(dev_info->w1_dev, reg); reg 108 drivers/power/supply/ds2781_battery.c static int ds2781_save_eeprom(struct ds2781_device_info *dev_info, int reg) reg 112 drivers/power/supply/ds2781_battery.c ret = ds2781_store_eeprom(dev_info->w1_dev, reg); reg 116 drivers/power/supply/ds2781_battery.c ret = ds2781_recall_eeprom(dev_info->w1_dev, reg); reg 69 drivers/power/supply/ds2782_battery.c static inline int ds278x_read_reg(struct ds278x_info *info, int reg, u8 *val) reg 73 drivers/power/supply/ds2782_battery.c ret = i2c_smbus_read_byte_data(info->client, reg); reg 61 drivers/power/supply/isp1704_charger.c static inline int isp1704_read(struct isp1704_charger *isp, u32 reg) reg 63 drivers/power/supply/isp1704_charger.c return usb_phy_io_read(isp->phy, reg); reg 66 drivers/power/supply/isp1704_charger.c static inline int isp1704_write(struct isp1704_charger *isp, u32 reg, u32 val) reg 68 drivers/power/supply/isp1704_charger.c return usb_phy_io_write(isp->phy, val, reg); reg 85 drivers/power/supply/isp1704_charger.c u8 reg; reg 94 drivers/power/supply/isp1704_charger.c reg = ULPI_OTG_CTRL_DM_PULLDOWN | ULPI_OTG_CTRL_DP_PULLDOWN; reg 95 drivers/power/supply/isp1704_charger.c isp1704_write(isp, ULPI_CLR(ULPI_OTG_CTRL), reg); reg 104 drivers/power/supply/isp1704_charger.c reg = ULPI_FUNC_CTRL_TERMSELECT | ULPI_FUNC_CTRL_RESET; reg 105 drivers/power/supply/isp1704_charger.c isp1704_write(isp, ULPI_SET(ULPI_FUNC_CTRL), reg); reg 108 drivers/power/supply/isp1704_charger.c reg = isp1704_read(isp, ULPI_DEBUG); reg 109 drivers/power/supply/isp1704_charger.c if ((reg & 3) != 3) reg 101 drivers/power/supply/lp8727_charger.c static int lp8727_read_bytes(struct lp8727_chg *pchg, u8 reg, u8 *data, u8 len) reg 106 drivers/power/supply/lp8727_charger.c ret = i2c_smbus_read_i2c_block_data(pchg->client, reg, len, data); reg 112 drivers/power/supply/lp8727_charger.c static inline int lp8727_read_byte(struct lp8727_chg *pchg, u8 reg, u8 *data) reg 114 drivers/power/supply/lp8727_charger.c return lp8727_read_bytes(pchg, reg, data, 1); reg 117 drivers/power/supply/lp8727_charger.c static int lp8727_write_byte(struct lp8727_chg *pchg, u8 reg, u8 data) reg 122 drivers/power/supply/lp8727_charger.c ret = i2c_smbus_write_byte_data(pchg->client, reg, data); reg 97 drivers/power/supply/ltc2941-battery-gauge.c enum ltc294x_reg reg, u8 *buf, int num_regs) reg 101 drivers/power/supply/ltc2941-battery-gauge.c u8 reg_start = reg; reg 119 drivers/power/supply/ltc2941-battery-gauge.c __func__, reg, num_regs, *buf); reg 125 drivers/power/supply/ltc2941-battery-gauge.c enum ltc294x_reg reg, const u8 *buf, int num_regs) reg 128 drivers/power/supply/ltc2941-battery-gauge.c u8 reg_start = reg; reg 137 drivers/power/supply/ltc2941-battery-gauge.c __func__, reg, num_regs, *buf); reg 188 drivers/power/supply/ltc2941-battery-gauge.c enum ltc294x_reg reg) reg 193 drivers/power/supply/ltc2941-battery-gauge.c ret = ltc294x_read_regs(info->client, reg, &datar[0], 2); reg 200 drivers/power/supply/ltc2941-battery-gauge.c enum ltc294x_reg reg, int *val) reg 202 drivers/power/supply/ltc2941-battery-gauge.c int value = ltc294x_read_charge_register(info, reg); reg 255 drivers/power/supply/ltc2941-battery-gauge.c enum ltc294x_reg reg, int val) reg 270 drivers/power/supply/ltc2941-battery-gauge.c return ltc294x_write_regs(info->client, reg, &dataw[0], 2); reg 338 drivers/power/supply/ltc2941-battery-gauge.c enum ltc294x_reg reg; reg 344 drivers/power/supply/ltc2941-battery-gauge.c reg = LTC2942_REG_TEMPERATURE_MSB; reg 347 drivers/power/supply/ltc2941-battery-gauge.c reg = LTC2943_REG_TEMPERATURE_MSB; reg 350 drivers/power/supply/ltc2941-battery-gauge.c ret = ltc294x_read_regs(info->client, reg, &datar[0], 2); reg 90 drivers/power/supply/max14656_charger_detector.c static int max14656_read_reg(struct i2c_client *client, int reg, u8 *val) reg 94 drivers/power/supply/max14656_charger_detector.c ret = i2c_smbus_read_byte_data(client, reg); reg 98 drivers/power/supply/max14656_charger_detector.c reg, ret); reg 105 drivers/power/supply/max14656_charger_detector.c static int max14656_write_reg(struct i2c_client *client, int reg, u8 val) reg 109 drivers/power/supply/max14656_charger_detector.c ret = i2c_smbus_write_byte_data(client, reg, val); reg 113 drivers/power/supply/max14656_charger_detector.c val, reg, ret); reg 119 drivers/power/supply/max14656_charger_detector.c static int max14656_read_block_reg(struct i2c_client *client, u8 reg, reg 124 drivers/power/supply/max14656_charger_detector.c ret = i2c_smbus_read_i2c_block_data(client, reg, length, val); reg 127 drivers/power/supply/max14656_charger_detector.c reg, ret); reg 72 drivers/power/supply/max17040_battery.c static int max17040_write_reg(struct i2c_client *client, int reg, u16 value) reg 76 drivers/power/supply/max17040_battery.c ret = i2c_smbus_write_word_swapped(client, reg, value); reg 84 drivers/power/supply/max17040_battery.c static int max17040_read_reg(struct i2c_client *client, int reg) reg 88 drivers/power/supply/max17040_battery.c ret = i2c_smbus_read_word_swapped(client, reg); reg 486 drivers/power/supply/max17042_battery.c static int max17042_write_verify_reg(struct regmap *map, u8 reg, u32 value) reg 493 drivers/power/supply/max17042_battery.c ret = regmap_write(map, reg, value); reg 494 drivers/power/supply/max17042_battery.c regmap_read(map, reg, &read_value); reg 508 drivers/power/supply/max17042_battery.c u8 reg, u16 value) reg 511 drivers/power/supply/max17042_battery.c regmap_write(map, reg, value); reg 73 drivers/power/supply/max1721x_battery.c static inline int max172xx_time_to_ps(unsigned int reg) reg 75 drivers/power/supply/max1721x_battery.c return reg * 5625 / 1000; /* in sec. */ reg 78 drivers/power/supply/max1721x_battery.c static inline int max172xx_percent_to_ps(unsigned int reg) reg 80 drivers/power/supply/max1721x_battery.c return reg / 256; /* in percent from 0 to 100 */ reg 83 drivers/power/supply/max1721x_battery.c static inline int max172xx_voltage_to_ps(unsigned int reg) reg 85 drivers/power/supply/max1721x_battery.c return reg * 1250; /* in uV */ reg 88 drivers/power/supply/max1721x_battery.c static inline int max172xx_capacity_to_ps(unsigned int reg) reg 90 drivers/power/supply/max1721x_battery.c return reg * 500; /* in uAh */ reg 98 drivers/power/supply/max1721x_battery.c static inline int max172xx_temperature_to_ps(unsigned int reg) reg 100 drivers/power/supply/max1721x_battery.c int val = (int16_t)(reg); reg 113 drivers/power/supply/max1721x_battery.c static inline int max172xx_current_to_voltage(unsigned int reg) reg 115 drivers/power/supply/max1721x_battery.c int val = (int16_t)(reg); reg 132 drivers/power/supply/max1721x_battery.c unsigned int reg = 0; reg 144 drivers/power/supply/max1721x_battery.c ®) ? 0 : !(reg & MAX172XX_BAT_PRESENT); reg 147 drivers/power/supply/max1721x_battery.c ret = regmap_read(info->regmap, MAX172XX_REG_REPSOC, ®); reg 148 drivers/power/supply/max1721x_battery.c val->intval = max172xx_percent_to_ps(reg); reg 151 drivers/power/supply/max1721x_battery.c ret = regmap_read(info->regmap, MAX172XX_REG_BATT, ®); reg 152 drivers/power/supply/max1721x_battery.c val->intval = max172xx_voltage_to_ps(reg); reg 155 drivers/power/supply/max1721x_battery.c ret = regmap_read(info->regmap, MAX172XX_REG_DESIGNCAP, ®); reg 156 drivers/power/supply/max1721x_battery.c val->intval = max172xx_capacity_to_ps(reg); reg 159 drivers/power/supply/max1721x_battery.c ret = regmap_read(info->regmap, MAX172XX_REG_REPCAP, ®); reg 160 drivers/power/supply/max1721x_battery.c val->intval = max172xx_capacity_to_ps(reg); reg 163 drivers/power/supply/max1721x_battery.c ret = regmap_read(info->regmap, MAX172XX_REG_TTE, ®); reg 164 drivers/power/supply/max1721x_battery.c val->intval = max172xx_time_to_ps(reg); reg 167 drivers/power/supply/max1721x_battery.c ret = regmap_read(info->regmap, MAX172XX_REG_TTF, ®); reg 168 drivers/power/supply/max1721x_battery.c val->intval = max172xx_time_to_ps(reg); reg 171 drivers/power/supply/max1721x_battery.c ret = regmap_read(info->regmap, MAX172XX_REG_TEMP, ®); reg 172 drivers/power/supply/max1721x_battery.c val->intval = max172xx_temperature_to_ps(reg); reg 176 drivers/power/supply/max1721x_battery.c ret = regmap_read(info->regmap, MAX172XX_REG_CURRENT, ®); reg 178 drivers/power/supply/max1721x_battery.c max172xx_current_to_voltage(reg) / (int)info->rsense; reg 181 drivers/power/supply/max1721x_battery.c ret = regmap_read(info->regmap, MAX172XX_REG_AVGCURRENT, ®); reg 183 drivers/power/supply/max1721x_battery.c max172xx_current_to_voltage(reg) / (int)info->rsense; reg 190 drivers/power/supply/max1721x_battery.c ret = regmap_read(info->regmap, MAX1721X_REG_DEV_STR, ®); reg 194 drivers/power/supply/max1721x_battery.c ret = regmap_read(info->regmap, MAX1721X_REG_MFG_STR, ®); reg 198 drivers/power/supply/max1721x_battery.c ret = regmap_read(info->regmap, MAX1721X_REG_SER_HEX, ®); reg 227 drivers/power/supply/max1721x_battery.c uint16_t reg, uint8_t nr, char *str) reg 231 drivers/power/supply/max1721x_battery.c if (!str || !(reg == MAX1721X_REG_MFG_STR || reg 232 drivers/power/supply/max1721x_battery.c reg == MAX1721X_REG_DEV_STR)) reg 236 drivers/power/supply/max1721x_battery.c if (regmap_read(info->regmap, reg++, &val)) reg 161 drivers/power/supply/max77650-charger.c int rv, reg; reg 163 drivers/power/supply/max77650-charger.c rv = regmap_read(chg->map, MAX77650_REG_STAT_CHG_B, ®); reg 170 drivers/power/supply/max77650-charger.c switch (MAX77650_CHGIN_DETAILS_BITS(reg)) { reg 195 drivers/power/supply/max77650-charger.c int rv, reg; reg 199 drivers/power/supply/max77650-charger.c rv = regmap_read(chg->map, MAX77650_REG_STAT_CHG_B, ®); reg 203 drivers/power/supply/max77650-charger.c if (MAX77650_CHARGER_CHG_CHARGING(reg)) { reg 208 drivers/power/supply/max77650-charger.c switch (MAX77650_CHG_DETAILS_BITS(reg)) { reg 232 drivers/power/supply/max77650-charger.c rv = regmap_read(chg->map, MAX77650_REG_STAT_CHG_B, ®); reg 236 drivers/power/supply/max77650-charger.c val->intval = MAX77650_CHARGER_CHG_CHARGING(reg); reg 239 drivers/power/supply/max77650-charger.c rv = regmap_read(chg->map, MAX77650_REG_STAT_CHG_B, ®); reg 243 drivers/power/supply/max77650-charger.c if (!MAX77650_CHARGER_CHG_CHARGING(reg)) { reg 248 drivers/power/supply/max77650-charger.c switch (MAX77650_CHG_DETAILS_BITS(reg)) { reg 36 drivers/power/supply/max8997_charger.c u8 reg; reg 41 drivers/power/supply/max8997_charger.c ret = max8997_read_reg(i2c, MAX8997_REG_STATUS4, ®); reg 44 drivers/power/supply/max8997_charger.c if ((reg & (1 << 0)) == 0x1) reg 50 drivers/power/supply/max8997_charger.c ret = max8997_read_reg(i2c, MAX8997_REG_STATUS4, ®); reg 53 drivers/power/supply/max8997_charger.c if ((reg & (1 << 2)) == 0x0) reg 59 drivers/power/supply/max8997_charger.c ret = max8997_read_reg(i2c, MAX8997_REG_STATUS4, ®); reg 63 drivers/power/supply/max8997_charger.c if (reg & (1 << 1)) reg 36 drivers/power/supply/max8998_charger.c u8 reg; reg 40 drivers/power/supply/max8998_charger.c ret = max8998_read_reg(i2c, MAX8998_REG_STATUS2, ®); reg 43 drivers/power/supply/max8998_charger.c if (reg & (1 << 4)) reg 49 drivers/power/supply/max8998_charger.c ret = max8998_read_reg(i2c, MAX8998_REG_STATUS2, ®); reg 52 drivers/power/supply/max8998_charger.c if (reg & (1 << 3)) reg 126 drivers/power/supply/pm2301_charger.c static int pm2xxx_reg_read(struct pm2xxx_charger *pm2, int reg, u8 *val) reg 133 drivers/power/supply/pm2301_charger.c ret = i2c_smbus_read_i2c_block_data(pm2->config.pm2xxx_i2c, reg, reg 136 drivers/power/supply/pm2301_charger.c dev_err(pm2->dev, "Error reading register at 0x%x\n", reg); reg 145 drivers/power/supply/pm2301_charger.c static int pm2xxx_reg_write(struct pm2xxx_charger *pm2, int reg, u8 val) reg 152 drivers/power/supply/pm2301_charger.c ret = i2c_smbus_write_i2c_block_data(pm2->config.pm2xxx_i2c, reg, reg 155 drivers/power/supply/pm2301_charger.c dev_err(pm2->dev, "Error writing register at 0x%x\n", reg); reg 492 drivers/power/supply/pm2301_charger.c &(interrupt->reg[i])); reg 494 drivers/power/supply/pm2301_charger.c if (interrupt->reg[i] > 0) reg 495 drivers/power/supply/pm2301_charger.c interrupt->handler[i](pm2, interrupt->reg[i]); reg 449 drivers/power/supply/pm2301_charger.h u8 reg[PM2XXX_NUM_INT_REG]; reg 180 drivers/power/supply/qcom_smbb.c unsigned int reg; reg 189 drivers/power/supply/qcom_smbb.c .reg = SMBB_CHG_ISAFE, reg 197 drivers/power/supply/qcom_smbb.c .reg = SMBB_CHG_IMAX, reg 205 drivers/power/supply/qcom_smbb.c .reg = SMBB_DC_IMAX, reg 212 drivers/power/supply/qcom_smbb.c .reg = SMBB_CHG_VSAFE, reg 220 drivers/power/supply/qcom_smbb.c .reg = SMBB_CHG_VMAX, reg 228 drivers/power/supply/qcom_smbb.c .reg = SMBB_CHG_VBAT_WEAK, reg 235 drivers/power/supply/qcom_smbb.c .reg = SMBB_CHG_VBAT_DET, reg 242 drivers/power/supply/qcom_smbb.c .reg = SMBB_CHG_VIN_MIN, reg 249 drivers/power/supply/qcom_smbb.c .reg = SMBB_USB_IMAX, reg 294 drivers/power/supply/qcom_smbb.c rc = regmap_write(chg->regmap, chg->addr + prop->reg, wval); reg 322 drivers/power/supply/qcom_smbb.c rc = regmap_read(chg->regmap, chg->addr + prop->reg, &val); reg 1550 drivers/power/supply/rt9455_charger.c static bool rt9455_is_writeable_reg(struct device *dev, unsigned int reg) reg 1552 drivers/power/supply/rt9455_charger.c switch (reg) { reg 1563 drivers/power/supply/rt9455_charger.c static bool rt9455_is_volatile_reg(struct device *dev, unsigned int reg) reg 1565 drivers/power/supply/rt9455_charger.c switch (reg) { reg 49 drivers/power/supply/sbs-charger.c unsigned int reg; reg 51 drivers/power/supply/sbs-charger.c reg = chip->last_state; reg 55 drivers/power/supply/sbs-charger.c val->intval = !!(reg & SBS_CHARGER_STATUS_BATTERY_PRESENT); reg 59 drivers/power/supply/sbs-charger.c val->intval = !!(reg & SBS_CHARGER_STATUS_AC_PRESENT); reg 65 drivers/power/supply/sbs-charger.c if (!(reg & SBS_CHARGER_STATUS_BATTERY_PRESENT)) reg 67 drivers/power/supply/sbs-charger.c else if (reg & SBS_CHARGER_STATUS_AC_PRESENT && reg 68 drivers/power/supply/sbs-charger.c !(reg & SBS_CHARGER_STATUS_CHARGE_INHIBITED)) reg 76 drivers/power/supply/sbs-charger.c if (reg & SBS_CHARGER_STATUS_RES_COLD) reg 78 drivers/power/supply/sbs-charger.c if (reg & SBS_CHARGER_STATUS_RES_HOT) reg 94 drivers/power/supply/sbs-charger.c unsigned int reg; reg 97 drivers/power/supply/sbs-charger.c ret = regmap_read(chip->regmap, SBS_CHARGER_REG_STATUS, ®); reg 98 drivers/power/supply/sbs-charger.c if (!ret && reg != chip->last_state) { reg 99 drivers/power/supply/sbs-charger.c chip->last_state = reg; reg 134 drivers/power/supply/sbs-charger.c static bool sbs_readable_reg(struct device *dev, unsigned int reg) reg 136 drivers/power/supply/sbs-charger.c return reg >= SBS_CHARGER_REG_SPEC_INFO; reg 139 drivers/power/supply/sbs-charger.c static bool sbs_volatile_reg(struct device *dev, unsigned int reg) reg 141 drivers/power/supply/sbs-charger.c switch (reg) { reg 60 drivers/power/supply/sbs-manager.c int reg, retries; reg 63 drivers/power/supply/sbs-manager.c reg = i2c_smbus_read_word_data(client, address); reg 64 drivers/power/supply/sbs-manager.c if (reg >= 0) reg 68 drivers/power/supply/sbs-manager.c if (reg < 0) { reg 73 drivers/power/supply/sbs-manager.c return reg; reg 177 drivers/power/supply/sbs-manager.c u16 reg; reg 183 drivers/power/supply/sbs-manager.c reg = BIT(SBSM_SMB_BAT_OFFSET + chan); reg 184 drivers/power/supply/sbs-manager.c ret = sbsm_write_word(data->client, SBSM_CMD_BATSYSSTATE, reg); reg 1136 drivers/power/supply/smb347-charger.c static bool smb347_volatile_reg(struct device *dev, unsigned int reg) reg 1138 drivers/power/supply/smb347-charger.c switch (reg) { reg 1153 drivers/power/supply/smb347-charger.c static bool smb347_readable_reg(struct device *dev, unsigned int reg) reg 1155 drivers/power/supply/smb347-charger.c switch (reg) { reg 1175 drivers/power/supply/smb347-charger.c return smb347_volatile_reg(dev, reg); reg 157 drivers/power/supply/twl4030_charger.c static int twl4030_clear_set(u8 mod_no, u8 clear, u8 set, u8 reg) reg 162 drivers/power/supply/twl4030_charger.c ret = twl_i2c_read_u8(mod_no, &val, reg); reg 169 drivers/power/supply/twl4030_charger.c return twl_i2c_write_u8(mod_no, val, reg); reg 172 drivers/power/supply/twl4030_charger.c static int twl4030_bci_read(u8 reg, u8 *val) reg 174 drivers/power/supply/twl4030_charger.c return twl_i2c_read_u8(TWL_MODULE_MAIN_CHARGE, val, reg); reg 184 drivers/power/supply/twl4030_charger.c static int twl4030bci_read_adc_val(u8 reg) reg 190 drivers/power/supply/twl4030_charger.c ret = twl4030_bci_read(reg + 1, &val); reg 197 drivers/power/supply/twl4030_charger.c ret = twl4030_bci_read(reg, &val); reg 242 drivers/power/supply/twl4030_charger.c unsigned reg, cur_reg; reg 295 drivers/power/supply/twl4030_charger.c reg = ua2regval(bci->ichg_eoc, cgain); reg 296 drivers/power/supply/twl4030_charger.c if (reg > 0x278) reg 297 drivers/power/supply/twl4030_charger.c reg = 0x278; reg 298 drivers/power/supply/twl4030_charger.c if (reg < 0x200) reg 299 drivers/power/supply/twl4030_charger.c reg = 0x200; reg 300 drivers/power/supply/twl4030_charger.c reg = (reg >> 3) & 0xf; reg 301 drivers/power/supply/twl4030_charger.c fullreg = reg << 4; reg 307 drivers/power/supply/twl4030_charger.c reg = ua2regval(bci->ichg_lo, cgain); reg 308 drivers/power/supply/twl4030_charger.c if (reg > 0x2F0) reg 309 drivers/power/supply/twl4030_charger.c reg = 0x2F0; reg 310 drivers/power/supply/twl4030_charger.c if (reg < 0x200) reg 311 drivers/power/supply/twl4030_charger.c reg = 0x200; reg 312 drivers/power/supply/twl4030_charger.c reg = (reg >> 4) & 0xf; reg 313 drivers/power/supply/twl4030_charger.c fullreg |= reg; reg 329 drivers/power/supply/twl4030_charger.c reg = ua2regval(bci->ichg_hi, cgain); reg 330 drivers/power/supply/twl4030_charger.c if (reg > 0x3E0) reg 331 drivers/power/supply/twl4030_charger.c reg = 0x3E0; reg 332 drivers/power/supply/twl4030_charger.c if (reg < 0x200) reg 333 drivers/power/supply/twl4030_charger.c reg = 0x200; reg 334 drivers/power/supply/twl4030_charger.c fullreg = (reg >> 5) & 0xF; reg 353 drivers/power/supply/twl4030_charger.c reg = ua2regval(cur, cgain); reg 355 drivers/power/supply/twl4030_charger.c if (reg > 0x3ff) reg 356 drivers/power/supply/twl4030_charger.c reg = 0x3ff; reg 365 drivers/power/supply/twl4030_charger.c if (reg != oldreg) { reg 373 drivers/power/supply/twl4030_charger.c (reg & 0x100) ? 3 : 2, reg 384 drivers/power/supply/twl4030_charger.c reg & 0xff, reg 439 drivers/power/supply/twl4030_charger.c u32 reg; reg 455 drivers/power/supply/twl4030_charger.c reg = ~(u32)(TWL4030_ICHGLOW | TWL4030_ICHGEOC | reg 458 drivers/power/supply/twl4030_charger.c ret = twl_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, reg, reg 475 drivers/power/supply/twl4030_charger.c reg = ~(u32)(TWL4030_ICHGLOW | TWL4030_TBATOR2 | reg 477 drivers/power/supply/twl4030_charger.c ret = twl_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, reg, reg 981 drivers/power/supply/twl4030_charger.c u32 reg; reg 1075 drivers/power/supply/twl4030_charger.c reg = ~(u32)(TWL4030_ICHGLOW | TWL4030_ICHGEOC | TWL4030_TBATOR2 | reg 1077 drivers/power/supply/twl4030_charger.c ret = twl_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, reg, reg 1084 drivers/power/supply/twl4030_charger.c reg = ~(u32)(TWL4030_VBATOV | TWL4030_VBUSOV | TWL4030_ACCHGOV); reg 1085 drivers/power/supply/twl4030_charger.c ret = twl_i2c_write_u8(TWL4030_MODULE_INTERRUPTS, reg, reg 120 drivers/power/supply/ucs1002_power.c unsigned int reg; reg 123 drivers/power/supply/ucs1002_power.c ret = regmap_read(info->regmap, UCS1002_REG_OTHER_STATUS, ®); reg 127 drivers/power/supply/ucs1002_power.c val->intval = !!(reg & F_CHG_ACT); reg 177 drivers/power/supply/ucs1002_power.c unsigned int reg; reg 181 drivers/power/supply/ucs1002_power.c ®, sizeof(u32)); reg 185 drivers/power/supply/ucs1002_power.c total_acc_charger = be32_to_cpu(reg); /* BE as per offsets above */ reg 206 drivers/power/supply/ucs1002_power.c unsigned int reg; reg 209 drivers/power/supply/ucs1002_power.c ret = regmap_read(info->regmap, UCS1002_REG_CURRENT_MEASUREMENT, ®); reg 213 drivers/power/supply/ucs1002_power.c current_measurement = reg; reg 233 drivers/power/supply/ucs1002_power.c unsigned int reg; reg 236 drivers/power/supply/ucs1002_power.c ret = regmap_read(info->regmap, UCS1002_REG_ILIMIT, ®); reg 240 drivers/power/supply/ucs1002_power.c val->intval = ucs1002_current_limit_uA[reg & UCS1002_ILIM_SW_MASK]; reg 247 drivers/power/supply/ucs1002_power.c unsigned int reg; reg 266 drivers/power/supply/ucs1002_power.c ret = regmap_read(info->regmap, UCS1002_REG_ILIMIT, ®); reg 270 drivers/power/supply/ucs1002_power.c if (reg != idx) reg 316 drivers/power/supply/ucs1002_power.c unsigned int reg; reg 319 drivers/power/supply/ucs1002_power.c ret = regmap_read(info->regmap, UCS1002_REG_PIN_STATUS, ®); reg 323 drivers/power/supply/ucs1002_power.c switch (reg & F_ACTIVE_MODE_MASK) { reg 349 drivers/power/supply/ucs1002_power.c unsigned int reg; reg 352 drivers/power/supply/ucs1002_power.c ret = regmap_read(info->regmap, UCS1002_REG_INTERRUPT_STATUS, ®); reg 356 drivers/power/supply/ucs1002_power.c if (reg & F_TSD) reg 358 drivers/power/supply/ucs1002_power.c else if (reg & (F_OVER_VOLT | F_BACK_VOLT)) reg 360 drivers/power/supply/ucs1002_power.c else if (reg & F_OVER_ILIM) reg 362 drivers/power/supply/ucs1002_power.c else if (reg & (F_DISCHARGE_ERR | F_MIN_KEEP_OUT)) reg 47 drivers/power/supply/wm831x_backup.c int ret, reg; reg 57 drivers/power/supply/wm831x_backup.c reg = 0; reg 60 drivers/power/supply/wm831x_backup.c reg |= WM831X_BKUP_CHG_ENA | WM831X_BKUP_BATT_DET_ENA; reg 62 drivers/power/supply/wm831x_backup.c reg |= WM831X_BKUP_CHG_MODE; reg 68 drivers/power/supply/wm831x_backup.c reg |= WM831X_BKUP_CHG_VLIM; reg 79 drivers/power/supply/wm831x_backup.c reg |= 1; reg 82 drivers/power/supply/wm831x_backup.c reg |= 2; reg 85 drivers/power/supply/wm831x_backup.c reg |= 3; reg 104 drivers/power/supply/wm831x_backup.c reg); reg 239 drivers/power/supply/wm831x_power.c int *reg, const char *name, reg 251 drivers/power/supply/wm831x_power.c *reg |= map[i].reg_val; reg 89 drivers/power/supply/wm8350_power.c u16 reg, eoc_mA, fast_limit_mA; reg 107 drivers/power/supply/wm8350_power.c reg = wm8350_reg_read(wm8350, WM8350_BATTERY_CHARGER_CONTROL_1) reg 110 drivers/power/supply/wm8350_power.c reg | eoc_mA | policy->trickle_start_mV | reg 310 drivers/power/supply/wm8350_power.c u16 reg; reg 315 drivers/power/supply/wm8350_power.c reg = wm8350_reg_read(wm8350, WM8350_CHARGER_OVERRIDES); reg 316 drivers/power/supply/wm8350_power.c if (reg & WM8350_CHG_BATT_HOT_OVRDE) reg 319 drivers/power/supply/wm8350_power.c if (reg & WM8350_CHG_BATT_COLD_OVRDE) reg 649 drivers/powercap/intel_rapl_common.c ra.reg = rd->regs[rp->id]; reg 650 drivers/powercap/intel_rapl_common.c if (!ra.reg) reg 669 drivers/powercap/intel_rapl_common.c pr_debug("failed to read reg 0x%llx on cpu %d\n", ra.reg, cpu); reg 701 drivers/powercap/intel_rapl_common.c ra.reg = rd->regs[rp->id]; reg 726 drivers/powercap/intel_rapl_common.c ra.reg = rp->priv->reg_unit; reg 754 drivers/powercap/intel_rapl_common.c ra.reg = rp->priv->reg_unit; reg 1092 drivers/powercap/intel_rapl_common.c ra.reg = priv->regs[RAPL_DOMAIN_PLATFORM][RAPL_DOMAIN_REG_STATUS]; reg 1098 drivers/powercap/intel_rapl_common.c ra.reg = priv->regs[RAPL_DOMAIN_PLATFORM][RAPL_DOMAIN_REG_LIMIT]; reg 1155 drivers/powercap/intel_rapl_common.c ra.reg = rp->priv->regs[domain][RAPL_DOMAIN_REG_STATUS]; reg 89 drivers/powercap/intel_rapl_msr.c u32 msr = (u32)ra->reg; reg 102 drivers/powercap/intel_rapl_msr.c u32 msr = (u32)ra->reg; reg 387 drivers/ps3/ps3-lpm.c u32 ps3_read_pm(u32 cpu, enum pm_reg_name reg) reg 392 drivers/ps3/ps3-lpm.c switch (reg) { reg 404 drivers/ps3/ps3-lpm.c "reg %u, %s\n", __func__, __LINE__, reg, reg 418 drivers/ps3/ps3-lpm.c "reg %u, %s\n", __func__, __LINE__, reg, reg 426 drivers/ps3/ps3-lpm.c __LINE__, reg); reg 439 drivers/ps3/ps3-lpm.c void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val) reg 444 drivers/ps3/ps3-lpm.c switch (reg) { reg 491 drivers/ps3/ps3-lpm.c __LINE__, reg); reg 498 drivers/ps3/ps3-lpm.c "reg %u, %s\n", __func__, __LINE__, reg, reg 32 drivers/pwm/pwm-ab8500.c u8 reg; reg 45 drivers/pwm/pwm-ab8500.c reg = AB8500_PWM_OUT_CTRL1_REG + ((chip->base - 1) * 2); reg 48 drivers/pwm/pwm-ab8500.c reg, (u8)lower_val); reg 52 drivers/pwm/pwm-ab8500.c (reg + 1), (u8)higher_val); reg 378 drivers/pwm/pwm-fsl-ftm.c static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg) reg 380 drivers/pwm/pwm-fsl-ftm.c switch (reg) { reg 81 drivers/pwm/pwm-img.c u32 reg, u32 val) reg 83 drivers/pwm/pwm-img.c writel(val, chip->base + reg); reg 87 drivers/pwm/pwm-img.c u32 reg) reg 89 drivers/pwm/pwm-img.c return readl(chip->base + reg); reg 143 drivers/pwm/pwm-lp3943.c err = lp3943_update_bits(lp3943, mux[index].reg, reg 113 drivers/pwm/pwm-lpc18xx-sct.c u32 reg, u32 val) reg 115 drivers/pwm/pwm-lpc18xx-sct.c writel(val, lpc18xx_pwm->base + reg); reg 119 drivers/pwm/pwm-lpc18xx-sct.c u32 reg) reg 121 drivers/pwm/pwm-lpc18xx-sct.c return readl(lpc18xx_pwm->base + reg); reg 511 drivers/pwm/pwm-meson.c channel->mux.reg = meson->base + REG_MISC_AB; reg 251 drivers/pwm/pwm-pca9685.c unsigned int reg; reg 287 drivers/pwm/pwm-pca9685.c reg = PCA9685_ALL_LED_OFF_H; reg 289 drivers/pwm/pwm-pca9685.c reg = LED_N_OFF_H(pwm->hwpwm); reg 291 drivers/pwm/pwm-pca9685.c regmap_write(pca->regmap, reg, LED_FULL); reg 299 drivers/pwm/pwm-pca9685.c reg = PCA9685_ALL_LED_OFF_L; reg 301 drivers/pwm/pwm-pca9685.c reg = LED_N_OFF_L(pwm->hwpwm); reg 303 drivers/pwm/pwm-pca9685.c regmap_write(pca->regmap, reg, 0x0); reg 306 drivers/pwm/pwm-pca9685.c reg = PCA9685_ALL_LED_OFF_H; reg 308 drivers/pwm/pwm-pca9685.c reg = LED_N_OFF_H(pwm->hwpwm); reg 310 drivers/pwm/pwm-pca9685.c regmap_write(pca->regmap, reg, 0x0); reg 314 drivers/pwm/pwm-pca9685.c reg = PCA9685_ALL_LED_ON_H; reg 316 drivers/pwm/pwm-pca9685.c reg = LED_N_ON_H(pwm->hwpwm); reg 318 drivers/pwm/pwm-pca9685.c regmap_write(pca->regmap, reg, LED_FULL); reg 327 drivers/pwm/pwm-pca9685.c reg = PCA9685_ALL_LED_OFF_L; reg 329 drivers/pwm/pwm-pca9685.c reg = LED_N_OFF_L(pwm->hwpwm); reg 331 drivers/pwm/pwm-pca9685.c regmap_write(pca->regmap, reg, (int)duty & 0xff); reg 334 drivers/pwm/pwm-pca9685.c reg = PCA9685_ALL_LED_OFF_H; reg 336 drivers/pwm/pwm-pca9685.c reg = LED_N_OFF_H(pwm->hwpwm); reg 338 drivers/pwm/pwm-pca9685.c regmap_write(pca->regmap, reg, ((int)duty >> 8) & 0xf); reg 342 drivers/pwm/pwm-pca9685.c reg = PCA9685_ALL_LED_ON_H; reg 344 drivers/pwm/pwm-pca9685.c reg = LED_N_ON_H(pwm->hwpwm); reg 346 drivers/pwm/pwm-pca9685.c regmap_write(pca->regmap, reg, 0); reg 354 drivers/pwm/pwm-pca9685.c unsigned int reg; reg 361 drivers/pwm/pwm-pca9685.c reg = PCA9685_ALL_LED_ON_L; reg 363 drivers/pwm/pwm-pca9685.c reg = LED_N_ON_L(pwm->hwpwm); reg 365 drivers/pwm/pwm-pca9685.c regmap_write(pca->regmap, reg, 0); reg 368 drivers/pwm/pwm-pca9685.c reg = PCA9685_ALL_LED_ON_H; reg 370 drivers/pwm/pwm-pca9685.c reg = LED_N_ON_H(pwm->hwpwm); reg 372 drivers/pwm/pwm-pca9685.c regmap_write(pca->regmap, reg, 0); reg 379 drivers/pwm/pwm-pca9685.c reg = PCA9685_ALL_LED_OFF_H; reg 381 drivers/pwm/pwm-pca9685.c reg = LED_N_OFF_H(pwm->hwpwm); reg 383 drivers/pwm/pwm-pca9685.c regmap_update_bits(pca->regmap, reg, LED_FULL, 0x0); reg 391 drivers/pwm/pwm-pca9685.c unsigned int reg; reg 394 drivers/pwm/pwm-pca9685.c reg = PCA9685_ALL_LED_OFF_H; reg 396 drivers/pwm/pwm-pca9685.c reg = LED_N_OFF_H(pwm->hwpwm); reg 398 drivers/pwm/pwm-pca9685.c regmap_write(pca->regmap, reg, LED_FULL); reg 402 drivers/pwm/pwm-pca9685.c reg = PCA9685_ALL_LED_OFF_L; reg 404 drivers/pwm/pwm-pca9685.c reg = LED_N_OFF_L(pwm->hwpwm); reg 406 drivers/pwm/pwm-pca9685.c regmap_write(pca->regmap, reg, 0x0); reg 125 drivers/pwm/pwm-samsung.c u32 reg; reg 132 drivers/pwm/pwm-samsung.c reg = readl(pwm->base + REG_TCFG1); reg 133 drivers/pwm/pwm-samsung.c reg &= ~(TCFG1_MUX_MASK << shift); reg 134 drivers/pwm/pwm-samsung.c reg |= bits << shift; reg 135 drivers/pwm/pwm-samsung.c writel(reg, pwm->base + REG_TCFG1); reg 143 drivers/pwm/pwm-samsung.c u32 reg; reg 145 drivers/pwm/pwm-samsung.c reg = readl(chip->base + REG_TCFG1); reg 146 drivers/pwm/pwm-samsung.c reg >>= TCFG1_SHIFT(chan); reg 147 drivers/pwm/pwm-samsung.c reg &= TCFG1_MUX_MASK; reg 149 drivers/pwm/pwm-samsung.c return (BIT(reg) & variant->tclk_mask) == 0; reg 156 drivers/pwm/pwm-samsung.c u32 reg; reg 160 drivers/pwm/pwm-samsung.c reg = readl(chip->base + REG_TCFG0); reg 162 drivers/pwm/pwm-samsung.c reg >>= TCFG0_PRESCALER1_SHIFT; reg 163 drivers/pwm/pwm-samsung.c reg &= TCFG0_PRESCALER_MASK; reg 165 drivers/pwm/pwm-samsung.c return rate / (reg + 1); reg 53 drivers/pwm/pwm-sprd.c static u32 sprd_pwm_read(struct sprd_pwm_chip *spc, u32 hwid, u32 reg) reg 55 drivers/pwm/pwm-sprd.c u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT); reg 61 drivers/pwm/pwm-sprd.c u32 reg, u32 val) reg 63 drivers/pwm/pwm-sprd.c u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT); reg 410 drivers/pwm/pwm-sti.c unsigned int reg; reg 445 drivers/pwm/pwm-sti.c regmap_read(pc->regmap, PWM_CPT_EDGE(devicenum), ®); reg 446 drivers/pwm/pwm-sti.c reg ^= PWM_CPT_EDGE_MASK; reg 447 drivers/pwm/pwm-sti.c regmap_write(pc->regmap, PWM_CPT_EDGE(devicenum), reg); reg 48 drivers/pwm/pwm-sun4i.c #define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1) reg 49 drivers/pwm/pwm-sun4i.c #define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK) reg 50 drivers/pwm/pwm-sun4i.c #define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK) reg 158 drivers/regulator/ab3100.c static int ab3100_enable_regulator(struct regulator_dev *reg) reg 160 drivers/regulator/ab3100.c struct ab3100_regulator *abreg = rdev_get_drvdata(reg); reg 167 drivers/regulator/ab3100.c dev_warn(®->dev, "failed to get regid %d value\n", reg 181 drivers/regulator/ab3100.c dev_warn(®->dev, "failed to set regid %d value\n", reg 189 drivers/regulator/ab3100.c static int ab3100_disable_regulator(struct regulator_dev *reg) reg 191 drivers/regulator/ab3100.c struct ab3100_regulator *abreg = rdev_get_drvdata(reg); reg 201 drivers/regulator/ab3100.c dev_info(®->dev, "disabling LDO D - shut down system\n"); reg 213 drivers/regulator/ab3100.c dev_err(®->dev, "unable to get register 0x%x\n", reg 222 drivers/regulator/ab3100.c static int ab3100_is_enabled_regulator(struct regulator_dev *reg) reg 224 drivers/regulator/ab3100.c struct ab3100_regulator *abreg = rdev_get_drvdata(reg); reg 231 drivers/regulator/ab3100.c dev_err(®->dev, "unable to get register 0x%x\n", reg 239 drivers/regulator/ab3100.c static int ab3100_get_voltage_regulator(struct regulator_dev *reg) reg 241 drivers/regulator/ab3100.c struct ab3100_regulator *abreg = rdev_get_drvdata(reg); reg 252 drivers/regulator/ab3100.c dev_warn(®->dev, reg 262 drivers/regulator/ab3100.c if (regval >= reg->desc->n_voltages) { reg 263 drivers/regulator/ab3100.c dev_err(®->dev, reg 269 drivers/regulator/ab3100.c return reg->desc->volt_table[regval]; reg 272 drivers/regulator/ab3100.c static int ab3100_set_voltage_regulator_sel(struct regulator_dev *reg, reg 275 drivers/regulator/ab3100.c struct ab3100_regulator *abreg = rdev_get_drvdata(reg); reg 282 drivers/regulator/ab3100.c dev_warn(®->dev, reg 295 drivers/regulator/ab3100.c dev_warn(®->dev, "failed to set regulator register %02x\n", reg 301 drivers/regulator/ab3100.c static int ab3100_set_suspend_voltage_regulator(struct regulator_dev *reg, reg 304 drivers/regulator/ab3100.c struct ab3100_regulator *abreg = rdev_get_drvdata(reg); reg 318 drivers/regulator/ab3100.c bestindex = regulator_map_voltage_iterate(reg, uV, uV); reg 323 drivers/regulator/ab3100.c dev_warn(®->dev, reg 336 drivers/regulator/ab3100.c dev_warn(®->dev, "failed to set regulator register %02x\n", reg 345 drivers/regulator/ab3100.c static int ab3100_get_voltage_regulator_external(struct regulator_dev *reg) reg 347 drivers/regulator/ab3100.c struct ab3100_regulator *abreg = rdev_get_drvdata(reg); reg 502 drivers/regulator/ab3100.c struct ab3100_regulator *reg; reg 516 drivers/regulator/ab3100.c reg = &ab3100_regulators[i]; reg 525 drivers/regulator/ab3100.c reg->dev = &pdev->dev; reg 527 drivers/regulator/ab3100.c reg->plfdata = plfdata; reg 534 drivers/regulator/ab3100.c config.driver_data = reg; reg 316 drivers/regulator/ab8500.c u8 bank, reg, mask, val; reg 327 drivers/regulator/ab8500.c reg = info->mode_reg; reg 331 drivers/regulator/ab8500.c reg = info->update_reg; reg 374 drivers/regulator/ab8500.c bank, reg, mask, val); reg 384 drivers/regulator/ab8500.c info->desc.name, bank, reg, reg 240 drivers/regulator/act8865-regulator.c int id = rdev->desc->id, reg, val; reg 244 drivers/regulator/act8865-regulator.c reg = ACT8865_DCDC1_SUS; reg 248 drivers/regulator/act8865-regulator.c reg = ACT8865_DCDC2_SUS; reg 252 drivers/regulator/act8865-regulator.c reg = ACT8865_DCDC3_SUS; reg 256 drivers/regulator/act8865-regulator.c reg = ACT8865_LDO1_SUS; reg 260 drivers/regulator/act8865-regulator.c reg = ACT8865_LDO2_SUS; reg 264 drivers/regulator/act8865-regulator.c reg = ACT8865_LDO3_SUS; reg 268 drivers/regulator/act8865-regulator.c reg = ACT8865_LDO4_SUS; reg 282 drivers/regulator/act8865-regulator.c return regmap_write(regmap, reg, val); reg 313 drivers/regulator/act8865-regulator.c int reg, val = 0; reg 317 drivers/regulator/act8865-regulator.c reg = ACT8865_DCDC1_CTRL; reg 320 drivers/regulator/act8865-regulator.c reg = ACT8865_DCDC2_CTRL; reg 323 drivers/regulator/act8865-regulator.c reg = ACT8865_DCDC3_CTRL; reg 326 drivers/regulator/act8865-regulator.c reg = ACT8865_LDO1_CTRL; reg 329 drivers/regulator/act8865-regulator.c reg = ACT8865_LDO2_CTRL; reg 332 drivers/regulator/act8865-regulator.c reg = ACT8865_LDO3_CTRL; reg 335 drivers/regulator/act8865-regulator.c reg = ACT8865_LDO4_CTRL; reg 355 drivers/regulator/act8865-regulator.c return regmap_update_bits(regmap, reg, BIT(5), val); reg 362 drivers/regulator/act8865-regulator.c int reg, ret, val = 0; reg 366 drivers/regulator/act8865-regulator.c reg = ACT8865_DCDC1_CTRL; reg 369 drivers/regulator/act8865-regulator.c reg = ACT8865_DCDC2_CTRL; reg 372 drivers/regulator/act8865-regulator.c reg = ACT8865_DCDC3_CTRL; reg 375 drivers/regulator/act8865-regulator.c reg = ACT8865_LDO1_CTRL; reg 378 drivers/regulator/act8865-regulator.c reg = ACT8865_LDO2_CTRL; reg 381 drivers/regulator/act8865-regulator.c reg = ACT8865_LDO3_CTRL; reg 384 drivers/regulator/act8865-regulator.c reg = ACT8865_LDO4_CTRL; reg 390 drivers/regulator/act8865-regulator.c ret = regmap_read(regmap, reg, &val); reg 86 drivers/regulator/act8945a-regulator.c int reg, val; reg 90 drivers/regulator/act8945a-regulator.c reg = ACT8945A_DCDC1_SUS; reg 94 drivers/regulator/act8945a-regulator.c reg = ACT8945A_DCDC2_SUS; reg 98 drivers/regulator/act8945a-regulator.c reg = ACT8945A_DCDC3_SUS; reg 102 drivers/regulator/act8945a-regulator.c reg = ACT8945A_LDO1_SUS; reg 106 drivers/regulator/act8945a-regulator.c reg = ACT8945A_LDO2_SUS; reg 110 drivers/regulator/act8945a-regulator.c reg = ACT8945A_LDO3_SUS; reg 114 drivers/regulator/act8945a-regulator.c reg = ACT8945A_LDO4_SUS; reg 128 drivers/regulator/act8945a-regulator.c return regmap_write(regmap, reg, val); reg 159 drivers/regulator/act8945a-regulator.c int reg, ret, val = 0; reg 163 drivers/regulator/act8945a-regulator.c reg = ACT8945A_DCDC1_CTRL; reg 166 drivers/regulator/act8945a-regulator.c reg = ACT8945A_DCDC2_CTRL; reg 169 drivers/regulator/act8945a-regulator.c reg = ACT8945A_DCDC3_CTRL; reg 172 drivers/regulator/act8945a-regulator.c reg = ACT8945A_LDO1_CTRL; reg 175 drivers/regulator/act8945a-regulator.c reg = ACT8945A_LDO2_CTRL; reg 178 drivers/regulator/act8945a-regulator.c reg = ACT8945A_LDO3_CTRL; reg 181 drivers/regulator/act8945a-regulator.c reg = ACT8945A_LDO4_CTRL; reg 200 drivers/regulator/act8945a-regulator.c ret = regmap_update_bits(regmap, reg, BIT(5), val); reg 34 drivers/regulator/anatop-regulator.c static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg, reg 38 drivers/regulator/anatop-regulator.c struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg); reg 50 drivers/regulator/anatop-regulator.c regmap_read(reg->regmap, anatop_reg->delay_reg, &val); reg 60 drivers/regulator/anatop-regulator.c static int anatop_regmap_enable(struct regulator_dev *reg) reg 62 drivers/regulator/anatop-regulator.c struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg); reg 66 drivers/regulator/anatop-regulator.c return regulator_set_voltage_sel_regmap(reg, sel); reg 69 drivers/regulator/anatop-regulator.c static int anatop_regmap_disable(struct regulator_dev *reg) reg 71 drivers/regulator/anatop-regulator.c return regulator_set_voltage_sel_regmap(reg, LDO_POWER_GATE); reg 74 drivers/regulator/anatop-regulator.c static int anatop_regmap_is_enabled(struct regulator_dev *reg) reg 76 drivers/regulator/anatop-regulator.c return regulator_get_voltage_sel_regmap(reg) != LDO_POWER_GATE; reg 79 drivers/regulator/anatop-regulator.c static int anatop_regmap_core_set_voltage_sel(struct regulator_dev *reg, reg 82 drivers/regulator/anatop-regulator.c struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg); reg 85 drivers/regulator/anatop-regulator.c if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) { reg 90 drivers/regulator/anatop-regulator.c ret = regulator_set_voltage_sel_regmap(reg, selector); reg 96 drivers/regulator/anatop-regulator.c static int anatop_regmap_core_get_voltage_sel(struct regulator_dev *reg) reg 98 drivers/regulator/anatop-regulator.c struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg); reg 100 drivers/regulator/anatop-regulator.c if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) reg 103 drivers/regulator/anatop-regulator.c return regulator_get_voltage_sel_regmap(reg); reg 106 drivers/regulator/anatop-regulator.c static int anatop_regmap_get_bypass(struct regulator_dev *reg, bool *enable) reg 108 drivers/regulator/anatop-regulator.c struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg); reg 111 drivers/regulator/anatop-regulator.c sel = regulator_get_voltage_sel_regmap(reg); reg 121 drivers/regulator/anatop-regulator.c static int anatop_regmap_set_bypass(struct regulator_dev *reg, bool enable) reg 123 drivers/regulator/anatop-regulator.c struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg); reg 132 drivers/regulator/anatop-regulator.c return regulator_set_voltage_sel_regmap(reg, sel); reg 371 drivers/regulator/axp20x-regulator.c u8 reg, mask, enable, cfg = 0xff; reg 380 drivers/regulator/axp20x-regulator.c reg = AXP20X_DCDC2_LDO3_V_RAMP; reg 392 drivers/regulator/axp20x-regulator.c reg = AXP20X_DCDC2_LDO3_V_RAMP; reg 433 drivers/regulator/axp20x-regulator.c return regmap_update_bits(axp20x->regmap, reg, mask, cfg); reg 1008 drivers/regulator/axp20x-regulator.c unsigned int reg = AXP20X_DCDC_FREQ; reg 1026 drivers/regulator/axp20x-regulator.c reg = AXP803_DCDC_FREQ_CTRL; reg 1034 drivers/regulator/axp20x-regulator.c reg = AXP806_DCDC_FREQ_CTRL; reg 1067 drivers/regulator/axp20x-regulator.c return regmap_update_bits(axp20x->regmap, reg, reg 1101 drivers/regulator/axp20x-regulator.c unsigned int reg = AXP20X_DCDC_MODE; reg 1122 drivers/regulator/axp20x-regulator.c reg = AXP806_DCDC_MODE_CTRL2; reg 1156 drivers/regulator/axp20x-regulator.c return regmap_update_bits(rdev->regmap, reg, mask, workmode); reg 1165 drivers/regulator/axp20x-regulator.c u32 reg = 0; reg 1174 drivers/regulator/axp20x-regulator.c regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, ®); reg 1178 drivers/regulator/axp20x-regulator.c return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL); reg 1180 drivers/regulator/axp20x-regulator.c return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL); reg 1185 drivers/regulator/axp20x-regulator.c regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, ®); reg 1189 drivers/regulator/axp20x-regulator.c return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) == reg 1191 drivers/regulator/axp20x-regulator.c ((reg & AXP806_DCDCABC_POLYPHASE_MASK) == reg 1194 drivers/regulator/axp20x-regulator.c return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) == reg 1197 drivers/regulator/axp20x-regulator.c return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL); reg 211 drivers/regulator/bcm590xx-regulator.c int reg = 0; reg 214 drivers/regulator/bcm590xx-regulator.c reg = BCM590XX_RFLDOPMCTRL1 + id * 2; reg 216 drivers/regulator/bcm590xx-regulator.c reg = BCM590XX_GPLDO1PMCTRL1 + id * 2; reg 220 drivers/regulator/bcm590xx-regulator.c reg = BCM590XX_CSRPMCTRL1; reg 223 drivers/regulator/bcm590xx-regulator.c reg = BCM590XX_IOSR1PMCTRL1; reg 226 drivers/regulator/bcm590xx-regulator.c reg = BCM590XX_IOSR2PMCTRL1; reg 229 drivers/regulator/bcm590xx-regulator.c reg = BCM590XX_MSRPMCTRL1; reg 232 drivers/regulator/bcm590xx-regulator.c reg = BCM590XX_SDSR1PMCTRL1; reg 235 drivers/regulator/bcm590xx-regulator.c reg = BCM590XX_SDSR2PMCTRL1; reg 238 drivers/regulator/bcm590xx-regulator.c reg = BCM590XX_VSRPMCTRL1; reg 241 drivers/regulator/bcm590xx-regulator.c reg = BCM590XX_OTG_CTRL; reg 246 drivers/regulator/bcm590xx-regulator.c return reg; reg 315 drivers/regulator/bd718x7-regulator.c unsigned int reg; reg 338 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_MVRFLTMASK2, reg 346 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_MVRFLTMASK2, reg 356 drivers/regulator/bd718x7-regulator.c unsigned int reg; reg 380 drivers/regulator/bd718x7-regulator.c ret = regmap_update_bits(regmap, dvs->reg, reg 396 drivers/regulator/bd718x7-regulator.c .reg = BD71837_REG_BUCK4_VOLT_RUN, reg 415 drivers/regulator/bd718x7-regulator.c .reg = BD71837_REG_BUCK3_VOLT_RUN, reg 435 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_BUCK2_VOLT_RUN, reg 439 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_BUCK2_VOLT_IDLE, reg 461 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_BUCK1_VOLT_RUN, reg 465 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_BUCK1_VOLT_IDLE, reg 469 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_BUCK1_VOLT_SUSP, reg 502 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_BUCK1_CTRL, reg 526 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_BUCK2_CTRL, reg 553 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_1ST_NODVS_BUCK_CTRL, reg 580 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_2ND_NODVS_BUCK_CTRL, reg 602 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_3RD_NODVS_BUCK_CTRL, reg 626 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_4TH_NODVS_BUCK_CTRL, reg 652 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_LDO1_VOLT, reg 674 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_LDO2_VOLT, reg 697 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_LDO3_VOLT, reg 720 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_LDO4_VOLT, reg 746 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_LDO5_VOLT, reg 771 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_LDO6_VOLT, reg 798 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_BUCK1_CTRL, reg 822 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_BUCK2_CTRL, reg 846 drivers/regulator/bd718x7-regulator.c .reg = BD71837_REG_BUCK3_CTRL, reg 870 drivers/regulator/bd718x7-regulator.c .reg = BD71837_REG_BUCK4_CTRL, reg 897 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_1ST_NODVS_BUCK_CTRL, reg 921 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_2ND_NODVS_BUCK_CTRL, reg 943 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_3RD_NODVS_BUCK_CTRL, reg 967 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_4TH_NODVS_BUCK_CTRL, reg 993 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_LDO1_VOLT, reg 1015 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_LDO2_VOLT, reg 1038 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_LDO3_VOLT, reg 1061 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_LDO4_VOLT, reg 1086 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_LDO5_VOLT, reg 1113 drivers/regulator/bd718x7-regulator.c .reg = BD718XX_REG_LDO6_VOLT, reg 1138 drivers/regulator/bd718x7-regulator.c .reg = BD71837_REG_LDO7_VOLT, reg 1257 drivers/regulator/bd718x7-regulator.c err = regmap_update_bits(mfd->chip.regmap, r->init.reg, reg 1268 drivers/regulator/bd718x7-regulator.c r->additional_inits[j].reg, reg 105 drivers/regulator/cpcap-regulator.c #define CPCAP_REG(_ID, reg, assignment_reg, assignment_mask, val_tbl, \ reg 118 drivers/regulator/cpcap-regulator.c .vsel_reg = (reg), \ reg 120 drivers/regulator/cpcap-regulator.c .enable_reg = (reg), \ reg 132 drivers/regulator/cpcap-regulator.c struct regmap *reg; reg 523 drivers/regulator/cpcap-regulator.c ddata->reg = dev_get_regmap(pdev->dev.parent, NULL); reg 524 drivers/regulator/cpcap-regulator.c if (!ddata->reg) reg 533 drivers/regulator/cpcap-regulator.c config.regmap = ddata->reg; reg 50 drivers/regulator/da9055-regulator.c int reg; reg 63 drivers/regulator/da9055-regulator.c int reg; reg 88 drivers/regulator/da9055-regulator.c ret = da9055_reg_read(regulator->da9055, info->mode.reg); reg 126 drivers/regulator/da9055-regulator.c return da9055_reg_update(regulator->da9055, info->mode.reg, reg 180 drivers/regulator/da9055-regulator.c ret = da9055_reg_read(regulator->da9055, info->conf.reg); reg 212 drivers/regulator/da9055-regulator.c ret = da9055_reg_update(regulator->da9055, info->conf.reg, reg 227 drivers/regulator/da9055-regulator.c ret = da9055_reg_read(regulator->da9055, info->conf.reg); reg 251 drivers/regulator/da9055-regulator.c ret = da9055_reg_update(regulator->da9055, info->conf.reg, reg 272 drivers/regulator/da9055-regulator.c return da9055_reg_update(regulator->da9055, info->conf.reg, reg 285 drivers/regulator/da9055-regulator.c return da9055_reg_update(regulator->da9055, info->conf.reg, reg 349 drivers/regulator/da9055-regulator.c .reg = DA9055_REG_BCORE_CONT + DA9055_ID_##_id, \ reg 383 drivers/regulator/da9055-regulator.c .reg = DA9055_REG_BCORE_CONT + DA9055_ID_##_id, \ reg 394 drivers/regulator/da9055-regulator.c .reg = DA9055_REG_BCORE_MODE,\ reg 446 drivers/regulator/da9055-regulator.c ret = da9055_reg_update(regulator->da9055, info->conf.reg, reg 474 drivers/regulator/da9055-regulator.c ret = da9055_reg_update(regulator->da9055, info->conf.reg, reg 896 drivers/regulator/da9062-regulator.c if (regl->info->oc_event.reg != DA9062AA_STATUS_D) reg 955 drivers/regulator/da9062-regulator.c if (regl->info->mode.reg) { reg 964 drivers/regulator/da9062-regulator.c if (regl->info->suspend.reg) { reg 973 drivers/regulator/da9062-regulator.c if (regl->info->sleep.reg) { reg 982 drivers/regulator/da9062-regulator.c if (regl->info->suspend_sleep.reg) { reg 607 drivers/regulator/da9063-regulator.c if (regl->info->oc_event.reg != DA9063_REG_STATUS_D) reg 816 drivers/regulator/da9063-regulator.c if (regl->info->mode.reg) { reg 823 drivers/regulator/da9063-regulator.c if (regl->info->suspend.reg) { reg 830 drivers/regulator/da9063-regulator.c if (regl->info->sleep.reg) { reg 837 drivers/regulator/da9063-regulator.c if (regl->info->suspend_sleep.reg) { reg 26 drivers/regulator/lp3971.c static u8 lp3971_reg_read(struct lp3971 *lp3971, u8 reg); reg 27 drivers/regulator/lp3971.c static int lp3971_set_bits(struct lp3971 *lp3971, u8 reg, u16 mask, u16 val); reg 139 drivers/regulator/lp3971.c u16 val, reg; reg 141 drivers/regulator/lp3971.c reg = lp3971_reg_read(lp3971, LP3971_LDO_VOL_CONTR_REG(ldo)); reg 142 drivers/regulator/lp3971.c val = (reg >> LDO_VOL_CONTR_SHIFT(ldo)) & LDO_VOL_CONTR_MASK; reg 201 drivers/regulator/lp3971.c u16 reg; reg 203 drivers/regulator/lp3971.c reg = lp3971_reg_read(lp3971, LP3971_BUCK_TARGET_VOL1_REG(buck)); reg 204 drivers/regulator/lp3971.c reg &= BUCK_TARGET_VOL_MASK; reg 206 drivers/regulator/lp3971.c return reg; reg 317 drivers/regulator/lp3971.c static int lp3971_i2c_read(struct i2c_client *i2c, char reg, int count, reg 324 drivers/regulator/lp3971.c ret = i2c_smbus_read_byte_data(i2c, reg); reg 332 drivers/regulator/lp3971.c static int lp3971_i2c_write(struct i2c_client *i2c, char reg, int count, reg 337 drivers/regulator/lp3971.c return i2c_smbus_write_byte_data(i2c, reg, *src); reg 340 drivers/regulator/lp3971.c static u8 lp3971_reg_read(struct lp3971 *lp3971, u8 reg) reg 346 drivers/regulator/lp3971.c lp3971_i2c_read(lp3971->i2c, reg, 1, &val); reg 348 drivers/regulator/lp3971.c dev_dbg(lp3971->dev, "reg read 0x%02x -> 0x%02x\n", (int)reg, reg 356 drivers/regulator/lp3971.c static int lp3971_set_bits(struct lp3971 *lp3971, u8 reg, u16 mask, u16 val) reg 363 drivers/regulator/lp3971.c ret = lp3971_i2c_read(lp3971->i2c, reg, 1, &tmp); reg 366 drivers/regulator/lp3971.c ret = lp3971_i2c_write(lp3971->i2c, reg, 1, &tmp); reg 367 drivers/regulator/lp3971.c dev_dbg(lp3971->dev, "reg write 0x%02x -> 0x%02x\n", (int)reg, reg 383 drivers/regulator/lp3971.c struct lp3971_regulator_subdev *reg = &pdata->regulators[i]; reg 387 drivers/regulator/lp3971.c config.init_data = reg->initdata; reg 391 drivers/regulator/lp3971.c ®ulators[reg->id], &config); reg 163 drivers/regulator/lp3972.c static int lp3972_i2c_read(struct i2c_client *i2c, char reg, int count, reg 170 drivers/regulator/lp3972.c ret = i2c_smbus_read_byte_data(i2c, reg); reg 178 drivers/regulator/lp3972.c static int lp3972_i2c_write(struct i2c_client *i2c, char reg, int count, reg 183 drivers/regulator/lp3972.c return i2c_smbus_write_byte_data(i2c, reg, *src); reg 186 drivers/regulator/lp3972.c static u8 lp3972_reg_read(struct lp3972 *lp3972, u8 reg) reg 192 drivers/regulator/lp3972.c lp3972_i2c_read(lp3972->i2c, reg, 1, &val); reg 194 drivers/regulator/lp3972.c dev_dbg(lp3972->dev, "reg read 0x%02x -> 0x%02x\n", (int)reg, reg 202 drivers/regulator/lp3972.c static int lp3972_set_bits(struct lp3972 *lp3972, u8 reg, u16 mask, u16 val) reg 209 drivers/regulator/lp3972.c ret = lp3972_i2c_read(lp3972->i2c, reg, 1, &tmp); reg 212 drivers/regulator/lp3972.c ret = lp3972_i2c_write(lp3972->i2c, reg, 1, &tmp); reg 213 drivers/regulator/lp3972.c dev_dbg(lp3972->dev, "reg write 0x%02x -> 0x%02x\n", (int)reg, reg 257 drivers/regulator/lp3972.c u16 val, reg; reg 259 drivers/regulator/lp3972.c reg = lp3972_reg_read(lp3972, LP3972_LDO_VOL_CONTR_REG(ldo)); reg 260 drivers/regulator/lp3972.c val = (reg >> LP3972_LDO_VOL_CONTR_SHIFT(ldo)) & mask; reg 353 drivers/regulator/lp3972.c u16 reg; reg 355 drivers/regulator/lp3972.c reg = lp3972_reg_read(lp3972, LP3972_BUCK_VOL1_REG(buck)); reg 356 drivers/regulator/lp3972.c reg &= LP3972_BUCK_VOL_MASK; reg 358 drivers/regulator/lp3972.c return reg; reg 477 drivers/regulator/lp3972.c struct lp3972_regulator_subdev *reg = &pdata->regulators[i]; reg 482 drivers/regulator/lp3972.c config.init_data = reg->initdata; reg 486 drivers/regulator/lp3972.c ®ulators[reg->id], &config); reg 82 drivers/regulator/lp873x-regulator.c unsigned int reg; reg 86 drivers/regulator/lp873x-regulator.c reg = 7; reg 88 drivers/regulator/lp873x-regulator.c reg = 6; reg 90 drivers/regulator/lp873x-regulator.c reg = 5; reg 92 drivers/regulator/lp873x-regulator.c reg = 4; reg 94 drivers/regulator/lp873x-regulator.c reg = 3; reg 96 drivers/regulator/lp873x-regulator.c reg = 2; reg 98 drivers/regulator/lp873x-regulator.c reg = 1; reg 100 drivers/regulator/lp873x-regulator.c reg = 0; reg 104 drivers/regulator/lp873x-regulator.c reg << __ffs(LP873X_BUCK0_CTRL_2_BUCK0_SLEW_RATE)); reg 110 drivers/regulator/lp873x-regulator.c rdev->constraints->ramp_delay = lp873x_buck_ramp_delay[reg]; reg 58 drivers/regulator/lp8755.c static int lp8755_read(struct lp8755_chip *pchip, unsigned int reg, reg 61 drivers/regulator/lp8755.c return regmap_read(pchip->regmap, reg, val); reg 70 drivers/regulator/lp8755.c static int lp8755_write(struct lp8755_chip *pchip, unsigned int reg, reg 73 drivers/regulator/lp8755.c return regmap_write(pchip->regmap, reg, val); reg 83 drivers/regulator/lp8755.c static int lp8755_update_bits(struct lp8755_chip *pchip, unsigned int reg, reg 86 drivers/regulator/lp8755.c return regmap_update_bits(pchip->regmap, reg, mask, val); reg 68 drivers/regulator/lp87565-regulator.c unsigned int reg; reg 72 drivers/regulator/lp87565-regulator.c reg = 7; reg 74 drivers/regulator/lp87565-regulator.c reg = 6; reg 76 drivers/regulator/lp87565-regulator.c reg = 5; reg 78 drivers/regulator/lp87565-regulator.c reg = 4; reg 80 drivers/regulator/lp87565-regulator.c reg = 3; reg 82 drivers/regulator/lp87565-regulator.c reg = 2; reg 84 drivers/regulator/lp87565-regulator.c reg = 1; reg 86 drivers/regulator/lp87565-regulator.c reg = 0; reg 90 drivers/regulator/lp87565-regulator.c reg << __ffs(LP87565_BUCK_CTRL_2_SLEW_RATE)); reg 96 drivers/regulator/lp87565-regulator.c rdev->constraints->ramp_delay = lp87565_buck_ramp_delay[reg]; reg 264 drivers/regulator/ltc3589.c static bool ltc3589_writeable_reg(struct device *dev, unsigned int reg) reg 266 drivers/regulator/ltc3589.c switch (reg) { reg 287 drivers/regulator/ltc3589.c static bool ltc3589_readable_reg(struct device *dev, unsigned int reg) reg 289 drivers/regulator/ltc3589.c switch (reg) { reg 310 drivers/regulator/ltc3589.c static bool ltc3589_volatile_reg(struct device *dev, unsigned int reg) reg 312 drivers/regulator/ltc3589.c switch (reg) { reg 235 drivers/regulator/ltc3676.c static bool ltc3676_readable_writeable_reg(struct device *dev, unsigned int reg) reg 237 drivers/regulator/ltc3676.c switch (reg) { reg 246 drivers/regulator/ltc3676.c static bool ltc3676_volatile_reg(struct device *dev, unsigned int reg) reg 248 drivers/regulator/ltc3676.c switch (reg) { reg 60 drivers/regulator/max77693-regulator.c unsigned int reg, sel; reg 64 drivers/regulator/max77693-regulator.c ret = regmap_read(rdev->regmap, reg_data->linear_reg, ®); reg 68 drivers/regulator/max77693-regulator.c sel = reg & reg_data->linear_mask; reg 73 drivers/regulator/max8660.c static int max8660_write(struct max8660 *max8660, u8 reg, u8 mask, u8 val) reg 80 drivers/regulator/max8660.c u8 reg_val = (max8660->shadow_regs[reg] & mask) | val; reg 83 drivers/regulator/max8660.c max8660_addresses[reg], reg_val); reg 86 drivers/regulator/max8660.c max8660_addresses[reg], reg_val); reg 88 drivers/regulator/max8660.c max8660->shadow_regs[reg] = reg_val; reg 126 drivers/regulator/max8660.c u8 reg = (rdev_get_id(rdev) == MAX8660_V3) ? MAX8660_ADTV2 : MAX8660_SDTV2; reg 127 drivers/regulator/max8660.c u8 selector = max8660->shadow_regs[reg]; reg 136 drivers/regulator/max8660.c u8 reg, bits; reg 139 drivers/regulator/max8660.c reg = (rdev_get_id(rdev) == MAX8660_V3) ? MAX8660_ADTV2 : MAX8660_SDTV2; reg 140 drivers/regulator/max8660.c ret = max8660_write(max8660, reg, 0, selector); reg 44 drivers/regulator/max8952.c static int max8952_read_reg(struct max8952_data *max8952, u8 reg) reg 46 drivers/regulator/max8952.c int ret = i2c_smbus_read_byte_data(max8952->client, reg); reg 55 drivers/regulator/max8952.c u8 reg, u8 value) reg 57 drivers/regulator/max8952.c return i2c_smbus_write_byte_data(max8952->client, reg, value); reg 169 drivers/regulator/max8997-regulator.c int *reg, int *mask, int *pattern) reg 175 drivers/regulator/max8997-regulator.c *reg = MAX8997_REG_LDO1CTRL + (rid - MAX8997_LDO1); reg 180 drivers/regulator/max8997-regulator.c *reg = MAX8997_REG_BUCK1CTRL; reg 185 drivers/regulator/max8997-regulator.c *reg = MAX8997_REG_BUCK2CTRL; reg 190 drivers/regulator/max8997-regulator.c *reg = MAX8997_REG_BUCK3CTRL; reg 195 drivers/regulator/max8997-regulator.c *reg = MAX8997_REG_BUCK4CTRL; reg 200 drivers/regulator/max8997-regulator.c *reg = MAX8997_REG_BUCK5CTRL; reg 205 drivers/regulator/max8997-regulator.c *reg = MAX8997_REG_BUCK6CTRL; reg 210 drivers/regulator/max8997-regulator.c *reg = MAX8997_REG_BUCK7CTRL; reg 215 drivers/regulator/max8997-regulator.c *reg = MAX8997_REG_MAINCON1; reg 220 drivers/regulator/max8997-regulator.c *reg = MAX8997_REG_MBCCTRL1; reg 225 drivers/regulator/max8997-regulator.c *reg = MAX8997_REG_SAFEOUTCTRL; reg 230 drivers/regulator/max8997-regulator.c *reg = MAX8997_REG_MBCCTRL2; reg 246 drivers/regulator/max8997-regulator.c int ret, reg, mask, pattern; reg 249 drivers/regulator/max8997-regulator.c ret = max8997_get_enable_register(rdev, ®, &mask, &pattern); reg 253 drivers/regulator/max8997-regulator.c ret = max8997_read_reg(i2c, reg, &val); reg 264 drivers/regulator/max8997-regulator.c int ret, reg, mask, pattern; reg 266 drivers/regulator/max8997-regulator.c ret = max8997_get_enable_register(rdev, ®, &mask, &pattern); reg 270 drivers/regulator/max8997-regulator.c return max8997_update_reg(i2c, reg, pattern, mask); reg 277 drivers/regulator/max8997-regulator.c int ret, reg, mask, pattern; reg 279 drivers/regulator/max8997-regulator.c ret = max8997_get_enable_register(rdev, ®, &mask, &pattern); reg 283 drivers/regulator/max8997-regulator.c return max8997_update_reg(i2c, reg, ~pattern, mask); reg 291 drivers/regulator/max8997-regulator.c int reg, shift = 0, mask = 0x3f; reg 295 drivers/regulator/max8997-regulator.c reg = MAX8997_REG_LDO1CTRL + (rid - MAX8997_LDO1); reg 298 drivers/regulator/max8997-regulator.c reg = MAX8997_REG_BUCK1DVS1; reg 300 drivers/regulator/max8997-regulator.c reg += max8997->buck125_gpioindex; reg 303 drivers/regulator/max8997-regulator.c reg = MAX8997_REG_BUCK2DVS1; reg 305 drivers/regulator/max8997-regulator.c reg += max8997->buck125_gpioindex; reg 308 drivers/regulator/max8997-regulator.c reg = MAX8997_REG_BUCK3DVS; reg 311 drivers/regulator/max8997-regulator.c reg = MAX8997_REG_BUCK4DVS; reg 314 drivers/regulator/max8997-regulator.c reg = MAX8997_REG_BUCK5DVS1; reg 316 drivers/regulator/max8997-regulator.c reg += max8997->buck125_gpioindex; reg 319 drivers/regulator/max8997-regulator.c reg = MAX8997_REG_BUCK7DVS; reg 322 drivers/regulator/max8997-regulator.c reg = MAX8997_REG_SAFEOUTCTRL; reg 327 drivers/regulator/max8997-regulator.c reg = MAX8997_REG_MBCCTRL3; reg 332 drivers/regulator/max8997-regulator.c reg = MAX8997_REG_MBCCTRL4; reg 337 drivers/regulator/max8997-regulator.c reg = MAX8997_REG_MBCCTRL5; reg 345 drivers/regulator/max8997-regulator.c *_reg = reg; reg 356 drivers/regulator/max8997-regulator.c int reg, shift, mask, ret; reg 359 drivers/regulator/max8997-regulator.c ret = max8997_get_voltage_register(rdev, ®, &shift, &mask); reg 363 drivers/regulator/max8997-regulator.c ret = max8997_read_reg(i2c, reg, &val); reg 403 drivers/regulator/max8997-regulator.c int reg, shift = 0, mask, ret = 0; reg 409 drivers/regulator/max8997-regulator.c ret = max8997_get_voltage_register(rdev, ®, &shift, &mask); reg 439 drivers/regulator/max8997-regulator.c ret = max8997_update_reg(i2c, reg, val << shift, mask); reg 455 drivers/regulator/max8997-regulator.c int i, reg, shift, mask, ret; reg 480 drivers/regulator/max8997-regulator.c ret = max8997_get_voltage_register(rdev, ®, &shift, &mask); reg 484 drivers/regulator/max8997-regulator.c ret = max8997_update_reg(i2c, reg, i << shift, mask << shift); reg 696 drivers/regulator/max8997-regulator.c int reg, shift = 0, mask, ret; reg 701 drivers/regulator/max8997-regulator.c ret = max8997_get_voltage_register(rdev, ®, &shift, &mask); reg 705 drivers/regulator/max8997-regulator.c return max8997_update_reg(i2c, reg, selector << shift, mask << shift); reg 712 drivers/regulator/max8997-regulator.c int ret, reg, mask, pattern; reg 715 drivers/regulator/max8997-regulator.c ret = max8997_get_enable_register(rdev, ®, &mask, &pattern); reg 719 drivers/regulator/max8997-regulator.c max8997_read_reg(i2c, reg, &max8997->saved_states[rid]); reg 726 drivers/regulator/max8997-regulator.c return max8997_update_reg(i2c, reg, 0x40, mask); reg 732 drivers/regulator/max8997-regulator.c return max8997_update_reg(i2c, reg, ~pattern, mask); reg 37 drivers/regulator/max8998.c int *reg, int *shift) reg 43 drivers/regulator/max8998.c *reg = MAX8998_REG_ONOFF1; reg 47 drivers/regulator/max8998.c *reg = MAX8998_REG_ONOFF2; reg 51 drivers/regulator/max8998.c *reg = MAX8998_REG_ONOFF3; reg 55 drivers/regulator/max8998.c *reg = MAX8998_REG_ONOFF1; reg 59 drivers/regulator/max8998.c *reg = MAX8998_REG_ONOFF4; reg 63 drivers/regulator/max8998.c *reg = MAX8998_REG_CHGR2; reg 77 drivers/regulator/max8998.c int ret, reg, shift = 8; reg 80 drivers/regulator/max8998.c ret = max8998_get_enable_register(rdev, ®, &shift); reg 84 drivers/regulator/max8998.c ret = max8998_read_reg(i2c, reg, &val); reg 95 drivers/regulator/max8998.c int reg, shift = 8, ret; reg 97 drivers/regulator/max8998.c ret = max8998_get_enable_register(rdev, ®, &shift); reg 101 drivers/regulator/max8998.c return max8998_update_reg(i2c, reg, 1<<shift, 1<<shift); reg 108 drivers/regulator/max8998.c int reg, shift = 8, ret; reg 110 drivers/regulator/max8998.c ret = max8998_get_enable_register(rdev, ®, &shift); reg 114 drivers/regulator/max8998.c return max8998_update_reg(i2c, reg, 0, 1<<shift); reg 122 drivers/regulator/max8998.c int reg, shift = 0, mask = 0xff; reg 126 drivers/regulator/max8998.c reg = MAX8998_REG_LDO2_LDO3; reg 134 drivers/regulator/max8998.c reg = MAX8998_REG_LDO4 + (ldo - MAX8998_LDO4); reg 137 drivers/regulator/max8998.c reg = MAX8998_REG_LDO8_LDO9; reg 145 drivers/regulator/max8998.c reg = MAX8998_REG_LDO10_LDO11; reg 155 drivers/regulator/max8998.c reg = MAX8998_REG_LDO12 + (ldo - MAX8998_LDO12); reg 158 drivers/regulator/max8998.c reg = MAX8998_REG_BUCK1_VOLTAGE1 + max8998->buck1_idx; reg 161 drivers/regulator/max8998.c reg = MAX8998_REG_BUCK2_VOLTAGE1 + max8998->buck2_idx; reg 164 drivers/regulator/max8998.c reg = MAX8998_REG_BUCK3; reg 167 drivers/regulator/max8998.c reg = MAX8998_REG_BUCK4; reg 173 drivers/regulator/max8998.c *_reg = reg; reg 184 drivers/regulator/max8998.c int reg, shift = 0, mask, ret; reg 187 drivers/regulator/max8998.c ret = max8998_get_voltage_register(rdev, ®, &shift, &mask); reg 191 drivers/regulator/max8998.c ret = max8998_read_reg(i2c, reg, &val); reg 206 drivers/regulator/max8998.c int reg, shift = 0, mask, ret; reg 208 drivers/regulator/max8998.c ret = max8998_get_voltage_register(rdev, ®, &shift, &mask); reg 212 drivers/regulator/max8998.c ret = max8998_update_reg(i2c, reg, selector<<shift, mask<<shift); reg 235 drivers/regulator/max8998.c int reg, shift = 0, mask, ret, j; reg 238 drivers/regulator/max8998.c ret = max8998_get_voltage_register(rdev, ®, &shift, &mask); reg 272 drivers/regulator/max8998.c ret = max8998_get_voltage_register(rdev, ®, reg 275 drivers/regulator/max8998.c ret = max8998_write_reg(i2c, reg, selector); reg 285 drivers/regulator/max8998.c ret = max8998_write_reg(i2c, reg, selector); reg 309 drivers/regulator/max8998.c ®, &shift, &mask); reg 310 drivers/regulator/max8998.c ret = max8998_write_reg(i2c, reg, selector); reg 317 drivers/regulator/max8998.c ret = max8998_write_reg(i2c, reg, selector); reg 323 drivers/regulator/max8998.c ret = max8998_update_reg(i2c, reg, selector<<shift, reg 231 drivers/regulator/mc13783-regulator.c #define MC13783_DEFINE(prefix, name, node, reg, vsel_reg, voltages) \ reg 232 drivers/regulator/mc13783-regulator.c MC13xxx_DEFINE(MC13783_REG_, name, node, reg, vsel_reg, voltages, \ reg 235 drivers/regulator/mc13783-regulator.c #define MC13783_FIXED_DEFINE(prefix, name, node, reg, voltages) \ reg 236 drivers/regulator/mc13783-regulator.c MC13xxx_FIXED_DEFINE(MC13783_REG_, name, node, reg, voltages, \ reg 239 drivers/regulator/mc13783-regulator.c #define MC13783_GPO_DEFINE(prefix, name, node, reg, voltages) \ reg 240 drivers/regulator/mc13783-regulator.c MC13xxx_GPO_DEFINE(MC13783_REG_, name, node, reg, voltages, \ reg 369 drivers/regulator/mc13783-regulator.c ret = mc13xxx_reg_read(priv->mc13xxx, mc13xxx_regulators[id].reg, &val); reg 249 drivers/regulator/mc13892-regulator.c #define MC13892_FIXED_DEFINE(name, node, reg, voltages) \ reg 250 drivers/regulator/mc13892-regulator.c MC13xxx_FIXED_DEFINE(MC13892_, name, node, reg, voltages, \ reg 253 drivers/regulator/mc13892-regulator.c #define MC13892_GPO_DEFINE(name, node, reg, voltages) \ reg 254 drivers/regulator/mc13892-regulator.c MC13xxx_GPO_DEFINE(MC13892_, name, node, reg, voltages, \ reg 257 drivers/regulator/mc13892-regulator.c #define MC13892_SW_DEFINE(name, node, reg, vsel_reg, voltages) \ reg 258 drivers/regulator/mc13892-regulator.c MC13xxx_DEFINE(MC13892_, name, node, reg, vsel_reg, voltages, \ reg 261 drivers/regulator/mc13892-regulator.c #define MC13892_DEFINE_REGU(name, node, reg, vsel_reg, voltages) \ reg 262 drivers/regulator/mc13892-regulator.c MC13xxx_DEFINE(MC13892_, name, node, reg, vsel_reg, voltages, \ reg 375 drivers/regulator/mc13892-regulator.c ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val); reg 499 drivers/regulator/mc13892-regulator.c ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13892_regulators[id].reg, reg 513 drivers/regulator/mc13892-regulator.c ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val); reg 35 drivers/regulator/mc13xxx-regulator-core.c return mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].reg, reg 48 drivers/regulator/mc13xxx-regulator-core.c return mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].reg, reg 59 drivers/regulator/mc13xxx-regulator-core.c ret = mc13xxx_reg_read(priv->mc13xxx, mc13xxx_regulators[id].reg, &val); reg 15 drivers/regulator/mc13xxx.h int reg; reg 66 drivers/regulator/mc13xxx.h .reg = prefix ## _reg, \ reg 84 drivers/regulator/mc13xxx.h .reg = prefix ## _reg, \ reg 99 drivers/regulator/mc13xxx.h .reg = prefix ## _reg, \ reg 153 drivers/regulator/mcp16502.c int reg = MCP16502_BASE(rdev_get_id(rdev)); reg 157 drivers/regulator/mcp16502.c return reg + MCP16502_OFFSET_MODE_A; reg 159 drivers/regulator/mcp16502.c return reg + MCP16502_OFFSET_MODE_LPM; reg 161 drivers/regulator/mcp16502.c return reg + MCP16502_OFFSET_MODE_HIB; reg 179 drivers/regulator/mcp16502.c int ret, reg; reg 181 drivers/regulator/mcp16502.c reg = mcp16502_get_reg(rdev, MCP16502_OPMODE_ACTIVE); reg 182 drivers/regulator/mcp16502.c if (reg < 0) reg 183 drivers/regulator/mcp16502.c return reg; reg 185 drivers/regulator/mcp16502.c ret = regmap_read(rdev->regmap, reg, &val); reg 210 drivers/regulator/mcp16502.c int reg; reg 212 drivers/regulator/mcp16502.c reg = mcp16502_get_reg(rdev, op_mode); reg 213 drivers/regulator/mcp16502.c if (reg < 0) reg 214 drivers/regulator/mcp16502.c return reg; reg 227 drivers/regulator/mcp16502.c reg = regmap_update_bits(rdev->regmap, reg, MCP16502_MODE, val); reg 228 drivers/regulator/mcp16502.c return reg; reg 289 drivers/regulator/mcp16502.c int reg = mcp16502_suspend_get_target_reg(rdev); reg 294 drivers/regulator/mcp16502.c if (reg < 0) reg 295 drivers/regulator/mcp16502.c return reg; reg 297 drivers/regulator/mcp16502.c return regmap_update_bits(rdev->regmap, reg, MCP16502_VSEL, sel); reg 325 drivers/regulator/mcp16502.c int reg = mcp16502_suspend_get_target_reg(rdev); reg 327 drivers/regulator/mcp16502.c if (reg < 0) reg 328 drivers/regulator/mcp16502.c return reg; reg 330 drivers/regulator/mcp16502.c return regmap_update_bits(rdev->regmap, reg, MCP16502_EN, MCP16502_EN); reg 338 drivers/regulator/mcp16502.c int reg = mcp16502_suspend_get_target_reg(rdev); reg 340 drivers/regulator/mcp16502.c if (reg < 0) reg 341 drivers/regulator/mcp16502.c return reg; reg 343 drivers/regulator/mcp16502.c return regmap_update_bits(rdev->regmap, reg, MCP16502_EN, 0); reg 398 drivers/regulator/palmas-regulator.c static int palmas_smps_read(struct palmas *palmas, unsigned int reg, reg 403 drivers/regulator/palmas-regulator.c addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg); reg 408 drivers/regulator/palmas-regulator.c static int palmas_smps_write(struct palmas *palmas, unsigned int reg, reg 413 drivers/regulator/palmas-regulator.c addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg); reg 418 drivers/regulator/palmas-regulator.c static int palmas_ldo_read(struct palmas *palmas, unsigned int reg, reg 423 drivers/regulator/palmas-regulator.c addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg); reg 428 drivers/regulator/palmas-regulator.c static int palmas_ldo_write(struct palmas *palmas, unsigned int reg, reg 433 drivers/regulator/palmas-regulator.c addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg); reg 445 drivers/regulator/palmas-regulator.c unsigned int reg; reg 448 drivers/regulator/palmas-regulator.c ret = palmas_smps_read(pmic->palmas, rinfo->ctrl_addr, ®); reg 452 drivers/regulator/palmas-regulator.c reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; reg 454 drivers/regulator/palmas-regulator.c if (reg == SMPS_CTRL_MODE_OFF) reg 459 drivers/regulator/palmas-regulator.c reg |= SMPS_CTRL_MODE_ON; reg 462 drivers/regulator/palmas-regulator.c reg |= SMPS_CTRL_MODE_ECO; reg 465 drivers/regulator/palmas-regulator.c reg |= SMPS_CTRL_MODE_PWM; reg 471 drivers/regulator/palmas-regulator.c pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; reg 473 drivers/regulator/palmas-regulator.c palmas_smps_write(pmic->palmas, rinfo->ctrl_addr, reg); reg 485 drivers/regulator/palmas-regulator.c unsigned int reg; reg 487 drivers/regulator/palmas-regulator.c reg = pmic->current_reg_mode[id] & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; reg 489 drivers/regulator/palmas-regulator.c switch (reg) { reg 508 drivers/regulator/palmas-regulator.c unsigned int reg = 0; reg 519 drivers/regulator/palmas-regulator.c reg = 0; reg 521 drivers/regulator/palmas-regulator.c reg = 3; reg 523 drivers/regulator/palmas-regulator.c reg = 2; reg 525 drivers/regulator/palmas-regulator.c reg = 1; reg 527 drivers/regulator/palmas-regulator.c ret = palmas_smps_write(pmic->palmas, rinfo->tstep_addr, reg); reg 533 drivers/regulator/palmas-regulator.c pmic->ramp_delay[id] = palmas_smps_ramp_delay[reg]; reg 602 drivers/regulator/palmas-regulator.c unsigned int reg; reg 604 drivers/regulator/palmas-regulator.c palmas_ldo_read(pmic->palmas, rinfo->ctrl_addr, ®); reg 606 drivers/regulator/palmas-regulator.c reg &= PALMAS_LDO1_CTRL_STATUS; reg 608 drivers/regulator/palmas-regulator.c return !!(reg); reg 698 drivers/regulator/palmas-regulator.c unsigned int reg; reg 704 drivers/regulator/palmas-regulator.c ret = palmas_smps_read(palmas, addr, ®); reg 711 drivers/regulator/palmas-regulator.c reg &= ~PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK; reg 713 drivers/regulator/palmas-regulator.c reg |= reg_init->mode_sleep << reg 718 drivers/regulator/palmas-regulator.c reg |= PALMAS_SMPS12_CTRL_WR_S; reg 720 drivers/regulator/palmas-regulator.c reg &= ~PALMAS_SMPS12_CTRL_WR_S; reg 723 drivers/regulator/palmas-regulator.c reg |= PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN; reg 725 drivers/regulator/palmas-regulator.c reg &= ~PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN; reg 727 drivers/regulator/palmas-regulator.c reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK; reg 729 drivers/regulator/palmas-regulator.c reg |= reg_init->mode_sleep << reg 733 drivers/regulator/palmas-regulator.c ret = palmas_smps_write(palmas, addr, reg); reg 739 drivers/regulator/palmas-regulator.c reg = reg_init->vsel; reg 741 drivers/regulator/palmas-regulator.c ret = palmas_smps_write(palmas, rinfo->vsel_addr, reg); reg 749 drivers/regulator/palmas-regulator.c ret = palmas_smps_read(palmas, addr, ®); reg 753 drivers/regulator/palmas-regulator.c if (!(reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK)) { reg 754 drivers/regulator/palmas-regulator.c reg |= SMPS_CTRL_MODE_ON; reg 755 drivers/regulator/palmas-regulator.c ret = palmas_smps_write(palmas, addr, reg); reg 767 drivers/regulator/palmas-regulator.c unsigned int reg; reg 775 drivers/regulator/palmas-regulator.c ret = palmas_ldo_read(palmas, addr, ®); reg 780 drivers/regulator/palmas-regulator.c reg |= PALMAS_LDO1_CTRL_WR_S; reg 782 drivers/regulator/palmas-regulator.c reg &= ~PALMAS_LDO1_CTRL_WR_S; reg 785 drivers/regulator/palmas-regulator.c reg |= PALMAS_LDO1_CTRL_MODE_SLEEP; reg 787 drivers/regulator/palmas-regulator.c reg &= ~PALMAS_LDO1_CTRL_MODE_SLEEP; reg 789 drivers/regulator/palmas-regulator.c ret = palmas_ldo_write(palmas, addr, reg); reg 849 drivers/regulator/palmas-regulator.c unsigned int reg; reg 858 drivers/regulator/palmas-regulator.c ret = palmas_ldo_read(palmas, addr, ®); reg 864 drivers/regulator/palmas-regulator.c reg |= PALMAS_LDO8_CTRL_LDO_TRACKING_EN; reg 865 drivers/regulator/palmas-regulator.c ret = palmas_ldo_write(palmas, addr, reg); reg 876 drivers/regulator/palmas-regulator.c ret = palmas_ldo_read(palmas, addr, ®); reg 882 drivers/regulator/palmas-regulator.c reg = (reg << 1) & PALMAS_LDO8_VOLTAGE_VSEL_MASK; reg 883 drivers/regulator/palmas-regulator.c ret = palmas_ldo_write(palmas, addr, reg); reg 1122 drivers/regulator/palmas-regulator.c unsigned int addr, reg; reg 1173 drivers/regulator/palmas-regulator.c ret = palmas_smps_read(pmic->palmas, addr, ®); reg 1179 drivers/regulator/palmas-regulator.c desc->ramp_delay = palmas_smps_ramp_delay[reg & 0x3]; reg 1228 drivers/regulator/palmas-regulator.c ret = palmas_smps_read(pmic->palmas, addr, ®); reg 1231 drivers/regulator/palmas-regulator.c if (reg & PALMAS_SMPS12_VOLTAGE_RANGE) reg 1249 drivers/regulator/palmas-regulator.c ret = palmas_smps_read(pmic->palmas, addr, ®); reg 1252 drivers/regulator/palmas-regulator.c pmic->current_reg_mode[id] = reg & reg 1292 drivers/regulator/palmas-regulator.c unsigned int addr, reg; reg 1332 drivers/regulator/palmas-regulator.c ret = palmas_smps_read(pmic->palmas, addr, ®); reg 1335 drivers/regulator/palmas-regulator.c if (reg & TPS65917_SMPS1_VOLTAGE_RANGE) reg 1355 drivers/regulator/palmas-regulator.c ret = palmas_smps_read(pmic->palmas, addr, ®); reg 1358 drivers/regulator/palmas-regulator.c pmic->current_reg_mode[id] = reg & reg 1606 drivers/regulator/palmas-regulator.c unsigned int reg; reg 1638 drivers/regulator/palmas-regulator.c ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, ®); reg 1642 drivers/regulator/palmas-regulator.c if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN) { reg 1647 drivers/regulator/palmas-regulator.c if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN) reg 94 drivers/regulator/pcap-regulator.c const u8 reg; reg 105 drivers/regulator/pcap-regulator.c .reg = _reg, \ reg 155 drivers/regulator/pcap-regulator.c return ezx_pcap_set_bits(pcap, vreg->reg, reg 169 drivers/regulator/pcap-regulator.c ezx_pcap_read(pcap, vreg->reg, &tmp); reg 182 drivers/regulator/pcap-regulator.c return ezx_pcap_set_bits(pcap, vreg->reg, 1 << vreg->en, 1 << vreg->en); reg 193 drivers/regulator/pcap-regulator.c return ezx_pcap_set_bits(pcap, vreg->reg, 1 << vreg->en, 0); reg 205 drivers/regulator/pcap-regulator.c ezx_pcap_read(pcap, vreg->reg, &tmp); reg 44 drivers/regulator/qcom_rpm-regulator.c #define FORCE_MODE_IS_2_BITS(reg) \ reg 45 drivers/regulator/qcom_rpm-regulator.c (((reg)->parts->fm.mask >> (reg)->parts->fm.shift) == 3) reg 940 drivers/regulator/qcom_rpm-regulator.c const struct rpm_regulator_data *reg; reg 959 drivers/regulator/qcom_rpm-regulator.c for (reg = match->data; reg->name; reg++) { reg 964 drivers/regulator/qcom_rpm-regulator.c memcpy(vreg, reg->template, sizeof(*vreg)); reg 968 drivers/regulator/qcom_rpm-regulator.c vreg->resource = reg->resource; reg 974 drivers/regulator/qcom_rpm-regulator.c vreg->desc.name = reg->name; reg 975 drivers/regulator/qcom_rpm-regulator.c vreg->desc.supply_name = reg->supply; reg 976 drivers/regulator/qcom_rpm-regulator.c vreg->desc.of_match = reg->name; reg 983 drivers/regulator/qcom_rpm-regulator.c dev_err(&pdev->dev, "failed to register %s\n", reg->name); reg 781 drivers/regulator/qcom_smd-regulator.c const struct rpm_regulator_data *reg; reg 800 drivers/regulator/qcom_smd-regulator.c for (reg = match->data; reg->name; reg++) { reg 806 drivers/regulator/qcom_smd-regulator.c vreg->type = reg->type; reg 807 drivers/regulator/qcom_smd-regulator.c vreg->id = reg->id; reg 810 drivers/regulator/qcom_smd-regulator.c memcpy(&vreg->desc, reg->desc, sizeof(vreg->desc)); reg 815 drivers/regulator/qcom_smd-regulator.c vreg->desc.name = reg->name; reg 816 drivers/regulator/qcom_smd-regulator.c vreg->desc.supply_name = reg->supply; reg 817 drivers/regulator/qcom_smd-regulator.c vreg->desc.of_match = reg->name; reg 823 drivers/regulator/qcom_smd-regulator.c dev_err(&pdev->dev, "failed to register %s\n", reg->name); reg 568 drivers/regulator/qcom_spmi-regulator.c u8 reg = SPMI_VS_OCP_OVERRIDE; reg 570 drivers/regulator/qcom_spmi-regulator.c return spmi_vreg_write(vreg, SPMI_VS_REG_OCP, ®, 1); reg 983 drivers/regulator/qcom_spmi-regulator.c u8 reg; reg 985 drivers/regulator/qcom_spmi-regulator.c spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1); reg 987 drivers/regulator/qcom_spmi-regulator.c reg &= SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK; reg 989 drivers/regulator/qcom_spmi-regulator.c switch (reg) { reg 1002 drivers/regulator/qcom_spmi-regulator.c u8 reg; reg 1004 drivers/regulator/qcom_spmi-regulator.c spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1); reg 1006 drivers/regulator/qcom_spmi-regulator.c switch (reg) { reg 1099 drivers/regulator/qcom_spmi-regulator.c u8 reg; reg 1112 drivers/regulator/qcom_spmi-regulator.c reg = (ilim_uA - 1) / 500; reg 1113 drivers/regulator/qcom_spmi-regulator.c reg |= SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK; reg 1115 drivers/regulator/qcom_spmi-regulator.c return spmi_vreg_update_bits(vreg, current_reg, reg, mask); reg 1552 drivers/regulator/qcom_spmi-regulator.c u8 reg = 0; reg 1556 drivers/regulator/qcom_spmi-regulator.c ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, ®, 1); reg 1575 drivers/regulator/qcom_spmi-regulator.c step = reg & SPMI_FTSMPS_STEP_CTRL_STEP_MASK; reg 1578 drivers/regulator/qcom_spmi-regulator.c delay = reg & SPMI_FTSMPS_STEP_CTRL_DELAY_MASK; reg 1597 drivers/regulator/qcom_spmi-regulator.c u8 reg = 0; reg 1601 drivers/regulator/qcom_spmi-regulator.c ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, ®, 1); reg 1607 drivers/regulator/qcom_spmi-regulator.c delay = reg & SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK; reg 1627 drivers/regulator/qcom_spmi-regulator.c u8 ctrl_reg[8], reg, mask; reg 1686 drivers/regulator/qcom_spmi-regulator.c reg = data->vs_soft_start_strength reg 1691 drivers/regulator/qcom_spmi-regulator.c reg, mask); reg 1957 drivers/regulator/qcom_spmi-regulator.c const struct spmi_regulator_data *reg; reg 1994 drivers/regulator/qcom_spmi-regulator.c for (reg = match->data; reg->name; reg++) { reg 1997 drivers/regulator/qcom_spmi-regulator.c reg_node = of_get_child_by_name(node, reg->name); reg 2010 drivers/regulator/qcom_spmi-regulator.c vreg->base = reg->base; reg 2012 drivers/regulator/qcom_spmi-regulator.c if (reg->ocp) { reg 2013 drivers/regulator/qcom_spmi-regulator.c vreg->ocp_irq = platform_get_irq_byname(pdev, reg->ocp); reg 2022 drivers/regulator/qcom_spmi-regulator.c vreg->desc.enable_reg = reg->base + SPMI_COMMON_REG_ENABLE; reg 2025 drivers/regulator/qcom_spmi-regulator.c vreg->desc.name = name = reg->name; reg 2026 drivers/regulator/qcom_spmi-regulator.c vreg->desc.supply_name = reg->supply; reg 2027 drivers/regulator/qcom_spmi-regulator.c vreg->desc.of_match = reg->name; reg 2031 drivers/regulator/qcom_spmi-regulator.c ret = spmi_regulator_match(vreg, reg->force_type); reg 2036 drivers/regulator/qcom_spmi-regulator.c reg_node = of_get_child_by_name(node, reg->name); reg 296 drivers/regulator/rk808-regulator.c unsigned int reg = rdev->desc->vsel_reg; reg 305 drivers/regulator/rk808-regulator.c reg += RK808_DVS_REG_OFFSET; reg 309 drivers/regulator/rk808-regulator.c reg + RK808_DVS_REG_OFFSET, reg 319 drivers/regulator/rk808-regulator.c ret = regmap_write(rdev->regmap, reg, sel); reg 346 drivers/regulator/rk808-regulator.c unsigned int reg = rk808_buck_config_regs[rdev_get_id(rdev)]; reg 365 drivers/regulator/rk808-regulator.c return regmap_update_bits(rdev->regmap, reg, reg 375 drivers/regulator/rk808-regulator.c unsigned int reg = RK817_BUCK_CONFIG_REG(rdev_get_id(rdev)); reg 395 drivers/regulator/rk808-regulator.c return regmap_update_bits(rdev->regmap, reg, reg 401 drivers/regulator/rk808-regulator.c unsigned int reg; reg 407 drivers/regulator/rk808-regulator.c reg = rdev->desc->vsel_reg + RK808_SLP_REG_OFFSET; reg 409 drivers/regulator/rk808-regulator.c return regmap_update_bits(rdev->regmap, reg, reg 416 drivers/regulator/rk808-regulator.c unsigned int reg; reg 422 drivers/regulator/rk808-regulator.c reg = rdev->desc->vsel_reg + RK808_SLP_REG_OFFSET; reg 424 drivers/regulator/rk808-regulator.c return regmap_update_bits(rdev->regmap, reg, reg 431 drivers/regulator/rk808-regulator.c unsigned int reg; reg 437 drivers/regulator/rk808-regulator.c reg = rdev->desc->vsel_reg + RK808_SLP_REG_OFFSET; reg 439 drivers/regulator/rk808-regulator.c return regmap_update_bits(rdev->regmap, reg, reg 446 drivers/regulator/rk808-regulator.c unsigned int reg; reg 448 drivers/regulator/rk808-regulator.c reg = rdev->desc->enable_reg + RK808_SLP_SET_OFF_REG_OFFSET; reg 450 drivers/regulator/rk808-regulator.c return regmap_update_bits(rdev->regmap, reg, reg 457 drivers/regulator/rk808-regulator.c unsigned int reg; reg 459 drivers/regulator/rk808-regulator.c reg = rdev->desc->enable_reg + RK808_SLP_SET_OFF_REG_OFFSET; reg 461 drivers/regulator/rk808-regulator.c return regmap_update_bits(rdev->regmap, reg, reg 468 drivers/regulator/rk808-regulator.c unsigned int reg; reg 470 drivers/regulator/rk808-regulator.c reg = rdev->desc->enable_reg + RK808_SLP_SET_OFF_REG_OFFSET; reg 472 drivers/regulator/rk808-regulator.c return regmap_update_bits(rdev->regmap, reg, reg 479 drivers/regulator/rk808-regulator.c unsigned int reg; reg 481 drivers/regulator/rk808-regulator.c reg = rdev->desc->enable_reg + RK808_SLP_SET_OFF_REG_OFFSET; reg 483 drivers/regulator/rk808-regulator.c return regmap_update_bits(rdev->regmap, reg, reg 491 drivers/regulator/rk808-regulator.c unsigned int reg; reg 504 drivers/regulator/rk808-regulator.c reg = RK817_POWER_SLP_EN_REG(id_slp / 8); reg 512 drivers/regulator/rk808-regulator.c return regmap_update_bits(rdev->regmap, reg, msk, val); reg 527 drivers/regulator/rk808-regulator.c unsigned int reg; reg 529 drivers/regulator/rk808-regulator.c reg = rdev->desc->vsel_reg + RK808_SLP_REG_OFFSET; reg 533 drivers/regulator/rk808-regulator.c return regmap_update_bits(rdev->regmap, reg, reg 536 drivers/regulator/rk808-regulator.c return regmap_update_bits(rdev->regmap, reg, reg 842 drivers/regulator/s2mps11.c unsigned int reg = valid_regulators[i]; reg 844 drivers/regulator/s2mps11.c if (!rdata[reg].init_data || !rdata[reg].of_node) reg 847 drivers/regulator/s2mps11.c gpio[reg] = devm_gpiod_get_from_of_node(&pdev->dev, reg 848 drivers/regulator/s2mps11.c rdata[reg].of_node, reg 853 drivers/regulator/s2mps11.c if (PTR_ERR(gpio[reg]) == -ENOENT) reg 854 drivers/regulator/s2mps11.c gpio[reg] = NULL; reg 855 drivers/regulator/s2mps11.c else if (IS_ERR(gpio[reg])) { reg 857 drivers/regulator/s2mps11.c reg, rdata[reg].name); reg 858 drivers/regulator/s2mps11.c gpio[reg] = NULL; reg 861 drivers/regulator/s2mps11.c if (gpio[reg]) reg 863 drivers/regulator/s2mps11.c reg, rdata[reg].name); reg 163 drivers/regulator/s5m8767.c int *reg, int *enable_ctrl) reg 170 drivers/regulator/s5m8767.c *reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1); reg 173 drivers/regulator/s5m8767.c *reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3); reg 176 drivers/regulator/s5m8767.c *reg = S5M8767_REG_BUCK1CTRL1; reg 179 drivers/regulator/s5m8767.c *reg = S5M8767_REG_BUCK2CTRL + (reg_id - S5M8767_BUCK2) * 9; reg 182 drivers/regulator/s5m8767.c *reg = S5M8767_REG_BUCK5CTRL1; reg 185 drivers/regulator/s5m8767.c *reg = S5M8767_REG_BUCK6CTRL1 + (reg_id - S5M8767_BUCK6) * 2; reg 208 drivers/regulator/s5m8767.c int reg; reg 212 drivers/regulator/s5m8767.c reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1); reg 215 drivers/regulator/s5m8767.c reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3); reg 218 drivers/regulator/s5m8767.c reg = S5M8767_REG_BUCK1CTRL2; reg 221 drivers/regulator/s5m8767.c reg = S5M8767_REG_BUCK2DVS1; reg 223 drivers/regulator/s5m8767.c reg += s5m8767->buck_gpioindex; reg 226 drivers/regulator/s5m8767.c reg = S5M8767_REG_BUCK3DVS1; reg 228 drivers/regulator/s5m8767.c reg += s5m8767->buck_gpioindex; reg 231 drivers/regulator/s5m8767.c reg = S5M8767_REG_BUCK4DVS1; reg 233 drivers/regulator/s5m8767.c reg += s5m8767->buck_gpioindex; reg 236 drivers/regulator/s5m8767.c reg = S5M8767_REG_BUCK5CTRL2; reg 239 drivers/regulator/s5m8767.c reg = S5M8767_REG_BUCK6CTRL2 + (reg_id - S5M8767_BUCK6) * 2; reg 245 drivers/regulator/s5m8767.c return reg; reg 468 drivers/regulator/s5m8767.c int ret, reg, enable_ctrl; reg 473 drivers/regulator/s5m8767.c ret = s5m8767_get_register(s5m8767, id, ®, &enable_ctrl); reg 478 drivers/regulator/s5m8767.c reg, S5M8767_ENCTRL_MASK, reg 251 drivers/regulator/slg51000-regulator.c unsigned int reg, val; reg 279 drivers/regulator/slg51000-regulator.c reg = SLG51000_LDO1_MISC1; reg 281 drivers/regulator/slg51000-regulator.c reg = SLG51000_LDO2_MISC1; reg 283 drivers/regulator/slg51000-regulator.c ret = regmap_read(chip->regmap, reg, &val); reg 306 drivers/regulator/slg51000-regulator.c reg = SLG51000_LDO5_TRIM2; reg 308 drivers/regulator/slg51000-regulator.c reg = SLG51000_LDO6_TRIM2; reg 310 drivers/regulator/slg51000-regulator.c ret = regmap_read(chip->regmap, reg, &val); reg 71 drivers/regulator/sy8106a-regulator.c unsigned int reg, vsel; reg 102 drivers/regulator/sy8106a-regulator.c error = regmap_read(regmap, SY8106A_REG_VOUT1_SEL, ®); reg 106 drivers/regulator/sy8106a-regulator.c if (!(reg & SY8106A_GO_BIT)) { reg 129 drivers/regulator/ti-abb-regulator.c static inline u32 ti_abb_rmw(u32 mask, u32 value, void __iomem *reg) reg 133 drivers/regulator/ti-abb-regulator.c val = readl(reg); reg 136 drivers/regulator/ti-abb-regulator.c writel(val, reg); reg 172 drivers/regulator/tps51632-regulator.c static bool is_volatile_reg(struct device *dev, unsigned int reg) reg 174 drivers/regulator/tps51632-regulator.c switch (reg) { reg 184 drivers/regulator/tps51632-regulator.c static bool is_read_reg(struct device *dev, unsigned int reg) reg 186 drivers/regulator/tps51632-regulator.c switch (reg) { reg 194 drivers/regulator/tps51632-regulator.c static bool is_write_reg(struct device *dev, unsigned int reg) reg 196 drivers/regulator/tps51632-regulator.c switch (reg) { reg 121 drivers/regulator/tps6507x-regulator.c static inline int tps6507x_pmic_read(struct tps6507x_pmic *tps, u8 reg) reg 126 drivers/regulator/tps6507x-regulator.c err = tps->mfd->read_dev(tps->mfd, reg, 1, &val); reg 134 drivers/regulator/tps6507x-regulator.c static inline int tps6507x_pmic_write(struct tps6507x_pmic *tps, u8 reg, u8 val) reg 136 drivers/regulator/tps6507x-regulator.c return tps->mfd->write_dev(tps->mfd, reg, 1, &val); reg 139 drivers/regulator/tps6507x-regulator.c static int tps6507x_pmic_set_bits(struct tps6507x_pmic *tps, u8 reg, u8 mask) reg 145 drivers/regulator/tps6507x-regulator.c data = tps6507x_pmic_read(tps, reg); reg 147 drivers/regulator/tps6507x-regulator.c dev_err(tps->mfd->dev, "Read from reg 0x%x failed\n", reg); reg 153 drivers/regulator/tps6507x-regulator.c err = tps6507x_pmic_write(tps, reg, data); reg 155 drivers/regulator/tps6507x-regulator.c dev_err(tps->mfd->dev, "Write for reg 0x%x failed\n", reg); reg 162 drivers/regulator/tps6507x-regulator.c static int tps6507x_pmic_clear_bits(struct tps6507x_pmic *tps, u8 reg, u8 mask) reg 168 drivers/regulator/tps6507x-regulator.c data = tps6507x_pmic_read(tps, reg); reg 170 drivers/regulator/tps6507x-regulator.c dev_err(tps->mfd->dev, "Read from reg 0x%x failed\n", reg); reg 176 drivers/regulator/tps6507x-regulator.c err = tps6507x_pmic_write(tps, reg, data); reg 178 drivers/regulator/tps6507x-regulator.c dev_err(tps->mfd->dev, "Write for reg 0x%x failed\n", reg); reg 185 drivers/regulator/tps6507x-regulator.c static int tps6507x_pmic_reg_read(struct tps6507x_pmic *tps, u8 reg) reg 191 drivers/regulator/tps6507x-regulator.c data = tps6507x_pmic_read(tps, reg); reg 193 drivers/regulator/tps6507x-regulator.c dev_err(tps->mfd->dev, "Read from reg 0x%x failed\n", reg); reg 199 drivers/regulator/tps6507x-regulator.c static int tps6507x_pmic_reg_write(struct tps6507x_pmic *tps, u8 reg, u8 val) reg 205 drivers/regulator/tps6507x-regulator.c err = tps6507x_pmic_write(tps, reg, val); reg 207 drivers/regulator/tps6507x-regulator.c dev_err(tps->mfd->dev, "Write for reg 0x%x failed\n", reg); reg 262 drivers/regulator/tps6507x-regulator.c u8 reg, mask; reg 266 drivers/regulator/tps6507x-regulator.c reg = TPS6507X_REG_DEFDCDC1; reg 271 drivers/regulator/tps6507x-regulator.c reg = TPS6507X_REG_DEFDCDC2_HIGH; reg 273 drivers/regulator/tps6507x-regulator.c reg = TPS6507X_REG_DEFDCDC2_LOW; reg 278 drivers/regulator/tps6507x-regulator.c reg = TPS6507X_REG_DEFDCDC3_HIGH; reg 280 drivers/regulator/tps6507x-regulator.c reg = TPS6507X_REG_DEFDCDC3_LOW; reg 284 drivers/regulator/tps6507x-regulator.c reg = TPS6507X_REG_LDO_CTRL1; reg 288 drivers/regulator/tps6507x-regulator.c reg = TPS6507X_REG_DEFLDO2; reg 295 drivers/regulator/tps6507x-regulator.c data = tps6507x_pmic_reg_read(tps, reg); reg 308 drivers/regulator/tps6507x-regulator.c u8 reg, mask; reg 312 drivers/regulator/tps6507x-regulator.c reg = TPS6507X_REG_DEFDCDC1; reg 317 drivers/regulator/tps6507x-regulator.c reg = TPS6507X_REG_DEFDCDC2_HIGH; reg 319 drivers/regulator/tps6507x-regulator.c reg = TPS6507X_REG_DEFDCDC2_LOW; reg 324 drivers/regulator/tps6507x-regulator.c reg = TPS6507X_REG_DEFDCDC3_HIGH; reg 326 drivers/regulator/tps6507x-regulator.c reg = TPS6507X_REG_DEFDCDC3_LOW; reg 330 drivers/regulator/tps6507x-regulator.c reg = TPS6507X_REG_LDO_CTRL1; reg 334 drivers/regulator/tps6507x-regulator.c reg = TPS6507X_REG_DEFLDO2; reg 341 drivers/regulator/tps6507x-regulator.c data = tps6507x_pmic_reg_read(tps, reg); reg 348 drivers/regulator/tps6507x-regulator.c return tps6507x_pmic_reg_write(tps, reg, data); reg 113 drivers/regulator/tps6524x-regulator.c #define CMD_READ(reg) ((reg) << 6) reg 114 drivers/regulator/tps6524x-regulator.c #define CMD_WRITE(reg) (BIT(5) | (reg) << 6) reg 121 drivers/regulator/tps6524x-regulator.c int reg; reg 142 drivers/regulator/tps6524x-regulator.c static int __read_reg(struct tps6524x *hw, int reg) reg 145 drivers/regulator/tps6524x-regulator.c u16 cmd = CMD_READ(reg), in; reg 173 drivers/regulator/tps6524x-regulator.c reg, in, status); reg 184 drivers/regulator/tps6524x-regulator.c static int read_reg(struct tps6524x *hw, int reg) reg 189 drivers/regulator/tps6524x-regulator.c ret = __read_reg(hw, reg); reg 195 drivers/regulator/tps6524x-regulator.c static int __write_reg(struct tps6524x *hw, int reg, int val) reg 198 drivers/regulator/tps6524x-regulator.c u16 cmd = CMD_WRITE(reg), out = val; reg 226 drivers/regulator/tps6524x-regulator.c reg, out, status); reg 237 drivers/regulator/tps6524x-regulator.c static int __rmw_reg(struct tps6524x *hw, int reg, int mask, int val) reg 241 drivers/regulator/tps6524x-regulator.c ret = __read_reg(hw, reg); reg 248 drivers/regulator/tps6524x-regulator.c ret = __write_reg(hw, reg, ret); reg 253 drivers/regulator/tps6524x-regulator.c static int rmw_protect(struct tps6524x *hw, int reg, int mask, int val) reg 265 drivers/regulator/tps6524x-regulator.c ret = __rmw_reg(hw, reg, mask, val); reg 267 drivers/regulator/tps6524x-regulator.c dev_err(hw->dev, "failed to rmw register %d\n", reg); reg 285 drivers/regulator/tps6524x-regulator.c tmp = read_reg(hw, field->reg); reg 298 drivers/regulator/tps6524x-regulator.c return rmw_protect(hw, field->reg, reg 372 drivers/regulator/tps6524x-regulator.c { .reg = (_reg), .mask = (_mask), .shift = (_shift), } reg 308 drivers/regulator/tps6586x-regulator.c uint8_t reg; reg 319 drivers/regulator/tps6586x-regulator.c reg = TPS6586X_SM0SL; reg 322 drivers/regulator/tps6586x-regulator.c reg = TPS6586X_SM1SL; reg 329 drivers/regulator/tps6586x-regulator.c return tps6586x_write(parent, reg, reg 394 drivers/regulator/tps65910-regulator.c int reg, value, id = rdev_get_id(dev); reg 396 drivers/regulator/tps65910-regulator.c reg = pmic->get_ctrl_reg(id); reg 397 drivers/regulator/tps65910-regulator.c if (reg < 0) reg 398 drivers/regulator/tps65910-regulator.c return reg; reg 402 drivers/regulator/tps65910-regulator.c return tps65910_reg_update_bits(pmic->mfd, reg, reg 407 drivers/regulator/tps65910-regulator.c return tps65910_reg_set_bits(mfd, reg, value); reg 409 drivers/regulator/tps65910-regulator.c return tps65910_reg_clear_bits(mfd, reg, LDO_ST_ON_BIT); reg 418 drivers/regulator/tps65910-regulator.c int ret, reg, value, id = rdev_get_id(dev); reg 420 drivers/regulator/tps65910-regulator.c reg = pmic->get_ctrl_reg(id); reg 421 drivers/regulator/tps65910-regulator.c if (reg < 0) reg 422 drivers/regulator/tps65910-regulator.c return reg; reg 424 drivers/regulator/tps65910-regulator.c ret = tps65910_reg_read(pmic->mfd, reg, &value); reg 517 drivers/regulator/tps65910-regulator.c int ret, reg, value, id = rdev_get_id(dev); reg 519 drivers/regulator/tps65910-regulator.c reg = pmic->get_ctrl_reg(id); reg 520 drivers/regulator/tps65910-regulator.c if (reg < 0) reg 521 drivers/regulator/tps65910-regulator.c return reg; reg 523 drivers/regulator/tps65910-regulator.c ret = tps65910_reg_read(pmic->mfd, reg, &value); reg 560 drivers/regulator/tps65910-regulator.c unsigned int value, reg; reg 562 drivers/regulator/tps65910-regulator.c reg = pmic->get_ctrl_reg(id); reg 564 drivers/regulator/tps65910-regulator.c ret = tps65910_reg_read(pmic->mfd, reg, &value); reg 636 drivers/regulator/tps65910-regulator.c int reg, id = rdev_get_id(dev); reg 638 drivers/regulator/tps65910-regulator.c reg = pmic->get_ctrl_reg(id); reg 639 drivers/regulator/tps65910-regulator.c if (reg < 0) reg 640 drivers/regulator/tps65910-regulator.c return reg; reg 652 drivers/regulator/tps65910-regulator.c return tps65910_reg_update_bits(pmic->mfd, reg, LDO_SEL_MASK, reg 655 drivers/regulator/tps65910-regulator.c return tps65910_reg_update_bits(pmic->mfd, reg, BBCH_BBSEL_MASK, reg 666 drivers/regulator/tps65910-regulator.c int reg, id = rdev_get_id(dev); reg 668 drivers/regulator/tps65910-regulator.c reg = pmic->get_ctrl_reg(id); reg 669 drivers/regulator/tps65910-regulator.c if (reg < 0) reg 670 drivers/regulator/tps65910-regulator.c return reg; reg 676 drivers/regulator/tps65910-regulator.c return tps65910_reg_update_bits(pmic->mfd, reg, LDO1_SEL_MASK, reg 683 drivers/regulator/tps65910-regulator.c return tps65910_reg_update_bits(pmic->mfd, reg, LDO3_SEL_MASK, reg 686 drivers/regulator/tps65910-regulator.c return tps65910_reg_update_bits(pmic->mfd, reg, LDO_SEL_MASK, reg 689 drivers/regulator/tps65910-regulator.c return tps65910_reg_update_bits(pmic->mfd, reg, BBCH_BBSEL_MASK, reg 64 drivers/regulator/wm831x-dcdc.c u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG; reg 67 drivers/regulator/wm831x-dcdc.c val = wm831x_reg_read(wm831x, reg); reg 88 drivers/regulator/wm831x-dcdc.c static int wm831x_dcdc_set_mode_int(struct wm831x *wm831x, int reg, reg 110 drivers/regulator/wm831x-dcdc.c return wm831x_set_bits(wm831x, reg, WM831X_DC1_ON_MODE_MASK, reg 118 drivers/regulator/wm831x-dcdc.c u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG; reg 120 drivers/regulator/wm831x-dcdc.c return wm831x_dcdc_set_mode_int(wm831x, reg, mode); reg 128 drivers/regulator/wm831x-dcdc.c u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL; reg 130 drivers/regulator/wm831x-dcdc.c return wm831x_dcdc_set_mode_int(wm831x, reg, mode); reg 285 drivers/regulator/wm831x-dcdc.c u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL; reg 292 drivers/regulator/wm831x-dcdc.c return wm831x_set_bits(wm831x, reg, WM831X_DC1_SLP_VSEL_MASK, vsel); reg 523 drivers/regulator/wm831x-dcdc.c u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL; reg 530 drivers/regulator/wm831x-dcdc.c return wm831x_set_bits(wm831x, reg, WM831X_DC3_ON_VSEL_MASK, sel); reg 28 drivers/regulator/wm831x-isink.c int reg; reg 40 drivers/regulator/wm831x-isink.c ret = wm831x_set_bits(wm831x, isink->reg, WM831X_CS1_ENA, reg 46 drivers/regulator/wm831x-isink.c ret = wm831x_set_bits(wm831x, isink->reg, WM831X_CS1_DRIVE, reg 49 drivers/regulator/wm831x-isink.c wm831x_set_bits(wm831x, isink->reg, WM831X_CS1_ENA, 0); reg 61 drivers/regulator/wm831x-isink.c ret = wm831x_set_bits(wm831x, isink->reg, WM831X_CS1_DRIVE, 0); reg 65 drivers/regulator/wm831x-isink.c ret = wm831x_set_bits(wm831x, isink->reg, WM831X_CS1_ENA, 0); reg 79 drivers/regulator/wm831x-isink.c ret = wm831x_reg_read(wm831x, isink->reg); reg 140 drivers/regulator/wm831x-isink.c isink->reg = res->start; reg 153 drivers/regulator/wm831x-isink.c isink->desc.csel_reg = isink->reg, reg 72 drivers/regulator/wm831x-ldo.c int sel, reg = ldo->base + WM831X_LDO_SLEEP_CONTROL; reg 78 drivers/regulator/wm831x-ldo.c return wm831x_set_bits(wm831x, reg, WM831X_LDO1_ON_VSEL_MASK, sel); reg 325 drivers/regulator/wm831x-ldo.c int sel, reg = ldo->base + WM831X_LDO_SLEEP_CONTROL; reg 331 drivers/regulator/wm831x-ldo.c return wm831x_set_bits(wm831x, reg, WM831X_LDO7_ON_VSEL_MASK, sel); reg 531 drivers/regulator/wm831x-ldo.c int sel, reg = ldo->base + WM831X_ALIVE_LDO_SLEEP_CONTROL; reg 537 drivers/regulator/wm831x-ldo.c return wm831x_set_bits(wm831x, reg, WM831X_LDO11_ON_VSEL_MASK, sel); reg 198 drivers/regulator/wm8350-regulator.c int reg; reg 202 drivers/regulator/wm8350-regulator.c reg = wm8350_reg_read(wm8350, WM8350_CSA_FLASH_CONTROL); reg 205 drivers/regulator/wm8350-regulator.c reg = wm8350_reg_read(wm8350, WM8350_CSB_FLASH_CONTROL); reg 211 drivers/regulator/wm8350-regulator.c if (reg & WM8350_CS1_FLASH_MODE) { reg 212 drivers/regulator/wm8350-regulator.c switch (reg & WM8350_CS1_ON_RAMP_MASK) { reg 223 drivers/regulator/wm8350-regulator.c switch (reg & WM8350_CS1_ON_RAMP_MASK) { reg 693 drivers/regulator/wm8350-regulator.c int reg = 0, ret; reg 697 drivers/regulator/wm8350-regulator.c reg = WM8350_DCDC1_FORCE_PWM; reg 700 drivers/regulator/wm8350-regulator.c reg = WM8350_DCDC3_FORCE_PWM; reg 703 drivers/regulator/wm8350-regulator.c reg = WM8350_DCDC4_FORCE_PWM; reg 706 drivers/regulator/wm8350-regulator.c reg = WM8350_DCDC6_FORCE_PWM; reg 713 drivers/regulator/wm8350-regulator.c ret = wm8350_set_bits(wm8350, reg, reg 716 drivers/regulator/wm8350-regulator.c ret = wm8350_clear_bits(wm8350, reg, reg 770 drivers/regulator/wm8350-regulator.c int reg; reg 774 drivers/regulator/wm8350-regulator.c reg = WM8350_DCDC1_FORCE_PWM; reg 777 drivers/regulator/wm8350-regulator.c reg = WM8350_DCDC3_FORCE_PWM; reg 780 drivers/regulator/wm8350-regulator.c reg = WM8350_DCDC4_FORCE_PWM; reg 783 drivers/regulator/wm8350-regulator.c reg = WM8350_DCDC6_FORCE_PWM; reg 791 drivers/regulator/wm8350-regulator.c force = wm8350_reg_read(wm8350, reg) & WM8350_DCDC1_FORCE_PWM_ENA; reg 1173 drivers/regulator/wm8350-regulator.c int wm8350_register_regulator(struct wm8350 *wm8350, int reg, reg 1178 drivers/regulator/wm8350-regulator.c if (reg < 0 || reg >= NUM_WM8350_REGULATORS) reg 1181 drivers/regulator/wm8350-regulator.c if (wm8350->pmic.pdev[reg]) reg 1184 drivers/regulator/wm8350-regulator.c if (reg >= WM8350_DCDC_1 && reg <= WM8350_DCDC_6 && reg 1185 drivers/regulator/wm8350-regulator.c reg > wm8350->pmic.max_dcdc) reg 1187 drivers/regulator/wm8350-regulator.c if (reg >= WM8350_ISINK_A && reg <= WM8350_ISINK_B && reg 1188 drivers/regulator/wm8350-regulator.c reg > wm8350->pmic.max_isink) reg 1191 drivers/regulator/wm8350-regulator.c pdev = platform_device_alloc("wm8350-regulator", reg); reg 1195 drivers/regulator/wm8350-regulator.c wm8350->pmic.pdev[reg] = pdev; reg 1207 drivers/regulator/wm8350-regulator.c reg, ret); reg 1209 drivers/regulator/wm8350-regulator.c wm8350->pmic.pdev[reg] = NULL; reg 241 drivers/regulator/wm8400-regulator.c int wm8400_register_regulator(struct device *dev, int reg, reg 246 drivers/regulator/wm8400-regulator.c if (wm8400->regulators[reg].name) reg 251 drivers/regulator/wm8400-regulator.c wm8400->regulators[reg].name = "wm8400-regulator"; reg 252 drivers/regulator/wm8400-regulator.c wm8400->regulators[reg].id = reg; reg 253 drivers/regulator/wm8400-regulator.c wm8400->regulators[reg].dev.parent = dev; reg 254 drivers/regulator/wm8400-regulator.c wm8400->regulators[reg].dev.platform_data = initdata; reg 256 drivers/regulator/wm8400-regulator.c return platform_device_register(&wm8400->regulators[reg]); reg 110 drivers/remoteproc/qcom_q6v5_mss.c struct regulator *reg; reg 212 drivers/remoteproc/qcom_q6v5_mss.c regs[i].reg = devm_regulator_get(dev, reg_res[i].supply); reg 213 drivers/remoteproc/qcom_q6v5_mss.c if (IS_ERR(regs[i].reg)) { reg 214 drivers/remoteproc/qcom_q6v5_mss.c rc = PTR_ERR(regs[i].reg); reg 236 drivers/remoteproc/qcom_q6v5_mss.c ret = regulator_set_voltage(regs[i].reg, reg 247 drivers/remoteproc/qcom_q6v5_mss.c ret = regulator_set_load(regs[i].reg, reg 256 drivers/remoteproc/qcom_q6v5_mss.c ret = regulator_enable(regs[i].reg); reg 267 drivers/remoteproc/qcom_q6v5_mss.c regulator_set_voltage(regs[i].reg, 0, INT_MAX); reg 270 drivers/remoteproc/qcom_q6v5_mss.c regulator_set_load(regs[i].reg, 0); reg 272 drivers/remoteproc/qcom_q6v5_mss.c regulator_disable(regs[i].reg); reg 285 drivers/remoteproc/qcom_q6v5_mss.c regulator_set_voltage(regs[i].reg, 0, INT_MAX); reg 288 drivers/remoteproc/qcom_q6v5_mss.c regulator_set_load(regs[i].reg, 0); reg 290 drivers/remoteproc/qcom_q6v5_mss.c regulator_disable(regs[i].reg); reg 39 drivers/remoteproc/stm32_rproc.c u32 reg; reg 349 drivers/remoteproc/stm32_rproc.c hold_boot.reg, val, 0, 0, 0, 0, &smc_res); reg 352 drivers/remoteproc/stm32_rproc.c err = regmap_update_bits(hold_boot.map, hold_boot.reg, reg 393 drivers/remoteproc/stm32_rproc.c err = regmap_update_bits(ddata->pdds.map, ddata->pdds.reg, reg 437 drivers/remoteproc/stm32_rproc.c err = regmap_update_bits(ddata->pdds.map, ddata->pdds.reg, reg 499 drivers/remoteproc/stm32_rproc.c err = of_property_read_u32_index(np, prop, 1, &syscon->reg); reg 551 drivers/remoteproc/stm32_rproc.c err = regmap_read(tz.map, tz.reg, &tzen); reg 50 drivers/reset/hisilicon/hi6220_reset.c u32 reg = PERIPH_ASSERT_OFFSET + bank * 0x10; reg 52 drivers/reset/hisilicon/hi6220_reset.c return regmap_write(regmap, reg, BIT(offset)); reg 62 drivers/reset/hisilicon/hi6220_reset.c u32 reg = PERIPH_DEASSERT_OFFSET + bank * 0x10; reg 64 drivers/reset/hisilicon/hi6220_reset.c return regmap_write(regmap, reg, BIT(offset)); reg 59 drivers/reset/reset-hsdk.c u32 reg; reg 61 drivers/reset/reset-hsdk.c reg = readl(rst->regs_rst + CGU_IP_SW_RESET); reg 62 drivers/reset/reset-hsdk.c reg &= ~CGU_IP_SW_RESET_DELAY_MASK; reg 63 drivers/reset/reset-hsdk.c reg |= CGU_IP_SW_RESET_DELAY << CGU_IP_SW_RESET_DELAY_SHIFT; reg 64 drivers/reset/reset-hsdk.c reg |= CGU_IP_SW_RESET_RESET; reg 65 drivers/reset/reset-hsdk.c writel(reg, rst->regs_rst + CGU_IP_SW_RESET); reg 68 drivers/reset/reset-hsdk.c return readl_poll_timeout_atomic(rst->regs_rst + CGU_IP_SW_RESET, reg, reg 69 drivers/reset/reset-hsdk.c !(reg & CGU_IP_SW_RESET_RESET), 5, SW_RESET_TIMEOUT); reg 51 drivers/reset/reset-meson.c u32 reg; reg 55 drivers/reset/reset-meson.c reg = readl(reg_addr); reg 57 drivers/reset/reset-meson.c writel(reg & ~BIT(offset), reg_addr); reg 59 drivers/reset/reset-meson.c writel(reg | BIT(offset), reg_addr); reg 15 drivers/reset/reset-qcom-aoss.c unsigned int reg; reg 56 drivers/reset/reset-qcom-aoss.c writel(1, data->base + map->reg); reg 68 drivers/reset/reset-qcom-aoss.c writel(0, data->base + map->reg); reg 39 drivers/reset/reset-simple.c u32 reg; reg 43 drivers/reset/reset-simple.c reg = readl(data->membase + (bank * reg_width)); reg 45 drivers/reset/reset-simple.c reg |= BIT(offset); reg 47 drivers/reset/reset-simple.c reg &= ~BIT(offset); reg 48 drivers/reset/reset-simple.c writel(reg, data->membase + (bank * reg_width)); reg 74 drivers/reset/reset-simple.c u32 reg; reg 76 drivers/reset/reset-simple.c reg = readl(data->membase + (bank * reg_width)); reg 78 drivers/reset/reset-simple.c return !(reg & BIT(offset)) ^ !data->status_active_low; reg 64 drivers/reset/reset-stm32mp1.c u32 reg; reg 66 drivers/reset/reset-stm32mp1.c reg = readl(data->membase + (bank * reg_width)); reg 68 drivers/reset/reset-stm32mp1.c return !!(reg & BIT(offset)); reg 17 drivers/reset/reset-uniphier.c unsigned int reg; reg 31 drivers/reset/reset-uniphier.c .reg = (_reg), \ reg 38 drivers/reset/reset-uniphier.c .reg = (_reg), \ reg 275 drivers/reset/reset-uniphier.c return regmap_write_bits(priv->regmap, p->reg, mask, val); reg 307 drivers/reset/reset-uniphier.c ret = regmap_read(priv->regmap, p->reg, &val); reg 71 drivers/reset/reset-zynq.c u32 reg; reg 76 drivers/reset/reset-zynq.c ret = regmap_read(priv->slcr, priv->offset + (bank * 4), ®); reg 80 drivers/reset/reset-zynq.c return !!(reg & BIT(offset)); reg 304 drivers/rtc/rtc-ab-b5ze-s3.c unsigned int reg; reg 337 drivers/rtc/rtc-ab-b5ze-s3.c ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL2, ®); reg 344 drivers/rtc/rtc-ab-b5ze-s3.c alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL2_WTAIE); reg 357 drivers/rtc/rtc-ab-b5ze-s3.c unsigned int reg; reg 398 drivers/rtc/rtc-ab-b5ze-s3.c ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL1, ®); reg 405 drivers/rtc/rtc-ab-b5ze-s3.c alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL1_AIE); reg 606 drivers/rtc/rtc-ab-b5ze-s3.c unsigned int reg; reg 690 drivers/rtc/rtc-ab-b5ze-s3.c ret = regmap_read(regmap, ABB5ZES3_REG_RTC_SC, ®); reg 697 drivers/rtc/rtc-ab-b5ze-s3.c if (reg & ABB5ZES3_REG_RTC_SC_OSC) { reg 708 drivers/rtc/rtc-ab-b5ze-s3.c ret = regmap_read(regmap, ABB5ZES3_REG_CTRL3, ®); reg 715 drivers/rtc/rtc-ab-b5ze-s3.c data->battery_low = reg & ABB5ZES3_REG_CTRL3_BLF; reg 123 drivers/rtc/rtc-ac100.c unsigned int reg, div; reg 125 drivers/rtc/rtc-ac100.c regmap_read(clk->regmap, clk->offset, ®); reg 129 drivers/rtc/rtc-ac100.c div = (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) & reg 136 drivers/rtc/rtc-ac100.c div = (reg >> AC100_CLKOUT_DIV_SHIFT) & reg 269 drivers/rtc/rtc-ac100.c unsigned int reg; reg 271 drivers/rtc/rtc-ac100.c regmap_read(clk->regmap, clk->offset, ®); reg 273 drivers/rtc/rtc-ac100.c return reg & AC100_CLKOUT_EN; reg 279 drivers/rtc/rtc-ac100.c unsigned int reg; reg 281 drivers/rtc/rtc-ac100.c regmap_read(clk->regmap, clk->offset, ®); reg 283 drivers/rtc/rtc-ac100.c return (reg >> AC100_CLKOUT_MUX_SHIFT) & 0x1; reg 388 drivers/rtc/rtc-ac100.c u16 reg[7]; reg 391 drivers/rtc/rtc-ac100.c ret = regmap_bulk_read(regmap, AC100_RTC_SEC, reg, 7); reg 395 drivers/rtc/rtc-ac100.c rtc_tm->tm_sec = bcd2bin(reg[0] & AC100_RTC_SEC_MASK); reg 396 drivers/rtc/rtc-ac100.c rtc_tm->tm_min = bcd2bin(reg[1] & AC100_RTC_MIN_MASK); reg 397 drivers/rtc/rtc-ac100.c rtc_tm->tm_hour = bcd2bin(reg[2] & AC100_RTC_HOU_MASK); reg 398 drivers/rtc/rtc-ac100.c rtc_tm->tm_wday = bcd2bin(reg[3] & AC100_RTC_WEE_MASK); reg 399 drivers/rtc/rtc-ac100.c rtc_tm->tm_mday = bcd2bin(reg[4] & AC100_RTC_DAY_MASK); reg 400 drivers/rtc/rtc-ac100.c rtc_tm->tm_mon = bcd2bin(reg[5] & AC100_RTC_MON_MASK) - 1; reg 401 drivers/rtc/rtc-ac100.c rtc_tm->tm_year = bcd2bin(reg[6] & AC100_RTC_YEA_MASK) + reg 412 drivers/rtc/rtc-ac100.c u16 reg[8]; reg 423 drivers/rtc/rtc-ac100.c reg[0] = bin2bcd(rtc_tm->tm_sec) & AC100_RTC_SEC_MASK; reg 424 drivers/rtc/rtc-ac100.c reg[1] = bin2bcd(rtc_tm->tm_min) & AC100_RTC_MIN_MASK; reg 425 drivers/rtc/rtc-ac100.c reg[2] = bin2bcd(rtc_tm->tm_hour) & AC100_RTC_HOU_MASK; reg 426 drivers/rtc/rtc-ac100.c reg[3] = bin2bcd(rtc_tm->tm_wday) & AC100_RTC_WEE_MASK; reg 427 drivers/rtc/rtc-ac100.c reg[4] = bin2bcd(rtc_tm->tm_mday) & AC100_RTC_DAY_MASK; reg 428 drivers/rtc/rtc-ac100.c reg[5] = bin2bcd(rtc_tm->tm_mon + 1) & AC100_RTC_MON_MASK; reg 429 drivers/rtc/rtc-ac100.c reg[6] = bin2bcd(year) & AC100_RTC_YEA_MASK; reg 431 drivers/rtc/rtc-ac100.c reg[7] = AC100_RTC_UPD_TRIGGER; reg 435 drivers/rtc/rtc-ac100.c reg[6] |= AC100_RTC_YEA_LEAP; reg 437 drivers/rtc/rtc-ac100.c return regmap_bulk_write(regmap, AC100_RTC_SEC, reg, 8); reg 456 drivers/rtc/rtc-ac100.c u16 reg[7]; reg 466 drivers/rtc/rtc-ac100.c ret = regmap_bulk_read(regmap, AC100_ALM_SEC, reg, 7); reg 470 drivers/rtc/rtc-ac100.c alrm_tm->tm_sec = bcd2bin(reg[0] & AC100_ALM_SEC_MASK); reg 471 drivers/rtc/rtc-ac100.c alrm_tm->tm_min = bcd2bin(reg[1] & AC100_ALM_MIN_MASK); reg 472 drivers/rtc/rtc-ac100.c alrm_tm->tm_hour = bcd2bin(reg[2] & AC100_ALM_HOU_MASK); reg 473 drivers/rtc/rtc-ac100.c alrm_tm->tm_wday = bcd2bin(reg[3] & AC100_ALM_WEE_MASK); reg 474 drivers/rtc/rtc-ac100.c alrm_tm->tm_mday = bcd2bin(reg[4] & AC100_ALM_DAY_MASK); reg 475 drivers/rtc/rtc-ac100.c alrm_tm->tm_mon = bcd2bin(reg[5] & AC100_ALM_MON_MASK) - 1; reg 476 drivers/rtc/rtc-ac100.c alrm_tm->tm_year = bcd2bin(reg[6] & AC100_ALM_YEA_MASK) + reg 487 drivers/rtc/rtc-ac100.c u16 reg[8]; reg 500 drivers/rtc/rtc-ac100.c reg[0] = (bin2bcd(alrm_tm->tm_sec) & AC100_ALM_SEC_MASK) | reg 502 drivers/rtc/rtc-ac100.c reg[1] = (bin2bcd(alrm_tm->tm_min) & AC100_ALM_MIN_MASK) | reg 504 drivers/rtc/rtc-ac100.c reg[2] = (bin2bcd(alrm_tm->tm_hour) & AC100_ALM_HOU_MASK) | reg 507 drivers/rtc/rtc-ac100.c reg[3] = bin2bcd(alrm_tm->tm_wday) & AC100_ALM_WEE_MASK; reg 508 drivers/rtc/rtc-ac100.c reg[4] = (bin2bcd(alrm_tm->tm_mday) & AC100_ALM_DAY_MASK) | reg 510 drivers/rtc/rtc-ac100.c reg[5] = (bin2bcd(alrm_tm->tm_mon + 1) & AC100_ALM_MON_MASK) | reg 512 drivers/rtc/rtc-ac100.c reg[6] = (bin2bcd(year) & AC100_ALM_YEA_MASK) | reg 515 drivers/rtc/rtc-ac100.c reg[7] = AC100_ALM_UPD_TRIGGER; reg 517 drivers/rtc/rtc-ac100.c ret = regmap_bulk_write(regmap, AC100_ALM_SEC, reg, 8); reg 115 drivers/rtc/rtc-armada38x.c u32 reg; reg 117 drivers/rtc/rtc-armada38x.c reg = readl(rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL); reg 118 drivers/rtc/rtc-armada38x.c reg &= ~RTC_38X_PERIOD_MASK; reg 119 drivers/rtc/rtc-armada38x.c reg |= 0x3FF << RTC_38X_PERIOD_OFFS; /* Maximum value */ reg 120 drivers/rtc/rtc-armada38x.c reg &= ~RTC_38X_READ_DELAY_MASK; reg 121 drivers/rtc/rtc-armada38x.c reg |= 0x1F << RTC_38X_READ_DELAY_OFFS; /* Maximum value */ reg 122 drivers/rtc/rtc-armada38x.c writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL); reg 127 drivers/rtc/rtc-armada38x.c u32 reg; reg 129 drivers/rtc/rtc-armada38x.c reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0); reg 130 drivers/rtc/rtc-armada38x.c reg &= ~RTC_8K_WRCLK_PERIOD_MASK; reg 131 drivers/rtc/rtc-armada38x.c reg |= 0x3FF << RTC_8K_WRCLK_PERIOD_OFFS; reg 132 drivers/rtc/rtc-armada38x.c reg &= ~RTC_8K_WRCLK_SETUP_MASK; reg 133 drivers/rtc/rtc-armada38x.c reg |= 0x29 << RTC_8K_WRCLK_SETUP_OFFS; reg 134 drivers/rtc/rtc-armada38x.c writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0); reg 136 drivers/rtc/rtc-armada38x.c reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1); reg 137 drivers/rtc/rtc-armada38x.c reg &= ~RTC_8K_READ_DELAY_MASK; reg 138 drivers/rtc/rtc-armada38x.c reg |= 0x3F << RTC_8K_READ_DELAY_OFFS; reg 139 drivers/rtc/rtc-armada38x.c writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1); reg 229 drivers/rtc/rtc-armada38x.c u32 reg; reg 231 drivers/rtc/rtc-armada38x.c reg = rtc->data->read_rtc_reg(rtc, RTC_CONF_TEST); reg 233 drivers/rtc/rtc-armada38x.c if (reg & 0xff) { reg 265 drivers/rtc/rtc-armada38x.c u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm); reg 271 drivers/rtc/rtc-armada38x.c time = rtc->data->read_rtc_reg(rtc, reg); reg 285 drivers/rtc/rtc-armada38x.c u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm); reg 293 drivers/rtc/rtc-armada38x.c rtc_delayed_write(time, rtc, reg); reg 144 drivers/rtc/rtc-bq32k.c unsigned char reg; reg 162 drivers/rtc/rtc-bq32k.c reg = 0x05; reg 172 drivers/rtc/rtc-bq32k.c reg = 0x45; reg 180 drivers/rtc/rtc-bq32k.c error = bq32k_write(dev, ®, BQ32K_CFG2, 1); reg 184 drivers/rtc/rtc-bq32k.c reg = 0x20; reg 185 drivers/rtc/rtc-bq32k.c error = bq32k_write(dev, ®, BQ32K_TCH2, 1); reg 197 drivers/rtc/rtc-bq32k.c int reg, error; reg 199 drivers/rtc/rtc-bq32k.c error = bq32k_read(dev, ®, BQ32K_CFG2, 1); reg 203 drivers/rtc/rtc-bq32k.c return sprintf(buf, "%d\n", (reg & BQ32K_TCFE) ? 1 : 0); reg 210 drivers/rtc/rtc-bq32k.c int reg, enable, error; reg 215 drivers/rtc/rtc-bq32k.c error = bq32k_read(dev, ®, BQ32K_CFG2, 1); reg 220 drivers/rtc/rtc-bq32k.c reg |= BQ32K_TCFE; reg 221 drivers/rtc/rtc-bq32k.c error = bq32k_write(dev, ®, BQ32K_CFG2, 1); reg 227 drivers/rtc/rtc-bq32k.c reg &= ~BQ32K_TCFE; reg 228 drivers/rtc/rtc-bq32k.c error = bq32k_write(dev, ®, BQ32K_CFG2, 1); reg 257 drivers/rtc/rtc-bq32k.c uint8_t reg; reg 264 drivers/rtc/rtc-bq32k.c error = bq32k_read(dev, ®, BQ32K_SECONDS, 1); reg 265 drivers/rtc/rtc-bq32k.c if (!error && (reg & BQ32K_STOP)) { reg 267 drivers/rtc/rtc-bq32k.c reg &= ~BQ32K_STOP; reg 268 drivers/rtc/rtc-bq32k.c error = bq32k_write(dev, ®, BQ32K_SECONDS, 1); reg 274 drivers/rtc/rtc-bq32k.c error = bq32k_read(dev, ®, BQ32K_MINUTES, 1); reg 277 drivers/rtc/rtc-bq32k.c if (reg & BQ32K_OF) reg 150 drivers/rtc/rtc-brcmstb-waketimer.c u32 reg; reg 159 drivers/rtc/rtc-brcmstb-waketimer.c reg = readl_relaxed(timer->base + BRCMSTB_WKTMR_EVENT); reg 160 drivers/rtc/rtc-brcmstb-waketimer.c alarm->pending = !!(reg & 1); reg 89 drivers/rtc/rtc-cadence.c u32 reg = enabled ? 0x0 : CDNS_RTC_CTLR_TIME_CAL; reg 91 drivers/rtc/rtc-cadence.c writel(reg, crtc->regs + CDNS_RTC_CTLR); reg 119 drivers/rtc/rtc-cadence.c static void cdns_rtc_reg2time(u32 reg, struct rtc_time *tm) reg 121 drivers/rtc/rtc-cadence.c tm->tm_sec = bcd2bin(FIELD_GET(CDNS_RTC_TIME_S, reg)); reg 122 drivers/rtc/rtc-cadence.c tm->tm_min = bcd2bin(FIELD_GET(CDNS_RTC_TIME_M, reg)); reg 123 drivers/rtc/rtc-cadence.c tm->tm_hour = bcd2bin(FIELD_GET(CDNS_RTC_TIME_HR, reg)); reg 129 drivers/rtc/rtc-cadence.c u32 reg; reg 137 drivers/rtc/rtc-cadence.c reg = readl(crtc->regs + CDNS_RTC_TIMR); reg 138 drivers/rtc/rtc-cadence.c cdns_rtc_reg2time(reg, tm); reg 140 drivers/rtc/rtc-cadence.c reg = readl(crtc->regs + CDNS_RTC_CALR); reg 141 drivers/rtc/rtc-cadence.c tm->tm_mday = bcd2bin(FIELD_GET(CDNS_RTC_CAL_D, reg)); reg 142 drivers/rtc/rtc-cadence.c tm->tm_mon = bcd2bin(FIELD_GET(CDNS_RTC_CAL_M, reg)) - 1; reg 143 drivers/rtc/rtc-cadence.c tm->tm_year = bcd2bin(FIELD_GET(CDNS_RTC_CAL_Y, reg)) reg 144 drivers/rtc/rtc-cadence.c + bcd2bin(FIELD_GET(CDNS_RTC_CAL_C, reg)) * 100 - 1900; reg 145 drivers/rtc/rtc-cadence.c tm->tm_wday = bcd2bin(FIELD_GET(CDNS_RTC_CAL_DAY, reg)) - 1; reg 205 drivers/rtc/rtc-cadence.c u32 reg; reg 207 drivers/rtc/rtc-cadence.c reg = readl(crtc->regs + CDNS_RTC_TIMAR); reg 208 drivers/rtc/rtc-cadence.c cdns_rtc_reg2time(reg, &alarm->time); reg 210 drivers/rtc/rtc-cadence.c reg = readl(crtc->regs + CDNS_RTC_CALAR); reg 211 drivers/rtc/rtc-cadence.c alarm->time.tm_mday = bcd2bin(FIELD_GET(CDNS_RTC_CAL_D, reg)); reg 212 drivers/rtc/rtc-cadence.c alarm->time.tm_mon = bcd2bin(FIELD_GET(CDNS_RTC_CAL_M, reg)) - 1; reg 25 drivers/rtc/rtc-ds1286.c static inline u8 ds1286_rtc_read(struct ds1286_priv *priv, int reg) reg 27 drivers/rtc/rtc-ds1286.c return __raw_readl(&priv->rtcregs[reg]) & 0xff; reg 30 drivers/rtc/rtc-ds1286.c static inline void ds1286_rtc_write(struct ds1286_priv *priv, u8 data, int reg) reg 32 drivers/rtc/rtc-ds1286.c __raw_writel(data, &priv->rtcregs[reg]); reg 636 drivers/rtc/rtc-ds1307.c int ret, reg; reg 641 drivers/rtc/rtc-ds1307.c ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®); reg 646 drivers/rtc/rtc-ds1307.c reg |= RX8130_REG_CONTROL0_AIE; reg 648 drivers/rtc/rtc-ds1307.c reg &= ~RX8130_REG_CONTROL0_AIE; reg 650 drivers/rtc/rtc-ds1307.c return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg); reg 657 drivers/rtc/rtc-ds1307.c int reg, ret; reg 662 drivers/rtc/rtc-ds1307.c ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®); reg 665 drivers/rtc/rtc-ds1307.c if (!(reg & MCP794XX_BIT_ALMX_IF)) reg 667 drivers/rtc/rtc-ds1307.c reg &= ~MCP794XX_BIT_ALMX_IF; reg 668 drivers/rtc/rtc-ds1307.c ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg); reg 86 drivers/rtc/rtc-ds1374.c int reg, int nbytes) reg 95 drivers/rtc/rtc-ds1374.c ret = i2c_smbus_read_i2c_block_data(client, reg, nbytes, buf); reg 109 drivers/rtc/rtc-ds1374.c int reg, int nbytes) reg 124 drivers/rtc/rtc-ds1374.c return i2c_smbus_write_i2c_block_data(client, reg, nbytes, buf); reg 102 drivers/rtc/rtc-ds1511.c rtc_write(uint8_t val, uint32_t reg) reg 104 drivers/rtc/rtc-ds1511.c writeb(val, ds1511_base + (reg * reg_spacing)); reg 108 drivers/rtc/rtc-ds1511.c rtc_write_alarm(uint8_t val, enum ds1511reg reg) reg 110 drivers/rtc/rtc-ds1511.c rtc_write((val | 0x80), reg); reg 114 drivers/rtc/rtc-ds1511.c rtc_read(enum ds1511reg reg) reg 116 drivers/rtc/rtc-ds1511.c return readb(ds1511_base + (reg * reg_spacing)); reg 42 drivers/rtc/rtc-ds1685.c ds1685_read(struct ds1685_priv *rtc, int reg) reg 45 drivers/rtc/rtc-ds1685.c (reg * rtc->regstep)); reg 55 drivers/rtc/rtc-ds1685.c ds1685_write(struct ds1685_priv *rtc, int reg, u8 value) reg 58 drivers/rtc/rtc-ds1685.c (reg * rtc->regstep))); reg 46 drivers/rtc/rtc-fsl-ftm-alarm.c static inline u32 rtc_readl(struct ftm_rtc *dev, u32 reg) reg 49 drivers/rtc/rtc-fsl-ftm-alarm.c return ioread32be(dev->base + reg); reg 51 drivers/rtc/rtc-fsl-ftm-alarm.c return ioread32(dev->base + reg); reg 54 drivers/rtc/rtc-fsl-ftm-alarm.c static inline void rtc_writel(struct ftm_rtc *dev, u32 reg, u32 val) reg 57 drivers/rtc/rtc-fsl-ftm-alarm.c iowrite32be(val, dev->base + reg); reg 59 drivers/rtc/rtc-fsl-ftm-alarm.c iowrite32(val, dev->base + reg); reg 171 drivers/rtc/rtc-imxdi.c unsigned reg) reg 174 drivers/rtc/rtc-imxdi.c writel(val, imxdi->ioaddr + reg); reg 496 drivers/rtc/rtc-imxdi.c static int di_write_wait(struct imxdi_dev *imxdi, u32 val, int reg) reg 510 drivers/rtc/rtc-imxdi.c writel(val, imxdi->ioaddr + reg); reg 521 drivers/rtc/rtc-imxdi.c "val = 0x%08x reg = 0x%08x\n", val, reg); reg 50 drivers/rtc/rtc-isl12022.c static int isl12022_read_regs(struct i2c_client *client, uint8_t reg, reg 70 drivers/rtc/rtc-isl12022.c data[0] = reg; reg 83 drivers/rtc/rtc-isl12022.c uint8_t reg, uint8_t val) reg 85 drivers/rtc/rtc-isl12022.c uint8_t data[2] = { reg, val }; reg 43 drivers/rtc/rtc-isl12026.c static int isl12026_read_reg(struct i2c_client *client, int reg) reg 45 drivers/rtc/rtc-isl12026.c u8 addr[] = {0, reg}; reg 136 drivers/rtc/rtc-isl12026.c static int isl12026_write_reg(struct i2c_client *client, int reg, u8 val) reg 139 drivers/rtc/rtc-isl12026.c u8 op[3] = {0, reg, val}; reg 120 drivers/rtc/rtc-isl1208.c isl1208_i2c_read_regs(struct i2c_client *client, u8 reg, u8 buf[], reg 125 drivers/rtc/rtc-isl1208.c WARN_ON(reg > ISL1219_REG_YRT); reg 126 drivers/rtc/rtc-isl1208.c WARN_ON(reg + len > ISL1219_REG_YRT + 1); reg 128 drivers/rtc/rtc-isl1208.c ret = i2c_smbus_read_i2c_block_data(client, reg, len, buf); reg 134 drivers/rtc/rtc-isl1208.c isl1208_i2c_set_regs(struct i2c_client *client, u8 reg, u8 const buf[], reg 139 drivers/rtc/rtc-isl1208.c WARN_ON(reg > ISL1219_REG_YRT); reg 140 drivers/rtc/rtc-isl1208.c WARN_ON(reg + len > ISL1219_REG_YRT + 1); reg 142 drivers/rtc/rtc-isl1208.c ret = i2c_smbus_write_i2c_block_data(client, reg, len, buf); reg 69 drivers/rtc/rtc-jz4740.c static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg) reg 71 drivers/rtc/rtc-jz4740.c return readl(rtc->base + reg); reg 104 drivers/rtc/rtc-jz4740.c static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg, reg 114 drivers/rtc/rtc-jz4740.c writel(val, rtc->base + reg); reg 59 drivers/rtc/rtc-lpc24xx.c #define rtc_readl(dev, reg) readl((dev)->rtc_base + (reg)) reg 60 drivers/rtc/rtc-lpc24xx.c #define rtc_writel(dev, reg, val) writel((val), (dev)->rtc_base + (reg)) reg 42 drivers/rtc/rtc-lpc32xx.c #define rtc_readl(dev, reg) \ reg 43 drivers/rtc/rtc-lpc32xx.c __raw_readl((dev)->rtc_base + (reg)) reg 44 drivers/rtc/rtc-lpc32xx.c #define rtc_writel(dev, reg, val) \ reg 45 drivers/rtc/rtc-lpc32xx.c __raw_writel((val), (dev)->rtc_base + (reg)) reg 287 drivers/rtc/rtc-m41t80.c int reg; reg 290 drivers/rtc/rtc-m41t80.c reg = i2c_smbus_read_byte_data(client, M41T80_REG_FLAGS); reg 291 drivers/rtc/rtc-m41t80.c if (reg < 0) reg 292 drivers/rtc/rtc-m41t80.c return reg; reg 294 drivers/rtc/rtc-m41t80.c (reg & M41T80_FLAGS_BATT_LOW) ? "exhausted" : "ok"); reg 479 drivers/rtc/rtc-m41t80.c int reg, ret, val = 0; reg 488 drivers/rtc/rtc-m41t80.c reg = i2c_smbus_read_byte_data(client, reg_sqw); reg 489 drivers/rtc/rtc-m41t80.c if (reg < 0) reg 490 drivers/rtc/rtc-m41t80.c return reg; reg 492 drivers/rtc/rtc-m41t80.c reg = (reg & 0x0f) | (val << 4); reg 494 drivers/rtc/rtc-m41t80.c ret = i2c_smbus_write_byte_data(client, reg_sqw, reg); reg 38 drivers/rtc/rtc-m48t35.c struct m48t35_rtc __iomem *reg; reg 56 drivers/rtc/rtc-m48t35.c control = readb(&priv->reg->control); reg 57 drivers/rtc/rtc-m48t35.c writeb(control | M48T35_RTC_READ, &priv->reg->control); reg 58 drivers/rtc/rtc-m48t35.c tm->tm_sec = readb(&priv->reg->sec); reg 59 drivers/rtc/rtc-m48t35.c tm->tm_min = readb(&priv->reg->min); reg 60 drivers/rtc/rtc-m48t35.c tm->tm_hour = readb(&priv->reg->hour); reg 61 drivers/rtc/rtc-m48t35.c tm->tm_mday = readb(&priv->reg->date); reg 62 drivers/rtc/rtc-m48t35.c tm->tm_mon = readb(&priv->reg->month); reg 63 drivers/rtc/rtc-m48t35.c tm->tm_year = readb(&priv->reg->year); reg 64 drivers/rtc/rtc-m48t35.c writeb(control, &priv->reg->control); reg 121 drivers/rtc/rtc-m48t35.c control = readb(&priv->reg->control); reg 122 drivers/rtc/rtc-m48t35.c writeb(control | M48T35_RTC_SET, &priv->reg->control); reg 123 drivers/rtc/rtc-m48t35.c writeb(yrs, &priv->reg->year); reg 124 drivers/rtc/rtc-m48t35.c writeb(mon, &priv->reg->month); reg 125 drivers/rtc/rtc-m48t35.c writeb(day, &priv->reg->date); reg 126 drivers/rtc/rtc-m48t35.c writeb(hrs, &priv->reg->hour); reg 127 drivers/rtc/rtc-m48t35.c writeb(min, &priv->reg->min); reg 128 drivers/rtc/rtc-m48t35.c writeb(sec, &priv->reg->sec); reg 129 drivers/rtc/rtc-m48t35.c writeb(control, &priv->reg->control); reg 162 drivers/rtc/rtc-m48t35.c priv->reg = devm_ioremap(&pdev->dev, priv->baseaddr, priv->size); reg 163 drivers/rtc/rtc-m48t35.c if (!priv->reg) reg 25 drivers/rtc/rtc-m48t59.c #define M48T59_READ(reg) (pdata->read_byte(dev, pdata->offset + reg)) reg 26 drivers/rtc/rtc-m48t59.c #define M48T59_WRITE(val, reg) \ reg 27 drivers/rtc/rtc-m48t59.c (pdata->write_byte(dev, pdata->offset + reg, val)) reg 29 drivers/rtc/rtc-m48t59.c #define M48T59_SET_BITS(mask, reg) \ reg 30 drivers/rtc/rtc-m48t59.c M48T59_WRITE((M48T59_READ(reg) | (mask)), (reg)) reg 31 drivers/rtc/rtc-m48t59.c #define M48T59_CLEAR_BITS(mask, reg) \ reg 32 drivers/rtc/rtc-m48t59.c M48T59_WRITE((M48T59_READ(reg) & ~(mask)), (reg)) reg 68 drivers/rtc/rtc-m48t86.c unsigned char reg; reg 70 drivers/rtc/rtc-m48t86.c reg = m48t86_readb(dev, M48T86_B); reg 72 drivers/rtc/rtc-m48t86.c if (reg & M48T86_B_DM) { reg 96 drivers/rtc/rtc-m48t86.c if (!(reg & M48T86_B_H24)) reg 105 drivers/rtc/rtc-m48t86.c unsigned char reg; reg 107 drivers/rtc/rtc-m48t86.c reg = m48t86_readb(dev, M48T86_B); reg 110 drivers/rtc/rtc-m48t86.c reg |= M48T86_B_SET | M48T86_B_H24; reg 111 drivers/rtc/rtc-m48t86.c m48t86_writeb(dev, reg, M48T86_B); reg 113 drivers/rtc/rtc-m48t86.c if (reg & M48T86_B_DM) { reg 134 drivers/rtc/rtc-m48t86.c reg &= ~M48T86_B_SET; reg 135 drivers/rtc/rtc-m48t86.c m48t86_writeb(dev, reg, M48T86_B); reg 142 drivers/rtc/rtc-m48t86.c unsigned char reg; reg 144 drivers/rtc/rtc-m48t86.c reg = m48t86_readb(dev, M48T86_B); reg 147 drivers/rtc/rtc-m48t86.c (reg & M48T86_B_DM) ? "binary" : "bcd"); reg 149 drivers/rtc/rtc-m48t86.c reg = m48t86_readb(dev, M48T86_D); reg 152 drivers/rtc/rtc-m48t86.c (reg & M48T86_D_VRT) ? "ok" : "exhausted"); reg 222 drivers/rtc/rtc-m48t86.c unsigned char reg; reg 273 drivers/rtc/rtc-m48t86.c reg = m48t86_readb(&pdev->dev, M48T86_D); reg 275 drivers/rtc/rtc-m48t86.c (reg & M48T86_D_VRT) ? "ok" : "exhausted"); reg 159 drivers/rtc/rtc-meson.c static int meson_rtc_serial_bus_reg_read(void *context, unsigned int reg, reg 171 drivers/rtc/rtc-meson.c meson_rtc_send_bits(rtc, reg, RTC_ADDR_BITS); reg 178 drivers/rtc/rtc-meson.c static int meson_rtc_serial_bus_reg_write(void *context, unsigned int reg, reg 191 drivers/rtc/rtc-meson.c meson_rtc_send_bits(rtc, reg, RTC_ADDR_BITS); reg 80 drivers/rtc/rtc-msm6242.c unsigned int reg) reg 82 drivers/rtc/rtc-msm6242.c return __raw_readl(&priv->regs[reg]) & 0xf; reg 86 drivers/rtc/rtc-msm6242.c unsigned int reg) reg 88 drivers/rtc/rtc-msm6242.c __raw_writel(val, &priv->regs[reg]); reg 92 drivers/rtc/rtc-msm6242.c unsigned int reg) reg 94 drivers/rtc/rtc-msm6242.c msm6242_write(priv, msm6242_read(priv, reg) | val, reg); reg 98 drivers/rtc/rtc-msm6242.c unsigned int reg) reg 100 drivers/rtc/rtc-msm6242.c msm6242_write(priv, msm6242_read(priv, reg) & ~val, reg); reg 108 drivers/rtc/rtc-mt7622.c static void mtk_w32(struct mtk_rtc *rtc, u32 reg, u32 val) reg 110 drivers/rtc/rtc-mt7622.c writel_relaxed(val, rtc->base + reg); reg 113 drivers/rtc/rtc-mt7622.c static u32 mtk_r32(struct mtk_rtc *rtc, u32 reg) reg 115 drivers/rtc/rtc-mt7622.c return readl_relaxed(rtc->base + reg); reg 118 drivers/rtc/rtc-mt7622.c static void mtk_rmw(struct mtk_rtc *rtc, u32 reg, u32 mask, u32 set) reg 122 drivers/rtc/rtc-mt7622.c val = mtk_r32(rtc, reg); reg 125 drivers/rtc/rtc-mt7622.c mtk_w32(rtc, reg, val); reg 128 drivers/rtc/rtc-mt7622.c static void mtk_set(struct mtk_rtc *rtc, u32 reg, u32 val) reg 130 drivers/rtc/rtc-mt7622.c mtk_rmw(rtc, reg, 0, val); reg 133 drivers/rtc/rtc-mt7622.c static void mtk_clr(struct mtk_rtc *rtc, u32 reg, u32 val) reg 135 drivers/rtc/rtc-mt7622.c mtk_rmw(rtc, reg, val, 0); reg 186 drivers/rtc/rtc-mxc.c u32 reg; reg 190 drivers/rtc/rtc-mxc.c reg = readw(ioaddr + RTC_RTCIENR); reg 193 drivers/rtc/rtc-mxc.c reg |= bit; reg 195 drivers/rtc/rtc-mxc.c reg &= ~bit; reg 197 drivers/rtc/rtc-mxc.c writew(reg, ioaddr + RTC_RTCIENR); reg 314 drivers/rtc/rtc-mxc.c u32 reg; reg 381 drivers/rtc/rtc-mxc.c reg = RTC_INPUT_CLK_32768HZ; reg 383 drivers/rtc/rtc-mxc.c reg = RTC_INPUT_CLK_32000HZ; reg 385 drivers/rtc/rtc-mxc.c reg = RTC_INPUT_CLK_38400HZ; reg 392 drivers/rtc/rtc-mxc.c reg |= RTC_ENABLE_BIT; reg 393 drivers/rtc/rtc-mxc.c writew(reg, (pdata->ioaddr + RTC_RTCCTL)); reg 155 drivers/rtc/rtc-omap.c static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg) reg 157 drivers/rtc/rtc-omap.c return readb(rtc->base + reg); reg 160 drivers/rtc/rtc-omap.c static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg) reg 162 drivers/rtc/rtc-omap.c return readl(rtc->base + reg); reg 165 drivers/rtc/rtc-omap.c static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val) reg 167 drivers/rtc/rtc-omap.c writeb(val, rtc->base + reg); reg 170 drivers/rtc/rtc-omap.c static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val) reg 172 drivers/rtc/rtc-omap.c writel(val, rtc->base + reg); reg 243 drivers/rtc/rtc-omap.c u8 reg, irqwake_reg = 0; reg 247 drivers/rtc/rtc-omap.c reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); reg 252 drivers/rtc/rtc-omap.c reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; reg 255 drivers/rtc/rtc-omap.c reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; reg 260 drivers/rtc/rtc-omap.c rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); reg 368 drivers/rtc/rtc-omap.c u8 reg, irqwake_reg = 0; reg 383 drivers/rtc/rtc-omap.c reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); reg 388 drivers/rtc/rtc-omap.c reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; reg 391 drivers/rtc/rtc-omap.c reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; reg 394 drivers/rtc/rtc-omap.c rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); reg 731 drivers/rtc/rtc-omap.c u8 reg, mask, new_ctrl; reg 791 drivers/rtc/rtc-omap.c reg = rtc_read(rtc, OMAP_RTC_OSC_REG); reg 793 drivers/rtc/rtc-omap.c reg | OMAP_RTC_OSC_32KCLK_EN); reg 797 drivers/rtc/rtc-omap.c reg = rtc_read(rtc, OMAP_RTC_STATUS_REG); reg 806 drivers/rtc/rtc-omap.c if (reg & OMAP_RTC_STATUS_POWER_UP) reg 810 drivers/rtc/rtc-omap.c if (reg & mask) reg 811 drivers/rtc/rtc-omap.c rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask); reg 814 drivers/rtc/rtc-omap.c reg = rtc_read(rtc, OMAP_RTC_CTRL_REG); reg 815 drivers/rtc/rtc-omap.c if (reg & OMAP_RTC_CTRL_STOP) reg 819 drivers/rtc/rtc-omap.c new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP); reg 840 drivers/rtc/rtc-omap.c if (reg != new_ctrl) reg 848 drivers/rtc/rtc-omap.c reg = rtc_read(rtc, OMAP_RTC_OSC_REG); reg 849 drivers/rtc/rtc-omap.c reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE; reg 850 drivers/rtc/rtc-omap.c reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC; reg 851 drivers/rtc/rtc-omap.c rtc_writel(rtc, OMAP_RTC_OSC_REG, reg); reg 922 drivers/rtc/rtc-omap.c u8 reg; reg 940 drivers/rtc/rtc-omap.c reg = rtc_read(rtc, OMAP_RTC_OSC_REG); reg 941 drivers/rtc/rtc-omap.c reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC; reg 942 drivers/rtc/rtc-omap.c rtc_write(rtc, OMAP_RTC_OSC_REG, reg); reg 267 drivers/rtc/rtc-palmas.c unsigned reg = PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG; reg 270 drivers/rtc/rtc-palmas.c reg = 0; reg 274 drivers/rtc/rtc-palmas.c PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG, reg); reg 124 drivers/rtc/rtc-pcf2123.c unsigned int reg; reg 126 drivers/rtc/rtc-pcf2123.c ret = regmap_read(pcf2123->map, PCF2123_REG_OFFSET, ®); reg 130 drivers/rtc/rtc-pcf2123.c val = sign_extend32((reg & OFFSET_MASK), OFFSET_SIGN_BIT); reg 132 drivers/rtc/rtc-pcf2123.c if (reg & OFFSET_COARSE) reg 153 drivers/rtc/rtc-pcf2123.c s8 reg; reg 156 drivers/rtc/rtc-pcf2123.c reg = 127; reg 158 drivers/rtc/rtc-pcf2123.c reg = -128; reg 160 drivers/rtc/rtc-pcf2123.c reg = DIV_ROUND_CLOSEST(offset, OFFSET_STEP); reg 163 drivers/rtc/rtc-pcf2123.c if (reg & 1 && reg <= 63 && reg >= -64) { reg 165 drivers/rtc/rtc-pcf2123.c reg &= ~OFFSET_COARSE; reg 168 drivers/rtc/rtc-pcf2123.c reg >>= 1; reg 169 drivers/rtc/rtc-pcf2123.c reg |= OFFSET_COARSE; reg 172 drivers/rtc/rtc-pcf2123.c return regmap_write(pcf2123->map, PCF2123_REG_OFFSET, (unsigned int)reg); reg 564 drivers/rtc/rtc-pcf2127.c const void *reg, size_t reg_size, reg 579 drivers/rtc/rtc-pcf2127.c memcpy(buf, reg, 1); reg 592 drivers/rtc/rtc-pcf2127.c static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size, reg 602 drivers/rtc/rtc-pcf2127.c ret = i2c_master_send(client, reg, 1); reg 238 drivers/rtc/rtc-pcf85063.c u32 reg; reg 241 drivers/rtc/rtc-pcf85063.c ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, ®); reg 245 drivers/rtc/rtc-pcf85063.c val = sign_extend32(reg & ~PCF85063_OFFSET_MODE, reg 248 drivers/rtc/rtc-pcf85063.c if (reg & PCF85063_OFFSET_MODE) reg 259 drivers/rtc/rtc-pcf85063.c s8 mode0, mode1, reg; reg 273 drivers/rtc/rtc-pcf85063.c reg = mode0 & ~PCF85063_OFFSET_MODE; reg 275 drivers/rtc/rtc-pcf85063.c reg = mode1 | PCF85063_OFFSET_MODE; reg 277 drivers/rtc/rtc-pcf85063.c return regmap_write(pcf85063->regmap, PCF85063_REG_OFFSET, reg); reg 349 drivers/rtc/rtc-pcf85063.c u8 reg = 0; reg 364 drivers/rtc/rtc-pcf85063.c reg = PCF85063_REG_CTRL1_CAP_SEL; reg 369 drivers/rtc/rtc-pcf85063.c PCF85063_REG_CTRL1_CAP_SEL, reg); reg 42 drivers/rtc/rtc-pcf8523.c static int pcf8523_read(struct i2c_client *client, u8 reg, u8 *valuep) reg 50 drivers/rtc/rtc-pcf8523.c msgs[0].len = sizeof(reg); reg 51 drivers/rtc/rtc-pcf8523.c msgs[0].buf = ® reg 67 drivers/rtc/rtc-pcf8523.c static int pcf8523_write(struct i2c_client *client, u8 reg, u8 value) reg 69 drivers/rtc/rtc-pcf8523.c u8 buffer[2] = { reg, value }; reg 87 drivers/rtc/rtc-pcf8563.c static int pcf8563_read_block_data(struct i2c_client *client, unsigned char reg, reg 94 drivers/rtc/rtc-pcf8563.c .buf = ®, reg 113 drivers/rtc/rtc-pcf8563.c unsigned char reg, unsigned char length, reg 119 drivers/rtc/rtc-pcf8563.c unsigned char data[2] = { reg + i, buf[i] }; reg 179 drivers/rtc/rtc-pm8xxx.c unsigned int reg; reg 193 drivers/rtc/rtc-pm8xxx.c rc = regmap_read(rtc_dd->regmap, regs->read, ®); reg 199 drivers/rtc/rtc-pm8xxx.c if (unlikely(reg < value[0])) { reg 71 drivers/rtc/rtc-pxa.c #define rtc_readl(pxa_rtc, reg) \ reg 72 drivers/rtc/rtc-pxa.c __raw_readl((pxa_rtc)->base + (reg)) reg 73 drivers/rtc/rtc-pxa.c #define rtc_writel(pxa_rtc, reg, value) \ reg 74 drivers/rtc/rtc-pxa.c __raw_writel((value), (pxa_rtc)->base + (reg)) reg 64 drivers/rtc/rtc-r7301.c static u8 rtc7301_read(struct rtc7301_priv *priv, unsigned int reg) reg 69 drivers/rtc/rtc-r7301.c regmap_read(priv->regmap, reg_stride * reg, &val); reg 74 drivers/rtc/rtc-r7301.c static void rtc7301_write(struct rtc7301_priv *priv, u8 val, unsigned int reg) reg 78 drivers/rtc/rtc-r7301.c regmap_write(priv->regmap, reg_stride * reg, val); reg 81 drivers/rtc/rtc-r7301.c static void rtc7301_update_bits(struct rtc7301_priv *priv, unsigned int reg, reg 86 drivers/rtc/rtc-r7301.c regmap_update_bits(priv->regmap, reg_stride * reg, mask, val); reg 71 drivers/rtc/rtc-rp5c01.c unsigned int reg) reg 73 drivers/rtc/rtc-rp5c01.c return __raw_readl(&priv->regs[reg]) & 0xf; reg 77 drivers/rtc/rtc-rp5c01.c unsigned int reg) reg 79 drivers/rtc/rtc-rp5c01.c __raw_writel(val, &priv->regs[reg]); reg 180 drivers/rtc/rtc-rs5c372.c static unsigned rs5c_reg2hr(struct rs5c372 *rs5c, unsigned reg) reg 185 drivers/rtc/rtc-rs5c372.c return bcd2bin(reg & 0x3f); reg 187 drivers/rtc/rtc-rs5c372.c hour = bcd2bin(reg & 0x1f); reg 190 drivers/rtc/rtc-rs5c372.c if (reg & 0x20) reg 124 drivers/rtc/rtc-rv3029c2.c static int rv3029_read_regs(struct device *dev, u8 reg, u8 *buf, reg 129 drivers/rtc/rtc-rv3029c2.c if ((reg > RV3029_USR1_RAM_PAGE + 7) || reg 130 drivers/rtc/rtc-rv3029c2.c (reg + len > RV3029_USR1_RAM_PAGE + 8)) reg 133 drivers/rtc/rtc-rv3029c2.c return regmap_bulk_read(rv3029->regmap, reg, buf, len); reg 136 drivers/rtc/rtc-rv3029c2.c static int rv3029_write_regs(struct device *dev, u8 reg, u8 const buf[], reg 141 drivers/rtc/rtc-rv3029c2.c if ((reg > RV3029_USR1_RAM_PAGE + 7) || reg 142 drivers/rtc/rtc-rv3029c2.c (reg + len > RV3029_USR1_RAM_PAGE + 8)) reg 145 drivers/rtc/rtc-rv3029c2.c return regmap_bulk_write(rv3029->regmap, reg, buf, len); reg 148 drivers/rtc/rtc-rv3029c2.c static int rv3029_update_bits(struct device *dev, u8 reg, u8 mask, u8 set) reg 153 drivers/rtc/rtc-rv3029c2.c ret = rv3029_read_regs(dev, reg, &buf, 1); reg 158 drivers/rtc/rtc-rv3029c2.c ret = rv3029_write_regs(dev, reg, &buf, 1); reg 260 drivers/rtc/rtc-rv3029c2.c static int rv3029_eeprom_read(struct device *dev, u8 reg, reg 269 drivers/rtc/rtc-rv3029c2.c ret = rv3029_read_regs(dev, reg, buf, len); reg 278 drivers/rtc/rtc-rv3029c2.c static int rv3029_eeprom_write(struct device *dev, u8 reg, reg 289 drivers/rtc/rtc-rv3029c2.c for (i = 0; i < len; i++, reg++) { reg 290 drivers/rtc/rtc-rv3029c2.c ret = rv3029_read_regs(dev, reg, &tmp, 1); reg 294 drivers/rtc/rtc-rv3029c2.c ret = rv3029_write_regs(dev, reg, &buf[i], 1); reg 311 drivers/rtc/rtc-rv3029c2.c u8 reg, u8 mask, u8 set) reg 316 drivers/rtc/rtc-rv3029c2.c ret = rv3029_eeprom_read(dev, reg, &buf, 1); reg 321 drivers/rtc/rtc-rv3029c2.c ret = rv3029_eeprom_write(dev, reg, &buf, 1); reg 69 drivers/rtc/rtc-rv8803.c static int rv8803_read_reg(const struct i2c_client *client, u8 reg) reg 79 drivers/rtc/rtc-rv8803.c ret = i2c_smbus_read_byte_data(client, reg); reg 82 drivers/rtc/rtc-rv8803.c dev_err(&client->dev, "Unable to read register 0x%02x\n", reg); reg 88 drivers/rtc/rtc-rv8803.c u8 reg, u8 count, u8 *values) reg 94 drivers/rtc/rtc-rv8803.c ret = i2c_smbus_read_i2c_block_data(client, reg, count, values); reg 99 drivers/rtc/rtc-rv8803.c reg, reg + count - 1); reg 106 drivers/rtc/rtc-rv8803.c static int rv8803_write_reg(const struct i2c_client *client, u8 reg, u8 value) reg 112 drivers/rtc/rtc-rv8803.c ret = i2c_smbus_write_byte_data(client, reg, value); reg 115 drivers/rtc/rtc-rv8803.c dev_err(&client->dev, "Unable to write register 0x%02x\n", reg); reg 121 drivers/rtc/rtc-rv8803.c u8 reg, u8 count, const u8 *values) reg 127 drivers/rtc/rtc-rv8803.c ret = i2c_smbus_write_i2c_block_data(client, reg, count, reg 133 drivers/rtc/rtc-rv8803.c reg, reg + count - 1); reg 71 drivers/rtc/rtc-s35390a.c static int s35390a_set_reg(struct s35390a *s35390a, int reg, char *buf, int len) reg 73 drivers/rtc/rtc-s35390a.c struct i2c_client *client = s35390a->client[reg]; reg 88 drivers/rtc/rtc-s35390a.c static int s35390a_get_reg(struct s35390a *s35390a, int reg, char *buf, int len) reg 90 drivers/rtc/rtc-s35390a.c struct i2c_client *client = s35390a->client[reg]; reg 196 drivers/rtc/rtc-s35390a.c static int s35390a_reg2hr(struct s35390a *s35390a, char reg) reg 201 drivers/rtc/rtc-s35390a.c return bcd2bin(reg & 0x3f); reg 203 drivers/rtc/rtc-s35390a.c hour = bcd2bin(reg & 0x3f); reg 204 drivers/rtc/rtc-s35390a.c if (reg & 0x40) reg 226 drivers/rtc/rtc-sun6i.c u32 reg; reg 247 drivers/rtc/rtc-sun6i.c reg = SUN6I_LOSC_CTRL_KEY; reg 250 drivers/rtc/rtc-sun6i.c reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS; reg 251 drivers/rtc/rtc-sun6i.c writel(reg, rtc->base + SUN6I_LOSC_CTRL); reg 255 drivers/rtc/rtc-sun6i.c reg |= SUN6I_LOSC_CTRL_EXT_OSC; reg 257 drivers/rtc/rtc-sun6i.c reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; reg 258 drivers/rtc/rtc-sun6i.c writel(reg, rtc->base + SUN6I_LOSC_CTRL); reg 554 drivers/rtc/rtc-sun6i.c u32 reg; reg 557 drivers/rtc/rtc-sun6i.c reg = readl(chip->base + offset); reg 558 drivers/rtc/rtc-sun6i.c reg &= mask; reg 560 drivers/rtc/rtc-sun6i.c if (!reg) reg 314 drivers/rtc/rtc-sunxi.c u32 reg; reg 317 drivers/rtc/rtc-sunxi.c reg = readl(chip->base + offset); reg 318 drivers/rtc/rtc-sunxi.c reg &= mask; reg 320 drivers/rtc/rtc-sunxi.c if (reg == mask) reg 158 drivers/rtc/rtc-twl.c static int twl_rtc_read_u8(struct twl_rtc *twl_rtc, u8 *data, u8 reg) reg 162 drivers/rtc/rtc-twl.c ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (twl_rtc->reg_map[reg])); reg 164 drivers/rtc/rtc-twl.c pr_err("Could not read TWL register %X - error %d\n", reg, ret); reg 171 drivers/rtc/rtc-twl.c static int twl_rtc_write_u8(struct twl_rtc *twl_rtc, u8 data, u8 reg) reg 175 drivers/rtc/rtc-twl.c ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (twl_rtc->reg_map[reg])); reg 178 drivers/rtc/rtc-twl.c reg, ret); reg 98 drivers/rtc/rtc-wm831x.c u16 reg; reg 107 drivers/rtc/rtc-wm831x.c reg = ret; reg 108 drivers/rtc/rtc-wm831x.c add_device_randomness(®, sizeof(reg)); reg 340 drivers/rtc/rtc-wm8350.c u16 reg; reg 342 drivers/rtc/rtc-wm8350.c reg = wm8350_reg_read(wm8350, WM8350_RTC_TIME_CONTROL); reg 345 drivers/rtc/rtc-wm8350.c reg & WM8350_RTC_ALMSTS) { reg 377 drivers/rtc/rtc-x1205.c unsigned char reg, mask, min, max; reg 450 drivers/rtc/rtc-x1205.c unsigned char reg, value; reg 452 drivers/rtc/rtc-x1205.c unsigned char addr[2] = { 0, probe_limits_pattern[i].reg }; reg 464 drivers/rtc/rtc-x1205.c .buf = ® reg 472 drivers/rtc/rtc-x1205.c __func__, probe_limits_pattern[i].reg); reg 477 drivers/rtc/rtc-x1205.c value = bcd2bin(reg & probe_limits_pattern[i].mask); reg 483 drivers/rtc/rtc-x1205.c __func__, probe_limits_pattern[i].reg, reg 404 drivers/s390/char/sclp.c struct sclp_register *reg; reg 417 drivers/s390/char/sclp.c reg = NULL; reg 419 drivers/s390/char/sclp.c reg = list_entry(l, struct sclp_register, list); reg 420 drivers/s390/char/sclp.c if (reg->receive_mask & SCLP_EVTYP_MASK(evbuf->type)) reg 423 drivers/s390/char/sclp.c reg = NULL; reg 425 drivers/s390/char/sclp.c if (reg && reg->receiver_fn) { reg 427 drivers/s390/char/sclp.c reg->receiver_fn(evbuf); reg 429 drivers/s390/char/sclp.c } else if (reg == NULL) reg 586 drivers/s390/char/sclp.c struct sclp_register *reg; reg 593 drivers/s390/char/sclp.c reg = NULL; reg 595 drivers/s390/char/sclp.c reg = list_entry(l, struct sclp_register, list); reg 596 drivers/s390/char/sclp.c receive_mask = reg->send_mask & sclp_receive_mask; reg 597 drivers/s390/char/sclp.c send_mask = reg->receive_mask & sclp_send_mask; reg 598 drivers/s390/char/sclp.c if (reg->sclp_receive_mask != receive_mask || reg 599 drivers/s390/char/sclp.c reg->sclp_send_mask != send_mask) { reg 600 drivers/s390/char/sclp.c reg->sclp_receive_mask = receive_mask; reg 601 drivers/s390/char/sclp.c reg->sclp_send_mask = send_mask; reg 604 drivers/s390/char/sclp.c reg = NULL; reg 607 drivers/s390/char/sclp.c if (reg && reg->state_change_fn) reg 608 drivers/s390/char/sclp.c reg->state_change_fn(reg); reg 609 drivers/s390/char/sclp.c } while (reg); reg 675 drivers/s390/char/sclp.c sclp_register(struct sclp_register *reg) reg 688 drivers/s390/char/sclp.c if (reg->receive_mask & receive_mask || reg->send_mask & send_mask) { reg 693 drivers/s390/char/sclp.c reg->sclp_receive_mask = 0; reg 694 drivers/s390/char/sclp.c reg->sclp_send_mask = 0; reg 695 drivers/s390/char/sclp.c reg->pm_event_posted = 0; reg 696 drivers/s390/char/sclp.c list_add(®->list, &sclp_reg_list); reg 701 drivers/s390/char/sclp.c list_del(®->list); reg 711 drivers/s390/char/sclp.c sclp_unregister(struct sclp_register *reg) reg 716 drivers/s390/char/sclp.c list_del(®->list); reg 1019 drivers/s390/char/sclp.c struct sclp_register *reg; reg 1024 drivers/s390/char/sclp.c list_for_each_entry(reg, &sclp_reg_list, list) reg 1025 drivers/s390/char/sclp.c reg->pm_event_posted = 0; reg 1030 drivers/s390/char/sclp.c list_for_each_entry(reg, &sclp_reg_list, list) { reg 1031 drivers/s390/char/sclp.c if (rollback && reg->pm_event_posted) reg 1033 drivers/s390/char/sclp.c if (!rollback && !reg->pm_event_posted) reg 1040 drivers/s390/char/sclp.c if (reg->pm_event_fn) reg 1041 drivers/s390/char/sclp.c reg->pm_event_fn(reg, sclp_pm_event); reg 1042 drivers/s390/char/sclp.c reg->pm_event_posted = rollback ? 0 : 1; reg 301 drivers/s390/char/sclp.h int sclp_register(struct sclp_register *reg); reg 302 drivers/s390/char/sclp.h void sclp_unregister(struct sclp_register *reg); reg 52 drivers/s390/char/sclp_quiesce.c static void sclp_quiesce_pm_event(struct sclp_register *reg, reg 29 drivers/s390/char/sclp_rw.c static void sclp_rw_pm_event(struct sclp_register *reg, reg 475 drivers/s390/char/sclp_tty.c sclp_tty_state_change(struct sclp_register *reg) reg 98 drivers/s390/char/sclp_vt220.c static void sclp_vt220_pm_event_fn(struct sclp_register *reg, reg 824 drivers/s390/char/sclp_vt220.c static void sclp_vt220_pm_event_fn(struct sclp_register *reg, reg 151 drivers/s390/char/zcore.c struct memblock_region *reg; reg 159 drivers/s390/char/zcore.c for_each_memblock(memory, reg) { reg 161 drivers/s390/char/zcore.c (unsigned long long) reg->base, reg 162 drivers/s390/char/zcore.c (unsigned long long) reg->size); reg 92 drivers/sbus/char/bbc_i2c.c const u32 *reg; reg 100 drivers/sbus/char/bbc_i2c.c reg = of_get_property(op->dev.of_node, "reg", NULL); reg 101 drivers/sbus/char/bbc_i2c.c if (!reg) { reg 106 drivers/sbus/char/bbc_i2c.c client->bus = reg[0]; reg 107 drivers/sbus/char/bbc_i2c.c client->address = reg[1]; reg 1126 drivers/scsi/3w-sas.c u32 reg, regl, regh, response, request_id = 0; reg 1133 drivers/scsi/3w-sas.c reg = readl(TWL_HISTAT_REG_ADDR(tw_dev)); reg 1136 drivers/scsi/3w-sas.c if (!(reg & TWL_HISTATUS_VALID_INTERRUPT)) reg 1146 drivers/scsi/3w-sas.c if (reg & TWL_HISTATUS_ATTENTION_INTERRUPT) { reg 1154 drivers/scsi/3w-sas.c while (reg & TWL_HISTATUS_RESPONSE_INTERRUPT) { reg 1230 drivers/scsi/3w-sas.c reg = readl(TWL_HISTAT_REG_ADDR(tw_dev)); reg 1239 drivers/scsi/3w-sas.c static int twl_poll_register(TW_Device_Extension *tw_dev, void *reg, u32 value, u32 result, int seconds) reg 1245 drivers/scsi/3w-sas.c reg_value = readl(reg); reg 1249 drivers/scsi/3w-sas.c reg_value = readl(reg); reg 481 drivers/scsi/53c700.h NCR_700_readb(struct Scsi_Host *host, __u32 reg) reg 486 drivers/scsi/53c700.h return ioread8(hostdata->base + (reg^bE)); reg 490 drivers/scsi/53c700.h NCR_700_readl(struct Scsi_Host *host, __u32 reg) reg 494 drivers/scsi/53c700.h __u32 value = bEBus ? ioread32be(hostdata->base + reg) : reg 495 drivers/scsi/53c700.h ioread32(hostdata->base + reg); reg 498 drivers/scsi/53c700.h BUG_ON((reg & 0x3) != 0); reg 505 drivers/scsi/53c700.h NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg) reg 510 drivers/scsi/53c700.h iowrite8(value, hostdata->base + (reg^bE)); reg 514 drivers/scsi/53c700.h NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg) reg 521 drivers/scsi/53c700.h BUG_ON((reg & 0x3) != 0); reg 524 drivers/scsi/53c700.h bEBus ? iowrite32be(value, hostdata->base + reg): reg 525 drivers/scsi/53c700.h iowrite32(value, hostdata->base + reg); reg 286 drivers/scsi/NCR5380.h unsigned int reg, u8 bit, u8 val, reg 289 drivers/scsi/NCR5380.h if ((NCR5380_read(reg) & bit) == val) reg 292 drivers/scsi/NCR5380.h return NCR5380_poll_politely2(hostdata, reg, bit, val, reg 293 drivers/scsi/NCR5380.h reg, bit, val, wait); reg 482 drivers/scsi/aic7xxx/aic79xx_osm.c ahd_pci_read_config(ahd_dev_softc_t pci, int reg, int width) reg 489 drivers/scsi/aic7xxx/aic79xx_osm.c pci_read_config_byte(pci, reg, &retval); reg 495 drivers/scsi/aic7xxx/aic79xx_osm.c pci_read_config_word(pci, reg, &retval); reg 501 drivers/scsi/aic7xxx/aic79xx_osm.c pci_read_config_dword(pci, reg, &retval); reg 512 drivers/scsi/aic7xxx/aic79xx_osm.c ahd_pci_write_config(ahd_dev_softc_t pci, int reg, uint32_t value, int width) reg 516 drivers/scsi/aic7xxx/aic79xx_osm.c pci_write_config_byte(pci, reg, value); reg 519 drivers/scsi/aic7xxx/aic79xx_osm.c pci_write_config_word(pci, reg, value); reg 522 drivers/scsi/aic7xxx/aic79xx_osm.c pci_write_config_dword(pci, reg, value); reg 461 drivers/scsi/aic7xxx/aic79xx_osm.h int reg, int width); reg 463 drivers/scsi/aic7xxx/aic79xx_osm.h int reg, uint32_t value, reg 790 drivers/scsi/aic7xxx/aic79xx_pci.c u_int reg; reg 804 drivers/scsi/aic7xxx/aic79xx_pci.c for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { reg 808 drivers/scsi/aic7xxx/aic79xx_pci.c pci_status[i] = ahd_inb(ahd, reg); reg 810 drivers/scsi/aic7xxx/aic79xx_pci.c ahd_outb(ahd, reg, pci_status[i]); reg 470 drivers/scsi/aic7xxx/aic7xxx_osm.h int reg, int width); reg 473 drivers/scsi/aic7xxx/aic7xxx_osm.h int reg, uint32_t value, reg 274 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c ahc_pci_read_config(ahc_dev_softc_t pci, int reg, int width) reg 281 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c pci_read_config_byte(pci, reg, &retval); reg 287 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c pci_read_config_word(pci, reg, &retval); reg 293 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c pci_read_config_dword(pci, reg, &retval); reg 304 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c ahc_pci_write_config(ahc_dev_softc_t pci, int reg, uint32_t value, int width) reg 308 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c pci_write_config_byte(pci, reg, value); reg 311 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c pci_write_config_word(pci, reg, value); reg 314 drivers/scsi/aic7xxx/aic7xxx_osm_pci.c pci_write_config_dword(pci, reg, value); reg 418 drivers/scsi/aic94xx/aic94xx_hwi.c u32 reg; reg 426 drivers/scsi/aic94xx/aic94xx_hwi.c reg = asd_read_reg_dword(asd_ha, CHIMINT); reg 427 drivers/scsi/aic94xx/aic94xx_hwi.c if (reg & HARDRSTDET) { reg 110 drivers/scsi/aic94xx/aic94xx_reg.c u32 reg) \ reg 113 drivers/scsi/aic94xx/aic94xx_reg.c u32 map_offs = (reg - io_handle->ww##_base) + asd_mem_offs_##ww();\ reg 119 drivers/scsi/aic94xx/aic94xx_reg.c u32 reg, type val) \ reg 122 drivers/scsi/aic94xx/aic94xx_reg.c u32 map_offs = (reg - io_handle->ww##_base) + asd_mem_offs_##ww();\ reg 170 drivers/scsi/aic94xx/aic94xx_reg.c static void asd_move_swb(struct asd_ha_struct *asd_ha, u32 reg) reg 172 drivers/scsi/aic94xx/aic94xx_reg.c u32 base = reg & ~(MBAR0_SWB_SIZE-1); reg 177 drivers/scsi/aic94xx/aic94xx_reg.c static void __asd_write_reg_byte(struct asd_ha_struct *asd_ha, u32 reg, u8 val) reg 180 drivers/scsi/aic94xx/aic94xx_reg.c BUG_ON(reg >= 0xC0000000 || reg < ALL_BASE_ADDR); reg 181 drivers/scsi/aic94xx/aic94xx_reg.c if (io_handle->swa_base <= reg reg 182 drivers/scsi/aic94xx/aic94xx_reg.c && reg < io_handle->swa_base + MBAR0_SWA_SIZE) reg 183 drivers/scsi/aic94xx/aic94xx_reg.c asd_write_swa_byte (asd_ha, reg,val); reg 184 drivers/scsi/aic94xx/aic94xx_reg.c else if (io_handle->swb_base <= reg reg 185 drivers/scsi/aic94xx/aic94xx_reg.c && reg < io_handle->swb_base + MBAR0_SWB_SIZE) reg 186 drivers/scsi/aic94xx/aic94xx_reg.c asd_write_swb_byte (asd_ha, reg, val); reg 187 drivers/scsi/aic94xx/aic94xx_reg.c else if (io_handle->swc_base <= reg reg 188 drivers/scsi/aic94xx/aic94xx_reg.c && reg < io_handle->swc_base + MBAR0_SWC_SIZE) reg 189 drivers/scsi/aic94xx/aic94xx_reg.c asd_write_swc_byte (asd_ha, reg, val); reg 192 drivers/scsi/aic94xx/aic94xx_reg.c asd_move_swb(asd_ha, reg); reg 193 drivers/scsi/aic94xx/aic94xx_reg.c asd_write_swb_byte (asd_ha, reg, val); reg 198 drivers/scsi/aic94xx/aic94xx_reg.c void asd_write_reg_##ord (struct asd_ha_struct *asd_ha, u32 reg, type val)\ reg 202 drivers/scsi/aic94xx/aic94xx_reg.c BUG_ON(reg >= 0xC0000000 || reg < ALL_BASE_ADDR); \ reg 204 drivers/scsi/aic94xx/aic94xx_reg.c if (io_handle->swa_base <= reg \ reg 205 drivers/scsi/aic94xx/aic94xx_reg.c && reg < io_handle->swa_base + MBAR0_SWA_SIZE) \ reg 206 drivers/scsi/aic94xx/aic94xx_reg.c asd_write_swa_##ord (asd_ha, reg,val); \ reg 207 drivers/scsi/aic94xx/aic94xx_reg.c else if (io_handle->swb_base <= reg \ reg 208 drivers/scsi/aic94xx/aic94xx_reg.c && reg < io_handle->swb_base + MBAR0_SWB_SIZE) \ reg 209 drivers/scsi/aic94xx/aic94xx_reg.c asd_write_swb_##ord (asd_ha, reg, val); \ reg 210 drivers/scsi/aic94xx/aic94xx_reg.c else if (io_handle->swc_base <= reg \ reg 211 drivers/scsi/aic94xx/aic94xx_reg.c && reg < io_handle->swc_base + MBAR0_SWC_SIZE) \ reg 212 drivers/scsi/aic94xx/aic94xx_reg.c asd_write_swc_##ord (asd_ha, reg, val); \ reg 215 drivers/scsi/aic94xx/aic94xx_reg.c asd_move_swb(asd_ha, reg); \ reg 216 drivers/scsi/aic94xx/aic94xx_reg.c asd_write_swb_##ord (asd_ha, reg, val); \ reg 225 drivers/scsi/aic94xx/aic94xx_reg.c static u8 __asd_read_reg_byte(struct asd_ha_struct *asd_ha, u32 reg) reg 229 drivers/scsi/aic94xx/aic94xx_reg.c BUG_ON(reg >= 0xC0000000 || reg < ALL_BASE_ADDR); reg 230 drivers/scsi/aic94xx/aic94xx_reg.c if (io_handle->swa_base <= reg reg 231 drivers/scsi/aic94xx/aic94xx_reg.c && reg < io_handle->swa_base + MBAR0_SWA_SIZE) reg 232 drivers/scsi/aic94xx/aic94xx_reg.c val = asd_read_swa_byte (asd_ha, reg); reg 233 drivers/scsi/aic94xx/aic94xx_reg.c else if (io_handle->swb_base <= reg reg 234 drivers/scsi/aic94xx/aic94xx_reg.c && reg < io_handle->swb_base + MBAR0_SWB_SIZE) reg 235 drivers/scsi/aic94xx/aic94xx_reg.c val = asd_read_swb_byte (asd_ha, reg); reg 236 drivers/scsi/aic94xx/aic94xx_reg.c else if (io_handle->swc_base <= reg reg 237 drivers/scsi/aic94xx/aic94xx_reg.c && reg < io_handle->swc_base + MBAR0_SWC_SIZE) reg 238 drivers/scsi/aic94xx/aic94xx_reg.c val = asd_read_swc_byte (asd_ha, reg); reg 241 drivers/scsi/aic94xx/aic94xx_reg.c asd_move_swb(asd_ha, reg); reg 242 drivers/scsi/aic94xx/aic94xx_reg.c val = asd_read_swb_byte (asd_ha, reg); reg 248 drivers/scsi/aic94xx/aic94xx_reg.c type asd_read_reg_##ord (struct asd_ha_struct *asd_ha, u32 reg) \ reg 253 drivers/scsi/aic94xx/aic94xx_reg.c BUG_ON(reg >= 0xC0000000 || reg < ALL_BASE_ADDR); \ reg 255 drivers/scsi/aic94xx/aic94xx_reg.c if (io_handle->swa_base <= reg \ reg 256 drivers/scsi/aic94xx/aic94xx_reg.c && reg < io_handle->swa_base + MBAR0_SWA_SIZE) \ reg 257 drivers/scsi/aic94xx/aic94xx_reg.c val = asd_read_swa_##ord (asd_ha, reg); \ reg 258 drivers/scsi/aic94xx/aic94xx_reg.c else if (io_handle->swb_base <= reg \ reg 259 drivers/scsi/aic94xx/aic94xx_reg.c && reg < io_handle->swb_base + MBAR0_SWB_SIZE) \ reg 260 drivers/scsi/aic94xx/aic94xx_reg.c val = asd_read_swb_##ord (asd_ha, reg); \ reg 261 drivers/scsi/aic94xx/aic94xx_reg.c else if (io_handle->swc_base <= reg \ reg 262 drivers/scsi/aic94xx/aic94xx_reg.c && reg < io_handle->swc_base + MBAR0_SWC_SIZE) \ reg 263 drivers/scsi/aic94xx/aic94xx_reg.c val = asd_read_swc_##ord (asd_ha, reg); \ reg 266 drivers/scsi/aic94xx/aic94xx_reg.c asd_move_swb(asd_ha, reg); \ reg 267 drivers/scsi/aic94xx/aic94xx_reg.c val = asd_read_swb_##ord (asd_ha, reg); \ reg 46 drivers/scsi/aic94xx/aic94xx_reg.h u8 asd_read_reg_byte(struct asd_ha_struct *asd_ha, u32 reg); reg 47 drivers/scsi/aic94xx/aic94xx_reg.h u16 asd_read_reg_word(struct asd_ha_struct *asd_ha, u32 reg); reg 48 drivers/scsi/aic94xx/aic94xx_reg.h u32 asd_read_reg_dword(struct asd_ha_struct *asd_ha, u32 reg); reg 50 drivers/scsi/aic94xx/aic94xx_reg.h void asd_write_reg_byte(struct asd_ha_struct *asd_ha, u32 reg, u8 val); reg 51 drivers/scsi/aic94xx/aic94xx_reg.h void asd_write_reg_word(struct asd_ha_struct *asd_ha, u32 reg, u16 val); reg 52 drivers/scsi/aic94xx/aic94xx_reg.h void asd_write_reg_dword(struct asd_ha_struct *asd_ha, u32 reg, u32 val); reg 248 drivers/scsi/aic94xx/aic94xx_reg.h static inline void asd_write_reg_addr(struct asd_ha_struct *asd_ha, u32 reg, reg 251 drivers/scsi/aic94xx/aic94xx_reg.h asd_write_reg_dword(asd_ha, reg, ASD_BUSADDR_LO(dma_handle)); reg 252 drivers/scsi/aic94xx/aic94xx_reg.h asd_write_reg_dword(asd_ha, reg+4, ASD_BUSADDR_HI(dma_handle)); reg 1381 drivers/scsi/aic94xx/aic94xx_reg_def.h #define LmSEQ_OOB_REG(phy_id, reg) LmSEQ_PHY_REG(5, (phy_id), (reg)) reg 302 drivers/scsi/aic94xx/aic94xx_scb.c u8 reg = dl->status_block[1]; reg 303 drivers/scsi/aic94xx/aic94xx_scb.c u32 cont = dl->status_block[2] << ((reg & 3)*8); reg 305 drivers/scsi/aic94xx/aic94xx_scb.c reg &= ~3; reg 306 drivers/scsi/aic94xx/aic94xx_scb.c switch (reg) { reg 327 drivers/scsi/aic94xx/aic94xx_scb.c phy_id, reg, cont); reg 344 drivers/scsi/aic94xx/aic94xx_scb.c phy_id, reg, cont); reg 297 drivers/scsi/aic94xx/aic94xx_sds.c u32 reg; reg 302 drivers/scsi/aic94xx/aic94xx_sds.c reg = asd_read_reg_dword(asd_ha, EXSICNFGR); reg 304 drivers/scsi/aic94xx/aic94xx_sds.c if (!(reg & OCMINITIALIZED)) { reg 613 drivers/scsi/aic94xx/aic94xx_sds.c u32 reg; reg 615 drivers/scsi/aic94xx/aic94xx_sds.c reg = asd_read_reg_dword(asd_ha, EXSICNFGR); reg 624 drivers/scsi/aic94xx/aic94xx_sds.c asd_ha->hw_prof.flash.wide = reg & FLASHW ? 1 : 0; reg 1085 drivers/scsi/aic94xx/aic94xx_sds.c u32 nv_offset, reg, i; reg 1087 drivers/scsi/aic94xx/aic94xx_sds.c reg = asd_ha->hw_prof.flash.bar; reg 1094 drivers/scsi/aic94xx/aic94xx_sds.c flash_char = asd_read_reg_byte(asd_ha, reg + nv_offset + i); reg 1114 drivers/scsi/aic94xx/aic94xx_sds.c u32 nv_offset, reg, i; reg 1117 drivers/scsi/aic94xx/aic94xx_sds.c reg = asd_ha->hw_prof.flash.bar; reg 1147 drivers/scsi/aic94xx/aic94xx_sds.c (reg + 0xAAA), 0xAA); reg 1149 drivers/scsi/aic94xx/aic94xx_sds.c (reg + 0x555), 0x55); reg 1151 drivers/scsi/aic94xx/aic94xx_sds.c (reg + 0xAAA), 0xA0); reg 1153 drivers/scsi/aic94xx/aic94xx_sds.c (reg + nv_offset + i), reg 1160 drivers/scsi/aic94xx/aic94xx_sds.c (reg + 0x555), 0xAA); reg 1162 drivers/scsi/aic94xx/aic94xx_sds.c (reg + 0x2AA), 0x55); reg 1164 drivers/scsi/aic94xx/aic94xx_sds.c (reg + 0x555), 0xA0); reg 1166 drivers/scsi/aic94xx/aic94xx_sds.c (reg + nv_offset + i), reg 1176 drivers/scsi/aic94xx/aic94xx_sds.c reg + nv_offset + i); reg 1192 drivers/scsi/aic94xx/aic94xx_sds.c u32 reg; reg 1201 drivers/scsi/aic94xx/aic94xx_sds.c reg = asd_ha->hw_prof.flash.bar; reg 1204 drivers/scsi/aic94xx/aic94xx_sds.c nv_data1 = asd_read_reg_byte(asd_ha, reg); reg 1205 drivers/scsi/aic94xx/aic94xx_sds.c nv_data2 = asd_read_reg_byte(asd_ha, reg); reg 1215 drivers/scsi/aic94xx/aic94xx_sds.c reg); reg 1217 drivers/scsi/aic94xx/aic94xx_sds.c reg); reg 1254 drivers/scsi/aic94xx/aic94xx_sds.c u32 reg; reg 1257 drivers/scsi/aic94xx/aic94xx_sds.c reg = asd_ha->hw_prof.flash.bar; reg 1269 drivers/scsi/aic94xx/aic94xx_sds.c asd_write_reg_byte(asd_ha, (reg + 0xAAA), 0xAA); reg 1270 drivers/scsi/aic94xx/aic94xx_sds.c asd_write_reg_byte(asd_ha, (reg + 0x555), 0x55); reg 1271 drivers/scsi/aic94xx/aic94xx_sds.c asd_write_reg_byte(asd_ha, (reg + 0xAAA), 0x80); reg 1272 drivers/scsi/aic94xx/aic94xx_sds.c asd_write_reg_byte(asd_ha, (reg + 0xAAA), 0xAA); reg 1273 drivers/scsi/aic94xx/aic94xx_sds.c asd_write_reg_byte(asd_ha, (reg + 0x555), 0x55); reg 1274 drivers/scsi/aic94xx/aic94xx_sds.c asd_write_reg_byte(asd_ha, (reg + sector_addr), 0x30); reg 1277 drivers/scsi/aic94xx/aic94xx_sds.c asd_write_reg_byte(asd_ha, (reg + 0x555), 0xAA); reg 1278 drivers/scsi/aic94xx/aic94xx_sds.c asd_write_reg_byte(asd_ha, (reg + 0x2AA), 0x55); reg 1279 drivers/scsi/aic94xx/aic94xx_sds.c asd_write_reg_byte(asd_ha, (reg + 0x555), 0x80); reg 1280 drivers/scsi/aic94xx/aic94xx_sds.c asd_write_reg_byte(asd_ha, (reg + 0x555), 0xAA); reg 1281 drivers/scsi/aic94xx/aic94xx_sds.c asd_write_reg_byte(asd_ha, (reg + 0x2AA), 0x55); reg 1282 drivers/scsi/aic94xx/aic94xx_sds.c asd_write_reg_byte(asd_ha, (reg + sector_addr), 0x30); reg 1303 drivers/scsi/aic94xx/aic94xx_sds.c u32 reg; reg 1307 drivers/scsi/aic94xx/aic94xx_sds.c reg = asd_ha->hw_prof.flash.bar; reg 1325 drivers/scsi/aic94xx/aic94xx_sds.c asd_write_reg_byte(asd_ha, reg + 0xAAA, 0xAA); reg 1326 drivers/scsi/aic94xx/aic94xx_sds.c asd_write_reg_byte(asd_ha, reg + 0x555, 0x55); reg 1327 drivers/scsi/aic94xx/aic94xx_sds.c asd_write_reg_byte(asd_ha, reg + 0xAAA, 0x90); reg 1328 drivers/scsi/aic94xx/aic94xx_sds.c manuf_id = asd_read_reg_byte(asd_ha, reg); reg 1329 drivers/scsi/aic94xx/aic94xx_sds.c dev_id = asd_read_reg_byte(asd_ha, reg + inc); reg 1330 drivers/scsi/aic94xx/aic94xx_sds.c sec_prot = asd_read_reg_byte(asd_ha, reg + inc + inc); reg 1390 drivers/scsi/aic94xx/aic94xx_sds.c asd_write_reg_byte(asd_ha, (reg + 0x555), 0xAA); reg 1391 drivers/scsi/aic94xx/aic94xx_sds.c asd_write_reg_byte(asd_ha, (reg + 0x2AA), 0x55); reg 1392 drivers/scsi/aic94xx/aic94xx_sds.c asd_write_reg_byte(asd_ha, (reg + 0x555), 0x90); reg 1393 drivers/scsi/aic94xx/aic94xx_sds.c manuf_id = asd_read_reg_byte(asd_ha, reg); reg 1394 drivers/scsi/aic94xx/aic94xx_sds.c dev_id = asd_read_reg_byte(asd_ha, reg + inc); reg 1395 drivers/scsi/aic94xx/aic94xx_sds.c sec_prot = asd_read_reg_byte(asd_ha, reg + inc + inc); reg 274 drivers/scsi/aic94xx/aic94xx_seq.c u32 reg; reg 312 drivers/scsi/aic94xx/aic94xx_seq.c reg = !page ? RESETOVLYDMA : 0; reg 313 drivers/scsi/aic94xx/aic94xx_seq.c reg |= (STARTOVLYDMA | OVLYHALTERR); reg 314 drivers/scsi/aic94xx/aic94xx_seq.c reg |= (lseq_mask ? (((u32)lseq_mask) << 8) : OVLYCSEQ); reg 316 drivers/scsi/aic94xx/aic94xx_seq.c asd_write_reg_dword(asd_ha, OVLYDMACTL, reg); reg 326 drivers/scsi/aic94xx/aic94xx_seq.c reg = asd_read_reg_dword(asd_ha, COMSTAT); reg 327 drivers/scsi/aic94xx/aic94xx_seq.c if (!(reg & OVLYDMADONE) || (reg & OVLYERR) reg 345 drivers/scsi/aic94xx/aic94xx_seq.c u32 reg = 0; reg 356 drivers/scsi/aic94xx/aic94xx_seq.c reg |= (lseq_mask ? (((u32)lseq_mask) << 8) : OVLYCSEQ); reg 357 drivers/scsi/aic94xx/aic94xx_seq.c reg |= PIOCMODE; reg 360 drivers/scsi/aic94xx/aic94xx_seq.c asd_write_reg_dword(asd_ha, OVLYDMACTL, reg); reg 368 drivers/scsi/aic94xx/aic94xx_seq.c reg = (reg & ~PIOCMODE) | OVLYHALTERR; reg 369 drivers/scsi/aic94xx/aic94xx_seq.c asd_write_reg_dword(asd_ha, OVLYDMACTL, reg); reg 103 drivers/scsi/am53c974.c static void pci_esp_write8(struct esp *esp, u8 val, unsigned long reg) reg 105 drivers/scsi/am53c974.c iowrite8(val, esp->regs + (reg * 4UL)); reg 108 drivers/scsi/am53c974.c static u8 pci_esp_read8(struct esp *esp, unsigned long reg) reg 110 drivers/scsi/am53c974.c return ioread8(esp->regs + (reg * 4UL)); reg 113 drivers/scsi/am53c974.c static void pci_esp_write32(struct esp *esp, u32 val, unsigned long reg) reg 115 drivers/scsi/am53c974.c return iowrite32(val, esp->regs + (reg * 4UL)); reg 383 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 387 drivers/scsi/arcmsr/arcmsr_hba.c if (readl(®->outbound_intstatus) & reg 390 drivers/scsi/arcmsr/arcmsr_hba.c ®->outbound_intstatus); reg 401 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 405 drivers/scsi/arcmsr/arcmsr_hba.c if (readl(reg->iop2drv_doorbell) reg 408 drivers/scsi/arcmsr/arcmsr_hba.c reg->iop2drv_doorbell); reg 410 drivers/scsi/arcmsr/arcmsr_hba.c reg->drv2iop_doorbell); reg 439 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = pACB->pmuD; reg 443 drivers/scsi/arcmsr/arcmsr_hba.c if (readl(reg->outbound_doorbell) reg 446 drivers/scsi/arcmsr/arcmsr_hba.c reg->outbound_doorbell); reg 474 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 476 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0); reg 490 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 492 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell); reg 506 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = pACB->pmuC; reg 508 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0); reg 509 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); reg 525 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = pACB->pmuD; reg 527 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, reg->inbound_msgaddr0); reg 542 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = pACB->pmuE; reg 544 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0); reg 546 drivers/scsi/arcmsr/arcmsr_hba.c writel(pACB->out_doorbell, ®->iobound_doorbell); reg 585 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 588 drivers/scsi/arcmsr/arcmsr_hba.c reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_1203); reg 589 drivers/scsi/arcmsr/arcmsr_hba.c reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK_1203); reg 590 drivers/scsi/arcmsr/arcmsr_hba.c reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_1203); reg 591 drivers/scsi/arcmsr/arcmsr_hba.c reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK_1203); reg 593 drivers/scsi/arcmsr/arcmsr_hba.c reg->drv2iop_doorbell= MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL); reg 594 drivers/scsi/arcmsr/arcmsr_hba.c reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK); reg 595 drivers/scsi/arcmsr/arcmsr_hba.c reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL); reg 596 drivers/scsi/arcmsr/arcmsr_hba.c reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK); reg 598 drivers/scsi/arcmsr/arcmsr_hba.c reg->message_wbuffer = MEM_BASE1(ARCMSR_MESSAGE_WBUFFER); reg 599 drivers/scsi/arcmsr/arcmsr_hba.c reg->message_rbuffer = MEM_BASE1(ARCMSR_MESSAGE_RBUFFER); reg 600 drivers/scsi/arcmsr/arcmsr_hba.c reg->message_rwbuffer = MEM_BASE1(ARCMSR_MESSAGE_RWBUFFER); reg 605 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = acb->pmuD; reg 607 drivers/scsi/arcmsr/arcmsr_hba.c reg->chip_id = MEM_BASE0(ARCMSR_ARC1214_CHIP_ID); reg 608 drivers/scsi/arcmsr/arcmsr_hba.c reg->cpu_mem_config = MEM_BASE0(ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION); reg 609 drivers/scsi/arcmsr/arcmsr_hba.c reg->i2o_host_interrupt_mask = MEM_BASE0(ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK); reg 610 drivers/scsi/arcmsr/arcmsr_hba.c reg->sample_at_reset = MEM_BASE0(ARCMSR_ARC1214_SAMPLE_RESET); reg 611 drivers/scsi/arcmsr/arcmsr_hba.c reg->reset_request = MEM_BASE0(ARCMSR_ARC1214_RESET_REQUEST); reg 612 drivers/scsi/arcmsr/arcmsr_hba.c reg->host_int_status = MEM_BASE0(ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS); reg 613 drivers/scsi/arcmsr/arcmsr_hba.c reg->pcief0_int_enable = MEM_BASE0(ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE); reg 614 drivers/scsi/arcmsr/arcmsr_hba.c reg->inbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE0); reg 615 drivers/scsi/arcmsr/arcmsr_hba.c reg->inbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE1); reg 616 drivers/scsi/arcmsr/arcmsr_hba.c reg->outbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE0); reg 617 drivers/scsi/arcmsr/arcmsr_hba.c reg->outbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE1); reg 618 drivers/scsi/arcmsr/arcmsr_hba.c reg->inbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_INBOUND_DOORBELL); reg 619 drivers/scsi/arcmsr/arcmsr_hba.c reg->outbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL); reg 620 drivers/scsi/arcmsr/arcmsr_hba.c reg->outbound_doorbell_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE); reg 621 drivers/scsi/arcmsr/arcmsr_hba.c reg->inboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW); reg 622 drivers/scsi/arcmsr/arcmsr_hba.c reg->inboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH); reg 623 drivers/scsi/arcmsr/arcmsr_hba.c reg->inboundlist_write_pointer = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER); reg 624 drivers/scsi/arcmsr/arcmsr_hba.c reg->outboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW); reg 625 drivers/scsi/arcmsr/arcmsr_hba.c reg->outboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH); reg 626 drivers/scsi/arcmsr/arcmsr_hba.c reg->outboundlist_copy_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER); reg 627 drivers/scsi/arcmsr/arcmsr_hba.c reg->outboundlist_read_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER); reg 628 drivers/scsi/arcmsr/arcmsr_hba.c reg->outboundlist_interrupt_cause = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE); reg 629 drivers/scsi/arcmsr/arcmsr_hba.c reg->outboundlist_interrupt_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE); reg 630 drivers/scsi/arcmsr/arcmsr_hba.c reg->message_wbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_WBUFFER); reg 631 drivers/scsi/arcmsr/arcmsr_hba.c reg->message_rbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RBUFFER); reg 632 drivers/scsi/arcmsr/arcmsr_hba.c reg->msgcode_rwbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RWBUFFER); reg 797 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 799 drivers/scsi/arcmsr/arcmsr_hba.c signature = (uint32_t __iomem *)(®->message_rwbuffer[0]); reg 800 drivers/scsi/arcmsr/arcmsr_hba.c devicemap = (char __iomem *)(®->message_rwbuffer[21]); reg 804 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 806 drivers/scsi/arcmsr/arcmsr_hba.c signature = (uint32_t __iomem *)(®->message_rwbuffer[0]); reg 807 drivers/scsi/arcmsr/arcmsr_hba.c devicemap = (char __iomem *)(®->message_rwbuffer[21]); reg 811 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = acb->pmuC; reg 813 drivers/scsi/arcmsr/arcmsr_hba.c signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]); reg 814 drivers/scsi/arcmsr/arcmsr_hba.c devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]); reg 818 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = acb->pmuD; reg 820 drivers/scsi/arcmsr/arcmsr_hba.c signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]); reg 821 drivers/scsi/arcmsr/arcmsr_hba.c devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]); reg 825 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = acb->pmuE; reg 827 drivers/scsi/arcmsr/arcmsr_hba.c signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]); reg 828 drivers/scsi/arcmsr/arcmsr_hba.c devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]); reg 1115 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 1118 drivers/scsi/arcmsr/arcmsr_hba.c reg->post_qbuffer[i] = 0; reg 1119 drivers/scsi/arcmsr/arcmsr_hba.c reg->done_qbuffer[i] = 0; reg 1121 drivers/scsi/arcmsr/arcmsr_hba.c reg->postq_index = 0; reg 1122 drivers/scsi/arcmsr/arcmsr_hba.c reg->doneq_index = 0; reg 1153 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 1154 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0); reg 1166 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 1168 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell); reg 1179 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = pACB->pmuC; reg 1180 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0); reg 1181 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); reg 1193 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = pACB->pmuD; reg 1195 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, reg->inbound_msgaddr0); reg 1206 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = pACB->pmuE; reg 1208 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0); reg 1210 drivers/scsi/arcmsr/arcmsr_hba.c writel(pACB->out_doorbell, ®->iobound_doorbell); reg 1292 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 1293 drivers/scsi/arcmsr/arcmsr_hba.c orig_mask = readl(®->outbound_intmask); reg 1295 drivers/scsi/arcmsr/arcmsr_hba.c ®->outbound_intmask); reg 1299 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 1300 drivers/scsi/arcmsr/arcmsr_hba.c orig_mask = readl(reg->iop2drv_doorbell_mask); reg 1301 drivers/scsi/arcmsr/arcmsr_hba.c writel(0, reg->iop2drv_doorbell_mask); reg 1305 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = acb->pmuC; reg 1307 drivers/scsi/arcmsr/arcmsr_hba.c orig_mask = readl(®->host_int_mask); /* disable outbound message0 int */ reg 1308 drivers/scsi/arcmsr/arcmsr_hba.c writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, ®->host_int_mask); reg 1312 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = acb->pmuD; reg 1314 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_ARC1214_ALL_INT_DISABLE, reg->pcief0_int_enable); reg 1318 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = acb->pmuE; reg 1319 drivers/scsi/arcmsr/arcmsr_hba.c orig_mask = readl(®->host_int_mask); reg 1320 drivers/scsi/arcmsr/arcmsr_hba.c writel(orig_mask | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR, ®->host_int_mask); reg 1321 drivers/scsi/arcmsr/arcmsr_hba.c readl(®->host_int_mask); /* Dummy readl to force pci flush */ reg 1420 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 1422 drivers/scsi/arcmsr/arcmsr_hba.c outbound_intstatus = readl(®->outbound_intstatus) & reg 1425 drivers/scsi/arcmsr/arcmsr_hba.c writel(outbound_intstatus, ®->outbound_intstatus);/*clear interrupt*/ reg 1426 drivers/scsi/arcmsr/arcmsr_hba.c while(((flag_ccb = readl(®->outbound_queueport)) != 0xFFFFFFFF) reg 1440 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 1442 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */ reg 1444 drivers/scsi/arcmsr/arcmsr_hba.c flag_ccb = reg->done_qbuffer[i]; reg 1446 drivers/scsi/arcmsr/arcmsr_hba.c reg->done_qbuffer[i] = 0; reg 1455 drivers/scsi/arcmsr/arcmsr_hba.c reg->post_qbuffer[i] = 0; reg 1457 drivers/scsi/arcmsr/arcmsr_hba.c reg->doneq_index = 0; reg 1458 drivers/scsi/arcmsr/arcmsr_hba.c reg->postq_index = 0; reg 1462 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = acb->pmuC; reg 1463 drivers/scsi/arcmsr/arcmsr_hba.c while ((readl(®->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < acb->maxOutstanding)) { reg 1465 drivers/scsi/arcmsr/arcmsr_hba.c flag_ccb = readl(®->outbound_queueport_low); reg 1681 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 1685 drivers/scsi/arcmsr/arcmsr_hba.c writel(mask, ®->outbound_intmask); reg 1691 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 1696 drivers/scsi/arcmsr/arcmsr_hba.c writel(mask, reg->iop2drv_doorbell_mask); reg 1701 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = acb->pmuC; reg 1703 drivers/scsi/arcmsr/arcmsr_hba.c writel(intmask_org & mask, ®->host_int_mask); reg 1708 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = acb->pmuD; reg 1711 drivers/scsi/arcmsr/arcmsr_hba.c writel(intmask_org | mask, reg->pcief0_int_enable); reg 1715 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = acb->pmuE; reg 1718 drivers/scsi/arcmsr/arcmsr_hba.c writel(intmask_org & mask, ®->host_int_mask); reg 1787 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 1791 drivers/scsi/arcmsr/arcmsr_hba.c ®->inbound_queueport); reg 1793 drivers/scsi/arcmsr/arcmsr_hba.c writel(cdb_phyaddr, ®->inbound_queueport); reg 1798 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 1799 drivers/scsi/arcmsr/arcmsr_hba.c uint32_t ending_index, index = reg->postq_index; reg 1802 drivers/scsi/arcmsr/arcmsr_hba.c reg->post_qbuffer[ending_index] = 0; reg 1804 drivers/scsi/arcmsr/arcmsr_hba.c reg->post_qbuffer[index] = reg 1807 drivers/scsi/arcmsr/arcmsr_hba.c reg->post_qbuffer[index] = cdb_phyaddr; reg 1811 drivers/scsi/arcmsr/arcmsr_hba.c reg->postq_index = index; reg 1812 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell); reg 1863 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 1865 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0); reg 1875 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 1877 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell); reg 1888 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = pACB->pmuC; reg 1890 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0); reg 1891 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); reg 1902 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = pACB->pmuD; reg 1905 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, reg->inbound_msgaddr0); reg 1913 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = pACB->pmuE; reg 1916 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0); reg 1918 drivers/scsi/arcmsr/arcmsr_hba.c writel(pACB->out_doorbell, ®->iobound_doorbell); reg 1959 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 1960 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, ®->inbound_doorbell); reg 1965 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 1966 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell); reg 1970 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = acb->pmuC; reg 1972 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, ®->inbound_doorbell); reg 1976 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = acb->pmuD; reg 1978 drivers/scsi/arcmsr/arcmsr_hba.c reg->inbound_doorbell); reg 1982 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = acb->pmuE; reg 1984 drivers/scsi/arcmsr/arcmsr_hba.c writel(acb->out_doorbell, ®->iobound_doorbell); reg 1994 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 1999 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, ®->inbound_doorbell); reg 2004 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 2009 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell); reg 2013 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = acb->pmuC; reg 2018 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, ®->inbound_doorbell); reg 2022 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = acb->pmuD; reg 2024 drivers/scsi/arcmsr/arcmsr_hba.c reg->inbound_doorbell); reg 2028 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = acb->pmuE; reg 2030 drivers/scsi/arcmsr/arcmsr_hba.c writel(acb->out_doorbell, ®->iobound_doorbell); reg 2042 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 2043 drivers/scsi/arcmsr/arcmsr_hba.c qbuffer = (struct QBUFFER __iomem *)®->message_rbuffer; reg 2048 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 2049 drivers/scsi/arcmsr/arcmsr_hba.c qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer; reg 2058 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = acb->pmuD; reg 2059 drivers/scsi/arcmsr/arcmsr_hba.c qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer; reg 2063 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = acb->pmuE; reg 2064 drivers/scsi/arcmsr/arcmsr_hba.c qbuffer = (struct QBUFFER __iomem *)®->message_rbuffer; reg 2077 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 2078 drivers/scsi/arcmsr/arcmsr_hba.c pqbuffer = (struct QBUFFER __iomem *) ®->message_wbuffer; reg 2083 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 2084 drivers/scsi/arcmsr/arcmsr_hba.c pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer; reg 2088 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = acb->pmuC; reg 2089 drivers/scsi/arcmsr/arcmsr_hba.c pqbuffer = (struct QBUFFER __iomem *)®->message_wbuffer; reg 2093 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = acb->pmuD; reg 2094 drivers/scsi/arcmsr/arcmsr_hba.c pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer; reg 2098 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = acb->pmuE; reg 2099 drivers/scsi/arcmsr/arcmsr_hba.c pqbuffer = (struct QBUFFER __iomem *)®->message_wbuffer; reg 2279 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 2280 drivers/scsi/arcmsr/arcmsr_hba.c outbound_doorbell = readl(®->outbound_doorbell); reg 2282 drivers/scsi/arcmsr/arcmsr_hba.c writel(outbound_doorbell, ®->outbound_doorbell); reg 2287 drivers/scsi/arcmsr/arcmsr_hba.c outbound_doorbell = readl(®->outbound_doorbell); reg 2294 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = pACB->pmuC; reg 2302 drivers/scsi/arcmsr/arcmsr_hba.c outbound_doorbell = readl(®->outbound_doorbell); reg 2304 drivers/scsi/arcmsr/arcmsr_hba.c writel(outbound_doorbell, ®->outbound_doorbell_clear); reg 2305 drivers/scsi/arcmsr/arcmsr_hba.c readl(®->outbound_doorbell_clear); reg 2312 drivers/scsi/arcmsr/arcmsr_hba.c outbound_doorbell = readl(®->outbound_doorbell); reg 2341 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = pACB->pmuE; reg 2343 drivers/scsi/arcmsr/arcmsr_hba.c in_doorbell = readl(®->iobound_doorbell); reg 2346 drivers/scsi/arcmsr/arcmsr_hba.c writel(0, ®->host_int_status); /* clear interrupt */ reg 2357 drivers/scsi/arcmsr/arcmsr_hba.c in_doorbell = readl(®->iobound_doorbell); reg 2368 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 2374 drivers/scsi/arcmsr/arcmsr_hba.c while ((flag_ccb = readl(®->outbound_queueport)) != 0xFFFFFFFF) { reg 2388 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 2394 drivers/scsi/arcmsr/arcmsr_hba.c index = reg->doneq_index; reg 2395 drivers/scsi/arcmsr/arcmsr_hba.c while ((flag_ccb = reg->done_qbuffer[index]) != 0) { reg 2403 drivers/scsi/arcmsr/arcmsr_hba.c reg->done_qbuffer[index] = 0; reg 2406 drivers/scsi/arcmsr/arcmsr_hba.c reg->doneq_index = index; reg 2528 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 2530 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, ®->outbound_intstatus); reg 2536 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 2539 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); reg 2554 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = acb->pmuC; reg 2556 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, ®->outbound_doorbell_clear); reg 2563 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = acb->pmuD; reg 2565 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, reg->outbound_doorbell); reg 2566 drivers/scsi/arcmsr/arcmsr_hba.c readl(reg->outbound_doorbell); reg 2573 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = acb->pmuE; reg 2575 drivers/scsi/arcmsr/arcmsr_hba.c writel(0, ®->host_int_status); reg 2583 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 2584 drivers/scsi/arcmsr/arcmsr_hba.c outbound_intstatus = readl(®->outbound_intstatus) & reg 2589 drivers/scsi/arcmsr/arcmsr_hba.c writel(outbound_intstatus, ®->outbound_intstatus); reg 2596 drivers/scsi/arcmsr/arcmsr_hba.c outbound_intstatus = readl(®->outbound_intstatus) & reg 2607 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 2608 drivers/scsi/arcmsr/arcmsr_hba.c outbound_doorbell = readl(reg->iop2drv_doorbell) & reg 2613 drivers/scsi/arcmsr/arcmsr_hba.c writel(~outbound_doorbell, reg->iop2drv_doorbell); reg 2614 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell); reg 2623 drivers/scsi/arcmsr/arcmsr_hba.c outbound_doorbell = readl(reg->iop2drv_doorbell) & reg 3168 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 3171 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); reg 3177 drivers/scsi/arcmsr/arcmsr_hba.c arcmsr_get_adapter_config(acb, reg->message_rwbuffer); reg 3182 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 3185 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell); reg 3190 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell); reg 3196 drivers/scsi/arcmsr/arcmsr_hba.c arcmsr_get_adapter_config(acb, reg->message_rwbuffer); reg 3203 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = pACB->pmuC; reg 3206 drivers/scsi/arcmsr/arcmsr_hba.c intmask_org = readl(®->host_int_mask); /* disable outbound message0 int */ reg 3207 drivers/scsi/arcmsr/arcmsr_hba.c writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, ®->host_int_mask); reg 3211 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); reg 3212 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); reg 3219 drivers/scsi/arcmsr/arcmsr_hba.c arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer); reg 3225 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = acb->pmuD; reg 3234 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0); reg 3241 drivers/scsi/arcmsr/arcmsr_hba.c arcmsr_get_adapter_config(acb, reg->msgcode_rwbuffer); reg 3247 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = pACB->pmuE; reg 3251 drivers/scsi/arcmsr/arcmsr_hba.c intmask_org = readl(®->host_int_mask); /* disable outbound message0 int */ reg 3252 drivers/scsi/arcmsr/arcmsr_hba.c writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, ®->host_int_mask); reg 3257 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); reg 3260 drivers/scsi/arcmsr/arcmsr_hba.c writel(pACB->out_doorbell, ®->iobound_doorbell); reg 3267 drivers/scsi/arcmsr/arcmsr_hba.c arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer); reg 3308 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 3318 drivers/scsi/arcmsr/arcmsr_hba.c outbound_intstatus = readl(®->outbound_intstatus) & acb->outbound_int_enable; reg 3319 drivers/scsi/arcmsr/arcmsr_hba.c writel(outbound_intstatus, ®->outbound_intstatus);/*clear interrupt*/ reg 3321 drivers/scsi/arcmsr/arcmsr_hba.c if ((flag_ccb = readl(®->outbound_queueport)) == 0xFFFFFFFF) { reg 3369 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 3380 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); reg 3382 drivers/scsi/arcmsr/arcmsr_hba.c index = reg->doneq_index; reg 3383 drivers/scsi/arcmsr/arcmsr_hba.c flag_ccb = reg->done_qbuffer[index]; reg 3397 drivers/scsi/arcmsr/arcmsr_hba.c reg->done_qbuffer[index] = 0; reg 3401 drivers/scsi/arcmsr/arcmsr_hba.c reg->doneq_index = index; reg 3438 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = acb->pmuC; reg 3450 drivers/scsi/arcmsr/arcmsr_hba.c if ((readl(®->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) { reg 3463 drivers/scsi/arcmsr/arcmsr_hba.c flag_ccb = readl(®->outbound_queueport_low); reg 3584 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = acb->pmuE; reg 3591 drivers/scsi/arcmsr/arcmsr_hba.c if ((readl(®->reply_post_producer_index) & 0xFFFF) == reg 3640 drivers/scsi/arcmsr/arcmsr_hba.c writel(doneq_index, ®->reply_post_consumer_index); reg 3706 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = pacb->pmuA; reg 3707 drivers/scsi/arcmsr/arcmsr_hba.c writel(datetime.b.msg_time[0], ®->message_rwbuffer[0]); reg 3708 drivers/scsi/arcmsr/arcmsr_hba.c writel(datetime.b.msg_time[1], ®->message_rwbuffer[1]); reg 3709 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0); reg 3714 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = pacb->pmuB; reg 3715 drivers/scsi/arcmsr/arcmsr_hba.c rwbuffer = reg->message_rwbuffer; reg 3718 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_MESSAGE_SYNC_TIMER, reg->drv2iop_doorbell); reg 3722 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = pacb->pmuC; reg 3723 drivers/scsi/arcmsr/arcmsr_hba.c writel(datetime.b.msg_time[0], ®->msgcode_rwbuffer[0]); reg 3724 drivers/scsi/arcmsr/arcmsr_hba.c writel(datetime.b.msg_time[1], ®->msgcode_rwbuffer[1]); reg 3725 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0); reg 3726 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); reg 3731 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = pacb->pmuD; reg 3732 drivers/scsi/arcmsr/arcmsr_hba.c rwbuffer = reg->msgcode_rwbuffer; reg 3735 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, reg->inbound_msgaddr0); reg 3739 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = pacb->pmuE; reg 3740 drivers/scsi/arcmsr/arcmsr_hba.c writel(datetime.b.msg_time[0], ®->msgcode_rwbuffer[0]); reg 3741 drivers/scsi/arcmsr/arcmsr_hba.c writel(datetime.b.msg_time[1], ®->msgcode_rwbuffer[1]); reg 3742 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0); reg 3744 drivers/scsi/arcmsr/arcmsr_hba.c writel(pacb->out_doorbell, ®->iobound_doorbell); reg 3792 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 3794 drivers/scsi/arcmsr/arcmsr_hba.c ®->message_rwbuffer[0]); reg 3795 drivers/scsi/arcmsr/arcmsr_hba.c writel(cdb_phyaddr_hi32, ®->message_rwbuffer[1]); reg 3797 drivers/scsi/arcmsr/arcmsr_hba.c ®->inbound_msgaddr0); reg 3811 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 3812 drivers/scsi/arcmsr/arcmsr_hba.c reg->postq_index = 0; reg 3813 drivers/scsi/arcmsr/arcmsr_hba.c reg->doneq_index = 0; reg 3814 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell); reg 3820 drivers/scsi/arcmsr/arcmsr_hba.c rwbuffer = reg->message_rwbuffer; reg 3832 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell); reg 3838 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell); reg 3847 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = acb->pmuC; reg 3851 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_SIGNATURE_SET_CONFIG, ®->msgcode_rwbuffer[0]); reg 3852 drivers/scsi/arcmsr/arcmsr_hba.c writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[1]); reg 3853 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0); reg 3854 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); reg 3864 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = acb->pmuD; reg 3865 drivers/scsi/arcmsr/arcmsr_hba.c reg->postq_index = 0; reg 3866 drivers/scsi/arcmsr/arcmsr_hba.c reg->doneq_index = 0; reg 3867 drivers/scsi/arcmsr/arcmsr_hba.c rwbuffer = reg->msgcode_rwbuffer; reg 3874 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, reg->inbound_msgaddr0); reg 3883 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = acb->pmuE; reg 3884 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_SIGNATURE_SET_CONFIG, ®->msgcode_rwbuffer[0]); reg 3885 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_SIGNATURE_1884, ®->msgcode_rwbuffer[1]); reg 3886 drivers/scsi/arcmsr/arcmsr_hba.c writel(cdb_phyaddr, ®->msgcode_rwbuffer[2]); reg 3887 drivers/scsi/arcmsr/arcmsr_hba.c writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[3]); reg 3888 drivers/scsi/arcmsr/arcmsr_hba.c writel(acb->ccbsize, ®->msgcode_rwbuffer[4]); reg 3892 drivers/scsi/arcmsr/arcmsr_hba.c writel(cdb_phyaddr, ®->msgcode_rwbuffer[5]); reg 3893 drivers/scsi/arcmsr/arcmsr_hba.c writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[6]); reg 3894 drivers/scsi/arcmsr/arcmsr_hba.c writel(acb->ioqueue_size, ®->msgcode_rwbuffer[7]); reg 3895 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0); reg 3897 drivers/scsi/arcmsr/arcmsr_hba.c writel(acb->out_doorbell, ®->iobound_doorbell); reg 3915 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 3919 drivers/scsi/arcmsr/arcmsr_hba.c firmware_state = readl(®->outbound_msgaddr1); reg 3925 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 3929 drivers/scsi/arcmsr/arcmsr_hba.c firmware_state = readl(reg->iop2drv_doorbell); reg 3931 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell); reg 3935 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = acb->pmuC; reg 3939 drivers/scsi/arcmsr/arcmsr_hba.c firmware_state = readl(®->outbound_msgaddr1); reg 3944 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = acb->pmuD; reg 3948 drivers/scsi/arcmsr/arcmsr_hba.c firmware_state = readl(reg->outbound_msgaddr1); reg 3954 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = acb->pmuE; reg 3958 drivers/scsi/arcmsr/arcmsr_hba.c firmware_state = readl(®->outbound_msgaddr1); reg 3988 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 3989 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); reg 3993 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 3994 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell); reg 3998 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = acb->pmuC; reg 3999 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); reg 4000 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); reg 4004 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = acb->pmuD; reg 4005 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0); reg 4009 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = acb->pmuE; reg 4010 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); reg 4012 drivers/scsi/arcmsr/arcmsr_hba.c writel(acb->out_doorbell, ®->iobound_doorbell); reg 4025 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 4027 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_MESG0_START_BGRB, ®->inbound_msgaddr0); reg 4036 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 4038 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell); reg 4109 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 4112 drivers/scsi/arcmsr/arcmsr_hba.c outbound_doorbell = readl(®->outbound_doorbell); reg 4114 drivers/scsi/arcmsr/arcmsr_hba.c writel(outbound_doorbell, ®->outbound_doorbell); reg 4115 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, ®->inbound_doorbell); reg 4120 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 4122 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); reg 4123 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell); reg 4127 drivers/scsi/arcmsr/arcmsr_hba.c outbound_doorbell = readl(reg->iop2drv_doorbell); reg 4129 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); reg 4130 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell); reg 4137 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = acb->pmuC; reg 4140 drivers/scsi/arcmsr/arcmsr_hba.c outbound_doorbell = readl(®->outbound_doorbell); reg 4141 drivers/scsi/arcmsr/arcmsr_hba.c writel(outbound_doorbell, ®->outbound_doorbell_clear); reg 4142 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, ®->inbound_doorbell); reg 4145 drivers/scsi/arcmsr/arcmsr_hba.c outbound_doorbell = readl(®->outbound_doorbell); reg 4149 drivers/scsi/arcmsr/arcmsr_hba.c ®->outbound_doorbell_clear); reg 4151 drivers/scsi/arcmsr/arcmsr_hba.c ®->inbound_doorbell); reg 4158 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = acb->pmuD; reg 4161 drivers/scsi/arcmsr/arcmsr_hba.c outbound_doorbell = readl(reg->outbound_doorbell); reg 4162 drivers/scsi/arcmsr/arcmsr_hba.c writel(outbound_doorbell, reg->outbound_doorbell); reg 4164 drivers/scsi/arcmsr/arcmsr_hba.c reg->inbound_doorbell); reg 4167 drivers/scsi/arcmsr/arcmsr_hba.c outbound_doorbell = readl(reg->outbound_doorbell); reg 4171 drivers/scsi/arcmsr/arcmsr_hba.c reg->outbound_doorbell); reg 4173 drivers/scsi/arcmsr/arcmsr_hba.c reg->inbound_doorbell); reg 4180 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = acb->pmuE; reg 4183 drivers/scsi/arcmsr/arcmsr_hba.c acb->in_doorbell = readl(®->iobound_doorbell); reg 4184 drivers/scsi/arcmsr/arcmsr_hba.c writel(0, ®->host_int_status); /*clear interrupt*/ reg 4186 drivers/scsi/arcmsr/arcmsr_hba.c writel(acb->out_doorbell, ®->iobound_doorbell); reg 4190 drivers/scsi/arcmsr/arcmsr_hba.c acb->in_doorbell = readl(®->iobound_doorbell); reg 4192 drivers/scsi/arcmsr/arcmsr_hba.c writel(0, ®->host_int_status); /*clear interrupt*/ reg 4194 drivers/scsi/arcmsr/arcmsr_hba.c writel(acb->out_doorbell, ®->iobound_doorbell); reg 4210 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 4211 drivers/scsi/arcmsr/arcmsr_hba.c writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell); reg 4284 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_A __iomem *reg = acb->pmuA; reg 4285 drivers/scsi/arcmsr/arcmsr_hba.c rtn = ((readl(®->outbound_msgaddr1) & reg 4290 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_B *reg = acb->pmuB; reg 4291 drivers/scsi/arcmsr/arcmsr_hba.c rtn = ((readl(reg->iop2drv_doorbell) & reg 4296 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_C __iomem *reg = acb->pmuC; reg 4297 drivers/scsi/arcmsr/arcmsr_hba.c rtn = (readl(®->host_diagnostic) & 0x04) ? true : false; reg 4301 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_D *reg = acb->pmuD; reg 4302 drivers/scsi/arcmsr/arcmsr_hba.c rtn = ((readl(reg->sample_at_reset) & 0x80) == 0) ? reg 4307 drivers/scsi/arcmsr/arcmsr_hba.c struct MessageUnit_E __iomem *reg = acb->pmuE; reg 4308 drivers/scsi/arcmsr/arcmsr_hba.c rtn = (readl(®->host_diagnostic_3xxx) & reg 195 drivers/scsi/arm/acornscsi.c static inline void sbic_arm_write(AS_Host *host, unsigned int reg, unsigned int value) reg 197 drivers/scsi/arm/acornscsi.c writeb(reg, host->base + SBIC_REGIDX); reg 201 drivers/scsi/arm/acornscsi.c static inline int sbic_arm_read(AS_Host *host, unsigned int reg) reg 203 drivers/scsi/arm/acornscsi.c if(reg == SBIC_ASR) reg 205 drivers/scsi/arm/acornscsi.c writeb(reg, host->base + SBIC_REGIDX); reg 213 drivers/scsi/arm/acornscsi.c #define dmac_read(host,reg) \ reg 214 drivers/scsi/arm/acornscsi.c readb((host)->base + DMAC_OFFSET + ((reg) << 2)) reg 216 drivers/scsi/arm/acornscsi.c #define dmac_write(host,reg,value) \ reg 217 drivers/scsi/arm/acornscsi.c ({ writeb((value), (host)->base + DMAC_OFFSET + ((reg) << 2)); }) reg 18 drivers/scsi/arm/cumana_1.c #define NCR5380_read(reg) cumanascsi_read(hostdata, reg) reg 19 drivers/scsi/arm/cumana_1.c #define NCR5380_write(reg, value) cumanascsi_write(hostdata, reg, value) reg 184 drivers/scsi/arm/cumana_1.c unsigned int reg) reg 191 drivers/scsi/arm/cumana_1.c val = readb(base + 0x2100 + (reg << 2)); reg 200 drivers/scsi/arm/cumana_1.c unsigned int reg, u8 value) reg 206 drivers/scsi/arm/cumana_1.c writeb(value, base + 0x2100 + (reg << 2)); reg 141 drivers/scsi/arm/fas216.c static inline unsigned char fas216_readb(FAS216_Info *info, unsigned int reg) reg 143 drivers/scsi/arm/fas216.c unsigned int off = reg << info->scsi.io_shift; reg 147 drivers/scsi/arm/fas216.c static inline void fas216_writeb(FAS216_Info *info, unsigned int reg, unsigned int val) reg 149 drivers/scsi/arm/fas216.c unsigned int off = reg << info->scsi.io_shift; reg 20 drivers/scsi/arm/oak.c #define NCR5380_read(reg) readb(hostdata->io + ((reg) << 2)) reg 21 drivers/scsi/arm/oak.c #define NCR5380_write(reg, value) writeb(value, hostdata->io + ((reg) << 2)) reg 63 drivers/scsi/atari_scsi.c #define NCR5380_read(reg) atari_scsi_reg_read(reg) reg 64 drivers/scsi/atari_scsi.c #define NCR5380_write(reg, value) atari_scsi_reg_write(reg, value) reg 637 drivers/scsi/atari_scsi.c static u8 atari_scsi_tt_reg_read(unsigned int reg) reg 639 drivers/scsi/atari_scsi.c return tt_scsi_regp[reg * 2]; reg 642 drivers/scsi/atari_scsi.c static void atari_scsi_tt_reg_write(unsigned int reg, u8 value) reg 644 drivers/scsi/atari_scsi.c tt_scsi_regp[reg * 2] = value; reg 647 drivers/scsi/atari_scsi.c static u8 atari_scsi_falcon_reg_read(unsigned int reg) reg 652 drivers/scsi/atari_scsi.c reg += 0x88; reg 654 drivers/scsi/atari_scsi.c dma_wd.dma_mode_status = (u_short)reg; reg 660 drivers/scsi/atari_scsi.c static void atari_scsi_falcon_reg_write(unsigned int reg, u8 value) reg 664 drivers/scsi/atari_scsi.c reg += 0x88; reg 666 drivers/scsi/atari_scsi.c dma_wd.dma_mode_status = (u_short)reg; reg 47 drivers/scsi/atp870u.c static inline void atp_writeb_base(struct atp_unit *atp, u8 reg, u8 val) reg 49 drivers/scsi/atp870u.c outb(val, atp->baseport + reg); reg 52 drivers/scsi/atp870u.c static inline void atp_writew_base(struct atp_unit *atp, u8 reg, u16 val) reg 54 drivers/scsi/atp870u.c outw(val, atp->baseport + reg); reg 57 drivers/scsi/atp870u.c static inline void atp_writeb_io(struct atp_unit *atp, u8 channel, u8 reg, u8 val) reg 59 drivers/scsi/atp870u.c outb(val, atp->ioport[channel] + reg); reg 62 drivers/scsi/atp870u.c static inline void atp_writew_io(struct atp_unit *atp, u8 channel, u8 reg, u16 val) reg 64 drivers/scsi/atp870u.c outw(val, atp->ioport[channel] + reg); reg 67 drivers/scsi/atp870u.c static inline void atp_writeb_pci(struct atp_unit *atp, u8 channel, u8 reg, u8 val) reg 69 drivers/scsi/atp870u.c outb(val, atp->pciport[channel] + reg); reg 72 drivers/scsi/atp870u.c static inline void atp_writel_pci(struct atp_unit *atp, u8 channel, u8 reg, u32 val) reg 74 drivers/scsi/atp870u.c outl(val, atp->pciport[channel] + reg); reg 77 drivers/scsi/atp870u.c static inline u8 atp_readb_base(struct atp_unit *atp, u8 reg) reg 79 drivers/scsi/atp870u.c return inb(atp->baseport + reg); reg 82 drivers/scsi/atp870u.c static inline u16 atp_readw_base(struct atp_unit *atp, u8 reg) reg 84 drivers/scsi/atp870u.c return inw(atp->baseport + reg); reg 87 drivers/scsi/atp870u.c static inline u32 atp_readl_base(struct atp_unit *atp, u8 reg) reg 89 drivers/scsi/atp870u.c return inl(atp->baseport + reg); reg 92 drivers/scsi/atp870u.c static inline u8 atp_readb_io(struct atp_unit *atp, u8 channel, u8 reg) reg 94 drivers/scsi/atp870u.c return inb(atp->ioport[channel] + reg); reg 97 drivers/scsi/atp870u.c static inline u16 atp_readw_io(struct atp_unit *atp, u8 channel, u8 reg) reg 99 drivers/scsi/atp870u.c return inw(atp->ioport[channel] + reg); reg 102 drivers/scsi/atp870u.c static inline u8 atp_readb_pci(struct atp_unit *atp, u8 channel, u8 reg) reg 104 drivers/scsi/atp870u.c return inb(atp->pciport[channel] + reg); reg 4101 drivers/scsi/be2iscsi/be_main.c u32 reg, i; reg 4109 drivers/scsi/be2iscsi/be_main.c reg = ioread32(addr); reg 4111 drivers/scsi/be2iscsi/be_main.c enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; reg 4113 drivers/scsi/be2iscsi/be_main.c reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; reg 4115 drivers/scsi/be2iscsi/be_main.c "BM_%d : reg =x%08x addr=%p\n", reg, addr); reg 4116 drivers/scsi/be2iscsi/be_main.c iowrite32(reg, addr); reg 4140 drivers/scsi/be2iscsi/be_main.c u32 reg = ioread32(addr); reg 4142 drivers/scsi/be2iscsi/be_main.c u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; reg 4144 drivers/scsi/be2iscsi/be_main.c reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; reg 4145 drivers/scsi/be2iscsi/be_main.c iowrite32(reg, addr); reg 1207 drivers/scsi/bfa/bfad.c u16 reg; reg 1239 drivers/scsi/bfa/bfad.c pci_read_config_word(pdev, PCI_COMMAND, ®); reg 1241 drivers/scsi/bfa/bfad.c if (!(reg & PCI_COMMAND_INTX_DISABLE)) reg 1243 drivers/scsi/bfa/bfad.c reg | PCI_COMMAND_INTX_DISABLE); reg 133 drivers/scsi/csiostor/csio_hw.c csio_hw_wait_op_done_val(struct csio_hw *hw, int reg, uint32_t mask, reg 138 drivers/scsi/csiostor/csio_hw.c val = csio_rd_reg32(hw, reg); reg 172 drivers/scsi/csiostor/csio_hw.c csio_set_reg_field(struct csio_hw *hw, uint32_t reg, uint32_t mask, reg 175 drivers/scsi/csiostor/csio_hw.c uint32_t val = csio_rd_reg32(hw, reg) & ~mask; reg 177 drivers/scsi/csiostor/csio_hw.c csio_wr_reg32(hw, val | value, reg); reg 179 drivers/scsi/csiostor/csio_hw.c csio_rd_reg32(hw, reg); reg 884 drivers/scsi/csiostor/csio_hw.c uint32_t reg; reg 888 drivers/scsi/csiostor/csio_hw.c while (((reg = csio_rd_reg32(hw, PL_WHOAMI_A)) == 0xFFFFFFFF) && reg 893 drivers/scsi/csiostor/csio_hw.c src_pf = SOURCEPF_G(reg); reg 895 drivers/scsi/csiostor/csio_hw.c src_pf = T6_SOURCEPF_G(reg); reg 899 drivers/scsi/csiostor/csio_hw.c csio_err(hw, "PL_WHOAMI returned 0x%x, cnt:%d\n", reg, cnt); reg 3113 drivers/scsi/csiostor/csio_hw.c csio_handle_intr_status(struct csio_hw *hw, unsigned int reg, reg 3118 drivers/scsi/csiostor/csio_hw.c unsigned int status = csio_rd_reg32(hw, reg); reg 3134 drivers/scsi/csiostor/csio_hw.c csio_wr_reg32(hw, status, reg); reg 205 drivers/scsi/csiostor/csio_hw_t5.c #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) reg 264 drivers/scsi/csiostor/csio_mb.c csio_mb_ldst(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo, int reg) reg 282 drivers/scsi/csiostor/csio_mb.c ldst_cmd->u.pcie.r = (uint8_t)reg; reg 175 drivers/scsi/csiostor/csio_mb.h int reg); reg 58 drivers/scsi/csiostor/csio_wr.c csio_get_flbuf_size(struct csio_hw *hw, struct csio_sge *sge, uint32_t reg) reg 60 drivers/scsi/csiostor/csio_wr.c sge->sge_fl_buf_size[reg] = csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE0_A + reg 61 drivers/scsi/csiostor/csio_wr.c reg * sizeof(uint32_t)); reg 859 drivers/scsi/cxlflash/main.c u64 reg, status; reg 875 drivers/scsi/cxlflash/main.c reg = readq_be(&fc_port_regs[FC_CONFIG2 / 8]); reg 876 drivers/scsi/cxlflash/main.c reg |= SISL_FC_SHUTDOWN_NORMAL; reg 877 drivers/scsi/cxlflash/main.c writeq_be(reg, &fc_port_regs[FC_CONFIG2 / 8]); reg 1271 drivers/scsi/cxlflash/main.c u64 reg; reg 1283 drivers/scsi/cxlflash/main.c reg = ((u64) (((hwq->ctx_hndl << 8) | SISL_MSI_ASYNC_ERROR)) << 40); reg 1286 drivers/scsi/cxlflash/main.c reg |= 1; /* Bit 63 indicates local lun */ reg 1287 drivers/scsi/cxlflash/main.c writeq_be(reg, &afu->afu_map->global.regs.afu_ctrl); reg 1299 drivers/scsi/cxlflash/main.c reg = readq_be(&fc_port_regs[FC_CONFIG2 / 8]); reg 1300 drivers/scsi/cxlflash/main.c reg &= SISL_FC_INTERNAL_MASK; reg 1302 drivers/scsi/cxlflash/main.c reg |= ((u64)(afu->internal_lun - 1) << SISL_FC_INTERNAL_SHIFT); reg 1303 drivers/scsi/cxlflash/main.c writeq_be(reg, &fc_port_regs[FC_CONFIG2 / 8]); reg 1322 drivers/scsi/cxlflash/main.c reg = readq_be(&hwq->host_map->ctx_ctrl); reg 1323 drivers/scsi/cxlflash/main.c WARN_ON((reg & SISL_CTX_CTRL_LISN_MASK) != 0); reg 1324 drivers/scsi/cxlflash/main.c reg |= SISL_MSI_SYNC_ERROR; reg 1325 drivers/scsi/cxlflash/main.c writeq_be(reg, &hwq->host_map->ctx_ctrl); reg 1342 drivers/scsi/cxlflash/main.c u64 reg; reg 1345 drivers/scsi/cxlflash/main.c reg = readq_be(&hwq->host_map->intr_status); reg 1346 drivers/scsi/cxlflash/main.c reg_unmasked = (reg & SISL_ISTATUS_UNMASK); reg 1350 drivers/scsi/cxlflash/main.c __func__, reg); reg 1355 drivers/scsi/cxlflash/main.c __func__, reg); reg 1553 drivers/scsi/cxlflash/main.c u64 reg; reg 1557 drivers/scsi/cxlflash/main.c reg = readq_be(&global->regs.aintr_status); reg 1558 drivers/scsi/cxlflash/main.c reg_unmasked = (reg & SISL_ASTATUS_UNMASK); reg 1562 drivers/scsi/cxlflash/main.c __func__, reg); reg 1602 drivers/scsi/cxlflash/main.c reg = readq_be(&fc_port_regs[FC_ERROR / 8]); reg 1610 drivers/scsi/cxlflash/main.c __func__, port, reg); reg 1612 drivers/scsi/cxlflash/main.c writeq_be(reg, &fc_port_regs[FC_ERROR / 8]); reg 1782 drivers/scsi/cxlflash/main.c u64 reg; reg 1806 drivers/scsi/cxlflash/main.c reg = readq_be(&afu->afu_map->global.regs.afu_config); reg 1807 drivers/scsi/cxlflash/main.c reg |= SISL_AFUCONF_AR_ALL|SISL_AFUCONF_ENDIAN; reg 1812 drivers/scsi/cxlflash/main.c writeq_be(reg, &afu->afu_map->global.regs.afu_config); reg 1850 drivers/scsi/cxlflash/main.c reg = cfg->ops->get_irq_objhndl(ctx, j); reg 1851 drivers/scsi/cxlflash/main.c writeq_be(reg, &hwq->ctrl_map->lisn_ea[j]); reg 1854 drivers/scsi/cxlflash/main.c reg = hwq->ctx_hndl; reg 1855 drivers/scsi/cxlflash/main.c writeq_be(SISL_LISN_PASID(reg, reg), reg 1857 drivers/scsi/cxlflash/main.c writeq_be(SISL_LISN_PASID(0UL, reg), reg 1882 drivers/scsi/cxlflash/main.c reg = readq_be(&hwq->host_map->ctx_ctrl); reg 1883 drivers/scsi/cxlflash/main.c if (reg & SISL_CTX_CTRL_UNMAP_SECTOR) reg 2121 drivers/scsi/cxlflash/main.c u64 reg; reg 2151 drivers/scsi/cxlflash/main.c reg = readq(&afu->afu_map->global.regs.afu_version); reg 2152 drivers/scsi/cxlflash/main.c memcpy(afu->version, ®, sizeof(reg)); reg 3317 drivers/scsi/cxlflash/main.c u64 reg; reg 3346 drivers/scsi/cxlflash/main.c reg = readq_be(&fc_port_regs[FC_MAX_NUM_LUNS / 8]); reg 3347 drivers/scsi/cxlflash/main.c lunprov->max_num_luns = reg; reg 3348 drivers/scsi/cxlflash/main.c reg = readq_be(&fc_port_regs[FC_CUR_NUM_LUNS / 8]); reg 3349 drivers/scsi/cxlflash/main.c lunprov->cur_num_luns = reg; reg 3350 drivers/scsi/cxlflash/main.c reg = readq_be(&fc_port_regs[FC_MAX_CAP_PORT / 8]); reg 3351 drivers/scsi/cxlflash/main.c lunprov->max_cap_port = reg; reg 3352 drivers/scsi/cxlflash/main.c reg = readq_be(&fc_port_regs[FC_CUR_CAP_PORT / 8]); reg 3353 drivers/scsi/cxlflash/main.c lunprov->cur_cap_port = reg; reg 1664 drivers/scsi/cxlflash/superpipe.c long reg; reg 1737 drivers/scsi/cxlflash/superpipe.c reg = readq_be(&hwq->ctrl_map->mbox_r); reg 1738 drivers/scsi/cxlflash/superpipe.c if (reg == -1) { reg 25 drivers/scsi/dmx3191d.c #define NCR5380_read(reg) inb(hostdata->base + (reg)) reg 26 drivers/scsi/dmx3191d.c #define NCR5380_write(reg, value) outb(value, hostdata->base + (reg)) reg 141 drivers/scsi/esas2r/esas2r.h #define esas2r_read_register_dword(a, reg) \ reg 142 drivers/scsi/esas2r/esas2r.h readl((void __iomem *)a->regs + (reg) + MW_REG_OFFSET_HWREG) reg 144 drivers/scsi/esas2r/esas2r.h #define esas2r_write_register_dword(a, reg, data) \ reg 145 drivers/scsi/esas2r/esas2r.h writel(data, (void __iomem *)(a->regs + (reg) + MW_REG_OFFSET_HWREG)) reg 153 drivers/scsi/esas2r/esas2r.h #define esas2r_read_data_byte(a, reg) \ reg 154 drivers/scsi/esas2r/esas2r.h readb((void __iomem *)a->data_window + (reg)) reg 361 drivers/scsi/esp_scsi.h void (*esp_write8)(struct esp *esp, u8 val, unsigned long reg); reg 362 drivers/scsi/esp_scsi.h u8 (*esp_read8)(struct esp *esp, unsigned long reg); reg 71 drivers/scsi/fnic/vnic_dev.h static inline u64 readq(void __iomem *reg) reg 73 drivers/scsi/fnic/vnic_dev.h return ((u64)readl(reg + 0x4UL) << 32) | (u64)readl(reg); reg 76 drivers/scsi/fnic/vnic_dev.h static inline void writeq(u64 val, void __iomem *reg) reg 78 drivers/scsi/fnic/vnic_dev.h writel(val & 0xffffffff, reg); reg 79 drivers/scsi/fnic/vnic_dev.h writel(val >> 32, reg + 0x4UL); reg 38 drivers/scsi/g_NCR5380.c #define NCR5380_read(reg) \ reg 39 drivers/scsi/g_NCR5380.c ioread8(hostdata->io + hostdata->offset + (reg)) reg 40 drivers/scsi/g_NCR5380.c #define NCR5380_write(reg, value) \ reg 41 drivers/scsi/g_NCR5380.c iowrite8(value, hostdata->io + hostdata->offset + (reg)) reg 116 drivers/scsi/hisi_sas/hisi_sas.h int reg; reg 2832 drivers/scsi/hisi_sas/hisi_sas_main.c const struct hisi_sas_debugfs_reg *reg = ptr; reg 2835 drivers/scsi/hisi_sas/hisi_sas_main.c for (i = 0; i < reg->count; i++) { reg 2839 drivers/scsi/hisi_sas/hisi_sas_main.c name = hisi_sas_debugfs_to_reg_name(off, reg->base_off, reg 2840 drivers/scsi/hisi_sas/hisi_sas_main.c reg->lu); reg 426 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_DQE_ECC_ADDR, reg 433 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_IOST_ECC_ADDR, reg 440 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_ITCT_ECC_ADDR, reg 447 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_LM_DFX_STATUS2, reg 454 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_LM_DFX_STATUS2, reg 461 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_CQE_ECC_ADDR, reg 468 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_RXM_DFX_STATUS14, reg 475 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_RXM_DFX_STATUS14, reg 482 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_RXM_DFX_STATUS14, reg 489 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_RXM_DFX_STATUS15, reg 499 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_DQE_ECC_ADDR, reg 506 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_IOST_ECC_ADDR, reg 513 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_ITCT_ECC_ADDR, reg 520 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_LM_DFX_STATUS2, reg 527 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_LM_DFX_STATUS2, reg 534 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_CQE_ECC_ADDR, reg 541 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_RXM_DFX_STATUS14, reg 548 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_RXM_DFX_STATUS14, reg 555 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_RXM_DFX_STATUS14, reg 562 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_RXM_DFX_STATUS15, reg 2947 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c val = hisi_sas_read32(hisi_hba, ecc_error->reg); reg 2967 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c val = hisi_sas_read32(hisi_hba, ecc_error->reg); reg 3035 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_AXI_FIFO_ERR_INFO, reg 3040 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c .reg = HGC_AXI_FIFO_ERR_INFO, reg 3076 drivers/scsi/hisi_sas/hisi_sas_v2_hw.c err_value = hisi_sas_read32(hisi_hba, axi_error->reg); reg 1838 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .reg = HGC_DQE_ECC_ADDR, reg 1845 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .reg = HGC_IOST_ECC_ADDR, reg 1852 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .reg = HGC_ITCT_ECC_ADDR, reg 1859 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .reg = HGC_LM_DFX_STATUS2, reg 1866 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .reg = HGC_LM_DFX_STATUS2, reg 1873 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .reg = HGC_CQE_ECC_ADDR, reg 1880 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .reg = HGC_RXM_DFX_STATUS14, reg 1887 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .reg = HGC_RXM_DFX_STATUS14, reg 1894 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .reg = HGC_RXM_DFX_STATUS14, reg 1901 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .reg = HGC_RXM_DFX_STATUS15, reg 1908 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .reg = AM_ROB_ECC_ERR_ADDR, reg 1923 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c val = hisi_sas_read32(hisi_hba, ecc_error->reg); reg 1984 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .reg = HGC_AXI_FIFO_ERR_INFO, reg 1989 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c .reg = HGC_AXI_FIFO_ERR_INFO, reg 2041 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c u32 err_value = hisi_sas_read32(hisi_hba, error->reg); reg 2813 drivers/scsi/initio.c u32 reg; reg 2822 drivers/scsi/initio.c pci_read_config_dword(pdev, 0x44, (u32 *) & reg); reg 2823 drivers/scsi/initio.c bios_seg = (u16) (reg & 0xFF); reg 2824 drivers/scsi/initio.c if (((reg & 0xFF00) >> 8) == 0xFF) reg 2825 drivers/scsi/initio.c reg = 0; reg 2826 drivers/scsi/initio.c bios_seg = (bios_seg << 8) + ((u16) ((reg & 0xFF00) >> 8)); reg 95 drivers/scsi/isci/phy.c struct scu_transport_layer_registers __iomem *reg) reg 99 drivers/scsi/isci/phy.c iphy->transport_layer_registers = reg; reg 201 drivers/scsi/isci/phy.c u32 reg; reg 203 drivers/scsi/isci/phy.c reg = readl(&xcvr->afe_xcvr_control0); reg 204 drivers/scsi/isci/phy.c reg |= (0x00100000 | (sas_type << 19)); reg 205 drivers/scsi/isci/phy.c writel(reg, &xcvr->afe_xcvr_control0); reg 207 drivers/scsi/isci/phy.c reg = readl(&xcvr->afe_tx_ssc_control); reg 208 drivers/scsi/isci/phy.c reg |= sas_spread << 8; reg 209 drivers/scsi/isci/phy.c writel(reg, &xcvr->afe_tx_ssc_control); reg 213 drivers/scsi/isci/phy.c u32 reg; reg 215 drivers/scsi/isci/phy.c reg = readl(&xcvr->afe_tx_ssc_control); reg 216 drivers/scsi/isci/phy.c reg |= sata_spread; reg 217 drivers/scsi/isci/phy.c writel(reg, &xcvr->afe_tx_ssc_control); reg 219 drivers/scsi/isci/phy.c reg = readl(&llr->stp_control); reg 220 drivers/scsi/isci/phy.c reg |= 1 << 12; reg 221 drivers/scsi/isci/phy.c writel(reg, &llr->stp_control); reg 32 drivers/scsi/jazz_esp.c static void jazz_esp_write8(struct esp *esp, u8 val, unsigned long reg) reg 34 drivers/scsi/jazz_esp.c *(volatile u8 *)(esp->regs + reg) = val; reg 37 drivers/scsi/jazz_esp.c static u8 jazz_esp_read8(struct esp *esp, unsigned long reg) reg 39 drivers/scsi/jazz_esp.c return *(volatile u8 *)(esp->regs + reg); reg 76 drivers/scsi/libsas/sas_host_smp.c unsigned int reg; reg 88 drivers/scsi/libsas/sas_host_smp.c reg = od >> 5; reg 90 drivers/scsi/libsas/sas_host_smp.c if (reg >= count) reg 97 drivers/scsi/libsas/sas_host_smp.c return &data[reg * 4 + byte]; reg 63 drivers/scsi/mac_esp.c static inline void mac_esp_write8(struct esp *esp, u8 val, unsigned long reg) reg 65 drivers/scsi/mac_esp.c nubus_writeb(val, esp->regs + reg * 16); reg 68 drivers/scsi/mac_esp.c static inline u8 mac_esp_read8(struct esp *esp, unsigned long reg) reg 70 drivers/scsi/mac_esp.c return nubus_readb(esp->regs + reg * 16); reg 38 drivers/scsi/mac_scsi.c #define NCR5380_read(reg) in_8(hostdata->io + ((reg) << 4)) reg 39 drivers/scsi/mac_scsi.c #define NCR5380_write(reg, value) out_8(hostdata->io + ((reg) << 4), value) reg 1794 drivers/scsi/megaraid/megaraid_sas.h __le32 reg; reg 2921 drivers/scsi/megaraid/megaraid_sas_base.c u32 __iomem *reg = (u32 __iomem *)reg_set; reg 2924 drivers/scsi/megaraid/megaraid_sas_base.c printk("%08x: %08x\n", (i * 4), readl(®[i])); reg 2979 drivers/scsi/megaraid/megaraid_sas_base.c u32 __iomem *reg = (u32 __iomem *)reg_set; reg 2984 drivers/scsi/megaraid/megaraid_sas_base.c readl(®[i])); reg 17 drivers/scsi/mvsas/mv_64xx.c u32 reg; reg 20 drivers/scsi/mvsas/mv_64xx.c reg = mr32(MVS_GBL_PORT_TYPE); reg 22 drivers/scsi/mvsas/mv_64xx.c if (reg & MODE_SAS_SATA & (1 << i)) reg 70 drivers/scsi/mvsas/mv_64xx.c u32 reg, tmp; reg 74 drivers/scsi/mvsas/mv_64xx.c pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, ®); reg 76 drivers/scsi/mvsas/mv_64xx.c pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, ®); reg 79 drivers/scsi/mvsas/mv_64xx.c reg = mr32(MVS_PHY_CTL); reg 81 drivers/scsi/mvsas/mv_64xx.c tmp = reg; reg 91 drivers/scsi/mvsas/mv_64xx.c pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, reg); reg 95 drivers/scsi/mvsas/mv_64xx.c pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, reg); reg 100 drivers/scsi/mvsas/mv_64xx.c mw32(MVS_PHY_CTL, reg); reg 16 drivers/scsi/mvsas/mv_94xx.c u32 reg; reg 21 drivers/scsi/mvsas/mv_94xx.c reg = mvs_read_port_vsr_data(mvi, i); reg 22 drivers/scsi/mvsas/mv_94xx.c phy_status = ((reg & 0x3f0000) >> 16) & 0xff; reg 14 drivers/scsi/mvsas/mv_chips.h #define mr32(reg) readl(regs + reg) reg 15 drivers/scsi/mvsas/mv_chips.h #define mw32(reg, val) writel((val), regs + reg) reg 16 drivers/scsi/mvsas/mv_chips.h #define mw32_f(reg, val) do { \ reg 17 drivers/scsi/mvsas/mv_chips.h mw32(reg, val); \ reg 18 drivers/scsi/mvsas/mv_chips.h mr32(reg); \ reg 21 drivers/scsi/mvsas/mv_chips.h #define iow32(reg, val) outl(val, (unsigned long)(regs + reg)) reg 22 drivers/scsi/mvsas/mv_chips.h #define ior32(reg) inl((unsigned long)(regs + reg)) reg 23 drivers/scsi/mvsas/mv_chips.h #define iow16(reg, val) outw((unsigned long)(val, regs + reg)) reg 24 drivers/scsi/mvsas/mv_chips.h #define ior16(reg) inw((unsigned long)(regs + reg)) reg 25 drivers/scsi/mvsas/mv_chips.h #define iow8(reg, val) outb((unsigned long)(val, regs + reg)) reg 26 drivers/scsi/mvsas/mv_chips.h #define ior8(reg) inb((unsigned long)(regs + reg)) reg 1652 drivers/scsi/ncr53c8xx.c struct ncr_reg __iomem *reg; /* memory mapped IO. */ reg 7709 drivers/scsi/ncr53c8xx.c if (np->reg) { reg 8377 drivers/scsi/ncr53c8xx.c np->reg = (struct ncr_reg __iomem *)np->vaddr; reg 8392 drivers/scsi/ncr53c8xx.c instance->base = (unsigned long) np->reg; reg 379 drivers/scsi/ncr53c8xx.h #define INB_OFF(o) readb_raw((char __iomem *)np->reg + ncr_offb(o)) reg 380 drivers/scsi/ncr53c8xx.h #define OUTB_OFF(o, val) writeb_raw((val), (char __iomem *)np->reg + ncr_offb(o)) reg 384 drivers/scsi/ncr53c8xx.h #define INW_OFF(o) readw_l2b((char __iomem *)np->reg + ncr_offw(o)) reg 385 drivers/scsi/ncr53c8xx.h #define INL_OFF(o) readl_l2b((char __iomem *)np->reg + (o)) reg 387 drivers/scsi/ncr53c8xx.h #define OUTW_OFF(o, val) writew_b2l((val), (char __iomem *)np->reg + ncr_offw(o)) reg 388 drivers/scsi/ncr53c8xx.h #define OUTL_OFF(o, val) writel_b2l((val), (char __iomem *)np->reg + (o)) reg 392 drivers/scsi/ncr53c8xx.h #define INW_OFF(o) readw_b2l((char __iomem *)np->reg + ncr_offw(o)) reg 393 drivers/scsi/ncr53c8xx.h #define INL_OFF(o) readl_b2l((char __iomem *)np->reg + (o)) reg 395 drivers/scsi/ncr53c8xx.h #define OUTW_OFF(o, val) writew_l2b((val), (char __iomem *)np->reg + ncr_offw(o)) reg 396 drivers/scsi/ncr53c8xx.h #define OUTL_OFF(o, val) writel_l2b((val), (char __iomem *)np->reg + (o)) reg 402 drivers/scsi/ncr53c8xx.h #define INW_OFF(o) (readb((char __iomem *)np->reg + ncr_offw(o)) << 8 | readb((char __iomem *)np->reg + ncr_offw(o) + 1)) reg 404 drivers/scsi/ncr53c8xx.h #define INW_OFF(o) readw_raw((char __iomem *)np->reg + ncr_offw(o)) reg 406 drivers/scsi/ncr53c8xx.h #define INL_OFF(o) readl_raw((char __iomem *)np->reg + (o)) reg 410 drivers/scsi/ncr53c8xx.h #define OUTW_OFF(o, val) do { writeb((char)((val) >> 8), (char __iomem *)np->reg + ncr_offw(o)); writeb((char)(val), (char __iomem *)np->reg + ncr_offw(o) + 1); } while (0) reg 412 drivers/scsi/ncr53c8xx.h #define OUTW_OFF(o, val) writew_raw((val), (char __iomem *)np->reg + ncr_offw(o)) reg 414 drivers/scsi/ncr53c8xx.h #define OUTL_OFF(o, val) writel_raw((val), (char __iomem *)np->reg + (o)) reg 1088 drivers/scsi/ncr53c8xx.h #define SCR_SFBR_REG(reg,op,data) \ reg 1089 drivers/scsi/ncr53c8xx.h (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) reg 1091 drivers/scsi/ncr53c8xx.h #define SCR_REG_SFBR(reg,op,data) \ reg 1092 drivers/scsi/ncr53c8xx.h (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) reg 1094 drivers/scsi/ncr53c8xx.h #define SCR_REG_REG(reg,op,data) \ reg 1095 drivers/scsi/ncr53c8xx.h (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) reg 1126 drivers/scsi/ncr53c8xx.h #define SCR_FROM_REG(reg) \ reg 1127 drivers/scsi/ncr53c8xx.h SCR_REG_SFBR(reg,SCR_OR,0) reg 1129 drivers/scsi/ncr53c8xx.h #define SCR_TO_REG(reg) \ reg 1130 drivers/scsi/ncr53c8xx.h SCR_SFBR_REG(reg,SCR_OR,0) reg 1132 drivers/scsi/ncr53c8xx.h #define SCR_LOAD_REG(reg,data) \ reg 1133 drivers/scsi/ncr53c8xx.h SCR_REG_REG(reg,SCR_LOAD,data) reg 1160 drivers/scsi/ncr53c8xx.h #define SCR_LOAD_R(reg, how, n) \ reg 1161 drivers/scsi/ncr53c8xx.h (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) reg 1163 drivers/scsi/ncr53c8xx.h #define SCR_STORE_R(reg, how, n) \ reg 1164 drivers/scsi/ncr53c8xx.h (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) reg 1166 drivers/scsi/ncr53c8xx.h #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) reg 1167 drivers/scsi/ncr53c8xx.h #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) reg 1168 drivers/scsi/ncr53c8xx.h #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) reg 1169 drivers/scsi/ncr53c8xx.h #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) reg 1171 drivers/scsi/ncr53c8xx.h #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n) reg 1172 drivers/scsi/ncr53c8xx.h #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n) reg 1173 drivers/scsi/ncr53c8xx.h #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) reg 1174 drivers/scsi/ncr53c8xx.h #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) reg 1289 drivers/scsi/ncr53c8xx.h volatile struct ncr_reg __iomem *reg; reg 3295 drivers/scsi/nsp32.c unsigned short reg; reg 3303 drivers/scsi/nsp32.c reg = nsp32_read2(data->BaseAddress, INDEX_REG); reg 3305 drivers/scsi/nsp32.c nsp32_msg(KERN_INFO, "io=0x%x reg=0x%x", data->BaseAddress, reg); reg 3307 drivers/scsi/nsp32.c if (reg == 0xffff) { reg 119 drivers/scsi/nsp32_io.h unsigned int reg) reg 121 drivers/scsi/nsp32_io.h outb(reg, base + INDEX_REG); reg 126 drivers/scsi/nsp32_io.h unsigned int reg, reg 129 drivers/scsi/nsp32_io.h outb(reg, base + INDEX_REG ); reg 134 drivers/scsi/nsp32_io.h unsigned int reg) reg 136 drivers/scsi/nsp32_io.h outb(reg, base + INDEX_REG); reg 141 drivers/scsi/nsp32_io.h unsigned int reg, reg 144 drivers/scsi/nsp32_io.h outb(reg, base + INDEX_REG ); reg 149 drivers/scsi/nsp32_io.h unsigned int reg) reg 153 drivers/scsi/nsp32_io.h outb(reg, base + INDEX_REG); reg 161 drivers/scsi/nsp32_io.h unsigned int reg, reg 169 drivers/scsi/nsp32_io.h outb(reg, base + INDEX_REG ); reg 177 drivers/scsi/nsp32_io.h unsigned int reg) reg 184 drivers/scsi/nsp32_io.h writeb(reg, index_ptr); reg 189 drivers/scsi/nsp32_io.h unsigned int reg, reg 197 drivers/scsi/nsp32_io.h writeb(reg, index_ptr); reg 202 drivers/scsi/nsp32_io.h unsigned int reg) reg 209 drivers/scsi/nsp32_io.h writeb(reg, index_ptr); reg 214 drivers/scsi/nsp32_io.h unsigned int reg, reg 222 drivers/scsi/nsp32_io.h writeb(reg, index_ptr); reg 229 drivers/scsi/nsp32_io.h unsigned int reg, reg 233 drivers/scsi/nsp32_io.h insl(base + reg, buf, count); reg 244 drivers/scsi/nsp32_io.h unsigned int reg, reg 248 drivers/scsi/nsp32_io.h outsl(base + reg, buf, count); reg 520 drivers/scsi/pcmcia/nsp_cs.c unsigned char reg; reg 528 drivers/scsi/pcmcia/nsp_cs.c reg = nsp_index_read(base, SCSIBUSMON); reg 529 drivers/scsi/pcmcia/nsp_cs.c if (reg == 0xff) { reg 532 drivers/scsi/pcmcia/nsp_cs.c } while ((--time_out != 0) && (reg & mask) != 0); reg 198 drivers/scsi/pcmcia/nsp_io.h unsigned int reg) reg 203 drivers/scsi/pcmcia/nsp_io.h writeb((unsigned char)reg, index_ptr); reg 208 drivers/scsi/pcmcia/nsp_io.h unsigned int reg, reg 214 drivers/scsi/pcmcia/nsp_io.h writeb((unsigned char)reg, index_ptr); reg 736 drivers/scsi/qla1280.c struct device_reg __iomem *reg; reg 737 drivers/scsi/qla1280.c reg = ha->iobase; reg 739 drivers/scsi/qla1280.c ha->mailbox_out[0] = RD_REG_WORD(®->mailbox0); reg 742 drivers/scsi/qla1280.c RD_REG_WORD(®->ictrl), RD_REG_WORD(®->istatus)); reg 1082 drivers/scsi/qla1280.c struct device_reg __iomem *reg; reg 1092 drivers/scsi/qla1280.c reg = ha->iobase; reg 1096 drivers/scsi/qla1280.c data = qla1280_debounce_register(®->istatus); reg 1408 drivers/scsi/qla1280.c struct device_reg __iomem *reg; reg 1427 drivers/scsi/qla1280.c reg = ha->iobase; reg 1430 drivers/scsi/qla1280.c WRT_REG_WORD(®->semaphore, 0); reg 1431 drivers/scsi/qla1280.c WRT_REG_WORD(®->host_cmd, HC_CLR_RISC_INT); reg 1432 drivers/scsi/qla1280.c WRT_REG_WORD(®->host_cmd, HC_CLR_HOST_INT); reg 1433 drivers/scsi/qla1280.c RD_REG_WORD(®->host_cmd); reg 1557 drivers/scsi/qla1280.c struct device_reg __iomem *reg = ha->iobase; reg 1561 drivers/scsi/qla1280.c dprintk(3, "qla1280_chip_diag: testing device at 0x%p \n", ®->id_l); reg 1566 drivers/scsi/qla1280.c WRT_REG_WORD(®->ictrl, ISP_RESET); reg 1576 drivers/scsi/qla1280.c data = qla1280_debounce_register(®->ictrl); reg 1582 drivers/scsi/qla1280.c data = RD_REG_WORD(®->ictrl); reg 1591 drivers/scsi/qla1280.c WRT_REG_WORD(®->cfg_1, 0); reg 1595 drivers/scsi/qla1280.c WRT_REG_WORD(®->host_cmd, HC_RESET_RISC | reg 1598 drivers/scsi/qla1280.c RD_REG_WORD(®->id_l); /* Flush PCI write */ reg 1599 drivers/scsi/qla1280.c data = qla1280_debounce_register(®->mailbox0); reg 1606 drivers/scsi/qla1280.c data = RD_REG_WORD(®->mailbox0); reg 1615 drivers/scsi/qla1280.c if (RD_REG_WORD(®->mailbox1) != PROD_ID_1 || reg 1616 drivers/scsi/qla1280.c (RD_REG_WORD(®->mailbox2) != PROD_ID_2 && reg 1617 drivers/scsi/qla1280.c RD_REG_WORD(®->mailbox2) != PROD_ID_2a) || reg 1618 drivers/scsi/qla1280.c RD_REG_WORD(®->mailbox3) != PROD_ID_3 || reg 1619 drivers/scsi/qla1280.c RD_REG_WORD(®->mailbox4) != PROD_ID_4) { reg 1622 drivers/scsi/qla1280.c RD_REG_WORD(®->mailbox1), reg 1623 drivers/scsi/qla1280.c RD_REG_WORD(®->mailbox2), reg 1624 drivers/scsi/qla1280.c RD_REG_WORD(®->mailbox3), reg 1625 drivers/scsi/qla1280.c RD_REG_WORD(®->mailbox4)); reg 2155 drivers/scsi/qla1280.c struct device_reg __iomem *reg = ha->iobase; reg 2182 drivers/scsi/qla1280.c hwrev = RD_REG_WORD(®->cfg_0) & ISP_CFG0_HWMSK; reg 2184 drivers/scsi/qla1280.c cfg1 = RD_REG_WORD(®->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6); reg 2185 drivers/scsi/qla1280.c cdma_conf = RD_REG_WORD(®->cdma_cfg); reg 2186 drivers/scsi/qla1280.c ddma_conf = RD_REG_WORD(®->ddma_cfg); reg 2193 drivers/scsi/qla1280.c WRT_REG_WORD(®->cfg_1, cfg1); reg 2195 drivers/scsi/qla1280.c WRT_REG_WORD(®->cdma_cfg, cdma_conf | CDMA_CONF_BENAB); reg 2196 drivers/scsi/qla1280.c WRT_REG_WORD(®->ddma_cfg, cdma_conf | DDMA_CONF_BENAB); reg 2206 drivers/scsi/qla1280.c WRT_REG_WORD(®->cfg_1, cfg1); reg 2209 drivers/scsi/qla1280.c WRT_REG_WORD(®->gpio_enable, reg 2214 drivers/scsi/qla1280.c RD_REG_WORD(®->id_l); /* Flush PCI write */ reg 2215 drivers/scsi/qla1280.c WRT_REG_WORD(®->gpio_data, term); reg 2217 drivers/scsi/qla1280.c RD_REG_WORD(®->id_l); /* Flush PCI write */ reg 2343 drivers/scsi/qla1280.c struct device_reg __iomem *reg = ha->iobase; reg 2362 drivers/scsi/qla1280.c WRT_REG_WORD(®->nvram, (NV_SELECT | NV_CLOCK)); reg 2363 drivers/scsi/qla1280.c RD_REG_WORD(®->id_l); /* Flush PCI write */ reg 2366 drivers/scsi/qla1280.c reg_data = RD_REG_WORD(®->nvram); reg 2369 drivers/scsi/qla1280.c WRT_REG_WORD(®->nvram, NV_SELECT); reg 2370 drivers/scsi/qla1280.c RD_REG_WORD(®->id_l); /* Flush PCI write */ reg 2376 drivers/scsi/qla1280.c WRT_REG_WORD(®->nvram, NV_DESELECT); reg 2377 drivers/scsi/qla1280.c RD_REG_WORD(®->id_l); /* Flush PCI write */ reg 2386 drivers/scsi/qla1280.c struct device_reg __iomem *reg = ha->iobase; reg 2388 drivers/scsi/qla1280.c WRT_REG_WORD(®->nvram, data | NV_SELECT); reg 2389 drivers/scsi/qla1280.c RD_REG_WORD(®->id_l); /* Flush PCI write */ reg 2391 drivers/scsi/qla1280.c WRT_REG_WORD(®->nvram, data | NV_SELECT | NV_CLOCK); reg 2392 drivers/scsi/qla1280.c RD_REG_WORD(®->id_l); /* Flush PCI write */ reg 2394 drivers/scsi/qla1280.c WRT_REG_WORD(®->nvram, data | NV_SELECT); reg 2395 drivers/scsi/qla1280.c RD_REG_WORD(®->id_l); /* Flush PCI write */ reg 2417 drivers/scsi/qla1280.c struct device_reg __iomem *reg = ha->iobase; reg 2437 drivers/scsi/qla1280.c mptr = (uint16_t __iomem *) ®->mailbox0; reg 2456 drivers/scsi/qla1280.c WRT_REG_WORD(®->host_cmd, HC_SET_HOST_INT); reg 2457 drivers/scsi/qla1280.c data = qla1280_debounce_register(®->istatus); reg 2471 drivers/scsi/qla1280.c mb[0], ha->mailbox_out[0], RD_REG_WORD(®->istatus)); reg 2473 drivers/scsi/qla1280.c RD_REG_WORD(®->mailbox0), RD_REG_WORD(®->mailbox1), reg 2474 drivers/scsi/qla1280.c RD_REG_WORD(®->mailbox2), RD_REG_WORD(®->mailbox3)); reg 2476 drivers/scsi/qla1280.c RD_REG_WORD(®->mailbox4), RD_REG_WORD(®->mailbox5), reg 2477 drivers/scsi/qla1280.c RD_REG_WORD(®->mailbox6), RD_REG_WORD(®->mailbox7)); reg 2508 drivers/scsi/qla1280.c struct device_reg __iomem *reg = ha->iobase; reg 2515 drivers/scsi/qla1280.c data = RD_REG_WORD(®->istatus); reg 2676 drivers/scsi/qla1280.c struct device_reg __iomem *reg = ha->iobase; reg 2682 drivers/scsi/qla1280.c WRT_REG_WORD(®->ictrl, ISP_RESET); reg 2683 drivers/scsi/qla1280.c WRT_REG_WORD(®->host_cmd, reg 2685 drivers/scsi/qla1280.c RD_REG_WORD(®->id_l); /* Flush PCI write */ reg 2740 drivers/scsi/qla1280.c struct device_reg __iomem *reg = ha->iobase; reg 2769 drivers/scsi/qla1280.c cnt = RD_REG_WORD(®->mailbox4); reg 2960 drivers/scsi/qla1280.c WRT_REG_WORD(®->mailbox4, ha->req_ring_index); reg 2994 drivers/scsi/qla1280.c struct device_reg __iomem *reg = ha->iobase; reg 3031 drivers/scsi/qla1280.c cnt = RD_REG_WORD(®->mailbox4); reg 3208 drivers/scsi/qla1280.c WRT_REG_WORD(®->mailbox4, ha->req_ring_index); reg 3234 drivers/scsi/qla1280.c struct device_reg __iomem *reg = ha->iobase; reg 3248 drivers/scsi/qla1280.c cnt = RD_REG_WORD(®->mailbox4); reg 3302 drivers/scsi/qla1280.c struct device_reg __iomem *reg = ha->iobase; reg 3321 drivers/scsi/qla1280.c WRT_REG_WORD(®->mailbox4, ha->req_ring_index); reg 3341 drivers/scsi/qla1280.c struct device_reg __iomem *reg = ha->iobase; reg 3351 drivers/scsi/qla1280.c istatus = RD_REG_WORD(®->istatus); reg 3356 drivers/scsi/qla1280.c mailbox[5] = RD_REG_WORD(®->mailbox5); reg 3360 drivers/scsi/qla1280.c mailbox[0] = RD_REG_WORD_dmasync(®->semaphore); reg 3367 drivers/scsi/qla1280.c *wptr++ = RD_REG_WORD(®->mailbox0); reg 3368 drivers/scsi/qla1280.c *wptr++ = RD_REG_WORD(®->mailbox1); reg 3369 drivers/scsi/qla1280.c *wptr = RD_REG_WORD(®->mailbox2); reg 3372 drivers/scsi/qla1280.c *wptr++ = RD_REG_WORD(®->mailbox3); reg 3373 drivers/scsi/qla1280.c *wptr++ = RD_REG_WORD(®->mailbox4); reg 3375 drivers/scsi/qla1280.c *wptr++ = RD_REG_WORD(®->mailbox6); reg 3376 drivers/scsi/qla1280.c *wptr = RD_REG_WORD(®->mailbox7); reg 3381 drivers/scsi/qla1280.c WRT_REG_WORD(®->semaphore, 0); reg 3382 drivers/scsi/qla1280.c WRT_REG_WORD(®->host_cmd, HC_CLR_RISC_INT); reg 3486 drivers/scsi/qla1280.c WRT_REG_WORD(®->host_cmd, HC_CLR_RISC_INT); reg 3543 drivers/scsi/qla1280.c WRT_REG_WORD(®->mailbox5, ha->rsp_ring_index); reg 3760 drivers/scsi/qla1280.c struct device_reg __iomem *reg = ha->iobase; reg 3775 drivers/scsi/qla1280.c WRT_REG_WORD(®->host_cmd, HC_PAUSE_RISC); reg 3776 drivers/scsi/qla1280.c RD_REG_WORD(®->id_l); reg 3867 drivers/scsi/qla1280.c struct device_reg __iomem *reg = ha->iobase; reg 3870 drivers/scsi/qla1280.c WRT_REG_WORD(®->host_cmd, HC_PAUSE_RISC); reg 3871 drivers/scsi/qla1280.c config_reg = RD_REG_WORD(®->cfg_1); reg 3872 drivers/scsi/qla1280.c WRT_REG_WORD(®->cfg_1, SET_SXP_BANK); reg 3873 drivers/scsi/qla1280.c scsi_control = RD_REG_WORD(®->scsiControlPins); reg 3874 drivers/scsi/qla1280.c WRT_REG_WORD(®->cfg_1, config_reg); reg 3875 drivers/scsi/qla1280.c WRT_REG_WORD(®->host_cmd, HC_RELEASE_RISC); reg 114 drivers/scsi/qla2xxx/qla_dbg.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 127 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox0, MBC_LOAD_DUMP_MPI_RAM); reg 128 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox1, LSW(addr)); reg 129 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox8, MSW(addr)); reg 131 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox2, MSW(LSD(dump_dma))); reg 132 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox3, LSW(LSD(dump_dma))); reg 133 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); reg 134 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); reg 136 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox4, MSW(dwords)); reg 137 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox5, LSW(dwords)); reg 139 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox9, 0); reg 140 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); reg 146 drivers/scsi/qla2xxx/qla_dbg.c stat = RD_REG_DWORD(®->host_status); reg 156 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); reg 157 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->hccr); reg 162 drivers/scsi/qla2xxx/qla_dbg.c rval = RD_REG_WORD(®->mailbox0) & MBS_MASK; reg 163 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); reg 164 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->hccr); reg 194 drivers/scsi/qla2xxx/qla_dbg.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 207 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED); reg 208 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox1, LSW(addr)); reg 209 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox8, MSW(addr)); reg 211 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox2, MSW(LSD(dump_dma))); reg 212 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox3, LSW(LSD(dump_dma))); reg 213 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); reg 214 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); reg 216 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox4, MSW(dwords)); reg 217 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mailbox5, LSW(dwords)); reg 218 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); reg 223 drivers/scsi/qla2xxx/qla_dbg.c stat = RD_REG_DWORD(®->host_status); reg 232 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); reg 233 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->hccr); reg 238 drivers/scsi/qla2xxx/qla_dbg.c rval = RD_REG_WORD(®->mailbox0) & MBS_MASK; reg 239 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); reg 240 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->hccr); reg 288 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, reg 293 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_addr, iobase); reg 294 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->iobase_window; reg 302 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_pause_risc(struct device_reg_24xx __iomem *reg, struct qla_hw_data *ha) reg 304 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); reg 308 drivers/scsi/qla2xxx/qla_dbg.c if (RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) reg 318 drivers/scsi/qla2xxx/qla_dbg.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 325 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); reg 327 drivers/scsi/qla2xxx/qla_dbg.c if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) reg 332 drivers/scsi/qla2xxx/qla_dbg.c if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)) reg 335 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->ctrl_status, reg 343 drivers/scsi/qla2xxx/qla_dbg.c if ((RD_REG_DWORD(®->ctrl_status) & reg 349 drivers/scsi/qla2xxx/qla_dbg.c if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_ISP_SOFT_RESET)) reg 352 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); reg 353 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->hccr); /* PCI Posting. */ reg 355 drivers/scsi/qla2xxx/qla_dbg.c for (cnt = 10000; RD_REG_WORD(®->mailbox0) != 0 && reg 375 drivers/scsi/qla2xxx/qla_dbg.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 382 drivers/scsi/qla2xxx/qla_dbg.c WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED); reg 391 drivers/scsi/qla2xxx/qla_dbg.c WRT_MAILBOX_REG(ha, reg, 1, LSW(addr)); reg 392 drivers/scsi/qla2xxx/qla_dbg.c WRT_MAILBOX_REG(ha, reg, 8, MSW(addr)); reg 394 drivers/scsi/qla2xxx/qla_dbg.c WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma)); reg 395 drivers/scsi/qla2xxx/qla_dbg.c WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma)); reg 396 drivers/scsi/qla2xxx/qla_dbg.c WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma))); reg 397 drivers/scsi/qla2xxx/qla_dbg.c WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma))); reg 399 drivers/scsi/qla2xxx/qla_dbg.c WRT_MAILBOX_REG(ha, reg, 4, words); reg 400 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); reg 404 drivers/scsi/qla2xxx/qla_dbg.c stat = RD_REG_DWORD(®->u.isp2300.host_status); reg 412 drivers/scsi/qla2xxx/qla_dbg.c mb0 = RD_MAILBOX_REG(ha, reg, 0); reg 415 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->semaphore, 0); reg 416 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->hccr, reg 418 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_WORD(®->hccr); reg 424 drivers/scsi/qla2xxx/qla_dbg.c mb0 = RD_MAILBOX_REG(ha, reg, 0); reg 426 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->hccr, reg 428 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_WORD(®->hccr); reg 433 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); reg 434 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_WORD(®->hccr); reg 453 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, reg 456 drivers/scsi/qla2xxx/qla_dbg.c uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd; reg 668 drivers/scsi/qla2xxx/qla_dbg.c device_reg_t *reg; reg 683 drivers/scsi/qla2xxx/qla_dbg.c reg = ISP_QUE_REG(ha, cnt); reg 686 drivers/scsi/qla2xxx/qla_dbg.c htonl(RD_REG_DWORD(®->isp25mq.req_q_in)); reg 688 drivers/scsi/qla2xxx/qla_dbg.c htonl(RD_REG_DWORD(®->isp25mq.req_q_out)); reg 690 drivers/scsi/qla2xxx/qla_dbg.c htonl(RD_REG_DWORD(®->isp25mq.rsp_q_in)); reg 692 drivers/scsi/qla2xxx/qla_dbg.c htonl(RD_REG_DWORD(®->isp25mq.rsp_q_out)); reg 728 drivers/scsi/qla2xxx/qla_dbg.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 759 drivers/scsi/qla2xxx/qla_dbg.c fw->hccr = htons(RD_REG_WORD(®->hccr)); reg 762 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); reg 765 drivers/scsi/qla2xxx/qla_dbg.c (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && reg 773 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_WORD(®->hccr); /* PCI Posting. */ reg 778 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->flash_address; reg 782 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->u.isp2300.req_q_in; reg 787 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->u.isp2300.mailbox0; reg 792 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->ctrl_status, 0x40); reg 793 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 32, fw->resp_dma_reg); reg 795 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->ctrl_status, 0x50); reg 796 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 48, fw->dma_reg); reg 798 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->ctrl_status, 0x00); reg 799 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->risc_hw; reg 804 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->pcr, 0x2000); reg 805 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); reg 807 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->pcr, 0x2200); reg 808 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); reg 810 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->pcr, 0x2400); reg 811 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); reg 813 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->pcr, 0x2600); reg 814 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); reg 816 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->pcr, 0x2800); reg 817 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); reg 819 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->pcr, 0x2A00); reg 820 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); reg 822 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->pcr, 0x2C00); reg 823 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); reg 825 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->pcr, 0x2E00); reg 826 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); reg 828 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->ctrl_status, 0x10); reg 829 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg); reg 831 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->ctrl_status, 0x20); reg 832 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); reg 834 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->ctrl_status, 0x30); reg 835 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); reg 838 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); reg 840 drivers/scsi/qla2xxx/qla_dbg.c if ((RD_REG_WORD(®->ctrl_status) & reg 849 drivers/scsi/qla2xxx/qla_dbg.c for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && reg 900 drivers/scsi/qla2xxx/qla_dbg.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 932 drivers/scsi/qla2xxx/qla_dbg.c fw->hccr = htons(RD_REG_WORD(®->hccr)); reg 935 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); reg 936 drivers/scsi/qla2xxx/qla_dbg.c for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && reg 944 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->flash_address; reg 948 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->u.isp2100.mailbox0; reg 951 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->u_end.isp2200.mailbox8; reg 956 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->u.isp2100.unused_2[0]; reg 960 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->ctrl_status, 0x00); reg 961 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->risc_hw; reg 965 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->pcr, 0x2000); reg 966 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); reg 968 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->pcr, 0x2100); reg 969 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); reg 971 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->pcr, 0x2200); reg 972 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); reg 974 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->pcr, 0x2300); reg 975 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); reg 977 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->pcr, 0x2400); reg 978 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); reg 980 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->pcr, 0x2500); reg 981 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); reg 983 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->pcr, 0x2600); reg 984 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); reg 986 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->pcr, 0x2700); reg 987 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); reg 989 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->ctrl_status, 0x10); reg 990 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg); reg 992 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->ctrl_status, 0x20); reg 993 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); reg 995 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->ctrl_status, 0x30); reg 996 drivers/scsi/qla2xxx/qla_dbg.c qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); reg 999 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); reg 1002 drivers/scsi/qla2xxx/qla_dbg.c for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && reg 1012 drivers/scsi/qla2xxx/qla_dbg.c (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { reg 1014 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); reg 1016 drivers/scsi/qla2xxx/qla_dbg.c (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && reg 1026 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mctr, 0xf1); reg 1028 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->mctr, 0xf2); reg 1029 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_WORD(®->mctr); /* PCI Posting. */ reg 1032 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); reg 1039 drivers/scsi/qla2xxx/qla_dbg.c WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); reg 1044 drivers/scsi/qla2xxx/qla_dbg.c WRT_MAILBOX_REG(ha, reg, 1, risc_address); reg 1045 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); reg 1049 drivers/scsi/qla2xxx/qla_dbg.c if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) { reg 1050 drivers/scsi/qla2xxx/qla_dbg.c if (RD_REG_WORD(®->semaphore) & BIT_0) { reg 1054 drivers/scsi/qla2xxx/qla_dbg.c mb0 = RD_MAILBOX_REG(ha, reg, 0); reg 1055 drivers/scsi/qla2xxx/qla_dbg.c mb2 = RD_MAILBOX_REG(ha, reg, 2); reg 1057 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->semaphore, 0); reg 1058 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->hccr, reg 1060 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_WORD(®->hccr); reg 1063 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); reg 1064 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_WORD(®->hccr); reg 1097 drivers/scsi/qla2xxx/qla_dbg.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 1136 drivers/scsi/qla2xxx/qla_dbg.c fw->host_status = htonl(RD_REG_DWORD(®->host_status)); reg 1142 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_pause_risc(reg, ha); reg 1145 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->flash_addr; reg 1150 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->ictrl, 0); reg 1151 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->ictrl); reg 1154 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_addr, 0x0F70); reg 1155 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->iobase_addr); reg 1156 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0000000); reg 1157 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1159 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0100000); reg 1160 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1162 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0200000); reg 1163 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1165 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0300000); reg 1166 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1168 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0400000); reg 1169 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1171 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0500000); reg 1172 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1174 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0600000); reg 1175 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1178 drivers/scsi/qla2xxx/qla_dbg.c mbx_reg = ®->mailbox0; reg 1184 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); reg 1185 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); reg 1186 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); reg 1187 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); reg 1188 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); reg 1189 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); reg 1190 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); reg 1191 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xBF70, 16, iter_reg); reg 1193 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg); reg 1194 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); reg 1198 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); reg 1199 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); reg 1200 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); reg 1201 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); reg 1202 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); reg 1203 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); reg 1204 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); reg 1205 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xFF70, 16, iter_reg); reg 1207 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg); reg 1208 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); reg 1209 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); reg 1212 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); reg 1216 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); reg 1217 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->iobase_q; reg 1222 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); reg 1223 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->iobase_q; reg 1228 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); reg 1229 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->iobase_q; reg 1235 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); reg 1236 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7610, 16, iter_reg); reg 1239 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); reg 1240 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7630, 16, iter_reg); reg 1243 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); reg 1244 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7650, 16, iter_reg); reg 1247 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); reg 1248 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7670, 16, iter_reg); reg 1251 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); reg 1252 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7690, 16, iter_reg); reg 1254 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); reg 1258 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); reg 1259 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7710, 16, iter_reg); reg 1262 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); reg 1263 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7730, 16, iter_reg); reg 1267 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); reg 1268 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); reg 1269 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); reg 1270 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); reg 1271 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); reg 1272 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); reg 1273 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); reg 1274 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x0F70, 16, iter_reg); reg 1278 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); reg 1279 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); reg 1280 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); reg 1281 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); reg 1282 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); reg 1283 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); reg 1284 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x3060, 16, iter_reg); reg 1288 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); reg 1289 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); reg 1290 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); reg 1291 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); reg 1292 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); reg 1293 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); reg 1294 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); reg 1295 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); reg 1296 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); reg 1297 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); reg 1298 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); reg 1299 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x40B0, 16, iter_reg); reg 1303 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); reg 1304 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); reg 1305 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); reg 1306 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); reg 1307 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); reg 1308 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); reg 1309 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); reg 1310 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); reg 1311 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); reg 1312 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); reg 1313 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x61B0, 16, iter_reg); reg 1356 drivers/scsi/qla2xxx/qla_dbg.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 1392 drivers/scsi/qla2xxx/qla_dbg.c fw->host_status = htonl(RD_REG_DWORD(®->host_status)); reg 1398 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_pause_risc(reg, ha); reg 1402 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); reg 1403 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7010, 16, iter_reg); reg 1406 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_addr, 0x7C00); reg 1407 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->iobase_addr); reg 1408 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_window, 0x01); reg 1409 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->iobase_c4; reg 1415 drivers/scsi/qla2xxx/qla_dbg.c fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); reg 1417 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_window, 0x00); reg 1418 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->iobase_window); reg 1421 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->flash_addr; reg 1426 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->ictrl, 0); reg 1427 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->ictrl); reg 1430 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_addr, 0x0F70); reg 1431 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->iobase_addr); reg 1432 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0000000); reg 1433 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1435 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0100000); reg 1436 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1438 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0200000); reg 1439 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1441 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0300000); reg 1442 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1444 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0400000); reg 1445 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1447 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0500000); reg 1448 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1450 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0600000); reg 1451 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1453 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0700000); reg 1454 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1456 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0800000); reg 1457 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1459 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0900000); reg 1460 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1462 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0A00000); reg 1463 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1466 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_addr, 0x0010); reg 1467 drivers/scsi/qla2xxx/qla_dbg.c fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); reg 1470 drivers/scsi/qla2xxx/qla_dbg.c mbx_reg = ®->mailbox0; reg 1476 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); reg 1477 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); reg 1478 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); reg 1479 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); reg 1480 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); reg 1481 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); reg 1482 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); reg 1483 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xBF70, 16, iter_reg); reg 1486 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); reg 1487 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); reg 1488 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); reg 1490 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); reg 1494 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); reg 1495 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); reg 1496 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); reg 1497 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); reg 1498 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); reg 1499 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); reg 1500 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); reg 1501 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xFF70, 16, iter_reg); reg 1504 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); reg 1505 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); reg 1507 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); reg 1508 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); reg 1512 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); reg 1513 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); reg 1514 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); reg 1515 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); reg 1516 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); reg 1517 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); reg 1518 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); reg 1519 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xB070, 16, iter_reg); reg 1522 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); reg 1523 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); reg 1525 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); reg 1526 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); reg 1529 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); reg 1533 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); reg 1534 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->iobase_q; reg 1539 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); reg 1540 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->iobase_q; reg 1545 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); reg 1546 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->iobase_q; reg 1552 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); reg 1553 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7610, 16, iter_reg); reg 1556 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); reg 1557 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7630, 16, iter_reg); reg 1560 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); reg 1561 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7650, 16, iter_reg); reg 1564 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); reg 1565 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7670, 16, iter_reg); reg 1568 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); reg 1569 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7690, 16, iter_reg); reg 1571 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); reg 1575 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); reg 1576 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7710, 16, iter_reg); reg 1579 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); reg 1580 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7730, 16, iter_reg); reg 1584 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); reg 1585 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); reg 1586 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); reg 1587 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); reg 1588 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); reg 1589 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); reg 1590 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); reg 1591 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x0F70, 16, iter_reg); reg 1595 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); reg 1596 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); reg 1597 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); reg 1598 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); reg 1599 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); reg 1600 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); reg 1601 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); reg 1602 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x3070, 16, iter_reg); reg 1606 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); reg 1607 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); reg 1608 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); reg 1609 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); reg 1610 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); reg 1611 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); reg 1612 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); reg 1613 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); reg 1614 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); reg 1615 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); reg 1616 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); reg 1617 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x40B0, 16, iter_reg); reg 1621 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); reg 1622 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); reg 1623 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); reg 1624 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); reg 1625 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); reg 1626 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); reg 1627 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); reg 1628 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); reg 1629 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); reg 1630 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); reg 1631 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); reg 1632 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x6F00, 16, iter_reg); reg 1682 drivers/scsi/qla2xxx/qla_dbg.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 1716 drivers/scsi/qla2xxx/qla_dbg.c fw->host_status = htonl(RD_REG_DWORD(®->host_status)); reg 1722 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_pause_risc(reg, ha); reg 1726 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); reg 1727 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7010, 16, iter_reg); reg 1730 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_addr, 0x7C00); reg 1731 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->iobase_addr); reg 1732 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_window, 0x01); reg 1733 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->iobase_c4; reg 1739 drivers/scsi/qla2xxx/qla_dbg.c fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); reg 1741 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_window, 0x00); reg 1742 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->iobase_window); reg 1745 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->flash_addr; reg 1750 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->ictrl, 0); reg 1751 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->ictrl); reg 1754 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_addr, 0x0F70); reg 1755 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->iobase_addr); reg 1756 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0000000); reg 1757 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1759 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0100000); reg 1760 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1762 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0200000); reg 1763 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1765 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0300000); reg 1766 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1768 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0400000); reg 1769 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1771 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0500000); reg 1772 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1774 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0600000); reg 1775 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1777 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0700000); reg 1778 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1780 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0800000); reg 1781 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1783 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0900000); reg 1784 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1786 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0A00000); reg 1787 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 1790 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_addr, 0x0010); reg 1791 drivers/scsi/qla2xxx/qla_dbg.c fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); reg 1794 drivers/scsi/qla2xxx/qla_dbg.c mbx_reg = ®->mailbox0; reg 1800 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); reg 1801 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); reg 1802 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); reg 1803 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); reg 1804 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); reg 1805 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); reg 1806 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); reg 1807 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xBF70, 16, iter_reg); reg 1810 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); reg 1811 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); reg 1812 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); reg 1814 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); reg 1818 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); reg 1819 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); reg 1820 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); reg 1821 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); reg 1822 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); reg 1823 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); reg 1824 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); reg 1825 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xFF70, 16, iter_reg); reg 1828 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); reg 1829 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); reg 1831 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); reg 1832 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); reg 1836 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); reg 1837 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); reg 1838 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); reg 1839 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); reg 1840 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); reg 1841 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); reg 1842 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); reg 1843 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xB070, 16, iter_reg); reg 1846 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); reg 1847 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); reg 1849 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); reg 1850 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); reg 1853 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); reg 1857 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); reg 1858 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->iobase_q; reg 1863 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); reg 1864 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->iobase_q; reg 1869 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); reg 1870 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->iobase_q; reg 1876 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); reg 1877 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7610, 16, iter_reg); reg 1880 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); reg 1881 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7630, 16, iter_reg); reg 1884 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); reg 1885 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7650, 16, iter_reg); reg 1888 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); reg 1889 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7670, 16, iter_reg); reg 1892 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); reg 1893 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7690, 16, iter_reg); reg 1895 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); reg 1899 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); reg 1900 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7710, 16, iter_reg); reg 1903 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); reg 1904 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7730, 16, iter_reg); reg 1908 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); reg 1909 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); reg 1910 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); reg 1911 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); reg 1912 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); reg 1913 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); reg 1914 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); reg 1915 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x0F70, 16, iter_reg); reg 1919 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); reg 1920 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); reg 1921 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); reg 1922 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); reg 1923 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); reg 1924 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); reg 1925 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); reg 1926 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x3070, 16, iter_reg); reg 1930 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); reg 1931 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); reg 1932 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); reg 1933 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); reg 1934 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); reg 1935 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); reg 1936 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); reg 1937 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); reg 1938 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); reg 1939 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); reg 1940 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); reg 1941 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); reg 1942 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); reg 1943 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x40D0, 16, iter_reg); reg 1947 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); reg 1948 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); reg 1949 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); reg 1950 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); reg 1951 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); reg 1952 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); reg 1953 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); reg 1954 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); reg 1955 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); reg 1956 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); reg 1957 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); reg 1958 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); reg 1959 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x6F00, 16, iter_reg); reg 2010 drivers/scsi/qla2xxx/qla_dbg.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 2044 drivers/scsi/qla2xxx/qla_dbg.c fw->host_status = htonl(RD_REG_DWORD(®->host_status)); reg 2050 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_pause_risc(reg, ha); reg 2052 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_addr, 0x6000); reg 2053 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->iobase_window; reg 2057 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->unused_4_1[0]; reg 2061 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_addr, 0x6010); reg 2062 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->unused_4_1[2]; reg 2067 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_addr, 0x0F70); reg 2068 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->iobase_addr); reg 2069 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0x60000000); /* write to F0h = PCR */ reg 2073 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); reg 2074 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg); reg 2075 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7040, 16, iter_reg); reg 2078 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_addr, 0x7C00); reg 2079 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->iobase_addr); reg 2080 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_window, 0x01); reg 2081 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->iobase_c4; reg 2087 drivers/scsi/qla2xxx/qla_dbg.c fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); reg 2089 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_window, 0x00); reg 2090 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->iobase_window); reg 2093 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->flash_addr; reg 2098 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->ictrl, 0); reg 2099 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->ictrl); reg 2102 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_addr, 0x0F70); reg 2103 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->iobase_addr); reg 2104 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0000000); reg 2105 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 2107 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0100000); reg 2108 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 2110 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0200000); reg 2111 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 2113 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0300000); reg 2114 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 2116 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0400000); reg 2117 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 2119 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0500000); reg 2120 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 2122 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0600000); reg 2123 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 2125 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0700000); reg 2126 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 2128 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0800000); reg 2129 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 2131 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0900000); reg 2132 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 2134 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_select, 0xB0A00000); reg 2135 drivers/scsi/qla2xxx/qla_dbg.c fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); reg 2138 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->iobase_addr, 0x0010); reg 2139 drivers/scsi/qla2xxx/qla_dbg.c fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); reg 2142 drivers/scsi/qla2xxx/qla_dbg.c mbx_reg = ®->mailbox0; reg 2148 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg); reg 2149 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg); reg 2150 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg); reg 2151 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg); reg 2152 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg); reg 2153 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg); reg 2154 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg); reg 2155 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg); reg 2156 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); reg 2157 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); reg 2158 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); reg 2159 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); reg 2160 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); reg 2161 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); reg 2162 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); reg 2163 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xBF70, 16, iter_reg); reg 2166 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); reg 2167 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); reg 2168 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); reg 2170 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); reg 2172 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg); reg 2176 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg); reg 2177 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg); reg 2178 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg); reg 2179 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg); reg 2180 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg); reg 2181 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg); reg 2182 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg); reg 2183 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg); reg 2184 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); reg 2185 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); reg 2186 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); reg 2187 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); reg 2188 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); reg 2189 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); reg 2190 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); reg 2191 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xFF70, 16, iter_reg); reg 2194 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); reg 2195 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); reg 2197 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); reg 2198 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); reg 2199 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg); reg 2203 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); reg 2204 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); reg 2205 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); reg 2206 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); reg 2207 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); reg 2208 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); reg 2209 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); reg 2210 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg); reg 2211 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg); reg 2212 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg); reg 2213 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg); reg 2214 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg); reg 2215 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg); reg 2216 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg); reg 2217 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg); reg 2218 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xB170, 16, iter_reg); reg 2221 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); reg 2222 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); reg 2224 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); reg 2225 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); reg 2226 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg); reg 2230 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg); reg 2231 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg); reg 2232 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg); reg 2233 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x71F0, 16, iter_reg); reg 2237 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); reg 2238 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->iobase_q; reg 2243 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); reg 2244 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->iobase_q; reg 2249 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); reg 2250 drivers/scsi/qla2xxx/qla_dbg.c dmp_reg = ®->iobase_q; reg 2256 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); reg 2257 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7610, 16, iter_reg); reg 2260 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); reg 2261 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7630, 16, iter_reg); reg 2264 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); reg 2265 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7650, 16, iter_reg); reg 2268 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); reg 2269 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7670, 16, iter_reg); reg 2272 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); reg 2273 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7690, 16, iter_reg); reg 2275 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); reg 2279 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); reg 2280 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7710, 16, iter_reg); reg 2283 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); reg 2284 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7730, 16, iter_reg); reg 2288 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); reg 2289 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); reg 2290 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); reg 2291 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); reg 2292 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); reg 2293 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); reg 2294 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); reg 2295 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x0F70, 16, iter_reg); reg 2299 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); reg 2300 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); reg 2301 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); reg 2302 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); reg 2303 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); reg 2304 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); reg 2305 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); reg 2306 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x3070, 16, iter_reg); reg 2310 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); reg 2311 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); reg 2312 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); reg 2313 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); reg 2314 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); reg 2315 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); reg 2316 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); reg 2317 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); reg 2318 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); reg 2319 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); reg 2320 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); reg 2321 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); reg 2322 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); reg 2323 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg); reg 2324 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg); reg 2325 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x40F0, 16, iter_reg); reg 2329 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg); reg 2330 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg); reg 2331 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg); reg 2332 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg); reg 2333 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg); reg 2334 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg); reg 2335 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg); reg 2336 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg); reg 2337 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg); reg 2338 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg); reg 2339 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg); reg 2340 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg); reg 2341 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg); reg 2342 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg); reg 2343 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg); reg 2344 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x5CF0, 16, iter_reg); reg 2348 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg); reg 2349 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg); reg 2350 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg); reg 2351 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg); reg 2352 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg); reg 2353 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg); reg 2354 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg); reg 2355 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg); reg 2356 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg); reg 2357 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg); reg 2358 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg); reg 2359 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg); reg 2360 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg); reg 2361 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg); reg 2362 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg); reg 2363 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x5DF0, 16, iter_reg); reg 2367 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg); reg 2368 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg); reg 2369 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg); reg 2370 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg); reg 2371 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg); reg 2372 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg); reg 2373 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg); reg 2374 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg); reg 2375 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg); reg 2376 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg); reg 2377 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg); reg 2378 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg); reg 2379 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg); reg 2380 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg); reg 2381 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg); reg 2382 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x5EF0, 16, iter_reg); reg 2386 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg); reg 2387 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg); reg 2388 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg); reg 2389 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg); reg 2390 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg); reg 2391 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg); reg 2392 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg); reg 2393 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg); reg 2394 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg); reg 2395 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg); reg 2396 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg); reg 2397 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg); reg 2398 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg); reg 2399 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg); reg 2400 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg); reg 2401 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x5FF0, 16, iter_reg); reg 2404 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg); reg 2405 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg); reg 2406 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg); reg 2407 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg); reg 2408 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg); reg 2409 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg); reg 2410 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg); reg 2411 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x70F0, 16, iter_reg); reg 2414 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg); reg 2418 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); reg 2419 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); reg 2420 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); reg 2421 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); reg 2422 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); reg 2423 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg); reg 2424 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg); reg 2425 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); reg 2426 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); reg 2427 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); reg 2428 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); reg 2429 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); reg 2430 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); reg 2431 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); reg 2432 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg); reg 2433 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg); reg 2434 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg); reg 2435 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg); reg 2436 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg); reg 2437 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg); reg 2438 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg); reg 2439 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg); reg 2440 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg); reg 2441 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg); reg 2442 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg); reg 2443 drivers/scsi/qla2xxx/qla_dbg.c iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg); reg 2444 drivers/scsi/qla2xxx/qla_dbg.c qla24xx_read_window(reg, 0x6F00, 16, iter_reg); reg 2458 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); reg 2459 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->hccr); reg 2461 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); reg 2462 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->hccr); reg 2464 drivers/scsi/qla2xxx/qla_dbg.c WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); reg 2465 drivers/scsi/qla2xxx/qla_dbg.c RD_REG_DWORD(®->hccr); reg 2467 drivers/scsi/qla2xxx/qla_dbg.c for (cnt = 30000; cnt && (RD_REG_WORD(®->mailbox0)); cnt--) reg 2717 drivers/scsi/qla2xxx/qla_dbg.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 2730 drivers/scsi/qla2xxx/qla_dbg.c mbx_reg = MAILBOX_REG(ha, reg, 0); reg 897 drivers/scsi/qla2xxx/qla_def.h #define ISP_REQ_Q_IN(ha, reg) \ reg 899 drivers/scsi/qla2xxx/qla_def.h &(reg)->u.isp2100.mailbox4 : \ reg 900 drivers/scsi/qla2xxx/qla_def.h &(reg)->u.isp2300.req_q_in) reg 901 drivers/scsi/qla2xxx/qla_def.h #define ISP_REQ_Q_OUT(ha, reg) \ reg 903 drivers/scsi/qla2xxx/qla_def.h &(reg)->u.isp2100.mailbox4 : \ reg 904 drivers/scsi/qla2xxx/qla_def.h &(reg)->u.isp2300.req_q_out) reg 905 drivers/scsi/qla2xxx/qla_def.h #define ISP_RSP_Q_IN(ha, reg) \ reg 907 drivers/scsi/qla2xxx/qla_def.h &(reg)->u.isp2100.mailbox5 : \ reg 908 drivers/scsi/qla2xxx/qla_def.h &(reg)->u.isp2300.rsp_q_in) reg 909 drivers/scsi/qla2xxx/qla_def.h #define ISP_RSP_Q_OUT(ha, reg) \ reg 911 drivers/scsi/qla2xxx/qla_def.h &(reg)->u.isp2100.mailbox5 : \ reg 912 drivers/scsi/qla2xxx/qla_def.h &(reg)->u.isp2300.rsp_q_out) reg 917 drivers/scsi/qla2xxx/qla_def.h #define MAILBOX_REG(ha, reg, num) \ reg 920 drivers/scsi/qla2xxx/qla_def.h &(reg)->u.isp2100.mailbox0 + (num) : \ reg 921 drivers/scsi/qla2xxx/qla_def.h &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ reg 922 drivers/scsi/qla2xxx/qla_def.h &(reg)->u.isp2300.mailbox0 + (num)) reg 923 drivers/scsi/qla2xxx/qla_def.h #define RD_MAILBOX_REG(ha, reg, num) \ reg 924 drivers/scsi/qla2xxx/qla_def.h RD_REG_WORD(MAILBOX_REG(ha, reg, num)) reg 925 drivers/scsi/qla2xxx/qla_def.h #define WRT_MAILBOX_REG(ha, reg, num, data) \ reg 926 drivers/scsi/qla2xxx/qla_def.h WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) reg 928 drivers/scsi/qla2xxx/qla_def.h #define FB_CMD_REG(ha, reg) \ reg 930 drivers/scsi/qla2xxx/qla_def.h &(reg)->fb_cmd_2100 : \ reg 931 drivers/scsi/qla2xxx/qla_def.h &(reg)->u.isp2300.fb_cmd) reg 932 drivers/scsi/qla2xxx/qla_def.h #define RD_FB_CMD_REG(ha, reg) \ reg 933 drivers/scsi/qla2xxx/qla_def.h RD_REG_WORD(FB_CMD_REG(ha, reg)) reg 934 drivers/scsi/qla2xxx/qla_def.h #define WRT_FB_CMD_REG(ha, reg, data) \ reg 935 drivers/scsi/qla2xxx/qla_def.h WRT_REG_WORD(FB_CMD_REG(ha, reg), data) reg 2179 drivers/scsi/qla2xxx/qla_init.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 2216 drivers/scsi/qla2xxx/qla_init.c if (RD_REG_DWORD(®->mailbox12) & BIT_0) { reg 2325 drivers/scsi/qla2xxx/qla_init.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 2338 drivers/scsi/qla2xxx/qla_init.c ha->pci_attr = RD_REG_WORD(®->ctrl_status); reg 2357 drivers/scsi/qla2xxx/qla_init.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 2380 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); reg 2382 drivers/scsi/qla2xxx/qla_init.c if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) reg 2389 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->ctrl_status, 0x20); reg 2390 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->ctrl_status); reg 2393 drivers/scsi/qla2xxx/qla_init.c ha->fb_rev = RD_FB_CMD_REG(ha, reg); reg 2399 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->ctrl_status, 0x0); reg 2400 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->ctrl_status); reg 2403 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); reg 2405 drivers/scsi/qla2xxx/qla_init.c if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0) reg 2420 drivers/scsi/qla2xxx/qla_init.c ha->pci_attr = RD_REG_WORD(®->ctrl_status); reg 2438 drivers/scsi/qla2xxx/qla_init.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 2464 drivers/scsi/qla2xxx/qla_init.c ha->pci_attr = RD_REG_DWORD(®->ctrl_status); reg 2548 drivers/scsi/qla2xxx/qla_init.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 2568 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); reg 2571 drivers/scsi/qla2xxx/qla_init.c if ((RD_REG_WORD(®->hccr) & reg 2577 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->hccr); /* PCI Posting. */ reg 2582 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->ctrl_status, 0x20); reg 2583 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ reg 2586 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->fpm_diag_config, 0x100); reg 2587 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->fpm_diag_config); /* PCI Posting. */ reg 2591 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->fpm_diag_config, 0x0); reg 2592 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->fpm_diag_config); /* PCI Posting. */ reg 2596 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->ctrl_status, 0x10); reg 2597 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ reg 2601 drivers/scsi/qla2xxx/qla_init.c WRT_FB_CMD_REG(ha, reg, 0xa000); reg 2602 drivers/scsi/qla2xxx/qla_init.c RD_FB_CMD_REG(ha, reg); /* PCI Posting. */ reg 2604 drivers/scsi/qla2xxx/qla_init.c WRT_FB_CMD_REG(ha, reg, 0x00fc); reg 2608 drivers/scsi/qla2xxx/qla_init.c if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0) reg 2615 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->ctrl_status, 0); reg 2616 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ reg 2619 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); reg 2620 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->hccr); /* PCI Posting. */ reg 2623 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); reg 2624 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->hccr); /* PCI Posting. */ reg 2627 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); reg 2628 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->hccr, HCCR_CLR_HOST_INT); reg 2631 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); reg 2642 drivers/scsi/qla2xxx/qla_init.c if ((RD_REG_WORD(®->ctrl_status) & reg 2651 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); reg 2653 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->semaphore, 0); reg 2656 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); reg 2657 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->hccr); /* PCI Posting. */ reg 2661 drivers/scsi/qla2xxx/qla_init.c if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY) reg 2675 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->hccr, HCCR_DISABLE_PARITY_PAUSE); reg 2676 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->hccr); /* PCI Posting. */ reg 2712 drivers/scsi/qla2xxx/qla_init.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 2721 drivers/scsi/qla2xxx/qla_init.c WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); reg 2723 drivers/scsi/qla2xxx/qla_init.c if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) reg 2729 drivers/scsi/qla2xxx/qla_init.c if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)) reg 2734 drivers/scsi/qla2xxx/qla_init.c RD_REG_DWORD(®->hccr), reg 2735 drivers/scsi/qla2xxx/qla_init.c RD_REG_DWORD(®->ctrl_status), reg 2736 drivers/scsi/qla2xxx/qla_init.c (RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)); reg 2738 drivers/scsi/qla2xxx/qla_init.c WRT_REG_DWORD(®->ctrl_status, reg 2745 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->mailbox0); reg 2746 drivers/scsi/qla2xxx/qla_init.c for (cnt = 10000; RD_REG_WORD(®->mailbox0) != 0 && reg 2760 drivers/scsi/qla2xxx/qla_init.c RD_REG_DWORD(®->hccr), reg 2761 drivers/scsi/qla2xxx/qla_init.c RD_REG_DWORD(®->mailbox0)); reg 2764 drivers/scsi/qla2xxx/qla_init.c RD_REG_DWORD(®->ctrl_status); reg 2767 drivers/scsi/qla2xxx/qla_init.c if ((RD_REG_DWORD(®->ctrl_status) & reg 2773 drivers/scsi/qla2xxx/qla_init.c if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_ISP_SOFT_RESET)) reg 2778 drivers/scsi/qla2xxx/qla_init.c RD_REG_DWORD(®->hccr), reg 2779 drivers/scsi/qla2xxx/qla_init.c RD_REG_DWORD(®->ctrl_status)); reg 2798 drivers/scsi/qla2xxx/qla_init.c WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); reg 2799 drivers/scsi/qla2xxx/qla_init.c RD_REG_DWORD(®->hccr); reg 2801 drivers/scsi/qla2xxx/qla_init.c WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); reg 2802 drivers/scsi/qla2xxx/qla_init.c RD_REG_DWORD(®->hccr); reg 2804 drivers/scsi/qla2xxx/qla_init.c WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); reg 2805 drivers/scsi/qla2xxx/qla_init.c RD_REG_DWORD(®->hccr); reg 2807 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->mailbox0); reg 2808 drivers/scsi/qla2xxx/qla_init.c for (cnt = 60; RD_REG_WORD(®->mailbox0) != 0 && reg 2821 drivers/scsi/qla2xxx/qla_init.c RD_REG_DWORD(®->hccr), reg 2822 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->mailbox0)); reg 2839 drivers/scsi/qla2xxx/qla_init.c struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; reg 2841 drivers/scsi/qla2xxx/qla_init.c WRT_REG_DWORD(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); reg 2842 drivers/scsi/qla2xxx/qla_init.c *data = RD_REG_DWORD(®->iobase_window + RISC_REGISTER_WINDOW_OFFET); reg 2849 drivers/scsi/qla2xxx/qla_init.c struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; reg 2851 drivers/scsi/qla2xxx/qla_init.c WRT_REG_DWORD(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); reg 2852 drivers/scsi/qla2xxx/qla_init.c WRT_REG_DWORD(®->iobase_window + RISC_REGISTER_WINDOW_OFFET, data); reg 2954 drivers/scsi/qla2xxx/qla_init.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 2965 drivers/scsi/qla2xxx/qla_init.c ®->flash_address); reg 2970 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); reg 2977 drivers/scsi/qla2xxx/qla_init.c data = qla2x00_debounce_register(®->ctrl_status); reg 2980 drivers/scsi/qla2xxx/qla_init.c data = RD_REG_WORD(®->ctrl_status); reg 2991 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); reg 2992 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); reg 2996 drivers/scsi/qla2xxx/qla_init.c data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0)); reg 2999 drivers/scsi/qla2xxx/qla_init.c data = RD_MAILBOX_REG(ha, reg, 0); reg 3011 drivers/scsi/qla2xxx/qla_init.c mb[1] = RD_MAILBOX_REG(ha, reg, 1); reg 3012 drivers/scsi/qla2xxx/qla_init.c mb[2] = RD_MAILBOX_REG(ha, reg, 2); reg 3013 drivers/scsi/qla2xxx/qla_init.c mb[3] = RD_MAILBOX_REG(ha, reg, 3); reg 3014 drivers/scsi/qla2xxx/qla_init.c mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4)); reg 3036 drivers/scsi/qla2xxx/qla_init.c RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) { reg 3592 drivers/scsi/qla2xxx/qla_init.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 3608 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x0)); reg 3609 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->hccr); reg 3703 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x1); reg 3706 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x7); reg 3707 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->hccr); reg 3932 drivers/scsi/qla2xxx/qla_init.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 3944 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0); reg 3945 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0); reg 3946 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0); reg 3947 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0); reg 3948 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */ reg 3955 drivers/scsi/qla2xxx/qla_init.c device_reg_t *reg = ISP_QUE_REG(ha, 0); reg 4010 drivers/scsi/qla2xxx/qla_init.c WRT_REG_DWORD(®->isp25mq.req_q_in, 0); reg 4011 drivers/scsi/qla2xxx/qla_init.c WRT_REG_DWORD(®->isp25mq.req_q_out, 0); reg 4012 drivers/scsi/qla2xxx/qla_init.c WRT_REG_DWORD(®->isp25mq.rsp_q_in, 0); reg 4013 drivers/scsi/qla2xxx/qla_init.c WRT_REG_DWORD(®->isp25mq.rsp_q_out, 0); reg 4015 drivers/scsi/qla2xxx/qla_init.c WRT_REG_DWORD(®->isp24.req_q_in, 0); reg 4016 drivers/scsi/qla2xxx/qla_init.c WRT_REG_DWORD(®->isp24.req_q_out, 0); reg 4017 drivers/scsi/qla2xxx/qla_init.c WRT_REG_DWORD(®->isp24.rsp_q_in, 0); reg 4018 drivers/scsi/qla2xxx/qla_init.c WRT_REG_DWORD(®->isp24.rsp_q_out, 0); reg 4495 drivers/scsi/qla2xxx/qla_init.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 4503 drivers/scsi/qla2xxx/qla_init.c if ((RD_REG_WORD(®->ctrl_status) >> 14) == 1) reg 7011 drivers/scsi/qla2xxx/qla_init.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 7017 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); reg 7018 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->hccr); /* PCI Posting. */ reg 7019 drivers/scsi/qla2xxx/qla_init.c WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); reg 7020 drivers/scsi/qla2xxx/qla_init.c RD_REG_WORD(®->hccr); /* PCI Posting. */ reg 7031 drivers/scsi/qla2xxx/qla_init.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 7041 drivers/scsi/qla2xxx/qla_init.c WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); reg 7042 drivers/scsi/qla2xxx/qla_init.c RD_REG_DWORD(®->hccr); reg 7043 drivers/scsi/qla2xxx/qla_init.c WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); reg 7044 drivers/scsi/qla2xxx/qla_init.c RD_REG_DWORD(®->hccr); reg 334 drivers/scsi/qla2xxx/qla_iocb.c struct device_reg_2xxx __iomem *reg; reg 342 drivers/scsi/qla2xxx/qla_iocb.c reg = &ha->iobase->isp; reg 379 drivers/scsi/qla2xxx/qla_iocb.c cnt = RD_REG_WORD_RELAXED(ISP_REQ_Q_OUT(ha, reg)); reg 431 drivers/scsi/qla2xxx/qla_iocb.c WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), req->ring_index); reg 432 drivers/scsi/qla2xxx/qla_iocb.c RD_REG_WORD_RELAXED(ISP_REQ_Q_IN(ha, reg)); /* PCI Posting. */ reg 460 drivers/scsi/qla2xxx/qla_iocb.c device_reg_t *reg = ISP_QUE_REG(ha, req->id); reg 480 drivers/scsi/qla2xxx/qla_iocb.c WRT_REG_DWORD(®->ispfx00.req_q_in, req->ring_index); reg 481 drivers/scsi/qla2xxx/qla_iocb.c RD_REG_DWORD_RELAXED(®->ispfx00.req_q_in); reg 484 drivers/scsi/qla2xxx/qla_iocb.c WRT_REG_DWORD(®->isp24.req_q_in, req->ring_index); reg 485 drivers/scsi/qla2xxx/qla_iocb.c RD_REG_DWORD_RELAXED(®->isp24.req_q_in); reg 487 drivers/scsi/qla2xxx/qla_iocb.c WRT_REG_WORD(ISP_REQ_Q_IN(ha, ®->isp), reg 489 drivers/scsi/qla2xxx/qla_iocb.c RD_REG_WORD_RELAXED(ISP_REQ_Q_IN(ha, ®->isp)); reg 2249 drivers/scsi/qla2xxx/qla_iocb.c device_reg_t *reg = ISP_QUE_REG(ha, req->id); reg 2269 drivers/scsi/qla2xxx/qla_iocb.c cnt = RD_REG_DWORD(®->isp25mq.req_q_out); reg 2271 drivers/scsi/qla2xxx/qla_iocb.c cnt = RD_REG_DWORD(®->isp82.req_q_out); reg 2273 drivers/scsi/qla2xxx/qla_iocb.c cnt = RD_REG_DWORD(®->isp24.req_q_out); reg 2275 drivers/scsi/qla2xxx/qla_iocb.c cnt = RD_REG_DWORD(®->ispfx00.req_q_out); reg 2278 drivers/scsi/qla2xxx/qla_iocb.c ISP_REQ_Q_OUT(ha, ®->isp)); reg 3087 drivers/scsi/qla2xxx/qla_iocb.c struct device_reg_82xx __iomem *reg; reg 3098 drivers/scsi/qla2xxx/qla_iocb.c reg = &ha->iobase->isp82; reg 3184 drivers/scsi/qla2xxx/qla_iocb.c ®->req_q_out[0]); reg 3293 drivers/scsi/qla2xxx/qla_iocb.c ®->req_q_out[0]); reg 48 drivers/scsi/qla2xxx/qla_isr.c struct device_reg_2xxx __iomem *reg; reg 64 drivers/scsi/qla2xxx/qla_isr.c reg = &ha->iobase->isp; reg 70 drivers/scsi/qla2xxx/qla_isr.c hccr = RD_REG_WORD(®->hccr); reg 82 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); reg 83 drivers/scsi/qla2xxx/qla_isr.c RD_REG_WORD(®->hccr); reg 88 drivers/scsi/qla2xxx/qla_isr.c } else if ((RD_REG_WORD(®->istatus) & ISR_RISC_INT) == 0) reg 91 drivers/scsi/qla2xxx/qla_isr.c if (RD_REG_WORD(®->semaphore) & BIT_0) { reg 92 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); reg 93 drivers/scsi/qla2xxx/qla_isr.c RD_REG_WORD(®->hccr); reg 96 drivers/scsi/qla2xxx/qla_isr.c mb[0] = RD_MAILBOX_REG(ha, reg, 0); reg 101 drivers/scsi/qla2xxx/qla_isr.c mb[1] = RD_MAILBOX_REG(ha, reg, 1); reg 102 drivers/scsi/qla2xxx/qla_isr.c mb[2] = RD_MAILBOX_REG(ha, reg, 2); reg 103 drivers/scsi/qla2xxx/qla_isr.c mb[3] = RD_MAILBOX_REG(ha, reg, 3); reg 112 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_WORD(®->semaphore, 0); reg 113 drivers/scsi/qla2xxx/qla_isr.c RD_REG_WORD(®->semaphore); reg 117 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); reg 118 drivers/scsi/qla2xxx/qla_isr.c RD_REG_WORD(®->hccr); reg 128 drivers/scsi/qla2xxx/qla_isr.c qla2x00_check_reg32_for_disconnect(scsi_qla_host_t *vha, uint32_t reg) reg 131 drivers/scsi/qla2xxx/qla_isr.c if (reg == 0xffffffff && !pci_channel_offline(vha->hw->pdev)) { reg 148 drivers/scsi/qla2xxx/qla_isr.c qla2x00_check_reg16_for_disconnect(scsi_qla_host_t *vha, uint16_t reg) reg 150 drivers/scsi/qla2xxx/qla_isr.c return qla2x00_check_reg32_for_disconnect(vha, 0xffff0000 | reg); reg 166 drivers/scsi/qla2xxx/qla_isr.c struct device_reg_2xxx __iomem *reg; reg 184 drivers/scsi/qla2xxx/qla_isr.c reg = &ha->iobase->isp; reg 190 drivers/scsi/qla2xxx/qla_isr.c stat = RD_REG_DWORD(®->u.isp2300.host_status); reg 197 drivers/scsi/qla2xxx/qla_isr.c hccr = RD_REG_WORD(®->hccr); reg 213 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_WORD(®->hccr, HCCR_RESET_RISC); reg 214 drivers/scsi/qla2xxx/qla_isr.c RD_REG_WORD(®->hccr); reg 231 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_WORD(®->semaphore, 0); reg 235 drivers/scsi/qla2xxx/qla_isr.c mb[1] = RD_MAILBOX_REG(ha, reg, 1); reg 236 drivers/scsi/qla2xxx/qla_isr.c mb[2] = RD_MAILBOX_REG(ha, reg, 2); reg 237 drivers/scsi/qla2xxx/qla_isr.c mb[3] = RD_MAILBOX_REG(ha, reg, 3); reg 251 drivers/scsi/qla2xxx/qla_isr.c mb[2] = RD_MAILBOX_REG(ha, reg, 2); reg 259 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); reg 260 drivers/scsi/qla2xxx/qla_isr.c RD_REG_WORD_RELAXED(®->hccr); reg 280 drivers/scsi/qla2xxx/qla_isr.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 294 drivers/scsi/qla2xxx/qla_isr.c wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1); reg 298 drivers/scsi/qla2xxx/qla_isr.c wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8); reg 635 drivers/scsi/qla2xxx/qla_isr.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 676 drivers/scsi/qla2xxx/qla_isr.c handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6); reg 684 drivers/scsi/qla2xxx/qla_isr.c handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6); reg 685 drivers/scsi/qla2xxx/qla_isr.c handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7); reg 692 drivers/scsi/qla2xxx/qla_isr.c ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) | reg 693 drivers/scsi/qla2xxx/qla_isr.c RD_MAILBOX_REG(ha, reg, 6)); reg 2045 drivers/scsi/qla2xxx/qla_isr.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 2077 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index); reg 2928 drivers/scsi/qla2xxx/qla_isr.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 2942 drivers/scsi/qla2xxx/qla_isr.c wptr = (uint16_t __iomem *)®->mailbox1; reg 3103 drivers/scsi/qla2xxx/qla_isr.c struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; reg 3105 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_DWORD(®->rsp_q_out[0], rsp->ring_index); reg 3117 drivers/scsi/qla2xxx/qla_isr.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 3124 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_DWORD(®->iobase_addr, 0x7C00); reg 3125 drivers/scsi/qla2xxx/qla_isr.c RD_REG_DWORD(®->iobase_addr); reg 3126 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_DWORD(®->iobase_window, 0x0001); reg 3127 drivers/scsi/qla2xxx/qla_isr.c for (cnt = 10000; (RD_REG_DWORD(®->iobase_window) & BIT_0) == 0 && reg 3130 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_DWORD(®->iobase_window, 0x0001); reg 3139 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_DWORD(®->iobase_window, 0x0003); reg 3140 drivers/scsi/qla2xxx/qla_isr.c for (cnt = 100; (RD_REG_DWORD(®->iobase_window) & BIT_0) == 0 && reg 3143 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_DWORD(®->iobase_window, 0x0003); reg 3152 drivers/scsi/qla2xxx/qla_isr.c if (RD_REG_DWORD(®->iobase_c8) & BIT_3) reg 3157 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_DWORD(®->iobase_window, 0x0000); reg 3158 drivers/scsi/qla2xxx/qla_isr.c RD_REG_DWORD(®->iobase_window); reg 3175 drivers/scsi/qla2xxx/qla_isr.c struct device_reg_24xx __iomem *reg; reg 3193 drivers/scsi/qla2xxx/qla_isr.c reg = &ha->iobase->isp24; reg 3202 drivers/scsi/qla2xxx/qla_isr.c stat = RD_REG_DWORD(®->host_status); reg 3209 drivers/scsi/qla2xxx/qla_isr.c hccr = RD_REG_DWORD(®->hccr); reg 3234 drivers/scsi/qla2xxx/qla_isr.c mb[1] = RD_REG_WORD(®->mailbox1); reg 3235 drivers/scsi/qla2xxx/qla_isr.c mb[2] = RD_REG_WORD(®->mailbox2); reg 3236 drivers/scsi/qla2xxx/qla_isr.c mb[3] = RD_REG_WORD(®->mailbox3); reg 3256 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); reg 3257 drivers/scsi/qla2xxx/qla_isr.c RD_REG_DWORD_RELAXED(®->hccr); reg 3278 drivers/scsi/qla2xxx/qla_isr.c struct device_reg_24xx __iomem *reg; reg 3289 drivers/scsi/qla2xxx/qla_isr.c reg = &ha->iobase->isp24; reg 3296 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); reg 3297 drivers/scsi/qla2xxx/qla_isr.c RD_REG_DWORD_RELAXED(®->hccr); reg 3310 drivers/scsi/qla2xxx/qla_isr.c struct device_reg_24xx __iomem *reg; reg 3325 drivers/scsi/qla2xxx/qla_isr.c reg = &ha->iobase->isp24; reg 3331 drivers/scsi/qla2xxx/qla_isr.c stat = RD_REG_DWORD(®->host_status); reg 3338 drivers/scsi/qla2xxx/qla_isr.c hccr = RD_REG_DWORD(®->hccr); reg 3363 drivers/scsi/qla2xxx/qla_isr.c mb[1] = RD_REG_WORD(®->mailbox1); reg 3364 drivers/scsi/qla2xxx/qla_isr.c mb[2] = RD_REG_WORD(®->mailbox2); reg 3365 drivers/scsi/qla2xxx/qla_isr.c mb[3] = RD_REG_WORD(®->mailbox3); reg 3385 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); reg 3404 drivers/scsi/qla2xxx/qla_isr.c struct device_reg_24xx __iomem *reg; reg 3417 drivers/scsi/qla2xxx/qla_isr.c reg = &ha->iobase->isp24; reg 3419 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); reg 3599 drivers/scsi/qla2xxx/qla_isr.c device_reg_t *reg = ha->iobase; reg 3680 drivers/scsi/qla2xxx/qla_isr.c WRT_REG_WORD(®->isp.semaphore, 0); reg 104 drivers/scsi/qla2xxx/qla_mbx.c device_reg_t *reg; reg 141 drivers/scsi/qla2xxx/qla_mbx.c reg = ha->iobase; reg 212 drivers/scsi/qla2xxx/qla_mbx.c optr = (uint16_t __iomem *)®->isp82.mailbox_in[0]; reg 214 drivers/scsi/qla2xxx/qla_mbx.c optr = (uint16_t __iomem *)®->isp24.mailbox0; reg 216 drivers/scsi/qla2xxx/qla_mbx.c optr = (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 0); reg 227 drivers/scsi/qla2xxx/qla_mbx.c (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 8); reg 257 drivers/scsi/qla2xxx/qla_mbx.c WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); reg 259 drivers/scsi/qla2xxx/qla_mbx.c WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); reg 261 drivers/scsi/qla2xxx/qla_mbx.c WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); reg 304 drivers/scsi/qla2xxx/qla_mbx.c if (RD_REG_DWORD(®->isp82.hint) & reg 315 drivers/scsi/qla2xxx/qla_mbx.c WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); reg 317 drivers/scsi/qla2xxx/qla_mbx.c WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); reg 319 drivers/scsi/qla2xxx/qla_mbx.c WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); reg 417 drivers/scsi/qla2xxx/qla_mbx.c mb[0] = RD_REG_WORD(®->isp24.mailbox0); reg 418 drivers/scsi/qla2xxx/qla_mbx.c mb[1] = RD_REG_WORD(®->isp24.mailbox1); reg 419 drivers/scsi/qla2xxx/qla_mbx.c mb[2] = RD_REG_WORD(®->isp24.mailbox2); reg 420 drivers/scsi/qla2xxx/qla_mbx.c mb[3] = RD_REG_WORD(®->isp24.mailbox3); reg 421 drivers/scsi/qla2xxx/qla_mbx.c mb[7] = RD_REG_WORD(®->isp24.mailbox7); reg 422 drivers/scsi/qla2xxx/qla_mbx.c ictrl = RD_REG_DWORD(®->isp24.ictrl); reg 423 drivers/scsi/qla2xxx/qla_mbx.c host_status = RD_REG_DWORD(®->isp24.host_status); reg 424 drivers/scsi/qla2xxx/qla_mbx.c hccr = RD_REG_DWORD(®->isp24.hccr); reg 433 drivers/scsi/qla2xxx/qla_mbx.c mb[0] = RD_MAILBOX_REG(ha, ®->isp, 0); reg 434 drivers/scsi/qla2xxx/qla_mbx.c ictrl = RD_REG_WORD(®->isp.ictrl); reg 577 drivers/scsi/qla2xxx/qla_mbx.c RD_REG_DWORD(®->isp24.host_status), reg 578 drivers/scsi/qla2xxx/qla_mbx.c RD_REG_DWORD(®->isp24.ictrl), reg 579 drivers/scsi/qla2xxx/qla_mbx.c RD_REG_DWORD(®->isp24.istatus)); reg 583 drivers/scsi/qla2xxx/qla_mbx.c RD_REG_WORD(®->isp.ctrl_status), reg 584 drivers/scsi/qla2xxx/qla_mbx.c RD_REG_WORD(®->isp.ictrl), reg 585 drivers/scsi/qla2xxx/qla_mbx.c RD_REG_WORD(®->isp.istatus)); reg 5267 drivers/scsi/qla2xxx/qla_mbx.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 5277 drivers/scsi/qla2xxx/qla_mbx.c WRT_REG_WORD(®->mailbox0, MBC_WRITE_MPI_REGISTER); reg 5278 drivers/scsi/qla2xxx/qla_mbx.c WRT_REG_WORD(®->mailbox1, mb[0]); reg 5279 drivers/scsi/qla2xxx/qla_mbx.c WRT_REG_WORD(®->mailbox2, mb[1]); reg 5280 drivers/scsi/qla2xxx/qla_mbx.c WRT_REG_WORD(®->mailbox3, mb[2]); reg 5281 drivers/scsi/qla2xxx/qla_mbx.c WRT_REG_WORD(®->mailbox4, mb[3]); reg 5283 drivers/scsi/qla2xxx/qla_mbx.c WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); reg 5288 drivers/scsi/qla2xxx/qla_mbx.c stat = RD_REG_DWORD(®->host_status); reg 5296 drivers/scsi/qla2xxx/qla_mbx.c mb0 = RD_REG_WORD(®->mailbox0); reg 5297 drivers/scsi/qla2xxx/qla_mbx.c WRT_REG_DWORD(®->hccr, reg 5299 drivers/scsi/qla2xxx/qla_mbx.c RD_REG_DWORD(®->hccr); reg 5920 drivers/scsi/qla2xxx/qla_mbx.c qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data) reg 5934 drivers/scsi/qla2xxx/qla_mbx.c mcp->mb[1] = LSW(reg); reg 5935 drivers/scsi/qla2xxx/qla_mbx.c mcp->mb[2] = MSW(reg); reg 5994 drivers/scsi/qla2xxx/qla_mbx.c qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data) reg 6009 drivers/scsi/qla2xxx/qla_mbx.c mcp->mb[1] = LSW(reg); reg 6010 drivers/scsi/qla2xxx/qla_mbx.c mcp->mb[2] = MSW(reg); reg 691 drivers/scsi/qla2xxx/qla_mid.c device_reg_t *reg; reg 759 drivers/scsi/qla2xxx/qla_mid.c reg = ISP_QUE_REG(ha, que_id); reg 760 drivers/scsi/qla2xxx/qla_mid.c req->req_q_in = ®->isp25mq.req_q_in; reg 761 drivers/scsi/qla2xxx/qla_mid.c req->req_q_out = ®->isp25mq.req_q_out; reg 821 drivers/scsi/qla2xxx/qla_mid.c device_reg_t *reg; reg 874 drivers/scsi/qla2xxx/qla_mid.c reg = ISP_QUE_REG(ha, que_id); reg 875 drivers/scsi/qla2xxx/qla_mid.c rsp->rsp_q_in = ®->isp25mq.rsp_q_in; reg 876 drivers/scsi/qla2xxx/qla_mid.c rsp->rsp_q_out = ®->isp25mq.rsp_q_out; reg 44 drivers/scsi/qla2xxx/qla_mr.c device_reg_t *reg; reg 69 drivers/scsi/qla2xxx/qla_mr.c reg = ha->iobase; reg 113 drivers/scsi/qla2xxx/qla_mr.c optr = (uint32_t __iomem *)®->ispfx00.mailbox0; reg 678 drivers/scsi/qla2xxx/qla_mr.c struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00; reg 680 drivers/scsi/qla2xxx/qla_mr.c WRT_REG_DWORD(®->req_q_in, 0); reg 681 drivers/scsi/qla2xxx/qla_mr.c WRT_REG_DWORD(®->req_q_out, 0); reg 683 drivers/scsi/qla2xxx/qla_mr.c WRT_REG_DWORD(®->rsp_q_in, 0); reg 684 drivers/scsi/qla2xxx/qla_mr.c WRT_REG_DWORD(®->rsp_q_out, 0); reg 687 drivers/scsi/qla2xxx/qla_mr.c RD_REG_DWORD(®->rsp_q_out); reg 907 drivers/scsi/qla2xxx/qla_mr.c struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00; reg 916 drivers/scsi/qla2xxx/qla_mr.c pseudo_aen = RD_REG_DWORD(®->pseudoaen); reg 918 drivers/scsi/qla2xxx/qla_mr.c aenmbx7 = RD_REG_DWORD(®->initval7); reg 929 drivers/scsi/qla2xxx/qla_mr.c aenmbx = RD_REG_DWORD(®->aenmailbox0); reg 948 drivers/scsi/qla2xxx/qla_mr.c aenmbx7 = RD_REG_DWORD(®->aenmailbox7); reg 951 drivers/scsi/qla2xxx/qla_mr.c ha->req_que_off = RD_REG_DWORD(®->aenmailbox1); reg 952 drivers/scsi/qla2xxx/qla_mr.c ha->rsp_que_off = RD_REG_DWORD(®->aenmailbox3); reg 953 drivers/scsi/qla2xxx/qla_mr.c ha->req_que_len = RD_REG_DWORD(®->aenmailbox5); reg 954 drivers/scsi/qla2xxx/qla_mr.c ha->rsp_que_len = RD_REG_DWORD(®->aenmailbox6); reg 955 drivers/scsi/qla2xxx/qla_mr.c WRT_REG_DWORD(®->aenmailbox0, 0); reg 956 drivers/scsi/qla2xxx/qla_mr.c RD_REG_DWORD_RELAXED(®->aenmailbox0); reg 986 drivers/scsi/qla2xxx/qla_mr.c aenmbx7 = RD_REG_DWORD(®->initval7); reg 989 drivers/scsi/qla2xxx/qla_mr.c ha->req_que_off = RD_REG_DWORD(®->initval1); reg 990 drivers/scsi/qla2xxx/qla_mr.c ha->rsp_que_off = RD_REG_DWORD(®->initval3); reg 991 drivers/scsi/qla2xxx/qla_mr.c ha->req_que_len = RD_REG_DWORD(®->initval5); reg 992 drivers/scsi/qla2xxx/qla_mr.c ha->rsp_que_len = RD_REG_DWORD(®->initval6); reg 1038 drivers/scsi/qla2xxx/qla_mr.c RD_REG_DWORD(®->aenmailbox7)); reg 1443 drivers/scsi/qla2xxx/qla_mr.c struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00; reg 1448 drivers/scsi/qla2xxx/qla_mr.c aenmbx7 = RD_REG_DWORD(®->aenmailbox7); reg 1451 drivers/scsi/qla2xxx/qla_mr.c ha->req_que_off = RD_REG_DWORD(®->aenmailbox1); reg 1452 drivers/scsi/qla2xxx/qla_mr.c ha->rsp_que_off = RD_REG_DWORD(®->aenmailbox3); reg 1453 drivers/scsi/qla2xxx/qla_mr.c ha->req_que_len = RD_REG_DWORD(®->aenmailbox5); reg 1454 drivers/scsi/qla2xxx/qla_mr.c ha->rsp_que_len = RD_REG_DWORD(®->aenmailbox6); reg 1488 drivers/scsi/qla2xxx/qla_mr.c struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00; reg 1499 drivers/scsi/qla2xxx/qla_mr.c fw_heart_beat = RD_REG_DWORD(®->fwheartbeat); reg 1519 drivers/scsi/qla2xxx/qla_mr.c aenmbx0 = RD_REG_DWORD(®->aenmailbox0); reg 2798 drivers/scsi/qla2xxx/qla_mr.c struct device_reg_fx00 __iomem *reg; reg 2801 drivers/scsi/qla2xxx/qla_mr.c reg = &ha->iobase->ispfx00; reg 2818 drivers/scsi/qla2xxx/qla_mr.c ha->aenmb[1] = RD_REG_DWORD(®->aenmailbox1); reg 2819 drivers/scsi/qla2xxx/qla_mr.c ha->aenmb[2] = RD_REG_DWORD(®->aenmailbox2); reg 2820 drivers/scsi/qla2xxx/qla_mr.c ha->aenmb[3] = RD_REG_DWORD(®->aenmailbox3); reg 2850 drivers/scsi/qla2xxx/qla_mr.c ha->aenmb[1] = RD_REG_WORD(®->aenmailbox1); reg 2851 drivers/scsi/qla2xxx/qla_mr.c ha->aenmb[2] = RD_REG_WORD(®->aenmailbox2); reg 2852 drivers/scsi/qla2xxx/qla_mr.c ha->aenmb[3] = RD_REG_WORD(®->aenmailbox3); reg 2853 drivers/scsi/qla2xxx/qla_mr.c ha->aenmb[4] = RD_REG_WORD(®->aenmailbox4); reg 2854 drivers/scsi/qla2xxx/qla_mr.c ha->aenmb[5] = RD_REG_WORD(®->aenmailbox5); reg 2855 drivers/scsi/qla2xxx/qla_mr.c ha->aenmb[6] = RD_REG_WORD(®->aenmailbox6); reg 2856 drivers/scsi/qla2xxx/qla_mr.c ha->aenmb[7] = RD_REG_WORD(®->aenmailbox7); reg 2878 drivers/scsi/qla2xxx/qla_mr.c struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00; reg 2886 drivers/scsi/qla2xxx/qla_mr.c wptr = (uint32_t __iomem *)®->mailbox17; reg 2908 drivers/scsi/qla2xxx/qla_mr.c struct device_reg_fx00 __iomem *reg; reg 2926 drivers/scsi/qla2xxx/qla_mr.c reg = &ha->iobase->ispfx00; reg 2943 drivers/scsi/qla2xxx/qla_mr.c mb[0] = RD_REG_WORD(®->mailbox16); reg 2949 drivers/scsi/qla2xxx/qla_mr.c ha->aenmb[0] = RD_REG_WORD(®->aenmailbox0); reg 1779 drivers/scsi/qla2xxx/qla_nx.c struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; reg 1793 drivers/scsi/qla2xxx/qla_nx.c WRT_REG_DWORD(®->req_q_out[0], 0); reg 1794 drivers/scsi/qla2xxx/qla_nx.c WRT_REG_DWORD(®->rsp_q_in[0], 0); reg 1795 drivers/scsi/qla2xxx/qla_nx.c WRT_REG_DWORD(®->rsp_q_out[0], 0); reg 2001 drivers/scsi/qla2xxx/qla_nx.c struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; reg 2003 drivers/scsi/qla2xxx/qla_nx.c wptr = (uint16_t __iomem *)®->mailbox_out[1]; reg 2034 drivers/scsi/qla2xxx/qla_nx.c struct device_reg_82xx __iomem *reg; reg 2066 drivers/scsi/qla2xxx/qla_nx.c reg = &ha->iobase->isp82; reg 2072 drivers/scsi/qla2xxx/qla_nx.c if (RD_REG_DWORD(®->host_int)) { reg 2073 drivers/scsi/qla2xxx/qla_nx.c stat = RD_REG_DWORD(®->host_status); reg 2085 drivers/scsi/qla2xxx/qla_nx.c mb[1] = RD_REG_WORD(®->mailbox_out[1]); reg 2086 drivers/scsi/qla2xxx/qla_nx.c mb[2] = RD_REG_WORD(®->mailbox_out[2]); reg 2087 drivers/scsi/qla2xxx/qla_nx.c mb[3] = RD_REG_WORD(®->mailbox_out[3]); reg 2100 drivers/scsi/qla2xxx/qla_nx.c WRT_REG_DWORD(®->host_int, 0); reg 2118 drivers/scsi/qla2xxx/qla_nx.c struct device_reg_82xx __iomem *reg; reg 2133 drivers/scsi/qla2xxx/qla_nx.c reg = &ha->iobase->isp82; reg 2138 drivers/scsi/qla2xxx/qla_nx.c host_int = RD_REG_DWORD(®->host_int); reg 2142 drivers/scsi/qla2xxx/qla_nx.c stat = RD_REG_DWORD(®->host_status); reg 2154 drivers/scsi/qla2xxx/qla_nx.c mb[1] = RD_REG_WORD(®->mailbox_out[1]); reg 2155 drivers/scsi/qla2xxx/qla_nx.c mb[2] = RD_REG_WORD(®->mailbox_out[2]); reg 2156 drivers/scsi/qla2xxx/qla_nx.c mb[3] = RD_REG_WORD(®->mailbox_out[3]); reg 2169 drivers/scsi/qla2xxx/qla_nx.c WRT_REG_DWORD(®->host_int, 0); reg 2184 drivers/scsi/qla2xxx/qla_nx.c struct device_reg_82xx __iomem *reg; reg 2196 drivers/scsi/qla2xxx/qla_nx.c reg = &ha->iobase->isp82; reg 2199 drivers/scsi/qla2xxx/qla_nx.c host_int = RD_REG_DWORD(®->host_int); reg 2203 drivers/scsi/qla2xxx/qla_nx.c WRT_REG_DWORD(®->host_int, 0); reg 2215 drivers/scsi/qla2xxx/qla_nx.c struct device_reg_82xx __iomem *reg; reg 2230 drivers/scsi/qla2xxx/qla_nx.c reg = &ha->iobase->isp82; reg 2234 drivers/scsi/qla2xxx/qla_nx.c host_int = RD_REG_DWORD(®->host_int); reg 2238 drivers/scsi/qla2xxx/qla_nx.c stat = RD_REG_DWORD(®->host_status); reg 2249 drivers/scsi/qla2xxx/qla_nx.c mb[1] = RD_REG_WORD(®->mailbox_out[1]); reg 2250 drivers/scsi/qla2xxx/qla_nx.c mb[2] = RD_REG_WORD(®->mailbox_out[2]); reg 2251 drivers/scsi/qla2xxx/qla_nx.c mb[3] = RD_REG_WORD(®->mailbox_out[3]); reg 2263 drivers/scsi/qla2xxx/qla_nx.c WRT_REG_DWORD(®->host_int, 0); reg 522 drivers/scsi/qla2xxx/qla_nx.h # define QLA82XX_CAM_RAM(reg) (QLA82XX_CAM_RAM_BASE + (reg)) reg 563 drivers/scsi/qla2xxx/qla_nx.h #define QLA82XX_PCIE_REG(reg) (QLA82XX_CRB_PCIE + (reg)) reg 568 drivers/scsi/qla2xxx/qla_nx.h #define QLA82XX_PCIX_PS_REG(reg) (QLA82XX_CRB_PCIX_MD + (reg)) reg 569 drivers/scsi/qla2xxx/qla_nx.h #define QLA82XX_PCIX_PS2_REG(reg) (QLA82XX_CRB_PCIE2 + (reg)) reg 3893 drivers/scsi/qla2xxx/qla_nx2.c struct device_reg_82xx __iomem *reg; reg 3945 drivers/scsi/qla2xxx/qla_nx2.c reg = &ha->iobase->isp82; reg 3949 drivers/scsi/qla2xxx/qla_nx2.c if (RD_REG_DWORD(®->host_int)) { reg 3950 drivers/scsi/qla2xxx/qla_nx2.c stat = RD_REG_DWORD(®->host_status); reg 3964 drivers/scsi/qla2xxx/qla_nx2.c mb[1] = RD_REG_WORD(®->mailbox_out[1]); reg 3965 drivers/scsi/qla2xxx/qla_nx2.c mb[2] = RD_REG_WORD(®->mailbox_out[2]); reg 3966 drivers/scsi/qla2xxx/qla_nx2.c mb[3] = RD_REG_WORD(®->mailbox_out[3]); reg 3979 drivers/scsi/qla2xxx/qla_nx2.c WRT_REG_DWORD(®->host_int, 0); reg 1199 drivers/scsi/qla2xxx/qla_os.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 1205 drivers/scsi/qla2xxx/qla_os.c return ((RD_REG_DWORD(®->host_status)) == reg 1881 drivers/scsi/qla2xxx/qla_os.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 1886 drivers/scsi/qla2xxx/qla_os.c WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); reg 1887 drivers/scsi/qla2xxx/qla_os.c RD_REG_WORD(®->ictrl); reg 1896 drivers/scsi/qla2xxx/qla_os.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 1901 drivers/scsi/qla2xxx/qla_os.c WRT_REG_WORD(®->ictrl, 0); reg 1902 drivers/scsi/qla2xxx/qla_os.c RD_REG_WORD(®->ictrl); reg 1910 drivers/scsi/qla2xxx/qla_os.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 1914 drivers/scsi/qla2xxx/qla_os.c WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); reg 1915 drivers/scsi/qla2xxx/qla_os.c RD_REG_DWORD(®->ictrl); reg 1923 drivers/scsi/qla2xxx/qla_os.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 1929 drivers/scsi/qla2xxx/qla_os.c WRT_REG_DWORD(®->ictrl, 0); reg 1930 drivers/scsi/qla2xxx/qla_os.c RD_REG_DWORD(®->ictrl); reg 6958 drivers/scsi/qla2xxx/qla_os.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 6966 drivers/scsi/qla2xxx/qla_os.c stat = RD_REG_DWORD(®->hccr); reg 6970 drivers/scsi/qla2xxx/qla_os.c stat = RD_REG_DWORD(®->u.isp2300.host_status); reg 26 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 29 drivers/scsi/qla2xxx/qla_sup.c data = RD_REG_WORD(®->nvram); reg 32 drivers/scsi/qla2xxx/qla_sup.c data = RD_REG_WORD(®->nvram); reg 36 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); reg 37 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->u.isp2300.host_semaphore); reg 39 drivers/scsi/qla2xxx/qla_sup.c data = RD_REG_WORD(®->u.isp2300.host_semaphore); reg 43 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); reg 44 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->u.isp2300.host_semaphore); reg 46 drivers/scsi/qla2xxx/qla_sup.c data = RD_REG_WORD(®->u.isp2300.host_semaphore); reg 58 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 61 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->u.isp2300.host_semaphore, 0); reg 62 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->u.isp2300.host_semaphore); reg 74 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 76 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); reg 77 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->nvram); /* PCI Posting. */ reg 79 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_CLOCK | reg 81 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->nvram); /* PCI Posting. */ reg 83 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); reg 84 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->nvram); /* PCI Posting. */ reg 107 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 123 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK); reg 124 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->nvram); /* PCI Posting. */ reg 127 drivers/scsi/qla2xxx/qla_sup.c reg_data = RD_REG_WORD(®->nvram); reg 130 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->nvram, NVR_SELECT); reg 131 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->nvram); /* PCI Posting. */ reg 136 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->nvram, NVR_DESELECT); reg 137 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->nvram); /* PCI Posting. */ reg 172 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 174 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->nvram, NVR_DESELECT); reg 175 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->nvram); /* PCI Posting. */ reg 191 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 219 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->nvram, NVR_SELECT); reg 220 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->nvram); /* PCI Posting. */ reg 229 drivers/scsi/qla2xxx/qla_sup.c word = RD_REG_WORD(®->nvram); reg 249 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 278 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->nvram, NVR_SELECT); reg 279 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->nvram); /* PCI Posting. */ reg 282 drivers/scsi/qla2xxx/qla_sup.c word = RD_REG_WORD(®->nvram); reg 309 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 350 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->nvram, NVR_SELECT); reg 351 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->nvram); /* PCI Posting. */ reg 360 drivers/scsi/qla2xxx/qla_sup.c word = RD_REG_WORD(®->nvram); reg 374 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 410 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->nvram, NVR_SELECT); reg 411 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->nvram); /* PCI Posting. */ reg 420 drivers/scsi/qla2xxx/qla_sup.c word = RD_REG_WORD(®->nvram); reg 456 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 459 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG); reg 462 drivers/scsi/qla2xxx/qla_sup.c if (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) { reg 463 drivers/scsi/qla2xxx/qla_sup.c *data = RD_REG_DWORD(®->flash_data); reg 499 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 502 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_DWORD(®->flash_data, data); reg 503 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG); reg 506 drivers/scsi/qla2xxx/qla_sup.c if (!(RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG)) reg 1194 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 1200 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_DWORD(®->ctrl_status, reg 1201 drivers/scsi/qla2xxx/qla_sup.c RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); reg 1202 drivers/scsi/qla2xxx/qla_sup.c RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ reg 1219 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 1243 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_DWORD(®->ctrl_status, reg 1244 drivers/scsi/qla2xxx/qla_sup.c RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); reg 1458 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 1469 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_DWORD(®->ctrl_status, reg 1470 drivers/scsi/qla2xxx/qla_sup.c RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); reg 1471 drivers/scsi/qla2xxx/qla_sup.c RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ reg 1493 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_DWORD(®->ctrl_status, reg 1494 drivers/scsi/qla2xxx/qla_sup.c RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); reg 1495 drivers/scsi/qla2xxx/qla_sup.c RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ reg 1579 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 1591 drivers/scsi/qla2xxx/qla_sup.c gpio_enable = RD_REG_WORD(®->gpioe); reg 1592 drivers/scsi/qla2xxx/qla_sup.c gpio_data = RD_REG_WORD(®->gpiod); reg 1601 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->gpioe, gpio_enable); reg 1602 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->gpioe); reg 1617 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->gpiod, gpio_data); reg 1618 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->gpiod); reg 1631 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 1648 drivers/scsi/qla2xxx/qla_sup.c gpio_enable = RD_REG_WORD(®->gpioe); reg 1649 drivers/scsi/qla2xxx/qla_sup.c gpio_data = RD_REG_WORD(®->gpiod); reg 1657 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->gpioe, gpio_enable); reg 1658 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->gpioe); reg 1666 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->gpiod, gpio_data); reg 1667 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->gpiod); reg 1730 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 1734 drivers/scsi/qla2xxx/qla_sup.c gpio_data = RD_REG_DWORD(®->gpiod); reg 1739 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_DWORD(®->gpiod, gpio_data); reg 1740 drivers/scsi/qla2xxx/qla_sup.c gpio_data = RD_REG_DWORD(®->gpiod); reg 1752 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_DWORD(®->gpiod, gpio_data); reg 1753 drivers/scsi/qla2xxx/qla_sup.c gpio_data = RD_REG_DWORD(®->gpiod); reg 1858 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 1884 drivers/scsi/qla2xxx/qla_sup.c gpio_data = RD_REG_DWORD(®->gpiod); reg 1888 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_DWORD(®->gpiod, gpio_data); reg 1889 drivers/scsi/qla2xxx/qla_sup.c RD_REG_DWORD(®->gpiod); reg 1910 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; reg 1932 drivers/scsi/qla2xxx/qla_sup.c gpio_data = RD_REG_DWORD(®->gpiod); reg 1936 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_DWORD(®->gpiod, gpio_data); reg 1937 drivers/scsi/qla2xxx/qla_sup.c RD_REG_DWORD(®->gpiod); reg 1971 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 1973 drivers/scsi/qla2xxx/qla_sup.c data = RD_REG_WORD(®->ctrl_status); reg 1975 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->ctrl_status, data); reg 1976 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ reg 1987 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 1989 drivers/scsi/qla2xxx/qla_sup.c data = RD_REG_WORD(®->ctrl_status); reg 1991 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->ctrl_status, data); reg 1992 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ reg 2009 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 2011 drivers/scsi/qla2xxx/qla_sup.c bank_select = RD_REG_WORD(®->ctrl_status); reg 2019 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->ctrl_status, bank_select); reg 2020 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ reg 2022 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->flash_address, (uint16_t)addr); reg 2023 drivers/scsi/qla2xxx/qla_sup.c data = RD_REG_WORD(®->flash_data); reg 2031 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->ctrl_status, bank_select); reg 2032 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ reg 2036 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->ctrl_status, bank_select); reg 2037 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ reg 2052 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->flash_address, (uint16_t)addr); reg 2053 drivers/scsi/qla2xxx/qla_sup.c data = qla2x00_debounce_register(®->flash_data); reg 2069 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 2071 drivers/scsi/qla2xxx/qla_sup.c bank_select = RD_REG_WORD(®->ctrl_status); reg 2078 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->ctrl_status, bank_select); reg 2079 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ reg 2081 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->flash_address, (uint16_t)addr); reg 2082 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ reg 2083 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->flash_data, (uint16_t)data); reg 2084 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ reg 2092 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->ctrl_status, bank_select); reg 2093 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ reg 2097 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->ctrl_status, bank_select); reg 2098 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ reg 2106 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->flash_address, (uint16_t)addr); reg 2107 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ reg 2108 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->flash_data, (uint16_t)data); reg 2109 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ reg 2286 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 2292 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->nvram, 0); reg 2293 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->nvram); reg 2296 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->nvram, NVR_SELECT); reg 2297 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->nvram); reg 2313 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 2322 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); reg 2323 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->hccr); reg 2326 drivers/scsi/qla2xxx/qla_sup.c if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) reg 2356 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 2365 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->nvram, 0); reg 2366 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->nvram); /* PCI Posting. */ reg 2369 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->nvram, NVR_SELECT); reg 2370 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->nvram); /* PCI Posting. */ reg 2393 drivers/scsi/qla2xxx/qla_sup.c struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; reg 2402 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); reg 2551 drivers/scsi/qla2xxx/qla_sup.c WRT_REG_WORD(®->nvram, NVR_SELECT); reg 2552 drivers/scsi/qla2xxx/qla_sup.c RD_REG_WORD(®->nvram); reg 11 drivers/scsi/qla2xxx/qla_tmpl.c #define IOBAR(reg) offsetof(typeof(*(reg)), iobase_addr) reg 86 drivers/scsi/qla2xxx/qla_tmpl.c qla27xx_read_reg(__iomem struct device_reg_24xx *reg, reg 89 drivers/scsi/qla2xxx/qla_tmpl.c void __iomem *window = (void __iomem *)reg + offset; reg 95 drivers/scsi/qla2xxx/qla_tmpl.c qla27xx_write_reg(__iomem struct device_reg_24xx *reg, reg 99 drivers/scsi/qla2xxx/qla_tmpl.c void __iomem *window = (void __iomem *)reg + offset; reg 106 drivers/scsi/qla2xxx/qla_tmpl.c qla27xx_read_window(__iomem struct device_reg_24xx *reg, reg 110 drivers/scsi/qla2xxx/qla_tmpl.c void __iomem *window = (void __iomem *)reg + offset; reg 113 drivers/scsi/qla2xxx/qla_tmpl.c qla27xx_write_reg(reg, IOBAR(reg), addr, buf); reg 47 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->mailbox[i])); reg 52 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->flash_address)); reg 55 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->flash_data)); reg 58 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->ctrl_status)); reg 63 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->u1.isp4010.nvram)); reg 67 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->u1.isp4022.intr_mask)); reg 70 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->u1.isp4022.nvram)); reg 73 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->u1.isp4022.semaphore)); reg 77 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->req_q_in)); reg 80 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->rsp_q_out)); reg 85 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->u2.isp4010.ext_hw_conf)); reg 88 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->u2.isp4010.port_ctrl)); reg 91 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->u2.isp4010.port_status)); reg 94 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->u2.isp4010.req_q_out)); reg 97 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->u2.isp4010.gp_out)); reg 100 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->u2.isp4010.gp_in)); reg 103 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->u2.isp4010.port_err_status)); reg 108 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->u2.isp4022.p0.ext_hw_conf)); reg 111 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->u2.isp4022.p0.port_ctrl)); reg 114 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->u2.isp4022.p0.port_status)); reg 117 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->u2.isp4022.p0.gp_out)); reg 120 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->u2.isp4022.p0.gp_in)); reg 123 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->u2.isp4022.p0.port_err_status)); reg 126 drivers/scsi/qla4xxx/ql4_dbg.c &ha->reg->ctrl_status); reg 129 drivers/scsi/qla4xxx/ql4_dbg.c readw(&ha->reg->u2.isp4022.p1.req_q_out)); reg 131 drivers/scsi/qla4xxx/ql4_dbg.c &ha->reg->ctrl_status); reg 607 drivers/scsi/qla4xxx/ql4_def.h struct isp_reg __iomem *reg; /* Base I/O address */ reg 921 drivers/scsi/qla4xxx/ql4_def.h &ha->reg->u1.isp4010.nvram : reg 922 drivers/scsi/qla4xxx/ql4_def.h &ha->reg->u1.isp4022.semaphore); reg 928 drivers/scsi/qla4xxx/ql4_def.h &ha->reg->u1.isp4010.nvram : reg 929 drivers/scsi/qla4xxx/ql4_def.h &ha->reg->u1.isp4022.nvram); reg 935 drivers/scsi/qla4xxx/ql4_def.h &ha->reg->u2.isp4010.ext_hw_conf : reg 936 drivers/scsi/qla4xxx/ql4_def.h &ha->reg->u2.isp4022.p0.ext_hw_conf); reg 942 drivers/scsi/qla4xxx/ql4_def.h &ha->reg->u2.isp4010.port_status : reg 943 drivers/scsi/qla4xxx/ql4_def.h &ha->reg->u2.isp4022.p0.port_status); reg 949 drivers/scsi/qla4xxx/ql4_def.h &ha->reg->u2.isp4010.port_ctrl : reg 950 drivers/scsi/qla4xxx/ql4_def.h &ha->reg->u2.isp4022.p0.port_ctrl); reg 956 drivers/scsi/qla4xxx/ql4_def.h &ha->reg->u2.isp4010.port_err_status : reg 957 drivers/scsi/qla4xxx/ql4_def.h &ha->reg->u2.isp4022.p0.port_err_status); reg 963 drivers/scsi/qla4xxx/ql4_def.h &ha->reg->u2.isp4010.gp_out : reg 964 drivers/scsi/qla4xxx/ql4_def.h &ha->reg->u2.isp4022.p0.gp_out); reg 22 drivers/scsi/qla4xxx/ql4_init.c value = readw(&ha->reg->ctrl_status); reg 129 drivers/scsi/qla4xxx/ql4_init.c writel(0, &ha->reg->req_q_in); reg 130 drivers/scsi/qla4xxx/ql4_init.c writel(0, &ha->reg->rsp_q_out); reg 131 drivers/scsi/qla4xxx/ql4_init.c readl(&ha->reg->rsp_q_out); reg 703 drivers/scsi/qla4xxx/ql4_init.c writel(jiffies, &ha->reg->mailbox[7]); reg 706 drivers/scsi/qla4xxx/ql4_init.c &ha->reg->u1.isp4022.nvram); reg 708 drivers/scsi/qla4xxx/ql4_init.c writel(2, &ha->reg->mailbox[6]); reg 709 drivers/scsi/qla4xxx/ql4_init.c readl(&ha->reg->mailbox[6]); reg 711 drivers/scsi/qla4xxx/ql4_init.c writel(set_rmask(CSR_BOOT_ENABLE), &ha->reg->ctrl_status); reg 712 drivers/scsi/qla4xxx/ql4_init.c readl(&ha->reg->ctrl_status); reg 724 drivers/scsi/qla4xxx/ql4_init.c ctrl_status = readw(&ha->reg->ctrl_status); reg 725 drivers/scsi/qla4xxx/ql4_init.c mbox_status = readw(&ha->reg->mailbox[0]); reg 746 drivers/scsi/qla4xxx/ql4_init.c &ha->reg->ctrl_status); reg 747 drivers/scsi/qla4xxx/ql4_init.c readl(&ha->reg->ctrl_status); reg 817 drivers/scsi/qla4xxx/ql4_init.c mbox_status = readw(&ha->reg->mailbox[0]); reg 829 drivers/scsi/qla4xxx/ql4_init.c &ha->reg->ctrl_status); reg 830 drivers/scsi/qla4xxx/ql4_init.c readl(&ha->reg->ctrl_status); reg 832 drivers/scsi/qla4xxx/ql4_init.c &ha->reg->ctrl_status); reg 833 drivers/scsi/qla4xxx/ql4_init.c readl(&ha->reg->ctrl_status); reg 43 drivers/scsi/qla4xxx/ql4_inline.h &ha->reg->u1.isp4022.intr_mask); reg 44 drivers/scsi/qla4xxx/ql4_inline.h readl(&ha->reg->u1.isp4022.intr_mask); reg 46 drivers/scsi/qla4xxx/ql4_inline.h writel(set_rmask(CSR_SCSI_INTR_ENABLE), &ha->reg->ctrl_status); reg 47 drivers/scsi/qla4xxx/ql4_inline.h readl(&ha->reg->ctrl_status); reg 57 drivers/scsi/qla4xxx/ql4_inline.h &ha->reg->u1.isp4022.intr_mask); reg 58 drivers/scsi/qla4xxx/ql4_inline.h readl(&ha->reg->u1.isp4022.intr_mask); reg 60 drivers/scsi/qla4xxx/ql4_inline.h writel(clr_rmask(CSR_SCSI_INTR_ENABLE), &ha->reg->ctrl_status); reg 61 drivers/scsi/qla4xxx/ql4_inline.h readl(&ha->reg->ctrl_status); reg 247 drivers/scsi/qla4xxx/ql4_iocb.c writel(ha->request_in, &ha->reg->req_q_in); reg 248 drivers/scsi/qla4xxx/ql4_iocb.c readl(&ha->reg->req_q_in); reg 261 drivers/scsi/qla4xxx/ql4_iocb.c writel(ha->response_out, &ha->reg->rsp_q_out); reg 262 drivers/scsi/qla4xxx/ql4_iocb.c readl(&ha->reg->rsp_q_out); reg 672 drivers/scsi/qla4xxx/ql4_isr.c mailbox_out = &ha->reg->mailbox[0]; reg 1086 drivers/scsi/qla4xxx/ql4_isr.c readl(&ha->reg->mailbox[0])); reg 1090 drivers/scsi/qla4xxx/ql4_isr.c &ha->reg->ctrl_status); reg 1091 drivers/scsi/qla4xxx/ql4_isr.c readl(&ha->reg->ctrl_status); reg 1151 drivers/scsi/qla4xxx/ql4_isr.c intr_status = readl(&ha->reg->ctrl_status); reg 1172 drivers/scsi/qla4xxx/ql4_isr.c if ((readl(&ha->reg->ctrl_status) & reg 1175 drivers/scsi/qla4xxx/ql4_isr.c &ha->reg->ctrl_status); reg 1176 drivers/scsi/qla4xxx/ql4_isr.c readl(&ha->reg->ctrl_status); reg 1180 drivers/scsi/qla4xxx/ql4_isr.c &ha->reg->ctrl_status); reg 1181 drivers/scsi/qla4xxx/ql4_isr.c readl(&ha->reg->ctrl_status); reg 1193 drivers/scsi/qla4xxx/ql4_isr.c &ha->reg->ctrl_status); reg 1194 drivers/scsi/qla4xxx/ql4_isr.c readl(&ha->reg->ctrl_status); reg 22 drivers/scsi/qla4xxx/ql4_mbx.c writel(mbx_cmd[i], &ha->reg->mailbox[i]); reg 25 drivers/scsi/qla4xxx/ql4_mbx.c writel(mbx_cmd[0], &ha->reg->mailbox[0]); reg 26 drivers/scsi/qla4xxx/ql4_mbx.c readl(&ha->reg->mailbox[0]); reg 27 drivers/scsi/qla4xxx/ql4_mbx.c writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status); reg 28 drivers/scsi/qla4xxx/ql4_mbx.c readl(&ha->reg->ctrl_status); reg 35 drivers/scsi/qla4xxx/ql4_mbx.c intr_status = readl(&ha->reg->ctrl_status); reg 557 drivers/scsi/qla4xxx/ql4_nx.h # define QLA82XX_CAM_RAM(reg) (QLA82XX_CAM_RAM_BASE + (reg)) reg 575 drivers/scsi/qla4xxx/ql4_nx.h #define QLA82XX_PCIE_REG(reg) (QLA82XX_CRB_PCIE + (reg)) reg 636 drivers/scsi/qla4xxx/ql4_nx.h #define QLA82XX_PCIX_PS_REG(reg) (QLA82XX_CRB_PCIX_MD + (reg)) reg 637 drivers/scsi/qla4xxx/ql4_nx.h #define QLA82XX_PCIX_PS2_REG(reg) (QLA82XX_CRB_PCIE2 + (reg)) reg 274 drivers/scsi/qla4xxx/ql4_os.c reg_val = readw(&ha->reg->ctrl_status); reg 4184 drivers/scsi/qla4xxx/ql4_os.c } else if (ha->reg) { reg 4185 drivers/scsi/qla4xxx/ql4_os.c iounmap(ha->reg); reg 4652 drivers/scsi/qla4xxx/ql4_os.c ctrl_status = readw(&ha->reg->ctrl_status); reg 4654 drivers/scsi/qla4xxx/ql4_os.c writel(set_rmask(CSR_SCSI_RESET_INTR), &ha->reg->ctrl_status); reg 4657 drivers/scsi/qla4xxx/ql4_os.c writel(set_rmask(CSR_SOFT_RESET), &ha->reg->ctrl_status); reg 4658 drivers/scsi/qla4xxx/ql4_os.c readl(&ha->reg->ctrl_status); reg 4684 drivers/scsi/qla4xxx/ql4_os.c ctrl_status = readw(&ha->reg->ctrl_status); reg 4699 drivers/scsi/qla4xxx/ql4_os.c writel(set_rmask(CSR_NET_RESET_INTR), &ha->reg->ctrl_status); reg 4700 drivers/scsi/qla4xxx/ql4_os.c readl(&ha->reg->ctrl_status); reg 4708 drivers/scsi/qla4xxx/ql4_os.c ctrl_status = readw(&ha->reg->ctrl_status); reg 4724 drivers/scsi/qla4xxx/ql4_os.c ctrl_status = readw(&ha->reg->ctrl_status); reg 4726 drivers/scsi/qla4xxx/ql4_os.c writel(set_rmask(CSR_SCSI_RESET_INTR), &ha->reg->ctrl_status); reg 4727 drivers/scsi/qla4xxx/ql4_os.c readl(&ha->reg->ctrl_status); reg 4740 drivers/scsi/qla4xxx/ql4_os.c writel(set_rmask(CSR_FORCE_SOFT_RESET), &ha->reg->ctrl_status); reg 4741 drivers/scsi/qla4xxx/ql4_os.c readl(&ha->reg->ctrl_status); reg 4747 drivers/scsi/qla4xxx/ql4_os.c ctrl_status = readw(&ha->reg->ctrl_status); reg 5377 drivers/scsi/qla4xxx/ql4_os.c while ((readw(&ha->reg->ctrl_status) & reg 5454 drivers/scsi/qla4xxx/ql4_os.c &ha->reg->ctrl_status); reg 5455 drivers/scsi/qla4xxx/ql4_os.c readl(&ha->reg->ctrl_status); reg 5600 drivers/scsi/qla4xxx/ql4_os.c ha->reg = ioremap(mmio, MIN_IOBASE_LEN); reg 5601 drivers/scsi/qla4xxx/ql4_os.c if (!ha->reg) { reg 8666 drivers/scsi/qla4xxx/ql4_os.c pdev->device, pdev->irq, ha->reg); reg 3768 drivers/scsi/smartpqi/smartpqi_init.c u32 reg; reg 3782 drivers/scsi/smartpqi/smartpqi_init.c reg = PQI_ADMIN_IQ_NUM_ELEMENTS | reg 3785 drivers/scsi/smartpqi/smartpqi_init.c writel(reg, &pqi_registers->admin_iq_num_elements); reg 29 drivers/scsi/snic/vnic_dev.h static inline u64 readq(void __iomem *reg) reg 31 drivers/scsi/snic/vnic_dev.h return ((u64)readl(reg + 0x4UL) << 32) | (u64)readl(reg); reg 34 drivers/scsi/snic/vnic_dev.h static inline void writeq(u64 val, void __iomem *reg) reg 36 drivers/scsi/snic/vnic_dev.h writel(lower_32_bits(val), reg); reg 37 drivers/scsi/snic/vnic_dev.h writel(upper_32_bits(val), reg + 0x4UL); reg 46 drivers/scsi/sun3_scsi.c #define NCR5380_read(reg) in_8(hostdata->io + (reg)) reg 47 drivers/scsi/sun3_scsi.c #define NCR5380_write(reg, value) out_8(hostdata->io + (reg), value) reg 169 drivers/scsi/sun3_scsi.c static inline unsigned short sun3_udc_read(unsigned char reg) reg 181 drivers/scsi/sun3_scsi.c static inline void sun3_udc_write(unsigned short val, unsigned char reg) reg 183 drivers/scsi/sun3_scsi.c dregs->udc_addr = reg; reg 54 drivers/scsi/sun3x_esp.c static void sun3x_esp_write8(struct esp *esp, u8 val, unsigned long reg) reg 56 drivers/scsi/sun3x_esp.c writeb(val, esp->regs + (reg * 4UL)); reg 59 drivers/scsi/sun3x_esp.c static u8 sun3x_esp_read8(struct esp *esp, unsigned long reg) reg 61 drivers/scsi/sun3x_esp.c return readb(esp->regs + (reg * 4UL)); reg 204 drivers/scsi/sun_esp.c static void sbus_esp_write8(struct esp *esp, u8 val, unsigned long reg) reg 206 drivers/scsi/sun_esp.c sbus_writeb(val, esp->regs + (reg * 4UL)); reg 209 drivers/scsi/sun_esp.c static u8 sbus_esp_read8(struct esp *esp, unsigned long reg) reg 211 drivers/scsi/sun_esp.c return sbus_readb(esp->regs + (reg * 4UL)); reg 571 drivers/scsi/sym53c8xx_2/sym_defs.h #define SCR_SFBR_REG(reg,op,data) \ reg 572 drivers/scsi/sym53c8xx_2/sym_defs.h (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) reg 574 drivers/scsi/sym53c8xx_2/sym_defs.h #define SCR_REG_SFBR(reg,op,data) \ reg 575 drivers/scsi/sym53c8xx_2/sym_defs.h (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) reg 577 drivers/scsi/sym53c8xx_2/sym_defs.h #define SCR_REG_REG(reg,op,data) \ reg 578 drivers/scsi/sym53c8xx_2/sym_defs.h (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) reg 609 drivers/scsi/sym53c8xx_2/sym_defs.h #define SCR_FROM_REG(reg) \ reg 610 drivers/scsi/sym53c8xx_2/sym_defs.h SCR_REG_SFBR(reg,SCR_OR,0) reg 612 drivers/scsi/sym53c8xx_2/sym_defs.h #define SCR_TO_REG(reg) \ reg 613 drivers/scsi/sym53c8xx_2/sym_defs.h SCR_SFBR_REG(reg,SCR_OR,0) reg 615 drivers/scsi/sym53c8xx_2/sym_defs.h #define SCR_LOAD_REG(reg,data) \ reg 616 drivers/scsi/sym53c8xx_2/sym_defs.h SCR_REG_REG(reg,SCR_LOAD,data) reg 643 drivers/scsi/sym53c8xx_2/sym_defs.h #define SCR_LOAD_R(reg, how, n) \ reg 644 drivers/scsi/sym53c8xx_2/sym_defs.h (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) reg 646 drivers/scsi/sym53c8xx_2/sym_defs.h #define SCR_STORE_R(reg, how, n) \ reg 647 drivers/scsi/sym53c8xx_2/sym_defs.h (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) reg 649 drivers/scsi/sym53c8xx_2/sym_defs.h #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) reg 650 drivers/scsi/sym53c8xx_2/sym_defs.h #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) reg 651 drivers/scsi/sym53c8xx_2/sym_defs.h #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) reg 652 drivers/scsi/sym53c8xx_2/sym_defs.h #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) reg 654 drivers/scsi/sym53c8xx_2/sym_defs.h #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n) reg 655 drivers/scsi/sym53c8xx_2/sym_defs.h #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n) reg 656 drivers/scsi/sym53c8xx_2/sym_defs.h #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) reg 657 drivers/scsi/sym53c8xx_2/sym_defs.h #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) reg 84 drivers/scsi/ufs/ufs-hisi.c u32 reg; reg 97 drivers/scsi/ufs/ufs-hisi.c reg = ufs_sys_ctrl_readl(host, PHY_CLK_CTRL); reg 98 drivers/scsi/ufs/ufs-hisi.c reg = (reg & ~MASK_SYSCTRL_CFG_CLOCK_FREQ) | UFS_FREQ_CFG_CLK; reg 100 drivers/scsi/ufs/ufs-hisi.c ufs_sys_ctrl_writel(host, reg, PHY_CLK_CTRL); reg 143 drivers/scsi/ufs/ufs-hisi.c uint32_t reg; reg 233 drivers/scsi/ufs/ufs-hisi.c reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER); reg 234 drivers/scsi/ufs/ufs-hisi.c reg = reg & (~UFS_AHIT_AH8ITV_MASK); reg 235 drivers/scsi/ufs/ufs-hisi.c ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER); reg 106 drivers/scsi/ufs/ufs-hisi.h #define ufs_sys_ctrl_writel(host, val, reg) \ reg 107 drivers/scsi/ufs/ufs-hisi.h writel((val), (host)->ufs_sys_ctrl + (reg)) reg 108 drivers/scsi/ufs/ufs-hisi.h #define ufs_sys_ctrl_readl(host, reg) readl((host)->ufs_sys_ctrl + (reg)) reg 109 drivers/scsi/ufs/ufs-hisi.h #define ufs_sys_ctrl_set_bits(host, mask, reg) \ reg 111 drivers/scsi/ufs/ufs-hisi.h (host), ((mask) | (ufs_sys_ctrl_readl((host), (reg)))), (reg)) reg 112 drivers/scsi/ufs/ufs-hisi.h #define ufs_sys_ctrl_clr_bits(host, mask, reg) \ reg 114 drivers/scsi/ufs/ufs-hisi.h ((~(mask)) & (ufs_sys_ctrl_readl((host), (reg)))), \ reg 115 drivers/scsi/ufs/ufs-hisi.h (reg)) reg 1338 drivers/scsi/ufs/ufs-qcom.c u32 reg; reg 1354 drivers/scsi/ufs/ufs-qcom.c reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC); reg 1355 drivers/scsi/ufs/ufs-qcom.c print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv); reg 1357 drivers/scsi/ufs/ufs-qcom.c reg = ufshcd_readl(hba, REG_UFS_CFG1); reg 1358 drivers/scsi/ufs/ufs-qcom.c reg |= UTP_DBG_RAMS_EN; reg 1359 drivers/scsi/ufs/ufs-qcom.c ufshcd_writel(hba, reg, REG_UFS_CFG1); reg 1361 drivers/scsi/ufs/ufs-qcom.c reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM); reg 1362 drivers/scsi/ufs/ufs-qcom.c print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv); reg 1364 drivers/scsi/ufs/ufs-qcom.c reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM); reg 1365 drivers/scsi/ufs/ufs-qcom.c print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv); reg 1367 drivers/scsi/ufs/ufs-qcom.c reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM); reg 1368 drivers/scsi/ufs/ufs-qcom.c print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv); reg 1373 drivers/scsi/ufs/ufs-qcom.c reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM); reg 1374 drivers/scsi/ufs/ufs-qcom.c print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv); reg 1376 drivers/scsi/ufs/ufs-qcom.c reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM); reg 1377 drivers/scsi/ufs/ufs-qcom.c print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv); reg 1379 drivers/scsi/ufs/ufs-qcom.c reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC); reg 1380 drivers/scsi/ufs/ufs-qcom.c print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv); reg 1382 drivers/scsi/ufs/ufs-qcom.c reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC); reg 1383 drivers/scsi/ufs/ufs-qcom.c print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv); reg 1385 drivers/scsi/ufs/ufs-qcom.c reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC); reg 1386 drivers/scsi/ufs/ufs-qcom.c print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv); reg 1388 drivers/scsi/ufs/ufs-qcom.c reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT); reg 1389 drivers/scsi/ufs/ufs-qcom.c print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv); reg 1391 drivers/scsi/ufs/ufs-qcom.c reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT); reg 1392 drivers/scsi/ufs/ufs-qcom.c print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv); reg 1428 drivers/scsi/ufs/ufs-qcom.c int reg; reg 1440 drivers/scsi/ufs/ufs-qcom.c reg = UFS_TEST_BUS_CTRL_0; reg 1444 drivers/scsi/ufs/ufs-qcom.c reg = UFS_TEST_BUS_CTRL_0; reg 1448 drivers/scsi/ufs/ufs-qcom.c reg = UFS_TEST_BUS_CTRL_0; reg 1452 drivers/scsi/ufs/ufs-qcom.c reg = UFS_TEST_BUS_CTRL_0; reg 1456 drivers/scsi/ufs/ufs-qcom.c reg = UFS_TEST_BUS_CTRL_1; reg 1460 drivers/scsi/ufs/ufs-qcom.c reg = UFS_TEST_BUS_CTRL_1; reg 1464 drivers/scsi/ufs/ufs-qcom.c reg = UFS_TEST_BUS_CTRL_1; reg 1468 drivers/scsi/ufs/ufs-qcom.c reg = UFS_TEST_BUS_CTRL_1; reg 1472 drivers/scsi/ufs/ufs-qcom.c reg = UFS_TEST_BUS_CTRL_2; reg 1476 drivers/scsi/ufs/ufs-qcom.c reg = UFS_TEST_BUS_CTRL_2; reg 1480 drivers/scsi/ufs/ufs-qcom.c reg = UFS_TEST_BUS_CTRL_2; reg 1484 drivers/scsi/ufs/ufs-qcom.c reg = UFS_UNIPRO_CFG; reg 1503 drivers/scsi/ufs/ufs-qcom.c reg); reg 242 drivers/scsi/ufs/ufs-qcom.h ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg) reg 245 drivers/scsi/ufs/ufs-qcom.h return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg); reg 247 drivers/scsi/ufs/ufs-qcom.h return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg); reg 514 drivers/scsi/ufs/ufs.h struct regulator *reg; reg 393 drivers/scsi/ufs/ufshcd.c if (err_hist->reg[p] == 0) reg 396 drivers/scsi/ufs/ufshcd.c err_hist->reg[p], ktime_to_us(err_hist->tstamp[p])); reg 554 drivers/scsi/ufs/ufshcd.c int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, reg 564 drivers/scsi/ufs/ufshcd.c while ((ufshcd_readl(hba, reg) & mask) != val) { reg 570 drivers/scsi/ufs/ufshcd.c if ((ufshcd_readl(hba, reg) & mask) != val) reg 722 drivers/scsi/ufs/ufshcd.c static inline int ufshcd_get_lists_status(u32 reg) reg 724 drivers/scsi/ufs/ufshcd.c return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); reg 4194 drivers/scsi/ufs/ufshcd.c u32 reg; reg 4224 drivers/scsi/ufs/ufshcd.c reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); reg 4225 drivers/scsi/ufs/ufshcd.c if (!(ufshcd_get_lists_status(reg))) { reg 4376 drivers/scsi/ufs/ufshcd.c u32 reg) reg 4378 drivers/scsi/ufs/ufshcd.c reg_hist->reg[reg_hist->pos] = reg; reg 5419 drivers/scsi/ufs/ufshcd.c u32 reg; reg 5422 drivers/scsi/ufs/ufshcd.c reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); reg 5424 drivers/scsi/ufs/ufshcd.c if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) && reg 5425 drivers/scsi/ufs/ufshcd.c (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) { reg 5431 drivers/scsi/ufs/ufshcd.c ufshcd_update_reg_hist(&hba->ufs_stats.pa_err, reg); reg 5435 drivers/scsi/ufs/ufshcd.c reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); reg 5436 drivers/scsi/ufs/ufshcd.c if (reg) reg 5437 drivers/scsi/ufs/ufshcd.c ufshcd_update_reg_hist(&hba->ufs_stats.dl_err, reg); reg 5439 drivers/scsi/ufs/ufshcd.c if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) reg 5443 drivers/scsi/ufs/ufshcd.c if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED) reg 5446 drivers/scsi/ufs/ufshcd.c else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) reg 5451 drivers/scsi/ufs/ufshcd.c reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); reg 5452 drivers/scsi/ufs/ufshcd.c if (reg) { reg 5453 drivers/scsi/ufs/ufshcd.c ufshcd_update_reg_hist(&hba->ufs_stats.nl_err, reg); reg 5457 drivers/scsi/ufs/ufshcd.c reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); reg 5458 drivers/scsi/ufs/ufshcd.c if (reg) { reg 5459 drivers/scsi/ufs/ufshcd.c ufshcd_update_reg_hist(&hba->ufs_stats.tl_err, reg); reg 5463 drivers/scsi/ufs/ufshcd.c reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); reg 5464 drivers/scsi/ufs/ufshcd.c if (reg) { reg 5465 drivers/scsi/ufs/ufshcd.c ufshcd_update_reg_hist(&hba->ufs_stats.dme_err, reg); reg 6048 drivers/scsi/ufs/ufshcd.c u32 reg; reg 6072 drivers/scsi/ufs/ufshcd.c reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); reg 6077 drivers/scsi/ufs/ufshcd.c __func__, tag, hba->outstanding_reqs, reg); reg 6081 drivers/scsi/ufs/ufshcd.c if (!(reg & (1 << tag))) { reg 6130 drivers/scsi/ufs/ufshcd.c reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); reg 6131 drivers/scsi/ufs/ufshcd.c if (reg & (1 << tag)) { reg 7097 drivers/scsi/ufs/ufshcd.c ret = regulator_set_load(vreg->reg, ua); reg 7125 drivers/scsi/ufs/ufshcd.c struct regulator *reg; reg 7131 drivers/scsi/ufs/ufshcd.c reg = vreg->reg; reg 7134 drivers/scsi/ufs/ufshcd.c if (regulator_count_voltages(reg) > 0) { reg 7137 drivers/scsi/ufs/ufshcd.c ret = regulator_set_voltage(reg, min_uV, vreg->max_uV); reg 7164 drivers/scsi/ufs/ufshcd.c ret = regulator_enable(vreg->reg); reg 7182 drivers/scsi/ufs/ufshcd.c ret = regulator_disable(vreg->reg); reg 7237 drivers/scsi/ufs/ufshcd.c vreg->reg = devm_regulator_get(dev, vreg->name); reg 7238 drivers/scsi/ufs/ufshcd.c if (IS_ERR(vreg->reg)) { reg 7239 drivers/scsi/ufs/ufshcd.c ret = PTR_ERR(vreg->reg); reg 427 drivers/scsi/ufs/ufshcd.h u32 reg[UFS_ERR_REG_HIST_LENGTH]; reg 780 drivers/scsi/ufs/ufshcd.h #define ufshcd_writel(hba, val, reg) \ reg 781 drivers/scsi/ufs/ufshcd.h writel((val), (hba)->mmio_base + (reg)) reg 782 drivers/scsi/ufs/ufshcd.h #define ufshcd_readl(hba, reg) \ reg 783 drivers/scsi/ufs/ufshcd.h readl((hba)->mmio_base + (reg)) reg 792 drivers/scsi/ufs/ufshcd.h static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) reg 796 drivers/scsi/ufs/ufshcd.h tmp = ufshcd_readl(hba, reg); reg 799 drivers/scsi/ufs/ufshcd.h ufshcd_writel(hba, tmp, reg); reg 806 drivers/scsi/ufs/ufshcd.h int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, reg 50 drivers/scsi/wd719x.c static inline u8 wd719x_readb(struct wd719x *wd, u8 reg) reg 52 drivers/scsi/wd719x.c return ioread8(wd->base + reg); reg 55 drivers/scsi/wd719x.c static inline u32 wd719x_readl(struct wd719x *wd, u8 reg) reg 57 drivers/scsi/wd719x.c return ioread32(wd->base + reg); reg 60 drivers/scsi/wd719x.c static inline void wd719x_writeb(struct wd719x *wd, u8 reg, u8 val) reg 62 drivers/scsi/wd719x.c iowrite8(val, wd->base + reg); reg 65 drivers/scsi/wd719x.c static inline void wd719x_writew(struct wd719x *wd, u8 reg, u16 val) reg 67 drivers/scsi/wd719x.c iowrite16(val, wd->base + reg); reg 70 drivers/scsi/wd719x.c static inline void wd719x_writel(struct wd719x *wd, u8 reg, u32 val) reg 72 drivers/scsi/wd719x.c iowrite32(val, wd->base + reg); reg 716 drivers/scsi/wd719x.c u8 reg = wd719x_readb(wd, WD719X_PCI_GPIO_DATA); reg 718 drivers/scsi/wd719x.c eeprom->reg_data_out = reg & WD719X_EE_DO; reg 724 drivers/scsi/wd719x.c u8 reg = 0; reg 727 drivers/scsi/wd719x.c reg |= WD719X_EE_DI; reg 729 drivers/scsi/wd719x.c reg |= WD719X_EE_CLK; reg 731 drivers/scsi/wd719x.c reg |= WD719X_EE_CS; reg 733 drivers/scsi/wd719x.c wd719x_writeb(wd, WD719X_PCI_GPIO_DATA, reg); reg 172 drivers/scsi/zorro_esp.c static void zorro_esp_write8(struct esp *esp, u8 val, unsigned long reg) reg 174 drivers/scsi/zorro_esp.c writeb(val, esp->regs + (reg * 4UL)); reg 177 drivers/scsi/zorro_esp.c static u8 zorro_esp_read8(struct esp *esp, unsigned long reg) reg 179 drivers/scsi/zorro_esp.c return readb(esp->regs + (reg * 4UL)); reg 46 drivers/sh/intc/access.c if (d->reg[k] == address) reg 172 drivers/sh/intc/core.c d->reg[cnt] = value; reg 233 drivers/sh/intc/core.c d->reg = kcalloc(d->nr_reg, sizeof(*d->reg), GFP_NOWAIT); reg 234 drivers/sh/intc/core.c if (!d->reg) reg 278 drivers/sh/intc/core.c k += save_reg(d, k, hw->sense_regs[i].reg, 0); reg 286 drivers/sh/intc/core.c if (hw->subgroups[i].reg) reg 287 drivers/sh/intc/core.c k+= save_reg(d, k, hw->subgroups[i].reg, 0); reg 393 drivers/sh/intc/core.c kfree(d->reg); reg 278 drivers/sh/intc/handle.c return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg), reg 24 drivers/sh/intc/internals.h #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c)) reg 28 drivers/sh/intc/internals.h #define INTC_REG(d, x, c) (d->reg[(x)]) reg 60 drivers/sh/intc/internals.h unsigned long *reg; reg 141 drivers/sh/intc/virq.c return _INTC_MK(fn, MODE_ENABLE_REG, intc_get_reg(d, subgroup->reg), reg 211 drivers/slimbus/core.c int reg[2], ret; reg 225 drivers/slimbus/core.c ret = of_property_read_u32_array(node, "reg", reg, 2); reg 232 drivers/slimbus/core.c e_addr.dev_index = reg[0]; reg 233 drivers/slimbus/core.c e_addr.instance = reg[1]; reg 41 drivers/soc/amlogic/meson-canvas.c static void canvas_write(struct meson_canvas *canvas, u32 reg, u32 val) reg 43 drivers/soc/amlogic/meson-canvas.c writel_relaxed(val, canvas->reg_base + reg); reg 46 drivers/soc/amlogic/meson-canvas.c static u32 canvas_read(struct meson_canvas *canvas, u32 reg) reg 48 drivers/soc/amlogic/meson-canvas.c return readl_relaxed(canvas->reg_base + reg); reg 41 drivers/soc/amlogic/meson-ee-pwrc.c unsigned int reg; reg 242 drivers/soc/amlogic/meson-ee-pwrc.c u32 reg; reg 245 drivers/soc/amlogic/meson-ee-pwrc.c pwrc_domain->desc.top_pd->sleep_reg, ®); reg 247 drivers/soc/amlogic/meson-ee-pwrc.c return (reg & pwrc_domain->desc.top_pd->sleep_mask); reg 265 drivers/soc/amlogic/meson-ee-pwrc.c pwrc_domain->desc.mem_pd[i].reg, reg 300 drivers/soc/amlogic/meson-ee-pwrc.c pwrc_domain->desc.mem_pd[i].reg, reg 247 drivers/soc/amlogic/meson-gx-pwrc-vpu.c u32 reg; reg 249 drivers/soc/amlogic/meson-gx-pwrc-vpu.c regmap_read(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, ®); reg 251 drivers/soc/amlogic/meson-gx-pwrc-vpu.c return (reg & GEN_PWR_VPU_HDMI); reg 130 drivers/soc/aspeed/aspeed-lpc-snoop.c u32 reg, data; reg 132 drivers/soc/aspeed/aspeed-lpc-snoop.c if (regmap_read(lpc_snoop->regmap, HICR6, ®)) reg 136 drivers/soc/aspeed/aspeed-lpc-snoop.c reg &= (HICR6_STR_SNP0W | HICR6_STR_SNP1W); reg 137 drivers/soc/aspeed/aspeed-lpc-snoop.c if (!reg) reg 141 drivers/soc/aspeed/aspeed-lpc-snoop.c regmap_write(lpc_snoop->regmap, HICR6, reg); reg 146 drivers/soc/aspeed/aspeed-lpc-snoop.c if (reg & HICR6_STR_SNP0W) { reg 151 drivers/soc/aspeed/aspeed-lpc-snoop.c if (reg & HICR6_STR_SNP1W) { reg 109 drivers/soc/bcm/bcm2835-power.c #define PM_READ(reg) readl(power->base + (reg)) reg 110 drivers/soc/bcm/bcm2835-power.c #define PM_WRITE(reg, val) writel(PM_PASSWORD | (val), power->base + (reg)) reg 129 drivers/soc/bcm/bcm2835-power.c #define ASB_READ(reg) readl(power->asb + (reg)) reg 130 drivers/soc/bcm/bcm2835-power.c #define ASB_WRITE(reg, val) writel(PM_PASSWORD | (val), power->asb + (reg)) reg 151 drivers/soc/bcm/bcm2835-power.c static int bcm2835_asb_enable(struct bcm2835_power *power, u32 reg) reg 155 drivers/soc/bcm/bcm2835-power.c if (!reg) reg 161 drivers/soc/bcm/bcm2835-power.c ASB_WRITE(reg, ASB_READ(reg) & ~ASB_REQ_STOP); reg 162 drivers/soc/bcm/bcm2835-power.c while (ASB_READ(reg) & ASB_ACK) { reg 171 drivers/soc/bcm/bcm2835-power.c static int bcm2835_asb_disable(struct bcm2835_power *power, u32 reg) reg 175 drivers/soc/bcm/bcm2835-power.c if (!reg) reg 181 drivers/soc/bcm/bcm2835-power.c ASB_WRITE(reg, ASB_READ(reg) | ASB_REQ_STOP); reg 182 drivers/soc/bcm/bcm2835-power.c while (!(ASB_READ(reg) & ASB_ACK)) { reg 34 drivers/soc/bcm/brcmstb/biuctrl.c static inline u32 cbc_readl(int reg) reg 36 drivers/soc/bcm/brcmstb/biuctrl.c int offset = cpubiuctrl_regs[reg]; reg 44 drivers/soc/bcm/brcmstb/biuctrl.c static inline void cbc_writel(u32 val, int reg) reg 46 drivers/soc/bcm/brcmstb/biuctrl.c int offset = cpubiuctrl_regs[reg]; reg 113 drivers/soc/bcm/brcmstb/biuctrl.c u32 reg; reg 115 drivers/soc/bcm/brcmstb/biuctrl.c reg = brcmstb_get_family_id(); reg 118 drivers/soc/bcm/brcmstb/biuctrl.c if (BRCM_ID(reg) == b53_mach_compat[i]) reg 126 drivers/soc/bcm/brcmstb/biuctrl.c reg = cbc_readl(CPU_CREDIT_REG); reg 128 drivers/soc/bcm/brcmstb/biuctrl.c reg &= ~(CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK << reg 130 drivers/soc/bcm/brcmstb/biuctrl.c reg &= ~(CPU_CREDIT_REG_MCPx_READ_CRED_MASK << reg 132 drivers/soc/bcm/brcmstb/biuctrl.c reg |= 8 << CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i); reg 133 drivers/soc/bcm/brcmstb/biuctrl.c reg |= 8 << CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i); reg 135 drivers/soc/bcm/brcmstb/biuctrl.c cbc_writel(reg, CPU_CREDIT_REG); reg 138 drivers/soc/bcm/brcmstb/biuctrl.c reg = cbc_readl(CPU_MCP_FLOW_REG); reg 140 drivers/soc/bcm/brcmstb/biuctrl.c reg |= CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK << reg 142 drivers/soc/bcm/brcmstb/biuctrl.c cbc_writel(reg, CPU_MCP_FLOW_REG); reg 147 drivers/soc/bcm/brcmstb/biuctrl.c reg = cbc_readl(CPU_WRITEBACK_CTRL_REG); reg 148 drivers/soc/bcm/brcmstb/biuctrl.c reg |= CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE; reg 149 drivers/soc/bcm/brcmstb/biuctrl.c reg &= ~CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK; reg 150 drivers/soc/bcm/brcmstb/biuctrl.c reg &= ~(CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK << reg 152 drivers/soc/bcm/brcmstb/biuctrl.c reg |= 8; reg 153 drivers/soc/bcm/brcmstb/biuctrl.c reg |= 7 << CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT; reg 154 drivers/soc/bcm/brcmstb/biuctrl.c cbc_writel(reg, CPU_WRITEBACK_CTRL_REG); reg 160 drivers/soc/fsl/dpio/qbman-portal.c u32 reg; reg 192 drivers/soc/fsl/dpio/qbman-portal.c reg = qbman_set_swp_cfg(p->dqrr.dqrr_size, reg 205 drivers/soc/fsl/dpio/qbman-portal.c reg |= 1 << SWP_CFG_CPBS_SHIFT | /* memory-backed mode */ reg 209 drivers/soc/fsl/dpio/qbman-portal.c qbman_write_register(p, QBMAN_CINH_SWP_CFG, reg); reg 210 drivers/soc/fsl/dpio/qbman-portal.c reg = qbman_read_register(p, QBMAN_CINH_SWP_CFG); reg 211 drivers/soc/fsl/dpio/qbman-portal.c if (!reg) { reg 174 drivers/soc/fsl/qe/qe_ic.c static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg) reg 176 drivers/soc/fsl/qe/qe_ic.c return in_be32(base + (reg >> 2)); reg 179 drivers/soc/fsl/qe/qe_ic.c static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg, reg 182 drivers/soc/fsl/qe/qe_ic.c out_be32(base + (reg >> 2), value); reg 135 drivers/soc/ixp4xx/ixp4xx-npe.c u32 reg, val; reg 186 drivers/soc/ixp4xx/ixp4xx-npe.c static void npe_clear_active(struct npe *npe, u32 reg) reg 188 drivers/soc/ixp4xx/ixp4xx-npe.c u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG); reg 189 drivers/soc/ixp4xx/ixp4xx-npe.c npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE); reg 368 drivers/soc/ixp4xx/ixp4xx-npe.c npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG, reg 123 drivers/soc/ixp4xx/ixp4xx-qmgr.c u32 __iomem *reg; reg 126 drivers/soc/ixp4xx/ixp4xx-qmgr.c reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */ reg 128 drivers/soc/ixp4xx/ixp4xx-qmgr.c __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), reg 129 drivers/soc/ixp4xx/ixp4xx-qmgr.c reg); reg 1000 drivers/soc/mediatek/mtk-pmic-wrap.c static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg) reg 1002 drivers/soc/mediatek/mtk-pmic-wrap.c return readl(wrp->base + wrp->master->regs[reg]); reg 1005 drivers/soc/mediatek/mtk-pmic-wrap.c static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg) reg 1007 drivers/soc/mediatek/mtk-pmic-wrap.c writel(val, wrp->base + wrp->master->regs[reg]); reg 64 drivers/soc/qcom/rpmh-rsc.c static u32 read_tcs_reg(struct rsc_drv *drv, int reg, int tcs_id, int cmd_id) reg 66 drivers/soc/qcom/rpmh-rsc.c return readl_relaxed(drv->tcs_base + reg + RSC_DRV_TCS_OFFSET * tcs_id + reg 70 drivers/soc/qcom/rpmh-rsc.c static void write_tcs_cmd(struct rsc_drv *drv, int reg, int tcs_id, int cmd_id, reg 73 drivers/soc/qcom/rpmh-rsc.c writel_relaxed(data, drv->tcs_base + reg + RSC_DRV_TCS_OFFSET * tcs_id + reg 77 drivers/soc/qcom/rpmh-rsc.c static void write_tcs_reg(struct rsc_drv *drv, int reg, int tcs_id, u32 data) reg 79 drivers/soc/qcom/rpmh-rsc.c writel_relaxed(data, drv->tcs_base + reg + RSC_DRV_TCS_OFFSET * tcs_id); reg 82 drivers/soc/qcom/rpmh-rsc.c static void write_tcs_reg_sync(struct rsc_drv *drv, int reg, int tcs_id, reg 85 drivers/soc/qcom/rpmh-rsc.c writel(data, drv->tcs_base + reg + RSC_DRV_TCS_OFFSET * tcs_id); reg 87 drivers/soc/qcom/rpmh-rsc.c if (data == readl(drv->tcs_base + reg + reg 116 drivers/soc/qcom/spm.c enum spm_reg reg, u32 val) reg 118 drivers/soc/qcom/spm.c if (drv->reg_data->reg_offset[reg]) reg 120 drivers/soc/qcom/spm.c drv->reg_data->reg_offset[reg]); reg 125 drivers/soc/qcom/spm.c enum spm_reg reg, u32 val) reg 129 drivers/soc/qcom/spm.c if (!drv->reg_data->reg_offset[reg]) reg 134 drivers/soc/qcom/spm.c drv->reg_data->reg_offset[reg]); reg 136 drivers/soc/qcom/spm.c drv->reg_data->reg_offset[reg]); reg 144 drivers/soc/qcom/spm.c enum spm_reg reg) reg 146 drivers/soc/qcom/spm.c return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]); reg 18 drivers/soc/renesas/renesas-soc.c u32 reg; /* CCCR or PRR, if not in DT */ reg 23 drivers/soc/renesas/renesas-soc.c .reg = 0xff000044, /* PRR (Product Register) */ reg 28 drivers/soc/renesas/renesas-soc.c .reg = 0xff000044, /* PRR (Product Register) */ reg 33 drivers/soc/renesas/renesas-soc.c .reg = 0xfff00044, /* PRR (Product Register) */ reg 38 drivers/soc/renesas/renesas-soc.c .reg = 0xe600101c, /* CCCR (Common Chip Code Register) */ reg 51 drivers/soc/renesas/renesas-soc.c .reg = 0xff000044, /* PRR (Product Register) */ reg 56 drivers/soc/renesas/renesas-soc.c .reg = 0xfff00044, /* PRR (Product Register) */ reg 61 drivers/soc/renesas/renesas-soc.c .reg = 0xe600101c, /* CCCR (Common Chip Code Register) */ reg 329 drivers/soc/renesas/renesas-soc.c } else if (soc->id && family->reg) { reg 330 drivers/soc/renesas/renesas-soc.c chipid = ioremap(family->reg, 4); reg 19 drivers/soc/rockchip/grf.c u32 reg; reg 166 drivers/soc/rockchip/grf.c val->desc, val->reg, val->val); reg 167 drivers/soc/rockchip/grf.c ret = regmap_write(grf, val->reg, val->val); reg 170 drivers/soc/rockchip/grf.c __func__, val->reg, ret); reg 32 drivers/soc/sunxi/sunxi_sram.c u8 reg; reg 54 drivers/soc/sunxi/sunxi_sram.c .reg = _reg, \ reg 141 drivers/soc/sunxi/sunxi_sram.c val = readl(base + sram_data->reg); reg 252 drivers/soc/sunxi/sunxi_sram.c val = readl(base + sram_data->reg); reg 255 drivers/soc/sunxi/sunxi_sram.c base + sram_data->reg); reg 303 drivers/soc/sunxi/sunxi_sram.c unsigned int reg) reg 305 drivers/soc/sunxi/sunxi_sram.c if (reg == SUNXI_SRAM_EMAC_CLOCK_REG) reg 74 drivers/soc/tegra/flowctrl.c unsigned int reg; reg 77 drivers/soc/tegra/flowctrl.c reg = flowctrl_read_cpu_csr(cpuid); reg 81 drivers/soc/tegra/flowctrl.c reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; reg 83 drivers/soc/tegra/flowctrl.c reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; reg 85 drivers/soc/tegra/flowctrl.c reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; reg 91 drivers/soc/tegra/flowctrl.c reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; reg 93 drivers/soc/tegra/flowctrl.c reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; reg 95 drivers/soc/tegra/flowctrl.c reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; reg 98 drivers/soc/tegra/flowctrl.c reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */ reg 99 drivers/soc/tegra/flowctrl.c reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */ reg 100 drivers/soc/tegra/flowctrl.c reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */ reg 101 drivers/soc/tegra/flowctrl.c flowctrl_write_cpu_csr(cpuid, reg); reg 106 drivers/soc/tegra/flowctrl.c reg = flowctrl_read_cpu_csr(i); reg 107 drivers/soc/tegra/flowctrl.c reg |= FLOW_CTRL_CSR_EVENT_FLAG; reg 108 drivers/soc/tegra/flowctrl.c reg |= FLOW_CTRL_CSR_INTR_FLAG; reg 109 drivers/soc/tegra/flowctrl.c flowctrl_write_cpu_csr(i, reg); reg 115 drivers/soc/tegra/flowctrl.c unsigned int reg; reg 118 drivers/soc/tegra/flowctrl.c reg = flowctrl_read_cpu_csr(cpuid); reg 122 drivers/soc/tegra/flowctrl.c reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; reg 124 drivers/soc/tegra/flowctrl.c reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; reg 130 drivers/soc/tegra/flowctrl.c reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; reg 132 drivers/soc/tegra/flowctrl.c reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; reg 135 drivers/soc/tegra/flowctrl.c reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */ reg 136 drivers/soc/tegra/flowctrl.c reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */ reg 137 drivers/soc/tegra/flowctrl.c reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */ reg 138 drivers/soc/tegra/flowctrl.c flowctrl_write_cpu_csr(cpuid, reg); reg 200 drivers/soc/tegra/fuse/fuse-tegra.c u32 reg; reg 202 drivers/soc/tegra/fuse/fuse-tegra.c reg = readl_relaxed(base + 0x48); reg 203 drivers/soc/tegra/fuse/fuse-tegra.c reg |= 1 << 28; reg 204 drivers/soc/tegra/fuse/fuse-tegra.c writel(reg, base + 0x48); reg 210 drivers/soc/tegra/fuse/fuse-tegra.c reg = readl(base + 0x14); reg 211 drivers/soc/tegra/fuse/fuse-tegra.c reg |= 1 << 7; reg 212 drivers/soc/tegra/fuse/fuse-tegra.c writel(reg, base + 0x14); reg 56 drivers/soc/tegra/fuse/speedo-tegra20.c u32 reg; reg 72 drivers/soc/tegra/fuse/speedo-tegra20.c reg = tegra_fuse_read_spare(i) | reg 74 drivers/soc/tegra/fuse/speedo-tegra20.c val = (val << 1) | (reg & 0x1); reg 87 drivers/soc/tegra/fuse/speedo-tegra20.c reg = tegra_fuse_read_spare(i) | reg 89 drivers/soc/tegra/fuse/speedo-tegra20.c val = (val << 1) | (reg & 0x1); reg 80 drivers/soc/tegra/fuse/speedo-tegra30.c u32 reg; reg 85 drivers/soc/tegra/fuse/speedo-tegra30.c reg = tegra_fuse_read_early(FUSE_SPEEDO_CALIB_0); reg 87 drivers/soc/tegra/fuse/speedo-tegra30.c *speedo_lp = (reg & 0xFFFF) * 4; reg 88 drivers/soc/tegra/fuse/speedo-tegra30.c *speedo_g = ((reg >> 16) & 0xFFFF) * 4; reg 242 drivers/soundwire/cadence_master.c char *buf, size_t pos, unsigned int reg) reg 245 drivers/soundwire/cadence_master.c "%4x\t%8x\n", reg, cdns_readl(cdns, reg)); reg 34 drivers/soundwire/debugfs.c char *buf, size_t pos, unsigned int reg) reg 38 drivers/soundwire/debugfs.c value = sdw_read(slave, reg); reg 41 drivers/soundwire/debugfs.c return scnprintf(buf + pos, RD_BUF - pos, "%3x\tXX\n", reg); reg 44 drivers/soundwire/debugfs.c "%3x\t%2x\n", reg, value); reg 180 drivers/soundwire/intel.c char *buf, size_t pos, unsigned int reg) reg 185 drivers/soundwire/intel.c value = intel_readl(mem, reg); reg 187 drivers/soundwire/intel.c value = intel_readw(mem, reg); reg 189 drivers/soundwire/intel.c return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value); reg 200 drivers/soundwire/intel.c unsigned int links, reg; reg 212 drivers/soundwire/intel.c reg = SDW_SHIM_LCAP + i * 4; reg 213 drivers/soundwire/intel.c ret += intel_sprintf(s, true, buf, ret, reg); reg 69 drivers/spi/spi-at91-usart.c #define at91_usart_spi_readl(port, reg) \ reg 70 drivers/spi/spi-at91-usart.c readl_relaxed((port)->regs + US_##reg) reg 71 drivers/spi/spi-at91-usart.c #define at91_usart_spi_writel(port, reg, value) \ reg 72 drivers/spi/spi-at91-usart.c writel_relaxed((value), (port)->regs + US_##reg) reg 74 drivers/spi/spi-at91-usart.c #define at91_usart_spi_readb(port, reg) \ reg 75 drivers/spi/spi-at91-usart.c readb_relaxed((port)->regs + US_##reg) reg 76 drivers/spi/spi-at91-usart.c #define at91_usart_spi_writeb(port, reg, value) \ reg 77 drivers/spi/spi-at91-usart.c writeb_relaxed((value), (port)->regs + US_##reg) reg 49 drivers/spi/spi-ath79.c static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg) reg 51 drivers/spi/spi-ath79.c return ioread32(sp->base + reg); reg 54 drivers/spi/spi-ath79.c static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val) reg 56 drivers/spi/spi-ath79.c iowrite32(val, sp->base + reg); reg 226 drivers/spi/spi-atmel.c #define spi_readl(port, reg) \ reg 227 drivers/spi/spi-atmel.c __raw_readl((port)->regs + SPI_##reg) reg 228 drivers/spi/spi-atmel.c #define spi_writel(port, reg, value) \ reg 229 drivers/spi/spi-atmel.c __raw_writel((value), (port)->regs + SPI_##reg) reg 231 drivers/spi/spi-atmel.c #define spi_readw(port, reg) \ reg 232 drivers/spi/spi-atmel.c __raw_readw((port)->regs + SPI_##reg) reg 233 drivers/spi/spi-atmel.c #define spi_writew(port, reg, value) \ reg 234 drivers/spi/spi-atmel.c __raw_writew((value), (port)->regs + SPI_##reg) reg 236 drivers/spi/spi-atmel.c #define spi_readb(port, reg) \ reg 237 drivers/spi/spi-atmel.c __raw_readb((port)->regs + SPI_##reg) reg 238 drivers/spi/spi-atmel.c #define spi_writeb(port, reg, value) \ reg 239 drivers/spi/spi-atmel.c __raw_writeb((value), (port)->regs + SPI_##reg) reg 241 drivers/spi/spi-atmel.c #define spi_readl(port, reg) \ reg 242 drivers/spi/spi-atmel.c readl_relaxed((port)->regs + SPI_##reg) reg 243 drivers/spi/spi-atmel.c #define spi_writel(port, reg, value) \ reg 244 drivers/spi/spi-atmel.c writel_relaxed((value), (port)->regs + SPI_##reg) reg 246 drivers/spi/spi-atmel.c #define spi_readw(port, reg) \ reg 247 drivers/spi/spi-atmel.c readw_relaxed((port)->regs + SPI_##reg) reg 248 drivers/spi/spi-atmel.c #define spi_writew(port, reg, value) \ reg 249 drivers/spi/spi-atmel.c writew_relaxed((value), (port)->regs + SPI_##reg) reg 251 drivers/spi/spi-atmel.c #define spi_readb(port, reg) \ reg 252 drivers/spi/spi-atmel.c readb_relaxed((port)->regs + SPI_##reg) reg 253 drivers/spi/spi-atmel.c #define spi_writeb(port, reg, value) \ reg 254 drivers/spi/spi-atmel.c writeb_relaxed((value), (port)->regs + SPI_##reg) reg 69 drivers/spi/spi-axi-spi-engine.c #define SPI_ENGINE_CMD_WRITE(reg, val) \ reg 70 drivers/spi/spi-axi-spi-engine.c SPI_ENGINE_CMD(SPI_ENGINE_INST_WRITE, (reg), (val)) reg 194 drivers/spi/spi-bcm2835.c static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg) reg 196 drivers/spi/spi-bcm2835.c return readl(bs->regs + reg); reg 199 drivers/spi/spi-bcm2835.c static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val) reg 201 drivers/spi/spi-bcm2835.c writel(val, bs->regs + reg); reg 146 drivers/spi/spi-bcm2835aux.c static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg) reg 148 drivers/spi/spi-bcm2835aux.c return readl(bs->regs + reg); reg 151 drivers/spi/spi-bcm2835aux.c static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg, reg 154 drivers/spi/spi-bcm2835aux.c writel(val, bs->regs + reg); reg 115 drivers/spi/spi-bcm63xx-hsspi.c u32 reg; reg 118 drivers/spi/spi-bcm63xx-hsspi.c reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); reg 120 drivers/spi/spi-bcm63xx-hsspi.c reg &= ~BIT(cs); reg 122 drivers/spi/spi-bcm63xx-hsspi.c reg |= BIT(cs); reg 124 drivers/spi/spi-bcm63xx-hsspi.c __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); reg 132 drivers/spi/spi-bcm63xx-hsspi.c u32 reg; reg 134 drivers/spi/spi-bcm63xx-hsspi.c reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz)); reg 135 drivers/spi/spi-bcm63xx-hsspi.c __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg, reg 138 drivers/spi/spi-bcm63xx-hsspi.c reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile)); reg 140 drivers/spi/spi-bcm63xx-hsspi.c reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH; reg 142 drivers/spi/spi-bcm63xx-hsspi.c reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH; reg 143 drivers/spi/spi-bcm63xx-hsspi.c __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile)); reg 147 drivers/spi/spi-bcm63xx-hsspi.c reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); reg 148 drivers/spi/spi-bcm63xx-hsspi.c reg &= ~GLOBAL_CTRL_CLK_POLARITY; reg 150 drivers/spi/spi-bcm63xx-hsspi.c reg |= GLOBAL_CTRL_CLK_POLARITY; reg 151 drivers/spi/spi-bcm63xx-hsspi.c __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); reg 226 drivers/spi/spi-bcm63xx-hsspi.c u32 reg; reg 228 drivers/spi/spi-bcm63xx-hsspi.c reg = __raw_readl(bs->regs + reg 230 drivers/spi/spi-bcm63xx-hsspi.c reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING); reg 232 drivers/spi/spi-bcm63xx-hsspi.c reg |= SIGNAL_CTRL_LAUNCH_RISING; reg 234 drivers/spi/spi-bcm63xx-hsspi.c reg |= SIGNAL_CTRL_LATCH_RISING; reg 235 drivers/spi/spi-bcm63xx-hsspi.c __raw_writel(reg, bs->regs + reg 239 drivers/spi/spi-bcm63xx-hsspi.c reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); reg 242 drivers/spi/spi-bcm63xx-hsspi.c if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) { reg 244 drivers/spi/spi-bcm63xx-hsspi.c reg |= BIT(spi->chip_select); reg 246 drivers/spi/spi-bcm63xx-hsspi.c reg &= ~BIT(spi->chip_select); reg 247 drivers/spi/spi-bcm63xx-hsspi.c __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); reg 268 drivers/spi/spi-bcm63xx-hsspi.c u32 reg; reg 302 drivers/spi/spi-bcm63xx-hsspi.c reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); reg 303 drivers/spi/spi-bcm63xx-hsspi.c reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK; reg 304 drivers/spi/spi-bcm63xx-hsspi.c reg |= bs->cs_polarity; reg 305 drivers/spi/spi-bcm63xx-hsspi.c __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); reg 337 drivers/spi/spi-bcm63xx-hsspi.c u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS; reg 420 drivers/spi/spi-bcm63xx-hsspi.c reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); reg 421 drivers/spi/spi-bcm63xx-hsspi.c bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK; reg 422 drivers/spi/spi-bcm63xx-hsspi.c __raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF, reg 199 drivers/spi/spi-bcm63xx.c u8 clk_cfg, reg; reg 214 drivers/spi/spi-bcm63xx.c reg = bcm_spi_readb(bs, SPI_CLK_CFG); reg 215 drivers/spi/spi-bcm63xx.c reg &= ~SPI_CLK_MASK; reg 216 drivers/spi/spi-bcm63xx.c reg |= clk_cfg; reg 218 drivers/spi/spi-bcm63xx.c bcm_spi_writeb(bs, reg, SPI_CLK_CFG); reg 282 drivers/spi/spi-efm32.c u32 reg = efm32_spi_read32(ddata, REG_ROUTE); reg 284 drivers/spi/spi-efm32.c return (reg & REG_ROUTE_LOCATION__MASK) >> __ffs(REG_ROUTE_LOCATION__MASK); reg 60 drivers/spi/spi-fsl-espi.c #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F) reg 61 drivers/spi/spi-fsl-espi.c #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F) reg 82 drivers/spi/spi-fsl-lib.h static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val) reg 84 drivers/spi/spi-fsl-lib.h iowrite32be(val, reg); reg 87 drivers/spi/spi-fsl-lib.h static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg) reg 89 drivers/spi/spi-fsl-lib.h return ioread32be(reg); reg 331 drivers/spi/spi-fsl-qspi.c u32 reg; reg 334 drivers/spi/spi-fsl-qspi.c reg = qspi_readl(q, q->iobase + QUADSPI_FR); reg 335 drivers/spi/spi-fsl-qspi.c qspi_writel(q, reg, q->iobase + QUADSPI_FR); reg 337 drivers/spi/spi-fsl-qspi.c if (reg & QUADSPI_FR_TFF_MASK) reg 340 drivers/spi/spi-fsl-qspi.c dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg); reg 498 drivers/spi/spi-fsl-qspi.c u32 reg; reg 500 drivers/spi/spi-fsl-qspi.c reg = qspi_readl(q, q->iobase + QUADSPI_MCR); reg 501 drivers/spi/spi-fsl-qspi.c reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK; reg 502 drivers/spi/spi-fsl-qspi.c qspi_writel(q, reg, q->iobase + QUADSPI_MCR); reg 510 drivers/spi/spi-fsl-qspi.c reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK); reg 511 drivers/spi/spi-fsl-qspi.c qspi_writel(q, reg, q->iobase + QUADSPI_MCR); reg 621 drivers/spi/spi-fsl-qspi.c u32 reg; reg 626 drivers/spi/spi-fsl-qspi.c return readl_poll_timeout(base, reg, !(reg & mask), delay_us, reg 707 drivers/spi/spi-fsl-qspi.c u32 reg, addr_offset = 0; reg 741 drivers/spi/spi-fsl-qspi.c reg = qspi_readl(q, base + QUADSPI_SMPR); reg 742 drivers/spi/spi-fsl-qspi.c qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK reg 109 drivers/spi/spi-img-spfi.c static inline u32 spfi_readl(struct img_spfi *spfi, u32 reg) reg 111 drivers/spi/spi-img-spfi.c return readl(spfi->regs + reg); reg 114 drivers/spi/spi-img-spfi.c static inline void spfi_writel(struct img_spfi *spfi, u32 val, u32 reg) reg 116 drivers/spi/spi-img-spfi.c writel(val, spfi->regs + reg); reg 481 drivers/spi/spi-imx.c u32 reg; reg 483 drivers/spi/spi-imx.c reg = readl(spi_imx->base + MX51_ECSPI_CTRL); reg 484 drivers/spi/spi-imx.c reg |= MX51_ECSPI_CTRL_XCH; reg 485 drivers/spi/spi-imx.c writel(reg, spi_imx->base + MX51_ECSPI_CTRL); reg 683 drivers/spi/spi-imx.c unsigned int reg; reg 685 drivers/spi/spi-imx.c reg = readl(spi_imx->base + MXC_CSPICTRL); reg 686 drivers/spi/spi-imx.c reg |= MX31_CSPICTRL_XCH; reg 687 drivers/spi/spi-imx.c writel(reg, spi_imx->base + MXC_CSPICTRL); reg 700 drivers/spi/spi-imx.c unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; reg 703 drivers/spi/spi-imx.c reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) << reg 708 drivers/spi/spi-imx.c reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT; reg 709 drivers/spi/spi-imx.c reg |= MX31_CSPICTRL_SSCTL; reg 711 drivers/spi/spi-imx.c reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT; reg 715 drivers/spi/spi-imx.c reg |= MX31_CSPICTRL_PHA; reg 717 drivers/spi/spi-imx.c reg |= MX31_CSPICTRL_POL; reg 719 drivers/spi/spi-imx.c reg |= MX31_CSPICTRL_SSPOL; reg 721 drivers/spi/spi-imx.c reg |= (spi->chip_select) << reg 726 drivers/spi/spi-imx.c reg |= MX31_CSPICTRL_SMC; reg 728 drivers/spi/spi-imx.c writel(reg, spi_imx->base + MXC_CSPICTRL); reg 730 drivers/spi/spi-imx.c reg = readl(spi_imx->base + MX31_CSPI_TESTREG); reg 732 drivers/spi/spi-imx.c reg |= MX31_TEST_LBC; reg 734 drivers/spi/spi-imx.c reg &= ~MX31_TEST_LBC; reg 735 drivers/spi/spi-imx.c writel(reg, spi_imx->base + MX31_CSPI_TESTREG); reg 788 drivers/spi/spi-imx.c unsigned int reg; reg 790 drivers/spi/spi-imx.c reg = readl(spi_imx->base + MXC_CSPICTRL); reg 791 drivers/spi/spi-imx.c reg |= MX21_CSPICTRL_XCH; reg 792 drivers/spi/spi-imx.c writel(reg, spi_imx->base + MXC_CSPICTRL); reg 805 drivers/spi/spi-imx.c unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; reg 809 drivers/spi/spi-imx.c reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, t->speed_hz, max, &clk) reg 813 drivers/spi/spi-imx.c reg |= spi_imx->bits_per_word - 1; reg 816 drivers/spi/spi-imx.c reg |= MX21_CSPICTRL_PHA; reg 818 drivers/spi/spi-imx.c reg |= MX21_CSPICTRL_POL; reg 820 drivers/spi/spi-imx.c reg |= MX21_CSPICTRL_SSPOL; reg 822 drivers/spi/spi-imx.c reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT; reg 824 drivers/spi/spi-imx.c writel(reg, spi_imx->base + MXC_CSPICTRL); reg 864 drivers/spi/spi-imx.c unsigned int reg; reg 866 drivers/spi/spi-imx.c reg = readl(spi_imx->base + MXC_CSPICTRL); reg 867 drivers/spi/spi-imx.c reg |= MX1_CSPICTRL_XCH; reg 868 drivers/spi/spi-imx.c writel(reg, spi_imx->base + MXC_CSPICTRL); reg 881 drivers/spi/spi-imx.c unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; reg 884 drivers/spi/spi-imx.c reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) << reg 888 drivers/spi/spi-imx.c reg |= spi_imx->bits_per_word - 1; reg 891 drivers/spi/spi-imx.c reg |= MX1_CSPICTRL_PHA; reg 893 drivers/spi/spi-imx.c reg |= MX1_CSPICTRL_POL; reg 895 drivers/spi/spi-imx.c writel(reg, spi_imx->base + MXC_CSPICTRL); reg 189 drivers/spi/spi-lantiq-ssc.c static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg) reg 191 drivers/spi/spi-lantiq-ssc.c return __raw_readl(spi->regbase + reg); reg 195 drivers/spi/spi-lantiq-ssc.c u32 reg) reg 197 drivers/spi/spi-lantiq-ssc.c __raw_writel(val, spi->regbase + reg); reg 201 drivers/spi/spi-lantiq-ssc.c u32 set, u32 reg) reg 203 drivers/spi/spi-lantiq-ssc.c u32 val = __raw_readl(spi->regbase + reg); reg 207 drivers/spi/spi-lantiq-ssc.c __raw_writel(val, spi->regbase + reg); reg 67 drivers/spi/spi-mt7621.c static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg) reg 69 drivers/spi/spi-mt7621.c return ioread32(rs->base + reg); reg 72 drivers/spi/spi-mt7621.c static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val) reg 74 drivers/spi/spi-mt7621.c iowrite32(val, rs->base + reg); reg 105 drivers/spi/spi-mt7621.c u32 reg; reg 118 drivers/spi/spi-mt7621.c reg = mt7621_spi_read(rs, MT7621_SPI_MASTER); reg 119 drivers/spi/spi-mt7621.c reg &= ~MASTER_RS_CLK_SEL; reg 120 drivers/spi/spi-mt7621.c reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT; reg 123 drivers/spi/spi-mt7621.c reg &= ~MT7621_LSB_FIRST; reg 125 drivers/spi/spi-mt7621.c reg |= MT7621_LSB_FIRST; reg 132 drivers/spi/spi-mt7621.c reg &= ~(MT7621_CPHA | MT7621_CPOL); reg 134 drivers/spi/spi-mt7621.c mt7621_spi_write(rs, MT7621_SPI_MASTER, reg); reg 129 drivers/spi/spi-mxs.c u32 reg; reg 132 drivers/spi/spi-mxs.c reg = readl_relaxed(ssp->base + offset); reg 135 drivers/spi/spi-mxs.c reg = ~reg; reg 137 drivers/spi/spi-mxs.c reg &= mask; reg 139 drivers/spi/spi-mxs.c if (reg == mask) reg 367 drivers/spi/spi-nxp-fspi.c u32 reg; reg 370 drivers/spi/spi-nxp-fspi.c reg = fspi_readl(f, f->iobase + FSPI_INTR); reg 373 drivers/spi/spi-nxp-fspi.c if (reg & FSPI_INTR_IPCMDDONE) reg 450 drivers/spi/spi-nxp-fspi.c u32 reg; reg 456 drivers/spi/spi-nxp-fspi.c return readl_poll_timeout(base, reg, (reg & mask), reg 459 drivers/spi/spi-nxp-fspi.c return readl_poll_timeout(base, reg, !(reg & mask), reg 470 drivers/spi/spi-nxp-fspi.c u32 reg; reg 473 drivers/spi/spi-nxp-fspi.c reg = fspi_readl(f, f->iobase + FSPI_MCR0); reg 474 drivers/spi/spi-nxp-fspi.c fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0); reg 752 drivers/spi/spi-nxp-fspi.c u32 reg; reg 754 drivers/spi/spi-nxp-fspi.c reg = fspi_readl(f, base + FSPI_IPRXFCR); reg 756 drivers/spi/spi-nxp-fspi.c reg &= ~FSPI_IPRXFCR_DMA_EN; reg 757 drivers/spi/spi-nxp-fspi.c reg = reg | FSPI_IPRXFCR_CLR; reg 758 drivers/spi/spi-nxp-fspi.c fspi_writel(f, reg, base + FSPI_IPRXFCR); reg 846 drivers/spi/spi-nxp-fspi.c u32 reg; reg 881 drivers/spi/spi-nxp-fspi.c reg = fspi_readl(f, f->iobase + FSPI_MCR2); reg 882 drivers/spi/spi-nxp-fspi.c reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN); reg 883 drivers/spi/spi-nxp-fspi.c fspi_writel(f, reg, base + FSPI_MCR2); reg 121 drivers/spi/spi-omap-uwire.c int shift, reg; reg 131 drivers/spi/spi-omap-uwire.c reg = UWIRE_SR1; reg 133 drivers/spi/spi-omap-uwire.c reg = UWIRE_SR2; reg 135 drivers/spi/spi-omap-uwire.c w = uwire_read_reg(reg); reg 138 drivers/spi/spi-omap-uwire.c uwire_write_reg(reg, w); reg 349 drivers/spi/spi-omap2-mcspi.c static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) reg 353 drivers/spi/spi-omap2-mcspi.c return readl_poll_timeout(reg, val, val & bit, 1, MSEC_PER_SEC); reg 106 drivers/spi/spi-orion.c static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg) reg 108 drivers/spi/spi-orion.c return orion_spi->base + reg; reg 112 drivers/spi/spi-orion.c orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask) reg 114 drivers/spi/spi-orion.c void __iomem *reg_addr = spi_reg(orion_spi, reg); reg 123 drivers/spi/spi-orion.c orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask) reg 125 drivers/spi/spi-orion.c void __iomem *reg_addr = spi_reg(orion_spi, reg); reg 138 drivers/spi/spi-orion.c u32 reg; reg 223 drivers/spi/spi-orion.c reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); reg 224 drivers/spi/spi-orion.c reg = ((reg & ~devdata->prescale_mask) | prescale); reg 225 drivers/spi/spi-orion.c writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); reg 233 drivers/spi/spi-orion.c u32 reg; reg 238 drivers/spi/spi-orion.c reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); reg 239 drivers/spi/spi-orion.c reg &= ~ORION_SPI_MODE_MASK; reg 241 drivers/spi/spi-orion.c reg |= ORION_SPI_MODE_CPOL; reg 243 drivers/spi/spi-orion.c reg |= ORION_SPI_MODE_CPHA; reg 245 drivers/spi/spi-orion.c reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF; reg 247 drivers/spi/spi-orion.c reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF); reg 249 drivers/spi/spi-orion.c writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); reg 255 drivers/spi/spi-orion.c u32 reg; reg 274 drivers/spi/spi-orion.c reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG)); reg 275 drivers/spi/spi-orion.c reg &= ~ORION_SPI_TMISO_SAMPLE_MASK; reg 280 drivers/spi/spi-orion.c reg |= ORION_SPI_TMISO_SAMPLE_2; reg 282 drivers/spi/spi-orion.c reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */ reg 284 drivers/spi/spi-orion.c writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG)); reg 155 drivers/spi/spi-pic32-sqi.c static inline void pic32_setbits(void __iomem *reg, u32 set) reg 157 drivers/spi/spi-pic32-sqi.c writel(readl(reg) | set, reg); reg 160 drivers/spi/spi-pic32-sqi.c static inline void pic32_clrbits(void __iomem *reg, u32 clr) reg 162 drivers/spi/spi-pic32-sqi.c writel(readl(reg) & ~clr, reg); reg 43 drivers/spi/spi-pl022.c #define SSP_WRITE_BITS(reg, val, mask, sb) \ reg 44 drivers/spi/spi-pl022.c ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) reg 91 drivers/spi/spi-pxa2xx.h unsigned reg) reg 93 drivers/spi/spi-pxa2xx.h return __raw_readl(drv_data->ioaddr + reg); reg 97 drivers/spi/spi-pxa2xx.h unsigned reg, u32 val) reg 99 drivers/spi/spi-pxa2xx.h __raw_writel(val, drv_data->ioaddr + reg); reg 25 drivers/spi/spi-rb4xx.c static inline u32 rb4xx_read(struct rb4xx_spi *rbspi, u32 reg) reg 27 drivers/spi/spi-rb4xx.c return __raw_readl(rbspi->base + reg); reg 30 drivers/spi/spi-rb4xx.c static inline void rb4xx_write(struct rb4xx_spi *rbspi, u32 reg, u32 value) reg 32 drivers/spi/spi-rb4xx.c __raw_writel(value, rbspi->base + reg); reg 20 drivers/spi/spi-rockchip.c #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \ reg 21 drivers/spi/spi-rockchip.c writel_relaxed(readl_relaxed(reg) & ~(bits), reg) reg 22 drivers/spi/spi-rockchip.c #define ROCKCHIP_SPI_SET_BITS(reg, bits) \ reg 23 drivers/spi/spi-rockchip.c writel_relaxed(readl_relaxed(reg) | (bits), reg) reg 381 drivers/spi/spi-rspi.c static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg) reg 385 drivers/spi/spi-rspi.c data = rspi_read8(rspi, reg); reg 388 drivers/spi/spi-rspi.c rspi_write8(rspi, data, reg); reg 46 drivers/spi/spi-sh-hspi.c static void hspi_write(struct hspi_priv *hspi, int reg, u32 val) reg 48 drivers/spi/spi-sh-hspi.c iowrite32(val, hspi->addr + reg); reg 51 drivers/spi/spi-sh-hspi.c static u32 hspi_read(struct hspi_priv *hspi, int reg) reg 53 drivers/spi/spi-sh-hspi.c return ioread32(hspi->addr + reg); reg 56 drivers/spi/spi-sh-hspi.c static void hspi_bit_set(struct hspi_priv *hspi, int reg, u32 mask, u32 set) reg 58 drivers/spi/spi-sh-hspi.c u32 val = hspi_read(hspi, reg); reg 63 drivers/spi/spi-sh-hspi.c hspi_write(hspi, reg, val); reg 231 drivers/spi/spi-sprd-adi.c unsigned long reg = sprd_adi_to_vaddr(sadi, reg_paddr); reg 256 drivers/spi/spi-sprd-adi.c writel_relaxed(val, (void __iomem *)reg); reg 185 drivers/spi/spi-stm32.c int reg; reg 642 drivers/spi/spi-stm32.c stm32_spi_set_bits(spi, spi->cfg->regs->en.reg, reg 1042 drivers/spi/spi-stm32.c (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) & reg 1044 drivers/spi/spi-stm32.c spi->base + spi->cfg->regs->cpol.reg); reg 1134 drivers/spi/spi-stm32.c dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg; reg 1141 drivers/spi/spi-stm32.c dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg; reg 1289 drivers/spi/spi-stm32.c stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg, reg 1345 drivers/spi/spi-stm32.c stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg, reg 1360 drivers/spi/spi-stm32.c stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg, reg 1424 drivers/spi/spi-stm32.c writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) & reg 1426 drivers/spi/spi-stm32.c spi->base + spi->cfg->regs->br.reg); reg 90 drivers/spi/spi-sun4i.c static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg) reg 92 drivers/spi/spi-sun4i.c return readl(sspi->base_addr + reg); reg 95 drivers/spi/spi-sun4i.c static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value) reg 97 drivers/spi/spi-sun4i.c writel(value, sspi->base_addr + reg); reg 102 drivers/spi/spi-sun4i.c u32 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG); reg 104 drivers/spi/spi-sun4i.c reg >>= SUN4I_FIFO_STA_TF_CNT_BITS; reg 106 drivers/spi/spi-sun4i.c return reg & SUN4I_FIFO_STA_TF_CNT_MASK; reg 111 drivers/spi/spi-sun4i.c u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG); reg 113 drivers/spi/spi-sun4i.c reg |= mask; reg 114 drivers/spi/spi-sun4i.c sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg); reg 119 drivers/spi/spi-sun4i.c u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG); reg 121 drivers/spi/spi-sun4i.c reg &= ~mask; reg 122 drivers/spi/spi-sun4i.c sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg); reg 127 drivers/spi/spi-sun4i.c u32 reg, cnt; reg 131 drivers/spi/spi-sun4i.c reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG); reg 132 drivers/spi/spi-sun4i.c reg &= SUN4I_FIFO_STA_RF_CNT_MASK; reg 133 drivers/spi/spi-sun4i.c cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS; reg 165 drivers/spi/spi-sun4i.c u32 reg; reg 167 drivers/spi/spi-sun4i.c reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); reg 169 drivers/spi/spi-sun4i.c reg &= ~SUN4I_CTL_CS_MASK; reg 170 drivers/spi/spi-sun4i.c reg |= SUN4I_CTL_CS(spi->chip_select); reg 173 drivers/spi/spi-sun4i.c reg |= SUN4I_CTL_CS_MANUAL; reg 176 drivers/spi/spi-sun4i.c reg |= SUN4I_CTL_CS_LEVEL; reg 178 drivers/spi/spi-sun4i.c reg &= ~SUN4I_CTL_CS_LEVEL; reg 192 drivers/spi/spi-sun4i.c reg &= ~SUN4I_CTL_CS_ACTIVE_LOW; reg 194 drivers/spi/spi-sun4i.c reg |= SUN4I_CTL_CS_ACTIVE_LOW; reg 196 drivers/spi/spi-sun4i.c sun4i_spi_write(sspi, SUN4I_CTL_REG, reg); reg 213 drivers/spi/spi-sun4i.c u32 reg; reg 231 drivers/spi/spi-sun4i.c reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); reg 235 drivers/spi/spi-sun4i.c reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST); reg 242 drivers/spi/spi-sun4i.c reg |= SUN4I_CTL_CPOL; reg 244 drivers/spi/spi-sun4i.c reg &= ~SUN4I_CTL_CPOL; reg 247 drivers/spi/spi-sun4i.c reg |= SUN4I_CTL_CPHA; reg 249 drivers/spi/spi-sun4i.c reg &= ~SUN4I_CTL_CPHA; reg 252 drivers/spi/spi-sun4i.c reg |= SUN4I_CTL_LMTF; reg 254 drivers/spi/spi-sun4i.c reg &= ~SUN4I_CTL_LMTF; reg 262 drivers/spi/spi-sun4i.c reg &= ~SUN4I_CTL_DHB; reg 264 drivers/spi/spi-sun4i.c reg |= SUN4I_CTL_DHB; reg 266 drivers/spi/spi-sun4i.c sun4i_spi_write(sspi, SUN4I_CTL_REG, reg); reg 294 drivers/spi/spi-sun4i.c reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; reg 297 drivers/spi/spi-sun4i.c reg = SUN4I_CLK_CTL_CDR1(div); reg 300 drivers/spi/spi-sun4i.c sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg); reg 325 drivers/spi/spi-sun4i.c reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); reg 326 drivers/spi/spi-sun4i.c sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH); reg 102 drivers/spi/spi-sun6i.c static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg) reg 104 drivers/spi/spi-sun6i.c return readl(sspi->base_addr + reg); reg 107 drivers/spi/spi-sun6i.c static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) reg 109 drivers/spi/spi-sun6i.c writel(value, sspi->base_addr + reg); reg 114 drivers/spi/spi-sun6i.c u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); reg 116 drivers/spi/spi-sun6i.c reg >>= SUN6I_FIFO_STA_TF_CNT_BITS; reg 118 drivers/spi/spi-sun6i.c return reg & SUN6I_FIFO_STA_TF_CNT_MASK; reg 123 drivers/spi/spi-sun6i.c u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); reg 125 drivers/spi/spi-sun6i.c reg |= mask; reg 126 drivers/spi/spi-sun6i.c sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); reg 131 drivers/spi/spi-sun6i.c u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); reg 133 drivers/spi/spi-sun6i.c reg &= ~mask; reg 134 drivers/spi/spi-sun6i.c sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); reg 139 drivers/spi/spi-sun6i.c u32 reg, cnt; reg 143 drivers/spi/spi-sun6i.c reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); reg 144 drivers/spi/spi-sun6i.c reg &= SUN6I_FIFO_STA_RF_CNT_MASK; reg 145 drivers/spi/spi-sun6i.c cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS; reg 177 drivers/spi/spi-sun6i.c u32 reg; reg 179 drivers/spi/spi-sun6i.c reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); reg 180 drivers/spi/spi-sun6i.c reg &= ~SUN6I_TFR_CTL_CS_MASK; reg 181 drivers/spi/spi-sun6i.c reg |= SUN6I_TFR_CTL_CS(spi->chip_select); reg 184 drivers/spi/spi-sun6i.c reg |= SUN6I_TFR_CTL_CS_LEVEL; reg 186 drivers/spi/spi-sun6i.c reg &= ~SUN6I_TFR_CTL_CS_LEVEL; reg 188 drivers/spi/spi-sun6i.c sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); reg 206 drivers/spi/spi-sun6i.c u32 reg; reg 238 drivers/spi/spi-sun6i.c reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); reg 241 drivers/spi/spi-sun6i.c reg |= SUN6I_TFR_CTL_CPOL; reg 243 drivers/spi/spi-sun6i.c reg &= ~SUN6I_TFR_CTL_CPOL; reg 246 drivers/spi/spi-sun6i.c reg |= SUN6I_TFR_CTL_CPHA; reg 248 drivers/spi/spi-sun6i.c reg &= ~SUN6I_TFR_CTL_CPHA; reg 251 drivers/spi/spi-sun6i.c reg |= SUN6I_TFR_CTL_FBS; reg 253 drivers/spi/spi-sun6i.c reg &= ~SUN6I_TFR_CTL_FBS; reg 260 drivers/spi/spi-sun6i.c reg &= ~SUN6I_TFR_CTL_DHB; reg 262 drivers/spi/spi-sun6i.c reg |= SUN6I_TFR_CTL_DHB; reg 265 drivers/spi/spi-sun6i.c reg |= SUN6I_TFR_CTL_CS_MANUAL; reg 267 drivers/spi/spi-sun6i.c sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); reg 295 drivers/spi/spi-sun6i.c reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS; reg 298 drivers/spi/spi-sun6i.c reg = SUN6I_CLK_CTL_CDR1(div); reg 301 drivers/spi/spi-sun6i.c sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); reg 324 drivers/spi/spi-sun6i.c reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); reg 325 drivers/spi/spi-sun6i.c sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH); reg 70 drivers/spi/spi-tegra114.c #define SPI_CS_SETUP_HOLD(reg, cs, val) \ reg 72 drivers/spi/spi-tegra114.c ((reg) & ~(0xFFu << ((cs) * 8)))) reg 83 drivers/spi/spi-tegra114.c #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val) \ reg 84 drivers/spi/spi-tegra114.c (reg = (((val) & 0x1) << ((cs) * 8 + 5)) | \ reg 85 drivers/spi/spi-tegra114.c ((reg) & ~(1 << ((cs) * 8 + 5)))) reg 86 drivers/spi/spi-tegra114.c #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) \ reg 87 drivers/spi/spi-tegra114.c (reg = (((val) & 0x1F) << ((cs) * 8)) | \ reg 88 drivers/spi/spi-tegra114.c ((reg) & ~(0x1F << ((cs) * 8)))) reg 228 drivers/spi/spi-tegra114.c unsigned long reg) reg 230 drivers/spi/spi-tegra114.c return readl(tspi->base + reg); reg 234 drivers/spi/spi-tegra114.c u32 val, unsigned long reg) reg 236 drivers/spi/spi-tegra114.c writel(val, tspi->base + reg); reg 239 drivers/spi/spi-tegra114.c if (reg != SPI_TX_FIFO) reg 140 drivers/spi/spi-tegra20-sflash.c unsigned long reg) reg 142 drivers/spi/spi-tegra20-sflash.c return readl(tsd->base + reg); reg 146 drivers/spi/spi-tegra20-sflash.c u32 val, unsigned long reg) reg 148 drivers/spi/spi-tegra20-sflash.c writel(val, tsd->base + reg); reg 211 drivers/spi/spi-tegra20-slink.c unsigned long reg) reg 213 drivers/spi/spi-tegra20-slink.c return readl(tspi->base + reg); reg 217 drivers/spi/spi-tegra20-slink.c u32 val, unsigned long reg) reg 219 drivers/spi/spi-tegra20-slink.c writel(val, tspi->base + reg); reg 222 drivers/spi/spi-tegra20-slink.c if (reg != SLINK_TX_FIFO) reg 131 drivers/spi/spi-ti-qspi.c unsigned long reg) reg 133 drivers/spi/spi-ti-qspi.c return readl(qspi->base + reg); reg 137 drivers/spi/spi-ti-qspi.c unsigned long val, unsigned long reg) reg 139 drivers/spi/spi-ti-qspi.c writel(val, qspi->base + reg); reg 86 drivers/spi/spi-txx9.c static u32 txx9spi_rd(struct txx9spi *c, int reg) reg 88 drivers/spi/spi-txx9.c return __raw_readl(c->membase + reg); reg 90 drivers/spi/spi-txx9.c static void txx9spi_wr(struct txx9spi *c, u32 val, int reg) reg 92 drivers/spi/spi-txx9.c __raw_writel(val, c->membase + reg); reg 47 drivers/spmi/spmi-pmic-arb.c #define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg) ((reg) & BIT(24)) reg 220 drivers/spmi/spmi-pmic-arb.c pmic_arb_read_data(struct spmi_pmic_arb *pmic_arb, u8 *buf, u32 reg, u8 bc) reg 222 drivers/spmi/spmi-pmic-arb.c u32 data = __raw_readl(pmic_arb->rd_base + reg); reg 234 drivers/spmi/spmi-pmic-arb.c u32 reg, u8 bc) reg 239 drivers/spmi/spmi-pmic-arb.c __raw_writel(data, pmic_arb->wr_base + reg); reg 460 drivers/spmi/spmi-pmic-arb.c static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf, reg 468 drivers/spmi/spmi-pmic-arb.c (per << 8) + reg, buf, len)) reg 473 drivers/spmi/spmi-pmic-arb.c static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len) reg 480 drivers/spmi/spmi-pmic-arb.c (per << 8) + reg, buf, len)) reg 459 drivers/spmi/spmi.c u32 reg[2]; reg 463 drivers/spmi/spmi.c err = of_property_read_u32_array(node, "reg", reg, 2); reg 471 drivers/spmi/spmi.c if (reg[1] != SPMI_USID) { reg 478 drivers/spmi/spmi.c if (reg[0] >= SPMI_MAX_SLAVE_ID) { reg 483 drivers/spmi/spmi.c dev_dbg(&ctrl->dev, "read usid %02x\n", reg[0]); reg 490 drivers/spmi/spmi.c sdev->usid = (u8) reg[0]; reg 111 drivers/ssb/driver_gige.c int reg, int size, u32 *val) reg 118 drivers/ssb/driver_gige.c if (reg >= 256) reg 124 drivers/ssb/driver_gige.c *val = gige_pcicfg_read8(dev, reg); reg 127 drivers/ssb/driver_gige.c *val = gige_pcicfg_read16(dev, reg); reg 130 drivers/ssb/driver_gige.c *val = gige_pcicfg_read32(dev, reg); reg 141 drivers/ssb/driver_gige.c int reg, int size, u32 val) reg 148 drivers/ssb/driver_gige.c if (reg >= 256) reg 154 drivers/ssb/driver_gige.c gige_pcicfg_write8(dev, reg, val); reg 157 drivers/ssb/driver_gige.c gige_pcicfg_write16(dev, reg, val); reg 160 drivers/ssb/driver_gige.c gige_pcicfg_write32(dev, reg, val); reg 205 drivers/ssb/driver_pcicore.c int reg, int size, u32 *val) reg 212 drivers/ssb/driver_pcicore.c PCI_FUNC(devfn), reg, val, size); reg 219 drivers/ssb/driver_pcicore.c int reg, int size, u32 val) reg 226 drivers/ssb/driver_pcicore.c PCI_FUNC(devfn), reg, &val, size); reg 1048 drivers/ssb/main.c static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask, reg 1055 drivers/ssb/main.c val = ssb_read32(dev, reg); reg 1067 drivers/ssb/main.c bitmask, reg, set ? "set" : "clear"); reg 134 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c u32 reg; reg 187 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) & reg 189 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c reg |= readl(clk_wzrd->base + WZRD_CLK_CFG_REG(2)) & reg 191 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c if (reg) reg 195 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) & reg 205 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c 0, reg, 1); reg 214 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) & reg 225 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c 0, 1, reg); reg 243 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(2) + i * 12); reg 244 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c reg &= WZRD_CLKOUT_DIVIDE_MASK; reg 245 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c reg >>= WZRD_CLKOUT_DIVIDE_SHIFT; reg 247 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c (&pdev->dev, clkout_name, clk_name, 0, 1, reg); reg 55 drivers/staging/comedi/drivers/addi_apci_1500.c static unsigned int z8536_read(struct comedi_device *dev, unsigned int reg) reg 61 drivers/staging/comedi/drivers/addi_apci_1500.c outb(reg, dev->iobase + APCI1500_Z8536_CTRL_REG); reg 69 drivers/staging/comedi/drivers/addi_apci_1500.c unsigned int val, unsigned int reg) reg 74 drivers/staging/comedi/drivers/addi_apci_1500.c outb(reg, dev->iobase + APCI1500_Z8536_CTRL_REG); reg 191 drivers/staging/comedi/drivers/addi_apci_1500.c unsigned int reg) reg 195 drivers/staging/comedi/drivers/addi_apci_1500.c val = z8536_read(dev, reg); reg 199 drivers/staging/comedi/drivers/addi_apci_1500.c z8536_write(dev, val, reg); reg 158 drivers/staging/comedi/drivers/addi_apci_3120.c unsigned int val, unsigned int reg) reg 164 drivers/staging/comedi/drivers/addi_apci_3120.c outw(reg, devpriv->addon + APCI3120_ADDON_ADDR_REG); reg 167 drivers/staging/comedi/drivers/addi_apci_3120.c outw(reg + 2, devpriv->addon + APCI3120_ADDON_ADDR_REG); reg 112 drivers/staging/comedi/drivers/adl_pci7x3x.c unsigned long reg = (unsigned long)s->private; reg 126 drivers/staging/comedi/drivers/adl_pci7x3x.c outl(val, dev->iobase + reg); reg 139 drivers/staging/comedi/drivers/adl_pci7x3x.c unsigned long reg = (unsigned long)s->private; reg 141 drivers/staging/comedi/drivers/adl_pci7x3x.c data[1] = inl(dev->iobase + reg); reg 213 drivers/staging/comedi/drivers/adv_pci_dio.c unsigned long reg = (unsigned long)s->private; reg 214 drivers/staging/comedi/drivers/adv_pci_dio.c unsigned long iobase = dev->iobase + reg; reg 232 drivers/staging/comedi/drivers/adv_pci_dio.c unsigned long reg = (unsigned long)s->private; reg 233 drivers/staging/comedi/drivers/adv_pci_dio.c unsigned long iobase = dev->iobase + reg; reg 247 drivers/staging/comedi/drivers/adv_pci_dio.c unsigned long reg = (unsigned long)s->private; reg 248 drivers/staging/comedi/drivers/adv_pci_dio.c unsigned long iobase = dev->iobase + reg; reg 270 drivers/staging/comedi/drivers/adv_pci_dio.c unsigned long reg = (unsigned long)s->private; reg 271 drivers/staging/comedi/drivers/adv_pci_dio.c unsigned long iobase = dev->iobase + reg; reg 485 drivers/staging/comedi/drivers/adv_pci_dio.c unsigned long reg = pci_resource_start(pcidev, 2) + 53; reg 487 drivers/staging/comedi/drivers/adv_pci_dio.c outb(0x05, reg); reg 488 drivers/staging/comedi/drivers/adv_pci_dio.c if ((inb(reg) & 0x07) == 0x02) { reg 489 drivers/staging/comedi/drivers/adv_pci_dio.c outb(0x02, reg); reg 490 drivers/staging/comedi/drivers/adv_pci_dio.c if ((inb(reg) & 0x07) == 0x05) reg 124 drivers/staging/comedi/drivers/comedi_8254.c static unsigned int __i8254_read(struct comedi_8254 *i8254, unsigned int reg) reg 126 drivers/staging/comedi/drivers/comedi_8254.c unsigned int reg_offset = (reg * i8254->iosize) << i8254->regshift; reg 154 drivers/staging/comedi/drivers/comedi_8254.c unsigned int val, unsigned int reg) reg 156 drivers/staging/comedi/drivers/comedi_8254.c unsigned int reg_offset = (reg * i8254->iosize) << i8254->regshift; reg 212 drivers/staging/comedi/drivers/das800.c unsigned int val, unsigned int reg) reg 218 drivers/staging/comedi/drivers/das800.c outb(reg, dev->iobase + DAS800_GAIN); reg 222 drivers/staging/comedi/drivers/das800.c static unsigned int das800_ind_read(struct comedi_device *dev, unsigned int reg) reg 228 drivers/staging/comedi/drivers/das800.c outb(reg, dev->iobase + DAS800_GAIN); reg 325 drivers/staging/comedi/drivers/dt9812.c u8 reg[2] = { F020_SFR_P3, F020_SFR_P1 }; reg 330 drivers/staging/comedi/drivers/dt9812.c ret = dt9812_read_multiple_registers(dev, 2, reg, value); reg 347 drivers/staging/comedi/drivers/dt9812.c u8 reg[1] = { F020_SFR_P2 }; reg 352 drivers/staging/comedi/drivers/dt9812.c ret = dt9812_write_multiple_registers(dev, 1, reg, value); reg 430 drivers/staging/comedi/drivers/dt9812.c u8 reg[3] = { reg 456 drivers/staging/comedi/drivers/dt9812.c ret = dt9812_read_multiple_registers(dev, 3, reg, val); reg 272 drivers/staging/comedi/drivers/ni_660x.c unsigned int bits, unsigned int reg) reg 275 drivers/staging/comedi/drivers/ni_660x.c ni_660x_reg_data[reg].offset; reg 277 drivers/staging/comedi/drivers/ni_660x.c if (ni_660x_reg_data[reg].size == 2) reg 284 drivers/staging/comedi/drivers/ni_660x.c unsigned int chip, unsigned int reg) reg 287 drivers/staging/comedi/drivers/ni_660x.c ni_660x_reg_data[reg].offset; reg 289 drivers/staging/comedi/drivers/ni_660x.c if (ni_660x_reg_data[reg].size == 2) reg 295 drivers/staging/comedi/drivers/ni_660x.c enum ni_gpct_register reg) reg 299 drivers/staging/comedi/drivers/ni_660x.c ni_660x_write(dev, counter->chip_index, bits, reg); reg 303 drivers/staging/comedi/drivers/ni_660x.c enum ni_gpct_register reg) reg 307 drivers/staging/comedi/drivers/ni_660x.c return ni_660x_read(dev, counter->chip_index, reg); reg 757 drivers/staging/comedi/drivers/ni_660x.c int reg = -1; reg 761 drivers/staging/comedi/drivers/ni_660x.c reg = ni_660x_get_pfi_routing(dev, dest); reg 785 drivers/staging/comedi/drivers/ni_660x.c reg = ni_tio_get_routing(devpriv->counter_dev, dest); reg 792 drivers/staging/comedi/drivers/ni_660x.c if (reg >= 0) reg 793 drivers/staging/comedi/drivers/ni_660x.c return ni_find_route_source(CR_CHAN(reg), dest, reg 809 drivers/staging/comedi/drivers/ni_660x.c s8 reg = ni_route_to_register(CR_CHAN(src), dest, reg 812 drivers/staging/comedi/drivers/ni_660x.c if (reg < 0) reg 824 drivers/staging/comedi/drivers/ni_660x.c s8 reg = ni_route_to_register(CR_CHAN(src), dest, reg 828 drivers/staging/comedi/drivers/ni_660x.c if (reg < 0) reg 845 drivers/staging/comedi/drivers/ni_660x.c ni_660x_set_pfi_routing(dev, dest, reg); reg 880 drivers/staging/comedi/drivers/ni_660x.c reg | (src & ~CR_CHAN(-1))); reg 891 drivers/staging/comedi/drivers/ni_660x.c s8 reg = ni_route_to_register(CR_CHAN(src), CR_CHAN(dest), reg 894 drivers/staging/comedi/drivers/ni_660x.c if (reg < 0) reg 515 drivers/staging/comedi/drivers/ni_atmio16d.c unsigned int reg = (chan) ? DAC1_REG : DAC0_REG; reg 532 drivers/staging/comedi/drivers/ni_atmio16d.c outw(val, dev->iobase + reg); reg 46 drivers/staging/comedi/drivers/ni_labpc.h unsigned int (*read_byte)(struct comedi_device *dev, unsigned long reg); reg 48 drivers/staging/comedi/drivers/ni_labpc.h unsigned int byte, unsigned long reg); reg 82 drivers/staging/comedi/drivers/ni_labpc_common.c static unsigned int labpc_inb(struct comedi_device *dev, unsigned long reg) reg 84 drivers/staging/comedi/drivers/ni_labpc_common.c return inb(dev->iobase + reg); reg 88 drivers/staging/comedi/drivers/ni_labpc_common.c unsigned int byte, unsigned long reg) reg 90 drivers/staging/comedi/drivers/ni_labpc_common.c outb(byte, dev->iobase + reg); reg 93 drivers/staging/comedi/drivers/ni_labpc_common.c static unsigned int labpc_readb(struct comedi_device *dev, unsigned long reg) reg 95 drivers/staging/comedi/drivers/ni_labpc_common.c return readb(dev->mmio + reg); reg 99 drivers/staging/comedi/drivers/ni_labpc_common.c unsigned int byte, unsigned long reg) reg 101 drivers/staging/comedi/drivers/ni_labpc_common.c writeb(byte, dev->mmio + reg); reg 222 drivers/staging/comedi/drivers/ni_mio_common.c static void ni_writel(struct comedi_device *dev, unsigned int data, int reg) reg 225 drivers/staging/comedi/drivers/ni_mio_common.c writel(data, dev->mmio + reg); reg 227 drivers/staging/comedi/drivers/ni_mio_common.c outl(data, dev->iobase + reg); reg 230 drivers/staging/comedi/drivers/ni_mio_common.c static void ni_writew(struct comedi_device *dev, unsigned int data, int reg) reg 233 drivers/staging/comedi/drivers/ni_mio_common.c writew(data, dev->mmio + reg); reg 235 drivers/staging/comedi/drivers/ni_mio_common.c outw(data, dev->iobase + reg); reg 238 drivers/staging/comedi/drivers/ni_mio_common.c static void ni_writeb(struct comedi_device *dev, unsigned int data, int reg) reg 241 drivers/staging/comedi/drivers/ni_mio_common.c writeb(data, dev->mmio + reg); reg 243 drivers/staging/comedi/drivers/ni_mio_common.c outb(data, dev->iobase + reg); reg 246 drivers/staging/comedi/drivers/ni_mio_common.c static unsigned int ni_readl(struct comedi_device *dev, int reg) reg 249 drivers/staging/comedi/drivers/ni_mio_common.c return readl(dev->mmio + reg); reg 251 drivers/staging/comedi/drivers/ni_mio_common.c return inl(dev->iobase + reg); reg 254 drivers/staging/comedi/drivers/ni_mio_common.c static unsigned int ni_readw(struct comedi_device *dev, int reg) reg 257 drivers/staging/comedi/drivers/ni_mio_common.c return readw(dev->mmio + reg); reg 259 drivers/staging/comedi/drivers/ni_mio_common.c return inw(dev->iobase + reg); reg 262 drivers/staging/comedi/drivers/ni_mio_common.c static unsigned int ni_readb(struct comedi_device *dev, int reg) reg 265 drivers/staging/comedi/drivers/ni_mio_common.c return readb(dev->mmio + reg); reg 267 drivers/staging/comedi/drivers/ni_mio_common.c return inb(dev->iobase + reg); reg 364 drivers/staging/comedi/drivers/ni_mio_common.c unsigned int data, unsigned int reg) reg 368 drivers/staging/comedi/drivers/ni_mio_common.c if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) { reg 369 drivers/staging/comedi/drivers/ni_mio_common.c regmap = &m_series_stc_write_regmap[reg]; reg 372 drivers/staging/comedi/drivers/ni_mio_common.c __func__, reg); reg 385 drivers/staging/comedi/drivers/ni_mio_common.c __func__, reg); reg 412 drivers/staging/comedi/drivers/ni_mio_common.c unsigned int reg) reg 416 drivers/staging/comedi/drivers/ni_mio_common.c if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) { reg 417 drivers/staging/comedi/drivers/ni_mio_common.c regmap = &m_series_stc_read_regmap[reg]; reg 420 drivers/staging/comedi/drivers/ni_mio_common.c __func__, reg); reg 433 drivers/staging/comedi/drivers/ni_mio_common.c __func__, reg); reg 439 drivers/staging/comedi/drivers/ni_mio_common.c unsigned int data, int reg) reg 445 drivers/staging/comedi/drivers/ni_mio_common.c m_series_stc_write(dev, data, reg); reg 448 drivers/staging/comedi/drivers/ni_mio_common.c if (!devpriv->mite && reg < 8) { reg 449 drivers/staging/comedi/drivers/ni_mio_common.c ni_writew(dev, data, reg * 2); reg 451 drivers/staging/comedi/drivers/ni_mio_common.c ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG); reg 459 drivers/staging/comedi/drivers/ni_mio_common.c unsigned int data, int reg) reg 464 drivers/staging/comedi/drivers/ni_mio_common.c m_series_stc_write(dev, data, reg); reg 466 drivers/staging/comedi/drivers/ni_mio_common.c ni_stc_writew(dev, data >> 16, reg); reg 467 drivers/staging/comedi/drivers/ni_mio_common.c ni_stc_writew(dev, data & 0xffff, reg + 1); reg 471 drivers/staging/comedi/drivers/ni_mio_common.c static unsigned int ni_stc_readw(struct comedi_device *dev, int reg) reg 478 drivers/staging/comedi/drivers/ni_mio_common.c val = m_series_stc_read(dev, reg); reg 481 drivers/staging/comedi/drivers/ni_mio_common.c if (!devpriv->mite && reg < 8) { reg 482 drivers/staging/comedi/drivers/ni_mio_common.c val = ni_readw(dev, reg * 2); reg 484 drivers/staging/comedi/drivers/ni_mio_common.c ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG); reg 492 drivers/staging/comedi/drivers/ni_mio_common.c static unsigned int ni_stc_readl(struct comedi_device *dev, int reg) reg 498 drivers/staging/comedi/drivers/ni_mio_common.c val = m_series_stc_read(dev, reg); reg 500 drivers/staging/comedi/drivers/ni_mio_common.c val = ni_stc_readw(dev, reg) << 16; reg 501 drivers/staging/comedi/drivers/ni_mio_common.c val |= ni_stc_readw(dev, reg + 1); reg 506 drivers/staging/comedi/drivers/ni_mio_common.c static inline void ni_set_bitfield(struct comedi_device *dev, int reg, reg 514 drivers/staging/comedi/drivers/ni_mio_common.c switch (reg) { reg 518 drivers/staging/comedi/drivers/ni_mio_common.c ni_stc_writew(dev, devpriv->int_a_enable_reg, reg); reg 523 drivers/staging/comedi/drivers/ni_mio_common.c ni_stc_writew(dev, devpriv->int_b_enable_reg, reg); reg 528 drivers/staging/comedi/drivers/ni_mio_common.c ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg); reg 533 drivers/staging/comedi/drivers/ni_mio_common.c ni_writeb(dev, devpriv->ai_ao_select_reg, reg); reg 538 drivers/staging/comedi/drivers/ni_mio_common.c ni_writeb(dev, devpriv->g0_g1_select_reg, reg); reg 543 drivers/staging/comedi/drivers/ni_mio_common.c ni_writeb(dev, devpriv->cdio_dma_select_reg, reg); reg 547 drivers/staging/comedi/drivers/ni_mio_common.c reg); reg 754 drivers/staging/comedi/drivers/ni_mio_common.c int reg; reg 764 drivers/staging/comedi/drivers/ni_mio_common.c reg = NISTC_INTA2_ENA_REG; reg 768 drivers/staging/comedi/drivers/ni_mio_common.c reg = NISTC_INTB2_ENA_REG; reg 772 drivers/staging/comedi/drivers/ni_mio_common.c ni_stc_writew(dev, val, reg); reg 863 drivers/staging/comedi/drivers/ni_mio_common.c static inline void ni_set_bits(struct comedi_device *dev, int reg, reg 872 drivers/staging/comedi/drivers/ni_mio_common.c ni_set_bitfield(dev, reg, bits, bit_values); reg 2685 drivers/staging/comedi/drivers/ni_mio_common.c int reg; reg 2691 drivers/staging/comedi/drivers/ni_mio_common.c reg = NI671X_DAC_DIRECT_DATA_REG(chan); reg 2693 drivers/staging/comedi/drivers/ni_mio_common.c reg = NI_M_DAC_DIRECT_DATA_REG(chan); reg 2695 drivers/staging/comedi/drivers/ni_mio_common.c reg = NI_E_DAC_DIRECT_DATA_REG(chan); reg 2712 drivers/staging/comedi/drivers/ni_mio_common.c ni_ao_win_outw(dev, val, reg); reg 2718 drivers/staging/comedi/drivers/ni_mio_common.c ni_writew(dev, val, reg); reg 2727 drivers/staging/comedi/drivers/ni_mio_common.c ni_writew(dev, val, reg); reg 3990 drivers/staging/comedi/drivers/ni_mio_common.c enum ni_gpct_register reg) reg 3994 drivers/staging/comedi/drivers/ni_mio_common.c if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) { reg 3995 drivers/staging/comedi/drivers/ni_mio_common.c regmap = &ni_gpct_to_stc_regmap[reg]; reg 3998 drivers/staging/comedi/drivers/ni_mio_common.c __func__, reg); reg 4006 drivers/staging/comedi/drivers/ni_mio_common.c enum ni_gpct_register reg) reg 4009 drivers/staging/comedi/drivers/ni_mio_common.c unsigned int stc_register = ni_gpct_to_stc_register(dev, reg); reg 4014 drivers/staging/comedi/drivers/ni_mio_common.c switch (reg) { reg 4052 drivers/staging/comedi/drivers/ni_mio_common.c enum ni_gpct_register reg) reg 4055 drivers/staging/comedi/drivers/ni_mio_common.c unsigned int stc_register = ni_gpct_to_stc_register(dev, reg); reg 4060 drivers/staging/comedi/drivers/ni_mio_common.c switch (reg) { reg 5269 drivers/staging/comedi/drivers/ni_mio_common.c static void set_rgout0_reg(int reg, struct comedi_device *dev) reg 5277 drivers/staging/comedi/drivers/ni_mio_common.c (reg << NISTC_RTSI_TRIG_DIR_SUB_SEL1_SHIFT) & reg 5284 drivers/staging/comedi/drivers/ni_mio_common.c (reg << NISTC_RTSI_TRIGB_SUB_SEL1_SHIFT) & reg 5294 drivers/staging/comedi/drivers/ni_mio_common.c int reg; reg 5297 drivers/staging/comedi/drivers/ni_mio_common.c reg = (devpriv->rtsi_trig_direction_reg & reg 5301 drivers/staging/comedi/drivers/ni_mio_common.c reg = (devpriv->rtsi_trig_b_output_reg & reg 5304 drivers/staging/comedi/drivers/ni_mio_common.c return reg; reg 5310 drivers/staging/comedi/drivers/ni_mio_common.c int reg = get_rgout0_reg(dev); reg 5312 drivers/staging/comedi/drivers/ni_mio_common.c return ni_find_route_source(reg, NI_RGOUT0, &devpriv->routing_tables); reg 5328 drivers/staging/comedi/drivers/ni_mio_common.c s8 reg = ni_lookup_route_register(CR_CHAN(src), NI_RGOUT0, reg 5331 drivers/staging/comedi/drivers/ni_mio_common.c if (reg < 0) reg 5334 drivers/staging/comedi/drivers/ni_mio_common.c if (devpriv->rgout0_usage > 0 && get_rgout0_reg(dev) != reg) reg 5338 drivers/staging/comedi/drivers/ni_mio_common.c set_rgout0_reg(reg, dev); reg 5354 drivers/staging/comedi/drivers/ni_mio_common.c s8 reg = ni_lookup_route_register(CR_CHAN(src), NI_RGOUT0, reg 5357 drivers/staging/comedi/drivers/ni_mio_common.c if (devpriv->rgout0_usage > 0 && get_rgout0_reg(dev) == reg) { reg 5372 drivers/staging/comedi/drivers/ni_mio_common.c static void set_ith_rtsi_brd_reg(int i, int reg, struct comedi_device *dev) reg 5387 drivers/staging/comedi/drivers/ni_mio_common.c devpriv->rtsi_shared_mux_reg |= (reg & reg_i_mask) << reg_i_shift; reg 5411 drivers/staging/comedi/drivers/ni_mio_common.c int reg; reg 5423 drivers/staging/comedi/drivers/ni_mio_common.c reg = get_ith_rtsi_brd_reg(brd_index, dev); reg 5425 drivers/staging/comedi/drivers/ni_mio_common.c return ni_find_route_source(reg, brd, &devpriv->routing_tables); reg 5441 drivers/staging/comedi/drivers/ni_mio_common.c s8 reg; reg 5446 drivers/staging/comedi/drivers/ni_mio_common.c reg = ni_lookup_route_register(CR_CHAN(src), NI_RTSI_BRD(i), reg 5449 drivers/staging/comedi/drivers/ni_mio_common.c if (reg < 0) reg 5464 drivers/staging/comedi/drivers/ni_mio_common.c if (get_ith_rtsi_brd_reg(i, dev) == reg) { reg 5482 drivers/staging/comedi/drivers/ni_mio_common.c set_ith_rtsi_brd_reg(i, reg, dev); reg 5497 drivers/staging/comedi/drivers/ni_mio_common.c s8 reg = ni_lookup_route_register(CR_CHAN(src), rtsi_brd, reg 5502 drivers/staging/comedi/drivers/ni_mio_common.c get_ith_rtsi_brd_reg(i, dev) == reg) { reg 5560 drivers/staging/comedi/drivers/ni_mio_common.c unsigned int reg = devpriv->an_trig_etc_reg; reg 5564 drivers/staging/comedi/drivers/ni_mio_common.c if (reg & NISTC_ATRIG_ETC_GPFO_0_ENA) reg 5565 drivers/staging/comedi/drivers/ni_mio_common.c return NISTC_ATRIG_ETC_GPFO_0_SEL_TO_SRC(reg); reg 5568 drivers/staging/comedi/drivers/ni_mio_common.c if (reg & NISTC_ATRIG_ETC_GPFO_1_ENA) reg 5569 drivers/staging/comedi/drivers/ni_mio_common.c return NISTC_ATRIG_ETC_GPFO_1_SEL_TO_SRC(reg); reg 5637 drivers/staging/comedi/drivers/ni_mio_common.c int reg = -1; reg 5641 drivers/staging/comedi/drivers/ni_mio_common.c reg = ni_get_pfi_routing(dev, dest); reg 5644 drivers/staging/comedi/drivers/ni_mio_common.c reg = ni_get_rtsi_routing(dev, dest); reg 5646 drivers/staging/comedi/drivers/ni_mio_common.c if (reg == NI_RTSI_OUTPUT_RGOUT0) { reg 5648 drivers/staging/comedi/drivers/ni_mio_common.c reg = get_rgout0_reg(dev); reg 5649 drivers/staging/comedi/drivers/ni_mio_common.c } else if (reg >= NI_RTSI_OUTPUT_RTSI_BRD(0) && reg 5650 drivers/staging/comedi/drivers/ni_mio_common.c reg <= NI_RTSI_OUTPUT_RTSI_BRD(3)) { reg 5651 drivers/staging/comedi/drivers/ni_mio_common.c const int i = reg - NI_RTSI_OUTPUT_RTSI_BRD(0); reg 5654 drivers/staging/comedi/drivers/ni_mio_common.c reg = get_ith_rtsi_brd_reg(i, dev); reg 5666 drivers/staging/comedi/drivers/ni_mio_common.c reg = ni_get_gout_routing(dest, dev); reg 5668 drivers/staging/comedi/drivers/ni_mio_common.c reg = ni_tio_get_routing(devpriv->counter_dev, dest); reg 5674 drivers/staging/comedi/drivers/ni_mio_common.c if (reg >= 0) reg 5675 drivers/staging/comedi/drivers/ni_mio_common.c return ni_find_route_source(CR_CHAN(reg), dest, reg 5691 drivers/staging/comedi/drivers/ni_mio_common.c s8 reg = ni_route_to_register(CR_CHAN(src), dest, reg 5694 drivers/staging/comedi/drivers/ni_mio_common.c if (reg < 0) reg 5706 drivers/staging/comedi/drivers/ni_mio_common.c s8 reg = ni_route_to_register(CR_CHAN(src), dest, reg 5710 drivers/staging/comedi/drivers/ni_mio_common.c if (reg < 0) reg 5724 drivers/staging/comedi/drivers/ni_mio_common.c ni_set_pfi_routing(dev, dest, reg); reg 5727 drivers/staging/comedi/drivers/ni_mio_common.c if (reg == NI_RTSI_OUTPUT_RGOUT0) { reg 5732 drivers/staging/comedi/drivers/ni_mio_common.c } else if (ni_rtsi_route_requires_mux(reg)) { reg 5740 drivers/staging/comedi/drivers/ni_mio_common.c reg = ni_lookup_route_register( reg 5745 drivers/staging/comedi/drivers/ni_mio_common.c ni_set_rtsi_routing(dev, dest, reg); reg 5763 drivers/staging/comedi/drivers/ni_mio_common.c reg | (src & ~CR_CHAN(-1))); reg 5774 drivers/staging/comedi/drivers/ni_mio_common.c s8 reg = ni_route_to_register(CR_CHAN(src), dest, reg 5777 drivers/staging/comedi/drivers/ni_mio_common.c if (reg < 0) reg 5790 drivers/staging/comedi/drivers/ni_mio_common.c if (reg == NI_RTSI_OUTPUT_RGOUT0) { reg 5795 drivers/staging/comedi/drivers/ni_mio_common.c } else if (ni_rtsi_route_requires_mux(reg)) { reg 5809 drivers/staging/comedi/drivers/ni_mio_common.c reg = default_rtsi_routing[dest - TRIGGER_LINE(0)]; reg 5811 drivers/staging/comedi/drivers/ni_mio_common.c ni_set_rtsi_routing(dev, dest, reg); reg 5821 drivers/staging/comedi/drivers/ni_mio_common.c reg = ni_disable_gout_routing(dest, dev); reg 150 drivers/staging/comedi/drivers/ni_tio.c enum ni_gpct_register reg) reg 152 drivers/staging/comedi/drivers/ni_tio.c if (reg < NITIO_NUM_REGS) reg 153 drivers/staging/comedi/drivers/ni_tio.c counter->counter_dev->write(counter, value, reg); reg 162 drivers/staging/comedi/drivers/ni_tio.c unsigned int ni_tio_read(struct ni_gpct *counter, enum ni_gpct_register reg) reg 164 drivers/staging/comedi/drivers/ni_tio.c if (reg < NITIO_NUM_REGS) reg 165 drivers/staging/comedi/drivers/ni_tio.c return counter->counter_dev->read(counter, reg); reg 222 drivers/staging/comedi/drivers/ni_tio.c enum ni_gpct_register reg, reg 230 drivers/staging/comedi/drivers/ni_tio.c if (reg < NITIO_NUM_REGS && chip < counter_dev->num_chips) { reg 234 drivers/staging/comedi/drivers/ni_tio.c regs[reg] &= ~mask; reg 235 drivers/staging/comedi/drivers/ni_tio.c regs[reg] |= (value & mask); reg 236 drivers/staging/comedi/drivers/ni_tio.c ni_tio_write(counter, regs[reg] | transient, reg); reg 252 drivers/staging/comedi/drivers/ni_tio.c void ni_tio_set_bits(struct ni_gpct *counter, enum ni_gpct_register reg, reg 255 drivers/staging/comedi/drivers/ni_tio.c ni_tio_set_bits_transient(counter, reg, mask, value, 0x0); reg 269 drivers/staging/comedi/drivers/ni_tio.c enum ni_gpct_register reg) reg 276 drivers/staging/comedi/drivers/ni_tio.c if (reg < NITIO_NUM_REGS && chip < counter_dev->num_chips) { reg 278 drivers/staging/comedi/drivers/ni_tio.c value = counter_dev->regs[chip][reg]; reg 448 drivers/staging/comedi/drivers/ni_tio.c unsigned int reg; reg 468 drivers/staging/comedi/drivers/ni_tio.c reg = NITIO_CNT_MODE_REG(cidx); reg 469 drivers/staging/comedi/drivers/ni_tio.c mode = ni_tio_get_soft_copy(counter, reg); reg 495 drivers/staging/comedi/drivers/ni_tio.c ni_tio_set_bits(counter, reg, mask, bits); reg 1520 drivers/staging/comedi/drivers/ni_tio.c unsigned int reg; reg 1523 drivers/staging/comedi/drivers/ni_tio.c ret = ni_tio_get_other_src(counter, dest, ®); reg 1525 drivers/staging/comedi/drivers/ni_tio.c ret = ni_tio_get_gate_src_raw(counter, 0, ®); reg 1527 drivers/staging/comedi/drivers/ni_tio.c ret = ni_tio_get_gate_src_raw(counter, 1, ®); reg 1539 drivers/staging/comedi/drivers/ni_tio.c return reg; reg 1556 drivers/staging/comedi/drivers/ni_tio.c unsigned int reg) reg 1564 drivers/staging/comedi/drivers/ni_tio.c ret = ni_tio_set_other_src(counter, dest, reg); reg 1566 drivers/staging/comedi/drivers/ni_tio.c ret = ni_tio_set_gate_src_raw(counter, 0, reg); reg 1568 drivers/staging/comedi/drivers/ni_tio.c ret = ni_tio_set_gate_src_raw(counter, 1, reg); reg 1766 drivers/staging/comedi/drivers/ni_tio.c enum ni_gpct_register reg), reg 1768 drivers/staging/comedi/drivers/ni_tio.c enum ni_gpct_register reg), reg 165 drivers/staging/comedi/drivers/ni_tio_internal.h void ni_tio_set_bits(struct ni_gpct *counter, enum ni_gpct_register reg, reg 168 drivers/staging/comedi/drivers/ni_tio_internal.h enum ni_gpct_register reg); reg 135 drivers/staging/comedi/drivers/ni_tiocmd.c int reg = CR_CHAN(cmd->start_arg); reg 137 drivers/staging/comedi/drivers/ni_tiocmd.c if (reg >= NI_NAMES_BASE) { reg 139 drivers/staging/comedi/drivers/ni_tiocmd.c reg = ni_get_reg_value(reg, reg 143 drivers/staging/comedi/drivers/ni_tiocmd.c reg |= NI_GPCT_HW_ARM; reg 145 drivers/staging/comedi/drivers/ni_tiocmd.c ret = ni_tio_arm(counter, true, reg); reg 181 drivers/staging/comedi/drivers/ni_tiocmd.c int reg = ni_get_reg_value(CR_CHAN(gate_source), reg 184 drivers/staging/comedi/drivers/ni_tiocmd.c if (reg < 0) reg 186 drivers/staging/comedi/drivers/ni_tiocmd.c retval = ni_tio_set_gate_src_raw(counter, 0, reg); reg 217 drivers/staging/comedi/drivers/pcl730.c unsigned long reg = (unsigned long)s->private; reg 223 drivers/staging/comedi/drivers/pcl730.c outb(s->state & 0xff, dev->iobase + reg); reg 225 drivers/staging/comedi/drivers/pcl730.c outb((s->state >> 8) & 0xff, dev->iobase + reg + 1); reg 227 drivers/staging/comedi/drivers/pcl730.c outb((s->state >> 16) & 0xff, dev->iobase + reg + 2); reg 229 drivers/staging/comedi/drivers/pcl730.c outb((s->state >> 24) & 0xff, dev->iobase + reg + 3); reg 240 drivers/staging/comedi/drivers/pcl730.c unsigned long reg = (unsigned long)s->private; reg 243 drivers/staging/comedi/drivers/pcl730.c val = inb(dev->iobase + reg); reg 245 drivers/staging/comedi/drivers/pcl730.c val |= (inb(dev->iobase + reg + 1) << 8); reg 247 drivers/staging/comedi/drivers/pcl730.c val |= (inb(dev->iobase + reg + 2) << 16); reg 249 drivers/staging/comedi/drivers/pcl730.c val |= (inb(dev->iobase + reg + 3) << 24); reg 107 drivers/staging/comedi/drivers/s626.c unsigned int cmd, unsigned int reg) reg 111 drivers/staging/comedi/drivers/s626.c writel(val, dev->mmio + reg); reg 115 drivers/staging/comedi/drivers/s626.c unsigned int cmd, unsigned int reg) reg 117 drivers/staging/comedi/drivers/s626.c writel(cmd << 16, dev->mmio + reg); reg 121 drivers/staging/comedi/drivers/s626.c unsigned int cmd, unsigned int reg) reg 125 drivers/staging/comedi/drivers/s626.c val = readl(dev->mmio + reg); reg 906 drivers/staging/comedi/drivers/s626.c u16 reg; reg 911 drivers/staging/comedi/drivers/s626.c reg = S626_LP_CRA(chan); reg 915 drivers/staging/comedi/drivers/s626.c reg = S626_LP_CRB(chan); reg 919 drivers/staging/comedi/drivers/s626.c s626_debi_replace(dev, reg, ~mask, set); reg 240 drivers/staging/comedi/drivers/vmk80xx.c int reg[2]; reg 249 drivers/staging/comedi/drivers/vmk80xx.c reg[0] = VMK8055_AI1_REG; reg 251 drivers/staging/comedi/drivers/vmk80xx.c reg[0] = VMK8055_AI2_REG; reg 255 drivers/staging/comedi/drivers/vmk80xx.c reg[0] = VMK8061_AI_REG1; reg 256 drivers/staging/comedi/drivers/vmk80xx.c reg[1] = VMK8061_AI_REG2; reg 267 drivers/staging/comedi/drivers/vmk80xx.c data[n] = devpriv->usb_rx_buf[reg[0]]; reg 272 drivers/staging/comedi/drivers/vmk80xx.c data[n] = devpriv->usb_rx_buf[reg[0]] + 256 * reg 273 drivers/staging/comedi/drivers/vmk80xx.c devpriv->usb_rx_buf[reg[1]]; reg 289 drivers/staging/comedi/drivers/vmk80xx.c int reg; reg 299 drivers/staging/comedi/drivers/vmk80xx.c reg = VMK8055_AO1_REG; reg 301 drivers/staging/comedi/drivers/vmk80xx.c reg = VMK8055_AO2_REG; reg 305 drivers/staging/comedi/drivers/vmk80xx.c reg = VMK8061_AO_REG; reg 311 drivers/staging/comedi/drivers/vmk80xx.c devpriv->usb_tx_buf[reg] = data[n]; reg 329 drivers/staging/comedi/drivers/vmk80xx.c int reg; reg 335 drivers/staging/comedi/drivers/vmk80xx.c reg = VMK8061_AO_REG - 1; reg 343 drivers/staging/comedi/drivers/vmk80xx.c data[n] = devpriv->usb_rx_buf[reg + chan]; reg 358 drivers/staging/comedi/drivers/vmk80xx.c int reg; reg 366 drivers/staging/comedi/drivers/vmk80xx.c reg = VMK8061_DI_REG; reg 369 drivers/staging/comedi/drivers/vmk80xx.c reg = VMK8055_DI_REG; reg 376 drivers/staging/comedi/drivers/vmk80xx.c data[1] = (((rx_buf[reg] >> 4) & 0x03) | reg 377 drivers/staging/comedi/drivers/vmk80xx.c ((rx_buf[reg] << 2) & 0x04) | reg 378 drivers/staging/comedi/drivers/vmk80xx.c ((rx_buf[reg] >> 3) & 0x18)); reg 380 drivers/staging/comedi/drivers/vmk80xx.c data[1] = rx_buf[reg]; reg 398 drivers/staging/comedi/drivers/vmk80xx.c int reg, cmd; reg 402 drivers/staging/comedi/drivers/vmk80xx.c reg = VMK8061_DO_REG; reg 405 drivers/staging/comedi/drivers/vmk80xx.c reg = VMK8055_DO_REG; reg 412 drivers/staging/comedi/drivers/vmk80xx.c tx_buf[reg] = s->state; reg 423 drivers/staging/comedi/drivers/vmk80xx.c data[1] = rx_buf[reg]; reg 441 drivers/staging/comedi/drivers/vmk80xx.c int reg[2]; reg 450 drivers/staging/comedi/drivers/vmk80xx.c reg[0] = VMK8055_CNT1_REG; reg 452 drivers/staging/comedi/drivers/vmk80xx.c reg[0] = VMK8055_CNT2_REG; reg 456 drivers/staging/comedi/drivers/vmk80xx.c reg[0] = VMK8061_CNT_REG; reg 457 drivers/staging/comedi/drivers/vmk80xx.c reg[1] = VMK8061_CNT_REG; reg 467 drivers/staging/comedi/drivers/vmk80xx.c data[n] = devpriv->usb_rx_buf[reg[0]]; reg 469 drivers/staging/comedi/drivers/vmk80xx.c data[n] = devpriv->usb_rx_buf[reg[0] * (chan + 1) + 1] reg 470 drivers/staging/comedi/drivers/vmk80xx.c + 256 * devpriv->usb_rx_buf[reg[1] * 2 + 2]; reg 486 drivers/staging/comedi/drivers/vmk80xx.c int reg; reg 495 drivers/staging/comedi/drivers/vmk80xx.c reg = VMK8055_CNT1_REG; reg 498 drivers/staging/comedi/drivers/vmk80xx.c reg = VMK8055_CNT2_REG; reg 500 drivers/staging/comedi/drivers/vmk80xx.c devpriv->usb_tx_buf[reg] = 0x00; reg 567 drivers/staging/comedi/drivers/vmk80xx.c int reg[2]; reg 575 drivers/staging/comedi/drivers/vmk80xx.c reg[0] = VMK8061_PWM_REG1; reg 576 drivers/staging/comedi/drivers/vmk80xx.c reg[1] = VMK8061_PWM_REG2; reg 584 drivers/staging/comedi/drivers/vmk80xx.c data[n] = rx_buf[reg[0]] + 4 * rx_buf[reg[1]]; reg 599 drivers/staging/comedi/drivers/vmk80xx.c int reg[2]; reg 607 drivers/staging/comedi/drivers/vmk80xx.c reg[0] = VMK8061_PWM_REG1; reg 608 drivers/staging/comedi/drivers/vmk80xx.c reg[1] = VMK8061_PWM_REG2; reg 626 drivers/staging/comedi/drivers/vmk80xx.c tx_buf[reg[0]] = (unsigned char)(data[n] & 0x03); reg 627 drivers/staging/comedi/drivers/vmk80xx.c tx_buf[reg[1]] = (unsigned char)(data[n] >> 2) & 0xff; reg 65 drivers/staging/gasket/gasket_core.h u64 reg; reg 102 drivers/staging/gasket/gasket_interrupt.c interrupt_data->interrupts[i].reg, reg 130 drivers/staging/gasket/gasket_interrupt.c interrupt_data->interrupts[i].reg); reg 137 drivers/staging/gasket/gasket_interrupt.c interrupt_data->interrupts[i].reg); reg 1028 drivers/staging/greybus/audio_codec.c static int gbcodec_write(struct snd_soc_codec *codec, unsigned int reg, reg 1035 drivers/staging/greybus/audio_codec.c unsigned int reg) reg 16 drivers/staging/greybus/audio_topology.c unsigned int reg, rreg, shift, rshift, invert; reg 209 drivers/staging/iio/adc/ad7280a.c unsigned int reg = devaddr << 27 | addr << 21 | reg 212 drivers/staging/iio/adc/ad7280a.c reg |= ad7280_calc_crc8(st->crc_tab, reg >> 11) << 3 | 0x2; reg 213 drivers/staging/iio/adc/ad7280a.c st->buf[0] = cpu_to_be32(reg); reg 20 drivers/staging/iio/addac/adt7316-i2c.c static int adt7316_i2c_read(void *client, u8 reg, u8 *data) reg 25 drivers/staging/iio/addac/adt7316-i2c.c ret = i2c_smbus_write_byte(cl, reg); reg 42 drivers/staging/iio/addac/adt7316-i2c.c static int adt7316_i2c_write(void *client, u8 reg, u8 data) reg 47 drivers/staging/iio/addac/adt7316-i2c.c ret = i2c_smbus_write_byte_data(cl, reg, data); reg 54 drivers/staging/iio/addac/adt7316-i2c.c static int adt7316_i2c_multi_read(void *client, u8 reg, u8 count, u8 *data) reg 63 drivers/staging/iio/addac/adt7316-i2c.c ret = adt7316_i2c_read(cl, reg, &data[i]); reg 73 drivers/staging/iio/addac/adt7316-i2c.c static int adt7316_i2c_multi_write(void *client, u8 reg, u8 count, u8 *data) reg 82 drivers/staging/iio/addac/adt7316-i2c.c ret = adt7316_i2c_write(cl, reg, data[i]); reg 25 drivers/staging/iio/addac/adt7316-spi.c static int adt7316_spi_multi_read(void *client, u8 reg, u8 count, u8 *data) reg 35 drivers/staging/iio/addac/adt7316-spi.c cmd[1] = reg; reg 54 drivers/staging/iio/addac/adt7316-spi.c static int adt7316_spi_multi_write(void *client, u8 reg, u8 count, u8 *data) reg 64 drivers/staging/iio/addac/adt7316-spi.c buf[1] = reg; reg 77 drivers/staging/iio/addac/adt7316-spi.c static int adt7316_spi_read(void *client, u8 reg, u8 *data) reg 79 drivers/staging/iio/addac/adt7316-spi.c return adt7316_spi_multi_read(client, reg, 1, data); reg 82 drivers/staging/iio/addac/adt7316-spi.c static int adt7316_spi_write(void *client, u8 reg, u8 val) reg 84 drivers/staging/iio/addac/adt7316-spi.c return adt7316_spi_multi_write(client, reg, 1, &val); reg 19 drivers/staging/iio/addac/adt7316.h int (*read)(void *client, u8 reg, u8 *data); reg 20 drivers/staging/iio/addac/adt7316.h int (*write)(void *client, u8 reg, u8 val); reg 427 drivers/staging/iio/cdc/ad7746.c int ret, reg; reg 442 drivers/staging/iio/cdc/ad7746.c reg = AD7746_REG_CAP_GAINH; reg 445 drivers/staging/iio/cdc/ad7746.c reg = AD7746_REG_VOLT_GAINH; reg 452 drivers/staging/iio/cdc/ad7746.c ret = i2c_smbus_write_word_swapped(chip->client, reg, val); reg 535 drivers/staging/iio/cdc/ad7746.c u8 regval, reg; reg 586 drivers/staging/iio/cdc/ad7746.c reg = AD7746_REG_CAP_GAINH; reg 589 drivers/staging/iio/cdc/ad7746.c reg = AD7746_REG_VOLT_GAINH; reg 596 drivers/staging/iio/cdc/ad7746.c ret = i2c_smbus_read_word_swapped(chip->client, reg); reg 73 drivers/staging/iio/frequency/ad9834.c struct regulator *reg; reg 397 drivers/staging/iio/frequency/ad9834.c struct regulator *reg; reg 401 drivers/staging/iio/frequency/ad9834.c reg = devm_regulator_get(&spi->dev, "avdd"); reg 402 drivers/staging/iio/frequency/ad9834.c if (IS_ERR(reg)) reg 403 drivers/staging/iio/frequency/ad9834.c return PTR_ERR(reg); reg 405 drivers/staging/iio/frequency/ad9834.c ret = regulator_enable(reg); reg 433 drivers/staging/iio/frequency/ad9834.c st->reg = reg; reg 502 drivers/staging/iio/frequency/ad9834.c regulator_disable(reg); reg 514 drivers/staging/iio/frequency/ad9834.c regulator_disable(st->reg); reg 87 drivers/staging/iio/impedance-analyzer/ad5933.c struct regulator *reg; reg 126 drivers/staging/iio/impedance-analyzer/ad5933.c static int ad5933_i2c_write(struct i2c_client *client, u8 reg, u8 len, u8 *data) reg 131 drivers/staging/iio/impedance-analyzer/ad5933.c ret = i2c_smbus_write_byte_data(client, reg++, *data++); reg 140 drivers/staging/iio/impedance-analyzer/ad5933.c static int ad5933_i2c_read(struct i2c_client *client, u8 reg, u8 len, u8 *data) reg 145 drivers/staging/iio/impedance-analyzer/ad5933.c ret = i2c_smbus_read_byte_data(client, reg++); reg 190 drivers/staging/iio/impedance-analyzer/ad5933.c unsigned int reg, unsigned long freq) reg 201 drivers/staging/iio/impedance-analyzer/ad5933.c switch (reg) { reg 213 drivers/staging/iio/impedance-analyzer/ad5933.c return ad5933_i2c_write(st->client, reg, 3, &dat.d8[1]); reg 697 drivers/staging/iio/impedance-analyzer/ad5933.c st->reg = devm_regulator_get(&client->dev, "vdd"); reg 698 drivers/staging/iio/impedance-analyzer/ad5933.c if (IS_ERR(st->reg)) reg 699 drivers/staging/iio/impedance-analyzer/ad5933.c return PTR_ERR(st->reg); reg 701 drivers/staging/iio/impedance-analyzer/ad5933.c ret = regulator_enable(st->reg); reg 706 drivers/staging/iio/impedance-analyzer/ad5933.c ret = regulator_get_voltage(st->reg); reg 764 drivers/staging/iio/impedance-analyzer/ad5933.c regulator_disable(st->reg); reg 776 drivers/staging/iio/impedance-analyzer/ad5933.c regulator_disable(st->reg); reg 301 drivers/staging/isdn/avm/avmcard.h unsigned int reg, reg 305 drivers/staging/isdn/avm/avmcard.h b1_put_word(base, reg); reg 310 drivers/staging/isdn/avm/avmcard.h unsigned int reg) reg 313 drivers/staging/isdn/avm/avmcard.h b1_put_word(base, reg); reg 136 drivers/staging/isdn/avm/b1dma.c static int WriteReg(avmcard *card, u32 reg, u8 val) reg 140 drivers/staging/isdn/avm/b1dma.c && b1dma_tolink(card, ®, 4) == 0) { reg 147 drivers/staging/isdn/avm/b1dma.c static u8 ReadReg(avmcard *card, u32 reg) reg 151 drivers/staging/isdn/avm/b1dma.c && b1dma_tolink(card, ®, 4) == 0) { reg 132 drivers/staging/kpc2000/kpc2000_spi.c u32 reg; reg 147 drivers/staging/kpc2000/kpc2000_spi.c u32 reg; reg 155 drivers/staging/kpc2000/kpc2000_spi.c u32 reg; reg 284 drivers/staging/kpc2000/kpc2000_spi.c kp_spi_write_reg(spidev->controller_state, KP_SPI_REG_CONFIG, sc.reg); reg 337 drivers/staging/kpc2000/kpc2000_spi.c sc.reg = kp_spi_read_reg(cs, KP_SPI_REG_CONFIG); reg 339 drivers/staging/kpc2000/kpc2000_spi.c kp_spi_write_reg(cs, KP_SPI_REG_CONFIG, sc.reg); reg 362 drivers/staging/kpc2000/kpc2000_spi.c sc.reg = kp_spi_read_reg(cs, KP_SPI_REG_CONFIG); reg 379 drivers/staging/kpc2000/kpc2000_spi.c kp_spi_write_reg(cs, KP_SPI_REG_CONFIG, sc.reg); reg 396 drivers/staging/kpc2000/kpc2000_spi.c sc.reg = kp_spi_read_reg(cs, KP_SPI_REG_CONFIG); reg 398 drivers/staging/kpc2000/kpc2000_spi.c kp_spi_write_reg(cs, KP_SPI_REG_CONFIG, sc.reg); reg 223 drivers/staging/ks7010/ks7010_sdio.c if (priv->reg.power_mgmt == POWER_MGMT_ACTIVE) reg 226 drivers/staging/ks7010/ks7010_sdio.c if (priv->reg.operation_mode != MODE_INFRASTRUCTURE) reg 853 drivers/staging/ks7010/ks7010_sdio.c priv->reg.tx_rate = TX_RATE_AUTO; reg 854 drivers/staging/ks7010/ks7010_sdio.c priv->reg.preamble = LONG_PREAMBLE; reg 855 drivers/staging/ks7010/ks7010_sdio.c priv->reg.power_mgmt = POWER_MGMT_ACTIVE; reg 856 drivers/staging/ks7010/ks7010_sdio.c priv->reg.scan_type = ACTIVE_SCAN; reg 857 drivers/staging/ks7010/ks7010_sdio.c priv->reg.beacon_lost_count = 20; reg 858 drivers/staging/ks7010/ks7010_sdio.c priv->reg.rts = 2347UL; reg 859 drivers/staging/ks7010/ks7010_sdio.c priv->reg.fragment = 2346UL; reg 860 drivers/staging/ks7010/ks7010_sdio.c priv->reg.phy_type = D_11BG_COMPATIBLE_MODE; reg 861 drivers/staging/ks7010/ks7010_sdio.c priv->reg.cts_mode = CTS_MODE_FALSE; reg 862 drivers/staging/ks7010/ks7010_sdio.c priv->reg.rate_set.body[11] = TX_RATE_54M; reg 863 drivers/staging/ks7010/ks7010_sdio.c priv->reg.rate_set.body[10] = TX_RATE_48M; reg 864 drivers/staging/ks7010/ks7010_sdio.c priv->reg.rate_set.body[9] = TX_RATE_36M; reg 865 drivers/staging/ks7010/ks7010_sdio.c priv->reg.rate_set.body[8] = TX_RATE_18M; reg 866 drivers/staging/ks7010/ks7010_sdio.c priv->reg.rate_set.body[7] = TX_RATE_9M; reg 867 drivers/staging/ks7010/ks7010_sdio.c priv->reg.rate_set.body[6] = TX_RATE_24M | BASIC_RATE; reg 868 drivers/staging/ks7010/ks7010_sdio.c priv->reg.rate_set.body[5] = TX_RATE_12M | BASIC_RATE; reg 869 drivers/staging/ks7010/ks7010_sdio.c priv->reg.rate_set.body[4] = TX_RATE_6M | BASIC_RATE; reg 870 drivers/staging/ks7010/ks7010_sdio.c priv->reg.rate_set.body[3] = TX_RATE_11M | BASIC_RATE; reg 871 drivers/staging/ks7010/ks7010_sdio.c priv->reg.rate_set.body[2] = TX_RATE_5M | BASIC_RATE; reg 872 drivers/staging/ks7010/ks7010_sdio.c priv->reg.rate_set.body[1] = TX_RATE_2M | BASIC_RATE; reg 873 drivers/staging/ks7010/ks7010_sdio.c priv->reg.rate_set.body[0] = TX_RATE_1M | BASIC_RATE; reg 874 drivers/staging/ks7010/ks7010_sdio.c priv->reg.tx_rate = TX_RATE_FULL_AUTO; reg 875 drivers/staging/ks7010/ks7010_sdio.c priv->reg.rate_set.size = 12; reg 117 drivers/staging/ks7010/ks_hostif.c memcpy(ap->ssid.body, priv->reg.ssid.body, reg 118 drivers/staging/ks7010/ks_hostif.c priv->reg.ssid.size); reg 119 drivers/staging/ks7010/ks_hostif.c ap->ssid.size = priv->reg.ssid.size; reg 687 drivers/staging/ks7010/ks_hostif.c if (priv->reg.power_mgmt > POWER_MGMT_ACTIVE && reg 688 drivers/staging/ks7010/ks_hostif.c priv->reg.operation_mode == MODE_INFRASTRUCTURE) { reg 1333 drivers/staging/ks7010/ks_hostif.c if (priv->reg.preamble == SHORT_PREAMBLE) reg 1338 drivers/staging/ks7010/ks_hostif.c if (priv->reg.phy_type != D_11B_ONLY_MODE) { reg 1349 drivers/staging/ks7010/ks_hostif.c req->phy_type = cpu_to_le16(priv->reg.phy_type); reg 1350 drivers/staging/ks7010/ks_hostif.c req->cts_mode = cpu_to_le16(priv->reg.cts_mode); reg 1351 drivers/staging/ks7010/ks_hostif.c req->scan_type = cpu_to_le16(priv->reg.scan_type); reg 1352 drivers/staging/ks7010/ks_hostif.c req->rate_set.size = priv->reg.rate_set.size; reg 1354 drivers/staging/ks7010/ks_hostif.c memcpy(&req->rate_set.body[0], &priv->reg.rate_set.body[0], reg 1355 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.size); reg 1368 drivers/staging/ks7010/ks_hostif.c pp->channel = cpu_to_le16(priv->reg.channel); reg 1383 drivers/staging/ks7010/ks_hostif.c pp->ssid.size = priv->reg.ssid.size; reg 1384 drivers/staging/ks7010/ks_hostif.c memcpy(&pp->ssid.body[0], &priv->reg.ssid.body[0], priv->reg.ssid.size); reg 1386 drivers/staging/ks7010/ks_hostif.c cpu_to_le16(priv->reg.beacon_lost_count); reg 1387 drivers/staging/ks7010/ks_hostif.c pp->auth_type = cpu_to_le16(priv->reg.authenticate_type); reg 1402 drivers/staging/ks7010/ks_hostif.c if (priv->reg.phy_type == D_11G_ONLY_MODE) { reg 1422 drivers/staging/ks7010/ks_hostif.c pp->channel = cpu_to_le16(priv->reg.channel); reg 1423 drivers/staging/ks7010/ks_hostif.c pp->ssid.size = priv->reg.ssid.size; reg 1424 drivers/staging/ks7010/ks_hostif.c memcpy(&pp->ssid.body[0], &priv->reg.ssid.body[0], priv->reg.ssid.size); reg 1439 drivers/staging/ks7010/ks_hostif.c pp->ssid.size = priv->reg.ssid.size; reg 1440 drivers/staging/ks7010/ks_hostif.c memcpy(&pp->ssid.body[0], &priv->reg.ssid.body[0], priv->reg.ssid.size); reg 1442 drivers/staging/ks7010/ks_hostif.c pp->channel_list.body[0] = priv->reg.channel; reg 1444 drivers/staging/ks7010/ks_hostif.c memcpy(pp->bssid, priv->reg.bssid, ETH_ALEN); reg 1470 drivers/staging/ks7010/ks_hostif.c if (priv->reg.phy_info_timer) { reg 1472 drivers/staging/ks7010/ks_hostif.c pp->time = cpu_to_le16(priv->reg.phy_info_timer); reg 1547 drivers/staging/ks7010/ks_hostif.c if (priv->reg.phy_type == D_11G_ONLY_MODE) { reg 1624 drivers/staging/ks7010/ks_hostif.c priv->reg.wep_index); reg 1631 drivers/staging/ks7010/ks_hostif.c &priv->reg.wep_key[0].val[0], reg 1632 drivers/staging/ks7010/ks_hostif.c priv->reg.wep_key[0].size); reg 1639 drivers/staging/ks7010/ks_hostif.c &priv->reg.wep_key[1].val[0], reg 1640 drivers/staging/ks7010/ks_hostif.c priv->reg.wep_key[1].size); reg 1647 drivers/staging/ks7010/ks_hostif.c &priv->reg.wep_key[2].val[0], reg 1648 drivers/staging/ks7010/ks_hostif.c priv->reg.wep_key[2].size); reg 1655 drivers/staging/ks7010/ks_hostif.c &priv->reg.wep_key[3].val[0], reg 1656 drivers/staging/ks7010/ks_hostif.c priv->reg.wep_key[3].size); reg 1660 drivers/staging/ks7010/ks_hostif.c priv->reg.privacy_invoked); reg 1804 drivers/staging/ks7010/ks_hostif.c if (priv->reg.tx_rate == TX_RATE_FULL_AUTO) { reg 1805 drivers/staging/ks7010/ks_hostif.c if (priv->reg.phy_type == D_11B_ONLY_MODE) { reg 1806 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.body[3] = TX_RATE_11M; reg 1807 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.body[2] = TX_RATE_5M; reg 1808 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.body[1] = TX_RATE_2M | BASIC_RATE; reg 1809 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.body[0] = TX_RATE_1M | BASIC_RATE; reg 1810 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.size = 4; reg 1812 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.body[11] = TX_RATE_54M; reg 1813 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.body[10] = TX_RATE_48M; reg 1814 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.body[9] = TX_RATE_36M; reg 1815 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.body[8] = TX_RATE_18M; reg 1816 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.body[7] = TX_RATE_9M; reg 1817 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.body[6] = TX_RATE_24M | BASIC_RATE; reg 1818 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.body[5] = TX_RATE_12M | BASIC_RATE; reg 1819 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.body[4] = TX_RATE_6M | BASIC_RATE; reg 1820 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.body[3] = TX_RATE_11M | BASIC_RATE; reg 1821 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.body[2] = TX_RATE_5M | BASIC_RATE; reg 1822 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.body[1] = TX_RATE_2M | BASIC_RATE; reg 1823 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.body[0] = TX_RATE_1M | BASIC_RATE; reg 1824 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.size = 12; reg 1829 drivers/staging/ks7010/ks_hostif.c if (priv->reg.phy_type == D_11B_ONLY_MODE) { reg 1830 drivers/staging/ks7010/ks_hostif.c for (i = 0; i < priv->reg.rate_set.size; i++) { reg 1831 drivers/staging/ks7010/ks_hostif.c if (!is_11b_rate(priv->reg.rate_set.body[i])) reg 1834 drivers/staging/ks7010/ks_hostif.c if ((priv->reg.rate_set.body[i] & RATE_MASK) >= TX_RATE_5M) { reg 1835 drivers/staging/ks7010/ks_hostif.c rate_octet[i] = priv->reg.rate_set.body[i] & reg 1838 drivers/staging/ks7010/ks_hostif.c rate_octet[i] = priv->reg.rate_set.body[i]; reg 1843 drivers/staging/ks7010/ks_hostif.c for (i = 0; i < priv->reg.rate_set.size; i++) { reg 1844 drivers/staging/ks7010/ks_hostif.c if (!is_11bg_rate(priv->reg.rate_set.body[i])) reg 1847 drivers/staging/ks7010/ks_hostif.c if (is_ofdm_ext_rate(priv->reg.rate_set.body[i])) { reg 1848 drivers/staging/ks7010/ks_hostif.c rate_octet[i] = priv->reg.rate_set.body[i] & reg 1851 drivers/staging/ks7010/ks_hostif.c rate_octet[i] = priv->reg.rate_set.body[i]; reg 1857 drivers/staging/ks7010/ks_hostif.c if (priv->reg.phy_type == D_11G_ONLY_MODE) reg 1865 drivers/staging/ks7010/ks_hostif.c priv->reg.rate_set.size = rate_size; reg 1866 drivers/staging/ks7010/ks_hostif.c memcpy(&priv->reg.rate_set.body[0], &rate_octet[0], rate_size); reg 1868 drivers/staging/ks7010/ks_hostif.c switch (priv->reg.operation_mode) { reg 1873 drivers/staging/ks7010/ks_hostif.c if (!is_valid_ether_addr((u8 *)priv->reg.bssid)) { reg 1880 drivers/staging/ks7010/ks_hostif.c "Infra bssid = %pM\n", priv->reg.bssid); reg 1884 drivers/staging/ks7010/ks_hostif.c if (!is_valid_ether_addr((u8 *)priv->reg.bssid)) { reg 1889 drivers/staging/ks7010/ks_hostif.c "Adhoc bssid = %pM\n", priv->reg.bssid); reg 1947 drivers/staging/ks7010/ks_hostif.c if (priv->reg.power_mgmt != POWER_MGMT_SAVE1 && reg 1948 drivers/staging/ks7010/ks_hostif.c priv->reg.power_mgmt != POWER_MGMT_SAVE2) { reg 1953 drivers/staging/ks7010/ks_hostif.c mode = (priv->reg.operation_mode == MODE_INFRASTRUCTURE) ? reg 1956 drivers/staging/ks7010/ks_hostif.c receive_dtims = (priv->reg.operation_mode == MODE_INFRASTRUCTURE && reg 1957 drivers/staging/ks7010/ks_hostif.c priv->reg.power_mgmt == POWER_MGMT_SAVE2); reg 1978 drivers/staging/ks7010/ks_hostif.c priv->reg.privacy_invoked); reg 2071 drivers/staging/ks7010/ks_hostif.c hostif_bss_scan_request(priv, priv->reg.scan_type, reg 2096 drivers/staging/ks7010/ks_hostif.c hostif_start_request(priv, priv->reg.operation_mode); reg 2112 drivers/staging/ks7010/ks_hostif.c priv->reg.rts); reg 2116 drivers/staging/ks7010/ks_hostif.c priv->reg.fragment); reg 2170 drivers/staging/ks7010/ks_hostif.c hostif_start_request(priv, priv->reg.operation_mode); reg 465 drivers/staging/ks7010/ks_wlan.h struct ks_wlan_parameter reg; reg 73 drivers/staging/ks7010/ks_wlan_net.c wstats->status = priv->reg.operation_mode; /* Operation mode */ reg 162 drivers/staging/ks7010/ks_wlan_net.c else if (priv->reg.phy_type == D_11B_ONLY_MODE) reg 164 drivers/staging/ks7010/ks_wlan_net.c else if (priv->reg.phy_type == D_11G_ONLY_MODE) reg 210 drivers/staging/ks7010/ks_wlan_net.c priv->reg.channel = (u8)(channel); reg 230 drivers/staging/ks7010/ks_wlan_net.c f = (int)priv->reg.channel; reg 252 drivers/staging/ks7010/ks_wlan_net.c memset(priv->reg.ssid.body, 0, sizeof(priv->reg.ssid.body)); reg 253 drivers/staging/ks7010/ks_wlan_net.c priv->reg.ssid.size = 0; reg 265 drivers/staging/ks7010/ks_wlan_net.c memset(priv->reg.ssid.body, 0, sizeof(priv->reg.ssid.body)); reg 266 drivers/staging/ks7010/ks_wlan_net.c memcpy(priv->reg.ssid.body, extra, len); reg 267 drivers/staging/ks7010/ks_wlan_net.c priv->reg.ssid.size = len; reg 290 drivers/staging/ks7010/ks_wlan_net.c if (priv->reg.ssid.size != 0) { reg 292 drivers/staging/ks7010/ks_wlan_net.c memcpy(extra, priv->reg.ssid.body, priv->reg.ssid.size); reg 297 drivers/staging/ks7010/ks_wlan_net.c dwrq->essid.length = priv->reg.ssid.size; reg 316 drivers/staging/ks7010/ks_wlan_net.c if (priv->reg.operation_mode != MODE_ADHOC && reg 317 drivers/staging/ks7010/ks_wlan_net.c priv->reg.operation_mode != MODE_INFRASTRUCTURE) { reg 318 drivers/staging/ks7010/ks_wlan_net.c eth_zero_addr(priv->reg.bssid); reg 322 drivers/staging/ks7010/ks_wlan_net.c ether_addr_copy(priv->reg.bssid, awrq->ap_addr.sa_data); reg 323 drivers/staging/ks7010/ks_wlan_net.c if (is_valid_ether_addr((u8 *)priv->reg.bssid)) reg 326 drivers/staging/ks7010/ks_wlan_net.c netdev_dbg(dev, "bssid = %pM\n", priv->reg.bssid); reg 403 drivers/staging/ks7010/ks_wlan_net.c if (priv->reg.phy_type == D_11B_ONLY_MODE) { reg 408 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[0] = reg 413 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[0] = reg 420 drivers/staging/ks7010/ks_wlan_net.c priv->reg.tx_rate = TX_RATE_FIXED; reg 421 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.size = 1; reg 426 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[3] = reg 431 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[2] = TX_RATE_5M; reg 435 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[1] = reg 440 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[0] = reg 447 drivers/staging/ks7010/ks_wlan_net.c priv->reg.tx_rate = TX_RATE_MANUAL_AUTO; reg 448 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.size = i; reg 450 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[3] = TX_RATE_11M; reg 451 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[2] = TX_RATE_5M; reg 452 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[1] = reg 454 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[0] = reg 456 drivers/staging/ks7010/ks_wlan_net.c priv->reg.tx_rate = TX_RATE_FULL_AUTO; reg 457 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.size = 4; reg 468 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[0] = reg 478 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[0] = reg 485 drivers/staging/ks7010/ks_wlan_net.c priv->reg.tx_rate = TX_RATE_FIXED; reg 486 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.size = 1; reg 491 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[11] = reg 496 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[10] = reg 501 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[9] = reg 512 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[8] = reg 515 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[7] = reg 518 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[6] = reg 521 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[5] = reg 524 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[4] = reg 527 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[3] = reg 531 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[7] = reg 534 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[6] = reg 537 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[5] = reg 540 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[4] = reg 543 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[3] = reg 547 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[6] = reg 550 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[5] = reg 553 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[4] = reg 556 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[3] = reg 560 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[5] = reg 563 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[4] = reg 566 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[3] = reg 570 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[4] = reg 573 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[3] = reg 577 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[3] = reg 583 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[2] = reg 588 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[1] = reg 593 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[0] = reg 600 drivers/staging/ks7010/ks_wlan_net.c priv->reg.tx_rate = TX_RATE_MANUAL_AUTO; reg 601 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.size = i; reg 603 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[11] = TX_RATE_54M; reg 604 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[10] = TX_RATE_48M; reg 605 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[9] = TX_RATE_36M; reg 606 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[8] = TX_RATE_18M; reg 607 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[7] = TX_RATE_9M; reg 608 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[6] = reg 610 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[5] = reg 612 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[4] = reg 614 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[3] = reg 616 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[2] = reg 618 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[1] = reg 620 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.body[0] = reg 622 drivers/staging/ks7010/ks_wlan_net.c priv->reg.tx_rate = TX_RATE_FULL_AUTO; reg 623 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rate_set.size = 12; reg 650 drivers/staging/ks7010/ks_wlan_net.c vwrq->bitrate.fixed = (priv->reg.tx_rate == TX_RATE_FIXED) ? 1 : 0; reg 670 drivers/staging/ks7010/ks_wlan_net.c priv->reg.rts = rthr; reg 685 drivers/staging/ks7010/ks_wlan_net.c vwrq->rts.value = priv->reg.rts; reg 709 drivers/staging/ks7010/ks_wlan_net.c priv->reg.fragment = fthr; reg 725 drivers/staging/ks7010/ks_wlan_net.c vwrq->frag.value = priv->reg.fragment; reg 745 drivers/staging/ks7010/ks_wlan_net.c priv->reg.operation_mode = (uwrq->mode == IW_MODE_ADHOC) ? reg 762 drivers/staging/ks7010/ks_wlan_net.c uwrq->mode = (priv->reg.operation_mode == MODE_INFRASTRUCTURE) ? reg 787 drivers/staging/ks7010/ks_wlan_net.c index = (index == 0) ? priv->reg.wep_index : (index - 1); reg 794 drivers/staging/ks7010/ks_wlan_net.c priv->reg.privacy_invoked = 0x01; reg 810 drivers/staging/ks7010/ks_wlan_net.c priv->reg.wep_key[index].size = key.len; reg 811 drivers/staging/ks7010/ks_wlan_net.c memcpy(&priv->reg.wep_key[index].val[0], &key.key[0], reg 812 drivers/staging/ks7010/ks_wlan_net.c priv->reg.wep_key[index].size); reg 814 drivers/staging/ks7010/ks_wlan_net.c priv->reg.wep_index = index; reg 818 drivers/staging/ks7010/ks_wlan_net.c priv->reg.wep_key[0].size = 0; reg 819 drivers/staging/ks7010/ks_wlan_net.c priv->reg.wep_key[1].size = 0; reg 820 drivers/staging/ks7010/ks_wlan_net.c priv->reg.wep_key[2].size = 0; reg 821 drivers/staging/ks7010/ks_wlan_net.c priv->reg.wep_key[3].size = 0; reg 822 drivers/staging/ks7010/ks_wlan_net.c priv->reg.privacy_invoked = 0x00; reg 823 drivers/staging/ks7010/ks_wlan_net.c if (priv->reg.authenticate_type == AUTH_TYPE_SHARED_KEY) reg 826 drivers/staging/ks7010/ks_wlan_net.c priv->reg.authenticate_type = AUTH_TYPE_OPEN_SYSTEM; reg 831 drivers/staging/ks7010/ks_wlan_net.c if (priv->reg.wep_key[index].size == 0) reg 833 drivers/staging/ks7010/ks_wlan_net.c priv->reg.wep_index = index; reg 843 drivers/staging/ks7010/ks_wlan_net.c if (priv->reg.authenticate_type == AUTH_TYPE_SHARED_KEY) reg 846 drivers/staging/ks7010/ks_wlan_net.c priv->reg.authenticate_type = AUTH_TYPE_OPEN_SYSTEM; reg 848 drivers/staging/ks7010/ks_wlan_net.c if (priv->reg.authenticate_type == AUTH_TYPE_OPEN_SYSTEM) reg 851 drivers/staging/ks7010/ks_wlan_net.c priv->reg.authenticate_type = AUTH_TYPE_SHARED_KEY; reg 875 drivers/staging/ks7010/ks_wlan_net.c switch (priv->reg.authenticate_type) { reg 886 drivers/staging/ks7010/ks_wlan_net.c index = priv->reg.wep_index; reg 887 drivers/staging/ks7010/ks_wlan_net.c if (priv->reg.privacy_invoked) { reg 894 drivers/staging/ks7010/ks_wlan_net.c enc->length = (priv->reg.wep_key[index].size <= 16) ? reg 895 drivers/staging/ks7010/ks_wlan_net.c priv->reg.wep_key[index].size : 0; reg 896 drivers/staging/ks7010/ks_wlan_net.c memcpy(extra, priv->reg.wep_key[index].val, enc->length); reg 929 drivers/staging/ks7010/ks_wlan_net.c if (priv->reg.phy_type == D_11B_ONLY_MODE || reg 930 drivers/staging/ks7010/ks_wlan_net.c priv->reg.phy_type == D_11BG_COMPATIBLE_MODE) { /* channel 14 */ reg 943 drivers/staging/ks7010/ks_wlan_net.c if (priv->reg.phy_type == D_11B_ONLY_MODE) { reg 1043 drivers/staging/ks7010/ks_wlan_net.c priv->reg.power_mgmt = POWER_MGMT_ACTIVE; reg 1045 drivers/staging/ks7010/ks_wlan_net.c if (priv->reg.operation_mode != MODE_INFRASTRUCTURE) reg 1047 drivers/staging/ks7010/ks_wlan_net.c priv->reg.power_mgmt = POWER_MGMT_SAVE1; reg 1064 drivers/staging/ks7010/ks_wlan_net.c vwrq->power.disabled = (priv->reg.power_mgmt <= 0); reg 1392 drivers/staging/ks7010/ks_wlan_net.c if (priv->reg.privacy_invoked) { reg 1393 drivers/staging/ks7010/ks_wlan_net.c priv->reg.privacy_invoked = 0x00; reg 1401 drivers/staging/ks7010/ks_wlan_net.c if (!priv->reg.privacy_invoked) { reg 1402 drivers/staging/ks7010/ks_wlan_net.c priv->reg.privacy_invoked = 0x01; reg 1415 drivers/staging/ks7010/ks_wlan_net.c if (priv->reg.privacy_invoked) { reg 1416 drivers/staging/ks7010/ks_wlan_net.c priv->reg.privacy_invoked = 0x00; reg 1424 drivers/staging/ks7010/ks_wlan_net.c if (!priv->reg.privacy_invoked) { reg 1425 drivers/staging/ks7010/ks_wlan_net.c priv->reg.privacy_invoked = 0x01; reg 1452 drivers/staging/ks7010/ks_wlan_net.c priv->reg.authenticate_type = AUTH_TYPE_OPEN_SYSTEM; reg 1456 drivers/staging/ks7010/ks_wlan_net.c priv->reg.authenticate_type = AUTH_TYPE_SHARED_KEY; reg 1468 drivers/staging/ks7010/ks_wlan_net.c if ((value && !priv->reg.privacy_invoked) || reg 1469 drivers/staging/ks7010/ks_wlan_net.c (!value && priv->reg.privacy_invoked)) { reg 1470 drivers/staging/ks7010/ks_wlan_net.c priv->reg.privacy_invoked = value ? 0x01 : 0x00; reg 1571 drivers/staging/ks7010/ks_wlan_net.c if (priv->reg.privacy_invoked) { reg 1572 drivers/staging/ks7010/ks_wlan_net.c priv->reg.privacy_invoked = 0x00; reg 1580 drivers/staging/ks7010/ks_wlan_net.c if (!priv->reg.privacy_invoked) { reg 1581 drivers/staging/ks7010/ks_wlan_net.c priv->reg.privacy_invoked = 0x01; reg 1591 drivers/staging/ks7010/ks_wlan_net.c if (!priv->reg.privacy_invoked) { reg 1592 drivers/staging/ks7010/ks_wlan_net.c priv->reg.privacy_invoked = 0x01; reg 1827 drivers/staging/ks7010/ks_wlan_net.c priv->reg.preamble = *uwrq; reg 1842 drivers/staging/ks7010/ks_wlan_net.c *uwrq = priv->reg.preamble; reg 1861 drivers/staging/ks7010/ks_wlan_net.c (priv->reg.operation_mode != MODE_INFRASTRUCTURE)) reg 1864 drivers/staging/ks7010/ks_wlan_net.c priv->reg.power_mgmt = *uwrq; reg 1880 drivers/staging/ks7010/ks_wlan_net.c *uwrq = priv->reg.power_mgmt; reg 1897 drivers/staging/ks7010/ks_wlan_net.c priv->reg.scan_type = *uwrq; reg 1910 drivers/staging/ks7010/ks_wlan_net.c *uwrq = priv->reg.scan_type; reg 1926 drivers/staging/ks7010/ks_wlan_net.c priv->reg.beacon_lost_count = *uwrq; reg 1928 drivers/staging/ks7010/ks_wlan_net.c if (priv->reg.operation_mode == MODE_INFRASTRUCTURE) { reg 1945 drivers/staging/ks7010/ks_wlan_net.c *uwrq = priv->reg.beacon_lost_count; reg 1964 drivers/staging/ks7010/ks_wlan_net.c priv->reg.phy_type = *uwrq; reg 1978 drivers/staging/ks7010/ks_wlan_net.c *uwrq = priv->reg.phy_type; reg 1994 drivers/staging/ks7010/ks_wlan_net.c priv->reg.cts_mode = (*uwrq == CTS_MODE_FALSE) ? *uwrq : reg 1995 drivers/staging/ks7010/ks_wlan_net.c (priv->reg.phy_type == D_11G_ONLY_MODE || reg 1996 drivers/staging/ks7010/ks_wlan_net.c priv->reg.phy_type == D_11BG_COMPATIBLE_MODE) ? reg 2012 drivers/staging/ks7010/ks_wlan_net.c *uwrq = priv->reg.cts_mode; reg 326 drivers/staging/media/hantro/hantro.h u32 val, u32 reg) reg 328 drivers/staging/media/hantro/hantro.h vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); reg 329 drivers/staging/media/hantro/hantro.h writel_relaxed(val, vpu->enc_base + reg); reg 332 drivers/staging/media/hantro/hantro.h static inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg) reg 334 drivers/staging/media/hantro/hantro.h vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); reg 335 drivers/staging/media/hantro/hantro.h writel(val, vpu->enc_base + reg); reg 338 drivers/staging/media/hantro/hantro.h static inline u32 vepu_read(struct hantro_dev *vpu, u32 reg) reg 340 drivers/staging/media/hantro/hantro.h u32 val = readl(vpu->enc_base + reg); reg 342 drivers/staging/media/hantro/hantro.h vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); reg 347 drivers/staging/media/hantro/hantro.h u32 val, u32 reg) reg 349 drivers/staging/media/hantro/hantro.h vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); reg 350 drivers/staging/media/hantro/hantro.h writel_relaxed(val, vpu->dec_base + reg); reg 353 drivers/staging/media/hantro/hantro.h static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg) reg 355 drivers/staging/media/hantro/hantro.h vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); reg 356 drivers/staging/media/hantro/hantro.h writel(val, vpu->dec_base + reg); reg 359 drivers/staging/media/hantro/hantro.h static inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg) reg 361 drivers/staging/media/hantro/hantro.h u32 val = readl(vpu->dec_base + reg); reg 363 drivers/staging/media/hantro/hantro.h vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val); reg 368 drivers/staging/media/hantro/hantro.h const struct hantro_reg *reg, reg 373 drivers/staging/media/hantro/hantro.h v = vdpu_read(vpu, reg->base); reg 374 drivers/staging/media/hantro/hantro.h v &= ~(reg->mask << reg->shift); reg 375 drivers/staging/media/hantro/hantro.h v |= ((val & reg->mask) << reg->shift); reg 376 drivers/staging/media/hantro/hantro.h vdpu_write_relaxed(vpu, v, reg->base); reg 31 drivers/staging/media/hantro/hantro_g1_h264_dec.c u32 reg; reg 34 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg = G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(0x0); reg 36 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_DEC_CTRL0_SEQ_MBAFF_E; reg 38 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_DEC_CTRL0_PICORD_COUNT_E; reg 40 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_DEC_CTRL0_WRITE_MVS_E; reg 46 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_DEC_CTRL0_PIC_INTERLACE_E; reg 48 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_DEC_CTRL0_PIC_FIELDMODE_E; reg 50 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_DEC_CTRL0_PIC_TOPFIELD_E; reg 51 drivers/staging/media/hantro/hantro_g1_h264_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); reg 54 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg = G1_REG_DEC_CTRL1_PIC_MB_WIDTH(sps->pic_width_in_mbs_minus1 + 1) | reg 57 drivers/staging/media/hantro/hantro_g1_h264_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1); reg 60 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg = G1_REG_DEC_CTRL2_CH_QP_OFFSET(pps->chroma_qp_index_offset) | reg 64 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_DEC_CTRL2_TYPE1_QUANT_E; reg 67 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_DEC_CTRL2_FIELDPIC_FLAG_E; reg 68 drivers/staging/media/hantro/hantro_g1_h264_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2); reg 71 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg = G1_REG_DEC_CTRL3_START_CODE_E | reg 74 drivers/staging/media/hantro/hantro_g1_h264_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL3); reg 77 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg = G1_REG_DEC_CTRL4_FRAMENUM_LEN(sps->log2_max_frame_num_minus4 + 4) | reg 81 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_DEC_CTRL4_CABAC_E; reg 83 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_DEC_CTRL4_DIR_8X8_INFER_E; reg 85 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_DEC_CTRL4_BLACKWHITE_E; reg 87 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_DEC_CTRL4_WEIGHT_PRED_E; reg 88 drivers/staging/media/hantro/hantro_g1_h264_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4); reg 91 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg = G1_REG_DEC_CTRL5_REFPIC_MK_LEN(slices[0].dec_ref_pic_marking_bit_size) | reg 94 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_DEC_CTRL5_CONST_INTRA_E; reg 96 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_DEC_CTRL5_FILT_CTRL_PRES; reg 98 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_DEC_CTRL5_RDPIC_CNT_PRES; reg 100 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_DEC_CTRL5_8X8TRANS_FLAG_E; reg 102 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_DEC_CTRL5_IDR_PIC_E; reg 103 drivers/staging/media/hantro/hantro_g1_h264_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL5); reg 106 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg = G1_REG_DEC_CTRL6_PPS_ID(slices[0].pic_parameter_set_id) | reg 110 drivers/staging/media/hantro/hantro_g1_h264_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL6); reg 138 drivers/staging/media/hantro/hantro_g1_h264_dec.c u32 reg; reg 162 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg = 0; reg 164 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_REF_PIC_REFER0_NBR(dpb[i].pic_num); reg 166 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_REF_PIC_REFER0_NBR(dpb[i].frame_num); reg 169 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_REF_PIC_REFER1_NBR(dpb[i + 1].pic_num); reg 171 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg |= G1_REG_REF_PIC_REFER1_NBR(dpb[i + 1].frame_num); reg 173 drivers/staging/media/hantro/hantro_g1_h264_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(i / 2)); reg 186 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg = G1_REG_BD_REF_PIC_BINIT_RLIST_F0(b0_reflist[i]) | reg 192 drivers/staging/media/hantro/hantro_g1_h264_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_BD_REF_PIC(reg_num++)); reg 200 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg = G1_REG_BD_P_REF_PIC_BINIT_RLIST_F15(b0_reflist[15]) | reg 206 drivers/staging/media/hantro/hantro_g1_h264_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_BD_P_REF_PIC); reg 214 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg = G1_REG_FWD_PIC_PINIT_RLIST_F0(p_reflist[i]) | reg 220 drivers/staging/media/hantro/hantro_g1_h264_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(reg_num++)); reg 168 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c u32 reg; reg 181 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c reg = G1_REG_DEC_AXI_RD_ID(0) | reg 195 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c vdpu_write_relaxed(vpu, reg, G1_SWREG(2)); reg 197 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c reg = G1_REG_DEC_MODE(5) | reg 208 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c vdpu_write_relaxed(vpu, reg, G1_SWREG(3)); reg 210 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c reg = G1_REG_PIC_MB_WIDTH(MPEG2_MB_WIDTH(ctx->dst_fmt.width)) | reg 214 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c vdpu_write_relaxed(vpu, reg, G1_SWREG(4)); reg 216 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c reg = G1_REG_STRM_START_BIT(slice_params->data_bit_offset) | reg 222 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c vdpu_write_relaxed(vpu, reg, G1_SWREG(5)); reg 224 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c reg = G1_REG_INIT_QP(1) | reg 226 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c vdpu_write_relaxed(vpu, reg, G1_SWREG(6)); reg 228 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c reg = G1_REG_ALT_SCAN_FLAG_E(picture->alternate_scan) | reg 235 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c vdpu_write_relaxed(vpu, reg, G1_SWREG(18)); reg 237 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c reg = G1_REG_STARTMB_X(0) | reg 239 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c vdpu_write_relaxed(vpu, reg, G1_SWREG(48)); reg 241 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c reg = G1_REG_APF_THRESHOLD(8); reg 242 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c vdpu_write_relaxed(vpu, reg, G1_SWREG(55)); reg 252 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c reg = G1_REG_DEC_E(1); reg 253 drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c vdpu_write(vpu, reg, G1_SWREG(1)); reg 142 drivers/staging/media/hantro/hantro_g1_vp8_dec.c u32 reg; reg 159 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg = G1_REG_REF_PIC_FILT_SHARPNESS(lf->sharpness_level); reg 161 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg |= G1_REG_REF_PIC_FILT_TYPE_E; reg 162 drivers/staging/media/hantro/hantro_g1_vp8_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(0)); reg 240 drivers/staging/media/hantro/hantro_g1_vp8_dec.c struct hantro_reg reg; reg 274 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.base = G1_REG_DEC_CTRL2; reg 275 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.mask = 0x3f; reg 276 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.shift = 18; reg 277 drivers/staging/media/hantro/hantro_g1_vp8_dec.c hantro_reg_write(vpu, ®, mb_start_bits); reg 280 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.base = G1_REG_DEC_CTRL6; reg 281 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.mask = 0x3fffff; reg 282 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.shift = 0; reg 283 drivers/staging/media/hantro/hantro_g1_vp8_dec.c hantro_reg_write(vpu, ®, mb_size + 1); reg 301 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.base = G1_REG_DEC_CTRL6; reg 302 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.mask = 0xf; reg 303 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.shift = 24; reg 304 drivers/staging/media/hantro/hantro_g1_vp8_dec.c hantro_reg_write(vpu, ®, hdr->num_dct_parts - 1); reg 334 drivers/staging/media/hantro/hantro_g1_vp8_dec.c struct hantro_reg reg; reg 338 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.base = G1_REG_BD_REF_PIC(3); reg 339 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.mask = 0xf; reg 354 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.shift = 8; reg 357 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.shift = 4; reg 360 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.shift = 0; reg 366 drivers/staging/media/hantro/hantro_g1_vp8_dec.c hantro_reg_write(vpu, ®, val); reg 409 drivers/staging/media/hantro/hantro_g1_vp8_dec.c u32 reg; reg 418 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg = G1_REG_FWD_PIC1_SEGMENT_BASE(ctx->vp8_dec.segment_map.dma); reg 420 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg |= G1_REG_FWD_PIC1_SEGMENT_E; reg 422 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg |= G1_REG_FWD_PIC1_SEGMENT_UPD_E; reg 424 drivers/staging/media/hantro/hantro_g1_vp8_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(0)); reg 437 drivers/staging/media/hantro/hantro_g1_vp8_dec.c u32 reg; reg 452 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg = G1_REG_CONFIG_DEC_TIMEOUT_E | reg 461 drivers/staging/media/hantro/hantro_g1_vp8_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_CONFIG); reg 463 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg = G1_REG_DEC_CTRL0_DEC_MODE(10); reg 465 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg |= G1_REG_DEC_CTRL0_PIC_INTER_E; reg 467 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg |= G1_REG_DEC_CTRL0_SKIP_MODE; reg 469 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg |= G1_REG_DEC_CTRL0_FILTERING_DIS; reg 470 drivers/staging/media/hantro/hantro_g1_vp8_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); reg 475 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg = G1_REG_DEC_CTRL1_PIC_MB_WIDTH(mb_width) | reg 479 drivers/staging/media/hantro/hantro_g1_vp8_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL1); reg 482 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg = G1_REG_DEC_CTRL2_BOOLEAN_RANGE(hdr->coder_state.range) reg 484 drivers/staging/media/hantro/hantro_g1_vp8_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2); reg 486 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg = 0; reg 488 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg |= G1_REG_DEC_CTRL4_VC1_HEIGHT_EXT; reg 490 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg |= G1_REG_DEC_CTRL4_BILIN_MC_E; reg 491 drivers/staging/media/hantro/hantro_g1_vp8_dec.c vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL4); reg 22 drivers/staging/media/hantro/hantro_h1_jpeg_enc.c u32 reg; reg 24 drivers/staging/media/hantro/hantro_h1_jpeg_enc.c reg = H1_REG_IN_IMG_CTRL_ROW_LEN(pix_fmt->width) reg 28 drivers/staging/media/hantro/hantro_h1_jpeg_enc.c vepu_write_relaxed(vpu, reg, H1_REG_IN_IMG_CTRL); reg 69 drivers/staging/media/hantro/hantro_h1_jpeg_enc.c u32 reg, i; reg 77 drivers/staging/media/hantro/hantro_h1_jpeg_enc.c reg = get_unaligned_be32(&luma_qtable_p[i]); reg 78 drivers/staging/media/hantro/hantro_h1_jpeg_enc.c vepu_write_relaxed(vpu, reg, H1_REG_JPEG_LUMA_QUAT(i)); reg 80 drivers/staging/media/hantro/hantro_h1_jpeg_enc.c reg = get_unaligned_be32(&chroma_qtable_p[i]); reg 81 drivers/staging/media/hantro/hantro_h1_jpeg_enc.c vepu_write_relaxed(vpu, reg, H1_REG_JPEG_CHROMA_QUAT(i)); reg 90 drivers/staging/media/hantro/hantro_h1_jpeg_enc.c u32 reg; reg 114 drivers/staging/media/hantro/hantro_h1_jpeg_enc.c reg = H1_REG_AXI_CTRL_OUTPUT_SWAP16 reg 122 drivers/staging/media/hantro/hantro_h1_jpeg_enc.c vepu_write(vpu, reg, H1_REG_AXI_CTRL); reg 124 drivers/staging/media/hantro/hantro_h1_jpeg_enc.c reg = H1_REG_ENC_CTRL_WIDTH(JPEG_MB_WIDTH(ctx->src_fmt.width)) reg 132 drivers/staging/media/hantro/hantro_h1_jpeg_enc.c vepu_write(vpu, reg, H1_REG_ENC_CTRL); reg 40 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c u32 reg; reg 46 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c reg = VEPU_REG_IN_IMG_CTRL_ROW_LEN(pix_fmt->width); reg 47 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c vepu_write_relaxed(vpu, reg, VEPU_REG_INPUT_LUMA_INFO); reg 49 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c reg = VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(0) | reg 57 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_OVER_FILL_STRM_OFFSET); reg 59 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c reg = VEPU_REG_IN_IMG_CTRL_FMT(ctx->vpu_src_fmt->enc_fmt); reg 60 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_CTRL1); reg 100 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c u32 reg, i; reg 108 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c reg = get_unaligned_be32(&luma_qtable_p[i]); reg 109 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c vepu_write_relaxed(vpu, reg, VEPU_REG_JPEG_LUMA_QUAT(i)); reg 111 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c reg = get_unaligned_be32(&chroma_qtable_p[i]); reg 112 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c vepu_write_relaxed(vpu, reg, VEPU_REG_JPEG_CHROMA_QUAT(i)); reg 121 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c u32 reg; reg 145 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c reg = VEPU_REG_OUTPUT_SWAP32 reg 152 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c vepu_write(vpu, reg, VEPU_REG_DATA_ENDIAN); reg 154 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c reg = VEPU_REG_AXI_CTRL_BURST_LEN(16); reg 155 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c vepu_write_relaxed(vpu, reg, VEPU_REG_AXI_CTRL); reg 157 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c reg = VEPU_REG_MB_WIDTH(JPEG_MB_WIDTH(ctx->src_fmt.width)) reg 165 drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c vepu_write(vpu, reg, VEPU_REG_ENCODE_START); reg 170 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c u32 reg; reg 182 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c reg = VDPU_REG_DEC_ADV_PRE_DIS(0) | reg 186 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50)); reg 188 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c reg = VDPU_REG_INIT_QP(1) | reg 190 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51)); reg 192 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c reg = VDPU_REG_APF_THRESHOLD(8) | reg 195 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52)); reg 197 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c reg = VDPU_REG_DEC_MODE(5); reg 198 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53)); reg 200 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c reg = VDPU_REG_DEC_STRENDIAN_E(1) | reg 206 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54)); reg 208 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c reg = VDPU_REG_DEC_DATA_DISC_E(0) | reg 212 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56)); reg 214 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c reg = VDPU_REG_RLC_MODE_E(0) | reg 224 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57)); reg 226 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c reg = VDPU_REG_PIC_MB_WIDTH(MPEG2_MB_WIDTH(ctx->dst_fmt.width)) | reg 230 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c vdpu_write_relaxed(vpu, reg, VDPU_SWREG(120)); reg 232 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c reg = VDPU_REG_STRM_START_BIT(slice_params->data_bit_offset) | reg 238 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c vdpu_write_relaxed(vpu, reg, VDPU_SWREG(122)); reg 240 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c reg = VDPU_REG_ALT_SCAN_FLAG_E(picture->alternate_scan) | reg 247 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c vdpu_write_relaxed(vpu, reg, VDPU_SWREG(136)); reg 258 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c reg = vdpu_read(vpu, VDPU_SWREG(57)) | VDPU_REG_DEC_E(1); reg 259 drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c vdpu_write(vpu, reg, VDPU_SWREG(57)); reg 283 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c u32 reg; reg 300 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c reg = VDPU_REG_REF_PIC_FILT_SHARPNESS(lf->sharpness_level); reg 302 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c reg |= VDPU_REG_REF_PIC_FILT_TYPE_E; reg 303 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c vdpu_write_relaxed(vpu, reg, VDPU_REG_FILTER_MB_ADJ); reg 487 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c u32 reg; reg 496 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c reg = VDPU_REG_FWD_PIC1_SEGMENT_BASE(ctx->vp8_dec.segment_map.dma); reg 498 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c reg |= VDPU_REG_FWD_PIC1_SEGMENT_E; reg 500 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c reg |= VDPU_REG_FWD_PIC1_SEGMENT_UPD_E; reg 502 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c vdpu_write_relaxed(vpu, reg, VDPU_REG_VP8_SEGMENT_VAL); reg 516 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c u32 reg; reg 540 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c reg = VDPU_REG_CONFIG_DEC_TIMEOUT_E reg 543 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c reg |= VDPU_REG_DEC_CTRL0_PIC_INTER_E; reg 544 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c vdpu_write_relaxed(vpu, reg, VDPU_REG_EN_FLAGS); reg 546 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c reg = VDPU_REG_CONFIG_DEC_STRENDIAN_E reg 552 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c vdpu_write_relaxed(vpu, reg, VDPU_REG_DATA_ENDIAN); reg 554 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c reg = VDPU_REG_CONFIG_DEC_MAX_BURST(16); reg 555 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c vdpu_write_relaxed(vpu, reg, VDPU_REG_AXI_CTRL); reg 557 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c reg = VDPU_REG_DEC_CTRL0_DEC_MODE(10); reg 558 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c vdpu_write_relaxed(vpu, reg, VDPU_REG_DEC_FORMAT); reg 578 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c reg = vdpu_read(vpu, VDPU_REG_VP8_DCT_START_BIT); reg 580 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c reg |= VDPU_REG_DEC_CTRL4_VC1_HEIGHT_EXT; reg 582 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c reg |= VDPU_REG_DEC_CTRL4_BILIN_MC_E; reg 583 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c vdpu_write_relaxed(vpu, reg, VDPU_REG_VP8_DCT_START_BIT); reg 223 drivers/staging/media/imx/imx6-mipi-csi2.c u32 reg; reg 227 drivers/staging/media/imx/imx6-mipi-csi2.c ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg, reg 228 drivers/staging/media/imx/imx6-mipi-csi2.c !(reg & PHY_RXULPSCLKNOT), 0, 500000); reg 230 drivers/staging/media/imx/imx6-mipi-csi2.c v4l2_err(&csi2->sd, "ULP timeout, phy_state = 0x%08x\n", reg); reg 235 drivers/staging/media/imx/imx6-mipi-csi2.c ret = readl_poll_timeout(csi2->base + CSI2_ERR1, reg, reg 236 drivers/staging/media/imx/imx6-mipi-csi2.c reg == 0x0, 0, 500000); reg 238 drivers/staging/media/imx/imx6-mipi-csi2.c v4l2_err(&csi2->sd, "stable bus timeout, err1 = 0x%08x\n", reg); reg 248 drivers/staging/media/imx/imx6-mipi-csi2.c u32 mask, reg; reg 254 drivers/staging/media/imx/imx6-mipi-csi2.c ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg, reg 255 drivers/staging/media/imx/imx6-mipi-csi2.c (reg & mask) == mask, 0, 500000); reg 258 drivers/staging/media/imx/imx6-mipi-csi2.c v4l2_warn(&csi2->sd, "phy_state = 0x%08x\n", reg); reg 265 drivers/staging/media/imx/imx6-mipi-csi2.c u32 reg; reg 268 drivers/staging/media/imx/imx6-mipi-csi2.c ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg, reg 269 drivers/staging/media/imx/imx6-mipi-csi2.c (reg & PHY_RXCLKACTIVEHS), 0, 500000); reg 272 drivers/staging/media/imx/imx6-mipi-csi2.c reg); reg 282 drivers/staging/media/imx/imx6-mipi-csi2.c u32 reg = 0; reg 287 drivers/staging/media/imx/imx6-mipi-csi2.c reg = CSI2IPU_YUV422_YUYV; reg 293 drivers/staging/media/imx/imx6-mipi-csi2.c writel(reg, csi2->base + CSI2IPU_GASKET); reg 203 drivers/staging/media/ipu3/ipu3-css.c static int imgu_hw_wait(void __iomem *base, int reg, u32 mask, u32 cmp) reg 207 drivers/staging/media/ipu3/ipu3-css.c return readl_poll_timeout(base + reg, val, (val & mask) == cmp, reg 378 drivers/staging/media/ipu3/ipu3-css.c u32 reg; reg 456 drivers/staging/media/ipu3/ipu3-css.c val = readl(base + stream_monitors[i].reg); reg 156 drivers/staging/media/meson/vdec/codec_mpeg12.c u32 reg; reg 164 drivers/staging/media/meson/vdec/codec_mpeg12.c reg = amvdec_read_dos(core, MREG_FATAL_ERROR); reg 165 drivers/staging/media/meson/vdec/codec_mpeg12.c if (reg == 1) { reg 171 drivers/staging/media/meson/vdec/codec_mpeg12.c reg = amvdec_read_dos(core, MREG_BUFFEROUT); reg 172 drivers/staging/media/meson/vdec/codec_mpeg12.c if (!reg) reg 176 drivers/staging/media/meson/vdec/codec_mpeg12.c if ((reg & GENMASK(23, 17)) == GENMASK(23, 17)) reg 188 drivers/staging/media/meson/vdec/codec_mpeg12.c buffer_index = ((reg & 0xf) - 1) & 7; reg 17 drivers/staging/media/meson/vdec/vdec_helpers.c u32 amvdec_read_dos(struct amvdec_core *core, u32 reg) reg 19 drivers/staging/media/meson/vdec/vdec_helpers.c return readl_relaxed(core->dos_base + reg); reg 23 drivers/staging/media/meson/vdec/vdec_helpers.c void amvdec_write_dos(struct amvdec_core *core, u32 reg, u32 val) reg 25 drivers/staging/media/meson/vdec/vdec_helpers.c writel_relaxed(val, core->dos_base + reg); reg 29 drivers/staging/media/meson/vdec/vdec_helpers.c void amvdec_write_dos_bits(struct amvdec_core *core, u32 reg, u32 val) reg 31 drivers/staging/media/meson/vdec/vdec_helpers.c amvdec_write_dos(core, reg, amvdec_read_dos(core, reg) | val); reg 35 drivers/staging/media/meson/vdec/vdec_helpers.c void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val) reg 37 drivers/staging/media/meson/vdec/vdec_helpers.c amvdec_write_dos(core, reg, amvdec_read_dos(core, reg) & ~val); reg 41 drivers/staging/media/meson/vdec/vdec_helpers.c u32 amvdec_read_parser(struct amvdec_core *core, u32 reg) reg 43 drivers/staging/media/meson/vdec/vdec_helpers.c return readl_relaxed(core->esparser_base + reg); reg 47 drivers/staging/media/meson/vdec/vdec_helpers.c void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val) reg 49 drivers/staging/media/meson/vdec/vdec_helpers.c writel_relaxed(val, core->esparser_base + reg); reg 72 drivers/staging/media/meson/vdec/vdec_helpers.c u32 height, u32 reg) reg 106 drivers/staging/media/meson/vdec/vdec_helpers.c amvdec_write_dos(core, reg, reg 116 drivers/staging/media/meson/vdec/vdec_helpers.c u32 height, u32 reg) reg 144 drivers/staging/media/meson/vdec/vdec_helpers.c amvdec_write_dos(core, reg, reg 23 drivers/staging/media/meson/vdec/vdec_helpers.h u32 amvdec_read_dos(struct amvdec_core *core, u32 reg); reg 24 drivers/staging/media/meson/vdec/vdec_helpers.h void amvdec_write_dos(struct amvdec_core *core, u32 reg, u32 val); reg 25 drivers/staging/media/meson/vdec/vdec_helpers.h void amvdec_write_dos_bits(struct amvdec_core *core, u32 reg, u32 val); reg 26 drivers/staging/media/meson/vdec/vdec_helpers.h void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val); reg 27 drivers/staging/media/meson/vdec/vdec_helpers.h u32 amvdec_read_parser(struct amvdec_core *core, u32 reg); reg 28 drivers/staging/media/meson/vdec/vdec_helpers.h void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val); reg 76 drivers/staging/media/omap4iss/iss.h u32 reg; reg 42 drivers/staging/media/omap4iss/iss_csi2.c u32 reg = 0; reg 45 drivers/staging/media/omap4iss/iss_csi2.c reg |= CSI2_CTRL_FRAME; reg 47 drivers/staging/media/omap4iss/iss_csi2.c reg &= ~CSI2_CTRL_FRAME; reg 50 drivers/staging/media/omap4iss/iss_csi2.c reg |= CSI2_CTRL_VP_CLK_EN; reg 52 drivers/staging/media/omap4iss/iss_csi2.c reg &= ~CSI2_CTRL_VP_CLK_EN; reg 55 drivers/staging/media/omap4iss/iss_csi2.c reg |= CSI2_CTRL_VP_ONLY_EN; reg 57 drivers/staging/media/omap4iss/iss_csi2.c reg &= ~CSI2_CTRL_VP_ONLY_EN; reg 59 drivers/staging/media/omap4iss/iss_csi2.c reg &= ~CSI2_CTRL_VP_OUT_CTRL_MASK; reg 60 drivers/staging/media/omap4iss/iss_csi2.c reg |= currctrl->vp_out_ctrl << CSI2_CTRL_VP_OUT_CTRL_SHIFT; reg 63 drivers/staging/media/omap4iss/iss_csi2.c reg |= CSI2_CTRL_ECC_EN; reg 65 drivers/staging/media/omap4iss/iss_csi2.c reg &= ~CSI2_CTRL_ECC_EN; reg 72 drivers/staging/media/omap4iss/iss_csi2.c reg &= ~(CSI2_CTRL_MFLAG_LEVH_MASK | CSI2_CTRL_MFLAG_LEVL_MASK); reg 73 drivers/staging/media/omap4iss/iss_csi2.c reg |= (2 << CSI2_CTRL_MFLAG_LEVH_SHIFT) | reg 77 drivers/staging/media/omap4iss/iss_csi2.c reg |= CSI2_CTRL_BURST_SIZE_EXPAND; reg 80 drivers/staging/media/omap4iss/iss_csi2.c reg |= CSI2_CTRL_NON_POSTED_WRITE; reg 86 drivers/staging/media/omap4iss/iss_csi2.c reg |= CSI2_CTRL_ENDIANNESS; reg 88 drivers/staging/media/omap4iss/iss_csi2.c iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTRL, reg); reg 284 drivers/staging/media/omap4iss/iss_csi2.c u32 reg; reg 286 drivers/staging/media/omap4iss/iss_csi2.c reg = iss_reg_read(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctxnum)); reg 296 drivers/staging/media/omap4iss/iss_csi2.c reg &= ~CSI2_CTX_CTRL1_COUNT_MASK; reg 297 drivers/staging/media/omap4iss/iss_csi2.c reg |= CSI2_CTX_CTRL1_COUNT_UNLOCK reg 301 drivers/staging/media/omap4iss/iss_csi2.c reg &= ~CSI2_CTX_CTRL1_CTX_EN; reg 304 drivers/staging/media/omap4iss/iss_csi2.c iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctxnum), reg); reg 316 drivers/staging/media/omap4iss/iss_csi2.c u32 reg = 0; reg 322 drivers/staging/media/omap4iss/iss_csi2.c reg = CSI2_CTX_CTRL1_EOF_EN; reg 325 drivers/staging/media/omap4iss/iss_csi2.c reg |= CSI2_CTX_CTRL1_EOL_EN; reg 328 drivers/staging/media/omap4iss/iss_csi2.c reg |= CSI2_CTX_CTRL1_CS_EN; reg 330 drivers/staging/media/omap4iss/iss_csi2.c iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctx->ctxnum), reg); reg 333 drivers/staging/media/omap4iss/iss_csi2.c reg = ctx->virtual_id << CSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT; reg 334 drivers/staging/media/omap4iss/iss_csi2.c reg |= ctx->format_id << CSI2_CTX_CTRL2_FORMAT_SHIFT; reg 337 drivers/staging/media/omap4iss/iss_csi2.c reg |= CSI2_CTX_CTRL2_DPCM_PRED; reg 340 drivers/staging/media/omap4iss/iss_csi2.c reg |= 2 << CSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT; reg 342 drivers/staging/media/omap4iss/iss_csi2.c iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL2(ctx->ctxnum), reg); reg 365 drivers/staging/media/omap4iss/iss_csi2.c u32 reg; reg 367 drivers/staging/media/omap4iss/iss_csi2.c reg = iss_reg_read(csi2->iss, csi2->regs1, CSI2_TIMING); reg 370 drivers/staging/media/omap4iss/iss_csi2.c reg |= CSI2_TIMING_FORCE_RX_MODE_IO1; reg 372 drivers/staging/media/omap4iss/iss_csi2.c reg &= ~CSI2_TIMING_FORCE_RX_MODE_IO1; reg 375 drivers/staging/media/omap4iss/iss_csi2.c reg |= CSI2_TIMING_STOP_STATE_X16_IO1; reg 377 drivers/staging/media/omap4iss/iss_csi2.c reg &= ~CSI2_TIMING_STOP_STATE_X16_IO1; reg 380 drivers/staging/media/omap4iss/iss_csi2.c reg |= CSI2_TIMING_STOP_STATE_X4_IO1; reg 382 drivers/staging/media/omap4iss/iss_csi2.c reg &= ~CSI2_TIMING_STOP_STATE_X4_IO1; reg 384 drivers/staging/media/omap4iss/iss_csi2.c reg &= ~CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK; reg 385 drivers/staging/media/omap4iss/iss_csi2.c reg |= timing->stop_state_counter << reg 388 drivers/staging/media/omap4iss/iss_csi2.c iss_reg_write(csi2->iss, csi2->regs1, CSI2_TIMING, reg); reg 418 drivers/staging/media/omap4iss/iss_csi2.c u32 reg; reg 420 drivers/staging/media/omap4iss/iss_csi2.c reg = CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT | reg 447 drivers/staging/media/omap4iss/iss_csi2.c iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQSTATUS, reg); reg 450 drivers/staging/media/omap4iss/iss_csi2.c reg); reg 462 drivers/staging/media/omap4iss/iss_csi2.c u32 reg; reg 464 drivers/staging/media/omap4iss/iss_csi2.c reg = CSI2_IRQ_OCP_ERR | reg 471 drivers/staging/media/omap4iss/iss_csi2.c iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQSTATUS, reg); reg 473 drivers/staging/media/omap4iss/iss_csi2.c iss_reg_set(csi2->iss, csi2->regs1, CSI2_IRQENABLE, reg); reg 29 drivers/staging/media/omap4iss/iss_csiphy.c u32 reg; reg 31 drivers/staging/media/omap4iss/iss_csiphy.c reg = iss_reg_read(phy->iss, phy->cfg_regs, CSI2_COMPLEXIO_CFG); reg 34 drivers/staging/media/omap4iss/iss_csiphy.c reg &= ~(CSI2_COMPLEXIO_CFG_DATA_POL(i + 1) | reg 36 drivers/staging/media/omap4iss/iss_csiphy.c reg |= (phy->lanes.data[i].pol ? reg 38 drivers/staging/media/omap4iss/iss_csiphy.c reg |= (phy->lanes.data[i].pos << reg 42 drivers/staging/media/omap4iss/iss_csiphy.c reg &= ~(CSI2_COMPLEXIO_CFG_CLOCK_POL | reg 44 drivers/staging/media/omap4iss/iss_csiphy.c reg |= phy->lanes.clk.pol ? CSI2_COMPLEXIO_CFG_CLOCK_POL : 0; reg 45 drivers/staging/media/omap4iss/iss_csiphy.c reg |= phy->lanes.clk.pos << CSI2_COMPLEXIO_CFG_CLOCK_POSITION_SHIFT; reg 47 drivers/staging/media/omap4iss/iss_csiphy.c iss_reg_write(phy->iss, phy->cfg_regs, CSI2_COMPLEXIO_CFG, reg); reg 58 drivers/staging/media/omap4iss/iss_csiphy.c u32 reg; reg 68 drivers/staging/media/omap4iss/iss_csiphy.c reg = iss_reg_read(phy->iss, phy->cfg_regs, CSI2_COMPLEXIO_CFG) reg 71 drivers/staging/media/omap4iss/iss_csiphy.c if (reg != power >> 2) reg 74 drivers/staging/media/omap4iss/iss_csiphy.c } while ((reg != power >> 2) && (retry_count < 250)); reg 91 drivers/staging/media/omap4iss/iss_csiphy.c u32 reg; reg 94 drivers/staging/media/omap4iss/iss_csiphy.c reg = phy->dphy.ths_term << REGISTER0_THS_TERM_SHIFT; reg 95 drivers/staging/media/omap4iss/iss_csiphy.c reg |= phy->dphy.ths_settle << REGISTER0_THS_SETTLE_SHIFT; reg 97 drivers/staging/media/omap4iss/iss_csiphy.c iss_reg_write(phy->iss, phy->phy_regs, REGISTER0, reg); reg 100 drivers/staging/media/omap4iss/iss_csiphy.c reg = phy->dphy.tclk_term << REGISTER1_TCLK_TERM_SHIFT; reg 101 drivers/staging/media/omap4iss/iss_csiphy.c reg |= phy->dphy.tclk_miss << REGISTER1_CTRLCLK_DIV_FACTOR_SHIFT; reg 102 drivers/staging/media/omap4iss/iss_csiphy.c reg |= phy->dphy.tclk_settle << REGISTER1_TCLK_SETTLE_SHIFT; reg 103 drivers/staging/media/omap4iss/iss_csiphy.c reg |= 0xb8 << REGISTER1_DPHY_HS_SYNC_PATTERN_SHIFT; reg 105 drivers/staging/media/omap4iss/iss_csiphy.c iss_reg_write(phy->iss, phy->phy_regs, REGISTER1, reg); reg 87 drivers/staging/media/soc_camera/mt9t031.c static int reg_read(struct i2c_client *client, const u8 reg) reg 89 drivers/staging/media/soc_camera/mt9t031.c return i2c_smbus_read_word_swapped(client, reg); reg 92 drivers/staging/media/soc_camera/mt9t031.c static int reg_write(struct i2c_client *client, const u8 reg, reg 95 drivers/staging/media/soc_camera/mt9t031.c return i2c_smbus_write_word_swapped(client, reg, data); reg 98 drivers/staging/media/soc_camera/mt9t031.c static int reg_set(struct i2c_client *client, const u8 reg, reg 103 drivers/staging/media/soc_camera/mt9t031.c ret = reg_read(client, reg); reg 106 drivers/staging/media/soc_camera/mt9t031.c return reg_write(client, reg, ret | data); reg 109 drivers/staging/media/soc_camera/mt9t031.c static int reg_clear(struct i2c_client *client, const u8 reg, reg 114 drivers/staging/media/soc_camera/mt9t031.c ret = reg_read(client, reg); reg 117 drivers/staging/media/soc_camera/mt9t031.c return reg_write(client, reg, ret & ~data); reg 406 drivers/staging/media/soc_camera/mt9t031.c struct v4l2_dbg_register *reg) reg 410 drivers/staging/media/soc_camera/mt9t031.c if (reg->reg > 0xff) reg 413 drivers/staging/media/soc_camera/mt9t031.c reg->size = 1; reg 414 drivers/staging/media/soc_camera/mt9t031.c reg->val = reg_read(client, reg->reg); reg 416 drivers/staging/media/soc_camera/mt9t031.c if (reg->val > 0xffff) reg 423 drivers/staging/media/soc_camera/mt9t031.c const struct v4l2_dbg_register *reg) reg 427 drivers/staging/media/soc_camera/mt9t031.c if (reg->reg > 0xff) reg 430 drivers/staging/media/soc_camera/mt9t031.c if (reg_write(client, reg->reg, reg->val) < 0) reg 156 drivers/staging/media/soc_camera/soc_mt9v022.c const struct mt9v02x_register *reg; reg 169 drivers/staging/media/soc_camera/soc_mt9v022.c static int reg_read(struct i2c_client *client, const u8 reg) reg 171 drivers/staging/media/soc_camera/soc_mt9v022.c return i2c_smbus_read_word_swapped(client, reg); reg 174 drivers/staging/media/soc_camera/soc_mt9v022.c static int reg_write(struct i2c_client *client, const u8 reg, reg 177 drivers/staging/media/soc_camera/soc_mt9v022.c return i2c_smbus_write_word_swapped(client, reg, data); reg 180 drivers/staging/media/soc_camera/soc_mt9v022.c static int reg_set(struct i2c_client *client, const u8 reg, reg 185 drivers/staging/media/soc_camera/soc_mt9v022.c ret = reg_read(client, reg); reg 188 drivers/staging/media/soc_camera/soc_mt9v022.c return reg_write(client, reg, ret | data); reg 191 drivers/staging/media/soc_camera/soc_mt9v022.c static int reg_clear(struct i2c_client *client, const u8 reg, reg 196 drivers/staging/media/soc_camera/soc_mt9v022.c ret = reg_read(client, reg); reg 199 drivers/staging/media/soc_camera/soc_mt9v022.c return reg_write(client, reg, ret & ~data); reg 226 drivers/staging/media/soc_camera/soc_mt9v022.c ret = reg_write(client, mt9v022->reg->max_total_shutter_width, 480); reg 306 drivers/staging/media/soc_camera/soc_mt9v022.c ret = reg_write(client, mt9v022->reg->max_total_shutter_width, reg 483 drivers/staging/media/soc_camera/soc_mt9v022.c struct v4l2_dbg_register *reg) reg 487 drivers/staging/media/soc_camera/soc_mt9v022.c if (reg->reg > 0xff) reg 490 drivers/staging/media/soc_camera/soc_mt9v022.c reg->size = 2; reg 491 drivers/staging/media/soc_camera/soc_mt9v022.c reg->val = reg_read(client, reg->reg); reg 493 drivers/staging/media/soc_camera/soc_mt9v022.c if (reg->val > 0xffff) reg 500 drivers/staging/media/soc_camera/soc_mt9v022.c const struct v4l2_dbg_register *reg) reg 504 drivers/staging/media/soc_camera/soc_mt9v022.c if (reg->reg > 0xff) reg 507 drivers/staging/media/soc_camera/soc_mt9v022.c if (reg_write(client, reg->reg, reg->val) < 0) reg 687 drivers/staging/media/soc_camera/soc_mt9v022.c mt9v022->reg = is_mt9v024(data) ? &mt9v024_register : reg 839 drivers/staging/media/soc_camera/soc_mt9v022.c ret = reg_write(client, mt9v022->reg->pixclk_fv_lv, pixclk); reg 638 drivers/staging/media/soc_camera/soc_ov5642.c static int reg_read(struct i2c_client *client, u16 reg, u8 *val) reg 642 drivers/staging/media/soc_camera/soc_ov5642.c unsigned char data[2] = { reg >> 8, reg & 0xff }; reg 647 drivers/staging/media/soc_camera/soc_ov5642.c __func__, reg); reg 654 drivers/staging/media/soc_camera/soc_ov5642.c __func__, reg); reg 660 drivers/staging/media/soc_camera/soc_ov5642.c static int reg_write(struct i2c_client *client, u16 reg, u8 val) reg 663 drivers/staging/media/soc_camera/soc_ov5642.c unsigned char data[3] = { reg >> 8, reg & 0xff, val }; reg 668 drivers/staging/media/soc_camera/soc_ov5642.c __func__, reg); reg 679 drivers/staging/media/soc_camera/soc_ov5642.c static int reg_write16(struct i2c_client *client, u16 reg, u16 val16) reg 683 drivers/staging/media/soc_camera/soc_ov5642.c ret = reg_write(client, reg, val16 >> 8); reg 686 drivers/staging/media/soc_camera/soc_ov5642.c return reg_write(client, reg + 1, val16 & 0x00ff); reg 691 drivers/staging/media/soc_camera/soc_ov5642.c struct v4l2_dbg_register *reg) reg 697 drivers/staging/media/soc_camera/soc_ov5642.c if (reg->reg & ~0xffff) reg 700 drivers/staging/media/soc_camera/soc_ov5642.c reg->size = 1; reg 702 drivers/staging/media/soc_camera/soc_ov5642.c ret = reg_read(client, reg->reg, &val); reg 704 drivers/staging/media/soc_camera/soc_ov5642.c reg->val = (__u64)val; reg 710 drivers/staging/media/soc_camera/soc_ov5642.c const struct v4l2_dbg_register *reg) reg 714 drivers/staging/media/soc_camera/soc_ov5642.c if (reg->reg & ~0xffff || reg->val & ~0xff) reg 717 drivers/staging/media/soc_camera/soc_ov5642.c return reg_write(client, reg->reg, reg->val); reg 188 drivers/staging/media/soc_camera/soc_ov9740.c u16 reg; reg 396 drivers/staging/media/soc_camera/soc_ov9740.c static int ov9740_reg_read(struct i2c_client *client, u16 reg, u8 *val) reg 404 drivers/staging/media/soc_camera/soc_ov9740.c .buf = (u8 *)®, reg 414 drivers/staging/media/soc_camera/soc_ov9740.c reg = swab16(reg); reg 418 drivers/staging/media/soc_camera/soc_ov9740.c dev_err(&client->dev, "Failed reading register 0x%04x!\n", reg); reg 426 drivers/staging/media/soc_camera/soc_ov9740.c static int ov9740_reg_write(struct i2c_client *client, u16 reg, u8 val) reg 430 drivers/staging/media/soc_camera/soc_ov9740.c u16 reg; reg 435 drivers/staging/media/soc_camera/soc_ov9740.c reg = swab16(reg); reg 437 drivers/staging/media/soc_camera/soc_ov9740.c buf.reg = reg; reg 447 drivers/staging/media/soc_camera/soc_ov9740.c dev_err(&client->dev, "Failed writing register 0x%04x!\n", reg); reg 456 drivers/staging/media/soc_camera/soc_ov9740.c static int ov9740_reg_rmw(struct i2c_client *client, u16 reg, u8 set, u8 unset) reg 461 drivers/staging/media/soc_camera/soc_ov9740.c ret = ov9740_reg_read(client, reg, &val); reg 465 drivers/staging/media/soc_camera/soc_ov9740.c reg); reg 472 drivers/staging/media/soc_camera/soc_ov9740.c ret = ov9740_reg_write(client, reg, val); reg 476 drivers/staging/media/soc_camera/soc_ov9740.c reg); reg 492 drivers/staging/media/soc_camera/soc_ov9740.c regarray[i].reg, regarray[i].val); reg 790 drivers/staging/media/soc_camera/soc_ov9740.c struct v4l2_dbg_register *reg) reg 796 drivers/staging/media/soc_camera/soc_ov9740.c if (reg->reg & ~0xffff) reg 799 drivers/staging/media/soc_camera/soc_ov9740.c reg->size = 2; reg 801 drivers/staging/media/soc_camera/soc_ov9740.c ret = ov9740_reg_read(client, reg->reg, &val); reg 805 drivers/staging/media/soc_camera/soc_ov9740.c reg->val = (__u64)val; reg 811 drivers/staging/media/soc_camera/soc_ov9740.c const struct v4l2_dbg_register *reg) reg 815 drivers/staging/media/soc_camera/soc_ov9740.c if (reg->reg & ~0xffff || reg->val & ~0xff) reg 818 drivers/staging/media/soc_camera/soc_ov9740.c return ov9740_reg_write(client, reg->reg, reg->val); reg 159 drivers/staging/media/sunxi/cedrus/cedrus.h static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val) reg 161 drivers/staging/media/sunxi/cedrus/cedrus.h writel(val, dev->base + reg); reg 164 drivers/staging/media/sunxi/cedrus/cedrus.h static inline u32 cedrus_read(struct cedrus_dev *dev, u32 reg) reg 166 drivers/staging/media/sunxi/cedrus/cedrus.h return readl(dev->base + reg); reg 308 drivers/staging/media/sunxi/cedrus/cedrus_h264.c u32 reg; reg 346 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg = 0; reg 351 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= (slice->num_ref_idx_l0_active_minus1 & 0x1f) << 10; reg 352 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= (slice->num_ref_idx_l1_active_minus1 & 0x1f) << 5; reg 353 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= (pps->weighted_bipred_idc & 0x3) << 2; reg 355 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= VE_H264_PPS_ENTROPY_CODING_MODE; reg 357 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= VE_H264_PPS_WEIGHTED_PRED; reg 359 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= VE_H264_PPS_CONSTRAINED_INTRA_PRED; reg 361 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= VE_H264_PPS_TRANSFORM_8X8_MODE; reg 362 drivers/staging/media/sunxi/cedrus/cedrus_h264.c cedrus_write(dev, VE_H264_PPS, reg); reg 365 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg = 0; reg 366 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= (sps->chroma_format_idc & 0x7) << 19; reg 367 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= (sps->pic_width_in_mbs_minus1 & 0xff) << 8; reg 368 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= sps->pic_height_in_map_units_minus1 & 0xff; reg 370 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= VE_H264_SPS_MBS_ONLY; reg 372 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD; reg 374 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= VE_H264_SPS_DIRECT_8X8_INFERENCE; reg 375 drivers/staging/media/sunxi/cedrus/cedrus_h264.c cedrus_write(dev, VE_H264_SPS, reg); reg 378 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg = 0; reg 379 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= decode->nal_ref_idc ? BIT(12) : 0; reg 380 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= (slice->slice_type & 0xf) << 8; reg 381 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= slice->cabac_init_idc & 0x3; reg 382 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= VE_H264_SHS_FIRST_SLICE_IN_PIC; reg 384 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= VE_H264_SHS_FIELD_PIC; reg 386 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= VE_H264_SHS_BOTTOM_FIELD; reg 388 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= VE_H264_SHS_DIRECT_SPATIAL_MV_PRED; reg 389 drivers/staging/media/sunxi/cedrus/cedrus_h264.c cedrus_write(dev, VE_H264_SHS, reg); reg 391 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg = 0; reg 392 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= VE_H264_SHS2_NUM_REF_IDX_ACTIVE_OVRD; reg 393 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= (slice->num_ref_idx_l0_active_minus1 & 0x1f) << 24; reg 394 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= (slice->num_ref_idx_l1_active_minus1 & 0x1f) << 16; reg 395 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= (slice->disable_deblocking_filter_idc & 0x3) << 8; reg 396 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= (slice->slice_alpha_c0_offset_div2 & 0xf) << 4; reg 397 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= slice->slice_beta_offset_div2 & 0xf; reg 398 drivers/staging/media/sunxi/cedrus/cedrus_h264.c cedrus_write(dev, VE_H264_SHS2, reg); reg 400 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg = 0; reg 401 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= (pps->second_chroma_qp_index_offset & 0x3f) << 16; reg 402 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= (pps->chroma_qp_index_offset & 0x3f) << 8; reg 403 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= (pps->pic_init_qp_minus26 + 26 + slice->slice_qp_delta) & 0x3f; reg 404 drivers/staging/media/sunxi/cedrus/cedrus_h264.c cedrus_write(dev, VE_H264_SHS_QP, reg); reg 420 drivers/staging/media/sunxi/cedrus/cedrus_h264.c u32 reg = cedrus_read(dev, VE_H264_STATUS); reg 422 drivers/staging/media/sunxi/cedrus/cedrus_h264.c if (reg & (VE_H264_STATUS_DECODE_ERR_INT | reg 426 drivers/staging/media/sunxi/cedrus/cedrus_h264.c if (reg & VE_H264_CTRL_SLICE_DECODE_INT) reg 443 drivers/staging/media/sunxi/cedrus/cedrus_h264.c u32 reg = cedrus_read(dev, VE_H264_CTRL); reg 446 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg & ~VE_H264_CTRL_INT_MASK); reg 35 drivers/staging/media/sunxi/cedrus/cedrus_hw.c u32 reg = 0; reg 41 drivers/staging/media/sunxi/cedrus/cedrus_hw.c reg |= VE_MODE_REC_WR_MODE_2MB; reg 42 drivers/staging/media/sunxi/cedrus/cedrus_hw.c reg |= VE_MODE_DDR_MODE_BW_128; reg 46 drivers/staging/media/sunxi/cedrus/cedrus_hw.c reg |= VE_MODE_DEC_MPEG; reg 50 drivers/staging/media/sunxi/cedrus/cedrus_hw.c reg |= VE_MODE_DEC_H264; reg 57 drivers/staging/media/sunxi/cedrus/cedrus_hw.c cedrus_write(dev, VE_MODE, reg); reg 73 drivers/staging/media/sunxi/cedrus/cedrus_hw.c u32 reg; reg 79 drivers/staging/media/sunxi/cedrus/cedrus_hw.c reg = VE_PRIMARY_OUT_FMT_NV12; reg 80 drivers/staging/media/sunxi/cedrus/cedrus_hw.c cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg); reg 82 drivers/staging/media/sunxi/cedrus/cedrus_hw.c reg = chroma_size / 2; reg 83 drivers/staging/media/sunxi/cedrus/cedrus_hw.c cedrus_write(dev, VE_PRIMARY_CHROMA_BUF_LEN, reg); reg 85 drivers/staging/media/sunxi/cedrus/cedrus_hw.c reg = VE_PRIMARY_FB_LINE_STRIDE_LUMA(ALIGN(width, 16)) | reg 87 drivers/staging/media/sunxi/cedrus/cedrus_hw.c cedrus_write(dev, VE_PRIMARY_FB_LINE_STRIDE, reg); reg 92 drivers/staging/media/sunxi/cedrus/cedrus_hw.c reg = VE_PRIMARY_OUT_FMT_TILED_32_NV12; reg 93 drivers/staging/media/sunxi/cedrus/cedrus_hw.c cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg); reg 95 drivers/staging/media/sunxi/cedrus/cedrus_hw.c reg = VE_SECONDARY_OUT_FMT_TILED_32_NV12; reg 96 drivers/staging/media/sunxi/cedrus/cedrus_hw.c cedrus_write(dev, VE_CHROMA_BUF_LEN, reg); reg 43 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c u32 reg; reg 45 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg = cedrus_read(dev, VE_DEC_MPEG_STATUS); reg 46 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg &= VE_DEC_MPEG_STATUS_CHECK_MASK; reg 48 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c if (!reg) reg 51 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c if (reg & VE_DEC_MPEG_STATUS_CHECK_ERROR || reg 52 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c !(reg & VE_DEC_MPEG_STATUS_SUCCESS)) reg 68 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c u32 reg = cedrus_read(dev, VE_DEC_MPEG_CTRL); reg 70 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg &= ~VE_DEC_MPEG_CTRL_IRQ_MASK; reg 72 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c cedrus_write(dev, VE_DEC_MPEG_CTRL, reg); reg 90 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c u32 reg; reg 109 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg = VE_DEC_MPEG_IQMINPUT_WEIGHT(i, matrix[i]); reg 110 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_IQMINPUT_FLAG_INTRA; reg 112 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c cedrus_write(dev, VE_DEC_MPEG_IQMINPUT, reg); reg 123 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg = VE_DEC_MPEG_IQMINPUT_WEIGHT(i, matrix[i]); reg 124 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_IQMINPUT_FLAG_NON_INTRA; reg 126 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c cedrus_write(dev, VE_DEC_MPEG_IQMINPUT, reg); reg 131 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg = VE_DEC_MPEG_MP12HDR_SLICE_TYPE(picture->picture_coding_type); reg 132 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_MP12HDR_F_CODE(0, 0, picture->f_code[0][0]); reg 133 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_MP12HDR_F_CODE(0, 1, picture->f_code[0][1]); reg 134 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_MP12HDR_F_CODE(1, 0, picture->f_code[1][0]); reg 135 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_MP12HDR_F_CODE(1, 1, picture->f_code[1][1]); reg 136 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_MP12HDR_INTRA_DC_PRECISION(picture->intra_dc_precision); reg 137 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_MP12HDR_INTRA_PICTURE_STRUCTURE(picture->picture_structure); reg 138 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(picture->top_field_first); reg 139 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(picture->frame_pred_frame_dct); reg 140 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(picture->concealment_motion_vectors); reg 141 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(picture->q_scale_type); reg 142 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_MP12HDR_INTRA_VLC_FORMAT(picture->intra_vlc_format); reg 143 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_MP12HDR_ALTERNATE_SCAN(picture->alternate_scan); reg 144 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_MP12HDR_FULL_PEL_FORWARD_VECTOR(0); reg 145 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_MP12HDR_FULL_PEL_BACKWARD_VECTOR(0); reg 147 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c cedrus_write(dev, VE_DEC_MPEG_MP12HDR, reg); reg 151 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg = VE_DEC_MPEG_PICCODEDSIZE_WIDTH(sequence->horizontal_size); reg 152 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_PICCODEDSIZE_HEIGHT(sequence->vertical_size); reg 154 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c cedrus_write(dev, VE_DEC_MPEG_PICCODEDSIZE, reg); reg 156 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg = VE_DEC_MPEG_PICBOUNDSIZE_WIDTH(ctx->src_fmt.width); reg 157 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_PICBOUNDSIZE_HEIGHT(ctx->src_fmt.height); reg 159 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c cedrus_write(dev, VE_DEC_MPEG_PICBOUNDSIZE, reg); reg 192 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg = slice_params->bit_size - slice_params->data_bit_offset; reg 193 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c cedrus_write(dev, VE_DEC_MPEG_VLD_LEN, reg); reg 199 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg = VE_DEC_MPEG_VLD_ADDR_BASE(src_buf_addr); reg 200 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_VLD_ADDR_VALID_PIC_DATA; reg 201 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_VLD_ADDR_LAST_PIC_DATA; reg 202 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg |= VE_DEC_MPEG_VLD_ADDR_FIRST_PIC_DATA; reg 204 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c cedrus_write(dev, VE_DEC_MPEG_VLD_ADDR, reg); reg 206 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg = src_buf_addr + DIV_ROUND_UP(slice_params->bit_size, 8); reg 207 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c cedrus_write(dev, VE_DEC_MPEG_VLD_END_ADDR, reg); reg 210 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg = VE_DEC_MPEG_MBADDR_Y(0) | VE_DEC_MPEG_MBADDR_X(0); reg 211 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c cedrus_write(dev, VE_DEC_MPEG_MBADDR, reg); reg 221 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg = VE_DEC_MPEG_CTRL_IRQ_MASK | VE_DEC_MPEG_CTRL_MC_NO_WRITEBACK | reg 224 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c cedrus_write(dev, VE_DEC_MPEG_CTRL, reg); reg 230 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c u32 reg; reg 233 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c reg = VE_DEC_MPEG_TRIGGER_HW_MPEG_VLD | VE_DEC_MPEG_TRIGGER_MPEG2 | reg 236 drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c cedrus_write(dev, VE_DEC_MPEG_TRIGGER, reg); reg 133 drivers/staging/media/tegra-vde/vde.c static void tegra_vde_mbe_set_0xa_reg(struct tegra_vde *vde, int reg, u32 val) reg 135 drivers/staging/media/tegra-vde/vde.c tegra_vde_writel(vde, 0xA0000000 | (reg << 24) | (val & 0xFFFF), reg 137 drivers/staging/media/tegra-vde/vde.c tegra_vde_writel(vde, 0xA0000000 | ((reg + 1) << 24) | (val >> 16), reg 138 drivers/staging/most/usb/usb.c static inline int drci_rd_reg(struct usb_device *dev, u16 reg, u16 *buf) reg 150 drivers/staging/most/usb/usb.c reg, dma_buf, sizeof(*dma_buf), 5 * HZ); reg 165 drivers/staging/most/usb/usb.c static inline int drci_wr_reg(struct usb_device *dev, u16 reg, u16 data) reg 172 drivers/staging/most/usb/usb.c reg, reg 878 drivers/staging/most/usb/usb.c u16 reg; reg 906 drivers/staging/most/usb/usb.c *reg_addr = regs[i].reg; reg 183 drivers/staging/mt7621-dma/mtk-hsdma.c static inline u32 mtk_hsdma_read(struct mtk_hsdam_engine *hsdma, u32 reg) reg 185 drivers/staging/mt7621-dma/mtk-hsdma.c return readl(hsdma->base + reg); reg 189 drivers/staging/mt7621-dma/mtk-hsdma.c unsigned int reg, u32 val) reg 191 drivers/staging/mt7621-dma/mtk-hsdma.c writel(val, hsdma->base + reg); reg 583 drivers/staging/mt7621-dma/mtk-hsdma.c u32 reg; reg 608 drivers/staging/mt7621-dma/mtk-hsdma.c reg = mtk_hsdma_read(hsdma, HSDMA_REG_INFO); reg 610 drivers/staging/mt7621-dma/mtk-hsdma.c (reg >> HSDMA_INFO_RX_SHIFT) & HSDMA_INFO_RX_MASK, reg 611 drivers/staging/mt7621-dma/mtk-hsdma.c (reg >> HSDMA_INFO_TX_SHIFT) & HSDMA_INFO_TX_MASK); reg 109 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c static inline u32 phy_read(struct mt7621_pci_phy *phy, u32 reg) reg 113 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c regmap_read(phy->regmap, reg, &val); reg 118 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c static inline void phy_write(struct mt7621_pci_phy *phy, u32 val, u32 reg) reg 120 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c regmap_write(phy->regmap, reg, val); reg 128 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c u32 reg; reg 130 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c reg = phy_read(phy, offset); reg 131 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c reg &= ~(RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC); reg 132 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c reg |= (RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC); reg 133 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c phy_write(phy, reg, offset); reg 140 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c u32 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); reg 144 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c reg = (reg >> 6) & 0x7; reg 165 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */ reg 172 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c if (reg >= 6) { reg 227 drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */ reg 147 drivers/staging/mt7621-pci/pci-mt7621.c static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg) reg 149 drivers/staging/mt7621-pci/pci-mt7621.c return readl(pcie->base + reg); reg 152 drivers/staging/mt7621-pci/pci-mt7621.c static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg) reg 154 drivers/staging/mt7621-pci/pci-mt7621.c writel(val, pcie->base + reg); reg 157 drivers/staging/mt7621-pci/pci-mt7621.c static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg) reg 159 drivers/staging/mt7621-pci/pci-mt7621.c return readl(port->base + reg); reg 163 drivers/staging/mt7621-pci/pci-mt7621.c u32 val, u32 reg) reg 165 drivers/staging/mt7621-pci/pci-mt7621.c writel(val, port->base + reg); reg 193 drivers/staging/mt7621-pci/pci-mt7621.c static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) reg 195 drivers/staging/mt7621-pci/pci-mt7621.c u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg); reg 202 drivers/staging/mt7621-pci/pci-mt7621.c u32 reg, u32 val) reg 204 drivers/staging/mt7621-pci/pci-mt7621.c u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg); reg 122 drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c u32 reg = SYSC_REG_GPIO_MODE; reg 139 drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c reg = SYSC_REG_GPIO_MODE2; reg 141 drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c mode = rt_sysc_r32(reg); reg 156 drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c rt_sysc_w32(mode, reg); reg 35 drivers/staging/netlogic/xlr_net.c static inline void xlr_nae_wreg(u32 __iomem *base, unsigned int reg, u32 val) reg 37 drivers/staging/netlogic/xlr_net.c __raw_writel(val, base + reg); reg 40 drivers/staging/netlogic/xlr_net.c static inline u32 xlr_nae_rdreg(u32 __iomem *base, unsigned int reg) reg 42 drivers/staging/netlogic/xlr_net.c return __raw_readl(base + reg); reg 1564 drivers/staging/octeon-usb/octeon-hcd.c u64 reg; reg 1574 drivers/staging/octeon-usb/octeon-hcd.c reg = CVMX_USBNX_DMA0_OUTB_CHN0(usb->index); reg 1576 drivers/staging/octeon-usb/octeon-hcd.c reg = CVMX_USBNX_DMA0_INB_CHN0(usb->index); reg 1577 drivers/staging/octeon-usb/octeon-hcd.c cvmx_write64_uint64(reg + channel * 8, dma_address); reg 54 drivers/staging/octeon-usb/octeon-hcd.h #define CVMX_USBCXREG1(reg, bid) \ reg 55 drivers/staging/octeon-usb/octeon-hcd.h (CVMX_ADD_IO_SEG(CVMX_USBCXBASE | reg) + \ reg 57 drivers/staging/octeon-usb/octeon-hcd.h #define CVMX_USBCXREG2(reg, bid, off) \ reg 58 drivers/staging/octeon-usb/octeon-hcd.h (CVMX_ADD_IO_SEG(CVMX_USBCXBASE | reg) + \ reg 89 drivers/staging/octeon-usb/octeon-hcd.h #define CVMX_USBNXREG1(reg, bid) \ reg 90 drivers/staging/octeon-usb/octeon-hcd.h (CVMX_ADD_IO_SEG(0x0001180068000000ull | reg) + CVMX_USBNXBID1(bid)) reg 91 drivers/staging/octeon-usb/octeon-hcd.h #define CVMX_USBNXREG2(reg, bid) \ reg 92 drivers/staging/octeon-usb/octeon-hcd.h (CVMX_ADD_IO_SEG(0x00016F0000000000ull | reg) + CVMX_USBNXBID2(bid)) reg 1181 drivers/staging/octeon/octeon-stubs.h static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, reg 1187 drivers/staging/octeon/octeon-stubs.h static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value) reg 1190 drivers/staging/octeon/octeon-stubs.h static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value) reg 1367 drivers/staging/octeon/octeon-stubs.h cvmx_fau_reg_32_t reg, reg 46 drivers/staging/olpc_dcon/olpc_dcon.c static s32 dcon_write(struct dcon_priv *dcon, u8 reg, u16 val) reg 48 drivers/staging/olpc_dcon/olpc_dcon.c return i2c_smbus_write_word_data(dcon->client, reg, val); reg 51 drivers/staging/olpc_dcon/olpc_dcon.c static s32 dcon_read(struct dcon_priv *dcon, u8 reg) reg 53 drivers/staging/olpc_dcon/olpc_dcon.c return i2c_smbus_read_word_data(dcon->client, reg); reg 75 drivers/staging/pi433/rf69.c static int rf69_set_bit(struct spi_device *spi, u8 reg, u8 mask) reg 79 drivers/staging/pi433/rf69.c tmp = rf69_read_reg(spi, reg); reg 81 drivers/staging/pi433/rf69.c return rf69_write_reg(spi, reg, tmp); reg 84 drivers/staging/pi433/rf69.c static int rf69_clear_bit(struct spi_device *spi, u8 reg, u8 mask) reg 88 drivers/staging/pi433/rf69.c tmp = rf69_read_reg(spi, reg); reg 90 drivers/staging/pi433/rf69.c return rf69_write_reg(spi, reg, tmp); reg 93 drivers/staging/pi433/rf69.c static inline int rf69_read_mod_write(struct spi_device *spi, u8 reg, reg 98 drivers/staging/pi433/rf69.c tmp = rf69_read_reg(spi, reg); reg 100 drivers/staging/pi433/rf69.c return rf69_write_reg(spi, reg, tmp); reg 462 drivers/staging/pi433/rf69.c static int rf69_set_bandwidth_intern(struct spi_device *spi, u8 reg, reg 481 drivers/staging/pi433/rf69.c bandwidth = rf69_read_reg(spi, reg); reg 503 drivers/staging/pi433/rf69.c return rf69_write_reg(spi, reg, bandwidth); reg 2158 drivers/staging/qlge/qlge.h static inline u32 ql_read32(const struct ql_adapter *qdev, int reg) reg 2160 drivers/staging/qlge/qlge.h return readl(qdev->reg_base + reg); reg 2166 drivers/staging/qlge/qlge.h static inline void ql_write32(const struct ql_adapter *qdev, int reg, u32 val) reg 2168 drivers/staging/qlge/qlge.h writel(val, qdev->reg_base + reg); reg 2214 drivers/staging/qlge/qlge.h u32 reg; reg 2215 drivers/staging/qlge/qlge.h reg = le32_to_cpu(*addr); reg 2217 drivers/staging/qlge/qlge.h return reg; reg 2226 drivers/staging/qlge/qlge.h int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data); reg 2236 drivers/staging/qlge/qlge.h int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 ebit); reg 2240 drivers/staging/qlge/qlge.h int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data); reg 2245 drivers/staging/qlge/qlge.h int ql_read_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 *data); reg 2246 drivers/staging/qlge/qlge.h int ql_write_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 data); reg 10 drivers/staging/qlge/qlge_dbg.c u32 reg) reg 19 drivers/staging/qlge/qlge_dbg.c | reg; reg 29 drivers/staging/qlge/qlge_dbg.c u32 reg, u32 reg_val) reg 37 drivers/staging/qlge/qlge_dbg.c | reg; reg 43 drivers/staging/qlge/qlge_dbg.c static int ql_wait_other_func_reg_rdy(struct ql_adapter *qdev, u32 reg, reg 50 drivers/staging/qlge/qlge_dbg.c temp = ql_read_other_func_reg(qdev, reg); reg 63 drivers/staging/qlge/qlge_dbg.c static int ql_read_other_func_serdes_reg(struct ql_adapter *qdev, u32 reg, reg 75 drivers/staging/qlge/qlge_dbg.c ql_write_other_func_reg(qdev, XG_SERDES_ADDR/4, reg | PROC_ADDR_R); reg 90 drivers/staging/qlge/qlge_dbg.c static int ql_read_serdes_reg(struct ql_adapter *qdev, u32 reg, u32 *data) reg 100 drivers/staging/qlge/qlge_dbg.c ql_write32(qdev, XG_SERDES_ADDR, reg | PROC_ADDR_R); reg 320 drivers/staging/qlge/qlge_dbg.c static int ql_read_other_func_xgmac_reg(struct ql_adapter *qdev, u32 reg, reg 332 drivers/staging/qlge/qlge_dbg.c ql_write_other_func_reg(qdev, XGMAC_ADDR / 4, reg | XGMAC_ADDR_R); reg 684 drivers/staging/qlge/qlge_dbg.c u32 func_num, reg, reg_val; reg 688 drivers/staging/qlge/qlge_dbg.c reg = MPI_NIC_REG_BLOCK reg 691 drivers/staging/qlge/qlge_dbg.c status = ql_read_mpi_reg(qdev, reg, ®_val); reg 1368 drivers/staging/qlge/qlge_dbg.c #define DUMP_XGMAC(qdev, reg) \ reg 1371 drivers/staging/qlge/qlge_dbg.c ql_read_xgmac_reg(qdev, reg, &data); \ reg 1372 drivers/staging/qlge/qlge_dbg.c pr_err("%s: %s = 0x%.08x\n", qdev->ndev->name, #reg, data); \ reg 1462 drivers/staging/qlge/qlge_dbg.c #define DUMP_REG(qdev, reg) \ reg 1463 drivers/staging/qlge/qlge_dbg.c pr_err("%-32s= 0x%x\n", #reg, ql_read32(qdev, reg)) reg 167 drivers/staging/qlge/qlge_main.c int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit) reg 173 drivers/staging/qlge/qlge_main.c temp = ql_read32(qdev, reg); reg 179 drivers/staging/qlge/qlge_main.c reg, temp); reg 187 drivers/staging/qlge/qlge_main.c "Timed out waiting for reg %x to come ready.\n", reg); reg 864 drivers/staging/qlge/qlge_main.c static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data) reg 875 drivers/staging/qlge/qlge_main.c ql_write32(qdev, XGMAC_ADDR, reg); reg 883 drivers/staging/qlge/qlge_main.c int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data) reg 892 drivers/staging/qlge/qlge_main.c ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R); reg 905 drivers/staging/qlge/qlge_main.c int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data) reg 911 drivers/staging/qlge/qlge_main.c status = ql_read_xgmac_reg(qdev, reg, &lo); reg 915 drivers/staging/qlge/qlge_main.c status = ql_read_xgmac_reg(qdev, reg + 4, &hi); reg 53 drivers/staging/qlge/qlge_mpi.c int ql_read_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 *data) reg 61 drivers/staging/qlge/qlge_mpi.c ql_write32(qdev, PROC_ADDR, reg | PROC_ADDR_R); reg 72 drivers/staging/qlge/qlge_mpi.c int ql_write_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 data) reg 82 drivers/staging/qlge/qlge_mpi.c ql_write32(qdev, PROC_ADDR, reg); reg 156 drivers/staging/ralink-gdma/ralink-gdma.c unsigned int reg) reg 158 drivers/staging/ralink-gdma/ralink-gdma.c return readl(dma_dev->base + reg); reg 162 drivers/staging/ralink-gdma/ralink-gdma.c unsigned int reg, uint32_t val) reg 164 drivers/staging/ralink-gdma/ralink-gdma.c writel(val, dma_dev->base + reg); reg 3948 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c struct p2p_reg_class *reg = NULL; reg 3961 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c if (reg == NULL) { reg 3962 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c reg = &channel_list->reg_class[cla]; reg 3964 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c reg->reg_class = o->op_class; reg 3965 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c reg->channels = 0; reg 3967 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c reg->channel[reg->channels] = ch; reg 3968 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c reg->channels++; reg 579 drivers/staging/rtl8188eu/hal/bb_cfg.c struct bb_reg_def *reg[4]; reg 581 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A] = &adapter->HalData->PHYRegDef[RF_PATH_A]; reg 582 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B] = &adapter->HalData->PHYRegDef[RF_PATH_B]; reg 584 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A]->rfintfs = rFPGA0_XAB_RFInterfaceSW; reg 585 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B]->rfintfs = rFPGA0_XAB_RFInterfaceSW; reg 587 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A]->rfintfi = rFPGA0_XAB_RFInterfaceRB; reg 588 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B]->rfintfi = rFPGA0_XAB_RFInterfaceRB; reg 590 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A]->rfintfo = rFPGA0_XA_RFInterfaceOE; reg 591 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B]->rfintfo = rFPGA0_XB_RFInterfaceOE; reg 593 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A]->rfintfe = rFPGA0_XA_RFInterfaceOE; reg 594 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B]->rfintfe = rFPGA0_XB_RFInterfaceOE; reg 596 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A]->rf3wireOffset = rFPGA0_XA_LSSIParameter; reg 597 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B]->rf3wireOffset = rFPGA0_XB_LSSIParameter; reg 599 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A]->rfLSSI_Select = rFPGA0_XAB_RFParameter; reg 600 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B]->rfLSSI_Select = rFPGA0_XAB_RFParameter; reg 602 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A]->rfTxGainStage = rFPGA0_TxGainStage; reg 603 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B]->rfTxGainStage = rFPGA0_TxGainStage; reg 605 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A]->rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; reg 606 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B]->rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; reg 608 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A]->rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; reg 609 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B]->rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; reg 611 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A]->rfSwitchControl = rFPGA0_XAB_SwitchControl; reg 612 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B]->rfSwitchControl = rFPGA0_XAB_SwitchControl; reg 614 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A]->rfAGCControl1 = rOFDM0_XAAGCCore1; reg 615 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B]->rfAGCControl1 = rOFDM0_XBAGCCore1; reg 617 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A]->rfAGCControl2 = rOFDM0_XAAGCCore2; reg 618 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B]->rfAGCControl2 = rOFDM0_XBAGCCore2; reg 620 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A]->rfRxIQImbalance = rOFDM0_XARxIQImbalance; reg 621 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B]->rfRxIQImbalance = rOFDM0_XBRxIQImbalance; reg 623 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A]->rfRxAFE = rOFDM0_XARxAFE; reg 624 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B]->rfRxAFE = rOFDM0_XBRxAFE; reg 626 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A]->rfTxIQImbalance = rOFDM0_XATxIQImbalance; reg 627 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B]->rfTxIQImbalance = rOFDM0_XBTxIQImbalance; reg 629 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A]->rfTxAFE = rOFDM0_XATxAFE; reg 630 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B]->rfTxAFE = rOFDM0_XBTxAFE; reg 632 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A]->rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; reg 633 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B]->rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; reg 635 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_A]->rfLSSIReadBackPi = TransceiverA_HSPI_Readback; reg 636 drivers/staging/rtl8188eu/hal/bb_cfg.c reg[RF_PATH_B]->rfLSSIReadBackPi = TransceiverB_HSPI_Readback; reg 699 drivers/staging/rtl8188eu/hal/phy.c u32 oldval_0, x, tx0_a, reg; reg 731 drivers/staging/rtl8188eu/hal/phy.c reg = result[final_candidate][2]; reg 732 drivers/staging/rtl8188eu/hal/phy.c phy_set_bb_reg(adapt, rOFDM0_XARxIQImbalance, 0x3FF, reg); reg 734 drivers/staging/rtl8188eu/hal/phy.c reg = result[final_candidate][3] & 0x3F; reg 735 drivers/staging/rtl8188eu/hal/phy.c phy_set_bb_reg(adapt, rOFDM0_XARxIQImbalance, 0xFC00, reg); reg 737 drivers/staging/rtl8188eu/hal/phy.c reg = (result[final_candidate][3] >> 6) & 0xF; reg 738 drivers/staging/rtl8188eu/hal/phy.c phy_set_bb_reg(adapt, rOFDM0_RxIQExtAnta, 0xF0000000, reg); reg 745 drivers/staging/rtl8188eu/hal/phy.c u32 oldval_1, x, tx1_a, reg; reg 778 drivers/staging/rtl8188eu/hal/phy.c reg = result[final_candidate][6]; reg 779 drivers/staging/rtl8188eu/hal/phy.c phy_set_bb_reg(adapt, rOFDM0_XBRxIQImbalance, 0x3FF, reg); reg 781 drivers/staging/rtl8188eu/hal/phy.c reg = result[final_candidate][7] & 0x3F; reg 782 drivers/staging/rtl8188eu/hal/phy.c phy_set_bb_reg(adapt, rOFDM0_XBRxIQImbalance, 0xFC00, reg); reg 784 drivers/staging/rtl8188eu/hal/phy.c reg = (result[final_candidate][7] >> 6) & 0xF; reg 785 drivers/staging/rtl8188eu/hal/phy.c phy_set_bb_reg(adapt, rOFDM0_AGCRSSITable, 0x0000F000, reg); reg 988 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c u32 reg; reg 990 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c reg = rtl92e_readl(dev, RCR); reg 995 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c priv->ReceiveConfig = reg |= RCR_CBSSID; reg 997 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c priv->ReceiveConfig = reg &= ~RCR_CBSSID; reg 999 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c rtl92e_writel(dev, RCR, reg); reg 15 drivers/staging/rtl8192e/rtl8192e/rtl_eeprom.c u8 reg = rtl92e_readb(dev, EPROM_CMD); reg 18 drivers/staging/rtl8192e/rtl8192e/rtl_eeprom.c reg |= 1 << no; reg 20 drivers/staging/rtl8192e/rtl8192e/rtl_eeprom.c reg &= ~(1 << no); reg 22 drivers/staging/rtl8192e/rtl8192e/rtl_eeprom.c rtl92e_writeb(dev, EPROM_CMD, reg); reg 28 drivers/staging/rtl8192e/rtl8192e/rtl_eeprom.c u8 reg = rtl92e_readb(dev, EPROM_CMD); reg 30 drivers/staging/rtl8192e/rtl8192e/rtl_eeprom.c return (reg >> no) & 0x1; reg 1733 drivers/staging/rtl8192u/r8192U_core.c u32 reg = 0; reg 1735 drivers/staging/rtl8192u/r8192U_core.c read_nic_dword(dev, RCR, ®); reg 1737 drivers/staging/rtl8192u/r8192U_core.c priv->ReceiveConfig = reg |= RCR_CBSSID; reg 1739 drivers/staging/rtl8192u/r8192U_core.c priv->ReceiveConfig = reg &= ~RCR_CBSSID; reg 1740 drivers/staging/rtl8192u/r8192U_core.c write_nic_dword(dev, RCR, reg); reg 71 drivers/staging/rtl8192u/r819xU_phy.c u32 reg, bitshift; reg 74 drivers/staging/rtl8192u/r819xU_phy.c read_nic_dword(dev, reg_addr, ®); reg 76 drivers/staging/rtl8192u/r819xU_phy.c reg &= ~bitmask; reg 77 drivers/staging/rtl8192u/r819xU_phy.c reg |= data << bitshift; reg 78 drivers/staging/rtl8192u/r819xU_phy.c write_nic_dword(dev, reg_addr, reg); reg 95 drivers/staging/rtl8192u/r819xU_phy.c u32 reg, bitshift; reg 97 drivers/staging/rtl8192u/r819xU_phy.c read_nic_dword(dev, reg_addr, ®); reg 100 drivers/staging/rtl8192u/r819xU_phy.c return (reg & bitmask) >> bitshift; reg 282 drivers/staging/rtl8192u/r819xU_phy.c u32 reg, bitshift; reg 290 drivers/staging/rtl8192u/r819xU_phy.c reg = phy_FwRFSerialRead(dev, e_rfpath, reg_addr); reg 292 drivers/staging/rtl8192u/r819xU_phy.c reg &= ~bitmask; reg 293 drivers/staging/rtl8192u/r819xU_phy.c reg |= data << bitshift; reg 295 drivers/staging/rtl8192u/r819xU_phy.c phy_FwRFSerialWrite(dev, e_rfpath, reg_addr, reg); reg 305 drivers/staging/rtl8192u/r819xU_phy.c reg = rtl8192_phy_RFSerialRead(dev, e_rfpath, reg_addr); reg 307 drivers/staging/rtl8192u/r819xU_phy.c reg &= ~bitmask; reg 308 drivers/staging/rtl8192u/r819xU_phy.c reg |= data << bitshift; reg 310 drivers/staging/rtl8192u/r819xU_phy.c rtl8192_phy_RFSerialWrite(dev, e_rfpath, reg_addr, reg); reg 330 drivers/staging/rtl8192u/r819xU_phy.c u32 reg, bitshift; reg 337 drivers/staging/rtl8192u/r819xU_phy.c reg = phy_FwRFSerialRead(dev, e_rfpath, reg_addr); reg 340 drivers/staging/rtl8192u/r819xU_phy.c reg = rtl8192_phy_RFSerialRead(dev, e_rfpath, reg_addr); reg 343 drivers/staging/rtl8192u/r819xU_phy.c reg = (reg & bitmask) >> bitshift; reg 344 drivers/staging/rtl8192u/r819xU_phy.c return reg; reg 361 drivers/staging/rtl8192u/r819xU_phy.c u32 reg = 0; reg 407 drivers/staging/rtl8192u/r819xU_phy.c read_nic_dword(dev, RF_DATA, ®); reg 409 drivers/staging/rtl8192u/r819xU_phy.c return reg; reg 692 drivers/staging/rtl8192u/r819xU_phy.c u32 i, CheckTimes = 4, reg = 0; reg 715 drivers/staging/rtl8192u/r819xU_phy.c read_nic_dword(dev, WriteAddr[CheckBlock], ®); reg 727 drivers/staging/rtl8192u/r819xU_phy.c reg = rtl8192_phy_QueryRFReg(dev, e_rfpath, reg 740 drivers/staging/rtl8192u/r819xU_phy.c if (reg != WriteData[i]) { reg 743 drivers/staging/rtl8192u/r819xU_phy.c reg, WriteData[i]); reg 135 drivers/staging/rtl8712/rtl871x_eeprom.c void r8712_eeprom_write16(struct _adapter *padapter, u16 reg, u16 data) reg 168 drivers/staging/rtl8712/rtl871x_eeprom.c shift_out_bits(padapter, reg, padapter->eeprom_address_size); reg 174 drivers/staging/rtl8712/rtl871x_eeprom.c shift_out_bits(padapter, reg, 4); reg 183 drivers/staging/rtl8712/rtl871x_eeprom.c u16 r8712_eeprom_read16(struct _adapter *padapter, u16 reg) /*ReadEEprom*/ reg 210 drivers/staging/rtl8712/rtl871x_eeprom.c shift_out_bits(padapter, reg, padapter->eeprom_address_size); reg 84 drivers/staging/rtl8712/rtl871x_eeprom.h void r8712_eeprom_write16(struct _adapter *padapter, u16 reg, u16 data); reg 85 drivers/staging/rtl8712/rtl871x_eeprom.h u16 r8712_eeprom_read16(struct _adapter *padapter, u16 reg); reg 150 drivers/staging/rtl8723bs/core/rtw_eeprom.c u16 eeprom_read16(_adapter *padapter, u16 reg) /*ReadEEprom*/ reg 177 drivers/staging/rtl8723bs/core/rtw_eeprom.c shift_out_bits(padapter, reg, padapter->EepromAddressSize); reg 194 drivers/staging/rtl8723bs/core/rtw_eeprom.c u16 reg, stmp, i = 0, idx = 0; reg 196 drivers/staging/rtl8723bs/core/rtw_eeprom.c reg = (u16)(addr_off >> 1); reg 201 drivers/staging/rtl8723bs/core/rtw_eeprom.c stmp = eeprom_read16(padapter, reg); reg 203 drivers/staging/rtl8723bs/core/rtw_eeprom.c reg++; sz--; reg 210 drivers/staging/rtl8723bs/core/rtw_eeprom.c stmp = eeprom_read16(padapter, reg+i); reg 215 drivers/staging/rtl8723bs/core/rtw_eeprom.c reg = reg+i; reg 217 drivers/staging/rtl8723bs/core/rtw_eeprom.c stmp = eeprom_read16(padapter, reg); reg 367 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c struct p2p_reg_class *reg = NULL; reg 380 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c if (!reg) { reg 381 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c reg = &channel_list->reg_class[cla]; reg 383 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c reg->reg_class = o->op_class; reg 384 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c reg->channels = 0; reg 386 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c reg->channel[reg->channels] = ch; reg 387 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c reg->channels++; reg 1090 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c u32 Oldval_0, X, TX0_A, reg; reg 1145 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c reg = result[final_candidate][2]; reg 1148 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, 0x3FF, reg); reg 1149 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c reg = result[final_candidate][3] & 0x3F; reg 1150 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, 0xFC00, reg); reg 1154 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c reg = (result[final_candidate][3] >> 6) & 0xF; reg 1155 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg); reg 1170 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c u32 Oldval_1, X, TX1_A, reg; reg 1229 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c reg = result[final_candidate][6]; reg 1230 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg); reg 1231 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c reg = result[final_candidate][7] & 0x3F; reg 1232 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg); reg 1236 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c reg = (result[final_candidate][7] >> 6) & 0xF; reg 1239 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = (reg << 28)|(PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord)&0x0fffffff); reg 3180 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c u16 frame_type, bool reg) reg 3192 drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c frame_type, reg); reg 106 drivers/staging/rtl8723bs/os_dep/wifi_regd.c struct rtw_regulatory *reg) reg 115 drivers/staging/rtl8723bs/os_dep/wifi_regd.c *reg) reg 120 drivers/staging/rtl8723bs/os_dep/wifi_regd.c static void _rtw_regd_init_wiphy(struct rtw_regulatory *reg, reg 135 drivers/staging/rtl8723bs/os_dep/wifi_regd.c regd = _rtw_regdomain_select(reg); reg 155 drivers/staging/rtl8723bs/os_dep/wifi_regd.c struct rtw_regulatory *reg = NULL; reg 159 drivers/staging/rtl8723bs/os_dep/wifi_regd.c _rtw_reg_notifier_apply(wiphy, request, reg); reg 42 drivers/staging/rts5208/rtsx.h #define rtsx_writel(chip, reg, value) \ reg 43 drivers/staging/rts5208/rtsx.h iowrite32(value, (chip)->rtsx->remap_addr + reg) reg 44 drivers/staging/rts5208/rtsx.h #define rtsx_readl(chip, reg) \ reg 45 drivers/staging/rts5208/rtsx.h ioread32((chip)->rtsx->remap_addr + reg) reg 46 drivers/staging/rts5208/rtsx.h #define rtsx_writew(chip, reg, value) \ reg 47 drivers/staging/rts5208/rtsx.h iowrite16(value, (chip)->rtsx->remap_addr + reg) reg 48 drivers/staging/rts5208/rtsx.h #define rtsx_readw(chip, reg) \ reg 49 drivers/staging/rts5208/rtsx.h ioread16((chip)->rtsx->remap_addr + reg) reg 50 drivers/staging/rts5208/rtsx.h #define rtsx_writeb(chip, reg, value) \ reg 51 drivers/staging/rts5208/rtsx.h iowrite8(value, (chip)->rtsx->remap_addr + reg) reg 52 drivers/staging/rts5208/rtsx.h #define rtsx_readb(chip, reg) \ reg 53 drivers/staging/rts5208/rtsx.h ioread8((chip)->rtsx->remap_addr + reg) reg 101 drivers/staging/rts5208/rtsx_card.c u8 buf[12], reg; reg 106 drivers/staging/rts5208/rtsx_card.c rtsx_read_register(chip, 0xFF25, ®); reg 107 drivers/staging/rts5208/rtsx_card.c if ((memcmp(buf, chip->sdio_raw_data, 12) != 0) || (reg & 0x03)) { reg 37 drivers/staging/rts5208/rtsx_chip.c u32 reg = rtsx_readl(chip, RTSX_BIER); reg 42 drivers/staging/rts5208/rtsx_chip.c reg |= XD_INT_EN; reg 44 drivers/staging/rts5208/rtsx_chip.c reg |= SD_INT_EN; reg 46 drivers/staging/rts5208/rtsx_chip.c reg |= MS_INT_EN; reg 49 drivers/staging/rts5208/rtsx_chip.c reg &= ~((u32)SD_INT_EN); reg 51 drivers/staging/rts5208/rtsx_chip.c rtsx_writel(chip, RTSX_BIER, reg); reg 56 drivers/staging/rts5208/rtsx_chip.c u32 reg = 0; reg 61 drivers/staging/rts5208/rtsx_chip.c reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN; reg 69 drivers/staging/rts5208/rtsx_chip.c reg |= XD_INT_EN; reg 71 drivers/staging/rts5208/rtsx_chip.c reg |= SD_INT_EN; reg 73 drivers/staging/rts5208/rtsx_chip.c reg |= MS_INT_EN; reg 76 drivers/staging/rts5208/rtsx_chip.c reg &= ~((u32)SD_INT_EN); reg 80 drivers/staging/rts5208/rtsx_chip.c reg |= DELINK_INT_EN; reg 82 drivers/staging/rts5208/rtsx_chip.c reg |= OC_INT_EN; reg 85 drivers/staging/rts5208/rtsx_chip.c reg |= DATA_DONE_INT_EN; reg 88 drivers/staging/rts5208/rtsx_chip.c rtsx_writel(chip, RTSX_BIER, reg); reg 90 drivers/staging/rts5208/rtsx_chip.c dev_dbg(rtsx_dev(chip), "RTSX_BIER: 0x%08x\n", reg); reg 306 drivers/staging/rts5208/rtsx_chip.c u16 reg; reg 308 drivers/staging/rts5208/rtsx_chip.c ret = rtsx_read_phy_register(chip, 0x00, ®); reg 312 drivers/staging/rts5208/rtsx_chip.c reg &= 0xFE7F; reg 313 drivers/staging/rts5208/rtsx_chip.c reg |= 0x80; reg 314 drivers/staging/rts5208/rtsx_chip.c ret = rtsx_write_phy_register(chip, 0x00, reg); reg 318 drivers/staging/rts5208/rtsx_chip.c ret = rtsx_read_phy_register(chip, 0x1C, ®); reg 322 drivers/staging/rts5208/rtsx_chip.c reg &= 0xFFF7; reg 323 drivers/staging/rts5208/rtsx_chip.c ret = rtsx_write_phy_register(chip, 0x1C, reg); reg 638 drivers/staging/rts5208/rtsx_chip.c u16 reg = 0; reg 650 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_read_phy_register(chip, 0x1C, ®); reg 655 drivers/staging/rts5208/rtsx_chip.c reg); reg 656 drivers/staging/rts5208/rtsx_chip.c chip->ic_version = (reg >> 4) & 0x07; reg 657 drivers/staging/rts5208/rtsx_chip.c chip->phy_debug_mode = reg & PHY_DEBUG_MODE ? 1 : 0; reg 1275 drivers/staging/rts5208/rtsx_chip.c u32 reg; reg 1277 drivers/staging/rts5208/rtsx_chip.c reg = rtsx_readl(chip, addr); reg 1278 drivers/staging/rts5208/rtsx_chip.c dev_dbg(rtsx_dev(chip), "BAR (0x%02x): 0x%08x\n", addr, reg); reg 1689 drivers/staging/rts5208/rtsx_chip.c int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit) reg 1694 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_read_phy_register(chip, reg, &value); reg 1700 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_write_phy_register(chip, reg, value); reg 1708 drivers/staging/rts5208/rtsx_chip.c int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit) reg 1713 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_read_phy_register(chip, reg, &value); reg 1719 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_write_phy_register(chip, reg, value); reg 973 drivers/staging/rts5208/rtsx_chip.h int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit); reg 974 drivers/staging/rts5208/rtsx_chip.h int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit); reg 1672 drivers/staging/rts5208/rtsx_scsi.c u16 reg; reg 1690 drivers/staging/rts5208/rtsx_scsi.c retval = rtsx_read_phy_register(chip, 0x1C, ®); reg 1694 drivers/staging/rts5208/rtsx_scsi.c reg |= 0x0001; reg 1695 drivers/staging/rts5208/rtsx_scsi.c retval = rtsx_write_phy_register(chip, 0x1C, reg); reg 1706 drivers/staging/rts5208/rtsx_scsi.c retval = rtsx_read_phy_register(chip, 0x1C, ®); reg 1710 drivers/staging/rts5208/rtsx_scsi.c reg &= 0xFFFE; reg 1711 drivers/staging/rts5208/rtsx_scsi.c retval = rtsx_write_phy_register(chip, 0x1C, reg); reg 204 drivers/staging/rts5208/xd.c u8 reg; reg 230 drivers/staging/rts5208/xd.c retval = rtsx_read_register(chip, XD_PAGE_STATUS, ®); reg 233 drivers/staging/rts5208/xd.c if (reg != XD_GPG) { reg 238 drivers/staging/rts5208/xd.c retval = rtsx_read_register(chip, XD_CTL, ®); reg 241 drivers/staging/rts5208/xd.c if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) { reg 245 drivers/staging/rts5208/xd.c if (reg & XD_ECC1_ERROR) { reg 267 drivers/staging/rts5208/xd.c } else if (!(reg & XD_ECC2_ERROR) || !(reg & XD_ECC2_UNCORRECTABLE)) { reg 273 drivers/staging/rts5208/xd.c if (reg & XD_ECC2_ERROR) { reg 998 drivers/staging/rts5208/xd.c u8 reg = 0; reg 1033 drivers/staging/rts5208/xd.c rtsx_read_register(chip, XD_DAT, ®); reg 1034 drivers/staging/rts5208/xd.c if (reg & PROGRAM_ERROR) reg 1050 drivers/staging/rts5208/xd.c u8 reg = 0; reg 1085 drivers/staging/rts5208/xd.c rtsx_read_register(chip, XD_DAT, ®); reg 1086 drivers/staging/rts5208/xd.c if (reg & PROGRAM_ERROR) { reg 1103 drivers/staging/rts5208/xd.c u8 i, reg = 0; reg 1147 drivers/staging/rts5208/xd.c reg = 0; reg 1148 drivers/staging/rts5208/xd.c rtsx_read_register(chip, XD_CTL, ®); reg 1149 drivers/staging/rts5208/xd.c if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) { reg 1158 drivers/staging/rts5208/xd.c if (((reg & XD_ECC1_ERROR) && reg 1159 drivers/staging/rts5208/xd.c (reg & XD_ECC1_UNCORRECTABLE)) || reg 1160 drivers/staging/rts5208/xd.c ((reg & XD_ECC2_ERROR) && reg 1161 drivers/staging/rts5208/xd.c (reg & XD_ECC2_UNCORRECTABLE))) { reg 1195 drivers/staging/rts5208/xd.c reg = 0; reg 1196 drivers/staging/rts5208/xd.c rtsx_read_register(chip, XD_DAT, ®); reg 1197 drivers/staging/rts5208/xd.c if (reg & PROGRAM_ERROR) { reg 1243 drivers/staging/rts5208/xd.c u8 reg = 0, *ptr; reg 1265 drivers/staging/rts5208/xd.c rtsx_read_register(chip, XD_DAT, ®); reg 1266 drivers/staging/rts5208/xd.c if (reg & PROGRAM_ERROR) { reg 88 drivers/staging/sm750fb/ddk750_chip.c unsigned int reg, divisor; reg 109 drivers/staging/sm750fb/ddk750_chip.c reg = peek32(CURRENT_GATE) & ~CURRENT_GATE_M2XCLK_MASK; reg 113 drivers/staging/sm750fb/ddk750_chip.c reg |= CURRENT_GATE_M2XCLK_DIV_1; reg 116 drivers/staging/sm750fb/ddk750_chip.c reg |= CURRENT_GATE_M2XCLK_DIV_2; reg 119 drivers/staging/sm750fb/ddk750_chip.c reg |= CURRENT_GATE_M2XCLK_DIV_3; reg 122 drivers/staging/sm750fb/ddk750_chip.c reg |= CURRENT_GATE_M2XCLK_DIV_4; reg 126 drivers/staging/sm750fb/ddk750_chip.c sm750_set_current_gate(reg); reg 140 drivers/staging/sm750fb/ddk750_chip.c unsigned int reg, divisor; reg 161 drivers/staging/sm750fb/ddk750_chip.c reg = peek32(CURRENT_GATE) & ~CURRENT_GATE_MCLK_MASK; reg 165 drivers/staging/sm750fb/ddk750_chip.c reg |= CURRENT_GATE_MCLK_DIV_3; reg 168 drivers/staging/sm750fb/ddk750_chip.c reg |= CURRENT_GATE_MCLK_DIV_4; reg 171 drivers/staging/sm750fb/ddk750_chip.c reg |= CURRENT_GATE_MCLK_DIV_6; reg 174 drivers/staging/sm750fb/ddk750_chip.c reg |= CURRENT_GATE_MCLK_DIV_8; reg 178 drivers/staging/sm750fb/ddk750_chip.c sm750_set_current_gate(reg); reg 184 drivers/staging/sm750fb/ddk750_chip.c unsigned int reg; reg 192 drivers/staging/sm750fb/ddk750_chip.c reg = peek32(MODE0_GATE); reg 193 drivers/staging/sm750fb/ddk750_chip.c reg |= MODE0_GATE_GPIO; reg 194 drivers/staging/sm750fb/ddk750_chip.c poke32(MODE0_GATE, reg); reg 197 drivers/staging/sm750fb/ddk750_chip.c reg = peek32(MISC_CTRL) & MISC_CTRL_LOCALMEM_SIZE_MASK; reg 198 drivers/staging/sm750fb/ddk750_chip.c switch (reg) { reg 216 drivers/staging/sm750fb/ddk750_chip.c unsigned int reg; reg 223 drivers/staging/sm750fb/ddk750_chip.c reg = peek32(CURRENT_GATE); reg 224 drivers/staging/sm750fb/ddk750_chip.c reg |= (CURRENT_GATE_DISPLAY | CURRENT_GATE_LOCALMEM); reg 225 drivers/staging/sm750fb/ddk750_chip.c sm750_set_current_gate(reg); reg 229 drivers/staging/sm750fb/ddk750_chip.c reg = peek32(VGA_CONFIGURATION); reg 230 drivers/staging/sm750fb/ddk750_chip.c reg |= (VGA_CONFIGURATION_PLL | VGA_CONFIGURATION_MODE); reg 231 drivers/staging/sm750fb/ddk750_chip.c poke32(VGA_CONFIGURATION, reg); reg 256 drivers/staging/sm750fb/ddk750_chip.c reg = peek32(MISC_CTRL); reg 257 drivers/staging/sm750fb/ddk750_chip.c reg &= ~MISC_CTRL_LOCALMEM_RESET; reg 258 drivers/staging/sm750fb/ddk750_chip.c poke32(MISC_CTRL, reg); reg 260 drivers/staging/sm750fb/ddk750_chip.c reg |= MISC_CTRL_LOCALMEM_RESET; reg 261 drivers/staging/sm750fb/ddk750_chip.c poke32(MISC_CTRL, reg); reg 268 drivers/staging/sm750fb/ddk750_chip.c reg = peek32(VIDEO_DISPLAY_CTRL); reg 269 drivers/staging/sm750fb/ddk750_chip.c reg &= ~DISPLAY_CTRL_PLANE; reg 270 drivers/staging/sm750fb/ddk750_chip.c poke32(VIDEO_DISPLAY_CTRL, reg); reg 273 drivers/staging/sm750fb/ddk750_chip.c reg = peek32(VIDEO_ALPHA_DISPLAY_CTRL); reg 274 drivers/staging/sm750fb/ddk750_chip.c reg &= ~DISPLAY_CTRL_PLANE; reg 275 drivers/staging/sm750fb/ddk750_chip.c poke32(VIDEO_ALPHA_DISPLAY_CTRL, reg); reg 278 drivers/staging/sm750fb/ddk750_chip.c reg = peek32(ALPHA_DISPLAY_CTRL); reg 279 drivers/staging/sm750fb/ddk750_chip.c reg &= ~DISPLAY_CTRL_PLANE; reg 280 drivers/staging/sm750fb/ddk750_chip.c poke32(ALPHA_DISPLAY_CTRL, reg); reg 283 drivers/staging/sm750fb/ddk750_chip.c reg = peek32(DMA_ABORT_INTERRUPT); reg 284 drivers/staging/sm750fb/ddk750_chip.c reg |= DMA_ABORT_INTERRUPT_ABORT_1; reg 285 drivers/staging/sm750fb/ddk750_chip.c poke32(DMA_ABORT_INTERRUPT, reg); reg 11 drivers/staging/sm750fb/ddk750_display.c unsigned long reg, val, reserved; reg 15 drivers/staging/sm750fb/ddk750_display.c reg = PANEL_DISPLAY_CTRL; reg 18 drivers/staging/sm750fb/ddk750_display.c reg = CRT_DISPLAY_CTRL; reg 22 drivers/staging/sm750fb/ddk750_display.c val = peek32(reg); reg 31 drivers/staging/sm750fb/ddk750_display.c poke32(reg, val); reg 42 drivers/staging/sm750fb/ddk750_display.c poke32(reg, val); reg 43 drivers/staging/sm750fb/ddk750_display.c } while ((peek32(reg) & ~reserved) != (val & ~reserved)); reg 56 drivers/staging/sm750fb/ddk750_display.c poke32(reg, val); reg 59 drivers/staging/sm750fb/ddk750_display.c poke32(reg, val); reg 90 drivers/staging/sm750fb/ddk750_display.c unsigned int reg; reg 93 drivers/staging/sm750fb/ddk750_display.c reg = peek32(PANEL_DISPLAY_CTRL); reg 94 drivers/staging/sm750fb/ddk750_display.c reg |= (disp ? PANEL_DISPLAY_CTRL_FPEN : 0); reg 95 drivers/staging/sm750fb/ddk750_display.c poke32(PANEL_DISPLAY_CTRL, reg); reg 98 drivers/staging/sm750fb/ddk750_display.c reg = peek32(PANEL_DISPLAY_CTRL); reg 99 drivers/staging/sm750fb/ddk750_display.c reg |= (disp ? PANEL_DISPLAY_CTRL_DATA : 0); reg 100 drivers/staging/sm750fb/ddk750_display.c poke32(PANEL_DISPLAY_CTRL, reg); reg 103 drivers/staging/sm750fb/ddk750_display.c reg = peek32(PANEL_DISPLAY_CTRL); reg 104 drivers/staging/sm750fb/ddk750_display.c reg |= (disp ? PANEL_DISPLAY_CTRL_VBIASEN : 0); reg 105 drivers/staging/sm750fb/ddk750_display.c poke32(PANEL_DISPLAY_CTRL, reg); reg 108 drivers/staging/sm750fb/ddk750_display.c reg = peek32(PANEL_DISPLAY_CTRL); reg 109 drivers/staging/sm750fb/ddk750_display.c reg |= (disp ? PANEL_DISPLAY_CTRL_FPEN : 0); reg 110 drivers/staging/sm750fb/ddk750_display.c poke32(PANEL_DISPLAY_CTRL, reg); reg 116 drivers/staging/sm750fb/ddk750_display.c unsigned int reg; reg 120 drivers/staging/sm750fb/ddk750_display.c reg = peek32(PANEL_DISPLAY_CTRL); reg 121 drivers/staging/sm750fb/ddk750_display.c reg &= ~PANEL_DISPLAY_CTRL_SELECT_MASK; reg 122 drivers/staging/sm750fb/ddk750_display.c reg |= (((output & PNL_2_MASK) >> PNL_2_OFFSET) << reg 124 drivers/staging/sm750fb/ddk750_display.c poke32(PANEL_DISPLAY_CTRL, reg); reg 129 drivers/staging/sm750fb/ddk750_display.c reg = peek32(CRT_DISPLAY_CTRL); reg 130 drivers/staging/sm750fb/ddk750_display.c reg &= ~CRT_DISPLAY_CTRL_SELECT_MASK; reg 131 drivers/staging/sm750fb/ddk750_display.c reg |= (((output & CRT_2_MASK) >> CRT_2_OFFSET) << reg 134 drivers/staging/sm750fb/ddk750_display.c reg &= ~CRT_DISPLAY_CTRL_BLANK; reg 135 drivers/staging/sm750fb/ddk750_display.c poke32(CRT_DISPLAY_CTRL, reg); reg 210 drivers/staging/sm750fb/ddk750_hwi2c.c unsigned char sm750_hw_i2c_read_reg(unsigned char addr, unsigned char reg) reg 214 drivers/staging/sm750fb/ddk750_hwi2c.c if (hw_i2c_write_data(addr, 1, ®) == 1) reg 234 drivers/staging/sm750fb/ddk750_hwi2c.c unsigned char reg, reg 239 drivers/staging/sm750fb/ddk750_hwi2c.c value[0] = reg; reg 9 drivers/staging/sm750fb/ddk750_hwi2c.h unsigned char sm750_hw_i2c_read_reg(unsigned char addr, unsigned char reg); reg 10 drivers/staging/sm750fb/ddk750_hwi2c.h int sm750_hw_i2c_write_reg(unsigned char addr, unsigned char reg, reg 82 drivers/staging/sm750fb/ddk750_mode.c unsigned int tmp, reg; reg 129 drivers/staging/sm750fb/ddk750_mode.c reg = peek32(CRT_DISPLAY_CTRL) & reg 134 drivers/staging/sm750fb/ddk750_mode.c poke32(CRT_DISPLAY_CTRL, tmp | reg); reg 142 drivers/staging/sm750fb/ddk750_mode.c reg = ((pModeParam->horizontal_total - 1) << reg 145 drivers/staging/sm750fb/ddk750_mode.c reg |= ((pModeParam->horizontal_display_end - 1) & reg 147 drivers/staging/sm750fb/ddk750_mode.c poke32(PANEL_HORIZONTAL_TOTAL, reg); reg 181 drivers/staging/sm750fb/ddk750_mode.c reg = (peek32(PANEL_DISPLAY_CTRL) & ~reserved) & reg 194 drivers/staging/sm750fb/ddk750_mode.c poke32(PANEL_DISPLAY_CTRL, tmp | reg); reg 197 drivers/staging/sm750fb/ddk750_mode.c (tmp | reg)) { reg 201 drivers/staging/sm750fb/ddk750_mode.c poke32(PANEL_DISPLAY_CTRL, tmp | reg); reg 445 drivers/staging/sm750fb/ddk750_swi2c.c unsigned char sm750_sw_i2c_read_reg(unsigned char addr, unsigned char reg) reg 456 drivers/staging/sm750fb/ddk750_swi2c.c sw_i2c_write_byte(reg); reg 483 drivers/staging/sm750fb/ddk750_swi2c.c unsigned char reg, reg 495 drivers/staging/sm750fb/ddk750_swi2c.c (sw_i2c_write_byte(reg) != 0) || reg 42 drivers/staging/sm750fb/ddk750_swi2c.h unsigned char sm750_sw_i2c_read_reg(unsigned char addr, unsigned char reg); reg 58 drivers/staging/sm750fb/ddk750_swi2c.h unsigned char reg, reg 39 drivers/staging/sm750fb/sm750_accel.c u32 reg, clr; reg 44 drivers/staging/sm750fb/sm750_accel.c reg = 0x3; reg 54 drivers/staging/sm750fb/sm750_accel.c (read_dpr(accel, DE_STRETCH_FORMAT) & ~clr) | reg); reg 78 drivers/staging/sm750fb/sm750_accel.c u32 reg; reg 81 drivers/staging/sm750fb/sm750_accel.c reg = read_dpr(accel, DE_STRETCH_FORMAT); reg 82 drivers/staging/sm750fb/sm750_accel.c reg &= ~DE_STRETCH_FORMAT_PIXEL_FORMAT_MASK; reg 83 drivers/staging/sm750fb/sm750_accel.c reg |= ((fmt << DE_STRETCH_FORMAT_PIXEL_FORMAT_SHIFT) & reg 85 drivers/staging/sm750fb/sm750_accel.c write_dpr(accel, DE_STRETCH_FORMAT, reg); reg 50 drivers/staging/sm750fb/sm750_cursor.c u32 reg; reg 52 drivers/staging/sm750fb/sm750_cursor.c reg = (cursor->offset & HWC_ADDRESS_ADDRESS_MASK) | HWC_ADDRESS_ENABLE; reg 53 drivers/staging/sm750fb/sm750_cursor.c poke32(HWC_ADDRESS, reg); reg 69 drivers/staging/sm750fb/sm750_cursor.c u32 reg; reg 71 drivers/staging/sm750fb/sm750_cursor.c reg = ((y << HWC_LOCATION_Y_SHIFT) & HWC_LOCATION_Y_MASK) | reg 73 drivers/staging/sm750fb/sm750_cursor.c poke32(HWC_LOCATION, reg); reg 78 drivers/staging/sm750fb/sm750_cursor.c u32 reg = (fg << HWC_COLOR_12_2_RGB565_SHIFT) & reg 81 drivers/staging/sm750fb/sm750_cursor.c poke32(HWC_COLOR_12, reg | (bg & HWC_COLOR_12_1_RGB565_MASK)); reg 213 drivers/staging/sm750fb/sm750_hw.c u32 reg; reg 215 drivers/staging/sm750fb/sm750_hw.c reg = peek32(DISPLAY_CONTROL_750LE); reg 216 drivers/staging/sm750fb/sm750_hw.c reg |= 0xf; reg 217 drivers/staging/sm750fb/sm750_hw.c poke32(DISPLAY_CONTROL_750LE, reg); reg 255 drivers/staging/sm750fb/sm750_hw.c u32 reg; reg 319 drivers/staging/sm750fb/sm750_hw.c reg = var->xres * (var->bits_per_pixel >> 3); reg 324 drivers/staging/sm750fb/sm750_hw.c reg = ALIGN(reg, crtc->line_pad); reg 325 drivers/staging/sm750fb/sm750_hw.c reg = (reg << PANEL_FB_WIDTH_WIDTH_SHIFT) & reg 327 drivers/staging/sm750fb/sm750_hw.c reg |= (fix->line_length & PANEL_FB_WIDTH_OFFSET_MASK); reg 328 drivers/staging/sm750fb/sm750_hw.c poke32(PANEL_FB_WIDTH, reg); reg 330 drivers/staging/sm750fb/sm750_hw.c reg = ((var->xres - 1) << PANEL_WINDOW_WIDTH_WIDTH_SHIFT) & reg 332 drivers/staging/sm750fb/sm750_hw.c reg |= (var->xoffset & PANEL_WINDOW_WIDTH_X_MASK); reg 333 drivers/staging/sm750fb/sm750_hw.c poke32(PANEL_WINDOW_WIDTH, reg); reg 335 drivers/staging/sm750fb/sm750_hw.c reg = (var->yres_virtual - 1) << reg 337 drivers/staging/sm750fb/sm750_hw.c reg &= PANEL_WINDOW_HEIGHT_HEIGHT_MASK; reg 338 drivers/staging/sm750fb/sm750_hw.c reg |= (var->yoffset & PANEL_WINDOW_HEIGHT_Y_MASK); reg 339 drivers/staging/sm750fb/sm750_hw.c poke32(PANEL_WINDOW_HEIGHT, reg); reg 343 drivers/staging/sm750fb/sm750_hw.c reg = ((var->yres - 1) << PANEL_PLANE_BR_BOTTOM_SHIFT) & reg 345 drivers/staging/sm750fb/sm750_hw.c reg |= ((var->xres - 1) & PANEL_PLANE_BR_RIGHT_MASK); reg 346 drivers/staging/sm750fb/sm750_hw.c poke32(PANEL_PLANE_BR, reg); reg 349 drivers/staging/sm750fb/sm750_hw.c reg = peek32(PANEL_DISPLAY_CTRL); reg 350 drivers/staging/sm750fb/sm750_hw.c poke32(PANEL_DISPLAY_CTRL, reg | (var->bits_per_pixel >> 4)); reg 354 drivers/staging/sm750fb/sm750_hw.c reg = var->xres * (var->bits_per_pixel >> 3); reg 359 drivers/staging/sm750fb/sm750_hw.c reg = ALIGN(reg, crtc->line_pad) << CRT_FB_WIDTH_WIDTH_SHIFT; reg 360 drivers/staging/sm750fb/sm750_hw.c reg &= CRT_FB_WIDTH_WIDTH_MASK; reg 361 drivers/staging/sm750fb/sm750_hw.c reg |= (fix->line_length & CRT_FB_WIDTH_OFFSET_MASK); reg 362 drivers/staging/sm750fb/sm750_hw.c poke32(CRT_FB_WIDTH, reg); reg 365 drivers/staging/sm750fb/sm750_hw.c reg = peek32(CRT_DISPLAY_CTRL); reg 366 drivers/staging/sm750fb/sm750_hw.c reg |= ((var->bits_per_pixel >> 4) & reg 368 drivers/staging/sm750fb/sm750_hw.c poke32(CRT_DISPLAY_CTRL, reg); reg 481 drivers/staging/sm750fb/sm750_hw.c u32 reg; reg 486 drivers/staging/sm750fb/sm750_hw.c reg = peek32(DE_STATE1); reg 487 drivers/staging/sm750fb/sm750_hw.c reg |= DE_STATE1_DE_ABORT; reg 488 drivers/staging/sm750fb/sm750_hw.c poke32(DE_STATE1, reg); reg 490 drivers/staging/sm750fb/sm750_hw.c reg = peek32(DE_STATE1); reg 491 drivers/staging/sm750fb/sm750_hw.c reg &= ~DE_STATE1_DE_ABORT; reg 492 drivers/staging/sm750fb/sm750_hw.c poke32(DE_STATE1, reg); reg 496 drivers/staging/sm750fb/sm750_hw.c reg = peek32(SYSTEM_CTRL); reg 497 drivers/staging/sm750fb/sm750_hw.c reg |= SYSTEM_CTRL_DE_ABORT; reg 498 drivers/staging/sm750fb/sm750_hw.c poke32(SYSTEM_CTRL, reg); reg 500 drivers/staging/sm750fb/sm750_hw.c reg = peek32(SYSTEM_CTRL); reg 501 drivers/staging/sm750fb/sm750_hw.c reg &= ~SYSTEM_CTRL_DE_ABORT; reg 502 drivers/staging/sm750fb/sm750_hw.c poke32(SYSTEM_CTRL, reg); reg 255 drivers/staging/uwb/i1480/dfu/mac.c u32 reg = 0x800000c0; reg 259 drivers/staging/uwb/i1480/dfu/mac.c reg = 0x8000d0d4; reg 260 drivers/staging/uwb/i1480/dfu/mac.c result = i1480->read(i1480, reg, sizeof(u32)); reg 264 drivers/staging/uwb/i1480/dfu/mac.c result = i1480->write(i1480, reg, buffer, sizeof(u32)); reg 279 drivers/staging/uwb/i1480/dfu/mac.c u32 reg = 0x800000c0; reg 283 drivers/staging/uwb/i1480/dfu/mac.c reg = 0x8000d0d4; reg 284 drivers/staging/uwb/i1480/dfu/mac.c result = i1480->read(i1480, reg, sizeof(u32)); reg 288 drivers/staging/uwb/i1480/dfu/mac.c result = i1480->write(i1480, reg, buffer, sizeof(u32)); reg 98 drivers/staging/uwb/include/whci.h extern int whci_wait_for(struct device *dev, u32 __iomem *reg, reg 62 drivers/staging/uwb/whci.c int whci_wait_for(struct device *dev, u32 __iomem *reg, u32 mask, u32 result, reg 68 drivers/staging/uwb/whci.c val = le_readl(reg); reg 73 drivers/staging/vt6656/usbpipe.c int vnt_control_out_u8(struct vnt_private *priv, u8 reg, u8 reg_off, u8 data) reg 76 drivers/staging/vt6656/usbpipe.c reg_off, reg, sizeof(u8), &data); reg 80 drivers/staging/vt6656/usbpipe.c u16 block, u8 reg, u16 length, u8 *data) reg 88 drivers/staging/vt6656/usbpipe.c i, reg, len, data + i); reg 136 drivers/staging/vt6656/usbpipe.c int vnt_control_in_u8(struct vnt_private *priv, u8 reg, u8 reg_off, u8 *data) reg 139 drivers/staging/vt6656/usbpipe.c reg_off, reg, sizeof(u8), data); reg 28 drivers/staging/vt6656/usbpipe.h int vnt_control_out_u8(struct vnt_private *priv, u8 reg, u8 ref_off, u8 data); reg 29 drivers/staging/vt6656/usbpipe.h int vnt_control_in_u8(struct vnt_private *priv, u8 reg, u8 reg_off, u8 *data); reg 32 drivers/staging/vt6656/usbpipe.h u16 block, u8 reg, u16 len, u8 *data); reg 35 drivers/staging/wilc1000/wilc_hif.c bool reg; reg 1774 drivers/staging/wilc1000/wilc_hif.c void wilc_frame_register(struct wilc_vif *vif, u16 frame_type, bool reg) reg 1786 drivers/staging/wilc1000/wilc_hif.c reg_frame.reg = reg; reg 221 drivers/staging/wilc1000/wilc_hif.h void wilc_frame_register(struct wilc_vif *vif, u16 frame_type, bool reg); reg 645 drivers/staging/wilc1000/wilc_netdev.c vif->frame_reg[0].reg); reg 649 drivers/staging/wilc1000/wilc_netdev.c vif->frame_reg[1].reg); reg 834 drivers/staging/wilc1000/wilc_netdev.c if ((type == vif->frame_reg[0].type && vif->frame_reg[0].reg) || reg 835 drivers/staging/wilc1000/wilc_netdev.c (type == vif->frame_reg[1].type && vif->frame_reg[1].reg)) { reg 879 drivers/staging/wilc1000/wilc_sdio.c u32 reg; reg 885 drivers/staging/wilc1000/wilc_sdio.c reg = flags; reg 887 drivers/staging/wilc1000/wilc_sdio.c reg = 0; reg 891 drivers/staging/wilc1000/wilc_sdio.c reg |= BIT(5); reg 894 drivers/staging/wilc1000/wilc_sdio.c reg |= BIT(6); reg 897 drivers/staging/wilc1000/wilc_sdio.c reg |= BIT(7); reg 898 drivers/staging/wilc1000/wilc_sdio.c if (reg) { reg 905 drivers/staging/wilc1000/wilc_sdio.c cmd.data = reg; reg 1000 drivers/staging/wilc1000/wilc_sdio.c u32 reg; reg 1017 drivers/staging/wilc1000/wilc_sdio.c if (!wilc_sdio_read_reg(wilc, WILC_MISC, ®)) { reg 1022 drivers/staging/wilc1000/wilc_sdio.c reg &= ~BIT(8); reg 1023 drivers/staging/wilc1000/wilc_sdio.c if (!wilc_sdio_write_reg(wilc, WILC_MISC, reg)) { reg 1029 drivers/staging/wilc1000/wilc_sdio.c u32 reg; reg 1035 drivers/staging/wilc1000/wilc_sdio.c ret = wilc_sdio_read_reg(wilc, WILC_PIN_MUX_0, ®); reg 1041 drivers/staging/wilc1000/wilc_sdio.c reg |= BIT(8); reg 1042 drivers/staging/wilc1000/wilc_sdio.c ret = wilc_sdio_write_reg(wilc, WILC_PIN_MUX_0, reg); reg 1052 drivers/staging/wilc1000/wilc_sdio.c ret = wilc_sdio_read_reg(wilc, WILC_INTR_ENABLE, ®); reg 1060 drivers/staging/wilc1000/wilc_sdio.c reg |= BIT((27 + i)); reg 1061 drivers/staging/wilc1000/wilc_sdio.c ret = wilc_sdio_write_reg(wilc, WILC_INTR_ENABLE, reg); reg 1068 drivers/staging/wilc1000/wilc_sdio.c ret = wilc_sdio_read_reg(wilc, WILC_INTR2_ENABLE, ®); reg 1077 drivers/staging/wilc1000/wilc_sdio.c reg |= BIT(i); reg 1079 drivers/staging/wilc1000/wilc_sdio.c ret = wilc_sdio_read_reg(wilc, WILC_INTR2_ENABLE, ®); reg 830 drivers/staging/wilc1000/wilc_spi.c u32 reg; reg 851 drivers/staging/wilc1000/wilc_spi.c if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®)) { reg 859 drivers/staging/wilc1000/wilc_spi.c if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®)) { reg 869 drivers/staging/wilc1000/wilc_spi.c reg &= ~0xc; /* disable crc checking */ reg 870 drivers/staging/wilc1000/wilc_spi.c reg &= ~0x70; reg 871 drivers/staging/wilc1000/wilc_spi.c reg |= (0x5 << 4); reg 872 drivers/staging/wilc1000/wilc_spi.c if (!spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg)) { reg 1052 drivers/staging/wilc1000/wilc_spi.c u32 reg; reg 1065 drivers/staging/wilc1000/wilc_spi.c ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®); reg 1071 drivers/staging/wilc1000/wilc_spi.c reg |= BIT(8); reg 1072 drivers/staging/wilc1000/wilc_spi.c ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg); reg 1082 drivers/staging/wilc1000/wilc_spi.c ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®); reg 1090 drivers/staging/wilc1000/wilc_spi.c reg |= (BIT((27 + i))); reg 1092 drivers/staging/wilc1000/wilc_spi.c ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg); reg 1099 drivers/staging/wilc1000/wilc_spi.c ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®); reg 1107 drivers/staging/wilc1000/wilc_spi.c reg |= BIT(i); reg 1109 drivers/staging/wilc1000/wilc_spi.c ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®); reg 1334 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c u16 frame_type, bool reg) reg 1345 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c vif->frame_reg[0].reg = reg; reg 1350 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c vif->frame_reg[1].reg = reg; reg 1359 drivers/staging/wilc1000/wilc_wfi_cfgoperations.c wilc_frame_register(vif, frame_type, reg); reg 25 drivers/staging/wilc1000/wilc_wfi_cfgoperations.h u16 frame_type, bool reg); reg 164 drivers/staging/wilc1000/wilc_wfi_netdevice.h bool reg; reg 394 drivers/staging/wilc1000/wilc_wlan.c u32 reg = 0; reg 396 drivers/staging/wilc1000/wilc_wlan.c wilc->hif_func->hif_read_reg(wilc, 0xf0, ®); reg 398 drivers/staging/wilc1000/wilc_wlan.c wilc->hif_func->hif_write_reg(wilc, 0xf0, reg & ~BIT(0)); reg 405 drivers/staging/wilc1000/wilc_wlan.c u32 reg, clk_status_reg; reg 409 drivers/staging/wilc1000/wilc_wlan.c wilc->hif_func->hif_read_reg(wilc, 1, ®); reg 410 drivers/staging/wilc1000/wilc_wlan.c wilc->hif_func->hif_write_reg(wilc, 1, reg | BIT(1)); reg 411 drivers/staging/wilc1000/wilc_wlan.c wilc->hif_func->hif_write_reg(wilc, 1, reg & ~BIT(1)); reg 421 drivers/staging/wilc1000/wilc_wlan.c wilc->hif_func->hif_read_reg(wilc, 0xf0, ®); reg 424 drivers/staging/wilc1000/wilc_wlan.c reg | BIT(0)); reg 436 drivers/staging/wilc1000/wilc_wlan.c reg & (~BIT(0))); reg 478 drivers/staging/wilc1000/wilc_wlan.c u32 reg; reg 542 drivers/staging/wilc1000/wilc_wlan.c ret = func->hif_read_reg(wilc, WILC_HOST_TX_CTRL, ®); reg 546 drivers/staging/wilc1000/wilc_wlan.c if ((reg & 0x1) == 0) reg 574 drivers/staging/wilc1000/wilc_wlan.c ret = func->hif_read_reg(wilc, WILC_HOST_VMM_CTL, ®); reg 577 drivers/staging/wilc1000/wilc_wlan.c if ((reg >> 2) & 0x1) { reg 578 drivers/staging/wilc1000/wilc_wlan.c entries = ((reg >> 3) & 0x3f); reg 591 drivers/staging/wilc1000/wilc_wlan.c ret = func->hif_read_reg(wilc, WILC_HOST_TX_CTRL, ®); reg 594 drivers/staging/wilc1000/wilc_wlan.c reg &= ~BIT(0); reg 595 drivers/staging/wilc1000/wilc_wlan.c ret = func->hif_write_reg(wilc, WILC_HOST_TX_CTRL, reg); reg 872 drivers/staging/wilc1000/wilc_wlan.c u32 reg = 0; reg 877 drivers/staging/wilc1000/wilc_wlan.c reg = 0; reg 878 drivers/staging/wilc1000/wilc_wlan.c reg |= BIT(3); reg 880 drivers/staging/wilc1000/wilc_wlan.c reg = 1; reg 883 drivers/staging/wilc1000/wilc_wlan.c ret = wilc->hif_func->hif_write_reg(wilc, WILC_VMM_CORE_CFG, reg); reg 888 drivers/staging/wilc1000/wilc_wlan.c reg = 0; reg 890 drivers/staging/wilc1000/wilc_wlan.c reg |= WILC_HAVE_SDIO_IRQ_GPIO; reg 894 drivers/staging/wilc1000/wilc_wlan.c reg |= WILC_HAVE_USE_PMU; reg 898 drivers/staging/wilc1000/wilc_wlan.c reg |= WILC_HAVE_SLEEP_CLK_SRC_XO; reg 900 drivers/staging/wilc1000/wilc_wlan.c reg |= WILC_HAVE_SLEEP_CLK_SRC_RTC; reg 904 drivers/staging/wilc1000/wilc_wlan.c reg |= WILC_HAVE_EXT_PA_INV_TX_RX; reg 906 drivers/staging/wilc1000/wilc_wlan.c reg |= WILC_HAVE_USE_IRQ_AS_HOST_WAKE; reg 907 drivers/staging/wilc1000/wilc_wlan.c reg |= WILC_HAVE_LEGACY_RF_SETTINGS; reg 909 drivers/staging/wilc1000/wilc_wlan.c reg |= WILC_HAVE_XTAL_24; reg 912 drivers/staging/wilc1000/wilc_wlan.c reg |= WILC_HAVE_DISABLE_WILC_UART; reg 915 drivers/staging/wilc1000/wilc_wlan.c ret = wilc->hif_func->hif_write_reg(wilc, WILC_GP_REG_1, reg); reg 929 drivers/staging/wilc1000/wilc_wlan.c wilc->hif_func->hif_read_reg(wilc, WILC_GLB_RESET_0, ®); reg 930 drivers/staging/wilc1000/wilc_wlan.c if ((reg & BIT(10)) == BIT(10)) { reg 931 drivers/staging/wilc1000/wilc_wlan.c reg &= ~BIT(10); reg 932 drivers/staging/wilc1000/wilc_wlan.c wilc->hif_func->hif_write_reg(wilc, WILC_GLB_RESET_0, reg); reg 933 drivers/staging/wilc1000/wilc_wlan.c wilc->hif_func->hif_read_reg(wilc, WILC_GLB_RESET_0, ®); reg 936 drivers/staging/wilc1000/wilc_wlan.c reg |= BIT(10); reg 937 drivers/staging/wilc1000/wilc_wlan.c ret = wilc->hif_func->hif_write_reg(wilc, WILC_GLB_RESET_0, reg); reg 938 drivers/staging/wilc1000/wilc_wlan.c wilc->hif_func->hif_read_reg(wilc, WILC_GLB_RESET_0, ®); reg 946 drivers/staging/wilc1000/wilc_wlan.c u32 reg = 0; reg 951 drivers/staging/wilc1000/wilc_wlan.c ret = wilc->hif_func->hif_read_reg(wilc, WILC_GP_REG_0, ®); reg 959 drivers/staging/wilc1000/wilc_wlan.c (reg | WILC_ABORT_REQ_BIT)); reg 966 drivers/staging/wilc1000/wilc_wlan.c ret = wilc->hif_func->hif_read_reg(wilc, WILC_FW_HOST_COMM, ®); reg 972 drivers/staging/wilc1000/wilc_wlan.c reg = BIT(0); reg 974 drivers/staging/wilc1000/wilc_wlan.c ret = wilc->hif_func->hif_write_reg(wilc, WILC_FW_HOST_COMM, reg); reg 1161 drivers/staging/wilc1000/wilc_wlan.c u32 reg, ret = 0; reg 1170 drivers/staging/wilc1000/wilc_wlan.c ret = wilc->hif_func->hif_read_reg(wilc, 0x1118, ®); reg 1175 drivers/staging/wilc1000/wilc_wlan.c reg |= BIT(0); reg 1176 drivers/staging/wilc1000/wilc_wlan.c ret = wilc->hif_func->hif_write_reg(wilc, 0x1118, reg); reg 1049 drivers/staging/wlan-ng/prism2mgmt.c u16 reg; reg 1070 drivers/staging/wlan-ng/prism2mgmt.c reg = HFA384x_CNFAUTHENTICATION_SHAREDKEY; reg 1072 drivers/staging/wlan-ng/prism2mgmt.c reg = HFA384x_CNFAUTHENTICATION_OPENSYSTEM; reg 1074 drivers/staging/wlan-ng/prism2mgmt.c hfa384x_drvr_setconfig16(hw, HFA384x_RID_CNFAUTHENTICATION, reg); reg 68 drivers/target/target_core_tmr.c struct t10_pr_registration *reg; reg 72 drivers/target/target_core_tmr.c list_for_each_entry(reg, list, pr_reg_abort_list) { reg 73 drivers/target/target_core_tmr.c if (reg->pr_res_key == cmd->pr_res_key) reg 144 drivers/thermal/armada_thermal.c u32 reg; reg 146 drivers/thermal/armada_thermal.c regmap_read(priv->syscon, data->syscon_control1_off, ®); reg 147 drivers/thermal/armada_thermal.c reg |= PMU_TDC0_OTF_CAL_MASK; reg 150 drivers/thermal/armada_thermal.c reg &= ~PMU_TDC0_REF_CAL_CNT_MASK; reg 151 drivers/thermal/armada_thermal.c reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS); reg 154 drivers/thermal/armada_thermal.c reg |= PMU_TDC0_SW_RST_MASK; reg 156 drivers/thermal/armada_thermal.c regmap_write(priv->syscon, data->syscon_control1_off, reg); reg 159 drivers/thermal/armada_thermal.c regmap_read(priv->syscon, data->syscon_status_off, ®); reg 160 drivers/thermal/armada_thermal.c reg &= ~PMU_TM_DISABLE_MASK; reg 161 drivers/thermal/armada_thermal.c regmap_write(priv->syscon, data->syscon_status_off, reg); reg 168 drivers/thermal/armada_thermal.c u32 reg; reg 170 drivers/thermal/armada_thermal.c regmap_read(priv->syscon, data->syscon_control1_off, ®); reg 171 drivers/thermal/armada_thermal.c reg |= PMU_TDC0_OTF_CAL_MASK; reg 174 drivers/thermal/armada_thermal.c reg &= ~PMU_TDC0_REF_CAL_CNT_MASK; reg 175 drivers/thermal/armada_thermal.c reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS); reg 178 drivers/thermal/armada_thermal.c reg &= ~PMU_TDC0_START_CAL_MASK; reg 180 drivers/thermal/armada_thermal.c regmap_write(priv->syscon, data->syscon_control1_off, reg); reg 189 drivers/thermal/armada_thermal.c u32 reg; reg 191 drivers/thermal/armada_thermal.c regmap_read(priv->syscon, data->syscon_control1_off, ®); reg 192 drivers/thermal/armada_thermal.c reg &= ~(A375_UNIT_CONTROL_MASK << A375_UNIT_CONTROL_SHIFT); reg 193 drivers/thermal/armada_thermal.c reg &= ~A375_READOUT_INVERT; reg 194 drivers/thermal/armada_thermal.c reg &= ~A375_HW_RESETn; reg 195 drivers/thermal/armada_thermal.c regmap_write(priv->syscon, data->syscon_control1_off, reg); reg 199 drivers/thermal/armada_thermal.c reg |= A375_HW_RESETn; reg 200 drivers/thermal/armada_thermal.c regmap_write(priv->syscon, data->syscon_control1_off, reg); reg 207 drivers/thermal/armada_thermal.c u32 reg; reg 210 drivers/thermal/armada_thermal.c priv->data->syscon_status_off, reg, reg 211 drivers/thermal/armada_thermal.c reg & priv->data->is_valid_bit, reg 220 drivers/thermal/armada_thermal.c u32 reg; reg 223 drivers/thermal/armada_thermal.c regmap_read(priv->syscon, data->syscon_control1_off, ®); reg 224 drivers/thermal/armada_thermal.c reg |= CONTROL1_EXT_TSEN_HW_RESETn; reg 225 drivers/thermal/armada_thermal.c reg &= ~CONTROL1_EXT_TSEN_SW_RESET; reg 226 drivers/thermal/armada_thermal.c regmap_write(priv->syscon, data->syscon_control1_off, reg); reg 229 drivers/thermal/armada_thermal.c regmap_read(priv->syscon, data->syscon_control0_off, ®); reg 230 drivers/thermal/armada_thermal.c reg &= ~CONTROL0_TSEN_TC_TRIM_MASK; reg 231 drivers/thermal/armada_thermal.c reg |= CONTROL0_TSEN_TC_TRIM_VAL; reg 232 drivers/thermal/armada_thermal.c regmap_write(priv->syscon, data->syscon_control0_off, reg); reg 239 drivers/thermal/armada_thermal.c u32 reg; reg 241 drivers/thermal/armada_thermal.c regmap_read(priv->syscon, data->syscon_control0_off, ®); reg 242 drivers/thermal/armada_thermal.c reg &= ~CONTROL0_TSEN_RESET; reg 243 drivers/thermal/armada_thermal.c reg |= CONTROL0_TSEN_START | CONTROL0_TSEN_ENABLE; reg 246 drivers/thermal/armada_thermal.c reg |= CONTROL0_TSEN_OSR_MAX << CONTROL0_TSEN_OSR_SHIFT; reg 249 drivers/thermal/armada_thermal.c reg &= ~CONTROL0_TSEN_AVG_BYPASS; reg 251 drivers/thermal/armada_thermal.c regmap_write(priv->syscon, data->syscon_control0_off, reg); reg 258 drivers/thermal/armada_thermal.c u32 reg; reg 263 drivers/thermal/armada_thermal.c regmap_read(priv->syscon, data->syscon_control0_off, ®); reg 264 drivers/thermal/armada_thermal.c reg |= CONTROL0_TSEN_OSR_MAX << CONTROL0_TSEN_OSR_SHIFT; reg 265 drivers/thermal/armada_thermal.c regmap_write(priv->syscon, data->syscon_control0_off, reg); reg 268 drivers/thermal/armada_thermal.c regmap_read(priv->syscon, data->syscon_control1_off, ®); reg 269 drivers/thermal/armada_thermal.c reg &= ~CONTROL1_TSEN_AVG_MASK; reg 270 drivers/thermal/armada_thermal.c reg |= 1; reg 271 drivers/thermal/armada_thermal.c regmap_write(priv->syscon, data->syscon_control1_off, reg); reg 276 drivers/thermal/armada_thermal.c u32 reg; reg 281 drivers/thermal/armada_thermal.c regmap_read(priv->syscon, priv->data->syscon_status_off, ®); reg 283 drivers/thermal/armada_thermal.c return reg & priv->data->is_valid_bit; reg 289 drivers/thermal/armada_thermal.c u32 reg; reg 292 drivers/thermal/armada_thermal.c regmap_read(priv->syscon, data->dfx_irq_cause_off, ®); reg 295 drivers/thermal/armada_thermal.c regmap_read(priv->syscon, data->dfx_irq_mask_off, ®); reg 296 drivers/thermal/armada_thermal.c reg |= data->dfx_overheat_irq; reg 297 drivers/thermal/armada_thermal.c regmap_write(priv->syscon, data->dfx_irq_mask_off, reg); reg 300 drivers/thermal/armada_thermal.c regmap_read(priv->syscon, data->dfx_server_irq_mask_off, ®); reg 301 drivers/thermal/armada_thermal.c reg |= data->dfx_server_irq_en; reg 302 drivers/thermal/armada_thermal.c regmap_write(priv->syscon, data->dfx_server_irq_mask_off, reg); reg 305 drivers/thermal/armada_thermal.c regmap_read(priv->syscon, data->syscon_control1_off, ®); reg 306 drivers/thermal/armada_thermal.c reg |= CONTROL1_TSEN_INT_EN; reg 307 drivers/thermal/armada_thermal.c regmap_write(priv->syscon, data->syscon_control1_off, reg); reg 314 drivers/thermal/armada_thermal.c u32 reg; reg 316 drivers/thermal/armada_thermal.c regmap_read(priv->syscon, data->syscon_control1_off, ®); reg 317 drivers/thermal/armada_thermal.c reg &= ~CONTROL1_TSEN_INT_EN; reg 318 drivers/thermal/armada_thermal.c regmap_write(priv->syscon, data->syscon_control1_off, reg); reg 375 drivers/thermal/armada_thermal.c u32 reg, div; reg 378 drivers/thermal/armada_thermal.c regmap_read(priv->syscon, priv->data->syscon_status_off, ®); reg 379 drivers/thermal/armada_thermal.c reg = (reg >> priv->data->temp_shift) & priv->data->temp_mask; reg 382 drivers/thermal/armada_thermal.c sample = sign_extend32(reg, fls(priv->data->temp_mask) - 1); reg 384 drivers/thermal/armada_thermal.c sample = reg; reg 44 drivers/thermal/dove_thermal.c u32 reg; reg 48 drivers/thermal/dove_thermal.c reg = readl_relaxed(priv->control); reg 51 drivers/thermal/dove_thermal.c reg &= ~PMU_TDC0_AVG_NUM_MASK; reg 52 drivers/thermal/dove_thermal.c reg |= (0x1 << PMU_TDC0_AVG_NUM_OFFS); reg 55 drivers/thermal/dove_thermal.c reg &= ~PMU_TDC0_REF_CAL_CNT_MASK; reg 56 drivers/thermal/dove_thermal.c reg |= (0x0F1 << PMU_TDC0_REF_CAL_CNT_OFFS); reg 59 drivers/thermal/dove_thermal.c reg &= ~PMU_TDC0_SEL_VCAL_MASK; reg 60 drivers/thermal/dove_thermal.c reg |= (0x2 << PMU_TDC0_SEL_VCAL_OFFS); reg 61 drivers/thermal/dove_thermal.c writel(reg, priv->control); reg 64 drivers/thermal/dove_thermal.c reg = readl_relaxed(priv->control); reg 65 drivers/thermal/dove_thermal.c writel((reg | PMU_TDC0_SW_RST_MASK), priv->control); reg 66 drivers/thermal/dove_thermal.c writel(reg, priv->control); reg 69 drivers/thermal/dove_thermal.c reg = readl_relaxed(priv->sensor); reg 70 drivers/thermal/dove_thermal.c reg &= ~PMU_TM_DISABLE_MASK; reg 71 drivers/thermal/dove_thermal.c writel(reg, priv->sensor); reg 75 drivers/thermal/dove_thermal.c reg = readl_relaxed(priv->sensor); reg 76 drivers/thermal/dove_thermal.c if (reg & DOVE_THERMAL_TEMP_MASK) reg 89 drivers/thermal/dove_thermal.c unsigned long reg; reg 93 drivers/thermal/dove_thermal.c reg = readl_relaxed(priv->control + PMU_TEMP_DIOD_CTRL1_REG); reg 94 drivers/thermal/dove_thermal.c if ((reg & PMU_TDC1_TEMP_VALID_MASK) == 0x0) { reg 105 drivers/thermal/dove_thermal.c reg = readl_relaxed(priv->sensor); reg 106 drivers/thermal/dove_thermal.c reg = (reg >> DOVE_THERMAL_TEMP_OFFSET) & DOVE_THERMAL_TEMP_MASK; reg 107 drivers/thermal/dove_thermal.c *temp = ((3220000000UL - (10000000UL * reg)) / 13625); reg 503 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c if (!ra->reg) reg 506 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c ra->value = readq((void __iomem *)ra->reg); reg 515 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c if (!ra->reg) reg 518 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c val = readq((void __iomem *)ra->reg); reg 521 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c writeq(val, (void __iomem *)ra->reg); reg 529 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c enum rapl_domain_reg_id reg; reg 545 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c for (reg = RAPL_DOMAIN_REG_LIMIT; reg < RAPL_DOMAIN_REG_MAX; reg++) reg 546 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c if (rapl_regs->regs[domain][reg]) reg 547 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c rapl_mmio_priv.regs[domain][reg] = reg 549 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c rapl_regs->regs[domain][reg]; reg 161 drivers/thermal/intel/intel_bxt_pmic_thermal.c u16 reg, evt_stat_reg; reg 172 drivers/thermal/intel/intel_bxt_pmic_thermal.c reg = td->maps[i].trip_config[j].irq_reg; reg 178 drivers/thermal/intel/intel_bxt_pmic_thermal.c if (regmap_read(regmap, reg, &ret)) reg 201 drivers/thermal/intel/intel_bxt_pmic_thermal.c regmap_write(regmap, reg, reg_val & mask); reg 216 drivers/thermal/intel/intel_bxt_pmic_thermal.c u16 reg; reg 258 drivers/thermal/intel/intel_bxt_pmic_thermal.c reg = thermal_data->maps[i].trip_config[j].irq_en; reg 260 drivers/thermal/intel/intel_bxt_pmic_thermal.c ret = regmap_update_bits(regmap, reg, mask, 0x00); reg 29 drivers/thermal/kirkwood_thermal.c unsigned long reg; reg 32 drivers/thermal/kirkwood_thermal.c reg = readl_relaxed(priv->sensor); reg 35 drivers/thermal/kirkwood_thermal.c if (!((reg >> KIRKWOOD_THERMAL_VALID_OFFSET) & reg 47 drivers/thermal/kirkwood_thermal.c reg = (reg >> KIRKWOOD_THERMAL_TEMP_OFFSET) & reg 49 drivers/thermal/kirkwood_thermal.c *temp = ((3220000000UL - (10000000UL * reg)) / 13625); reg 112 drivers/thermal/qcom/qcom-spmi-temp-alarm.c u8 reg = 0; reg 114 drivers/thermal/qcom/qcom-spmi-temp-alarm.c ret = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, ®); reg 119 drivers/thermal/qcom/qcom-spmi-temp-alarm.c ret = reg & STATUS_GEN1_STAGE_MASK; reg 121 drivers/thermal/qcom/qcom-spmi-temp-alarm.c ret = (reg & STATUS_GEN2_STATE_MASK) >> STATUS_GEN2_STATE_SHIFT; reg 202 drivers/thermal/qcom/qcom-spmi-temp-alarm.c u8 reg; reg 211 drivers/thermal/qcom/qcom-spmi-temp-alarm.c reg = SHUTDOWN_CTRL1_RATE_25HZ; reg 235 drivers/thermal/qcom/qcom-spmi-temp-alarm.c reg |= chip->thresh; reg 237 drivers/thermal/qcom/qcom-spmi-temp-alarm.c reg |= SHUTDOWN_CTRL1_OVERRIDE_S2; reg 239 drivers/thermal/qcom/qcom-spmi-temp-alarm.c return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg); reg 308 drivers/thermal/qcom/qcom-spmi-temp-alarm.c u8 reg = 0; reg 313 drivers/thermal/qcom/qcom-spmi-temp-alarm.c ret = qpnp_tm_read(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, ®); reg 317 drivers/thermal/qcom/qcom-spmi-temp-alarm.c chip->thresh = reg & SHUTDOWN_CTRL1_THRESHOLD_MASK; reg 339 drivers/thermal/qcom/qcom-spmi-temp-alarm.c reg = ALARM_CTRL_FORCE_ENABLE; reg 340 drivers/thermal/qcom/qcom-spmi-temp-alarm.c ret = qpnp_tm_write(chip, QPNP_TM_REG_ALARM_CTRL, reg); reg 118 drivers/thermal/qcom/tsens-8960.c u32 reg, mask; reg 120 drivers/thermal/qcom/tsens-8960.c ret = regmap_read(priv->tm_map, CNTL_ADDR, ®); reg 125 drivers/thermal/qcom/tsens-8960.c ret = regmap_write(priv->tm_map, CNTL_ADDR, reg | SW_RST); reg 130 drivers/thermal/qcom/tsens-8960.c reg |= mask | SLP_CLK_ENA | EN; reg 132 drivers/thermal/qcom/tsens-8960.c reg |= mask | SLP_CLK_ENA_8660 | EN; reg 134 drivers/thermal/qcom/tsens-8960.c ret = regmap_write(priv->tm_map, CNTL_ADDR, reg); reg 97 drivers/thermal/rcar_gen3_thermal.c u32 reg) reg 99 drivers/thermal/rcar_gen3_thermal.c return ioread32(tsc->base + reg); reg 103 drivers/thermal/rcar_gen3_thermal.c u32 reg, u32 data) reg 105 drivers/thermal/rcar_gen3_thermal.c iowrite32(data, tsc->base + reg); reg 172 drivers/thermal/rcar_gen3_thermal.c u32 reg; reg 175 drivers/thermal/rcar_gen3_thermal.c reg = rcar_gen3_thermal_read(tsc, REG_GEN3_TEMP) & CTEMP_MASK; reg 177 drivers/thermal/rcar_gen3_thermal.c if (reg <= thcode[tsc->id][1]) reg 178 drivers/thermal/rcar_gen3_thermal.c val = FIXPT_DIV(FIXPT_INT(reg) - tsc->coef.b1, reg 181 drivers/thermal/rcar_gen3_thermal.c val = FIXPT_DIV(FIXPT_INT(reg) - tsc->coef.b2, reg 145 drivers/thermal/rcar_thermal.c u32 reg) reg 147 drivers/thermal/rcar_thermal.c return ioread32(common->base + reg); reg 153 drivers/thermal/rcar_thermal.c u32 reg, u32 data) reg 155 drivers/thermal/rcar_thermal.c iowrite32(data, common->base + reg); reg 161 drivers/thermal/rcar_thermal.c u32 reg, u32 mask, u32 data) reg 165 drivers/thermal/rcar_thermal.c val = ioread32(common->base + reg); reg 168 drivers/thermal/rcar_thermal.c iowrite32(val, common->base + reg); reg 172 drivers/thermal/rcar_thermal.c static u32 _rcar_thermal_read(struct rcar_thermal_priv *priv, u32 reg) reg 174 drivers/thermal/rcar_thermal.c return ioread32(priv->base + reg); reg 179 drivers/thermal/rcar_thermal.c u32 reg, u32 data) reg 181 drivers/thermal/rcar_thermal.c iowrite32(data, priv->base + reg); reg 185 drivers/thermal/rcar_thermal.c static void _rcar_thermal_bset(struct rcar_thermal_priv *priv, u32 reg, reg 190 drivers/thermal/rcar_thermal.c val = ioread32(priv->base + reg); reg 193 drivers/thermal/rcar_thermal.c iowrite32(val, priv->base + reg); reg 108 drivers/thermal/rockchip_thermal.c void __iomem *reg, enum tshut_polarity p); reg 109 drivers/thermal/rockchip_thermal.c void (*irq_ack)(void __iomem *reg); reg 110 drivers/thermal/rockchip_thermal.c void (*control)(void __iomem *reg, bool on); reg 114 drivers/thermal/rockchip_thermal.c int chn, void __iomem *reg, int *temp); reg 116 drivers/thermal/rockchip_thermal.c int chn, void __iomem *reg, int temp); reg 118 drivers/thermal/rockchip_thermal.c int chn, void __iomem *reg, int temp); reg 119 drivers/thermal/rockchip_thermal.c void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m); reg 301 drivers/thermal/tegra/soctherm.c void __iomem *reg; reg 368 drivers/thermal/tegra/soctherm.c static inline void ccroc_writel(struct tegra_soctherm *ts, u32 value, u32 reg) reg 370 drivers/thermal/tegra/soctherm.c writel(value, (ts->ccroc_regs + reg)); reg 380 drivers/thermal/tegra/soctherm.c static inline u32 ccroc_readl(struct tegra_soctherm *ts, u32 reg) reg 382 drivers/thermal/tegra/soctherm.c return readl(ts->ccroc_regs + reg); reg 429 drivers/thermal/tegra/soctherm.c val = readl(zone->reg); reg 2220 drivers/thermal/tegra/soctherm.c zone->reg = tegra->regs + soc->ttgs[i]->sensor_temp_offset; reg 44 drivers/thermal/ti-soc-thermal/ti-bandgap.c static u32 ti_bandgap_readl(struct ti_bandgap *bgp, u32 reg) reg 46 drivers/thermal/ti-soc-thermal/ti-bandgap.c return readl(bgp->base + reg); reg 57 drivers/thermal/ti-soc-thermal/ti-bandgap.c static void ti_bandgap_writel(struct ti_bandgap *bgp, u32 val, u32 reg) reg 59 drivers/thermal/ti-soc-thermal/ti-bandgap.c writel(val, bgp->base + reg); reg 68 drivers/thermal/ti-soc-thermal/ti-bandgap.c #define RMW_BITS(bgp, id, reg, mask, val) \ reg 74 drivers/thermal/ti-soc-thermal/ti-bandgap.c r = ti_bandgap_readl(bgp, t->reg); \ reg 77 drivers/thermal/ti-soc-thermal/ti-bandgap.c ti_bandgap_writel(bgp, r, t->reg); \ reg 121 drivers/thermal/ti-soc-thermal/ti-bandgap.c static u32 ti_errata814_bandgap_read_temp(struct ti_bandgap *bgp, u32 reg) reg 125 drivers/thermal/ti-soc-thermal/ti-bandgap.c val1 = ti_bandgap_readl(bgp, reg); reg 126 drivers/thermal/ti-soc-thermal/ti-bandgap.c val2 = ti_bandgap_readl(bgp, reg); reg 133 drivers/thermal/ti-soc-thermal/ti-bandgap.c return ti_bandgap_readl(bgp, reg); reg 151 drivers/thermal/ti-soc-thermal/ti-bandgap.c u32 temp, reg; reg 154 drivers/thermal/ti-soc-thermal/ti-bandgap.c reg = tsr->temp_sensor_ctrl; reg 162 drivers/thermal/ti-soc-thermal/ti-bandgap.c reg = tsr->ctrl_dtemp_1; reg 167 drivers/thermal/ti-soc-thermal/ti-bandgap.c temp = ti_errata814_bandgap_read_temp(bgp, reg); reg 169 drivers/thermal/ti-soc-thermal/ti-bandgap.c temp = ti_bandgap_readl(bgp, reg); reg 58 drivers/thunderbolt/nhi.c int reg = REG_RING_INTERRUPT_BASE + reg 94 drivers/thunderbolt/nhi.c old = ioread32(ring->nhi->iobase + reg); reg 102 drivers/thunderbolt/nhi.c active ? "enabling" : "disabling", reg, bit, old, new); reg 109 drivers/thunderbolt/nhi.c iowrite32(new, ring->nhi->iobase + reg); reg 339 drivers/thunderbolt/nhi.c int reg = REG_RING_INTERRUPT_BASE + idx / 32 * 4; reg 343 drivers/thunderbolt/nhi.c val = ioread32(ring->nhi->iobase + reg); reg 348 drivers/thunderbolt/nhi.c iowrite32(val, ring->nhi->iobase + reg); reg 922 drivers/thunderbolt/nhi.c u32 reg = REG_INT_THROTTLING_RATE + i * 4; reg 923 drivers/thunderbolt/nhi.c iowrite32(throttle, nhi->iobase + reg); reg 293 drivers/tty/cyclades.c static void cyy_writeb(struct cyclades_port *port, u32 reg, u8 val) reg 297 drivers/tty/cyclades.c cy_writeb(port->u.cyy.base_addr + (reg << card->bus_index), val); reg 300 drivers/tty/cyclades.c static u8 cyy_readb(struct cyclades_port *port, u32 reg) reg 304 drivers/tty/cyclades.c return readb(port->u.cyy.base_addr + (reg << card->bus_index)); reg 160 drivers/tty/hvc/hvc_opal.c const __be32 *reg; reg 175 drivers/tty/hvc/hvc_opal.c reg = of_get_property(dev->dev.of_node, "reg", NULL); reg 176 drivers/tty/hvc/hvc_opal.c termno = reg ? be32_to_cpup(reg) : 0; reg 152 drivers/tty/mips_ejtag_fdc.c void __iomem *reg; reg 174 drivers/tty/mips_ejtag_fdc.c __raw_writel(data, priv->reg + offs); reg 180 drivers/tty/mips_ejtag_fdc.c return __raw_readl(priv->reg + offs); reg 901 drivers/tty/mips_ejtag_fdc.c priv->reg = devm_ioremap_nocache(priv->dev, dev->res.start, reg 903 drivers/tty/mips_ejtag_fdc.c if (!priv->reg) { reg 952 drivers/tty/mips_ejtag_fdc.c mips_ejtag_fdc_con.regs[dev->cpu] = priv->reg; reg 100 drivers/tty/serial/8250/8250_aspeed_vuart.c u8 reg; reg 102 drivers/tty/serial/8250/8250_aspeed_vuart.c reg = readb(vuart->regs + ASPEED_VUART_GCRB); reg 103 drivers/tty/serial/8250/8250_aspeed_vuart.c reg &= ASPEED_VUART_GCRB_HOST_SIRQ_MASK; reg 104 drivers/tty/serial/8250/8250_aspeed_vuart.c reg >>= ASPEED_VUART_GCRB_HOST_SIRQ_SHIFT; reg 106 drivers/tty/serial/8250/8250_aspeed_vuart.c return snprintf(buf, PAGE_SIZE - 1, "%u\n", reg); reg 115 drivers/tty/serial/8250/8250_aspeed_vuart.c u8 reg; reg 124 drivers/tty/serial/8250/8250_aspeed_vuart.c reg = readb(vuart->regs + ASPEED_VUART_GCRB); reg 125 drivers/tty/serial/8250/8250_aspeed_vuart.c reg &= ~ASPEED_VUART_GCRB_HOST_SIRQ_MASK; reg 126 drivers/tty/serial/8250/8250_aspeed_vuart.c reg |= val; reg 127 drivers/tty/serial/8250/8250_aspeed_vuart.c writeb(reg, vuart->regs + ASPEED_VUART_GCRB); reg 146 drivers/tty/serial/8250/8250_aspeed_vuart.c u8 reg = readb(vuart->regs + ASPEED_VUART_GCRA); reg 149 drivers/tty/serial/8250/8250_aspeed_vuart.c reg |= ASPEED_VUART_GCRA_VUART_EN; reg 151 drivers/tty/serial/8250/8250_aspeed_vuart.c reg &= ~ASPEED_VUART_GCRA_VUART_EN; reg 153 drivers/tty/serial/8250/8250_aspeed_vuart.c writeb(reg, vuart->regs + ASPEED_VUART_GCRA); reg 159 drivers/tty/serial/8250/8250_aspeed_vuart.c u8 reg; reg 161 drivers/tty/serial/8250/8250_aspeed_vuart.c reg = readb(vuart->regs + ASPEED_VUART_GCRA); reg 165 drivers/tty/serial/8250/8250_aspeed_vuart.c reg |= ASPEED_VUART_GCRA_DISABLE_HOST_TX_DISCARD; reg 167 drivers/tty/serial/8250/8250_aspeed_vuart.c reg &= ~ASPEED_VUART_GCRA_DISABLE_HOST_TX_DISCARD; reg 169 drivers/tty/serial/8250/8250_aspeed_vuart.c writeb(reg, vuart->regs + ASPEED_VUART_GCRA); reg 42 drivers/tty/serial/8250/8250_dwlib.c static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg) reg 45 drivers/tty/serial/8250/8250_dwlib.c iowrite32be(reg, p->membase + offset); reg 47 drivers/tty/serial/8250/8250_dwlib.c writel(reg, p->membase + offset); reg 83 drivers/tty/serial/8250/8250_dwlib.c u32 reg; reg 89 drivers/tty/serial/8250/8250_dwlib.c reg = dw8250_readl_ext(p, DW_UART_UCV); reg 90 drivers/tty/serial/8250/8250_dwlib.c if (!reg) reg 94 drivers/tty/serial/8250/8250_dwlib.c (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); reg 97 drivers/tty/serial/8250/8250_dwlib.c reg = dw8250_readl_ext(p, DW_UART_DLF); reg 100 drivers/tty/serial/8250/8250_dwlib.c if (reg) { reg 103 drivers/tty/serial/8250/8250_dwlib.c d->dlf_size = fls(reg); reg 108 drivers/tty/serial/8250/8250_dwlib.c reg = dw8250_readl_ext(p, DW_UART_CPR); reg 109 drivers/tty/serial/8250/8250_dwlib.c if (!reg) reg 113 drivers/tty/serial/8250/8250_dwlib.c if (reg & DW_UART_CPR_FIFO_MODE) { reg 116 drivers/tty/serial/8250/8250_dwlib.c p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); reg 120 drivers/tty/serial/8250/8250_dwlib.c if (reg & DW_UART_CPR_AFCE_MODE) reg 123 drivers/tty/serial/8250/8250_dwlib.c if (reg & DW_UART_CPR_SIR_MODE) reg 101 drivers/tty/serial/8250/8250_fintek.c static u8 sio_read_reg(struct fintek_8250 *pdata, u8 reg) reg 103 drivers/tty/serial/8250/8250_fintek.c outb(reg, pdata->base_port + ADDR_PORT); reg 107 drivers/tty/serial/8250/8250_fintek.c static void sio_write_reg(struct fintek_8250 *pdata, u8 reg, u8 data) reg 109 drivers/tty/serial/8250/8250_fintek.c outb(reg, pdata->base_port + ADDR_PORT); reg 113 drivers/tty/serial/8250/8250_fintek.c static void sio_write_mask_reg(struct fintek_8250 *pdata, u8 reg, u8 mask, reg 118 drivers/tty/serial/8250/8250_fintek.c tmp = (sio_read_reg(pdata, reg) & ~mask) | (mask & data); reg 119 drivers/tty/serial/8250/8250_fintek.c sio_write_reg(pdata, reg, tmp); reg 313 drivers/tty/serial/8250/8250_fintek.c u8 reg; reg 328 drivers/tty/serial/8250/8250_fintek.c reg = RS485; reg 331 drivers/tty/serial/8250/8250_fintek.c reg = F81866_UART_CLK; reg 354 drivers/tty/serial/8250/8250_fintek.c sio_write_mask_reg(pdata, reg, F81866_UART_CLK_MASK, reg 80 drivers/tty/serial/8250/8250_lpss.c u32 reg; reg 98 drivers/tty/serial/8250/8250_lpss.c reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT); reg 99 drivers/tty/serial/8250/8250_lpss.c writel(reg, p->membase + BYT_PRV_CLK); reg 100 drivers/tty/serial/8250/8250_lpss.c reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE; reg 101 drivers/tty/serial/8250/8250_lpss.c writel(reg, p->membase + BYT_PRV_CLK); reg 131 drivers/tty/serial/8250/8250_omap.c static u32 uart_read(struct uart_8250_port *up, u32 reg) reg 133 drivers/tty/serial/8250/8250_omap.c return readl(up->port.membase + (reg << up->port.regshift)); reg 1207 drivers/tty/serial/8250/8250_pci.c u8 reg, qopr; reg 1211 drivers/tty/serial/8250/8250_pci.c reg = pci_quatech_rqopr(port) & 0xC0; reg 1212 drivers/tty/serial/8250/8250_pci.c if (reg != QPCR_TEST_GET1) reg 1215 drivers/tty/serial/8250/8250_pci.c reg = pci_quatech_rqopr(port) & 0xC0; reg 1216 drivers/tty/serial/8250/8250_pci.c if (reg != QPCR_TEST_GET2) reg 1219 drivers/tty/serial/8250/8250_pci.c reg = pci_quatech_rqopr(port) & 0xC0; reg 1220 drivers/tty/serial/8250/8250_pci.c if (reg != QPCR_TEST_GET3) reg 1223 drivers/tty/serial/8250/8250_pci.c reg = pci_quatech_rqopr(port) & 0xC0; reg 1224 drivers/tty/serial/8250/8250_pci.c if (reg != QPCR_TEST_GET4) reg 1233 drivers/tty/serial/8250/8250_pci.c u8 qopr, reg, set; reg 1242 drivers/tty/serial/8250/8250_pci.c reg = pci_quatech_rqopr(port); reg 1243 drivers/tty/serial/8250/8250_pci.c if (reg & QOPR_CLOCK_X8) { reg 1248 drivers/tty/serial/8250/8250_pci.c reg = pci_quatech_rqopr(port); reg 1249 drivers/tty/serial/8250/8250_pci.c if (!(reg & QOPR_CLOCK_X8)) { reg 1253 drivers/tty/serial/8250/8250_pci.c reg &= QOPR_CLOCK_X8; reg 1254 drivers/tty/serial/8250/8250_pci.c if (reg == QOPR_CLOCK_X2) { reg 1257 drivers/tty/serial/8250/8250_pci.c } else if (reg == QOPR_CLOCK_X4) { reg 1260 drivers/tty/serial/8250/8250_pci.c } else if (reg == QOPR_CLOCK_X8) { reg 84 drivers/tty/serial/altera_uart.c static u32 altera_uart_readl(struct uart_port *port, int reg) reg 86 drivers/tty/serial/altera_uart.c return readl(port->membase + (reg << port->regshift)); reg 89 drivers/tty/serial/altera_uart.c static void altera_uart_writel(struct uart_port *port, u32 dat, int reg) reg 91 drivers/tty/serial/altera_uart.c writel(dat, port->membase + (reg << port->regshift)); reg 284 drivers/tty/serial/amba-pl011.c unsigned int reg) reg 286 drivers/tty/serial/amba-pl011.c return uap->reg_offset[reg]; reg 290 drivers/tty/serial/amba-pl011.c unsigned int reg) reg 292 drivers/tty/serial/amba-pl011.c void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); reg 299 drivers/tty/serial/amba-pl011.c unsigned int reg) reg 301 drivers/tty/serial/amba-pl011.c void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); reg 72 drivers/tty/serial/arc_uart.c #define RBASE(port, reg) (port->membase + reg) reg 216 drivers/tty/serial/atmel_serial.c static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg) reg 218 drivers/tty/serial/atmel_serial.c return __raw_readl(port->membase + reg); reg 221 drivers/tty/serial/atmel_serial.c static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value) reg 223 drivers/tty/serial/atmel_serial.c __raw_writel(value, port->membase + reg); reg 145 drivers/tty/serial/atmel_serial.h #define ATMEL_US_TXFL(reg) (((reg) >> 0) & 0x3f) /* TX FIFO Level */ reg 146 drivers/tty/serial/atmel_serial.h #define ATMEL_US_RXFL(reg) (((reg) >> 16) & 0x3f) /* RX FIFO Level */ reg 1287 drivers/tty/serial/fsl_lpuart.c unsigned char reg; reg 1289 drivers/tty/serial/fsl_lpuart.c reg = readb(port->membase + UARTMODEM); reg 1290 drivers/tty/serial/fsl_lpuart.c if (reg & UARTMODEM_TXCTSE) reg 1293 drivers/tty/serial/fsl_lpuart.c if (reg & UARTMODEM_RXRTSE) reg 1302 drivers/tty/serial/fsl_lpuart.c unsigned long reg; reg 1304 drivers/tty/serial/fsl_lpuart.c reg = lpuart32_read(port, UARTMODIR); reg 1305 drivers/tty/serial/fsl_lpuart.c if (reg & UARTMODIR_TXCTSE) reg 1308 drivers/tty/serial/fsl_lpuart.c if (reg & UARTMODIR_RXRTSE) reg 114 drivers/tty/serial/ip22zilog.c unsigned char reg) reg 118 drivers/tty/serial/ip22zilog.c writeb(reg, &channel->control); reg 127 drivers/tty/serial/ip22zilog.c unsigned char reg, unsigned char value) reg 129 drivers/tty/serial/ip22zilog.c writeb(reg, &channel->control); reg 125 drivers/tty/serial/lantiq.c static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg) reg 127 drivers/tty/serial/lantiq.c u32 tmp = __raw_readl(reg); reg 129 drivers/tty/serial/lantiq.c __raw_writel((tmp & ~clear) | set, reg); reg 290 drivers/tty/serial/max310x.c static u8 max310x_port_read(struct uart_port *port, u8 reg) reg 295 drivers/tty/serial/max310x.c regmap_read(s->regmap, port->iobase + reg, &val); reg 300 drivers/tty/serial/max310x.c static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) reg 304 drivers/tty/serial/max310x.c regmap_write(s->regmap, port->iobase + reg, val); reg 307 drivers/tty/serial/max310x.c static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) reg 311 drivers/tty/serial/max310x.c regmap_update_bits(s->regmap, port->iobase + reg, mask, val); reg 448 drivers/tty/serial/max310x.c static bool max310x_reg_writeable(struct device *dev, unsigned int reg) reg 450 drivers/tty/serial/max310x.c switch (reg & 0x1f) { reg 465 drivers/tty/serial/max310x.c static bool max310x_reg_volatile(struct device *dev, unsigned int reg) reg 467 drivers/tty/serial/max310x.c switch (reg & 0x1f) { reg 487 drivers/tty/serial/max310x.c static bool max310x_reg_precious(struct device *dev, unsigned int reg) reg 489 drivers/tty/serial/max310x.c switch (reg & 0x1f) { reg 141 drivers/tty/serial/men_z135_uart.c u32 reg; reg 145 drivers/tty/serial/men_z135_uart.c reg = ioread32(port->membase + addr); reg 146 drivers/tty/serial/men_z135_uart.c reg |= val; reg 147 drivers/tty/serial/men_z135_uart.c iowrite32(reg, port->membase + addr); reg 163 drivers/tty/serial/men_z135_uart.c u32 reg; reg 167 drivers/tty/serial/men_z135_uart.c reg = ioread32(port->membase + addr); reg 168 drivers/tty/serial/men_z135_uart.c reg &= ~val; reg 169 drivers/tty/serial/men_z135_uart.c iowrite32(reg, port->membase + addr); reg 801 drivers/tty/serial/mvebu-uart.c struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0); reg 808 drivers/tty/serial/mvebu-uart.c if (!reg) { reg 850 drivers/tty/serial/mvebu-uart.c port->mapbase = reg->start; reg 852 drivers/tty/serial/mvebu-uart.c port->membase = devm_ioremap_resource(&pdev->dev, reg); reg 488 drivers/tty/serial/mxs-auart.c unsigned int reg) reg 490 drivers/tty/serial/mxs-auart.c return uap->vendor->reg_offset[reg]; reg 494 drivers/tty/serial/mxs-auart.c unsigned int reg) reg 496 drivers/tty/serial/mxs-auart.c void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); reg 502 drivers/tty/serial/mxs-auart.c unsigned int reg) reg 504 drivers/tty/serial/mxs-auart.c void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); reg 510 drivers/tty/serial/mxs-auart.c unsigned int reg) reg 512 drivers/tty/serial/mxs-auart.c void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); reg 518 drivers/tty/serial/mxs-auart.c unsigned int reg) reg 520 drivers/tty/serial/mxs-auart.c void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); reg 1175 drivers/tty/serial/mxs-auart.c unsigned int reg; reg 1180 drivers/tty/serial/mxs-auart.c reg = mxs_read(s, REG_CTRL0); reg 1181 drivers/tty/serial/mxs-auart.c if (!(reg & AUART_CTRL0_SFTRST)) reg 1191 drivers/tty/serial/mxs-auart.c u32 reg; reg 1193 drivers/tty/serial/mxs-auart.c reg = mxs_read(s, REG_CTRL0); reg 1195 drivers/tty/serial/mxs-auart.c if (reg & AUART_CTRL0_SFTRST) reg 1202 drivers/tty/serial/mxs-auart.c reg = mxs_read(s, REG_CTRL0); reg 1204 drivers/tty/serial/mxs-auart.c if (reg & AUART_CTRL0_CLKGATE) reg 75 drivers/tty/serial/pic32_uart.h u32 reg, u32 val) reg 79 drivers/tty/serial/pic32_uart.h __raw_writel(val, port->membase + reg); reg 82 drivers/tty/serial/pic32_uart.h static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg) reg 86 drivers/tty/serial/pic32_uart.h return __raw_readl(port->membase + reg); reg 85 drivers/tty/serial/pmac_zilog.h static inline u8 read_zsreg(struct uart_pmac_port *port, u8 reg) reg 87 drivers/tty/serial/pmac_zilog.h if (reg != 0) reg 88 drivers/tty/serial/pmac_zilog.h writeb(reg, port->control_reg); reg 92 drivers/tty/serial/pmac_zilog.h static inline void write_zsreg(struct uart_pmac_port *port, u8 reg, u8 value) reg 94 drivers/tty/serial/pmac_zilog.h if (reg != 0) reg 95 drivers/tty/serial/pmac_zilog.h writeb(reg, port->control_reg); reg 267 drivers/tty/serial/qcom_geni_serial.c u32 reg; reg 292 drivers/tty/serial/qcom_geni_serial.c reg = readl(uport->membase + offset); reg 293 drivers/tty/serial/qcom_geni_serial.c if ((bool)(reg & field) == set) reg 234 drivers/tty/serial/rp2.c static void rp2_rmw(struct rp2_uart_port *up, int reg, reg 237 drivers/tty/serial/rp2.c u32 tmp = readl(up->base + reg); reg 240 drivers/tty/serial/rp2.c writel(tmp, up->base + reg); reg 243 drivers/tty/serial/rp2.c static void rp2_rmw_clr(struct rp2_uart_port *up, int reg, u32 val) reg 245 drivers/tty/serial/rp2.c rp2_rmw(up, reg, val, 0); reg 248 drivers/tty/serial/rp2.c static void rp2_rmw_set(struct rp2_uart_port *up, int reg, u32 val) reg 250 drivers/tty/serial/rp2.c rp2_rmw(up, reg, 0, val); reg 109 drivers/tty/serial/samsung.h #define portaddr(port, reg) ((port)->membase + (reg)) reg 110 drivers/tty/serial/samsung.h #define portaddrl(port, reg) \ reg 111 drivers/tty/serial/samsung.h ((unsigned long *)(unsigned long)((port)->membase + (reg))) reg 113 drivers/tty/serial/samsung.h #define rd_regb(port, reg) (readb_relaxed(portaddr(port, reg))) reg 114 drivers/tty/serial/samsung.h #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg))) reg 116 drivers/tty/serial/samsung.h #define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg)) reg 117 drivers/tty/serial/samsung.h #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg)) reg 122 drivers/tty/serial/samsung.h unsigned int reg) reg 128 drivers/tty/serial/samsung.h val = rd_regl(port, reg); reg 130 drivers/tty/serial/samsung.h wr_regl(port, reg, val); reg 135 drivers/tty/serial/samsung.h unsigned int reg) reg 141 drivers/tty/serial/samsung.h val = rd_regl(port, reg); reg 143 drivers/tty/serial/samsung.h wr_regl(port, reg, val); reg 121 drivers/tty/serial/sb1250-duart.c static u64 __read_sbdchn(struct sbd_port *sport, int reg) reg 123 drivers/tty/serial/sb1250-duart.c void __iomem *csr = sport->port.membase + reg; reg 128 drivers/tty/serial/sb1250-duart.c static u64 __read_sbdshr(struct sbd_port *sport, int reg) reg 130 drivers/tty/serial/sb1250-duart.c void __iomem *csr = sport->memctrl + reg; reg 135 drivers/tty/serial/sb1250-duart.c static void __write_sbdchn(struct sbd_port *sport, int reg, u64 value) reg 137 drivers/tty/serial/sb1250-duart.c void __iomem *csr = sport->port.membase + reg; reg 142 drivers/tty/serial/sb1250-duart.c static void __write_sbdshr(struct sbd_port *sport, int reg, u64 value) reg 144 drivers/tty/serial/sb1250-duart.c void __iomem *csr = sport->memctrl + reg; reg 159 drivers/tty/serial/sb1250-duart.c static unsigned char read_sbdchn(struct sbd_port *sport, int reg) reg 163 drivers/tty/serial/sb1250-duart.c retval = __read_sbdchn(sport, reg); reg 169 drivers/tty/serial/sb1250-duart.c static unsigned char read_sbdshr(struct sbd_port *sport, int reg) reg 173 drivers/tty/serial/sb1250-duart.c retval = __read_sbdshr(sport, reg); reg 179 drivers/tty/serial/sb1250-duart.c static void write_sbdchn(struct sbd_port *sport, int reg, unsigned int value) reg 181 drivers/tty/serial/sb1250-duart.c __write_sbdchn(sport, reg, value); reg 186 drivers/tty/serial/sb1250-duart.c static void write_sbdshr(struct sbd_port *sport, int reg, unsigned int value) reg 188 drivers/tty/serial/sb1250-duart.c __write_sbdshr(sport, reg, value); reg 146 drivers/tty/serial/sc16is7xx.c * reg set */ reg 353 drivers/tty/serial/sc16is7xx.c static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) reg 359 drivers/tty/serial/sc16is7xx.c regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val); reg 364 drivers/tty/serial/sc16is7xx.c static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) reg 369 drivers/tty/serial/sc16is7xx.c regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val); reg 401 drivers/tty/serial/sc16is7xx.c static void sc16is7xx_port_update(struct uart_port *port, u8 reg, reg 407 drivers/tty/serial/sc16is7xx.c regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, reg 461 drivers/tty/serial/sc16is7xx.c static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) reg 463 drivers/tty/serial/sc16is7xx.c switch (reg >> SC16IS7XX_REG_SHIFT) { reg 479 drivers/tty/serial/sc16is7xx.c static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg) reg 481 drivers/tty/serial/sc16is7xx.c switch (reg >> SC16IS7XX_REG_SHIFT) { reg 227 drivers/tty/serial/sccnxp.c static u8 sccnxp_read(struct uart_port *port, u8 reg) reg 232 drivers/tty/serial/sccnxp.c ret = readb(port->membase + (reg << port->regshift)); reg 239 drivers/tty/serial/sccnxp.c static void sccnxp_write(struct uart_port *port, u8 reg, u8 v) reg 243 drivers/tty/serial/sccnxp.c writeb(v, port->membase + (reg << port->regshift)); reg 248 drivers/tty/serial/sccnxp.c static u8 sccnxp_port_read(struct uart_port *port, u8 reg) reg 250 drivers/tty/serial/sccnxp.c return sccnxp_read(port, (port->line << 3) + reg); reg 253 drivers/tty/serial/sccnxp.c static void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v) reg 255 drivers/tty/serial/sccnxp.c sccnxp_write(port, (port->line << 3) + reg, v); reg 152 drivers/tty/serial/serial-tegra.c unsigned long reg) reg 154 drivers/tty/serial/serial-tegra.c return readl(tup->uport.membase + (reg << tup->uport.regshift)); reg 158 drivers/tty/serial/serial-tegra.c unsigned long reg) reg 160 drivers/tty/serial/serial-tegra.c writel(val, tup->uport.membase + (reg << tup->uport.regshift)); reg 508 drivers/tty/serial/sh-sci.c const struct plat_sci_reg *reg = sci_getreg(p, offset); reg 510 drivers/tty/serial/sh-sci.c if (reg->size == 8) reg 511 drivers/tty/serial/sh-sci.c return ioread8(p->membase + (reg->offset << p->regshift)); reg 512 drivers/tty/serial/sh-sci.c else if (reg->size == 16) reg 513 drivers/tty/serial/sh-sci.c return ioread16(p->membase + (reg->offset << p->regshift)); reg 522 drivers/tty/serial/sh-sci.c const struct plat_sci_reg *reg = sci_getreg(p, offset); reg 524 drivers/tty/serial/sh-sci.c if (reg->size == 8) reg 525 drivers/tty/serial/sh-sci.c iowrite8(value, p->membase + (reg->offset << p->regshift)); reg 526 drivers/tty/serial/sh-sci.c else if (reg->size == 16) reg 527 drivers/tty/serial/sh-sci.c iowrite16(value, p->membase + (reg->offset << p->regshift)); reg 759 drivers/tty/serial/sh-sci.c const struct plat_sci_reg *reg; reg 761 drivers/tty/serial/sh-sci.c reg = sci_getreg(port, SCTFDR); reg 762 drivers/tty/serial/sh-sci.c if (reg->size) reg 765 drivers/tty/serial/sh-sci.c reg = sci_getreg(port, SCFDR); reg 766 drivers/tty/serial/sh-sci.c if (reg->size) reg 781 drivers/tty/serial/sh-sci.c const struct plat_sci_reg *reg; reg 783 drivers/tty/serial/sh-sci.c reg = sci_getreg(port, SCRFDR); reg 784 drivers/tty/serial/sh-sci.c if (reg->size) reg 787 drivers/tty/serial/sh-sci.c reg = sci_getreg(port, SCFDR); reg 788 drivers/tty/serial/sh-sci.c if (reg->size) reg 973 drivers/tty/serial/sh-sci.c const struct plat_sci_reg *reg; reg 977 drivers/tty/serial/sh-sci.c reg = sci_getreg(port, s->params->overrun_reg); reg 978 drivers/tty/serial/sh-sci.c if (!reg->size) reg 2054 drivers/tty/serial/sh-sci.c const struct plat_sci_reg *reg; reg 2059 drivers/tty/serial/sh-sci.c reg = sci_getreg(port, SCFCR); reg 2060 drivers/tty/serial/sh-sci.c if (reg->size) reg 2339 drivers/tty/serial/sh-sci.c const struct plat_sci_reg *reg; reg 2345 drivers/tty/serial/sh-sci.c reg = sci_getreg(port, SCFCR); reg 2346 drivers/tty/serial/sh-sci.c if (reg->size) reg 2379 drivers/tty/serial/sh-sci.c const struct plat_sci_reg *reg; reg 2575 drivers/tty/serial/sh-sci.c reg = sci_getreg(port, SCFCR); reg 2576 drivers/tty/serial/sh-sci.c if (reg->size) { reg 68 drivers/tty/serial/sirfsoc_uart.c unsigned long reg; reg 72 drivers/tty/serial/sirfsoc_uart.c reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status); reg 73 drivers/tty/serial/sirfsoc_uart.c return (reg & ufifo_st->ff_empty(port)) ? TIOCSER_TEMT : 0; reg 439 drivers/tty/serial/sirfsoc_uart.h #define portaddr(port, reg) ((port)->membase + (reg)) reg 440 drivers/tty/serial/sirfsoc_uart.h #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg))) reg 441 drivers/tty/serial/sirfsoc_uart.h #define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg)) reg 48 drivers/tty/serial/stm32-usart.c static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits) reg 52 drivers/tty/serial/stm32-usart.c val = readl_relaxed(port->membase + reg); reg 54 drivers/tty/serial/stm32-usart.c writel_relaxed(val, port->membase + reg); reg 57 drivers/tty/serial/stm32-usart.c static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits) reg 61 drivers/tty/serial/stm32-usart.c val = readl_relaxed(port->membase + reg); reg 63 drivers/tty/serial/stm32-usart.c writel_relaxed(val, port->membase + reg); reg 131 drivers/tty/serial/sunzilog.c unsigned char reg) reg 135 drivers/tty/serial/sunzilog.c writeb(reg, &channel->control); reg 144 drivers/tty/serial/sunzilog.c unsigned char reg, unsigned char value) reg 146 drivers/tty/serial/sunzilog.c writeb(reg, &channel->control); reg 142 drivers/tty/serial/zs.c static u8 read_zsreg(struct zs_port *zport, int reg) reg 147 drivers/tty/serial/zs.c if (reg != 0) { reg 148 drivers/tty/serial/zs.c writeb(reg & 0xf, control); reg 157 drivers/tty/serial/zs.c static void write_zsreg(struct zs_port *zport, int reg, u8 value) reg 161 drivers/tty/serial/zs.c if (reg != 0) { reg 162 drivers/tty/serial/zs.c writeb(reg & 0xf, control); reg 2093 drivers/tty/synclink_gt.c unsigned short reg; reg 2096 drivers/tty/synclink_gt.c reg = rd_reg16(info, RDR); reg 2097 drivers/tty/synclink_gt.c DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg)); reg 2104 drivers/tty/synclink_gt.c info->rbufs[i].buf[count++] = (unsigned char)reg; reg 2107 drivers/tty/synclink_gt.c info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8); reg 2108 drivers/tty/synclink_gt.c if (count == info->rbuf_fill_level || (reg & BIT10)) { reg 2111 drivers/tty/synclink_gt.c set_desc_status(info->rbufs[i], BIT15 | (reg >> 8)); reg 70 drivers/usb/c67x00/c67x00-ll-hpi.c static inline u16 hpi_read_reg(struct c67x00_device *dev, int reg) reg 73 drivers/usb/c67x00/c67x00-ll-hpi.c return __raw_readw(dev->hpi.base + reg * dev->hpi.regstep); reg 76 drivers/usb/c67x00/c67x00-ll-hpi.c static inline void hpi_write_reg(struct c67x00_device *dev, int reg, u16 value) reg 79 drivers/usb/c67x00/c67x00-ll-hpi.c __raw_writew(value, dev->hpi.base + reg * dev->hpi.regstep); reg 82 drivers/usb/c67x00/c67x00-ll-hpi.c static inline u16 hpi_read_word_nolock(struct c67x00_device *dev, u16 reg) reg 84 drivers/usb/c67x00/c67x00-ll-hpi.c hpi_write_reg(dev, HPI_ADDR, reg); reg 88 drivers/usb/c67x00/c67x00-ll-hpi.c static u16 hpi_read_word(struct c67x00_device *dev, u16 reg) reg 94 drivers/usb/c67x00/c67x00-ll-hpi.c value = hpi_read_word_nolock(dev, reg); reg 100 drivers/usb/c67x00/c67x00-ll-hpi.c static void hpi_write_word_nolock(struct c67x00_device *dev, u16 reg, u16 value) reg 102 drivers/usb/c67x00/c67x00-ll-hpi.c hpi_write_reg(dev, HPI_ADDR, reg); reg 106 drivers/usb/c67x00/c67x00-ll-hpi.c static void hpi_write_word(struct c67x00_device *dev, u16 reg, u16 value) reg 111 drivers/usb/c67x00/c67x00-ll-hpi.c hpi_write_word_nolock(dev, reg, value); reg 150 drivers/usb/c67x00/c67x00-ll-hpi.c static void hpi_set_bits(struct c67x00_device *dev, u16 reg, u16 mask) reg 156 drivers/usb/c67x00/c67x00-ll-hpi.c value = hpi_read_word_nolock(dev, reg); reg 157 drivers/usb/c67x00/c67x00-ll-hpi.c hpi_write_word_nolock(dev, reg, value | mask); reg 161 drivers/usb/c67x00/c67x00-ll-hpi.c static void hpi_clear_bits(struct c67x00_device *dev, u16 reg, u16 mask) reg 167 drivers/usb/c67x00/c67x00-ll-hpi.c value = hpi_read_word_nolock(dev, reg); reg 168 drivers/usb/c67x00/c67x00-ll-hpi.c hpi_write_word_nolock(dev, reg, value & ~mask); reg 33 drivers/usb/cdns3/drd.c u32 reg; reg 43 drivers/usb/cdns3/drd.c reg = readl(&cdns->otg_v1_regs->override); reg 44 drivers/usb/cdns3/drd.c reg |= OVERRIDE_IDPULLUP; reg 45 drivers/usb/cdns3/drd.c writel(reg, &cdns->otg_v1_regs->override); reg 47 drivers/usb/cdns3/drd.c reg = readl(&cdns->otg_v0_regs->ctrl1); reg 48 drivers/usb/cdns3/drd.c reg |= OVERRIDE_IDPULLUP_V0; reg 49 drivers/usb/cdns3/drd.c writel(reg, &cdns->otg_v0_regs->ctrl1); reg 137 drivers/usb/cdns3/drd.c u32 reg = OTGCMD_OTG_DIS; reg 141 drivers/usb/cdns3/drd.c writel(OTGCMD_HOST_BUS_REQ | reg, &cdns->otg_regs->cmd); reg 174 drivers/usb/cdns3/drd.c u32 reg = OTGCMD_OTG_DIS; reg 178 drivers/usb/cdns3/drd.c writel(OTGCMD_DEV_BUS_REQ | reg, &cdns->otg_regs->cmd); reg 279 drivers/usb/cdns3/drd.c u32 reg; reg 284 drivers/usb/cdns3/drd.c reg = readl(&cdns->otg_regs->ivect); reg 286 drivers/usb/cdns3/drd.c if (!reg) reg 289 drivers/usb/cdns3/drd.c if (reg & OTGIEN_ID_CHANGE_INT) { reg 296 drivers/usb/cdns3/drd.c if (reg & (OTGIEN_VBUSVALID_RISE_INT | OTGIEN_VBUSVALID_FALL_INT)) { reg 198 drivers/usb/cdns3/ep0.c u32 reg; reg 216 drivers/usb/cdns3/ep0.c reg = readl(&priv_dev->regs->usb_cmd); reg 218 drivers/usb/cdns3/ep0.c writel(reg | USB_CMD_FADDR(addr) | USB_CMD_SET_ADDR, reg 331 drivers/usb/cdns3/gadget.c u32 reg; reg 333 drivers/usb/cdns3/gadget.c reg = readl(&priv_dev->regs->usb_sts); reg 335 drivers/usb/cdns3/gadget.c if (DEV_SUPERSPEED(reg)) reg 337 drivers/usb/cdns3/gadget.c else if (DEV_HIGHSPEED(reg)) reg 339 drivers/usb/cdns3/gadget.c else if (DEV_FULLSPEED(reg)) reg 341 drivers/usb/cdns3/gadget.c else if (DEV_LOWSPEED(reg)) reg 382 drivers/usb/cdns3/gadget.c #define cdns3_wa2_enable_detection(priv_dev, ep_priv, reg) do { \ reg 385 drivers/usb/cdns3/gadget.c (reg) |= EP_STS_EN_DESCMISEN; \ reg 483 drivers/usb/cdns3/gadget.c u32 reg; reg 487 drivers/usb/cdns3/gadget.c reg = readl(&priv_dev->regs->ep_sts_en); reg 488 drivers/usb/cdns3/gadget.c reg &= ~EP_STS_EN_DESCMISEN; reg 490 drivers/usb/cdns3/gadget.c writel(reg, &priv_dev->regs->ep_sts_en); reg 1380 drivers/usb/cdns3/gadget.c u32 reg; reg 1383 drivers/usb/cdns3/gadget.c reg = readl(&priv_dev->regs->usb_ists); reg 1384 drivers/usb/cdns3/gadget.c if (reg) { reg 1392 drivers/usb/cdns3/gadget.c reg = ~reg & readl(&priv_dev->regs->usb_ien); reg 1394 drivers/usb/cdns3/gadget.c writel(reg, &priv_dev->regs->usb_ien); reg 1399 drivers/usb/cdns3/gadget.c reg = readl(&priv_dev->regs->ep_ists); reg 1400 drivers/usb/cdns3/gadget.c if (reg) { reg 1423 drivers/usb/cdns3/gadget.c u32 reg; reg 1427 drivers/usb/cdns3/gadget.c reg = readl(&priv_dev->regs->usb_ists); reg 1428 drivers/usb/cdns3/gadget.c if (reg) { reg 1429 drivers/usb/cdns3/gadget.c writel(reg, &priv_dev->regs->usb_ists); reg 1431 drivers/usb/cdns3/gadget.c cdns3_check_usb_interrupt_proceed(priv_dev, reg); reg 1435 drivers/usb/cdns3/gadget.c reg = readl(&priv_dev->regs->ep_ists); reg 1438 drivers/usb/cdns3/gadget.c if (reg & EP_ISTS_EP_OUT0) { reg 1444 drivers/usb/cdns3/gadget.c if (reg & EP_ISTS_EP_IN0) { reg 1450 drivers/usb/cdns3/gadget.c reg &= ~(EP_ISTS_EP_OUT0 | EP_ISTS_EP_IN0); reg 1451 drivers/usb/cdns3/gadget.c if (!reg) reg 1454 drivers/usb/cdns3/gadget.c for_each_set_bit(bit, (unsigned long *)®, reg 1775 drivers/usb/cdns3/gadget.c u32 reg = EP_STS_EN_TRBERREN; reg 1841 drivers/usb/cdns3/gadget.c cdns3_wa2_enable_detection(priv_dev, priv_ep, reg); reg 1843 drivers/usb/cdns3/gadget.c writel(reg, &priv_dev->regs->ep_sts_en); reg 1866 drivers/usb/cdns3/gadget.c reg = readl(&priv_dev->regs->ep_sts); reg 1867 drivers/usb/cdns3/gadget.c priv_ep->pcs = !!EP_STS_CCS(reg); reg 1868 drivers/usb/cdns3/gadget.c priv_ep->ccs = !!EP_STS_CCS(reg); reg 2303 drivers/usb/cdns3/gadget.c u32 reg; reg 2315 drivers/usb/cdns3/gadget.c reg = readl(®s->dbg_link1); reg 2317 drivers/usb/cdns3/gadget.c reg &= ~DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK; reg 2318 drivers/usb/cdns3/gadget.c reg |= DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(0x55) | reg 2320 drivers/usb/cdns3/gadget.c writel(reg, ®s->dbg_link1); reg 2328 drivers/usb/cdns3/gadget.c reg = readl(®s->dma_axi_ctrl); reg 2329 drivers/usb/cdns3/gadget.c reg |= DMA_AXI_CTRL_MARPROT(DMA_AXI_CTRL_NON_SECURE) | reg 2331 drivers/usb/cdns3/gadget.c writel(reg, ®s->dma_axi_ctrl); reg 2597 drivers/usb/cdns3/gadget.c u32 reg = readl(&priv_dev->regs->usb_cap2); reg 2599 drivers/usb/cdns3/gadget.c priv_dev->onchip_buffers = USB_CAP2_ACTUAL_MEM_SIZE(reg); reg 886 drivers/usb/cdns3/gadget.h #define EP_IS_IMPLEMENTED(reg, index) ((reg) & (1 << (index))) reg 889 drivers/usb/cdns3/gadget.h #define EP_SUPPORT_ISO(reg, index) ((reg) & (1 << (index))) reg 892 drivers/usb/cdns3/gadget.h #define EP_SUPPORT_STREAM(reg, index) ((reg) & (1 << (index))) reg 343 drivers/usb/chipidea/ci.h static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask) reg 345 drivers/usb/chipidea/ci.h return ioread32(ci->hw_bank.regmap[reg]) & mask; reg 375 drivers/usb/chipidea/ci.h static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg, reg 379 drivers/usb/chipidea/ci.h data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask) reg 382 drivers/usb/chipidea/ci.h __hw_write(ci, data, ci->hw_bank.regmap[reg]); reg 393 drivers/usb/chipidea/ci.h static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg, reg 396 drivers/usb/chipidea/ci.h u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask; reg 398 drivers/usb/chipidea/ci.h __hw_write(ci, val, ci->hw_bank.regmap[reg]); reg 411 drivers/usb/chipidea/ci.h static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg, reg 414 drivers/usb/chipidea/ci.h u32 val = hw_read(ci, reg, ~0); reg 416 drivers/usb/chipidea/ci.h hw_write(ci, reg, mask, data); reg 225 drivers/usb/chipidea/core.c enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC; reg 226 drivers/usb/chipidea/core.c bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm))); reg 229 drivers/usb/chipidea/core.c hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), reg 232 drivers/usb/chipidea/core.c hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), reg 238 drivers/usb/chipidea/core.c u32 reg; reg 248 drivers/usb/chipidea/core.c reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >> reg 250 drivers/usb/chipidea/core.c ci->hw_bank.lpm = reg; reg 251 drivers/usb/chipidea/core.c if (reg) reg 252 drivers/usb/chipidea/core.c hw_alloc_regmap(ci, !!reg); reg 257 drivers/usb/chipidea/core.c reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >> reg 259 drivers/usb/chipidea/core.c ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */ reg 314 drivers/usb/chipidea/host.c u32 __iomem *reg = &ehci->regs->port_status[port]; reg 315 drivers/usb/chipidea/host.c u32 portsc = ehci_readl(ehci, reg); reg 340 drivers/usb/chipidea/host.c tmp = ehci_readl(ehci, reg); reg 342 drivers/usb/chipidea/host.c ehci_writel(ehci, tmp, reg); reg 220 drivers/usb/chipidea/udc.c enum ci_hw_regs reg = OP_ENDPTCTRL + num; reg 225 drivers/usb/chipidea/udc.c hw_write(ci, reg, mask_xs|mask_xr, reg 264 drivers/usb/chipidea/udc.c u32 reg = hw_read_intr_status(ci) & hw_read_intr_enable(ci); reg 266 drivers/usb/chipidea/udc.c hw_write(ci, OP_USBSTS, ~0, reg); reg 267 drivers/usb/chipidea/udc.c return reg; reg 176 drivers/usb/chipidea/usbmisc_imx.c void __iomem *reg; reg 187 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX25_USB_PHY_CTRL_OFFSET; reg 188 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg); reg 195 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); reg 236 drivers/usb/chipidea/usbmisc_imx.c void __iomem *reg = NULL; reg 254 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX53_USB_OTG_PHY_CTRL_0_OFFSET; reg 255 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | MX53_BM_OVER_CUR_DIS_OTG; reg 256 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); reg 261 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX53_USB_OTG_PHY_CTRL_0_OFFSET; reg 262 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | MX53_BM_OVER_CUR_DIS_H1; reg 263 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); reg 269 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX53_USB_CTRL_1_OFFSET; reg 270 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | MX53_USB_CTRL_1_UH2_ULPI_EN; reg 274 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); reg 276 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX53_USB_UH2_CTRL_OFFSET; reg 277 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | MX53_USB_UHx_CTRL_WAKE_UP_EN reg 279 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); reg 282 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + reg 284 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | reg 286 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); reg 291 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX53_USB_UH2_CTRL_OFFSET; reg 292 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | MX53_BM_OVER_CUR_DIS_UHx; reg 293 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); reg 299 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX53_USB_CTRL_1_OFFSET; reg 300 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | MX53_USB_CTRL_1_UH3_ULPI_EN; reg 304 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); reg 306 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX53_USB_UH3_CTRL_OFFSET; reg 307 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | MX53_USB_UHx_CTRL_WAKE_UP_EN reg 309 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); reg 313 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + reg 315 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | reg 317 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); reg 321 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX53_USB_UH3_CTRL_OFFSET; reg 322 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg) | MX53_BM_OVER_CUR_DIS_UHx; reg 323 drivers/usb/chipidea/usbmisc_imx.c writel(val, reg); reg 365 drivers/usb/chipidea/usbmisc_imx.c u32 reg; reg 372 drivers/usb/chipidea/usbmisc_imx.c reg = readl(usbmisc->base + data->index * 4); reg 374 drivers/usb/chipidea/usbmisc_imx.c reg |= MX6_BM_OVER_CUR_DIS; reg 376 drivers/usb/chipidea/usbmisc_imx.c reg &= ~MX6_BM_OVER_CUR_DIS; reg 383 drivers/usb/chipidea/usbmisc_imx.c reg |= MX6_BM_OVER_CUR_POLARITY; reg 385 drivers/usb/chipidea/usbmisc_imx.c reg &= ~MX6_BM_OVER_CUR_POLARITY; reg 389 drivers/usb/chipidea/usbmisc_imx.c reg |= MX6_BM_PWR_POLARITY; reg 390 drivers/usb/chipidea/usbmisc_imx.c writel(reg, usbmisc->base + data->index * 4); reg 393 drivers/usb/chipidea/usbmisc_imx.c reg = readl(usbmisc->base + data->index * 4); reg 394 drivers/usb/chipidea/usbmisc_imx.c writel(reg | MX6_BM_NON_BURST_SETTING, reg 399 drivers/usb/chipidea/usbmisc_imx.c reg = readl(usbmisc->base + data->index * 4); reg 400 drivers/usb/chipidea/usbmisc_imx.c writel(reg | MX6_BM_UTMI_ON_CLOCK, reg 402 drivers/usb/chipidea/usbmisc_imx.c reg = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET reg 404 drivers/usb/chipidea/usbmisc_imx.c reg |= MX6_BM_HSIC_EN | MX6_BM_HSIC_CLK_ON; reg 405 drivers/usb/chipidea/usbmisc_imx.c writel(reg, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET reg 491 drivers/usb/chipidea/usbmisc_imx.c void __iomem *reg = NULL; reg 499 drivers/usb/chipidea/usbmisc_imx.c reg = usbmisc->base + MX6_USB_OTG1_PHY_CTRL + data->index * 4; reg 502 drivers/usb/chipidea/usbmisc_imx.c val = readl(reg); reg 503 drivers/usb/chipidea/usbmisc_imx.c writel(val | MX6SX_USB_VBUS_WAKEUP_SOURCE_BVALID, reg); reg 527 drivers/usb/chipidea/usbmisc_imx.c u32 reg; reg 537 drivers/usb/chipidea/usbmisc_imx.c reg = readl(usbmisc->base); reg 538 drivers/usb/chipidea/usbmisc_imx.c writel(reg | VF610_OVER_CUR_DIS, usbmisc->base); reg 571 drivers/usb/chipidea/usbmisc_imx.c u32 reg; reg 577 drivers/usb/chipidea/usbmisc_imx.c reg = readl(usbmisc->base); reg 579 drivers/usb/chipidea/usbmisc_imx.c reg |= MX6_BM_OVER_CUR_DIS; reg 581 drivers/usb/chipidea/usbmisc_imx.c reg &= ~MX6_BM_OVER_CUR_DIS; reg 588 drivers/usb/chipidea/usbmisc_imx.c reg |= MX6_BM_OVER_CUR_POLARITY; reg 590 drivers/usb/chipidea/usbmisc_imx.c reg &= ~MX6_BM_OVER_CUR_POLARITY; reg 594 drivers/usb/chipidea/usbmisc_imx.c reg |= MX6_BM_PWR_POLARITY; reg 595 drivers/usb/chipidea/usbmisc_imx.c writel(reg, usbmisc->base); reg 597 drivers/usb/chipidea/usbmisc_imx.c reg = readl(usbmisc->base + MX7D_USBNC_USB_CTRL2); reg 598 drivers/usb/chipidea/usbmisc_imx.c reg &= ~MX7D_USB_VBUS_WAKEUP_SOURCE_MASK; reg 599 drivers/usb/chipidea/usbmisc_imx.c writel(reg | MX7D_USB_VBUS_WAKEUP_SOURCE_BVALID, reg 28 drivers/usb/core/of.c u32 reg; reg 31 drivers/usb/core/of.c if (of_property_read_u32(node, "reg", ®)) reg 34 drivers/usb/core/of.c if (reg == port1) reg 95 drivers/usb/core/of.c u32 reg[2]; reg 98 drivers/usb/core/of.c if (of_property_read_u32_array(node, "reg", reg, 2)) reg 101 drivers/usb/core/of.c if (reg[0] == ifnum && reg[1] == config) reg 1333 drivers/usb/dwc2/core.h int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, reg 1335 drivers/usb/dwc2/core.h int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, reg 1860 drivers/usb/dwc2/gadget.c u32 reg; reg 1864 drivers/usb/dwc2/gadget.c reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0; reg 1871 drivers/usb/dwc2/gadget.c ctrl = dwc2_readl(hsotg, reg); reg 1874 drivers/usb/dwc2/gadget.c dwc2_writel(hsotg, ctrl, reg); reg 1878 drivers/usb/dwc2/gadget.c ctrl, reg, dwc2_readl(hsotg, reg)); reg 2558 drivers/usb/dwc2/gadget.c u32 reg; reg 2583 drivers/usb/dwc2/gadget.c reg = dwc2_readl(hsotg, DIEPCTL(ep)); reg 2584 drivers/usb/dwc2/gadget.c reg &= ~DXEPCTL_MPS_MASK; reg 2585 drivers/usb/dwc2/gadget.c reg |= mps; reg 2586 drivers/usb/dwc2/gadget.c dwc2_writel(hsotg, reg, DIEPCTL(ep)); reg 2588 drivers/usb/dwc2/gadget.c reg = dwc2_readl(hsotg, DOEPCTL(ep)); reg 2589 drivers/usb/dwc2/gadget.c reg &= ~DXEPCTL_MPS_MASK; reg 2590 drivers/usb/dwc2/gadget.c reg |= mps; reg 2591 drivers/usb/dwc2/gadget.c dwc2_writel(hsotg, reg, DOEPCTL(ep)); reg 105 drivers/usb/dwc3/core.c u32 reg; reg 107 drivers/usb/dwc3/core.c reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg 108 drivers/usb/dwc3/core.c reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); reg 109 drivers/usb/dwc3/core.c reg |= DWC3_GCTL_PRTCAPDIR(mode); reg 110 drivers/usb/dwc3/core.c dwc3_writel(dwc->regs, DWC3_GCTL, reg); reg 209 drivers/usb/dwc3/core.c u32 reg; reg 215 drivers/usb/dwc3/core.c reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); reg 217 drivers/usb/dwc3/core.c return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); reg 226 drivers/usb/dwc3/core.c u32 reg; reg 250 drivers/usb/dwc3/core.c reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg 251 drivers/usb/dwc3/core.c reg |= DWC3_DCTL_CSFTRST; reg 252 drivers/usb/dwc3/core.c dwc3_writel(dwc->regs, DWC3_DCTL, reg); reg 264 drivers/usb/dwc3/core.c reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg 265 drivers/usb/dwc3/core.c if (!(reg & DWC3_DCTL_CSFTRST)) reg 304 drivers/usb/dwc3/core.c u32 reg; reg 313 drivers/usb/dwc3/core.c reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); reg 314 drivers/usb/dwc3/core.c dft = reg & DWC3_GFLADJ_30MHZ_MASK; reg 316 drivers/usb/dwc3/core.c reg &= ~DWC3_GFLADJ_30MHZ_MASK; reg 317 drivers/usb/dwc3/core.c reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; reg 318 drivers/usb/dwc3/core.c dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); reg 569 drivers/usb/dwc3/core.c u32 reg; reg 571 drivers/usb/dwc3/core.c reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); reg 577 drivers/usb/dwc3/core.c reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; reg 586 drivers/usb/dwc3/core.c reg |= DWC3_GUSB3PIPECTL_SUSPHY; reg 589 drivers/usb/dwc3/core.c reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; reg 592 drivers/usb/dwc3/core.c reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; reg 595 drivers/usb/dwc3/core.c reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; reg 598 drivers/usb/dwc3/core.c reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; reg 601 drivers/usb/dwc3/core.c reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; reg 604 drivers/usb/dwc3/core.c reg |= DWC3_GUSB3PIPECTL_LFPSFILT; reg 607 drivers/usb/dwc3/core.c reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; reg 610 drivers/usb/dwc3/core.c reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); reg 613 drivers/usb/dwc3/core.c reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; reg 616 drivers/usb/dwc3/core.c reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; reg 618 drivers/usb/dwc3/core.c dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); reg 620 drivers/usb/dwc3/core.c reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); reg 627 drivers/usb/dwc3/core.c reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; reg 631 drivers/usb/dwc3/core.c reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; reg 632 drivers/usb/dwc3/core.c dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); reg 635 drivers/usb/dwc3/core.c if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) reg 647 drivers/usb/dwc3/core.c reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | reg 649 drivers/usb/dwc3/core.c reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | reg 653 drivers/usb/dwc3/core.c reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | reg 655 drivers/usb/dwc3/core.c reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | reg 669 drivers/usb/dwc3/core.c reg |= DWC3_GUSB2PHYCFG_SUSPHY; reg 672 drivers/usb/dwc3/core.c reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; reg 675 drivers/usb/dwc3/core.c reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; reg 677 drivers/usb/dwc3/core.c reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; reg 680 drivers/usb/dwc3/core.c reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; reg 682 drivers/usb/dwc3/core.c dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); reg 706 drivers/usb/dwc3/core.c u32 reg; reg 708 drivers/usb/dwc3/core.c reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); reg 711 drivers/usb/dwc3/core.c if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { reg 713 drivers/usb/dwc3/core.c dwc->revision = reg; reg 714 drivers/usb/dwc3/core.c } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { reg 729 drivers/usb/dwc3/core.c u32 reg; reg 731 drivers/usb/dwc3/core.c reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg 732 drivers/usb/dwc3/core.c reg &= ~DWC3_GCTL_SCALEDOWN_MASK; reg 752 drivers/usb/dwc3/core.c reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; reg 754 drivers/usb/dwc3/core.c reg &= ~DWC3_GCTL_DSBLCLKGTNG; reg 764 drivers/usb/dwc3/core.c reg |= DWC3_GCTL_GBLHIBERNATIONEN; reg 781 drivers/usb/dwc3/core.c reg |= DWC3_GCTL_DISSCRAMBLE; reg 783 drivers/usb/dwc3/core.c reg &= ~DWC3_GCTL_DISSCRAMBLE; reg 786 drivers/usb/dwc3/core.c reg |= DWC3_GCTL_U2EXIT_LFPS; reg 795 drivers/usb/dwc3/core.c reg |= DWC3_GCTL_U2RSTECN; reg 797 drivers/usb/dwc3/core.c dwc3_writel(dwc->regs, DWC3_GCTL, reg); reg 905 drivers/usb/dwc3/core.c u32 reg; reg 977 drivers/usb/dwc3/core.c reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); reg 978 drivers/usb/dwc3/core.c reg |= DWC3_GUCTL2_RST_ACTBITLATER; reg 979 drivers/usb/dwc3/core.c dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); reg 983 drivers/usb/dwc3/core.c reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); reg 990 drivers/usb/dwc3/core.c reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; reg 993 drivers/usb/dwc3/core.c reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; reg 996 drivers/usb/dwc3/core.c reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; reg 998 drivers/usb/dwc3/core.c dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); reg 1003 drivers/usb/dwc3/core.c reg = dwc3_readl(dwc->regs, DWC3_GUCTL); reg 1012 drivers/usb/dwc3/core.c reg |= DWC3_GUCTL_HSTINAUTORETRY; reg 1014 drivers/usb/dwc3/core.c dwc3_writel(dwc->regs, DWC3_GUCTL, reg); reg 1028 drivers/usb/dwc3/core.c reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); reg 1029 drivers/usb/dwc3/core.c reg |= DWC31_RXTHRNUMPKTSEL_PRD; reg 1031 drivers/usb/dwc3/core.c reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); reg 1032 drivers/usb/dwc3/core.c reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); reg 1034 drivers/usb/dwc3/core.c reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); reg 1035 drivers/usb/dwc3/core.c reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); reg 1037 drivers/usb/dwc3/core.c dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); reg 1041 drivers/usb/dwc3/core.c reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); reg 1042 drivers/usb/dwc3/core.c reg |= DWC31_TXTHRNUMPKTSEL_PRD; reg 1044 drivers/usb/dwc3/core.c reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); reg 1045 drivers/usb/dwc3/core.c reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); reg 1047 drivers/usb/dwc3/core.c reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); reg 1048 drivers/usb/dwc3/core.c reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); reg 1050 drivers/usb/dwc3/core.c dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); reg 1604 drivers/usb/dwc3/core.c u32 reg; reg 1623 drivers/usb/dwc3/core.c reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); reg 1624 drivers/usb/dwc3/core.c reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | reg 1626 drivers/usb/dwc3/core.c dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); reg 1662 drivers/usb/dwc3/core.c u32 reg; reg 1684 drivers/usb/dwc3/core.c reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); reg 1686 drivers/usb/dwc3/core.c reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; reg 1689 drivers/usb/dwc3/core.c reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; reg 1691 drivers/usb/dwc3/core.c dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); reg 285 drivers/usb/dwc3/debugfs.c u32 reg; reg 296 drivers/usb/dwc3/debugfs.c reg = DWC3_GDBGLSPMUX_HOSTSELECT(sel); reg 298 drivers/usb/dwc3/debugfs.c dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg); reg 303 drivers/usb/dwc3/debugfs.c reg |= DWC3_GDBGLSPMUX_ENDBC; reg 304 drivers/usb/dwc3/debugfs.c dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg); reg 314 drivers/usb/dwc3/debugfs.c u32 reg; reg 317 drivers/usb/dwc3/debugfs.c reg = DWC3_GDBGLSPMUX_DEVSELECT(i); reg 318 drivers/usb/dwc3/debugfs.c dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg); reg 319 drivers/usb/dwc3/debugfs.c reg = dwc3_readl(dwc->regs, DWC3_GDBGLSP); reg 320 drivers/usb/dwc3/debugfs.c seq_printf(s, "GDBGLSP[%d] = 0x%08x\n", i, reg); reg 329 drivers/usb/dwc3/debugfs.c u32 reg; reg 332 drivers/usb/dwc3/debugfs.c reg = dwc3_readl(dwc->regs, DWC3_GSTS); reg 333 drivers/usb/dwc3/debugfs.c current_mode = DWC3_GSTS_CURMOD(reg); reg 392 drivers/usb/dwc3/debugfs.c u32 reg; reg 395 drivers/usb/dwc3/debugfs.c reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg 398 drivers/usb/dwc3/debugfs.c switch (DWC3_GCTL_PRTCAP(reg)) { reg 409 drivers/usb/dwc3/debugfs.c seq_printf(s, "UNKNOWN %08x\n", DWC3_GCTL_PRTCAP(reg)); reg 457 drivers/usb/dwc3/debugfs.c u32 reg; reg 460 drivers/usb/dwc3/debugfs.c reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg 461 drivers/usb/dwc3/debugfs.c reg &= DWC3_DCTL_TSTCTRL_MASK; reg 462 drivers/usb/dwc3/debugfs.c reg >>= 1; reg 465 drivers/usb/dwc3/debugfs.c switch (reg) { reg 485 drivers/usb/dwc3/debugfs.c seq_printf(s, "UNKNOWN %d\n", reg); reg 541 drivers/usb/dwc3/debugfs.c u32 reg; reg 545 drivers/usb/dwc3/debugfs.c reg = dwc3_readl(dwc->regs, DWC3_GSTS); reg 546 drivers/usb/dwc3/debugfs.c if (DWC3_GSTS_CURMOD(reg) != DWC3_GSTS_CURMOD_DEVICE) { reg 552 drivers/usb/dwc3/debugfs.c reg = dwc3_readl(dwc->regs, DWC3_DSTS); reg 553 drivers/usb/dwc3/debugfs.c state = DWC3_DSTS_USBLNKST(reg); reg 554 drivers/usb/dwc3/debugfs.c speed = reg & DWC3_DSTS_CONNECTSPD; reg 577 drivers/usb/dwc3/debugfs.c u32 reg; reg 599 drivers/usb/dwc3/debugfs.c reg = dwc3_readl(dwc->regs, DWC3_GSTS); reg 600 drivers/usb/dwc3/debugfs.c if (DWC3_GSTS_CURMOD(reg) != DWC3_GSTS_CURMOD_DEVICE) { reg 605 drivers/usb/dwc3/debugfs.c reg = dwc3_readl(dwc->regs, DWC3_DSTS); reg 606 drivers/usb/dwc3/debugfs.c speed = reg & DWC3_DSTS_CONNECTSPD; reg 828 drivers/usb/dwc3/debugfs.c u32 reg; reg 831 drivers/usb/dwc3/debugfs.c reg = DWC3_GDBGLSPMUX_EPSELECT(dep->number); reg 832 drivers/usb/dwc3/debugfs.c dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg); reg 21 drivers/usb/dwc3/drd.c u32 reg = dwc3_readl(dwc->regs, DWC3_OEVTEN); reg 23 drivers/usb/dwc3/drd.c reg &= ~(disable_mask); reg 24 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); reg 29 drivers/usb/dwc3/drd.c u32 reg = dwc3_readl(dwc->regs, DWC3_OEVTEN); reg 31 drivers/usb/dwc3/drd.c reg |= (enable_mask); reg 32 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); reg 37 drivers/usb/dwc3/drd.c u32 reg = dwc3_readl(dwc->regs, DWC3_OEVT); reg 39 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); reg 71 drivers/usb/dwc3/drd.c u32 reg; reg 75 drivers/usb/dwc3/drd.c reg = dwc3_readl(dwc->regs, DWC3_OEVT); reg 76 drivers/usb/dwc3/drd.c if (reg) { reg 78 drivers/usb/dwc3/drd.c if (!(reg & DWC3_OTG_ALL_EVENTS)) { reg 79 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_OEVT, reg); reg 84 drivers/usb/dwc3/drd.c !(reg & DWC3_OEVT_DEVICEMODE)) reg 86 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_OEVT, reg); reg 95 drivers/usb/dwc3/drd.c u32 reg; reg 103 drivers/usb/dwc3/drd.c reg = dwc3_readl(dwc->regs, DWC3_OCFG); reg 104 drivers/usb/dwc3/drd.c reg |= DWC3_OCFG_SFTRSTMASK; reg 105 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_OCFG, reg); reg 108 drivers/usb/dwc3/drd.c reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg 109 drivers/usb/dwc3/drd.c reg &= ~DWC3_GCTL_GBLHIBERNATIONEN; reg 110 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_GCTL, reg); reg 117 drivers/usb/dwc3/drd.c reg = dwc3_readl(dwc->regs, DWC3_OCFG); reg 118 drivers/usb/dwc3/drd.c reg &= ~(DWC3_OCFG_SRPCAP | DWC3_OCFG_HNPCAP); reg 119 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_OCFG, reg); reg 130 drivers/usb/dwc3/drd.c reg = dwc3_readl(dwc->regs, DWC3_OCTL); reg 131 drivers/usb/dwc3/drd.c reg |= DWC3_OCTL_PERIMODE; reg 132 drivers/usb/dwc3/drd.c reg &= ~(DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HSTSETHNPEN | reg 134 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_OCTL, reg); reg 169 drivers/usb/dwc3/drd.c u32 reg; reg 178 drivers/usb/dwc3/drd.c reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); reg 179 drivers/usb/dwc3/drd.c reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; reg 180 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); reg 197 drivers/usb/dwc3/drd.c u32 reg; reg 206 drivers/usb/dwc3/drd.c reg = dwc3_readl(dwc->regs, DWC3_OCTL); reg 207 drivers/usb/dwc3/drd.c reg &= ~(DWC3_OCTL_PERIMODE | DWC3_OCTL_TERMSELIDPULSE | reg 209 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_OCTL, reg); reg 214 drivers/usb/dwc3/drd.c reg = dwc3_readl(dwc->regs, DWC3_OCFG); reg 215 drivers/usb/dwc3/drd.c reg &= ~DWC3_OCFG_DISPWRCUTTOFF; reg 216 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_OCFG, reg); reg 232 drivers/usb/dwc3/drd.c reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); reg 233 drivers/usb/dwc3/drd.c reg |= DWC3_GUSB2PHYCFG_SUSPHY; reg 234 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); reg 238 drivers/usb/dwc3/drd.c reg = dwc3_readl(dwc->regs, DWC3_OCTL); reg 239 drivers/usb/dwc3/drd.c reg |= DWC3_OCTL_PRTPWRCTL; reg 240 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_OCTL, reg); reg 246 drivers/usb/dwc3/drd.c u32 reg; reg 261 drivers/usb/dwc3/drd.c reg = dwc3_readl(dwc->regs, DWC3_OCTL); reg 262 drivers/usb/dwc3/drd.c reg &= ~(DWC3_OCTL_HSTSETHNPEN | DWC3_OCTL_PRTPWRCTL); reg 263 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_OCTL, reg); reg 269 drivers/usb/dwc3/drd.c u32 reg; reg 277 drivers/usb/dwc3/drd.c reg = dwc3_readl(dwc->regs, DWC3_OCFG); reg 279 drivers/usb/dwc3/drd.c reg |= DWC3_OCFG_SFTRSTMASK; reg 280 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_OCFG, reg); reg 286 drivers/usb/dwc3/drd.c reg = dwc3_readl(dwc->regs, DWC3_OCTL); reg 287 drivers/usb/dwc3/drd.c reg |= DWC3_OCTL_PERIMODE; reg 288 drivers/usb/dwc3/drd.c reg &= ~(DWC3_OCTL_TERMSELIDPULSE | DWC3_OCTL_HNPREQ | reg 290 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_OCTL, reg); reg 295 drivers/usb/dwc3/drd.c reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); reg 296 drivers/usb/dwc3/drd.c reg |= DWC3_GUSB2PHYCFG_SUSPHY; reg 297 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); reg 305 drivers/usb/dwc3/drd.c u32 reg; reg 322 drivers/usb/dwc3/drd.c reg = dwc3_readl(dwc->regs, DWC3_OCTL); reg 323 drivers/usb/dwc3/drd.c reg &= ~(DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HNPREQ); reg 324 drivers/usb/dwc3/drd.c reg |= DWC3_OCTL_PERIMODE; reg 325 drivers/usb/dwc3/drd.c dwc3_writel(dwc->regs, DWC3_OCTL, reg); reg 331 drivers/usb/dwc3/drd.c u32 reg; reg 343 drivers/usb/dwc3/drd.c reg = dwc3_readl(dwc->regs, DWC3_OSTS); reg 344 drivers/usb/dwc3/drd.c id = !!(reg & DWC3_OSTS_CONIDSTS); reg 283 drivers/usb/dwc3/dwc3-meson-g12a.c u32 reg; reg 285 drivers/usb/dwc3/dwc3-meson-g12a.c regmap_read(priv->regmap, USB_R5, ®); reg 287 drivers/usb/dwc3/dwc3-meson-g12a.c if (reg & (USB_R5_ID_DIG_SYNC | USB_R5_ID_DIG_REG)) reg 285 drivers/usb/dwc3/dwc3-omap.c u32 reg; reg 288 drivers/usb/dwc3/dwc3-omap.c reg = dwc3_omap_read_irqmisc_status(omap); reg 289 drivers/usb/dwc3/dwc3-omap.c dwc3_omap_write_irqmisc_status(omap, reg); reg 291 drivers/usb/dwc3/dwc3-omap.c reg = dwc3_omap_read_irq0_status(omap); reg 292 drivers/usb/dwc3/dwc3-omap.c dwc3_omap_write_irq0_status(omap, reg); reg 302 drivers/usb/dwc3/dwc3-omap.c u32 reg; reg 305 drivers/usb/dwc3/dwc3-omap.c reg = USBOTGSS_IRQO_COREIRQ_ST; reg 306 drivers/usb/dwc3/dwc3-omap.c dwc3_omap_write_irq0_set(omap, reg); reg 308 drivers/usb/dwc3/dwc3-omap.c reg = (USBOTGSS_IRQMISC_OEVT | reg 318 drivers/usb/dwc3/dwc3-omap.c dwc3_omap_write_irqmisc_set(omap, reg); reg 323 drivers/usb/dwc3/dwc3-omap.c u32 reg; reg 326 drivers/usb/dwc3/dwc3-omap.c reg = USBOTGSS_IRQO_COREIRQ_ST; reg 327 drivers/usb/dwc3/dwc3-omap.c dwc3_omap_write_irq0_clr(omap, reg); reg 329 drivers/usb/dwc3/dwc3-omap.c reg = (USBOTGSS_IRQMISC_OEVT | reg 339 drivers/usb/dwc3/dwc3-omap.c dwc3_omap_write_irqmisc_clr(omap, reg); reg 391 drivers/usb/dwc3/dwc3-omap.c u32 reg; reg 395 drivers/usb/dwc3/dwc3-omap.c reg = dwc3_omap_read_utmi_ctrl(omap); reg 401 drivers/usb/dwc3/dwc3-omap.c reg |= USBOTGSS_UTMI_OTG_CTRL_SW_MODE; reg 404 drivers/usb/dwc3/dwc3-omap.c reg &= ~USBOTGSS_UTMI_OTG_CTRL_SW_MODE; reg 410 drivers/usb/dwc3/dwc3-omap.c dwc3_omap_write_utmi_ctrl(omap, reg); reg 460 drivers/usb/dwc3/dwc3-omap.c u32 reg; reg 507 drivers/usb/dwc3/dwc3-omap.c reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); reg 89 drivers/usb/dwc3/dwc3-pci.c void __iomem *reg; reg 92 drivers/usb/dwc3/dwc3-pci.c reg = pcim_iomap(pci, GP_RWBAR, 0); reg 93 drivers/usb/dwc3/dwc3-pci.c if (!reg) reg 96 drivers/usb/dwc3/dwc3-pci.c value = readl(reg + GP_RWREG1); reg 101 drivers/usb/dwc3/dwc3-pci.c writel(value, reg + GP_RWREG1); reg 105 drivers/usb/dwc3/dwc3-pci.c pcim_iounmap(pci, reg); reg 83 drivers/usb/dwc3/dwc3-qcom.c u32 reg; reg 85 drivers/usb/dwc3/dwc3-qcom.c reg = readl(base + offset); reg 86 drivers/usb/dwc3/dwc3-qcom.c reg |= val; reg 87 drivers/usb/dwc3/dwc3-qcom.c writel(reg, base + offset); reg 95 drivers/usb/dwc3/dwc3-qcom.c u32 reg; reg 97 drivers/usb/dwc3/dwc3-qcom.c reg = readl(base + offset); reg 98 drivers/usb/dwc3/dwc3-qcom.c reg &= ~val; reg 99 drivers/usb/dwc3/dwc3-qcom.c writel(reg, base + offset); reg 175 drivers/usb/dwc3/dwc3-st.c u32 reg = st_dwc3_readl(dwc3_data->glue_base, CLKRST_CTRL); reg 177 drivers/usb/dwc3/dwc3-st.c reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION; reg 178 drivers/usb/dwc3/dwc3-st.c reg &= ~SW_PIPEW_RESET_N; reg 179 drivers/usb/dwc3/dwc3-st.c st_dwc3_writel(dwc3_data->glue_base, CLKRST_CTRL, reg); reg 182 drivers/usb/dwc3/dwc3-st.c reg = st_dwc3_readl(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1); reg 184 drivers/usb/dwc3/dwc3-st.c reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) | reg 188 drivers/usb/dwc3/dwc3-st.c st_dwc3_writel(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1, reg); reg 190 drivers/usb/dwc3/dwc3-st.c reg = st_dwc3_readl(dwc3_data->glue_base, CLKRST_CTRL); reg 191 drivers/usb/dwc3/dwc3-st.c reg |= SW_PIPEW_RESET_N; reg 192 drivers/usb/dwc3/dwc3-st.c st_dwc3_writel(dwc3_data->glue_base, CLKRST_CTRL, reg); reg 313 drivers/usb/dwc3/ep0.c u32 reg; reg 332 drivers/usb/dwc3/ep0.c reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg 333 drivers/usb/dwc3/ep0.c if (reg & DWC3_DCTL_INITU1ENA) reg 335 drivers/usb/dwc3/ep0.c if (reg & DWC3_DCTL_INITU2ENA) reg 375 drivers/usb/dwc3/ep0.c u32 reg; reg 385 drivers/usb/dwc3/ep0.c reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg 387 drivers/usb/dwc3/ep0.c reg |= DWC3_DCTL_INITU1ENA; reg 389 drivers/usb/dwc3/ep0.c reg &= ~DWC3_DCTL_INITU1ENA; reg 390 drivers/usb/dwc3/ep0.c dwc3_writel(dwc->regs, DWC3_DCTL, reg); reg 398 drivers/usb/dwc3/ep0.c u32 reg; reg 409 drivers/usb/dwc3/ep0.c reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg 411 drivers/usb/dwc3/ep0.c reg |= DWC3_DCTL_INITU2ENA; reg 413 drivers/usb/dwc3/ep0.c reg &= ~DWC3_DCTL_INITU2ENA; reg 414 drivers/usb/dwc3/ep0.c dwc3_writel(dwc->regs, DWC3_DCTL, reg); reg 564 drivers/usb/dwc3/ep0.c u32 reg; reg 577 drivers/usb/dwc3/ep0.c reg = dwc3_readl(dwc->regs, DWC3_DCFG); reg 578 drivers/usb/dwc3/ep0.c reg &= ~(DWC3_DCFG_DEVADDR_MASK); reg 579 drivers/usb/dwc3/ep0.c reg |= DWC3_DCFG_DEVADDR(addr); reg 580 drivers/usb/dwc3/ep0.c dwc3_writel(dwc->regs, DWC3_DCFG, reg); reg 605 drivers/usb/dwc3/ep0.c u32 reg; reg 632 drivers/usb/dwc3/ep0.c reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg 634 drivers/usb/dwc3/ep0.c reg |= DWC3_DCTL_ACCEPTU1ENA; reg 636 drivers/usb/dwc3/ep0.c reg |= DWC3_DCTL_ACCEPTU2ENA; reg 637 drivers/usb/dwc3/ep0.c dwc3_writel(dwc->regs, DWC3_DCTL, reg); reg 659 drivers/usb/dwc3/ep0.c u32 reg; reg 677 drivers/usb/dwc3/ep0.c reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg 678 drivers/usb/dwc3/ep0.c if (reg & DWC3_DCTL_INITU2ENA) reg 680 drivers/usb/dwc3/ep0.c if (reg & DWC3_DCTL_INITU1ENA) reg 43 drivers/usb/dwc3/gadget.c u32 reg; reg 45 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg 46 drivers/usb/dwc3/gadget.c reg &= ~DWC3_DCTL_TSTCTRL_MASK; reg 54 drivers/usb/dwc3/gadget.c reg |= mode << 1; reg 60 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_DCTL, reg); reg 74 drivers/usb/dwc3/gadget.c u32 reg; reg 76 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DSTS); reg 78 drivers/usb/dwc3/gadget.c return DWC3_DSTS_USBLNKST(reg); reg 92 drivers/usb/dwc3/gadget.c u32 reg; reg 100 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DSTS); reg 101 drivers/usb/dwc3/gadget.c if (reg & DWC3_DSTS_DCNRD) reg 111 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg 112 drivers/usb/dwc3/gadget.c reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; reg 115 drivers/usb/dwc3/gadget.c reg |= DWC3_DCTL_ULSTCHNGREQ(state); reg 116 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_DCTL, reg); reg 128 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DSTS); reg 130 drivers/usb/dwc3/gadget.c if (DWC3_DSTS_USBLNKST(reg) == state) reg 232 drivers/usb/dwc3/gadget.c u32 reg; reg 238 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DGCMD); reg 239 drivers/usb/dwc3/gadget.c if (!(reg & DWC3_DGCMD_CMDACT)) { reg 240 drivers/usb/dwc3/gadget.c status = DWC3_DGCMD_STATUS(reg); reg 275 drivers/usb/dwc3/gadget.c u32 reg; reg 291 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); reg 292 drivers/usb/dwc3/gadget.c if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) { reg 294 drivers/usb/dwc3/gadget.c reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; reg 297 drivers/usb/dwc3/gadget.c if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) { reg 299 drivers/usb/dwc3/gadget.c reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; reg 303 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); reg 347 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dep->regs, DWC3_DEPCMD); reg 348 drivers/usb/dwc3/gadget.c if (!(reg & DWC3_DEPCMD_CMDACT)) { reg 349 drivers/usb/dwc3/gadget.c cmd_status = DWC3_DEPCMD_STATUS(reg); reg 393 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); reg 394 drivers/usb/dwc3/gadget.c reg |= saved_config; reg 395 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); reg 616 drivers/usb/dwc3/gadget.c u32 reg; reg 636 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); reg 637 drivers/usb/dwc3/gadget.c reg |= DWC3_DALEPENA_EP(dep->number); reg 638 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); reg 731 drivers/usb/dwc3/gadget.c u32 reg; reg 741 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); reg 742 drivers/usb/dwc3/gadget.c reg &= ~DWC3_DALEPENA_EP(dep->number); reg 743 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); reg 1275 drivers/usb/dwc3/gadget.c u32 reg; reg 1277 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DSTS); reg 1278 drivers/usb/dwc3/gadget.c return DWC3_DSTS_SOFFN(reg); reg 1725 drivers/usb/dwc3/gadget.c u32 reg; reg 1735 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DSTS); reg 1737 drivers/usb/dwc3/gadget.c link_state = DWC3_DSTS_USBLNKST(reg); reg 1758 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg 1759 drivers/usb/dwc3/gadget.c reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; reg 1760 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_DCTL, reg); reg 1767 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DSTS); reg 1770 drivers/usb/dwc3/gadget.c if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) reg 1774 drivers/usb/dwc3/gadget.c if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { reg 1810 drivers/usb/dwc3/gadget.c u32 reg; reg 1816 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg 1819 drivers/usb/dwc3/gadget.c reg &= ~DWC3_DCTL_TRGTULST_MASK; reg 1820 drivers/usb/dwc3/gadget.c reg |= DWC3_DCTL_TRGTULST_RX_DET; reg 1824 drivers/usb/dwc3/gadget.c reg &= ~DWC3_DCTL_KEEP_CONNECT; reg 1825 drivers/usb/dwc3/gadget.c reg |= DWC3_DCTL_RUN_STOP; reg 1828 drivers/usb/dwc3/gadget.c reg |= DWC3_DCTL_KEEP_CONNECT; reg 1832 drivers/usb/dwc3/gadget.c reg &= ~DWC3_DCTL_RUN_STOP; reg 1835 drivers/usb/dwc3/gadget.c reg &= ~DWC3_DCTL_KEEP_CONNECT; reg 1840 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_DCTL, reg); reg 1843 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DSTS); reg 1844 drivers/usb/dwc3/gadget.c reg &= DWC3_DSTS_DEVCTRLHLT; reg 1845 drivers/usb/dwc3/gadget.c } while (--timeout && !(!is_on ^ !reg)); reg 1885 drivers/usb/dwc3/gadget.c u32 reg; reg 1888 drivers/usb/dwc3/gadget.c reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | reg 1898 drivers/usb/dwc3/gadget.c reg |= DWC3_DEVTEN_ULSTCNGEN; reg 1900 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); reg 1938 drivers/usb/dwc3/gadget.c u32 reg; reg 1947 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DCFG); reg 1948 drivers/usb/dwc3/gadget.c reg &= ~DWC3_DCFG_NUMP_MASK; reg 1949 drivers/usb/dwc3/gadget.c reg |= nump << DWC3_DCFG_NUMP_SHIFT; reg 1950 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_DCFG, reg); reg 1957 drivers/usb/dwc3/gadget.c u32 reg; reg 1977 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); reg 1979 drivers/usb/dwc3/gadget.c reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL; reg 1981 drivers/usb/dwc3/gadget.c reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL; reg 1983 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); reg 2135 drivers/usb/dwc3/gadget.c u32 reg; reg 2138 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DCFG); reg 2139 drivers/usb/dwc3/gadget.c reg &= ~(DWC3_DCFG_SPEED_MASK); reg 2156 drivers/usb/dwc3/gadget.c reg |= DWC3_DCFG_SUPERSPEED; reg 2160 drivers/usb/dwc3/gadget.c reg |= DWC3_DCFG_LOWSPEED; reg 2163 drivers/usb/dwc3/gadget.c reg |= DWC3_DCFG_FULLSPEED; reg 2166 drivers/usb/dwc3/gadget.c reg |= DWC3_DCFG_HIGHSPEED; reg 2169 drivers/usb/dwc3/gadget.c reg |= DWC3_DCFG_SUPERSPEED; reg 2173 drivers/usb/dwc3/gadget.c reg |= DWC3_DCFG_SUPERSPEED_PLUS; reg 2175 drivers/usb/dwc3/gadget.c reg |= DWC3_DCFG_SUPERSPEED; reg 2181 drivers/usb/dwc3/gadget.c reg |= DWC3_DCFG_SUPERSPEED_PLUS; reg 2183 drivers/usb/dwc3/gadget.c reg |= DWC3_DCFG_SUPERSPEED; reg 2186 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_DCFG, reg); reg 2593 drivers/usb/dwc3/gadget.c u32 reg; reg 2606 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg 2607 drivers/usb/dwc3/gadget.c reg |= dwc->u1u2; reg 2608 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_DCTL, reg); reg 2796 drivers/usb/dwc3/gadget.c int reg; reg 2798 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg 2799 drivers/usb/dwc3/gadget.c reg &= ~DWC3_DCTL_INITU1ENA; reg 2800 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_DCTL, reg); reg 2802 drivers/usb/dwc3/gadget.c reg &= ~DWC3_DCTL_INITU2ENA; reg 2803 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_DCTL, reg); reg 2816 drivers/usb/dwc3/gadget.c u32 reg; reg 2853 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg 2854 drivers/usb/dwc3/gadget.c reg &= ~DWC3_DCTL_TSTCTRL_MASK; reg 2855 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_DCTL, reg); reg 2860 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DCFG); reg 2861 drivers/usb/dwc3/gadget.c reg &= ~(DWC3_DCFG_DEVADDR_MASK); reg 2862 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_DCFG, reg); reg 2869 drivers/usb/dwc3/gadget.c u32 reg; reg 2872 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DSTS); reg 2873 drivers/usb/dwc3/gadget.c speed = reg & DWC3_DSTS_CONNECTSPD; reg 2936 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DCFG); reg 2937 drivers/usb/dwc3/gadget.c reg |= DWC3_DCFG_LPM_CAP; reg 2938 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_DCFG, reg); reg 2940 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg 2941 drivers/usb/dwc3/gadget.c reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); reg 2943 drivers/usb/dwc3/gadget.c reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold | reg 2957 drivers/usb/dwc3/gadget.c reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold); reg 2959 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_DCTL, reg); reg 2961 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg 2962 drivers/usb/dwc3/gadget.c reg &= ~DWC3_DCTL_HIRD_THRES_MASK; reg 2963 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_DCTL, reg); reg 3056 drivers/usb/dwc3/gadget.c u32 reg; reg 3061 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg 3062 drivers/usb/dwc3/gadget.c u1u2 = reg & (DWC3_DCTL_INITU2ENA reg 3068 drivers/usb/dwc3/gadget.c dwc->u1u2 = reg & u1u2; reg 3070 drivers/usb/dwc3/gadget.c reg &= ~u1u2; reg 3072 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_DCTL, reg); reg 3202 drivers/usb/dwc3/gadget.c u32 reg; reg 3234 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); reg 3235 drivers/usb/dwc3/gadget.c reg &= ~DWC3_GEVNTSIZ_INTMASK; reg 3236 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); reg 3265 drivers/usb/dwc3/gadget.c u32 reg; reg 3292 drivers/usb/dwc3/gadget.c reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); reg 3293 drivers/usb/dwc3/gadget.c reg |= DWC3_GEVNTSIZ_INTMASK; reg 3294 drivers/usb/dwc3/gadget.c dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); reg 23 drivers/usb/dwc3/ulpi.c u32 reg; reg 26 drivers/usb/dwc3/ulpi.c reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0)); reg 27 drivers/usb/dwc3/ulpi.c if (!(reg & DWC3_GUSB2PHYACC_BUSY)) reg 38 drivers/usb/dwc3/ulpi.c u32 reg; reg 41 drivers/usb/dwc3/ulpi.c reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); reg 42 drivers/usb/dwc3/ulpi.c if (reg & DWC3_GUSB2PHYCFG_SUSPHY) { reg 43 drivers/usb/dwc3/ulpi.c reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; reg 44 drivers/usb/dwc3/ulpi.c dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); reg 47 drivers/usb/dwc3/ulpi.c reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr); reg 48 drivers/usb/dwc3/ulpi.c dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg); reg 54 drivers/usb/dwc3/ulpi.c reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0)); reg 56 drivers/usb/dwc3/ulpi.c return DWC3_GUSB2PHYACC_DATA(reg); reg 62 drivers/usb/dwc3/ulpi.c u32 reg; reg 64 drivers/usb/dwc3/ulpi.c reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); reg 65 drivers/usb/dwc3/ulpi.c if (reg & DWC3_GUSB2PHYCFG_SUSPHY) { reg 66 drivers/usb/dwc3/ulpi.c reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; reg 67 drivers/usb/dwc3/ulpi.c dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); reg 70 drivers/usb/dwc3/ulpi.c reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr); reg 71 drivers/usb/dwc3/ulpi.c reg |= DWC3_GUSB2PHYACC_WRITE | val; reg 72 drivers/usb/dwc3/ulpi.c dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg); reg 754 drivers/usb/early/xhci-dbc.c u32 reg; reg 767 drivers/usb/early/xhci-dbc.c reg = readl(&xdbc.xdbc_reg->control); reg 768 drivers/usb/early/xhci-dbc.c if (!(reg & CTRL_DBC_ENABLE)) { reg 776 drivers/usb/early/xhci-dbc.c reg = readl(&xdbc.xdbc_reg->control); reg 777 drivers/usb/early/xhci-dbc.c if (reg & CTRL_DBC_RUN_CHANGE) { reg 778 drivers/usb/early/xhci-dbc.c writel(reg, &xdbc.xdbc_reg->control); reg 779 drivers/usb/early/xhci-dbc.c if (reg & CTRL_DBC_RUN) reg 786 drivers/usb/early/xhci-dbc.c reg = readl(&xdbc.xdbc_reg->control); reg 787 drivers/usb/early/xhci-dbc.c if (reg & CTRL_HALT_IN_TR) { reg 795 drivers/usb/early/xhci-dbc.c if (reg & CTRL_HALT_OUT_TR) reg 53 drivers/usb/gadget/udc/aspeed-vhub/dev.c u32 reg, hmsk, i; reg 62 drivers/usb/gadget/udc/aspeed-vhub/dev.c reg = VHUB_DEV_EN_ENABLE_PORT | reg 67 drivers/usb/gadget/udc/aspeed-vhub/dev.c reg |= VHUB_DEV_EN_SPEED_SEL_HIGH; reg 68 drivers/usb/gadget/udc/aspeed-vhub/dev.c writel(reg, d->regs + AST_VHUB_DEV_EN_CTRL); reg 72 drivers/usb/gadget/udc/aspeed-vhub/dev.c reg = readl(d->vhub->regs + AST_VHUB_IER); reg 73 drivers/usb/gadget/udc/aspeed-vhub/dev.c reg |= hmsk; reg 74 drivers/usb/gadget/udc/aspeed-vhub/dev.c writel(reg, d->vhub->regs + AST_VHUB_IER); reg 97 drivers/usb/gadget/udc/aspeed-vhub/dev.c u32 reg, hmsk; reg 104 drivers/usb/gadget/udc/aspeed-vhub/dev.c reg = readl(d->vhub->regs + AST_VHUB_IER); reg 105 drivers/usb/gadget/udc/aspeed-vhub/dev.c reg &= ~hmsk; reg 106 drivers/usb/gadget/udc/aspeed-vhub/dev.c writel(reg, d->vhub->regs + AST_VHUB_IER); reg 202 drivers/usb/gadget/udc/aspeed-vhub/dev.c u32 reg; reg 206 drivers/usb/gadget/udc/aspeed-vhub/dev.c reg = readl(d->regs + AST_VHUB_DEV_EN_CTRL); reg 207 drivers/usb/gadget/udc/aspeed-vhub/dev.c reg &= ~VHUB_DEV_EN_ADDR_MASK; reg 208 drivers/usb/gadget/udc/aspeed-vhub/dev.c reg |= VHUB_DEV_EN_SET_ADDR(addr); reg 209 drivers/usb/gadget/udc/aspeed-vhub/dev.c writel(reg, d->regs + AST_VHUB_DEV_EN_CTRL); reg 186 drivers/usb/gadget/udc/aspeed-vhub/ep0.c u32 reg; reg 227 drivers/usb/gadget/udc/aspeed-vhub/ep0.c reg = VHUB_EP0_SET_TX_LEN(chunk); reg 228 drivers/usb/gadget/udc/aspeed-vhub/ep0.c writel(reg, ep->ep0.ctlstat); reg 229 drivers/usb/gadget/udc/aspeed-vhub/ep0.c writel(reg | VHUB_EP0_TX_BUFF_RDY, ep->ep0.ctlstat); reg 420 drivers/usb/gadget/udc/aspeed-vhub/epn.c u32 state, reg, loops; reg 453 drivers/usb/gadget/udc/aspeed-vhub/epn.c reg = VHUB_EP_DMA_SET_RPTR(ep->epn.d_next) | reg 455 drivers/usb/gadget/udc/aspeed-vhub/epn.c writel(reg, ep->epn.regs + AST_VHUB_EP_DESC_STATUS); reg 498 drivers/usb/gadget/udc/aspeed-vhub/epn.c u32 reg; reg 502 drivers/usb/gadget/udc/aspeed-vhub/epn.c reg = readl(ep->epn.regs + AST_VHUB_EP_CONFIG); reg 504 drivers/usb/gadget/udc/aspeed-vhub/epn.c reg |= VHUB_EP_CFG_STALL_CTRL; reg 506 drivers/usb/gadget/udc/aspeed-vhub/epn.c reg &= ~VHUB_EP_CFG_STALL_CTRL; reg 507 drivers/usb/gadget/udc/aspeed-vhub/epn.c writel(reg, ep->epn.regs + AST_VHUB_EP_CONFIG); reg 236 drivers/usb/gadget/udc/aspeed-vhub/hub.c u32 reg; reg 253 drivers/usb/gadget/udc/aspeed-vhub/hub.c reg = readl(ep->vhub->regs + AST_VHUB_EP1_CTRL); reg 255 drivers/usb/gadget/udc/aspeed-vhub/hub.c reg |= VHUB_EP1_CTRL_STALL; reg 257 drivers/usb/gadget/udc/aspeed-vhub/hub.c reg &= ~VHUB_EP1_CTRL_STALL; reg 258 drivers/usb/gadget/udc/aspeed-vhub/hub.c reg |= VHUB_EP1_CTRL_RESET_TOGGLE; reg 260 drivers/usb/gadget/udc/aspeed-vhub/hub.c writel(reg, ep->vhub->regs + AST_VHUB_EP1_CTRL); reg 417 drivers/usb/gadget/udc/aspeed-vhub/hub.c u32 reg = readl(vhub->regs + AST_VHUB_EP1_STS_CHG); reg 420 drivers/usb/gadget/udc/aspeed-vhub/hub.c reg |= pmask; reg 422 drivers/usb/gadget/udc/aspeed-vhub/hub.c reg &= ~pmask; reg 423 drivers/usb/gadget/udc/aspeed-vhub/hub.c writel(reg, vhub->regs + AST_VHUB_EP1_STS_CHG); reg 467 drivers/usb/gadget/udc/aspeed-vhub/hub.c u32 reg = readl(vhub->regs + AST_VHUB_CTRL); reg 469 drivers/usb/gadget/udc/aspeed-vhub/hub.c reg |= VHUB_CTRL_MANUAL_REMOTE_WAKEUP; reg 470 drivers/usb/gadget/udc/aspeed-vhub/hub.c writel(reg, vhub->regs + AST_VHUB_CTRL); reg 89 drivers/usb/gadget/udc/at91_udc.c #define at91_udp_read(udc, reg) \ reg 90 drivers/usb/gadget/udc/at91_udc.c __raw_readl((udc)->udp_baseaddr + (reg)) reg 91 drivers/usb/gadget/udc/at91_udc.c #define at91_udp_write(udc, reg, val) \ reg 92 drivers/usb/gadget/udc/at91_udc.c __raw_writel((val), (udc)->udp_baseaddr + (reg)) reg 188 drivers/usb/gadget/udc/atmel_usba_udc.h #define usba_readl(udc, reg) \ reg 189 drivers/usb/gadget/udc/atmel_usba_udc.h readl_relaxed((udc)->regs + USBA_##reg) reg 190 drivers/usb/gadget/udc/atmel_usba_udc.h #define usba_writel(udc, reg, value) \ reg 191 drivers/usb/gadget/udc/atmel_usba_udc.h writel_relaxed((value), (udc)->regs + USBA_##reg) reg 192 drivers/usb/gadget/udc/atmel_usba_udc.h #define usba_ep_readl(ep, reg) \ reg 193 drivers/usb/gadget/udc/atmel_usba_udc.h readl_relaxed((ep)->ep_regs + USBA_EPT_##reg) reg 194 drivers/usb/gadget/udc/atmel_usba_udc.h #define usba_ep_writel(ep, reg, value) \ reg 195 drivers/usb/gadget/udc/atmel_usba_udc.h writel_relaxed((value), (ep)->ep_regs + USBA_EPT_##reg) reg 196 drivers/usb/gadget/udc/atmel_usba_udc.h #define usba_dma_readl(ep, reg) \ reg 197 drivers/usb/gadget/udc/atmel_usba_udc.h readl_relaxed((ep)->dma_regs + USBA_DMA_##reg) reg 198 drivers/usb/gadget/udc/atmel_usba_udc.h #define usba_dma_writel(ep, reg, value) \ reg 199 drivers/usb/gadget/udc/atmel_usba_udc.h writel_relaxed((value), (ep)->dma_regs + USBA_DMA_##reg) reg 1895 drivers/usb/gadget/udc/bcm63xx_udc.c u32 reg = usbd_readl(udc, USBD_STATUS_REG); reg 1897 drivers/usb/gadget/udc/bcm63xx_udc.c udc->cfg = (reg & USBD_STATUS_CFG_MASK) >> USBD_STATUS_CFG_SHIFT; reg 1898 drivers/usb/gadget/udc/bcm63xx_udc.c udc->iface = (reg & USBD_STATUS_INTF_MASK) >> USBD_STATUS_INTF_SHIFT; reg 1899 drivers/usb/gadget/udc/bcm63xx_udc.c udc->alt_iface = (reg & USBD_STATUS_ALTINTF_MASK) >> reg 1913 drivers/usb/gadget/udc/bcm63xx_udc.c u32 reg = usbd_readl(udc, USBD_STATUS_REG); reg 1916 drivers/usb/gadget/udc/bcm63xx_udc.c switch ((reg & USBD_STATUS_SPD_MASK) >> USBD_STATUS_SPD_SHIFT) { reg 30 drivers/usb/gadget/udc/fotg210-udc.c u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1); reg 36 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1); reg 41 drivers/usb/gadget/udc/fotg210-udc.c u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1); reg 47 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1); reg 52 drivers/usb/gadget/udc/fotg210-udc.c u32 value = ioread32(fotg210->reg + FOTG210_DCFESR); reg 55 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, fotg210->reg + FOTG210_DCFESR); reg 92 drivers/usb/gadget/udc/fotg210-udc.c val = ioread32(fotg210->reg + FOTG210_EPMAP); reg 95 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(val, fotg210->reg + FOTG210_EPMAP); reg 98 drivers/usb/gadget/udc/fotg210-udc.c val = ioread32(fotg210->reg + FOTG210_FIFOMAP); reg 101 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(val, fotg210->reg + FOTG210_FIFOMAP); reg 104 drivers/usb/gadget/udc/fotg210-udc.c val = ioread32(fotg210->reg + FOTG210_FIFOCF); reg 106 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(val, fotg210->reg + FOTG210_FIFOCF); reg 114 drivers/usb/gadget/udc/fotg210-udc.c val = ioread32(fotg210->reg + FOTG210_FIFOMAP); reg 116 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(val, fotg210->reg + FOTG210_FIFOMAP); reg 124 drivers/usb/gadget/udc/fotg210-udc.c val = ioread32(fotg210->reg + FOTG210_FIFOCF); reg 126 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(val, fotg210->reg + FOTG210_FIFOCF); reg 137 drivers/usb/gadget/udc/fotg210-udc.c val = ioread32(fotg210->reg + offset); reg 139 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(val, fotg210->reg + offset); reg 177 drivers/usb/gadget/udc/fotg210-udc.c void __iomem *reg; reg 179 drivers/usb/gadget/udc/fotg210-udc.c reg = (ep->dir_in) ? reg 180 drivers/usb/gadget/udc/fotg210-udc.c fotg210->reg + FOTG210_INEPMPSR(epnum) : reg 181 drivers/usb/gadget/udc/fotg210-udc.c fotg210->reg + FOTG210_OUTEPMPSR(epnum); reg 187 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(reg); reg 189 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, reg); reg 191 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(reg); reg 193 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, reg); reg 260 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(fotg210->reg + FOTG210_DMACPSR1); reg 263 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, fotg210->reg + FOTG210_DMACPSR1); reg 266 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(fotg210->reg + FOTG210_DMATFNR); reg 271 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, fotg210->reg + FOTG210_DMATFNR); reg 274 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(d, fotg210->reg + FOTG210_DMACPSR2); reg 277 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(fotg210->reg + FOTG210_DMISGR2); reg 279 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, fotg210->reg + FOTG210_DMISGR2); reg 282 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(fotg210->reg + FOTG210_DMACPSR1); reg 284 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, fotg210->reg + FOTG210_DMACPSR1); reg 289 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(DMATFNR_DISDMA, ep->fotg210->reg + FOTG210_DMATFNR); reg 297 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(ep->fotg210->reg + FOTG210_DISGR2); reg 304 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, ep->fotg210->reg + FOTG210_DISGR2); reg 308 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(ep->fotg210->reg + FOTG210_DMACPSR1); reg 310 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, ep->fotg210->reg + FOTG210_DMACPSR1); reg 314 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(ep->fotg210->reg + reg 317 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, ep->fotg210->reg + reg 320 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(ep->fotg210->reg + FOTG210_DCFESR); reg 322 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, ep->fotg210->reg + FOTG210_DCFESR); reg 340 drivers/usb/gadget/udc/fotg210-udc.c length = ioread32(ep->fotg210->reg + reg 386 drivers/usb/gadget/udc/fotg210-udc.c u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR0); reg 389 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR0); reg 448 drivers/usb/gadget/udc/fotg210-udc.c void __iomem *reg; reg 453 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(fotg210->reg + FOTG210_DCFESR); reg 457 drivers/usb/gadget/udc/fotg210-udc.c reg = (ep->dir_in) ? reg 458 drivers/usb/gadget/udc/fotg210-udc.c fotg210->reg + FOTG210_INEPMPSR(ep->epnum) : reg 459 drivers/usb/gadget/udc/fotg210-udc.c fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum); reg 460 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(reg); reg 462 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, reg); reg 469 drivers/usb/gadget/udc/fotg210-udc.c void __iomem *reg; reg 471 drivers/usb/gadget/udc/fotg210-udc.c reg = (ep->dir_in) ? reg 472 drivers/usb/gadget/udc/fotg210-udc.c fotg210->reg + FOTG210_INEPMPSR(ep->epnum) : reg 473 drivers/usb/gadget/udc/fotg210-udc.c fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum); reg 474 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(reg); reg 476 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, reg); reg 540 drivers/usb/gadget/udc/fotg210-udc.c u32 value = ioread32(fotg210->reg + FOTG210_TX0BYTE); reg 544 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, fotg210->reg + FOTG210_TX0BYTE); reg 549 drivers/usb/gadget/udc/fotg210-udc.c u32 value = ioread32(fotg210->reg + FOTG210_RX0BYTE); reg 553 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, fotg210->reg + FOTG210_RX0BYTE); reg 565 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(DMATFNR_ACC_CXF, fotg210->reg + FOTG210_DMATFNR); reg 568 drivers/usb/gadget/udc/fotg210-udc.c data = ioread32(fotg210->reg + FOTG210_CXPORT); reg 578 drivers/usb/gadget/udc/fotg210-udc.c data = ioread32(fotg210->reg + FOTG210_CXPORT); reg 582 drivers/usb/gadget/udc/fotg210-udc.c data = ioread32(fotg210->reg + FOTG210_CXPORT); reg 587 drivers/usb/gadget/udc/fotg210-udc.c data = ioread32(fotg210->reg + FOTG210_CXPORT); reg 596 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(DMATFNR_DISDMA, fotg210->reg + FOTG210_DMATFNR); reg 601 drivers/usb/gadget/udc/fotg210-udc.c u32 value = ioread32(fotg210->reg + FOTG210_DAR); reg 604 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, fotg210->reg + FOTG210_DAR); reg 609 drivers/usb/gadget/udc/fotg210-udc.c u32 value = ioread32(fotg210->reg + FOTG210_DAR); reg 612 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, fotg210->reg + FOTG210_DAR); reg 617 drivers/usb/gadget/udc/fotg210-udc.c u32 value = ioread32(fotg210->reg + FOTG210_DCFESR); reg 620 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, fotg210->reg + FOTG210_DCFESR); reg 700 drivers/usb/gadget/udc/fotg210-udc.c void __iomem *reg; reg 702 drivers/usb/gadget/udc/fotg210-udc.c reg = (ep->dir_in) ? reg 703 drivers/usb/gadget/udc/fotg210-udc.c fotg210->reg + FOTG210_INEPMPSR(ep->epnum) : reg 704 drivers/usb/gadget/udc/fotg210-udc.c fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum); reg 705 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(reg); reg 755 drivers/usb/gadget/udc/fotg210-udc.c u32 value = ioread32(fotg210->reg + FOTG210_DMCR); reg 832 drivers/usb/gadget/udc/fotg210-udc.c u32 value = ioread32(fotg210->reg + FOTG210_DISGR0); reg 835 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, fotg210->reg + FOTG210_DISGR0); reg 864 drivers/usb/gadget/udc/fotg210-udc.c u32 int_grp = ioread32(fotg210->reg + FOTG210_DIGR); reg 865 drivers/usb/gadget/udc/fotg210-udc.c u32 int_msk = ioread32(fotg210->reg + FOTG210_DMIGR); reg 872 drivers/usb/gadget/udc/fotg210-udc.c void __iomem *reg = fotg210->reg + FOTG210_DISGR2; reg 873 drivers/usb/gadget/udc/fotg210-udc.c u32 int_grp2 = ioread32(reg); reg 874 drivers/usb/gadget/udc/fotg210-udc.c u32 int_msk2 = ioread32(fotg210->reg + FOTG210_DMISGR2); reg 880 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(reg); reg 882 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, reg); reg 886 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(reg); reg 888 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, reg); reg 892 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(reg); reg 894 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, reg); reg 898 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(reg); reg 900 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, reg); reg 904 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(reg); reg 906 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, reg); reg 911 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(reg); reg 913 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, reg); reg 918 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(reg); reg 920 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, reg); reg 924 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(reg); reg 926 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, reg); reg 931 drivers/usb/gadget/udc/fotg210-udc.c void __iomem *reg = fotg210->reg + FOTG210_DISGR0; reg 932 drivers/usb/gadget/udc/fotg210-udc.c u32 int_grp0 = ioread32(reg); reg 933 drivers/usb/gadget/udc/fotg210-udc.c u32 int_msk0 = ioread32(fotg210->reg + FOTG210_DMISGR0); reg 969 drivers/usb/gadget/udc/fotg210-udc.c void __iomem *reg = fotg210->reg + FOTG210_DISGR1; reg 970 drivers/usb/gadget/udc/fotg210-udc.c u32 int_grp1 = ioread32(reg); reg 971 drivers/usb/gadget/udc/fotg210-udc.c u32 int_msk1 = ioread32(fotg210->reg + FOTG210_DMISGR1); reg 993 drivers/usb/gadget/udc/fotg210-udc.c u32 reg = ioread32(fotg210->reg + FOTG210_PHYTMSR); reg 995 drivers/usb/gadget/udc/fotg210-udc.c reg &= ~PHYTMSR_UNPLUG; reg 996 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(reg, fotg210->reg + FOTG210_PHYTMSR); reg 1010 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(fotg210->reg + FOTG210_DMCR); reg 1012 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, fotg210->reg + FOTG210_DMCR); reg 1023 drivers/usb/gadget/udc/fotg210-udc.c fotg210->reg + FOTG210_GMIR); reg 1026 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(fotg210->reg + FOTG210_DMCR); reg 1028 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, fotg210->reg + FOTG210_DMCR); reg 1031 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(~(u32)0, fotg210->reg + FOTG210_DMISGR1); reg 1034 drivers/usb/gadget/udc/fotg210-udc.c value = ioread32(fotg210->reg + FOTG210_DMISGR0); reg 1036 drivers/usb/gadget/udc/fotg210-udc.c iowrite32(value, fotg210->reg + FOTG210_DMISGR0); reg 1065 drivers/usb/gadget/udc/fotg210-udc.c iounmap(fotg210->reg); reg 1110 drivers/usb/gadget/udc/fotg210-udc.c fotg210->reg = ioremap(res->start, resource_size(res)); reg 1111 drivers/usb/gadget/udc/fotg210-udc.c if (fotg210->reg == NULL) { reg 1189 drivers/usb/gadget/udc/fotg210-udc.c iounmap(fotg210->reg); reg 233 drivers/usb/gadget/udc/fotg210.h void __iomem *reg; reg 1723 drivers/usb/gadget/udc/fsl_udc_core.c static inline enum usb_device_speed portscx_device_speed(u32 reg) reg 1725 drivers/usb/gadget/udc/fsl_udc_core.c switch (reg & PORTSCX_PORT_SPEED_MASK) { reg 39 drivers/usb/gadget/udc/fusb300_udc.c u32 reg = ioread32(fusb300->reg + offset); reg 41 drivers/usb/gadget/udc/fusb300_udc.c reg |= value; reg 42 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, fusb300->reg + offset); reg 48 drivers/usb/gadget/udc/fusb300_udc.c u32 reg = ioread32(fusb300->reg + offset); reg 50 drivers/usb/gadget/udc/fusb300_udc.c reg &= ~value; reg 51 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, fusb300->reg + offset); reg 75 drivers/usb/gadget/udc/fusb300_udc.c u32 val = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); reg 79 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(val, fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); reg 85 drivers/usb/gadget/udc/fusb300_udc.c u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); reg 88 drivers/usb/gadget/udc/fusb300_udc.c reg &= ~FUSB300_EPSET1_START_ENTRY_MSK ; reg 89 drivers/usb/gadget/udc/fusb300_udc.c reg |= FUSB300_EPSET1_START_ENTRY(start_entry); reg 90 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); reg 103 drivers/usb/gadget/udc/fusb300_udc.c u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum)); reg 105 drivers/usb/gadget/udc/fusb300_udc.c reg &= ~FUSB300_EPSET2_ADDROFS_MSK; reg 106 drivers/usb/gadget/udc/fusb300_udc.c reg |= FUSB300_EPSET2_ADDROFS(fusb300->addrofs); reg 107 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum)); reg 122 drivers/usb/gadget/udc/fusb300_udc.c u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); reg 124 drivers/usb/gadget/udc/fusb300_udc.c reg &= ~FUSB300_EPSET1_TYPE_MSK; reg 125 drivers/usb/gadget/udc/fusb300_udc.c reg |= FUSB300_EPSET1_TYPE(info.type); reg 126 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); reg 132 drivers/usb/gadget/udc/fusb300_udc.c u32 reg; reg 136 drivers/usb/gadget/udc/fusb300_udc.c reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); reg 137 drivers/usb/gadget/udc/fusb300_udc.c reg &= ~FUSB300_EPSET1_DIR_MSK; reg 138 drivers/usb/gadget/udc/fusb300_udc.c reg |= FUSB300_EPSET1_DIRIN; reg 139 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); reg 145 drivers/usb/gadget/udc/fusb300_udc.c u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); reg 147 drivers/usb/gadget/udc/fusb300_udc.c reg |= FUSB300_EPSET1_ACTEN; reg 148 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep)); reg 154 drivers/usb/gadget/udc/fusb300_udc.c u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum)); reg 156 drivers/usb/gadget/udc/fusb300_udc.c reg &= ~FUSB300_EPSET2_MPS_MSK; reg 157 drivers/usb/gadget/udc/fusb300_udc.c reg |= FUSB300_EPSET2_MPS(info.maxpacket); reg 158 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum)); reg 164 drivers/usb/gadget/udc/fusb300_udc.c u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); reg 166 drivers/usb/gadget/udc/fusb300_udc.c reg &= ~FUSB300_EPSET1_INTERVAL(0x7); reg 167 drivers/usb/gadget/udc/fusb300_udc.c reg |= FUSB300_EPSET1_INTERVAL(info.interval); reg 168 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); reg 174 drivers/usb/gadget/udc/fusb300_udc.c u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); reg 176 drivers/usb/gadget/udc/fusb300_udc.c reg &= ~FUSB300_EPSET1_BWNUM(0x3); reg 177 drivers/usb/gadget/udc/fusb300_udc.c reg |= FUSB300_EPSET1_BWNUM(info.bw_num); reg 178 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum)); reg 321 drivers/usb/gadget/udc/fusb300_udc.c u32 reg; reg 323 drivers/usb/gadget/udc/fusb300_udc.c reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR); reg 324 drivers/usb/gadget/udc/fusb300_udc.c reg &= ~FUSB300_CSR_LEN_MSK; reg 325 drivers/usb/gadget/udc/fusb300_udc.c reg |= FUSB300_CSR_LEN(length); reg 326 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, fusb300->reg + FUSB300_OFFSET_CSR); reg 346 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); reg 356 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); reg 363 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); reg 368 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); reg 373 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT); reg 390 drivers/usb/gadget/udc/fusb300_udc.c u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep)); reg 392 drivers/usb/gadget/udc/fusb300_udc.c if (reg & FUSB300_EPSET0_STL) { reg 394 drivers/usb/gadget/udc/fusb300_udc.c reg |= FUSB300_EPSET0_STL_CLR; reg 395 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET0(ep)); reg 537 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(value, fusb300->reg + offset); reg 567 drivers/usb/gadget/udc/fusb300_udc.c data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT); reg 578 drivers/usb/gadget/udc/fusb300_udc.c data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT); reg 583 drivers/usb/gadget/udc/fusb300_udc.c data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT); reg 589 drivers/usb/gadget/udc/fusb300_udc.c data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT); reg 606 drivers/usb/gadget/udc/fusb300_udc.c u32 data, reg; reg 616 drivers/usb/gadget/udc/fusb300_udc.c data = ioread32(fusb300->reg + reg 627 drivers/usb/gadget/udc/fusb300_udc.c data = ioread32(fusb300->reg + reg 632 drivers/usb/gadget/udc/fusb300_udc.c data = ioread32(fusb300->reg + reg 638 drivers/usb/gadget/udc/fusb300_udc.c data = ioread32(fusb300->reg + reg 649 drivers/usb/gadget/udc/fusb300_udc.c reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1); reg 650 drivers/usb/gadget/udc/fusb300_udc.c reg &= FUSB300_IGR1_SYNF0_EMPTY_INT; reg 654 drivers/usb/gadget/udc/fusb300_udc.c } while (!reg); reg 660 drivers/usb/gadget/udc/fusb300_udc.c u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep)); reg 662 drivers/usb/gadget/udc/fusb300_udc.c value = reg & FUSB300_EPSET0_STL; reg 670 drivers/usb/gadget/udc/fusb300_udc.c u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR); reg 672 drivers/usb/gadget/udc/fusb300_udc.c value = (reg & FUSB300_CSR_STL) >> 1; reg 793 drivers/usb/gadget/udc/fusb300_udc.c u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_DAR); reg 795 drivers/usb/gadget/udc/fusb300_udc.c reg &= ~FUSB300_DAR_DRVADDR_MSK; reg 796 drivers/usb/gadget/udc/fusb300_udc.c reg |= FUSB300_DAR_DRVADDR(addr); reg 798 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, fusb300->reg + FUSB300_OFFSET_DAR); reg 891 drivers/usb/gadget/udc/fusb300_udc.c u32 reg; reg 895 drivers/usb/gadget/udc/fusb300_udc.c reg = ioread32(ep->fusb300->reg + reg 897 drivers/usb/gadget/udc/fusb300_udc.c reg &= FUSB300_EPPRD0_H; reg 898 drivers/usb/gadget/udc/fusb300_udc.c } while (reg); reg 900 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(d, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W1(ep->epnum)); reg 904 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(value, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W0(ep->epnum)); reg 906 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(0x0, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W2(ep->epnum)); reg 914 drivers/usb/gadget/udc/fusb300_udc.c u32 reg; reg 917 drivers/usb/gadget/udc/fusb300_udc.c reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR1); reg 918 drivers/usb/gadget/udc/fusb300_udc.c if ((reg & FUSB300_IGR1_VBUS_CHG_INT) || reg 919 drivers/usb/gadget/udc/fusb300_udc.c (reg & FUSB300_IGR1_WARM_RST_INT) || reg 920 drivers/usb/gadget/udc/fusb300_udc.c (reg & FUSB300_IGR1_HOT_RST_INT) || reg 921 drivers/usb/gadget/udc/fusb300_udc.c (reg & FUSB300_IGR1_USBRST_INT) reg 924 drivers/usb/gadget/udc/fusb300_udc.c reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR0); reg 925 drivers/usb/gadget/udc/fusb300_udc.c reg &= FUSB300_IGR0_EPn_PRD_INT(ep->epnum); reg 926 drivers/usb/gadget/udc/fusb300_udc.c } while (!reg); reg 933 drivers/usb/gadget/udc/fusb300_udc.c reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGER0); reg 934 drivers/usb/gadget/udc/fusb300_udc.c reg &= ~FUSB300_IGER0_EEPn_PRD_INT(ep->epnum); reg 935 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, ep->fusb300->reg + FUSB300_OFFSET_IGER0); reg 974 drivers/usb/gadget/udc/fusb300_udc.c u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPFFR(ep->epnum)); reg 975 drivers/usb/gadget/udc/fusb300_udc.c u32 length = reg & FUSB300_FFR_BYCNT; reg 986 drivers/usb/gadget/udc/fusb300_udc.c u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_GCR); reg 988 drivers/usb/gadget/udc/fusb300_udc.c switch (reg & FUSB300_GCR_DEVEN_MSK) { reg 1002 drivers/usb/gadget/udc/fusb300_udc.c printk(KERN_INFO "dev_mode = %d\n", (reg & FUSB300_GCR_DEVEN_MSK)); reg 1009 drivers/usb/gadget/udc/fusb300_udc.c u32 reg; reg 1020 drivers/usb/gadget/udc/fusb300_udc.c reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1); reg 1021 drivers/usb/gadget/udc/fusb300_udc.c reg &= ~FUSB300_IGER1_CX_OUT_INT; reg 1022 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, fusb300->reg + FUSB300_OFFSET_IGER1); reg 1062 drivers/usb/gadget/udc/fusb300_udc.c u32 int_grp1 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1); reg 1063 drivers/usb/gadget/udc/fusb300_udc.c u32 int_grp1_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1); reg 1064 drivers/usb/gadget/udc/fusb300_udc.c u32 int_grp0 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR0); reg 1065 drivers/usb/gadget/udc/fusb300_udc.c u32 int_grp0_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER0); reg 1068 drivers/usb/gadget/udc/fusb300_udc.c u32 reg; reg 1240 drivers/usb/gadget/udc/fusb300_udc.c reg = ioread32(fusb300->reg + reg 1242 drivers/usb/gadget/udc/fusb300_udc.c in = (reg & FUSB300_EPSET1_DIRIN) ? 1 : 0; reg 1259 drivers/usb/gadget/udc/fusb300_udc.c u32 reg; reg 1261 drivers/usb/gadget/udc/fusb300_udc.c reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT); reg 1262 drivers/usb/gadget/udc/fusb300_udc.c reg &= ~0xff; reg 1263 drivers/usb/gadget/udc/fusb300_udc.c reg |= FUSB300_SSCR2_U2TIMEOUT(time); reg 1265 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT); reg 1271 drivers/usb/gadget/udc/fusb300_udc.c u32 reg; reg 1273 drivers/usb/gadget/udc/fusb300_udc.c reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT); reg 1274 drivers/usb/gadget/udc/fusb300_udc.c reg &= ~(0xff << 8); reg 1275 drivers/usb/gadget/udc/fusb300_udc.c reg |= FUSB300_SSCR2_U1TIMEOUT(time); reg 1277 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT); reg 1282 drivers/usb/gadget/udc/fusb300_udc.c u32 reg; reg 1288 drivers/usb/gadget/udc/fusb300_udc.c reg = ioread32(fusb300->reg + FUSB300_OFFSET_AHBCR); reg 1289 drivers/usb/gadget/udc/fusb300_udc.c reg &= ~mask; reg 1290 drivers/usb/gadget/udc/fusb300_udc.c reg |= val; reg 1291 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, fusb300->reg + FUSB300_OFFSET_AHBCR); reg 1295 drivers/usb/gadget/udc/fusb300_udc.c reg = ioread32(fusb300->reg + FUSB300_OFFSET_HSCR); reg 1296 drivers/usb/gadget/udc/fusb300_udc.c reg &= ~mask; reg 1297 drivers/usb/gadget/udc/fusb300_udc.c reg |= val; reg 1298 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(reg, fusb300->reg + FUSB300_OFFSET_HSCR); reg 1305 drivers/usb/gadget/udc/fusb300_udc.c iowrite32(0xcfffff9f, fusb300->reg + FUSB300_OFFSET_IGER1); reg 1348 drivers/usb/gadget/udc/fusb300_udc.c iounmap(fusb300->reg); reg 1362 drivers/usb/gadget/udc/fusb300_udc.c void __iomem *reg = NULL; reg 1391 drivers/usb/gadget/udc/fusb300_udc.c reg = ioremap(res->start, resource_size(res)); reg 1392 drivers/usb/gadget/udc/fusb300_udc.c if (reg == NULL) { reg 1422 drivers/usb/gadget/udc/fusb300_udc.c fusb300->reg = reg; reg 1501 drivers/usb/gadget/udc/fusb300_udc.c if (reg) reg 1502 drivers/usb/gadget/udc/fusb300_udc.c iounmap(reg); reg 654 drivers/usb/gadget/udc/fusb300_udc.h void __iomem *reg; reg 50 drivers/usb/gadget/udc/m66592-udc.c unsigned long reg) reg 57 drivers/usb/gadget/udc/m66592-udc.c m66592_bset(m66592, (1 << pipenum), reg); reg 62 drivers/usb/gadget/udc/m66592-udc.c unsigned long reg) reg 69 drivers/usb/gadget/udc/m66592-udc.c m66592_bclr(m66592, (1 << pipenum), reg); reg 1523 drivers/usb/gadget/udc/m66592-udc.c iounmap(m66592->reg); reg 1541 drivers/usb/gadget/udc/m66592-udc.c void __iomem *reg = NULL; reg 1562 drivers/usb/gadget/udc/m66592-udc.c reg = ioremap(res->start, resource_size(res)); reg 1563 drivers/usb/gadget/udc/m66592-udc.c if (reg == NULL) { reg 1593 drivers/usb/gadget/udc/m66592-udc.c m66592->reg = reg; reg 1684 drivers/usb/gadget/udc/m66592-udc.c if (reg) reg 1685 drivers/usb/gadget/udc/m66592-udc.c iounmap(reg); reg 464 drivers/usb/gadget/udc/m66592-udc.h void __iomem *reg; reg 523 drivers/usb/gadget/udc/m66592-udc.h return ioread16(m66592->reg + offset); reg 530 drivers/usb/gadget/udc/m66592-udc.h void __iomem *fifoaddr = m66592->reg + offset; reg 544 drivers/usb/gadget/udc/m66592-udc.h iowrite16(val, m66592->reg + offset); reg 566 drivers/usb/gadget/udc/m66592-udc.h void __iomem *fifoaddr = m66592->reg + ep->fifoaddr; reg 476 drivers/usb/gadget/udc/net2272.h net2272_reg_addr(struct net2272 *dev, unsigned int reg) reg 478 drivers/usb/gadget/udc/net2272.h return dev->base_addr + (reg << dev->base_shift); reg 482 drivers/usb/gadget/udc/net2272.h net2272_write(struct net2272 *dev, unsigned int reg, u8 value) reg 484 drivers/usb/gadget/udc/net2272.h if (reg >= REG_INDEXED_THRESHOLD) { reg 493 drivers/usb/gadget/udc/net2272.h writeb((u8)reg, net2272_reg_addr(dev, REGADDRPTR)); reg 497 drivers/usb/gadget/udc/net2272.h writeb(value, net2272_reg_addr(dev, reg)); reg 501 drivers/usb/gadget/udc/net2272.h net2272_read(struct net2272 *dev, unsigned int reg) reg 505 drivers/usb/gadget/udc/net2272.h if (reg >= REG_INDEXED_THRESHOLD) { reg 514 drivers/usb/gadget/udc/net2272.h writeb((u8)reg, net2272_reg_addr(dev, REGADDRPTR)); reg 518 drivers/usb/gadget/udc/net2272.h ret = readb(net2272_reg_addr(dev, reg)); reg 524 drivers/usb/gadget/udc/net2272.h net2272_ep_write(struct net2272_ep *ep, unsigned int reg, u8 value) reg 532 drivers/usb/gadget/udc/net2272.h net2272_write(dev, reg, value); reg 536 drivers/usb/gadget/udc/net2272.h net2272_ep_read(struct net2272_ep *ep, unsigned int reg) reg 544 drivers/usb/gadget/udc/net2272.h return net2272_read(dev, reg); reg 362 drivers/usb/gadget/udc/net2280.h u32 reg; reg 367 drivers/usb/gadget/udc/net2280.h reg = ep_enhanced[ep->num]; reg 370 drivers/usb/gadget/udc/net2280.h reg += 2; reg 373 drivers/usb/gadget/udc/net2280.h reg += 1; reg 380 drivers/usb/gadget/udc/net2280.h reg = (ep->num + 1) * 0x10; reg 382 drivers/usb/gadget/udc/net2280.h reg += 1; reg 385 drivers/usb/gadget/udc/net2280.h set_idx_reg(ep->dev->regs, reg, max); reg 699 drivers/usb/gadget/udc/omap_udc.c u16 reg; reg 705 drivers/usb/gadget/udc/omap_udc.c reg = omap_readw(UDC_TXDMA_CFG); reg 707 drivers/usb/gadget/udc/omap_udc.c reg = omap_readw(UDC_RXDMA_CFG); reg 708 drivers/usb/gadget/udc/omap_udc.c reg |= UDC_DMA_REQ; /* "pulse" activated */ reg 713 drivers/usb/gadget/udc/omap_udc.c if ((reg & 0x0f00) == 0) reg 715 drivers/usb/gadget/udc/omap_udc.c else if ((reg & 0x00f0) == 0) reg 717 drivers/usb/gadget/udc/omap_udc.c else if ((reg & 0x000f) == 0) /* preferred for ISO */ reg 724 drivers/usb/gadget/udc/omap_udc.c reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1)); reg 732 drivers/usb/gadget/udc/omap_udc.c omap_writew(reg, UDC_TXDMA_CFG); reg 749 drivers/usb/gadget/udc/omap_udc.c omap_writew(reg, UDC_RXDMA_CFG); reg 408 drivers/usb/gadget/udc/pch_udc.c static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg) reg 410 drivers/usb/gadget/udc/pch_udc.c return ioread32(dev->base_addr + reg); reg 414 drivers/usb/gadget/udc/pch_udc.c unsigned long val, unsigned long reg) reg 416 drivers/usb/gadget/udc/pch_udc.c iowrite32(val, dev->base_addr + reg); reg 420 drivers/usb/gadget/udc/pch_udc.c unsigned long reg, reg 423 drivers/usb/gadget/udc/pch_udc.c pch_udc_writel(dev, pch_udc_readl(dev, reg) | bitmask, reg); reg 427 drivers/usb/gadget/udc/pch_udc.c unsigned long reg, reg 430 drivers/usb/gadget/udc/pch_udc.c pch_udc_writel(dev, pch_udc_readl(dev, reg) & ~(bitmask), reg); reg 433 drivers/usb/gadget/udc/pch_udc.c static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg) reg 435 drivers/usb/gadget/udc/pch_udc.c return ioread32(ep->dev->base_addr + ep->offset_addr + reg); reg 439 drivers/usb/gadget/udc/pch_udc.c unsigned long val, unsigned long reg) reg 441 drivers/usb/gadget/udc/pch_udc.c iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg); reg 445 drivers/usb/gadget/udc/pch_udc.c unsigned long reg, reg 448 drivers/usb/gadget/udc/pch_udc.c pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg); reg 452 drivers/usb/gadget/udc/pch_udc.c unsigned long reg, reg 455 drivers/usb/gadget/udc/pch_udc.c pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg); reg 483 drivers/usb/gadget/udc/pch_udc.c unsigned long reg = PCH_UDC_CSR(ep); reg 486 drivers/usb/gadget/udc/pch_udc.c pch_udc_writel(dev, val, reg); reg 499 drivers/usb/gadget/udc/pch_udc.c unsigned long reg = PCH_UDC_CSR(ep); reg 502 drivers/usb/gadget/udc/pch_udc.c pch_udc_readl(dev, reg); /* Dummy read */ reg 504 drivers/usb/gadget/udc/pch_udc.c return pch_udc_readl(dev, reg); reg 2617 drivers/usb/gadget/udc/pch_udc.c u32 reg, dev_stat = 0; reg 2634 drivers/usb/gadget/udc/pch_udc.c reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX); reg 2635 drivers/usb/gadget/udc/pch_udc.c reg = (reg & ~UDC_CSR_NE_INTF_MASK) | reg 2637 drivers/usb/gadget/udc/pch_udc.c reg = (reg & ~UDC_CSR_NE_ALT_MASK) | reg 2639 drivers/usb/gadget/udc/pch_udc.c pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX); reg 2659 drivers/usb/gadget/udc/pch_udc.c u32 reg, dev_stat = 0; reg 2671 drivers/usb/gadget/udc/pch_udc.c reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX); reg 2672 drivers/usb/gadget/udc/pch_udc.c reg = (reg & ~UDC_CSR_NE_CFG_MASK) | reg 2674 drivers/usb/gadget/udc/pch_udc.c pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX); reg 297 drivers/usb/gadget/udc/pxa25x_udc.c static inline void udc_set_reg(struct pxa25x_udc *dev, u32 reg, u32 val) reg 299 drivers/usb/gadget/udc/pxa25x_udc.c iowrite32be(val, dev->regs + reg); reg 302 drivers/usb/gadget/udc/pxa25x_udc.c static inline u32 udc_get_reg(struct pxa25x_udc *dev, u32 reg) reg 304 drivers/usb/gadget/udc/pxa25x_udc.c return ioread32be(dev->regs + reg); reg 307 drivers/usb/gadget/udc/pxa25x_udc.c static inline void udc_set_reg(struct pxa25x_udc *dev, u32 reg, u32 val) reg 309 drivers/usb/gadget/udc/pxa25x_udc.c writel(val, dev->regs + reg); reg 312 drivers/usb/gadget/udc/pxa25x_udc.c static inline u32 udc_get_reg(struct pxa25x_udc *dev, u32 reg) reg 314 drivers/usb/gadget/udc/pxa25x_udc.c return readl(dev->regs + reg); reg 180 drivers/usb/gadget/udc/pxa27x_udc.h #define udc_ep_readl(ep, reg) \ reg 181 drivers/usb/gadget/udc/pxa27x_udc.h __raw_readl((ep)->dev->regs + ofs_##reg(ep)) reg 182 drivers/usb/gadget/udc/pxa27x_udc.h #define udc_ep_writel(ep, reg, value) \ reg 183 drivers/usb/gadget/udc/pxa27x_udc.h __raw_writel((value), ep->dev->regs + ofs_##reg(ep)) reg 184 drivers/usb/gadget/udc/pxa27x_udc.h #define udc_ep_readb(ep, reg) \ reg 185 drivers/usb/gadget/udc/pxa27x_udc.h __raw_readb((ep)->dev->regs + ofs_##reg(ep)) reg 186 drivers/usb/gadget/udc/pxa27x_udc.h #define udc_ep_writeb(ep, reg, value) \ reg 187 drivers/usb/gadget/udc/pxa27x_udc.h __raw_writeb((value), ep->dev->regs + ofs_##reg(ep)) reg 188 drivers/usb/gadget/udc/pxa27x_udc.h #define udc_readl(dev, reg) \ reg 189 drivers/usb/gadget/udc/pxa27x_udc.h __raw_readl((dev)->regs + (reg)) reg 190 drivers/usb/gadget/udc/pxa27x_udc.h #define udc_writel(udc, reg, value) \ reg 191 drivers/usb/gadget/udc/pxa27x_udc.h __raw_writel((value), (udc)->regs + (reg)) reg 51 drivers/usb/gadget/udc/r8a66597-udc.c unsigned long reg) reg 58 drivers/usb/gadget/udc/r8a66597-udc.c r8a66597_bset(r8a66597, (1 << pipenum), reg); reg 63 drivers/usb/gadget/udc/r8a66597-udc.c unsigned long reg) reg 70 drivers/usb/gadget/udc/r8a66597-udc.c r8a66597_bclr(r8a66597, (1 << pipenum), reg); reg 1843 drivers/usb/gadget/udc/r8a66597-udc.c void __iomem *reg = NULL; reg 1850 drivers/usb/gadget/udc/r8a66597-udc.c reg = devm_ioremap_resource(&pdev->dev, res); reg 1851 drivers/usb/gadget/udc/r8a66597-udc.c if (IS_ERR(reg)) reg 1852 drivers/usb/gadget/udc/r8a66597-udc.c return PTR_ERR(reg); reg 1878 drivers/usb/gadget/udc/r8a66597-udc.c r8a66597->reg = reg; reg 86 drivers/usb/gadget/udc/r8a66597-udc.h void __iomem *reg; reg 124 drivers/usb/gadget/udc/r8a66597-udc.h return ioread16(r8a66597->reg + offset); reg 132 drivers/usb/gadget/udc/r8a66597-udc.h void __iomem *fifoaddr = r8a66597->reg + offset; reg 176 drivers/usb/gadget/udc/r8a66597-udc.h iowrite16(val, r8a66597->reg + offset); reg 199 drivers/usb/gadget/udc/r8a66597-udc.h void __iomem *fifoaddr = r8a66597->reg + ep->fifoaddr; reg 332 drivers/usb/gadget/udc/renesas_usb3.c void __iomem *reg; reg 398 drivers/usb/gadget/udc/renesas_usb3.c iowrite32(data, usb3->reg + offs); reg 403 drivers/usb/gadget/udc/renesas_usb3.c return ioread32(usb3->reg + offs); reg 422 drivers/usb/gadget/udc/renesas_usb3.c static int usb3_wait(struct renesas_usb3 *usb3, u32 reg, u32 mask, reg 428 drivers/usb/gadget/udc/renesas_usb3.c if ((usb3_read(usb3, reg) & mask) == expected) reg 434 drivers/usb/gadget/udc/renesas_usb3.c __func__, reg, mask, expected); reg 1095 drivers/usb/gadget/udc/renesas_usb3.c iowrite32_rep(usb3->reg + fifo_reg, buf, len / 4); reg 1140 drivers/usb/gadget/udc/renesas_usb3.c ioread32_rep(usb3->reg + fifo_reg, buf, len / 4); reg 2756 drivers/usb/gadget/udc/renesas_usb3.c usb3->reg = devm_ioremap_resource(&pdev->dev, res); reg 2757 drivers/usb/gadget/udc/renesas_usb3.c if (IS_ERR(usb3->reg)) reg 2758 drivers/usb/gadget/udc/renesas_usb3.c return PTR_ERR(usb3->reg); reg 64 drivers/usb/gadget/udc/s3c2410_udc.c static inline u32 udc_read(u32 reg) reg 66 drivers/usb/gadget/udc/s3c2410_udc.c return readb(base_addr + reg); reg 69 drivers/usb/gadget/udc/s3c2410_udc.c static inline void udc_write(u32 value, u32 reg) reg 71 drivers/usb/gadget/udc/s3c2410_udc.c writeb(value, base_addr + reg); reg 74 drivers/usb/gadget/udc/s3c2410_udc.c static inline void udc_writeb(void __iomem *base, u32 value, u32 reg) reg 76 drivers/usb/gadget/udc/s3c2410_udc.c writeb(value, base + reg); reg 1531 drivers/usb/gadget/udc/snps_udc_core.c u32 reg; reg 1583 drivers/usb/gadget/udc/snps_udc_core.c reg = readl(&dev->ep[tmp].regs->ctl); reg 1584 drivers/usb/gadget/udc/snps_udc_core.c reg |= AMD_BIT(UDC_EPCTL_SNAK); reg 1585 drivers/usb/gadget/udc/snps_udc_core.c writel(reg, &dev->ep[tmp].regs->ctl); reg 2027 drivers/usb/gadget/udc/snps_udc_core.c u32 reg; reg 2035 drivers/usb/gadget/udc/snps_udc_core.c reg = readl(&dev->ep[tmp].regs->ctl); reg 2036 drivers/usb/gadget/udc/snps_udc_core.c reg |= AMD_BIT(UDC_EPCTL_CNAK); reg 2037 drivers/usb/gadget/udc/snps_udc_core.c writel(reg, &dev->ep[tmp].regs->ctl); reg 2046 drivers/usb/gadget/udc/snps_udc_core.c reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl); reg 2047 drivers/usb/gadget/udc/snps_udc_core.c reg |= AMD_BIT(UDC_EPCTL_CNAK); reg 2048 drivers/usb/gadget/udc/snps_udc_core.c writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl); reg 2999 drivers/usb/gadget/udc/snps_udc_core.c u32 reg; reg 3007 drivers/usb/gadget/udc/snps_udc_core.c reg = readl(&dev->regs->ep_irqsts); reg 3008 drivers/usb/gadget/udc/snps_udc_core.c if (reg) { reg 3009 drivers/usb/gadget/udc/snps_udc_core.c if (reg & AMD_BIT(UDC_EPINT_OUT_EP0)) reg 3011 drivers/usb/gadget/udc/snps_udc_core.c if (reg & AMD_BIT(UDC_EPINT_IN_EP0)) reg 3020 drivers/usb/gadget/udc/snps_udc_core.c if (!(reg & ep_irq) || i == UDC_EPINT_OUT_EP0) reg 3037 drivers/usb/gadget/udc/snps_udc_core.c reg = readl(&dev->regs->irqsts); reg 3038 drivers/usb/gadget/udc/snps_udc_core.c if (reg) { reg 3040 drivers/usb/gadget/udc/snps_udc_core.c writel(reg, &dev->regs->irqsts); reg 3041 drivers/usb/gadget/udc/snps_udc_core.c ret_val |= udc_dev_isr(dev, reg); reg 3157 drivers/usb/gadget/udc/snps_udc_core.c u32 reg; reg 3203 drivers/usb/gadget/udc/snps_udc_core.c reg = readl(&dev->regs->ctl); reg 3204 drivers/usb/gadget/udc/snps_udc_core.c reg |= AMD_BIT(UDC_DEVCTL_SD); reg 3205 drivers/usb/gadget/udc/snps_udc_core.c writel(reg, &dev->regs->ctl); reg 36 drivers/usb/gadget/udc/snps_udc_plat.c u32 reg; reg 41 drivers/usb/gadget/udc/snps_udc_plat.c reg = readl(&udc->regs->ctl); reg 42 drivers/usb/gadget/udc/snps_udc_plat.c reg |= AMD_BIT(UDC_DEVCTL_SRX_FLUSH); reg 43 drivers/usb/gadget/udc/snps_udc_plat.c writel(reg, &udc->regs->ctl); reg 45 drivers/usb/gadget/udc/snps_udc_plat.c reg = readl(&udc->regs->ctl); reg 46 drivers/usb/gadget/udc/snps_udc_plat.c reg &= ~(AMD_BIT(UDC_DEVCTL_SRX_FLUSH)); reg 47 drivers/usb/gadget/udc/snps_udc_plat.c writel(reg, &udc->regs->ctl); reg 321 drivers/usb/gadget/udc/udc-xilinx.c u32 reg; reg 338 drivers/usb/gadget/udc/udc-xilinx.c reg = udc->read_fn(udc->addr + XUSB_DMA_STATUS_OFFSET); reg 339 drivers/usb/gadget/udc/udc-xilinx.c if (!(reg & XUSB_DMA_DMASR_BUSY)) reg 50 drivers/usb/host/bcma-hcd.c static int bcma_wait_bits(struct bcma_device *dev, u16 reg, u32 bitmask, reg 57 drivers/usb/host/bcma-hcd.c val = bcma_read32(dev, reg); reg 36 drivers/usb/host/ehci-hub.c u32 __iomem *reg; reg 59 drivers/usb/host/ehci-hub.c reg = &ehci->regs->port_status[port]; reg 60 drivers/usb/host/ehci-hub.c status = ehci_readl(ehci, reg) & ~PORT_RWC_BITS; reg 73 drivers/usb/host/ehci-hub.c reg = &ehci->regs->port_status[port]; reg 74 drivers/usb/host/ehci-hub.c status = ehci_readl(ehci, reg) & ~PORT_RWC_BITS; reg 80 drivers/usb/host/ehci-hub.c ehci_writel(ehci, status & ~PORT_PE, reg); reg 110 drivers/usb/host/ehci-hub.c reg = &ehci->regs->port_status[port]; reg 111 drivers/usb/host/ehci-hub.c status = ehci_readl(ehci, reg) & ~PORT_RWC_BITS; reg 113 drivers/usb/host/ehci-hub.c ehci_writel(ehci, status | PORT_CSC, reg); reg 117 drivers/usb/host/ehci-hub.c ehci_writel(ehci, status & ~PORT_PE, reg); reg 179 drivers/usb/host/ehci-hub.c u32 __iomem *reg = &ehci->regs->port_status[port]; reg 180 drivers/usb/host/ehci-hub.c u32 t1 = ehci_readl(ehci, reg) & ~PORT_RWC_BITS; reg 192 drivers/usb/host/ehci-hub.c ehci_writel(ehci, t2, reg); reg 258 drivers/usb/host/ehci-hub.c u32 __iomem *reg = &ehci->regs->port_status [port]; reg 259 drivers/usb/host/ehci-hub.c u32 t1 = ehci_readl(ehci, reg) & ~PORT_RWC_BITS; reg 294 drivers/usb/host/ehci-hub.c ehci_writel(ehci, t2, reg); reg 1327 drivers/usb/host/ehci-hub.c u32 __iomem *reg; reg 1331 drivers/usb/host/ehci-hub.c reg = &ehci->regs->port_status[portnum - 1]; reg 1332 drivers/usb/host/ehci-hub.c return ehci_readl(ehci, reg) & PORT_OWNER; reg 60 drivers/usb/host/ehci-omap.c static inline void ehci_write(void __iomem *base, u32 reg, u32 val) reg 62 drivers/usb/host/ehci-omap.c __raw_writel(val, base + reg); reg 65 drivers/usb/host/ehci-omap.c static inline u32 ehci_read(void __iomem *base, u32 reg) reg 67 drivers/usb/host/ehci-omap.c return __raw_readl(base + reg); reg 308 drivers/usb/host/fsl-mph-dr-of.c u32 reg = 0; reg 311 drivers/usb/host/fsl-mph-dr-of.c reg |= GC_PPP; reg 314 drivers/usb/host/fsl-mph-dr-of.c reg |= GC_PFP; reg 317 drivers/usb/host/fsl-mph-dr-of.c out_be32(pdata->regs + USBGENCTRL, reg); reg 77 drivers/usb/host/imx21-hcd.c void __iomem *reg = imx21->regs + offset; reg 78 drivers/usb/host/imx21-hcd.c writel(readl(reg) | mask, reg); reg 84 drivers/usb/host/imx21-hcd.c void __iomem *reg = imx21->regs + offset; reg 85 drivers/usb/host/imx21-hcd.c writel(readl(reg) & ~mask, reg); reg 90 drivers/usb/host/imx21-hcd.c void __iomem *reg = imx21->regs + offset; reg 92 drivers/usb/host/imx21-hcd.c if (readl(reg) & mask) reg 93 drivers/usb/host/imx21-hcd.c writel(mask, reg); reg 98 drivers/usb/host/imx21-hcd.c void __iomem *reg = imx21->regs + offset; reg 100 drivers/usb/host/imx21-hcd.c if (!(readl(reg) & mask)) reg 101 drivers/usb/host/imx21-hcd.c writel(mask, reg); reg 946 drivers/usb/host/isp116x-hcd.c u32 reg = isp116x->rhdesca; reg 951 drivers/usb/host/isp116x-hcd.c desc->bNbrPorts = (u8) (reg & 0x3); reg 953 drivers/usb/host/isp116x-hcd.c desc->wHubCharacteristics = cpu_to_le16((u16) ((reg >> 8) & reg 957 drivers/usb/host/isp116x-hcd.c desc->bPwrOn2PwrGood = (u8) ((reg >> 24) & 0xff); reg 358 drivers/usb/host/isp116x.h static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg) reg 360 drivers/usb/host/isp116x.h writew(reg & 0xff, isp116x->addr_reg); reg 416 drivers/usb/host/isp116x.h static u16 isp116x_read_reg16(struct isp116x *isp116x, unsigned reg) reg 418 drivers/usb/host/isp116x.h isp116x_write_addr(isp116x, reg); reg 422 drivers/usb/host/isp116x.h static u32 isp116x_read_reg32(struct isp116x *isp116x, unsigned reg) reg 424 drivers/usb/host/isp116x.h isp116x_write_addr(isp116x, reg); reg 428 drivers/usb/host/isp116x.h static void isp116x_write_reg16(struct isp116x *isp116x, unsigned reg, reg 431 drivers/usb/host/isp116x.h isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET); reg 435 drivers/usb/host/isp116x.h static void isp116x_write_reg32(struct isp116x *isp116x, unsigned reg, reg 438 drivers/usb/host/isp116x.h isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET); reg 1539 drivers/usb/host/isp1362-hcd.c u32 reg = isp1362_hcd->rhdesca; reg 1546 drivers/usb/host/isp1362-hcd.c desc->bNbrPorts = reg & 0x3; reg 1548 drivers/usb/host/isp1362-hcd.c desc->wHubCharacteristics = cpu_to_le16((reg >> 8) & reg 1554 drivers/usb/host/isp1362-hcd.c desc->bPwrOn2PwrGood = (reg >> 24) & 0xff; reg 586 drivers/usb/host/isp1362.h static void isp1362_write_addr(struct isp1362_hcd *isp1362_hcd, isp1362_reg_t reg) reg 588 drivers/usb/host/isp1362.h REG_ACCESS_TEST(reg); reg 590 drivers/usb/host/isp1362.h writew(ISP1362_REG_NO(reg), isp1362_hcd->addr_reg); reg 353 drivers/usb/host/max3421-hcd.c spi_rd8(struct usb_hcd *hcd, unsigned int reg) reg 365 drivers/usb/host/max3421-hcd.c (field(reg, MAX3421_SPI_REG_SHIFT) | reg 379 drivers/usb/host/max3421-hcd.c spi_wr8(struct usb_hcd *hcd, unsigned int reg, u8 val) reg 391 drivers/usb/host/max3421-hcd.c (field(reg, MAX3421_SPI_REG_SHIFT) | reg 403 drivers/usb/host/max3421-hcd.c spi_rd_buf(struct usb_hcd *hcd, unsigned int reg, void *buf, size_t len) reg 415 drivers/usb/host/max3421-hcd.c (field(reg, MAX3421_SPI_REG_SHIFT) | reg 429 drivers/usb/host/max3421-hcd.c spi_wr_buf(struct usb_hcd *hcd, unsigned int reg, void *buf, size_t len) reg 441 drivers/usb/host/max3421-hcd.c (field(reg, MAX3421_SPI_REG_SHIFT) | reg 679 drivers/usb/host/oxu210hp-hcd.c static inline u32 oxu_readl(void *base, u32 reg) reg 681 drivers/usb/host/oxu210hp-hcd.c return readl(base + reg); reg 684 drivers/usb/host/oxu210hp-hcd.c static inline void oxu_writel(void *base, u32 reg, u32 val) reg 686 drivers/usb/host/oxu210hp-hcd.c writel(val, base + reg); reg 3885 drivers/usb/host/oxu210hp-hcd.c u32 __iomem *reg = &oxu->regs->port_status[port]; reg 3886 drivers/usb/host/oxu210hp-hcd.c u32 t1 = readl(reg) & ~PORT_RWC_BITS; reg 3905 drivers/usb/host/oxu210hp-hcd.c writel(t2, reg); reg 551 drivers/usb/host/pci-quirks.c u16 reg; reg 588 drivers/usb/host/pci-quirks.c reg = PT4_P2_REG; reg 591 drivers/usb/host/pci-quirks.c reg = PT4_P1_REG; reg 602 drivers/usb/host/pci-quirks.c reg = PT2_P2_REG; reg 605 drivers/usb/host/pci-quirks.c reg = PT2_P1_REG; reg 616 drivers/usb/host/pci-quirks.c reg = PT1_P2_REG; reg 619 drivers/usb/host/pci-quirks.c reg = PT1_P1_REG; reg 626 drivers/usb/host/pci-quirks.c pci_write_config_word(pdev, PT_ADDR_INDX, reg); reg 46 drivers/usb/host/r8a66597-hcd.c unsigned long reg) reg 52 drivers/usb/host/r8a66597-hcd.c r8a66597_bset(r8a66597, 1 << pipenum, reg); reg 58 drivers/usb/host/r8a66597-hcd.c unsigned long reg) reg 64 drivers/usb/host/r8a66597-hcd.c r8a66597_bclr(r8a66597, 1 << pipenum, reg); reg 434 drivers/usb/host/r8a66597-hcd.c static void r8a66597_reg_wait(struct r8a66597 *r8a66597, unsigned long reg, reg 441 drivers/usb/host/r8a66597-hcd.c tmp = r8a66597_read(r8a66597, reg); reg 444 drivers/usb/host/r8a66597-hcd.c "is timeout\n", reg, loop); reg 2392 drivers/usb/host/r8a66597-hcd.c iounmap(r8a66597->reg); reg 2404 drivers/usb/host/r8a66597-hcd.c void __iomem *reg = NULL; reg 2432 drivers/usb/host/r8a66597-hcd.c reg = ioremap(res->start, resource_size(res)); reg 2433 drivers/usb/host/r8a66597-hcd.c if (reg == NULL) { reg 2473 drivers/usb/host/r8a66597-hcd.c r8a66597->reg = reg; reg 2509 drivers/usb/host/r8a66597-hcd.c if (reg) reg 2510 drivers/usb/host/r8a66597-hcd.c iounmap(reg); reg 107 drivers/usb/host/r8a66597.h void __iomem *reg; reg 162 drivers/usb/host/r8a66597.h return ioread16(r8a66597->reg + offset); reg 169 drivers/usb/host/r8a66597.h void __iomem *fifoaddr = r8a66597->reg + offset; reg 190 drivers/usb/host/r8a66597.h iowrite16(val, r8a66597->reg + offset); reg 212 drivers/usb/host/r8a66597.h void __iomem *fifoaddr = r8a66597->reg + pipe->fifoaddr; reg 198 drivers/usb/host/sl811.h static inline u8 sl811_read(struct sl811 *sl811, int reg) reg 200 drivers/usb/host/sl811.h writeb(reg, sl811->addr_reg); reg 204 drivers/usb/host/sl811.h static inline void sl811_write(struct sl811 *sl811, int reg, u8 val) reg 206 drivers/usb/host/sl811.h writeb(reg, sl811->addr_reg); reg 514 drivers/usb/host/uhci-hcd.h static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg) reg 516 drivers/usb/host/uhci-hcd.h return inl(uhci->io_addr + reg); reg 519 drivers/usb/host/uhci-hcd.h static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg) reg 521 drivers/usb/host/uhci-hcd.h outl(val, uhci->io_addr + reg); reg 524 drivers/usb/host/uhci-hcd.h static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg) reg 526 drivers/usb/host/uhci-hcd.h return inw(uhci->io_addr + reg); reg 529 drivers/usb/host/uhci-hcd.h static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg) reg 531 drivers/usb/host/uhci-hcd.h outw(val, uhci->io_addr + reg); reg 534 drivers/usb/host/uhci-hcd.h static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg) reg 536 drivers/usb/host/uhci-hcd.h return inb(uhci->io_addr + reg); reg 539 drivers/usb/host/uhci-hcd.h static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg) reg 541 drivers/usb/host/uhci-hcd.h outb(val, uhci->io_addr + reg); reg 561 drivers/usb/host/uhci-hcd.h static inline int uhci_aspeed_reg(unsigned int reg) reg 563 drivers/usb/host/uhci-hcd.h switch (reg) { reg 585 drivers/usb/host/uhci-hcd.h pr_warn("UHCI: Unsupported register 0x%02x on Aspeed\n", reg); reg 591 drivers/usb/host/uhci-hcd.h static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg) reg 594 drivers/usb/host/uhci-hcd.h return inl(uhci->io_addr + reg); reg 596 drivers/usb/host/uhci-hcd.h return readl(uhci->regs + uhci_aspeed_reg(reg)); reg 599 drivers/usb/host/uhci-hcd.h return readl_be(uhci->regs + reg); reg 602 drivers/usb/host/uhci-hcd.h return readl(uhci->regs + reg); reg 605 drivers/usb/host/uhci-hcd.h static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg) reg 608 drivers/usb/host/uhci-hcd.h outl(val, uhci->io_addr + reg); reg 610 drivers/usb/host/uhci-hcd.h writel(val, uhci->regs + uhci_aspeed_reg(reg)); reg 613 drivers/usb/host/uhci-hcd.h writel_be(val, uhci->regs + reg); reg 616 drivers/usb/host/uhci-hcd.h writel(val, uhci->regs + reg); reg 619 drivers/usb/host/uhci-hcd.h static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg) reg 622 drivers/usb/host/uhci-hcd.h return inw(uhci->io_addr + reg); reg 624 drivers/usb/host/uhci-hcd.h return readl(uhci->regs + uhci_aspeed_reg(reg)); reg 627 drivers/usb/host/uhci-hcd.h return readw_be(uhci->regs + reg); reg 630 drivers/usb/host/uhci-hcd.h return readw(uhci->regs + reg); reg 633 drivers/usb/host/uhci-hcd.h static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg) reg 636 drivers/usb/host/uhci-hcd.h outw(val, uhci->io_addr + reg); reg 638 drivers/usb/host/uhci-hcd.h writel(val, uhci->regs + uhci_aspeed_reg(reg)); reg 641 drivers/usb/host/uhci-hcd.h writew_be(val, uhci->regs + reg); reg 644 drivers/usb/host/uhci-hcd.h writew(val, uhci->regs + reg); reg 647 drivers/usb/host/uhci-hcd.h static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg) reg 650 drivers/usb/host/uhci-hcd.h return inb(uhci->io_addr + reg); reg 652 drivers/usb/host/uhci-hcd.h return readl(uhci->regs + uhci_aspeed_reg(reg)); reg 655 drivers/usb/host/uhci-hcd.h return readb_be(uhci->regs + reg); reg 658 drivers/usb/host/uhci-hcd.h return readb(uhci->regs + reg); reg 661 drivers/usb/host/uhci-hcd.h static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg) reg 664 drivers/usb/host/uhci-hcd.h outb(val, uhci->io_addr + reg); reg 666 drivers/usb/host/uhci-hcd.h writel(val, uhci->regs + uhci_aspeed_reg(reg)); reg 669 drivers/usb/host/uhci-hcd.h writeb_be(val, uhci->regs + reg); reg 672 drivers/usb/host/uhci-hcd.h writeb(val, uhci->regs + reg); reg 833 drivers/usb/host/xhci-dbgcap.c u32 reg; reg 851 drivers/usb/host/xhci-dbgcap.c reg = readl(&dbc->regs->control); reg 852 drivers/usb/host/xhci-dbgcap.c if (reg & DBC_CTRL_DBC_ENABLE) { reg 295 drivers/usb/host/xhci-mtk.c u32 reg, msk, val; reg 299 drivers/usb/host/xhci-mtk.c reg = mtk->uwk_reg_base + PERI_WK_CTRL1; reg 304 drivers/usb/host/xhci-mtk.c reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL; reg 311 drivers/usb/host/xhci-mtk.c regmap_update_bits(mtk->uwk, reg, msk, val); reg 420 drivers/usb/host/xhci-pci.c void __iomem *reg; reg 424 drivers/usb/host/xhci-pci.c reg = (void __iomem *) xhci->cap_regs + reg 429 drivers/usb/host/xhci-pci.c val = readl(reg) & ~PROG_DONE; reg 430 drivers/usb/host/xhci-pci.c writel(val, reg); reg 433 drivers/usb/host/xhci-pci.c val = readl(reg); reg 438 drivers/usb/host/xhci-pci.c writel(val, reg); reg 441 drivers/usb/host/xhci-pci.c val = readl(reg) | PROG_DONE; reg 442 drivers/usb/host/xhci-pci.c writel(val, reg); reg 443 drivers/usb/host/xhci-pci.c readl(reg); reg 454 drivers/usb/host/xhci-pci.c void __iomem *reg; reg 457 drivers/usb/host/xhci-pci.c reg = (void __iomem *) xhci->cap_regs + 0x80a4; reg 458 drivers/usb/host/xhci-pci.c val = readl(reg); reg 459 drivers/usb/host/xhci-pci.c writel(val | BIT(28), reg); reg 460 drivers/usb/host/xhci-pci.c readl(reg); reg 55 drivers/usb/isp1760/isp1760-core.h static inline u32 isp1760_read32(void __iomem *base, u32 reg) reg 57 drivers/usb/isp1760/isp1760-core.h return readl(base + reg); reg 60 drivers/usb/isp1760/isp1760-core.h static inline void isp1760_write32(void __iomem *base, u32 reg, u32 val) reg 62 drivers/usb/isp1760/isp1760-core.h writel(val, base + reg); reg 163 drivers/usb/isp1760/isp1760-hcd.c static u32 reg_read32(void __iomem *base, u32 reg) reg 165 drivers/usb/isp1760/isp1760-hcd.c return isp1760_read32(base, reg); reg 168 drivers/usb/isp1760/isp1760-hcd.c static void reg_write32(void __iomem *base, u32 reg, u32 val) reg 170 drivers/usb/isp1760/isp1760-hcd.c isp1760_write32(base, reg, val); reg 379 drivers/usb/isp1760/isp1760-hcd.c static int handshake(struct usb_hcd *hcd, u32 reg, reg 385 drivers/usb/isp1760/isp1760-hcd.c result = reg_read32(hcd->regs, reg); reg 48 drivers/usb/isp1760/isp1760-udc.c static inline u32 isp1760_udc_read(struct isp1760_udc *udc, u16 reg) reg 50 drivers/usb/isp1760/isp1760-udc.c return isp1760_read32(udc->regs, reg); reg 53 drivers/usb/isp1760/isp1760-udc.c static inline void isp1760_udc_write(struct isp1760_udc *udc, u16 reg, u32 val) reg 55 drivers/usb/isp1760/isp1760-udc.c isp1760_write32(udc->regs, reg, val); reg 2163 drivers/usb/misc/ftdi-elan.c int reg = 0; reg 2164 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_read_config(ftdi, activePCIfn | reg, 0, reg 2398 drivers/usb/misc/ftdi-elan.c int reg = 0; reg 2403 drivers/usb/misc/ftdi-elan.c reg = 16; reg 2404 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_write_config(ftdi, activePCIfn | reg, 0, reg 2408 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_read_config(ftdi, activePCIfn | reg, 0, reg 2412 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_write_config(ftdi, activePCIfn | reg, 0, reg 2416 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_read_config(ftdi, activePCIfn | reg, 0, reg 2420 drivers/usb/misc/ftdi-elan.c reg = 12; reg 2421 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_read_config(ftdi, activePCIfn | reg, 0, reg 2427 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_write_config(ftdi, activePCIfn | reg, 0x00, reg 2431 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_read_config(ftdi, activePCIfn | reg, 0, reg 2435 drivers/usb/misc/ftdi-elan.c reg = 4; reg 2436 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_write_config(ftdi, activePCIfn | reg, 0x00, reg 2440 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_read_config(ftdi, activePCIfn | reg, 0, reg 2444 drivers/usb/misc/ftdi-elan.c for (reg = 0; reg <= 0x54; reg += 4) { reg 2445 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_read_pcimem(ftdi, reg, 0, &pcidata); reg 2457 drivers/usb/misc/ftdi-elan.c int reg = 0; reg 2462 drivers/usb/misc/ftdi-elan.c reg = 16; reg 2463 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_write_config(ftdi, activePCIfn | reg, 0, reg 2467 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_read_config(ftdi, activePCIfn | reg, 0, reg 2471 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_write_config(ftdi, activePCIfn | reg, 0, reg 2475 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_read_config(ftdi, activePCIfn | reg, 0, reg 2479 drivers/usb/misc/ftdi-elan.c reg = 12; reg 2480 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_read_config(ftdi, activePCIfn | reg, 0, reg 2486 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_write_config(ftdi, activePCIfn | reg, 0x00, reg 2490 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_read_config(ftdi, activePCIfn | reg, 0, reg 2494 drivers/usb/misc/ftdi-elan.c reg = 4; reg 2495 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_write_config(ftdi, activePCIfn | reg, 0x00, reg 2499 drivers/usb/misc/ftdi-elan.c return ftdi_elan_read_config(ftdi, activePCIfn | reg, 0, &pcidata); reg 2571 drivers/usb/misc/ftdi-elan.c int reg = 0; reg 2583 drivers/usb/misc/ftdi-elan.c UxxxStatus = ftdi_elan_read_config(ftdi, activePCIfn | reg, 0, reg 51 drivers/usb/misc/uss720.c __u8 reg[7]; /* USB registers */ reg 63 drivers/usb/misc/uss720.c __u8 reg[7]; reg 109 drivers/usb/misc/uss720.c memcpy(priv->reg, rq->reg, sizeof(priv->reg)); reg 112 drivers/usb/misc/uss720.c priv->reg); reg 115 drivers/usb/misc/uss720.c if (rq->reg[2] & rq->reg[1] & 0x10 && pp) reg 158 drivers/usb/misc/uss720.c rq->dr->wLength = cpu_to_le16((request == 3) ? sizeof(rq->reg) : 0); reg 161 drivers/usb/misc/uss720.c (request == 3) ? rq->reg : NULL, (request == 3) ? sizeof(rq->reg) : 0, async_complete, rq); reg 192 drivers/usb/misc/uss720.c static int get_1284_register(struct parport *pp, unsigned char reg, unsigned char *val, gfp_t mem_flags) reg 204 drivers/usb/misc/uss720.c rq = submit_async_request(priv, 3, 0xc0, ((unsigned int)reg) << 8, 0, mem_flags); reg 207 drivers/usb/misc/uss720.c (unsigned int)reg); reg 216 drivers/usb/misc/uss720.c *val = priv->reg[(reg >= 9) ? 0 : regindex[reg]]; reg 228 drivers/usb/misc/uss720.c static int set_1284_register(struct parport *pp, unsigned char reg, unsigned char val, gfp_t mem_flags) reg 236 drivers/usb/misc/uss720.c rq = submit_async_request(priv, 4, 0x40, (((unsigned int)reg) << 8) | val, 0, mem_flags); reg 239 drivers/usb/misc/uss720.c (unsigned int)reg, (unsigned int)val); reg 260 drivers/usb/misc/uss720.c __u8 reg; reg 262 drivers/usb/misc/uss720.c if (get_1284_register(pp, 6, ®, GFP_KERNEL)) reg 265 drivers/usb/misc/uss720.c mode = (priv->reg[2] >> 5) & 0x7; reg 273 drivers/usb/misc/uss720.c if (m <= ECR_PS2 && !(priv->reg[1] & 0x20)) { reg 282 drivers/usb/misc/uss720.c if (get_1284_register(pp, 6, ®, GFP_KERNEL)) reg 284 drivers/usb/misc/uss720.c if (priv->reg[2] & 0x01) reg 298 drivers/usb/misc/uss720.c if (get_1284_register(pp, 6, ®, GFP_KERNEL)) reg 326 drivers/usb/misc/uss720.c memcpy(priv->reg, buffer, 4); reg 328 drivers/usb/misc/uss720.c if (priv->reg[2] & priv->reg[1] & 0x10) reg 352 drivers/usb/misc/uss720.c d = (d & 0xf) | (priv->reg[1] & 0xf0); reg 355 drivers/usb/misc/uss720.c priv->reg[1] = d; reg 361 drivers/usb/misc/uss720.c return priv->reg[1] & 0xf; /* Use soft copy */ reg 371 drivers/usb/misc/uss720.c d = (priv->reg[1] & (~mask)) ^ val; reg 374 drivers/usb/misc/uss720.c priv->reg[1] = d; reg 392 drivers/usb/misc/uss720.c d = priv->reg[1] & ~0x10; reg 395 drivers/usb/misc/uss720.c priv->reg[1] = d; reg 403 drivers/usb/misc/uss720.c d = priv->reg[1] | 0x10; reg 406 drivers/usb/misc/uss720.c priv->reg[1] = d; reg 414 drivers/usb/misc/uss720.c d = priv->reg[1] & ~0x20; reg 417 drivers/usb/misc/uss720.c priv->reg[1] = d; reg 425 drivers/usb/misc/uss720.c d = priv->reg[1] | 0x20; reg 428 drivers/usb/misc/uss720.c priv->reg[1] = d; reg 445 drivers/usb/misc/uss720.c s->u.pc.ctr = priv->reg[1]; reg 446 drivers/usb/misc/uss720.c s->u.pc.ecr = priv->reg[2]; reg 456 drivers/usb/misc/uss720.c priv->reg[1] = s->u.pc.ctr; reg 457 drivers/usb/misc/uss720.c priv->reg[2] = s->u.pc.ecr; reg 471 drivers/usb/misc/uss720.c if (priv->reg[0] & 0x01) { reg 494 drivers/usb/misc/uss720.c if (priv->reg[0] & 0x01) { reg 530 drivers/usb/misc/uss720.c if (priv->reg[0] & 0x01) { reg 552 drivers/usb/misc/uss720.c if (priv->reg[0] & 0x01) { reg 678 drivers/usb/misc/uss720.c unsigned char reg; reg 728 drivers/usb/misc/uss720.c get_1284_register(pp, 0, ®, GFP_KERNEL); reg 729 drivers/usb/misc/uss720.c dev_dbg(&intf->dev, "reg: %7ph\n", priv->reg); reg 43 drivers/usb/mtu3/mtu3_host.c u32 reg, msk, val; reg 47 drivers/usb/mtu3/mtu3_host.c reg = ssusb->uwk_reg_base + PERI_WK_CTRL1; reg 52 drivers/usb/mtu3/mtu3_host.c reg = ssusb->uwk_reg_base + PERI_SSUSB_SPM_CTRL; reg 59 drivers/usb/mtu3/mtu3_host.c regmap_update_bits(ssusb->uwk, reg, msk, val); reg 129 drivers/usb/musb/musb_core.c static int musb_ulpi_read(struct usb_phy *phy, u32 reg) reg 148 drivers/usb/musb/musb_core.c musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg); reg 173 drivers/usb/musb/musb_core.c static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg) reg 188 drivers/usb/musb/musb_core.c musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg); reg 489 drivers/usb/musb/musb_core.c u8 reg; reg 506 drivers/usb/musb/musb_core.c reg = musb_readb(mbase, MUSB_POWER); reg 507 drivers/usb/musb/musb_core.c reg |= MUSB_POWER_SUSPENDM; reg 508 drivers/usb/musb/musb_core.c musb_writeb(mbase, MUSB_POWER, reg); reg 1458 drivers/usb/musb/musb_core.c u8 reg; reg 1466 drivers/usb/musb/musb_core.c reg = musb_read_configdata(mbase); reg 1468 drivers/usb/musb/musb_core.c strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); reg 1469 drivers/usb/musb/musb_core.c if (reg & MUSB_CONFIGDATA_DYNFIFO) { reg 1473 drivers/usb/musb/musb_core.c if (reg & MUSB_CONFIGDATA_MPRXE) { reg 1477 drivers/usb/musb/musb_core.c if (reg & MUSB_CONFIGDATA_MPTXE) { reg 1481 drivers/usb/musb/musb_core.c if (reg & MUSB_CONFIGDATA_HBRXE) { reg 1485 drivers/usb/musb/musb_core.c if (reg & MUSB_CONFIGDATA_HBTXE) { reg 1489 drivers/usb/musb/musb_core.c if (reg & MUSB_CONFIGDATA_SOFTCONE) reg 1492 drivers/usb/musb/musb_core.c pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo); reg 447 drivers/usb/musb/musb_core.h u8 reg = 0; reg 450 drivers/usb/musb/musb_core.h reg = musb_readb(mbase, musb->io.ep_offset(epnum, MUSB_FIFOSIZE)); reg 452 drivers/usb/musb/musb_core.h if (!reg) reg 458 drivers/usb/musb/musb_core.h hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f); reg 461 drivers/usb/musb/musb_core.h if ((reg & 0xf0) == 0xf0) { reg 466 drivers/usb/musb/musb_core.h hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4); reg 235 drivers/usb/musb/musb_debugfs.c u8 reg; reg 243 drivers/usb/musb/musb_debugfs.c reg = musb_readb(musb->mregs, MUSB_DEVCTL); reg 244 drivers/usb/musb/musb_debugfs.c connect = reg & MUSB_DEVCTL_SESSION ? 1 : 0; reg 269 drivers/usb/musb/musb_debugfs.c u8 reg; reg 281 drivers/usb/musb/musb_debugfs.c reg = musb_readb(musb->mregs, MUSB_DEVCTL); reg 282 drivers/usb/musb/musb_debugfs.c reg &= ~MUSB_DEVCTL_SESSION; reg 283 drivers/usb/musb/musb_debugfs.c musb_writeb(musb->mregs, MUSB_DEVCTL, reg); reg 298 drivers/usb/musb/musb_debugfs.c reg = musb_readb(musb->mregs, MUSB_DEVCTL); reg 299 drivers/usb/musb/musb_debugfs.c reg |= MUSB_DEVCTL_SESSION; reg 300 drivers/usb/musb/musb_debugfs.c musb_writeb(musb->mregs, MUSB_DEVCTL, reg); reg 516 drivers/usb/musb/musb_dsps.c u32 reg; reg 518 drivers/usb/musb/musb_dsps.c reg = musb_readl(ctrl_base, wrp->mode); reg 522 drivers/usb/musb/musb_dsps.c reg &= ~(1 << wrp->iddig); reg 529 drivers/usb/musb/musb_dsps.c reg |= (1 << wrp->iddig_mux); reg 531 drivers/usb/musb/musb_dsps.c musb_writel(ctrl_base, wrp->mode, reg); reg 535 drivers/usb/musb/musb_dsps.c reg |= (1 << wrp->iddig); reg 542 drivers/usb/musb/musb_dsps.c reg |= (1 << wrp->iddig_mux); reg 544 drivers/usb/musb/musb_dsps.c musb_writel(ctrl_base, wrp->mode, reg); reg 328 drivers/usb/musb/tusb6010.c u32 reg; reg 343 drivers/usb/musb/tusb6010.c reg = musb_readl(tbase, TUSB_PRCM_MNGMT); reg 346 drivers/usb/musb/tusb6010.c reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN; reg 349 drivers/usb/musb/tusb6010.c reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); reg 351 drivers/usb/musb/tusb6010.c musb_writel(tbase, TUSB_PRCM_MNGMT, reg); reg 364 drivers/usb/musb/tusb6010.c u32 reg; reg 366 drivers/usb/musb/tusb6010.c reg = musb_readl(tbase, TUSB_PRCM_CONF); reg 367 drivers/usb/musb/tusb6010.c reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3); reg 375 drivers/usb/musb/tusb6010.c reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3); reg 377 drivers/usb/musb/tusb6010.c musb_writel(tbase, TUSB_PRCM_CONF, reg); reg 391 drivers/usb/musb/tusb6010.c u32 reg; reg 407 drivers/usb/musb/tusb6010.c reg = musb_readl(tbase, TUSB_PRCM_MNGMT); reg 410 drivers/usb/musb/tusb6010.c reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; reg 411 drivers/usb/musb/tusb6010.c reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN; reg 413 drivers/usb/musb/tusb6010.c reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN; reg 414 drivers/usb/musb/tusb6010.c reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; reg 416 drivers/usb/musb/tusb6010.c reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE; reg 417 drivers/usb/musb/tusb6010.c musb_writel(tbase, TUSB_PRCM_MNGMT, reg); reg 837 drivers/usb/musb/tusb6010.c u32 reg; reg 849 drivers/usb/musb/tusb6010.c reg = musb_readl(tbase, TUSB_SCRATCH_PAD); reg 850 drivers/usb/musb/tusb6010.c if (reg == i) reg 858 drivers/usb/musb/tusb6010.c reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE); reg 859 drivers/usb/musb/tusb6010.c musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg); reg 860 drivers/usb/musb/tusb6010.c if (reg & ~TUSB_PRCM_WNORCS) { reg 865 drivers/usb/musb/tusb6010.c musb->is_active ? "" : "in", reg); reg 1025 drivers/usb/musb/tusb6010.c u32 reg; reg 1069 drivers/usb/musb/tusb6010.c reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); reg 1070 drivers/usb/musb/tusb6010.c reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; reg 1071 drivers/usb/musb/tusb6010.c musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg); reg 1073 drivers/usb/musb/tusb6010.c reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL); reg 1074 drivers/usb/musb/tusb6010.c reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; reg 1075 drivers/usb/musb/tusb6010.c musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg); reg 63 drivers/usb/musb/tusb6010_omap.c u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); reg 65 drivers/usb/musb/tusb6010_omap.c if (reg != 0) { reg 67 drivers/usb/musb/tusb6010_omap.c chdat->epnum, reg & 0xf); reg 72 drivers/usb/musb/tusb6010_omap.c reg = (1 << 4) | chdat->epnum; reg 74 drivers/usb/musb/tusb6010_omap.c reg = chdat->epnum; reg 76 drivers/usb/musb/tusb6010_omap.c musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); reg 83 drivers/usb/musb/tusb6010_omap.c u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); reg 85 drivers/usb/musb/tusb6010_omap.c if ((reg & 0xf) != chdat->epnum) { reg 87 drivers/usb/musb/tusb6010_omap.c chdat->epnum, reg & 0xf); reg 381 drivers/usb/musb/tusb6010_omap.c u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); reg 385 drivers/usb/musb/tusb6010_omap.c int cur = (reg & (0xf << (i * 5))) >> (i * 5); reg 395 drivers/usb/musb/tusb6010_omap.c reg |= (chdat->epnum << (dmareq_nr * 5)); reg 397 drivers/usb/musb/tusb6010_omap.c reg |= ((1 << 4) << (dmareq_nr * 5)); reg 398 drivers/usb/musb/tusb6010_omap.c musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); reg 407 drivers/usb/musb/tusb6010_omap.c u32 reg; reg 412 drivers/usb/musb/tusb6010_omap.c reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); reg 413 drivers/usb/musb/tusb6010_omap.c reg &= ~(0x1f << (chdat->dma_data->dmareq * 5)); reg 414 drivers/usb/musb/tusb6010_omap.c musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); reg 508 drivers/usb/phy/phy-ab8500-usb.c u8 reg; reg 515 drivers/usb/phy/phy-ab8500-usb.c AB8500_USB, AB8500_USB_LINE_STAT_REG, ®); reg 518 drivers/usb/phy/phy-ab8500-usb.c lsts = (reg >> 3) & 0x0F; reg 524 drivers/usb/phy/phy-ab8500-usb.c AB8500_USB, AB8505_USB_LINE_STAT_REG, ®); reg 527 drivers/usb/phy/phy-ab8500-usb.c lsts = (reg >> 3) & 0x1F; reg 35 drivers/usb/phy/phy-am335x-control.c u32 reg; reg 41 drivers/usb/phy/phy-am335x-control.c reg = AM335X_PHY0_WK_EN; reg 44 drivers/usb/phy/phy-am335x-control.c reg = AM335X_PHY1_WK_EN; reg 55 drivers/usb/phy/phy-am335x-control.c val |= reg; reg 57 drivers/usb/phy/phy-am335x-control.c val &= ~reg; reg 68 drivers/usb/phy/phy-am335x-control.c u32 reg; reg 74 drivers/usb/phy/phy-am335x-control.c reg = AM335X_USB0_CTRL; reg 77 drivers/usb/phy/phy-am335x-control.c reg = AM335X_USB1_CTRL; reg 84 drivers/usb/phy/phy-am335x-control.c val = readl(usb_ctrl->phy_reg + reg); reg 98 drivers/usb/phy/phy-am335x-control.c writel(val, usb_ctrl->phy_reg + reg); reg 139 drivers/usb/phy/phy-isp1301-omap.c isp1301_get_u8(struct isp1301 *isp, u8 reg) reg 141 drivers/usb/phy/phy-isp1301-omap.c return i2c_smbus_read_byte_data(isp->client, reg + 0); reg 145 drivers/usb/phy/phy-isp1301-omap.c isp1301_get_u16(struct isp1301 *isp, u8 reg) reg 147 drivers/usb/phy/phy-isp1301-omap.c return i2c_smbus_read_word_data(isp->client, reg); reg 151 drivers/usb/phy/phy-isp1301-omap.c isp1301_set_bits(struct isp1301 *isp, u8 reg, u8 bits) reg 153 drivers/usb/phy/phy-isp1301-omap.c return i2c_smbus_write_byte_data(isp->client, reg + 0, bits); reg 157 drivers/usb/phy/phy-isp1301-omap.c isp1301_clear_bits(struct isp1301 *isp, u8 reg, u8 bits) reg 159 drivers/usb/phy/phy-isp1301-omap.c return i2c_smbus_write_byte_data(isp->client, reg + 1, bits); reg 41 drivers/usb/phy/phy-isp1301.c static int __isp1301_write(struct isp1301 *isp, u8 reg, u8 value, u8 clear) reg 43 drivers/usb/phy/phy-isp1301.c return i2c_smbus_write_byte_data(isp->client, reg | clear, value); reg 46 drivers/usb/phy/phy-isp1301.c static int isp1301_write(struct isp1301 *isp, u8 reg, u8 value) reg 48 drivers/usb/phy/phy-isp1301.c return __isp1301_write(isp, reg, value, 0); reg 51 drivers/usb/phy/phy-isp1301.c static int isp1301_clear(struct isp1301 *isp, u8 reg, u8 value) reg 53 drivers/usb/phy/phy-isp1301.c return __isp1301_write(isp, reg, value, ISP1301_I2C_REG_CLEAR_ADDR); reg 312 drivers/usb/phy/phy-mxs-usb.c unsigned int reg = mxs_phy->port_id ? reg 319 drivers/usb/phy/phy-mxs-usb.c regmap_write(mxs_phy->regmap_anatop, reg, reg 360 drivers/usb/phy/phy-mxs-usb.c u32 reg; reg 367 drivers/usb/phy/phy-mxs-usb.c reg = disconnect ? ANADIG_USB1_LOOPBACK_SET reg 369 drivers/usb/phy/phy-mxs-usb.c regmap_write(mxs_phy->regmap_anatop, reg, reg 373 drivers/usb/phy/phy-mxs-usb.c reg = disconnect ? ANADIG_USB2_LOOPBACK_SET reg 375 drivers/usb/phy/phy-mxs-usb.c regmap_write(mxs_phy->regmap_anatop, reg, reg 465 drivers/usb/phy/phy-mxs-usb.c unsigned int reg = ANADIG_USB1_MISC; reg 472 drivers/usb/phy/phy-mxs-usb.c reg = ANADIG_USB1_MISC; reg 474 drivers/usb/phy/phy-mxs-usb.c reg = ANADIG_USB2_MISC; reg 476 drivers/usb/phy/phy-mxs-usb.c regmap_read(mxs_phy->regmap_anatop, reg, &line_state); reg 823 drivers/usb/phy/phy-mxs-usb.c unsigned int reg = on ? ANADIG_ANA_MISC0_SET : ANADIG_ANA_MISC0_CLR; reg 830 drivers/usb/phy/phy-mxs-usb.c regmap_write(mxs_phy->regmap_anatop, reg, reg 834 drivers/usb/phy/phy-mxs-usb.c reg, BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL); reg 73 drivers/usb/phy/phy-tahvo.c int reg, prev_state; reg 75 drivers/usb/phy/phy-tahvo.c reg = retu_read(rdev, TAHVO_REG_IDSR); reg 76 drivers/usb/phy/phy-tahvo.c if (reg & TAHVO_STAT_VBUS) { reg 114 drivers/usb/phy/phy-tahvo.c tu->vbus_state = reg & TAHVO_STAT_VBUS; reg 376 drivers/usb/phy/phy-tegra-usb.c static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result) reg 380 drivers/usb/phy/phy-tegra-usb.c return readl_poll_timeout(reg, tmp, (tmp & mask) == result, reg 35 drivers/usb/phy/phy-ulpi-viewport.c static int ulpi_viewport_read(struct usb_phy *otg, u32 reg) reg 45 drivers/usb/phy/phy-ulpi-viewport.c writel(ULPI_VIEW_RUN | ULPI_VIEW_READ | ULPI_VIEW_ADDR(reg), view); reg 53 drivers/usb/phy/phy-ulpi-viewport.c static int ulpi_viewport_write(struct usb_phy *otg, u32 val, u32 reg) reg 64 drivers/usb/phy/phy-ulpi-viewport.c ULPI_VIEW_ADDR(reg), view); reg 62 drivers/usb/renesas_usbhs/common.c u16 usbhs_read(struct usbhs_priv *priv, u32 reg) reg 64 drivers/usb/renesas_usbhs/common.c return ioread16(priv->base + reg); reg 67 drivers/usb/renesas_usbhs/common.c void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data) reg 69 drivers/usb/renesas_usbhs/common.c iowrite16(data, priv->base + reg); reg 72 drivers/usb/renesas_usbhs/common.c void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data) reg 74 drivers/usb/renesas_usbhs/common.c u16 val = usbhs_read(priv, reg); reg 79 drivers/usb/renesas_usbhs/common.c usbhs_write(priv, reg, val); reg 238 drivers/usb/renesas_usbhs/common.c u32 reg = DEVADD0 + (2 * devnum); reg 265 drivers/usb/renesas_usbhs/common.c usbhs_write(priv, reg, UPPHUB(upphub) | reg 290 drivers/usb/renesas_usbhs/common.h u16 usbhs_read(struct usbhs_priv *priv, u32 reg); reg 291 drivers/usb/renesas_usbhs/common.h void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data); reg 292 drivers/usb/renesas_usbhs/common.h void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data); reg 119 drivers/usb/renesas_usbhs/pipe.c u16 reg; reg 127 drivers/usb/renesas_usbhs/pipe.c reg = PIPE ## a ## TRN; \ reg 147 drivers/usb/renesas_usbhs/pipe.c __usbhsp_pipe_xxx_set(pipe, 0, reg, mask, val); reg 155 drivers/usb/renesas_usbhs/pipe.c u16 reg; reg 163 drivers/usb/renesas_usbhs/pipe.c reg = PIPE ## a ## TRE; \ reg 184 drivers/usb/renesas_usbhs/pipe.c __usbhsp_pipe_xxx_set(pipe, 0, reg, mask, val); reg 37 drivers/usb/renesas_usbhs/rcar3.c static void usbhs_write32(struct usbhs_priv *priv, u32 reg, u32 data) reg 39 drivers/usb/renesas_usbhs/rcar3.c iowrite32(data, priv->base + reg); reg 42 drivers/usb/renesas_usbhs/rcar3.c static u32 usbhs_read32(struct usbhs_priv *priv, u32 reg) reg 44 drivers/usb/renesas_usbhs/rcar3.c return ioread32(priv->base + reg); reg 78 drivers/usb/serial/ark3116.c unsigned reg, __u8 val) reg 84 drivers/usb/serial/ark3116.c 0xfe, 0x40, val, reg, reg 93 drivers/usb/serial/ark3116.c unsigned reg, unsigned char *buf) reg 99 drivers/usb/serial/ark3116.c 0xfe, 0xc0, 0, reg, reg 104 drivers/usb/serial/ark3116.c reg, result); reg 87 drivers/usb/serial/f81232.c static int f81232_get_register(struct usb_serial_port *port, u16 reg, u8 *val) reg 101 drivers/usb/serial/f81232.c reg, reg 122 drivers/usb/serial/f81232.c static int f81232_set_register(struct usb_serial_port *port, u16 reg, u8 val) reg 138 drivers/usb/serial/f81232.c reg, reg 158 drivers/usb/serial/f81232.c static int f81232_set_mask_register(struct usb_serial_port *port, u16 reg, reg 164 drivers/usb/serial/f81232.c status = f81232_get_register(port, reg, &tmp); reg 170 drivers/usb/serial/f81232.c return f81232_set_register(port, reg, tmp); reg 214 drivers/usb/serial/f81534.c static int f81534_set_register(struct usb_serial *serial, u16 reg, u8 data) reg 236 drivers/usb/serial/f81534.c reg, 0, tmp, sizeof(u8), reg 248 drivers/usb/serial/f81534.c __func__, reg, data, status); reg 255 drivers/usb/serial/f81534.c static int f81534_get_register(struct usb_serial *serial, u16 reg, u8 *data) reg 275 drivers/usb/serial/f81534.c reg, 0, tmp, sizeof(u8), reg 287 drivers/usb/serial/f81534.c reg, status); reg 298 drivers/usb/serial/f81534.c static int f81534_set_mask_register(struct usb_serial *serial, u16 reg, reg 304 drivers/usb/serial/f81534.c status = f81534_get_register(serial, reg, &tmp); reg 311 drivers/usb/serial/f81534.c return f81534_set_register(serial, reg, tmp); reg 315 drivers/usb/serial/f81534.c u16 reg, u8 data) reg 317 drivers/usb/serial/f81534.c return f81534_set_register(serial, reg + F81534_UART_OFFSET * phy, reg 322 drivers/usb/serial/f81534.c u16 reg, u8 *data) reg 324 drivers/usb/serial/f81534.c return f81534_get_register(serial, reg + F81534_UART_OFFSET * phy, reg 328 drivers/usb/serial/f81534.c static int f81534_set_port_register(struct usb_serial_port *port, u16 reg, reg 334 drivers/usb/serial/f81534.c reg + port_priv->phy_num * F81534_UART_OFFSET, data); reg 337 drivers/usb/serial/f81534.c static int f81534_get_port_register(struct usb_serial_port *port, u16 reg, reg 343 drivers/usb/serial/f81534.c reg + port_priv->phy_num * F81534_UART_OFFSET, data); reg 381 drivers/usb/serial/f81534.c static int f81534_get_spi_register(struct usb_serial *serial, u16 reg, reg 386 drivers/usb/serial/f81534.c status = f81534_get_register(serial, reg, data); reg 393 drivers/usb/serial/f81534.c static int f81534_set_spi_register(struct usb_serial *serial, u16 reg, u8 data) reg 397 drivers/usb/serial/f81534.c status = f81534_set_register(serial, reg, data); reg 145 drivers/usb/serial/mos7720.c static inline __u16 get_reg_index(enum mos_regs reg) reg 169 drivers/usb/serial/mos7720.c return mos7715_index_lookup_table[reg]; reg 176 drivers/usb/serial/mos7720.c static inline __u16 get_reg_value(enum mos_regs reg, reg 179 drivers/usb/serial/mos7720.c if (reg >= MOS7720_SP1_REG) /* control reg */ reg 182 drivers/usb/serial/mos7720.c else if (reg >= MOS7720_DPR) /* parallel port reg (7715 only) */ reg 195 drivers/usb/serial/mos7720.c enum mos_regs reg, __u8 data) reg 201 drivers/usb/serial/mos7720.c __u16 index = get_reg_index(reg); reg 202 drivers/usb/serial/mos7720.c __u16 value = get_reg_value(reg, serial_portnum) + data; reg 217 drivers/usb/serial/mos7720.c enum mos_regs reg, __u8 *data) reg 223 drivers/usb/serial/mos7720.c __u16 index = get_reg_index(reg); reg 224 drivers/usb/serial/mos7720.c __u16 value = get_reg_value(reg, serial_portnum); reg 356 drivers/usb/serial/mos7720.c enum mos_regs reg, __u8 data) reg 382 drivers/usb/serial/mos7720.c urbtrack->setup->wValue = cpu_to_le16(get_reg_value(reg, dummy)); reg 383 drivers/usb/serial/mos7720.c urbtrack->setup->wIndex = cpu_to_le16(get_reg_index(reg)); reg 249 drivers/usb/serial/mos7840.c static int mos7840_set_reg_sync(struct usb_serial_port *port, __u16 reg, reg 254 drivers/usb/serial/mos7840.c dev_dbg(&port->dev, "mos7840_set_reg_sync offset is %x, value %x\n", reg, val); reg 257 drivers/usb/serial/mos7840.c MCS_WR_RTYPE, val, reg, NULL, 0, reg 267 drivers/usb/serial/mos7840.c static int mos7840_get_reg_sync(struct usb_serial_port *port, __u16 reg, reg 279 drivers/usb/serial/mos7840.c MCS_RD_RTYPE, 0, reg, buf, VENDOR_READ_LENGTH, reg 288 drivers/usb/serial/mos7840.c dev_dbg(&port->dev, "%s offset is %x, return val %x\n", __func__, reg, *val); reg 300 drivers/usb/serial/mos7840.c static int mos7840_set_uart_reg(struct usb_serial_port *port, __u16 reg, reg 314 drivers/usb/serial/mos7840.c MCS_WR_RTYPE, val, reg, NULL, 0, reg 324 drivers/usb/serial/mos7840.c static int mos7840_get_uart_reg(struct usb_serial_port *port, __u16 reg, reg 343 drivers/usb/serial/mos7840.c MCS_RD_RTYPE, Wval, reg, buf, VENDOR_READ_LENGTH, reg 484 drivers/usb/serial/mos7840.c static int mos7840_get_reg(struct moschip_port *mcs, __u16 Wval, __u16 reg, reg 498 drivers/usb/serial/mos7840.c dr->wIndex = cpu_to_le16(reg); reg 532 drivers/usb/serial/mos7840.c __u16 reg) reg 540 drivers/usb/serial/mos7840.c dr->wIndex = cpu_to_le16(reg); reg 549 drivers/usb/serial/mos7840.c static void mos7840_set_led_sync(struct usb_serial_port *port, __u16 reg, reg 555 drivers/usb/serial/mos7840.c val, reg, NULL, 0, MOS_WDR_TIMEOUT); reg 232 drivers/usb/serial/pl2303.c static int pl2303_update_reg(struct usb_serial *serial, u8 reg, u8 mask, u8 val) reg 241 drivers/usb/serial/pl2303.c ret = pl2303_vendor_read(serial, reg | 0x80, buf); reg 248 drivers/usb/serial/pl2303.c ret = pl2303_vendor_write(serial, reg, *buf); reg 189 drivers/usb/serial/quatech2.c u8 reg, reg 195 drivers/usb/serial/quatech2.c QT_SET_GET_REGISTER, 0xc0, reg, reg 206 drivers/usb/serial/quatech2.c u8 uart, u8 reg, u16 data) reg 208 drivers/usb/serial/quatech2.c u16 value = (data << 8) | reg; reg 99 drivers/usb/serial/ssu100.c unsigned short reg, reg 105 drivers/usb/serial/ssu100.c QT_SET_GET_REGISTER, 0xc0, reg, reg 118 drivers/usb/serial/ssu100.c unsigned short reg, reg 121 drivers/usb/serial/ssu100.c u16 value = (data << 8) | reg; reg 224 drivers/usb/storage/shuttle_usbat.c unsigned char reg, reg 231 drivers/usb/storage/shuttle_usbat.c (u16)reg, reg 242 drivers/usb/storage/shuttle_usbat.c unsigned char reg, reg 249 drivers/usb/storage/shuttle_usbat.c short_pack(reg, content), reg 46 drivers/usb/typec/tcpm/tcpci.c static int tcpci_read16(struct tcpci *tcpci, unsigned int reg, u16 *val) reg 48 drivers/usb/typec/tcpm/tcpci.c return regmap_raw_read(tcpci->regmap, reg, val, sizeof(u16)); reg 51 drivers/usb/typec/tcpm/tcpci.c static int tcpci_write16(struct tcpci *tcpci, unsigned int reg, u16 val) reg 53 drivers/usb/typec/tcpm/tcpci.c return regmap_raw_write(tcpci->regmap, reg, &val, sizeof(u16)); reg 59 drivers/usb/typec/tcpm/tcpci.c unsigned int reg; reg 64 drivers/usb/typec/tcpm/tcpci.c reg = (TCPC_ROLE_CTRL_CC_RA << TCPC_ROLE_CTRL_CC1_SHIFT) | reg 68 drivers/usb/typec/tcpm/tcpci.c reg = (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) | reg 72 drivers/usb/typec/tcpm/tcpci.c reg = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) | reg 78 drivers/usb/typec/tcpm/tcpci.c reg = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) | reg 84 drivers/usb/typec/tcpm/tcpci.c reg = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) | reg 91 drivers/usb/typec/tcpm/tcpci.c reg = (TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC1_SHIFT) | reg 96 drivers/usb/typec/tcpm/tcpci.c ret = regmap_write(tcpci->regmap, TCPC_ROLE_CTRL, reg); reg 109 drivers/usb/typec/tcpm/tcpci.c unsigned int reg = TCPC_ROLE_CTRL_DRP; reg 124 drivers/usb/typec/tcpm/tcpci.c reg |= (TCPC_ROLE_CTRL_RP_VAL_DEF << reg 128 drivers/usb/typec/tcpm/tcpci.c reg |= (TCPC_ROLE_CTRL_RP_VAL_1_5 << reg 132 drivers/usb/typec/tcpm/tcpci.c reg |= (TCPC_ROLE_CTRL_RP_VAL_3_0 << reg 138 drivers/usb/typec/tcpm/tcpci.c reg |= (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) | reg 141 drivers/usb/typec/tcpm/tcpci.c reg |= (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) | reg 143 drivers/usb/typec/tcpm/tcpci.c ret = regmap_write(tcpci->regmap, TCPC_ROLE_CTRL, reg); reg 171 drivers/usb/typec/tcpm/tcpci.c unsigned int reg; reg 174 drivers/usb/typec/tcpm/tcpci.c ret = regmap_read(tcpci->regmap, TCPC_CC_STATUS, ®); reg 178 drivers/usb/typec/tcpm/tcpci.c *cc1 = tcpci_to_typec_cc((reg >> TCPC_CC_STATUS_CC1_SHIFT) & reg 180 drivers/usb/typec/tcpm/tcpci.c reg & TCPC_CC_STATUS_TERM); reg 181 drivers/usb/typec/tcpm/tcpci.c *cc2 = tcpci_to_typec_cc((reg >> TCPC_CC_STATUS_CC2_SHIFT) & reg 183 drivers/usb/typec/tcpm/tcpci.c reg & TCPC_CC_STATUS_TERM); reg 192 drivers/usb/typec/tcpm/tcpci.c unsigned int reg; reg 196 drivers/usb/typec/tcpm/tcpci.c ret = regmap_read(tcpci->regmap, TCPC_ROLE_CTRL, ®); reg 201 drivers/usb/typec/tcpm/tcpci.c reg |= TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC1_SHIFT; reg 203 drivers/usb/typec/tcpm/tcpci.c reg |= TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC2_SHIFT; reg 204 drivers/usb/typec/tcpm/tcpci.c ret = regmap_write(tcpci->regmap, TCPC_ROLE_CTRL, reg); reg 234 drivers/usb/typec/tcpm/tcpci.c unsigned int reg; reg 237 drivers/usb/typec/tcpm/tcpci.c reg = PD_REV20 << TCPC_MSG_HDR_INFO_REV_SHIFT; reg 239 drivers/usb/typec/tcpm/tcpci.c reg |= TCPC_MSG_HDR_INFO_PWR_ROLE; reg 241 drivers/usb/typec/tcpm/tcpci.c reg |= TCPC_MSG_HDR_INFO_DATA_ROLE; reg 242 drivers/usb/typec/tcpm/tcpci.c ret = regmap_write(tcpci->regmap, TCPC_MSG_HDR_INFO, reg); reg 252 drivers/usb/typec/tcpm/tcpci.c unsigned int reg = 0; reg 256 drivers/usb/typec/tcpm/tcpci.c reg = TCPC_RX_DETECT_SOP | TCPC_RX_DETECT_HARD_RESET; reg 257 drivers/usb/typec/tcpm/tcpci.c ret = regmap_write(tcpci->regmap, TCPC_RX_DETECT, reg); reg 267 drivers/usb/typec/tcpm/tcpci.c unsigned int reg; reg 270 drivers/usb/typec/tcpm/tcpci.c ret = regmap_read(tcpci->regmap, TCPC_POWER_STATUS, ®); reg 274 drivers/usb/typec/tcpm/tcpci.c return !!(reg & TCPC_POWER_STATUS_VBUS_PRES); reg 321 drivers/usb/typec/tcpm/tcpci.c unsigned int reg, cnt; reg 340 drivers/usb/typec/tcpm/tcpci.c reg = (PD_RETRY_COUNT << TCPC_TRANSMIT_RETRY_SHIFT) | reg 342 drivers/usb/typec/tcpm/tcpci.c ret = regmap_write(tcpci->regmap, TCPC_TRANSMIT, reg); reg 353 drivers/usb/typec/tcpm/tcpci.c unsigned int reg; reg 357 drivers/usb/typec/tcpm/tcpci.c ret = regmap_read(tcpci->regmap, TCPC_POWER_STATUS, ®); reg 360 drivers/usb/typec/tcpm/tcpci.c if (!(reg & TCPC_POWER_STATUS_UNINIT)) reg 380 drivers/usb/typec/tcpm/tcpci.c reg = TCPC_POWER_STATUS_VBUS_PRES; reg 382 drivers/usb/typec/tcpm/tcpci.c reg = 0; reg 383 drivers/usb/typec/tcpm/tcpci.c ret = regmap_write(tcpci->regmap, TCPC_POWER_STATUS_MASK, reg); reg 393 drivers/usb/typec/tcpm/tcpci.c reg = TCPC_ALERT_TX_SUCCESS | TCPC_ALERT_TX_FAILED | reg 397 drivers/usb/typec/tcpm/tcpci.c reg |= TCPC_ALERT_POWER_STATUS; reg 398 drivers/usb/typec/tcpm/tcpci.c return tcpci_write16(tcpci, TCPC_ALERT_MASK, reg); reg 419 drivers/usb/typec/tcpm/tcpci.c unsigned int reg; reg 421 drivers/usb/typec/tcpm/tcpci.c regmap_read(tcpci->regmap, TCPC_POWER_STATUS_MASK, ®); reg 427 drivers/usb/typec/tcpm/tcpci.c if (reg == 0xff) reg 44 drivers/usb/typec/tcpm/tcpci_rt1711h.c static int rt1711h_read16(struct rt1711h_chip *chip, unsigned int reg, u16 *val) reg 46 drivers/usb/typec/tcpm/tcpci_rt1711h.c return regmap_raw_read(chip->data.regmap, reg, val, sizeof(u16)); reg 49 drivers/usb/typec/tcpm/tcpci_rt1711h.c static int rt1711h_write16(struct rt1711h_chip *chip, unsigned int reg, u16 val) reg 51 drivers/usb/typec/tcpm/tcpci_rt1711h.c return regmap_raw_write(chip->data.regmap, reg, &val, sizeof(u16)); reg 54 drivers/usb/typec/tcpm/tcpci_rt1711h.c static int rt1711h_read8(struct rt1711h_chip *chip, unsigned int reg, u8 *val) reg 56 drivers/usb/typec/tcpm/tcpci_rt1711h.c return regmap_raw_read(chip->data.regmap, reg, val, sizeof(u8)); reg 59 drivers/usb/typec/tcpm/tcpci_rt1711h.c static int rt1711h_write8(struct rt1711h_chip *chip, unsigned int reg, u8 val) reg 61 drivers/usb/typec/tcpm/tcpci_rt1711h.c return regmap_raw_write(chip->data.regmap, reg, &val, sizeof(u8)); reg 122 drivers/usb/typec/tcpm/tcpci_rt1711h.c unsigned int reg = 0; reg 127 drivers/usb/typec/tcpm/tcpci_rt1711h.c reg |= (TCPC_ROLE_CTRL_RP_VAL_DEF << reg 131 drivers/usb/typec/tcpm/tcpci_rt1711h.c reg |= (TCPC_ROLE_CTRL_RP_VAL_1_5 << reg 135 drivers/usb/typec/tcpm/tcpci_rt1711h.c reg |= (TCPC_ROLE_CTRL_RP_VAL_3_0 << reg 141 drivers/usb/typec/tcpm/tcpci_rt1711h.c reg |= (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) | reg 144 drivers/usb/typec/tcpm/tcpci_rt1711h.c reg |= (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) | reg 147 drivers/usb/typec/tcpm/tcpci_rt1711h.c ret = rt1711h_write8(chip, TCPC_ROLE_CTRL, reg); reg 107 drivers/usb/typec/tps6598x.c tps6598x_block_read(struct tps6598x *tps, u8 reg, void *val, size_t len) reg 116 drivers/usb/typec/tps6598x.c return regmap_raw_read(tps->regmap, reg, val, len); reg 118 drivers/usb/typec/tps6598x.c ret = regmap_raw_read(tps->regmap, reg, data, sizeof(data)); reg 129 drivers/usb/typec/tps6598x.c static int tps6598x_block_write(struct tps6598x *tps, u8 reg, reg 135 drivers/usb/typec/tps6598x.c return regmap_raw_write(tps->regmap, reg, val, len); reg 140 drivers/usb/typec/tps6598x.c return regmap_raw_write(tps->regmap, reg, data, sizeof(data)); reg 143 drivers/usb/typec/tps6598x.c static inline int tps6598x_read16(struct tps6598x *tps, u8 reg, u16 *val) reg 145 drivers/usb/typec/tps6598x.c return tps6598x_block_read(tps, reg, val, sizeof(u16)); reg 148 drivers/usb/typec/tps6598x.c static inline int tps6598x_read32(struct tps6598x *tps, u8 reg, u32 *val) reg 150 drivers/usb/typec/tps6598x.c return tps6598x_block_read(tps, reg, val, sizeof(u32)); reg 153 drivers/usb/typec/tps6598x.c static inline int tps6598x_read64(struct tps6598x *tps, u8 reg, u64 *val) reg 155 drivers/usb/typec/tps6598x.c return tps6598x_block_read(tps, reg, val, sizeof(u64)); reg 158 drivers/usb/typec/tps6598x.c static inline int tps6598x_write16(struct tps6598x *tps, u8 reg, u16 val) reg 160 drivers/usb/typec/tps6598x.c return tps6598x_block_write(tps, reg, &val, sizeof(u16)); reg 163 drivers/usb/typec/tps6598x.c static inline int tps6598x_write32(struct tps6598x *tps, u8 reg, u32 val) reg 165 drivers/usb/typec/tps6598x.c return tps6598x_block_write(tps, reg, &val, sizeof(u32)); reg 168 drivers/usb/typec/tps6598x.c static inline int tps6598x_write64(struct tps6598x *tps, u8 reg, u64 val) reg 170 drivers/usb/typec/tps6598x.c return tps6598x_block_write(tps, reg, &val, sizeof(u64)); reg 174 drivers/usb/typec/tps6598x.c tps6598x_write_4cc(struct tps6598x *tps, u8 reg, const char *val) reg 176 drivers/usb/typec/tps6598x.c return tps6598x_block_write(tps, reg, val, 4); reg 165 drivers/usb/typec/ucsi/ucsi_ccg.c u16 reg; reg 495 drivers/usb/typec/ucsi/ucsi_ccg.c switch (cmd->reg & 0xF000) { reg 504 drivers/usb/typec/ucsi/ucsi_ccg.c ret = ccg_write(uc, cmd->reg, (u8 *)&cmd->data, cmd->len); reg 513 drivers/usb/typec/ucsi/ucsi_ccg.c switch (cmd->reg & 0xF000) { reg 533 drivers/usb/typec/ucsi/ucsi_ccg.c cmd.reg = CCGX_RAB_ENTER_FLASHING; reg 559 drivers/usb/typec/ucsi/ucsi_ccg.c cmd.reg = CCGX_RAB_RESET_REQ; reg 588 drivers/usb/typec/ucsi/ucsi_ccg.c cmd.reg = CCGX_RAB_PDPORT_ENABLE; reg 615 drivers/usb/typec/ucsi/ucsi_ccg.c cmd.reg = CCGX_RAB_JUMP_TO_BOOT; reg 670 drivers/usb/typec/ucsi/ucsi_ccg.c cmd.reg = CCGX_RAB_FLASH_ROW_RW; reg 697 drivers/usb/typec/ucsi/ucsi_ccg.c cmd.reg = CCGX_RAB_VALIDATE_FW; reg 213 drivers/vfio/pci/vfio_pci_nvlink2.c u64 reg[2]; reg 240 drivers/vfio/pci/vfio_pci_nvlink2.c if (of_property_read_variable_u64_array(mem_node, "reg", reg, reg 241 drivers/vfio/pci/vfio_pci_nvlink2.c ARRAY_SIZE(reg), ARRAY_SIZE(reg)) != reg 242 drivers/vfio/pci/vfio_pci_nvlink2.c ARRAY_SIZE(reg)) reg 254 drivers/vfio/pci/vfio_pci_nvlink2.c data->gpu_hpa = reg[0]; reg 256 drivers/vfio/pci/vfio_pci_nvlink2.c data->size = reg[1]; reg 28 drivers/vfio/platform/reset/vfio_platform_amdxgbe.c unsigned int reg) reg 32 drivers/vfio/platform/reset/vfio_platform_amdxgbe.c mmd_address = (mmd << 16) | ((reg) & 0xffff); reg 39 drivers/vfio/platform/reset/vfio_platform_amdxgbe.c unsigned int reg, unsigned int value) reg 43 drivers/vfio/platform/reset/vfio_platform_amdxgbe.c mmd_address = (mmd << 16) | ((reg) & 0xffff); reg 81 drivers/vfio/platform/reset/vfio_platform_bcmflexrm.c struct vfio_platform_region *reg = &vdev->regions[0]; reg 84 drivers/vfio/platform/reset/vfio_platform_bcmflexrm.c if (!reg->ioaddr) { reg 85 drivers/vfio/platform/reset/vfio_platform_bcmflexrm.c reg->ioaddr = ioremap_nocache(reg->addr, reg->size); reg 86 drivers/vfio/platform/reset/vfio_platform_bcmflexrm.c if (!reg->ioaddr) reg 91 drivers/vfio/platform/reset/vfio_platform_bcmflexrm.c for (ring = reg->ioaddr; reg 92 drivers/vfio/platform/reset/vfio_platform_bcmflexrm.c ring < (reg->ioaddr + reg->size); ring += RING_REGS_SIZE) { reg 51 drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c struct vfio_platform_region *reg = &vdev->regions[0]; reg 53 drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c if (!reg->ioaddr) { reg 54 drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c reg->ioaddr = reg 55 drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c ioremap_nocache(reg->addr, reg->size); reg 56 drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c if (!reg->ioaddr) reg 61 drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c writel(0, reg->ioaddr + XGMAC_DMA_INTR_ENA); reg 64 drivers/vfio/platform/reset/vfio_platform_calxedaxgmac.c xgmac_mac_disable(reg->ioaddr); reg 404 drivers/vfio/platform/vfio_platform_common.c static ssize_t vfio_platform_read_mmio(struct vfio_platform_region *reg, reg 410 drivers/vfio/platform/vfio_platform_common.c if (!reg->ioaddr) { reg 411 drivers/vfio/platform/vfio_platform_common.c reg->ioaddr = reg 412 drivers/vfio/platform/vfio_platform_common.c ioremap_nocache(reg->addr, reg->size); reg 414 drivers/vfio/platform/vfio_platform_common.c if (!reg->ioaddr) reg 424 drivers/vfio/platform/vfio_platform_common.c val = ioread32(reg->ioaddr + off); reg 432 drivers/vfio/platform/vfio_platform_common.c val = ioread16(reg->ioaddr + off); reg 440 drivers/vfio/platform/vfio_platform_common.c val = ioread8(reg->ioaddr + off); reg 481 drivers/vfio/platform/vfio_platform_common.c static ssize_t vfio_platform_write_mmio(struct vfio_platform_region *reg, reg 487 drivers/vfio/platform/vfio_platform_common.c if (!reg->ioaddr) { reg 488 drivers/vfio/platform/vfio_platform_common.c reg->ioaddr = reg 489 drivers/vfio/platform/vfio_platform_common.c ioremap_nocache(reg->addr, reg->size); reg 491 drivers/vfio/platform/vfio_platform_common.c if (!reg->ioaddr) reg 503 drivers/vfio/platform/vfio_platform_common.c iowrite32(val, reg->ioaddr + off); reg 511 drivers/vfio/platform/vfio_platform_common.c iowrite16(val, reg->ioaddr + off); reg 519 drivers/vfio/platform/vfio_platform_common.c iowrite8(val, reg->ioaddr + off); reg 143 drivers/video/backlight/adp5520_bl.c static ssize_t adp5520_show(struct device *dev, char *buf, int reg) reg 150 drivers/video/backlight/adp5520_bl.c ret = adp5520_read(data->master, reg, ®_val); reg 160 drivers/video/backlight/adp5520_bl.c size_t count, int reg) reg 171 drivers/video/backlight/adp5520_bl.c adp5520_write(data->master, reg, val); reg 119 drivers/video/backlight/adp8860_bl.c static int adp8860_read(struct i2c_client *client, int reg, uint8_t *val) reg 123 drivers/video/backlight/adp8860_bl.c ret = i2c_smbus_read_byte_data(client, reg); reg 125 drivers/video/backlight/adp8860_bl.c dev_err(&client->dev, "failed reading at 0x%02x\n", reg); reg 133 drivers/video/backlight/adp8860_bl.c static int adp8860_write(struct i2c_client *client, u8 reg, u8 val) reg 135 drivers/video/backlight/adp8860_bl.c return i2c_smbus_write_byte_data(client, reg, val); reg 138 drivers/video/backlight/adp8860_bl.c static int adp8860_set_bits(struct i2c_client *client, int reg, uint8_t bit_mask) reg 146 drivers/video/backlight/adp8860_bl.c ret = adp8860_read(client, reg, ®_val); reg 150 drivers/video/backlight/adp8860_bl.c ret = adp8860_write(client, reg, reg_val); reg 157 drivers/video/backlight/adp8860_bl.c static int adp8860_clr_bits(struct i2c_client *client, int reg, uint8_t bit_mask) reg 165 drivers/video/backlight/adp8860_bl.c ret = adp8860_read(client, reg, ®_val); reg 169 drivers/video/backlight/adp8860_bl.c ret = adp8860_write(client, reg, reg_val); reg 429 drivers/video/backlight/adp8860_bl.c static ssize_t adp8860_show(struct device *dev, char *buf, int reg) reg 436 drivers/video/backlight/adp8860_bl.c error = adp8860_read(data->client, reg, ®_val); reg 446 drivers/video/backlight/adp8860_bl.c size_t count, int reg) reg 457 drivers/video/backlight/adp8860_bl.c adp8860_write(data->client, reg, val); reg 128 drivers/video/backlight/adp8870_bl.c static int adp8870_read(struct i2c_client *client, int reg, uint8_t *val) reg 132 drivers/video/backlight/adp8870_bl.c ret = i2c_smbus_read_byte_data(client, reg); reg 134 drivers/video/backlight/adp8870_bl.c dev_err(&client->dev, "failed reading at 0x%02x\n", reg); reg 143 drivers/video/backlight/adp8870_bl.c static int adp8870_write(struct i2c_client *client, u8 reg, u8 val) reg 145 drivers/video/backlight/adp8870_bl.c int ret = i2c_smbus_write_byte_data(client, reg, val); reg 153 drivers/video/backlight/adp8870_bl.c static int adp8870_set_bits(struct i2c_client *client, int reg, uint8_t bit_mask) reg 161 drivers/video/backlight/adp8870_bl.c ret = adp8870_read(client, reg, ®_val); reg 165 drivers/video/backlight/adp8870_bl.c ret = adp8870_write(client, reg, reg_val); reg 172 drivers/video/backlight/adp8870_bl.c static int adp8870_clr_bits(struct i2c_client *client, int reg, uint8_t bit_mask) reg 180 drivers/video/backlight/adp8870_bl.c ret = adp8870_read(client, reg, ®_val); reg 184 drivers/video/backlight/adp8870_bl.c ret = adp8870_write(client, reg, reg_val); reg 550 drivers/video/backlight/adp8870_bl.c static ssize_t adp8870_show(struct device *dev, char *buf, int reg) reg 557 drivers/video/backlight/adp8870_bl.c error = adp8870_read(data->client, reg, ®_val); reg 567 drivers/video/backlight/adp8870_bl.c size_t count, int reg) reg 578 drivers/video/backlight/adp8870_bl.c adp8870_write(data->client, reg, val); reg 94 drivers/video/backlight/arcxcnn_bl.c static int arcxcnn_update_field(struct arcxcnn *lp, u8 reg, u8 mask, u8 data) reg 99 drivers/video/backlight/arcxcnn_bl.c ret = i2c_smbus_read_byte_data(lp->client, reg); reg 101 drivers/video/backlight/arcxcnn_bl.c dev_err(lp->dev, "failed to read 0x%.2x\n", reg); reg 109 drivers/video/backlight/arcxcnn_bl.c return i2c_smbus_write_byte_data(lp->client, reg, tmp); reg 75 drivers/video/backlight/as3711_bl.c unsigned int reg) reg 80 drivers/video/backlight/as3711_bl.c return regmap_update_bits(as3711->regmap, reg, 0xf0, reg 76 drivers/video/backlight/bd6107.c static int bd6107_write(struct bd6107 *bd, u8 reg, u8 data) reg 78 drivers/video/backlight/bd6107.c return i2c_smbus_write_byte_data(bd->client, reg, data); reg 100 drivers/video/backlight/corgi_lcd.c static int corgi_ssp_lcdtg_send(struct corgi_lcd *lcd, int reg, uint8_t val); reg 190 drivers/video/backlight/ili922x.c static int ili922x_read(struct spi_device *spi, u8 reg, u16 *rx) reg 209 drivers/video/backlight/ili922x.c tbuf[2] = set_tx_byte(reg); reg 244 drivers/video/backlight/ili922x.c static int ili922x_write(struct spi_device *spi, u8 reg, u16 value) reg 264 drivers/video/backlight/ili922x.c tbuf[2] = set_tx_byte(reg); reg 299 drivers/video/backlight/ili922x.c u8 reg; reg 303 drivers/video/backlight/ili922x.c for (reg = REG_START_OSCILLATION; reg 304 drivers/video/backlight/ili922x.c reg <= REG_OTP_PROGRAMMING_ID_KEY; reg++) { reg 305 drivers/video/backlight/ili922x.c ili922x_read(spi, reg, &rx); reg 306 drivers/video/backlight/ili922x.c dev_dbg(&spi->dev, "reg @ 0x%02X: 0x%04X\n", reg, rx); reg 477 drivers/video/backlight/ili922x.c u16 reg = 0; reg 487 drivers/video/backlight/ili922x.c ret = ili922x_read(spi, REG_DRIVER_CODE_READ, ®); reg 488 drivers/video/backlight/ili922x.c if (ret || ((reg & ILITEK_DEVICE_ID_MASK) != ILITEK_DEVICE_ID)) { reg 491 drivers/video/backlight/ili922x.c reg, ret); reg 496 drivers/video/backlight/ili922x.c reg, spi->max_speed_hz, spi->mode); reg 498 drivers/video/backlight/ili922x.c ret = ili922x_read_status(spi, ®); reg 504 drivers/video/backlight/ili922x.c dev_dbg(&spi->dev, "status: 0x%x\n", reg); reg 27 drivers/video/backlight/ili9320.c unsigned int reg, reg 39 drivers/video/backlight/ili9320.c addr[1] = reg >> 8; reg 40 drivers/video/backlight/ili9320.c addr[2] = reg; reg 51 drivers/video/backlight/ili9320.c int ili9320_write(struct ili9320 *ili, unsigned int reg, unsigned int value) reg 53 drivers/video/backlight/ili9320.c dev_dbg(ili->dev, "write: reg=%02x, val=%04x\n", reg, value); reg 54 drivers/video/backlight/ili9320.c return ili->write(ili, reg, value); reg 53 drivers/video/backlight/ili9320.h int (*write)(struct ili9320 *ili, unsigned int reg, unsigned int val); reg 60 drivers/video/backlight/ili9320.h unsigned int reg, unsigned int value); reg 56 drivers/video/backlight/lm3630a_bl.c static int lm3630a_read(struct lm3630a_chip *pchip, unsigned int reg) reg 61 drivers/video/backlight/lm3630a_bl.c rval = regmap_read(pchip->regmap, reg, ®_val); reg 68 drivers/video/backlight/lm3630a_bl.c unsigned int reg, unsigned int data) reg 70 drivers/video/backlight/lm3630a_bl.c return regmap_write(pchip->regmap, reg, data); reg 74 drivers/video/backlight/lm3630a_bl.c unsigned int reg, unsigned int mask, reg 77 drivers/video/backlight/lm3630a_bl.c return regmap_update_bits(pchip->regmap, reg, mask, data); reg 25 drivers/video/backlight/lms283gf05.c unsigned char reg; reg 112 drivers/video/backlight/lms283gf05.c buf[2] = seq[i].reg; reg 77 drivers/video/backlight/lp855x_bl.c static int lp855x_write_byte(struct lp855x *lp, u8 reg, u8 data) reg 79 drivers/video/backlight/lp855x_bl.c return i2c_smbus_write_byte_data(lp->client, reg, data); reg 82 drivers/video/backlight/lp855x_bl.c static int lp855x_update_bit(struct lp855x *lp, u8 reg, u8 mask, u8 data) reg 87 drivers/video/backlight/lp855x_bl.c ret = i2c_smbus_read_byte_data(lp->client, reg); reg 89 drivers/video/backlight/lp855x_bl.c dev_err(lp->dev, "failed to read 0x%.2x\n", reg); reg 97 drivers/video/backlight/lp855x_bl.c return lp855x_write_byte(lp, reg, tmp); reg 37 drivers/video/backlight/ltv350qv.c static int ltv350qv_write_reg(struct ltv350qv *lcd, u8 reg, u16 val) reg 53 drivers/video/backlight/ltv350qv.c lcd->buffer[2] = reg & 0x7f; reg 41 drivers/video/backlight/lv5207lp.c static int lv5207lp_write(struct lv5207lp *lv, u8 reg, u8 data) reg 43 drivers/video/backlight/lv5207lp.c return i2c_smbus_write_byte_data(lv->client, reg, data); reg 81 drivers/video/backlight/otm3225a.c unsigned char reg; /* register to write */ reg 169 drivers/video/backlight/otm3225a.c buf[2] = instruction->reg; reg 94 drivers/video/backlight/sky81452-backlight.c unsigned int reg, value = 0; reg 98 drivers/video/backlight/sky81452-backlight.c reg = !strcmp(attr->attr.name, "open") ? SKY81452_REG5 : SKY81452_REG4; reg 99 drivers/video/backlight/sky81452-backlight.c ret = regmap_read(regmap, reg, &value); reg 108 drivers/video/console/mdacon.c static void write_mda_b(unsigned int val, unsigned char reg) reg 114 drivers/video/console/mdacon.c outb_p(reg, mda_index_port); reg 120 drivers/video/console/mdacon.c static void write_mda_w(unsigned int val, unsigned char reg) reg 126 drivers/video/console/mdacon.c outb_p(reg, mda_index_port); outb_p(val >> 8, mda_value_port); reg 127 drivers/video/console/mdacon.c outb_p(reg+1, mda_index_port); outb_p(val & 0xff, mda_value_port); reg 133 drivers/video/console/mdacon.c static int test_mda_b(unsigned char val, unsigned char reg) reg 139 drivers/video/console/mdacon.c outb_p(reg, mda_index_port); reg 146 drivers/video/console/vgacon.c static inline void write_vga(unsigned char reg, unsigned int val) reg 156 drivers/video/console/vgacon.c v1 = reg + (val & 0xff00); reg 157 drivers/video/console/vgacon.c v2 = reg + 1 + ((val << 8) & 0xff00); reg 32 drivers/video/fbdev/acornfb.h u_int reg:4; reg 637 drivers/video/fbdev/amifb.c #define CMOVE(val, reg) (CUSTOM_OFS(reg) << 16 | (val)) reg 638 drivers/video/fbdev/amifb.c #define CMOVE2(val, reg) ((CUSTOM_OFS(reg) + 2) << 16 | (val)) reg 321 drivers/video/fbdev/arkfb.c static inline u8 dac_read_reg(struct dac_info *info, u8 reg) reg 323 drivers/video/fbdev/arkfb.c u8 code[2] = {reg, 0}; reg 333 drivers/video/fbdev/arkfb.c static inline void dac_write_reg(struct dac_info *info, u8 reg, u8 val) reg 335 drivers/video/fbdev/arkfb.c u8 code[2] = {reg, val}; reg 54 drivers/video/fbdev/asiliantfb.c static void mm_write_xr(struct fb_info *p, u8 reg, u8 data) reg 56 drivers/video/fbdev/asiliantfb.c mm_write_ind(reg, data, 0x7ac, 0x7ad); reg 60 drivers/video/fbdev/asiliantfb.c static void mm_write_fr(struct fb_info *p, u8 reg, u8 data) reg 62 drivers/video/fbdev/asiliantfb.c mm_write_ind(reg, data, 0x7a0, 0x7a1); reg 66 drivers/video/fbdev/asiliantfb.c static void mm_write_cr(struct fb_info *p, u8 reg, u8 data) reg 68 drivers/video/fbdev/asiliantfb.c mm_write_ind(reg, data, 0x7a8, 0x7a9); reg 72 drivers/video/fbdev/asiliantfb.c static void mm_write_gr(struct fb_info *p, u8 reg, u8 data) reg 74 drivers/video/fbdev/asiliantfb.c mm_write_ind(reg, data, 0x79c, 0x79d); reg 78 drivers/video/fbdev/asiliantfb.c static void mm_write_sr(struct fb_info *p, u8 reg, u8 data) reg 80 drivers/video/fbdev/asiliantfb.c mm_write_ind(reg, data, 0x788, 0x789); reg 84 drivers/video/fbdev/asiliantfb.c static void mm_write_ar(struct fb_info *p, u8 reg, u8 data) reg 87 drivers/video/fbdev/asiliantfb.c mm_write_ind(reg, data, 0x780, 0x780); reg 70 drivers/video/fbdev/atmel_lcdfb.c #define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg)) reg 71 drivers/video/fbdev/atmel_lcdfb.c #define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg)) reg 1300 drivers/video/fbdev/aty/aty128fb.c u32 reg; reg 1306 drivers/video/fbdev/aty/aty128fb.c reg = aty_ld_le32(LVDS_GEN_CNTL); reg 1307 drivers/video/fbdev/aty/aty128fb.c reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION; reg 1308 drivers/video/fbdev/aty/aty128fb.c reg &= ~LVDS_DISPLAY_DIS; reg 1309 drivers/video/fbdev/aty/aty128fb.c aty_st_le32(LVDS_GEN_CNTL, reg); reg 1317 drivers/video/fbdev/aty/aty128fb.c reg = aty_ld_le32(LVDS_GEN_CNTL); reg 1318 drivers/video/fbdev/aty/aty128fb.c reg |= LVDS_DISPLAY_DIS; reg 1319 drivers/video/fbdev/aty/aty128fb.c aty_st_le32(LVDS_GEN_CNTL, reg); reg 1321 drivers/video/fbdev/aty/aty128fb.c reg &= ~(LVDS_ON /*| LVDS_EN*/); reg 1322 drivers/video/fbdev/aty/aty128fb.c aty_st_le32(LVDS_GEN_CNTL, reg); reg 1771 drivers/video/fbdev/aty/aty128fb.c unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL); reg 1781 drivers/video/fbdev/aty/aty128fb.c reg |= LVDS_BL_MOD_EN | LVDS_BLON; reg 1783 drivers/video/fbdev/aty/aty128fb.c reg |= LVDS_DIGION; reg 1784 drivers/video/fbdev/aty/aty128fb.c if (!(reg & LVDS_ON)) { reg 1785 drivers/video/fbdev/aty/aty128fb.c reg &= ~LVDS_BLON; reg 1786 drivers/video/fbdev/aty/aty128fb.c aty_st_le32(LVDS_GEN_CNTL, reg); reg 1789 drivers/video/fbdev/aty/aty128fb.c reg |= LVDS_BLON; reg 1790 drivers/video/fbdev/aty/aty128fb.c aty_st_le32(LVDS_GEN_CNTL, reg); reg 1792 drivers/video/fbdev/aty/aty128fb.c reg &= ~LVDS_BL_MOD_LEVEL_MASK; reg 1793 drivers/video/fbdev/aty/aty128fb.c reg |= (aty128_bl_get_level_brightness(par, level) << reg 1796 drivers/video/fbdev/aty/aty128fb.c reg |= LVDS_ON | LVDS_EN; reg 1797 drivers/video/fbdev/aty/aty128fb.c reg &= ~LVDS_DISPLAY_DIS; reg 1799 drivers/video/fbdev/aty/aty128fb.c aty_st_le32(LVDS_GEN_CNTL, reg); reg 1804 drivers/video/fbdev/aty/aty128fb.c reg &= ~LVDS_BL_MOD_LEVEL_MASK; reg 1805 drivers/video/fbdev/aty/aty128fb.c reg |= (aty128_bl_get_level_brightness(par, 0) << reg 1808 drivers/video/fbdev/aty/aty128fb.c reg |= LVDS_DISPLAY_DIS; reg 1809 drivers/video/fbdev/aty/aty128fb.c aty_st_le32(LVDS_GEN_CNTL, reg); reg 1812 drivers/video/fbdev/aty/aty128fb.c reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION); reg 1814 drivers/video/fbdev/aty/aty128fb.c aty_st_le32(LVDS_GEN_CNTL, reg); reg 2181 drivers/video/fbdev/aty/atyfb_base.c unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par); reg 2190 drivers/video/fbdev/aty/atyfb_base.c reg |= (BLMOD_EN | BIASMOD_EN); reg 2192 drivers/video/fbdev/aty/atyfb_base.c reg &= ~BIAS_MOD_LEVEL_MASK; reg 2193 drivers/video/fbdev/aty/atyfb_base.c reg |= (aty_bl_get_level_brightness(par, level) << BIAS_MOD_LEVEL_SHIFT); reg 2195 drivers/video/fbdev/aty/atyfb_base.c reg &= ~BIAS_MOD_LEVEL_MASK; reg 2196 drivers/video/fbdev/aty/atyfb_base.c reg |= (aty_bl_get_level_brightness(par, 0) << BIAS_MOD_LEVEL_SHIFT); reg 2198 drivers/video/fbdev/aty/atyfb_base.c aty_st_lcd(LCD_MISC_CNTL, reg, par); reg 234 drivers/video/fbdev/aty/radeon_base.c u16 reg; reg 1480 drivers/video/fbdev/aty/radeon_base.c OUTREG(common_regs[i].reg, common_regs[i].val); reg 780 drivers/video/fbdev/aty/radeon_pm.c u32 reg; reg 782 drivers/video/fbdev/aty/radeon_pm.c reg = INREG(BUS_CNTL1); reg 784 drivers/video/fbdev/aty/radeon_pm.c reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK; reg 785 drivers/video/fbdev/aty/radeon_pm.c reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT); reg 787 drivers/video/fbdev/aty/radeon_pm.c reg |= 0x4080; reg 789 drivers/video/fbdev/aty/radeon_pm.c OUTREG(BUS_CNTL1, reg); reg 791 drivers/video/fbdev/aty/radeon_pm.c reg = INPLL(PLL_PWRMGT_CNTL); reg 792 drivers/video/fbdev/aty/radeon_pm.c reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF | reg 794 drivers/video/fbdev/aty/radeon_pm.c reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK; reg 795 drivers/video/fbdev/aty/radeon_pm.c reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU; reg 796 drivers/video/fbdev/aty/radeon_pm.c OUTPLL(PLL_PWRMGT_CNTL, reg); reg 798 drivers/video/fbdev/aty/radeon_pm.c reg = INREG(TV_DAC_CNTL); reg 799 drivers/video/fbdev/aty/radeon_pm.c reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK); reg 800 drivers/video/fbdev/aty/radeon_pm.c reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD | reg 803 drivers/video/fbdev/aty/radeon_pm.c OUTREG(TV_DAC_CNTL, reg); reg 805 drivers/video/fbdev/aty/radeon_pm.c reg = INREG(TMDS_TRANSMITTER_CNTL); reg 806 drivers/video/fbdev/aty/radeon_pm.c reg &= ~(TMDS_PLL_EN | TMDS_PLLRST); reg 807 drivers/video/fbdev/aty/radeon_pm.c OUTREG(TMDS_TRANSMITTER_CNTL, reg); reg 809 drivers/video/fbdev/aty/radeon_pm.c reg = INREG(DAC_CNTL); reg 810 drivers/video/fbdev/aty/radeon_pm.c reg &= ~DAC_CMP_EN; reg 811 drivers/video/fbdev/aty/radeon_pm.c OUTREG(DAC_CNTL, reg); reg 813 drivers/video/fbdev/aty/radeon_pm.c reg = INREG(DAC_CNTL2); reg 814 drivers/video/fbdev/aty/radeon_pm.c reg &= ~DAC2_CMP_EN; reg 815 drivers/video/fbdev/aty/radeon_pm.c OUTREG(DAC_CNTL2, reg); reg 817 drivers/video/fbdev/aty/radeon_pm.c reg = INREG(TV_DAC_CNTL); reg 818 drivers/video/fbdev/aty/radeon_pm.c reg &= ~TV_DAC_CNTL_DETECT; reg 819 drivers/video/fbdev/aty/radeon_pm.c OUTREG(TV_DAC_CNTL, reg); reg 258 drivers/video/fbdev/broadsheetfb.c static void broadsheet_gpio_write_reg(struct broadsheetfb_par *par, u16 reg, reg 271 drivers/video/fbdev/broadsheetfb.c broadsheet_gpio_issue_data(par, reg); reg 277 drivers/video/fbdev/broadsheetfb.c static void broadsheet_mmio_write_reg(struct broadsheetfb_par *par, u16 reg, reg 281 drivers/video/fbdev/broadsheetfb.c par->board->mmio_write(par, BS_MMIO_DATA, reg); reg 286 drivers/video/fbdev/broadsheetfb.c static void broadsheet_write_reg(struct broadsheetfb_par *par, u16 reg, reg 290 drivers/video/fbdev/broadsheetfb.c broadsheet_mmio_write_reg(par, reg, data); reg 292 drivers/video/fbdev/broadsheetfb.c broadsheet_gpio_write_reg(par, reg, data); reg 295 drivers/video/fbdev/broadsheetfb.c static void broadsheet_write_reg32(struct broadsheetfb_par *par, u16 reg, reg 298 drivers/video/fbdev/broadsheetfb.c broadsheet_write_reg(par, reg, cpu_to_le32(data) & 0xFFFF); reg 299 drivers/video/fbdev/broadsheetfb.c broadsheet_write_reg(par, reg + 2, (cpu_to_le32(data) >> 16) & 0xFFFF); reg 303 drivers/video/fbdev/broadsheetfb.c static u16 broadsheet_read_reg(struct broadsheetfb_par *par, u16 reg) reg 305 drivers/video/fbdev/broadsheetfb.c broadsheet_send_cmdargs(par, BS_CMD_RD_REG, 1, ®); reg 364 drivers/video/fbdev/broadsheetfb.c u16 reg, int bitnum, int val, reg 370 drivers/video/fbdev/broadsheetfb.c tmp = broadsheet_read_reg(par, reg); reg 2820 drivers/video/fbdev/cirrusfb.c unsigned reg; reg 2827 drivers/video/fbdev/cirrusfb.c reg = va_arg(list, int); reg 2831 drivers/video/fbdev/cirrusfb.c val = vga_rcrt(regbase, (unsigned char) reg); reg 2834 drivers/video/fbdev/cirrusfb.c val = vga_rseq(regbase, (unsigned char) reg); reg 110 drivers/video/fbdev/cyber2000fb.c #define cyber2000fb_writel(val, reg, cfb) writel(val, (cfb)->regs + (reg)) reg 111 drivers/video/fbdev/cyber2000fb.c #define cyber2000fb_writew(val, reg, cfb) writew(val, (cfb)->regs + (reg)) reg 112 drivers/video/fbdev/cyber2000fb.c #define cyber2000fb_writeb(val, reg, cfb) writeb(val, (cfb)->regs + (reg)) reg 114 drivers/video/fbdev/cyber2000fb.c #define cyber2000fb_readb(reg, cfb) readb((cfb)->regs + (reg)) reg 117 drivers/video/fbdev/cyber2000fb.c cyber2000_crtcw(unsigned int reg, unsigned int val, struct cfb_info *cfb) reg 119 drivers/video/fbdev/cyber2000fb.c cyber2000fb_writew((reg & 255) | val << 8, 0x3d4, cfb); reg 123 drivers/video/fbdev/cyber2000fb.c cyber2000_grphw(unsigned int reg, unsigned int val, struct cfb_info *cfb) reg 125 drivers/video/fbdev/cyber2000fb.c cyber2000fb_writew((reg & 255) | val << 8, 0x3ce, cfb); reg 129 drivers/video/fbdev/cyber2000fb.c cyber2000_grphr(unsigned int reg, struct cfb_info *cfb) reg 131 drivers/video/fbdev/cyber2000fb.c cyber2000fb_writeb(reg, 0x3ce, cfb); reg 136 drivers/video/fbdev/cyber2000fb.c cyber2000_attrw(unsigned int reg, unsigned int val, struct cfb_info *cfb) reg 139 drivers/video/fbdev/cyber2000fb.c cyber2000fb_writeb(reg, 0x3c0, cfb); reg 145 drivers/video/fbdev/cyber2000fb.c cyber2000_seqw(unsigned int reg, unsigned int val, struct cfb_info *cfb) reg 147 drivers/video/fbdev/cyber2000fb.c cyber2000fb_writew((reg & 255) | val << 8, 0x3c4, cfb); reg 1178 drivers/video/fbdev/cyber2000fb.c unsigned char reg; reg 1181 drivers/video/fbdev/cyber2000fb.c reg = cyber2000_grphr(DDC_REG, cfb); reg 1183 drivers/video/fbdev/cyber2000fb.c reg |= DDC_SCL_OUT; reg 1185 drivers/video/fbdev/cyber2000fb.c reg &= ~DDC_SCL_OUT; reg 1186 drivers/video/fbdev/cyber2000fb.c cyber2000_grphw(DDC_REG, reg, cfb); reg 1193 drivers/video/fbdev/cyber2000fb.c unsigned char reg; reg 1196 drivers/video/fbdev/cyber2000fb.c reg = cyber2000_grphr(DDC_REG, cfb); reg 1198 drivers/video/fbdev/cyber2000fb.c reg |= DDC_SDA_OUT; reg 1200 drivers/video/fbdev/cyber2000fb.c reg &= ~DDC_SDA_OUT; reg 1201 drivers/video/fbdev/cyber2000fb.c cyber2000_grphw(DDC_REG, reg, cfb); reg 256 drivers/video/fbdev/da8xx-fb.c u32 reg; reg 270 drivers/video/fbdev/da8xx-fb.c reg = lcdc_read(LCD_RASTER_CTRL_REG); reg 271 drivers/video/fbdev/da8xx-fb.c if (!(reg & LCD_RASTER_ENABLE)) reg 272 drivers/video/fbdev/da8xx-fb.c lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); reg 278 drivers/video/fbdev/da8xx-fb.c u32 reg; reg 281 drivers/video/fbdev/da8xx-fb.c reg = lcdc_read(LCD_RASTER_CTRL_REG); reg 282 drivers/video/fbdev/da8xx-fb.c if (reg & LCD_RASTER_ENABLE) reg 283 drivers/video/fbdev/da8xx-fb.c lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); reg 364 drivers/video/fbdev/da8xx-fb.c u32 reg; reg 366 drivers/video/fbdev/da8xx-fb.c reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001; reg 369 drivers/video/fbdev/da8xx-fb.c reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1); reg 372 drivers/video/fbdev/da8xx-fb.c reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2); reg 375 drivers/video/fbdev/da8xx-fb.c reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4); reg 378 drivers/video/fbdev/da8xx-fb.c reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8); reg 382 drivers/video/fbdev/da8xx-fb.c reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); reg 386 drivers/video/fbdev/da8xx-fb.c reg |= (fifo_th << 8); reg 388 drivers/video/fbdev/da8xx-fb.c lcdc_write(reg, LCD_DMA_CTRL_REG); reg 395 drivers/video/fbdev/da8xx-fb.c u32 reg; reg 398 drivers/video/fbdev/da8xx-fb.c reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000; reg 399 drivers/video/fbdev/da8xx-fb.c reg |= LCD_AC_BIAS_FREQUENCY(period) | reg 401 drivers/video/fbdev/da8xx-fb.c lcdc_write(reg, LCD_RASTER_TIMING_2_REG); reg 407 drivers/video/fbdev/da8xx-fb.c u32 reg; reg 409 drivers/video/fbdev/da8xx-fb.c reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0x3ff; reg 410 drivers/video/fbdev/da8xx-fb.c reg |= (((back_porch-1) & 0xff) << 24) reg 413 drivers/video/fbdev/da8xx-fb.c lcdc_write(reg, LCD_RASTER_TIMING_0_REG); reg 423 drivers/video/fbdev/da8xx-fb.c reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & ~0x780000ff; reg 424 drivers/video/fbdev/da8xx-fb.c reg |= ((front_porch-1) & 0x300) >> 8; reg 425 drivers/video/fbdev/da8xx-fb.c reg |= ((back_porch-1) & 0x300) >> 4; reg 426 drivers/video/fbdev/da8xx-fb.c reg |= ((pulse_width-1) & 0x3c0) << 21; reg 427 drivers/video/fbdev/da8xx-fb.c lcdc_write(reg, LCD_RASTER_TIMING_2_REG); reg 434 drivers/video/fbdev/da8xx-fb.c u32 reg; reg 436 drivers/video/fbdev/da8xx-fb.c reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff; reg 437 drivers/video/fbdev/da8xx-fb.c reg |= ((back_porch & 0xff) << 24) reg 440 drivers/video/fbdev/da8xx-fb.c lcdc_write(reg, LCD_RASTER_TIMING_1_REG); reg 446 drivers/video/fbdev/da8xx-fb.c u32 reg; reg 449 drivers/video/fbdev/da8xx-fb.c reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE | reg 455 drivers/video/fbdev/da8xx-fb.c reg |= LCD_MONOCHROME_MODE; reg 457 drivers/video/fbdev/da8xx-fb.c reg |= LCD_MONO_8BIT_MODE; reg 460 drivers/video/fbdev/da8xx-fb.c reg |= LCD_TFT_MODE; reg 462 drivers/video/fbdev/da8xx-fb.c reg |= LCD_TFT_ALT_ENABLE; reg 469 drivers/video/fbdev/da8xx-fb.c reg |= LCD_STN_565_ENABLE; reg 478 drivers/video/fbdev/da8xx-fb.c reg |= LCD_V1_UNDERFLOW_INT_ENA; reg 485 drivers/video/fbdev/da8xx-fb.c lcdc_write(reg, LCD_RASTER_CTRL_REG); reg 487 drivers/video/fbdev/da8xx-fb.c reg = lcdc_read(LCD_RASTER_TIMING_2_REG); reg 489 drivers/video/fbdev/da8xx-fb.c reg |= LCD_SYNC_CTRL; reg 492 drivers/video/fbdev/da8xx-fb.c reg |= LCD_SYNC_EDGE; reg 494 drivers/video/fbdev/da8xx-fb.c reg &= ~LCD_SYNC_EDGE; reg 497 drivers/video/fbdev/da8xx-fb.c reg |= LCD_INVERT_LINE_CLOCK; reg 499 drivers/video/fbdev/da8xx-fb.c reg &= ~LCD_INVERT_LINE_CLOCK; reg 502 drivers/video/fbdev/da8xx-fb.c reg |= LCD_INVERT_FRAME_CLOCK; reg 504 drivers/video/fbdev/da8xx-fb.c reg &= ~LCD_INVERT_FRAME_CLOCK; reg 506 drivers/video/fbdev/da8xx-fb.c lcdc_write(reg, LCD_RASTER_TIMING_2_REG); reg 514 drivers/video/fbdev/da8xx-fb.c u32 reg; reg 535 drivers/video/fbdev/da8xx-fb.c reg = lcdc_read(LCD_RASTER_TIMING_0_REG); reg 536 drivers/video/fbdev/da8xx-fb.c reg &= 0xfffffc00; reg 538 drivers/video/fbdev/da8xx-fb.c reg |= ((width >> 4) - 1) << 4; reg 541 drivers/video/fbdev/da8xx-fb.c reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3); reg 543 drivers/video/fbdev/da8xx-fb.c lcdc_write(reg, LCD_RASTER_TIMING_0_REG); reg 547 drivers/video/fbdev/da8xx-fb.c reg = lcdc_read(LCD_RASTER_TIMING_1_REG); reg 548 drivers/video/fbdev/da8xx-fb.c reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); reg 549 drivers/video/fbdev/da8xx-fb.c lcdc_write(reg, LCD_RASTER_TIMING_1_REG); reg 553 drivers/video/fbdev/da8xx-fb.c reg = lcdc_read(LCD_RASTER_TIMING_2_REG); reg 554 drivers/video/fbdev/da8xx-fb.c reg |= ((height - 1) & 0x400) << 16; reg 555 drivers/video/fbdev/da8xx-fb.c lcdc_write(reg, LCD_RASTER_TIMING_2_REG); reg 559 drivers/video/fbdev/da8xx-fb.c reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8); reg 561 drivers/video/fbdev/da8xx-fb.c reg |= LCD_RASTER_ORDER; reg 572 drivers/video/fbdev/da8xx-fb.c reg |= LCD_V2_TFT_24BPP_MODE; reg 575 drivers/video/fbdev/da8xx-fb.c reg |= LCD_V2_TFT_24BPP_MODE; reg 576 drivers/video/fbdev/da8xx-fb.c reg |= LCD_V2_TFT_24BPP_UNPACK; reg 586 drivers/video/fbdev/da8xx-fb.c lcdc_write(reg, LCD_RASTER_CTRL_REG); reg 138 drivers/video/fbdev/ep93xx-fb.c unsigned int val, unsigned int reg) reg 145 drivers/video/fbdev/ep93xx-fb.c ep93xxfb_writel(fbi, val, reg); reg 493 drivers/video/fbdev/fsl-diu-fb.c void wr_reg_wa(u32 *reg, u32 val) reg 496 drivers/video/fbdev/fsl-diu-fb.c out_be32(reg, val); reg 497 drivers/video/fbdev/fsl-diu-fb.c } while (in_be32(reg) != val); reg 23 drivers/video/fbdev/geode/display_gx1.c static u8 gx1_read_conf_reg(u8 reg) reg 34 drivers/video/fbdev/geode/display_gx1.c outb(reg, 0x22); reg 298 drivers/video/fbdev/geode/gxfb.h static inline uint32_t read_gp(struct gxfb_par *par, int reg) reg 300 drivers/video/fbdev/geode/gxfb.h return readl(par->gp_regs + 4*reg); reg 303 drivers/video/fbdev/geode/gxfb.h static inline void write_gp(struct gxfb_par *par, int reg, uint32_t val) reg 305 drivers/video/fbdev/geode/gxfb.h writel(val, par->gp_regs + 4*reg); reg 308 drivers/video/fbdev/geode/gxfb.h static inline uint32_t read_dc(struct gxfb_par *par, int reg) reg 310 drivers/video/fbdev/geode/gxfb.h return readl(par->dc_regs + 4*reg); reg 313 drivers/video/fbdev/geode/gxfb.h static inline void write_dc(struct gxfb_par *par, int reg, uint32_t val) reg 315 drivers/video/fbdev/geode/gxfb.h writel(val, par->dc_regs + 4*reg); reg 318 drivers/video/fbdev/geode/gxfb.h static inline uint32_t read_vp(struct gxfb_par *par, int reg) reg 320 drivers/video/fbdev/geode/gxfb.h return readl(par->vid_regs + 8*reg); reg 323 drivers/video/fbdev/geode/gxfb.h static inline void write_vp(struct gxfb_par *par, int reg, uint32_t val) reg 325 drivers/video/fbdev/geode/gxfb.h writel(val, par->vid_regs + 8*reg); reg 328 drivers/video/fbdev/geode/gxfb.h static inline uint32_t read_fp(struct gxfb_par *par, int reg) reg 330 drivers/video/fbdev/geode/gxfb.h return readl(par->vid_regs + 8*reg + VP_FP_START); reg 333 drivers/video/fbdev/geode/gxfb.h static inline void write_fp(struct gxfb_par *par, int reg, uint32_t val) reg 335 drivers/video/fbdev/geode/gxfb.h writel(val, par->vid_regs + 8*reg + VP_FP_START); reg 381 drivers/video/fbdev/geode/lxfb.h static inline uint32_t read_gp(struct lxfb_par *par, int reg) reg 383 drivers/video/fbdev/geode/lxfb.h return readl(par->gp_regs + 4*reg); reg 386 drivers/video/fbdev/geode/lxfb.h static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val) reg 388 drivers/video/fbdev/geode/lxfb.h writel(val, par->gp_regs + 4*reg); reg 391 drivers/video/fbdev/geode/lxfb.h static inline uint32_t read_dc(struct lxfb_par *par, int reg) reg 393 drivers/video/fbdev/geode/lxfb.h return readl(par->dc_regs + 4*reg); reg 396 drivers/video/fbdev/geode/lxfb.h static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val) reg 398 drivers/video/fbdev/geode/lxfb.h writel(val, par->dc_regs + 4*reg); reg 401 drivers/video/fbdev/geode/lxfb.h static inline uint32_t read_vp(struct lxfb_par *par, int reg) reg 403 drivers/video/fbdev/geode/lxfb.h return readl(par->vp_regs + 8*reg); reg 406 drivers/video/fbdev/geode/lxfb.h static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val) reg 408 drivers/video/fbdev/geode/lxfb.h writel(val, par->vp_regs + 8*reg); reg 411 drivers/video/fbdev/geode/lxfb.h static inline uint32_t read_fp(struct lxfb_par *par, int reg) reg 413 drivers/video/fbdev/geode/lxfb.h return readl(par->vp_regs + 8*reg + VP_FP_START); reg 416 drivers/video/fbdev/geode/lxfb.h static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val) reg 418 drivers/video/fbdev/geode/lxfb.h writel(val, par->vp_regs + 8*reg + VP_FP_START); reg 141 drivers/video/fbdev/gxt4500.c #define readreg(par, reg) readl((par)->regs + (reg)) reg 142 drivers/video/fbdev/gxt4500.c #define writereg(par, reg, val) writel((val), (par)->regs + (reg)) reg 512 drivers/video/fbdev/gxt4500.c static int gxt4500_setcolreg(unsigned int reg, unsigned int red, reg 519 drivers/video/fbdev/gxt4500.c if (reg > 1023) reg 523 drivers/video/fbdev/gxt4500.c writereg(par, CMAP + reg * 4, cmap_entry); reg 525 drivers/video/fbdev/gxt4500.c if (reg < 16 && par->pixfmt != DFA_PIX_8BIT) { reg 527 drivers/video/fbdev/gxt4500.c u32 val = reg; reg 530 drivers/video/fbdev/gxt4500.c val |= (reg << 11) | (reg << 5); reg 533 drivers/video/fbdev/gxt4500.c val |= (reg << 10) | (reg << 5); reg 536 drivers/video/fbdev/gxt4500.c val |= (reg << 24); reg 539 drivers/video/fbdev/gxt4500.c val |= (reg << 16) | (reg << 8); reg 542 drivers/video/fbdev/gxt4500.c pal[reg] = val; reg 144 drivers/video/fbdev/hgafb.c static void write_hga_b(unsigned int val, unsigned char reg) reg 146 drivers/video/fbdev/hgafb.c outb_p(reg, HGA_INDEX_PORT); reg 150 drivers/video/fbdev/hgafb.c static void write_hga_w(unsigned int val, unsigned char reg) reg 152 drivers/video/fbdev/hgafb.c outb_p(reg, HGA_INDEX_PORT); outb_p(val >> 8, HGA_VALUE_PORT); reg 153 drivers/video/fbdev/hgafb.c outb_p(reg+1, HGA_INDEX_PORT); outb_p(val & 0xff, HGA_VALUE_PORT); reg 156 drivers/video/fbdev/hgafb.c static int test_hga_b(unsigned char val, unsigned char reg) reg 158 drivers/video/fbdev/hgafb.c outb_p(reg, HGA_INDEX_PORT); reg 103 drivers/video/fbdev/i740fb.c static inline void i740outreg(struct i740fb_par *par, u16 port, u8 reg, u8 val) reg 105 drivers/video/fbdev/i740fb.c vga_mm_w_fast(par->regs, port, reg, val); reg 107 drivers/video/fbdev/i740fb.c static inline u8 i740inreg(struct i740fb_par *par, u16 port, u8 reg) reg 109 drivers/video/fbdev/i740fb.c vga_mm_w(par->regs, port, reg); reg 112 drivers/video/fbdev/i740fb.c static inline void i740outreg_mask(struct i740fb_par *par, u16 port, u8 reg, reg 115 drivers/video/fbdev/i740fb.c vga_mm_w_fast(par->regs, port, reg, (val & mask) reg 116 drivers/video/fbdev/i740fb.c | (i740inreg(par, port, reg) & ~mask)); reg 212 drivers/video/fbdev/i810/i810_main.c u8 reg; reg 215 drivers/video/fbdev/i810/i810_main.c reg = i810_readb(CR_DATA_CGA, mmio); reg 216 drivers/video/fbdev/i810/i810_main.c reg = (mode == OFF) ? reg & ~0x80 : reg 217 drivers/video/fbdev/i810/i810_main.c reg | 0x80; reg 220 drivers/video/fbdev/i810/i810_main.c i810_writeb(CR_DATA_CGA, mmio, reg); reg 1817 drivers/video/fbdev/i810/i810_main.c u8 reg; reg 1832 drivers/video/fbdev/i810/i810_main.c pci_read_config_byte(par->dev, 0x50, ®); reg 1833 drivers/video/fbdev/i810/i810_main.c reg &= FREQ_MASK; reg 1834 drivers/video/fbdev/i810/i810_main.c par->mem_freq = (reg) ? 133 : 100; reg 1270 drivers/video/fbdev/imsttfb.c __u32 reg[2]; reg 1275 drivers/video/fbdev/imsttfb.c if (copy_from_user(reg, argp, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0])) reg 1277 drivers/video/fbdev/imsttfb.c write_reg_le32(par->dc_regs, reg[0], reg[1]); reg 1280 drivers/video/fbdev/imsttfb.c if (copy_from_user(reg, argp, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0])) reg 1282 drivers/video/fbdev/imsttfb.c reg[1] = read_reg_le32(par->dc_regs, reg[0]); reg 1283 drivers/video/fbdev/imsttfb.c if (copy_to_user((void __user *)(arg + 4), ®[1], 4)) reg 1287 drivers/video/fbdev/imsttfb.c if (copy_from_user(reg, argp, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0])) reg 1289 drivers/video/fbdev/imsttfb.c write_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0], reg[1]); reg 1292 drivers/video/fbdev/imsttfb.c if (copy_from_user(reg, argp, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0])) reg 1294 drivers/video/fbdev/imsttfb.c reg[1] = read_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0]); reg 1295 drivers/video/fbdev/imsttfb.c if (copy_to_user((void __user *)(arg + 4), ®[1], 4)) reg 250 drivers/video/fbdev/intelfb/intelfb.h u32 reg; reg 60 drivers/video/fbdev/intelfb/intelfb_i2c.c OUTREG(chan->reg, (state ? SCL_VAL_OUT : 0) | reg 62 drivers/video/fbdev/intelfb/intelfb_i2c.c val = INREG(chan->reg); reg 71 drivers/video/fbdev/intelfb/intelfb_i2c.c OUTREG(chan->reg, (state ? SDA_VAL_OUT : 0) | reg 73 drivers/video/fbdev/intelfb/intelfb_i2c.c val = INREG(chan->reg); reg 82 drivers/video/fbdev/intelfb/intelfb_i2c.c OUTREG(chan->reg, SCL_DIR_MASK); reg 83 drivers/video/fbdev/intelfb/intelfb_i2c.c OUTREG(chan->reg, 0); reg 84 drivers/video/fbdev/intelfb/intelfb_i2c.c val = INREG(chan->reg); reg 94 drivers/video/fbdev/intelfb/intelfb_i2c.c OUTREG(chan->reg, SDA_DIR_MASK); reg 95 drivers/video/fbdev/intelfb/intelfb_i2c.c OUTREG(chan->reg, 0); reg 96 drivers/video/fbdev/intelfb/intelfb_i2c.c val = INREG(chan->reg); reg 102 drivers/video/fbdev/intelfb/intelfb_i2c.c const u32 reg, const char *name, reg 108 drivers/video/fbdev/intelfb/intelfb_i2c.c chan->reg = reg; reg 24 drivers/video/fbdev/kyro/STG4000Reg.h #define STG_WRITE_REG(reg,data) (writel(data,&pSTGReg->reg)) reg 25 drivers/video/fbdev/kyro/STG4000Reg.h #define STG_READ_REG(reg) (readl(&pSTGReg->reg)) reg 27 drivers/video/fbdev/kyro/STG4000Reg.h #define STG_WRITE_REG(reg,data) (pSTGReg->reg = data) reg 28 drivers/video/fbdev/kyro/STG4000Reg.h #define STG_READ_REG(reg) (pSTGReg->reg) reg 613 drivers/video/fbdev/matrox/matroxfb_DAC1064.c int reg; reg 622 drivers/video/fbdev/matrox/matroxfb_DAC1064.c case 0: reg = M1064_XPIXPLLAM; break; reg 623 drivers/video/fbdev/matrox/matroxfb_DAC1064.c case 1: reg = M1064_XPIXPLLBM; break; reg 624 drivers/video/fbdev/matrox/matroxfb_DAC1064.c default: reg = M1064_XPIXPLLCM; break; reg 626 drivers/video/fbdev/matrox/matroxfb_DAC1064.c outDAC1064(minfo, reg++, m); reg 627 drivers/video/fbdev/matrox/matroxfb_DAC1064.c outDAC1064(minfo, reg++, n); reg 628 drivers/video/fbdev/matrox/matroxfb_DAC1064.c outDAC1064(minfo, reg, p); reg 645 drivers/video/fbdev/matrox/matroxfb_DAC1064.c printk(KERN_ERR "matroxfb: Pixel PLL%c not locked after usual time\n", (reg-M1064_XPIXPLLAM-2)/4 + 'A'); reg 721 drivers/video/fbdev/matrox/matroxfb_DAC1064.c pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3 & ~0x00300C03); reg 724 drivers/video/fbdev/matrox/matroxfb_DAC1064.c if (((minfo->values.reg.opt3 & 0x000003) == 0x000003) || reg 725 drivers/video/fbdev/matrox/matroxfb_DAC1064.c ((minfo->values.reg.opt3 & 0x000C00) == 0x000C00) || reg 726 drivers/video/fbdev/matrox/matroxfb_DAC1064.c ((minfo->values.reg.opt3 & 0x300000) == 0x300000)) { reg 741 drivers/video/fbdev/matrox/matroxfb_DAC1064.c pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3); reg 754 drivers/video/fbdev/matrox/matroxfb_DAC1064.c minfo->hw.MXoptionReg |= 0x00207E00 & minfo->values.reg.opt; reg 756 drivers/video/fbdev/matrox/matroxfb_DAC1064.c pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, minfo->values.reg.opt2); reg 758 drivers/video/fbdev/matrox/matroxfb_DAC1064.c mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); reg 761 drivers/video/fbdev/matrox/matroxfb_DAC1064.c pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc & ~0x80000000U); reg 762 drivers/video/fbdev/matrox/matroxfb_DAC1064.c mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); reg 763 drivers/video/fbdev/matrox/matroxfb_DAC1064.c mga_outl(M_MACCESS, minfo->values.reg.maccess); reg 765 drivers/video/fbdev/matrox/matroxfb_DAC1064.c pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc | 0x80000000U); reg 770 drivers/video/fbdev/matrox/matroxfb_DAC1064.c mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk & ~0x1000); reg 772 drivers/video/fbdev/matrox/matroxfb_DAC1064.c mga_outl(M_MACCESS, minfo->values.reg.maccess | 0x8000); reg 776 drivers/video/fbdev/matrox/matroxfb_DAC1064.c minfo->hw.MXoptionReg |= 0x001F8000 & minfo->values.reg.opt; reg 783 drivers/video/fbdev/matrox/matroxfb_DAC1064.c if (minfo->values.reg.mctlwtst != minfo->values.reg.mctlwtst_core) { reg 784 drivers/video/fbdev/matrox/matroxfb_DAC1064.c mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst_core); reg 804 drivers/video/fbdev/matrox/matroxfb_DAC1064.c minfo->hw.MXoptionReg |= minfo->values.reg.opt & 0x03400040; reg 911 drivers/video/fbdev/matrox/matroxfb_DAC1064.c mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); reg 942 drivers/video/fbdev/matrox/matroxfb_DAC1064.c hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00; reg 947 drivers/video/fbdev/matrox/matroxfb_DAC1064.c mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); reg 948 drivers/video/fbdev/matrox/matroxfb_DAC1064.c mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); reg 953 drivers/video/fbdev/matrox/matroxfb_DAC1064.c mga_outw(M_MEMRDBK, minfo->values.reg.memrdbk); reg 962 drivers/video/fbdev/matrox/matroxfb_DAC1064.c hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00; reg 967 drivers/video/fbdev/matrox/matroxfb_DAC1064.c mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); reg 968 drivers/video/fbdev/matrox/matroxfb_DAC1064.c mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); reg 973 drivers/video/fbdev/matrox/matroxfb_DAC1064.c mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); reg 487 drivers/video/fbdev/matrox/matroxfb_base.h } reg; reg 693 drivers/video/fbdev/matrox/matroxfb_base.h extern void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg, reg 695 drivers/video/fbdev/matrox/matroxfb_base.h extern int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg); reg 98 drivers/video/fbdev/matrox/matroxfb_g450.c static int cve2_get_reg(struct matrox_fb_info *minfo, int reg) reg 104 drivers/video/fbdev/matrox/matroxfb_g450.c matroxfb_DAC_out(minfo, 0x87, reg); reg 110 drivers/video/fbdev/matrox/matroxfb_g450.c static void cve2_set_reg(struct matrox_fb_info *minfo, int reg, int val) reg 115 drivers/video/fbdev/matrox/matroxfb_g450.c matroxfb_DAC_out(minfo, 0x87, reg); reg 120 drivers/video/fbdev/matrox/matroxfb_g450.c static void cve2_set_reg10(struct matrox_fb_info *minfo, int reg, int val) reg 125 drivers/video/fbdev/matrox/matroxfb_g450.c matroxfb_DAC_out(minfo, 0x87, reg); reg 127 drivers/video/fbdev/matrox/matroxfb_g450.c matroxfb_DAC_out(minfo, 0x87, reg + 1); reg 139 drivers/video/fbdev/matrox/matroxfb_maven.c static int maven_get_reg(struct i2c_client* c, char reg) { reg 145 drivers/video/fbdev/matrox/matroxfb_maven.c .len = sizeof(reg), reg 146 drivers/video/fbdev/matrox/matroxfb_maven.c .buf = ® reg 159 drivers/video/fbdev/matrox/matroxfb_maven.c printk(KERN_INFO "ReadReg(%d) failed\n", reg); reg 163 drivers/video/fbdev/matrox/matroxfb_maven.c static int maven_set_reg(struct i2c_client* c, int reg, int val) { reg 166 drivers/video/fbdev/matrox/matroxfb_maven.c err = i2c_smbus_write_byte_data(c, reg, val); reg 168 drivers/video/fbdev/matrox/matroxfb_maven.c printk(KERN_INFO "WriteReg(%d) failed\n", reg); reg 172 drivers/video/fbdev/matrox/matroxfb_maven.c static int maven_set_reg_pair(struct i2c_client* c, int reg, int val) { reg 175 drivers/video/fbdev/matrox/matroxfb_maven.c err = i2c_smbus_write_word_data(c, reg, val); reg 177 drivers/video/fbdev/matrox/matroxfb_maven.c printk(KERN_INFO "WriteRegPair(%d) failed\n", reg); reg 93 drivers/video/fbdev/matrox/matroxfb_misc.c void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg, int val) reg 96 drivers/video/fbdev/matrox/matroxfb_misc.c mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg); reg 100 drivers/video/fbdev/matrox/matroxfb_misc.c int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg) reg 103 drivers/video/fbdev/matrox/matroxfb_misc.c mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg); reg 548 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.mctlwtst = 0x00030101; reg 558 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.mctlwtst = 0x00030101; reg 566 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) | reg 580 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.mctlwtst = 0x00030101; reg 590 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 48) == 0xFFFFFFFF ? reg 593 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) | reg 597 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.opt = (bd->pins[54] & 7) << 10; reg 598 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.opt2 = bd->pins[58] << 12; reg 608 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.mctlwtst = 0x01250A21; reg 609 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.memrdbk = 0x00000000; reg 610 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.opt = 0x00000C00; reg 611 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.opt2 = 0x00000000; reg 620 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 71); reg 621 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) | reg 625 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) | reg 628 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 67); reg 639 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.mctlwtst = 0x04A450A1; reg 640 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.memrdbk = 0x000000E7; reg 641 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.opt = 0x10000400; reg 642 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.opt3 = 0x0190A419; reg 662 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.opt = get_unaligned_le32(bd->pins + 48); reg 663 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.opt2 = get_unaligned_le32(bd->pins + 52); reg 664 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 94); reg 665 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 98); reg 666 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.memmisc = get_unaligned_le32(bd->pins + 102); reg 667 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.memrdbk = get_unaligned_le32(bd->pins + 106); reg 672 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.maccess = minfo->values.memory.emrswen ? 0x00004000 : 0x00000000; reg 674 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.mctlwtst_core = minfo->values.reg.mctlwtst; reg 677 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.mctlwtst_core = (minfo->values.reg.mctlwtst & ~7) | reg 678 drivers/video/fbdev/matrox/matroxfb_misc.c wtst_xlat[minfo->values.reg.mctlwtst & 7]; reg 695 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.opt = 0x404A1160; reg 696 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.opt2 = 0x0000AC00; reg 697 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.opt3 = 0x0090A409; reg 698 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.mctlwtst_core = reg 699 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.mctlwtst = 0x0C81462B; reg 700 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.memmisc = 0x80000004; reg 701 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.memrdbk = 0x01001103; reg 706 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.reg.maccess = 0x00004000; reg 803 drivers/video/fbdev/matrox/matroxfb_misc.c (minfo->values.reg.opt & 0x1C00) >> 10); reg 20 drivers/video/fbdev/mb862xx/mb862xx-i2c.c u32 reg; reg 24 drivers/video/fbdev/mb862xx/mb862xx-i2c.c reg = inreg(i2c, GC_I2C_BCR); reg 25 drivers/video/fbdev/mb862xx/mb862xx-i2c.c if (reg & (I2C_INT | I2C_BER)) reg 29 drivers/video/fbdev/mb862xx/mb862xx-i2c.c return (reg & I2C_BER) ? 0 : 1; reg 203 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c unsigned long reg, sc; reg 213 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_DCM1); reg 214 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg &= ~GC_DCM01_DEN; reg 215 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_DCM1, reg); reg 219 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_DCM1); reg 220 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC); reg 221 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg |= sc << 8; reg 222 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_DCM1, reg); reg 226 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT, reg 229 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg |= GC_L0M_L0C_16; reg 230 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L0M, reg); reg 233 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_L0EM); reg 234 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24); reg 237 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = pack(fbi->var.yres - 1, fbi->var.xres); reg 238 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_WH_WW, reg); reg 243 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L0WH_L0WW, reg); reg 246 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_CPM_CUTC); reg 247 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg &= ~(GC_CPM_CEN0 | GC_CPM_CEN1); reg 248 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_CPM_CUTC, reg); reg 251 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = pack(fbi->var.xres - 1, fbi->var.xres - 1); reg 252 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_HDB_HDP, reg); reg 253 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = pack((fbi->var.yres - 1), vsp(&fbi->var)); reg 254 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_VDP_VSP, reg); reg 255 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = ((fbi->var.vsync_len - 1) << 24) | reg 257 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_VSW_HSW_HSP, reg); reg 262 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_DCM1); reg 263 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg |= GC_DCM01_DEN | GC_DCM01_L0E; reg 264 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg &= ~GC_DCM01_ESY; reg 265 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_DCM1, reg); reg 273 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c unsigned long reg; reg 275 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = pack(var->yoffset, var->xoffset); reg 276 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L0WY_L0WX, reg); reg 278 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = pack(info->var.yres_virtual, info->var.xres_virtual); reg 279 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_L0WH_L0WW, reg); reg 286 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c unsigned long reg; reg 292 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_DCM1); reg 293 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg &= ~GC_DCM01_DEN; reg 294 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_DCM1, reg); reg 297 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_DCM1); reg 298 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg |= GC_DCM01_DEN; reg 299 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_DCM1, reg); reg 422 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c unsigned long reg; reg 441 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_DCM1); reg 442 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) { reg 444 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c unsigned long sc = ((reg & GC_DCM01_SC) >> 8) + 1; reg 450 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_VDP_VSP); reg 451 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c fbi->var.yres = ((reg >> 16) & 0x0fff) + 1; reg 452 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c vsp = (reg & 0x0fff) + 1; reg 455 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_L0EM); reg 456 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c if (reg & GC_L0EM_L0EC_24) { reg 459 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_L0M); reg 460 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c if (reg & GC_L0M_L0C_16) reg 465 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_VSW_HSW_HSP); reg 466 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c fbi->var.hsync_len = ((reg & 0xff0000) >> 16) + 1; reg 467 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c fbi->var.vsync_len = ((reg & 0x3f000000) >> 24) + 1; reg 468 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c hsp = (reg & 0xffff) + 1; reg 549 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c unsigned int reg; reg 551 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c for (reg = GC_DCM0; reg <= GC_L0DY_L0DX; reg += 4) reg 553 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg, inreg(disp, reg)); reg 555 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c for (reg = GC_CPM_CUTC; reg <= GC_CUY1_CUX1; reg += 4) reg 557 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg, inreg(disp, reg)); reg 559 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c for (reg = GC_DCM1; reg <= GC_L0WH_L0WW; reg += 4) reg 561 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg, inreg(disp, reg)); reg 563 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c for (reg = 0x400; reg <= 0x410; reg += 4) reg 565 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg, inreg(geo, reg)); reg 567 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c for (reg = 0x400; reg <= 0x410; reg += 4) reg 569 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg, inreg(draw, reg)); reg 571 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c for (reg = 0x440; reg <= 0x450; reg += 4) reg 573 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg, inreg(draw, reg)); reg 787 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c unsigned long reg; reg 792 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_DCM1); reg 793 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E); reg 794 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_DCM1, reg); reg 865 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c unsigned long reg; reg 870 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_DCM1); reg 871 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) reg 924 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c unsigned long reg; reg 939 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = GC_CTRL_CLK_EN_DRAM | GC_CTRL_CLK_EN_2D3D | GC_CTRL_CLK_EN_DISP0; reg 940 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(ctrl, GC_CTRL_CLK_ENABLE, reg); reg 949 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg &= ~GC_CTRL_CLK_EN_2D3D; reg 950 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(ctrl, GC_CTRL_CLK_ENABLE, reg); reg 1131 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c unsigned long reg; reg 1136 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg = inreg(disp, GC_DCM1); reg 1137 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E); reg 1138 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c outreg(disp, GC_DCM1, reg); reg 38 drivers/video/fbdev/mbx/mbxfb.c #define write_reg(val, reg) do { writel((val), (reg)); } while(0) reg 44 drivers/video/fbdev/mbx/mbxfb.c #define write_reg_dly(val, reg) do { writel((val), reg); udelay(1000); } while(0) reg 607 drivers/video/fbdev/mbx/mbxfb.c struct mbxfb_reg reg; reg 643 drivers/video/fbdev/mbx/mbxfb.c if (copy_from_user(®, (void __user*)arg, reg 647 drivers/video/fbdev/mbx/mbxfb.c if (reg.addr >= 0x10000) /* regs are from 0x3fe0000 to 0x3feffff */ reg 650 drivers/video/fbdev/mbx/mbxfb.c tmp = readl(virt_base_2700 + reg.addr); reg 651 drivers/video/fbdev/mbx/mbxfb.c tmp &= ~reg.mask; reg 652 drivers/video/fbdev/mbx/mbxfb.c tmp |= reg.val & reg.mask; reg 653 drivers/video/fbdev/mbx/mbxfb.c writel(tmp, virt_base_2700 + reg.addr); reg 657 drivers/video/fbdev/mbx/mbxfb.c if (copy_from_user(®, (void __user*)arg, reg 661 drivers/video/fbdev/mbx/mbxfb.c if (reg.addr >= 0x10000) /* regs are from 0x3fe0000 to 0x3feffff */ reg 663 drivers/video/fbdev/mbx/mbxfb.c reg.val = readl(virt_base_2700 + reg.addr); reg 665 drivers/video/fbdev/mbx/mbxfb.c if (copy_to_user((void __user*)arg, ®, reg 343 drivers/video/fbdev/mx3fb.c static u32 mx3fb_read_reg(struct mx3fb_data *mx3fb, unsigned long reg) reg 345 drivers/video/fbdev/mx3fb.c return __raw_readl(mx3fb->reg_base + reg); reg 348 drivers/video/fbdev/mx3fb.c static void mx3fb_write_reg(struct mx3fb_data *mx3fb, u32 value, unsigned long reg) reg 350 drivers/video/fbdev/mx3fb.c __raw_writel(value, mx3fb->reg_base + reg); reg 366 drivers/video/fbdev/mx3fb.c uint32_t reg; reg 368 drivers/video/fbdev/mx3fb.c reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); reg 370 drivers/video/fbdev/mx3fb.c mx3fb_write_reg(mx3fb, reg | SDC_COM_BG_EN, SDC_COM_CONF); reg 377 drivers/video/fbdev/mx3fb.c uint32_t reg; reg 379 drivers/video/fbdev/mx3fb.c reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); reg 381 drivers/video/fbdev/mx3fb.c mx3fb_write_reg(mx3fb, reg & ~SDC_COM_BG_EN, SDC_COM_CONF); reg 383 drivers/video/fbdev/mx3fb.c return reg & SDC_COM_BG_EN; reg 515 drivers/video/fbdev/mx3fb.c uint32_t reg; reg 527 drivers/video/fbdev/mx3fb.c reg = ((uint32_t) (h_sync_width - 1) << 26) | reg 529 drivers/video/fbdev/mx3fb.c mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF); reg 532 drivers/video/fbdev/mx3fb.c printk(KERN_CONT " hor_conf %x,", reg); reg 535 drivers/video/fbdev/mx3fb.c reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L | reg 537 drivers/video/fbdev/mx3fb.c mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF); reg 540 drivers/video/fbdev/mx3fb.c printk(KERN_CONT " ver_conf %x\n", reg); reg 635 drivers/video/fbdev/mx3fb.c uint32_t reg, sdc_conf; reg 647 drivers/video/fbdev/mx3fb.c reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0xFF000000L; reg 648 drivers/video/fbdev/mx3fb.c mx3fb_write_reg(mx3fb, reg | (color_key & 0x00FFFFFFL), reg 672 drivers/video/fbdev/mx3fb.c uint32_t reg; reg 678 drivers/video/fbdev/mx3fb.c reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0x00FFFFFFL; reg 679 drivers/video/fbdev/mx3fb.c mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL); reg 681 drivers/video/fbdev/mx3fb.c reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); reg 682 drivers/video/fbdev/mx3fb.c mx3fb_write_reg(mx3fb, reg | SDC_COM_GLB_A, SDC_COM_CONF); reg 684 drivers/video/fbdev/mx3fb.c reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); reg 685 drivers/video/fbdev/mx3fb.c mx3fb_write_reg(mx3fb, reg & ~SDC_COM_GLB_A, SDC_COM_CONF); reg 1265 drivers/video/fbdev/neofb.c int seqflags, lcdflags, dpmsflags, reg, tmpdisp; reg 1350 drivers/video/fbdev/neofb.c reg = (vga_rseq(NULL, 0x01) & ~0x20) | seqflags; reg 1351 drivers/video/fbdev/neofb.c vga_wseq(NULL, 0x01, reg); reg 1352 drivers/video/fbdev/neofb.c reg = (vga_rgfx(NULL, 0x20) & ~0x02) | lcdflags; reg 1353 drivers/video/fbdev/neofb.c vga_wgfx(NULL, 0x20, reg); reg 1354 drivers/video/fbdev/neofb.c reg = (vga_rgfx(NULL, 0x01) & ~0xF0) | 0x80 | dpmsflags; reg 1355 drivers/video/fbdev/neofb.c vga_wgfx(NULL, 0x01, reg); reg 127 drivers/video/fbdev/omap/hwa742.c static u8 hwa742_read_reg(u8 reg) reg 132 drivers/video/fbdev/omap/hwa742.c hwa742.extif->write_command(®, 1); reg 138 drivers/video/fbdev/omap/hwa742.c static void hwa742_write_reg(u8 reg, u8 data) reg 141 drivers/video/fbdev/omap/hwa742.c hwa742.extif->write_command(®, 1); reg 117 drivers/video/fbdev/omap/lcd_mipid.c int reg, const u8 *buf, int len) reg 119 drivers/video/fbdev/omap/lcd_mipid.c mipid_transfer(md, reg, buf, len, NULL, 0); reg 123 drivers/video/fbdev/omap/lcd_mipid.c int reg, u8 *buf, int len) reg 125 drivers/video/fbdev/omap/lcd_mipid.c mipid_transfer(md, reg, NULL, 0, buf, len); reg 70 drivers/video/fbdev/omap/sossi.c static inline u32 sossi_read_reg(int reg) reg 72 drivers/video/fbdev/omap/sossi.c return readl(sossi.base + reg); reg 75 drivers/video/fbdev/omap/sossi.c static inline u16 sossi_read_reg16(int reg) reg 77 drivers/video/fbdev/omap/sossi.c return readw(sossi.base + reg); reg 80 drivers/video/fbdev/omap/sossi.c static inline u8 sossi_read_reg8(int reg) reg 82 drivers/video/fbdev/omap/sossi.c return readb(sossi.base + reg); reg 85 drivers/video/fbdev/omap/sossi.c static inline void sossi_write_reg(int reg, u32 value) reg 87 drivers/video/fbdev/omap/sossi.c writel(value, sossi.base + reg); reg 90 drivers/video/fbdev/omap/sossi.c static inline void sossi_write_reg16(int reg, u16 value) reg 92 drivers/video/fbdev/omap/sossi.c writew(value, sossi.base + reg); reg 95 drivers/video/fbdev/omap/sossi.c static inline void sossi_write_reg8(int reg, u8 value) reg 97 drivers/video/fbdev/omap/sossi.c writeb(value, sossi.base + reg); reg 100 drivers/video/fbdev/omap/sossi.c static void sossi_set_bits(int reg, u32 bits) reg 102 drivers/video/fbdev/omap/sossi.c sossi_write_reg(reg, sossi_read_reg(reg) | bits); reg 105 drivers/video/fbdev/omap/sossi.c static void sossi_clear_bits(int reg, u32 bits) reg 107 drivers/video/fbdev/omap/sossi.c sossi_write_reg(reg, sossi_read_reg(reg) & ~bits); reg 57 drivers/video/fbdev/omap2/omapfb/displays/panel-lgphilips-lb035q02.c static int lb035q02_write_reg(struct spi_device *spi, u8 reg, u16 val) reg 74 drivers/video/fbdev/omap2/omapfb/displays/panel-lgphilips-lb035q02.c buffer[2] = reg & 0x7f; reg 161 drivers/video/fbdev/omap2/omapfb/displays/panel-sony-acx565akm.c int reg, const u8 *buf, int len) reg 163 drivers/video/fbdev/omap2/omapfb/displays/panel-sony-acx565akm.c acx565akm_transfer(ddata, reg, buf, len, NULL, 0); reg 167 drivers/video/fbdev/omap2/omapfb/displays/panel-sony-acx565akm.c int reg, u8 *buf, int len) reg 169 drivers/video/fbdev/omap2/omapfb/displays/panel-sony-acx565akm.c acx565akm_transfer(ddata, reg, NULL, 0, buf, len); reg 55 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c static int jbt_ret_write_0(struct panel_drv_data *ddata, u8 reg) reg 58 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c u16 tx_buf = JBT_COMMAND | reg; reg 69 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c static int jbt_reg_write_1(struct panel_drv_data *ddata, u8 reg, u8 data) reg 74 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c tx_buf[0] = JBT_COMMAND | reg; reg 85 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c static int jbt_reg_write_2(struct panel_drv_data *ddata, u8 reg, u16 data) reg 90 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c tx_buf[0] = JBT_COMMAND | reg; reg 156 drivers/video/fbdev/omap2/omapfb/dss/dispc.c u16 reg; reg 264 drivers/video/fbdev/omap2/omapfb/dss/dispc.c return REG_GET(rfld.reg, rfld.high, rfld.low); reg 270 drivers/video/fbdev/omap2/omapfb/dss/dispc.c const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG; reg 276 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low); reg 282 drivers/video/fbdev/omap2/omapfb/dss/dispc.c #define SR(reg) \ reg 283 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg) reg 284 drivers/video/fbdev/omap2/omapfb/dss/dispc.c #define RR(reg) \ reg 285 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)]) reg 606 drivers/video/fbdev/omap2/omapfb/dss/dispc.c static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value) reg 608 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value); reg 611 drivers/video/fbdev/omap2/omapfb/dss/dispc.c static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value) reg 613 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value); reg 616 drivers/video/fbdev/omap2/omapfb/dss/dispc.c static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value) reg 618 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value); reg 621 drivers/video/fbdev/omap2/omapfb/dss/dispc.c static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value) reg 625 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value); reg 628 drivers/video/fbdev/omap2/omapfb/dss/dispc.c static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg, reg 633 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value); reg 636 drivers/video/fbdev/omap2/omapfb/dss/dispc.c static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value) reg 640 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value); reg 111 drivers/video/fbdev/omap2/omapfb/dss/dss-of.c u32 reg; reg 113 drivers/video/fbdev/omap2/omapfb/dss/dss-of.c r = of_property_read_u32(port, "reg", ®); reg 115 drivers/video/fbdev/omap2/omapfb/dss/dss-of.c reg = 0; reg 117 drivers/video/fbdev/omap2/omapfb/dss/dss-of.c return reg; reg 123 drivers/video/fbdev/omap2/omapfb/dss/dss.c #define SR(reg) \ reg 124 drivers/video/fbdev/omap2/omapfb/dss/dss.c dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg) reg 125 drivers/video/fbdev/omap2/omapfb/dss/dss.c #define RR(reg) \ reg 126 drivers/video/fbdev/omap2/omapfb/dss/dss.c dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)]) reg 933 drivers/video/fbdev/omap2/omapfb/dss/dss.c u32 reg; reg 935 drivers/video/fbdev/omap2/omapfb/dss/dss.c r = of_property_read_u32(port, "reg", ®); reg 937 drivers/video/fbdev/omap2/omapfb/dss/dss.c reg = 0; reg 939 drivers/video/fbdev/omap2/omapfb/dss/dss.c if (reg >= dss.feat->num_ports) reg 942 drivers/video/fbdev/omap2/omapfb/dss/dss.c port_type = dss.feat->ports[reg]; reg 980 drivers/video/fbdev/omap2/omapfb/dss/dss.c u32 reg; reg 983 drivers/video/fbdev/omap2/omapfb/dss/dss.c r = of_property_read_u32(port, "reg", ®); reg 985 drivers/video/fbdev/omap2/omapfb/dss/dss.c reg = 0; reg 987 drivers/video/fbdev/omap2/omapfb/dss/dss.c if (reg >= dss.feat->num_ports) reg 990 drivers/video/fbdev/omap2/omapfb/dss/dss.c port_type = dss.feat->ports[reg]; reg 92 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c struct regulator *reg; reg 97 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); reg 99 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c if (IS_ERR(reg)) { reg 100 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c if (PTR_ERR(reg) != -EPROBE_DEFER) reg 102 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c return PTR_ERR(reg); reg 105 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi.vdda_reg = reg; reg 111 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c struct regulator *reg; reg 116 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); reg 117 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c if (IS_ERR(reg)) { reg 119 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c return PTR_ERR(reg); reg 122 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi.vdda_reg = reg; reg 128 drivers/video/fbdev/omap2/omapfb/dss/output.c u32 reg; reg 134 drivers/video/fbdev/omap2/omapfb/dss/output.c reg = dss_of_port_get_port_number(port); reg 137 drivers/video/fbdev/omap2/omapfb/dss/output.c if (out->dev->of_node == src_node && out->port_num == reg) { reg 187 drivers/video/fbdev/omap2/omapfb/dss/pll.c static int wait_for_bit_change(void __iomem *reg, int bitnum, int value) reg 196 drivers/video/fbdev/omap2/omapfb/dss/pll.c if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value) reg 203 drivers/video/fbdev/omap2/omapfb/dss/pll.c if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value) reg 27 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c #define REG_MOD(reg, val, start, end) \ reg 28 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg) reg 279 drivers/video/fbdev/platinumfb.c out_be32(&platinum_regs->reg[24].r, 7); /* turn display off */ reg 282 drivers/video/fbdev/platinumfb.c out_be32(&platinum_regs->reg[i+32].r, init->regs[i]); reg 284 drivers/video/fbdev/platinumfb.c out_be32(&platinum_regs->reg[26+32].r, (pinfo->total_vram == 0x100000 ? reg 287 drivers/video/fbdev/platinumfb.c out_be32(&platinum_regs->reg[16].r, (unsigned) pinfo->frame_buffer_phys+init->fb_offset+0x10); reg 288 drivers/video/fbdev/platinumfb.c out_be32(&platinum_regs->reg[18].r, init->pitch[cmode]); reg 289 drivers/video/fbdev/platinumfb.c out_be32(&platinum_regs->reg[19].r, (pinfo->total_vram == 0x100000 ? reg 292 drivers/video/fbdev/platinumfb.c out_be32(&platinum_regs->reg[20].r, (pinfo->total_vram == 0x100000 ? 0x11 : 0x1011)); reg 293 drivers/video/fbdev/platinumfb.c out_be32(&platinum_regs->reg[21].r, 0x100); reg 294 drivers/video/fbdev/platinumfb.c out_be32(&platinum_regs->reg[22].r, 1); reg 295 drivers/video/fbdev/platinumfb.c out_be32(&platinum_regs->reg[23].r, 1); reg 296 drivers/video/fbdev/platinumfb.c out_be32(&platinum_regs->reg[26].r, 0xc00); reg 297 drivers/video/fbdev/platinumfb.c out_be32(&platinum_regs->reg[27].r, 0x235); reg 308 drivers/video/fbdev/platinumfb.c out_be32(&platinum_regs->reg[24].r, 0); /* turn display on */ reg 414 drivers/video/fbdev/platinumfb.c out_be32(&platinum_regs->reg[23].r, 7); /* turn off drivers */ reg 416 drivers/video/fbdev/platinumfb.c sense = (~in_be32(&platinum_regs->reg[23].r) & 7) << 8; reg 419 drivers/video/fbdev/platinumfb.c out_be32(&platinum_regs->reg[23].r, 3); /* drive A low */ reg 421 drivers/video/fbdev/platinumfb.c sense |= (~in_be32(&platinum_regs->reg[23].r) & 3) << 4; reg 422 drivers/video/fbdev/platinumfb.c out_be32(&platinum_regs->reg[23].r, 5); /* drive B low */ reg 424 drivers/video/fbdev/platinumfb.c sense |= (~in_be32(&platinum_regs->reg[23].r) & 4) << 1; reg 425 drivers/video/fbdev/platinumfb.c sense |= (~in_be32(&platinum_regs->reg[23].r) & 1) << 2; reg 426 drivers/video/fbdev/platinumfb.c out_be32(&platinum_regs->reg[23].r, 6); /* drive C low */ reg 428 drivers/video/fbdev/platinumfb.c sense |= (~in_be32(&platinum_regs->reg[23].r) & 6) >> 1; reg 430 drivers/video/fbdev/platinumfb.c out_be32(&platinum_regs->reg[23].r, 7); /* turn off drivers */ reg 584 drivers/video/fbdev/platinumfb.c out_be32(&pinfo->platinum_regs->reg[16].r, (unsigned)pinfo->frame_buffer_phys); reg 585 drivers/video/fbdev/platinumfb.c out_be32(&pinfo->platinum_regs->reg[20].r, 0x1011); /* select max vram */ reg 586 drivers/video/fbdev/platinumfb.c out_be32(&pinfo->platinum_regs->reg[24].r, 0); /* switch in vram */ reg 45 drivers/video/fbdev/platinumfb.h struct preg reg[128]; reg 80 drivers/video/fbdev/pmag-ba-fb.c static inline void dac_write(struct pmagbafb_par *par, unsigned int reg, u8 v) reg 82 drivers/video/fbdev/pmag-ba-fb.c writeb(v, par->dac + reg / 4); reg 85 drivers/video/fbdev/pmag-ba-fb.c static inline u8 dac_read(struct pmagbafb_par *par, unsigned int reg) reg 87 drivers/video/fbdev/pmag-ba-fb.c return readb(par->dac + reg / 4); reg 69 drivers/video/fbdev/pmagb-b-fb.c static inline void sfb_write(struct pmagbbfb_par *par, unsigned int reg, u32 v) reg 71 drivers/video/fbdev/pmagb-b-fb.c writel(v, par->sfb + reg / 4); reg 74 drivers/video/fbdev/pmagb-b-fb.c static inline u32 sfb_read(struct pmagbbfb_par *par, unsigned int reg) reg 76 drivers/video/fbdev/pmagb-b-fb.c return readl(par->sfb + reg / 4); reg 79 drivers/video/fbdev/pmagb-b-fb.c static inline void dac_write(struct pmagbbfb_par *par, unsigned int reg, u8 v) reg 81 drivers/video/fbdev/pmagb-b-fb.c writeb(v, par->dac + reg / 4); reg 84 drivers/video/fbdev/pmagb-b-fb.c static inline u8 dac_read(struct pmagbbfb_par *par, unsigned int reg) reg 86 drivers/video/fbdev/pmagb-b-fb.c return readb(par->dac + reg / 4); reg 44 drivers/video/fbdev/riva/nvreg.h #define DEVICE_ACCESS(device,reg) \ reg 45 drivers/video/fbdev/riva/nvreg.h nvCONTROL[(NV_##device##_##reg)/4] reg 47 drivers/video/fbdev/riva/nvreg.h #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) reg 48 drivers/video/fbdev/riva/nvreg.h #define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) reg 49 drivers/video/fbdev/riva/nvreg.h #define DEVICE_PRINT(device,reg) \ reg 50 drivers/video/fbdev/riva/nvreg.h ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg)) reg 56 drivers/video/fbdev/riva/nvreg.h #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) reg 57 drivers/video/fbdev/riva/nvreg.h #define PDAC_Read(reg) DEVICE_READ(PDAC,reg) reg 58 drivers/video/fbdev/riva/nvreg.h #define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg) reg 63 drivers/video/fbdev/riva/nvreg.h #define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) reg 64 drivers/video/fbdev/riva/nvreg.h #define PFB_Read(reg) DEVICE_READ(PFB,reg) reg 65 drivers/video/fbdev/riva/nvreg.h #define PFB_Print(reg) DEVICE_PRINT(PFB,reg) reg 70 drivers/video/fbdev/riva/nvreg.h #define PRM_Write(reg,value) DEVICE_WRITE(PRM,reg,value) reg 71 drivers/video/fbdev/riva/nvreg.h #define PRM_Read(reg) DEVICE_READ(PRM,reg) reg 72 drivers/video/fbdev/riva/nvreg.h #define PRM_Print(reg) DEVICE_PRINT(PRM,reg) reg 77 drivers/video/fbdev/riva/nvreg.h #define PGRAPH_Write(reg,value) DEVICE_WRITE(PGRAPH,reg,value) reg 78 drivers/video/fbdev/riva/nvreg.h #define PGRAPH_Read(reg) DEVICE_READ(PGRAPH,reg) reg 79 drivers/video/fbdev/riva/nvreg.h #define PGRAPH_Print(reg) DEVICE_PRINT(PGRAPH,reg) reg 84 drivers/video/fbdev/riva/nvreg.h #define PDMA_Write(reg,value) DEVICE_WRITE(PDMA,reg,value) reg 85 drivers/video/fbdev/riva/nvreg.h #define PDMA_Read(reg) DEVICE_READ(PDMA,reg) reg 86 drivers/video/fbdev/riva/nvreg.h #define PDMA_Print(reg) DEVICE_PRINT(PDMA,reg) reg 91 drivers/video/fbdev/riva/nvreg.h #define PTIMER_Write(reg,value) DEVICE_WRITE(PTIMER,reg,value) reg 92 drivers/video/fbdev/riva/nvreg.h #define PTIMER_Read(reg) DEVICE_READ(PTIMER,reg) reg 93 drivers/video/fbdev/riva/nvreg.h #define PTIMER_Print(reg) DEVICE_PRINT(PTIMER,reg) reg 98 drivers/video/fbdev/riva/nvreg.h #define PEXTDEV_Write(reg,value) DEVICE_WRITE(PEXTDEV,reg,value) reg 99 drivers/video/fbdev/riva/nvreg.h #define PEXTDEV_Read(reg) DEVICE_READ(PEXTDEV,reg) reg 100 drivers/video/fbdev/riva/nvreg.h #define PEXTDEV_Print(reg) DEVICE_PRINT(PEXTDEV,reg) reg 105 drivers/video/fbdev/riva/nvreg.h #define PFIFO_Write(reg,value) DEVICE_WRITE(PFIFO,reg,value) reg 106 drivers/video/fbdev/riva/nvreg.h #define PFIFO_Read(reg) DEVICE_READ(PFIFO,reg) reg 107 drivers/video/fbdev/riva/nvreg.h #define PFIFO_Print(reg) DEVICE_PRINT(PFIFO,reg) reg 112 drivers/video/fbdev/riva/nvreg.h #define PRAM_Write(reg,value) DEVICE_WRITE(PRAM,reg,value) reg 113 drivers/video/fbdev/riva/nvreg.h #define PRAM_Read(reg) DEVICE_READ(PRAM,reg) reg 114 drivers/video/fbdev/riva/nvreg.h #define PRAM_Print(reg) DEVICE_PRINT(PRAM,reg) reg 119 drivers/video/fbdev/riva/nvreg.h #define PRAMFC_Write(reg,value) DEVICE_WRITE(PRAMFC,reg,value) reg 120 drivers/video/fbdev/riva/nvreg.h #define PRAMFC_Read(reg) DEVICE_READ(PRAMFC,reg) reg 121 drivers/video/fbdev/riva/nvreg.h #define PRAMFC_Print(reg) DEVICE_PRINT(PRAMFC,reg) reg 126 drivers/video/fbdev/riva/nvreg.h #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value) reg 127 drivers/video/fbdev/riva/nvreg.h #define PMC_Read(reg) DEVICE_READ(PMC,reg) reg 128 drivers/video/fbdev/riva/nvreg.h #define PMC_Print(reg) DEVICE_PRINT(PMC,reg) reg 133 drivers/video/fbdev/riva/nvreg.h #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value) reg 134 drivers/video/fbdev/riva/nvreg.h #define PMC_Read(reg) DEVICE_READ(PMC,reg) reg 135 drivers/video/fbdev/riva/nvreg.h #define PMC_Print(reg) DEVICE_PRINT(PMC,reg) reg 141 drivers/video/fbdev/riva/nvreg.h #define PBUS_Write(reg,value) DEVICE_WRITE(PBUS,reg,value) reg 142 drivers/video/fbdev/riva/nvreg.h #define PBUS_Read(reg) DEVICE_READ(PBUS,reg) reg 143 drivers/video/fbdev/riva/nvreg.h #define PBUS_Print(reg) DEVICE_PRINT(PBUS,reg) reg 149 drivers/video/fbdev/riva/nvreg.h #define PRAMDAC_Write(reg,value) DEVICE_WRITE(PRAMDAC,reg,value) reg 150 drivers/video/fbdev/riva/nvreg.h #define PRAMDAC_Read(reg) DEVICE_READ(PRAMDAC,reg) reg 151 drivers/video/fbdev/riva/nvreg.h #define PRAMDAC_Print(reg) DEVICE_PRINT(PRAMDAC,reg) reg 157 drivers/video/fbdev/riva/nvreg.h #define PDAC_ReadExt(reg) \ reg 158 drivers/video/fbdev/riva/nvreg.h ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\ reg 159 drivers/video/fbdev/riva/nvreg.h (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\ reg 162 drivers/video/fbdev/riva/nvreg.h #define PDAC_WriteExt(reg,value)\ reg 163 drivers/video/fbdev/riva/nvreg.h ((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\ reg 164 drivers/video/fbdev/riva/nvreg.h (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\ reg 425 drivers/video/fbdev/s3c-fb.c u32 reg; reg 431 drivers/video/fbdev/s3c-fb.c reg = readl(sfb->regs + SHADOWCON); reg 432 drivers/video/fbdev/s3c-fb.c writel(reg | SHADOWCON_WINx_PROTECT(win->index), reg 439 drivers/video/fbdev/s3c-fb.c reg = readl(sfb->regs + SHADOWCON); reg 440 drivers/video/fbdev/s3c-fb.c writel(reg & ~SHADOWCON_WINx_PROTECT(win->index), reg 698 drivers/video/fbdev/s3c-fb.c unsigned int reg, reg 707 drivers/video/fbdev/s3c-fb.c __func__, win->index, reg, palreg, value); reg 709 drivers/video/fbdev/s3c-fb.c win->palette_buffer[reg] = value; reg 715 drivers/video/fbdev/s3c-fb.c writew(value, palreg + (reg * 2)); reg 717 drivers/video/fbdev/s3c-fb.c writel(value, palreg + (reg * 4)); reg 1339 drivers/video/fbdev/s3c-fb.c u32 reg; reg 1347 drivers/video/fbdev/s3c-fb.c reg = readl(sfb->regs + SHADOWCON); reg 1348 drivers/video/fbdev/s3c-fb.c reg &= ~(SHADOWCON_WINx_PROTECT(win) | reg 1351 drivers/video/fbdev/s3c-fb.c writel(reg, sfb->regs + SHADOWCON); reg 1365 drivers/video/fbdev/s3c-fb.c u32 reg; reg 1448 drivers/video/fbdev/s3c-fb.c reg = readl(sfb->regs + VIDCON1); reg 1449 drivers/video/fbdev/s3c-fb.c reg &= ~VIDCON1_VCLK_MASK; reg 1450 drivers/video/fbdev/s3c-fb.c reg |= VIDCON1_VCLK_RUN; reg 1451 drivers/video/fbdev/s3c-fb.c writel(reg, sfb->regs + VIDCON1); reg 1569 drivers/video/fbdev/s3c-fb.c u32 reg; reg 1584 drivers/video/fbdev/s3c-fb.c reg = readl(sfb->regs + VIDCON1); reg 1585 drivers/video/fbdev/s3c-fb.c reg &= ~VIDCON1_VCLK_MASK; reg 1586 drivers/video/fbdev/s3c-fb.c reg |= VIDCON1_VCLK_RUN; reg 1587 drivers/video/fbdev/s3c-fb.c writel(reg, sfb->regs + VIDCON1); reg 674 drivers/video/fbdev/s3c2410fb.c static inline void modify_gpio(void __iomem *reg, reg 679 drivers/video/fbdev/s3c2410fb.c tmp = readl(reg) & ~mask; reg 680 drivers/video/fbdev/s3c2410fb.c writel(tmp | set, reg); reg 210 drivers/video/fbdev/s3fb.c unsigned char reg; reg 212 drivers/video/fbdev/s3fb.c reg = s3fb_ddc_read(par) | DDC_DRIVE_EN; reg 214 drivers/video/fbdev/s3fb.c reg |= DDC_SCL_OUT; reg 216 drivers/video/fbdev/s3fb.c reg &= ~DDC_SCL_OUT; reg 217 drivers/video/fbdev/s3fb.c s3fb_ddc_write(par, reg); reg 223 drivers/video/fbdev/s3fb.c unsigned char reg; reg 225 drivers/video/fbdev/s3fb.c reg = s3fb_ddc_read(par) | DDC_DRIVE_EN; reg 227 drivers/video/fbdev/s3fb.c reg |= DDC_SDA_OUT; reg 229 drivers/video/fbdev/s3fb.c reg &= ~DDC_SDA_OUT; reg 230 drivers/video/fbdev/s3fb.c s3fb_ddc_write(par, reg); reg 50 drivers/video/fbdev/savage/savagefb-i2c.c r = readl(chan->ioaddr + chan->reg); reg 55 drivers/video/fbdev/savage/savagefb-i2c.c writel(r, chan->ioaddr + chan->reg); reg 56 drivers/video/fbdev/savage/savagefb-i2c.c readl(chan->ioaddr + chan->reg); /* flush posted write */ reg 64 drivers/video/fbdev/savage/savagefb-i2c.c r = readl(chan->ioaddr + chan->reg); reg 69 drivers/video/fbdev/savage/savagefb-i2c.c writel(r, chan->ioaddr + chan->reg); reg 70 drivers/video/fbdev/savage/savagefb-i2c.c readl(chan->ioaddr + chan->reg); /* flush posted write */ reg 77 drivers/video/fbdev/savage/savagefb-i2c.c return (0 != (readl(chan->ioaddr + chan->reg) & SAVAGE4_I2C_SCL_IN)); reg 84 drivers/video/fbdev/savage/savagefb-i2c.c return (0 != (readl(chan->ioaddr + chan->reg) & SAVAGE4_I2C_SDA_IN)); reg 92 drivers/video/fbdev/savage/savagefb-i2c.c r = VGArCR(chan->reg, chan->par); reg 100 drivers/video/fbdev/savage/savagefb-i2c.c VGAwCR(chan->reg, r, chan->par); reg 108 drivers/video/fbdev/savage/savagefb-i2c.c r = VGArCR(chan->reg, chan->par); reg 116 drivers/video/fbdev/savage/savagefb-i2c.c VGAwCR(chan->reg, r, chan->par); reg 123 drivers/video/fbdev/savage/savagefb-i2c.c return (VGArCR(chan->reg, chan->par) & PROSAVAGE_I2C_SCL_IN) ? 1 : 0; reg 130 drivers/video/fbdev/savage/savagefb-i2c.c return (VGArCR(chan->reg, chan->par) & PROSAVAGE_I2C_SDA_IN) ? 1 : 0; reg 176 drivers/video/fbdev/savage/savagefb-i2c.c par->chan.reg = CR_SERIAL2; reg 184 drivers/video/fbdev/savage/savagefb-i2c.c par->chan.reg = CR_SERIAL1; reg 186 drivers/video/fbdev/savage/savagefb-i2c.c par->chan.reg = CR_SERIAL2; reg 194 drivers/video/fbdev/savage/savagefb-i2c.c par->chan.reg = MM_SERIAL1; reg 186 drivers/video/fbdev/savage/savagefb.h u32 reg; reg 117 drivers/video/fbdev/savage/savagefb_driver.c static void vgaHWRestore(struct savagefb_par *par, struct savage_reg *reg) reg 121 drivers/video/fbdev/savage/savagefb_driver.c VGAwMISC(reg->MiscOutReg, par); reg 124 drivers/video/fbdev/savage/savagefb_driver.c VGAwSEQ(i, reg->Sequencer[i], par); reg 128 drivers/video/fbdev/savage/savagefb_driver.c VGAwCR(17, reg->CRTC[17] & ~0x80, par); reg 131 drivers/video/fbdev/savage/savagefb_driver.c VGAwCR(i, reg->CRTC[i], par); reg 134 drivers/video/fbdev/savage/savagefb_driver.c VGAwGR(i, reg->Graphics[i], par); reg 139 drivers/video/fbdev/savage/savagefb_driver.c VGAwATTR(i, reg->Attribute[i], par); reg 147 drivers/video/fbdev/savage/savagefb_driver.c struct savage_reg *reg) reg 149 drivers/video/fbdev/savage/savagefb_driver.c reg->MiscOutReg = 0x23; reg 152 drivers/video/fbdev/savage/savagefb_driver.c reg->MiscOutReg |= 0x40; reg 155 drivers/video/fbdev/savage/savagefb_driver.c reg->MiscOutReg |= 0x80; reg 160 drivers/video/fbdev/savage/savagefb_driver.c reg->Sequencer[0x00] = 0x00; reg 161 drivers/video/fbdev/savage/savagefb_driver.c reg->Sequencer[0x01] = 0x01; reg 162 drivers/video/fbdev/savage/savagefb_driver.c reg->Sequencer[0x02] = 0x0F; reg 163 drivers/video/fbdev/savage/savagefb_driver.c reg->Sequencer[0x03] = 0x00; /* Font select */ reg 164 drivers/video/fbdev/savage/savagefb_driver.c reg->Sequencer[0x04] = 0x0E; /* Misc */ reg 169 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x00] = (timings->HTotal >> 3) - 5; reg 170 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1; reg 171 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1; reg 172 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80; reg 173 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x04] = (timings->HSyncStart >> 3); reg 174 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) | reg 176 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF; reg 177 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) | reg 185 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x08] = 0x00; reg 186 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40; reg 189 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x09] |= 0x80; reg 191 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x0a] = 0x00; reg 192 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x0b] = 0x00; reg 193 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x0c] = 0x00; reg 194 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x0d] = 0x00; reg 195 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x0e] = 0x00; reg 196 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x0f] = 0x00; reg 197 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x10] = timings->VSyncStart & 0xff; reg 198 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20; reg 199 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff; reg 200 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x13] = var->xres_virtual >> 4; reg 201 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x14] = 0x00; reg 202 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff; reg 203 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff; reg 204 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x17] = 0xc3; reg 205 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x18] = 0xff; reg 216 drivers/video/fbdev/savage/savagefb_driver.c reg->Graphics[0x00] = 0x00; reg 217 drivers/video/fbdev/savage/savagefb_driver.c reg->Graphics[0x01] = 0x00; reg 218 drivers/video/fbdev/savage/savagefb_driver.c reg->Graphics[0x02] = 0x00; reg 219 drivers/video/fbdev/savage/savagefb_driver.c reg->Graphics[0x03] = 0x00; reg 220 drivers/video/fbdev/savage/savagefb_driver.c reg->Graphics[0x04] = 0x00; reg 221 drivers/video/fbdev/savage/savagefb_driver.c reg->Graphics[0x05] = 0x40; reg 222 drivers/video/fbdev/savage/savagefb_driver.c reg->Graphics[0x06] = 0x05; /* only map 64k VGA memory !!!! */ reg 223 drivers/video/fbdev/savage/savagefb_driver.c reg->Graphics[0x07] = 0x0F; reg 224 drivers/video/fbdev/savage/savagefb_driver.c reg->Graphics[0x08] = 0xFF; reg 227 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x00] = 0x00; /* standard colormap translation */ reg 228 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x01] = 0x01; reg 229 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x02] = 0x02; reg 230 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x03] = 0x03; reg 231 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x04] = 0x04; reg 232 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x05] = 0x05; reg 233 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x06] = 0x06; reg 234 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x07] = 0x07; reg 235 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x08] = 0x08; reg 236 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x09] = 0x09; reg 237 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x0a] = 0x0A; reg 238 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x0b] = 0x0B; reg 239 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x0c] = 0x0C; reg 240 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x0d] = 0x0D; reg 241 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x0e] = 0x0E; reg 242 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x0f] = 0x0F; reg 243 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x10] = 0x41; reg 244 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x11] = 0xFF; reg 245 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x12] = 0x0F; reg 246 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x13] = 0x00; reg 247 drivers/video/fbdev/savage/savagefb_driver.c reg->Attribute[0x14] = 0x00; reg 540 drivers/video/fbdev/savage/savagefb_driver.c static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg) reg 570 drivers/video/fbdev/savage/savagefb_driver.c reg->SR08 = vga_in8(0x3c5, par); reg 575 drivers/video/fbdev/savage/savagefb_driver.c reg->CR31 = vga_in8(0x3d5, par); reg 577 drivers/video/fbdev/savage/savagefb_driver.c reg->CR32 = vga_in8(0x3d5, par); reg 579 drivers/video/fbdev/savage/savagefb_driver.c reg->CR34 = vga_in8(0x3d5, par); reg 581 drivers/video/fbdev/savage/savagefb_driver.c reg->CR36 = vga_in8(0x3d5, par); reg 583 drivers/video/fbdev/savage/savagefb_driver.c reg->CR3A = vga_in8(0x3d5, par); reg 585 drivers/video/fbdev/savage/savagefb_driver.c reg->CR40 = vga_in8(0x3d5, par); reg 587 drivers/video/fbdev/savage/savagefb_driver.c reg->CR42 = vga_in8(0x3d5, par); reg 589 drivers/video/fbdev/savage/savagefb_driver.c reg->CR45 = vga_in8(0x3d5, par); reg 591 drivers/video/fbdev/savage/savagefb_driver.c reg->CR50 = vga_in8(0x3d5, par); reg 593 drivers/video/fbdev/savage/savagefb_driver.c reg->CR51 = vga_in8(0x3d5, par); reg 595 drivers/video/fbdev/savage/savagefb_driver.c reg->CR53 = vga_in8(0x3d5, par); reg 597 drivers/video/fbdev/savage/savagefb_driver.c reg->CR58 = vga_in8(0x3d5, par); reg 599 drivers/video/fbdev/savage/savagefb_driver.c reg->CR60 = vga_in8(0x3d5, par); reg 601 drivers/video/fbdev/savage/savagefb_driver.c reg->CR66 = vga_in8(0x3d5, par); reg 603 drivers/video/fbdev/savage/savagefb_driver.c reg->CR67 = vga_in8(0x3d5, par); reg 605 drivers/video/fbdev/savage/savagefb_driver.c reg->CR68 = vga_in8(0x3d5, par); reg 607 drivers/video/fbdev/savage/savagefb_driver.c reg->CR69 = vga_in8(0x3d5, par); reg 609 drivers/video/fbdev/savage/savagefb_driver.c reg->CR6F = vga_in8(0x3d5, par); reg 612 drivers/video/fbdev/savage/savagefb_driver.c reg->CR33 = vga_in8(0x3d5, par); reg 614 drivers/video/fbdev/savage/savagefb_driver.c reg->CR86 = vga_in8(0x3d5, par); reg 616 drivers/video/fbdev/savage/savagefb_driver.c reg->CR88 = vga_in8(0x3d5, par); reg 618 drivers/video/fbdev/savage/savagefb_driver.c reg->CR90 = vga_in8(0x3d5, par); reg 620 drivers/video/fbdev/savage/savagefb_driver.c reg->CR91 = vga_in8(0x3d5, par); reg 622 drivers/video/fbdev/savage/savagefb_driver.c reg->CRB0 = vga_in8(0x3d5, par) | 0x80; reg 626 drivers/video/fbdev/savage/savagefb_driver.c reg->CR3B = vga_in8(0x3d5, par); reg 628 drivers/video/fbdev/savage/savagefb_driver.c reg->CR3C = vga_in8(0x3d5, par); reg 630 drivers/video/fbdev/savage/savagefb_driver.c reg->CR43 = vga_in8(0x3d5, par); reg 632 drivers/video/fbdev/savage/savagefb_driver.c reg->CR5D = vga_in8(0x3d5, par); reg 634 drivers/video/fbdev/savage/savagefb_driver.c reg->CR5E = vga_in8(0x3d5, par); reg 636 drivers/video/fbdev/savage/savagefb_driver.c reg->CR65 = vga_in8(0x3d5, par); reg 640 drivers/video/fbdev/savage/savagefb_driver.c reg->SR0E = vga_in8(0x3c5, par); reg 642 drivers/video/fbdev/savage/savagefb_driver.c reg->SR0F = vga_in8(0x3c5, par); reg 644 drivers/video/fbdev/savage/savagefb_driver.c reg->SR10 = vga_in8(0x3c5, par); reg 646 drivers/video/fbdev/savage/savagefb_driver.c reg->SR11 = vga_in8(0x3c5, par); reg 648 drivers/video/fbdev/savage/savagefb_driver.c reg->SR12 = vga_in8(0x3c5, par); reg 650 drivers/video/fbdev/savage/savagefb_driver.c reg->SR13 = vga_in8(0x3c5, par); reg 652 drivers/video/fbdev/savage/savagefb_driver.c reg->SR29 = vga_in8(0x3c5, par); reg 655 drivers/video/fbdev/savage/savagefb_driver.c reg->SR15 = vga_in8(0x3c5, par); reg 657 drivers/video/fbdev/savage/savagefb_driver.c reg->SR30 = vga_in8(0x3c5, par); reg 659 drivers/video/fbdev/savage/savagefb_driver.c reg->SR18 = vga_in8(0x3c5, par); reg 667 drivers/video/fbdev/savage/savagefb_driver.c reg->SR54[i] = vga_in8(0x3c5, par); reg 680 drivers/video/fbdev/savage/savagefb_driver.c reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par); reg 681 drivers/video/fbdev/savage/savagefb_driver.c reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par); reg 682 drivers/video/fbdev/savage/savagefb_driver.c reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par); reg 683 drivers/video/fbdev/savage/savagefb_driver.c reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par); reg 693 drivers/video/fbdev/savage/savagefb_driver.c struct savage_reg *reg) reg 723 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR08, par); reg 728 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR31, par); reg 730 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR32, par); reg 732 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR34, par); reg 734 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5,reg->CR36, par); reg 736 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR3A, par); reg 738 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR40, par); reg 740 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR42, par); reg 742 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR45, par); reg 744 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR50, par); reg 746 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR51, par); reg 748 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR53, par); reg 750 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR58, par); reg 752 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR60, par); reg 754 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR66, par); reg 756 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR67, par); reg 758 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR68, par); reg 760 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR69, par); reg 762 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR6F, par); reg 765 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR33, par); reg 767 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR86, par); reg 769 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR88, par); reg 771 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR90, par); reg 773 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR91, par); reg 775 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CRB0, par); reg 779 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR3B, par); reg 781 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR3C, par); reg 783 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR43, par); reg 785 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR5D, par); reg 787 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR5E, par); reg 789 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR65, par); reg 793 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR0E, par); reg 795 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR0F, par); reg 797 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR10, par); reg 799 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR11, par); reg 801 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR12, par); reg 803 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR13, par); reg 805 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR29, par); reg 808 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR15, par); reg 810 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR30, par); reg 812 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR18, par); reg 820 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR54[i], par); reg 833 drivers/video/fbdev/savage/savagefb_driver.c savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par); reg 834 drivers/video/fbdev/savage/savagefb_driver.c savage_out32(MIU_CONTROL_REG, reg->MMPR1, par); reg 835 drivers/video/fbdev/savage/savagefb_driver.c savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par); reg 836 drivers/video/fbdev/savage/savagefb_driver.c savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par); reg 971 drivers/video/fbdev/savage/savagefb_driver.c struct savage_reg *reg) reg 1013 drivers/video/fbdev/savage/savagefb_driver.c vgaHWInit(var, par, &timings, reg); reg 1018 drivers/video/fbdev/savage/savagefb_driver.c reg->CR67 = 0x00; reg 1023 drivers/video/fbdev/savage/savagefb_driver.c reg->CR67 = 0x10; /* 8bpp, 2 pixels/clock */ reg 1025 drivers/video/fbdev/savage/savagefb_driver.c reg->CR67 = 0x00; /* 8bpp, 1 pixel/clock */ reg 1030 drivers/video/fbdev/savage/savagefb_driver.c reg->CR67 = 0x30; /* 15bpp, 2 pixel/clock */ reg 1032 drivers/video/fbdev/savage/savagefb_driver.c reg->CR67 = 0x20; /* 15bpp, 1 pixels/clock */ reg 1037 drivers/video/fbdev/savage/savagefb_driver.c reg->CR67 = 0x50; /* 16bpp, 2 pixel/clock */ reg 1039 drivers/video/fbdev/savage/savagefb_driver.c reg->CR67 = 0x40; /* 16bpp, 1 pixels/clock */ reg 1042 drivers/video/fbdev/savage/savagefb_driver.c reg->CR67 = 0x70; reg 1045 drivers/video/fbdev/savage/savagefb_driver.c reg->CR67 = 0xd0; reg 1057 drivers/video/fbdev/savage/savagefb_driver.c reg->CR3A = (tmp & 0x7f) | 0x15; reg 1059 drivers/video/fbdev/savage/savagefb_driver.c reg->CR3A = tmp | 0x95; reg 1061 drivers/video/fbdev/savage/savagefb_driver.c reg->CR53 = 0x00; reg 1062 drivers/video/fbdev/savage/savagefb_driver.c reg->CR31 = 0x8c; reg 1063 drivers/video/fbdev/savage/savagefb_driver.c reg->CR66 = 0x89; reg 1066 drivers/video/fbdev/savage/savagefb_driver.c reg->CR58 = vga_in8(0x3d5, par) & 0x80; reg 1067 drivers/video/fbdev/savage/savagefb_driver.c reg->CR58 |= 0x13; reg 1069 drivers/video/fbdev/savage/savagefb_driver.c reg->SR15 = 0x03 | 0x80; reg 1070 drivers/video/fbdev/savage/savagefb_driver.c reg->SR18 = 0x00; reg 1071 drivers/video/fbdev/savage/savagefb_driver.c reg->CR43 = reg->CR45 = reg->CR65 = 0x00; reg 1074 drivers/video/fbdev/savage/savagefb_driver.c reg->CR40 = vga_in8(0x3d5, par) & ~0x01; reg 1076 drivers/video/fbdev/savage/savagefb_driver.c reg->MMPR0 = 0x010400; reg 1077 drivers/video/fbdev/savage/savagefb_driver.c reg->MMPR1 = 0x00; reg 1078 drivers/video/fbdev/savage/savagefb_driver.c reg->MMPR2 = 0x0808; reg 1079 drivers/video/fbdev/savage/savagefb_driver.c reg->MMPR3 = 0x08080810; reg 1085 drivers/video/fbdev/savage/savagefb_driver.c reg->SR10 = 255; reg 1086 drivers/video/fbdev/savage/savagefb_driver.c reg->SR11 = 255; reg 1089 drivers/video/fbdev/savage/savagefb_driver.c ®->SR11, ®->SR10); reg 1094 drivers/video/fbdev/savage/savagefb_driver.c reg->SR12 = (r << 6) | (n & 0x3f); reg 1095 drivers/video/fbdev/savage/savagefb_driver.c reg->SR13 = m & 0xff; reg 1096 drivers/video/fbdev/savage/savagefb_driver.c reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2; reg 1099 drivers/video/fbdev/savage/savagefb_driver.c reg->MMPR0 -= 0x8000; reg 1101 drivers/video/fbdev/savage/savagefb_driver.c reg->MMPR0 -= 0x4000; reg 1104 drivers/video/fbdev/savage/savagefb_driver.c reg->CR42 = 0x20; reg 1106 drivers/video/fbdev/savage/savagefb_driver.c reg->CR42 = 0x00; reg 1108 drivers/video/fbdev/savage/savagefb_driver.c reg->CR34 = 0x10; /* display fifo */ reg 1120 drivers/video/fbdev/savage/savagefb_driver.c j = (reg->CRTC[0] + ((i & 0x01) << 8) + reg 1121 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2; reg 1123 drivers/video/fbdev/savage/savagefb_driver.c if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) { reg 1124 drivers/video/fbdev/savage/savagefb_driver.c if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <= reg 1125 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0] + ((i & 0x01) << 8)) reg 1126 drivers/video/fbdev/savage/savagefb_driver.c j = reg->CRTC[4] + ((i & 0x10) << 4) + 4; reg 1128 drivers/video/fbdev/savage/savagefb_driver.c j = reg->CRTC[0] + ((i & 0x01) << 8) + 1; reg 1131 drivers/video/fbdev/savage/savagefb_driver.c reg->CR3B = j & 0xff; reg 1133 drivers/video/fbdev/savage/savagefb_driver.c reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2; reg 1134 drivers/video/fbdev/savage/savagefb_driver.c reg->CR5D = i; reg 1135 drivers/video/fbdev/savage/savagefb_driver.c reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) | reg 1140 drivers/video/fbdev/savage/savagefb_driver.c reg->CR91 = reg->CRTC[19] = 0xff & width; reg 1141 drivers/video/fbdev/savage/savagefb_driver.c reg->CR51 = (0x300 & width) >> 4; reg 1142 drivers/video/fbdev/savage/savagefb_driver.c reg->CR90 = 0x80 | (width >> 8); reg 1143 drivers/video/fbdev/savage/savagefb_driver.c reg->MiscOutReg |= 0x0c; reg 1148 drivers/video/fbdev/savage/savagefb_driver.c reg->CR50 = 0; reg 1150 drivers/video/fbdev/savage/savagefb_driver.c reg->CR50 = 0x10; reg 1152 drivers/video/fbdev/savage/savagefb_driver.c reg->CR50 = 0x30; reg 1155 drivers/video/fbdev/savage/savagefb_driver.c reg->CR50 |= 0x40; reg 1157 drivers/video/fbdev/savage/savagefb_driver.c reg->CR50 |= 0x80; reg 1159 drivers/video/fbdev/savage/savagefb_driver.c reg->CR50 |= 0x00; reg 1161 drivers/video/fbdev/savage/savagefb_driver.c reg->CR50 |= 0x01; reg 1163 drivers/video/fbdev/savage/savagefb_driver.c reg->CR50 |= 0xc0; reg 1165 drivers/video/fbdev/savage/savagefb_driver.c reg->CR50 |= 0x81; reg 1167 drivers/video/fbdev/savage/savagefb_driver.c reg->CR50 |= 0xc1; /* Use GBD */ reg 1170 drivers/video/fbdev/savage/savagefb_driver.c reg->CR33 = 0x08; reg 1172 drivers/video/fbdev/savage/savagefb_driver.c reg->CR33 = 0x20; reg 1174 drivers/video/fbdev/savage/savagefb_driver.c reg->CRTC[0x17] = 0xeb; reg 1176 drivers/video/fbdev/savage/savagefb_driver.c reg->CR67 |= 1; reg 1179 drivers/video/fbdev/savage/savagefb_driver.c reg->CR36 = vga_in8(0x3d5, par); reg 1181 drivers/video/fbdev/savage/savagefb_driver.c reg->CR68 = vga_in8(0x3d5, par); reg 1182 drivers/video/fbdev/savage/savagefb_driver.c reg->CR69 = 0; reg 1184 drivers/video/fbdev/savage/savagefb_driver.c reg->CR6F = vga_in8(0x3d5, par); reg 1186 drivers/video/fbdev/savage/savagefb_driver.c reg->CR86 = vga_in8(0x3d5, par); reg 1188 drivers/video/fbdev/savage/savagefb_driver.c reg->CR88 = vga_in8(0x3d5, par) | 0x08; reg 1190 drivers/video/fbdev/savage/savagefb_driver.c reg->CRB0 = vga_in8(0x3d5, par) | 0x80; reg 1257 drivers/video/fbdev/savage/savagefb_driver.c static void savagefb_set_par_int(struct savagefb_par *par, struct savage_reg *reg) reg 1292 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR66, par); reg 1294 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR3A, par); reg 1296 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR31, par); reg 1298 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR32, par); reg 1300 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR58, par); reg 1302 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR53 & 0x7f, par); reg 1309 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR0E, par); reg 1311 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR0F, par); reg 1313 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR29, par); reg 1315 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR15, par); reg 1323 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR54[i], par); reg 1327 drivers/video/fbdev/savage/savagefb_driver.c vgaHWRestore (par, reg); reg 1331 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR53, par); reg 1333 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR5D, par); reg 1335 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR5E, par); reg 1337 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR3B, par); reg 1339 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR3C, par); reg 1341 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR43, par); reg 1343 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR65, par); reg 1353 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR67 & ~0x0c, par); reg 1357 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR34, par); reg 1359 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR40, par); reg 1361 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR42, par); reg 1363 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR45, par); reg 1365 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR50, par); reg 1367 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR51, par); reg 1371 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR36, par); reg 1373 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR60, par); reg 1375 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR68, par); reg 1377 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR69, par); reg 1379 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR6F, par); reg 1382 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR33, par); reg 1384 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR86, par); reg 1386 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR88, par); reg 1388 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR90, par); reg 1390 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR91, par); reg 1394 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CRB0, par); reg 1398 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR32, par); reg 1407 drivers/video/fbdev/savage/savagefb_driver.c if (reg->SR10 != 255) { reg 1409 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR10, par); reg 1411 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR11, par); reg 1416 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR0E, par); reg 1418 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR0F, par); reg 1420 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR12, par); reg 1422 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR13, par); reg 1424 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR29, par); reg 1426 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR18, par); reg 1435 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR15, par); reg 1439 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR30, par); reg 1441 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3c5, reg->SR08, par); reg 1446 drivers/video/fbdev/savage/savagefb_driver.c vga_out8(0x3d5, reg->CR67, par); reg 1457 drivers/video/fbdev/savage/savagefb_driver.c savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par); reg 1459 drivers/video/fbdev/savage/savagefb_driver.c savage_out32(MIU_CONTROL_REG, reg->MMPR1, par); reg 1461 drivers/video/fbdev/savage/savagefb_driver.c savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par); reg 1463 drivers/video/fbdev/savage/savagefb_driver.c savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par); reg 311 drivers/video/fbdev/sh_mobile_lcdcfb.c int reg, unsigned long data) reg 313 drivers/video/fbdev/sh_mobile_lcdcfb.c iowrite32(data, ovl->channel->lcdc->base + reg); reg 314 drivers/video/fbdev/sh_mobile_lcdcfb.c iowrite32(data, ovl->channel->lcdc->base + reg + SIDE_B_OFFSET); reg 412 drivers/video/fbdev/sis/init301.c static void SiS_SetCH70xx(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val); reg 465 drivers/video/fbdev/sis/init301.c unsigned short romindex = 0, reg = 0, idx = 0; reg 477 drivers/video/fbdev/sis/init301.c if(SiS_Pr->ChipType < SIS_661) reg = 0x3c; reg 478 drivers/video/fbdev/sis/init301.c else reg = 0x7d; reg 480 drivers/video/fbdev/sis/init301.c idx = (SiS_GetReg(SiS_Pr->SiS_P3d4,reg) & 0x1f) * 26; reg 934 drivers/video/fbdev/sis/init301.c SiS_WaitRetrace2(struct SiS_Private *SiS_Pr, unsigned short reg) reg 939 drivers/video/fbdev/sis/init301.c while((SiS_GetReg(SiS_Pr->SiS_Part1Port,reg) & 0x02) && --watchdog); reg 941 drivers/video/fbdev/sis/init301.c while((!(SiS_GetReg(SiS_Pr->SiS_Part1Port,reg) & 0x02)) && --watchdog); reg 9101 drivers/video/fbdev/sis/init301.c SiS_SetChReg(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val, unsigned short myor) reg 9113 drivers/video/fbdev/sis/init301.c temp = SiS_WriteDDC2Data(SiS_Pr, (reg | myor)); /* Write RAB (700x: set bit 7, see datasheet) */ reg 9126 drivers/video/fbdev/sis/init301.c SiS_SetCH700x(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val) reg 9139 drivers/video/fbdev/sis/init301.c if( (!(SiS_SetChReg(SiS_Pr, reg, val, 0x80))) && reg 9146 drivers/video/fbdev/sis/init301.c SiS_SetChReg(SiS_Pr, reg, val, 0x80); reg 9153 drivers/video/fbdev/sis/init301.c SiS_SetCH701x(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val) reg 9160 drivers/video/fbdev/sis/init301.c SiS_SetChReg(SiS_Pr, reg, val, 0); reg 9165 drivers/video/fbdev/sis/init301.c SiS_SetCH70xx(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val) reg 9168 drivers/video/fbdev/sis/init301.c SiS_SetCH700x(SiS_Pr, reg, val); reg 9170 drivers/video/fbdev/sis/init301.c SiS_SetCH701x(SiS_Pr, reg, val); reg 9261 drivers/video/fbdev/sis/init301.c SiS_SetCH70xxANDOR(struct SiS_Private *SiS_Pr, unsigned short reg, reg 9266 drivers/video/fbdev/sis/init301.c tempbl = (SiS_GetCH70xx(SiS_Pr, (reg & 0xFF)) & myand) | myor; reg 9267 drivers/video/fbdev/sis/init301.c SiS_SetCH70xx(SiS_Pr, reg, tempbl); reg 90 drivers/video/fbdev/sis/init301.h void SiS_SetCH700x(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val); reg 92 drivers/video/fbdev/sis/init301.h void SiS_SetCH701x(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val); reg 94 drivers/video/fbdev/sis/init301.h void SiS_SetCH70xxANDOR(struct SiS_Private *SiS_Pr, unsigned short reg, reg 132 drivers/video/fbdev/sis/init301.h extern unsigned int sisfb_read_nbridge_pci_dword(struct SiS_Private *SiS_Pr, int reg); reg 133 drivers/video/fbdev/sis/init301.h extern unsigned int sisfb_read_lpc_pci_dword(struct SiS_Private *SiS_Pr, int reg); reg 380 drivers/video/fbdev/sis/sis.h extern unsigned int sisfb_read_nbridge_pci_dword(struct SiS_Private *SiS_Pr, int reg); reg 381 drivers/video/fbdev/sis/sis.h extern void sisfb_write_nbridge_pci_dword(struct SiS_Private *SiS_Pr, int reg, reg 385 drivers/video/fbdev/sis/sis.h extern void sisfb_write_nbridge_pci_byte(struct SiS_Private *SiS_Pr, int reg, reg 387 drivers/video/fbdev/sis/sis.h extern unsigned int sisfb_read_mio_pci_word(struct SiS_Private *SiS_Pr, int reg); reg 666 drivers/video/fbdev/sis/sis.h unsigned int sisfb_read_nbridge_pci_dword(struct SiS_Private *SiS_Pr, int reg); reg 667 drivers/video/fbdev/sis/sis.h void sisfb_write_nbridge_pci_dword(struct SiS_Private *SiS_Pr, int reg, unsigned int val); reg 668 drivers/video/fbdev/sis/sis.h unsigned int sisfb_read_lpc_pci_dword(struct SiS_Private *SiS_Pr, int reg); reg 671 drivers/video/fbdev/sis/sis.h void sisfb_write_nbridge_pci_byte(struct SiS_Private *SiS_Pr, int reg, unsigned char val); reg 672 drivers/video/fbdev/sis/sis.h unsigned int sisfb_read_mio_pci_word(struct SiS_Private *SiS_Pr, int reg); reg 823 drivers/video/fbdev/sis/sis_main.c unsigned char temp, reg; reg 826 drivers/video/fbdev/sis/sis_main.c case SIS_300_VGA: reg = 0x25; break; reg 827 drivers/video/fbdev/sis/sis_main.c case SIS_315_VGA: reg = 0x30; break; reg 831 drivers/video/fbdev/sis/sis_main.c temp = SiS_GetReg(SISPART1, reg); reg 1027 drivers/video/fbdev/sis/sis_main.c sisfb_read_nbridge_pci_dword(struct SiS_Private *SiS_Pr, int reg) reg 1032 drivers/video/fbdev/sis/sis_main.c pci_read_config_dword(ivideo->nbridge, reg, &val); reg 1037 drivers/video/fbdev/sis/sis_main.c sisfb_write_nbridge_pci_dword(struct SiS_Private *SiS_Pr, int reg, unsigned int val) reg 1041 drivers/video/fbdev/sis/sis_main.c pci_write_config_dword(ivideo->nbridge, reg, (u32)val); reg 1045 drivers/video/fbdev/sis/sis_main.c sisfb_read_lpc_pci_dword(struct SiS_Private *SiS_Pr, int reg) reg 1052 drivers/video/fbdev/sis/sis_main.c pci_read_config_dword(ivideo->lpcdev, reg, &val); reg 1059 drivers/video/fbdev/sis/sis_main.c sisfb_write_nbridge_pci_byte(struct SiS_Private *SiS_Pr, int reg, unsigned char val) reg 1063 drivers/video/fbdev/sis/sis_main.c pci_write_config_byte(ivideo->nbridge, reg, (u8)val); reg 1067 drivers/video/fbdev/sis/sis_main.c sisfb_read_mio_pci_word(struct SiS_Private *SiS_Pr, int reg) reg 1074 drivers/video/fbdev/sis/sis_main.c pci_read_config_word(ivideo->lpcdev, reg, &val); reg 1972 drivers/video/fbdev/sis/sis_main.c u8 reg; reg 1981 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x14); reg 1982 drivers/video/fbdev/sis/sis_main.c ivideo->video_size = ((reg & 0x3F) + 1) << 20; reg 1989 drivers/video/fbdev/sis/sis_main.c pci_read_config_byte(ivideo->nbridge, 0x63, ®); reg 1990 drivers/video/fbdev/sis/sis_main.c ivideo->video_size = 1 << (((reg & 0x70) >> 4) + 21); reg 1997 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x14); reg 1998 drivers/video/fbdev/sis/sis_main.c ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20; reg 1999 drivers/video/fbdev/sis/sis_main.c switch((reg >> 2) & 0x03) { reg 2009 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x14); reg 2010 drivers/video/fbdev/sis/sis_main.c ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20; reg 2011 drivers/video/fbdev/sis/sis_main.c if(reg & 0x0c) ivideo->video_size <<= 1; reg 2016 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x14); reg 2017 drivers/video/fbdev/sis/sis_main.c ivideo->video_size = (((reg & 0x3f) + 1) << 2) << 20; reg 2021 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x79); reg 2022 drivers/video/fbdev/sis/sis_main.c ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20; reg 2027 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x79); reg 2028 drivers/video/fbdev/sis/sis_main.c reg = (reg & 0xf0) >> 4; reg 2029 drivers/video/fbdev/sis/sis_main.c if(reg) { reg 2030 drivers/video/fbdev/sis/sis_main.c ivideo->video_size = (1 << reg) << 20; reg 2033 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x78); reg 2034 drivers/video/fbdev/sis/sis_main.c reg &= 0x30; reg 2035 drivers/video/fbdev/sis/sis_main.c if(reg) { reg 2036 drivers/video/fbdev/sis/sis_main.c if(reg == 0x10) { reg 2047 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x14); reg 2048 drivers/video/fbdev/sis/sis_main.c ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20; reg 2050 drivers/video/fbdev/sis/sis_main.c reg = (reg & 0x0c) >> 2; reg 2052 drivers/video/fbdev/sis/sis_main.c if(reg & 0x01) reg = 0x02; reg 2053 drivers/video/fbdev/sis/sis_main.c else reg = 0x00; reg 2055 drivers/video/fbdev/sis/sis_main.c if(reg == 0x02) ivideo->video_size <<= 1; reg 2056 drivers/video/fbdev/sis/sis_main.c else if(reg == 0x03) ivideo->video_size <<= 2; reg 2290 drivers/video/fbdev/sis/sis_main.c u8 reg, cr37 = 0, paneltype = 0; reg 2302 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x32); reg 2303 drivers/video/fbdev/sis/sis_main.c if(reg & 0x08) reg 2671 drivers/video/fbdev/sis/sis_main.c u8 reg; reg 2680 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISPART4, 0x01); reg 2681 drivers/video/fbdev/sis/sis_main.c if(reg < 0xb0) { reg 2685 drivers/video/fbdev/sis/sis_main.c } else if(reg < 0xc0) { reg 2688 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISPART4, 0x23); reg 2689 drivers/video/fbdev/sis/sis_main.c if(!(reg & 0x02)) { reg 2696 drivers/video/fbdev/sis/sis_main.c } else if(reg < 0xd0) { reg 2700 drivers/video/fbdev/sis/sis_main.c } else if(reg < 0xe0) { reg 2704 drivers/video/fbdev/sis/sis_main.c } else if(reg <= 0xe1) { reg 2705 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISPART4, 0x39); reg 2706 drivers/video/fbdev/sis/sis_main.c if(reg == 0xff) { reg 2730 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x37); reg 2731 drivers/video/fbdev/sis/sis_main.c reg &= SIS_EXTERNAL_CHIP_MASK; reg 2732 drivers/video/fbdev/sis/sis_main.c reg >>= 1; reg 2735 drivers/video/fbdev/sis/sis_main.c switch(reg) { reg 2757 drivers/video/fbdev/sis/sis_main.c switch (reg) { reg 2771 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x38); reg 2772 drivers/video/fbdev/sis/sis_main.c reg >>= 5; reg 2773 drivers/video/fbdev/sis/sis_main.c switch(reg) { reg 2930 drivers/video/fbdev/sis/sis_main.c u8 reg; reg 2933 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x36); reg 2934 drivers/video/fbdev/sis/sis_main.c reg &= 0x0f; reg 2936 drivers/video/fbdev/sis/sis_main.c ivideo->CRT2LCDType = sis300paneltype[reg]; reg 2938 drivers/video/fbdev/sis/sis_main.c ivideo->CRT2LCDType = sis661paneltype[reg]; reg 2940 drivers/video/fbdev/sis/sis_main.c ivideo->CRT2LCDType = sis310paneltype[reg]; reg 2954 drivers/video/fbdev/sis/sis_main.c printk(KERN_DEBUG "sisfb: Invalid panel ID (%02x), assuming 1024x768, RGB18\n", reg); reg 3817 drivers/video/fbdev/sis/sis_main.c u8 reg; reg 3842 drivers/video/fbdev/sis/sis_main.c reg = 0x00; reg 3845 drivers/video/fbdev/sis/sis_main.c reg = 0x80; reg 3847 drivers/video/fbdev/sis/sis_main.c SiS_SetRegANDOR(SISCR, 0x17, 0x7f, reg); reg 3854 drivers/video/fbdev/sis/sis_main.c reg = 0x40; reg 3858 drivers/video/fbdev/sis/sis_main.c reg = 0x00; reg 3861 drivers/video/fbdev/sis/sis_main.c SiS_SetRegANDOR(SISCR, ivideo->SiS_Pr.SiS_MyCR63, ~0x40, reg); reg 4195 drivers/video/fbdev/sis/sis_main.c unsigned char reg; reg 4210 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x05); reg 4211 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x05); reg 4213 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x05); reg 4214 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x05); reg 4224 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x3b); reg 4225 drivers/video/fbdev/sis/sis_main.c if(reg & 0x01) { reg 4351 drivers/video/fbdev/sis/sis_main.c u8 reg, v1, v2, v3, v4, v5, v6, v7, v8; reg 4461 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISPART4, 0x00); reg 4462 drivers/video/fbdev/sis/sis_main.c if((reg == 1) || (reg == 2)) { reg 4475 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISPART4, 0x01); reg 4476 drivers/video/fbdev/sis/sis_main.c if(reg >= 0xb0) { reg 4477 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISPART4, 0x23); reg 4478 drivers/video/fbdev/sis/sis_main.c reg &= 0x20; reg 4479 drivers/video/fbdev/sis/sis_main.c reg <<= 1; reg 4480 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISPART4, 0x23, reg); reg 4489 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x16); reg 4490 drivers/video/fbdev/sis/sis_main.c reg &= 0xc3; reg 4491 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISCR, 0x35, reg); reg 4496 drivers/video/fbdev/sis/sis_main.c reg = ((sisfb_videoram >> 10) - 1) | 0x40; reg 4497 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISSR, 0x14, reg); reg 4520 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x3a); reg 4521 drivers/video/fbdev/sis/sis_main.c if((reg & 0x30) == 0x30) { reg 4572 drivers/video/fbdev/sis/sis_main.c u8 reg; reg 4575 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x05); reg 4576 drivers/video/fbdev/sis/sis_main.c reg++; reg 4635 drivers/video/fbdev/sis/sis_main.c u8 reg, sr14; reg 4687 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x97); reg 4688 drivers/video/fbdev/sis/sis_main.c if(!(reg & 0x01)) { /* Single 32/16 */ reg 4740 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x97); reg 4741 drivers/video/fbdev/sis/sis_main.c if(!(reg & 0x10)) { reg 4742 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x39); reg 4743 drivers/video/fbdev/sis/sis_main.c reg >>= 1; reg 4746 drivers/video/fbdev/sis/sis_main.c if(reg & 0x01) { /* DDRII */ reg 4842 drivers/video/fbdev/sis/sis_main.c reg = (ivideo->chip == XGI_20) ? reg 4844 drivers/video/fbdev/sis/sis_main.c SiS_SetRegANDOR(SISSR, 0x13, 0x80, reg); reg 4850 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x13); reg 4851 drivers/video/fbdev/sis/sis_main.c if(reg & 0x80) ranksize <<= 1; reg 4860 drivers/video/fbdev/sis/sis_main.c reg = 0; reg 4864 drivers/video/fbdev/sis/sis_main.c while((ranksize >>= 1)) reg += 0x10; reg 4867 drivers/video/fbdev/sis/sis_main.c if(!reg) continue; reg 4869 drivers/video/fbdev/sis/sis_main.c SiS_SetRegANDOR(SISSR, 0x14, 0x0f, (reg & 0xf0)); reg 4872 drivers/video/fbdev/sis/sis_main.c if (sisfb_post_xgi_rwtest(ivideo, j, ((reg >> 4) + channelab - 2 + 20), mapsize)) { reg 5032 drivers/video/fbdev/sis/sis_main.c u8 reg; reg 5040 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x86); reg 5042 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x86); reg 5052 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x85); reg 5054 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x85); reg 5069 drivers/video/fbdev/sis/sis_main.c u8 reg; reg 5081 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x48); reg 5083 drivers/video/fbdev/sis/sis_main.c ramtype = reg & 0x01; /* GPIOH */ reg 5086 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x97); reg 5087 drivers/video/fbdev/sis/sis_main.c if (reg & 0x10) { reg 5088 drivers/video/fbdev/sis/sis_main.c ramtype = (reg & 0x01) << 1; reg 5091 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x39); reg 5092 drivers/video/fbdev/sis/sis_main.c ramtype = reg & 0x02; reg 5094 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x3a); reg 5095 drivers/video/fbdev/sis/sis_main.c ramtype = (reg >> 1) & 0x01; reg 5110 drivers/video/fbdev/sis/sis_main.c u8 v1, v2, v3, v4, v5, reg, ramtype; reg 5170 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetRegByte(SISVGAENABLE) | 0x01; reg 5171 drivers/video/fbdev/sis/sis_main.c SiS_SetRegByte(SISVGAENABLE, reg); reg 5174 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetRegByte(SISMISCR) | 0x01; reg 5175 drivers/video/fbdev/sis/sis_main.c SiS_SetRegByte(SISMISCW, reg); reg 5179 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x05); reg 5180 drivers/video/fbdev/sis/sis_main.c if(reg != 0xa1) reg 5240 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0xcb); reg 5241 drivers/video/fbdev/sis/sis_main.c if(reg & 0x20) { reg 5242 drivers/video/fbdev/sis/sis_main.c SiS_SetRegANDOR(SISCR, 0x58, 0xd7, (reg & 0x10) ? 0x08 : 0x20); /* =0x28 Z7 ? */ reg 5246 drivers/video/fbdev/sis/sis_main.c reg = (ivideo->chip == XGI_40) ? 0x20 : 0x00; reg 5247 drivers/video/fbdev/sis/sis_main.c SiS_SetRegANDOR(SISCR, 0x38, 0x1f, reg); reg 5267 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISPART4, 0x00); reg 5268 drivers/video/fbdev/sis/sis_main.c if(reg == 1 || reg == 2) { reg 5275 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISPART4, 0x01); reg 5276 drivers/video/fbdev/sis/sis_main.c if((reg & 0xf0) >= 0xb0) { reg 5277 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISPART4, 0x23); reg 5278 drivers/video/fbdev/sis/sis_main.c if(reg & 0x20) reg |= 0x40; reg 5279 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISPART4, 0x23, reg); reg 5280 drivers/video/fbdev/sis/sis_main.c reg = (reg & 0x20) ? 0x02 : 0x00; reg 5281 drivers/video/fbdev/sis/sis_main.c SiS_SetRegANDOR(SISPART1, 0x1e, 0xfd, reg); reg 5287 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x3b); reg 5288 drivers/video/fbdev/sis/sis_main.c if(reg & 0x02) { reg 5289 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x3a); reg 5290 drivers/video/fbdev/sis/sis_main.c v2 = (reg & 0x30) >> 3; reg 5292 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x39); reg 5293 drivers/video/fbdev/sis/sis_main.c if(reg & 0x80) v2 |= 0x80; reg 5347 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, 0x3b); reg 5349 drivers/video/fbdev/sis/sis_main.c if((!(reg & 0x02)) && (v2 & 0x0e)) reg 5432 drivers/video/fbdev/sis/sis_main.c reg = 0x00; reg 5434 drivers/video/fbdev/sis/sis_main.c reg &= 0xf3; reg 5435 drivers/video/fbdev/sis/sis_main.c if(regd & 0x01) reg |= 0x04; reg 5436 drivers/video/fbdev/sis/sis_main.c if(regd & 0x02) reg |= 0x08; reg 5438 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISCR, rega, reg); reg 5439 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, rega); reg 5440 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, rega); reg 5441 drivers/video/fbdev/sis/sis_main.c reg += 0x10; reg 5454 drivers/video/fbdev/sis/sis_main.c reg = 0x00; reg 5463 drivers/video/fbdev/sis/sis_main.c reg &= 0xfc; reg 5464 drivers/video/fbdev/sis/sis_main.c if(regd & 0x01) reg |= 0x01; reg 5465 drivers/video/fbdev/sis/sis_main.c if(regd & 0x02) reg |= 0x02; reg 5467 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISCR, 0x6f, reg); reg 5468 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x6f); reg 5469 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x6f); reg 5470 drivers/video/fbdev/sis/sis_main.c reg += 0x08; reg 5491 drivers/video/fbdev/sis/sis_main.c reg = 0x80; reg 5493 drivers/video/fbdev/sis/sis_main.c reg &= 0xfc; reg 5494 drivers/video/fbdev/sis/sis_main.c if(regd & 0x01) reg |= 0x01; reg 5495 drivers/video/fbdev/sis/sis_main.c if(regd & 0x02) reg |= 0x02; reg 5497 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISCR, 0x89, reg); reg 5498 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x89); reg 5499 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x89); reg 5500 drivers/video/fbdev/sis/sis_main.c reg += 0x10; reg 5582 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x86); reg 5584 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x86); reg 5588 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x85); reg 5590 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x85); reg 5662 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x86); reg 5666 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x85); reg 5668 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x85); reg 5787 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, i); reg 5788 drivers/video/fbdev/sis/sis_main.c printk(KERN_DEBUG "CR%02x(%x) = 0x%02x\n", i, SISCR, reg); reg 5791 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISSR, i); reg 5792 drivers/video/fbdev/sis/sis_main.c printk(KERN_DEBUG "SR%02x(%x) = 0x%02x\n", i, SISSR, reg); reg 5801 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISPART4, 0x00); reg 5802 drivers/video/fbdev/sis/sis_main.c if((reg == 1) || (reg == 2)) { reg 5828 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0xca); reg 5830 drivers/video/fbdev/sis/sis_main.c if((reg & 0x10) && (!(v1 & 0x04))) { reg 5847 drivers/video/fbdev/sis/sis_main.c u8 reg; reg 6085 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x34); reg 6086 drivers/video/fbdev/sis/sis_main.c if(reg & 0x7f) { reg 6087 drivers/video/fbdev/sis/sis_main.c ivideo->modeprechange = reg & 0x7f; reg 6130 drivers/video/fbdev/sis/sis_main.c reg = SiS_GetReg(SISCR, 0x48); reg 6131 drivers/video/fbdev/sis/sis_main.c if (reg & 0x02) { /* GPIOG */ reg 529 drivers/video/fbdev/sm501fb.c unsigned long reg; reg 538 drivers/video/fbdev/sm501fb.c reg = info->fix.line_length; reg 539 drivers/video/fbdev/sm501fb.c reg |= ((var->xres * var->bits_per_pixel)/8) << 16; reg 541 drivers/video/fbdev/sm501fb.c smc501_writel(reg, fbi->regs + (par->head == HEAD_CRT ? reg 546 drivers/video/fbdev/sm501fb.c reg = (h_total(var) - 1) << 16; reg 547 drivers/video/fbdev/sm501fb.c reg |= (var->xres - 1); reg 549 drivers/video/fbdev/sm501fb.c smc501_writel(reg, base + SM501_OFF_DC_H_TOT); reg 553 drivers/video/fbdev/sm501fb.c reg = var->hsync_len << 16; reg 554 drivers/video/fbdev/sm501fb.c reg |= var->xres + var->right_margin - 1; reg 556 drivers/video/fbdev/sm501fb.c smc501_writel(reg, base + SM501_OFF_DC_H_SYNC); reg 560 drivers/video/fbdev/sm501fb.c reg = (v_total(var) - 1) << 16; reg 561 drivers/video/fbdev/sm501fb.c reg |= (var->yres - 1); reg 563 drivers/video/fbdev/sm501fb.c smc501_writel(reg, base + SM501_OFF_DC_V_TOT); reg 566 drivers/video/fbdev/sm501fb.c reg = var->vsync_len << 16; reg 567 drivers/video/fbdev/sm501fb.c reg |= var->yres + var->lower_margin - 1; reg 569 drivers/video/fbdev/sm501fb.c smc501_writel(reg, base + SM501_OFF_DC_V_SYNC); reg 583 drivers/video/fbdev/sm501fb.c unsigned long reg; reg 588 drivers/video/fbdev/sm501fb.c reg = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL); reg 590 drivers/video/fbdev/sm501fb.c reg &= ~SM501_DC_CRT_CONTROL_PIXEL_MASK; reg 591 drivers/video/fbdev/sm501fb.c reg |= ((xoffs & 15) / bytes_pixel) << 4; reg 592 drivers/video/fbdev/sm501fb.c smc501_writel(reg, fbi->regs + SM501_DC_CRT_CONTROL); reg 594 drivers/video/fbdev/sm501fb.c reg = (par->screen.sm_addr + xoffs + reg 596 drivers/video/fbdev/sm501fb.c smc501_writel(reg | SM501_ADDR_FLIP, fbi->regs + SM501_DC_CRT_FB_ADDR); reg 612 drivers/video/fbdev/sm501fb.c unsigned long reg; reg 614 drivers/video/fbdev/sm501fb.c reg = var->xoffset | (info->var.xres_virtual << 16); reg 615 drivers/video/fbdev/sm501fb.c smc501_writel(reg, fbi->regs + SM501_DC_PANEL_FB_WIDTH); reg 617 drivers/video/fbdev/sm501fb.c reg = var->yoffset | (info->var.yres_virtual << 16); reg 618 drivers/video/fbdev/sm501fb.c smc501_writel(reg, fbi->regs + SM501_DC_PANEL_FB_HEIGHT); reg 805 drivers/video/fbdev/sm501fb.c unsigned long reg; reg 861 drivers/video/fbdev/sm501fb.c reg = var->xres - 1; reg 862 drivers/video/fbdev/sm501fb.c reg |= (var->yres - 1) << 16; reg 864 drivers/video/fbdev/sm501fb.c smc501_writel(reg, fbi->regs + SM501_DC_PANEL_BR_LOC); reg 1227 drivers/video/fbdev/sm501fb.c unsigned int reg; reg 1229 drivers/video/fbdev/sm501fb.c for (reg = start; reg < (len + start); reg += 4) reg 1230 drivers/video/fbdev/sm501fb.c ptr += sprintf(ptr, "%08x = %08x\n", reg, reg 1231 drivers/video/fbdev/sm501fb.c smc501_readl(mem + reg)); reg 27 drivers/video/fbdev/sm712.h #define smtc_mmiowb(dat, reg) writeb(dat, smtc_regbaseaddress + reg) reg 29 drivers/video/fbdev/sm712.h #define smtc_mmiorb(reg) readb(smtc_regbaseaddress + reg) reg 42 drivers/video/fbdev/sm712.h static inline void smtc_crtcw(int reg, int val) reg 44 drivers/video/fbdev/sm712.h smtc_mmiowb(reg, 0x3d4); reg 48 drivers/video/fbdev/sm712.h static inline void smtc_grphw(int reg, int val) reg 50 drivers/video/fbdev/sm712.h smtc_mmiowb(reg, 0x3ce); reg 54 drivers/video/fbdev/sm712.h static inline void smtc_attrw(int reg, int val) reg 57 drivers/video/fbdev/sm712.h smtc_mmiowb(reg, 0x3c0); reg 62 drivers/video/fbdev/sm712.h static inline void smtc_seqw(int reg, int val) reg 64 drivers/video/fbdev/sm712.h smtc_mmiowb(reg, 0x3c4); reg 68 drivers/video/fbdev/sm712.h static inline unsigned int smtc_seqr(int reg) reg 70 drivers/video/fbdev/sm712.h smtc_mmiowb(reg, 0x3c4); reg 128 drivers/video/fbdev/sstfb.c static void sst_dbg_print_read_reg(u32 reg, u32 val) { reg 130 drivers/video/fbdev/sstfb.c switch (reg) { reg 141 drivers/video/fbdev/sstfb.c r_ddprintk("sst_read(%#x): %#x\n", reg, val); reg 146 drivers/video/fbdev/sstfb.c static void sst_dbg_print_write_reg(u32 reg, u32 val) { reg 148 drivers/video/fbdev/sstfb.c switch (reg) { reg 159 drivers/video/fbdev/sstfb.c r_ddprintk("sst_write(%#x, %#x)\n", reg, val); reg 164 drivers/video/fbdev/sstfb.c # define sst_dbg_print_read_reg(reg, val) do {} while(0) reg 165 drivers/video/fbdev/sstfb.c # define sst_dbg_print_write_reg(reg, val) do {} while(0) reg 173 drivers/video/fbdev/sstfb.c #define sst_read(reg) __sst_read(par->mmio_vbase, reg) reg 174 drivers/video/fbdev/sstfb.c #define sst_write(reg,val) __sst_write(par->mmio_vbase, reg, val) reg 175 drivers/video/fbdev/sstfb.c #define sst_set_bits(reg,val) __sst_set_bits(par->mmio_vbase, reg, val) reg 176 drivers/video/fbdev/sstfb.c #define sst_unset_bits(reg,val) __sst_unset_bits(par->mmio_vbase, reg, val) reg 177 drivers/video/fbdev/sstfb.c #define sst_dac_read(reg) __sst_dac_read(par->mmio_vbase, reg) reg 178 drivers/video/fbdev/sstfb.c #define sst_dac_write(reg,val) __sst_dac_write(par->mmio_vbase, reg, val) reg 179 drivers/video/fbdev/sstfb.c #define dac_i_read(reg) __dac_i_read(par->mmio_vbase, reg) reg 180 drivers/video/fbdev/sstfb.c #define dac_i_write(reg,val) __dac_i_write(par->mmio_vbase, reg, val) reg 182 drivers/video/fbdev/sstfb.c static inline u32 __sst_read(u8 __iomem *vbase, u32 reg) reg 184 drivers/video/fbdev/sstfb.c u32 ret = readl(vbase + reg); reg 185 drivers/video/fbdev/sstfb.c sst_dbg_print_read_reg(reg, ret); reg 189 drivers/video/fbdev/sstfb.c static inline void __sst_write(u8 __iomem *vbase, u32 reg, u32 val) reg 191 drivers/video/fbdev/sstfb.c sst_dbg_print_write_reg(reg, val); reg 192 drivers/video/fbdev/sstfb.c writel(val, vbase + reg); reg 195 drivers/video/fbdev/sstfb.c static inline void __sst_set_bits(u8 __iomem *vbase, u32 reg, u32 val) reg 197 drivers/video/fbdev/sstfb.c r_dprintk("sst_set_bits(%#x, %#x)\n", reg, val); reg 198 drivers/video/fbdev/sstfb.c __sst_write(vbase, reg, __sst_read(vbase, reg) | val); reg 201 drivers/video/fbdev/sstfb.c static inline void __sst_unset_bits(u8 __iomem *vbase, u32 reg, u32 val) reg 203 drivers/video/fbdev/sstfb.c r_dprintk("sst_unset_bits(%#x, %#x)\n", reg, val); reg 204 drivers/video/fbdev/sstfb.c __sst_write(vbase, reg, __sst_read(vbase, reg) & ~val); reg 241 drivers/video/fbdev/sstfb.c static u8 __sst_dac_read(u8 __iomem *vbase, u8 reg) reg 245 drivers/video/fbdev/sstfb.c reg &= 0x07; reg 246 drivers/video/fbdev/sstfb.c __sst_write(vbase, DAC_DATA, ((u32)reg << 8) | DAC_READ_CMD ); reg 250 drivers/video/fbdev/sstfb.c r_dprintk("sst_dac_read(%#x): %#x\n", reg, ret); reg 255 drivers/video/fbdev/sstfb.c static void __sst_dac_write(u8 __iomem *vbase, u8 reg, u8 val) reg 257 drivers/video/fbdev/sstfb.c r_dprintk("sst_dac_write(%#x, %#x)\n", reg, val); reg 258 drivers/video/fbdev/sstfb.c reg &= 0x07; reg 259 drivers/video/fbdev/sstfb.c __sst_write(vbase, DAC_DATA,(((u32)reg << 8)) | (u32)val); reg 264 drivers/video/fbdev/sstfb.c static u32 __dac_i_read(u8 __iomem *vbase, u8 reg) reg 268 drivers/video/fbdev/sstfb.c __sst_dac_write(vbase, DACREG_ADDR_I, reg); reg 270 drivers/video/fbdev/sstfb.c r_dprintk("sst_dac_read_i(%#x): %#x\n", reg, ret); reg 273 drivers/video/fbdev/sstfb.c static void __dac_i_write(u8 __iomem *vbase, u8 reg,u8 val) reg 275 drivers/video/fbdev/sstfb.c r_dprintk("sst_dac_write_i(%#x, %#x)\n", reg, val); reg 276 drivers/video/fbdev/sstfb.c __sst_dac_write(vbase, DACREG_ADDR_I, reg); reg 156 drivers/video/fbdev/stifb.c #define READ_BYTE(fb,reg) gsc_readb((fb)->info.fix.mmio_start + (reg)) reg 157 drivers/video/fbdev/stifb.c #define READ_WORD(fb,reg) gsc_readl((fb)->info.fix.mmio_start + (reg)) reg 163 drivers/video/fbdev/stifb.c # define WRITE_BYTE(value,fb,reg) gsc_writeb((value),(fb)->info.fix.mmio_start + (reg)) reg 164 drivers/video/fbdev/stifb.c # define WRITE_WORD(value,fb,reg) gsc_writel((value),(fb)->info.fix.mmio_start + (reg)) reg 169 drivers/video/fbdev/stifb.c # define WRITE_BYTE(value,fb,reg) do { if (debug_on) \ reg 171 drivers/video/fbdev/stifb.c __func__, reg, value, READ_BYTE(fb,reg)); \ reg 172 drivers/video/fbdev/stifb.c gsc_writeb((value),(fb)->info.fix.mmio_start + (reg)); } while (0) reg 173 drivers/video/fbdev/stifb.c # define WRITE_WORD(value,fb,reg) do { if (debug_on) \ reg 175 drivers/video/fbdev/stifb.c __func__, reg, value, READ_WORD(fb,reg)); \ reg 176 drivers/video/fbdev/stifb.c gsc_writel((value),(fb)->info.fix.mmio_start + (reg)); } while (0) reg 159 drivers/video/fbdev/tdfxfb.c static inline u8 vga_inb(struct tdfx_par *par, u32 reg) reg 161 drivers/video/fbdev/tdfxfb.c return inb(par->iobase + reg - 0x300); reg 164 drivers/video/fbdev/tdfxfb.c static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) reg 166 drivers/video/fbdev/tdfxfb.c outb(val, par->iobase + reg - 0x300); reg 243 drivers/video/fbdev/tdfxfb.c static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg) reg 245 drivers/video/fbdev/tdfxfb.c return readl(par->regbase_virt + reg); reg 248 drivers/video/fbdev/tdfxfb.c static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val) reg 250 drivers/video/fbdev/tdfxfb.c writel(val, par->regbase_virt + reg); reg 338 drivers/video/fbdev/tdfxfb.c static void do_write_regs(struct fb_info *info, struct banshee_reg *reg) reg 350 drivers/video/fbdev/tdfxfb.c tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF); reg 351 drivers/video/fbdev/tdfxfb.c tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001); reg 353 drivers/video/fbdev/tdfxfb.c tdfx_outl(par, PLLCTRL1, reg->mempll); reg 354 drivers/video/fbdev/tdfxfb.c tdfx_outl(par, PLLCTRL2, reg->gfxpll); reg 356 drivers/video/fbdev/tdfxfb.c tdfx_outl(par, PLLCTRL0, reg->vidpll); reg 358 drivers/video/fbdev/tdfxfb.c vga_outb(par, MISC_W, reg->misc[0x00] | 0x01); reg 361 drivers/video/fbdev/tdfxfb.c seq_outb(par, i, reg->seq[i]); reg 364 drivers/video/fbdev/tdfxfb.c crt_outb(par, i, reg->crt[i]); reg 367 drivers/video/fbdev/tdfxfb.c gra_outb(par, i, reg->gra[i]); reg 370 drivers/video/fbdev/tdfxfb.c att_outb(par, i, reg->att[i]); reg 372 drivers/video/fbdev/tdfxfb.c crt_outb(par, 0x1a, reg->ext[0]); reg 373 drivers/video/fbdev/tdfxfb.c crt_outb(par, 0x1b, reg->ext[1]); reg 379 drivers/video/fbdev/tdfxfb.c tdfx_outl(par, VGAINIT0, reg->vgainit0); reg 380 drivers/video/fbdev/tdfxfb.c tdfx_outl(par, DACMODE, reg->dacmode); reg 381 drivers/video/fbdev/tdfxfb.c tdfx_outl(par, VIDDESKSTRIDE, reg->stride); reg 382 drivers/video/fbdev/tdfxfb.c tdfx_outl(par, HWCURPATADDR, reg->curspataddr); reg 384 drivers/video/fbdev/tdfxfb.c tdfx_outl(par, VIDSCREENSIZE, reg->screensize); reg 385 drivers/video/fbdev/tdfxfb.c tdfx_outl(par, VIDDESKSTART, reg->startaddr); reg 386 drivers/video/fbdev/tdfxfb.c tdfx_outl(par, VIDPROCCFG, reg->vidcfg); reg 387 drivers/video/fbdev/tdfxfb.c tdfx_outl(par, VGAINIT1, reg->vgainit1); reg 388 drivers/video/fbdev/tdfxfb.c tdfx_outl(par, MISCINIT0, reg->miscinit0); reg 391 drivers/video/fbdev/tdfxfb.c tdfx_outl(par, SRCBASE, reg->startaddr); reg 392 drivers/video/fbdev/tdfxfb.c tdfx_outl(par, DSTBASE, reg->startaddr); reg 553 drivers/video/fbdev/tdfxfb.c struct banshee_reg reg; reg 558 drivers/video/fbdev/tdfxfb.c memset(®, 0, sizeof(reg)); reg 560 drivers/video/fbdev/tdfxfb.c reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE | reg 568 drivers/video/fbdev/tdfxfb.c reg.vidcfg &= ~VIDCFG_2X; reg 572 drivers/video/fbdev/tdfxfb.c reg.dacmode |= DACMODE_2X; reg 573 drivers/video/fbdev/tdfxfb.c reg.vidcfg |= VIDCFG_2X; reg 593 drivers/video/fbdev/tdfxfb.c reg.screensize = info->var.xres | (info->var.yres << 13); reg 594 drivers/video/fbdev/tdfxfb.c reg.vidcfg |= VIDCFG_HALF_MODE; reg 595 drivers/video/fbdev/tdfxfb.c reg.crt[0x09] = 0x80; reg 601 drivers/video/fbdev/tdfxfb.c reg.screensize = info->var.xres | (info->var.yres << 12); reg 602 drivers/video/fbdev/tdfxfb.c reg.vidcfg &= ~VIDCFG_HALF_MODE; reg 608 drivers/video/fbdev/tdfxfb.c reg.misc[0x00] = 0x0f | reg 613 drivers/video/fbdev/tdfxfb.c reg.gra[0x05] = 0x40; reg 614 drivers/video/fbdev/tdfxfb.c reg.gra[0x06] = 0x05; reg 615 drivers/video/fbdev/tdfxfb.c reg.gra[0x07] = 0x0f; reg 616 drivers/video/fbdev/tdfxfb.c reg.gra[0x08] = 0xff; reg 618 drivers/video/fbdev/tdfxfb.c reg.att[0x00] = 0x00; reg 619 drivers/video/fbdev/tdfxfb.c reg.att[0x01] = 0x01; reg 620 drivers/video/fbdev/tdfxfb.c reg.att[0x02] = 0x02; reg 621 drivers/video/fbdev/tdfxfb.c reg.att[0x03] = 0x03; reg 622 drivers/video/fbdev/tdfxfb.c reg.att[0x04] = 0x04; reg 623 drivers/video/fbdev/tdfxfb.c reg.att[0x05] = 0x05; reg 624 drivers/video/fbdev/tdfxfb.c reg.att[0x06] = 0x06; reg 625 drivers/video/fbdev/tdfxfb.c reg.att[0x07] = 0x07; reg 626 drivers/video/fbdev/tdfxfb.c reg.att[0x08] = 0x08; reg 627 drivers/video/fbdev/tdfxfb.c reg.att[0x09] = 0x09; reg 628 drivers/video/fbdev/tdfxfb.c reg.att[0x0a] = 0x0a; reg 629 drivers/video/fbdev/tdfxfb.c reg.att[0x0b] = 0x0b; reg 630 drivers/video/fbdev/tdfxfb.c reg.att[0x0c] = 0x0c; reg 631 drivers/video/fbdev/tdfxfb.c reg.att[0x0d] = 0x0d; reg 632 drivers/video/fbdev/tdfxfb.c reg.att[0x0e] = 0x0e; reg 633 drivers/video/fbdev/tdfxfb.c reg.att[0x0f] = 0x0f; reg 634 drivers/video/fbdev/tdfxfb.c reg.att[0x10] = 0x41; reg 635 drivers/video/fbdev/tdfxfb.c reg.att[0x12] = 0x0f; reg 637 drivers/video/fbdev/tdfxfb.c reg.seq[0x00] = 0x03; reg 638 drivers/video/fbdev/tdfxfb.c reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */ reg 639 drivers/video/fbdev/tdfxfb.c reg.seq[0x02] = 0x0f; reg 640 drivers/video/fbdev/tdfxfb.c reg.seq[0x03] = 0x00; reg 641 drivers/video/fbdev/tdfxfb.c reg.seq[0x04] = 0x0e; reg 643 drivers/video/fbdev/tdfxfb.c reg.crt[0x00] = ht - 4; reg 644 drivers/video/fbdev/tdfxfb.c reg.crt[0x01] = hd; reg 645 drivers/video/fbdev/tdfxfb.c reg.crt[0x02] = hbs; reg 646 drivers/video/fbdev/tdfxfb.c reg.crt[0x03] = 0x80 | (hbe & 0x1f); reg 647 drivers/video/fbdev/tdfxfb.c reg.crt[0x04] = hs; reg 648 drivers/video/fbdev/tdfxfb.c reg.crt[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f); reg 649 drivers/video/fbdev/tdfxfb.c reg.crt[0x06] = vt; reg 650 drivers/video/fbdev/tdfxfb.c reg.crt[0x07] = ((vs & 0x200) >> 2) | reg 657 drivers/video/fbdev/tdfxfb.c reg.crt[0x09] |= 0x40 | ((vbs & 0x200) >> 4); reg 658 drivers/video/fbdev/tdfxfb.c reg.crt[0x10] = vs; reg 659 drivers/video/fbdev/tdfxfb.c reg.crt[0x11] = (ve & 0x0f) | 0x20; reg 660 drivers/video/fbdev/tdfxfb.c reg.crt[0x12] = vd; reg 661 drivers/video/fbdev/tdfxfb.c reg.crt[0x13] = wd; reg 662 drivers/video/fbdev/tdfxfb.c reg.crt[0x15] = vbs; reg 663 drivers/video/fbdev/tdfxfb.c reg.crt[0x16] = vbe + 1; reg 664 drivers/video/fbdev/tdfxfb.c reg.crt[0x17] = 0xc3; reg 665 drivers/video/fbdev/tdfxfb.c reg.crt[0x18] = 0xff; reg 668 drivers/video/fbdev/tdfxfb.c reg.ext[0x00] = (((ht & 0x100) >> 8) | reg 674 drivers/video/fbdev/tdfxfb.c reg.ext[0x01] = (((vt & 0x400) >> 10) | reg 679 drivers/video/fbdev/tdfxfb.c reg.vgainit0 = VGAINIT0_8BIT_DAC | reg 684 drivers/video/fbdev/tdfxfb.c reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff; reg 687 drivers/video/fbdev/tdfxfb.c reg.curspataddr = info->fix.smem_len; reg 689 drivers/video/fbdev/tdfxfb.c reg.cursloc = 0; reg 691 drivers/video/fbdev/tdfxfb.c reg.cursc0 = 0; reg 692 drivers/video/fbdev/tdfxfb.c reg.cursc1 = 0xffffff; reg 694 drivers/video/fbdev/tdfxfb.c reg.stride = info->var.xres * cpp; reg 695 drivers/video/fbdev/tdfxfb.c reg.startaddr = info->var.yoffset * reg.stride reg 698 drivers/video/fbdev/tdfxfb.c reg.vidpll = do_calc_pll(freq, &fout); reg 700 drivers/video/fbdev/tdfxfb.c reg.mempll = do_calc_pll(..., &fout); reg 701 drivers/video/fbdev/tdfxfb.c reg.gfxpll = do_calc_pll(..., &fout); reg 705 drivers/video/fbdev/tdfxfb.c reg.vidcfg |= VIDCFG_INTERLACE; reg 706 drivers/video/fbdev/tdfxfb.c reg.miscinit0 = tdfx_inl(par, MISCINIT0); reg 712 drivers/video/fbdev/tdfxfb.c reg.miscinit0 &= ~(1 << 30); reg 713 drivers/video/fbdev/tdfxfb.c reg.miscinit0 &= ~(1 << 31); reg 716 drivers/video/fbdev/tdfxfb.c reg.miscinit0 |= (1 << 30); reg 717 drivers/video/fbdev/tdfxfb.c reg.miscinit0 |= (1 << 31); reg 720 drivers/video/fbdev/tdfxfb.c reg.miscinit0 |= (1 << 30); reg 721 drivers/video/fbdev/tdfxfb.c reg.miscinit0 &= ~(1 << 31); reg 725 drivers/video/fbdev/tdfxfb.c do_write_regs(info, ®); reg 728 drivers/video/fbdev/tdfxfb.c info->fix.line_length = reg.stride; reg 164 drivers/video/fbdev/tridentfb.c static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg) reg 166 drivers/video/fbdev/tridentfb.c fb_writeb(val, p->io_virt + reg); reg 169 drivers/video/fbdev/tridentfb.c static inline u8 t_inb(struct tridentfb_par *p, u16 reg) reg 171 drivers/video/fbdev/tridentfb.c return fb_readb(p->io_virt + reg); reg 193 drivers/video/fbdev/tridentfb.c u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI; reg 196 drivers/video/fbdev/tridentfb.c reg &= ~DDC_SCL_DRIVE_TGUI; /* disable drive - don't drive hi */ reg 198 drivers/video/fbdev/tridentfb.c reg |= DDC_SCL_DRIVE_TGUI; /* drive low */ reg 200 drivers/video/fbdev/tridentfb.c vga_mm_wcrt(par->io_virt, I2C, reg); reg 206 drivers/video/fbdev/tridentfb.c u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI; reg 209 drivers/video/fbdev/tridentfb.c reg &= ~DDC_SDA_DRIVE_TGUI; /* disable drive - don't drive hi */ reg 211 drivers/video/fbdev/tridentfb.c reg |= DDC_SDA_DRIVE_TGUI; /* drive low */ reg 213 drivers/video/fbdev/tridentfb.c vga_mm_wcrt(par->io_virt, I2C, reg); reg 232 drivers/video/fbdev/tridentfb.c unsigned char reg; reg 234 drivers/video/fbdev/tridentfb.c reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK; reg 236 drivers/video/fbdev/tridentfb.c reg |= DDC_SCL_OUT; reg 238 drivers/video/fbdev/tridentfb.c reg &= ~DDC_SCL_OUT; reg 239 drivers/video/fbdev/tridentfb.c vga_mm_wcrt(par->io_virt, I2C, reg); reg 245 drivers/video/fbdev/tridentfb.c unsigned char reg; reg 247 drivers/video/fbdev/tridentfb.c reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK; reg 249 drivers/video/fbdev/tridentfb.c reg |= DDC_SDA_OUT; reg 251 drivers/video/fbdev/tridentfb.c reg &= ~DDC_SDA_OUT; reg 252 drivers/video/fbdev/tridentfb.c vga_mm_wcrt(par->io_virt, I2C, reg); reg 695 drivers/video/fbdev/tridentfb.c static inline unsigned char read3X4(struct tridentfb_par *par, int reg) reg 697 drivers/video/fbdev/tridentfb.c return vga_mm_rcrt(par->io_virt, reg); reg 700 drivers/video/fbdev/tridentfb.c static inline void write3X4(struct tridentfb_par *par, int reg, reg 703 drivers/video/fbdev/tridentfb.c vga_mm_wcrt(par->io_virt, reg, val); reg 707 drivers/video/fbdev/tridentfb.c unsigned char reg) reg 709 drivers/video/fbdev/tridentfb.c return vga_mm_rgfx(par->io_virt, reg); reg 712 drivers/video/fbdev/tridentfb.c static inline void writeAttr(struct tridentfb_par *par, int reg, reg 716 drivers/video/fbdev/tridentfb.c vga_mm_wattr(par->io_virt, reg, val); reg 719 drivers/video/fbdev/tridentfb.c static inline void write3CE(struct tridentfb_par *par, int reg, reg 722 drivers/video/fbdev/tridentfb.c vga_mm_wgfx(par->io_virt, reg, val); reg 90 drivers/video/fbdev/udlfb.c static char *dlfb_set_register(char *buf, u8 reg, u8 val) reg 94 drivers/video/fbdev/udlfb.c *buf++ = reg; reg 121 drivers/video/fbdev/udlfb.c u8 reg; reg 125 drivers/video/fbdev/udlfb.c reg = 0x07; reg 128 drivers/video/fbdev/udlfb.c reg = 0x05; reg 131 drivers/video/fbdev/udlfb.c reg = 0x03; reg 134 drivers/video/fbdev/udlfb.c reg = 0x01; reg 137 drivers/video/fbdev/udlfb.c reg = 0x00; reg 140 drivers/video/fbdev/udlfb.c buf = dlfb_set_register(buf, 0x1F, reg); reg 169 drivers/video/fbdev/udlfb.c static char *dlfb_set_register_16(char *wrptr, u8 reg, u16 value) reg 171 drivers/video/fbdev/udlfb.c wrptr = dlfb_set_register(wrptr, reg, value >> 8); reg 172 drivers/video/fbdev/udlfb.c return dlfb_set_register(wrptr, reg+1, value); reg 179 drivers/video/fbdev/udlfb.c static char *dlfb_set_register_16be(char *wrptr, u8 reg, u16 value) reg 181 drivers/video/fbdev/udlfb.c wrptr = dlfb_set_register(wrptr, reg, value); reg 182 drivers/video/fbdev/udlfb.c return dlfb_set_register(wrptr, reg+1, value >> 8); reg 211 drivers/video/fbdev/udlfb.c static char *dlfb_set_register_lfsr16(char *wrptr, u8 reg, u16 value) reg 213 drivers/video/fbdev/udlfb.c return dlfb_set_register_16(wrptr, reg, dlfb_lfsr16(value)); reg 965 drivers/video/fbdev/via/hw.c struct io_register *reg, reg 979 drivers/video/fbdev/via/hw.c start_index = reg[i].start_bit; reg 980 drivers/video/fbdev/via/hw.c end_index = reg[i].end_bit; reg 981 drivers/video/fbdev/via/hw.c cr_index = reg[i].io_addr; reg 1016 drivers/video/fbdev/via/hw.c struct io_register *reg = NULL; reg 1023 drivers/video/fbdev/via/hw.c reg = fetch_count_reg.iga1_fetch_count_reg.reg; reg 1024 drivers/video/fbdev/via/hw.c viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); reg 1030 drivers/video/fbdev/via/hw.c reg = fetch_count_reg.iga2_fetch_count_reg.reg; reg 1031 drivers/video/fbdev/via/hw.c viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); reg 1041 drivers/video/fbdev/via/hw.c struct io_register *reg = NULL; reg 1162 drivers/video/fbdev/via/hw.c reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg; reg 1163 drivers/video/fbdev/via/hw.c viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); reg 1170 drivers/video/fbdev/via/hw.c reg = reg 1172 drivers/video/fbdev/via/hw.c iga1_fifo_threshold_select_reg.reg; reg 1173 drivers/video/fbdev/via/hw.c viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); reg 1181 drivers/video/fbdev/via/hw.c reg = reg 1183 drivers/video/fbdev/via/hw.c iga1_fifo_high_threshold_select_reg.reg; reg 1184 drivers/video/fbdev/via/hw.c viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); reg 1193 drivers/video/fbdev/via/hw.c reg = reg 1195 drivers/video/fbdev/via/hw.c iga1_display_queue_expire_num_reg.reg; reg 1196 drivers/video/fbdev/via/hw.c viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); reg 1316 drivers/video/fbdev/via/hw.c reg = reg 1318 drivers/video/fbdev/via/hw.c iga2_fifo_depth_select_reg.reg; reg 1320 drivers/video/fbdev/via/hw.c viafb_load_reg_num, reg, VIACR); reg 1329 drivers/video/fbdev/via/hw.c reg = reg 1331 drivers/video/fbdev/via/hw.c iga2_fifo_depth_select_reg.reg; reg 1333 drivers/video/fbdev/via/hw.c viafb_load_reg_num, reg, VIACR); reg 1341 drivers/video/fbdev/via/hw.c reg = reg 1343 drivers/video/fbdev/via/hw.c iga2_fifo_threshold_select_reg.reg; reg 1344 drivers/video/fbdev/via/hw.c viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); reg 1352 drivers/video/fbdev/via/hw.c reg = reg 1354 drivers/video/fbdev/via/hw.c iga2_fifo_high_threshold_select_reg.reg; reg 1355 drivers/video/fbdev/via/hw.c viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); reg 1364 drivers/video/fbdev/via/hw.c reg = reg 1366 drivers/video/fbdev/via/hw.c iga2_display_queue_expire_num_reg.reg; reg 1367 drivers/video/fbdev/via/hw.c viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); reg 356 drivers/video/fbdev/via/hw.h struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM]; reg 362 drivers/video/fbdev/via/hw.h struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM]; reg 368 drivers/video/fbdev/via/hw.h struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM]; reg 374 drivers/video/fbdev/via/hw.h struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM]; reg 380 drivers/video/fbdev/via/hw.h struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM]; reg 386 drivers/video/fbdev/via/hw.h struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM]; reg 392 drivers/video/fbdev/via/hw.h struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM]; reg 398 drivers/video/fbdev/via/hw.h struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM]; reg 404 drivers/video/fbdev/via/hw.h struct io_register reg[IGA1_FETCH_COUNT_REG_NUM]; reg 410 drivers/video/fbdev/via/hw.h struct io_register reg[IGA2_FETCH_COUNT_REG_NUM]; reg 421 drivers/video/fbdev/via/hw.h struct io_register reg[IGA1_STARTING_ADDR_REG_NUM]; reg 426 drivers/video/fbdev/via/hw.h struct io_register reg[IGA2_STARTING_ADDR_REG_NUM]; reg 437 drivers/video/fbdev/via/hw.h struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM]; reg 442 drivers/video/fbdev/via/hw.h struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM]; reg 447 drivers/video/fbdev/via/hw.h struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM]; reg 452 drivers/video/fbdev/via/hw.h struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM]; reg 465 drivers/video/fbdev/via/hw.h struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM]; reg 470 drivers/video/fbdev/via/hw.h struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM]; reg 501 drivers/video/fbdev/via/hw.h struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM]; reg 506 drivers/video/fbdev/via/hw.h struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM]; reg 511 drivers/video/fbdev/via/hw.h struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM]; reg 516 drivers/video/fbdev/via/hw.h struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM]; reg 521 drivers/video/fbdev/via/hw.h struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM]; reg 526 drivers/video/fbdev/via/hw.h struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM]; reg 531 drivers/video/fbdev/via/hw.h struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM]; reg 536 drivers/video/fbdev/via/hw.h struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM]; reg 632 drivers/video/fbdev/via/hw.h struct io_register *reg, reg 340 drivers/video/fbdev/via/lcd.c struct io_register *reg = NULL; reg 358 drivers/video/fbdev/via/lcd.c reg = lcd_scaling_factor_CLE.lcd_hor_scaling_factor.reg; reg 360 drivers/video/fbdev/via/lcd.c viafb_load_reg_num, reg, VIACR); reg 379 drivers/video/fbdev/via/lcd.c reg = lcd_scaling_factor.lcd_hor_scaling_factor.reg; reg 381 drivers/video/fbdev/via/lcd.c viafb_load_reg_num, reg, VIACR); reg 402 drivers/video/fbdev/via/lcd.c reg = lcd_scaling_factor_CLE.lcd_ver_scaling_factor.reg; reg 404 drivers/video/fbdev/via/lcd.c viafb_load_reg_num, reg, VIACR); reg 423 drivers/video/fbdev/via/lcd.c reg = lcd_scaling_factor.lcd_ver_scaling_factor.reg; reg 425 drivers/video/fbdev/via/lcd.c viafb_load_reg_num, reg, VIACR); reg 57 drivers/video/fbdev/via/via-core.c static inline void viafb_mmio_write(int reg, u32 v) reg 59 drivers/video/fbdev/via/via-core.c iowrite32(v, global_dev.engine_mmio + reg); reg 62 drivers/video/fbdev/via/via-core.c static inline int viafb_mmio_read(int reg) reg 64 drivers/video/fbdev/via/via-core.c return ioread32(global_dev.engine_mmio + reg); reg 87 drivers/video/fbdev/via/via-gpio.c u8 reg; reg 93 drivers/video/fbdev/via/via-gpio.c reg = via_read_reg(VIASR, gpio->vg_port_index); reg 94 drivers/video/fbdev/via/via-gpio.c reg |= 0x40 << gpio->vg_mask_shift; /* output enable */ reg 96 drivers/video/fbdev/via/via-gpio.c reg |= 0x10 << gpio->vg_mask_shift; reg 98 drivers/video/fbdev/via/via-gpio.c reg &= ~(0x10 << gpio->vg_mask_shift); reg 99 drivers/video/fbdev/via/via-gpio.c via_write_reg(VIASR, gpio->vg_port_index, reg); reg 131 drivers/video/fbdev/via/via-gpio.c u8 reg; reg 137 drivers/video/fbdev/via/via-gpio.c reg = via_read_reg(VIASR, gpio->vg_port_index); reg 139 drivers/video/fbdev/via/via-gpio.c return !!(reg & (0x04 << gpio->vg_mask_shift)); reg 35 drivers/video/vgastate.c unsigned char reg) reg 37 drivers/video/vgastate.c vga_w(regbase, iobase + 0x4, reg); reg 42 drivers/video/vgastate.c unsigned char reg, unsigned char val) reg 44 drivers/video/vgastate.c vga_w(regbase, iobase + 0x4, reg); reg 116 drivers/w1/masters/ds1wm.c static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg, reg 122 drivers/w1/masters/ds1wm.c iowrite8(val, ds1wm_data->map + (reg << 0)); reg 125 drivers/w1/masters/ds1wm.c iowrite16be((u16)val, ds1wm_data->map + (reg << 1)); reg 128 drivers/w1/masters/ds1wm.c iowrite32be((u32)val, ds1wm_data->map + (reg << 2)); reg 134 drivers/w1/masters/ds1wm.c iowrite8(val, ds1wm_data->map + (reg << 0)); reg 137 drivers/w1/masters/ds1wm.c iowrite16((u16)val, ds1wm_data->map + (reg << 1)); reg 140 drivers/w1/masters/ds1wm.c iowrite32((u32)val, ds1wm_data->map + (reg << 2)); reg 146 drivers/w1/masters/ds1wm.c static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg) reg 153 drivers/w1/masters/ds1wm.c val = ioread8(ds1wm_data->map + (reg << 0)); reg 156 drivers/w1/masters/ds1wm.c val = ioread16be(ds1wm_data->map + (reg << 1)); reg 159 drivers/w1/masters/ds1wm.c val = ioread32be(ds1wm_data->map + (reg << 2)); reg 165 drivers/w1/masters/ds1wm.c val = ioread8(ds1wm_data->map + (reg << 0)); reg 168 drivers/w1/masters/ds1wm.c val = ioread16(ds1wm_data->map + (reg << 1)); reg 171 drivers/w1/masters/ds1wm.c val = ioread32(ds1wm_data->map + (reg << 2)); reg 176 drivers/w1/masters/ds1wm.c "ds1wm_read_register reg: %d, 32 bit val:%x\n", reg, val); reg 67 drivers/w1/masters/matrox_w1.c static __inline__ u8 matrox_w1_read_reg(struct matrox_device *dev, u8 reg) reg 71 drivers/w1/masters/matrox_w1.c writeb(reg, dev->port_index); reg 78 drivers/w1/masters/matrox_w1.c static __inline__ void matrox_w1_write_reg(struct matrox_device *dev, u8 reg, u8 val) reg 80 drivers/w1/masters/matrox_w1.c writeb(reg, dev->port_index); reg 79 drivers/watchdog/armada_37xx_wdt.c void __iomem *reg; reg 93 drivers/watchdog/armada_37xx_wdt.c val = readl(dev->reg + CNTR_COUNT_LOW(id)); reg 94 drivers/watchdog/armada_37xx_wdt.c val |= ((u64)readl(dev->reg + CNTR_COUNT_HIGH(id))) << 32; reg 101 drivers/watchdog/armada_37xx_wdt.c writel(val & 0xffffffff, dev->reg + CNTR_COUNT_LOW(id)); reg 102 drivers/watchdog/armada_37xx_wdt.c writel(val >> 32, dev->reg + CNTR_COUNT_HIGH(id)); reg 107 drivers/watchdog/armada_37xx_wdt.c u32 reg; reg 109 drivers/watchdog/armada_37xx_wdt.c reg = readl(dev->reg + CNTR_CTRL(id)); reg 110 drivers/watchdog/armada_37xx_wdt.c reg |= CNTR_CTRL_ENABLE; reg 111 drivers/watchdog/armada_37xx_wdt.c writel(reg, dev->reg + CNTR_CTRL(id)); reg 116 drivers/watchdog/armada_37xx_wdt.c u32 reg; reg 118 drivers/watchdog/armada_37xx_wdt.c reg = readl(dev->reg + CNTR_CTRL(id)); reg 119 drivers/watchdog/armada_37xx_wdt.c reg &= ~CNTR_CTRL_ENABLE; reg 120 drivers/watchdog/armada_37xx_wdt.c writel(reg, dev->reg + CNTR_CTRL(id)); reg 126 drivers/watchdog/armada_37xx_wdt.c u32 reg; reg 128 drivers/watchdog/armada_37xx_wdt.c reg = readl(dev->reg + CNTR_CTRL(id)); reg 130 drivers/watchdog/armada_37xx_wdt.c reg &= ~(CNTR_CTRL_MODE_MASK | CNTR_CTRL_PRESCALE_MASK | reg 134 drivers/watchdog/armada_37xx_wdt.c reg |= mode & CNTR_CTRL_MODE_MASK; reg 137 drivers/watchdog/armada_37xx_wdt.c reg |= CNTR_CTRL_PRESCALE_MIN << CNTR_CTRL_PRESCALE_SHIFT; reg 140 drivers/watchdog/armada_37xx_wdt.c reg |= trig_src & CNTR_CTRL_TRIG_SRC_MASK; reg 142 drivers/watchdog/armada_37xx_wdt.c writel(reg, dev->reg + CNTR_CTRL(id)); reg 187 drivers/watchdog/armada_37xx_wdt.c u32 reg; reg 189 drivers/watchdog/armada_37xx_wdt.c regmap_read(dev->cpu_misc, WDT_TIMER_SELECT, ®); reg 190 drivers/watchdog/armada_37xx_wdt.c if ((reg & WDT_TIMER_SELECT_MASK) != WDT_TIMER_SELECT_VAL) reg 193 drivers/watchdog/armada_37xx_wdt.c reg = readl(dev->reg + CNTR_CTRL(CNTR_ID_WDOG)); reg 194 drivers/watchdog/armada_37xx_wdt.c return !!(reg & CNTR_CTRL_ACTIVE); reg 276 drivers/watchdog/armada_37xx_wdt.c dev->reg = devm_ioremap(&pdev->dev, res->start, resource_size(res)); reg 325 drivers/watchdog/aspeed_wdt.c u32 reg = readl(wdt->base + WDT_RESET_WIDTH); reg 327 drivers/watchdog/aspeed_wdt.c reg &= config->ext_pulse_width_mask; reg 329 drivers/watchdog/aspeed_wdt.c reg |= WDT_PUSH_PULL_MAGIC; reg 331 drivers/watchdog/aspeed_wdt.c reg |= WDT_OPEN_DRAIN_MAGIC; reg 333 drivers/watchdog/aspeed_wdt.c writel(reg, wdt->base + WDT_RESET_WIDTH); reg 335 drivers/watchdog/aspeed_wdt.c reg &= config->ext_pulse_width_mask; reg 337 drivers/watchdog/aspeed_wdt.c reg |= WDT_ACTIVE_HIGH_MAGIC; reg 339 drivers/watchdog/aspeed_wdt.c reg |= WDT_ACTIVE_LOW_MAGIC; reg 341 drivers/watchdog/aspeed_wdt.c writel(reg, wdt->base + WDT_RESET_WIDTH); reg 71 drivers/watchdog/ath79_wdt.c static inline void ath79_wdt_wr(unsigned reg, u32 val) reg 73 drivers/watchdog/ath79_wdt.c iowrite32(val, wdt_base + reg); reg 76 drivers/watchdog/ath79_wdt.c static inline u32 ath79_wdt_rr(unsigned reg) reg 78 drivers/watchdog/ath79_wdt.c return ioread32(wdt_base + reg); reg 229 drivers/watchdog/bd70528_wdt.c unsigned int reg; reg 260 drivers/watchdog/bd70528_wdt.c ret = regmap_read(w->regmap, BD70528_REG_WDT_CTRL, ®); reg 267 drivers/watchdog/bd70528_wdt.c if (reg & BD70528_MASK_WDT_EN) { reg 130 drivers/watchdog/f71808e_wdt.c static inline int superio_inb(int base, int reg); reg 131 drivers/watchdog/f71808e_wdt.c static inline int superio_inw(int base, int reg); reg 132 drivers/watchdog/f71808e_wdt.c static inline void superio_outb(int base, int reg, u8 val); reg 133 drivers/watchdog/f71808e_wdt.c static inline void superio_set_bit(int base, int reg, int bit); reg 134 drivers/watchdog/f71808e_wdt.c static inline void superio_clear_bit(int base, int reg, int bit); reg 160 drivers/watchdog/f71808e_wdt.c static inline int superio_inb(int base, int reg) reg 162 drivers/watchdog/f71808e_wdt.c outb(reg, base); reg 166 drivers/watchdog/f71808e_wdt.c static int superio_inw(int base, int reg) reg 169 drivers/watchdog/f71808e_wdt.c val = superio_inb(base, reg) << 8; reg 170 drivers/watchdog/f71808e_wdt.c val |= superio_inb(base, reg + 1); reg 174 drivers/watchdog/f71808e_wdt.c static inline void superio_outb(int base, int reg, u8 val) reg 176 drivers/watchdog/f71808e_wdt.c outb(reg, base); reg 180 drivers/watchdog/f71808e_wdt.c static inline void superio_set_bit(int base, int reg, int bit) reg 182 drivers/watchdog/f71808e_wdt.c unsigned long val = superio_inb(base, reg); reg 184 drivers/watchdog/f71808e_wdt.c superio_outb(base, reg, val); reg 187 drivers/watchdog/f71808e_wdt.c static inline void superio_clear_bit(int base, int reg, int bit) reg 189 drivers/watchdog/f71808e_wdt.c unsigned long val = superio_inb(base, reg); reg 191 drivers/watchdog/f71808e_wdt.c superio_outb(base, reg, val); reg 125 drivers/watchdog/ftwdt010_wdt.c unsigned int reg; reg 151 drivers/watchdog/ftwdt010_wdt.c reg = readw(gwdt->base + FTWDT010_WDCR); reg 152 drivers/watchdog/ftwdt010_wdt.c if (reg & WDCR_ENABLE) { reg 154 drivers/watchdog/ftwdt010_wdt.c reg &= ~WDCR_ENABLE; reg 155 drivers/watchdog/ftwdt010_wdt.c writel(reg, gwdt->base + FTWDT010_WDCR); reg 181 drivers/watchdog/ftwdt010_wdt.c unsigned int reg; reg 183 drivers/watchdog/ftwdt010_wdt.c reg = readw(gwdt->base + FTWDT010_WDCR); reg 184 drivers/watchdog/ftwdt010_wdt.c reg &= ~WDCR_ENABLE; reg 185 drivers/watchdog/ftwdt010_wdt.c writel(reg, gwdt->base + FTWDT010_WDCR); reg 193 drivers/watchdog/ftwdt010_wdt.c unsigned int reg; reg 196 drivers/watchdog/ftwdt010_wdt.c reg = readw(gwdt->base + FTWDT010_WDCR); reg 197 drivers/watchdog/ftwdt010_wdt.c reg |= WDCR_ENABLE; reg 198 drivers/watchdog/ftwdt010_wdt.c writel(reg, gwdt->base + FTWDT010_WDCR); reg 75 drivers/watchdog/ibmasr.c unsigned char reg; reg 77 drivers/watchdog/ibmasr.c reg = inb(asr_read_addr); reg 79 drivers/watchdog/ibmasr.c outb(reg & ~asr_toggle_mask, asr_write_addr); reg 80 drivers/watchdog/ibmasr.c reg = inb(asr_read_addr); reg 82 drivers/watchdog/ibmasr.c outb(reg | asr_toggle_mask, asr_write_addr); reg 83 drivers/watchdog/ibmasr.c reg = inb(asr_read_addr); reg 85 drivers/watchdog/ibmasr.c outb(reg & ~asr_toggle_mask, asr_write_addr); reg 86 drivers/watchdog/ibmasr.c reg = inb(asr_read_addr); reg 98 drivers/watchdog/ibmasr.c unsigned char reg; reg 103 drivers/watchdog/ibmasr.c reg = inb(asr_read_addr); reg 104 drivers/watchdog/ibmasr.c outb(reg & ~(TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE), reg 113 drivers/watchdog/ibmasr.c reg = inb(asr_read_addr); reg 114 drivers/watchdog/ibmasr.c outb(reg & ~asr_disable_mask, asr_write_addr); reg 116 drivers/watchdog/ibmasr.c reg = inb(asr_read_addr); reg 122 drivers/watchdog/ibmasr.c unsigned char reg; reg 125 drivers/watchdog/ibmasr.c reg = inb(asr_read_addr); reg 129 drivers/watchdog/ibmasr.c outb(reg | TOPAZ_ASR_TOGGLE | TOPAZ_ASR_DISABLE, reg 132 drivers/watchdog/ibmasr.c outb(reg | asr_toggle_mask, asr_write_addr); reg 133 drivers/watchdog/ibmasr.c reg = inb(asr_read_addr); reg 135 drivers/watchdog/ibmasr.c outb(reg | asr_disable_mask, asr_write_addr); reg 137 drivers/watchdog/ibmasr.c reg = inb(asr_read_addr); reg 93 drivers/watchdog/it8712f_wdt.c static int superio_inb(int reg) reg 95 drivers/watchdog/it8712f_wdt.c outb(reg, REG); reg 99 drivers/watchdog/it8712f_wdt.c static void superio_outb(int val, int reg) reg 101 drivers/watchdog/it8712f_wdt.c outb(reg, REG); reg 105 drivers/watchdog/it8712f_wdt.c static int superio_inw(int reg) reg 108 drivers/watchdog/it8712f_wdt.c outb(reg++, REG); reg 110 drivers/watchdog/it8712f_wdt.c outb(reg, REG); reg 130 drivers/watchdog/it87_wdt.c static inline int superio_inb(int reg) reg 132 drivers/watchdog/it87_wdt.c outb(reg, REG); reg 136 drivers/watchdog/it87_wdt.c static inline void superio_outb(int val, int reg) reg 138 drivers/watchdog/it87_wdt.c outb(reg, REG); reg 142 drivers/watchdog/it87_wdt.c static inline int superio_inw(int reg) reg 145 drivers/watchdog/it87_wdt.c outb(reg++, REG); reg 147 drivers/watchdog/it87_wdt.c outb(reg, REG); reg 152 drivers/watchdog/it87_wdt.c static inline void superio_outw(int val, int reg) reg 154 drivers/watchdog/it87_wdt.c outb(reg++, REG); reg 156 drivers/watchdog/it87_wdt.c outb(reg, REG); reg 75 drivers/watchdog/menz69_wdt.c u16 reg, val, ena; reg 80 drivers/watchdog/menz69_wdt.c reg = readw(drv->base + MEN_Z069_WVR); reg 81 drivers/watchdog/menz69_wdt.c ena = reg & MEN_Z069_WTR_WDEN; reg 82 drivers/watchdog/menz69_wdt.c reg = ena | val; reg 83 drivers/watchdog/menz69_wdt.c writew(reg, drv->base + MEN_Z069_WTR); reg 88 drivers/watchdog/meson_gxbb_wdt.c unsigned long reg; reg 90 drivers/watchdog/meson_gxbb_wdt.c reg = readl(data->reg_base + GXBB_WDT_TCNT_REG); reg 92 drivers/watchdog/meson_gxbb_wdt.c return ((reg & GXBB_WDT_TCNT_SETUP_MASK) - reg 93 drivers/watchdog/meson_gxbb_wdt.c (reg >> GXBB_WDT_TCNT_CNT_SHIFT)) / 1000; reg 90 drivers/watchdog/meson_wdt.c u32 reg; reg 92 drivers/watchdog/meson_wdt.c reg = readl(meson_wdt->wdt_base + MESON_WDT_TC); reg 93 drivers/watchdog/meson_wdt.c reg &= ~meson_wdt->data->terminal_count_mask; reg 94 drivers/watchdog/meson_wdt.c reg |= MESON_SEC_TO_TC(timeout, meson_wdt->data->count_unit); reg 95 drivers/watchdog/meson_wdt.c writel(reg, meson_wdt->wdt_base + MESON_WDT_TC); reg 112 drivers/watchdog/meson_wdt.c u32 reg; reg 114 drivers/watchdog/meson_wdt.c reg = readl(meson_wdt->wdt_base + MESON_WDT_TC); reg 115 drivers/watchdog/meson_wdt.c reg &= ~meson_wdt->data->enable; reg 116 drivers/watchdog/meson_wdt.c writel(reg, meson_wdt->wdt_base + MESON_WDT_TC); reg 124 drivers/watchdog/meson_wdt.c u32 reg; reg 129 drivers/watchdog/meson_wdt.c reg = readl(meson_wdt->wdt_base + MESON_WDT_TC); reg 130 drivers/watchdog/meson_wdt.c reg |= meson_wdt->data->enable; reg 131 drivers/watchdog/meson_wdt.c writel(reg, meson_wdt->wdt_base + MESON_WDT_TC); reg 68 drivers/watchdog/mlx_wdt.c rc = regmap_read(wdt->regmap, reg_data->reg, ®val); reg 83 drivers/watchdog/mlx_wdt.c return regmap_update_bits(wdt->regmap, reg_data->reg, ~reg_data->mask, reg 92 drivers/watchdog/mlx_wdt.c return regmap_update_bits(wdt->regmap, reg_data->reg, ~reg_data->mask, reg 101 drivers/watchdog/mlx_wdt.c return regmap_update_bits_base(wdt->regmap, reg_data->reg, reg 115 drivers/watchdog/mlx_wdt.c rc = regmap_read(wdt->regmap, reg_data->reg, ®val); reg 129 drivers/watchdog/mlx_wdt.c rc = regmap_write(wdt->regmap, reg_data->reg, regval); reg 153 drivers/watchdog/mlx_wdt.c rc = regmap_read(wdt->regmap, reg_data->reg, ®val); reg 43 drivers/watchdog/mt7621_wdt.c static inline void rt_wdt_w32(unsigned reg, u32 val) reg 45 drivers/watchdog/mt7621_wdt.c iowrite32(val, mt7621_wdt_base + reg); reg 48 drivers/watchdog/mt7621_wdt.c static inline u32 rt_wdt_r32(unsigned reg) reg 50 drivers/watchdog/mt7621_wdt.c return ioread32(mt7621_wdt_base + reg); reg 89 drivers/watchdog/mtk_wdt.c u32 reg; reg 97 drivers/watchdog/mtk_wdt.c reg = WDT_LENGTH_TIMEOUT(timeout << 6) | WDT_LENGTH_KEY; reg 98 drivers/watchdog/mtk_wdt.c iowrite32(reg, wdt_base + WDT_LENGTH); reg 109 drivers/watchdog/mtk_wdt.c u32 reg; reg 111 drivers/watchdog/mtk_wdt.c reg = readl(wdt_base + WDT_MODE); reg 112 drivers/watchdog/mtk_wdt.c reg &= ~WDT_MODE_EN; reg 113 drivers/watchdog/mtk_wdt.c reg |= WDT_MODE_KEY; reg 114 drivers/watchdog/mtk_wdt.c iowrite32(reg, wdt_base + WDT_MODE); reg 121 drivers/watchdog/mtk_wdt.c u32 reg; reg 130 drivers/watchdog/mtk_wdt.c reg = ioread32(wdt_base + WDT_MODE); reg 131 drivers/watchdog/mtk_wdt.c reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN); reg 132 drivers/watchdog/mtk_wdt.c reg |= (WDT_MODE_EN | WDT_MODE_KEY); reg 133 drivers/watchdog/mtk_wdt.c iowrite32(reg, wdt_base + WDT_MODE); reg 45 drivers/watchdog/npcm_wdt.c void __iomem *reg; reg 58 drivers/watchdog/npcm_wdt.c val = readl(wdt->reg); reg 59 drivers/watchdog/npcm_wdt.c writel(val | NPCM_WTR, wdt->reg); reg 92 drivers/watchdog/npcm_wdt.c writel(val, wdt->reg); reg 101 drivers/watchdog/npcm_wdt.c writel(0, wdt->reg); reg 151 drivers/watchdog/npcm_wdt.c writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, wdt->reg); reg 161 drivers/watchdog/npcm_wdt.c return readl(wdt->reg) & NPCM_WTE; reg 191 drivers/watchdog/npcm_wdt.c wdt->reg = devm_platform_ioremap_resource(pdev, 0); reg 192 drivers/watchdog/npcm_wdt.c if (IS_ERR(wdt->reg)) reg 193 drivers/watchdog/npcm_wdt.c return PTR_ERR(wdt->reg); reg 207 drivers/watchdog/octeon-wdt-main.c void octeon_wdt_nmi_stage3(u64 reg[32]) reg 231 drivers/watchdog/octeon-wdt-main.c octeon_wdt_write_hex(reg[i], 16); reg 73 drivers/watchdog/orion_wdt.c void __iomem *reg; reg 114 drivers/watchdog/orion_wdt.c atomic_io_modify(dev->reg + TIMER_CTRL, reg 135 drivers/watchdog/orion_wdt.c atomic_io_modify(dev->reg + TIMER_CTRL, reg 154 drivers/watchdog/orion_wdt.c atomic_io_modify(dev->reg + TIMER_CTRL, reg 179 drivers/watchdog/orion_wdt.c atomic_io_modify(dev->reg + TIMER_CTRL, val, val); reg 190 drivers/watchdog/orion_wdt.c dev->reg + dev->data->wdt_counter_offset); reg 193 drivers/watchdog/orion_wdt.c dev->reg + TIMER1_VAL_OFF); reg 201 drivers/watchdog/orion_wdt.c u32 reg; reg 205 drivers/watchdog/orion_wdt.c dev->reg + dev->data->wdt_counter_offset); reg 208 drivers/watchdog/orion_wdt.c dev->reg + TIMER1_VAL_OFF); reg 211 drivers/watchdog/orion_wdt.c atomic_io_modify(dev->reg + TIMER_A370_STATUS, WDT_A370_EXPIRED, 0); reg 214 drivers/watchdog/orion_wdt.c reg = dev->data->wdt_enable_bit; reg 216 drivers/watchdog/orion_wdt.c reg |= TIMER1_ENABLE_BIT; reg 217 drivers/watchdog/orion_wdt.c atomic_io_modify(dev->reg + TIMER_CTRL, reg, reg); reg 220 drivers/watchdog/orion_wdt.c reg = readl(dev->rstout); reg 221 drivers/watchdog/orion_wdt.c reg |= dev->data->rstout_enable_bit; reg 222 drivers/watchdog/orion_wdt.c writel(reg, dev->rstout); reg 231 drivers/watchdog/orion_wdt.c u32 reg; reg 235 drivers/watchdog/orion_wdt.c dev->reg + dev->data->wdt_counter_offset); reg 238 drivers/watchdog/orion_wdt.c atomic_io_modify(dev->reg + TIMER_A370_STATUS, WDT_A370_EXPIRED, 0); reg 241 drivers/watchdog/orion_wdt.c atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, reg 245 drivers/watchdog/orion_wdt.c reg = readl(dev->rstout); reg 246 drivers/watchdog/orion_wdt.c reg |= dev->data->rstout_enable_bit; reg 247 drivers/watchdog/orion_wdt.c writel(reg, dev->rstout); reg 257 drivers/watchdog/orion_wdt.c dev->reg + dev->data->wdt_counter_offset); reg 260 drivers/watchdog/orion_wdt.c atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, reg 286 drivers/watchdog/orion_wdt.c atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, 0); reg 294 drivers/watchdog/orion_wdt.c u32 reg, mask; reg 299 drivers/watchdog/orion_wdt.c reg = readl(dev->rstout); reg 300 drivers/watchdog/orion_wdt.c reg &= ~dev->data->rstout_enable_bit; reg 301 drivers/watchdog/orion_wdt.c writel(reg, dev->rstout); reg 307 drivers/watchdog/orion_wdt.c atomic_io_modify(dev->reg + TIMER_CTRL, mask, 0); reg 315 drivers/watchdog/orion_wdt.c u32 reg; reg 318 drivers/watchdog/orion_wdt.c reg = readl(dev->rstout); reg 319 drivers/watchdog/orion_wdt.c reg &= ~dev->data->rstout_enable_bit; reg 320 drivers/watchdog/orion_wdt.c writel(reg, dev->rstout); reg 323 drivers/watchdog/orion_wdt.c atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, 0); reg 340 drivers/watchdog/orion_wdt.c running = readl(dev->reg + TIMER_CTRL) & dev->data->wdt_enable_bit; reg 351 drivers/watchdog/orion_wdt.c running = readl(dev->reg + TIMER_CTRL) & dev->data->wdt_enable_bit; reg 366 drivers/watchdog/orion_wdt.c return readl(dev->reg + dev->data->wdt_counter_offset) / dev->clk_rate; reg 392 drivers/watchdog/orion_wdt.c atomic_io_modify(dev->reg + TIMER_A370_STATUS, reg 507 drivers/watchdog/orion_wdt.c dev->reg = devm_ioremap(&pdev->dev, res->start, reg 509 drivers/watchdog/orion_wdt.c if (!dev->reg) reg 50 drivers/watchdog/qcom-wdt.c static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg) reg 52 drivers/watchdog/qcom-wdt.c return wdt->base + wdt->layout[reg]; reg 55 drivers/watchdog/renesas_wdt.c static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg) reg 57 drivers/watchdog/renesas_wdt.c if (reg == RWTCNT) reg 62 drivers/watchdog/renesas_wdt.c writel_relaxed(val, priv->base + reg); reg 54 drivers/watchdog/rt2880_wdt.c static inline void rt_wdt_w32(unsigned reg, u32 val) reg 56 drivers/watchdog/rt2880_wdt.c iowrite32(val, rt288x_wdt_base + reg); reg 59 drivers/watchdog/rt2880_wdt.c static inline u32 rt_wdt_r32(unsigned reg) reg 61 drivers/watchdog/rt2880_wdt.c return ioread32(rt288x_wdt_base + reg); reg 179 drivers/watchdog/sama5d4_wdt.c u32 reg; reg 189 drivers/watchdog/sama5d4_wdt.c reg = wdt_read(wdt, AT91_WDT_MR); reg 190 drivers/watchdog/sama5d4_wdt.c if (!(reg & AT91_WDT_WDDIS)) reg 192 drivers/watchdog/sama5d4_wdt.c reg | AT91_WDT_WDDIS); reg 133 drivers/watchdog/sc1200wdt.c unsigned char reg; reg 136 drivers/watchdog/sc1200wdt.c __sc1200wdt_read_data(WDCF, ®); reg 138 drivers/watchdog/sc1200wdt.c reg |= (KBC_IRQ | MSE_IRQ | UART1_IRQ | UART2_IRQ); reg 139 drivers/watchdog/sc1200wdt.c __sc1200wdt_write_data(WDCF, reg); reg 330 drivers/watchdog/sc1200wdt.c unsigned char reg; reg 332 drivers/watchdog/sc1200wdt.c sc1200wdt_read_data(PMC3, ®); reg 333 drivers/watchdog/sc1200wdt.c reg &= 0x0f; /* we don't want the UART busy bits */ reg 334 drivers/watchdog/sc1200wdt.c return (reg == 0x0e) ? 0 : -ENODEV; reg 93 drivers/watchdog/sch311x_wdt.c static inline int sch311x_sio_inb(int sio_config_port, int reg) reg 95 drivers/watchdog/sch311x_wdt.c outb(reg, sio_config_port); reg 99 drivers/watchdog/sch311x_wdt.c static inline void sch311x_sio_outb(int sio_config_port, int reg, int val) reg 101 drivers/watchdog/sch311x_wdt.c outb(reg, sio_config_port); reg 458 drivers/watchdog/sch311x_wdt.c int err = 0, reg; reg 466 drivers/watchdog/sch311x_wdt.c reg = force_id ? force_id : sch311x_sio_inb(sio_config_port, 0x20); reg 467 drivers/watchdog/sch311x_wdt.c if (!(reg == 0x7c || reg == 0x7d || reg == 0x7f)) { reg 471 drivers/watchdog/sch311x_wdt.c dev_id = reg == 0x7c ? 2 : reg == 0x7d ? 4 : 6; reg 111 drivers/watchdog/smsc37b787_wdt.c static inline void write_io_cr(unsigned char reg, unsigned char data) reg 113 drivers/watchdog/smsc37b787_wdt.c outb(reg, IOPORT); reg 118 drivers/watchdog/smsc37b787_wdt.c static inline char read_io_cr(unsigned char reg) reg 120 drivers/watchdog/smsc37b787_wdt.c outb(reg, IOPORT); reg 126 drivers/watchdog/smsc37b787_wdt.c static inline void gpio_bit12(unsigned char reg) reg 137 drivers/watchdog/smsc37b787_wdt.c write_io_cr(0xE2, reg); reg 140 drivers/watchdog/smsc37b787_wdt.c static inline void gpio_bit13(unsigned char reg) reg 150 drivers/watchdog/smsc37b787_wdt.c write_io_cr(0xE3, reg); reg 187 drivers/watchdog/smsc37b787_wdt.c static inline void wdt_timer_ctrl(unsigned char reg) reg 206 drivers/watchdog/smsc37b787_wdt.c write_io_cr(0xF4, reg); reg 77 drivers/watchdog/stm32_iwdg.c static inline u32 reg_read(void __iomem *base, u32 reg) reg 79 drivers/watchdog/stm32_iwdg.c return readl_relaxed(base + reg); reg 82 drivers/watchdog/stm32_iwdg.c static inline void reg_write(void __iomem *base, u32 reg, u32 val) reg 84 drivers/watchdog/stm32_iwdg.c writel_relaxed(val, base + reg); reg 134 drivers/watchdog/sunxi_wdt.c u32 reg; reg 141 drivers/watchdog/sunxi_wdt.c reg = readl(wdt_base + regs->wdt_mode); reg 142 drivers/watchdog/sunxi_wdt.c reg &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift); reg 143 drivers/watchdog/sunxi_wdt.c reg |= wdt_timeout_map[timeout] << regs->wdt_timeout_shift; reg 144 drivers/watchdog/sunxi_wdt.c writel(reg, wdt_base + regs->wdt_mode); reg 164 drivers/watchdog/sunxi_wdt.c u32 reg; reg 176 drivers/watchdog/sunxi_wdt.c reg = readl(wdt_base + regs->wdt_cfg); reg 177 drivers/watchdog/sunxi_wdt.c reg &= ~(regs->wdt_reset_mask); reg 178 drivers/watchdog/sunxi_wdt.c reg |= regs->wdt_reset_val; reg 179 drivers/watchdog/sunxi_wdt.c writel(reg, wdt_base + regs->wdt_cfg); reg 182 drivers/watchdog/sunxi_wdt.c reg = readl(wdt_base + regs->wdt_mode); reg 183 drivers/watchdog/sunxi_wdt.c reg |= WDT_MODE_EN; reg 184 drivers/watchdog/sunxi_wdt.c writel(reg, wdt_base + regs->wdt_mode); reg 116 drivers/watchdog/ts4800_wdt.c u32 reg; reg 125 drivers/watchdog/ts4800_wdt.c ret = of_property_read_u32_index(np, "syscon", 1, ®); reg 137 drivers/watchdog/ts4800_wdt.c wdt->feed_offset = reg; reg 115 drivers/watchdog/w83627hf_wdt.c static void superio_outb(int reg, int val) reg 117 drivers/watchdog/w83627hf_wdt.c outb(reg, WDT_EFER); reg 121 drivers/watchdog/w83627hf_wdt.c static inline int superio_inb(int reg) reg 123 drivers/watchdog/w83627hf_wdt.c outb(reg, WDT_EFER); reg 26 drivers/watchdog/wdat_wdt.c void __iomem *reg; reg 71 drivers/watchdog/wdat_wdt.c *value = ioread8(instr->reg); reg 74 drivers/watchdog/wdat_wdt.c *value = ioread16(instr->reg); reg 77 drivers/watchdog/wdat_wdt.c *value = ioread32(instr->reg); reg 96 drivers/watchdog/wdat_wdt.c iowrite8((u8)value, instr->reg); reg 99 drivers/watchdog/wdat_wdt.c iowrite16((u16)value, instr->reg); reg 102 drivers/watchdog/wdat_wdt.c iowrite32(value, instr->reg); reg 354 drivers/watchdog/wdat_wdt.c void __iomem *reg; reg 358 drivers/watchdog/wdat_wdt.c reg = devm_ioremap_resource(dev, res); reg 359 drivers/watchdog/wdat_wdt.c if (IS_ERR(reg)) reg 360 drivers/watchdog/wdat_wdt.c return PTR_ERR(reg); reg 362 drivers/watchdog/wdat_wdt.c reg = devm_ioport_map(dev, res->start, 1); reg 363 drivers/watchdog/wdat_wdt.c if (!reg) reg 370 drivers/watchdog/wdat_wdt.c regs[i] = reg; reg 414 drivers/watchdog/wdat_wdt.c instr->reg = regs[j] + r.start - res->start; reg 419 drivers/watchdog/wdat_wdt.c if (!instr->reg) { reg 102 drivers/watchdog/wm831x_wdt.c u16 reg; reg 114 drivers/watchdog/wm831x_wdt.c reg = wm831x_reg_read(wm831x, WM831X_WATCHDOG); reg 116 drivers/watchdog/wm831x_wdt.c if (!(reg & WM831X_WDOG_RST_SRC)) { reg 122 drivers/watchdog/wm831x_wdt.c reg |= WM831X_WDOG_RESET; reg 126 drivers/watchdog/wm831x_wdt.c ret = wm831x_reg_write(wm831x, WM831X_WATCHDOG, reg); reg 189 drivers/watchdog/wm831x_wdt.c int reg, ret, i; reg 197 drivers/watchdog/wm831x_wdt.c reg = ret; reg 199 drivers/watchdog/wm831x_wdt.c if (reg & WM831X_WDOG_DEBUG) reg 217 drivers/watchdog/wm831x_wdt.c reg = wm831x_reg_read(wm831x, WM831X_WATCHDOG); reg 218 drivers/watchdog/wm831x_wdt.c reg &= WM831X_WDOG_TO_MASK; reg 220 drivers/watchdog/wm831x_wdt.c if (wm831x_wdt_cfgs[i].val == reg) reg 224 drivers/watchdog/wm831x_wdt.c "Unknown watchdog timeout: %x\n", reg); reg 235 drivers/watchdog/wm831x_wdt.c reg &= ~(WM831X_WDOG_SECACT_MASK | WM831X_WDOG_PRIMACT_MASK | reg 238 drivers/watchdog/wm831x_wdt.c reg |= pdata->primary << WM831X_WDOG_PRIMACT_SHIFT; reg 239 drivers/watchdog/wm831x_wdt.c reg |= pdata->secondary << WM831X_WDOG_SECACT_SHIFT; reg 240 drivers/watchdog/wm831x_wdt.c reg |= pdata->software << WM831X_WDOG_RST_SRC_SHIFT; reg 256 drivers/watchdog/wm831x_wdt.c reg |= WM831X_WDOG_RST_SRC; reg 261 drivers/watchdog/wm831x_wdt.c ret = wm831x_reg_write(wm831x, WM831X_WATCHDOG, reg); reg 41 drivers/watchdog/wm8350_wdt.c u16 reg; reg 52 drivers/watchdog/wm8350_wdt.c reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2); reg 53 drivers/watchdog/wm8350_wdt.c reg &= ~WM8350_WDOG_TO_MASK; reg 54 drivers/watchdog/wm8350_wdt.c reg |= wm8350_wdt_cfgs[i].val; reg 55 drivers/watchdog/wm8350_wdt.c ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg); reg 68 drivers/watchdog/wm8350_wdt.c u16 reg; reg 73 drivers/watchdog/wm8350_wdt.c reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2); reg 74 drivers/watchdog/wm8350_wdt.c reg &= ~WM8350_WDOG_MODE_MASK; reg 75 drivers/watchdog/wm8350_wdt.c reg |= 0x20; reg 76 drivers/watchdog/wm8350_wdt.c ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg); reg 88 drivers/watchdog/wm8350_wdt.c u16 reg; reg 93 drivers/watchdog/wm8350_wdt.c reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2); reg 94 drivers/watchdog/wm8350_wdt.c reg &= ~WM8350_WDOG_MODE_MASK; reg 95 drivers/watchdog/wm8350_wdt.c ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg); reg 107 drivers/watchdog/wm8350_wdt.c u16 reg; reg 111 drivers/watchdog/wm8350_wdt.c reg = wm8350_reg_read(wm8350, WM8350_SYSTEM_CONTROL_2); reg 112 drivers/watchdog/wm8350_wdt.c ret = wm8350_reg_write(wm8350, WM8350_SYSTEM_CONTROL_2, reg); reg 54 drivers/watchdog/zx2967_wdt.c static inline u32 zx2967_wdt_readl(struct zx2967_wdt *wdt, u16 reg) reg 56 drivers/watchdog/zx2967_wdt.c return readl_relaxed(wdt->reg_base + reg); reg 59 drivers/watchdog/zx2967_wdt.c static inline void zx2967_wdt_writel(struct zx2967_wdt *wdt, u16 reg, u32 val) reg 61 drivers/watchdog/zx2967_wdt.c writel_relaxed(val | ZX2967_WDT_WRITEKEY, wdt->reg_base + reg); reg 75 drivers/xen/xen-acpi-processor.c dst_cx->reg.space_id = ACPI_ADR_SPACE_SYSTEM_IO; reg 77 drivers/xen/xen-acpi-processor.c dst_cx->reg.bit_width = 8; reg 78 drivers/xen/xen-acpi-processor.c dst_cx->reg.bit_offset = 0; reg 79 drivers/xen/xen-acpi-processor.c dst_cx->reg.access_size = 1; reg 81 drivers/xen/xen-acpi-processor.c dst_cx->reg.space_id = ACPI_ADR_SPACE_FIXED_HARDWARE; reg 84 drivers/xen/xen-acpi-processor.c dst_cx->reg.bit_offset = 2; reg 85 drivers/xen/xen-acpi-processor.c dst_cx->reg.bit_width = 1; /* VENDOR_INTEL */ reg 87 drivers/xen/xen-acpi-processor.c dst_cx->reg.access_size = 0; reg 89 drivers/xen/xen-acpi-processor.c dst_cx->reg.address = cx->address; reg 49 drivers/xen/xen-pciback/conf_space_quirks.c int xen_pcibk_field_is_dup(struct pci_dev *dev, unsigned int reg) reg 56 drivers/xen/xen-pciback/conf_space_quirks.c if (OFFSET(cfg_entry) == reg) { reg 24 drivers/xen/xen-pciback/conf_space_quirks.h int xen_pcibk_config_quirks_remove_field(struct pci_dev *dev, int reg); reg 32 drivers/xen/xen-pciback/conf_space_quirks.h int xen_pcibk_field_is_dup(struct pci_dev *dev, unsigned int reg); reg 1046 drivers/xen/xen-pciback/pci_stub.c *slot, int *func, int *reg, int *size, int *mask) reg 1051 drivers/xen/xen-pciback/pci_stub.c reg, size, mask, &parsed); reg 1057 drivers/xen/xen-pciback/pci_stub.c sscanf(buf, " %x:%x.%x-%x:%x:%x %n", bus, slot, func, reg, size, reg 1135 drivers/xen/xen-pciback/pci_stub.c unsigned int reg, unsigned int size, reg 1143 drivers/xen/xen-pciback/pci_stub.c if (reg > 0xfff || (size < 4 && (mask >> (size * 8)))) reg 1159 drivers/xen/xen-pciback/pci_stub.c field->offset = reg; reg 1309 drivers/xen/xen-pciback/pci_stub.c int domain, bus, slot, func, reg, size, mask; reg 1312 drivers/xen/xen-pciback/pci_stub.c err = str_to_quirk(buf, &domain, &bus, &slot, &func, ®, &size, reg 1317 drivers/xen/xen-pciback/pci_stub.c err = pcistub_reg_add(domain, bus, slot, func, reg, size, mask); reg 290 fs/ocfs2/cluster/heartbeat.c struct o2hb_region *reg = reg 295 fs/ocfs2/cluster/heartbeat.c "milliseconds\n", reg->hr_dev_name, reg 296 fs/ocfs2/cluster/heartbeat.c jiffies_to_msecs(jiffies - reg->hr_last_timeout_start)); reg 300 fs/ocfs2/cluster/heartbeat.c if (test_bit(reg->hr_region_num, o2hb_quorum_region_bitmap)) reg 301 fs/ocfs2/cluster/heartbeat.c set_bit(reg->hr_region_num, o2hb_failed_region_bitmap); reg 322 fs/ocfs2/cluster/heartbeat.c static void o2hb_arm_timeout(struct o2hb_region *reg) reg 325 fs/ocfs2/cluster/heartbeat.c if (atomic_read(®->hr_steady_iterations) != 0) reg 333 fs/ocfs2/cluster/heartbeat.c clear_bit(reg->hr_region_num, o2hb_failed_region_bitmap); reg 336 fs/ocfs2/cluster/heartbeat.c cancel_delayed_work(®->hr_write_timeout_work); reg 337 fs/ocfs2/cluster/heartbeat.c schedule_delayed_work(®->hr_write_timeout_work, reg 340 fs/ocfs2/cluster/heartbeat.c cancel_delayed_work(®->hr_nego_timeout_work); reg 342 fs/ocfs2/cluster/heartbeat.c schedule_delayed_work(®->hr_nego_timeout_work, reg 344 fs/ocfs2/cluster/heartbeat.c memset(reg->hr_nego_node_bitmap, 0, sizeof(reg->hr_nego_node_bitmap)); reg 347 fs/ocfs2/cluster/heartbeat.c static void o2hb_disarm_timeout(struct o2hb_region *reg) reg 349 fs/ocfs2/cluster/heartbeat.c cancel_delayed_work_sync(®->hr_write_timeout_work); reg 350 fs/ocfs2/cluster/heartbeat.c cancel_delayed_work_sync(®->hr_nego_timeout_work); reg 375 fs/ocfs2/cluster/heartbeat.c struct o2hb_region *reg; reg 377 fs/ocfs2/cluster/heartbeat.c reg = container_of(work, struct o2hb_region, hr_nego_timeout_work.work); reg 381 fs/ocfs2/cluster/heartbeat.c if (reg->hr_last_hb_status) reg 389 fs/ocfs2/cluster/heartbeat.c if (!test_bit(master_node, reg->hr_nego_node_bitmap)) { reg 392 fs/ocfs2/cluster/heartbeat.c config_item_name(®->hr_item), reg->hr_dev_name); reg 393 fs/ocfs2/cluster/heartbeat.c set_bit(master_node, reg->hr_nego_node_bitmap); reg 395 fs/ocfs2/cluster/heartbeat.c if (memcmp(reg->hr_nego_node_bitmap, live_node_bitmap, reg 396 fs/ocfs2/cluster/heartbeat.c sizeof(reg->hr_nego_node_bitmap))) { reg 400 fs/ocfs2/cluster/heartbeat.c schedule_delayed_work(®->hr_nego_timeout_work, reg 407 fs/ocfs2/cluster/heartbeat.c config_item_name(®->hr_item), reg->hr_dev_name); reg 409 fs/ocfs2/cluster/heartbeat.c o2hb_arm_timeout(reg); reg 418 fs/ocfs2/cluster/heartbeat.c ret = o2hb_send_nego_msg(reg->hr_key, reg 427 fs/ocfs2/cluster/heartbeat.c o2nm_this_node(), O2HB_NEGO_TIMEOUT_MS/1000, config_item_name(®->hr_item), reg 428 fs/ocfs2/cluster/heartbeat.c reg->hr_dev_name, master_node); reg 429 fs/ocfs2/cluster/heartbeat.c ret = o2hb_send_nego_msg(reg->hr_key, O2HB_NEGO_TIMEOUT_MSG, reg 440 fs/ocfs2/cluster/heartbeat.c struct o2hb_region *reg = data; reg 445 fs/ocfs2/cluster/heartbeat.c nego_msg->node_num, config_item_name(®->hr_item), reg->hr_dev_name); reg 447 fs/ocfs2/cluster/heartbeat.c set_bit(nego_msg->node_num, reg->hr_nego_node_bitmap); reg 457 fs/ocfs2/cluster/heartbeat.c struct o2hb_region *reg = data; reg 460 fs/ocfs2/cluster/heartbeat.c config_item_name(®->hr_item), reg->hr_dev_name); reg 461 fs/ocfs2/cluster/heartbeat.c o2hb_arm_timeout(reg); reg 507 fs/ocfs2/cluster/heartbeat.c static struct bio *o2hb_setup_one_bio(struct o2hb_region *reg, reg 515 fs/ocfs2/cluster/heartbeat.c unsigned int bits = reg->hr_block_bits; reg 516 fs/ocfs2/cluster/heartbeat.c unsigned int spp = reg->hr_slots_per_page; reg 533 fs/ocfs2/cluster/heartbeat.c bio->bi_iter.bi_sector = (reg->hr_start_block + cs) << (bits - 9); reg 534 fs/ocfs2/cluster/heartbeat.c bio_set_dev(bio, reg->hr_bdev); reg 542 fs/ocfs2/cluster/heartbeat.c page = reg->hr_slot_data[current_page]; reg 562 fs/ocfs2/cluster/heartbeat.c static int o2hb_read_slots(struct o2hb_region *reg, reg 574 fs/ocfs2/cluster/heartbeat.c bio = o2hb_setup_one_bio(reg, &wc, ¤t_slot, max_slots, reg 596 fs/ocfs2/cluster/heartbeat.c static int o2hb_issue_node_write(struct o2hb_region *reg, reg 607 fs/ocfs2/cluster/heartbeat.c bio = o2hb_setup_one_bio(reg, write_wc, &slot, slot+1, REQ_OP_WRITE, reg 623 fs/ocfs2/cluster/heartbeat.c static u32 o2hb_compute_block_crc_le(struct o2hb_region *reg, reg 635 fs/ocfs2/cluster/heartbeat.c ret = crc32_le(0, (unsigned char *) hb_block, reg->hr_block_bytes); reg 651 fs/ocfs2/cluster/heartbeat.c static int o2hb_verify_crc(struct o2hb_region *reg, reg 657 fs/ocfs2/cluster/heartbeat.c computed = o2hb_compute_block_crc_le(reg, hb_block); reg 669 fs/ocfs2/cluster/heartbeat.c static int o2hb_check_own_slot(struct o2hb_region *reg) reg 675 fs/ocfs2/cluster/heartbeat.c slot = ®->hr_slots[o2nm_this_node()]; reg 699 fs/ocfs2/cluster/heartbeat.c "ondisk(%u:0x%llx, 0x%llx)\n", errstr, reg->hr_dev_name, reg 708 fs/ocfs2/cluster/heartbeat.c static inline void o2hb_prepare_block(struct o2hb_region *reg, reg 717 fs/ocfs2/cluster/heartbeat.c slot = ®->hr_slots[node_num]; reg 720 fs/ocfs2/cluster/heartbeat.c memset(hb_block, 0, reg->hr_block_bytes); reg 732 fs/ocfs2/cluster/heartbeat.c hb_block->hb_cksum = cpu_to_le32(o2hb_compute_block_crc_le(reg, reg 845 fs/ocfs2/cluster/heartbeat.c static void o2hb_set_quorum_device(struct o2hb_region *reg) reg 855 fs/ocfs2/cluster/heartbeat.c if (atomic_read(®->hr_steady_iterations) != 0) reg 860 fs/ocfs2/cluster/heartbeat.c if (test_bit(reg->hr_region_num, o2hb_quorum_region_bitmap)) reg 868 fs/ocfs2/cluster/heartbeat.c if (memcmp(reg->hr_live_node_bitmap, o2hb_live_node_bitmap, reg 873 fs/ocfs2/cluster/heartbeat.c config_item_name(®->hr_item), reg->hr_dev_name); reg 875 fs/ocfs2/cluster/heartbeat.c set_bit(reg->hr_region_num, o2hb_quorum_region_bitmap); reg 888 fs/ocfs2/cluster/heartbeat.c static int o2hb_check_slot(struct o2hb_region *reg, reg 895 fs/ocfs2/cluster/heartbeat.c struct o2hb_disk_heartbeat_block *hb_block = reg->hr_tmp_block; reg 902 fs/ocfs2/cluster/heartbeat.c memcpy(hb_block, slot->ds_raw_block, reg->hr_block_bytes); reg 917 fs/ocfs2/cluster/heartbeat.c if (!o2hb_verify_crc(reg, hb_block)) { reg 932 fs/ocfs2/cluster/heartbeat.c slot->ds_node_num, reg->hr_dev_name); reg 982 fs/ocfs2/cluster/heartbeat.c set_bit(slot->ds_node_num, reg->hr_live_node_bitmap); reg 1015 fs/ocfs2/cluster/heartbeat.c slot->ds_node_num, reg->hr_dev_name, slot_dead_ms, reg 1032 fs/ocfs2/cluster/heartbeat.c clear_bit(slot->ds_node_num, reg->hr_live_node_bitmap); reg 1080 fs/ocfs2/cluster/heartbeat.c static int o2hb_do_disk_heartbeat(struct o2hb_region *reg) reg 1118 fs/ocfs2/cluster/heartbeat.c ret = o2hb_read_slots(reg, lowest_node, highest_node + 1); reg 1127 fs/ocfs2/cluster/heartbeat.c own_slot_ok = o2hb_check_own_slot(reg); reg 1130 fs/ocfs2/cluster/heartbeat.c o2hb_prepare_block(reg, reg->hr_generation); reg 1132 fs/ocfs2/cluster/heartbeat.c ret = o2hb_issue_node_write(reg, &write_wc); reg 1141 fs/ocfs2/cluster/heartbeat.c membership_change |= o2hb_check_slot(reg, ®->hr_slots[i]); reg 1155 fs/ocfs2/cluster/heartbeat.c write_wc.wc_error, reg->hr_dev_name); reg 1162 fs/ocfs2/cluster/heartbeat.c o2hb_set_quorum_device(reg); reg 1163 fs/ocfs2/cluster/heartbeat.c o2hb_arm_timeout(reg); reg 1164 fs/ocfs2/cluster/heartbeat.c reg->hr_last_timeout_start = jiffies; reg 1169 fs/ocfs2/cluster/heartbeat.c if (atomic_read(®->hr_steady_iterations) != 0) { reg 1171 fs/ocfs2/cluster/heartbeat.c if (atomic_dec_and_test(®->hr_steady_iterations)) reg 1176 fs/ocfs2/cluster/heartbeat.c if (atomic_read(®->hr_steady_iterations) != 0) { reg 1177 fs/ocfs2/cluster/heartbeat.c if (atomic_dec_and_test(®->hr_unsteady_iterations)) { reg 1180 fs/ocfs2/cluster/heartbeat.c config_item_name(®->hr_item), reg 1181 fs/ocfs2/cluster/heartbeat.c reg->hr_dev_name); reg 1182 fs/ocfs2/cluster/heartbeat.c atomic_set(®->hr_steady_iterations, 0); reg 1183 fs/ocfs2/cluster/heartbeat.c reg->hr_aborted_start = 1; reg 1200 fs/ocfs2/cluster/heartbeat.c struct o2hb_region *reg = data; reg 1213 fs/ocfs2/cluster/heartbeat.c reg->hr_node_deleted = 1; reg 1219 fs/ocfs2/cluster/heartbeat.c !reg->hr_unclean_stop && !reg->hr_aborted_start) { reg 1227 fs/ocfs2/cluster/heartbeat.c ret = o2hb_do_disk_heartbeat(reg); reg 1228 fs/ocfs2/cluster/heartbeat.c reg->hr_last_hb_status = ret; reg 1240 fs/ocfs2/cluster/heartbeat.c elapsed_msec < reg->hr_timeout_ms) { reg 1243 fs/ocfs2/cluster/heartbeat.c msleep_interruptible(reg->hr_timeout_ms - elapsed_msec); reg 1247 fs/ocfs2/cluster/heartbeat.c o2hb_disarm_timeout(reg); reg 1250 fs/ocfs2/cluster/heartbeat.c for(i = 0; !reg->hr_unclean_stop && i < reg->hr_blocks; i++) reg 1251 fs/ocfs2/cluster/heartbeat.c o2hb_shutdown_slot(®->hr_slots[i]); reg 1258 fs/ocfs2/cluster/heartbeat.c if (!reg->hr_unclean_stop && !reg->hr_aborted_start) { reg 1259 fs/ocfs2/cluster/heartbeat.c o2hb_prepare_block(reg, 0); reg 1260 fs/ocfs2/cluster/heartbeat.c ret = o2hb_issue_node_write(reg, &write_wc); reg 1279 fs/ocfs2/cluster/heartbeat.c struct o2hb_region *reg; reg 1305 fs/ocfs2/cluster/heartbeat.c reg = (struct o2hb_region *)db->db_data; reg 1306 fs/ocfs2/cluster/heartbeat.c memcpy(map, reg->hr_live_node_bitmap, db->db_size); reg 1311 fs/ocfs2/cluster/heartbeat.c reg = (struct o2hb_region *)db->db_data; reg 1313 fs/ocfs2/cluster/heartbeat.c reg->hr_region_num); reg 1317 fs/ocfs2/cluster/heartbeat.c reg = (struct o2hb_region *)db->db_data; reg 1318 fs/ocfs2/cluster/heartbeat.c lts = reg->hr_last_timeout_start; reg 1326 fs/ocfs2/cluster/heartbeat.c reg = (struct o2hb_region *)db->db_data; reg 1328 fs/ocfs2/cluster/heartbeat.c !!reg->hr_item_pinned); reg 1503 fs/ocfs2/cluster/heartbeat.c struct o2hb_region *reg = to_o2hb_region(item); reg 1505 fs/ocfs2/cluster/heartbeat.c mlog(ML_HEARTBEAT, "hb region release (%s)\n", reg->hr_dev_name); reg 1507 fs/ocfs2/cluster/heartbeat.c kfree(reg->hr_tmp_block); reg 1509 fs/ocfs2/cluster/heartbeat.c if (reg->hr_slot_data) { reg 1510 fs/ocfs2/cluster/heartbeat.c for (i = 0; i < reg->hr_num_pages; i++) { reg 1511 fs/ocfs2/cluster/heartbeat.c page = reg->hr_slot_data[i]; reg 1515 fs/ocfs2/cluster/heartbeat.c kfree(reg->hr_slot_data); reg 1518 fs/ocfs2/cluster/heartbeat.c if (reg->hr_bdev) reg 1519 fs/ocfs2/cluster/heartbeat.c blkdev_put(reg->hr_bdev, FMODE_READ|FMODE_WRITE); reg 1521 fs/ocfs2/cluster/heartbeat.c kfree(reg->hr_slots); reg 1523 fs/ocfs2/cluster/heartbeat.c debugfs_remove_recursive(reg->hr_debug_dir); reg 1524 fs/ocfs2/cluster/heartbeat.c kfree(reg->hr_db_livenodes); reg 1525 fs/ocfs2/cluster/heartbeat.c kfree(reg->hr_db_regnum); reg 1526 fs/ocfs2/cluster/heartbeat.c kfree(reg->hr_db_elapsed_time); reg 1527 fs/ocfs2/cluster/heartbeat.c kfree(reg->hr_db_pinned); reg 1530 fs/ocfs2/cluster/heartbeat.c list_del(®->hr_all_item); reg 1533 fs/ocfs2/cluster/heartbeat.c o2net_unregister_handler_list(®->hr_handler_list); reg 1534 fs/ocfs2/cluster/heartbeat.c kfree(reg); reg 1537 fs/ocfs2/cluster/heartbeat.c static int o2hb_read_block_input(struct o2hb_region *reg, reg 1573 fs/ocfs2/cluster/heartbeat.c struct o2hb_region *reg = to_o2hb_region(item); reg 1578 fs/ocfs2/cluster/heartbeat.c if (reg->hr_bdev) reg 1581 fs/ocfs2/cluster/heartbeat.c status = o2hb_read_block_input(reg, page, &block_bytes, reg 1586 fs/ocfs2/cluster/heartbeat.c reg->hr_block_bytes = (unsigned int)block_bytes; reg 1587 fs/ocfs2/cluster/heartbeat.c reg->hr_block_bits = block_bits; reg 1602 fs/ocfs2/cluster/heartbeat.c struct o2hb_region *reg = to_o2hb_region(item); reg 1606 fs/ocfs2/cluster/heartbeat.c if (reg->hr_bdev) reg 1613 fs/ocfs2/cluster/heartbeat.c reg->hr_start_block = tmp; reg 1627 fs/ocfs2/cluster/heartbeat.c struct o2hb_region *reg = to_o2hb_region(item); reg 1631 fs/ocfs2/cluster/heartbeat.c if (reg->hr_bdev) reg 1641 fs/ocfs2/cluster/heartbeat.c reg->hr_blocks = (unsigned int)tmp; reg 1656 fs/ocfs2/cluster/heartbeat.c static void o2hb_init_region_params(struct o2hb_region *reg) reg 1658 fs/ocfs2/cluster/heartbeat.c reg->hr_slots_per_page = PAGE_SIZE >> reg->hr_block_bits; reg 1659 fs/ocfs2/cluster/heartbeat.c reg->hr_timeout_ms = O2HB_REGION_TIMEOUT_MS; reg 1662 fs/ocfs2/cluster/heartbeat.c reg->hr_start_block, reg->hr_blocks); reg 1664 fs/ocfs2/cluster/heartbeat.c reg->hr_block_bytes, reg->hr_block_bits); reg 1665 fs/ocfs2/cluster/heartbeat.c mlog(ML_HEARTBEAT, "hr_timeout_ms = %u\n", reg->hr_timeout_ms); reg 1669 fs/ocfs2/cluster/heartbeat.c static int o2hb_map_slot_data(struct o2hb_region *reg) reg 1673 fs/ocfs2/cluster/heartbeat.c unsigned int spp = reg->hr_slots_per_page; reg 1678 fs/ocfs2/cluster/heartbeat.c reg->hr_tmp_block = kmalloc(reg->hr_block_bytes, GFP_KERNEL); reg 1679 fs/ocfs2/cluster/heartbeat.c if (reg->hr_tmp_block == NULL) reg 1682 fs/ocfs2/cluster/heartbeat.c reg->hr_slots = kcalloc(reg->hr_blocks, reg 1684 fs/ocfs2/cluster/heartbeat.c if (reg->hr_slots == NULL) reg 1687 fs/ocfs2/cluster/heartbeat.c for(i = 0; i < reg->hr_blocks; i++) { reg 1688 fs/ocfs2/cluster/heartbeat.c slot = ®->hr_slots[i]; reg 1694 fs/ocfs2/cluster/heartbeat.c reg->hr_num_pages = (reg->hr_blocks + spp - 1) / spp; reg 1697 fs/ocfs2/cluster/heartbeat.c reg->hr_num_pages, reg->hr_blocks, spp); reg 1699 fs/ocfs2/cluster/heartbeat.c reg->hr_slot_data = kcalloc(reg->hr_num_pages, sizeof(struct page *), reg 1701 fs/ocfs2/cluster/heartbeat.c if (!reg->hr_slot_data) reg 1704 fs/ocfs2/cluster/heartbeat.c for(i = 0; i < reg->hr_num_pages; i++) { reg 1709 fs/ocfs2/cluster/heartbeat.c reg->hr_slot_data[i] = page; reg 1714 fs/ocfs2/cluster/heartbeat.c (j < spp) && ((j + last_slot) < reg->hr_blocks); reg 1716 fs/ocfs2/cluster/heartbeat.c BUG_ON((j + last_slot) >= reg->hr_blocks); reg 1718 fs/ocfs2/cluster/heartbeat.c slot = ®->hr_slots[j + last_slot]; reg 1722 fs/ocfs2/cluster/heartbeat.c raw += reg->hr_block_bytes; reg 1732 fs/ocfs2/cluster/heartbeat.c static int o2hb_populate_slot_data(struct o2hb_region *reg) reg 1738 fs/ocfs2/cluster/heartbeat.c ret = o2hb_read_slots(reg, 0, reg->hr_blocks); reg 1746 fs/ocfs2/cluster/heartbeat.c for(i = 0; i < reg->hr_blocks; i++) { reg 1747 fs/ocfs2/cluster/heartbeat.c slot = ®->hr_slots[i]; reg 1765 fs/ocfs2/cluster/heartbeat.c struct o2hb_region *reg = to_o2hb_region(item); reg 1775 fs/ocfs2/cluster/heartbeat.c if (reg->hr_bdev) reg 1794 fs/ocfs2/cluster/heartbeat.c if (reg->hr_blocks == 0 || reg->hr_start_block == 0 || reg 1795 fs/ocfs2/cluster/heartbeat.c reg->hr_block_bytes == 0) reg 1805 fs/ocfs2/cluster/heartbeat.c reg->hr_bdev = I_BDEV(f.file->f_mapping->host); reg 1806 fs/ocfs2/cluster/heartbeat.c ret = blkdev_get(reg->hr_bdev, FMODE_WRITE | FMODE_READ, NULL); reg 1808 fs/ocfs2/cluster/heartbeat.c reg->hr_bdev = NULL; reg 1813 fs/ocfs2/cluster/heartbeat.c bdevname(reg->hr_bdev, reg->hr_dev_name); reg 1815 fs/ocfs2/cluster/heartbeat.c sectsize = bdev_logical_block_size(reg->hr_bdev); reg 1816 fs/ocfs2/cluster/heartbeat.c if (sectsize != reg->hr_block_bytes) { reg 1819 fs/ocfs2/cluster/heartbeat.c reg->hr_block_bytes, sectsize); reg 1824 fs/ocfs2/cluster/heartbeat.c o2hb_init_region_params(reg); reg 1828 fs/ocfs2/cluster/heartbeat.c get_random_bytes(®->hr_generation, reg 1829 fs/ocfs2/cluster/heartbeat.c sizeof(reg->hr_generation)); reg 1830 fs/ocfs2/cluster/heartbeat.c } while (reg->hr_generation == 0); reg 1832 fs/ocfs2/cluster/heartbeat.c ret = o2hb_map_slot_data(reg); reg 1838 fs/ocfs2/cluster/heartbeat.c ret = o2hb_populate_slot_data(reg); reg 1844 fs/ocfs2/cluster/heartbeat.c INIT_DELAYED_WORK(®->hr_write_timeout_work, o2hb_write_timeout); reg 1845 fs/ocfs2/cluster/heartbeat.c INIT_DELAYED_WORK(®->hr_nego_timeout_work, o2hb_nego_timeout); reg 1863 fs/ocfs2/cluster/heartbeat.c atomic_set(®->hr_steady_iterations, live_threshold); reg 1865 fs/ocfs2/cluster/heartbeat.c atomic_set(®->hr_unsteady_iterations, (live_threshold * 3)); reg 1867 fs/ocfs2/cluster/heartbeat.c hb_task = kthread_run(o2hb_thread, reg, "o2hb-%s", reg 1868 fs/ocfs2/cluster/heartbeat.c reg->hr_item.ci_name); reg 1876 fs/ocfs2/cluster/heartbeat.c reg->hr_task = hb_task; reg 1880 fs/ocfs2/cluster/heartbeat.c atomic_read(®->hr_steady_iterations) == 0 || reg 1881 fs/ocfs2/cluster/heartbeat.c reg->hr_node_deleted); reg 1883 fs/ocfs2/cluster/heartbeat.c atomic_set(®->hr_steady_iterations, 0); reg 1884 fs/ocfs2/cluster/heartbeat.c reg->hr_aborted_start = 1; reg 1887 fs/ocfs2/cluster/heartbeat.c if (reg->hr_aborted_start) { reg 1892 fs/ocfs2/cluster/heartbeat.c if (reg->hr_node_deleted) { reg 1899 fs/ocfs2/cluster/heartbeat.c hb_task = reg->hr_task; reg 1901 fs/ocfs2/cluster/heartbeat.c set_bit(reg->hr_region_num, o2hb_live_region_bitmap); reg 1911 fs/ocfs2/cluster/heartbeat.c config_item_name(®->hr_item), reg->hr_dev_name); reg 1919 fs/ocfs2/cluster/heartbeat.c if (reg->hr_bdev) { reg 1920 fs/ocfs2/cluster/heartbeat.c blkdev_put(reg->hr_bdev, FMODE_READ|FMODE_WRITE); reg 1921 fs/ocfs2/cluster/heartbeat.c reg->hr_bdev = NULL; reg 1929 fs/ocfs2/cluster/heartbeat.c struct o2hb_region *reg = to_o2hb_region(item); reg 1933 fs/ocfs2/cluster/heartbeat.c if (reg->hr_task) reg 1934 fs/ocfs2/cluster/heartbeat.c pid = task_pid_nr(reg->hr_task); reg 1982 fs/ocfs2/cluster/heartbeat.c static void o2hb_debug_region_init(struct o2hb_region *reg, reg 1987 fs/ocfs2/cluster/heartbeat.c dir = debugfs_create_dir(config_item_name(®->hr_item), parent); reg 1988 fs/ocfs2/cluster/heartbeat.c reg->hr_debug_dir = dir; reg 1990 fs/ocfs2/cluster/heartbeat.c o2hb_debug_create(O2HB_DEBUG_LIVENODES, dir, &(reg->hr_db_livenodes), reg 1991 fs/ocfs2/cluster/heartbeat.c sizeof(*(reg->hr_db_livenodes)), reg 1993 fs/ocfs2/cluster/heartbeat.c sizeof(reg->hr_live_node_bitmap), O2NM_MAX_NODES, reg 1994 fs/ocfs2/cluster/heartbeat.c reg); reg 1996 fs/ocfs2/cluster/heartbeat.c o2hb_debug_create(O2HB_DEBUG_REGION_NUMBER, dir, &(reg->hr_db_regnum), reg 1997 fs/ocfs2/cluster/heartbeat.c sizeof(*(reg->hr_db_regnum)), reg 1998 fs/ocfs2/cluster/heartbeat.c O2HB_DB_TYPE_REGION_NUMBER, 0, O2NM_MAX_NODES, reg); reg 2001 fs/ocfs2/cluster/heartbeat.c &(reg->hr_db_elapsed_time), reg 2002 fs/ocfs2/cluster/heartbeat.c sizeof(*(reg->hr_db_elapsed_time)), reg 2003 fs/ocfs2/cluster/heartbeat.c O2HB_DB_TYPE_REGION_ELAPSED_TIME, 0, 0, reg); reg 2005 fs/ocfs2/cluster/heartbeat.c o2hb_debug_create(O2HB_DEBUG_REGION_PINNED, dir, &(reg->hr_db_pinned), reg 2006 fs/ocfs2/cluster/heartbeat.c sizeof(*(reg->hr_db_pinned)), reg 2007 fs/ocfs2/cluster/heartbeat.c O2HB_DB_TYPE_REGION_PINNED, 0, 0, reg); reg 2014 fs/ocfs2/cluster/heartbeat.c struct o2hb_region *reg = NULL; reg 2017 fs/ocfs2/cluster/heartbeat.c reg = kzalloc(sizeof(struct o2hb_region), GFP_KERNEL); reg 2018 fs/ocfs2/cluster/heartbeat.c if (reg == NULL) reg 2027 fs/ocfs2/cluster/heartbeat.c reg->hr_region_num = 0; reg 2029 fs/ocfs2/cluster/heartbeat.c reg->hr_region_num = find_first_zero_bit(o2hb_region_bitmap, reg 2031 fs/ocfs2/cluster/heartbeat.c if (reg->hr_region_num >= O2NM_MAX_REGIONS) { reg 2036 fs/ocfs2/cluster/heartbeat.c set_bit(reg->hr_region_num, o2hb_region_bitmap); reg 2038 fs/ocfs2/cluster/heartbeat.c list_add_tail(®->hr_all_item, &o2hb_all_regions); reg 2041 fs/ocfs2/cluster/heartbeat.c config_item_init_type_name(®->hr_item, name, &o2hb_region_type); reg 2047 fs/ocfs2/cluster/heartbeat.c reg->hr_key = crc32_le(reg->hr_region_num + O2NM_MAX_REGIONS, reg 2049 fs/ocfs2/cluster/heartbeat.c INIT_LIST_HEAD(®->hr_handler_list); reg 2050 fs/ocfs2/cluster/heartbeat.c ret = o2net_register_handler(O2HB_NEGO_TIMEOUT_MSG, reg->hr_key, reg 2053 fs/ocfs2/cluster/heartbeat.c reg, NULL, ®->hr_handler_list); reg 2057 fs/ocfs2/cluster/heartbeat.c ret = o2net_register_handler(O2HB_NEGO_APPROVE_MSG, reg->hr_key, reg 2060 fs/ocfs2/cluster/heartbeat.c reg, NULL, ®->hr_handler_list); reg 2064 fs/ocfs2/cluster/heartbeat.c o2hb_debug_region_init(reg, o2hb_debug_dir); reg 2066 fs/ocfs2/cluster/heartbeat.c return ®->hr_item; reg 2069 fs/ocfs2/cluster/heartbeat.c o2net_unregister_handler_list(®->hr_handler_list); reg 2071 fs/ocfs2/cluster/heartbeat.c kfree(reg); reg 2079 fs/ocfs2/cluster/heartbeat.c struct o2hb_region *reg = to_o2hb_region(item); reg 2084 fs/ocfs2/cluster/heartbeat.c hb_task = reg->hr_task; reg 2085 fs/ocfs2/cluster/heartbeat.c reg->hr_task = NULL; reg 2086 fs/ocfs2/cluster/heartbeat.c reg->hr_item_dropped = 1; reg 2094 fs/ocfs2/cluster/heartbeat.c clear_bit(reg->hr_region_num, o2hb_region_bitmap); reg 2095 fs/ocfs2/cluster/heartbeat.c clear_bit(reg->hr_region_num, o2hb_live_region_bitmap); reg 2096 fs/ocfs2/cluster/heartbeat.c if (test_bit(reg->hr_region_num, o2hb_quorum_region_bitmap)) reg 2098 fs/ocfs2/cluster/heartbeat.c clear_bit(reg->hr_region_num, o2hb_quorum_region_bitmap); reg 2101 fs/ocfs2/cluster/heartbeat.c ((atomic_read(®->hr_steady_iterations) == 0) ? reg 2103 fs/ocfs2/cluster/heartbeat.c reg->hr_dev_name); reg 2110 fs/ocfs2/cluster/heartbeat.c if (atomic_read(®->hr_steady_iterations) != 0) { reg 2111 fs/ocfs2/cluster/heartbeat.c reg->hr_aborted_start = 1; reg 2112 fs/ocfs2/cluster/heartbeat.c atomic_set(®->hr_steady_iterations, 0); reg 2275 fs/ocfs2/cluster/heartbeat.c struct o2hb_region *reg; reg 2280 fs/ocfs2/cluster/heartbeat.c list_for_each_entry(reg, &o2hb_all_regions, hr_all_item) { reg 2281 fs/ocfs2/cluster/heartbeat.c if (reg->hr_item_dropped) reg 2284 fs/ocfs2/cluster/heartbeat.c uuid = config_item_name(®->hr_item); reg 2293 fs/ocfs2/cluster/heartbeat.c if (reg->hr_item_pinned || reg->hr_item_dropped) reg 2297 fs/ocfs2/cluster/heartbeat.c ret = o2nm_depend_item(®->hr_item); reg 2300 fs/ocfs2/cluster/heartbeat.c reg->hr_item_pinned = 1; reg 2327 fs/ocfs2/cluster/heartbeat.c struct o2hb_region *reg; reg 2333 fs/ocfs2/cluster/heartbeat.c list_for_each_entry(reg, &o2hb_all_regions, hr_all_item) { reg 2334 fs/ocfs2/cluster/heartbeat.c if (reg->hr_item_dropped) reg 2337 fs/ocfs2/cluster/heartbeat.c uuid = config_item_name(®->hr_item); reg 2344 fs/ocfs2/cluster/heartbeat.c if (reg->hr_item_pinned) { reg 2346 fs/ocfs2/cluster/heartbeat.c o2nm_undepend_item(®->hr_item); reg 2347 fs/ocfs2/cluster/heartbeat.c reg->hr_item_pinned = 0; reg 2512 fs/ocfs2/cluster/heartbeat.c struct o2hb_region *reg; reg 2518 fs/ocfs2/cluster/heartbeat.c list_for_each_entry(reg, &o2hb_all_regions, hr_all_item) reg 2519 fs/ocfs2/cluster/heartbeat.c reg->hr_unclean_stop = 1; reg 2527 fs/ocfs2/cluster/heartbeat.c struct o2hb_region *reg; reg 2534 fs/ocfs2/cluster/heartbeat.c list_for_each_entry(reg, &o2hb_all_regions, hr_all_item) { reg 2535 fs/ocfs2/cluster/heartbeat.c if (reg->hr_item_dropped) reg 2538 fs/ocfs2/cluster/heartbeat.c mlog(0, "Region: %s\n", config_item_name(®->hr_item)); reg 2540 fs/ocfs2/cluster/heartbeat.c memcpy(p, config_item_name(®->hr_item), reg 133 fs/squashfs/inode.c struct squashfs_reg_inode *sqsh_ino = &squashfs_ino.reg; reg 400 fs/squashfs/squashfs_fs.h struct squashfs_reg_inode reg; reg 820 fs/xfs/xfs_log.c struct xfs_log_iovec reg = { reg 827 fs/xfs/xfs_log.c .lv_iovecp = ®, reg 1521 fs/xfs/xfs_log.c struct xfs_log_iovec reg = { reg 1528 fs/xfs/xfs_log.c .lv_iovecp = ®, reg 2412 fs/xfs/xfs_log.c struct xfs_log_iovec *reg; reg 2426 fs/xfs/xfs_log.c reg = &vecp[index]; reg 2427 fs/xfs/xfs_log.c ASSERT(reg->i_len % sizeof(int32_t) == 0); reg 2446 fs/xfs/xfs_log.c reg->i_len, reg 2462 fs/xfs/xfs_log.c memcpy(ptr, reg->i_addr + copy_off, copy_len); reg 297 include/acpi/acpiosxf.h u32 reg, u64 *value, u32 width); reg 303 include/acpi/acpiosxf.h u32 reg, u64 value, u32 width); reg 831 include/acpi/acpixf.h struct acpi_generic_address *reg)) reg 835 include/acpi/acpixf.h struct acpi_generic_address *reg)) reg 54 include/acpi/cppc_acpi.h struct cpc_reg reg; reg 143 include/acpi/cppc_acpi.h extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val); reg 144 include/acpi/cppc_acpi.h extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val); reg 276 include/acpi/processor.h struct acpi_power_register *reg); reg 289 include/acpi/processor.h *reg) reg 36 include/clocksource/timer-davinci.h struct resource reg; reg 255 include/clocksource/timer-ti-dm.h static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg, reg 259 include/clocksource/timer-ti-dm.h while (readl_relaxed(timer->pend) & (reg >> WPSHIFT)) reg 262 include/clocksource/timer-ti-dm.h return readl_relaxed(timer->func_base + (reg & 0xff)); reg 266 include/clocksource/timer-ti-dm.h u32 reg, u32 val, int posted) reg 269 include/clocksource/timer-ti-dm.h while (readl_relaxed(timer->pend) & (reg >> WPSHIFT)) reg 272 include/clocksource/timer-ti-dm.h writel_relaxed(val, timer->func_base + (reg & 0xff)); reg 49 include/kvm/arm_psci.h int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); reg 50 include/kvm/arm_psci.h int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); reg 368 include/kvm/arm_vgic.h void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1); reg 332 include/linux/atmel-ssc.h #define ssc_readl(base, reg) __raw_readl(base + SSC_##reg) reg 333 include/linux/atmel-ssc.h #define ssc_writel(base, reg, value) __raw_writel((value), base + SSC_##reg) reg 271 include/linux/bpf_verifier.h #define bpf_for_each_spilled_reg(iter, frame, reg) \ reg 272 include/linux/bpf_verifier.h for (iter = 0, reg = bpf_get_spilled_reg(iter, frame); \ reg 274 include/linux/bpf_verifier.h iter++, reg = bpf_get_spilled_reg(iter, frame)) reg 39 include/linux/can/rx-offload.h u64 reg); reg 77 include/linux/cb710.h int reg, uint32_t and, uint32_t xor); reg 376 include/linux/clk-provider.h void __iomem *reg; reg 391 include/linux/clk-provider.h void __iomem *reg, u8 bit_idx, reg 395 include/linux/clk-provider.h void __iomem *reg, u8 bit_idx, reg 448 include/linux/clk-provider.h void __iomem *reg; reg 488 include/linux/clk-provider.h void __iomem *reg, u8 shift, u8 width, reg 492 include/linux/clk-provider.h void __iomem *reg, u8 shift, u8 width, reg 496 include/linux/clk-provider.h void __iomem *reg, u8 shift, u8 width, reg 501 include/linux/clk-provider.h void __iomem *reg, u8 shift, u8 width, reg 538 include/linux/clk-provider.h void __iomem *reg; reg 561 include/linux/clk-provider.h void __iomem *reg, u8 shift, u8 width, reg 566 include/linux/clk-provider.h void __iomem *reg, u8 shift, u8 width, reg 572 include/linux/clk-provider.h void __iomem *reg, u8 shift, u32 mask, reg 577 include/linux/clk-provider.h void __iomem *reg, u8 shift, u32 mask, reg 643 include/linux/clk-provider.h void __iomem *reg; reg 665 include/linux/clk-provider.h void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, reg 669 include/linux/clk-provider.h void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, reg 699 include/linux/clk-provider.h void __iomem *reg; reg 231 include/linux/clk/ti.h u32 (*clk_readl)(const struct clk_omap_reg *reg); reg 232 include/linux/clk/ti.h void (*clk_writel)(u32 val, const struct clk_omap_reg *reg); reg 233 include/linux/clk/ti.h void (*clk_rmw)(u32 val, u32 mask, const struct clk_omap_reg *reg); reg 173 include/linux/cs5535.h void cs5535_gpio_set(unsigned offset, unsigned int reg); reg 174 include/linux/cs5535.h void cs5535_gpio_clear(unsigned offset, unsigned int reg); reg 175 include/linux/cs5535.h int cs5535_gpio_isset(unsigned offset, unsigned int reg); reg 212 include/linux/cs5535.h uint16_t reg); reg 213 include/linux/cs5535.h extern void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg, reg 52 include/linux/dm-region-hash.h void *dm_rh_region_context(struct dm_region *reg); reg 58 include/linux/dm-region-hash.h region_t dm_rh_get_region_key(struct dm_region *reg); reg 94 include/linux/dm-region-hash.h void dm_rh_recovery_end(struct dm_region *reg, int error); reg 32 include/linux/dm9000.h void (*inblk)(void __iomem *reg, void *data, int len); reg 33 include/linux/dm9000.h void (*outblk)(void __iomem *reg, void *data, int len); reg 34 include/linux/dm9000.h void (*dumpblk)(void __iomem *reg, int len); reg 48 include/linux/firmware/trusted_foundations.h static inline void tf_dummy_write_sec(unsigned long val, unsigned int reg) reg 263 include/linux/fsl/bestcomm/bestcomm_priv.h u16 reg; reg 264 include/linux/fsl/bestcomm/bestcomm_priv.h reg = in_be16(&bcom_eng->regs->tcr[task]); reg 265 include/linux/fsl/bestcomm/bestcomm_priv.h out_be16(&bcom_eng->regs->tcr[task], reg | TASK_ENABLE); reg 271 include/linux/fsl/bestcomm/bestcomm_priv.h u16 reg = in_be16(&bcom_eng->regs->tcr[task]); reg 272 include/linux/fsl/bestcomm/bestcomm_priv.h out_be16(&bcom_eng->regs->tcr[task], reg & ~TASK_ENABLE); reg 385 include/linux/gpio/driver.h unsigned long (*read_reg)(void __iomem *reg); reg 386 include/linux/gpio/driver.h void (*write_reg)(void __iomem *reg, unsigned long data); reg 8 include/linux/gpio/gpio-reg.h struct gpio_chip *gpio_reg_init(struct device *dev, void __iomem *reg, reg 227 include/linux/host1x.h int (*is_addr_reg)(struct device *dev, u32 class, u32 reg); reg 278 include/linux/hp_sdc.h hp_sdc_irqhook *timer, *reg, *hil, *pup, *cooked; reg 58 include/linux/i2c-algo-pca.h void (*write_byte) (void *data, int reg, int val); reg 59 include/linux/i2c-algo-pca.h int (*read_byte) (void *data, int reg); reg 1260 include/linux/ide.h u8 reg; /* byte pci reg holding the enable-bit */ reg 112 include/linux/iio/adc/ad_sigma_delta.h int ad_sd_write_reg(struct ad_sigma_delta *sigma_delta, unsigned int reg, reg 114 include/linux/iio/adc/ad_sigma_delta.h int ad_sd_read_reg(struct ad_sigma_delta *sigma_delta, unsigned int reg, reg 294 include/linux/iio/common/st_sensors.h unsigned reg, unsigned writeval, reg 455 include/linux/iio/iio.h unsigned reg, unsigned writeval, reg 16 include/linux/iio/imu/adis.h #define ADIS_WRITE_REG(reg) ((0x80 | (reg))) reg 17 include/linux/iio/imu/adis.h #define ADIS_READ_REG(reg) ((reg) & 0x7f) reg 78 include/linux/iio/imu/adis.h int adis_write_reg(struct adis *adis, unsigned int reg, reg 80 include/linux/iio/imu/adis.h int adis_read_reg(struct adis *adis, unsigned int reg, reg 89 include/linux/iio/imu/adis.h static inline int adis_write_reg_8(struct adis *adis, unsigned int reg, reg 92 include/linux/iio/imu/adis.h return adis_write_reg(adis, reg, val, 1); reg 101 include/linux/iio/imu/adis.h static inline int adis_write_reg_16(struct adis *adis, unsigned int reg, reg 104 include/linux/iio/imu/adis.h return adis_write_reg(adis, reg, val, 2); reg 113 include/linux/iio/imu/adis.h static inline int adis_write_reg_32(struct adis *adis, unsigned int reg, reg 116 include/linux/iio/imu/adis.h return adis_write_reg(adis, reg, val, 4); reg 125 include/linux/iio/imu/adis.h static inline int adis_read_reg_16(struct adis *adis, unsigned int reg, reg 131 include/linux/iio/imu/adis.h ret = adis_read_reg(adis, reg, &tmp, 2); reg 143 include/linux/iio/imu/adis.h static inline int adis_read_reg_32(struct adis *adis, unsigned int reg, reg 149 include/linux/iio/imu/adis.h ret = adis_read_reg(adis, reg, &tmp, 4); reg 291 include/linux/iio/imu/adis.h unsigned int reg, unsigned int writeval, unsigned int *readval); reg 289 include/linux/intel-iommu.h sts = op(iommu->reg + offset); \ reg 522 include/linux/intel-iommu.h void __iomem *reg; /* Pointer to hardware regs, virtual addr */ reg 93 include/linux/intel_rapl.h u64 reg; reg 91 include/linux/ioc3.h extern void ioc3_write_ireg(struct ioc3_driver_data *idd, uint32_t value, int reg); reg 157 include/linux/irqchip/arm-gic-v3.h #define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \ reg 158 include/linux/irqchip/arm-gic-v3.h (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT) reg 160 include/linux/irqchip/arm-gic-v3.h #define GIC_BASER_SHAREABILITY(reg, type) \ reg 161 include/linux/irqchip/arm-gic-v3.h (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT) reg 20 include/linux/irqchip/irq-davinci-aintc.h struct resource reg; reg 19 include/linux/irqchip/irq-davinci-cp-intc.h struct resource reg; reg 1127 include/linux/libata.h extern int sata_scr_read(struct ata_link *link, int reg, u32 *val); reg 1128 include/linux/libata.h extern int sata_scr_write(struct ata_link *link, int reg, u32 val); reg 1129 include/linux/libata.h extern int sata_scr_write_flush(struct ata_link *link, int reg, u32 val); reg 1147 include/linux/libata.h extern u32 ata_wait_register(struct ata_port *ap, void __iomem *reg, u32 mask, reg 1216 include/linux/libata.h unsigned int reg; /* PCI config register to read */ reg 255 include/linux/mdio.h u16 reg = 0; reg 258 include/linux/mdio.h reg |= MDIO_EEE_100TX; reg 260 include/linux/mdio.h reg |= MDIO_EEE_1000T; reg 262 include/linux/mdio.h reg |= MDIO_EEE_10GT; reg 264 include/linux/mdio.h reg |= MDIO_EEE_1000KX; reg 266 include/linux/mdio.h reg |= MDIO_EEE_10GKX4; reg 268 include/linux/mdio.h reg |= MDIO_EEE_10GKR; reg 270 include/linux/mdio.h return reg; reg 486 include/linux/memblock.h static inline unsigned long memblock_region_memory_base_pfn(const struct memblock_region *reg) reg 488 include/linux/memblock.h return PFN_UP(reg->base); reg 497 include/linux/memblock.h static inline unsigned long memblock_region_memory_end_pfn(const struct memblock_region *reg) reg 499 include/linux/memblock.h return PFN_DOWN(reg->base + reg->size); reg 508 include/linux/memblock.h static inline unsigned long memblock_region_reserved_base_pfn(const struct memblock_region *reg) reg 510 include/linux/memblock.h return PFN_DOWN(reg->base); reg 519 include/linux/memblock.h static inline unsigned long memblock_region_reserved_end_pfn(const struct memblock_region *reg) reg 521 include/linux/memblock.h return PFN_UP(reg->base + reg->size); reg 27 include/linux/mfd/abx500.h u8 reg; reg 307 include/linux/mfd/abx500.h int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg, reg 309 include/linux/mfd/abx500.h int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg, reg 328 include/linux/mfd/abx500.h u8 reg, u8 bitmask, u8 bitvalues); reg 13 include/linux/mfd/abx500/ab8500-sysctrl.h int ab8500_sysctrl_read(u16 reg, u8 *value); reg 14 include/linux/mfd/abx500/ab8500-sysctrl.h int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value); reg 18 include/linux/mfd/abx500/ab8500-sysctrl.h static inline int ab8500_sysctrl_read(u16 reg, u8 *value) reg 23 include/linux/mfd/abx500/ab8500-sysctrl.h static inline int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value) reg 30 include/linux/mfd/abx500/ab8500-sysctrl.h static inline int ab8500_sysctrl_set(u16 reg, u8 bits) reg 32 include/linux/mfd/abx500/ab8500-sysctrl.h return ab8500_sysctrl_write(reg, bits, bits); reg 35 include/linux/mfd/abx500/ab8500-sysctrl.h static inline int ab8500_sysctrl_clear(u16 reg, u8 bits) reg 37 include/linux/mfd/abx500/ab8500-sysctrl.h return ab8500_sysctrl_write(reg, bits, 0); reg 510 include/linux/mfd/abx500/ab8500.h extern int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); reg 287 include/linux/mfd/adp5520.h extern int adp5520_read(struct device *dev, int reg, uint8_t *val); reg 288 include/linux/mfd/adp5520.h extern int adp5520_write(struct device *dev, int reg, u8 val); reg 289 include/linux/mfd/adp5520.h extern int adp5520_clr_bits(struct device *dev, int reg, uint8_t bit_mask); reg 290 include/linux/mfd/adp5520.h extern int adp5520_set_bits(struct device *dev, int reg, uint8_t bit_mask); reg 386 include/linux/mfd/as3722.h static inline int as3722_read(struct as3722 *as3722, u32 reg, u32 *dest) reg 388 include/linux/mfd/as3722.h return regmap_read(as3722->regmap, reg, dest); reg 391 include/linux/mfd/as3722.h static inline int as3722_write(struct as3722 *as3722, u32 reg, u32 value) reg 393 include/linux/mfd/as3722.h return regmap_write(as3722->regmap, reg, value); reg 396 include/linux/mfd/as3722.h static inline int as3722_block_read(struct as3722 *as3722, u32 reg, reg 399 include/linux/mfd/as3722.h return regmap_bulk_read(as3722->regmap, reg, buf, count); reg 402 include/linux/mfd/as3722.h static inline int as3722_block_write(struct as3722 *as3722, u32 reg, reg 405 include/linux/mfd/as3722.h return regmap_bulk_write(as3722->regmap, reg, data, count); reg 408 include/linux/mfd/as3722.h static inline int as3722_update_bits(struct as3722 *as3722, u32 reg, reg 411 include/linux/mfd/as3722.h return regmap_update_bits(as3722->regmap, reg, mask, val); reg 61 include/linux/mfd/asic3.h #define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg) reg 62 include/linux/mfd/asic3.h #define ASIC3_GPIO_OFFSET(base, reg) \ reg 63 include/linux/mfd/asic3.h (ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg) reg 310 include/linux/mfd/asic3.h extern void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 val); reg 311 include/linux/mfd/asic3.h extern u32 asic3_read_register(struct asic3 *asic, unsigned int reg); reg 650 include/linux/mfd/axp20x.h unsigned int reg, unsigned int width) reg 655 include/linux/mfd/axp20x.h err = regmap_read(regmap, reg, ®_val); reg 661 include/linux/mfd/axp20x.h err = regmap_read(regmap, reg + 1, ®_val); reg 241 include/linux/mfd/da903x.h extern int da903x_write(struct device *dev, int reg, uint8_t val); reg 242 include/linux/mfd/da903x.h extern int da903x_writes(struct device *dev, int reg, int len, uint8_t *val); reg 243 include/linux/mfd/da903x.h extern int da903x_read(struct device *dev, int reg, uint8_t *val); reg 244 include/linux/mfd/da903x.h extern int da903x_reads(struct device *dev, int reg, int len, uint8_t *val); reg 245 include/linux/mfd/da903x.h extern int da903x_update(struct device *dev, int reg, uint8_t val, uint8_t mask); reg 246 include/linux/mfd/da903x.h extern int da903x_set_bits(struct device *dev, int reg, uint8_t bit_mask); reg 247 include/linux/mfd/da903x.h extern int da903x_clr_bits(struct device *dev, int reg, uint8_t bit_mask); reg 97 include/linux/mfd/da9052/da9052.h int (*fix_io) (struct da9052 *da9052, unsigned char reg); reg 105 include/linux/mfd/da9052/da9052.h static inline int da9052_reg_read(struct da9052 *da9052, unsigned char reg) reg 109 include/linux/mfd/da9052/da9052.h ret = regmap_read(da9052->regmap, reg, &val); reg 114 include/linux/mfd/da9052/da9052.h ret = da9052->fix_io(da9052, reg); reg 122 include/linux/mfd/da9052/da9052.h static inline int da9052_reg_write(struct da9052 *da9052, unsigned char reg, reg 127 include/linux/mfd/da9052/da9052.h ret = regmap_write(da9052->regmap, reg, val); reg 132 include/linux/mfd/da9052/da9052.h ret = da9052->fix_io(da9052, reg); reg 140 include/linux/mfd/da9052/da9052.h static inline int da9052_group_read(struct da9052 *da9052, unsigned char reg, reg 148 include/linux/mfd/da9052/da9052.h ret = regmap_read(da9052->regmap, reg + i, &tmp); reg 155 include/linux/mfd/da9052/da9052.h ret = da9052->fix_io(da9052, reg); reg 163 include/linux/mfd/da9052/da9052.h static inline int da9052_group_write(struct da9052 *da9052, unsigned char reg, reg 170 include/linux/mfd/da9052/da9052.h ret = regmap_write(da9052->regmap, reg + i, val[i]); reg 176 include/linux/mfd/da9052/da9052.h ret = da9052->fix_io(da9052, reg); reg 184 include/linux/mfd/da9052/da9052.h static inline int da9052_reg_update(struct da9052 *da9052, unsigned char reg, reg 190 include/linux/mfd/da9052/da9052.h ret = regmap_update_bits(da9052->regmap, reg, bit_mask, reg_val); reg 195 include/linux/mfd/da9052/da9052.h ret = da9052->fix_io(da9052, reg); reg 38 include/linux/mfd/da9055/core.h static inline int da9055_reg_read(struct da9055 *da9055, unsigned char reg) reg 42 include/linux/mfd/da9055/core.h ret = regmap_read(da9055->regmap, reg, &val); reg 49 include/linux/mfd/da9055/core.h static inline int da9055_reg_write(struct da9055 *da9055, unsigned char reg, reg 52 include/linux/mfd/da9055/core.h return regmap_write(da9055->regmap, reg, val); reg 55 include/linux/mfd/da9055/core.h static inline int da9055_group_read(struct da9055 *da9055, unsigned char reg, reg 58 include/linux/mfd/da9055/core.h return regmap_bulk_read(da9055->regmap, reg, val, reg_cnt); reg 61 include/linux/mfd/da9055/core.h static inline int da9055_group_write(struct da9055 *da9055, unsigned char reg, reg 64 include/linux/mfd/da9055/core.h return regmap_raw_write(da9055->regmap, reg, val, reg_cnt); reg 67 include/linux/mfd/da9055/core.h static inline int da9055_reg_update(struct da9055 *da9055, unsigned char reg, reg 71 include/linux/mfd/da9055/core.h return regmap_update_bits(da9055->regmap, reg, bit_mask, reg_val); reg 74 include/linux/mfd/da9150/core.h u8 da9150_reg_read(struct da9150 *da9150, u16 reg); reg 75 include/linux/mfd/da9150/core.h void da9150_reg_write(struct da9150 *da9150, u16 reg, u8 val); reg 76 include/linux/mfd/da9150/core.h void da9150_set_bits(struct da9150 *da9150, u16 reg, u8 mask, u8 val); reg 78 include/linux/mfd/da9150/core.h void da9150_bulk_read(struct da9150 *da9150, u16 reg, int count, u8 *buf); reg 79 include/linux/mfd/da9150/core.h void da9150_bulk_write(struct da9150 *da9150, u16 reg, int count, const u8 *buf); reg 509 include/linux/mfd/db8500-prcmu.h int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); reg 510 include/linux/mfd/db8500-prcmu.h int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); reg 543 include/linux/mfd/db8500-prcmu.h u32 db8500_prcmu_read(unsigned int reg); reg 544 include/linux/mfd/db8500-prcmu.h void db8500_prcmu_write(unsigned int reg, u32 value); reg 545 include/linux/mfd/db8500-prcmu.h void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value); reg 641 include/linux/mfd/db8500-prcmu.h static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) reg 646 include/linux/mfd/db8500-prcmu.h static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) reg 754 include/linux/mfd/db8500-prcmu.h static inline u32 db8500_prcmu_read(unsigned int reg) reg 759 include/linux/mfd/db8500-prcmu.h static inline void db8500_prcmu_write(unsigned int reg, u32 value) {} reg 761 include/linux/mfd/db8500-prcmu.h static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask, reg 256 include/linux/mfd/dbx500-prcmu.h int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); reg 257 include/linux/mfd/dbx500-prcmu.h int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); reg 258 include/linux/mfd/dbx500-prcmu.h int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size); reg 363 include/linux/mfd/dbx500-prcmu.h static inline u32 prcmu_read(unsigned int reg) reg 365 include/linux/mfd/dbx500-prcmu.h return db8500_prcmu_read(reg); reg 368 include/linux/mfd/dbx500-prcmu.h static inline void prcmu_write(unsigned int reg, u32 value) reg 370 include/linux/mfd/dbx500-prcmu.h db8500_prcmu_write(reg, value); reg 373 include/linux/mfd/dbx500-prcmu.h static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) reg 375 include/linux/mfd/dbx500-prcmu.h db8500_prcmu_write_masked(reg, mask, value); reg 421 include/linux/mfd/dbx500-prcmu.h static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) reg 426 include/linux/mfd/dbx500-prcmu.h static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) reg 431 include/linux/mfd/dbx500-prcmu.h static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, reg 560 include/linux/mfd/dbx500-prcmu.h static inline u32 prcmu_read(unsigned int reg) reg 565 include/linux/mfd/dbx500-prcmu.h static inline void prcmu_write(unsigned int reg, u32 value) {} reg 567 include/linux/mfd/dbx500-prcmu.h static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {} reg 571 include/linux/mfd/dbx500-prcmu.h static inline void prcmu_set(unsigned int reg, u32 bits) reg 573 include/linux/mfd/dbx500-prcmu.h prcmu_write_masked(reg, bits, bits); reg 576 include/linux/mfd/dbx500-prcmu.h static inline void prcmu_clear(unsigned int reg, u32 bits) reg 578 include/linux/mfd/dbx500-prcmu.h prcmu_write_masked(reg, bits, 0); reg 17 include/linux/mfd/dm355evm_msp.h extern int dm355evm_msp_write(u8 value, u8 reg); reg 18 include/linux/mfd/dm355evm_msp.h extern int dm355evm_msp_read(u8 reg); reg 18 include/linux/mfd/htc-pasic3.h extern void pasic3_write_register(struct device *dev, u32 reg, u8 val); reg 19 include/linux/mfd/htc-pasic3.h extern u8 pasic3_read_register(struct device *dev, u32 reg); reg 433 include/linux/mfd/intel_msic.h extern int intel_msic_reg_read(unsigned short reg, u8 *val); reg 434 include/linux/mfd/intel_msic.h extern int intel_msic_reg_write(unsigned short reg, u8 val); reg 435 include/linux/mfd/intel_msic.h extern int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask); reg 436 include/linux/mfd/intel_msic.h extern int intel_msic_bulk_read(unsigned short *reg, u8 *buf, size_t count); reg 437 include/linux/mfd/intel_msic.h extern int intel_msic_bulk_write(unsigned short *reg, u8 *buf, size_t count); reg 450 include/linux/mfd/intel_msic.h extern int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg, reg 96 include/linux/mfd/lm3533.h extern int lm3533_read(struct lm3533 *lm3533, u8 reg, u8 *val); reg 97 include/linux/mfd/lm3533.h extern int lm3533_write(struct lm3533 *lm3533, u8 reg, u8 val); reg 98 include/linux/mfd/lm3533.h extern int lm3533_update(struct lm3533 *lm3533, u8 reg, u8 val, u8 mask); reg 82 include/linux/mfd/lp3943.h u8 reg; reg 107 include/linux/mfd/lp3943.h int lp3943_read_byte(struct lp3943 *lp3943, u8 reg, u8 *read); reg 108 include/linux/mfd/lp3943.h int lp3943_write_byte(struct lp3943 *lp3943, u8 reg, u8 data); reg 109 include/linux/mfd/lp3943.h int lp3943_update_bits(struct lp3943 *lp3943, u8 reg, u8 mask, u8 data); reg 326 include/linux/mfd/lp8788.h int lp8788_read_byte(struct lp8788 *lp, u8 reg, u8 *data); reg 327 include/linux/mfd/lp8788.h int lp8788_read_multi_bytes(struct lp8788 *lp, u8 reg, u8 *data, size_t count); reg 328 include/linux/mfd/lp8788.h int lp8788_write_byte(struct lp8788 *lp, u8 reg, u8 data); reg 329 include/linux/mfd/lp8788.h int lp8788_update_bits(struct lp8788 *lp, u8 reg, u8 mask, u8 data); reg 442 include/linux/mfd/max14577-private.h static inline int max14577_read_reg(struct regmap *map, u8 reg, u8 *dest) reg 447 include/linux/mfd/max14577-private.h ret = regmap_read(map, reg, &val); reg 453 include/linux/mfd/max14577-private.h static inline int max14577_bulk_read(struct regmap *map, u8 reg, u8 *buf, reg 456 include/linux/mfd/max14577-private.h return regmap_bulk_read(map, reg, buf, count); reg 459 include/linux/mfd/max14577-private.h static inline int max14577_write_reg(struct regmap *map, u8 reg, u8 value) reg 461 include/linux/mfd/max14577-private.h return regmap_write(map, reg, value); reg 464 include/linux/mfd/max14577-private.h static inline int max14577_bulk_write(struct regmap *map, u8 reg, u8 *buf, reg 467 include/linux/mfd/max14577-private.h return regmap_bulk_write(map, reg, buf, count); reg 470 include/linux/mfd/max14577-private.h static inline int max14577_update_reg(struct regmap *map, u8 reg, u8 mask, reg 473 include/linux/mfd/max14577-private.h return regmap_update_bits(map, reg, mask, val); reg 403 include/linux/mfd/max8997-private.h extern int max8997_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest); reg 404 include/linux/mfd/max8997-private.h extern int max8997_bulk_read(struct i2c_client *i2c, u8 reg, int count, reg 406 include/linux/mfd/max8997-private.h extern int max8997_write_reg(struct i2c_client *i2c, u8 reg, u8 value); reg 407 include/linux/mfd/max8997-private.h extern int max8997_bulk_write(struct i2c_client *i2c, u8 reg, int count, reg 409 include/linux/mfd/max8997-private.h extern int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask); reg 161 include/linux/mfd/max8998-private.h extern int max8998_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest); reg 162 include/linux/mfd/max8998-private.h extern int max8998_bulk_read(struct i2c_client *i2c, u8 reg, int count, reg 164 include/linux/mfd/max8998-private.h extern int max8998_write_reg(struct i2c_client *i2c, u8 reg, u8 value); reg 165 include/linux/mfd/max8998-private.h extern int max8998_bulk_write(struct i2c_client *i2c, u8 reg, int count, reg 167 include/linux/mfd/max8998-private.h extern int max8998_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask); reg 3752 include/linux/mfd/palmas.h unsigned int reg, unsigned int *val) reg 3754 include/linux/mfd/palmas.h unsigned int addr = PALMAS_BASE_TO_REG(base, reg); reg 3761 include/linux/mfd/palmas.h unsigned int reg, unsigned int value) reg 3763 include/linux/mfd/palmas.h unsigned int addr = PALMAS_BASE_TO_REG(base, reg); reg 3770 include/linux/mfd/palmas.h unsigned int reg, const void *val, size_t val_count) reg 3772 include/linux/mfd/palmas.h unsigned int addr = PALMAS_BASE_TO_REG(base, reg); reg 3780 include/linux/mfd/palmas.h unsigned int reg, void *val, size_t val_count) reg 3782 include/linux/mfd/palmas.h unsigned int addr = PALMAS_BASE_TO_REG(base, reg); reg 3790 include/linux/mfd/palmas.h unsigned int reg, unsigned int mask, unsigned int val) reg 3792 include/linux/mfd/palmas.h unsigned int addr = PALMAS_BASE_TO_REG(base, reg); reg 61 include/linux/mfd/pcf50633/core.h int pcf50633_read_block(struct pcf50633 *, u8 reg, reg 63 include/linux/mfd/pcf50633/core.h int pcf50633_write_block(struct pcf50633 *pcf, u8 reg, reg 65 include/linux/mfd/pcf50633/core.h u8 pcf50633_reg_read(struct pcf50633 *, u8 reg); reg 66 include/linux/mfd/pcf50633/core.h int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val); reg 68 include/linux/mfd/pcf50633/core.h int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val); reg 69 include/linux/mfd/pcf50633/core.h int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits); reg 326 include/linux/mfd/rc5t583.h static inline int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val) reg 329 include/linux/mfd/rc5t583.h return regmap_write(rc5t583->regmap, reg, val); reg 332 include/linux/mfd/rc5t583.h static inline int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val) reg 337 include/linux/mfd/rc5t583.h ret = regmap_read(rc5t583->regmap, reg, &ival); reg 343 include/linux/mfd/rc5t583.h static inline int rc5t583_set_bits(struct device *dev, unsigned int reg, reg 347 include/linux/mfd/rc5t583.h return regmap_update_bits(rc5t583->regmap, reg, bit_mask, bit_mask); reg 350 include/linux/mfd/rc5t583.h static inline int rc5t583_clear_bits(struct device *dev, unsigned int reg, reg 354 include/linux/mfd/rc5t583.h return regmap_update_bits(rc5t583->regmap, reg, bit_mask, 0); reg 357 include/linux/mfd/rc5t583.h static inline int rc5t583_update(struct device *dev, unsigned int reg, reg 361 include/linux/mfd/rc5t583.h return regmap_update_bits(rc5t583->regmap, reg, mask, val); reg 37 include/linux/mfd/smsc.h static inline int smsc_read(struct device *child, unsigned int reg, reg 42 include/linux/mfd/smsc.h return regmap_read(smsc->regmap, reg, dest); reg 45 include/linux/mfd/smsc.h static inline int smsc_write(struct device *child, unsigned int reg, reg 50 include/linux/mfd/smsc.h return regmap_write(smsc->regmap, reg, value); reg 196 include/linux/mfd/sta2x11-mfd.h sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val) reg 198 include/linux/mfd/sta2x11-mfd.h return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apbreg); reg 229 include/linux/mfd/sta2x11-mfd.h u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val) reg 231 include/linux/mfd/sta2x11-mfd.h return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_sctl); reg 368 include/linux/mfd/sta2x11-mfd.h u32 sta2x11_apb_soc_regs_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val) reg 370 include/linux/mfd/sta2x11-mfd.h return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apb_soc_regs); reg 129 include/linux/mfd/stm32-timers.h enum stm32_timers_dmas id, u32 reg, reg 135 include/linux/mfd/stm32-timers.h u32 reg, reg 148 include/linux/mfd/stmpe.h extern int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 data); reg 149 include/linux/mfd/stmpe.h extern int stmpe_reg_read(struct stmpe *stmpe, u8 reg); reg 150 include/linux/mfd/stmpe.h extern int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, reg 152 include/linux/mfd/stmpe.h extern int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length, reg 154 include/linux/mfd/stmpe.h extern int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val); reg 125 include/linux/mfd/tc3589x.h extern int tc3589x_reg_write(struct tc3589x *tc3589x, u8 reg, u8 data); reg 126 include/linux/mfd/tc3589x.h extern int tc3589x_reg_read(struct tc3589x *tc3589x, u8 reg); reg 127 include/linux/mfd/tc3589x.h extern int tc3589x_block_read(struct tc3589x *tc3589x, u8 reg, u8 length, reg 129 include/linux/mfd/tc3589x.h extern int tc3589x_block_write(struct tc3589x *tc3589x, u8 reg, u8 length, reg 131 include/linux/mfd/tc3589x.h extern int tc3589x_set_bits(struct tc3589x *tc3589x, u8 reg, u8 mask, u8 val); reg 28 include/linux/mfd/tmio.h #define sd_config_write8(base, shift, reg, val) \ reg 29 include/linux/mfd/tmio.h tmio_iowrite8((val), (base) + ((reg) << (shift))) reg 30 include/linux/mfd/tmio.h #define sd_config_write16(base, shift, reg, val) \ reg 31 include/linux/mfd/tmio.h tmio_iowrite16((val), (base) + ((reg) << (shift))) reg 32 include/linux/mfd/tmio.h #define sd_config_write32(base, shift, reg, val) \ reg 34 include/linux/mfd/tmio.h tmio_iowrite16((val), (base) + ((reg) << (shift))); \ reg 35 include/linux/mfd/tmio.h tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \ reg 159 include/linux/mfd/tps6507x.h int (*read_dev)(struct tps6507x_dev *tps6507x, char reg, int size, reg 161 include/linux/mfd/tps6507x.h int (*write_dev)(struct tps6507x_dev *tps6507x, char reg, int size, reg 114 include/linux/mfd/tps65090.h static inline int tps65090_write(struct device *dev, int reg, uint8_t val) reg 118 include/linux/mfd/tps65090.h return regmap_write(tps->rmap, reg, val); reg 121 include/linux/mfd/tps65090.h static inline int tps65090_read(struct device *dev, int reg, uint8_t *val) reg 127 include/linux/mfd/tps65090.h ret = regmap_read(tps->rmap, reg, &temp_val); reg 133 include/linux/mfd/tps65090.h static inline int tps65090_set_bits(struct device *dev, int reg, reg 138 include/linux/mfd/tps65090.h return regmap_update_bits(tps->rmap, reg, BIT(bit_num), ~0u); reg 141 include/linux/mfd/tps65090.h static inline int tps65090_clr_bits(struct device *dev, int reg, reg 146 include/linux/mfd/tps65090.h return regmap_update_bits(tps->rmap, reg, BIT(bit_num), 0u); reg 280 include/linux/mfd/tps65217.h int tps65217_reg_read(struct tps65217 *tps, unsigned int reg, reg 282 include/linux/mfd/tps65217.h int tps65217_reg_write(struct tps65217 *tps, unsigned int reg, reg 284 include/linux/mfd/tps65217.h int tps65217_set_bits(struct tps65217 *tps, unsigned int reg, reg 286 include/linux/mfd/tps65217.h int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg, reg 274 include/linux/mfd/tps65218.h int tps65218_reg_write(struct tps65218 *tps, unsigned int reg, reg 276 include/linux/mfd/tps65218.h int tps65218_set_bits(struct tps65218 *tps, unsigned int reg, reg 278 include/linux/mfd/tps65218.h int tps65218_clear_bits(struct tps65218 *tps, unsigned int reg, reg 101 include/linux/mfd/tps6586x.h extern int tps6586x_write(struct device *dev, int reg, uint8_t val); reg 102 include/linux/mfd/tps6586x.h extern int tps6586x_writes(struct device *dev, int reg, int len, uint8_t *val); reg 103 include/linux/mfd/tps6586x.h extern int tps6586x_read(struct device *dev, int reg, uint8_t *val); reg 104 include/linux/mfd/tps6586x.h extern int tps6586x_reads(struct device *dev, int reg, int len, uint8_t *val); reg 105 include/linux/mfd/tps6586x.h extern int tps6586x_set_bits(struct device *dev, int reg, uint8_t bit_mask); reg 106 include/linux/mfd/tps6586x.h extern int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask); reg 107 include/linux/mfd/tps6586x.h extern int tps6586x_update(struct device *dev, int reg, uint8_t val, reg 916 include/linux/mfd/tps65910.h static inline int tps65910_reg_read(struct tps65910 *tps65910, u8 reg, reg 919 include/linux/mfd/tps65910.h return regmap_read(tps65910->regmap, reg, val); reg 922 include/linux/mfd/tps65910.h static inline int tps65910_reg_write(struct tps65910 *tps65910, u8 reg, reg 925 include/linux/mfd/tps65910.h return regmap_write(tps65910->regmap, reg, val); reg 928 include/linux/mfd/tps65910.h static inline int tps65910_reg_set_bits(struct tps65910 *tps65910, u8 reg, reg 931 include/linux/mfd/tps65910.h return regmap_update_bits(tps65910->regmap, reg, mask, mask); reg 934 include/linux/mfd/tps65910.h static inline int tps65910_reg_clear_bits(struct tps65910 *tps65910, u8 reg, reg 937 include/linux/mfd/tps65910.h return regmap_update_bits(tps65910->regmap, reg, mask, 0); reg 940 include/linux/mfd/tps65910.h static inline int tps65910_reg_update_bits(struct tps65910 *tps65910, u8 reg, reg 943 include/linux/mfd/tps65910.h return regmap_update_bits(tps65910->regmap, reg, mask, val); reg 548 include/linux/mfd/tps80031.h int reg, uint8_t val) reg 552 include/linux/mfd/tps80031.h return regmap_write(tps80031->regmap[sid], reg, val); reg 555 include/linux/mfd/tps80031.h static inline int tps80031_writes(struct device *dev, int sid, int reg, reg 560 include/linux/mfd/tps80031.h return regmap_bulk_write(tps80031->regmap[sid], reg, val, len); reg 564 include/linux/mfd/tps80031.h int reg, uint8_t *val) reg 570 include/linux/mfd/tps80031.h ret = regmap_read(tps80031->regmap[sid], reg, &ival); reg 572 include/linux/mfd/tps80031.h dev_err(dev, "failed reading from reg 0x%02x\n", reg); reg 581 include/linux/mfd/tps80031.h int reg, int len, uint8_t *val) reg 585 include/linux/mfd/tps80031.h return regmap_bulk_read(tps80031->regmap[sid], reg, val, len); reg 589 include/linux/mfd/tps80031.h int reg, uint8_t bit_mask) reg 593 include/linux/mfd/tps80031.h return regmap_update_bits(tps80031->regmap[sid], reg, reg 598 include/linux/mfd/tps80031.h int reg, uint8_t bit_mask) reg 602 include/linux/mfd/tps80031.h return regmap_update_bits(tps80031->regmap[sid], reg, bit_mask, 0); reg 606 include/linux/mfd/tps80031.h int reg, uint8_t val, uint8_t mask) reg 610 include/linux/mfd/tps80031.h return regmap_update_bits(tps80031->regmap[sid], reg, mask, val); reg 169 include/linux/mfd/twl.h int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); reg 170 include/linux/mfd/twl.h int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); reg 175 include/linux/mfd/twl.h static inline int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg) { reg 176 include/linux/mfd/twl.h return twl_i2c_write(mod_no, &val, reg, 1); reg 179 include/linux/mfd/twl.h static inline int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg) { reg 180 include/linux/mfd/twl.h return twl_i2c_read(mod_no, val, reg, 1); reg 183 include/linux/mfd/twl.h static inline int twl_i2c_write_u16(u8 mod_no, u16 val, u8 reg) { reg 185 include/linux/mfd/twl.h return twl_i2c_write(mod_no, (u8*) &val, reg, 2); reg 188 include/linux/mfd/twl.h static inline int twl_i2c_read_u16(u8 mod_no, u16 *val, u8 reg) { reg 190 include/linux/mfd/twl.h ret = twl_i2c_read(mod_no, (u8*) val, reg, 2); reg 235 include/linux/mfd/twl6040.h int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg); reg 236 include/linux/mfd/twl6040.h int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg, reg 238 include/linux/mfd/twl6040.h int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg, reg 240 include/linux/mfd/twl6040.h int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg, reg 209 include/linux/mfd/ucb1x00.h static inline void ucb1x00_reg_write(struct ucb1x00 *ucb, unsigned int reg, unsigned int val) reg 211 include/linux/mfd/ucb1x00.h mcp_reg_write(ucb->mcp, reg, val); reg 222 include/linux/mfd/ucb1x00.h static inline unsigned int ucb1x00_reg_read(struct ucb1x00 *ucb, unsigned int reg) reg 224 include/linux/mfd/ucb1x00.h return mcp_reg_read(ucb->mcp, reg); reg 405 include/linux/mfd/wm831x/core.h int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg); reg 406 include/linux/mfd/wm831x/core.h int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg, reg 410 include/linux/mfd/wm831x/core.h int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg, reg 412 include/linux/mfd/wm831x/core.h int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg, reg 645 include/linux/mfd/wm8350/core.h int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask); reg 646 include/linux/mfd/wm8350/core.h int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask); reg 647 include/linux/mfd/wm8350/core.h u16 wm8350_reg_read(struct wm8350 *wm8350, int reg); reg 648 include/linux/mfd/wm8350/core.h int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val); reg 651 include/linux/mfd/wm8350/core.h int wm8350_block_read(struct wm8350 *wm8350, int reg, int size, u16 *dest); reg 652 include/linux/mfd/wm8350/core.h int wm8350_block_write(struct wm8350 *wm8350, int reg, int size, u16 *src); reg 750 include/linux/mfd/wm8350/pmic.h int wm8350_register_regulator(struct wm8350 *wm8350, int reg, reg 24 include/linux/mfd/wm8400.h int wm8400_register_regulator(struct device *dev, int reg, reg 82 include/linux/mfd/wm8994/core.h static inline int wm8994_reg_read(struct wm8994 *wm8994, unsigned short reg) reg 87 include/linux/mfd/wm8994/core.h ret = regmap_read(wm8994->regmap, reg, &val); reg 95 include/linux/mfd/wm8994/core.h static inline int wm8994_reg_write(struct wm8994 *wm8994, unsigned short reg, reg 98 include/linux/mfd/wm8994/core.h return regmap_write(wm8994->regmap, reg, val); reg 101 include/linux/mfd/wm8994/core.h static inline int wm8994_bulk_read(struct wm8994 *wm8994, unsigned short reg, reg 104 include/linux/mfd/wm8994/core.h return regmap_bulk_read(wm8994->regmap, reg, buf, count); reg 107 include/linux/mfd/wm8994/core.h static inline int wm8994_bulk_write(struct wm8994 *wm8994, unsigned short reg, reg 110 include/linux/mfd/wm8994/core.h return regmap_raw_write(wm8994->regmap, reg, buf, count * sizeof(u16)); reg 113 include/linux/mfd/wm8994/core.h static inline int wm8994_set_bits(struct wm8994 *wm8994, unsigned short reg, reg 116 include/linux/mfd/wm8994/core.h return regmap_update_bits(wm8994->regmap, reg, mask, val); reg 734 include/linux/mlx4/device.h void __iomem *reg; reg 1267 include/linux/mlx5/device.h #define MLX5_CAP_PCAM_REG(mdev, reg) \ reg 1268 include/linux/mlx5/device.h MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg) reg 1270 include/linux/mlx5/device.h #define MLX5_CAP_MCAM_REG(mdev, reg) \ reg 1271 include/linux/mlx5/device.h MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg) reg 126 include/linux/mlx5/port.h #define MLX5_GET_ETH_PROTO(reg, out, ext, field) \ reg 127 include/linux/mlx5/port.h (ext ? MLX5_GET(reg, out, ext_##field) : \ reg 128 include/linux/mlx5/port.h MLX5_GET(reg, out, field)) reg 81 include/linux/mmc/sh_mmcif.h static inline u32 sh_mmcif_readl(void __iomem *addr, int reg) reg 83 include/linux/mmc/sh_mmcif.h return __raw_readl(addr + reg); reg 86 include/linux/mmc/sh_mmcif.h static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val) reg 88 include/linux/mmc/sh_mmcif.h __raw_writel(val, addr + reg); reg 81 include/linux/mtd/doc2000.h static inline u8 ReadDOC_(u32 __iomem *addr, unsigned long reg) reg 83 include/linux/mtd/doc2000.h return __raw_readl(addr + reg); reg 85 include/linux/mtd/doc2000.h static inline void WriteDOC_(u8 data, u32 __iomem *addr, unsigned long reg) reg 87 include/linux/mtd/doc2000.h __raw_writel(data, addr + reg); reg 92 include/linux/mtd/doc2000.h static inline u8 ReadDOC_(u16 __iomem *addr, unsigned long reg) reg 94 include/linux/mtd/doc2000.h return __raw_readw(addr + reg); reg 96 include/linux/mtd/doc2000.h static inline void WriteDOC_(u8 data, u16 __iomem *addr, unsigned long reg) reg 98 include/linux/mtd/doc2000.h __raw_writew(data, addr + reg); reg 103 include/linux/mtd/doc2000.h #define ReadDOC_(adr, reg) readb((void __iomem *)(adr) + (reg)) reg 104 include/linux/mtd/doc2000.h #define WriteDOC_(d, adr, reg) writeb(d, (void __iomem *)(adr) + (reg)) reg 114 include/linux/mtd/doc2000.h #define ReadDOC(adr, reg) ReadDOC_(adr,DoC_##reg) reg 115 include/linux/mtd/doc2000.h #define WriteDOC(d, adr, reg) WriteDOC_(d,adr,DoC_##reg) reg 18 include/linux/mtd/sh_flctl.h #define FLCMNCR(f) (f->reg + 0x0) reg 19 include/linux/mtd/sh_flctl.h #define FLCMDCR(f) (f->reg + 0x4) reg 20 include/linux/mtd/sh_flctl.h #define FLCMCDR(f) (f->reg + 0x8) reg 21 include/linux/mtd/sh_flctl.h #define FLADR(f) (f->reg + 0xC) reg 22 include/linux/mtd/sh_flctl.h #define FLADR2(f) (f->reg + 0x3C) reg 23 include/linux/mtd/sh_flctl.h #define FLDATAR(f) (f->reg + 0x10) reg 24 include/linux/mtd/sh_flctl.h #define FLDTCNTR(f) (f->reg + 0x14) reg 25 include/linux/mtd/sh_flctl.h #define FLINTDMACR(f) (f->reg + 0x18) reg 26 include/linux/mtd/sh_flctl.h #define FLBSYTMR(f) (f->reg + 0x1C) reg 27 include/linux/mtd/sh_flctl.h #define FLBSYCNT(f) (f->reg + 0x20) reg 28 include/linux/mtd/sh_flctl.h #define FLDTFIFO(f) (f->reg + 0x24) reg 29 include/linux/mtd/sh_flctl.h #define FLECFIFO(f) (f->reg + 0x28) reg 30 include/linux/mtd/sh_flctl.h #define FLTRCR(f) (f->reg + 0x2C) reg 31 include/linux/mtd/sh_flctl.h #define FLHOLDCR(f) (f->reg + 0x38) reg 32 include/linux/mtd/sh_flctl.h #define FL4ECCRESULT0(f) (f->reg + 0x80) reg 33 include/linux/mtd/sh_flctl.h #define FL4ECCRESULT1(f) (f->reg + 0x84) reg 34 include/linux/mtd/sh_flctl.h #define FL4ECCRESULT2(f) (f->reg + 0x88) reg 35 include/linux/mtd/sh_flctl.h #define FL4ECCRESULT3(f) (f->reg + 0x8C) reg 36 include/linux/mtd/sh_flctl.h #define FL4ECCCR(f) (f->reg + 0x90) reg 37 include/linux/mtd/sh_flctl.h #define FL4ECCCNT(f) (f->reg + 0x94) reg 38 include/linux/mtd/sh_flctl.h #define FLERRADR(f) (f->reg + 0x98) reg 137 include/linux/mtd/sh_flctl.h void __iomem *reg; reg 41 include/linux/mtd/spinand.h #define SPINAND_SET_FEATURE_OP(reg, valptr) \ reg 43 include/linux/mtd/spinand.h SPI_MEM_OP_ADDR(1, reg, 1), \ reg 47 include/linux/mtd/spinand.h #define SPINAND_GET_FEATURE_OP(reg, valptr) \ reg 49 include/linux/mtd/spinand.h SPI_MEM_OP_ADDR(1, reg, 1), \ reg 185 include/linux/netfilter.h int nf_register_net_hooks(struct net *net, const struct nf_hook_ops *reg, reg 187 include/linux/netfilter.h void nf_unregister_net_hooks(struct net *net, const struct nf_hook_ops *reg, reg 192 include/linux/netfilter.h int nf_register_sockopt(struct nf_sockopt_ops *reg); reg 193 include/linux/netfilter.h void nf_unregister_sockopt(struct nf_sockopt_ops *reg); reg 175 include/linux/node.h static inline void register_hugetlbfs_with_node(node_registration_func_t reg, reg 48 include/linux/of_graph.h const struct device_node *parent, int port_reg, int reg); reg 84 include/linux/of_graph.h const struct device_node *parent, int port_reg, int reg) reg 281 include/linux/omap-dma.h void (*dma_write)(u32 val, int reg, int lch); reg 282 include/linux/omap-dma.h u32 (*dma_read)(int reg, int lch); reg 709 include/linux/pci.h int reg, int len, u32 *val); reg 711 include/linux/pci.h int reg, int len, u32 val); reg 113 include/linux/perf_event.h unsigned int reg; /* register address or index */ reg 1964 include/linux/platform_data/cros_ec_commands.h uint8_t ctrl, reg, value; reg 1965 include/linux/platform_data/cros_ec_commands.h } reg; reg 1997 include/linux/platform_data/cros_ec_commands.h uint8_t reg; reg 4253 include/linux/platform_data/cros_ec_commands.h uint8_t reg; reg 4261 include/linux/platform_data/cros_ec_commands.h uint8_t reg; reg 4270 include/linux/platform_data/cros_ec_commands.h uint8_t reg; reg 36 include/linux/platform_data/i2c-mux-reg.h void __iomem *reg; reg 10 include/linux/platform_data/keypad-omap.h #define omap_readw(reg) 0 reg 11 include/linux/platform_data/keypad-omap.h #define omap_writew(val, reg) do {} while (0) reg 86 include/linux/platform_data/mlxreg.h u32 reg; reg 113 include/linux/platform_data/mlxreg.h u32 reg; reg 37 include/linux/power/bq27xxx_battery.h int (*read)(struct bq27xxx_device_info *di, u8 reg, bool single); reg 38 include/linux/power/bq27xxx_battery.h int (*write)(struct bq27xxx_device_info *di, u8 reg, int value, bool single); reg 39 include/linux/power/bq27xxx_battery.h int (*read_bulk)(struct bq27xxx_device_info *di, u8 reg, u8 *data, int len); reg 40 include/linux/power/bq27xxx_battery.h int (*write_bulk)(struct bq27xxx_device_info *di, u8 reg, u8 *data, int len); reg 232 include/linux/pxa2xx_ssp.h static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val) reg 234 include/linux/pxa2xx_ssp.h __raw_writel(val, dev->mmio_base + reg); reg 243 include/linux/pxa2xx_ssp.h static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg) reg 245 include/linux/pxa2xx_ssp.h return __raw_readl(dev->mmio_base + reg); reg 54 include/linux/regmap.h unsigned int reg; reg 69 include/linux/regmap.h unsigned int reg; reg 74 include/linux/regmap.h #define regmap_update_bits(map, reg, mask, val) \ reg 75 include/linux/regmap.h regmap_update_bits_base(map, reg, mask, val, NULL, false, false) reg 76 include/linux/regmap.h #define regmap_update_bits_async(map, reg, mask, val)\ reg 77 include/linux/regmap.h regmap_update_bits_base(map, reg, mask, val, NULL, true, false) reg 78 include/linux/regmap.h #define regmap_update_bits_check(map, reg, mask, val, change)\ reg 79 include/linux/regmap.h regmap_update_bits_base(map, reg, mask, val, change, false, false) reg 80 include/linux/regmap.h #define regmap_update_bits_check_async(map, reg, mask, val, change)\ reg 81 include/linux/regmap.h regmap_update_bits_base(map, reg, mask, val, change, true, false) reg 83 include/linux/regmap.h #define regmap_write_bits(map, reg, mask, val) \ reg 84 include/linux/regmap.h regmap_update_bits_base(map, reg, mask, val, NULL, false, true) reg 360 include/linux/regmap.h bool (*writeable_reg)(struct device *dev, unsigned int reg); reg 361 include/linux/regmap.h bool (*readable_reg)(struct device *dev, unsigned int reg); reg 362 include/linux/regmap.h bool (*volatile_reg)(struct device *dev, unsigned int reg); reg 363 include/linux/regmap.h bool (*precious_reg)(struct device *dev, unsigned int reg); reg 364 include/linux/regmap.h bool (*writeable_noinc_reg)(struct device *dev, unsigned int reg); reg 365 include/linux/regmap.h bool (*readable_noinc_reg)(struct device *dev, unsigned int reg); reg 372 include/linux/regmap.h int (*reg_read)(void *context, unsigned int reg, unsigned int *val); reg 373 include/linux/regmap.h int (*reg_write)(void *context, unsigned int reg, unsigned int val); reg 451 include/linux/regmap.h const void *reg, size_t reg_len, reg 454 include/linux/regmap.h const void *reg, size_t reg_len, reg 460 include/linux/regmap.h typedef int (*regmap_hw_reg_read)(void *context, unsigned int reg, reg 462 include/linux/regmap.h typedef int (*regmap_hw_reg_write)(void *context, unsigned int reg, reg 464 include/linux/regmap.h typedef int (*regmap_hw_reg_update_bits)(void *context, unsigned int reg, reg 800 include/linux/regmap.h bool regmap_ac97_default_volatile(struct device *dev, unsigned int reg); reg 1009 include/linux/regmap.h int regmap_write(struct regmap *map, unsigned int reg, unsigned int val); reg 1010 include/linux/regmap.h int regmap_write_async(struct regmap *map, unsigned int reg, unsigned int val); reg 1011 include/linux/regmap.h int regmap_raw_write(struct regmap *map, unsigned int reg, reg 1013 include/linux/regmap.h int regmap_noinc_write(struct regmap *map, unsigned int reg, reg 1015 include/linux/regmap.h int regmap_bulk_write(struct regmap *map, unsigned int reg, const void *val, reg 1022 include/linux/regmap.h int regmap_raw_write_async(struct regmap *map, unsigned int reg, reg 1024 include/linux/regmap.h int regmap_read(struct regmap *map, unsigned int reg, unsigned int *val); reg 1025 include/linux/regmap.h int regmap_raw_read(struct regmap *map, unsigned int reg, reg 1027 include/linux/regmap.h int regmap_noinc_read(struct regmap *map, unsigned int reg, reg 1029 include/linux/regmap.h int regmap_bulk_read(struct regmap *map, unsigned int reg, void *val, reg 1031 include/linux/regmap.h int regmap_update_bits_base(struct regmap *map, unsigned int reg, reg 1051 include/linux/regmap.h bool regmap_check_range_table(struct regmap *map, unsigned int reg, reg 1059 include/linux/regmap.h static inline bool regmap_reg_in_range(unsigned int reg, reg 1062 include/linux/regmap.h return reg >= range->range_min && reg <= range->range_max; reg 1065 include/linux/regmap.h bool regmap_reg_in_ranges(unsigned int reg, reg 1079 include/linux/regmap.h unsigned int reg; reg 1087 include/linux/regmap.h .reg = _reg, \ reg 1290 include/linux/regmap.h static inline int regmap_write(struct regmap *map, unsigned int reg, reg 1297 include/linux/regmap.h static inline int regmap_write_async(struct regmap *map, unsigned int reg, reg 1304 include/linux/regmap.h static inline int regmap_raw_write(struct regmap *map, unsigned int reg, reg 1311 include/linux/regmap.h static inline int regmap_raw_write_async(struct regmap *map, unsigned int reg, reg 1318 include/linux/regmap.h static inline int regmap_noinc_write(struct regmap *map, unsigned int reg, reg 1325 include/linux/regmap.h static inline int regmap_bulk_write(struct regmap *map, unsigned int reg, reg 1332 include/linux/regmap.h static inline int regmap_read(struct regmap *map, unsigned int reg, reg 1339 include/linux/regmap.h static inline int regmap_raw_read(struct regmap *map, unsigned int reg, reg 1346 include/linux/regmap.h static inline int regmap_noinc_read(struct regmap *map, unsigned int reg, reg 1353 include/linux/regmap.h static inline int regmap_bulk_read(struct regmap *map, unsigned int reg, reg 1360 include/linux/regmap.h static inline int regmap_update_bits_base(struct regmap *map, unsigned int reg, reg 89 include/linux/rtsx_pci.h #define rtsx_pci_writel(pcr, reg, value) \ reg 90 include/linux/rtsx_pci.h iowrite32(value, (pcr)->remap_addr + reg) reg 91 include/linux/rtsx_pci.h #define rtsx_pci_readl(pcr, reg) \ reg 92 include/linux/rtsx_pci.h ioread32((pcr)->remap_addr + reg) reg 93 include/linux/rtsx_pci.h #define rtsx_pci_writew(pcr, reg, value) \ reg 94 include/linux/rtsx_pci.h iowrite16(value, (pcr)->remap_addr + reg) reg 95 include/linux/rtsx_pci.h #define rtsx_pci_readw(pcr, reg) \ reg 96 include/linux/rtsx_pci.h ioread16((pcr)->remap_addr + reg) reg 97 include/linux/rtsx_pci.h #define rtsx_pci_writeb(pcr, reg, value) \ reg 98 include/linux/rtsx_pci.h iowrite8(value, (pcr)->remap_addr + reg) reg 99 include/linux/rtsx_pci.h #define rtsx_pci_readb(pcr, reg) \ reg 100 include/linux/rtsx_pci.h ioread8((pcr)->remap_addr + reg) reg 1334 include/linux/rtsx_pci.h static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val) reg 1336 include/linux/rtsx_pci.h rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg, 0xFF, val >> 24); reg 1337 include/linux/rtsx_pci.h rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 1, 0xFF, val >> 16); reg 1338 include/linux/rtsx_pci.h rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 2, 0xFF, val >> 8); reg 1339 include/linux/rtsx_pci.h rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val); reg 412 include/linux/serial_core.h int uart_add_one_port(struct uart_driver *reg, struct uart_port *port); reg 413 include/linux/serial_core.h int uart_remove_one_port(struct uart_driver *reg, struct uart_port *port); reg 419 include/linux/serial_core.h int uart_suspend_port(struct uart_driver *reg, struct uart_port *port); reg 420 include/linux/serial_core.h int uart_resume_port(struct uart_driver *reg, struct uart_port *port); reg 42 include/linux/sh_intc.h unsigned long reg, reg_width; reg 67 include/linux/sh_intc.h unsigned long reg, reg_width, field_width; reg 72 include/linux/sh_intc.h #define INTC_SMP_BALANCING(reg) .dist_reg = (reg) reg 74 include/linux/sh_intc.h #define INTC_SMP_BALANCING(reg) reg 33 include/linux/sm501.h unsigned long reg, reg 5 include/linux/soc/brcmstb/brcmstb.h static inline u32 BRCM_ID(u32 reg) reg 7 include/linux/soc/brcmstb/brcmstb.h return reg >> 28 ? reg >> 16 : reg >> 8; reg 10 include/linux/soc/brcmstb/brcmstb.h static inline u32 BRCM_REV(u32 reg) reg 12 include/linux/soc/brcmstb/brcmstb.h return reg & 0xff; reg 18 include/linux/spi/max7301.h int (*write)(struct device *dev, unsigned int reg, unsigned int val); reg 19 include/linux/spi/max7301.h int (*read)(struct device *dev, unsigned int reg); reg 16 include/linux/ssbi.h ssbi_reg_read(void *context, unsigned int reg, unsigned int *val) reg 21 include/linux/ssbi.h ret = ssbi_read(context, reg, &v, 1); reg 29 include/linux/ssbi.h ssbi_reg_write(void *context, unsigned int reg, unsigned int val) reg 32 include/linux/ssbi.h return ssbi_write(context, reg, &v, 1); reg 57 include/linux/sungem_phy.h int (*mdio_read) (struct net_device *dev, int mii_id, int reg); reg 58 include/linux/sungem_phy.h void (*mdio_write) (struct net_device *dev, int mii_id, int reg, int val); reg 196 include/linux/trace_events.h int (*reg)(struct trace_event_call *event, reg 282 include/linux/tracepoint.h #define DEFINE_TRACE_FN(name, reg, unreg) \ reg 287 include/linux/tracepoint.h { __tpstrtab_##name, STATIC_KEY_INIT_FALSE, reg, unreg, NULL };\ reg 325 include/linux/tracepoint.h #define DEFINE_TRACE_FN(name, reg, unreg) reg 522 include/linux/tracepoint.h #define DEFINE_EVENT_FN(template, name, proto, args, reg, unreg)\ reg 534 include/linux/tracepoint.h assign, print, reg, unreg) \ reg 537 include/linux/tracepoint.h assign, print, reg, unreg) \ reg 112 include/linux/ucb1400.h static inline u16 ucb1400_reg_read(struct snd_ac97 *ac97, u16 reg) reg 114 include/linux/ucb1400.h return ac97->bus->ops->read(ac97, reg); reg 117 include/linux/ucb1400.h static inline void ucb1400_reg_write(struct snd_ac97 *ac97, u16 reg, u16 val) reg 119 include/linux/ucb1400.h ac97->bus->ops->write(ac97, reg, val); reg 73 include/linux/usb/phy.h int (*read)(struct usb_phy *x, u32 reg); reg 74 include/linux/usb/phy.h int (*write)(struct usb_phy *x, u32 val, u32 reg); reg 166 include/linux/usb/phy.h static inline int usb_phy_io_read(struct usb_phy *x, u32 reg) reg 169 include/linux/usb/phy.h return x->io_ops->read(x, reg); reg 174 include/linux/usb/phy.h static inline int usb_phy_io_write(struct usb_phy *x, u32 val, u32 reg) reg 177 include/linux/usb/phy.h return x->io_ops->write(x, val, reg); reg 328 include/linux/wm97xx.h int wm97xx_reg_read(struct wm97xx *wm, u16 reg); reg 329 include/linux/wm97xx.h void wm97xx_reg_write(struct wm97xx *wm, u16 reg, u16 val); reg 550 include/media/v4l2-ioctl.h struct v4l2_dbg_register *reg); reg 552 include/media/v4l2-ioctl.h const struct v4l2_dbg_register *reg); reg 202 include/media/v4l2-subdev.h int (*g_register)(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg); reg 203 include/media/v4l2-subdev.h int (*s_register)(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg); reg 3825 include/net/cfg80211.h u16 frame_type, bool reg); reg 195 include/net/netfilter/nf_tables.h static inline enum nft_data_types nft_dreg_to_type(enum nft_registers reg) reg 197 include/net/netfilter/nf_tables.h return reg == NFT_REG_VERDICT ? NFT_DATA_VERDICT : NFT_DATA_VALUE; reg 207 include/net/netfilter/nf_tables.h int nft_dump_register(struct sk_buff *skb, unsigned int attr, unsigned int reg); reg 209 include/net/netfilter/nf_tables.h int nft_validate_register_load(enum nft_registers reg, unsigned int len); reg 211 include/net/netfilter/nf_tables.h enum nft_registers reg, reg 38 include/net/netfilter/nft_fib.h void nft_fib_store_result(void *reg, const struct nft_fib *priv, reg 41 include/rdma/rw.h } *reg; reg 34 include/soc/arc/aux.h #define READ_BCR(reg, into) \ reg 37 include/soc/arc/aux.h tmp = read_aux_reg(reg); \ reg 46 include/soc/arc/aux.h #define WRITE_AUX(reg, into) \ reg 51 include/soc/arc/aux.h write_aux_reg(reg, tmp); \ reg 132 include/soc/at91/atmel_tcb.h #define ATMEL_TC_REG(idx, reg) (ATMEL_TC_CHAN(idx) + ATMEL_TC_ ## reg) reg 125 include/soc/nps/common.h blkid:6, reg:8, __reserved:2; reg 134 include/soc/nps/common.h u32 base:7, blkid:11, reg:12, __reserved:2; reg 140 include/soc/nps/common.h static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg) reg 146 include/soc/nps/common.h reg_address.reg = reg; reg 151 include/soc/nps/common.h static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg) reg 160 include/soc/nps/common.h reg_address.reg = reg; reg 18 include/soc/tegra/mc.h unsigned int reg; reg 30 include/soc/tegra/mc.h unsigned int reg; reg 50 include/soc/tegra/mc.h unsigned int reg; reg 58 include/sound/ac97/controller.h unsigned short reg, unsigned short val); reg 59 include/sound/ac97/controller.h int (*read)(struct ac97_controller *adrv, int slot, unsigned short reg); reg 192 include/sound/ac97_codec.h void (*write) (struct snd_ac97 *ac97, unsigned short reg, unsigned short val); reg 193 include/sound/ac97_codec.h unsigned short (*read) (struct snd_ac97 *ac97, unsigned short reg); reg 220 include/sound/ac97_codec.h unsigned short reg; /* register */ reg 320 include/sound/ac97_codec.h void snd_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short value); reg 321 include/sound/ac97_codec.h unsigned short snd_ac97_read(struct snd_ac97 *ac97, unsigned short reg); reg 322 include/sound/ac97_codec.h void snd_ac97_write_cache(struct snd_ac97 *ac97, unsigned short reg, unsigned short value); reg 323 include/sound/ac97_codec.h int snd_ac97_update(struct snd_ac97 *ac97, unsigned short reg, unsigned short value); reg 324 include/sound/ac97_codec.h int snd_ac97_update_bits(struct snd_ac97 *ac97, unsigned short reg, unsigned short mask, unsigned short value); reg 326 include/sound/ac97_codec.h int snd_ac97_update_power(struct snd_ac97 *ac97, int reg, int powerup); reg 328 include/sound/ac97_codec.h static inline int snd_ac97_update_power(struct snd_ac97 *ac97, int reg, reg 367 include/sound/ac97_codec.h int snd_ac97_set_rate(struct snd_ac97 *ac97, int reg, unsigned int rate); reg 15 include/sound/ad1843.h int (*read)(void *chip, int reg); reg 16 include/sound/ad1843.h int (*write)(void *chip, int reg, int val); reg 303 include/sound/ak4113.h void snd_ak4113_reg_write(struct ak4113 *ak4113, unsigned char reg, reg 185 include/sound/ak4114.h void snd_ak4114_reg_write(struct ak4114 *ak4114, unsigned char reg, unsigned char mask, unsigned char val); reg 172 include/sound/ak4117.h void snd_ak4117_reg_write(struct ak4117 *ak4117, unsigned char reg, unsigned char mask, unsigned char val); reg 53 include/sound/ak4531_codec.h void (*write) (struct snd_ak4531 *ak4531, unsigned short reg, reg 21 include/sound/ak4xxx-adda.h void (*write)(struct snd_akm4xxx *ak, int chip, unsigned char reg, reg 70 include/sound/ak4xxx-adda.h void snd_akm4xxx_write(struct snd_akm4xxx *ak, int chip, unsigned char reg, reg 76 include/sound/ak4xxx-adda.h #define snd_akm4xxx_get(ak,chip,reg) \ reg 77 include/sound/ak4xxx-adda.h (ak)->images[(chip) * 16 + (reg)] reg 78 include/sound/ak4xxx-adda.h #define snd_akm4xxx_set(ak,chip,reg,val) \ reg 79 include/sound/ak4xxx-adda.h ((ak)->images[(chip) * 16 + (reg)] = (val)) reg 80 include/sound/ak4xxx-adda.h #define snd_akm4xxx_get_vol(ak,chip,reg) \ reg 81 include/sound/ak4xxx-adda.h (ak)->volumes[(chip) * 16 + (reg)] reg 82 include/sound/ak4xxx-adda.h #define snd_akm4xxx_set_vol(ak,chip,reg,val) \ reg 83 include/sound/ak4xxx-adda.h ((ak)->volumes[(chip) * 16 + (reg)] = (val)) reg 142 include/sound/cs4231-regs.h #define CS4236_I23VAL(reg) ((((reg)&0xf) << 4) | (((reg)&0x10) >> 2) | 0x8) reg 179 include/sound/cs8427.h int snd_cs8427_reg_write(struct snd_i2c_device *device, unsigned char reg, reg 1823 include/sound/emu10k1.h unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); reg 1824 include/sound/emu10k1.h void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); reg 1825 include/sound/emu10k1.h unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); reg 1826 include/sound/emu10k1.h void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); reg 1828 include/sound/emu10k1.h int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value); reg 1829 include/sound/emu10k1.h int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, u32 reg, u32 value); reg 1830 include/sound/emu10k1.h int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, u32 reg, u32 *value); reg 1845 include/sound/emu10k1.h unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg); reg 1846 include/sound/emu10k1.h void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data); reg 90 include/sound/emu8000.h void snd_emu8000_poke(struct snd_emu8000 *emu, unsigned int port, unsigned int reg, reg 93 include/sound/emu8000.h unsigned int reg); reg 94 include/sound/emu8000.h void snd_emu8000_poke_dw(struct snd_emu8000 *emu, unsigned int port, unsigned int reg, reg 97 include/sound/emu8000.h unsigned int reg); reg 24 include/sound/emu8000_reg.h #define EMU8000_CMD(reg, chan) ((reg)<<5 | (chan)) reg 177 include/sound/emux_synth.h struct soundfont_voice_info reg; reg 93 include/sound/es1688.h void snd_es1688_mixer_write(struct snd_es1688 *chip, unsigned char reg, unsigned char data); reg 470 include/sound/gus.h extern void snd_gf1_ctrl_stop(struct snd_gus_card * gus, unsigned char reg); reg 472 include/sound/gus.h extern void snd_gf1_write8(struct snd_gus_card * gus, unsigned char reg, unsigned char data); reg 473 include/sound/gus.h extern unsigned char snd_gf1_look8(struct snd_gus_card * gus, unsigned char reg); reg 474 include/sound/gus.h static inline unsigned char snd_gf1_read8(struct snd_gus_card * gus, unsigned char reg) reg 476 include/sound/gus.h return snd_gf1_look8(gus, reg | 0x80); reg 478 include/sound/gus.h extern void snd_gf1_write16(struct snd_gus_card * gus, unsigned char reg, unsigned int data); reg 479 include/sound/gus.h extern unsigned short snd_gf1_look16(struct snd_gus_card * gus, unsigned char reg); reg 480 include/sound/gus.h static inline unsigned short snd_gf1_read16(struct snd_gus_card * gus, unsigned char reg) reg 482 include/sound/gus.h return snd_gf1_look16(gus, reg | 0x80); reg 484 include/sound/gus.h extern void snd_gf1_adlib_write(struct snd_gus_card * gus, unsigned char reg, unsigned char data); reg 488 include/sound/gus.h extern void snd_gf1_write_addr(struct snd_gus_card * gus, unsigned char reg, unsigned int addr, short w_16bit); reg 489 include/sound/gus.h extern unsigned int snd_gf1_read_addr(struct snd_gus_card * gus, unsigned char reg, short w_16bit); reg 490 include/sound/gus.h extern void snd_gf1_i_ctrl_stop(struct snd_gus_card * gus, unsigned char reg); reg 491 include/sound/gus.h extern void snd_gf1_i_write8(struct snd_gus_card * gus, unsigned char reg, unsigned char data); reg 492 include/sound/gus.h extern unsigned char snd_gf1_i_look8(struct snd_gus_card * gus, unsigned char reg); reg 493 include/sound/gus.h extern void snd_gf1_i_write16(struct snd_gus_card * gus, unsigned char reg, unsigned int data); reg 494 include/sound/gus.h static inline unsigned char snd_gf1_i_read8(struct snd_gus_card * gus, unsigned char reg) reg 496 include/sound/gus.h return snd_gf1_i_look8(gus, reg | 0x80); reg 498 include/sound/gus.h extern unsigned short snd_gf1_i_look16(struct snd_gus_card * gus, unsigned char reg); reg 499 include/sound/gus.h static inline unsigned short snd_gf1_i_read16(struct snd_gus_card * gus, unsigned char reg) reg 501 include/sound/gus.h return snd_gf1_i_look16(gus, reg | 0x80); reg 19 include/sound/hda_regmap.h int snd_hdac_regmap_read_raw(struct hdac_device *codec, unsigned int reg, reg 22 include/sound/hda_regmap.h unsigned int reg, unsigned int *val); reg 23 include/sound/hda_regmap.h int snd_hdac_regmap_write_raw(struct hdac_device *codec, unsigned int reg, reg 25 include/sound/hda_regmap.h int snd_hdac_regmap_update_raw(struct hdac_device *codec, unsigned int reg, reg 27 include/sound/hda_regmap.h int snd_hdac_regmap_update_raw_once(struct hdac_device *codec, unsigned int reg, reg 454 include/sound/hdaudio.h #define _snd_hdac_chip_writeb(chip, reg, value) \ reg 455 include/sound/hdaudio.h snd_hdac_reg_writeb(chip, (chip)->remap_addr + (reg), value) reg 456 include/sound/hdaudio.h #define _snd_hdac_chip_readb(chip, reg) \ reg 457 include/sound/hdaudio.h snd_hdac_reg_readb(chip, (chip)->remap_addr + (reg)) reg 458 include/sound/hdaudio.h #define _snd_hdac_chip_writew(chip, reg, value) \ reg 459 include/sound/hdaudio.h snd_hdac_reg_writew(chip, (chip)->remap_addr + (reg), value) reg 460 include/sound/hdaudio.h #define _snd_hdac_chip_readw(chip, reg) \ reg 461 include/sound/hdaudio.h snd_hdac_reg_readw(chip, (chip)->remap_addr + (reg)) reg 462 include/sound/hdaudio.h #define _snd_hdac_chip_writel(chip, reg, value) \ reg 463 include/sound/hdaudio.h snd_hdac_reg_writel(chip, (chip)->remap_addr + (reg), value) reg 464 include/sound/hdaudio.h #define _snd_hdac_chip_readl(chip, reg) \ reg 465 include/sound/hdaudio.h snd_hdac_reg_readl(chip, (chip)->remap_addr + (reg)) reg 468 include/sound/hdaudio.h #define snd_hdac_chip_writel(chip, reg, value) \ reg 469 include/sound/hdaudio.h _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value) reg 470 include/sound/hdaudio.h #define snd_hdac_chip_writew(chip, reg, value) \ reg 471 include/sound/hdaudio.h _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value) reg 472 include/sound/hdaudio.h #define snd_hdac_chip_writeb(chip, reg, value) \ reg 473 include/sound/hdaudio.h _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value) reg 474 include/sound/hdaudio.h #define snd_hdac_chip_readl(chip, reg) \ reg 475 include/sound/hdaudio.h _snd_hdac_chip_readl(chip, AZX_REG_ ## reg) reg 476 include/sound/hdaudio.h #define snd_hdac_chip_readw(chip, reg) \ reg 477 include/sound/hdaudio.h _snd_hdac_chip_readw(chip, AZX_REG_ ## reg) reg 478 include/sound/hdaudio.h #define snd_hdac_chip_readb(chip, reg) \ reg 479 include/sound/hdaudio.h _snd_hdac_chip_readb(chip, AZX_REG_ ## reg) reg 482 include/sound/hdaudio.h #define snd_hdac_chip_updatel(chip, reg, mask, val) \ reg 483 include/sound/hdaudio.h snd_hdac_chip_writel(chip, reg, \ reg 484 include/sound/hdaudio.h (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val)) reg 485 include/sound/hdaudio.h #define snd_hdac_chip_updatew(chip, reg, mask, val) \ reg 486 include/sound/hdaudio.h snd_hdac_chip_writew(chip, reg, \ reg 487 include/sound/hdaudio.h (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val)) reg 488 include/sound/hdaudio.h #define snd_hdac_chip_updateb(chip, reg, mask, val) \ reg 489 include/sound/hdaudio.h snd_hdac_chip_writeb(chip, reg, \ reg 490 include/sound/hdaudio.h (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val)) reg 560 include/sound/hdaudio.h unsigned int streams, unsigned int reg); reg 572 include/sound/hdaudio.h #define snd_hdac_stream_writel(dev, reg, value) \ reg 573 include/sound/hdaudio.h snd_hdac_reg_writel((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) reg 574 include/sound/hdaudio.h #define snd_hdac_stream_writew(dev, reg, value) \ reg 575 include/sound/hdaudio.h snd_hdac_reg_writew((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) reg 576 include/sound/hdaudio.h #define snd_hdac_stream_writeb(dev, reg, value) \ reg 577 include/sound/hdaudio.h snd_hdac_reg_writeb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) reg 578 include/sound/hdaudio.h #define snd_hdac_stream_readl(dev, reg) \ reg 579 include/sound/hdaudio.h snd_hdac_reg_readl((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) reg 580 include/sound/hdaudio.h #define snd_hdac_stream_readw(dev, reg) \ reg 581 include/sound/hdaudio.h snd_hdac_reg_readw((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) reg 582 include/sound/hdaudio.h #define snd_hdac_stream_readb(dev, reg) \ reg 583 include/sound/hdaudio.h snd_hdac_reg_readb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) reg 586 include/sound/hdaudio.h #define snd_hdac_stream_updatel(dev, reg, mask, val) \ reg 587 include/sound/hdaudio.h snd_hdac_stream_writel(dev, reg, \ reg 588 include/sound/hdaudio.h (snd_hdac_stream_readl(dev, reg) & \ reg 590 include/sound/hdaudio.h #define snd_hdac_stream_updatew(dev, reg, mask, val) \ reg 591 include/sound/hdaudio.h snd_hdac_stream_writew(dev, reg, \ reg 592 include/sound/hdaudio.h (snd_hdac_stream_readw(dev, reg) & \ reg 594 include/sound/hdaudio.h #define snd_hdac_stream_updateb(dev, reg, mask, val) \ reg 595 include/sound/hdaudio.h snd_hdac_stream_writeb(dev, reg, \ reg 596 include/sound/hdaudio.h (snd_hdac_stream_readb(dev, reg) & \ reg 135 include/sound/hdaudio_ext.h #define snd_hdac_updatel(addr, reg, mask, val) \ reg 136 include/sound/hdaudio_ext.h writel(((readl(addr + reg) & ~(mask)) | (val)), \ reg 137 include/sound/hdaudio_ext.h addr + reg) reg 139 include/sound/hdaudio_ext.h #define snd_hdac_updatew(addr, reg, mask, val) \ reg 140 include/sound/hdaudio_ext.h writew(((readw(addr + reg) & ~(mask)) | (val)), \ reg 141 include/sound/hdaudio_ext.h addr + reg) reg 71 include/sound/pcm_oss.h int reg; reg 31 include/sound/pxa2xx-lib.h extern int pxa2xx_ac97_read(int slot, unsigned short reg); reg 32 include/sound/pxa2xx-lib.h extern int pxa2xx_ac97_write(int slot, unsigned short reg, unsigned short val); reg 287 include/sound/sb.h void snd_sbmixer_write(struct snd_sb *chip, unsigned char reg, unsigned char data); reg 288 include/sound/sb.h unsigned char snd_sbmixer_read(struct snd_sb *chip, unsigned char reg); reg 326 include/sound/sb.h #define SB_MIXVAL_SINGLE(reg, shift, mask) \ reg 327 include/sound/sb.h ((reg) | ((shift) << 16) | ((mask) << 24)) reg 340 include/sound/sb.h #define SB_SINGLE(xname, reg, shift, mask) \ reg 343 include/sound/sb.h .private_value = SB_MIXVAL_SINGLE(reg, shift, mask) } reg 49 include/sound/soc-component.h unsigned int reg); reg 51 include/sound/soc-component.h unsigned int reg, unsigned int val); reg 258 include/sound/soc-component.h unsigned int reg, unsigned int *val); reg 260 include/sound/soc-component.h unsigned int reg); reg 262 include/sound/soc-component.h unsigned int reg, unsigned int val); reg 264 include/sound/soc-component.h unsigned int reg, unsigned int mask, reg 267 include/sound/soc-component.h unsigned int reg, unsigned int mask, reg 271 include/sound/soc-component.h unsigned int reg, unsigned int mask, reg 48 include/sound/soc-dapm.h .num_kcontrols = 0, .reg = SND_SOC_NOPM } reg 51 include/sound/soc-dapm.h .num_kcontrols = 0, .reg = SND_SOC_NOPM } reg 54 include/sound/soc-dapm.h .num_kcontrols = 0, .reg = SND_SOC_NOPM } reg 57 include/sound/soc-dapm.h .num_kcontrols = 0, .reg = SND_SOC_NOPM } reg 60 include/sound/soc-dapm.h .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ reg 64 include/sound/soc-dapm.h .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ reg 68 include/sound/soc-dapm.h .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ reg 72 include/sound/soc-dapm.h .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ reg 76 include/sound/soc-dapm.h .reg = wreg, .mask = 1, .shift = wshift, \ reg 209 include/sound/soc-dapm.h .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ reg 213 include/sound/soc-dapm.h .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ reg 252 include/sound/soc-dapm.h .reg = SND_SOC_NOPM, .event = dapm_clock_event, \ reg 258 include/sound/soc-dapm.h .reg = wreg, .shift = wshift, .mask = wmask, \ reg 266 include/sound/soc-dapm.h .reg = SND_SOC_NOPM, .shift = wdelay, .event = dapm_regulator_event, \ reg 273 include/sound/soc-dapm.h .reg = SND_SOC_NOPM, .event = dapm_pinctrl_event, \ reg 279 include/sound/soc-dapm.h #define SOC_DAPM_DOUBLE(xname, reg, lshift, rshift, max, invert) \ reg 283 include/sound/soc-dapm.h .private_value = SOC_DOUBLE_VALUE(reg, lshift, rshift, max, invert, 0) } reg 289 include/sound/soc-dapm.h #define SOC_DAPM_SINGLE(xname, reg, shift, max, invert) \ reg 293 include/sound/soc-dapm.h .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) } reg 294 include/sound/soc-dapm.h #define SOC_DAPM_SINGLE_AUTODISABLE(xname, reg, shift, max, invert) \ reg 298 include/sound/soc-dapm.h .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 1) } reg 301 include/sound/soc-dapm.h #define SOC_DAPM_SINGLE_TLV(xname, reg, shift, max, invert, tlv_array) \ reg 307 include/sound/soc-dapm.h .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) } reg 308 include/sound/soc-dapm.h #define SOC_DAPM_SINGLE_TLV_AUTODISABLE(xname, reg, shift, max, invert, tlv_array) \ reg 314 include/sound/soc-dapm.h .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 1) } reg 606 include/sound/soc-dapm.h int reg; /* negative reg = no direct dapm */ reg 651 include/sound/soc-dapm.h int reg; reg 33 include/sound/soc.h {.reg = xreg, .rreg = xreg, .shift = shift_left, \ reg 38 include/sound/soc.h {.reg = xreg, .rreg = xreg, .shift = shift_left, \ reg 45 include/sound/soc.h {.reg = xreg, .max = xmax, .platform_max = xmax, .invert = xinvert}) reg 48 include/sound/soc.h {.reg = xlreg, .rreg = xrreg, .shift = xshift, .rshift = xshift, \ reg 52 include/sound/soc.h {.reg = xlreg, .rreg = xrreg, .shift = xshift, .rshift = xshift, \ reg 57 include/sound/soc.h {.reg = xlreg, .rreg = xrreg, .shift = xshift, .rshift = xshift, \ reg 59 include/sound/soc.h #define SOC_SINGLE(xname, reg, shift, max, invert) \ reg 63 include/sound/soc.h .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) } reg 69 include/sound/soc.h {.reg = xreg, .rreg = xreg, .shift = xshift, \ reg 72 include/sound/soc.h #define SOC_SINGLE_TLV(xname, reg, shift, max, invert, tlv_array) \ reg 79 include/sound/soc.h .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) } reg 89 include/sound/soc.h {.reg = xreg, .rreg = xreg, \ reg 100 include/sound/soc.h {.reg = xreg, .rreg = xreg, .shift = xshift, \ reg 103 include/sound/soc.h #define SOC_DOUBLE(xname, reg, shift_left, shift_right, max, invert) \ reg 107 include/sound/soc.h .private_value = SOC_DOUBLE_VALUE(reg, shift_left, shift_right, \ reg 109 include/sound/soc.h #define SOC_DOUBLE_STS(xname, reg, shift_left, shift_right, max, invert) \ reg 115 include/sound/soc.h .private_value = SOC_DOUBLE_VALUE(reg, shift_left, shift_right, \ reg 130 include/sound/soc.h #define SOC_DOUBLE_TLV(xname, reg, shift_left, shift_right, max, invert, tlv_array) \ reg 137 include/sound/soc.h .private_value = SOC_DOUBLE_VALUE(reg, shift_left, shift_right, \ reg 167 include/sound/soc.h {.reg = xreg, .rreg = xrreg, \ reg 187 include/sound/soc.h {.reg = xreg, .rreg = xreg, \ reg 199 include/sound/soc.h { .reg = xreg, .shift_l = xshift_l, .shift_r = xshift_r, \ reg 207 include/sound/soc.h { .reg = xreg, .shift_l = xshift_l, .shift_r = xshift_r, \ reg 212 include/sound/soc.h { .reg = xreg, .shift_l = xshift, .shift_r = xshift, \ reg 228 include/sound/soc.h #define SOC_DOUBLE_EXT(xname, reg, shift_left, shift_right, max, invert,\ reg 234 include/sound/soc.h SOC_DOUBLE_VALUE(reg, shift_left, shift_right, max, invert, 0) } reg 260 include/sound/soc.h {.reg = xreg, .rreg = xreg, .shift = xshift, \ reg 1167 include/sound/soc.h int reg, rreg; reg 1200 include/sound/soc.h int reg; reg 1226 include/sound/soc.h if (mc->reg == mc->rreg && mc->shift == mc->rshift) reg 76 include/sound/vx_core.h unsigned char (*in8)(struct vx_core *chip, int reg); reg 77 include/sound/vx_core.h unsigned int (*in32)(struct vx_core *chip, int reg); reg 78 include/sound/vx_core.h void (*out8)(struct vx_core *chip, int reg, unsigned char val); reg 79 include/sound/vx_core.h void (*out32)(struct vx_core *chip, int reg, unsigned int val); reg 85 include/sound/vx_core.h void (*akm_write)(struct vx_core *chip, int reg, unsigned int data); reg 224 include/sound/vx_core.h static inline unsigned char snd_vx_inb(struct vx_core *chip, int reg) reg 226 include/sound/vx_core.h return chip->ops->in8(chip, reg); reg 229 include/sound/vx_core.h static inline unsigned int snd_vx_inl(struct vx_core *chip, int reg) reg 231 include/sound/vx_core.h return chip->ops->in32(chip, reg); reg 234 include/sound/vx_core.h static inline void snd_vx_outb(struct vx_core *chip, int reg, unsigned char val) reg 236 include/sound/vx_core.h chip->ops->out8(chip, reg, val); reg 239 include/sound/vx_core.h static inline void snd_vx_outl(struct vx_core *chip, int reg, unsigned int val) reg 241 include/sound/vx_core.h chip->ops->out32(chip, reg, val); reg 244 include/sound/vx_core.h #define vx_inb(chip,reg) snd_vx_inb(chip, VX_##reg) reg 245 include/sound/vx_core.h #define vx_outb(chip,reg,val) snd_vx_outb(chip, VX_##reg,val) reg 246 include/sound/vx_core.h #define vx_inl(chip,reg) snd_vx_inl(chip, VX_##reg) reg 247 include/sound/vx_core.h #define vx_outl(chip,reg,val) snd_vx_outl(chip, VX_##reg,val) reg 266 include/sound/vx_core.h int snd_vx_check_reg_bit(struct vx_core *chip, int reg, int mask, int bit, int time); reg 121 include/sound/wss.h void snd_wss_out(struct snd_wss *chip, unsigned char reg, unsigned char val); reg 122 include/sound/wss.h unsigned char snd_wss_in(struct snd_wss *chip, unsigned char reg); reg 124 include/sound/wss.h unsigned char reg, unsigned char val); reg 125 include/sound/wss.h unsigned char snd_cs4236_ext_in(struct snd_wss *chip, unsigned char reg); reg 162 include/sound/wss.h #define WSS_SINGLE(xname, xindex, reg, shift, mask, invert) \ reg 169 include/sound/wss.h .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } reg 188 include/sound/wss.h #define WSS_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \ reg 196 include/sound/wss.h .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \ reg 41 include/trace/define_trace.h assign, print, reg, unreg) \ reg 42 include/trace/define_trace.h DEFINE_TRACE_FN(name, reg, unreg) reg 46 include/trace/define_trace.h assign, print, reg, unreg) \ reg 47 include/trace/define_trace.h DEFINE_TRACE_FN(name, reg, unreg) reg 60 include/trace/define_trace.h #define DEFINE_EVENT_FN(template, name, proto, args, reg, unreg) \ reg 61 include/trace/define_trace.h DEFINE_TRACE_FN(name, reg, unreg) reg 126 include/trace/trace_events.h #define DEFINE_EVENT_FN(template, name, proto, args, reg, unreg) \ reg 136 include/trace/trace_events.h assign, print, reg, unreg) \ reg 142 include/trace/trace_events.h assign, print, reg, unreg) \ reg 768 include/trace/trace_events.h .reg = trace_event_reg, \ reg 276 include/uapi/drm/radeon_drm.h unsigned char cmd_type, reg, n_bufs, flags; reg 11 include/uapi/linux/adb.h #define ADB_WRITEREG(id, reg) (0x08 | (reg) | ((id) << 4)) reg 12 include/uapi/linux/adb.h #define ADB_READREG(id, reg) (0x0C | (reg) | ((id) << 4)) reg 79 include/uapi/linux/isst_if.h __u32 reg; reg 1165 include/uapi/linux/kvm.h __u64 reg[0]; reg 18 include/uapi/linux/phantom.h __u32 reg; reg 2374 include/uapi/linux/videodev2.h __u64 reg; reg 104 include/uapi/rdma/rdma_user_rxe.h } reg; reg 265 include/uapi/sound/asoc.h __le32 reg; reg 484 include/uapi/sound/asoc.h __le32 reg; /* negative reg = no direct dapm */ reg 49 include/video/broadsheetfb.h void (*write_reg)(struct broadsheetfb_par *, u16 reg, u16 val); reg 50 include/video/broadsheetfb.h u16 (*read_reg)(struct broadsheetfb_par *, u16 reg); reg 88 include/video/gbe.h #define GET_GBE_FIELD(reg, field, v) \ reg 89 include/video/gbe.h GET((v), GBE_##reg##_##field##_MSB, GBE_##reg##_##field##_LSB) reg 90 include/video/gbe.h #define SET_GBE_FIELD(reg, field, v, f) \ reg 91 include/video/gbe.h SET((v), (f), GBE_##reg##_##field##_MSB, GBE_##reg##_##field##_LSB) reg 212 include/video/vga.h static inline void vga_io_w_fast (unsigned short port, unsigned char reg, reg 215 include/video/vga.h outw(VGA_OUT16VAL (val, reg), port); reg 229 include/video/vga.h unsigned char reg, unsigned char val) reg 231 include/video/vga.h writew (VGA_OUT16VAL (val, reg), regbase + port); reg 252 include/video/vga.h unsigned char reg, unsigned char val) reg 255 include/video/vga.h vga_mm_w_fast (regbase, port, reg, val); reg 257 include/video/vga.h vga_io_w_fast (port, reg, val); reg 265 include/video/vga.h static inline unsigned char vga_rcrt (void __iomem *regbase, unsigned char reg) reg 267 include/video/vga.h vga_w (regbase, VGA_CRT_IC, reg); reg 271 include/video/vga.h static inline void vga_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val) reg 274 include/video/vga.h vga_w_fast (regbase, VGA_CRT_IC, reg, val); reg 276 include/video/vga.h vga_w (regbase, VGA_CRT_IC, reg); reg 281 include/video/vga.h static inline unsigned char vga_io_rcrt (unsigned char reg) reg 283 include/video/vga.h vga_io_w (VGA_CRT_IC, reg); reg 287 include/video/vga.h static inline void vga_io_wcrt (unsigned char reg, unsigned char val) reg 290 include/video/vga.h vga_io_w_fast (VGA_CRT_IC, reg, val); reg 292 include/video/vga.h vga_io_w (VGA_CRT_IC, reg); reg 297 include/video/vga.h static inline unsigned char vga_mm_rcrt (void __iomem *regbase, unsigned char reg) reg 299 include/video/vga.h vga_mm_w (regbase, VGA_CRT_IC, reg); reg 303 include/video/vga.h static inline void vga_mm_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val) reg 306 include/video/vga.h vga_mm_w_fast (regbase, VGA_CRT_IC, reg, val); reg 308 include/video/vga.h vga_mm_w (regbase, VGA_CRT_IC, reg); reg 318 include/video/vga.h static inline unsigned char vga_rseq (void __iomem *regbase, unsigned char reg) reg 320 include/video/vga.h vga_w (regbase, VGA_SEQ_I, reg); reg 324 include/video/vga.h static inline void vga_wseq (void __iomem *regbase, unsigned char reg, unsigned char val) reg 327 include/video/vga.h vga_w_fast (regbase, VGA_SEQ_I, reg, val); reg 329 include/video/vga.h vga_w (regbase, VGA_SEQ_I, reg); reg 334 include/video/vga.h static inline unsigned char vga_io_rseq (unsigned char reg) reg 336 include/video/vga.h vga_io_w (VGA_SEQ_I, reg); reg 340 include/video/vga.h static inline void vga_io_wseq (unsigned char reg, unsigned char val) reg 343 include/video/vga.h vga_io_w_fast (VGA_SEQ_I, reg, val); reg 345 include/video/vga.h vga_io_w (VGA_SEQ_I, reg); reg 350 include/video/vga.h static inline unsigned char vga_mm_rseq (void __iomem *regbase, unsigned char reg) reg 352 include/video/vga.h vga_mm_w (regbase, VGA_SEQ_I, reg); reg 356 include/video/vga.h static inline void vga_mm_wseq (void __iomem *regbase, unsigned char reg, unsigned char val) reg 359 include/video/vga.h vga_mm_w_fast (regbase, VGA_SEQ_I, reg, val); reg 361 include/video/vga.h vga_mm_w (regbase, VGA_SEQ_I, reg); reg 370 include/video/vga.h static inline unsigned char vga_rgfx (void __iomem *regbase, unsigned char reg) reg 372 include/video/vga.h vga_w (regbase, VGA_GFX_I, reg); reg 376 include/video/vga.h static inline void vga_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val) reg 379 include/video/vga.h vga_w_fast (regbase, VGA_GFX_I, reg, val); reg 381 include/video/vga.h vga_w (regbase, VGA_GFX_I, reg); reg 386 include/video/vga.h static inline unsigned char vga_io_rgfx (unsigned char reg) reg 388 include/video/vga.h vga_io_w (VGA_GFX_I, reg); reg 392 include/video/vga.h static inline void vga_io_wgfx (unsigned char reg, unsigned char val) reg 395 include/video/vga.h vga_io_w_fast (VGA_GFX_I, reg, val); reg 397 include/video/vga.h vga_io_w (VGA_GFX_I, reg); reg 402 include/video/vga.h static inline unsigned char vga_mm_rgfx (void __iomem *regbase, unsigned char reg) reg 404 include/video/vga.h vga_mm_w (regbase, VGA_GFX_I, reg); reg 408 include/video/vga.h static inline void vga_mm_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val) reg 411 include/video/vga.h vga_mm_w_fast (regbase, VGA_GFX_I, reg, val); reg 413 include/video/vga.h vga_mm_w (regbase, VGA_GFX_I, reg); reg 423 include/video/vga.h static inline unsigned char vga_rattr (void __iomem *regbase, unsigned char reg) reg 425 include/video/vga.h vga_w (regbase, VGA_ATT_IW, reg); reg 429 include/video/vga.h static inline void vga_wattr (void __iomem *regbase, unsigned char reg, unsigned char val) reg 431 include/video/vga.h vga_w (regbase, VGA_ATT_IW, reg); reg 435 include/video/vga.h static inline unsigned char vga_io_rattr (unsigned char reg) reg 437 include/video/vga.h vga_io_w (VGA_ATT_IW, reg); reg 441 include/video/vga.h static inline void vga_io_wattr (unsigned char reg, unsigned char val) reg 443 include/video/vga.h vga_io_w (VGA_ATT_IW, reg); reg 447 include/video/vga.h static inline unsigned char vga_mm_rattr (void __iomem *regbase, unsigned char reg) reg 449 include/video/vga.h vga_mm_w (regbase, VGA_ATT_IW, reg); reg 453 include/video/vga.h static inline void vga_mm_wattr (void __iomem *regbase, unsigned char reg, unsigned char val) reg 455 include/video/vga.h vga_mm_w (regbase, VGA_ATT_IW, reg); reg 112 include/xen/interface/physdev.h uint32_t reg; reg 71 include/xen/interface/platform.h uint32_t reg; reg 86 include/xen/interface/platform.h uint32_t reg; reg 94 include/xen/interface/platform.h uint32_t reg; reg 361 include/xen/interface/platform.h struct xen_power_register reg; /* GAS for Cx trigger register */ reg 108 include/xen/interface/xen-mca.h uint64_t reg; /* MSR */ reg 340 kernel/bpf/verifier.c static bool reg_may_point_to_spin_lock(const struct bpf_reg_state *reg) reg 342 kernel/bpf/verifier.c return reg->type == PTR_TO_MAP_VALUE && reg 343 kernel/bpf/verifier.c map_value_has_spin_lock(reg->map_ptr); reg 425 kernel/bpf/verifier.c const struct bpf_reg_state *reg) reg 429 kernel/bpf/verifier.c return cur->frame[reg->frameno]; reg 435 kernel/bpf/verifier.c const struct bpf_reg_state *reg; reg 442 kernel/bpf/verifier.c reg = &state->regs[i]; reg 443 kernel/bpf/verifier.c t = reg->type; reg 447 kernel/bpf/verifier.c print_liveness(env, reg->live); reg 449 kernel/bpf/verifier.c if (t == SCALAR_VALUE && reg->precise) reg 452 kernel/bpf/verifier.c tnum_is_const(reg->var_off)) { reg 454 kernel/bpf/verifier.c verbose(env, "%lld", reg->var_off.value + reg->off); reg 456 kernel/bpf/verifier.c verbose(env, "(id=%d", reg->id); reg 458 kernel/bpf/verifier.c verbose(env, ",ref_obj_id=%d", reg->ref_obj_id); reg 460 kernel/bpf/verifier.c verbose(env, ",off=%d", reg->off); reg 462 kernel/bpf/verifier.c verbose(env, ",r=%d", reg->range); reg 467 kernel/bpf/verifier.c reg->map_ptr->key_size, reg 468 kernel/bpf/verifier.c reg->map_ptr->value_size); reg 469 kernel/bpf/verifier.c if (tnum_is_const(reg->var_off)) { reg 474 kernel/bpf/verifier.c verbose(env, ",imm=%llx", reg->var_off.value); reg 476 kernel/bpf/verifier.c if (reg->smin_value != reg->umin_value && reg 477 kernel/bpf/verifier.c reg->smin_value != S64_MIN) reg 479 kernel/bpf/verifier.c (long long)reg->smin_value); reg 480 kernel/bpf/verifier.c if (reg->smax_value != reg->umax_value && reg 481 kernel/bpf/verifier.c reg->smax_value != S64_MAX) reg 483 kernel/bpf/verifier.c (long long)reg->smax_value); reg 484 kernel/bpf/verifier.c if (reg->umin_value != 0) reg 486 kernel/bpf/verifier.c (unsigned long long)reg->umin_value); reg 487 kernel/bpf/verifier.c if (reg->umax_value != U64_MAX) reg 489 kernel/bpf/verifier.c (unsigned long long)reg->umax_value); reg 490 kernel/bpf/verifier.c if (!tnum_is_unknown(reg->var_off)) { reg 493 kernel/bpf/verifier.c tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); reg 517 kernel/bpf/verifier.c reg = &state->stack[i].spilled_ptr; reg 518 kernel/bpf/verifier.c t = reg->type; reg 520 kernel/bpf/verifier.c if (t == SCALAR_VALUE && reg->precise) reg 522 kernel/bpf/verifier.c if (t == SCALAR_VALUE && tnum_is_const(reg->var_off)) reg 523 kernel/bpf/verifier.c verbose(env, "%lld", reg->var_off.value + reg->off); reg 855 kernel/bpf/verifier.c struct bpf_reg_state *reg); reg 860 kernel/bpf/verifier.c static void __mark_reg_known(struct bpf_reg_state *reg, u64 imm) reg 863 kernel/bpf/verifier.c memset(((u8 *)reg) + sizeof(reg->type), 0, reg 864 kernel/bpf/verifier.c offsetof(struct bpf_reg_state, var_off) - sizeof(reg->type)); reg 865 kernel/bpf/verifier.c reg->var_off = tnum_const(imm); reg 866 kernel/bpf/verifier.c reg->smin_value = (s64)imm; reg 867 kernel/bpf/verifier.c reg->smax_value = (s64)imm; reg 868 kernel/bpf/verifier.c reg->umin_value = imm; reg 869 kernel/bpf/verifier.c reg->umax_value = imm; reg 875 kernel/bpf/verifier.c static void __mark_reg_known_zero(struct bpf_reg_state *reg) reg 877 kernel/bpf/verifier.c __mark_reg_known(reg, 0); reg 880 kernel/bpf/verifier.c static void __mark_reg_const_zero(struct bpf_reg_state *reg) reg 882 kernel/bpf/verifier.c __mark_reg_known(reg, 0); reg 883 kernel/bpf/verifier.c reg->type = SCALAR_VALUE; reg 899 kernel/bpf/verifier.c static bool reg_is_pkt_pointer(const struct bpf_reg_state *reg) reg 901 kernel/bpf/verifier.c return type_is_pkt_pointer(reg->type); reg 904 kernel/bpf/verifier.c static bool reg_is_pkt_pointer_any(const struct bpf_reg_state *reg) reg 906 kernel/bpf/verifier.c return reg_is_pkt_pointer(reg) || reg 907 kernel/bpf/verifier.c reg->type == PTR_TO_PACKET_END; reg 911 kernel/bpf/verifier.c static bool reg_is_init_pkt_pointer(const struct bpf_reg_state *reg, reg 918 kernel/bpf/verifier.c return reg->type == which && reg 919 kernel/bpf/verifier.c reg->id == 0 && reg 920 kernel/bpf/verifier.c reg->off == 0 && reg 921 kernel/bpf/verifier.c tnum_equals_const(reg->var_off, 0); reg 925 kernel/bpf/verifier.c static void __update_reg_bounds(struct bpf_reg_state *reg) reg 928 kernel/bpf/verifier.c reg->smin_value = max_t(s64, reg->smin_value, reg 929 kernel/bpf/verifier.c reg->var_off.value | (reg->var_off.mask & S64_MIN)); reg 931 kernel/bpf/verifier.c reg->smax_value = min_t(s64, reg->smax_value, reg 932 kernel/bpf/verifier.c reg->var_off.value | (reg->var_off.mask & S64_MAX)); reg 933 kernel/bpf/verifier.c reg->umin_value = max(reg->umin_value, reg->var_off.value); reg 934 kernel/bpf/verifier.c reg->umax_value = min(reg->umax_value, reg 935 kernel/bpf/verifier.c reg->var_off.value | reg->var_off.mask); reg 939 kernel/bpf/verifier.c static void __reg_deduce_bounds(struct bpf_reg_state *reg) reg 946 kernel/bpf/verifier.c if (reg->smin_value >= 0 || reg->smax_value < 0) { reg 947 kernel/bpf/verifier.c reg->smin_value = reg->umin_value = max_t(u64, reg->smin_value, reg 948 kernel/bpf/verifier.c reg->umin_value); reg 949 kernel/bpf/verifier.c reg->smax_value = reg->umax_value = min_t(u64, reg->smax_value, reg 950 kernel/bpf/verifier.c reg->umax_value); reg 956 kernel/bpf/verifier.c if ((s64)reg->umax_value >= 0) { reg 960 kernel/bpf/verifier.c reg->smin_value = reg->umin_value; reg 961 kernel/bpf/verifier.c reg->smax_value = reg->umax_value = min_t(u64, reg->smax_value, reg 962 kernel/bpf/verifier.c reg->umax_value); reg 963 kernel/bpf/verifier.c } else if ((s64)reg->umin_value < 0) { reg 967 kernel/bpf/verifier.c reg->smin_value = reg->umin_value = max_t(u64, reg->smin_value, reg 968 kernel/bpf/verifier.c reg->umin_value); reg 969 kernel/bpf/verifier.c reg->smax_value = reg->umax_value; reg 974 kernel/bpf/verifier.c static void __reg_bound_offset(struct bpf_reg_state *reg) reg 976 kernel/bpf/verifier.c reg->var_off = tnum_intersect(reg->var_off, reg 977 kernel/bpf/verifier.c tnum_range(reg->umin_value, reg 978 kernel/bpf/verifier.c reg->umax_value)); reg 982 kernel/bpf/verifier.c static void __mark_reg_unbounded(struct bpf_reg_state *reg) reg 984 kernel/bpf/verifier.c reg->smin_value = S64_MIN; reg 985 kernel/bpf/verifier.c reg->smax_value = S64_MAX; reg 986 kernel/bpf/verifier.c reg->umin_value = 0; reg 987 kernel/bpf/verifier.c reg->umax_value = U64_MAX; reg 992 kernel/bpf/verifier.c struct bpf_reg_state *reg) reg 998 kernel/bpf/verifier.c memset(reg, 0, offsetof(struct bpf_reg_state, var_off)); reg 999 kernel/bpf/verifier.c reg->type = SCALAR_VALUE; reg 1000 kernel/bpf/verifier.c reg->var_off = tnum_unknown; reg 1001 kernel/bpf/verifier.c reg->frameno = 0; reg 1002 kernel/bpf/verifier.c reg->precise = env->subprog_cnt > 1 || !env->allow_ptr_leaks ? reg 1004 kernel/bpf/verifier.c __mark_reg_unbounded(reg); reg 1021 kernel/bpf/verifier.c struct bpf_reg_state *reg) reg 1023 kernel/bpf/verifier.c __mark_reg_unknown(env, reg); reg 1024 kernel/bpf/verifier.c reg->type = NOT_INIT; reg 1248 kernel/bpf/verifier.c u32 regno, struct bpf_reg_state *reg, enum reg_arg_type t) reg 1295 kernel/bpf/verifier.c if (reg->type != SCALAR_VALUE) reg 1346 kernel/bpf/verifier.c struct bpf_reg_state *reg) reg 1348 kernel/bpf/verifier.c s32 def_idx = reg->subreg_def; reg 1355 kernel/bpf/verifier.c reg->subreg_def = DEF_NOT_SUBREG; reg 1364 kernel/bpf/verifier.c struct bpf_reg_state *reg, *regs = state->regs; reg 1372 kernel/bpf/verifier.c reg = ®s[regno]; reg 1373 kernel/bpf/verifier.c rw64 = is_reg64(env, insn, regno, reg, t); reg 1376 kernel/bpf/verifier.c if (reg->type == NOT_INIT) { reg 1385 kernel/bpf/verifier.c mark_insn_zext(env, reg); reg 1387 kernel/bpf/verifier.c return mark_reg_read(env, reg, reg->parent, reg 1395 kernel/bpf/verifier.c reg->live |= REG_LIVE_WRITTEN; reg 1396 kernel/bpf/verifier.c reg->subreg_def = rw64 ? DEF_NOT_SUBREG : env->insn_idx + 1; reg 1634 kernel/bpf/verifier.c struct bpf_reg_state *reg; reg 1644 kernel/bpf/verifier.c reg = &func->regs[j]; reg 1645 kernel/bpf/verifier.c if (reg->type != SCALAR_VALUE) reg 1647 kernel/bpf/verifier.c reg->precise = true; reg 1652 kernel/bpf/verifier.c reg = &func->stack[j].spilled_ptr; reg 1653 kernel/bpf/verifier.c if (reg->type != SCALAR_VALUE) reg 1655 kernel/bpf/verifier.c reg->precise = true; reg 1667 kernel/bpf/verifier.c struct bpf_reg_state *reg; reg 1680 kernel/bpf/verifier.c reg = &func->regs[regno]; reg 1681 kernel/bpf/verifier.c if (reg->type != SCALAR_VALUE) { reg 1685 kernel/bpf/verifier.c if (!reg->precise) reg 1689 kernel/bpf/verifier.c reg->precise = true; reg 1697 kernel/bpf/verifier.c reg = &func->stack[spi].spilled_ptr; reg 1698 kernel/bpf/verifier.c if (reg->type != SCALAR_VALUE) { reg 1702 kernel/bpf/verifier.c if (!reg->precise) reg 1706 kernel/bpf/verifier.c reg->precise = true; reg 1762 kernel/bpf/verifier.c reg = &func->regs[i]; reg 1763 kernel/bpf/verifier.c if (reg->type != SCALAR_VALUE) { reg 1767 kernel/bpf/verifier.c if (!reg->precise) reg 1769 kernel/bpf/verifier.c reg->precise = true; reg 1796 kernel/bpf/verifier.c reg = &func->stack[i].spilled_ptr; reg 1797 kernel/bpf/verifier.c if (reg->type != SCALAR_VALUE) { reg 1801 kernel/bpf/verifier.c if (!reg->precise) reg 1803 kernel/bpf/verifier.c reg->precise = true; reg 1859 kernel/bpf/verifier.c static bool register_is_null(struct bpf_reg_state *reg) reg 1861 kernel/bpf/verifier.c return reg->type == SCALAR_VALUE && tnum_equals_const(reg->var_off, 0); reg 1864 kernel/bpf/verifier.c static bool register_is_const(struct bpf_reg_state *reg) reg 1866 kernel/bpf/verifier.c return reg->type == SCALAR_VALUE && tnum_is_const(reg->var_off); reg 1870 kernel/bpf/verifier.c const struct bpf_reg_state *reg) reg 1875 kernel/bpf/verifier.c return reg->type != SCALAR_VALUE; reg 1879 kernel/bpf/verifier.c int spi, struct bpf_reg_state *reg) reg 1883 kernel/bpf/verifier.c state->stack[spi].spilled_ptr = *reg; reg 1900 kernel/bpf/verifier.c struct bpf_reg_state *reg = NULL; reg 1918 kernel/bpf/verifier.c reg = &cur->regs[value_regno]; reg 1920 kernel/bpf/verifier.c if (reg && size == BPF_REG_SIZE && register_is_const(reg) && reg 1921 kernel/bpf/verifier.c !register_is_null(reg) && env->allow_ptr_leaks) { reg 1933 kernel/bpf/verifier.c save_register_state(state, spi, reg); reg 1934 kernel/bpf/verifier.c } else if (reg && is_spillable_regtype(reg->type)) { reg 1942 kernel/bpf/verifier.c if (state != cur && reg->type == PTR_TO_STACK) { reg 1982 kernel/bpf/verifier.c save_register_state(state, spi, reg); reg 2005 kernel/bpf/verifier.c if (reg && register_is_null(reg)) { reg 2028 kernel/bpf/verifier.c struct bpf_reg_state *reg; reg 2037 kernel/bpf/verifier.c reg = ®_state->stack[spi].spilled_ptr; reg 2041 kernel/bpf/verifier.c if (reg->type != SCALAR_VALUE) { reg 2050 kernel/bpf/verifier.c mark_reg_read(env, reg, reg->parent, REG_LIVE_READ64); reg 2062 kernel/bpf/verifier.c state->regs[value_regno] = *reg; reg 2068 kernel/bpf/verifier.c } else if (__is_pointer_value(env->allow_ptr_leaks, reg)) { reg 2079 kernel/bpf/verifier.c mark_reg_read(env, reg, reg->parent, REG_LIVE_READ64); reg 2094 kernel/bpf/verifier.c mark_reg_read(env, reg, reg->parent, REG_LIVE_READ64); reg 2123 kernel/bpf/verifier.c const struct bpf_reg_state *reg, reg 2130 kernel/bpf/verifier.c if (!tnum_is_const(reg->var_off)) { reg 2133 kernel/bpf/verifier.c tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); reg 2191 kernel/bpf/verifier.c struct bpf_reg_state *reg = &state->regs[regno]; reg 2207 kernel/bpf/verifier.c if (reg->smin_value < 0 && reg 2208 kernel/bpf/verifier.c (reg->smin_value == S64_MIN || reg 2209 kernel/bpf/verifier.c (off + reg->smin_value != (s64)(s32)(off + reg->smin_value)) || reg 2210 kernel/bpf/verifier.c reg->smin_value + off < 0)) { reg 2215 kernel/bpf/verifier.c err = __check_map_access(env, regno, reg->smin_value + off, size, reg 2227 kernel/bpf/verifier.c if (reg->umax_value >= BPF_MAX_VAR_OFF) { reg 2232 kernel/bpf/verifier.c err = __check_map_access(env, regno, reg->umax_value + off, size, reg 2238 kernel/bpf/verifier.c if (map_value_has_spin_lock(reg->map_ptr)) { reg 2239 kernel/bpf/verifier.c u32 lock = reg->map_ptr->spin_lock_off; reg 2246 kernel/bpf/verifier.c if (reg->smin_value + off < lock + sizeof(struct bpf_spin_lock) && reg 2247 kernel/bpf/verifier.c lock < reg->umax_value + off + size) { reg 2301 kernel/bpf/verifier.c struct bpf_reg_state *reg = ®s[regno]; reg 2304 kernel/bpf/verifier.c (u64)off + size > reg->range) { reg 2306 kernel/bpf/verifier.c off, size, regno, reg->id, reg->off, reg->range); reg 2316 kernel/bpf/verifier.c struct bpf_reg_state *reg = ®s[regno]; reg 2327 kernel/bpf/verifier.c if (reg->smin_value < 0) { reg 2346 kernel/bpf/verifier.c off + reg->umax_value + size - 1); reg 2398 kernel/bpf/verifier.c struct bpf_reg_state *reg = ®s[regno]; reg 2402 kernel/bpf/verifier.c if (reg->smin_value < 0) { reg 2408 kernel/bpf/verifier.c switch (reg->type) { reg 2433 kernel/bpf/verifier.c regno, reg_type_str[reg->type], off, size); reg 2450 kernel/bpf/verifier.c const struct bpf_reg_state *reg = reg_state(env, regno); reg 2452 kernel/bpf/verifier.c return reg->type == PTR_TO_CTX; reg 2457 kernel/bpf/verifier.c const struct bpf_reg_state *reg = reg_state(env, regno); reg 2459 kernel/bpf/verifier.c return type_is_sk_pointer(reg->type); reg 2464 kernel/bpf/verifier.c const struct bpf_reg_state *reg = reg_state(env, regno); reg 2466 kernel/bpf/verifier.c return type_is_pkt_pointer(reg->type); reg 2471 kernel/bpf/verifier.c const struct bpf_reg_state *reg = reg_state(env, regno); reg 2474 kernel/bpf/verifier.c return reg->type == PTR_TO_FLOW_KEYS; reg 2478 kernel/bpf/verifier.c const struct bpf_reg_state *reg, reg 2498 kernel/bpf/verifier.c reg_off = tnum_add(reg->var_off, tnum_const(ip_align + reg->off + off)); reg 2502 kernel/bpf/verifier.c tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); reg 2505 kernel/bpf/verifier.c ip_align, tn_buf, reg->off, off, size); reg 2513 kernel/bpf/verifier.c const struct bpf_reg_state *reg, reg 2523 kernel/bpf/verifier.c reg_off = tnum_add(reg->var_off, tnum_const(reg->off + off)); reg 2527 kernel/bpf/verifier.c tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); reg 2529 kernel/bpf/verifier.c pointer_desc, tn_buf, reg->off, off, size); reg 2537 kernel/bpf/verifier.c const struct bpf_reg_state *reg, int off, reg 2543 kernel/bpf/verifier.c switch (reg->type) { reg 2549 kernel/bpf/verifier.c return check_pkt_ptr_alignment(env, reg, off, size, strict); reg 2582 kernel/bpf/verifier.c return check_generic_ptr_alignment(env, reg, pointer_desc, off, size, reg 2680 kernel/bpf/verifier.c const struct bpf_reg_state *reg, int regno) reg 2686 kernel/bpf/verifier.c if (reg->off) { reg 2688 kernel/bpf/verifier.c regno, reg->off); reg 2692 kernel/bpf/verifier.c if (!tnum_is_const(reg->var_off) || reg->var_off.value) { reg 2695 kernel/bpf/verifier.c tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); reg 2704 kernel/bpf/verifier.c const struct bpf_reg_state *reg, reg 2713 kernel/bpf/verifier.c if (!tnum_is_const(reg->var_off) || reg->var_off.value) { reg 2716 kernel/bpf/verifier.c tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); reg 2732 kernel/bpf/verifier.c static void coerce_reg_to_size(struct bpf_reg_state *reg, int size) reg 2737 kernel/bpf/verifier.c reg->var_off = tnum_cast(reg->var_off, size); reg 2741 kernel/bpf/verifier.c if ((reg->umin_value & ~mask) == (reg->umax_value & ~mask)) { reg 2742 kernel/bpf/verifier.c reg->umin_value &= mask; reg 2743 kernel/bpf/verifier.c reg->umax_value &= mask; reg 2745 kernel/bpf/verifier.c reg->umin_value = 0; reg 2746 kernel/bpf/verifier.c reg->umax_value = mask; reg 2748 kernel/bpf/verifier.c reg->smin_value = reg->umin_value; reg 2749 kernel/bpf/verifier.c reg->smax_value = reg->umax_value; reg 2763 kernel/bpf/verifier.c struct bpf_reg_state *reg = regs + regno; reg 2772 kernel/bpf/verifier.c err = check_ptr_alignment(env, reg, off, size, strict_alignment_once); reg 2777 kernel/bpf/verifier.c off += reg->off; reg 2779 kernel/bpf/verifier.c if (reg->type == PTR_TO_MAP_VALUE) { reg 2792 kernel/bpf/verifier.c } else if (reg->type == PTR_TO_CTX) { reg 2801 kernel/bpf/verifier.c err = check_ctx_reg(env, reg, regno); reg 2828 kernel/bpf/verifier.c } else if (reg->type == PTR_TO_STACK) { reg 2829 kernel/bpf/verifier.c off += reg->var_off.value; reg 2830 kernel/bpf/verifier.c err = check_stack_access(env, reg, off, size); reg 2834 kernel/bpf/verifier.c state = func(env, reg); reg 2845 kernel/bpf/verifier.c } else if (reg_is_pkt_pointer(reg)) { reg 2859 kernel/bpf/verifier.c } else if (reg->type == PTR_TO_FLOW_KEYS) { reg 2870 kernel/bpf/verifier.c } else if (type_is_sk_pointer(reg->type)) { reg 2873 kernel/bpf/verifier.c regno, reg_type_str[reg->type]); reg 2879 kernel/bpf/verifier.c } else if (reg->type == PTR_TO_TP_BUFFER) { reg 2880 kernel/bpf/verifier.c err = check_tp_buffer_access(env, reg, regno, off, size); reg 2885 kernel/bpf/verifier.c reg_type_str[reg->type]); reg 2947 kernel/bpf/verifier.c struct bpf_reg_state *reg = reg_state(env, regno); reg 2951 kernel/bpf/verifier.c if (tnum_is_const(reg->var_off)) { reg 2957 kernel/bpf/verifier.c tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); reg 2976 kernel/bpf/verifier.c struct bpf_reg_state *reg = reg_state(env, regno); reg 2977 kernel/bpf/verifier.c struct bpf_func_state *state = func(env, reg); reg 2980 kernel/bpf/verifier.c if (reg->type != PTR_TO_STACK) { reg 2983 kernel/bpf/verifier.c register_is_null(reg)) reg 2987 kernel/bpf/verifier.c reg_type_str[reg->type], reg 2992 kernel/bpf/verifier.c if (tnum_is_const(reg->var_off)) { reg 2993 kernel/bpf/verifier.c min_off = max_off = reg->var_off.value + reg->off; reg 3007 kernel/bpf/verifier.c tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); reg 3021 kernel/bpf/verifier.c if (reg->smax_value >= BPF_MAX_VAR_OFF || reg 3022 kernel/bpf/verifier.c reg->smax_value <= -BPF_MAX_VAR_OFF) { reg 3027 kernel/bpf/verifier.c min_off = reg->smin_value + reg->off; reg 3028 kernel/bpf/verifier.c max_off = reg->smax_value + reg->off; reg 3075 kernel/bpf/verifier.c if (tnum_is_const(reg->var_off)) { reg 3081 kernel/bpf/verifier.c tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); reg 3101 kernel/bpf/verifier.c struct bpf_reg_state *regs = cur_regs(env), *reg = ®s[regno]; reg 3103 kernel/bpf/verifier.c switch (reg->type) { reg 3106 kernel/bpf/verifier.c return check_packet_access(env, regno, reg->off, access_size, reg 3109 kernel/bpf/verifier.c if (check_map_access_type(env, regno, reg->off, access_size, reg 3113 kernel/bpf/verifier.c return check_map_access(env, regno, reg->off, access_size, reg 3143 kernel/bpf/verifier.c struct bpf_reg_state *regs = cur_regs(env), *reg = ®s[regno]; reg 3145 kernel/bpf/verifier.c bool is_const = tnum_is_const(reg->var_off); reg 3146 kernel/bpf/verifier.c struct bpf_map *map = reg->map_ptr; reg 3147 kernel/bpf/verifier.c u64 val = reg->var_off.value; reg 3149 kernel/bpf/verifier.c if (reg->type != PTR_TO_MAP_VALUE) { reg 3180 kernel/bpf/verifier.c if (map->spin_lock_off != val + reg->off) { reg 3182 kernel/bpf/verifier.c val + reg->off); reg 3191 kernel/bpf/verifier.c cur->active_spin_lock = reg->id; reg 3197 kernel/bpf/verifier.c if (cur->active_spin_lock != reg->id) { reg 3239 kernel/bpf/verifier.c struct bpf_reg_state *regs = cur_regs(env), *reg = ®s[regno]; reg 3240 kernel/bpf/verifier.c enum bpf_reg_type expected_type, type = reg->type; reg 3270 kernel/bpf/verifier.c if (register_is_null(reg) && reg 3290 kernel/bpf/verifier.c err = check_ctx_reg(env, reg, regno); reg 3298 kernel/bpf/verifier.c if (reg->ref_obj_id) { reg 3301 kernel/bpf/verifier.c regno, reg->ref_obj_id, reg 3305 kernel/bpf/verifier.c meta->ref_obj_id = reg->ref_obj_id; reg 3328 kernel/bpf/verifier.c if (register_is_null(reg) && reg 3349 kernel/bpf/verifier.c meta->map_ptr = reg->map_ptr; reg 3369 kernel/bpf/verifier.c !register_is_null(reg)) || reg 3389 kernel/bpf/verifier.c meta->msize_max_value = reg->umax_value; reg 3394 kernel/bpf/verifier.c if (!tnum_is_const(reg->var_off)) reg 3402 kernel/bpf/verifier.c if (reg->smin_value < 0) { reg 3408 kernel/bpf/verifier.c if (reg->umin_value == 0) { reg 3416 kernel/bpf/verifier.c if (reg->umax_value >= BPF_MAX_VAR_SIZ) { reg 3422 kernel/bpf/verifier.c reg->umax_value, reg 3432 kernel/bpf/verifier.c err = check_ptr_alignment(env, reg, 0, size, true); reg 3696 kernel/bpf/verifier.c struct bpf_reg_state *regs = state->regs, *reg; reg 3703 kernel/bpf/verifier.c bpf_for_each_spilled_reg(i, state, reg) { reg 3704 kernel/bpf/verifier.c if (!reg) reg 3706 kernel/bpf/verifier.c if (reg_is_pkt_pointer_any(reg)) reg 3707 kernel/bpf/verifier.c __mark_reg_unknown(env, reg); reg 3724 kernel/bpf/verifier.c struct bpf_reg_state *regs = state->regs, *reg; reg 3731 kernel/bpf/verifier.c bpf_for_each_spilled_reg(i, state, reg) { reg 3732 kernel/bpf/verifier.c if (!reg) reg 3734 kernel/bpf/verifier.c if (reg->ref_obj_id == ref_obj_id) reg 3735 kernel/bpf/verifier.c __mark_reg_unknown(env, reg); reg 4198 kernel/bpf/verifier.c const struct bpf_reg_state *reg, reg 4201 kernel/bpf/verifier.c bool known = tnum_is_const(reg->var_off); reg 4202 kernel/bpf/verifier.c s64 val = reg->var_off.value; reg 4203 kernel/bpf/verifier.c s64 smin = reg->smin_value; reg 4211 kernel/bpf/verifier.c if (reg->off >= BPF_MAX_VAR_OFF || reg->off <= -BPF_MAX_VAR_OFF) { reg 4213 kernel/bpf/verifier.c reg_type_str[type], reg->off); reg 5126 kernel/bpf/verifier.c struct bpf_reg_state *reg; reg 5130 kernel/bpf/verifier.c reg = &state->regs[i]; reg 5131 kernel/bpf/verifier.c if (reg->type == type && reg->id == dst_reg->id) reg 5133 kernel/bpf/verifier.c reg->range = max(reg->range, new_range); reg 5136 kernel/bpf/verifier.c bpf_for_each_spilled_reg(i, state, reg) { reg 5137 kernel/bpf/verifier.c if (!reg) reg 5139 kernel/bpf/verifier.c if (reg->type == type && reg->id == dst_reg->id) reg 5140 kernel/bpf/verifier.c reg->range = max(reg->range, new_range); reg 5226 kernel/bpf/verifier.c static int is_branch_taken(struct bpf_reg_state *reg, u64 val, u8 opcode, reg 5232 kernel/bpf/verifier.c if (__is_pointer_value(false, reg)) reg 5236 kernel/bpf/verifier.c reg_lo = *reg; reg 5237 kernel/bpf/verifier.c reg = ®_lo; reg 5242 kernel/bpf/verifier.c coerce_reg_to_size(reg, 4); reg 5256 kernel/bpf/verifier.c if ((reg->umax_value ^ reg->umin_value) & reg 5258 kernel/bpf/verifier.c reg->smin_value = S32_MIN; reg 5259 kernel/bpf/verifier.c reg->smax_value = S32_MAX; reg 5261 kernel/bpf/verifier.c reg->smin_value = (s64)(s32)reg->smin_value; reg 5262 kernel/bpf/verifier.c reg->smax_value = (s64)(s32)reg->smax_value; reg 5272 kernel/bpf/verifier.c if (tnum_is_const(reg->var_off)) reg 5273 kernel/bpf/verifier.c return !!tnum_equals_const(reg->var_off, val); reg 5276 kernel/bpf/verifier.c if (tnum_is_const(reg->var_off)) reg 5277 kernel/bpf/verifier.c return !tnum_equals_const(reg->var_off, val); reg 5280 kernel/bpf/verifier.c if ((~reg->var_off.mask & reg->var_off.value) & val) reg 5282 kernel/bpf/verifier.c if (!((reg->var_off.mask | reg->var_off.value) & val)) reg 5286 kernel/bpf/verifier.c if (reg->umin_value > val) reg 5288 kernel/bpf/verifier.c else if (reg->umax_value <= val) reg 5292 kernel/bpf/verifier.c if (reg->smin_value > sval) reg 5294 kernel/bpf/verifier.c else if (reg->smax_value < sval) reg 5298 kernel/bpf/verifier.c if (reg->umax_value < val) reg 5300 kernel/bpf/verifier.c else if (reg->umin_value >= val) reg 5304 kernel/bpf/verifier.c if (reg->smax_value < sval) reg 5306 kernel/bpf/verifier.c else if (reg->smin_value >= sval) reg 5310 kernel/bpf/verifier.c if (reg->umin_value >= val) reg 5312 kernel/bpf/verifier.c else if (reg->umax_value < val) reg 5316 kernel/bpf/verifier.c if (reg->smin_value >= sval) reg 5318 kernel/bpf/verifier.c else if (reg->smax_value < sval) reg 5322 kernel/bpf/verifier.c if (reg->umax_value <= val) reg 5324 kernel/bpf/verifier.c else if (reg->umin_value > val) reg 5328 kernel/bpf/verifier.c if (reg->smax_value <= sval) reg 5330 kernel/bpf/verifier.c else if (reg->smin_value > sval) reg 5353 kernel/bpf/verifier.c static bool cmp_val_with_extended_s64(s64 sval, struct bpf_reg_state *reg) reg 5356 kernel/bpf/verifier.c reg->smin_value >= 0 && reg->smax_value <= S32_MAX) || reg 5358 kernel/bpf/verifier.c reg->smax_value <= 0 && reg->smin_value >= S32_MIN); reg 5366 kernel/bpf/verifier.c static void set_upper_bound(struct bpf_reg_state *reg, u64 bound, bool is_jmp32, reg 5385 kernel/bpf/verifier.c reg->var_off = tnum_intersect(reg->var_off, t); reg 5388 kernel/bpf/verifier.c bound += gen_hi_max(reg->var_off); reg 5390 kernel/bpf/verifier.c reg->umax_value = min(reg->umax_value, bound); reg 5398 kernel/bpf/verifier.c static void set_lower_bound(struct bpf_reg_state *reg, u64 bound, bool is_jmp32, reg 5417 kernel/bpf/verifier.c reg->var_off = tnum_intersect(reg->var_off, t); reg 5420 kernel/bpf/verifier.c bound += gen_hi_min(reg->var_off); reg 5422 kernel/bpf/verifier.c reg->umin_value = max(reg->umin_value, bound); reg 5452 kernel/bpf/verifier.c struct bpf_reg_state *reg = reg 5460 kernel/bpf/verifier.c u64 old_v = reg->var_off.value; reg 5463 kernel/bpf/verifier.c reg->var_off.value = (old_v & hi_mask) | val; reg 5464 kernel/bpf/verifier.c reg->var_off.mask &= hi_mask; reg 5466 kernel/bpf/verifier.c __mark_reg_known(reg, val); reg 5554 kernel/bpf/verifier.c struct bpf_reg_state *reg = reg 5558 kernel/bpf/verifier.c u64 old_v = reg->var_off.value; reg 5561 kernel/bpf/verifier.c reg->var_off.value = (old_v & hi_mask) | val; reg 5562 kernel/bpf/verifier.c reg->var_off.mask &= hi_mask; reg 5564 kernel/bpf/verifier.c __mark_reg_known(reg, val); reg 5678 kernel/bpf/verifier.c struct bpf_reg_state *reg, u32 id, reg 5681 kernel/bpf/verifier.c if (reg_type_may_be_null(reg->type) && reg->id == id) { reg 5686 kernel/bpf/verifier.c if (WARN_ON_ONCE(reg->smin_value || reg->smax_value || reg 5687 kernel/bpf/verifier.c !tnum_equals_const(reg->var_off, 0) || reg 5688 kernel/bpf/verifier.c reg->off)) { reg 5689 kernel/bpf/verifier.c __mark_reg_known_zero(reg); reg 5690 kernel/bpf/verifier.c reg->off = 0; reg 5693 kernel/bpf/verifier.c reg->type = SCALAR_VALUE; reg 5694 kernel/bpf/verifier.c } else if (reg->type == PTR_TO_MAP_VALUE_OR_NULL) { reg 5695 kernel/bpf/verifier.c if (reg->map_ptr->inner_map_meta) { reg 5696 kernel/bpf/verifier.c reg->type = CONST_PTR_TO_MAP; reg 5697 kernel/bpf/verifier.c reg->map_ptr = reg->map_ptr->inner_map_meta; reg 5698 kernel/bpf/verifier.c } else if (reg->map_ptr->map_type == reg 5700 kernel/bpf/verifier.c reg->type = PTR_TO_XDP_SOCK; reg 5702 kernel/bpf/verifier.c reg->type = PTR_TO_MAP_VALUE; reg 5704 kernel/bpf/verifier.c } else if (reg->type == PTR_TO_SOCKET_OR_NULL) { reg 5705 kernel/bpf/verifier.c reg->type = PTR_TO_SOCKET; reg 5706 kernel/bpf/verifier.c } else if (reg->type == PTR_TO_SOCK_COMMON_OR_NULL) { reg 5707 kernel/bpf/verifier.c reg->type = PTR_TO_SOCK_COMMON; reg 5708 kernel/bpf/verifier.c } else if (reg->type == PTR_TO_TCP_SOCK_OR_NULL) { reg 5709 kernel/bpf/verifier.c reg->type = PTR_TO_TCP_SOCK; reg 5716 kernel/bpf/verifier.c reg->id = 0; reg 5717 kernel/bpf/verifier.c reg->ref_obj_id = 0; reg 5718 kernel/bpf/verifier.c } else if (!reg_may_point_to_spin_lock(reg)) { reg 5725 kernel/bpf/verifier.c reg->id = 0; reg 5733 kernel/bpf/verifier.c struct bpf_reg_state *reg; reg 5739 kernel/bpf/verifier.c bpf_for_each_spilled_reg(i, state, reg) { reg 5740 kernel/bpf/verifier.c if (!reg) reg 5742 kernel/bpf/verifier.c mark_ptr_or_null_reg(state, reg, id, is_null); reg 6188 kernel/bpf/verifier.c struct bpf_reg_state *reg; reg 6213 kernel/bpf/verifier.c reg = cur_regs(env) + BPF_REG_0; reg 6214 kernel/bpf/verifier.c if (reg->type != SCALAR_VALUE) { reg 6216 kernel/bpf/verifier.c reg_type_str[reg->type]); reg 6220 kernel/bpf/verifier.c if (!tnum_in(range, reg->var_off)) { reg 6224 kernel/bpf/verifier.c if (!tnum_is_unknown(reg->var_off)) { reg 6225 kernel/bpf/verifier.c tnum_strn(tn_buf, sizeof(tn_buf), reg->var_off); reg 6236 kernel/bpf/verifier.c tnum_in(enforce_attach_type_range, reg->var_off)) reg 7172 kernel/bpf/verifier.c struct bpf_reg_state *reg, reg 7176 kernel/bpf/verifier.c u8 flag = reg->live & REG_LIVE_READ; reg 7190 kernel/bpf/verifier.c err = mark_reg_read(env, reg, parent_reg, flag); reg 75 kernel/dma/contiguous.c struct memblock_region *reg; reg 82 kernel/dma/contiguous.c for_each_memblock(memory, reg) reg 83 kernel/dma/contiguous.c total_pages += memblock_region_memory_end_pfn(reg) - reg 84 kernel/dma/contiguous.c memblock_region_memory_base_pfn(reg); reg 1818 kernel/trace/trace.h int (*reg)(char *glob, reg 124 kernel/trace/trace_event_perf.c ret = tp_event->class->reg(tp_event, TRACE_REG_PERF_REGISTER, NULL); reg 157 kernel/trace/trace_event_perf.c tp_event->class->reg(tp_event, TRACE_REG_PERF_UNREGISTER, NULL); reg 181 kernel/trace/trace_event_perf.c return tp_event->class->reg(tp_event, TRACE_REG_PERF_OPEN, p_event); reg 187 kernel/trace/trace_event_perf.c tp_event->class->reg(tp_event, TRACE_REG_PERF_CLOSE, p_event); reg 221 kernel/trace/trace_event_perf.c tp_event->class && tp_event->class->reg && reg 362 kernel/trace/trace_event_perf.c if (!tp_event->class->reg(tp_event, TRACE_REG_PERF_ADD, p_event)) { reg 386 kernel/trace/trace_event_perf.c if (!tp_event->class->reg(tp_event, TRACE_REG_PERF_DEL, p_event)) reg 406 kernel/trace/trace_events.c call->class->reg(call, TRACE_REG_UNREGISTER, file); reg 450 kernel/trace/trace_events.c ret = call->class->reg(call, TRACE_REG_REGISTER, file); reg 746 kernel/trace/trace_events.c if (!name || !call->class || !call->class->reg) reg 911 kernel/trace/trace_events.c if (call->class && call->class->reg && reg 1108 kernel/trace/trace_events.c if (!trace_event_name(call) || !call->class || !call->class->reg) reg 1976 kernel/trace/trace_events.c if (call->class->reg && !(call->flags & TRACE_EVENT_FL_IGNORE_ENABLE)) reg 1981 kernel/trace/trace_events.c if (call->event.type && call->class->reg) reg 2498 kernel/trace/trace_events.c if (!file || !file->event_call->class->reg || reg 1215 kernel/trace/trace_events_hist.c call->class->reg = trace_event_reg; reg 6321 kernel/trace/trace_events_hist.c ret = cmd_ops->reg(glob, trigger_ops, trigger_data, file); reg 6382 kernel/trace/trace_events_hist.c .reg = hist_register_trigger, reg 6495 kernel/trace/trace_events_hist.c .reg = event_enable_register_trigger, reg 6506 kernel/trace/trace_events_hist.c .reg = event_enable_register_trigger, reg 686 kernel/trace/trace_events_trigger.c ret = cmd_ops->reg(glob, trigger_ops, trigger_data, file); reg 1043 kernel/trace/trace_events_trigger.c .reg = register_trigger, reg 1054 kernel/trace/trace_events_trigger.c .reg = register_trigger, reg 1129 kernel/trace/trace_events_trigger.c .reg = register_snapshot_trigger, reg 1219 kernel/trace/trace_events_trigger.c .reg = register_trigger, reg 1464 kernel/trace/trace_events_trigger.c ret = cmd_ops->reg(glob, trigger_ops, trigger_data, file); reg 1591 kernel/trace/trace_events_trigger.c .reg = event_enable_register_trigger, reg 1601 kernel/trace/trace_events_trigger.c .reg = event_enable_register_trigger, reg 178 kernel/trace/trace_export.c .reg = regfn, \ reg 1573 kernel/trace/trace_kprobe.c call->class->reg = kprobe_register; reg 515 kernel/trace/trace_syscalls.c .reg = syscall_enter_register, reg 523 kernel/trace/trace_syscalls.c .reg = syscall_exit_register, reg 1539 kernel/trace/trace_uprobe.c call->class->reg = trace_uprobe_register; reg 38 lib/reed_solomon/decode_rs.c uint16_t *reg = rsc->buffers + RS_DECODE_REG * (nroots + 1); reg 198 lib/reed_solomon/decode_rs.c memcpy(®[1], &lambda[1], nroots * sizeof(reg[0])); reg 203 lib/reed_solomon/decode_rs.c if (reg[j] != nn) { reg 204 lib/reed_solomon/decode_rs.c reg[j] = rs_modnn(rs, reg[j] + j); reg 205 lib/reed_solomon/decode_rs.c q ^= alpha_to[reg[j]]; reg 1991 mm/memblock.c struct memblock_region *reg; reg 1996 mm/memblock.c reg = &type->regions[i]; reg 1997 mm/memblock.c end = reg->base + reg->size - 1; reg 2000 mm/memblock.c seq_printf(m, "%pa..%pa\n", ®->base, &end); reg 300 mm/sparse.c struct memblock_region *reg; reg 302 mm/sparse.c for_each_memblock(memory, reg) { reg 303 mm/sparse.c memory_present(memblock_get_region_node(reg), reg 304 mm/sparse.c memblock_region_memory_base_pfn(reg), reg 305 mm/sparse.c memblock_region_memory_end_pfn(reg)); reg 8021 net/core/filter.c int reg = BPF_REG_9; \ reg 8024 net/core/filter.c if (si->dst_reg == reg || si->src_reg == reg) \ reg 8025 net/core/filter.c reg--; \ reg 8026 net/core/filter.c if (si->dst_reg == reg || si->src_reg == reg) \ reg 8027 net/core/filter.c reg--; \ reg 8028 net/core/filter.c *insn++ = BPF_STX_MEM(BPF_DW, si->dst_reg, reg, \ reg 8034 net/core/filter.c reg, si->dst_reg, \ reg 8037 net/core/filter.c *insn++ = BPF_JMP_IMM(BPF_JEQ, reg, 0, 2); \ reg 8040 net/core/filter.c reg, si->dst_reg, \ reg 8043 net/core/filter.c reg, si->src_reg, \ reg 8045 net/core/filter.c *insn++ = BPF_LDX_MEM(BPF_DW, reg, si->dst_reg, \ reg 687 net/dsa/dsa2.c u32 reg; reg 696 net/dsa/dsa2.c err = of_property_read_u32(port, "reg", ®); reg 700 net/dsa/dsa2.c if (reg >= ds->num_ports) { reg 705 net/dsa/dsa2.c dp = &ds->ports[reg]; reg 28 net/dsa/slave.c static int dsa_slave_phy_read(struct mii_bus *bus, int addr, int reg) reg 33 net/dsa/slave.c return ds->ops->phy_read(ds, addr, reg); reg 38 net/dsa/slave.c static int dsa_slave_phy_write(struct mii_bus *bus, int addr, int reg, u16 val) reg 43 net/dsa/slave.c return ds->ops->phy_write(ds, addr, reg, val); reg 3471 net/mac80211/cfg.c u16 frame_type, bool reg) reg 3478 net/mac80211/cfg.c if (reg) { reg 105 net/netfilter/core.c const struct nf_hook_ops *reg) reg 142 net/netfilter/core.c if (inserted || reg->priority > orig_ops[i]->priority) { reg 147 net/netfilter/core.c new_ops[nhooks] = (void *)reg; reg 148 net/netfilter/core.c new->hooks[nhooks].hook = reg->hook; reg 149 net/netfilter/core.c new->hooks[nhooks].priv = reg->priv; reg 156 net/netfilter/core.c new_ops[nhooks] = (void *)reg; reg 157 net/netfilter/core.c new->hooks[nhooks].hook = reg->hook; reg 158 net/netfilter/core.c new->hooks[nhooks].priv = reg->priv; reg 186 net/netfilter/core.c const struct nf_hook_ops *reg) reg 192 net/netfilter/core.c new_hooks = nf_hook_entries_grow(p, reg); reg 315 net/netfilter/core.c const struct nf_hook_ops *reg) reg 322 net/netfilter/core.c if (reg->hooknum == NF_NETDEV_INGRESS) reg 325 net/netfilter/core.c if (reg->hooknum != NF_NETDEV_INGRESS || reg 326 net/netfilter/core.c !reg->dev || dev_net(reg->dev) != net) reg 330 net/netfilter/core.c pp = nf_hook_entry_head(net, pf, reg->hooknum, reg->dev); reg 337 net/netfilter/core.c new_hooks = nf_hook_entries_grow(p, reg); reg 348 net/netfilter/core.c if (pf == NFPROTO_NETDEV && reg->hooknum == NF_NETDEV_INGRESS) reg 352 net/netfilter/core.c static_key_slow_inc(&nf_hooks_needed[pf][reg->hooknum]); reg 387 net/netfilter/core.c const struct nf_hook_ops *reg) reg 392 net/netfilter/core.c pp = nf_hook_entry_head(net, pf, reg->hooknum, reg->dev); reg 404 net/netfilter/core.c if (nf_remove_net_hook(p, reg)) { reg 406 net/netfilter/core.c if (pf == NFPROTO_NETDEV && reg->hooknum == NF_NETDEV_INGRESS) reg 410 net/netfilter/core.c static_key_slow_dec(&nf_hooks_needed[pf][reg->hooknum]); reg 413 net/netfilter/core.c WARN_ONCE(1, "hook not found, pf %d num %d", pf, reg->hooknum); reg 425 net/netfilter/core.c void nf_unregister_net_hook(struct net *net, const struct nf_hook_ops *reg) reg 427 net/netfilter/core.c if (reg->pf == NFPROTO_INET) { reg 428 net/netfilter/core.c __nf_unregister_net_hook(net, NFPROTO_IPV4, reg); reg 429 net/netfilter/core.c __nf_unregister_net_hook(net, NFPROTO_IPV6, reg); reg 431 net/netfilter/core.c __nf_unregister_net_hook(net, reg->pf, reg); reg 437 net/netfilter/core.c const struct nf_hook_ops *reg) reg 442 net/netfilter/core.c if (nf_remove_net_hook(p, reg)) { reg 449 net/netfilter/core.c int nf_register_net_hook(struct net *net, const struct nf_hook_ops *reg) reg 453 net/netfilter/core.c if (reg->pf == NFPROTO_INET) { reg 454 net/netfilter/core.c err = __nf_register_net_hook(net, NFPROTO_IPV4, reg); reg 458 net/netfilter/core.c err = __nf_register_net_hook(net, NFPROTO_IPV6, reg); reg 460 net/netfilter/core.c __nf_unregister_net_hook(net, NFPROTO_IPV4, reg); reg 464 net/netfilter/core.c err = __nf_register_net_hook(net, reg->pf, reg); reg 473 net/netfilter/core.c int nf_register_net_hooks(struct net *net, const struct nf_hook_ops *reg, reg 480 net/netfilter/core.c err = nf_register_net_hook(net, ®[i]); reg 488 net/netfilter/core.c nf_unregister_net_hooks(net, reg, i); reg 493 net/netfilter/core.c void nf_unregister_net_hooks(struct net *net, const struct nf_hook_ops *reg, reg 499 net/netfilter/core.c nf_unregister_net_hook(net, ®[i]); reg 17 net/netfilter/nf_internals.h const struct nf_hook_ops *reg); reg 19 net/netfilter/nf_internals.h const struct nf_hook_ops *reg); reg 25 net/netfilter/nf_sockopt.c int nf_register_sockopt(struct nf_sockopt_ops *reg) reg 32 net/netfilter/nf_sockopt.c if (ops->pf == reg->pf reg 34 net/netfilter/nf_sockopt.c reg->set_optmin, reg->set_optmax) reg 36 net/netfilter/nf_sockopt.c reg->get_optmin, reg->get_optmax))) { reg 40 net/netfilter/nf_sockopt.c reg->set_optmin, reg->set_optmax, reg 41 net/netfilter/nf_sockopt.c reg->get_optmin, reg->get_optmax); reg 47 net/netfilter/nf_sockopt.c list_add(®->list, &nf_sockopts); reg 54 net/netfilter/nf_sockopt.c void nf_unregister_sockopt(struct nf_sockopt_ops *reg) reg 57 net/netfilter/nf_sockopt.c list_del(®->list); reg 7352 net/netfilter/nf_tables_api.c unsigned int reg; reg 7354 net/netfilter/nf_tables_api.c reg = ntohl(nla_get_be32(attr)); reg 7355 net/netfilter/nf_tables_api.c switch (reg) { reg 7357 net/netfilter/nf_tables_api.c return reg * NFT_REG_SIZE / NFT_REG32_SIZE; reg 7359 net/netfilter/nf_tables_api.c return reg + NFT_REG_SIZE / NFT_REG32_SIZE - NFT_REG32_00; reg 7375 net/netfilter/nf_tables_api.c int nft_dump_register(struct sk_buff *skb, unsigned int attr, unsigned int reg) reg 7377 net/netfilter/nf_tables_api.c if (reg % (NFT_REG_SIZE / NFT_REG32_SIZE) == 0) reg 7378 net/netfilter/nf_tables_api.c reg = reg / (NFT_REG_SIZE / NFT_REG32_SIZE); reg 7380 net/netfilter/nf_tables_api.c reg = reg - NFT_REG_SIZE / NFT_REG32_SIZE + NFT_REG32_00; reg 7382 net/netfilter/nf_tables_api.c return nla_put_be32(skb, attr, htonl(reg)); reg 7395 net/netfilter/nf_tables_api.c int nft_validate_register_load(enum nft_registers reg, unsigned int len) reg 7397 net/netfilter/nf_tables_api.c if (reg < NFT_REG_1 * NFT_REG_SIZE / NFT_REG32_SIZE) reg 7401 net/netfilter/nf_tables_api.c if (reg * NFT_REG32_SIZE + len > FIELD_SIZEOF(struct nft_regs, data)) reg 7423 net/netfilter/nf_tables_api.c enum nft_registers reg, reg 7429 net/netfilter/nf_tables_api.c switch (reg) { reg 7444 net/netfilter/nf_tables_api.c if (reg < NFT_REG_1 * NFT_REG_SIZE / NFT_REG32_SIZE) reg 7448 net/netfilter/nf_tables_api.c if (reg * NFT_REG32_SIZE + len > reg 137 net/netfilter/nft_bitwise.c struct nft_offload_reg *reg = &ctx->regs[priv->dreg]; reg 140 net/netfilter/nft_bitwise.c priv->sreg != priv->dreg || priv->len != reg->len) reg 143 net/netfilter/nft_bitwise.c memcpy(®->mask, &priv->mask, sizeof(priv->mask)); reg 121 net/netfilter/nft_cmp.c struct nft_offload_reg *reg = &ctx->regs[priv->sreg]; reg 125 net/netfilter/nft_cmp.c if (priv->op != NFT_CMP_EQ || reg->len != priv->len) reg 128 net/netfilter/nft_cmp.c memcpy(key + reg->offset, &priv->data, priv->len); reg 129 net/netfilter/nft_cmp.c memcpy(mask + reg->offset, ®->mask, priv->len); reg 131 net/netfilter/nft_cmp.c flow->match.dissector.used_keys |= BIT(reg->key); reg 132 net/netfilter/nft_cmp.c flow->match.dissector.offset[reg->key] = reg->base_offset; reg 135 net/netfilter/nft_fib.c void nft_fib_store_result(void *reg, const struct nft_fib *priv, reg 138 net/netfilter/nft_fib.c u32 *dreg = reg; reg 150 net/netfilter/nft_fib.c strncpy(reg, dev ? dev->name : "", IFNAMSIZ); reg 537 net/netfilter/nft_meta.c struct nft_offload_reg *reg = &ctx->regs[priv->dreg]; reg 542 net/netfilter/nft_meta.c sizeof(__u16), reg); reg 547 net/netfilter/nft_meta.c sizeof(__u8), reg); reg 161 net/netfilter/nft_payload.c struct nft_offload_reg *reg = &ctx->regs[priv->dreg]; reg 169 net/netfilter/nft_payload.c src, ETH_ALEN, reg); reg 176 net/netfilter/nft_payload.c dst, ETH_ALEN, reg); reg 189 net/netfilter/nft_payload.c struct nft_offload_reg *reg = &ctx->regs[priv->dreg]; reg 197 net/netfilter/nft_payload.c sizeof(struct in_addr), reg); reg 204 net/netfilter/nft_payload.c sizeof(struct in_addr), reg); reg 211 net/netfilter/nft_payload.c sizeof(__u8), reg); reg 225 net/netfilter/nft_payload.c struct nft_offload_reg *reg = &ctx->regs[priv->dreg]; reg 233 net/netfilter/nft_payload.c sizeof(struct in6_addr), reg); reg 240 net/netfilter/nft_payload.c sizeof(struct in6_addr), reg); reg 247 net/netfilter/nft_payload.c sizeof(__u8), reg); reg 281 net/netfilter/nft_payload.c struct nft_offload_reg *reg = &ctx->regs[priv->dreg]; reg 289 net/netfilter/nft_payload.c sizeof(__be16), reg); reg 296 net/netfilter/nft_payload.c sizeof(__be16), reg); reg 309 net/netfilter/nft_payload.c struct nft_offload_reg *reg = &ctx->regs[priv->dreg]; reg 317 net/netfilter/nft_payload.c sizeof(__be16), reg); reg 324 net/netfilter/nft_payload.c sizeof(__be16), reg); reg 1043 net/wireless/core.c struct cfg80211_beacon_registration *reg, *treg; reg 1045 net/wireless/core.c list_for_each_entry_safe(reg, treg, &rdev->beacon_registrations, list) { reg 1046 net/wireless/core.c list_del(®->list); reg 1047 net/wireless/core.c kfree(reg); reg 434 net/wireless/mlme.c struct cfg80211_mgmt_registration *reg; reg 439 net/wireless/mlme.c while ((reg = list_first_entry_or_null(&rdev->mlme_unreg, reg 442 net/wireless/mlme.c list_del(®->list); reg 446 net/wireless/mlme.c u16 frame_type = le16_to_cpu(reg->frame_type); reg 448 net/wireless/mlme.c rdev_mgmt_frame_register(rdev, reg->wdev, reg 452 net/wireless/mlme.c kfree(reg); reg 477 net/wireless/mlme.c struct cfg80211_mgmt_registration *reg, *nreg; reg 494 net/wireless/mlme.c nreg = kzalloc(sizeof(*reg) + match_len, GFP_KERNEL); reg 500 net/wireless/mlme.c list_for_each_entry(reg, &wdev->mgmt_registrations, list) { reg 501 net/wireless/mlme.c int mlen = min(match_len, reg->match_len); reg 503 net/wireless/mlme.c if (frame_type != le16_to_cpu(reg->frame_type)) reg 506 net/wireless/mlme.c if (memcmp(reg->match, match_data, mlen) == 0) { reg 543 net/wireless/mlme.c struct cfg80211_mgmt_registration *reg, *tmp; reg 547 net/wireless/mlme.c list_for_each_entry_safe(reg, tmp, &wdev->mgmt_registrations, list) { reg 548 net/wireless/mlme.c if (reg->nlportid != nlportid) reg 551 net/wireless/mlme.c list_del(®->list); reg 553 net/wireless/mlme.c list_add_tail(®->list, &rdev->mlme_unreg); reg 704 net/wireless/mlme.c struct cfg80211_mgmt_registration *reg; reg 728 net/wireless/mlme.c list_for_each_entry(reg, &wdev->mgmt_registrations, list) { reg 729 net/wireless/mlme.c if (reg->frame_type != ftype) reg 732 net/wireless/mlme.c if (reg->match_len > data_len) reg 735 net/wireless/mlme.c if (memcmp(reg->match, data, reg->match_len)) reg 741 net/wireless/mlme.c if (nl80211_send_mgmt(rdev, wdev, reg->nlportid, reg 12147 net/wireless/nl80211.c struct cfg80211_beacon_registration *reg, *nreg; reg 12159 net/wireless/nl80211.c list_for_each_entry(reg, &rdev->beacon_registrations, list) { reg 12160 net/wireless/nl80211.c if (reg->nlportid == info->snd_portid) { reg 16477 net/wireless/nl80211.c struct cfg80211_beacon_registration *reg; reg 16482 net/wireless/nl80211.c list_for_each_entry(reg, &rdev->beacon_registrations, list) { reg 16503 net/wireless/nl80211.c genlmsg_unicast(wiphy_net(&rdev->wiphy), msg, reg->nlportid); reg 16737 net/wireless/nl80211.c struct cfg80211_beacon_registration *reg, *tmp; reg 16770 net/wireless/nl80211.c list_for_each_entry_safe(reg, tmp, &rdev->beacon_registrations, reg 16772 net/wireless/nl80211.c if (reg->nlportid == notify->portid) { reg 16773 net/wireless/nl80211.c list_del(®->list); reg 16774 net/wireless/nl80211.c kfree(reg); reg 810 net/wireless/rdev-ops.h struct wireless_dev *wdev, u16 frame_type, bool reg) reg 814 net/wireless/rdev-ops.h trace_rdev_mgmt_frame_register(&rdev->wiphy, wdev , frame_type, reg); reg 815 net/wireless/rdev-ops.h rdev->ops->mgmt_frame_register(&rdev->wiphy, wdev , frame_type, reg); reg 1570 net/wireless/trace.h u16 frame_type, bool reg), reg 1571 net/wireless/trace.h TP_ARGS(wiphy, wdev, frame_type, reg), reg 1576 net/wireless/trace.h __field(bool, reg) reg 1582 net/wireless/trace.h __entry->reg = reg; reg 1586 net/wireless/trace.h __entry->reg ? "true" : "false") reg 879 scripts/dtc/checks.c unsigned int dev, func, reg; reg 895 scripts/dtc/checks.c reg = fdt32_to_cpu(cells[0]); reg 896 scripts/dtc/checks.c dev = (reg & 0xf800) >> 11; reg 897 scripts/dtc/checks.c func = (reg & 0x700) >> 8; reg 899 scripts/dtc/checks.c if (reg & 0xff000000) reg 901 scripts/dtc/checks.c if (reg & 0x000000ff) reg 954 scripts/dtc/checks.c uint64_t reg = 0; reg 978 scripts/dtc/checks.c reg = (reg << 32) | fdt32_to_cpu(*(cells++)); reg 980 scripts/dtc/checks.c snprintf(unit_addr, sizeof(unit_addr), "%"PRIx64, reg); reg 1022 scripts/dtc/checks.c uint32_t reg = 0; reg 1038 scripts/dtc/checks.c reg = fdt32_to_cpu(*cells); reg 1039 scripts/dtc/checks.c snprintf(unit_addr, sizeof(unit_addr), "%x", reg); reg 1045 scripts/dtc/checks.c reg = fdt32_to_cpu(*(cells++)); reg 1046 scripts/dtc/checks.c if (reg > 0x3ff) reg 1048 scripts/dtc/checks.c reg); reg 1104 scripts/dtc/checks.c uint32_t reg = 0; reg 1122 scripts/dtc/checks.c reg = fdt32_to_cpu(*cells); reg 1123 scripts/dtc/checks.c snprintf(unit_addr, sizeof(unit_addr), "%x", reg); reg 1158 scripts/dtc/checks.c struct property *reg, *ranges; reg 1163 scripts/dtc/checks.c reg = get_property(node, "reg"); reg 1166 scripts/dtc/checks.c if (!reg && !ranges) reg 627 scripts/dtc/livetree.c struct property *reg; reg 638 scripts/dtc/livetree.c reg = get_property(bootcpu, "reg"); reg 639 scripts/dtc/livetree.c if (!reg || (reg->val.len != sizeof(uint32_t))) reg 644 scripts/dtc/livetree.c return propval_cell(reg); reg 22 security/keys/persistent.c struct key *reg = keyring_alloc(".persistent_register", reg 28 security/keys/persistent.c if (IS_ERR(reg)) reg 29 security/keys/persistent.c return PTR_ERR(reg); reg 31 security/keys/persistent.c ns->persistent_keyring_register = reg; reg 40 sound/ac97/bus.c unsigned short reg, unsigned short val) reg 46 sound/ac97/bus.c unsigned short reg) reg 74 sound/ac97/bus.c u32 reg; reg 81 sound/ac97/bus.c if ((idx != of_property_read_u32(node, "reg", ®)) || reg 38 sound/ac97/snd_ac97_compat.c static void compat_ac97_write(struct snd_ac97 *ac97, unsigned short reg, reg 44 sound/ac97/snd_ac97_compat.c actrl->ops->write(actrl, ac97->num, reg, val); reg 48 sound/ac97/snd_ac97_compat.c unsigned short reg) reg 53 sound/ac97/snd_ac97_compat.c return actrl->ops->read(actrl, ac97->num, reg); reg 65 sound/aoa/codecs/onyx.c static int onyx_read_register(struct onyx *onyx, u8 reg, u8 *value) reg 69 sound/aoa/codecs/onyx.c if (reg != ONYX_REG_CONTROL) { reg 70 sound/aoa/codecs/onyx.c *value = onyx->cache[reg-FIRSTREGISTER]; reg 73 sound/aoa/codecs/onyx.c v = i2c_smbus_read_byte_data(onyx->i2c, reg); reg 83 sound/aoa/codecs/onyx.c static int onyx_write_register(struct onyx *onyx, u8 reg, u8 value) reg 87 sound/aoa/codecs/onyx.c result = i2c_smbus_write_byte_data(onyx->i2c, reg, value); reg 89 sound/aoa/codecs/onyx.c onyx->cache[reg-FIRSTREGISTER] = value; reg 108 sound/aoa/codecs/tas.c static inline int tas_write_reg(struct tas *tas, u8 reg, u8 len, u8 *data) reg 111 sound/aoa/codecs/tas.c return i2c_smbus_write_byte_data(tas->i2c, reg, *data); reg 113 sound/aoa/codecs/tas.c return i2c_smbus_write_i2c_block_data(tas->i2c, reg, len, data); reg 60 sound/aoa/core/gpio-feature.c const u32 *reg; reg 90 sound/aoa/core/gpio-feature.c reg = of_get_property(np, "reg", NULL); reg 91 sound/aoa/core/gpio-feature.c if (!reg) { reg 96 sound/aoa/core/gpio-feature.c *gpioptr = *reg; reg 104 sound/aoa/core/gpio-feature.c reg = of_get_property(np, "audio-gpio-active-state", NULL); reg 105 sound/aoa/core/gpio-feature.c if (!reg) reg 113 sound/aoa/core/gpio-feature.c *gpioactiveptr = *reg; reg 119 sound/aoa/soundbus/i2sbus/core.c const u32 *reg; reg 138 sound/aoa/soundbus/i2sbus/core.c reg = of_get_property(np, "reg", NULL); reg 139 sound/aoa/soundbus/i2sbus/core.c if (reg == NULL) { reg 143 sound/aoa/soundbus/i2sbus/core.c res->start += reg[index * 2]; reg 144 sound/aoa/soundbus/i2sbus/core.c res->end = res->start + reg[index * 2 + 1] - 1; reg 66 sound/arm/aaci.c static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg, reg 85 sound/arm/aaci.c writel(reg << 12, aaci->base + AACI_SL1TX); reg 107 sound/arm/aaci.c static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg) reg 123 sound/arm/aaci.c writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX); reg 160 sound/arm/aaci.c if (v == reg) { reg 170 sound/arm/aaci.c v, reg); reg 46 sound/arm/pxa2xx-ac97-lib.c int pxa2xx_ac97_read(int slot, unsigned short reg) reg 57 sound/arm/pxa2xx-ac97-lib.c if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS) reg 61 sound/arm/pxa2xx-ac97-lib.c reg_addr += (reg >> 1); reg 67 sound/arm/pxa2xx-ac97-lib.c if (reg == AC97_GPIO_STATUS) reg 72 sound/arm/pxa2xx-ac97-lib.c __func__, reg, GSR | gsr_bits); reg 89 sound/arm/pxa2xx-ac97-lib.c int pxa2xx_ac97_write(int slot, unsigned short reg, unsigned short val) reg 97 sound/arm/pxa2xx-ac97-lib.c if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS) reg 101 sound/arm/pxa2xx-ac97-lib.c reg_addr += (reg >> 1); reg 109 sound/arm/pxa2xx-ac97-lib.c __func__, reg, GSR | gsr_bits); reg 36 sound/arm/pxa2xx-ac97.c unsigned short reg) reg 40 sound/arm/pxa2xx-ac97.c ret = pxa2xx_ac97_read(ac97->num, reg); reg 48 sound/arm/pxa2xx-ac97.c unsigned short reg, unsigned short val) reg 52 sound/arm/pxa2xx-ac97.c ret = pxa2xx_ac97_write(ac97->num, reg, val); reg 106 sound/arm/pxa2xx-ac97.c int reg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? reg 114 sound/arm/pxa2xx-ac97.c return snd_ac97_set_rate(pxa2xx_ac97_ac97, reg, runtime->rate); reg 59 sound/atmel/ac97c.c #define ac97c_writel(chip, reg, val) \ reg 60 sound/atmel/ac97c.c __raw_writel((val), (chip)->regs + AC97C_##reg) reg 61 sound/atmel/ac97c.c #define ac97c_readl(chip, reg) \ reg 62 sound/atmel/ac97c.c __raw_readl((chip)->regs + AC97C_##reg) reg 623 sound/atmel/ac97c.c static void atmel_ac97c_write(struct snd_ac97 *ac97, unsigned short reg, reg 630 sound/atmel/ac97c.c word = (reg & 0x7f) << 16 | val; reg 644 sound/atmel/ac97c.c unsigned short reg) reg 651 sound/atmel/ac97c.c word = (0x80 | (reg & 0x7f)) << 16; reg 3091 sound/core/oss/pcm_oss.c pcm->oss.reg = 0; reg 3105 sound/core/oss/pcm_oss.c pcm->oss.reg++; reg 3110 sound/core/oss/pcm_oss.c pcm->oss.reg++; reg 3114 sound/core/oss/pcm_oss.c if (pcm->oss.reg) reg 3122 sound/core/oss/pcm_oss.c if (pcm->oss.reg) { reg 3138 sound/core/oss/pcm_oss.c pcm->oss.reg = 0; reg 94 sound/core/seq/oss/seq_oss_synth.c struct snd_seq_oss_reg *reg = SNDRV_SEQ_DEVICE_ARGPTR(dev); reg 101 sound/core/seq/oss/seq_oss_synth.c rec->synth_type = reg->type; reg 102 sound/core/seq/oss/seq_oss_synth.c rec->synth_subtype = reg->subtype; reg 103 sound/core/seq/oss/seq_oss_synth.c rec->nr_voices = reg->nvoices; reg 104 sound/core/seq/oss/seq_oss_synth.c rec->oper = reg->oper; reg 105 sound/core/seq/oss/seq_oss_synth.c rec->private_data = reg->private_data; reg 258 sound/drivers/ml403-ac97cr.c #define LM4550_RF_OK(reg) (lm4550_regfile[reg / 2].flag & LM4550_REG_OK) reg 818 sound/drivers/ml403-ac97cr.c snd_ml403_ac97cr_codec_read(struct snd_ac97 *ac97, unsigned short reg) reg 828 sound/drivers/ml403-ac97cr.c if (!LM4550_RF_OK(reg)) { reg 831 sound/drivers/ml403-ac97cr.c "ignored!\n", reg); reg 835 sound/drivers/ml403-ac97cr.c if ((lm4550_regfile[reg / 2].flag & reg 837 sound/drivers/ml403-ac97cr.c !(lm4550_regfile[reg / 2].flag & LM4550_REG_NOSHADOW)) { reg 838 sound/drivers/ml403-ac97cr.c if (lm4550_regfile[reg / 2].flag & LM4550_REG_FAKEREAD) { reg 841 sound/drivers/ml403-ac97cr.c reg, lm4550_regfile[reg / 2].def, reg 842 sound/drivers/ml403-ac97cr.c lm4550_regfile[reg / 2].def); reg 843 sound/drivers/ml403-ac97cr.c return lm4550_regfile[reg / 2].def; reg 844 sound/drivers/ml403-ac97cr.c } else if ((lm4550_regfile[reg / 2].flag & reg 849 sound/drivers/ml403-ac97cr.c reg, lm4550_regfile[reg / 2].value, reg 850 sound/drivers/ml403-ac97cr.c lm4550_regfile[reg / 2].value); reg 851 sound/drivers/ml403-ac97cr.c return lm4550_regfile[reg / 2].value; reg 857 sound/drivers/ml403-ac97cr.c reg, lm4550_regfile[reg / 2].value, reg 858 sound/drivers/ml403-ac97cr.c lm4550_regfile[reg / 2].value, reg 865 sound/drivers/ml403-ac97cr.c reg, lm4550_regfile[reg / 2].value, reg 866 sound/drivers/ml403-ac97cr.c lm4550_regfile[reg / 2].value); reg 868 sound/drivers/ml403-ac97cr.c return lm4550_regfile[reg / 2].value; reg 879 sound/drivers/ml403-ac97cr.c CR_CODEC_ADDR(reg) | CR_CODEC_READ); reg 892 sound/drivers/ml403-ac97cr.c reg, value, value, stat); reg 900 sound/drivers/ml403-ac97cr.c reg, value, value); reg 902 sound/drivers/ml403-ac97cr.c lm4550_regfile[reg / 2].value = value; reg 903 sound/drivers/ml403-ac97cr.c lm4550_regfile[reg / 2].flag |= LM4550_REG_DONEREAD; reg 921 sound/drivers/ml403-ac97cr.c reg, stat, value, value, rafaccess, reg 927 sound/drivers/ml403-ac97cr.c reg, value, value); reg 932 sound/drivers/ml403-ac97cr.c lm4550_regfile[reg / 2].value = value; reg 933 sound/drivers/ml403-ac97cr.c lm4550_regfile[reg / 2].flag |= LM4550_REG_DONEREAD; reg 939 sound/drivers/ml403-ac97cr.c snd_ml403_ac97cr_codec_write(struct snd_ac97 *ac97, unsigned short reg, reg 952 sound/drivers/ml403-ac97cr.c if (!LM4550_RF_OK(reg)) { reg 955 sound/drivers/ml403-ac97cr.c "ignored!\n", reg); reg 958 sound/drivers/ml403-ac97cr.c if (lm4550_regfile[reg / 2].flag & LM4550_REG_READONLY) { reg 961 sound/drivers/ml403-ac97cr.c "ignored!\n", reg); reg 964 sound/drivers/ml403-ac97cr.c if ((val & lm4550_regfile[reg / 2].wmask) != val) { reg 968 sound/drivers/ml403-ac97cr.c reg, val, val); reg 969 sound/drivers/ml403-ac97cr.c val = val & lm4550_regfile[reg / 2].wmask; reg 971 sound/drivers/ml403-ac97cr.c if (((lm4550_regfile[reg / 2].flag & LM4550_REG_FAKEPROBE) && reg 973 sound/drivers/ml403-ac97cr.c !(lm4550_regfile[reg / 2].flag & LM4550_REG_NOSHADOW)) { reg 975 sound/drivers/ml403-ac97cr.c "val=0x%x / %d\n", reg, val, val); reg 976 sound/drivers/ml403-ac97cr.c lm4550_regfile[reg / 2].value = (val & reg 977 sound/drivers/ml403-ac97cr.c lm4550_regfile[reg / 2].wmask); reg 989 sound/drivers/ml403-ac97cr.c CR_CODEC_ADDR(reg) | CR_CODEC_WRITE); reg 1008 sound/drivers/ml403-ac97cr.c reg, val, val); reg 1009 sound/drivers/ml403-ac97cr.c if (!(lm4550_regfile[reg / 2].flag & reg 1011 sound/drivers/ml403-ac97cr.c !(lm4550_regfile[reg / 2].flag & reg 1013 sound/drivers/ml403-ac97cr.c lm4550_regfile[reg / 2].value = val; reg 1014 sound/drivers/ml403-ac97cr.c lm4550_regfile[reg / 2].flag |= LM4550_REG_DONEREAD; reg 1027 sound/drivers/ml403-ac97cr.c reg, val, val, stat, rafaccess, ml403_ac97cr->ac97_write, reg 1032 sound/drivers/ml403-ac97cr.c reg, val, val); reg 1046 sound/drivers/ml403-ac97cr.c reg, val, val); reg 206 sound/drivers/mtpav.c static u8 snd_mtpav_getreg(struct mtpav *chip, u16 reg) reg 210 sound/drivers/mtpav.c if (reg == SREG) { reg 213 sound/drivers/mtpav.c } else if (reg == CREG) { reg 224 sound/drivers/mtpav.c static inline void snd_mtpav_mputreg(struct mtpav *chip, u16 reg, u8 val) reg 226 sound/drivers/mtpav.c if (reg == DREG || reg == CREG) reg 227 sound/drivers/mtpav.c outb(val, chip->port + reg); reg 26 sound/drivers/opl3/opl3_voice.h void snd_opl3_calc_volume(unsigned char *reg, int vel, struct snd_midi_channel *chan); reg 26 sound/drivers/opl4/opl4_lib.c void snd_opl4_write(struct snd_opl4 *opl4, u8 reg, u8 value) reg 29 sound/drivers/opl4/opl4_lib.c outb(reg, opl4->pcm_port); reg 37 sound/drivers/opl4/opl4_lib.c u8 snd_opl4_read(struct snd_opl4 *opl4, u8 reg) reg 40 sound/drivers/opl4/opl4_lib.c outb(reg, opl4->pcm_port); reg 202 sound/drivers/opl4/opl4_local.h void snd_opl4_write(struct snd_opl4 *opl4, u8 reg, u8 value); reg 203 sound/drivers/opl4/opl4_local.h u8 snd_opl4_read(struct snd_opl4 *opl4, u8 reg); reg 23 sound/drivers/opl4/opl4_mixer.c u8 reg = kcontrol->private_value; reg 27 sound/drivers/opl4/opl4_mixer.c value = snd_opl4_read(opl4, reg); reg 38 sound/drivers/opl4/opl4_mixer.c u8 reg = kcontrol->private_value; reg 44 sound/drivers/opl4/opl4_mixer.c old_value = snd_opl4_read(opl4, reg); reg 45 sound/drivers/opl4/opl4_mixer.c snd_opl4_write(opl4, reg, value); reg 39 sound/drivers/vx/vx_core.c int snd_vx_check_reg_bit(struct vx_core *chip, int reg, int mask, int bit, int time) reg 51 sound/drivers/vx/vx_core.c if ((snd_vx_inb(chip, reg) & mask) == bit) reg 55 sound/drivers/vx/vx_core.c snd_printd(KERN_DEBUG "vx_check_reg_bit: timeout, reg=%s, mask=0x%x, val=0x%x\n", reg_names[reg], mask, snd_vx_inb(chip, reg)); reg 74 sound/drivers/vx/vx_mixer.c static void vx_set_codec_reg(struct vx_core *chip, int codec, int reg, int val) reg 79 sound/drivers/vx/vx_mixer.c SET_CDC_DATA_REG(data, reg); reg 24 sound/firewire/dice/dice-alesis.c __be32 reg; reg 29 sound/firewire/dice/dice-alesis.c err = snd_dice_transaction_read_tx(dice, TX_NUMBER_AUDIO, ®, reg 30 sound/firewire/dice/dice-alesis.c sizeof(reg)); reg 33 sound/firewire/dice/dice-alesis.c data = be32_to_cpu(reg); reg 66 sound/firewire/dice/dice-extension.c __be32 reg[2]; reg 74 sound/firewire/dice/dice-extension.c reg, sizeof(reg)); reg 77 sound/firewire/dice/dice-extension.c pcm_channels[i][mode] = be32_to_cpu(reg[0]); reg 78 sound/firewire/dice/dice-extension.c midi_ports[i] = max(midi_ports[i], be32_to_cpu(reg[1])); reg 87 sound/firewire/dice/dice-extension.c __be32 reg[2]; reg 114 sound/firewire/dice/dice-extension.c ®, sizeof(reg)); reg 119 sound/firewire/dice/dice-extension.c stream_count = be32_to_cpu(reg[0]); reg 128 sound/firewire/dice/dice-extension.c stream_count = be32_to_cpu(reg[1]); reg 66 sound/firewire/dice/dice-stream.c __be32 reg, nominal; reg 72 sound/firewire/dice/dice-stream.c ®, sizeof(reg)); reg 76 sound/firewire/dice/dice-stream.c data = be32_to_cpu(reg); reg 90 sound/firewire/dice/dice-stream.c reg = cpu_to_be32(data); reg 92 sound/firewire/dice/dice-stream.c ®, sizeof(reg)); reg 118 sound/firewire/dice/dice-stream.c __be32 reg[2]; reg 121 sound/firewire/dice/dice-stream.c err = snd_dice_transaction_read_tx(dice, TX_NUMBER, reg, sizeof(reg)); reg 125 sound/firewire/dice/dice-stream.c min_t(unsigned int, be32_to_cpu(reg[0]), MAX_STREAMS); reg 126 sound/firewire/dice/dice-stream.c tx_params->size = be32_to_cpu(reg[1]) * 4; reg 128 sound/firewire/dice/dice-stream.c err = snd_dice_transaction_read_rx(dice, RX_NUMBER, reg, sizeof(reg)); reg 132 sound/firewire/dice/dice-stream.c min_t(unsigned int, be32_to_cpu(reg[0]), MAX_STREAMS); reg 133 sound/firewire/dice/dice-stream.c rx_params->size = be32_to_cpu(reg[1]) * 4; reg 151 sound/firewire/dice/dice-stream.c __be32 reg; reg 155 sound/firewire/dice/dice-stream.c reg = cpu_to_be32((u32)-1); reg 159 sound/firewire/dice/dice-stream.c ®, sizeof(reg)); reg 163 sound/firewire/dice/dice-stream.c ®, sizeof(reg)); reg 223 sound/firewire/dice/dice-stream.c __be32 reg[2]; reg 239 sound/firewire/dice/dice-stream.c reg, sizeof(reg)); reg 248 sound/firewire/dice/dice-stream.c reg, sizeof(reg)); reg 252 sound/firewire/dice/dice-stream.c pcm_chs = be32_to_cpu(reg[0]); reg 253 sound/firewire/dice/dice-stream.c midi_ports = be32_to_cpu(reg[1]); reg 345 sound/firewire/dice/dice-stream.c __be32 reg; reg 355 sound/firewire/dice/dice-stream.c reg = cpu_to_be32(resources->channel); reg 359 sound/firewire/dice/dice-stream.c ®, sizeof(reg)); reg 363 sound/firewire/dice/dice-stream.c ®, sizeof(reg)); reg 369 sound/firewire/dice/dice-stream.c reg = cpu_to_be32(max_speed); reg 372 sound/firewire/dice/dice-stream.c ®, sizeof(reg)); reg 626 sound/firewire/dice/dice-stream.c __be32 reg[2]; reg 664 sound/firewire/dice/dice-stream.c reg, sizeof(reg)); reg 667 sound/firewire/dice/dice-stream.c dice->tx_pcm_chs[i][mode] = be32_to_cpu(reg[0]); reg 669 sound/firewire/dice/dice-stream.c be32_to_cpu(reg[1]), dice->tx_midi_ports[i]); reg 674 sound/firewire/dice/dice-stream.c reg, sizeof(reg)); reg 677 sound/firewire/dice/dice-stream.c dice->rx_pcm_chs[i][mode] = be32_to_cpu(reg[0]); reg 679 sound/firewire/dice/dice-stream.c be32_to_cpu(reg[1]), dice->rx_midi_ports[i]); reg 33 sound/firewire/digi00x/digi00x-stream.c __be32 reg; reg 38 sound/firewire/digi00x/digi00x-stream.c ®, sizeof(reg), 0); reg 42 sound/firewire/digi00x/digi00x-stream.c data = be32_to_cpu(reg) & 0x0f; reg 53 sound/firewire/digi00x/digi00x-stream.c __be32 reg; reg 63 sound/firewire/digi00x/digi00x-stream.c reg = cpu_to_be32(i); reg 66 sound/firewire/digi00x/digi00x-stream.c ®, sizeof(reg), 0); reg 72 sound/firewire/digi00x/digi00x-stream.c __be32 reg; reg 77 sound/firewire/digi00x/digi00x-stream.c ®, sizeof(reg), 0); reg 81 sound/firewire/digi00x/digi00x-stream.c *clock = be32_to_cpu(reg) & 0x0f; reg 90 sound/firewire/digi00x/digi00x-stream.c __be32 reg; reg 95 sound/firewire/digi00x/digi00x-stream.c ®, sizeof(reg), 0); reg 97 sound/firewire/digi00x/digi00x-stream.c *detect = be32_to_cpu(reg) > 0; reg 106 sound/firewire/digi00x/digi00x-stream.c __be32 reg; reg 111 sound/firewire/digi00x/digi00x-stream.c ®, sizeof(reg), 0); reg 115 sound/firewire/digi00x/digi00x-stream.c data = be32_to_cpu(reg) & 0x0f; reg 76 sound/firewire/fireface/ff-protocol-former.c __le32 reg; reg 81 sound/firewire/fireface/ff-protocol-former.c FORMER_REG_CLOCK_CONFIG, ®, sizeof(reg), 0); reg 84 sound/firewire/fireface/ff-protocol-former.c data = le32_to_cpu(reg); reg 92 sound/firewire/fireface/ff-protocol-former.c __le32 *reg; reg 100 sound/firewire/fireface/ff-protocol-former.c reg = kcalloc(count, sizeof(__le32), GFP_KERNEL); reg 101 sound/firewire/fireface/ff-protocol-former.c if (!reg) reg 113 sound/firewire/fireface/ff-protocol-former.c reg[i] = cpu_to_le32(0x00000001); reg 117 sound/firewire/fireface/ff-protocol-former.c FORMER_REG_FETCH_PCM_FRAMES, reg, reg 119 sound/firewire/fireface/ff-protocol-former.c kfree(reg); reg 125 sound/firewire/fireface/ff-protocol-former.c __le32 reg; reg 133 sound/firewire/fireface/ff-protocol-former.c FORMER_REG_CLOCK_CONFIG, ®, sizeof(reg), 0); reg 136 sound/firewire/fireface/ff-protocol-former.c data = le32_to_cpu(reg); reg 197 sound/firewire/fireface/ff-protocol-former.c __le32 reg[2]; reg 203 sound/firewire/fireface/ff-protocol-former.c FORMER_REG_SYNC_STATUS, reg, sizeof(reg), 0); reg 206 sound/firewire/fireface/ff-protocol-former.c data[0] = le32_to_cpu(reg[0]); reg 207 sound/firewire/fireface/ff-protocol-former.c data[1] = le32_to_cpu(reg[1]); reg 298 sound/firewire/fireface/ff-protocol-former.c __le32 reg; reg 303 sound/firewire/fireface/ff-protocol-former.c reg = cpu_to_le32(ff->tx_stream.data_block_quadlets); reg 305 sound/firewire/fireface/ff-protocol-former.c FF800_ALLOC_TX_STREAM, ®, sizeof(reg), 0); reg 314 sound/firewire/fireface/ff-protocol-former.c FF800_TX_PACKET_ISOC_CH, ®, sizeof(reg), 0); reg 318 sound/firewire/fireface/ff-protocol-former.c data = le32_to_cpu(reg); reg 340 sound/firewire/fireface/ff-protocol-former.c __le32 reg; reg 343 sound/firewire/fireface/ff-protocol-former.c reg = cpu_to_le32(rate); reg 345 sound/firewire/fireface/ff-protocol-former.c FF800_STF, ®, sizeof(reg), 0); reg 366 sound/firewire/fireface/ff-protocol-former.c reg = cpu_to_le32(data); reg 368 sound/firewire/fireface/ff-protocol-former.c FF800_RX_PACKET_FORMAT, ®, sizeof(reg), 0); reg 378 sound/firewire/fireface/ff-protocol-former.c __le32 reg; reg 386 sound/firewire/fireface/ff-protocol-former.c reg = cpu_to_le32(0x80000000); reg 387 sound/firewire/fireface/ff-protocol-former.c reg |= cpu_to_le32(ff->tx_stream.data_block_quadlets); reg 389 sound/firewire/fireface/ff-protocol-former.c reg |= cpu_to_le32(FF800_TX_S800_FLAG); reg 391 sound/firewire/fireface/ff-protocol-former.c FF800_ISOC_COMM_START, ®, sizeof(reg), 0); reg 396 sound/firewire/fireface/ff-protocol-former.c __le32 reg; reg 398 sound/firewire/fireface/ff-protocol-former.c reg = cpu_to_le32(0x80000000); reg 400 sound/firewire/fireface/ff-protocol-former.c FF800_ISOC_COMM_STOP, ®, sizeof(reg), 0); reg 443 sound/firewire/fireface/ff-protocol-former.c __le32 reg; reg 457 sound/firewire/fireface/ff-protocol-former.c reg = cpu_to_le32(rate); reg 459 sound/firewire/fireface/ff-protocol-former.c FF400_STF, ®, sizeof(reg), 0); reg 491 sound/firewire/fireface/ff-protocol-former.c __le32 reg; reg 506 sound/firewire/fireface/ff-protocol-former.c reg = cpu_to_le32(((ff->rx_stream.data_block_quadlets << 3) << 8) | reg 509 sound/firewire/fireface/ff-protocol-former.c FF400_RX_PACKET_FORMAT, ®, sizeof(reg), 0); reg 516 sound/firewire/fireface/ff-protocol-former.c reg = cpu_to_le32((0x80 << 24) | reg 520 sound/firewire/fireface/ff-protocol-former.c FF400_TX_PACKET_FORMAT, ®, sizeof(reg), 0); reg 525 sound/firewire/fireface/ff-protocol-former.c reg = cpu_to_le32(0x00000001); reg 527 sound/firewire/fireface/ff-protocol-former.c FF400_ISOC_COMM_START, ®, sizeof(reg), 0); reg 532 sound/firewire/fireface/ff-protocol-former.c __le32 reg; reg 534 sound/firewire/fireface/ff-protocol-former.c reg = cpu_to_le32(0x80000000); reg 536 sound/firewire/fireface/ff-protocol-former.c FF400_ISOC_COMM_STOP, ®, sizeof(reg), 0); reg 72 sound/firewire/fireface/ff-protocol-latter.c __le32 reg; reg 77 sound/firewire/fireface/ff-protocol-latter.c LATTER_SYNC_STATUS, ®, sizeof(reg), 0); reg 80 sound/firewire/fireface/ff-protocol-latter.c data = le32_to_cpu(reg); reg 88 sound/firewire/fireface/ff-protocol-latter.c __le32 reg; reg 94 sound/firewire/fireface/ff-protocol-latter.c reg = cpu_to_le32(data); reg 97 sound/firewire/fireface/ff-protocol-latter.c LATTER_FETCH_MODE, ®, sizeof(reg), 0); reg 104 sound/firewire/fireface/ff-protocol-latter.c __le32 reg; reg 124 sound/firewire/fireface/ff-protocol-latter.c reg = cpu_to_le32(code); reg 126 sound/firewire/fireface/ff-protocol-latter.c LATTER_STF, ®, sizeof(reg), 0); reg 181 sound/firewire/fireface/ff-protocol-latter.c __le32 reg; reg 204 sound/firewire/fireface/ff-protocol-latter.c reg = cpu_to_le32(data); reg 206 sound/firewire/fireface/ff-protocol-latter.c LATTER_ISOC_CHANNELS, ®, sizeof(reg), 0); reg 212 sound/firewire/fireface/ff-protocol-latter.c reg = cpu_to_le32(flag); reg 214 sound/firewire/fireface/ff-protocol-latter.c LATTER_ISOC_START, ®, sizeof(reg), 0); reg 219 sound/firewire/fireface/ff-protocol-latter.c __le32 reg; reg 221 sound/firewire/fireface/ff-protocol-latter.c reg = cpu_to_le32(0x00000000); reg 223 sound/firewire/fireface/ff-protocol-latter.c LATTER_ISOC_START, ®, sizeof(reg), 0); reg 237 sound/firewire/fireface/ff-protocol-latter.c __le32 reg; reg 246 sound/firewire/fireface/ff-protocol-latter.c LATTER_SYNC_STATUS, ®, sizeof(reg), 0); reg 249 sound/firewire/fireface/ff-protocol-latter.c data = le32_to_cpu(reg); reg 178 sound/firewire/fireface/ff-transaction.c __le32 reg; reg 185 sound/firewire/fireface/ff-transaction.c reg = cpu_to_le32(addr); reg 188 sound/firewire/fireface/ff-transaction.c ®, sizeof(reg), 0); reg 219 sound/firewire/fireface/ff-transaction.c __le32 reg; reg 226 sound/firewire/fireface/ff-transaction.c reg = cpu_to_le32(0x00000000); reg 229 sound/firewire/fireface/ff-transaction.c ®, sizeof(reg), 0); reg 31 sound/firewire/motu/motu-protocol-v2.c __be32 reg; reg 35 sound/firewire/motu/motu-protocol-v2.c err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®, reg 36 sound/firewire/motu/motu-protocol-v2.c sizeof(reg)); reg 40 sound/firewire/motu/motu-protocol-v2.c index = (be32_to_cpu(reg) & V2_CLOCK_RATE_MASK) >> V2_CLOCK_RATE_SHIFT; reg 51 sound/firewire/motu/motu-protocol-v2.c __be32 reg; reg 63 sound/firewire/motu/motu-protocol-v2.c err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®, reg 64 sound/firewire/motu/motu-protocol-v2.c sizeof(reg)); reg 67 sound/firewire/motu/motu-protocol-v2.c data = be32_to_cpu(reg); reg 77 sound/firewire/motu/motu-protocol-v2.c reg = cpu_to_be32(data); reg 78 sound/firewire/motu/motu-protocol-v2.c return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET, ®, reg 79 sound/firewire/motu/motu-protocol-v2.c sizeof(reg)); reg 85 sound/firewire/motu/motu-protocol-v2.c __be32 reg; reg 89 sound/firewire/motu/motu-protocol-v2.c err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®, reg 90 sound/firewire/motu/motu-protocol-v2.c sizeof(reg)); reg 94 sound/firewire/motu/motu-protocol-v2.c index = be32_to_cpu(reg) & V2_CLOCK_SRC_MASK; reg 99 sound/firewire/motu/motu-protocol-v2.c err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET, ®, reg 100 sound/firewire/motu/motu-protocol-v2.c sizeof(reg)); reg 109 sound/firewire/motu/motu-protocol-v2.c if (be32_to_cpu(reg) & 0x00000200) reg 132 sound/firewire/motu/motu-protocol-v2.c __be32 reg; reg 139 sound/firewire/motu/motu-protocol-v2.c ®, sizeof(reg)); reg 142 sound/firewire/motu/motu-protocol-v2.c data = be32_to_cpu(reg); reg 162 sound/firewire/motu/motu-protocol-v2.c reg = cpu_to_be32(data); reg 164 sound/firewire/motu/motu-protocol-v2.c ®, sizeof(reg)); reg 254 sound/firewire/motu/motu-protocol-v2.c __be32 reg; reg 258 sound/firewire/motu/motu-protocol-v2.c err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET, ®, reg 259 sound/firewire/motu/motu-protocol-v2.c sizeof(reg)); reg 262 sound/firewire/motu/motu-protocol-v2.c data = be32_to_cpu(reg); reg 29 sound/firewire/motu/motu-protocol-v3.c __be32 reg; reg 33 sound/firewire/motu/motu-protocol-v3.c err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®, reg 34 sound/firewire/motu/motu-protocol-v3.c sizeof(reg)); reg 37 sound/firewire/motu/motu-protocol-v3.c data = be32_to_cpu(reg); reg 50 sound/firewire/motu/motu-protocol-v3.c __be32 reg; reg 62 sound/firewire/motu/motu-protocol-v3.c err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®, reg 63 sound/firewire/motu/motu-protocol-v3.c sizeof(reg)); reg 66 sound/firewire/motu/motu-protocol-v3.c data = be32_to_cpu(reg); reg 71 sound/firewire/motu/motu-protocol-v3.c need_to_wait = data != be32_to_cpu(reg); reg 73 sound/firewire/motu/motu-protocol-v3.c reg = cpu_to_be32(data); reg 74 sound/firewire/motu/motu-protocol-v3.c err = snd_motu_transaction_write(motu, V3_CLOCK_STATUS_OFFSET, ®, reg 75 sound/firewire/motu/motu-protocol-v3.c sizeof(reg)); reg 91 sound/firewire/motu/motu-protocol-v3.c __be32 reg; reg 96 sound/firewire/motu/motu-protocol-v3.c err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®, reg 97 sound/firewire/motu/motu-protocol-v3.c sizeof(reg)); reg 100 sound/firewire/motu/motu-protocol-v3.c data = be32_to_cpu(reg); reg 111 sound/firewire/motu/motu-protocol-v3.c ®, sizeof(reg)); reg 114 sound/firewire/motu/motu-protocol-v3.c data = be32_to_cpu(reg); reg 136 sound/firewire/motu/motu-protocol-v3.c __be32 reg; reg 140 sound/firewire/motu/motu-protocol-v3.c err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, ®, reg 141 sound/firewire/motu/motu-protocol-v3.c sizeof(reg)); reg 144 sound/firewire/motu/motu-protocol-v3.c data = be32_to_cpu(reg); reg 151 sound/firewire/motu/motu-protocol-v3.c reg = cpu_to_be32(data); reg 152 sound/firewire/motu/motu-protocol-v3.c return snd_motu_transaction_write(motu, V3_CLOCK_STATUS_OFFSET, ®, reg 153 sound/firewire/motu/motu-protocol-v3.c sizeof(reg)); reg 278 sound/firewire/motu/motu-protocol-v3.c __be32 reg; reg 282 sound/firewire/motu/motu-protocol-v3.c err = snd_motu_transaction_read(motu, V3_OPT_IFACE_MODE_OFFSET, ®, reg 283 sound/firewire/motu/motu-protocol-v3.c sizeof(reg)); reg 286 sound/firewire/motu/motu-protocol-v3.c data = be32_to_cpu(reg); reg 64 sound/firewire/motu/motu-stream.c __be32 reg; reg 69 sound/firewire/motu/motu-stream.c err = snd_motu_transaction_read(motu, ISOC_COMM_CONTROL_OFFSET, ®, reg 70 sound/firewire/motu/motu-stream.c sizeof(reg)); reg 73 sound/firewire/motu/motu-stream.c data = be32_to_cpu(reg) & ~ISOC_COMM_CONTROL_MASK; reg 80 sound/firewire/motu/motu-stream.c reg = cpu_to_be32(data); reg 81 sound/firewire/motu/motu-stream.c return snd_motu_transaction_write(motu, ISOC_COMM_CONTROL_OFFSET, ®, reg 82 sound/firewire/motu/motu-stream.c sizeof(reg)); reg 87 sound/firewire/motu/motu-stream.c __be32 reg; reg 95 sound/firewire/motu/motu-stream.c err = snd_motu_transaction_read(motu, ISOC_COMM_CONTROL_OFFSET, ®, reg 96 sound/firewire/motu/motu-stream.c sizeof(reg)); reg 99 sound/firewire/motu/motu-stream.c data = be32_to_cpu(reg); reg 104 sound/firewire/motu/motu-stream.c reg = cpu_to_be32(data); reg 105 sound/firewire/motu/motu-stream.c snd_motu_transaction_write(motu, ISOC_COMM_CONTROL_OFFSET, ®, reg 106 sound/firewire/motu/motu-stream.c sizeof(reg)); reg 181 sound/firewire/motu/motu-stream.c __be32 reg; reg 185 sound/firewire/motu/motu-stream.c err = snd_motu_transaction_read(motu, PACKET_FORMAT_OFFSET, ®, reg 186 sound/firewire/motu/motu-stream.c sizeof(reg)); reg 189 sound/firewire/motu/motu-stream.c data = be32_to_cpu(reg); reg 200 sound/firewire/motu/motu-stream.c reg = cpu_to_be32(data); reg 201 sound/firewire/motu/motu-stream.c return snd_motu_transaction_write(motu, PACKET_FORMAT_OFFSET, ®, reg 202 sound/firewire/motu/motu-stream.c sizeof(reg)); reg 15 sound/firewire/motu/motu-transaction.c int snd_motu_transaction_read(struct snd_motu *motu, u32 offset, __be32 *reg, reg 28 sound/firewire/motu/motu-transaction.c SND_MOTU_ADDR_BASE + offset, reg, size, 0); reg 31 sound/firewire/motu/motu-transaction.c int snd_motu_transaction_write(struct snd_motu *motu, u32 offset, __be32 *reg, reg 44 sound/firewire/motu/motu-transaction.c SND_MOTU_ADDR_BASE + offset, reg, size, 0); reg 146 sound/firewire/motu/motu.h int snd_motu_transaction_read(struct snd_motu *motu, u32 offset, __be32 *reg, reg 148 sound/firewire/motu/motu.h int snd_motu_transaction_write(struct snd_motu *motu, u32 offset, __be32 *reg, reg 15 sound/firewire/tascam/tascam-proc.c unsigned int reg, fpga, arm, hw; reg 23 sound/firewire/tascam/tascam-proc.c reg = be32_to_cpu(data); reg 46 sound/firewire/tascam/tascam-proc.c snd_iprintf(buffer, "Register: %d (0x%08x)\n", reg & 0xffff, reg); reg 19 sound/firewire/tascam/tascam-stream.c __be32 reg; reg 25 sound/firewire/tascam/tascam-stream.c ®, sizeof(reg), 0); reg 29 sound/firewire/tascam/tascam-stream.c *data = be32_to_cpu(reg); reg 48 sound/firewire/tascam/tascam-stream.c __be32 reg; reg 79 sound/firewire/tascam/tascam-stream.c reg = cpu_to_be32(data); reg 83 sound/firewire/tascam/tascam-stream.c ®, sizeof(reg), 0); reg 88 sound/firewire/tascam/tascam-stream.c reg = cpu_to_be32(0x0000001a); reg 90 sound/firewire/tascam/tascam-stream.c reg = cpu_to_be32(0x0000000d); reg 94 sound/firewire/tascam/tascam-stream.c ®, sizeof(reg), 0); reg 143 sound/firewire/tascam/tascam-stream.c __be32 reg; reg 156 sound/firewire/tascam/tascam-stream.c reg = cpu_to_be32(data); reg 159 sound/firewire/tascam/tascam-stream.c ®, sizeof(reg), 0); reg 171 sound/firewire/tascam/tascam-stream.c reg = cpu_to_be32(data); reg 174 sound/firewire/tascam/tascam-stream.c ®, sizeof(reg), 0); reg 179 sound/firewire/tascam/tascam-stream.c __be32 reg; reg 183 sound/firewire/tascam/tascam-stream.c reg = cpu_to_be32(0x00200000); reg 186 sound/firewire/tascam/tascam-stream.c ®, sizeof(reg), 0); reg 195 sound/firewire/tascam/tascam-stream.c __be32 reg; reg 197 sound/firewire/tascam/tascam-stream.c reg = 0; reg 200 sound/firewire/tascam/tascam-stream.c ®, sizeof(reg), 0); reg 202 sound/firewire/tascam/tascam-stream.c reg = 0; reg 205 sound/firewire/tascam/tascam-stream.c ®, sizeof(reg), 0); reg 208 sound/firewire/tascam/tascam-stream.c reg = cpu_to_be32(0x00000000); reg 211 sound/firewire/tascam/tascam-stream.c ®, sizeof(reg), 0); reg 212 sound/firewire/tascam/tascam-stream.c reg = cpu_to_be32(0x00000000); reg 215 sound/firewire/tascam/tascam-stream.c ®, sizeof(reg), 0); reg 216 sound/firewire/tascam/tascam-stream.c reg = cpu_to_be32(0x00000000); reg 219 sound/firewire/tascam/tascam-stream.c ®, sizeof(reg), 0); reg 224 sound/firewire/tascam/tascam-stream.c __be32 reg; reg 228 sound/firewire/tascam/tascam-stream.c reg = cpu_to_be32(tscm->tx_resources.channel); reg 231 sound/firewire/tascam/tascam-stream.c ®, sizeof(reg), 0); reg 236 sound/firewire/tascam/tascam-stream.c reg = cpu_to_be32(0x00000002); reg 239 sound/firewire/tascam/tascam-stream.c ®, sizeof(reg), 0); reg 244 sound/firewire/tascam/tascam-stream.c reg = cpu_to_be32(tscm->rx_resources.channel); reg 247 sound/firewire/tascam/tascam-stream.c ®, sizeof(reg), 0); reg 251 sound/firewire/tascam/tascam-stream.c reg = cpu_to_be32(0x00000001); reg 254 sound/firewire/tascam/tascam-stream.c ®, sizeof(reg), 0); reg 258 sound/firewire/tascam/tascam-stream.c reg = cpu_to_be32(0x00000001); reg 261 sound/firewire/tascam/tascam-stream.c ®, sizeof(reg), 0); reg 266 sound/firewire/tascam/tascam-stream.c reg = cpu_to_be32(0x00002000); reg 269 sound/firewire/tascam/tascam-stream.c ®, sizeof(reg), 0); reg 274 sound/firewire/tascam/tascam-stream.c reg = cpu_to_be32(0x00000001); reg 278 sound/firewire/tascam/tascam-stream.c ®, sizeof(reg), 0); reg 336 sound/firewire/tascam/tascam-transaction.c __be32 reg; reg 340 sound/firewire/tascam/tascam-transaction.c reg = cpu_to_be32((device->card->node_id << 16) | reg 344 sound/firewire/tascam/tascam-transaction.c ®, sizeof(reg), 0); reg 348 sound/firewire/tascam/tascam-transaction.c reg = cpu_to_be32(tscm->async_handler.offset); reg 351 sound/firewire/tascam/tascam-transaction.c ®, sizeof(reg), 0); reg 356 sound/firewire/tascam/tascam-transaction.c reg = cpu_to_be32(0x00000001); reg 359 sound/firewire/tascam/tascam-transaction.c ®, sizeof(reg), 0); reg 364 sound/firewire/tascam/tascam-transaction.c reg = cpu_to_be32(0x0001008e); reg 367 sound/firewire/tascam/tascam-transaction.c ®, sizeof(reg), 0); reg 372 sound/firewire/tascam/tascam-transaction.c __be32 reg; reg 378 sound/firewire/tascam/tascam-transaction.c reg = cpu_to_be32(0x0000008e); reg 381 sound/firewire/tascam/tascam-transaction.c ®, sizeof(reg), 0); reg 384 sound/firewire/tascam/tascam-transaction.c reg = cpu_to_be32(0x00000000); reg 387 sound/firewire/tascam/tascam-transaction.c ®, sizeof(reg), 0); reg 392 sound/firewire/tascam/tascam-transaction.c ®, sizeof(reg), 0); reg 395 sound/firewire/tascam/tascam-transaction.c ®, sizeof(reg), 0); reg 37 sound/hda/hdac_regmap.c #define get_verb(reg) (((reg) >> 8) & 0xfff) reg 39 sound/hda/hdac_regmap.c static bool hda_volatile_reg(struct device *dev, unsigned int reg) reg 42 sound/hda/hdac_regmap.c unsigned int verb = get_verb(reg); reg 66 sound/hda/hdac_regmap.c static bool hda_writeable_reg(struct device *dev, unsigned int reg) reg 69 sound/hda/hdac_regmap.c unsigned int verb = get_verb(reg); reg 115 sound/hda/hdac_regmap.c static bool hda_readable_reg(struct device *dev, unsigned int reg) reg 118 sound/hda/hdac_regmap.c unsigned int verb = get_verb(reg); reg 137 sound/hda/hdac_regmap.c return hda_writeable_reg(dev, reg); reg 148 sound/hda/hdac_regmap.c static bool is_stereo_amp_verb(unsigned int reg) reg 150 sound/hda/hdac_regmap.c if (((reg >> 8) & 0x700) != AC_VERB_SET_AMP_GAIN_MUTE) reg 152 sound/hda/hdac_regmap.c return (reg & (AC_AMP_SET_LEFT | AC_AMP_SET_RIGHT)) == reg 158 sound/hda/hdac_regmap.c unsigned int reg, unsigned int *val) reg 163 sound/hda/hdac_regmap.c reg &= ~(AC_AMP_SET_LEFT | AC_AMP_SET_RIGHT); reg 164 sound/hda/hdac_regmap.c err = snd_hdac_exec_verb(codec, reg | AC_AMP_GET_LEFT, 0, &left); reg 167 sound/hda/hdac_regmap.c err = snd_hdac_exec_verb(codec, reg | AC_AMP_GET_RIGHT, 0, &right); reg 176 sound/hda/hdac_regmap.c unsigned int reg, unsigned int val) reg 182 sound/hda/hdac_regmap.c if (reg & AC_AMP_GET_OUTPUT) reg 185 sound/hda/hdac_regmap.c verb |= AC_AMP_SET_INPUT | ((reg & 0xf) << 8); reg 186 sound/hda/hdac_regmap.c reg = (reg & ~0xfffff) | verb; reg 191 sound/hda/hdac_regmap.c reg |= AC_AMP_SET_LEFT | AC_AMP_SET_RIGHT; reg 192 sound/hda/hdac_regmap.c return snd_hdac_exec_verb(codec, reg | left, 0, NULL); reg 195 sound/hda/hdac_regmap.c err = snd_hdac_exec_verb(codec, reg | AC_AMP_SET_LEFT | left, 0, NULL); reg 198 sound/hda/hdac_regmap.c err = snd_hdac_exec_verb(codec, reg | AC_AMP_SET_RIGHT | right, 0, NULL); reg 205 sound/hda/hdac_regmap.c static int hda_reg_read_coef(struct hdac_device *codec, unsigned int reg, reg 214 sound/hda/hdac_regmap.c verb = (reg & ~0xfff00) | (AC_VERB_SET_COEF_INDEX << 8); reg 218 sound/hda/hdac_regmap.c verb = (reg & ~0xfffff) | (AC_VERB_GET_COEF_INDEX << 8); reg 223 sound/hda/hdac_regmap.c static int hda_reg_write_coef(struct hdac_device *codec, unsigned int reg, reg 232 sound/hda/hdac_regmap.c verb = (reg & ~0xfff00) | (AC_VERB_SET_COEF_INDEX << 8); reg 236 sound/hda/hdac_regmap.c verb = (reg & ~0xfffff) | (AC_VERB_GET_COEF_INDEX << 8) | reg 241 sound/hda/hdac_regmap.c static int hda_reg_read(void *context, unsigned int reg, unsigned int *val) reg 244 sound/hda/hdac_regmap.c int verb = get_verb(reg); reg 253 sound/hda/hdac_regmap.c reg |= (codec->addr << 28); reg 254 sound/hda/hdac_regmap.c if (is_stereo_amp_verb(reg)) { reg 255 sound/hda/hdac_regmap.c err = hda_reg_read_stereo_amp(codec, reg, val); reg 259 sound/hda/hdac_regmap.c err = hda_reg_read_coef(codec, reg, val); reg 263 sound/hda/hdac_regmap.c reg &= ~AC_AMP_FAKE_MUTE; reg 265 sound/hda/hdac_regmap.c err = snd_hdac_exec_verb(codec, reg, 0, val); reg 280 sound/hda/hdac_regmap.c static int hda_reg_write(void *context, unsigned int reg, unsigned int val) reg 290 sound/hda/hdac_regmap.c reg &= ~0x00080000U; /* drop GET bit */ reg 291 sound/hda/hdac_regmap.c reg |= (codec->addr << 28); reg 292 sound/hda/hdac_regmap.c verb = get_verb(reg); reg 300 sound/hda/hdac_regmap.c if (is_stereo_amp_verb(reg)) { reg 301 sound/hda/hdac_regmap.c err = hda_reg_write_stereo_amp(codec, reg, val); reg 306 sound/hda/hdac_regmap.c err = hda_reg_write_coef(codec, reg, val); reg 312 sound/hda/hdac_regmap.c if ((reg & AC_AMP_FAKE_MUTE) && (val & AC_AMP_MUTE)) reg 315 sound/hda/hdac_regmap.c if (reg & AC_AMP_GET_LEFT) reg 319 sound/hda/hdac_regmap.c if (reg & AC_AMP_GET_OUTPUT) { reg 323 sound/hda/hdac_regmap.c verb |= reg & 0xf; reg 341 sound/hda/hdac_regmap.c reg &= ~0xfffff; reg 342 sound/hda/hdac_regmap.c reg |= (verb + i) << 8 | ((val >> (8 * i)) & 0xff); reg 343 sound/hda/hdac_regmap.c err = snd_hdac_exec_verb(codec, reg, 0, NULL); reg 426 sound/hda/hdac_regmap.c static int reg_raw_write(struct hdac_device *codec, unsigned int reg, reg 433 sound/hda/hdac_regmap.c err = hda_reg_write(codec, reg, val); reg 435 sound/hda/hdac_regmap.c err = regmap_write(codec->regmap, reg, val); reg 460 sound/hda/hdac_regmap.c int snd_hdac_regmap_write_raw(struct hdac_device *codec, unsigned int reg, reg 463 sound/hda/hdac_regmap.c return CALL_RAW_FUNC(codec, reg_raw_write(codec, reg, val)); reg 467 sound/hda/hdac_regmap.c static int reg_raw_read(struct hdac_device *codec, unsigned int reg, reg 474 sound/hda/hdac_regmap.c err = hda_reg_read(codec, reg, val); reg 476 sound/hda/hdac_regmap.c err = regmap_read(codec->regmap, reg, val); reg 482 sound/hda/hdac_regmap.c unsigned int reg, unsigned int *val, reg 485 sound/hda/hdac_regmap.c return CALL_RAW_FUNC(codec, reg_raw_read(codec, reg, val, uncached)); reg 496 sound/hda/hdac_regmap.c int snd_hdac_regmap_read_raw(struct hdac_device *codec, unsigned int reg, reg 499 sound/hda/hdac_regmap.c return __snd_hdac_regmap_read_raw(codec, reg, val, false); reg 507 sound/hda/hdac_regmap.c unsigned int reg, unsigned int *val) reg 509 sound/hda/hdac_regmap.c return __snd_hdac_regmap_read_raw(codec, reg, val, true); reg 512 sound/hda/hdac_regmap.c static int reg_raw_update(struct hdac_device *codec, unsigned int reg, reg 521 sound/hda/hdac_regmap.c err = regmap_update_bits_check(codec->regmap, reg, mask, val, reg 526 sound/hda/hdac_regmap.c err = hda_reg_read(codec, reg, &orig); reg 531 sound/hda/hdac_regmap.c err = hda_reg_write(codec, reg, val); reg 550 sound/hda/hdac_regmap.c int snd_hdac_regmap_update_raw(struct hdac_device *codec, unsigned int reg, reg 553 sound/hda/hdac_regmap.c return CALL_RAW_FUNC(codec, reg_raw_update(codec, reg, mask, val)); reg 557 sound/hda/hdac_regmap.c static int reg_raw_update_once(struct hdac_device *codec, unsigned int reg, reg 564 sound/hda/hdac_regmap.c return reg_raw_update(codec, reg, mask, val); reg 568 sound/hda/hdac_regmap.c err = regmap_read(codec->regmap, reg, &orig); reg 571 sound/hda/hdac_regmap.c err = regmap_update_bits(codec->regmap, reg, mask, val); reg 587 sound/hda/hdac_regmap.c int snd_hdac_regmap_update_raw_once(struct hdac_device *codec, unsigned int reg, reg 590 sound/hda/hdac_regmap.c return CALL_RAW_FUNC(codec, reg_raw_update_once(codec, reg, mask, val)); reg 596 sound/hda/hdac_stream.c unsigned int streams, unsigned int reg) reg 601 sound/hda/hdac_stream.c if (!reg) reg 602 sound/hda/hdac_stream.c reg = AZX_REG_SSYNC; reg 603 sound/hda/hdac_stream.c val = _snd_hdac_chip_readl(bus, reg); reg 608 sound/hda/hdac_stream.c _snd_hdac_chip_writel(bus, reg, val); reg 45 sound/i2c/cs8427.c int snd_cs8427_reg_write(struct snd_i2c_device *device, unsigned char reg, reg 51 sound/i2c/cs8427.c buf[0] = reg & 0x7f; reg 63 sound/i2c/cs8427.c static int snd_cs8427_reg_read(struct snd_i2c_device *device, unsigned char reg) reg 68 sound/i2c/cs8427.c if ((err = snd_i2c_sendbytes(device, ®, 1)) != 1) { reg 70 sound/i2c/cs8427.c "to CS8427\n", reg); reg 75 sound/i2c/cs8427.c "from CS8427\n", reg); reg 382 sound/i2c/cs8427.c unsigned char reg = CS8427_REG_QSUBCODE; reg 386 sound/i2c/cs8427.c if ((err = snd_i2c_sendbytes(device, ®, 1)) != 1) { reg 388 sound/i2c/cs8427.c "to CS8427\n", reg); reg 29 sound/i2c/other/ak4113.c static void reg_write(struct ak4113 *ak4113, unsigned char reg, reg 32 sound/i2c/other/ak4113.c ak4113->write(ak4113->private_data, reg, val); reg 33 sound/i2c/other/ak4113.c if (reg < sizeof(ak4113->regmap)) reg 34 sound/i2c/other/ak4113.c ak4113->regmap[reg] = val; reg 37 sound/i2c/other/ak4113.c static inline unsigned char reg_read(struct ak4113 *ak4113, unsigned char reg) reg 39 sound/i2c/other/ak4113.c return ak4113->read(ak4113->private_data, reg); reg 62 sound/i2c/other/ak4113.c unsigned char reg; reg 79 sound/i2c/other/ak4113.c for (reg = 0; reg < AK4113_WRITABLE_REGS ; reg++) reg 80 sound/i2c/other/ak4113.c chip->regmap[reg] = pgm[reg]; reg 101 sound/i2c/other/ak4113.c void snd_ak4113_reg_write(struct ak4113 *chip, unsigned char reg, reg 104 sound/i2c/other/ak4113.c if (reg >= AK4113_WRITABLE_REGS) reg 106 sound/i2c/other/ak4113.c reg_write(chip, reg, (chip->regmap[reg] & ~mask) | val); reg 112 sound/i2c/other/ak4113.c unsigned char old = chip->regmap[AK4113_REG_PWRDN], reg; reg 120 sound/i2c/other/ak4113.c for (reg = 1; reg < AK4113_WRITABLE_REGS; reg++) reg 121 sound/i2c/other/ak4113.c reg_write(chip, reg, chip->regmap[reg]); reg 202 sound/i2c/other/ak4113.c unsigned char reg = kcontrol->private_value & 0xff; reg 207 sound/i2c/other/ak4113.c ((reg_read(chip, reg) & (1 << bit)) ? 1 : 0) ^ inv; reg 470 sound/i2c/other/ak4113.c int reg, val; reg 472 sound/i2c/other/ak4113.c for (reg = 0; reg < 0x1d; reg++) { reg 473 sound/i2c/other/ak4113.c val = reg_read(ak4113, reg); reg 474 sound/i2c/other/ak4113.c snd_iprintf(buffer, "0x%02x = 0x%02x\n", reg, val); reg 27 sound/i2c/other/ak4114.c static void reg_write(struct ak4114 *ak4114, unsigned char reg, unsigned char val) reg 29 sound/i2c/other/ak4114.c ak4114->write(ak4114->private_data, reg, val); reg 30 sound/i2c/other/ak4114.c if (reg <= AK4114_REG_INT1_MASK) reg 31 sound/i2c/other/ak4114.c ak4114->regmap[reg] = val; reg 32 sound/i2c/other/ak4114.c else if (reg >= AK4114_REG_TXCSB0 && reg <= AK4114_REG_TXCSB4) reg 33 sound/i2c/other/ak4114.c ak4114->txcsb[reg-AK4114_REG_TXCSB0] = val; reg 36 sound/i2c/other/ak4114.c static inline unsigned char reg_read(struct ak4114 *ak4114, unsigned char reg) reg 38 sound/i2c/other/ak4114.c return ak4114->read(ak4114->private_data, reg); reg 73 sound/i2c/other/ak4114.c unsigned char reg; reg 90 sound/i2c/other/ak4114.c for (reg = 0; reg < 6; reg++) reg 91 sound/i2c/other/ak4114.c chip->regmap[reg] = pgm[reg]; reg 92 sound/i2c/other/ak4114.c for (reg = 0; reg < 5; reg++) reg 93 sound/i2c/other/ak4114.c chip->txcsb[reg] = txcsb[reg]; reg 113 sound/i2c/other/ak4114.c void snd_ak4114_reg_write(struct ak4114 *chip, unsigned char reg, unsigned char mask, unsigned char val) reg 115 sound/i2c/other/ak4114.c if (reg <= AK4114_REG_INT1_MASK) reg 116 sound/i2c/other/ak4114.c reg_write(chip, reg, (chip->regmap[reg] & ~mask) | val); reg 117 sound/i2c/other/ak4114.c else if (reg >= AK4114_REG_TXCSB0 && reg <= AK4114_REG_TXCSB4) reg 118 sound/i2c/other/ak4114.c reg_write(chip, reg, reg 119 sound/i2c/other/ak4114.c (chip->txcsb[reg-AK4114_REG_TXCSB0] & ~mask) | val); reg 125 sound/i2c/other/ak4114.c unsigned char old = chip->regmap[AK4114_REG_PWRDN], reg; reg 133 sound/i2c/other/ak4114.c for (reg = 1; reg < 6; reg++) reg 134 sound/i2c/other/ak4114.c reg_write(chip, reg, chip->regmap[reg]); reg 135 sound/i2c/other/ak4114.c for (reg = 0; reg < 5; reg++) reg 136 sound/i2c/other/ak4114.c reg_write(chip, reg + AK4114_REG_TXCSB0, chip->txcsb[reg]); reg 197 sound/i2c/other/ak4114.c unsigned char reg = kcontrol->private_value & 0xff; reg 201 sound/i2c/other/ak4114.c ucontrol->value.integer.value[0] = ((reg_read(chip, reg) & (1 << bit)) ? 1 : 0) ^ inv; reg 443 sound/i2c/other/ak4114.c int reg, val; reg 445 sound/i2c/other/ak4114.c for (reg = 0; reg < 0x20; reg++) { reg 446 sound/i2c/other/ak4114.c val = reg_read(ak4114, reg); reg 447 sound/i2c/other/ak4114.c snd_iprintf(buffer, "0x%02x = 0x%02x\n", reg, val); reg 25 sound/i2c/other/ak4117.c static void reg_write(struct ak4117 *ak4117, unsigned char reg, unsigned char val) reg 27 sound/i2c/other/ak4117.c ak4117->write(ak4117->private_data, reg, val); reg 28 sound/i2c/other/ak4117.c if (reg < sizeof(ak4117->regmap)) reg 29 sound/i2c/other/ak4117.c ak4117->regmap[reg] = val; reg 32 sound/i2c/other/ak4117.c static inline unsigned char reg_read(struct ak4117 *ak4117, unsigned char reg) reg 34 sound/i2c/other/ak4117.c return ak4117->read(ak4117->private_data, reg); reg 66 sound/i2c/other/ak4117.c unsigned char reg; reg 81 sound/i2c/other/ak4117.c for (reg = 0; reg < 5; reg++) reg 82 sound/i2c/other/ak4117.c chip->regmap[reg] = pgm[reg]; reg 101 sound/i2c/other/ak4117.c void snd_ak4117_reg_write(struct ak4117 *chip, unsigned char reg, unsigned char mask, unsigned char val) reg 103 sound/i2c/other/ak4117.c if (reg >= 5) reg 105 sound/i2c/other/ak4117.c reg_write(chip, reg, (chip->regmap[reg] & ~mask) | val); reg 110 sound/i2c/other/ak4117.c unsigned char old = chip->regmap[AK4117_REG_PWRDN], reg; reg 120 sound/i2c/other/ak4117.c for (reg = 1; reg < 5; reg++) reg 121 sound/i2c/other/ak4117.c reg_write(chip, reg, chip->regmap[reg]); reg 171 sound/i2c/other/ak4117.c unsigned char reg = kcontrol->private_value & 0xff; reg 175 sound/i2c/other/ak4117.c ucontrol->value.integer.value[0] = ((reg_read(chip, reg) & (1 << bit)) ? 1 : 0) ^ inv; reg 26 sound/i2c/other/ak4xxx-adda.c void snd_akm4xxx_write(struct snd_akm4xxx *ak, int chip, unsigned char reg, reg 30 sound/i2c/other/ak4xxx-adda.c ak->ops.write(ak, chip, reg, val); reg 33 sound/i2c/other/ak4xxx-adda.c snd_akm4xxx_set(ak, chip, reg, val); reg 43 sound/i2c/other/ak4xxx-adda.c unsigned char reg; reg 50 sound/i2c/other/ak4xxx-adda.c for (reg = 0x04; reg < ak->total_regs; reg++) reg 51 sound/i2c/other/ak4xxx-adda.c snd_akm4xxx_write(ak, chip, reg, reg 52 sound/i2c/other/ak4xxx-adda.c snd_akm4xxx_get(ak, chip, reg)); reg 59 sound/i2c/other/ak4xxx-adda.c unsigned char reg; reg 65 sound/i2c/other/ak4xxx-adda.c for (reg = 0x00; reg < ak->total_regs; reg++) reg 66 sound/i2c/other/ak4xxx-adda.c if (reg != 0x01) reg 67 sound/i2c/other/ak4xxx-adda.c snd_akm4xxx_write(ak, 0, reg, reg 68 sound/i2c/other/ak4xxx-adda.c snd_akm4xxx_get(ak, 0, reg)); reg 76 sound/i2c/other/ak4xxx-adda.c unsigned char reg; reg 81 sound/i2c/other/ak4xxx-adda.c for (reg = 0x01; reg < ak->total_regs; reg++) reg 82 sound/i2c/other/ak4xxx-adda.c snd_akm4xxx_write(ak, chip, reg, reg 83 sound/i2c/other/ak4xxx-adda.c snd_akm4xxx_get(ak, chip, reg)); reg 262 sound/i2c/other/ak4xxx-adda.c unsigned char reg, data; reg 324 sound/i2c/other/ak4xxx-adda.c reg = *ptr++; reg 326 sound/i2c/other/ak4xxx-adda.c snd_akm4xxx_write(ak, chip, reg, data); reg 853 sound/i2c/other/ak4xxx-adda.c int reg, val, chip; reg 855 sound/i2c/other/ak4xxx-adda.c for (reg = 0; reg < ak->total_regs; reg++) { reg 856 sound/i2c/other/ak4xxx-adda.c val = snd_akm4xxx_get(ak, chip, reg); reg 858 sound/i2c/other/ak4xxx-adda.c reg, val); reg 32 sound/isa/ad1816a/ad1816a_lib.c static inline unsigned char snd_ad1816a_in(struct snd_ad1816a *chip, unsigned char reg) reg 35 sound/isa/ad1816a/ad1816a_lib.c return inb(AD1816A_REG(reg)); reg 38 sound/isa/ad1816a/ad1816a_lib.c static inline void snd_ad1816a_out(struct snd_ad1816a *chip, unsigned char reg, reg 42 sound/isa/ad1816a/ad1816a_lib.c outb(value, AD1816A_REG(reg)); reg 45 sound/isa/ad1816a/ad1816a_lib.c static inline void snd_ad1816a_out_mask(struct snd_ad1816a *chip, unsigned char reg, reg 48 sound/isa/ad1816a/ad1816a_lib.c snd_ad1816a_out(chip, reg, reg 49 sound/isa/ad1816a/ad1816a_lib.c (value & mask) | (snd_ad1816a_in(chip, reg) & ~mask)); reg 52 sound/isa/ad1816a/ad1816a_lib.c static unsigned short snd_ad1816a_read(struct snd_ad1816a *chip, unsigned char reg) reg 54 sound/isa/ad1816a/ad1816a_lib.c snd_ad1816a_out(chip, AD1816A_INDIR_ADDR, reg & 0x3f); reg 59 sound/isa/ad1816a/ad1816a_lib.c static void snd_ad1816a_write(struct snd_ad1816a *chip, unsigned char reg, reg 62 sound/isa/ad1816a/ad1816a_lib.c snd_ad1816a_out(chip, AD1816A_INDIR_ADDR, reg & 0x3f); reg 67 sound/isa/ad1816a/ad1816a_lib.c static void snd_ad1816a_write_mask(struct snd_ad1816a *chip, unsigned char reg, reg 70 sound/isa/ad1816a/ad1816a_lib.c snd_ad1816a_write(chip, reg, reg 71 sound/isa/ad1816a/ad1816a_lib.c (value & mask) | (snd_ad1816a_read(chip, reg) & ~mask)); reg 506 sound/isa/ad1816a/ad1816a_lib.c int reg; reg 510 sound/isa/ad1816a/ad1816a_lib.c for (reg = 0; reg < 48; reg++) reg 511 sound/isa/ad1816a/ad1816a_lib.c chip->image[reg] = snd_ad1816a_read(chip, reg); reg 517 sound/isa/ad1816a/ad1816a_lib.c int reg; reg 522 sound/isa/ad1816a/ad1816a_lib.c for (reg = 0; reg < 48; reg++) reg 523 sound/isa/ad1816a/ad1816a_lib.c snd_ad1816a_write(chip, reg, chip->image[reg]); reg 758 sound/isa/ad1816a/ad1816a_lib.c #define AD1816A_SINGLE_TLV(xname, reg, shift, mask, invert, xtlv) \ reg 763 sound/isa/ad1816a/ad1816a_lib.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \ reg 765 sound/isa/ad1816a/ad1816a_lib.c #define AD1816A_SINGLE(xname, reg, shift, mask, invert) \ reg 768 sound/isa/ad1816a/ad1816a_lib.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } reg 785 sound/isa/ad1816a/ad1816a_lib.c int reg = kcontrol->private_value & 0xff; reg 791 sound/isa/ad1816a/ad1816a_lib.c ucontrol->value.integer.value[0] = (snd_ad1816a_read(chip, reg) >> shift) & mask; reg 802 sound/isa/ad1816a/ad1816a_lib.c int reg = kcontrol->private_value & 0xff; reg 814 sound/isa/ad1816a/ad1816a_lib.c old_val = snd_ad1816a_read(chip, reg); reg 817 sound/isa/ad1816a/ad1816a_lib.c snd_ad1816a_write(chip, reg, val); reg 822 sound/isa/ad1816a/ad1816a_lib.c #define AD1816A_DOUBLE_TLV(xname, reg, shift_left, shift_right, mask, invert, xtlv) \ reg 827 sound/isa/ad1816a/ad1816a_lib.c .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24), \ reg 830 sound/isa/ad1816a/ad1816a_lib.c #define AD1816A_DOUBLE(xname, reg, shift_left, shift_right, mask, invert) \ reg 833 sound/isa/ad1816a/ad1816a_lib.c .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24) } reg 850 sound/isa/ad1816a/ad1816a_lib.c int reg = kcontrol->private_value & 0xff; reg 858 sound/isa/ad1816a/ad1816a_lib.c val = snd_ad1816a_read(chip, reg); reg 873 sound/isa/ad1816a/ad1816a_lib.c int reg = kcontrol->private_value & 0xff; reg 890 sound/isa/ad1816a/ad1816a_lib.c old_val = snd_ad1816a_read(chip, reg); reg 893 sound/isa/ad1816a/ad1816a_lib.c snd_ad1816a_write(chip, reg, val1); reg 114 sound/isa/cmi8328.c static u8 snd_cmi8328_cfg_read(u16 port, u8 reg) reg 118 sound/isa/cmi8328.c outb(reg, port + 3); reg 122 sound/isa/cmi8328.c static void snd_cmi8328_cfg_write(u16 port, u8 reg, u8 val) reg 126 sound/isa/cmi8328.c outb(reg, port + 3); reg 109 sound/isa/cs423x/cs4236_lib.c unsigned char reg, unsigned char val) reg 111 sound/isa/cs423x/cs4236_lib.c outb(reg, chip->cport + 3); reg 112 sound/isa/cs423x/cs4236_lib.c outb(chip->cimage[reg] = val, chip->cport + 4); reg 115 sound/isa/cs423x/cs4236_lib.c static unsigned char snd_cs4236_ctrl_in(struct snd_wss *chip, unsigned char reg) reg 117 sound/isa/cs423x/cs4236_lib.c outb(reg, chip->cport + 3); reg 208 sound/isa/cs423x/cs4236_lib.c int reg; reg 212 sound/isa/cs423x/cs4236_lib.c for (reg = 0; reg < 32; reg++) reg 213 sound/isa/cs423x/cs4236_lib.c chip->image[reg] = snd_wss_in(chip, reg); reg 214 sound/isa/cs423x/cs4236_lib.c for (reg = 0; reg < 18; reg++) reg 215 sound/isa/cs423x/cs4236_lib.c chip->eimage[reg] = snd_cs4236_ext_in(chip, CS4236_I23VAL(reg)); reg 216 sound/isa/cs423x/cs4236_lib.c for (reg = 2; reg < 9; reg++) reg 217 sound/isa/cs423x/cs4236_lib.c chip->cimage[reg] = snd_cs4236_ctrl_in(chip, reg); reg 223 sound/isa/cs423x/cs4236_lib.c int reg; reg 228 sound/isa/cs423x/cs4236_lib.c for (reg = 0; reg < 32; reg++) { reg 229 sound/isa/cs423x/cs4236_lib.c switch (reg) { reg 236 sound/isa/cs423x/cs4236_lib.c snd_wss_out(chip, reg, chip->image[reg]); reg 240 sound/isa/cs423x/cs4236_lib.c for (reg = 0; reg < 18; reg++) reg 241 sound/isa/cs423x/cs4236_lib.c snd_cs4236_ext_out(chip, CS4236_I23VAL(reg), chip->eimage[reg]); reg 242 sound/isa/cs423x/cs4236_lib.c for (reg = 2; reg < 9; reg++) { reg 243 sound/isa/cs423x/cs4236_lib.c switch (reg) { reg 247 sound/isa/cs423x/cs4236_lib.c snd_cs4236_ctrl_out(chip, reg, chip->cimage[reg]); reg 269 sound/isa/cs423x/cs4236_lib.c unsigned int reg; reg 318 sound/isa/cs423x/cs4236_lib.c reg = ((IEC958_AES1_CON_PCM_CODER & 3) << 6) | reg 320 sound/isa/cs423x/cs4236_lib.c snd_cs4236_ctrl_out(chip, 5, reg); reg 339 sound/isa/cs423x/cs4236_lib.c for (reg = 0; reg < sizeof(snd_cs4236_ext_map); reg++) reg 340 sound/isa/cs423x/cs4236_lib.c snd_cs4236_ext_out(chip, CS4236_I23VAL(reg), reg 341 sound/isa/cs423x/cs4236_lib.c snd_cs4236_ext_map[reg]); reg 380 sound/isa/cs423x/cs4236_lib.c #define CS4236_SINGLE(xname, xindex, reg, shift, mask, invert) \ reg 384 sound/isa/cs423x/cs4236_lib.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } reg 386 sound/isa/cs423x/cs4236_lib.c #define CS4236_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \ reg 391 sound/isa/cs423x/cs4236_lib.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \ reg 409 sound/isa/cs423x/cs4236_lib.c int reg = kcontrol->private_value & 0xff; reg 415 sound/isa/cs423x/cs4236_lib.c ucontrol->value.integer.value[0] = (chip->eimage[CS4236_REG(reg)] >> shift) & mask; reg 426 sound/isa/cs423x/cs4236_lib.c int reg = kcontrol->private_value & 0xff; reg 438 sound/isa/cs423x/cs4236_lib.c val = (chip->eimage[CS4236_REG(reg)] & ~(mask << shift)) | val; reg 439 sound/isa/cs423x/cs4236_lib.c change = val != chip->eimage[CS4236_REG(reg)]; reg 440 sound/isa/cs423x/cs4236_lib.c snd_cs4236_ext_out(chip, reg, val); reg 445 sound/isa/cs423x/cs4236_lib.c #define CS4236_SINGLEC(xname, xindex, reg, shift, mask, invert) \ reg 449 sound/isa/cs423x/cs4236_lib.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } reg 455 sound/isa/cs423x/cs4236_lib.c int reg = kcontrol->private_value & 0xff; reg 461 sound/isa/cs423x/cs4236_lib.c ucontrol->value.integer.value[0] = (chip->cimage[reg] >> shift) & mask; reg 472 sound/isa/cs423x/cs4236_lib.c int reg = kcontrol->private_value & 0xff; reg 484 sound/isa/cs423x/cs4236_lib.c val = (chip->cimage[reg] & ~(mask << shift)) | val; reg 485 sound/isa/cs423x/cs4236_lib.c change = val != chip->cimage[reg]; reg 486 sound/isa/cs423x/cs4236_lib.c snd_cs4236_ctrl_out(chip, reg, val); reg 51 sound/isa/es1688/es1688_lib.c unsigned char reg, unsigned char data) reg 53 sound/isa/es1688/es1688_lib.c if (!snd_es1688_dsp_command(chip, reg)) reg 58 sound/isa/es1688/es1688_lib.c static int snd_es1688_read(struct snd_es1688 *chip, unsigned char reg) reg 63 sound/isa/es1688/es1688_lib.c if (!snd_es1688_dsp_command(chip, reg)) reg 69 sound/isa/es1688/es1688_lib.c unsigned char reg, unsigned char data) reg 71 sound/isa/es1688/es1688_lib.c outb(reg, ES1688P(chip, MIXER_ADDR)); reg 77 sound/isa/es1688/es1688_lib.c static unsigned char snd_es1688_mixer_read(struct snd_es1688 *chip, unsigned char reg) reg 81 sound/isa/es1688/es1688_lib.c outb(reg, ES1688P(chip, MIXER_ADDR)); reg 777 sound/isa/es1688/es1688_lib.c #define ES1688_SINGLE(xname, xindex, reg, shift, mask, invert) \ reg 781 sound/isa/es1688/es1688_lib.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } reg 798 sound/isa/es1688/es1688_lib.c int reg = kcontrol->private_value & 0xff; reg 804 sound/isa/es1688/es1688_lib.c ucontrol->value.integer.value[0] = (snd_es1688_mixer_read(chip, reg) >> shift) & mask; reg 815 sound/isa/es1688/es1688_lib.c int reg = kcontrol->private_value & 0xff; reg 827 sound/isa/es1688/es1688_lib.c oval = snd_es1688_mixer_read(chip, reg); reg 831 sound/isa/es1688/es1688_lib.c snd_es1688_mixer_write(chip, reg, nval); reg 989 sound/isa/es1688/es1688_lib.c unsigned char reg, val; reg 1001 sound/isa/es1688/es1688_lib.c reg = snd_es1688_init_table[idx][0]; reg 1003 sound/isa/es1688/es1688_lib.c if (reg < 0xa0) reg 1004 sound/isa/es1688/es1688_lib.c snd_es1688_mixer_write(chip, reg, val); reg 1006 sound/isa/es1688/es1688_lib.c snd_es1688_write(chip, reg, val); reg 190 sound/isa/es18xx.c unsigned char reg, unsigned char data) reg 196 sound/isa/es18xx.c ret = snd_es18xx_dsp_command(chip, reg); reg 203 sound/isa/es18xx.c snd_printk(KERN_DEBUG "Reg %02x set to %02x\n", reg, data); reg 208 sound/isa/es18xx.c static int snd_es18xx_read(struct snd_es18xx *chip, unsigned char reg) reg 216 sound/isa/es18xx.c ret = snd_es18xx_dsp_command(chip, reg); reg 222 sound/isa/es18xx.c snd_printk(KERN_DEBUG "Reg %02x now is %02x (%d)\n", reg, data, ret); reg 230 sound/isa/es18xx.c static int snd_es18xx_bits(struct snd_es18xx *chip, unsigned char reg, reg 240 sound/isa/es18xx.c ret = snd_es18xx_dsp_command(chip, reg); reg 250 sound/isa/es18xx.c ret = snd_es18xx_dsp_command(chip, reg); reg 259 sound/isa/es18xx.c reg, old, new, ret); reg 269 sound/isa/es18xx.c unsigned char reg, unsigned char data) reg 273 sound/isa/es18xx.c outb(reg, chip->port + 0x04); reg 277 sound/isa/es18xx.c snd_printk(KERN_DEBUG "Mixer reg %02x set to %02x\n", reg, data); reg 281 sound/isa/es18xx.c static inline int snd_es18xx_mixer_read(struct snd_es18xx *chip, unsigned char reg) reg 286 sound/isa/es18xx.c outb(reg, chip->port + 0x04); reg 290 sound/isa/es18xx.c snd_printk(KERN_DEBUG "Mixer reg %02x now is %02x\n", reg, data); reg 296 sound/isa/es18xx.c static inline int snd_es18xx_mixer_bits(struct snd_es18xx *chip, unsigned char reg, reg 302 sound/isa/es18xx.c outb(reg, chip->port + 0x04); reg 310 sound/isa/es18xx.c reg, old, new); reg 317 sound/isa/es18xx.c static inline int snd_es18xx_mixer_writable(struct snd_es18xx *chip, unsigned char reg, reg 323 sound/isa/es18xx.c outb(reg, chip->port + 0x04); reg 331 sound/isa/es18xx.c reg, old, expected, new); reg 1093 sound/isa/es18xx.c static int snd_es18xx_reg_bits(struct snd_es18xx *chip, unsigned char reg, reg 1096 sound/isa/es18xx.c if (reg < 0xa0) reg 1097 sound/isa/es18xx.c return snd_es18xx_mixer_bits(chip, reg, mask, val); reg 1099 sound/isa/es18xx.c return snd_es18xx_bits(chip, reg, mask, val); reg 1102 sound/isa/es18xx.c static int snd_es18xx_reg_read(struct snd_es18xx *chip, unsigned char reg) reg 1104 sound/isa/es18xx.c if (reg < 0xa0) reg 1105 sound/isa/es18xx.c return snd_es18xx_mixer_read(chip, reg); reg 1107 sound/isa/es18xx.c return snd_es18xx_read(chip, reg); reg 1110 sound/isa/es18xx.c #define ES18XX_SINGLE(xname, xindex, reg, shift, mask, flags) \ reg 1114 sound/isa/es18xx.c .private_value = reg | (shift << 8) | (mask << 16) | (flags << 24) } reg 1133 sound/isa/es18xx.c int reg = kcontrol->private_value & 0xff; reg 1143 sound/isa/es18xx.c val = snd_es18xx_reg_read(chip, reg); reg 1153 sound/isa/es18xx.c int reg = kcontrol->private_value & 0xff; reg 1174 sound/isa/es18xx.c return snd_es18xx_reg_bits(chip, reg, mask, val) != val; reg 1359 sound/isa/es18xx.c static int snd_es18xx_config_read(struct snd_es18xx *chip, unsigned char reg) reg 1363 sound/isa/es18xx.c outb(reg, chip->ctrl_port); reg 1369 sound/isa/es18xx.c unsigned char reg, unsigned char data) reg 1373 sound/isa/es18xx.c outb(reg, chip->ctrl_port); reg 1376 sound/isa/es18xx.c snd_printk(KERN_DEBUG "Config reg %02x set to %02x\n", reg, data); reg 31 sound/isa/gus/gus_io.c static inline void __snd_gf1_ctrl_stop(struct snd_gus_card * gus, unsigned char reg) reg 35 sound/isa/gus/gus_io.c outb(reg | 0x80, gus->gf1.reg_regsel); reg 39 sound/isa/gus/gus_io.c outb(reg, gus->gf1.reg_regsel); reg 46 sound/isa/gus/gus_io.c unsigned char reg, reg 49 sound/isa/gus/gus_io.c outb(reg, gus->gf1.reg_regsel); reg 56 sound/isa/gus/gus_io.c unsigned char reg) reg 58 sound/isa/gus/gus_io.c outb(reg, gus->gf1.reg_regsel); reg 64 sound/isa/gus/gus_io.c unsigned char reg, unsigned int data) reg 66 sound/isa/gus/gus_io.c outb(reg, gus->gf1.reg_regsel); reg 73 sound/isa/gus/gus_io.c unsigned char reg) reg 75 sound/isa/gus/gus_io.c outb(reg, gus->gf1.reg_regsel); reg 81 sound/isa/gus/gus_io.c unsigned char reg, unsigned char data) reg 83 sound/isa/gus/gus_io.c outb(reg, gus->gf1.reg_timerctrl); reg 91 sound/isa/gus/gus_io.c static inline void __snd_gf1_write_addr(struct snd_gus_card * gus, unsigned char reg, reg 100 sound/isa/gus/gus_io.c __snd_gf1_write16(gus, reg, (unsigned short) (addr >> 11)); reg 101 sound/isa/gus/gus_io.c __snd_gf1_write16(gus, reg + 1, (unsigned short) (addr << 5)); reg 105 sound/isa/gus/gus_io.c unsigned char reg, short w_16bit) reg 109 sound/isa/gus/gus_io.c res = ((unsigned int) __snd_gf1_look16(gus, reg | 0x80) << 11) & 0xfff800; reg 110 sound/isa/gus/gus_io.c res |= ((unsigned int) __snd_gf1_look16(gus, (reg + 1) | 0x80) >> 5) & 0x0007ff; reg 125 sound/isa/gus/gus_io.c void snd_gf1_ctrl_stop(struct snd_gus_card * gus, unsigned char reg) reg 127 sound/isa/gus/gus_io.c __snd_gf1_ctrl_stop(gus, reg); reg 131 sound/isa/gus/gus_io.c unsigned char reg, reg 134 sound/isa/gus/gus_io.c __snd_gf1_write8(gus, reg, data); reg 137 sound/isa/gus/gus_io.c unsigned char snd_gf1_look8(struct snd_gus_card * gus, unsigned char reg) reg 139 sound/isa/gus/gus_io.c return __snd_gf1_look8(gus, reg); reg 143 sound/isa/gus/gus_io.c unsigned char reg, reg 146 sound/isa/gus/gus_io.c __snd_gf1_write16(gus, reg, data); reg 149 sound/isa/gus/gus_io.c unsigned short snd_gf1_look16(struct snd_gus_card * gus, unsigned char reg) reg 151 sound/isa/gus/gus_io.c return __snd_gf1_look16(gus, reg); reg 155 sound/isa/gus/gus_io.c unsigned char reg, reg 158 sound/isa/gus/gus_io.c __snd_gf1_adlib_write(gus, reg, data); reg 161 sound/isa/gus/gus_io.c void snd_gf1_write_addr(struct snd_gus_card * gus, unsigned char reg, reg 164 sound/isa/gus/gus_io.c __snd_gf1_write_addr(gus, reg, addr, w_16bit); reg 168 sound/isa/gus/gus_io.c unsigned char reg, reg 171 sound/isa/gus/gus_io.c return __snd_gf1_read_addr(gus, reg, w_16bit); reg 178 sound/isa/gus/gus_io.c void snd_gf1_i_ctrl_stop(struct snd_gus_card * gus, unsigned char reg) reg 183 sound/isa/gus/gus_io.c __snd_gf1_ctrl_stop(gus, reg); reg 188 sound/isa/gus/gus_io.c unsigned char reg, reg 194 sound/isa/gus/gus_io.c __snd_gf1_write8(gus, reg, data); reg 198 sound/isa/gus/gus_io.c unsigned char snd_gf1_i_look8(struct snd_gus_card * gus, unsigned char reg) reg 204 sound/isa/gus/gus_io.c res = __snd_gf1_look8(gus, reg); reg 210 sound/isa/gus/gus_io.c unsigned char reg, reg 216 sound/isa/gus/gus_io.c __snd_gf1_write16(gus, reg, data); reg 220 sound/isa/gus/gus_io.c unsigned short snd_gf1_i_look16(struct snd_gus_card * gus, unsigned char reg) reg 226 sound/isa/gus/gus_io.c res = __snd_gf1_look16(gus, reg); reg 234 sound/isa/gus/gus_io.c unsigned char reg, reg 240 sound/isa/gus/gus_io.c __snd_gf1_adlib_write(gus, reg, data); reg 244 sound/isa/gus/gus_io.c void snd_gf1_i_write_addr(struct snd_gus_card * gus, unsigned char reg, reg 250 sound/isa/gus/gus_io.c __snd_gf1_write_addr(gus, reg, addr, w_16bit); reg 258 sound/isa/gus/gus_io.c unsigned char reg, short w_16bit) reg 264 sound/isa/gus/gus_io.c res = __snd_gf1_read_addr(gus, reg, w_16bit); reg 640 sound/isa/msnd/msnd_pinnacle.c static int snd_msnd_write_cfg(int cfg, int reg, int value) reg 642 sound/isa/msnd/msnd_pinnacle.c outb(reg, cfg); reg 160 sound/isa/opl3sa2.c static unsigned char __snd_opl3sa2_read(struct snd_opl3sa2 *chip, unsigned char reg) reg 167 sound/isa/opl3sa2.c outb(reg, chip->port); /* register */ reg 177 sound/isa/opl3sa2.c static unsigned char snd_opl3sa2_read(struct snd_opl3sa2 *chip, unsigned char reg) reg 183 sound/isa/opl3sa2.c result = __snd_opl3sa2_read(chip, reg); reg 189 sound/isa/opl3sa2.c static void __snd_opl3sa2_write(struct snd_opl3sa2 *chip, unsigned char reg, unsigned char value) reg 194 sound/isa/opl3sa2.c outb(reg, chip->port); /* register */ reg 196 sound/isa/opl3sa2.c chip->ctlregs[reg] = value; reg 200 sound/isa/opl3sa2.c static void snd_opl3sa2_write(struct snd_opl3sa2 *chip, unsigned char reg, unsigned char value) reg 204 sound/isa/opl3sa2.c __snd_opl3sa2_write(chip, reg, value); reg 326 sound/isa/opl3sa2.c #define OPL3SA2_SINGLE(xname, xindex, reg, shift, mask, invert) \ reg 330 sound/isa/opl3sa2.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } reg 331 sound/isa/opl3sa2.c #define OPL3SA2_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \ reg 337 sound/isa/opl3sa2.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \ reg 344 sound/isa/opl3sa2.c int reg = kcontrol->private_value & 0xff; reg 350 sound/isa/opl3sa2.c ucontrol->value.integer.value[0] = (chip->ctlregs[reg] >> shift) & mask; reg 361 sound/isa/opl3sa2.c int reg = kcontrol->private_value & 0xff; reg 373 sound/isa/opl3sa2.c oval = chip->ctlregs[reg]; reg 376 sound/isa/opl3sa2.c __snd_opl3sa2_write(chip, reg, val); reg 403 sound/isa/opti9xx/miro.c int reg = kcontrol->private_value & 0xff; reg 408 sound/isa/opti9xx/miro.c if ((reg >= ACI_GET_EQ1) && (reg <= ACI_GET_EQ7)) { reg 811 sound/isa/opti9xx/miro.c unsigned char reg) reg 821 sound/isa/opti9xx/miro.c if (reg > 7) { reg 822 sound/isa/opti9xx/miro.c outb(reg, chip->mc_base + 8); reg 830 sound/isa/opti9xx/miro.c retval = inb(chip->mc_base + reg); reg 841 sound/isa/opti9xx/miro.c static void snd_miro_write(struct snd_miro *chip, unsigned char reg, reg 851 sound/isa/opti9xx/miro.c if (reg > 7) { reg 852 sound/isa/opti9xx/miro.c outb(reg, chip->mc_base + 8); reg 860 sound/isa/opti9xx/miro.c outb(value, chip->mc_base + reg); reg 871 sound/isa/opti9xx/miro.c unsigned char reg, unsigned char value, unsigned char mask) reg 873 sound/isa/opti9xx/miro.c unsigned char oldval = snd_miro_read(chip, reg); reg 875 sound/isa/opti9xx/miro.c snd_miro_write(chip, reg, (oldval & ~mask) | (value & mask)); reg 234 sound/isa/opti9xx/opti92x-ad1848.c unsigned char reg) reg 246 sound/isa/opti9xx/opti92x-ad1848.c if (reg > 7) { reg 247 sound/isa/opti9xx/opti92x-ad1848.c outb(reg, chip->mc_base + 8); reg 256 sound/isa/opti9xx/opti92x-ad1848.c retval = inb(chip->mc_base + reg); reg 263 sound/isa/opti9xx/opti92x-ad1848.c outb(reg, chip->mc_indir_index); reg 277 sound/isa/opti9xx/opti92x-ad1848.c static void snd_opti9xx_write(struct snd_opti9xx *chip, unsigned char reg, reg 289 sound/isa/opti9xx/opti92x-ad1848.c if (reg > 7) { reg 290 sound/isa/opti9xx/opti92x-ad1848.c outb(reg, chip->mc_base + 8); reg 299 sound/isa/opti9xx/opti92x-ad1848.c outb(value, chip->mc_base + reg); reg 306 sound/isa/opti9xx/opti92x-ad1848.c outb(reg, chip->mc_indir_index); reg 321 sound/isa/opti9xx/opti92x-ad1848.c unsigned char reg, unsigned char value, unsigned char mask) reg 323 sound/isa/opti9xx/opti92x-ad1848.c unsigned char oldval = snd_opti9xx_read(chip, reg); reg 325 sound/isa/opti9xx/opti92x-ad1848.c snd_opti9xx_write(chip, reg, (oldval & ~mask) | (value & mask)); reg 35 sound/isa/sb/emu8000.c void snd_emu8000_poke(struct snd_emu8000 *emu, unsigned int port, unsigned int reg, unsigned int val) reg 39 sound/isa/sb/emu8000.c if (reg != emu->last_reg) { reg 40 sound/isa/sb/emu8000.c outw((unsigned short)reg, EMU8000_PTR(emu)); /* Set register */ reg 41 sound/isa/sb/emu8000.c emu->last_reg = reg; reg 48 sound/isa/sb/emu8000.c unsigned short snd_emu8000_peek(struct snd_emu8000 *emu, unsigned int port, unsigned int reg) reg 53 sound/isa/sb/emu8000.c if (reg != emu->last_reg) { reg 54 sound/isa/sb/emu8000.c outw((unsigned short)reg, EMU8000_PTR(emu)); /* Set register */ reg 55 sound/isa/sb/emu8000.c emu->last_reg = reg; reg 63 sound/isa/sb/emu8000.c void snd_emu8000_poke_dw(struct snd_emu8000 *emu, unsigned int port, unsigned int reg, unsigned int val) reg 67 sound/isa/sb/emu8000.c if (reg != emu->last_reg) { reg 68 sound/isa/sb/emu8000.c outw((unsigned short)reg, EMU8000_PTR(emu)); /* Set register */ reg 69 sound/isa/sb/emu8000.c emu->last_reg = reg; reg 77 sound/isa/sb/emu8000.c unsigned int snd_emu8000_peek_dw(struct snd_emu8000 *emu, unsigned int port, unsigned int reg) reg 83 sound/isa/sb/emu8000.c if (reg != emu->last_reg) { reg 84 sound/isa/sb/emu8000.c outw((unsigned short)reg, EMU8000_PTR(emu)); /* Set register */ reg 85 sound/isa/sb/emu8000.c emu->last_reg = reg; reg 89 sound/isa/sb/emu8000_callback.c dcysusv = 0x8000 | (unsigned char)vp->reg.parm.modrelease; reg 91 sound/isa/sb/emu8000_callback.c dcysusv = 0x8000 | (unsigned char)vp->reg.parm.volrelease; reg 194 sound/isa/sb/emu8000_callback.c (vp->reg.sample_mode & SNDRV_SFNT_SAMPLE_SINGLESHOT)) { reg 196 sound/isa/sb/emu8000_callback.c if (val >= vp->reg.loopstart) reg 244 sound/isa/sb/emu8000_callback.c EMU8000_ENVVAL_WRITE(hw, ch, vp->reg.parm.moddelay); reg 245 sound/isa/sb/emu8000_callback.c EMU8000_ATKHLD_WRITE(hw, ch, vp->reg.parm.modatkhld); reg 246 sound/isa/sb/emu8000_callback.c EMU8000_DCYSUS_WRITE(hw, ch, vp->reg.parm.moddcysus); reg 247 sound/isa/sb/emu8000_callback.c EMU8000_ENVVOL_WRITE(hw, ch, vp->reg.parm.voldelay); reg 248 sound/isa/sb/emu8000_callback.c EMU8000_ATKHLDV_WRITE(hw, ch, vp->reg.parm.volatkhld); reg 256 sound/isa/sb/emu8000_callback.c EMU8000_PEFE_WRITE(hw, ch, vp->reg.parm.pefe); reg 259 sound/isa/sb/emu8000_callback.c EMU8000_LFO1VAL_WRITE(hw, ch, vp->reg.parm.lfo1delay); reg 260 sound/isa/sb/emu8000_callback.c EMU8000_LFO2VAL_WRITE(hw, ch, vp->reg.parm.lfo2delay); reg 272 sound/isa/sb/emu8000_callback.c addr = vp->reg.loopend - 1; reg 273 sound/isa/sb/emu8000_callback.c temp = vp->reg.parm.chorus; reg 280 sound/isa/sb/emu8000_callback.c addr = vp->reg.start - 1; reg 281 sound/isa/sb/emu8000_callback.c temp = vp->reg.parm.filterQ; reg 310 sound/isa/sb/emu8000_callback.c temp = vp->reg.parm.reverb; reg 316 sound/isa/sb/emu8000_callback.c EMU8000_DCYSUSV_WRITE(hw, ch, vp->reg.parm.voldcysus); reg 363 sound/isa/sb/emu8000_callback.c temp = ((unsigned int)vp->apan<<24) | ((unsigned int)vp->reg.loopstart - 1); reg 377 sound/isa/sb/emu8000_callback.c pitch = (char)(vp->reg.parm.fmmod>>8); reg 378 sound/isa/sb/emu8000_callback.c cutoff = (vp->reg.parm.fmmod & 0xff); reg 390 sound/isa/sb/emu8000_callback.c EMU8000_TREMFRQ_WRITE(hw, vp->ch, vp->reg.parm.tremfrq); reg 402 sound/isa/sb/emu8000_callback.c pitch = (char)(vp->reg.parm.fm2frq2>>8); reg 403 sound/isa/sb/emu8000_callback.c freq = vp->reg.parm.fm2frq2 & 0xff; reg 417 sound/isa/sb/emu8000_callback.c addr |= (vp->reg.parm.filterQ << 28); reg 73 sound/isa/sb/sb16_csp.c static int set_register(struct snd_sb *chip, unsigned char reg, unsigned char val); reg 74 sound/isa/sb/sb16_csp.c static int read_register(struct snd_sb *chip, unsigned char reg); reg 504 sound/isa/sb/sb16_csp.c static int set_register(struct snd_sb *chip, unsigned char reg, unsigned char val) reg 509 sound/isa/sb/sb16_csp.c dsp_cmd[1] = reg; /* CSP Register */ reg 518 sound/isa/sb/sb16_csp.c static int read_register(struct snd_sb *chip, unsigned char reg) reg 523 sound/isa/sb/sb16_csp.c dsp_cmd[1] = reg; /* CSP Register */ reg 16 sound/isa/sb/sb_mixer.c void snd_sbmixer_write(struct snd_sb *chip, unsigned char reg, unsigned char data) reg 18 sound/isa/sb/sb_mixer.c outb(reg, SBP(chip, MIXER_ADDR)); reg 23 sound/isa/sb/sb_mixer.c snd_printk(KERN_DEBUG "mixer_write 0x%x 0x%x\n", reg, data); reg 27 sound/isa/sb/sb_mixer.c unsigned char snd_sbmixer_read(struct snd_sb *chip, unsigned char reg) reg 31 sound/isa/sb/sb_mixer.c outb(reg, SBP(chip, MIXER_ADDR)); reg 36 sound/isa/sb/sb_mixer.c snd_printk(KERN_DEBUG "mixer_read 0x%x 0x%x\n", reg, result); reg 60 sound/isa/sb/sb_mixer.c int reg = kcontrol->private_value & 0xff; reg 66 sound/isa/sb/sb_mixer.c val = (snd_sbmixer_read(sb, reg) >> shift) & mask; reg 76 sound/isa/sb/sb_mixer.c int reg = kcontrol->private_value & 0xff; reg 84 sound/isa/sb/sb_mixer.c oval = snd_sbmixer_read(sb, reg); reg 88 sound/isa/sb/sb_mixer.c snd_sbmixer_write(sb, reg, val); reg 188 sound/isa/sscape.c static inline void sscape_write_unsafe(unsigned io_base, enum GA_REG reg, reg 191 sound/isa/sscape.c outb(reg, ODIE_ADDR_IO(io_base)); reg 199 sound/isa/sscape.c static void sscape_write(struct soundscape *s, enum GA_REG reg, reg 205 sound/isa/sscape.c sscape_write_unsafe(s->io_base, reg, val); reg 214 sound/isa/sscape.c enum GA_REG reg) reg 216 sound/isa/sscape.c outb(reg, ODIE_ADDR_IO(io_base)); reg 345 sound/isa/sscape.c static void sscape_start_dma_unsafe(unsigned io_base, enum GA_REG reg) reg 347 sound/isa/sscape.c sscape_write_unsafe(io_base, reg, reg 348 sound/isa/sscape.c sscape_read_unsafe(io_base, reg) | 0x01); reg 349 sound/isa/sscape.c sscape_write_unsafe(io_base, reg, reg 350 sound/isa/sscape.c sscape_read_unsafe(io_base, reg) & 0xfe); reg 357 sound/isa/sscape.c static int sscape_wait_dma_unsafe(unsigned io_base, enum GA_REG reg, reg 360 sound/isa/sscape.c while (!(sscape_read_unsafe(io_base, reg) & 0x01) && (timeout != 0)) { reg 365 sound/isa/sscape.c return sscape_read_unsafe(io_base, reg) & 0x01; reg 171 sound/isa/wss/wss_lib.c static void snd_wss_dout(struct snd_wss *chip, unsigned char reg, reg 180 sound/isa/wss/wss_lib.c wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg); reg 185 sound/isa/wss/wss_lib.c void snd_wss_out(struct snd_wss *chip, unsigned char reg, unsigned char value) reg 191 sound/isa/wss/wss_lib.c "- reg = 0x%x, value = 0x%x\n", reg, value); reg 193 sound/isa/wss/wss_lib.c wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg); reg 195 sound/isa/wss/wss_lib.c chip->image[reg] = value; reg 198 sound/isa/wss/wss_lib.c chip->mce_bit | reg, value); reg 202 sound/isa/wss/wss_lib.c unsigned char snd_wss_in(struct snd_wss *chip, unsigned char reg) reg 208 sound/isa/wss/wss_lib.c "- reg = 0x%x\n", reg); reg 210 sound/isa/wss/wss_lib.c wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg); reg 216 sound/isa/wss/wss_lib.c void snd_cs4236_ext_out(struct snd_wss *chip, unsigned char reg, reg 221 sound/isa/wss/wss_lib.c reg | (chip->image[CS4236_EXT_REG] & 0x01)); reg 223 sound/isa/wss/wss_lib.c chip->eimage[CS4236_REG(reg)] = val; reg 225 sound/isa/wss/wss_lib.c printk(KERN_DEBUG "ext out : reg = 0x%x, val = 0x%x\n", reg, val); reg 230 sound/isa/wss/wss_lib.c unsigned char snd_cs4236_ext_in(struct snd_wss *chip, unsigned char reg) reg 234 sound/isa/wss/wss_lib.c reg | (chip->image[CS4236_EXT_REG] & 0x01)); reg 242 sound/isa/wss/wss_lib.c reg, res); reg 1611 sound/isa/wss/wss_lib.c int reg; reg 1615 sound/isa/wss/wss_lib.c for (reg = 0; reg < 32; reg++) reg 1616 sound/isa/wss/wss_lib.c chip->image[reg] = snd_wss_in(chip, reg); reg 1625 sound/isa/wss/wss_lib.c int reg; reg 1633 sound/isa/wss/wss_lib.c for (reg = 0; reg < 32; reg++) { reg 1634 sound/isa/wss/wss_lib.c switch (reg) { reg 1638 sound/isa/wss/wss_lib.c snd_wss_out(chip, reg, chip->image[reg]); reg 2058 sound/isa/wss/wss_lib.c int reg = kcontrol->private_value & 0xff; reg 2064 sound/isa/wss/wss_lib.c ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask; reg 2077 sound/isa/wss/wss_lib.c int reg = kcontrol->private_value & 0xff; reg 2089 sound/isa/wss/wss_lib.c val = (chip->image[reg] & ~(mask << shift)) | val; reg 2090 sound/isa/wss/wss_lib.c change = val != chip->image[reg]; reg 2091 sound/isa/wss/wss_lib.c snd_wss_out(chip, reg, val); reg 29 sound/mips/ad1843.c char reg; reg 177 sound/mips/ad1843.c w = ad1843->read(ad1843->chip, field->reg); reg 191 sound/mips/ad1843.c w = ad1843->read(ad1843->chip, field->reg); reg 196 sound/mips/ad1843.c ad1843->write(ad1843->chip, field->reg, w); reg 218 sound/mips/ad1843.c int w = 0, mask, *value, reg = -1; reg 224 sound/mips/ad1843.c if (reg == -1) { reg 225 sound/mips/ad1843.c reg = fp->reg; reg 226 sound/mips/ad1843.c w = ad1843->read(ad1843->chip, reg); reg 249 sound/mips/ad1843.c int reg; reg 256 sound/mips/ad1843.c reg = -1; reg 262 sound/mips/ad1843.c if (reg == -1) reg 263 sound/mips/ad1843.c reg = fp->reg; reg 265 sound/mips/ad1843.c WARN_ON(reg != fp->reg); reg 273 sound/mips/ad1843.c w = ad1843->read(ad1843->chip, reg); reg 277 sound/mips/ad1843.c ad1843->write(ad1843->chip, reg, w); reg 92 sound/mips/hal2.c static inline u32 hal2_read(u32 *reg) reg 94 sound/mips/hal2.c return __raw_readl(reg); reg 97 sound/mips/hal2.c static inline void hal2_write(u32 val, u32 *reg) reg 99 sound/mips/hal2.c __raw_writel(val, reg); reg 102 sound/mips/sgio2audio.c static int read_ad1843_reg(void *priv, int reg) reg 110 sound/mips/sgio2audio.c writeq((reg << CODEC_CONTROL_ADDRESS_SHIFT) | reg 125 sound/mips/sgio2audio.c static int write_ad1843_reg(void *priv, int reg, int word) reg 133 sound/mips/sgio2audio.c writeq((reg << CODEC_CONTROL_ADDRESS_SHIFT) | reg 214 sound/pci/ac97/ac97_codec.c static int snd_ac97_valid_reg(struct snd_ac97 *ac97, unsigned short reg) reg 219 sound/pci/ac97/ac97_codec.c if (reg == 0x08) reg 223 sound/pci/ac97/ac97_codec.c if (reg == 0x22 || reg == 0x7a) reg 228 sound/pci/ac97/ac97_codec.c if (reg <= 0x1c || reg == 0x20 || reg == 0x26 || reg >= 0x7c) reg 234 sound/pci/ac97/ac97_codec.c if (reg >= 0x3a && reg <= 0x6e) /* 0x59 */ reg 241 sound/pci/ac97/ac97_codec.c if (reg == 0x5a) reg 243 sound/pci/ac97/ac97_codec.c if (reg >= 0x3c && reg <= 0x6e) /* 0x59 */ reg 253 sound/pci/ac97/ac97_codec.c if (reg <= 0x3a || reg >= 0x5a) reg 272 sound/pci/ac97/ac97_codec.c void snd_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short value) reg 274 sound/pci/ac97/ac97_codec.c if (!snd_ac97_valid_reg(ac97, reg)) reg 278 sound/pci/ac97/ac97_codec.c if (reg == AC97_MASTER || reg == AC97_HEADPHONE) reg 281 sound/pci/ac97/ac97_codec.c ac97->bus->ops->write(ac97, reg, value); reg 297 sound/pci/ac97/ac97_codec.c unsigned short snd_ac97_read(struct snd_ac97 *ac97, unsigned short reg) reg 299 sound/pci/ac97/ac97_codec.c if (!snd_ac97_valid_reg(ac97, reg)) reg 301 sound/pci/ac97/ac97_codec.c return ac97->bus->ops->read(ac97, reg); reg 305 sound/pci/ac97/ac97_codec.c static inline unsigned short snd_ac97_read_cache(struct snd_ac97 *ac97, unsigned short reg) reg 307 sound/pci/ac97/ac97_codec.c if (! test_bit(reg, ac97->reg_accessed)) { reg 308 sound/pci/ac97/ac97_codec.c ac97->regs[reg] = ac97->bus->ops->read(ac97, reg); reg 311 sound/pci/ac97/ac97_codec.c return ac97->regs[reg]; reg 326 sound/pci/ac97/ac97_codec.c void snd_ac97_write_cache(struct snd_ac97 *ac97, unsigned short reg, unsigned short value) reg 328 sound/pci/ac97/ac97_codec.c if (!snd_ac97_valid_reg(ac97, reg)) reg 331 sound/pci/ac97/ac97_codec.c ac97->regs[reg] = value; reg 332 sound/pci/ac97/ac97_codec.c ac97->bus->ops->write(ac97, reg, value); reg 333 sound/pci/ac97/ac97_codec.c set_bit(reg, ac97->reg_accessed); reg 351 sound/pci/ac97/ac97_codec.c int snd_ac97_update(struct snd_ac97 *ac97, unsigned short reg, unsigned short value) reg 355 sound/pci/ac97/ac97_codec.c if (!snd_ac97_valid_reg(ac97, reg)) reg 358 sound/pci/ac97/ac97_codec.c change = ac97->regs[reg] != value; reg 360 sound/pci/ac97/ac97_codec.c ac97->regs[reg] = value; reg 361 sound/pci/ac97/ac97_codec.c ac97->bus->ops->write(ac97, reg, value); reg 363 sound/pci/ac97/ac97_codec.c set_bit(reg, ac97->reg_accessed); reg 383 sound/pci/ac97/ac97_codec.c int snd_ac97_update_bits(struct snd_ac97 *ac97, unsigned short reg, unsigned short mask, unsigned short value) reg 387 sound/pci/ac97/ac97_codec.c if (!snd_ac97_valid_reg(ac97, reg)) reg 390 sound/pci/ac97/ac97_codec.c change = snd_ac97_update_bits_nolock(ac97, reg, mask, value); reg 398 sound/pci/ac97/ac97_codec.c int snd_ac97_update_bits_nolock(struct snd_ac97 *ac97, unsigned short reg, reg 404 sound/pci/ac97/ac97_codec.c old = snd_ac97_read_cache(ac97, reg); reg 408 sound/pci/ac97/ac97_codec.c ac97->regs[reg] = new; reg 409 sound/pci/ac97/ac97_codec.c ac97->bus->ops->write(ac97, reg, new); reg 411 sound/pci/ac97/ac97_codec.c set_bit(reg, ac97->reg_accessed); reg 465 sound/pci/ac97/ac97_codec.c val = snd_ac97_read_cache(ac97, e->reg); reg 493 sound/pci/ac97/ac97_codec.c return snd_ac97_update_bits(ac97, e->reg, mask, val); reg 497 sound/pci/ac97/ac97_codec.c static int snd_ac97_page_save(struct snd_ac97 *ac97, int reg, struct snd_kcontrol *kcontrol) reg 502 sound/pci/ac97/ac97_codec.c (reg >= 0x60 && reg < 0x70)) { reg 538 sound/pci/ac97/ac97_codec.c int reg = kcontrol->private_value & 0xff; reg 545 sound/pci/ac97/ac97_codec.c page_save = snd_ac97_page_save(ac97, reg, kcontrol); reg 546 sound/pci/ac97/ac97_codec.c ucontrol->value.integer.value[0] = (snd_ac97_read_cache(ac97, reg) >> shift) & mask; reg 548 sound/pci/ac97/ac97_codec.c ucontrol->value.integer.value[1] = (snd_ac97_read_cache(ac97, reg) >> rshift) & mask; reg 562 sound/pci/ac97/ac97_codec.c int reg = kcontrol->private_value & 0xff; reg 570 sound/pci/ac97/ac97_codec.c page_save = snd_ac97_page_save(ac97, reg, kcontrol); reg 583 sound/pci/ac97/ac97_codec.c err = snd_ac97_update_bits(ac97, reg, val_mask, val); reg 590 sound/pci/ac97/ac97_codec.c ac97->power_up &= ~(1 << (reg>>1)); reg 592 sound/pci/ac97/ac97_codec.c ac97->power_up |= 1 << (reg>>1); reg 806 sound/pci/ac97/ac97_codec.c int reg = kcontrol->private_value & 0xff; reg 818 sound/pci/ac97/ac97_codec.c old = snd_ac97_read_cache(ac97, reg); reg 825 sound/pci/ac97/ac97_codec.c change = snd_ac97_update_bits_nolock(ac97, reg, mask, value); reg 1025 sound/pci/ac97/ac97_codec.c static int snd_ac97_try_volume_mix(struct snd_ac97 * ac97, int reg) reg 1029 sound/pci/ac97/ac97_codec.c if (! snd_ac97_valid_reg(ac97, reg)) reg 1032 sound/pci/ac97/ac97_codec.c switch (reg) { reg 1041 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, reg); reg 1053 sound/pci/ac97/ac97_codec.c reg = AC97_CENTER_LFE_MASTER; reg 1062 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, reg); reg 1066 sound/pci/ac97/ac97_codec.c snd_ac97_write_cache(ac97, reg, val | mask); reg 1067 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, reg); reg 1068 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, reg); reg 1075 sound/pci/ac97/ac97_codec.c static void check_volume_resolution(struct snd_ac97 *ac97, int reg, unsigned char *lo_max, unsigned char *hi_max) reg 1084 sound/pci/ac97/ac97_codec.c for (tbl = ac97->res_table; tbl->reg; tbl++) { reg 1085 sound/pci/ac97/ac97_codec.c if (tbl->reg == reg) { reg 1097 sound/pci/ac97/ac97_codec.c ac97, reg, reg 1104 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, reg); reg 1105 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, reg); reg 1115 sound/pci/ac97/ac97_codec.c static int snd_ac97_try_bit(struct snd_ac97 * ac97, int reg, int bit) reg 1120 sound/pci/ac97/ac97_codec.c orig = snd_ac97_read(ac97, reg); reg 1122 sound/pci/ac97/ac97_codec.c snd_ac97_write(ac97, reg, val); reg 1123 sound/pci/ac97/ac97_codec.c res = snd_ac97_read(ac97, reg); reg 1124 sound/pci/ac97/ac97_codec.c snd_ac97_write_cache(ac97, reg, orig); reg 1129 sound/pci/ac97/ac97_codec.c static void snd_ac97_change_volume_params2(struct snd_ac97 * ac97, int reg, int shift, unsigned char *max) reg 1135 sound/pci/ac97/ac97_codec.c snd_ac97_write(ac97, reg, val); reg 1136 sound/pci/ac97/ac97_codec.c val1 = snd_ac97_read(ac97, reg); reg 1141 sound/pci/ac97/ac97_codec.c snd_ac97_write_cache(ac97, reg, AC97_MUTE_MASK_STEREO); reg 1167 sound/pci/ac97/ac97_codec.c static int snd_ac97_cmute_new_stereo(struct snd_card *card, char *name, int reg, reg 1175 sound/pci/ac97/ac97_codec.c if (! snd_ac97_valid_reg(ac97, reg)) reg 1179 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, reg); reg 1183 sound/pci/ac97/ac97_codec.c snd_ac97_write(ac97, reg, val1); reg 1184 sound/pci/ac97/ac97_codec.c if (val1 == snd_ac97_read(ac97, reg)) reg 1188 sound/pci/ac97/ac97_codec.c struct snd_kcontrol_new tmp = AC97_DOUBLE(name, reg, 15, 7, 1, 1); reg 1194 sound/pci/ac97/ac97_codec.c struct snd_kcontrol_new tmp = AC97_SINGLE(name, reg, 15, 1, 1); reg 1204 sound/pci/ac97/ac97_codec.c snd_ac97_write_cache(ac97, reg, val | mute_mask); reg 1237 sound/pci/ac97/ac97_codec.c static int snd_ac97_cvol_new(struct snd_card *card, char *name, int reg, unsigned int lo_max, reg 1243 sound/pci/ac97/ac97_codec.c if (! snd_ac97_valid_reg(ac97, reg)) reg 1247 sound/pci/ac97/ac97_codec.c struct snd_kcontrol_new tmp = AC97_DOUBLE(name, reg, 8, 0, lo_max, 1); reg 1252 sound/pci/ac97/ac97_codec.c struct snd_kcontrol_new tmp = AC97_SINGLE(name, reg, 0, lo_max, 1); reg 1258 sound/pci/ac97/ac97_codec.c if (reg >= AC97_PHONE && reg <= AC97_PCM) reg 1266 sound/pci/ac97/ac97_codec.c ac97, reg, reg 1267 sound/pci/ac97/ac97_codec.c (snd_ac97_read(ac97, reg) & AC97_MUTE_MASK_STEREO) reg 1277 sound/pci/ac97/ac97_codec.c int reg, int check_stereo, int check_amix, reg 1284 sound/pci/ac97/ac97_codec.c if (! snd_ac97_valid_reg(ac97, reg)) reg 1287 sound/pci/ac97/ac97_codec.c if (snd_ac97_try_bit(ac97, reg, 15)) { reg 1289 sound/pci/ac97/ac97_codec.c if ((err = snd_ac97_cmute_new_stereo(card, name, reg, reg 1294 sound/pci/ac97/ac97_codec.c check_volume_resolution(ac97, reg, &lo_max, &hi_max); reg 1297 sound/pci/ac97/ac97_codec.c if ((err = snd_ac97_cvol_new(card, name, reg, lo_max, hi_max, ac97)) < 0) reg 1303 sound/pci/ac97/ac97_codec.c #define snd_ac97_cmix_new(card, pfx, reg, acheck, ac97) \ reg 1304 sound/pci/ac97/ac97_codec.c snd_ac97_cmix_new_stereo(card, pfx, reg, 0, acheck, ac97) reg 1305 sound/pci/ac97/ac97_codec.c #define snd_ac97_cmute_new(card, name, reg, acheck, ac97) \ reg 1306 sound/pci/ac97/ac97_codec.c snd_ac97_cmute_new_stereo(card, name, reg, 0, acheck, ac97) reg 1679 sound/pci/ac97/ac97_codec.c static int snd_ac97_test_rate(struct snd_ac97 *ac97, int reg, int shadow_reg, int rate) reg 1685 sound/pci/ac97/ac97_codec.c snd_ac97_write_cache(ac97, reg, tmp & 0xffff); reg 1688 sound/pci/ac97/ac97_codec.c val = snd_ac97_read(ac97, reg); reg 1692 sound/pci/ac97/ac97_codec.c static void snd_ac97_determine_rates(struct snd_ac97 *ac97, int reg, int shadow_reg, unsigned int *r_result) reg 1700 sound/pci/ac97/ac97_codec.c reg == AC97_PCM_FRONT_DAC_RATE) reg 1705 sound/pci/ac97/ac97_codec.c saved = snd_ac97_read(ac97, reg); reg 1706 sound/pci/ac97/ac97_codec.c if ((ac97->ext_id & AC97_EI_DRA) && reg == AC97_PCM_FRONT_DAC_RATE) reg 1710 sound/pci/ac97/ac97_codec.c if (snd_ac97_test_rate(ac97, reg, shadow_reg, 11000)) reg 1713 sound/pci/ac97/ac97_codec.c if (snd_ac97_test_rate(ac97, reg, shadow_reg, 8000)) reg 1715 sound/pci/ac97/ac97_codec.c if (snd_ac97_test_rate(ac97, reg, shadow_reg, 11025)) reg 1717 sound/pci/ac97/ac97_codec.c if (snd_ac97_test_rate(ac97, reg, shadow_reg, 16000)) reg 1719 sound/pci/ac97/ac97_codec.c if (snd_ac97_test_rate(ac97, reg, shadow_reg, 22050)) reg 1721 sound/pci/ac97/ac97_codec.c if (snd_ac97_test_rate(ac97, reg, shadow_reg, 32000)) reg 1723 sound/pci/ac97/ac97_codec.c if (snd_ac97_test_rate(ac97, reg, shadow_reg, 44100)) reg 1725 sound/pci/ac97/ac97_codec.c if (snd_ac97_test_rate(ac97, reg, shadow_reg, 48000)) reg 1728 sound/pci/ac97/ac97_codec.c reg == AC97_PCM_FRONT_DAC_RATE) { reg 1732 sound/pci/ac97/ac97_codec.c if (snd_ac97_test_rate(ac97, reg, shadow_reg, 64000 / 2)) reg 1734 sound/pci/ac97/ac97_codec.c if (snd_ac97_test_rate(ac97, reg, shadow_reg, 88200 / 2)) reg 1736 sound/pci/ac97/ac97_codec.c if (snd_ac97_test_rate(ac97, reg, shadow_reg, 96000 / 2)) reg 1739 sound/pci/ac97/ac97_codec.c if (!snd_ac97_test_rate(ac97, reg, shadow_reg, 76100 / 2)) reg 1745 sound/pci/ac97/ac97_codec.c snd_ac97_write_cache(ac97, reg, saved); reg 2000 sound/pci/ac97/ac97_codec.c unsigned int reg; reg 2190 sound/pci/ac97/ac97_codec.c reg = snd_ac97_read(ac97, AC97_EXTENDED_STATUS); reg 2191 sound/pci/ac97/ac97_codec.c reg |= ac97->ext_id & 0x01c0; /* LDAC/SDAC/CDAC */ reg 2193 sound/pci/ac97/ac97_codec.c reg |= ac97->ext_id & 0x0009; /* VRA/VRM */ reg 2194 sound/pci/ac97/ac97_codec.c snd_ac97_write_cache(ac97, AC97_EXTENDED_STATUS, reg); reg 2341 sound/pci/ac97/ac97_codec.c unsigned short reg; reg 2370 sound/pci/ac97/ac97_codec.c int snd_ac97_update_power(struct snd_ac97 *ac97, int reg, int powerup) reg 2377 sound/pci/ac97/ac97_codec.c if (reg) { reg 2379 sound/pci/ac97/ac97_codec.c if (reg == AC97_SPDIF) reg 2380 sound/pci/ac97/ac97_codec.c reg = AC97_PCM_FRONT_DAC_RATE; reg 2382 sound/pci/ac97/ac97_codec.c if (power_regs[i].reg == reg) { reg 12 sound/pci/ac97/ac97_local.h int snd_ac97_update_bits_nolock(struct snd_ac97 *ac97, unsigned short reg, reg 53 sound/pci/ac97/ac97_patch.c static int ac97_update_bits_page(struct snd_ac97 *ac97, unsigned short reg, unsigned short mask, unsigned short value, unsigned short page) reg 61 sound/pci/ac97/ac97_patch.c ret = snd_ac97_update_bits(ac97, reg, mask, value); reg 1370 sound/pci/ac97/ac97_patch.c unsigned short reg = setup_regs[i]; reg 1371 sound/pci/ac97/ac97_patch.c if (test_bit(reg, ac97->reg_accessed)) { reg 1372 sound/pci/ac97/ac97_patch.c snd_ac97_write(ac97, reg, ac97->regs[reg]); reg 1373 sound/pci/ac97/ac97_patch.c snd_ac97_read(ac97, reg); reg 2316 sound/pci/ac97/ac97_patch.c unsigned short reg = ac97->regs[AC97_AD_MISC2]; reg 2317 sound/pci/ac97/ac97_patch.c if ((reg & AC97_AD1986_MVREF0) != 0) reg 2319 sound/pci/ac97/ac97_patch.c else if ((reg & AC97_AD1986_MVREF1) != 0) reg 2321 sound/pci/ac97/ac97_patch.c else if ((reg & AC97_AD1986_MVREF2) != 0) reg 10 sound/pci/ac97/ac97_patch.h #define AC97_SINGLE_VALUE(reg,shift,mask,invert) \ reg 11 sound/pci/ac97/ac97_patch.h ((reg) | ((shift) << 8) | ((shift) << 12) | ((mask) << 16) | \ reg 13 sound/pci/ac97/ac97_patch.h #define AC97_PAGE_SINGLE_VALUE(reg,shift,mask,invert,page) \ reg 14 sound/pci/ac97/ac97_patch.h (AC97_SINGLE_VALUE(reg,shift,mask,invert) | (1<<25) | ((page) << 26)) reg 15 sound/pci/ac97/ac97_patch.h #define AC97_SINGLE(xname, reg, shift, mask, invert) \ reg 19 sound/pci/ac97/ac97_patch.h .private_value = AC97_SINGLE_VALUE(reg, shift, mask, invert) } reg 20 sound/pci/ac97/ac97_patch.h #define AC97_PAGE_SINGLE(xname, reg, shift, mask, invert, page) \ reg 24 sound/pci/ac97/ac97_patch.h .private_value = AC97_PAGE_SINGLE_VALUE(reg, shift, mask, invert, page) } reg 25 sound/pci/ac97/ac97_patch.h #define AC97_DOUBLE(xname, reg, shift_left, shift_right, mask, invert) \ reg 29 sound/pci/ac97/ac97_patch.h .private_value = (reg) | ((shift_left) << 8) | ((shift_right) << 12) | ((mask) << 16) | ((invert) << 24) } reg 33 sound/pci/ac97/ac97_patch.h unsigned char reg; reg 41 sound/pci/ac97/ac97_patch.h { .reg = xreg, .shift_l = xshift_l, .shift_r = xshift_r, \ reg 62 sound/pci/ac97/ac97_patch.h static int snd_ac97_try_bit(struct snd_ac97 * ac97, int reg, int bit); reg 161 sound/pci/ac97/ac97_pcm.c unsigned short old, bits, reg, mask; reg 176 sound/pci/ac97/ac97_pcm.c reg = AC97_CSR_SPDIF; reg 191 sound/pci/ac97/ac97_pcm.c reg = AC97_SPDIF; reg 196 sound/pci/ac97/ac97_pcm.c old = snd_ac97_read(ac97, reg) & mask; reg 199 sound/pci/ac97/ac97_pcm.c snd_ac97_update_bits_nolock(ac97, reg, mask, bits); reg 243 sound/pci/ac97/ac97_pcm.c int snd_ac97_set_rate(struct snd_ac97 *ac97, int reg, unsigned int rate) reg 252 sound/pci/ac97/ac97_pcm.c if (reg != AC97_PCM_FRONT_DAC_RATE) reg 256 sound/pci/ac97/ac97_pcm.c snd_ac97_update_power(ac97, reg, 1); reg 257 sound/pci/ac97/ac97_pcm.c switch (reg) { reg 288 sound/pci/ac97/ac97_pcm.c if ((ac97->ext_id & AC97_EI_DRA) && reg == AC97_PCM_FRONT_DAC_RATE) reg 291 sound/pci/ac97/ac97_pcm.c snd_ac97_update(ac97, reg, tmp & 0xffff); reg 292 sound/pci/ac97/ac97_pcm.c snd_ac97_read(ac97, reg); reg 293 sound/pci/ac97/ac97_pcm.c if ((ac97->ext_id & AC97_EI_DRA) && reg == AC97_PCM_FRONT_DAC_RATE) { reg 397 sound/pci/ac97/ac97_pcm.c unsigned char reg; reg 402 sound/pci/ac97/ac97_pcm.c reg = get_slot_reg(pcm, cidx, i, dbl); reg 403 sound/pci/ac97/ac97_pcm.c switch (reg) { reg 561 sound/pci/ac97/ac97_pcm.c unsigned char reg; reg 606 sound/pci/ac97/ac97_pcm.c reg = get_slot_reg(pcm, cidx, i, r); reg 607 sound/pci/ac97/ac97_pcm.c if (reg == 0xff) { reg 612 sound/pci/ac97/ac97_pcm.c if (reg_ok[cidx] & (1 << (reg - AC97_PCM_FRONT_DAC_RATE))) reg 616 sound/pci/ac97/ac97_pcm.c reg, rate); reg 617 sound/pci/ac97/ac97_pcm.c err = snd_ac97_set_rate(pcm->r[r].codec[cidx], reg, rate); reg 621 sound/pci/ac97/ac97_pcm.c cidx, reg, rate, err); reg 623 sound/pci/ac97/ac97_pcm.c reg_ok[cidx] |= (1 << (reg - AC97_PCM_FRONT_DAC_RATE)); reg 659 sound/pci/ac97/ac97_pcm.c int reg = get_slot_reg(pcm, cidx, i, r); reg 661 sound/pci/ac97/ac97_pcm.c reg, 0); reg 367 sound/pci/ac97/ac97_proc.c unsigned int reg, val; reg 370 sound/pci/ac97/ac97_proc.c if (sscanf(line, "%x %x", ®, &val) != 2) reg 373 sound/pci/ac97/ac97_proc.c if (reg < 0x80 && (reg & 1) == 0 && val <= 0xffff) reg 374 sound/pci/ac97/ac97_proc.c snd_ac97_write_cache(ac97, reg, val); reg 382 sound/pci/ac97/ac97_proc.c int reg, val; reg 384 sound/pci/ac97/ac97_proc.c for (reg = 0; reg < 0x80; reg += 2) { reg 385 sound/pci/ac97/ac97_proc.c val = snd_ac97_read(ac97, reg); reg 386 sound/pci/ac97/ac97_proc.c snd_iprintf(buffer, "%i:%02x = %04x\n", subidx, reg, val); reg 69 sound/pci/ad1889.c u16 reg; /* reg setup */ reg 98 sound/pci/ad1889.c ad1889_readw(struct snd_ad1889 *chip, unsigned reg) reg 100 sound/pci/ad1889.c return readw(chip->iobase + reg); reg 104 sound/pci/ad1889.c ad1889_writew(struct snd_ad1889 *chip, unsigned reg, u16 val) reg 106 sound/pci/ad1889.c writew(val, chip->iobase + reg); reg 110 sound/pci/ad1889.c ad1889_readl(struct snd_ad1889 *chip, unsigned reg) reg 112 sound/pci/ad1889.c return readl(chip->iobase + reg); reg 116 sound/pci/ad1889.c ad1889_writel(struct snd_ad1889 *chip, unsigned reg, u32 val) reg 118 sound/pci/ad1889.c writel(val, chip->iobase + reg); reg 185 sound/pci/ad1889.c u16 reg; reg 189 sound/pci/ad1889.c reg = ad1889_readw(chip, AD_DS_WSMC) & ~AD_DS_WSMC_WAEN; reg 190 sound/pci/ad1889.c ad1889_writew(chip, AD_DS_WSMC, reg); reg 191 sound/pci/ad1889.c chip->wave.reg = reg; reg 194 sound/pci/ad1889.c reg = ad1889_readw(chip, AD_DMA_WAV); reg 195 sound/pci/ad1889.c reg &= AD_DMA_IM_DIS; reg 196 sound/pci/ad1889.c reg &= ~AD_DMA_LOOP; reg 197 sound/pci/ad1889.c ad1889_writew(chip, AD_DMA_WAV, reg); reg 210 sound/pci/ad1889.c reg = ad1889_readw(chip, AD_DS_RAMC) & ~AD_DS_RAMC_ADEN; reg 211 sound/pci/ad1889.c ad1889_writew(chip, AD_DS_RAMC, reg); reg 212 sound/pci/ad1889.c chip->ramc.reg = reg; reg 214 sound/pci/ad1889.c reg = ad1889_readw(chip, AD_DMA_ADC); reg 215 sound/pci/ad1889.c reg &= AD_DMA_IM_DIS; reg 216 sound/pci/ad1889.c reg &= ~AD_DMA_LOOP; reg 217 sound/pci/ad1889.c ad1889_writew(chip, AD_DMA_ADC, reg); reg 229 sound/pci/ad1889.c snd_ad1889_ac97_read(struct snd_ac97 *ac97, unsigned short reg) reg 232 sound/pci/ad1889.c return ad1889_readw(chip, AD_AC97_BASE + reg); reg 236 sound/pci/ad1889.c snd_ad1889_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) reg 239 sound/pci/ad1889.c ad1889_writew(chip, AD_AC97_BASE + reg, val); reg 355 sound/pci/ad1889.c u16 reg; reg 359 sound/pci/ad1889.c reg = ad1889_readw(chip, AD_DS_WSMC); reg 362 sound/pci/ad1889.c reg &= ~(AD_DS_WSMC_WA16 | AD_DS_WSMC_WAST); reg 365 sound/pci/ad1889.c reg |= AD_DS_WSMC_WA16; reg 368 sound/pci/ad1889.c reg |= AD_DS_WSMC_WAST; reg 374 sound/pci/ad1889.c chip->wave.reg = reg; reg 377 sound/pci/ad1889.c ad1889_writew(chip, AD_DS_WSMC, chip->wave.reg); reg 394 sound/pci/ad1889.c chip->wave.addr, count, size, reg, rt->rate); reg 405 sound/pci/ad1889.c u16 reg; reg 409 sound/pci/ad1889.c reg = ad1889_readw(chip, AD_DS_RAMC); reg 412 sound/pci/ad1889.c reg &= ~(AD_DS_RAMC_AD16 | AD_DS_RAMC_ADST); reg 415 sound/pci/ad1889.c reg |= AD_DS_RAMC_AD16; reg 418 sound/pci/ad1889.c reg |= AD_DS_RAMC_ADST; reg 424 sound/pci/ad1889.c chip->ramc.reg = reg; reg 427 sound/pci/ad1889.c ad1889_writew(chip, AD_DS_RAMC, chip->ramc.reg); reg 441 sound/pci/ad1889.c chip->ramc.addr, count, size, reg, rt->rate); reg 475 sound/pci/ad1889.c chip->wave.reg = wsmc; reg 513 sound/pci/ad1889.c chip->ramc.reg = ramc; reg 531 sound/pci/ad1889.c if (unlikely(!(chip->wave.reg & AD_DS_WSMC_WAEN))) reg 550 sound/pci/ad1889.c if (unlikely(!(chip->ramc.reg & AD_DS_RAMC_ADEN))) reg 647 sound/pci/ad1889.c u16 reg; reg 650 sound/pci/ad1889.c reg = ad1889_readw(chip, AD_DS_WSMC); reg 652 sound/pci/ad1889.c (reg & AD_DS_WSMC_WAEN) ? "enabled" : "disabled"); reg 654 sound/pci/ad1889.c (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono"); reg 656 sound/pci/ad1889.c (reg & AD_DS_WSMC_WA16) ? 16 : 8); reg 659 sound/pci/ad1889.c tmp = (reg & AD_DS_WSMC_WARQ) ? reg 660 sound/pci/ad1889.c ((((reg & AD_DS_WSMC_WARQ) >> 12) & 0x01) ? 12 : 18) : 4; reg 661 sound/pci/ad1889.c tmp /= (reg & AD_DS_WSMC_WAST) ? 2 : 1; reg 664 sound/pci/ad1889.c (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono"); reg 668 sound/pci/ad1889.c reg & AD_DS_WSMC_SYEN ? "enabled" : "disabled"); reg 671 sound/pci/ad1889.c tmp = (reg & AD_DS_WSMC_SYRQ) ? reg 672 sound/pci/ad1889.c ((((reg & AD_DS_WSMC_SYRQ) >> 4) & 0x01) ? 12 : 18) : 4; reg 673 sound/pci/ad1889.c tmp /= (reg & AD_DS_WSMC_WAST) ? 2 : 1; reg 676 sound/pci/ad1889.c (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono"); reg 678 sound/pci/ad1889.c reg = ad1889_readw(chip, AD_DS_RAMC); reg 680 sound/pci/ad1889.c (reg & AD_DS_RAMC_ADEN) ? "enabled" : "disabled"); reg 682 sound/pci/ad1889.c (reg & AD_DS_RAMC_ADST) ? "stereo" : "mono"); reg 684 sound/pci/ad1889.c (reg & AD_DS_RAMC_AD16) ? 16 : 8); reg 687 sound/pci/ad1889.c tmp = (reg & AD_DS_RAMC_ACRQ) ? reg 688 sound/pci/ad1889.c ((((reg & AD_DS_RAMC_ACRQ) >> 4) & 0x01) ? 12 : 18) : 4; reg 689 sound/pci/ad1889.c tmp /= (reg & AD_DS_RAMC_ADST) ? 2 : 1; reg 692 sound/pci/ad1889.c (reg & AD_DS_RAMC_ADST) ? "stereo" : "mono"); reg 695 sound/pci/ad1889.c reg & AD_DS_RAMC_REEN ? "enabled" : "disabled"); reg 698 sound/pci/ad1889.c tmp = (reg & AD_DS_RAMC_RERQ) ? reg 699 sound/pci/ad1889.c ((((reg & AD_DS_RAMC_RERQ) >> 12) & 0x01) ? 12 : 18) : 4; reg 700 sound/pci/ad1889.c tmp /= (reg & AD_DS_RAMC_ADST) ? 2 : 1; reg 703 sound/pci/ad1889.c (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono"); reg 709 sound/pci/ad1889.c reg = ad1889_readw(chip, AD_DS_WADA); reg 711 sound/pci/ad1889.c (reg & AD_DS_WADA_LWAM) ? "mute" : "unmute", reg 712 sound/pci/ad1889.c ((reg & AD_DS_WADA_LWAA) >> 8) * 3); reg 713 sound/pci/ad1889.c reg = ad1889_readw(chip, AD_DS_WADA); reg 715 sound/pci/ad1889.c (reg & AD_DS_WADA_RWAM) ? "mute" : "unmute", reg 716 sound/pci/ad1889.c (reg & AD_DS_WADA_RWAA) * 3); reg 718 sound/pci/ad1889.c reg = ad1889_readw(chip, AD_DS_WAS); reg 719 sound/pci/ad1889.c snd_iprintf(buffer, "Wave samplerate: %u Hz\n", reg); reg 720 sound/pci/ad1889.c reg = ad1889_readw(chip, AD_DS_RES); reg 721 sound/pci/ad1889.c snd_iprintf(buffer, "Resampler samplerate: %u Hz\n", reg); reg 745 sound/pci/ad1889.c u16 reg; reg 747 sound/pci/ad1889.c reg = ad1889_readw(chip, AD_AC97_ACIC); reg 748 sound/pci/ad1889.c reg |= AD_AC97_ACIC_ACRD; /* Reset Disable */ reg 749 sound/pci/ad1889.c ad1889_writew(chip, AD_AC97_ACIC, reg); reg 753 sound/pci/ad1889.c reg |= AD_AC97_ACIC_ACIE; reg 754 sound/pci/ad1889.c ad1889_writew(chip, AD_AC97_ACIC, reg); reg 759 sound/pci/ad1889.c reg = ad1889_readw(chip, AD_AC97_ACIC); reg 760 sound/pci/ad1889.c reg |= AD_AC97_ACIC_ASOE | AD_AC97_ACIC_VSRM; reg 761 sound/pci/ad1889.c ad1889_writew(chip, AD_AC97_ACIC, reg); reg 46 sound/pci/ak4531_codec.c #define AK4531_SINGLE(xname, xindex, reg, shift, mask, invert) \ reg 50 sound/pci/ak4531_codec.c .private_value = reg | (shift << 16) | (mask << 24) | (invert << 22) } reg 51 sound/pci/ak4531_codec.c #define AK4531_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \ reg 57 sound/pci/ak4531_codec.c .private_value = reg | (shift << 16) | (mask << 24) | (invert << 22), \ reg 74 sound/pci/ak4531_codec.c int reg = kcontrol->private_value & 0xff; reg 81 sound/pci/ak4531_codec.c val = (ak4531->regs[reg] >> shift) & mask; reg 93 sound/pci/ak4531_codec.c int reg = kcontrol->private_value & 0xff; reg 106 sound/pci/ak4531_codec.c val = (ak4531->regs[reg] & ~(mask << shift)) | val; reg 107 sound/pci/ak4531_codec.c change = val != ak4531->regs[reg]; reg 108 sound/pci/ak4531_codec.c ak4531->write(ak4531, reg, ak4531->regs[reg] = val); reg 324 sound/pci/ali5451/ali5451.c unsigned short reg, reg 330 sound/pci/ali5451/ali5451.c if (reg >= 0x80) { reg 332 sound/pci/ali5451/ali5451.c "ali_codec_poke: reg(%xh) invalid.\n", reg); reg 343 sound/pci/ali5451/ali5451.c dwVal = (unsigned int) (reg & 0xff); reg 357 sound/pci/ali5451/ali5451.c unsigned short reg) reg 362 sound/pci/ali5451/ali5451.c if (reg >= 0x80) { reg 364 sound/pci/ali5451/ali5451.c "ali_codec_peek: reg(%xh) invalid.\n", reg); reg 375 sound/pci/ali5451/ali5451.c dwVal = (unsigned int) (reg & 0xff); reg 391 sound/pci/ali5451/ali5451.c unsigned short reg, reg 396 sound/pci/ali5451/ali5451.c dev_dbg(codec->card->dev, "codec_write: reg=%xh data=%xh.\n", reg, val); reg 397 sound/pci/ali5451/ali5451.c if (reg == AC97_GPIO_STATUS) { reg 402 sound/pci/ali5451/ali5451.c snd_ali_codec_poke(codec, ac97->num, reg, val); reg 408 sound/pci/ali5451/ali5451.c unsigned short reg) reg 412 sound/pci/ali5451/ali5451.c dev_dbg(codec->card->dev, "codec_read reg=%xh.\n", reg); reg 413 sound/pci/ali5451/ali5451.c return snd_ali_codec_peek(codec, ac97->num, reg); reg 138 sound/pci/als300.c static inline u32 snd_als300_gcr_read(unsigned long port, unsigned short reg) reg 140 sound/pci/als300.c outb(reg, port+GCR_INDEX); reg 145 sound/pci/als300.c unsigned short reg, u32 val) reg 147 sound/pci/als300.c outb(reg, port+GCR_INDEX); reg 258 sound/pci/als300.c unsigned short reg) reg 268 sound/pci/als300.c outl((reg << 24) | (1 << 31), chip->port+AC97_ACCESS); reg 279 sound/pci/als300.c unsigned short reg, unsigned short val) reg 289 sound/pci/als300.c outl((reg << 24) | val, chip->port+AC97_ACCESS); reg 489 sound/pci/als300.c unsigned short reg; reg 493 sound/pci/als300.c reg = data->control_register; reg 499 sound/pci/als300.c tmp = snd_als300_gcr_read(chip->port, reg); reg 501 sound/pci/als300.c snd_als300_gcr_write(chip->port, reg, tmp | TRANSFER_START); reg 506 sound/pci/als300.c tmp = snd_als300_gcr_read(chip->port, reg); reg 507 sound/pci/als300.c snd_als300_gcr_write(chip->port, reg, tmp & ~TRANSFER_START); reg 511 sound/pci/als300.c tmp = snd_als300_gcr_read(chip->port, reg); reg 512 sound/pci/als300.c snd_als300_gcr_write(chip->port, reg, tmp | FIFO_PAUSE); reg 516 sound/pci/als300.c tmp = snd_als300_gcr_read(chip->port, reg); reg 517 sound/pci/als300.c snd_als300_gcr_write(chip->port, reg, tmp & ~FIFO_PAUSE); reg 178 sound/pci/als4000.c enum als4k_iobase_t reg, reg 181 sound/pci/als4000.c outb(val, iobase + reg); reg 185 sound/pci/als4000.c enum als4k_iobase_t reg, reg 188 sound/pci/als4000.c outl(val, iobase + reg); reg 192 sound/pci/als4000.c enum als4k_iobase_t reg) reg 194 sound/pci/als4000.c return inb(iobase + reg); reg 198 sound/pci/als4000.c enum als4k_iobase_t reg) reg 200 sound/pci/als4000.c return inl(iobase + reg); reg 204 sound/pci/als4000.c enum als4k_gcr_t reg, reg 207 sound/pci/als4000.c snd_als4k_iobase_writeb(iobase, ALS4K_IOB_0C_GCR_INDEX, reg); reg 212 sound/pci/als4000.c enum als4k_gcr_t reg, reg 215 sound/pci/als4000.c snd_als4k_gcr_write_addr(sb->alt_port, reg, val); reg 219 sound/pci/als4000.c enum als4k_gcr_t reg) reg 222 sound/pci/als4000.c snd_als4k_iobase_writeb(iobase, ALS4K_IOB_0C_GCR_INDEX, reg); reg 226 sound/pci/als4000.c static inline u32 snd_als4k_gcr_read(struct snd_sb *sb, enum als4k_gcr_t reg) reg 228 sound/pci/als4000.c return snd_als4k_gcr_read_addr(sb->alt_port, reg); reg 256 sound/pci/als4000.c enum als4k_cr_t reg, reg 262 sound/pci/als4000.c snd_sbmixer_write(chip, reg | 0xc0, data); reg 266 sound/pci/als4000.c enum als4k_cr_t reg) reg 269 sound/pci/als4000.c return snd_sbmixer_read(chip, reg | 0xc0); reg 299 sound/pci/atiixp.c static int snd_atiixp_update_bits(struct atiixp *chip, unsigned int reg, reg 302 sound/pci/atiixp.c void __iomem *addr = chip->remap_addr + reg; reg 316 sound/pci/atiixp.c #define atiixp_write(chip,reg,value) \ reg 317 sound/pci/atiixp.c writel(value, chip->remap_addr + ATI_REG_##reg) reg 318 sound/pci/atiixp.c #define atiixp_read(chip,reg) \ reg 319 sound/pci/atiixp.c readl(chip->remap_addr + ATI_REG_##reg) reg 320 sound/pci/atiixp.c #define atiixp_update(chip,reg,mask,val) \ reg 321 sound/pci/atiixp.c snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val) reg 429 sound/pci/atiixp.c static unsigned short snd_atiixp_codec_read(struct atiixp *chip, unsigned short codec, unsigned short reg) reg 436 sound/pci/atiixp.c data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | reg 451 sound/pci/atiixp.c if (reg < 0x7c) reg 452 sound/pci/atiixp.c dev_warn(chip->card->dev, "codec read timeout (reg %x)\n", reg); reg 458 sound/pci/atiixp.c unsigned short reg, unsigned short val) reg 465 sound/pci/atiixp.c ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | reg 472 sound/pci/atiixp.c unsigned short reg) reg 475 sound/pci/atiixp.c return snd_atiixp_codec_read(chip, ac97->num, reg); reg 479 sound/pci/atiixp.c static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg, reg 483 sound/pci/atiixp.c snd_atiixp_codec_write(chip, ac97->num, reg, val); reg 600 sound/pci/atiixp.c unsigned int reg; reg 603 sound/pci/atiixp.c reg = atiixp_read(chip, CMD); reg 604 sound/pci/atiixp.c reg |= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT; reg 605 sound/pci/atiixp.c reg |= ATI_REG_CMD_BURST_EN; reg 606 sound/pci/atiixp.c atiixp_write(chip, CMD, reg); reg 608 sound/pci/atiixp.c reg = atiixp_read(chip, SPDF_CMD); reg 609 sound/pci/atiixp.c reg &= ~(ATI_REG_SPDF_CMD_LFSR|ATI_REG_SPDF_CMD_SINGLE_CH); reg 610 sound/pci/atiixp.c atiixp_write(chip, SPDF_CMD, reg); reg 267 sound/pci/atiixp_modem.c static int snd_atiixp_update_bits(struct atiixp_modem *chip, unsigned int reg, reg 270 sound/pci/atiixp_modem.c void __iomem *addr = chip->remap_addr + reg; reg 284 sound/pci/atiixp_modem.c #define atiixp_write(chip,reg,value) \ reg 285 sound/pci/atiixp_modem.c writel(value, chip->remap_addr + ATI_REG_##reg) reg 286 sound/pci/atiixp_modem.c #define atiixp_read(chip,reg) \ reg 287 sound/pci/atiixp_modem.c readl(chip->remap_addr + ATI_REG_##reg) reg 288 sound/pci/atiixp_modem.c #define atiixp_update(chip,reg,mask,val) \ reg 289 sound/pci/atiixp_modem.c snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val) reg 399 sound/pci/atiixp_modem.c unsigned short reg) reg 406 sound/pci/atiixp_modem.c data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | reg 421 sound/pci/atiixp_modem.c if (reg < 0x7c) reg 422 sound/pci/atiixp_modem.c dev_warn(chip->card->dev, "codec read timeout (reg %x)\n", reg); reg 429 sound/pci/atiixp_modem.c unsigned short reg, unsigned short val) reg 436 sound/pci/atiixp_modem.c ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | reg 443 sound/pci/atiixp_modem.c unsigned short reg) reg 446 sound/pci/atiixp_modem.c return snd_atiixp_codec_read(chip, ac97->num, reg); reg 450 sound/pci/atiixp_modem.c static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg, reg 454 sound/pci/atiixp_modem.c if (reg == AC97_GPIO_STATUS) { reg 459 sound/pci/atiixp_modem.c snd_atiixp_codec_write(chip, ac97->num, reg, val); reg 554 sound/pci/atiixp_modem.c unsigned int reg; reg 557 sound/pci/atiixp_modem.c reg = atiixp_read(chip, CMD); reg 558 sound/pci/atiixp_modem.c reg |= ATI_REG_CMD_BURST_EN; reg 559 sound/pci/atiixp_modem.c if(!(reg & ATI_REG_CMD_MODEM_PRESENT)) reg 560 sound/pci/atiixp_modem.c reg |= ATI_REG_CMD_MODEM_PRESENT; reg 561 sound/pci/atiixp_modem.c atiixp_write(chip, CMD, reg); reg 106 sound/pci/au88x0/au88x0_a3d.h #define a3d_addrA(slice,source,reg) (((slice)<<0xd)+((source)*0x3A4)+(reg)) reg 107 sound/pci/au88x0/au88x0_a3d.h #define a3d_addrB(slice,source,reg) (((slice)<<0xd)+((source)*0x2C8)+(reg)) reg 108 sound/pci/au88x0/au88x0_a3d.h #define a3d_addrS(slice,reg) (((slice)<<0xd)+(reg)) reg 368 sound/pci/au88x0/au88x0_eq.c static void vortex_EqHw_SetControlReg(vortex_t * vortex, u32 reg) reg 370 sound/pci/au88x0/au88x0_eq.c hwwrite(vortex->mmio, 0x2b440, reg); reg 379 sound/pci/au88x0/au88x0_eq.c static void vortex_EqHw_GetControlReg(vortex_t * vortex, u32 *reg) reg 381 sound/pci/au88x0/au88x0_eq.c *reg = hwread(vortex->mmio, 0x2b440); reg 22 sound/pci/au88x0/au88x0_synth.c static int vortex_wt_SetReg(vortex_t * vortex, unsigned char reg, int wt, reg 142 sound/pci/au88x0/au88x0_synth.c static int vortex_wt_GetReg(vortex_t * vortex, char reg, int wt) reg 146 sound/pci/au88x0/au88x0_synth.c if (reg == 4) { reg 149 sound/pci/au88x0/au88x0_synth.c if (reg == 7) { reg 158 sound/pci/au88x0/au88x0_synth.c vortex_wt_SetReg2(vortex_t * vortex, unsigned char reg, int wt, reg 182 sound/pci/au88x0/au88x0_synth.c vortex_wt_SetReg(vortex_t * vortex, unsigned char reg, int wt, reg 187 sound/pci/au88x0/au88x0_synth.c if ((reg == 5) || ((reg >= 7) && (reg <= 10)) || (reg == 0xc)) { reg 191 sound/pci/au88x0/au88x0_synth.c reg, wt); reg 201 sound/pci/au88x0/au88x0_synth.c if (reg > 0xc) reg 204 sound/pci/au88x0/au88x0_synth.c switch (reg) { reg 320 sound/pci/azt3328.c snd_azf3328_io_reg_setb(unsigned reg, u8 mask, bool do_set) reg 325 sound/pci/azt3328.c u8 prev = inb(reg), new; reg 330 sound/pci/azt3328.c outb(new, reg); reg 339 sound/pci/azt3328.c unsigned reg, reg 343 sound/pci/azt3328.c outb(value, codec->io_base + reg); reg 347 sound/pci/azt3328.c snd_azf3328_codec_inb(const struct snd_azf3328_codec_data *codec, unsigned reg) reg 349 sound/pci/azt3328.c return inb(codec->io_base + reg); reg 354 sound/pci/azt3328.c unsigned reg, reg 358 sound/pci/azt3328.c outw(value, codec->io_base + reg); reg 362 sound/pci/azt3328.c snd_azf3328_codec_inw(const struct snd_azf3328_codec_data *codec, unsigned reg) reg 364 sound/pci/azt3328.c return inw(codec->io_base + reg); reg 369 sound/pci/azt3328.c unsigned reg, reg 373 sound/pci/azt3328.c outl(value, codec->io_base + reg); reg 378 sound/pci/azt3328.c unsigned reg, const void *buffer, int count reg 381 sound/pci/azt3328.c unsigned long addr = codec->io_base + reg; reg 392 sound/pci/azt3328.c snd_azf3328_codec_inl(const struct snd_azf3328_codec_data *codec, unsigned reg) reg 394 sound/pci/azt3328.c return inl(codec->io_base + reg); reg 398 sound/pci/azt3328.c snd_azf3328_ctrl_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value) reg 400 sound/pci/azt3328.c outb(value, chip->ctrl_io + reg); reg 404 sound/pci/azt3328.c snd_azf3328_ctrl_inb(const struct snd_azf3328 *chip, unsigned reg) reg 406 sound/pci/azt3328.c return inb(chip->ctrl_io + reg); reg 410 sound/pci/azt3328.c snd_azf3328_ctrl_inw(const struct snd_azf3328 *chip, unsigned reg) reg 412 sound/pci/azt3328.c return inw(chip->ctrl_io + reg); reg 416 sound/pci/azt3328.c snd_azf3328_ctrl_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) reg 418 sound/pci/azt3328.c outw(value, chip->ctrl_io + reg); reg 422 sound/pci/azt3328.c snd_azf3328_ctrl_outl(const struct snd_azf3328 *chip, unsigned reg, u32 value) reg 424 sound/pci/azt3328.c outl(value, chip->ctrl_io + reg); reg 428 sound/pci/azt3328.c snd_azf3328_game_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value) reg 430 sound/pci/azt3328.c outb(value, chip->game_io + reg); reg 434 sound/pci/azt3328.c snd_azf3328_game_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) reg 436 sound/pci/azt3328.c outw(value, chip->game_io + reg); reg 440 sound/pci/azt3328.c snd_azf3328_game_inb(const struct snd_azf3328 *chip, unsigned reg) reg 442 sound/pci/azt3328.c return inb(chip->game_io + reg); reg 446 sound/pci/azt3328.c snd_azf3328_game_inw(const struct snd_azf3328 *chip, unsigned reg) reg 448 sound/pci/azt3328.c return inw(chip->game_io + reg); reg 452 sound/pci/azt3328.c snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) reg 454 sound/pci/azt3328.c outw(value, chip->mixer_io + reg); reg 458 sound/pci/azt3328.c snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, unsigned reg) reg 460 sound/pci/azt3328.c return inw(chip->mixer_io + reg); reg 467 sound/pci/azt3328.c unsigned reg, bool do_mute reg 470 sound/pci/azt3328.c unsigned long portbase = chip->mixer_io + reg + 1; reg 519 sound/pci/azt3328.c unsigned short reg, const char *mode) reg 524 sound/pci/azt3328.c mode, reg); reg 542 sound/pci/azt3328.c snd_azf3328_mixer_ac97_map_reg_idx(unsigned short reg) reg 585 sound/pci/azt3328.c if (reg <= AC97_3D_CONTROL) { reg 586 sound/pci/azt3328.c unsigned short reg_idx = reg / 2; reg 592 sound/pci/azt3328.c switch (reg) { reg 798 sound/pci/azt3328.c unsigned reg, reg 804 sound/pci/azt3328.c unsigned long portbase = chip->mixer_io + reg; reg 854 sound/pci/azt3328.c unsigned reg; reg 862 sound/pci/azt3328.c #define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \ reg 863 sound/pci/azt3328.c ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \ reg 871 sound/pci/azt3328.c r->reg = val & 0xff; reg 884 sound/pci/azt3328.c #define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \ reg 888 sound/pci/azt3328.c .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \ reg 891 sound/pci/azt3328.c #define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \ reg 895 sound/pci/azt3328.c .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \ reg 898 sound/pci/azt3328.c #define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \ reg 902 sound/pci/azt3328.c .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \ reg 905 sound/pci/azt3328.c #define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \ reg 909 sound/pci/azt3328.c .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \ reg 912 sound/pci/azt3328.c #define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \ reg 916 sound/pci/azt3328.c .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \ reg 923 sound/pci/azt3328.c struct azf3328_mixer_reg reg; reg 925 sound/pci/azt3328.c snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); reg 926 sound/pci/azt3328.c uinfo->type = reg.mask == 1 ? reg 928 sound/pci/azt3328.c uinfo->count = reg.stereo + 1; reg 930 sound/pci/azt3328.c uinfo->value.integer.max = reg.mask; reg 939 sound/pci/azt3328.c struct azf3328_mixer_reg reg; reg 942 sound/pci/azt3328.c snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); reg 944 sound/pci/azt3328.c oreg = snd_azf3328_mixer_inw(chip, reg.reg); reg 945 sound/pci/azt3328.c val = (oreg >> reg.lchan_shift) & reg.mask; reg 946 sound/pci/azt3328.c if (reg.invert) reg 947 sound/pci/azt3328.c val = reg.mask - val; reg 949 sound/pci/azt3328.c if (reg.stereo) { reg 950 sound/pci/azt3328.c val = (oreg >> reg.rchan_shift) & reg.mask; reg 951 sound/pci/azt3328.c if (reg.invert) reg 952 sound/pci/azt3328.c val = reg.mask - val; reg 957 sound/pci/azt3328.c reg.reg, oreg, reg 959 sound/pci/azt3328.c reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo); reg 968 sound/pci/azt3328.c struct azf3328_mixer_reg reg; reg 971 sound/pci/azt3328.c snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); reg 972 sound/pci/azt3328.c oreg = snd_azf3328_mixer_inw(chip, reg.reg); reg 973 sound/pci/azt3328.c val = ucontrol->value.integer.value[0] & reg.mask; reg 974 sound/pci/azt3328.c if (reg.invert) reg 975 sound/pci/azt3328.c val = reg.mask - val; reg 976 sound/pci/azt3328.c nreg = oreg & ~(reg.mask << reg.lchan_shift); reg 977 sound/pci/azt3328.c nreg |= (val << reg.lchan_shift); reg 978 sound/pci/azt3328.c if (reg.stereo) { reg 979 sound/pci/azt3328.c val = ucontrol->value.integer.value[1] & reg.mask; reg 980 sound/pci/azt3328.c if (reg.invert) reg 981 sound/pci/azt3328.c val = reg.mask - val; reg 982 sound/pci/azt3328.c nreg &= ~(reg.mask << reg.rchan_shift); reg 983 sound/pci/azt3328.c nreg |= (val << reg.rchan_shift); reg 985 sound/pci/azt3328.c if (reg.mask >= 0x07) /* it's a volume control, so better take care */ reg 987 sound/pci/azt3328.c chip, reg.reg, nreg >> 8, nreg & 0xff, reg 992 sound/pci/azt3328.c snd_azf3328_mixer_outw(chip, reg.reg, nreg); reg 996 sound/pci/azt3328.c reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1], reg 997 sound/pci/azt3328.c oreg, reg.lchan_shift, reg.rchan_shift, reg 998 sound/pci/azt3328.c nreg, snd_azf3328_mixer_inw(chip, reg.reg)); reg 1019 sound/pci/azt3328.c struct azf3328_mixer_reg reg; reg 1022 sound/pci/azt3328.c snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); reg 1023 sound/pci/azt3328.c if (reg.reg == IDX_MIXER_ADVCTL2) { reg 1024 sound/pci/azt3328.c switch(reg.lchan_shift) { reg 1035 sound/pci/azt3328.c } else if (reg.reg == IDX_MIXER_REC_SELECT) reg 1039 sound/pci/azt3328.c (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1, reg 1040 sound/pci/azt3328.c reg.enum_c, p); reg 1048 sound/pci/azt3328.c struct azf3328_mixer_reg reg; reg 1051 sound/pci/azt3328.c snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); reg 1052 sound/pci/azt3328.c val = snd_azf3328_mixer_inw(chip, reg.reg); reg 1053 sound/pci/azt3328.c if (reg.reg == IDX_MIXER_REC_SELECT) { reg 1054 sound/pci/azt3328.c ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1); reg 1055 sound/pci/azt3328.c ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1); reg 1057 sound/pci/azt3328.c ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1); reg 1061 sound/pci/azt3328.c reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1], reg 1062 sound/pci/azt3328.c reg.lchan_shift, reg.enum_c); reg 1071 sound/pci/azt3328.c struct azf3328_mixer_reg reg; reg 1074 sound/pci/azt3328.c snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); reg 1075 sound/pci/azt3328.c oreg = snd_azf3328_mixer_inw(chip, reg.reg); reg 1077 sound/pci/azt3328.c if (reg.reg == IDX_MIXER_REC_SELECT) { reg 1078 sound/pci/azt3328.c if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U || reg 1079 sound/pci/azt3328.c ucontrol->value.enumerated.item[1] > reg.enum_c - 1U) reg 1084 sound/pci/azt3328.c if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U) reg 1086 sound/pci/azt3328.c val &= ~((reg.enum_c - 1) << reg.lchan_shift); reg 1087 sound/pci/azt3328.c val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift); reg 1089 sound/pci/azt3328.c snd_azf3328_mixer_outw(chip, reg.reg, val); reg 1093 sound/pci/azt3328.c "put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg); reg 2303 sound/pci/azt3328.c snd_azf3328_test_bit(unsigned unsigned reg, int bit) reg 2307 sound/pci/azt3328.c val = inb(reg); reg 2309 sound/pci/azt3328.c outb(val & ~(1 << bit), reg); reg 2310 sound/pci/azt3328.c valoff = inb(reg); reg 2312 sound/pci/azt3328.c outb(val|(1 << bit), reg); reg 2313 sound/pci/azt3328.c valon = inb(reg); reg 2315 sound/pci/azt3328.c outb(val, reg); reg 2318 sound/pci/azt3328.c reg, bit, val, valoff, valon reg 2617 sound/pci/azt3328.c unsigned reg; reg 2619 sound/pci/azt3328.c for (reg = 0; reg < count; ++reg) { reg 2635 sound/pci/azt3328.c unsigned reg; reg 2637 sound/pci/azt3328.c for (reg = 0; reg < count; ++reg) { reg 203 sound/pci/bt87x.c static inline u32 snd_bt87x_readl(struct snd_bt87x *chip, u32 reg) reg 205 sound/pci/bt87x.c return readl(chip->mmio + reg); reg 208 sound/pci/bt87x.c static inline void snd_bt87x_writel(struct snd_bt87x *chip, u32 reg, u32 value) reg 210 sound/pci/bt87x.c writel(value, chip->mmio + reg); reg 708 sound/pci/ca0106/ca0106.h unsigned int reg, reg 712 sound/pci/ca0106/ca0106.h unsigned int reg, reg 716 sound/pci/ca0106/ca0106.h int snd_ca0106_i2c_write(struct snd_ca0106 *emu, u32 reg, u32 value); reg 333 sound/pci/ca0106/ca0106_main.c unsigned int reg, reg 339 sound/pci/ca0106/ca0106_main.c regptr = (reg << 16) | chn; reg 349 sound/pci/ca0106/ca0106_main.c unsigned int reg, reg 356 sound/pci/ca0106/ca0106_main.c regptr = (reg << 16) | chn; reg 368 sound/pci/ca0106/ca0106_main.c unsigned int reg, tmp; reg 370 sound/pci/ca0106/ca0106_main.c reg = SPI; reg 373 sound/pci/ca0106/ca0106_main.c tmp = snd_ca0106_ptr_read(emu, reg, 0); reg 376 sound/pci/ca0106/ca0106_main.c snd_ca0106_ptr_write(emu, reg, 0, reset | data); reg 377 sound/pci/ca0106/ca0106_main.c tmp = snd_ca0106_ptr_read(emu, reg, 0); /* write post */ reg 378 sound/pci/ca0106/ca0106_main.c snd_ca0106_ptr_write(emu, reg, 0, set | data); reg 383 sound/pci/ca0106/ca0106_main.c tmp = snd_ca0106_ptr_read(emu, reg, 0); reg 391 sound/pci/ca0106/ca0106_main.c snd_ca0106_ptr_write(emu, reg, 0, reset | data); reg 392 sound/pci/ca0106/ca0106_main.c tmp = snd_ca0106_ptr_read(emu, reg, 0); /* Write post */ reg 398 sound/pci/ca0106/ca0106_main.c u32 reg, reg 405 sound/pci/ca0106/ca0106_main.c if ((reg > 0x7f) || (value > 0x1ff)) { reg 410 sound/pci/ca0106/ca0106_main.c tmp = reg << 25 | value << 16; reg 531 sound/pci/ca0106/ca0106_main.c const int reg = spi_dacd_reg[dac]; reg 536 sound/pci/ca0106/ca0106_main.c chip->spi_dac_reg[reg] &= ~bit; reg 539 sound/pci/ca0106/ca0106_main.c chip->spi_dac_reg[reg] |= bit; reg 540 sound/pci/ca0106/ca0106_main.c return snd_ca0106_spi_write(chip, chip->spi_dac_reg[reg]); reg 1186 sound/pci/ca0106/ca0106_main.c unsigned short reg) reg 1193 sound/pci/ca0106/ca0106_main.c outb(reg, emu->port + AC97ADDRESS); reg 1200 sound/pci/ca0106/ca0106_main.c unsigned short reg, unsigned short val) reg 1206 sound/pci/ca0106/ca0106_main.c outb(reg, emu->port + AC97ADDRESS); reg 1414 sound/pci/ca0106/ca0106_main.c #define SPI_REG(reg, value) (((reg) << SPI_REG_SHIFT) | (value)) reg 1615 sound/pci/ca0106/ca0106_main.c int reg = spi_dac_init[n] >> SPI_REG_SHIFT; reg 1618 sound/pci/ca0106/ca0106_main.c if (reg < ARRAY_SIZE(chip->spi_dac_reg)) reg 1619 sound/pci/ca0106/ca0106_main.c chip->spi_dac_reg[reg] = spi_dac_init[n]; reg 416 sound/pci/ca0106/ca0106_mixer.c int channel_id, reg; reg 419 sound/pci/ca0106/ca0106_mixer.c reg = kcontrol->private_value & 0xff; reg 421 sound/pci/ca0106/ca0106_mixer.c value = snd_ca0106_ptr_read(emu, reg, channel_id); reg 432 sound/pci/ca0106/ca0106_mixer.c int channel_id, reg; reg 435 sound/pci/ca0106/ca0106_mixer.c reg = kcontrol->private_value & 0xff; reg 437 sound/pci/ca0106/ca0106_mixer.c oval = snd_ca0106_ptr_read(emu, reg, channel_id); reg 444 sound/pci/ca0106/ca0106_mixer.c snd_ca0106_ptr_write(emu, reg, channel_id, nval); reg 511 sound/pci/ca0106/ca0106_mixer.c unsigned int reg = kcontrol->private_value >> SPI_REG_SHIFT; reg 514 sound/pci/ca0106/ca0106_mixer.c ucontrol->value.integer.value[0] = !(emu->spi_dac_reg[reg] & bit); reg 522 sound/pci/ca0106/ca0106_mixer.c unsigned int reg = kcontrol->private_value >> SPI_REG_SHIFT; reg 526 sound/pci/ca0106/ca0106_mixer.c ret = emu->spi_dac_reg[reg] & bit; reg 530 sound/pci/ca0106/ca0106_mixer.c emu->spi_dac_reg[reg] &= ~bit; reg 534 sound/pci/ca0106/ca0106_mixer.c emu->spi_dac_reg[reg] |= bit; reg 537 sound/pci/ca0106/ca0106_mixer.c ret = snd_ca0106_spi_write(emu, emu->spi_dac_reg[reg]); reg 541 sound/pci/ca0106/ca0106_mixer.c #define CA_VOLUME(xname,chid,reg) \ reg 550 sound/pci/ca0106/ca0106_mixer.c .private_value = ((chid) << 8) | (reg) \ reg 661 sound/pci/ca0106/ca0106_mixer.c int reg, bit; reg 692 sound/pci/ca0106/ca0106_mixer.c reg = spi_dmute_reg[dac_id]; reg 695 sound/pci/ca0106/ca0106_mixer.c spi_switch.private_value = (reg << SPI_REG_SHIFT) | bit; reg 875 sound/pci/ca0106/ca0106_mixer.c unsigned int reg; reg 897 sound/pci/ca0106/ca0106_mixer.c snd_ca0106_ptr_read(chip, saved_volumes[i].reg, reg 906 sound/pci/ca0106/ca0106_mixer.c snd_ca0106_ptr_write(chip, saved_volumes[i].reg, reg 286 sound/pci/ca0106/ca0106_proc.c u32 reg, val; reg 288 sound/pci/ca0106/ca0106_proc.c if (sscanf(line, "%x %x", ®, &val) != 2) reg 290 sound/pci/ca0106/ca0106_proc.c if (reg < 0x40 && val <= 0xffffffff) { reg 292 sound/pci/ca0106/ca0106_proc.c outl(val, emu->port + (reg & 0xfffffffc)); reg 387 sound/pci/ca0106/ca0106_proc.c unsigned int reg, channel_id , val; reg 389 sound/pci/ca0106/ca0106_proc.c if (sscanf(line, "%x %x %x", ®, &channel_id, &val) != 3) reg 391 sound/pci/ca0106/ca0106_proc.c if (reg < 0x80 && val <= 0xffffffff && channel_id <= 3) reg 392 sound/pci/ca0106/ca0106_proc.c snd_ca0106_ptr_write(emu, reg, channel_id, val); reg 401 sound/pci/ca0106/ca0106_proc.c unsigned int reg, val; reg 403 sound/pci/ca0106/ca0106_proc.c if (sscanf(line, "%x %x", ®, &val) != 2) reg 405 sound/pci/ca0106/ca0106_proc.c if ((reg <= 0x7f) || (val <= 0x1ff)) { reg 406 sound/pci/ca0106/ca0106_proc.c snd_ca0106_i2c_write(emu, reg, val); reg 653 sound/pci/cmipci.c unsigned int reg = CM_REG_PLL + slot; reg 662 sound/pci/cmipci.c snd_cmipci_write_b(cm, reg, rate>>8); reg 663 sound/pci/cmipci.c snd_cmipci_write_b(cm, reg, rate&0xff); reg 772 sound/pci/cmipci.c unsigned int reg, freq, freq_ext, val; reg 803 sound/pci/cmipci.c reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; reg 804 sound/pci/cmipci.c snd_cmipci_write(cm, reg, rec->offset); reg 806 sound/pci/cmipci.c reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; reg 807 sound/pci/cmipci.c snd_cmipci_write_w(cm, reg, rec->dma_size - 1); reg 808 sound/pci/cmipci.c snd_cmipci_write_w(cm, reg + 2, period_size - 1); reg 931 sound/pci/cmipci.c unsigned int reg, rem, tries; reg 936 sound/pci/cmipci.c reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; reg 938 sound/pci/cmipci.c rem = snd_cmipci_read_w(cm, reg); reg 947 sound/pci/cmipci.c reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; reg 948 sound/pci/cmipci.c ptr = snd_cmipci_read(cm, reg) - rec->offset; reg 1325 sound/pci/cmipci.c unsigned int reg, val; reg 1330 sound/pci/cmipci.c reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; reg 1332 sound/pci/cmipci.c snd_cmipci_write(cm, reg, val); reg 2006 sound/pci/cmipci.c #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1) reg 2007 sound/pci/cmipci.c #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0) reg 2025 sound/pci/cmipci.c struct cmipci_sb_reg reg; reg 2027 sound/pci/cmipci.c cmipci_sb_reg_decode(®, kcontrol->private_value); reg 2028 sound/pci/cmipci.c uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; reg 2029 sound/pci/cmipci.c uinfo->count = reg.stereo + 1; reg 2031 sound/pci/cmipci.c uinfo->value.integer.max = reg.mask; reg 2039 sound/pci/cmipci.c struct cmipci_sb_reg reg; reg 2042 sound/pci/cmipci.c cmipci_sb_reg_decode(®, kcontrol->private_value); reg 2044 sound/pci/cmipci.c val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask; reg 2045 sound/pci/cmipci.c if (reg.invert) reg 2046 sound/pci/cmipci.c val = reg.mask - val; reg 2048 sound/pci/cmipci.c if (reg.stereo) { reg 2049 sound/pci/cmipci.c val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask; reg 2050 sound/pci/cmipci.c if (reg.invert) reg 2051 sound/pci/cmipci.c val = reg.mask - val; reg 2062 sound/pci/cmipci.c struct cmipci_sb_reg reg; reg 2066 sound/pci/cmipci.c cmipci_sb_reg_decode(®, kcontrol->private_value); reg 2067 sound/pci/cmipci.c left = ucontrol->value.integer.value[0] & reg.mask; reg 2068 sound/pci/cmipci.c if (reg.invert) reg 2069 sound/pci/cmipci.c left = reg.mask - left; reg 2070 sound/pci/cmipci.c left <<= reg.left_shift; reg 2071 sound/pci/cmipci.c if (reg.stereo) { reg 2072 sound/pci/cmipci.c right = ucontrol->value.integer.value[1] & reg.mask; reg 2073 sound/pci/cmipci.c if (reg.invert) reg 2074 sound/pci/cmipci.c right = reg.mask - right; reg 2075 sound/pci/cmipci.c right <<= reg.right_shift; reg 2079 sound/pci/cmipci.c oleft = snd_cmipci_mixer_read(cm, reg.left_reg); reg 2080 sound/pci/cmipci.c left |= oleft & ~(reg.mask << reg.left_shift); reg 2082 sound/pci/cmipci.c if (reg.stereo) { reg 2083 sound/pci/cmipci.c if (reg.left_reg != reg.right_reg) { reg 2084 sound/pci/cmipci.c snd_cmipci_mixer_write(cm, reg.left_reg, left); reg 2085 sound/pci/cmipci.c oright = snd_cmipci_mixer_read(cm, reg.right_reg); reg 2088 sound/pci/cmipci.c right |= oright & ~(reg.mask << reg.right_shift); reg 2090 sound/pci/cmipci.c snd_cmipci_mixer_write(cm, reg.right_reg, right); reg 2092 sound/pci/cmipci.c snd_cmipci_mixer_write(cm, reg.left_reg, left); reg 2121 sound/pci/cmipci.c struct cmipci_sb_reg reg; reg 2124 sound/pci/cmipci.c cmipci_sb_reg_decode(®, kcontrol->private_value); reg 2126 sound/pci/cmipci.c val1 = snd_cmipci_mixer_read(cm, reg.left_reg); reg 2127 sound/pci/cmipci.c val2 = snd_cmipci_mixer_read(cm, reg.right_reg); reg 2129 sound/pci/cmipci.c ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1; reg 2130 sound/pci/cmipci.c ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1; reg 2131 sound/pci/cmipci.c ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1; reg 2132 sound/pci/cmipci.c ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1; reg 2140 sound/pci/cmipci.c struct cmipci_sb_reg reg; reg 2144 sound/pci/cmipci.c cmipci_sb_reg_decode(®, kcontrol->private_value); reg 2146 sound/pci/cmipci.c oval1 = snd_cmipci_mixer_read(cm, reg.left_reg); reg 2147 sound/pci/cmipci.c oval2 = snd_cmipci_mixer_read(cm, reg.right_reg); reg 2148 sound/pci/cmipci.c val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); reg 2149 sound/pci/cmipci.c val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); reg 2150 sound/pci/cmipci.c val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift; reg 2151 sound/pci/cmipci.c val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift; reg 2152 sound/pci/cmipci.c val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift; reg 2153 sound/pci/cmipci.c val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift; reg 2155 sound/pci/cmipci.c snd_cmipci_mixer_write(cm, reg.left_reg, val1); reg 2156 sound/pci/cmipci.c snd_cmipci_mixer_write(cm, reg.right_reg, val2); reg 2165 sound/pci/cmipci.c #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \ reg 2169 sound/pci/cmipci.c .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \ reg 2172 sound/pci/cmipci.c #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \ reg 2176 sound/pci/cmipci.c .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \ reg 2179 sound/pci/cmipci.c #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \ reg 2183 sound/pci/cmipci.c .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \ reg 2186 sound/pci/cmipci.c #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \ reg 2190 sound/pci/cmipci.c .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \ reg 2196 sound/pci/cmipci.c struct cmipci_sb_reg reg; reg 2198 sound/pci/cmipci.c cmipci_sb_reg_decode(®, kcontrol->private_value); reg 2199 sound/pci/cmipci.c uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; reg 2200 sound/pci/cmipci.c uinfo->count = reg.stereo + 1; reg 2202 sound/pci/cmipci.c uinfo->value.integer.max = reg.mask; reg 2211 sound/pci/cmipci.c struct cmipci_sb_reg reg; reg 2214 sound/pci/cmipci.c cmipci_sb_reg_decode(®, kcontrol->private_value); reg 2216 sound/pci/cmipci.c oreg = inb(cm->iobase + reg.left_reg); reg 2217 sound/pci/cmipci.c val = (oreg >> reg.left_shift) & reg.mask; reg 2218 sound/pci/cmipci.c if (reg.invert) reg 2219 sound/pci/cmipci.c val = reg.mask - val; reg 2221 sound/pci/cmipci.c if (reg.stereo) { reg 2222 sound/pci/cmipci.c val = (oreg >> reg.right_shift) & reg.mask; reg 2223 sound/pci/cmipci.c if (reg.invert) reg 2224 sound/pci/cmipci.c val = reg.mask - val; reg 2235 sound/pci/cmipci.c struct cmipci_sb_reg reg; reg 2238 sound/pci/cmipci.c cmipci_sb_reg_decode(®, kcontrol->private_value); reg 2240 sound/pci/cmipci.c oreg = inb(cm->iobase + reg.left_reg); reg 2241 sound/pci/cmipci.c val = ucontrol->value.integer.value[0] & reg.mask; reg 2242 sound/pci/cmipci.c if (reg.invert) reg 2243 sound/pci/cmipci.c val = reg.mask - val; reg 2244 sound/pci/cmipci.c nreg = oreg & ~(reg.mask << reg.left_shift); reg 2245 sound/pci/cmipci.c nreg |= (val << reg.left_shift); reg 2246 sound/pci/cmipci.c if (reg.stereo) { reg 2247 sound/pci/cmipci.c val = ucontrol->value.integer.value[1] & reg.mask; reg 2248 sound/pci/cmipci.c if (reg.invert) reg 2249 sound/pci/cmipci.c val = reg.mask - val; reg 2250 sound/pci/cmipci.c nreg &= ~(reg.mask << reg.right_shift); reg 2251 sound/pci/cmipci.c nreg |= (val << reg.right_shift); reg 2253 sound/pci/cmipci.c outb(nreg, cm->iobase + reg.left_reg); reg 2323 sound/pci/cmipci.c int reg; /* register index */ reg 2348 sound/pci/cmipci.c val = inb(cm->iobase + args->reg); reg 2350 sound/pci/cmipci.c val = snd_cmipci_read(cm, args->reg); reg 2381 sound/pci/cmipci.c val = inb(cm->iobase + args->reg); reg 2383 sound/pci/cmipci.c val = snd_cmipci_read(cm, args->reg); reg 2393 sound/pci/cmipci.c outb((unsigned char)val, cm->iobase + args->reg); reg 2395 sound/pci/cmipci.c snd_cmipci_write(cm, args->reg, val); reg 2413 sound/pci/cmipci.c .reg = xreg, \ reg 511 sound/pci/cs4281.c unsigned short reg, unsigned short val) reg 535 sound/pci/cs4281.c snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg); reg 553 sound/pci/cs4281.c "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val); reg 557 sound/pci/cs4281.c unsigned short reg) reg 590 sound/pci/cs4281.c snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg); reg 614 sound/pci/cs4281.c "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg); reg 634 sound/pci/cs4281.c "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg); reg 1651 sound/pci/cs46xx/cs46xx.h struct snd_cs46xx_region reg; reg 75 sound/pci/cs46xx/cs46xx_lib.c unsigned short reg, reg 125 sound/pci/cs46xx/cs46xx_lib.c snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg); reg 157 sound/pci/cs46xx/cs46xx_lib.c "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg); reg 178 sound/pci/cs46xx/cs46xx_lib.c codec_index, reg); reg 189 sound/pci/cs46xx/cs46xx_lib.c "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg, reg 202 sound/pci/cs46xx/cs46xx_lib.c unsigned short reg) reg 212 sound/pci/cs46xx/cs46xx_lib.c val = snd_cs46xx_codec_read(chip, reg, codec_index); reg 219 sound/pci/cs46xx/cs46xx_lib.c unsigned short reg, reg 251 sound/pci/cs46xx/cs46xx_lib.c snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg); reg 280 sound/pci/cs46xx/cs46xx_lib.c codec_index, reg, val); reg 286 sound/pci/cs46xx/cs46xx_lib.c unsigned short reg, reg 296 sound/pci/cs46xx/cs46xx_lib.c snd_cs46xx_codec_write(chip, reg, val, codec_index); reg 1903 sound/pci/cs46xx/cs46xx_lib.c int reg = kcontrol->private_value; reg 1904 sound/pci/cs46xx/cs46xx_lib.c unsigned int val = snd_cs46xx_peek(chip, reg); reg 1913 sound/pci/cs46xx/cs46xx_lib.c int reg = kcontrol->private_value; reg 1916 sound/pci/cs46xx/cs46xx_lib.c unsigned int old = snd_cs46xx_peek(chip, reg); reg 1920 sound/pci/cs46xx/cs46xx_lib.c snd_cs46xx_poke(chip, reg, val); reg 1987 sound/pci/cs46xx/cs46xx_lib.c int reg = kcontrol->private_value; reg 1989 sound/pci/cs46xx/cs46xx_lib.c if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT) reg 3926 sound/pci/cs46xx/cs46xx_lib.c region = &chip->region.name.reg; reg 45 sound/pci/cs46xx/cs46xx_lib.h static inline void snd_cs46xx_poke(struct snd_cs46xx *chip, unsigned long reg, unsigned int val) reg 47 sound/pci/cs46xx/cs46xx_lib.h unsigned int bank = reg >> 16; reg 48 sound/pci/cs46xx/cs46xx_lib.h unsigned int offset = reg & 0xffff; reg 58 sound/pci/cs46xx/cs46xx_lib.h static inline unsigned int snd_cs46xx_peek(struct snd_cs46xx *chip, unsigned long reg) reg 60 sound/pci/cs46xx/cs46xx_lib.h unsigned int bank = reg >> 16; reg 61 sound/pci/cs46xx/cs46xx_lib.h unsigned int offset = reg & 0xffff; reg 87 sound/pci/cs5530.c static u8 snd_cs5530_mixer_read(unsigned long io, u8 reg) reg 89 sound/pci/cs5530.c outb(reg, io + 4); reg 91 sound/pci/cs5530.c reg = inb(io + 5); reg 93 sound/pci/cs5530.c return reg; reg 78 sound/pci/cs5535audio/cs5535audio.c unsigned short reg) reg 84 sound/pci/cs5535audio/cs5535audio.c regdata = ((unsigned int) reg) << 24; reg 94 sound/pci/cs5535audio/cs5535audio.c if ((val & STS_NEW) && reg == (val >> 24)) reg 101 sound/pci/cs5535audio/cs5535audio.c reg, val); reg 107 sound/pci/cs5535audio/cs5535audio.c unsigned short reg, unsigned short val) reg 111 sound/pci/cs5535audio/cs5535audio.c regdata = ((unsigned int) reg) << 24; reg 122 sound/pci/cs5535audio/cs5535audio.c unsigned short reg, unsigned short val) reg 125 sound/pci/cs5535audio/cs5535audio.c snd_cs5535audio_codec_write(cs5535au, reg, val); reg 129 sound/pci/cs5535audio/cs5535audio.c unsigned short reg) reg 132 sound/pci/cs5535audio/cs5535audio.c return snd_cs5535audio_codec_read(cs5535au, reg); reg 5 sound/pci/cs5535audio/cs5535audio.h #define cs_writel(cs5535au, reg, val) outl(val, (cs5535au)->port + reg) reg 6 sound/pci/cs5535audio/cs5535audio.h #define cs_writeb(cs5535au, reg, val) outb(val, (cs5535au)->port + reg) reg 7 sound/pci/cs5535audio/cs5535audio.h #define cs_readl(cs5535au, reg) inl((cs5535au)->port + reg) reg 8 sound/pci/cs5535audio/cs5535audio.h #define cs_readw(cs5535au, reg) inw((cs5535au)->port + reg) reg 9 sound/pci/cs5535audio/cs5535audio.h #define cs_readb(cs5535au, reg) inb((cs5535au)->port + reg) reg 32 sound/pci/ctxfi/cthw20k1.c static u32 hw_read_20kx(struct hw *hw, u32 reg); reg 33 sound/pci/ctxfi/cthw20k1.c static void hw_write_20kx(struct hw *hw, u32 reg, u32 data); reg 34 sound/pci/ctxfi/cthw20k1.c static u32 hw_read_pci(struct hw *hw, u32 reg); reg 35 sound/pci/ctxfi/cthw20k1.c static void hw_write_pci(struct hw *hw, u32 reg, u32 data); reg 2098 sound/pci/ctxfi/cthw20k1.c static u32 hw_read_20kx(struct hw *hw, u32 reg) reg 2105 sound/pci/ctxfi/cthw20k1.c outl(reg, hw->io_base + 0x0); reg 2113 sound/pci/ctxfi/cthw20k1.c static void hw_write_20kx(struct hw *hw, u32 reg, u32 data) reg 2119 sound/pci/ctxfi/cthw20k1.c outl(reg, hw->io_base + 0x0); reg 2126 sound/pci/ctxfi/cthw20k1.c static u32 hw_read_pci(struct hw *hw, u32 reg) reg 2133 sound/pci/ctxfi/cthw20k1.c outl(reg, hw->io_base + 0x10); reg 2141 sound/pci/ctxfi/cthw20k1.c static void hw_write_pci(struct hw *hw, u32 reg, u32 data) reg 2147 sound/pci/ctxfi/cthw20k1.c outl(reg, hw->io_base + 0x10); reg 35 sound/pci/ctxfi/cthw20k2.c static u32 hw_read_20kx(struct hw *hw, u32 reg); reg 36 sound/pci/ctxfi/cthw20k2.c static void hw_write_20kx(struct hw *hw, u32 reg, u32 data); reg 2209 sound/pci/ctxfi/cthw20k2.c static u32 hw_read_20kx(struct hw *hw, u32 reg) reg 2211 sound/pci/ctxfi/cthw20k2.c return readl(hw->mem_base + reg); reg 2214 sound/pci/ctxfi/cthw20k2.c static void hw_write_20kx(struct hw *hw, u32 reg, u32 data) reg 2216 sound/pci/ctxfi/cthw20k2.c writel(data, hw->mem_base + reg); reg 122 sound/pci/emu10k1/emu10k1_callback.c dcysusv = 0x8000 | (unsigned char)vp->reg.parm.modrelease; reg 124 sound/pci/emu10k1/emu10k1_callback.c dcysusv = 0x8000 | (unsigned char)vp->reg.parm.volrelease | DCYSUSV_CHANNELENABLE_MASK; reg 195 sound/pci/emu10k1/emu10k1_callback.c snd_emu10k1_ptr_write(hw, TREMFRQ, vp->ch, vp->reg.parm.tremfrq); reg 255 sound/pci/emu10k1/emu10k1_callback.c (vp->reg.sample_mode & SNDRV_SFNT_SAMPLE_SINGLESHOT)) { reg 257 sound/pci/emu10k1/emu10k1_callback.c if (val >= vp->reg.loopstart) reg 331 sound/pci/emu10k1/emu10k1_callback.c vp->reg.start += mapped_offset; reg 332 sound/pci/emu10k1/emu10k1_callback.c vp->reg.end += mapped_offset; reg 333 sound/pci/emu10k1/emu10k1_callback.c vp->reg.loopstart += mapped_offset; reg 334 sound/pci/emu10k1/emu10k1_callback.c vp->reg.loopend += mapped_offset; reg 359 sound/pci/emu10k1/emu10k1_callback.c snd_emu10k1_ptr_write(hw, ENVVAL, ch, vp->reg.parm.moddelay); reg 360 sound/pci/emu10k1/emu10k1_callback.c snd_emu10k1_ptr_write(hw, ATKHLDM, ch, vp->reg.parm.modatkhld); reg 361 sound/pci/emu10k1/emu10k1_callback.c snd_emu10k1_ptr_write(hw, DCYSUSM, ch, vp->reg.parm.moddcysus); reg 362 sound/pci/emu10k1/emu10k1_callback.c snd_emu10k1_ptr_write(hw, ENVVOL, ch, vp->reg.parm.voldelay); reg 363 sound/pci/emu10k1/emu10k1_callback.c snd_emu10k1_ptr_write(hw, ATKHLDV, ch, vp->reg.parm.volatkhld); reg 372 sound/pci/emu10k1/emu10k1_callback.c snd_emu10k1_ptr_write(hw, PEFE, ch, vp->reg.parm.pefe); reg 375 sound/pci/emu10k1/emu10k1_callback.c snd_emu10k1_ptr_write(hw, LFOVAL1, ch, vp->reg.parm.lfo1delay); reg 376 sound/pci/emu10k1/emu10k1_callback.c snd_emu10k1_ptr_write(hw, LFOVAL2, ch, vp->reg.parm.lfo2delay); reg 381 sound/pci/emu10k1/emu10k1_callback.c snd_emu10k1_ptr_write(hw, TREMFRQ, vp->ch, vp->reg.parm.tremfrq); reg 386 sound/pci/emu10k1/emu10k1_callback.c temp = vp->reg.parm.reverb; reg 389 sound/pci/emu10k1/emu10k1_callback.c addr = vp->reg.loopstart; reg 393 sound/pci/emu10k1/emu10k1_callback.c addr = vp->reg.loopend; reg 394 sound/pci/emu10k1/emu10k1_callback.c temp = vp->reg.parm.chorus; reg 413 sound/pci/emu10k1/emu10k1_callback.c if (vp->reg.sample_mode & SNDRV_SFNT_SAMPLE_8BITS) reg 439 sound/pci/emu10k1/emu10k1_callback.c addr = vp->reg.start; reg 440 sound/pci/emu10k1/emu10k1_callback.c temp = vp->reg.parm.filterQ; reg 448 sound/pci/emu10k1/emu10k1_callback.c if (vp->reg.sample_mode & SNDRV_SFNT_SAMPLE_8BITS) reg 488 sound/pci/emu10k1/emu10k1_callback.c snd_emu10k1_ptr_write(hw, DCYSUSV, vp->ch, vp->reg.parm.voldcysus|DCYSUSV_CHANNELENABLE_MASK); reg 502 sound/pci/emu10k1/emu10k1_callback.c pitch = (char)(vp->reg.parm.fmmod>>8); reg 503 sound/pci/emu10k1/emu10k1_callback.c cutoff = (vp->reg.parm.fmmod & 0xff); reg 520 sound/pci/emu10k1/emu10k1_callback.c pitch = (char)(vp->reg.parm.fm2frq2>>8); reg 521 sound/pci/emu10k1/emu10k1_callback.c freq = vp->reg.parm.fm2frq2 & 0xff; reg 535 sound/pci/emu10k1/emu10k1_callback.c val |= (vp->reg.parm.filterQ << 28); reg 311 sound/pci/emu10k1/emu10k1_main.c unsigned int reg = inl(emu->port + A_IOCFG); reg 312 sound/pci/emu10k1/emu10k1_main.c outl(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG); reg 314 sound/pci/emu10k1/emu10k1_main.c outl(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG); reg 316 sound/pci/emu10k1/emu10k1_main.c outl(reg, emu->port + A_IOCFG); reg 318 sound/pci/emu10k1/emu10k1_main.c unsigned int reg = inl(emu->port + HCFG); reg 319 sound/pci/emu10k1/emu10k1_main.c outl(reg | HCFG_GPOUT2, emu->port + HCFG); reg 321 sound/pci/emu10k1/emu10k1_main.c outl(reg | HCFG_GPOUT1 | HCFG_GPOUT2, emu->port + HCFG); reg 323 sound/pci/emu10k1/emu10k1_main.c outl(reg, emu->port + HCFG); reg 332 sound/pci/emu10k1/emu10k1_main.c unsigned int reg = inl(emu->port + A_IOCFG); reg 333 sound/pci/emu10k1/emu10k1_main.c outl(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG); reg 654 sound/pci/emu10k1/emu10k1_main.c int reg; reg 678 sound/pci/emu10k1/emu10k1_main.c reg = 0x80; reg 680 sound/pci/emu10k1/emu10k1_main.c reg = reg | 0x20; reg 682 sound/pci/emu10k1/emu10k1_main.c outl(reg, emu->port + A_IOCFG); reg 684 sound/pci/emu10k1/emu10k1_main.c outl(reg | 0x40, emu->port + A_IOCFG); reg 733 sound/pci/emu10k1/emu10k1_main.c u32 tmp, tmp2, reg; reg 745 sound/pci/emu10k1/emu10k1_main.c snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®); /* OPTIONS: Which cards are attached to the EMU */ reg 746 sound/pci/emu10k1/emu10k1_main.c if (reg & EMU_HANA_OPTION_DOCK_OFFLINE) { reg 782 sound/pci/emu10k1/emu10k1_main.c } else if (!reg && emu->emu1010.last_reg) { reg 790 sound/pci/emu10k1/emu10k1_main.c emu->emu1010.last_reg = reg; reg 830 sound/pci/emu10k1/emu10k1_main.c u32 tmp, tmp2, reg; reg 857 sound/pci/emu10k1/emu10k1_main.c snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®); reg 858 sound/pci/emu10k1/emu10k1_main.c dev_dbg(emu->card->dev, "reg1 = 0x%x\n", reg); reg 859 sound/pci/emu10k1/emu10k1_main.c if ((reg & 0x3f) == 0x15) { reg 865 sound/pci/emu10k1/emu10k1_main.c snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®); reg 866 sound/pci/emu10k1/emu10k1_main.c dev_dbg(emu->card->dev, "reg2 = 0x%x\n", reg); reg 867 sound/pci/emu10k1/emu10k1_main.c if ((reg & 0x3f) == 0x15) { reg 873 sound/pci/emu10k1/emu10k1_main.c dev_info(emu->card->dev, "emu1010: EMU_HANA_ID = 0x%x\n", reg); reg 882 sound/pci/emu10k1/emu10k1_main.c snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®); reg 883 sound/pci/emu10k1/emu10k1_main.c if ((reg & 0x3f) != 0x15) { reg 887 sound/pci/emu10k1/emu10k1_main.c reg); reg 898 sound/pci/emu10k1/emu10k1_main.c snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®); reg 899 sound/pci/emu10k1/emu10k1_main.c dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg); reg 900 sound/pci/emu10k1/emu10k1_main.c snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®); reg 901 sound/pci/emu10k1/emu10k1_main.c dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg); reg 939 sound/pci/emu10k1/emu10k1_main.c snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®); reg 940 sound/pci/emu10k1/emu10k1_main.c dev_info(emu->card->dev, "emu1010: Card options3 = 0x%x\n", reg); reg 2096 sound/pci/emu10k1/emu10k1_main.c unsigned char *reg; reg 2100 sound/pci/emu10k1/emu10k1_main.c for (reg = saved_regs; *reg != 0xff; reg++) reg 2102 sound/pci/emu10k1/emu10k1_main.c *val = snd_emu10k1_ptr_read(emu, *reg, i); reg 2104 sound/pci/emu10k1/emu10k1_main.c for (reg = saved_regs_audigy; *reg != 0xff; reg++) reg 2106 sound/pci/emu10k1/emu10k1_main.c *val = snd_emu10k1_ptr_read(emu, *reg, i); reg 2129 sound/pci/emu10k1/emu10k1_main.c unsigned char *reg; reg 2140 sound/pci/emu10k1/emu10k1_main.c for (reg = saved_regs; *reg != 0xff; reg++) reg 2142 sound/pci/emu10k1/emu10k1_main.c snd_emu10k1_ptr_write(emu, *reg, i, *val); reg 2144 sound/pci/emu10k1/emu10k1_main.c for (reg = saved_regs_audigy; *reg != 0xff; reg++) reg 2146 sound/pci/emu10k1/emu10k1_main.c snd_emu10k1_ptr_write(emu, *reg, i, *val); reg 282 sound/pci/emu10k1/emu10k1x.c unsigned int reg, reg 288 sound/pci/emu10k1/emu10k1x.c regptr = (reg << 16) | chn; reg 298 sound/pci/emu10k1/emu10k1x.c unsigned int reg, reg 305 sound/pci/emu10k1/emu10k1x.c regptr = (reg << 16) | chn; reg 695 sound/pci/emu10k1/emu10k1x.c unsigned short reg) reg 702 sound/pci/emu10k1/emu10k1x.c outb(reg, emu->port + AC97ADDRESS); reg 709 sound/pci/emu10k1/emu10k1x.c unsigned short reg, unsigned short val) reg 715 sound/pci/emu10k1/emu10k1x.c outb(reg, emu->port + AC97ADDRESS); reg 1041 sound/pci/emu10k1/emu10k1x.c unsigned int reg, channel_id , val; reg 1044 sound/pci/emu10k1/emu10k1x.c if (sscanf(line, "%x %x %x", ®, &channel_id, &val) != 3) reg 1047 sound/pci/emu10k1/emu10k1x.c if (reg < 0x49 && val <= 0xffffffff && channel_id <= 2) reg 1048 sound/pci/emu10k1/emu10k1x.c snd_emu10k1x_ptr_write(emu, reg, channel_id, val); reg 1099 sound/pci/emu10k1/emumixer.c unsigned int reg, val, tmp; reg 1119 sound/pci/emu10k1/emumixer.c reg = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0); reg 1120 sound/pci/emu10k1/emumixer.c tmp = reg & ~A_SPDIF_RATE_MASK; reg 1122 sound/pci/emu10k1/emumixer.c if ((change = (tmp != reg))) reg 1649 sound/pci/emu10k1/emumixer.c unsigned int reg, val, sw; reg 1659 sound/pci/emu10k1/emumixer.c reg = inl(emu->port + A_IOCFG); reg 1661 sound/pci/emu10k1/emumixer.c change = (reg & A_IOCFG_GPOUT0) != val; reg 1663 sound/pci/emu10k1/emumixer.c reg &= ~A_IOCFG_GPOUT0; reg 1664 sound/pci/emu10k1/emumixer.c reg |= val; reg 1665 sound/pci/emu10k1/emumixer.c outl(reg | val, emu->port + A_IOCFG); reg 1668 sound/pci/emu10k1/emumixer.c reg = inl(emu->port + HCFG); reg 1670 sound/pci/emu10k1/emumixer.c change |= (reg & HCFG_GPOUT0) != val; reg 1672 sound/pci/emu10k1/emumixer.c reg &= ~HCFG_GPOUT0; reg 1673 sound/pci/emu10k1/emumixer.c reg |= val; reg 1674 sound/pci/emu10k1/emumixer.c outl(reg | val, emu->port + HCFG); reg 419 sound/pci/emu10k1/emuproc.c u32 reg, val; reg 421 sound/pci/emu10k1/emuproc.c if (sscanf(line, "%x %x", ®, &val) != 2) reg 423 sound/pci/emu10k1/emuproc.c if (reg < 0x40 && val <= 0xffffffff) { reg 425 sound/pci/emu10k1/emuproc.c outl(val, emu->port + (reg & 0xfffffffc)); reg 433 sound/pci/emu10k1/emuproc.c unsigned int reg, reg 439 sound/pci/emu10k1/emuproc.c regptr = (reg << 16) | chn; reg 450 sound/pci/emu10k1/emuproc.c unsigned int reg, reg 457 sound/pci/emu10k1/emuproc.c regptr = (reg << 16) | chn; reg 495 sound/pci/emu10k1/emuproc.c unsigned int reg, channel_id , val; reg 497 sound/pci/emu10k1/emuproc.c if (sscanf(line, "%x %x %x", ®, &channel_id, &val) != 3) reg 499 sound/pci/emu10k1/emuproc.c if (reg < 0xa0 && val <= 0xffffffff && channel_id <= 3) reg 500 sound/pci/emu10k1/emuproc.c snd_ptr_write(emu, iobase, reg, channel_id, val); reg 21 sound/pci/emu10k1/io.c unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn) reg 28 sound/pci/emu10k1/io.c regptr = ((reg << 16) & mask) | (chn & PTR_CHANNELNUM_MASK); reg 30 sound/pci/emu10k1/io.c if (reg & 0xff000000) { reg 33 sound/pci/emu10k1/io.c size = (reg >> 24) & 0x3f; reg 34 sound/pci/emu10k1/io.c offset = (reg >> 16) & 0x1f; reg 54 sound/pci/emu10k1/io.c void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data) reg 63 sound/pci/emu10k1/io.c regptr = ((reg << 16) & mask) | (chn & PTR_CHANNELNUM_MASK); reg 65 sound/pci/emu10k1/io.c if (reg & 0xff000000) { reg 68 sound/pci/emu10k1/io.c size = (reg >> 24) & 0x3f; reg 69 sound/pci/emu10k1/io.c offset = (reg >> 16) & 0x1f; reg 89 sound/pci/emu10k1/io.c unsigned int reg, reg 95 sound/pci/emu10k1/io.c regptr = (reg << 16) | chn; reg 105 sound/pci/emu10k1/io.c unsigned int reg, reg 112 sound/pci/emu10k1/io.c regptr = (reg << 16) | chn; reg 124 sound/pci/emu10k1/io.c unsigned int reg, tmp; reg 131 sound/pci/emu10k1/io.c reg = 0x3c; /* PTR20, reg 0x3c */ reg 144 sound/pci/emu10k1/io.c tmp = snd_emu10k1_ptr20_read(emu, reg, 0); reg 147 sound/pci/emu10k1/io.c snd_emu10k1_ptr20_write(emu, reg, 0, reset | data); reg 148 sound/pci/emu10k1/io.c tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* write post */ reg 149 sound/pci/emu10k1/io.c snd_emu10k1_ptr20_write(emu, reg, 0, set | data); reg 154 sound/pci/emu10k1/io.c tmp = snd_emu10k1_ptr20_read(emu, reg, 0); reg 165 sound/pci/emu10k1/io.c snd_emu10k1_ptr20_write(emu, reg, 0, reset | data); reg 166 sound/pci/emu10k1/io.c tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* Write post */ reg 175 sound/pci/emu10k1/io.c u32 reg, reg 184 sound/pci/emu10k1/io.c if ((reg > 0x7f) || (value > 0x1ff)) { reg 192 sound/pci/emu10k1/io.c tmp = reg << 25 | value << 16; reg 227 sound/pci/emu10k1/io.c status, reg, value); reg 236 sound/pci/emu10k1/io.c int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, u32 reg, u32 value) reg 240 sound/pci/emu10k1/io.c if (reg > 0x3f) reg 242 sound/pci/emu10k1/io.c reg += 0x40; /* 0x40 upwards are registers. */ reg 246 sound/pci/emu10k1/io.c outl(reg, emu->port + A_IOCFG); reg 248 sound/pci/emu10k1/io.c outl(reg | 0x80, emu->port + A_IOCFG); /* High bit clocks the value into the fpga. */ reg 258 sound/pci/emu10k1/io.c int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, u32 reg, u32 *value) reg 261 sound/pci/emu10k1/io.c if (reg > 0x3f) reg 263 sound/pci/emu10k1/io.c reg += 0x40; /* 0x40 upwards are registers. */ reg 265 sound/pci/emu10k1/io.c outl(reg, emu->port + A_IOCFG); reg 267 sound/pci/emu10k1/io.c outl(reg | 0x80, emu->port + A_IOCFG); /* High bit clocks the value into the fpga. */ reg 483 sound/pci/emu10k1/io.c unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg) reg 490 sound/pci/emu10k1/io.c outb(reg, emu->port + AC97ADDRESS); reg 496 sound/pci/emu10k1/io.c void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data) reg 502 sound/pci/emu10k1/io.c outb(reg, emu->port + AC97ADDRESS); reg 685 sound/pci/emu10k1/p16v.c int reg = kcontrol->private_value & 0xff; reg 688 sound/pci/emu10k1/p16v.c value = snd_emu10k1_ptr20_read(emu, reg, high_low); reg 704 sound/pci/emu10k1/p16v.c int reg = kcontrol->private_value & 0xff; reg 707 sound/pci/emu10k1/p16v.c oval = value = snd_emu10k1_ptr20_read(emu, reg, 0); reg 718 sound/pci/emu10k1/p16v.c snd_emu10k1_ptr20_write(emu, reg, 0, value); reg 519 sound/pci/ens1370.c static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg) reg 529 sound/pci/ens1370.c r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000; reg 547 sound/pci/ens1370.c r |= ES_1371_SRC_RAM_ADDRO(reg); reg 554 sound/pci/ens1370.c unsigned short reg, unsigned short data) reg 561 sound/pci/ens1370.c r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data); reg 570 sound/pci/ens1370.c unsigned short reg, unsigned short val) reg 578 sound/pci/ens1370.c reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC)); reg 582 sound/pci/ens1370.c outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC)); reg 601 sound/pci/ens1370.c unsigned short reg, unsigned short val) reg 628 sound/pci/ens1370.c outl(ES_1371_CODEC_WRITE(reg, val) | flag, reg 643 sound/pci/ens1370.c unsigned short reg) reg 671 sound/pci/ens1370.c outl(ES_1371_CODEC_READS(reg) | flag, reg 697 sound/pci/ens1370.c ES_REG(ensoniq, 1371_CODEC), reg, reg 244 sound/pci/es1938.c static void snd_es1938_mixer_write(struct es1938 *chip, unsigned char reg, unsigned char val) reg 248 sound/pci/es1938.c outb(reg, SLSB_REG(chip, MIXERADDR)); reg 251 sound/pci/es1938.c dev_dbg(chip->card->dev, "Mixer reg %02x set to %02x\n", reg, val); reg 257 sound/pci/es1938.c static int snd_es1938_mixer_read(struct es1938 *chip, unsigned char reg) reg 262 sound/pci/es1938.c outb(reg, SLSB_REG(chip, MIXERADDR)); reg 265 sound/pci/es1938.c dev_dbg(chip->card->dev, "Mixer reg %02x now is %02x\n", reg, data); reg 272 sound/pci/es1938.c static int snd_es1938_mixer_bits(struct es1938 *chip, unsigned char reg, reg 278 sound/pci/es1938.c outb(reg, SLSB_REG(chip, MIXERADDR)); reg 286 sound/pci/es1938.c reg, old, new); reg 326 sound/pci/es1938.c static void snd_es1938_write(struct es1938 *chip, unsigned char reg, unsigned char val) reg 330 sound/pci/es1938.c snd_es1938_write_cmd(chip, reg); reg 333 sound/pci/es1938.c dev_dbg(chip->card->dev, "Reg %02x set to %02x\n", reg, val); reg 339 sound/pci/es1938.c static unsigned char snd_es1938_read(struct es1938 *chip, unsigned char reg) reg 345 sound/pci/es1938.c snd_es1938_write_cmd(chip, reg); reg 348 sound/pci/es1938.c dev_dbg(chip->card->dev, "Reg %02x now is %02x\n", reg, val); reg 355 sound/pci/es1938.c static int snd_es1938_bits(struct es1938 *chip, unsigned char reg, unsigned char mask, reg 362 sound/pci/es1938.c snd_es1938_write_cmd(chip, reg); reg 366 sound/pci/es1938.c snd_es1938_write_cmd(chip, reg); reg 370 sound/pci/es1938.c reg, old, new); reg 1142 sound/pci/es1938.c static int snd_es1938_reg_bits(struct es1938 *chip, unsigned char reg, reg 1145 sound/pci/es1938.c if (reg < 0xa0) reg 1146 sound/pci/es1938.c return snd_es1938_mixer_bits(chip, reg, mask, val); reg 1148 sound/pci/es1938.c return snd_es1938_bits(chip, reg, mask, val); reg 1151 sound/pci/es1938.c static int snd_es1938_reg_read(struct es1938 *chip, unsigned char reg) reg 1153 sound/pci/es1938.c if (reg < 0xa0) reg 1154 sound/pci/es1938.c return snd_es1938_mixer_read(chip, reg); reg 1156 sound/pci/es1938.c return snd_es1938_read(chip, reg); reg 1159 sound/pci/es1938.c #define ES1938_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \ reg 1165 sound/pci/es1938.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \ reg 1167 sound/pci/es1938.c #define ES1938_SINGLE(xname, xindex, reg, shift, mask, invert) \ reg 1171 sound/pci/es1938.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } reg 1189 sound/pci/es1938.c int reg = kcontrol->private_value & 0xff; reg 1195 sound/pci/es1938.c val = snd_es1938_reg_read(chip, reg); reg 1206 sound/pci/es1938.c int reg = kcontrol->private_value & 0xff; reg 1217 sound/pci/es1938.c return snd_es1938_reg_bits(chip, reg, mask, val) != val; reg 576 sound/pci/es1968.c static void __maestro_write(struct es1968 *chip, u16 reg, u16 data) reg 578 sound/pci/es1968.c outw(reg, chip->io_port + ESM_INDEX); reg 580 sound/pci/es1968.c chip->maestro_map[reg] = data; reg 583 sound/pci/es1968.c static inline void maestro_write(struct es1968 *chip, u16 reg, u16 data) reg 587 sound/pci/es1968.c __maestro_write(chip, reg, data); reg 592 sound/pci/es1968.c static u16 __maestro_read(struct es1968 *chip, u16 reg) reg 594 sound/pci/es1968.c if (READABLE_MAP & (1 << reg)) { reg 595 sound/pci/es1968.c outw(reg, chip->io_port + ESM_INDEX); reg 596 sound/pci/es1968.c chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA); reg 598 sound/pci/es1968.c return chip->maestro_map[reg]; reg 601 sound/pci/es1968.c static inline u16 maestro_read(struct es1968 *chip, u16 reg) reg 606 sound/pci/es1968.c result = __maestro_read(chip, reg); reg 637 sound/pci/es1968.c static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) reg 646 sound/pci/es1968.c outb(reg, chip->io_port + ESM_AC97_INDEX); reg 650 sound/pci/es1968.c static unsigned short snd_es1968_ac97_read(struct snd_ac97 *ac97, unsigned short reg) reg 657 sound/pci/es1968.c outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX); reg 692 sound/pci/es1968.c static void __apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data) reg 697 sound/pci/es1968.c chip->apu_map[channel][reg] = data; reg 699 sound/pci/es1968.c reg |= (channel << 4); reg 700 sound/pci/es1968.c apu_index_set(chip, reg); reg 704 sound/pci/es1968.c static void apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data) reg 708 sound/pci/es1968.c __apu_set_register(chip, channel, reg, data); reg 712 sound/pci/es1968.c static u16 __apu_get_register(struct es1968 *chip, u16 channel, u8 reg) reg 716 sound/pci/es1968.c reg |= (channel << 4); reg 717 sound/pci/es1968.c apu_index_set(chip, reg); reg 721 sound/pci/es1968.c static u16 apu_get_register(struct es1968 *chip, u16 channel, u8 reg) reg 726 sound/pci/es1968.c v = __apu_get_register(chip, channel, reg); reg 733 sound/pci/es1968.c static void assp_set_register(struct es1968 *chip, u32 reg, u32 value) reg 738 sound/pci/es1968.c outl(reg, chip->io_port + ASSP_INDEX); reg 743 sound/pci/es1968.c static u32 assp_get_register(struct es1968 *chip, u32 reg) reg 749 sound/pci/es1968.c outl(reg, chip->io_port + ASSP_INDEX); reg 758 sound/pci/es1968.c static void wave_set_register(struct es1968 *chip, u16 reg, u16 value) reg 763 sound/pci/es1968.c outw(reg, chip->io_port + WC_INDEX); reg 768 sound/pci/es1968.c static u16 wave_get_register(struct es1968 *chip, u16 reg) reg 774 sound/pci/es1968.c outw(reg, chip->io_port + WC_INDEX); reg 787 sound/pci/es1968.c u16 reg; reg 789 sound/pci/es1968.c reg = __maestro_read(chip, 0x11); reg 790 sound/pci/es1968.c reg &= ~ESM_BOB_ENABLE; reg 791 sound/pci/es1968.c __maestro_write(chip, 0x11, reg); reg 792 sound/pci/es1968.c reg = __maestro_read(chip, 0x17); reg 793 sound/pci/es1968.c reg &= ~ESM_BOB_START; reg 794 sound/pci/es1968.c __maestro_write(chip, 0x17, reg); reg 66 sound/pci/fm801.c #define fm801_writew(chip,reg,value) outw((value), chip->port + FM801_##reg) reg 67 sound/pci/fm801.c #define fm801_readw(chip,reg) inw(chip->port + FM801_##reg) reg 69 sound/pci/fm801.c #define fm801_writel(chip,reg,value) outl((value), chip->port + FM801_##reg) reg 255 sound/pci/fm801.c static int snd_fm801_update_bits(struct fm801 *chip, unsigned short reg, reg 263 sound/pci/fm801.c old = fm801_ioread16(chip, reg); reg 267 sound/pci/fm801.c fm801_iowrite16(chip, reg, new); reg 273 sound/pci/fm801.c unsigned short reg, reg 288 sound/pci/fm801.c fm801_writew(chip, AC97_CMD, reg | (ac97->addr << FM801_AC97_ADDR_SHIFT)); reg 297 sound/pci/fm801.c static unsigned short snd_fm801_codec_read(struct snd_ac97 *ac97, unsigned short reg) reg 311 sound/pci/fm801.c reg | (ac97->addr << FM801_AC97_ADDR_SHIFT) | FM801_AC97_READ); reg 757 sound/pci/fm801.c unsigned short reg = fm801_readw(chip, GPIO_CTRL); reg 760 sound/pci/fm801.c reg &= ~(FM801_GPIO_GP(gpio.data) | reg 764 sound/pci/fm801.c reg |= (pins & TEA575X_DATA) ? FM801_GPIO_GP(gpio.data) : 0; reg 765 sound/pci/fm801.c reg |= (pins & TEA575X_CLK) ? FM801_GPIO_GP(gpio.clk) : 0; reg 767 sound/pci/fm801.c reg |= (pins & TEA575X_WREN) ? 0 : FM801_GPIO_GP(gpio.wren); reg 769 sound/pci/fm801.c fm801_writew(chip, GPIO_CTRL, reg); reg 775 sound/pci/fm801.c unsigned short reg = fm801_readw(chip, GPIO_CTRL); reg 780 sound/pci/fm801.c if (reg & FM801_GPIO_GP(gpio.data)) reg 782 sound/pci/fm801.c if (reg & FM801_GPIO_GP(gpio.most)) reg 790 sound/pci/fm801.c unsigned short reg = fm801_readw(chip, GPIO_CTRL); reg 794 sound/pci/fm801.c reg |= FM801_GPIO_GS(gpio.data) | reg 801 sound/pci/fm801.c reg &= ~(FM801_GPIO_GD(gpio.data) | reg 809 sound/pci/fm801.c reg |= FM801_GPIO_GD(gpio.data) | reg 816 sound/pci/fm801.c reg &= ~(FM801_GPIO_GD(gpio.wren) | reg 821 sound/pci/fm801.c fm801_writew(chip, GPIO_CTRL, reg); reg 835 sound/pci/fm801.c #define FM801_SINGLE(xname, reg, shift, mask, invert) \ reg 838 sound/pci/fm801.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } reg 856 sound/pci/fm801.c int reg = kcontrol->private_value & 0xff; reg 862 sound/pci/fm801.c value[0] = (fm801_ioread16(chip, reg) >> shift) & mask; reg 872 sound/pci/fm801.c int reg = kcontrol->private_value & 0xff; reg 881 sound/pci/fm801.c return snd_fm801_update_bits(chip, reg, mask << shift, val << shift); reg 884 sound/pci/fm801.c #define FM801_DOUBLE(xname, reg, shift_left, shift_right, mask, invert) \ reg 887 sound/pci/fm801.c .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24) } reg 888 sound/pci/fm801.c #define FM801_DOUBLE_TLV(xname, reg, shift_left, shift_right, mask, invert, xtlv) \ reg 893 sound/pci/fm801.c .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24), \ reg 912 sound/pci/fm801.c int reg = kcontrol->private_value & 0xff; reg 920 sound/pci/fm801.c value[0] = (fm801_ioread16(chip, reg) >> shift_left) & mask; reg 921 sound/pci/fm801.c value[1] = (fm801_ioread16(chip, reg) >> shift_right) & mask; reg 934 sound/pci/fm801.c int reg = kcontrol->private_value & 0xff; reg 947 sound/pci/fm801.c return snd_fm801_update_bits(chip, reg, reg 1083 sound/pci/fm801.c unsigned short reg, unsigned long waits) reg 1088 sound/pci/fm801.c reg | (codec_id << FM801_AC97_ADDR_SHIFT) | FM801_AC97_READ); reg 167 sound/pci/hda/hda_controller.h #define azx_writel(chip, reg, value) \ reg 168 sound/pci/hda/hda_controller.h snd_hdac_chip_writel(azx_bus(chip), reg, value) reg 169 sound/pci/hda/hda_controller.h #define azx_readl(chip, reg) \ reg 170 sound/pci/hda/hda_controller.h snd_hdac_chip_readl(azx_bus(chip), reg) reg 171 sound/pci/hda/hda_controller.h #define azx_writew(chip, reg, value) \ reg 172 sound/pci/hda/hda_controller.h snd_hdac_chip_writew(azx_bus(chip), reg, value) reg 173 sound/pci/hda/hda_controller.h #define azx_readw(chip, reg) \ reg 174 sound/pci/hda/hda_controller.h snd_hdac_chip_readw(azx_bus(chip), reg) reg 175 sound/pci/hda/hda_controller.h #define azx_writeb(chip, reg, value) \ reg 176 sound/pci/hda/hda_controller.h snd_hdac_chip_writeb(azx_bus(chip), reg, value) reg 177 sound/pci/hda/hda_controller.h #define azx_readb(chip, reg) \ reg 178 sound/pci/hda/hda_controller.h snd_hdac_chip_readb(azx_bus(chip), reg) reg 403 sound/pci/hda/hda_intel.c static void update_pci_byte(struct pci_dev *pci, unsigned int reg, reg 408 sound/pci/hda/hda_intel.c pci_read_config_byte(pci, reg, &data); reg 411 sound/pci/hda/hda_intel.c pci_write_config_byte(pci, reg, data); reg 1222 sound/pci/hda/patch_ca0132.c unsigned int reg, reg 1231 sound/pci/hda/patch_ca0132.c reg, data); reg 1610 sound/pci/hda/patch_ca0132.c static int dspio_send(struct hda_codec *codec, unsigned int reg, reg 1618 sound/pci/hda/patch_ca0132.c res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); reg 2391 sound/pci/hda/patch_ca0132.c unsigned int reg = 0; reg 2398 sound/pci/hda/patch_ca0132.c DSPDMAC_CHNLSTART_INST_OFFSET, ®); reg 2406 sound/pci/hda/patch_ca0132.c reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | reg 2411 sound/pci/hda/patch_ca0132.c reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); reg 2427 sound/pci/hda/patch_ca0132.c unsigned int reg = 0; reg 2434 sound/pci/hda/patch_ca0132.c DSPDMAC_CHNLSTART_INST_OFFSET, ®); reg 2441 sound/pci/hda/patch_ca0132.c reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | reg 2446 sound/pci/hda/patch_ca0132.c reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); reg 64 sound/pci/hda/patch_si3054.c #define GET_REG(codec,reg) (snd_hda_codec_read(codec,reg,0,SI3054_VERB_READ_NODE,0)) reg 65 sound/pci/hda/patch_si3054.c #define SET_REG(codec,reg,val) (snd_hda_codec_write(codec,reg,0,SI3054_VERB_WRITE_NODE,val)) reg 66 sound/pci/hda/patch_si3054.c #define SET_REG_CACHE(codec,reg,val) \ reg 67 sound/pci/hda/patch_si3054.c snd_hda_codec_write_cache(codec,reg,0,SI3054_VERB_WRITE_NODE,val) reg 79 sound/pci/hda/patch_si3054.c #define PRIVATE_VALUE(reg,mask) ((reg<<16)|(mask&0xffff)) reg 89 sound/pci/hda/patch_si3054.c u16 reg = PRIVATE_REG(kcontrol->private_value); reg 91 sound/pci/hda/patch_si3054.c uvalue->value.integer.value[0] = (GET_REG(codec, reg)) & mask ? 1 : 0 ; reg 99 sound/pci/hda/patch_si3054.c u16 reg = PRIVATE_REG(kcontrol->private_value); reg 102 sound/pci/hda/patch_si3054.c SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) | mask); reg 104 sound/pci/hda/patch_si3054.c SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) & ~mask); reg 108 sound/pci/hda/patch_si3054.c #define SI3054_KCONTROL(kname,reg,mask) { \ reg 111 sound/pci/hda/patch_si3054.c .subdevice = HDA_SUBDEV_NID_FLAG | reg, \ reg 115 sound/pci/hda/patch_si3054.c .private_value = PRIVATE_VALUE(reg,mask), \ reg 19 sound/pci/ice1712/amp.c static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val) reg 22 sound/pci/ice1712/amp.c cval = (reg << 9) | val; reg 97 sound/pci/ice1712/aureon.c static void aureon_pca9554_write(struct snd_ice1712 *ice, unsigned char reg, reg 144 sound/pci/ice1712/aureon.c val = reg; reg 229 sound/pci/ice1712/aureon.c static void aureon_ac97_write(struct snd_ice1712 *ice, unsigned short reg, reg 236 sound/pci/ice1712/aureon.c tmp = (snd_ice1712_gpio_read(ice) & ~0xFF) | (reg & 0x7F); reg 280 sound/pci/ice1712/aureon.c spec->stac9744[(reg & 0x7F) >> 1] = val; reg 283 sound/pci/ice1712/aureon.c static unsigned short aureon_ac97_read(struct snd_ice1712 *ice, unsigned short reg) reg 286 sound/pci/ice1712/aureon.c return spec->stac9744[(reg & 0x7F) >> 1]; reg 578 sound/pci/ice1712/aureon.c static unsigned char aureon_cs8415_get(struct snd_ice1712 *ice, int reg) reg 581 sound/pci/ice1712/aureon.c aureon_spi_write(ice, AUREON_CS8415_CS, 0x2000 | reg, 16); reg 586 sound/pci/ice1712/aureon.c static void aureon_cs8415_read(struct snd_ice1712 *ice, int reg, reg 589 sound/pci/ice1712/aureon.c aureon_spi_write(ice, AUREON_CS8415_CS, 0x2000 | reg, 16); reg 593 sound/pci/ice1712/aureon.c static void aureon_cs8415_put(struct snd_ice1712 *ice, int reg, reg 596 sound/pci/ice1712/aureon.c aureon_spi_write(ice, AUREON_CS8415_CS, 0x200000 | (reg << 8) | val, 24); reg 602 sound/pci/ice1712/aureon.c static unsigned short wm_get(struct snd_ice1712 *ice, int reg) reg 604 sound/pci/ice1712/aureon.c reg <<= 1; reg 605 sound/pci/ice1712/aureon.c return ((unsigned short)ice->akm[0].images[reg] << 8) | reg 606 sound/pci/ice1712/aureon.c ice->akm[0].images[reg + 1]; reg 612 sound/pci/ice1712/aureon.c static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val) reg 618 sound/pci/ice1712/aureon.c (reg << 9) | (val & 0x1ff), 16); reg 624 sound/pci/ice1712/aureon.c static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val) reg 626 sound/pci/ice1712/aureon.c wm_put_nocache(ice, reg, val); reg 627 sound/pci/ice1712/aureon.c reg <<= 1; reg 628 sound/pci/ice1712/aureon.c ice->akm[0].images[reg] = val >> 8; reg 629 sound/pci/ice1712/aureon.c ice->akm[0].images[reg + 1] = val; reg 410 sound/pci/ice1712/delta.c char reg = 0x10; /* CS8427 receiver error register */ reg 413 sound/pci/ice1712/delta.c if (snd_i2c_sendbytes(ice->cs8427, ®, 1) != 1) reg 415 sound/pci/ice1712/delta.c "unable to send register 0x%x byte to CS8427\n", reg); reg 416 sound/pci/ice1712/delta.c snd_i2c_readbytes(ice->cs8427, ®, 1); reg 417 sound/pci/ice1712/delta.c ucontrol->value.integer.value[0] = (reg & CS8427_UNLOCK) ? 1 : 0; reg 407 sound/pci/ice1712/ews.c static int snd_ice1712_6fire_write_pca(struct snd_ice1712 *ice, unsigned char reg, unsigned char data); reg 808 sound/pci/ice1712/ews.c static int snd_ice1712_6fire_read_pca(struct snd_ice1712 *ice, unsigned char reg) reg 814 sound/pci/ice1712/ews.c byte = reg; reg 831 sound/pci/ice1712/ews.c static int snd_ice1712_6fire_write_pca(struct snd_ice1712 *ice, unsigned char reg, unsigned char data) reg 837 sound/pci/ice1712/ews.c bytes[0] = reg; reg 136 sound/pci/ice1712/ice1712.c unsigned short reg, reg 151 sound/pci/ice1712/ice1712.c outb(reg, ICEREG(ice, AC97_INDEX)); reg 161 sound/pci/ice1712/ice1712.c unsigned short reg) reg 175 sound/pci/ice1712/ice1712.c outb(reg, ICEREG(ice, AC97_INDEX)); reg 190 sound/pci/ice1712/ice1712.c unsigned short reg, reg 205 sound/pci/ice1712/ice1712.c outb(reg, ICEMT(ice, AC97_INDEX)); reg 216 sound/pci/ice1712/ice1712.c unsigned short reg) reg 230 sound/pci/ice1712/ice1712.c outb(reg, ICEMT(ice, AC97_INDEX)); reg 325 sound/pci/ice1712/ice1712.c unsigned char reg[2] = { 0x80 | 4, 0 }; /* CS8427 auto increment | register number 4 + data */ reg 330 sound/pci/ice1712/ice1712.c if (snd_i2c_sendbytes(ice->cs8427, reg, 1) != 1) { reg 344 sound/pci/ice1712/ice1712.c reg[1] = nval; reg 345 sound/pci/ice1712/ice1712.c if (snd_i2c_sendbytes(ice->cs8427, reg, 2) != 2) { reg 150 sound/pci/ice1712/ice1724.c unsigned short reg, reg 159 sound/pci/ice1712/ice1724.c outb(reg, ICEMT1724(ice, AC97_INDEX)); reg 165 sound/pci/ice1712/ice1724.c static unsigned short snd_vt1724_ac97_read(struct snd_ac97 *ac97, unsigned short reg) reg 173 sound/pci/ice1712/ice1724.c outb(reg, ICEMT1724(ice, AC97_INDEX)); reg 551 sound/pci/ice1712/ice1724.c const struct vt1724_pcm_reg *reg; reg 552 sound/pci/ice1712/ice1724.c reg = s->runtime->private_data; reg 553 sound/pci/ice1712/ice1724.c what |= reg->start; reg 841 sound/pci/ice1712/ice1724.c const struct vt1724_pcm_reg *reg = substream->runtime->private_data; reg 844 sound/pci/ice1712/ice1724.c outl(substream->runtime->dma_addr, ice->profi_port + reg->addr); reg 846 sound/pci/ice1712/ice1724.c ice->profi_port + reg->size); reg 848 sound/pci/ice1712/ice1724.c ice->profi_port + reg->count); reg 856 sound/pci/ice1712/ice1724.c const struct vt1724_pcm_reg *reg = substream->runtime->private_data; reg 859 sound/pci/ice1712/ice1724.c if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & reg->start)) reg 862 sound/pci/ice1712/ice1724.c ptr = inl(ice->profi_port + reg->addr); reg 866 sound/pci/ice1712/ice1724.c ptr = inw(ice->profi_port + reg->size); reg 149 sound/pci/ice1712/juli.c static void juli_ak4114_write(void *private_data, unsigned char reg, reg 153 sound/pci/ice1712/juli.c reg, val); reg 156 sound/pci/ice1712/juli.c static unsigned char juli_ak4114_read(void *private_data, unsigned char reg) reg 159 sound/pci/ice1712/juli.c AK4114_ADDR, reg); reg 77 sound/pci/ice1712/maya44.c unsigned char reg, unsigned short val) reg 84 sound/pci/ice1712/maya44.c (reg << 1) | ((val >> 8) & 1), reg 86 sound/pci/ice1712/maya44.c wm->regs[reg] = val; reg 93 sound/pci/ice1712/maya44.c unsigned char reg, reg 96 sound/pci/ice1712/maya44.c val |= wm->regs[reg] & ~mask; reg 97 sound/pci/ice1712/maya44.c if (val != wm->regs[reg]) { reg 98 sound/pci/ice1712/maya44.c wm8776_write(ice, wm, reg, val); reg 224 sound/pci/ice1712/maya44.c #define COMPOSE_SW_VAL(idx, reg, mask) ((idx) | ((reg) << 8) | ((mask) << 16)) reg 564 sound/pci/ice1712/maya44.c unsigned char reg; reg 573 sound/pci/ice1712/maya44.c reg = *ptr++; reg 575 sound/pci/ice1712/maya44.c wm8776_write(ice, wm, reg, data); reg 239 sound/pci/ice1712/phase.c static unsigned short wm_get(struct snd_ice1712 *ice, int reg) reg 241 sound/pci/ice1712/phase.c reg <<= 1; reg 242 sound/pci/ice1712/phase.c return ((unsigned short)ice->akm[0].images[reg] << 8) | reg 243 sound/pci/ice1712/phase.c ice->akm[0].images[reg + 1]; reg 249 sound/pci/ice1712/phase.c static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val) reg 251 sound/pci/ice1712/phase.c phase28_spi_write(ice, PHASE28_WM_CS, (reg << 9) | (val & 0x1ff), 16); reg 257 sound/pci/ice1712/phase.c static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val) reg 259 sound/pci/ice1712/phase.c wm_put_nocache(ice, reg, val); reg 260 sound/pci/ice1712/phase.c reg <<= 1; reg 261 sound/pci/ice1712/phase.c ice->akm[0].images[reg] = val >> 8; reg 262 sound/pci/ice1712/phase.c ice->akm[0].images[reg + 1] = val; reg 67 sound/pci/ice1712/pontis.c static unsigned short wm_get(struct snd_ice1712 *ice, int reg) reg 69 sound/pci/ice1712/pontis.c reg <<= 1; reg 70 sound/pci/ice1712/pontis.c return ((unsigned short)ice->akm[0].images[reg] << 8) | reg 71 sound/pci/ice1712/pontis.c ice->akm[0].images[reg + 1]; reg 77 sound/pci/ice1712/pontis.c static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val) reg 80 sound/pci/ice1712/pontis.c cval = (reg << 9) | val; reg 84 sound/pci/ice1712/pontis.c static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val) reg 86 sound/pci/ice1712/pontis.c wm_put_nocache(ice, reg, val); reg 87 sound/pci/ice1712/pontis.c reg <<= 1; reg 88 sound/pci/ice1712/pontis.c ice->akm[0].images[reg] = val >> 8; reg 89 sound/pci/ice1712/pontis.c ice->akm[0].images[reg + 1] = val; reg 356 sound/pci/ice1712/pontis.c static void spi_write(struct snd_ice1712 *ice, unsigned int dev, unsigned int reg, unsigned int data) reg 362 sound/pci/ice1712/pontis.c spi_send_byte(ice, reg); /* MAP */ reg 372 sound/pci/ice1712/pontis.c static unsigned int spi_read(struct snd_ice1712 *ice, unsigned int dev, unsigned int reg) reg 379 sound/pci/ice1712/pontis.c spi_send_byte(ice, reg); /* MAP */ reg 622 sound/pci/ice1712/pontis.c unsigned int reg, val; reg 625 sound/pci/ice1712/pontis.c if (sscanf(line, "%x %x", ®, &val) != 2) reg 627 sound/pci/ice1712/pontis.c if (reg <= 0x17 && val <= 0xffff) reg 628 sound/pci/ice1712/pontis.c wm_put(ice, reg, val); reg 636 sound/pci/ice1712/pontis.c int reg, val; reg 639 sound/pci/ice1712/pontis.c for (reg = 0; reg <= 0x17; reg++) { reg 640 sound/pci/ice1712/pontis.c val = wm_get(ice, reg); reg 641 sound/pci/ice1712/pontis.c snd_iprintf(buffer, "%02x = %04x\n", reg, val); reg 655 sound/pci/ice1712/pontis.c int reg, val; reg 658 sound/pci/ice1712/pontis.c for (reg = 0; reg <= 0x26; reg++) { reg 659 sound/pci/ice1712/pontis.c val = spi_read(ice, CS_DEV, reg); reg 660 sound/pci/ice1712/pontis.c snd_iprintf(buffer, "%02x = %02x\n", reg, val); reg 61 sound/pci/ice1712/prodigy192.c static inline void stac9460_put(struct snd_ice1712 *ice, int reg, unsigned char val) reg 63 sound/pci/ice1712/prodigy192.c snd_vt1724_write_i2c(ice, PRODIGY192_STAC9460_ADDR, reg, val); reg 66 sound/pci/ice1712/prodigy192.c static inline unsigned char stac9460_get(struct snd_ice1712 *ice, int reg) reg 68 sound/pci/ice1712/prodigy192.c return snd_vt1724_read_i2c(ice, PRODIGY192_STAC9460_ADDR, reg); reg 207 sound/pci/ice1712/prodigy192.c int i, reg; reg 211 sound/pci/ice1712/prodigy192.c reg = STAC946X_MIC_L_VOLUME + i; reg 212 sound/pci/ice1712/prodigy192.c old = stac9460_get(ice, reg); reg 216 sound/pci/ice1712/prodigy192.c stac9460_put(ice, reg, new); reg 237 sound/pci/ice1712/prodigy192.c int i, reg; reg 241 sound/pci/ice1712/prodigy192.c reg = STAC946X_MIC_L_VOLUME + i; reg 242 sound/pci/ice1712/prodigy192.c vol = stac9460_get(ice, reg) & 0x0f; reg 252 sound/pci/ice1712/prodigy192.c int i, reg; reg 257 sound/pci/ice1712/prodigy192.c reg = STAC946X_MIC_L_VOLUME + i; reg 259 sound/pci/ice1712/prodigy192.c ovol = 0x0f - stac9460_get(ice, reg); reg 262 sound/pci/ice1712/prodigy192.c stac9460_put(ice, reg, (0x0f - nvol) | (ovol & ~0x0f)); reg 629 sound/pci/ice1712/prodigy192.c int reg, val; reg 631 sound/pci/ice1712/prodigy192.c for (reg = 0; reg <= 0x15; reg++) { reg 632 sound/pci/ice1712/prodigy192.c val = stac9460_get(ice, reg); reg 633 sound/pci/ice1712/prodigy192.c snd_iprintf(buffer, "0x%02x = 0x%02x\n", reg, val); reg 113 sound/pci/ice1712/prodigy_hifi.c static unsigned short wm_get(struct snd_ice1712 *ice, int reg) reg 115 sound/pci/ice1712/prodigy_hifi.c reg <<= 1; reg 116 sound/pci/ice1712/prodigy_hifi.c return ((unsigned short)ice->akm[0].images[reg] << 8) | reg 117 sound/pci/ice1712/prodigy_hifi.c ice->akm[0].images[reg + 1]; reg 123 sound/pci/ice1712/prodigy_hifi.c static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val) reg 126 sound/pci/ice1712/prodigy_hifi.c cval = (reg << 9) | val; reg 130 sound/pci/ice1712/prodigy_hifi.c static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val) reg 132 sound/pci/ice1712/prodigy_hifi.c wm_put_nocache(ice, reg, val); reg 133 sound/pci/ice1712/prodigy_hifi.c reg <<= 1; reg 134 sound/pci/ice1712/prodigy_hifi.c ice->akm[0].images[reg] = val >> 8; reg 135 sound/pci/ice1712/prodigy_hifi.c ice->akm[0].images[reg + 1] = val; reg 170 sound/pci/ice1712/prodigy_hifi.c static void wm8766_spi_write(struct snd_ice1712 *ice, unsigned int reg, reg 181 sound/pci/ice1712/prodigy_hifi.c block = (reg << 9) | (data & 0x1ff); reg 210 sound/pci/ice1712/prodigy_hifi.c static void ak4396_write(struct snd_ice1712 *ice, unsigned int reg, reg 220 sound/pci/ice1712/prodigy_hifi.c ((reg & 0x1f) << 8) | (data & 0xff); reg 866 sound/pci/ice1712/prodigy_hifi.c unsigned int reg, val; reg 869 sound/pci/ice1712/prodigy_hifi.c if (sscanf(line, "%x %x", ®, &val) != 2) reg 871 sound/pci/ice1712/prodigy_hifi.c if (reg <= 0x17 && val <= 0xffff) reg 872 sound/pci/ice1712/prodigy_hifi.c wm_put(ice, reg, val); reg 881 sound/pci/ice1712/prodigy_hifi.c int reg, val; reg 884 sound/pci/ice1712/prodigy_hifi.c for (reg = 0; reg <= 0x17; reg++) { reg 885 sound/pci/ice1712/prodigy_hifi.c val = wm_get(ice, reg); reg 886 sound/pci/ice1712/prodigy_hifi.c snd_iprintf(buffer, "%02x = %04x\n", reg, val); reg 236 sound/pci/ice1712/quartet.c static void qtet_ak4113_write(void *private_data, unsigned char reg, reg 240 sound/pci/ice1712/quartet.c reg, val); reg 243 sound/pci/ice1712/quartet.c static unsigned char qtet_ak4113_read(void *private_data, unsigned char reg) reg 246 sound/pci/ice1712/quartet.c AK4113_ADDR, reg); reg 394 sound/pci/ice1712/quartet.c static void reg_write(struct snd_ice1712 *ice, unsigned int reg, reg 417 sound/pci/ice1712/quartet.c tmp &= ~reg; reg 421 sound/pci/ice1712/quartet.c tmp |= reg; reg 42 sound/pci/ice1712/revo.c int reg, shift; reg 56 sound/pci/ice1712/revo.c reg = 2; reg 59 sound/pci/ice1712/revo.c reg = 1; reg 62 sound/pci/ice1712/revo.c tmp = snd_akm4xxx_get(ak, 0, reg); reg 69 sound/pci/ice1712/revo.c tmp = snd_akm4xxx_get(ak, 0, reg); reg 73 sound/pci/ice1712/revo.c snd_akm4xxx_set(ak, 0, reg, tmp); /* value is written in reset(0) */ reg 35 sound/pci/ice1712/wtm.c static inline void stac9460_put(struct snd_ice1712 *ice, int reg, reg 38 sound/pci/ice1712/wtm.c snd_vt1724_write_i2c(ice, STAC9460_I2C_ADDR, reg, val); reg 41 sound/pci/ice1712/wtm.c static inline unsigned char stac9460_get(struct snd_ice1712 *ice, int reg) reg 43 sound/pci/ice1712/wtm.c return snd_vt1724_read_i2c(ice, STAC9460_I2C_ADDR, reg); reg 49 sound/pci/ice1712/wtm.c static inline void stac9460_2_put(struct snd_ice1712 *ice, int reg, reg 52 sound/pci/ice1712/wtm.c snd_vt1724_write_i2c(ice, STAC9460_2_I2C_ADDR, reg, val); reg 55 sound/pci/ice1712/wtm.c static inline unsigned char stac9460_2_get(struct snd_ice1712 *ice, int reg) reg 57 sound/pci/ice1712/wtm.c return snd_vt1724_read_i2c(ice, STAC9460_2_I2C_ADDR, reg); reg 285 sound/pci/ice1712/wtm.c int i, reg, id; reg 291 sound/pci/ice1712/wtm.c reg = STAC946X_MIC_L_VOLUME + i; reg 292 sound/pci/ice1712/wtm.c old = stac9460_get(ice, reg); reg 297 sound/pci/ice1712/wtm.c stac9460_put(ice, reg, new); reg 301 sound/pci/ice1712/wtm.c reg = STAC946X_MIC_L_VOLUME + i; reg 302 sound/pci/ice1712/wtm.c old = stac9460_2_get(ice, reg); reg 307 sound/pci/ice1712/wtm.c stac9460_2_put(ice, reg, new); reg 330 sound/pci/ice1712/wtm.c int i, reg, id; reg 336 sound/pci/ice1712/wtm.c reg = STAC946X_MIC_L_VOLUME + i; reg 337 sound/pci/ice1712/wtm.c vol = stac9460_get(ice, reg) & 0x0f; reg 342 sound/pci/ice1712/wtm.c reg = STAC946X_MIC_L_VOLUME + i; reg 343 sound/pci/ice1712/wtm.c vol = stac9460_2_get(ice, reg) & 0x0f; reg 354 sound/pci/ice1712/wtm.c int i, reg, id; reg 361 sound/pci/ice1712/wtm.c reg = STAC946X_MIC_L_VOLUME + i; reg 363 sound/pci/ice1712/wtm.c ovol = 0x0f - stac9460_get(ice, reg); reg 366 sound/pci/ice1712/wtm.c stac9460_put(ice, reg, (0x0f - nvol) | reg 371 sound/pci/ice1712/wtm.c reg = STAC946X_MIC_L_VOLUME + i; reg 373 sound/pci/ice1712/wtm.c ovol = 0x0f - stac9460_2_get(ice, reg); reg 376 sound/pci/ice1712/wtm.c stac9460_2_put(ice, reg, (0x0f - nvol) | reg 534 sound/pci/intel8x0.c unsigned short reg, reg 543 sound/pci/intel8x0.c ac97->num, reg); reg 545 sound/pci/intel8x0.c iaputword(chip, reg + ac97->num * 0x80, val); reg 549 sound/pci/intel8x0.c unsigned short reg) reg 559 sound/pci/intel8x0.c ac97->num, reg); reg 562 sound/pci/intel8x0.c res = iagetword(chip, reg + ac97->num * 0x80); reg 570 sound/pci/intel8x0.c ac97->num, reg); reg 620 sound/pci/intel8x0.c static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg) reg 627 sound/pci/intel8x0.c reg |= ALI_CPR_ADDR_READ; reg 629 sound/pci/intel8x0.c reg |= ALI_CPR_ADDR_SECONDARY; reg 630 sound/pci/intel8x0.c iputword(chip, ICHREG(ALI_CPR_ADDR), reg); reg 638 sound/pci/intel8x0.c static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg, reg 647 sound/pci/intel8x0.c reg |= ALI_CPR_ADDR_SECONDARY; reg 648 sound/pci/intel8x0.c iputword(chip, ICHREG(ALI_CPR_ADDR), reg); reg 2215 sound/pci/intel8x0.c unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR)); reg 2216 sound/pci/intel8x0.c if (reg & 0x40) { reg 2220 sound/pci/intel8x0.c iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40); reg 2486 sound/pci/intel8x0.c u32 reg; reg 2489 sound/pci/intel8x0.c reg = igetdword(chip, ICHREG(ALI_SCR)); reg 2490 sound/pci/intel8x0.c if ((reg & 2) == 0) /* Cold required */ reg 2491 sound/pci/intel8x0.c reg |= 2; reg 2493 sound/pci/intel8x0.c reg |= 1; /* Warm */ reg 2494 sound/pci/intel8x0.c reg &= ~0x80000000; /* ACLink on */ reg 2495 sound/pci/intel8x0.c iputdword(chip, ICHREG(ALI_SCR), reg); reg 2508 sound/pci/intel8x0.c reg = igetdword(chip, ICHREG(ALI_RTSR)); reg 2509 sound/pci/intel8x0.c if (reg & 0x80) /* primary codec */ reg 2511 sound/pci/intel8x0.c iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80); reg 331 sound/pci/intel8x0m.c unsigned short reg, reg 340 sound/pci/intel8x0m.c ac97->num, reg); reg 342 sound/pci/intel8x0m.c iaputword(chip, reg + ac97->num * 0x80, val); reg 346 sound/pci/intel8x0m.c unsigned short reg) reg 356 sound/pci/intel8x0m.c ac97->num, reg); reg 359 sound/pci/intel8x0m.c res = iagetword(chip, reg + ac97->num * 0x80); reg 367 sound/pci/intel8x0m.c ac97->num, reg); reg 371 sound/pci/intel8x0m.c if (reg == AC97_GPIO_STATUS) reg 227 sound/pci/lola/lola.c unsigned int reg; reg 241 sound/pci/lola/lola.c reg = lola_dsd_read(chip, i, STS); reg 242 sound/pci/lola/lola.c if (reg & LOLA_DSD_STS_DESE) /* error */ reg 244 sound/pci/lola/lola.c if (reg & LOLA_DSD_STS_BCIS) /* notify */ reg 247 sound/pci/lola/lola.c lola_dsd_write(chip, i, STS, reg); reg 255 sound/pci/lola/lola.c reg = lola_dsd_read(chip, i + MAX_STREAM_IN_COUNT, STS); reg 256 sound/pci/lola/lola.c if (reg & LOLA_DSD_STS_DESE) /* error */ reg 258 sound/pci/lola/lola.c if (reg & LOLA_DSD_STS_BCIS) /* notify */ reg 260 sound/pci/lola/lola.c lola_dsd_write(chip, i + MAX_STREAM_IN_COUNT, STS, reg); reg 103 sound/pci/lola/lola_pcm.c unsigned int reg = lola_dsd_read(chip, str->dsd, STS); reg 104 sound/pci/lola/lola_pcm.c if ((reg & LOLA_DSD_STS_FIFORDY) == val) reg 132 sound/pci/lola/lola_pcm.c unsigned int reg; reg 133 sound/pci/lola/lola_pcm.c reg = lola_dsd_read(chip, str->dsd, STS); reg 134 sound/pci/lola/lola_pcm.c if ((reg & LOLA_DSD_STS_FIFORDY) != val) { reg 606 sound/pci/lx6464es/lx6464es.c u32 reg; reg 613 sound/pci/lx6464es/lx6464es.c reg = lx_dsp_reg_read(chip, eReg_CSM); reg 615 sound/pci/lx6464es/lx6464es.c if (reg) { reg 616 sound/pci/lx6464es/lx6464es.c dev_err(chip->card->dev, "Problem: Reg_CSM %x.\n", reg); reg 621 sound/pci/lx6464es/lx6464es.c reg = lx_dsp_reg_read(chip, eReg_CSM); reg 622 sound/pci/lx6464es/lx6464es.c if (reg) { reg 623 sound/pci/lx6464es/lx6464es.c dev_err(chip->card->dev, "Error: Reg_CSM %x.\n", reg); reg 258 sound/pci/lx6464es/lx_core.c u32 reg = ED_DSP_TIMED_OUT; reg 262 sound/pci/lx6464es/lx_core.c dev_err(chip->card->dev, "PIOSendMessage eReg_CSM %x\n", reg); reg 276 sound/pci/lx6464es/lx_core.c reg = lx_dsp_reg_read(chip, eReg_CRM1); reg 278 sound/pci/lx6464es/lx_core.c reg = 0; reg 287 sound/pci/lx6464es/lx_core.c if ((reg & ERROR_VALUE) == 0) { reg 295 sound/pci/lx6464es/lx_core.c dev_err(chip->card->dev, "rmh error: %08x\n", reg); reg 300 sound/pci/lx6464es/lx_core.c switch (reg) { reg 312 sound/pci/lx6464es/lx_core.c return reg; reg 1154 sound/pci/lx6464es/lx_core.c u32 reg = lx_plx_reg_read(chip, ePLX_IRQCS); reg 1162 sound/pci/lx6464es/lx_core.c reg |= (IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB); reg 1164 sound/pci/lx6464es/lx_core.c reg &= ~(IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB); reg 1165 sound/pci/lx6464es/lx_core.c lx_plx_reg_write(chip, ePLX_IRQCS, reg); reg 915 sound/pci/maestro3.c static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg) reg 917 sound/pci/maestro3.c outw(value, chip->iobase + reg); reg 920 sound/pci/maestro3.c static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg) reg 922 sound/pci/maestro3.c return inw(chip->iobase + reg); reg 925 sound/pci/maestro3.c static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg) reg 927 sound/pci/maestro3.c outb(value, chip->iobase + reg); reg 930 sound/pci/maestro3.c static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg) reg 932 sound/pci/maestro3.c return inb(chip->iobase + reg); reg 1893 sound/pci/maestro3.c snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg) reg 1900 sound/pci/maestro3.c snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND); reg 1909 sound/pci/maestro3.c snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) reg 1916 sound/pci/maestro3.c snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND); reg 1922 sound/pci/maestro3.c if (ac97->id == 0x45838308 && reg == AC97_MASTER) { reg 1925 sound/pci/maestro3.c snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND); reg 487 sound/pci/nm256/nm256.c static void snd_nm256_pcm_mark(struct nm256 *chip, struct nm256_stream *s, int reg) reg 491 sound/pci/nm256/nm256.c snd_nm256_writel(chip, reg, s->buf + s->cur_period * s->period_size); reg 1178 sound/pci/nm256/nm256.c unsigned short reg; reg 1203 sound/pci/nm256/nm256.c static int nm256_ac97_idx(unsigned short reg) reg 1207 sound/pci/nm256/nm256.c if (nm256_ac97_init_val[i].reg == reg) reg 1218 sound/pci/nm256/nm256.c snd_nm256_ac97_read(struct snd_ac97 *ac97, unsigned short reg) reg 1221 sound/pci/nm256/nm256.c int idx = nm256_ac97_idx(reg); reg 1232 sound/pci/nm256/nm256.c unsigned short reg, unsigned short val) reg 1236 sound/pci/nm256/nm256.c int idx = nm256_ac97_idx(reg); reg 1248 sound/pci/nm256/nm256.c snd_nm256_writew(chip, base + reg, val); reg 1299 sound/pci/nm256/nm256.c snd_nm256_ac97_write(ac97, nm256_ac97_init_val[i].reg, reg 143 sound/pci/oxygen/oxygen.c u8 reg, u8 value) reg 156 sound/pci/oxygen/oxygen.c AK4396_WRITE | (reg << 8) | value); reg 157 sound/pci/oxygen/oxygen.c data->ak4396_regs[codec][reg] = value; reg 161 sound/pci/oxygen/oxygen.c u8 reg, u8 value) reg 165 sound/pci/oxygen/oxygen.c if (value != data->ak4396_regs[codec][reg]) reg 166 sound/pci/oxygen/oxygen.c ak4396_write(chip, codec, reg, value); reg 169 sound/pci/oxygen/oxygen.c static void wm8785_write(struct oxygen *chip, u8 reg, unsigned int value) reg 178 sound/pci/oxygen/oxygen.c (reg << 9) | value); reg 179 sound/pci/oxygen/oxygen.c if (reg < ARRAY_SIZE(data->wm8785_regs)) reg 180 sound/pci/oxygen/oxygen.c data->wm8785_regs[reg] = value; reg 454 sound/pci/oxygen/oxygen.c u8 reg; reg 457 sound/pci/oxygen/oxygen.c reg = data->ak4396_regs[0][AK4396_CONTROL_2]; reg 459 sound/pci/oxygen/oxygen.c reg |= AK4396_SLOW; reg 461 sound/pci/oxygen/oxygen.c reg &= ~AK4396_SLOW; reg 462 sound/pci/oxygen/oxygen.c changed = reg != data->ak4396_regs[0][AK4396_CONTROL_2]; reg 465 sound/pci/oxygen/oxygen.c ak4396_write(chip, i, AK4396_CONTROL_2, reg); reg 502 sound/pci/oxygen/oxygen.c unsigned int reg; reg 506 sound/pci/oxygen/oxygen.c reg = data->wm8785_regs[WM8785_R2] & ~(WM8785_HPFR | WM8785_HPFL); reg 508 sound/pci/oxygen/oxygen.c reg |= WM8785_HPFR | WM8785_HPFL; reg 509 sound/pci/oxygen/oxygen.c changed = reg != data->wm8785_regs[WM8785_R2]; reg 511 sound/pci/oxygen/oxygen.c wm8785_write(chip, WM8785_R2, reg); reg 101 sound/pci/oxygen/oxygen.h unsigned int reg, unsigned int mute); reg 182 sound/pci/oxygen/oxygen.h u8 oxygen_read8(struct oxygen *chip, unsigned int reg); reg 183 sound/pci/oxygen/oxygen.h u16 oxygen_read16(struct oxygen *chip, unsigned int reg); reg 184 sound/pci/oxygen/oxygen.h u32 oxygen_read32(struct oxygen *chip, unsigned int reg); reg 185 sound/pci/oxygen/oxygen.h void oxygen_write8(struct oxygen *chip, unsigned int reg, u8 value); reg 186 sound/pci/oxygen/oxygen.h void oxygen_write16(struct oxygen *chip, unsigned int reg, u16 value); reg 187 sound/pci/oxygen/oxygen.h void oxygen_write32(struct oxygen *chip, unsigned int reg, u32 value); reg 188 sound/pci/oxygen/oxygen.h void oxygen_write8_masked(struct oxygen *chip, unsigned int reg, reg 190 sound/pci/oxygen/oxygen.h void oxygen_write16_masked(struct oxygen *chip, unsigned int reg, reg 192 sound/pci/oxygen/oxygen.h void oxygen_write32_masked(struct oxygen *chip, unsigned int reg, reg 212 sound/pci/oxygen/oxygen.h unsigned int reg, u8 value) reg 214 sound/pci/oxygen/oxygen.h oxygen_write8_masked(chip, reg, value, value); reg 218 sound/pci/oxygen/oxygen.h unsigned int reg, u16 value) reg 220 sound/pci/oxygen/oxygen.h oxygen_write16_masked(chip, reg, value, value); reg 224 sound/pci/oxygen/oxygen.h unsigned int reg, u32 value) reg 226 sound/pci/oxygen/oxygen.h oxygen_write32_masked(chip, reg, value, value); reg 230 sound/pci/oxygen/oxygen.h unsigned int reg, u8 value) reg 232 sound/pci/oxygen/oxygen.h oxygen_write8_masked(chip, reg, 0, value); reg 236 sound/pci/oxygen/oxygen.h unsigned int reg, u16 value) reg 238 sound/pci/oxygen/oxygen.h oxygen_write16_masked(chip, reg, 0, value); reg 242 sound/pci/oxygen/oxygen.h unsigned int reg, u32 value) reg 244 sound/pci/oxygen/oxygen.h oxygen_write32_masked(chip, reg, 0, value); reg 16 sound/pci/oxygen/oxygen_io.c u8 oxygen_read8(struct oxygen *chip, unsigned int reg) reg 18 sound/pci/oxygen/oxygen_io.c return inb(chip->addr + reg); reg 22 sound/pci/oxygen/oxygen_io.c u16 oxygen_read16(struct oxygen *chip, unsigned int reg) reg 24 sound/pci/oxygen/oxygen_io.c return inw(chip->addr + reg); reg 28 sound/pci/oxygen/oxygen_io.c u32 oxygen_read32(struct oxygen *chip, unsigned int reg) reg 30 sound/pci/oxygen/oxygen_io.c return inl(chip->addr + reg); reg 34 sound/pci/oxygen/oxygen_io.c void oxygen_write8(struct oxygen *chip, unsigned int reg, u8 value) reg 36 sound/pci/oxygen/oxygen_io.c outb(value, chip->addr + reg); reg 37 sound/pci/oxygen/oxygen_io.c chip->saved_registers._8[reg] = value; reg 41 sound/pci/oxygen/oxygen_io.c void oxygen_write16(struct oxygen *chip, unsigned int reg, u16 value) reg 43 sound/pci/oxygen/oxygen_io.c outw(value, chip->addr + reg); reg 44 sound/pci/oxygen/oxygen_io.c chip->saved_registers._16[reg / 2] = cpu_to_le16(value); reg 48 sound/pci/oxygen/oxygen_io.c void oxygen_write32(struct oxygen *chip, unsigned int reg, u32 value) reg 50 sound/pci/oxygen/oxygen_io.c outl(value, chip->addr + reg); reg 51 sound/pci/oxygen/oxygen_io.c chip->saved_registers._32[reg / 4] = cpu_to_le32(value); reg 55 sound/pci/oxygen/oxygen_io.c void oxygen_write8_masked(struct oxygen *chip, unsigned int reg, reg 58 sound/pci/oxygen/oxygen_io.c u8 tmp = inb(chip->addr + reg); reg 61 sound/pci/oxygen/oxygen_io.c outb(tmp, chip->addr + reg); reg 62 sound/pci/oxygen/oxygen_io.c chip->saved_registers._8[reg] = tmp; reg 66 sound/pci/oxygen/oxygen_io.c void oxygen_write16_masked(struct oxygen *chip, unsigned int reg, reg 69 sound/pci/oxygen/oxygen_io.c u16 tmp = inw(chip->addr + reg); reg 72 sound/pci/oxygen/oxygen_io.c outw(tmp, chip->addr + reg); reg 73 sound/pci/oxygen/oxygen_io.c chip->saved_registers._16[reg / 2] = cpu_to_le16(tmp); reg 77 sound/pci/oxygen/oxygen_io.c void oxygen_write32_masked(struct oxygen *chip, unsigned int reg, reg 80 sound/pci/oxygen/oxygen_io.c u32 tmp = inl(chip->addr + reg); reg 83 sound/pci/oxygen/oxygen_io.c outl(tmp, chip->addr + reg); reg 84 sound/pci/oxygen/oxygen_io.c chip->saved_registers._32[reg / 4] = cpu_to_le32(tmp); reg 121 sound/pci/oxygen/oxygen_io.c u32 reg; reg 123 sound/pci/oxygen/oxygen_io.c reg = data; reg 124 sound/pci/oxygen/oxygen_io.c reg |= index << OXYGEN_AC97_REG_ADDR_SHIFT; reg 125 sound/pci/oxygen/oxygen_io.c reg |= OXYGEN_AC97_REG_DIR_WRITE; reg 126 sound/pci/oxygen/oxygen_io.c reg |= codec << OXYGEN_AC97_REG_CODEC_SHIFT; reg 130 sound/pci/oxygen/oxygen_io.c oxygen_write32(chip, OXYGEN_AC97_REGS, reg); reg 147 sound/pci/oxygen/oxygen_io.c u32 reg; reg 149 sound/pci/oxygen/oxygen_io.c reg = index << OXYGEN_AC97_REG_ADDR_SHIFT; reg 150 sound/pci/oxygen/oxygen_io.c reg |= OXYGEN_AC97_REG_DIR_READ; reg 151 sound/pci/oxygen/oxygen_io.c reg |= codec << OXYGEN_AC97_REG_CODEC_SHIFT; reg 154 sound/pci/oxygen/oxygen_io.c oxygen_write32(chip, OXYGEN_AC97_REGS, reg); reg 167 sound/pci/oxygen/oxygen_io.c reg ^= 0xffff; reg 122 sound/pci/oxygen/oxygen_lib.c u32 reg; reg 131 sound/pci/oxygen/oxygen_lib.c reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); reg 132 sound/pci/oxygen/oxygen_lib.c if ((reg & (OXYGEN_SPDIF_SENSE_STATUS | reg 139 sound/pci/oxygen/oxygen_lib.c reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK; reg 140 sound/pci/oxygen/oxygen_lib.c oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg); reg 144 sound/pci/oxygen/oxygen_lib.c reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); reg 145 sound/pci/oxygen/oxygen_lib.c if ((reg & (OXYGEN_SPDIF_SENSE_STATUS | reg 149 sound/pci/oxygen/oxygen_lib.c if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK) reg 155 sound/pci/oxygen/oxygen_lib.c reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK; reg 156 sound/pci/oxygen/oxygen_lib.c reg |= OXYGEN_SPDIF_IN_CLOCK_96; reg 157 sound/pci/oxygen/oxygen_lib.c oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg); reg 512 sound/pci/oxygen/oxygen_mixer.c u16 reg; reg 515 sound/pci/oxygen/oxygen_mixer.c reg = oxygen_read_ac97(chip, codec, index); reg 517 sound/pci/oxygen/oxygen_mixer.c if (!(reg & (1 << bitnr)) ^ !invert) reg 605 sound/pci/oxygen/oxygen_mixer.c u16 reg; reg 608 sound/pci/oxygen/oxygen_mixer.c reg = oxygen_read_ac97(chip, codec, index); reg 611 sound/pci/oxygen/oxygen_mixer.c value->value.integer.value[0] = 31 - (reg & 0x1f); reg 613 sound/pci/oxygen/oxygen_mixer.c value->value.integer.value[0] = 31 - ((reg >> 8) & 0x1f); reg 614 sound/pci/oxygen/oxygen_mixer.c value->value.integer.value[1] = 31 - (reg & 0x1f); reg 700 sound/pci/oxygen/oxygen_mixer.c u16 reg; reg 703 sound/pci/oxygen/oxygen_mixer.c reg = oxygen_read_ac97(chip, 1, AC97_REC_GAIN); reg 705 sound/pci/oxygen/oxygen_mixer.c value->value.integer.value[0] = reg & 7; reg 706 sound/pci/oxygen/oxygen_mixer.c value->value.integer.value[1] = (reg >> 8) & 7; reg 66 sound/pci/oxygen/xonar_cs43xx.c static void cs4398_write(struct oxygen *chip, u8 reg, u8 value) reg 70 sound/pci/oxygen/xonar_cs43xx.c oxygen_write_i2c(chip, I2C_DEVICE_CS4398, reg, value); reg 71 sound/pci/oxygen/xonar_cs43xx.c if (reg < ARRAY_SIZE(data->cs4398_regs)) reg 72 sound/pci/oxygen/xonar_cs43xx.c data->cs4398_regs[reg] = value; reg 75 sound/pci/oxygen/xonar_cs43xx.c static void cs4398_write_cached(struct oxygen *chip, u8 reg, u8 value) reg 79 sound/pci/oxygen/xonar_cs43xx.c if (value != data->cs4398_regs[reg]) reg 80 sound/pci/oxygen/xonar_cs43xx.c cs4398_write(chip, reg, value); reg 83 sound/pci/oxygen/xonar_cs43xx.c static void cs4362a_write(struct oxygen *chip, u8 reg, u8 value) reg 87 sound/pci/oxygen/xonar_cs43xx.c oxygen_write_i2c(chip, I2C_DEVICE_CS4362A, reg, value); reg 88 sound/pci/oxygen/xonar_cs43xx.c if (reg < ARRAY_SIZE(data->cs4362a_regs)) reg 89 sound/pci/oxygen/xonar_cs43xx.c data->cs4362a_regs[reg] = value; reg 92 sound/pci/oxygen/xonar_cs43xx.c static void cs4362a_write_cached(struct oxygen *chip, u8 reg, u8 value) reg 96 sound/pci/oxygen/xonar_cs43xx.c if (value != data->cs4362a_regs[reg]) reg 97 sound/pci/oxygen/xonar_cs43xx.c cs4362a_write(chip, reg, value); reg 252 sound/pci/oxygen/xonar_cs43xx.c u8 reg; reg 254 sound/pci/oxygen/xonar_cs43xx.c reg = CS4398_MUTEP_LOW | CS4398_PAMUTE; reg 256 sound/pci/oxygen/xonar_cs43xx.c reg |= CS4398_MUTE_B | CS4398_MUTE_A; reg 257 sound/pci/oxygen/xonar_cs43xx.c cs4398_write_cached(chip, 4, reg); reg 264 sound/pci/oxygen/xonar_cs43xx.c u8 reg; reg 266 sound/pci/oxygen/xonar_cs43xx.c reg = data->cs4362a_regs[9] & ~CS4362A_ATAPI_MASK; reg 268 sound/pci/oxygen/xonar_cs43xx.c reg |= CS4362A_ATAPI_B_LR | CS4362A_ATAPI_A_LR; reg 270 sound/pci/oxygen/xonar_cs43xx.c reg |= CS4362A_ATAPI_B_R | CS4362A_ATAPI_A_L; reg 271 sound/pci/oxygen/xonar_cs43xx.c cs4362a_write_cached(chip, 9, reg); reg 310 sound/pci/oxygen/xonar_cs43xx.c u8 reg; reg 313 sound/pci/oxygen/xonar_cs43xx.c reg = data->cs4398_regs[7]; reg 315 sound/pci/oxygen/xonar_cs43xx.c reg |= CS4398_FILT_SEL; reg 317 sound/pci/oxygen/xonar_cs43xx.c reg &= ~CS4398_FILT_SEL; reg 318 sound/pci/oxygen/xonar_cs43xx.c changed = reg != data->cs4398_regs[7]; reg 320 sound/pci/oxygen/xonar_cs43xx.c cs4398_write(chip, 7, reg); reg 321 sound/pci/oxygen/xonar_cs43xx.c if (reg & CS4398_FILT_SEL) reg 322 sound/pci/oxygen/xonar_cs43xx.c reg = data->cs4362a_regs[0x04] | CS4362A_FILT_SEL; reg 324 sound/pci/oxygen/xonar_cs43xx.c reg = data->cs4362a_regs[0x04] & ~CS4362A_FILT_SEL; reg 325 sound/pci/oxygen/xonar_cs43xx.c cs4362a_write(chip, 0x04, reg); reg 340 sound/pci/oxygen/xonar_cs43xx.c unsigned int reg, unsigned int mute) reg 342 sound/pci/oxygen/xonar_cs43xx.c if (reg == AC97_LINE) { reg 57 sound/pci/oxygen/xonar_dg.c int cs4245_write_spi(struct oxygen *chip, u8 reg) reg 62 sound/pci/oxygen/xonar_dg.c packet = reg << 8; reg 64 sound/pci/oxygen/xonar_dg.c packet |= data->cs4245_shadow[reg]; reg 39 sound/pci/oxygen/xonar_dg.h int cs4245_write_spi(struct oxygen *chip, u8 reg); reg 40 sound/pci/oxygen/xonar_dg.h int cs4245_read_spi(struct oxygen *chip, u8 reg); reg 341 sound/pci/oxygen/xonar_dg_mixer.c u8 reg; reg 345 sound/pci/oxygen/xonar_dg_mixer.c reg = data->cs4245_shadow[CS4245_ADC_CTRL] & ~CS4245_HPF_FREEZE; reg 347 sound/pci/oxygen/xonar_dg_mixer.c reg |= CS4245_HPF_FREEZE; reg 348 sound/pci/oxygen/xonar_dg_mixer.c changed = reg != data->cs4245_shadow[CS4245_ADC_CTRL]; reg 350 sound/pci/oxygen/xonar_dg_mixer.c data->cs4245_shadow[CS4245_ADC_CTRL] = reg; reg 233 sound/pci/oxygen/xonar_pcm179x.c u8 reg, u8 value) reg 244 sound/pci/oxygen/xonar_pcm179x.c (reg << 8) | value); reg 248 sound/pci/oxygen/xonar_pcm179x.c u8 reg, u8 value) reg 250 sound/pci/oxygen/xonar_pcm179x.c oxygen_write_i2c(chip, I2C_DEVICE_PCM1796(codec), reg, value); reg 254 sound/pci/oxygen/xonar_pcm179x.c u8 reg, u8 value) reg 260 sound/pci/oxygen/xonar_pcm179x.c pcm1796_write_spi(chip, codec, reg, value); reg 262 sound/pci/oxygen/xonar_pcm179x.c pcm1796_write_i2c(chip, codec, reg, value); reg 263 sound/pci/oxygen/xonar_pcm179x.c if ((unsigned int)(reg - PCM1796_REG_BASE) reg 265 sound/pci/oxygen/xonar_pcm179x.c data->pcm1796_regs[codec][reg - PCM1796_REG_BASE] = value; reg 269 sound/pci/oxygen/xonar_pcm179x.c u8 reg, u8 value) reg 273 sound/pci/oxygen/xonar_pcm179x.c if (value != data->pcm1796_regs[codec][reg - PCM1796_REG_BASE]) reg 274 sound/pci/oxygen/xonar_pcm179x.c pcm1796_write(chip, codec, reg, value); reg 277 sound/pci/oxygen/xonar_pcm179x.c static void cs2000_write(struct oxygen *chip, u8 reg, u8 value) reg 281 sound/pci/oxygen/xonar_pcm179x.c oxygen_write_i2c(chip, I2C_DEVICE_CS2000, reg, value); reg 282 sound/pci/oxygen/xonar_pcm179x.c data->cs2000_regs[reg] = value; reg 285 sound/pci/oxygen/xonar_pcm179x.c static void cs2000_write_cached(struct oxygen *chip, u8 reg, u8 value) reg 289 sound/pci/oxygen/xonar_pcm179x.c if (value != data->cs2000_regs[reg]) reg 290 sound/pci/oxygen/xonar_pcm179x.c cs2000_write(chip, reg, value); reg 603 sound/pci/oxygen/xonar_pcm179x.c u8 reg; reg 606 sound/pci/oxygen/xonar_pcm179x.c reg = PCM1796_OS_128; reg 608 sound/pci/oxygen/xonar_pcm179x.c reg = PCM1796_OS_64; reg 610 sound/pci/oxygen/xonar_pcm179x.c pcm1796_write_cached(chip, i, 20, reg); reg 617 sound/pci/oxygen/xonar_pcm179x.c u8 reg; reg 619 sound/pci/oxygen/xonar_pcm179x.c reg = data->pcm1796_regs[0][18 - PCM1796_REG_BASE] & ~PCM1796_DMF_MASK; reg 621 sound/pci/oxygen/xonar_pcm179x.c reg |= PCM1796_DMF_48; reg 623 sound/pci/oxygen/xonar_pcm179x.c reg |= PCM1796_DMF_441; reg 625 sound/pci/oxygen/xonar_pcm179x.c reg |= PCM1796_DMF_32; reg 627 sound/pci/oxygen/xonar_pcm179x.c pcm1796_write_cached(chip, i, 18, reg); reg 675 sound/pci/oxygen/xonar_pcm179x.c u8 rate_mclk, reg; reg 697 sound/pci/oxygen/xonar_pcm179x.c reg = CS2000_REF_CLK_DIV_1; reg 700 sound/pci/oxygen/xonar_pcm179x.c reg = CS2000_REF_CLK_DIV_2; reg 705 sound/pci/oxygen/xonar_pcm179x.c cs2000_write_cached(chip, CS2000_FUN_CFG_1, reg); reg 763 sound/pci/oxygen/xonar_pcm179x.c u8 reg; reg 766 sound/pci/oxygen/xonar_pcm179x.c reg = data->pcm1796_regs[0][19 - PCM1796_REG_BASE]; reg 767 sound/pci/oxygen/xonar_pcm179x.c reg &= ~PCM1796_FLT_MASK; reg 769 sound/pci/oxygen/xonar_pcm179x.c reg |= PCM1796_FLT_SHARP; reg 771 sound/pci/oxygen/xonar_pcm179x.c reg |= PCM1796_FLT_SLOW; reg 772 sound/pci/oxygen/xonar_pcm179x.c changed = reg != data->pcm1796_regs[0][19 - PCM1796_REG_BASE]; reg 775 sound/pci/oxygen/xonar_pcm179x.c pcm1796_write(chip, i, 19, reg); reg 807 sound/pci/oxygen/xonar_pcm179x.c u8 reg; reg 810 sound/pci/oxygen/xonar_pcm179x.c reg = data->pcm1796_regs[0][18 - PCM1796_REG_BASE]; reg 812 sound/pci/oxygen/xonar_pcm179x.c reg &= ~PCM1796_DME; reg 814 sound/pci/oxygen/xonar_pcm179x.c reg |= PCM1796_DME; reg 815 sound/pci/oxygen/xonar_pcm179x.c changed = reg != data->pcm1796_regs[0][18 - PCM1796_REG_BASE]; reg 818 sound/pci/oxygen/xonar_pcm179x.c pcm1796_write(chip, i, 18, reg); reg 1027 sound/pci/oxygen/xonar_pcm179x.c unsigned int reg, unsigned int mute) reg 1029 sound/pci/oxygen/xonar_pcm179x.c if (reg == AC97_LINE) { reg 91 sound/pci/oxygen/xonar_wm87x6.c unsigned int reg, unsigned int value) reg 98 sound/pci/oxygen/xonar_wm87x6.c (reg << 9) | value); reg 102 sound/pci/oxygen/xonar_wm87x6.c unsigned int reg, unsigned int value) reg 105 sound/pci/oxygen/xonar_wm87x6.c (reg << 1) | (value >> 8), value); reg 109 sound/pci/oxygen/xonar_wm87x6.c unsigned int reg, unsigned int value) reg 115 sound/pci/oxygen/xonar_wm87x6.c wm8776_write_spi(chip, reg, value); reg 117 sound/pci/oxygen/xonar_wm87x6.c wm8776_write_i2c(chip, reg, value); reg 118 sound/pci/oxygen/xonar_wm87x6.c if (reg < ARRAY_SIZE(data->wm8776_regs)) { reg 119 sound/pci/oxygen/xonar_wm87x6.c if (reg >= WM8776_HPLVOL && reg <= WM8776_DACMASTER) reg 121 sound/pci/oxygen/xonar_wm87x6.c data->wm8776_regs[reg] = value; reg 126 sound/pci/oxygen/xonar_wm87x6.c unsigned int reg, unsigned int value) reg 130 sound/pci/oxygen/xonar_wm87x6.c if (reg >= ARRAY_SIZE(data->wm8776_regs) || reg 131 sound/pci/oxygen/xonar_wm87x6.c value != data->wm8776_regs[reg]) reg 132 sound/pci/oxygen/xonar_wm87x6.c wm8776_write(chip, reg, value); reg 136 sound/pci/oxygen/xonar_wm87x6.c unsigned int reg, unsigned int value) reg 145 sound/pci/oxygen/xonar_wm87x6.c (reg << 9) | value); reg 146 sound/pci/oxygen/xonar_wm87x6.c if (reg < ARRAY_SIZE(data->wm8766_regs)) { reg 147 sound/pci/oxygen/xonar_wm87x6.c if ((reg >= WM8766_LDA1 && reg <= WM8766_RDA1) || reg 148 sound/pci/oxygen/xonar_wm87x6.c (reg >= WM8766_LDA2 && reg <= WM8766_MASTDA)) reg 150 sound/pci/oxygen/xonar_wm87x6.c data->wm8766_regs[reg] = value; reg 155 sound/pci/oxygen/xonar_wm87x6.c unsigned int reg, unsigned int value) reg 159 sound/pci/oxygen/xonar_wm87x6.c if (reg >= ARRAY_SIZE(data->wm8766_regs) || reg 160 sound/pci/oxygen/xonar_wm87x6.c value != data->wm8766_regs[reg]) reg 161 sound/pci/oxygen/xonar_wm87x6.c wm8766_write(chip, reg, value); reg 236 sound/pci/oxygen/xonar_wm87x6.c unsigned int reg; reg 247 sound/pci/oxygen/xonar_wm87x6.c reg = data->wm8766_regs[WM8766_DAC_CTRL] & ~WM8766_MUTEALL; reg 249 sound/pci/oxygen/xonar_wm87x6.c reg |= WM8766_MUTEALL; reg 250 sound/pci/oxygen/xonar_wm87x6.c wm8766_write_cached(chip, WM8766_DAC_CTRL, reg); reg 375 sound/pci/oxygen/xonar_wm87x6.c u16 reg; reg 377 sound/pci/oxygen/xonar_wm87x6.c reg = WM8776_ADCRATE_256 | WM8776_DACRATE_256; reg 379 sound/pci/oxygen/xonar_wm87x6.c reg |= WM8776_ADCOSR; reg 380 sound/pci/oxygen/xonar_wm87x6.c wm8776_write_cached(chip, WM8776_MSTRCTRL, reg); reg 477 sound/pci/oxygen/xonar_wm87x6.c unsigned int reg; reg 483 sound/pci/oxygen/xonar_wm87x6.c reg = data->wm8766_regs[WM8766_DAC_CTRL] & reg 486 sound/pci/oxygen/xonar_wm87x6.c reg |= WM8766_PL_LEFT_LRMIX | WM8766_PL_RIGHT_LRMIX; reg 488 sound/pci/oxygen/xonar_wm87x6.c reg |= WM8766_PL_LEFT_LEFT | WM8766_PL_RIGHT_RIGHT; reg 489 sound/pci/oxygen/xonar_wm87x6.c wm8766_write_cached(chip, WM8766_DAC_CTRL, reg); reg 768 sound/pci/oxygen/xonar_wm87x6.c u16 reg; reg 772 sound/pci/oxygen/xonar_wm87x6.c reg = data->wm8776_regs[WM8776_ADCMUX]; reg 774 sound/pci/oxygen/xonar_wm87x6.c reg |= mux_bit; reg 777 sound/pci/oxygen/xonar_wm87x6.c if (reg & mux_bit) { reg 778 sound/pci/oxygen/xonar_wm87x6.c reg &= ~mux_bit; reg 787 sound/pci/oxygen/xonar_wm87x6.c reg &= ~mux_bit; reg 788 sound/pci/oxygen/xonar_wm87x6.c changed = reg != data->wm8776_regs[WM8776_ADCMUX]; reg 791 sound/pci/oxygen/xonar_wm87x6.c reg & 1 ? GPIO_DS_INPUT_ROUTE : 0, reg 793 sound/pci/oxygen/xonar_wm87x6.c wm8776_write(chip, WM8776_ADCMUX, reg); reg 954 sound/pci/oxygen/xonar_wm87x6.c unsigned int reg; reg 958 sound/pci/oxygen/xonar_wm87x6.c reg = data->wm8776_regs[WM8776_ADCIFCTRL] & ~WM8776_ADCHPD; reg 960 sound/pci/oxygen/xonar_wm87x6.c reg |= WM8776_ADCHPD; reg 961 sound/pci/oxygen/xonar_wm87x6.c changed = reg != data->wm8776_regs[WM8776_ADCIFCTRL]; reg 963 sound/pci/oxygen/xonar_wm87x6.c wm8776_write(chip, WM8776_ADCIFCTRL, reg); reg 968 sound/pci/oxygen/xonar_wm87x6.c #define WM8776_BIT_SWITCH(xname, reg, bit, invert, flags) { \ reg 974 sound/pci/oxygen/xonar_wm87x6.c .private_value = ((reg) << 16) | (bit) | ((invert) << 24) | (flags), \ reg 976 sound/pci/oxygen/xonar_wm87x6.c #define _WM8776_FIELD_CTL(xname, reg, shift, initval, min, max, mask, flags) \ reg 980 sound/pci/oxygen/xonar_wm87x6.c ((mask) << 16) | ((shift) << 20) | ((reg) << 24) | (flags) reg 981 sound/pci/oxygen/xonar_wm87x6.c #define WM8776_FIELD_CTL_ENUM(xname, reg, shift, init, min, max, mask, flags) {\ reg 983 sound/pci/oxygen/xonar_wm87x6.c reg, shift, init, min, max, mask, flags), \ reg 187 sound/pci/pcxhr/pcxhr.c unsigned int reg; reg 191 sound/pci/pcxhr/pcxhr.c reg = (28224000 * 2) / freq; reg 192 sound/pci/pcxhr/pcxhr.c reg = (reg - 1) / 2; reg 193 sound/pci/pcxhr/pcxhr.c if (reg < 0x200) reg 194 sound/pci/pcxhr/pcxhr.c *pllreg = reg + 0x800; reg 195 sound/pci/pcxhr/pcxhr.c else if (reg < 0x400) reg 196 sound/pci/pcxhr/pcxhr.c *pllreg = reg & 0x1ff; reg 197 sound/pci/pcxhr/pcxhr.c else if (reg < 0x800) { reg 198 sound/pci/pcxhr/pcxhr.c *pllreg = ((reg >> 1) & 0x1ff) + 0x200; reg 199 sound/pci/pcxhr/pcxhr.c reg &= ~1; reg 201 sound/pci/pcxhr/pcxhr.c *pllreg = ((reg >> 2) & 0x1ff) + 0x400; reg 202 sound/pci/pcxhr/pcxhr.c reg &= ~3; reg 205 sound/pci/pcxhr/pcxhr.c *realfreq = (28224000 / (reg + 1)); reg 236 sound/pci/pcxhr/pcxhr.c unsigned int *reg, unsigned int *freq) reg 302 sound/pci/pcxhr/pcxhr.c *reg = val; reg 418 sound/pci/pcxhr/pcxhr.c unsigned char reg; reg 423 sound/pci/pcxhr/pcxhr.c reg = REG_STATUS_WORD_CLOCK; reg 426 sound/pci/pcxhr/pcxhr.c reg = REG_STATUS_AES_SYNC; reg 429 sound/pci/pcxhr/pcxhr.c reg = REG_STATUS_AES_1; reg 432 sound/pci/pcxhr/pcxhr.c reg = REG_STATUS_AES_2; reg 435 sound/pci/pcxhr/pcxhr.c reg = REG_STATUS_AES_3; reg 438 sound/pci/pcxhr/pcxhr.c reg = REG_STATUS_AES_4; reg 446 sound/pci/pcxhr/pcxhr.c if (mgr->last_reg_stat != reg) { reg 447 sound/pci/pcxhr/pcxhr.c rmh.cmd[1] = reg; reg 452 sound/pci/pcxhr/pcxhr.c mgr->last_reg_stat = reg; reg 113 sound/pci/pcxhr/pcxhr_core.c static int pcxhr_check_reg_bit(struct pcxhr_mgr *mgr, unsigned int reg, reg 120 sound/pci/pcxhr/pcxhr_core.c *read = PCXHR_INPB(mgr, reg); reg 125 sound/pci/pcxhr/pcxhr_core.c reg, i); reg 132 sound/pci/pcxhr/pcxhr_core.c reg, mask, *read); reg 170 sound/pci/pcxhr/pcxhr_core.c unsigned char reg; reg 179 sound/pci/pcxhr/pcxhr_core.c reg = (PCXHR_ICR_HI08_RREQ | reg 183 sound/pci/pcxhr/pcxhr_core.c reg |= PCXHR_ICR_HI08_HF0; reg 185 sound/pci/pcxhr/pcxhr_core.c reg |= PCXHR_ICR_HI08_HF1; reg 186 sound/pci/pcxhr/pcxhr_core.c PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg); reg 188 sound/pci/pcxhr/pcxhr_core.c reg = (unsigned char)(((itdsp & PCXHR_MASK_EXTRA_INFO) >> 1) | reg 190 sound/pci/pcxhr/pcxhr_core.c PCXHR_OUTPB(mgr, PCXHR_DSP_CVR, reg); reg 205 sound/pci/pcxhr/pcxhr_core.c PCXHR_TIMEOUT_DSP, ®); reg 216 sound/pci/pcxhr/pcxhr_core.c ®); reg 235 sound/pci/pcxhr/pcxhr_core.c unsigned int reg = PCXHR_INPL(mgr, PCXHR_PLX_IRQCS); reg 238 sound/pci/pcxhr/pcxhr_core.c reg |= (PCXHR_IRQCS_ENABLE_PCIIRQ | PCXHR_IRQCS_ENABLE_PCIDB); reg 240 sound/pci/pcxhr/pcxhr_core.c reg &= ~(PCXHR_IRQCS_ENABLE_PCIIRQ | PCXHR_IRQCS_ENABLE_PCIDB); reg 241 sound/pci/pcxhr/pcxhr_core.c PCXHR_OUTPL(mgr, PCXHR_PLX_IRQCS, reg); reg 375 sound/pci/pcxhr/pcxhr_core.c unsigned char reg; reg 378 sound/pci/pcxhr/pcxhr_core.c reg = PCXHR_ICR_HI08_RREQ | PCXHR_ICR_HI08_TREQ | PCXHR_ICR_HI08_HDRQ; reg 383 sound/pci/pcxhr/pcxhr_core.c PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg | PCXHR_ICR_HI08_INIT); reg 385 sound/pci/pcxhr/pcxhr_core.c PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg); reg 390 sound/pci/pcxhr/pcxhr_core.c PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg); reg 397 sound/pci/pcxhr/pcxhr_core.c PCXHR_ISR_HI08_CHK, PCXHR_TIMEOUT_DSP, ®); reg 538 sound/pci/pcxhr/pcxhr_core.c unsigned char reg; reg 550 sound/pci/pcxhr/pcxhr_core.c PCXHR_TIMEOUT_DSP, ®); reg 554 sound/pci/pcxhr/pcxhr_core.c reg, i); reg 600 sound/pci/pcxhr/pcxhr_core.c unsigned char reg; reg 612 sound/pci/pcxhr/pcxhr_core.c PCXHR_ISR_HI08_CHK, PCXHR_TIMEOUT_DSP, ®); reg 621 sound/pci/pcxhr/pcxhr_core.c PCXHR_TIMEOUT_DSP, ®); reg 638 sound/pci/pcxhr/pcxhr_core.c PCXHR_ISR_HI08_TRDY, PCXHR_TIMEOUT_DSP, ®); reg 651 sound/pci/pcxhr/pcxhr_core.c PCXHR_TIMEOUT_DSP, ®); reg 669 sound/pci/pcxhr/pcxhr_core.c PCXHR_TIMEOUT_DSP, ®); reg 679 sound/pci/pcxhr/pcxhr_core.c PCXHR_ISR_HI08_CHK, PCXHR_TIMEOUT_DSP, ®); reg 683 sound/pci/pcxhr/pcxhr_core.c if (reg & PCXHR_ISR_HI08_ERR) { reg 688 sound/pci/pcxhr/pcxhr_core.c PCXHR_TIMEOUT_DSP, ®); reg 691 sound/pci/pcxhr/pcxhr_core.c "ERROR RMH: ISR:RXDF=1 (ISR = %x)\n", reg); reg 1220 sound/pci/pcxhr/pcxhr_core.c unsigned int reg; reg 1223 sound/pci/pcxhr/pcxhr_core.c reg = PCXHR_INPL(mgr, PCXHR_PLX_IRQCS); reg 1224 sound/pci/pcxhr/pcxhr_core.c if (! (reg & PCXHR_IRQCS_ACTIVE_PCIDB)) { reg 1230 sound/pci/pcxhr/pcxhr_core.c reg = PCXHR_INPL(mgr, PCXHR_PLX_L2PCIDB); reg 1231 sound/pci/pcxhr/pcxhr_core.c PCXHR_OUTPL(mgr, PCXHR_PLX_L2PCIDB, reg); reg 1234 sound/pci/pcxhr/pcxhr_core.c if (reg & PCXHR_IRQ_TIMER) { reg 1235 sound/pci/pcxhr/pcxhr_core.c int timer_toggle = reg & PCXHR_IRQ_TIMER; reg 1242 sound/pci/pcxhr/pcxhr_core.c mgr->src_it_dsp = reg; reg 1247 sound/pci/pcxhr/pcxhr_core.c if (reg & PCXHR_IRQ_MASK) { reg 1248 sound/pci/pcxhr/pcxhr_core.c if (reg & PCXHR_IRQ_ASYNC) { reg 1255 sound/pci/pcxhr/pcxhr_core.c mgr->src_it_dsp = reg; reg 1259 sound/pci/pcxhr/pcxhr_core.c if (reg & PCXHR_FATAL_DSP_ERR) reg 1260 sound/pci/pcxhr/pcxhr_core.c dev_dbg(&mgr->pci->dev, "FATAL DSP ERROR : %x\n", reg); reg 273 sound/pci/pcxhr/pcxhr_mix22.c unsigned char reg; reg 278 sound/pci/pcxhr/pcxhr_mix22.c reg = PCXHR_INPB(mgr, PCXHR_XLX_STATUS); reg 279 sound/pci/pcxhr/pcxhr_mix22.c if (reg & PCXHR_STAT_MIC_CAPS) reg 314 sound/pci/pcxhr/pcxhr_mix22.c unsigned int reg; reg 318 sound/pci/pcxhr/pcxhr_mix22.c reg = (28224000 * 2) / freq; reg 319 sound/pci/pcxhr/pcxhr_mix22.c reg = (reg - 1) / 2; reg 320 sound/pci/pcxhr/pcxhr_mix22.c if (reg < 0x100) reg 321 sound/pci/pcxhr/pcxhr_mix22.c *pllreg = reg + 0xC00; reg 322 sound/pci/pcxhr/pcxhr_mix22.c else if (reg < 0x200) reg 323 sound/pci/pcxhr/pcxhr_mix22.c *pllreg = reg + 0x800; reg 324 sound/pci/pcxhr/pcxhr_mix22.c else if (reg < 0x400) reg 325 sound/pci/pcxhr/pcxhr_mix22.c *pllreg = reg & 0x1ff; reg 326 sound/pci/pcxhr/pcxhr_mix22.c else if (reg < 0x800) { reg 327 sound/pci/pcxhr/pcxhr_mix22.c *pllreg = ((reg >> 1) & 0x1ff) + 0x200; reg 328 sound/pci/pcxhr/pcxhr_mix22.c reg &= ~1; reg 330 sound/pci/pcxhr/pcxhr_mix22.c *pllreg = ((reg >> 2) & 0x1ff) + 0x400; reg 331 sound/pci/pcxhr/pcxhr_mix22.c reg &= ~3; reg 334 sound/pci/pcxhr/pcxhr_mix22.c *realfreq = (28224000 / (reg + 1)); reg 408 sound/pci/pcxhr/pcxhr_mix22.c unsigned char mask, reg; reg 414 sound/pci/pcxhr/pcxhr_mix22.c reg = PCXHR_STAT_FREQ_SYNC_MASK; reg 420 sound/pci/pcxhr/pcxhr_mix22.c reg = PCXHR_STAT_FREQ_UER1_MASK; reg 436 sound/pci/pcxhr/pcxhr_mix22.c PCXHR_OUTPB(mgr, PCXHR_XLX_STATUS, reg); /* calculate freq */ reg 439 sound/pci/pcxhr/pcxhr_mix22.c reg |= PCXHR_STAT_FREQ_SAVE_MASK; reg 441 sound/pci/pcxhr/pcxhr_mix22.c if (mgr->last_reg_stat != reg) { reg 443 sound/pci/pcxhr/pcxhr_mix22.c mgr->last_reg_stat = reg; reg 446 sound/pci/pcxhr/pcxhr_mix22.c PCXHR_OUTPB(mgr, PCXHR_XLX_STATUS, reg); /* save */ reg 499 sound/pci/pcxhr/pcxhr_mix22.c unsigned char reg = PCXHR_INPB(mgr, PCXHR_XLX_STATUS); reg 500 sound/pci/pcxhr/pcxhr_mix22.c *value = (int)(reg & PCXHR_STAT_GPI_MASK) >> reg 512 sound/pci/pcxhr/pcxhr_mix22.c unsigned char reg = mgr->dsp_reset & ~PCXHR_DSP_RESET_GPO_MASK; reg 514 sound/pci/pcxhr/pcxhr_mix22.c reg |= (unsigned char)(value << PCXHR_DSP_RESET_GPO_OFFSET) & reg 517 sound/pci/pcxhr/pcxhr_mix22.c PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, reg); reg 518 sound/pci/pcxhr/pcxhr_mix22.c mgr->dsp_reset = reg; reg 574 sound/pci/pcxhr/pcxhr_mixer.c unsigned int mask, reg; reg 586 sound/pci/pcxhr/pcxhr_mixer.c reg = mask; /* audio source from digital plug */ reg 588 sound/pci/pcxhr/pcxhr_mixer.c reg = 0; /* audio source from analog plug */ reg 591 sound/pci/pcxhr/pcxhr_mixer.c pcxhr_write_io_num_reg_cont(chip->mgr, mask, reg, &changed); reg 1727 sound/pci/riptide/riptide.c snd_riptide_codec_write(struct snd_ac97 *ac97, unsigned short reg, reg 1738 sound/pci/riptide/riptide.c snd_printdd("Write AC97 reg 0x%x 0x%x\n", reg, val); reg 1740 sound/pci/riptide/riptide.c SEND_SACR(cif, val, reg); reg 1741 sound/pci/riptide/riptide.c SEND_RACR(cif, reg, &rptr); reg 1748 sound/pci/riptide/riptide.c unsigned short reg) reg 1757 sound/pci/riptide/riptide.c if (SEND_RACR(cif, reg, &rptr) != 0) reg 1758 sound/pci/riptide/riptide.c SEND_RACR(cif, reg, &rptr); reg 1759 sound/pci/riptide/riptide.c snd_printdd("Read AC97 reg 0x%x got 0x%x\n", reg, rptr.retwords[1]); reg 646 sound/pci/rme9652/hdsp.c static void hdsp_write(struct hdsp *hdsp, int reg, int val) reg 648 sound/pci/rme9652/hdsp.c writel(val, hdsp->iobase + reg); reg 651 sound/pci/rme9652/hdsp.c static unsigned int hdsp_read(struct hdsp *hdsp, int reg) reg 653 sound/pci/rme9652/hdsp.c return readl (hdsp->iobase + reg); reg 1099 sound/pci/rme9652/hdspm.c unsigned int reg, int channels); reg 1131 sound/pci/rme9652/hdspm.c static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, reg 1134 sound/pci/rme9652/hdspm.c writel(val, hdspm->iobase + reg); reg 1137 sound/pci/rme9652/hdspm.c static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) reg 1139 sound/pci/rme9652/hdspm.c return readl(hdspm->iobase + reg); reg 3200 sound/pci/rme9652/hdspm.c u32 reg; reg 3203 sound/pci/rme9652/hdspm.c reg = hdspm->settings_register; reg 3205 sound/pci/rme9652/hdspm.c reg = hdspm->control_register; reg 3207 sound/pci/rme9652/hdspm.c return (reg & regmask) ? 1 : 0; reg 3212 sound/pci/rme9652/hdspm.c u32 *reg; reg 3216 sound/pci/rme9652/hdspm.c reg = &(hdspm->settings_register); reg 3219 sound/pci/rme9652/hdspm.c reg = &(hdspm->control_register); reg 3224 sound/pci/rme9652/hdspm.c *reg |= regmask; reg 3226 sound/pci/rme9652/hdspm.c *reg &= ~regmask; reg 3228 sound/pci/rme9652/hdspm.c hdspm_write(hdspm, target_reg, *reg); reg 3476 sound/pci/rme9652/hdspm.c u32 reg = hdspm->settings_register & (regmask * 3); reg 3477 sound/pci/rme9652/hdspm.c return reg / regmask; reg 6420 sound/pci/rme9652/hdspm.c unsigned int reg, int channel) reg 6425 sound/pci/rme9652/hdspm.c hdspm_write(hdspm, reg + 4 * i, reg 309 sound/pci/rme9652/rme9652.c static inline void rme9652_write(struct snd_rme9652 *rme9652, int reg, int val) reg 311 sound/pci/rme9652/rme9652.c writel(val, rme9652->iobase + reg); reg 314 sound/pci/rme9652/rme9652.c static inline unsigned int rme9652_read(struct snd_rme9652 *rme9652, int reg) reg 316 sound/pci/rme9652/rme9652.c return readl(rme9652->iobase + reg); reg 520 sound/pci/sis7019.c u32 format, dma_addr, control, sso_eso, delta, reg; reg 564 sound/pci/sis7019.c for (reg = 0; reg < SIS_WAVE_SIZE; reg += 4) reg 565 sound/pci/sis7019.c writel(0, wave_base + reg); reg 725 sound/pci/sis7019.c u32 vperiod, sso, reg; reg 807 sound/pci/sis7019.c for (reg = 0; reg < SIS_WAVE_SIZE; reg += 4) reg 808 sound/pci/sis7019.c writel(0, wave_base + reg); reg 981 sound/pci/sis7019.c static void sis_ac97_write(struct snd_ac97 *ac97, unsigned short reg, reg 990 sound/pci/sis7019.c (val << 16) | (reg << 8) | cmd[ac97->num]); reg 993 sound/pci/sis7019.c static unsigned short sis_ac97_read(struct snd_ac97 *ac97, unsigned short reg) reg 1001 sound/pci/sis7019.c (reg << 8) | cmd[ac97->num]); reg 294 sound/pci/sonicvibes.c unsigned char reg, reg 297 sound/pci/sonicvibes.c outb(reg, SV_REG(sonic, INDEX)); reg 304 sound/pci/sonicvibes.c unsigned char reg, reg 310 sound/pci/sonicvibes.c outb(reg, SV_REG(sonic, INDEX)); reg 317 sound/pci/sonicvibes.c static unsigned char snd_sonicvibes_in1(struct sonicvibes * sonic, unsigned char reg) reg 321 sound/pci/sonicvibes.c outb(reg, SV_REG(sonic, INDEX)); reg 328 sound/pci/sonicvibes.c static unsigned char snd_sonicvibes_in(struct sonicvibes * sonic, unsigned char reg) reg 334 sound/pci/sonicvibes.c outb(reg, SV_REG(sonic, INDEX)); reg 502 sound/pci/sonicvibes.c "pll: m = 0x%x, r = 0x%x, n = 0x%x\n", reg, m, r, n); reg 507 sound/pci/sonicvibes.c unsigned char reg, reg 516 sound/pci/sonicvibes.c snd_sonicvibes_out1(sonic, reg, m); reg 517 sound/pci/sonicvibes.c snd_sonicvibes_out1(sonic, reg + 1, r | n); reg 944 sound/pci/sonicvibes.c #define SONICVIBES_SINGLE(xname, xindex, reg, shift, mask, invert) \ reg 948 sound/pci/sonicvibes.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } reg 964 sound/pci/sonicvibes.c int reg = kcontrol->private_value & 0xff; reg 970 sound/pci/sonicvibes.c ucontrol->value.integer.value[0] = (snd_sonicvibes_in1(sonic, reg)>> shift) & mask; reg 980 sound/pci/sonicvibes.c int reg = kcontrol->private_value & 0xff; reg 992 sound/pci/sonicvibes.c oval = snd_sonicvibes_in1(sonic, reg); reg 995 sound/pci/sonicvibes.c snd_sonicvibes_out1(sonic, reg, val); reg 106 sound/pci/trident/trident_main.c static unsigned short snd_trident_codec_read(struct snd_ac97 *ac97, unsigned short reg) reg 115 sound/pci/trident/trident_main.c data = (DX_AC97_BUSY_READ | (reg & 0x000000ff)); reg 123 sound/pci/trident/trident_main.c data = (NX_AC97_BUSY_READ | (reg & 0x000000ff)); reg 132 sound/pci/trident/trident_main.c data = SI_AC97_BUSY_READ | SI_AC97_AUDIO_BUSY | (reg & 0x000000ff); reg 146 sound/pci/trident/trident_main.c reg, data); reg 168 sound/pci/trident/trident_main.c static void snd_trident_codec_write(struct snd_ac97 *ac97, unsigned short reg, reg 188 sound/pci/trident/trident_main.c data |= (DX_AC97_BUSY_WRITE | (reg & 0x000000ff)); reg 198 sound/pci/trident/trident_main.c data |= (NX_AC97_BUSY_WRITE | (ac97->num << 8) | (reg & 0x000000ff)); reg 208 sound/pci/trident/trident_main.c data |= SI_AC97_BUSY_WRITE | SI_AC97_AUDIO_BUSY | (reg & 0x000000ff); reg 290 sound/pci/trident/trident_main.c unsigned int reg = (voice & 0x20) ? T4D_START_B : T4D_START_A; reg 292 sound/pci/trident/trident_main.c outl(mask, TRID_REG(trident, reg)); reg 314 sound/pci/trident/trident_main.c unsigned int reg = (voice & 0x20) ? T4D_STOP_B : T4D_STOP_A; reg 316 sound/pci/trident/trident_main.c outl(mask, TRID_REG(trident, reg)); reg 553 sound/pci/via82xx.c unsigned short reg, reg 561 sound/pci/via82xx.c xval |= reg << VIA_REG_AC97_CMD_SHIFT; reg 567 sound/pci/via82xx.c static unsigned short snd_via82xx_codec_read(struct snd_ac97 *ac97, unsigned short reg) reg 576 sound/pci/via82xx.c xval |= (reg & 0x7f) << VIA_REG_AC97_CMD_SHIFT; reg 406 sound/pci/via82xx_modem.c unsigned short reg, reg 411 sound/pci/via82xx_modem.c if(reg == AC97_GPIO_STATUS) { reg 417 sound/pci/via82xx_modem.c xval |= reg << VIA_REG_AC97_CMD_SHIFT; reg 423 sound/pci/via82xx_modem.c static unsigned short snd_via82xx_codec_read(struct snd_ac97 *ac97, unsigned short reg) reg 432 sound/pci/via82xx_modem.c xval |= (reg & 0x7f) << VIA_REG_AC97_CMD_SHIFT; reg 74 sound/pci/vx222/vx222_ops.c static inline unsigned long vx2_reg_addr(struct vx_core *_chip, int reg) reg 77 sound/pci/vx222/vx222_ops.c return chip->port[vx2_reg_index[reg]] + vx2_reg_offset[reg]; reg 132 sound/pci/vx222/vx222_ops.c #define vx_inb(chip,reg) vx2_inb((struct vx_core*)(chip), VX_##reg) reg 134 sound/pci/vx222/vx222_ops.c #define vx_outb(chip,reg,val) vx2_outb((struct vx_core*)(chip), VX_##reg, val) reg 136 sound/pci/vx222/vx222_ops.c #define vx_inl(chip,reg) vx2_inl((struct vx_core*)(chip), VX_##reg) reg 138 sound/pci/vx222/vx222_ops.c #define vx_outl(chip,reg,val) vx2_outl((struct vx_core*)(chip), VX_##reg, val) reg 664 sound/pci/vx222/vx222_ops.c static void vx2_write_akm(struct vx_core *chip, int reg, unsigned int data) reg 668 sound/pci/vx222/vx222_ops.c if (reg == XX_CODEC_DAC_CONTROL_REGISTER) { reg 680 sound/pci/vx222/vx222_ops.c switch (reg) { reg 20 sound/pci/ymfpci/ymfpci.h #define YMFREG(chip, reg) (chip->port + YDSXGR_##reg) reg 67 sound/pci/ymfpci/ymfpci_main.c u32 reg = secondary ? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR; reg 71 sound/pci/ymfpci/ymfpci_main.c if ((snd_ymfpci_readw(chip, reg) & 0x8000) == 0) reg 77 sound/pci/ymfpci/ymfpci_main.c secondary, snd_ymfpci_readw(chip, reg)); reg 81 sound/pci/ymfpci/ymfpci_main.c static void snd_ymfpci_codec_write(struct snd_ac97 *ac97, u16 reg, u16 val) reg 87 sound/pci/ymfpci/ymfpci_main.c cmd = ((YDSXG_AC97WRITECMD | reg) << 16) | val; reg 91 sound/pci/ymfpci/ymfpci_main.c static u16 snd_ymfpci_codec_read(struct snd_ac97 *ac97, u16 reg) reg 97 sound/pci/ymfpci/ymfpci_main.c snd_ymfpci_writew(chip, YDSXGR_AC97CMDADR, YDSXG_AC97READCMD | reg); reg 1400 sound/pci/ymfpci/ymfpci_main.c u16 reg; reg 1403 sound/pci/ymfpci/ymfpci_main.c reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL); reg 1405 sound/pci/ymfpci/ymfpci_main.c if (!(reg & 0x100)) reg 1408 sound/pci/ymfpci/ymfpci_main.c value->value.enumerated.item[0] = 1 + ((reg & 0x200) != 0); reg 1415 sound/pci/ymfpci/ymfpci_main.c u16 reg, old_reg; reg 1420 sound/pci/ymfpci/ymfpci_main.c reg = old_reg & ~0x100; reg 1422 sound/pci/ymfpci/ymfpci_main.c reg = (old_reg & ~0x300) | 0x100 | ((value->value.enumerated.item[0] == 2) << 9); reg 1423 sound/pci/ymfpci/ymfpci_main.c snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, reg); reg 1425 sound/pci/ymfpci/ymfpci_main.c return reg != old_reg; reg 1441 sound/pci/ymfpci/ymfpci_main.c #define YMFPCI_SINGLE(xname, xindex, reg, shift) \ reg 1445 sound/pci/ymfpci/ymfpci_main.c .private_value = ((reg) | ((shift) << 16)) } reg 1453 sound/pci/ymfpci/ymfpci_main.c int reg = kcontrol->private_value & 0xffff; reg 1457 sound/pci/ymfpci/ymfpci_main.c switch (reg) { reg 1463 sound/pci/ymfpci/ymfpci_main.c (snd_ymfpci_readl(chip, reg) >> shift) & mask; reg 1471 sound/pci/ymfpci/ymfpci_main.c int reg = kcontrol->private_value & 0xffff; reg 1477 sound/pci/ymfpci/ymfpci_main.c switch (reg) { reg 1485 sound/pci/ymfpci/ymfpci_main.c oval = snd_ymfpci_readl(chip, reg); reg 1488 sound/pci/ymfpci/ymfpci_main.c snd_ymfpci_writel(chip, reg, val); reg 1495 sound/pci/ymfpci/ymfpci_main.c #define YMFPCI_DOUBLE(xname, xindex, reg) \ reg 1500 sound/pci/ymfpci/ymfpci_main.c .private_value = reg, \ reg 1505 sound/pci/ymfpci/ymfpci_main.c unsigned int reg = kcontrol->private_value; reg 1507 sound/pci/ymfpci/ymfpci_main.c if (reg < 0x80 || reg >= 0xc0) reg 1519 sound/pci/ymfpci/ymfpci_main.c unsigned int reg = kcontrol->private_value; reg 1523 sound/pci/ymfpci/ymfpci_main.c if (reg < 0x80 || reg >= 0xc0) reg 1526 sound/pci/ymfpci/ymfpci_main.c val = snd_ymfpci_readl(chip, reg); reg 1536 sound/pci/ymfpci/ymfpci_main.c unsigned int reg = kcontrol->private_value; reg 1541 sound/pci/ymfpci/ymfpci_main.c if (reg < 0x80 || reg >= 0xc0) reg 1548 sound/pci/ymfpci/ymfpci_main.c oval = snd_ymfpci_readl(chip, reg); reg 1551 sound/pci/ymfpci/ymfpci_main.c snd_ymfpci_writel(chip, reg, val1); reg 1560 sound/pci/ymfpci/ymfpci_main.c unsigned int reg = YDSXGR_NATIVEDACOUTVOL; reg 1568 sound/pci/ymfpci/ymfpci_main.c oval = snd_ymfpci_readl(chip, reg); reg 1570 sound/pci/ymfpci/ymfpci_main.c snd_ymfpci_writel(chip, reg, value); reg 1643 sound/pci/ymfpci/ymfpci_main.c u16 reg, mode; reg 1647 sound/pci/ymfpci/ymfpci_main.c reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE); reg 1648 sound/pci/ymfpci/ymfpci_main.c reg &= ~(1 << (pin + 8)); reg 1649 sound/pci/ymfpci/ymfpci_main.c reg |= (1 << pin); reg 1650 sound/pci/ymfpci/ymfpci_main.c snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg); reg 1655 sound/pci/ymfpci/ymfpci_main.c snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8))); reg 1663 sound/pci/ymfpci/ymfpci_main.c u16 reg; reg 1667 sound/pci/ymfpci/ymfpci_main.c reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE); reg 1668 sound/pci/ymfpci/ymfpci_main.c reg &= ~(1 << pin); reg 1669 sound/pci/ymfpci/ymfpci_main.c reg &= ~(1 << (pin + 8)); reg 1670 sound/pci/ymfpci/ymfpci_main.c snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg); reg 1672 sound/pci/ymfpci/ymfpci_main.c snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8))); reg 2094 sound/pci/ymfpci/ymfpci_main.c int voice, bank, reg; reg 2177 sound/pci/ymfpci/ymfpci_main.c for (reg = 0x80; reg < 0xc0; reg += 4) reg 2178 sound/pci/ymfpci/ymfpci_main.c snd_ymfpci_writel(chip, reg, 0); reg 106 sound/pcmcia/pdaudiocf/pdaudiocf.h static inline void pdacf_reg_write(struct snd_pdacf *chip, unsigned char reg, unsigned short val) reg 108 sound/pcmcia/pdaudiocf/pdaudiocf.h outw(chip->regmap[reg>>1] = val, chip->port + reg); reg 111 sound/pcmcia/pdaudiocf/pdaudiocf.h static inline unsigned short pdacf_reg_read(struct snd_pdacf *chip, unsigned char reg) reg 113 sound/pcmcia/pdaudiocf/pdaudiocf.h return inw(chip->port + reg); reg 18 sound/pcmcia/pdaudiocf/pdaudiocf_core.c static unsigned char pdacf_ak4117_read(void *private_data, unsigned char reg) reg 35 sound/pcmcia/pdaudiocf/pdaudiocf_core.c pdacf_reg_write(chip, PDAUDIOCF_REG_AK_IFR, (u16)reg << 8); reg 50 sound/pcmcia/pdaudiocf/pdaudiocf_core.c static void pdacf_ak4117_write(void *private_data, unsigned char reg, unsigned char val) reg 66 sound/pcmcia/pdaudiocf/pdaudiocf_core.c outw((u16)reg << 8 | val | (1<<13), chip->port + PDAUDIOCF_REG_AK_IFR); reg 38 sound/pcmcia/vx/vxp_ops.c static inline unsigned long vxp_reg_addr(struct vx_core *_chip, int reg) reg 41 sound/pcmcia/vx/vxp_ops.c return chip->port + vxp_reg_offset[reg]; reg 67 sound/pcmcia/vx/vxp_ops.c #define vx_inb(chip,reg) vxp_inb((struct vx_core *)(chip), VX_##reg) reg 69 sound/pcmcia/vx/vxp_ops.c #define vx_outb(chip,reg,val) vxp_outb((struct vx_core *)(chip), VX_##reg,val) reg 67 sound/ppc/awacs.c snd_pmac_awacs_write_reg(struct snd_pmac *chip, int reg, int val) reg 69 sound/ppc/awacs.c snd_pmac_awacs_write(chip, val | (reg << 12)); reg 70 sound/ppc/awacs.c chip->awacs_reg[reg] = val; reg 74 sound/ppc/awacs.c snd_pmac_awacs_write_noreg(struct snd_pmac *chip, int reg, int val) reg 76 sound/ppc/awacs.c snd_pmac_awacs_write(chip, val | (reg << 12)); reg 136 sound/ppc/awacs.c int reg = kcontrol->private_value & 0xff; reg 143 sound/ppc/awacs.c vol[0] = (chip->awacs_reg[reg] >> lshift) & 0xf; reg 144 sound/ppc/awacs.c vol[1] = chip->awacs_reg[reg] & 0xf; reg 159 sound/ppc/awacs.c int reg = kcontrol->private_value & 0xff; reg 177 sound/ppc/awacs.c oldval = chip->awacs_reg[reg]; reg 182 sound/ppc/awacs.c snd_pmac_awacs_write_reg(chip, reg, val); reg 184 sound/ppc/awacs.c return oldval != reg; reg 202 sound/ppc/awacs.c int reg = kcontrol->private_value & 0xff; reg 209 sound/ppc/awacs.c val = (chip->awacs_reg[reg] >> shift) & 1; reg 221 sound/ppc/awacs.c int reg = kcontrol->private_value & 0xff; reg 229 sound/ppc/awacs.c val = chip->awacs_reg[reg] & ~mask; reg 232 sound/ppc/awacs.c changed = chip->awacs_reg[reg] != val; reg 234 sound/ppc/awacs.c snd_pmac_awacs_write_reg(chip, reg, val); reg 254 sound/ppc/awacs.c static void awacs_set_cuda(int reg, int val) reg 258 sound/ppc/awacs.c reg, val); reg 825 sound/ppc/awacs.c int reg = chip->awacs_reg[1] reg 828 sound/ppc/awacs.c reg &= ~MASK_SPKMUTE; reg 829 sound/ppc/awacs.c reg |= MASK_PAROUT1; reg 831 sound/ppc/awacs.c reg &= ~MASK_SPKMUTE; reg 832 sound/ppc/awacs.c reg &= ~MASK_PAROUT1; reg 835 sound/ppc/awacs.c reg &= ~MASK_HDMUTE; reg 837 sound/ppc/awacs.c reg &= ~MASK_PAROUT1; reg 839 sound/ppc/awacs.c reg |= MASK_PAROUT1; reg 841 sound/ppc/awacs.c reg &= ~MASK_SPKMUTE; reg 842 sound/ppc/awacs.c if (do_notify && reg == chip->awacs_reg[1]) reg 844 sound/ppc/awacs.c snd_pmac_awacs_write_reg(chip, 1, reg); reg 572 sound/ppc/burgundy.c int reg, oreg; reg 573 sound/ppc/burgundy.c reg = oreg = snd_pmac_burgundy_rcb(chip, reg 575 sound/ppc/burgundy.c reg &= imac ? ~(BURGUNDY_OUTPUT_LEFT | BURGUNDY_OUTPUT_RIGHT reg 580 sound/ppc/burgundy.c reg |= imac ? (BURGUNDY_HP_LEFT | BURGUNDY_HP_RIGHT) reg 584 sound/ppc/burgundy.c reg |= imac ? (BURGUNDY_OUTPUT_LEFT reg 587 sound/ppc/burgundy.c if (do_notify && reg == oreg) reg 590 sound/ppc/burgundy.c MASK_ADDR_BURGUNDY_MORE_OUTPUTENABLES, reg); reg 57 sound/ppc/snd_ps3.c static inline u32 read_reg(unsigned int reg) reg 59 sound/ppc/snd_ps3.c return in_be32(the_card.mapped_mmio_vaddr + reg); reg 61 sound/ppc/snd_ps3.c static inline void write_reg(unsigned int reg, u32 val) reg 63 sound/ppc/snd_ps3.c out_be32(the_card.mapped_mmio_vaddr + reg, val); reg 65 sound/ppc/snd_ps3.c static inline void update_reg(unsigned int reg, u32 or_val) reg 67 sound/ppc/snd_ps3.c u32 newval = read_reg(reg) | or_val; reg 68 sound/ppc/snd_ps3.c write_reg(reg, newval); reg 70 sound/ppc/snd_ps3.c static inline void update_mask_reg(unsigned int reg, u32 mask, u32 or_val) reg 72 sound/ppc/snd_ps3.c u32 newval = (read_reg(reg) & mask) | or_val; reg 73 sound/ppc/snd_ps3.c write_reg(reg, newval); reg 478 sound/ppc/tumbler.c int reg; reg 500 sound/ppc/tumbler.c if (i2c_smbus_write_i2c_block_data(mix->i2c.client, info->reg, reg 558 sound/ppc/tumbler.c .reg = TAS_REG_PCM, reg 566 sound/ppc/tumbler.c .reg = TAS_REG_BASS, reg 574 sound/ppc/tumbler.c .reg = TAS_REG_TREBLE, reg 583 sound/ppc/tumbler.c .reg = TAS_REG_BASS, reg 591 sound/ppc/tumbler.c .reg = TAS_REG_TREBLE, reg 621 sound/ppc/tumbler.c static int snapper_set_mix_vol1(struct pmac_tumbler *mix, int idx, int ch, int reg) reg 638 sound/ppc/tumbler.c if (i2c_smbus_write_i2c_block_data(mix->i2c.client, reg, reg 640 sound/ppc/tumbler.c snd_printk(KERN_ERR "failed to set mono volume %d\n", reg); reg 118 sound/soc/amd/acp-pcm-dma.c static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg) reg 120 sound/soc/amd/acp-pcm-dma.c return readl(acp_mmio + (reg * 4)); reg 123 sound/soc/amd/acp-pcm-dma.c static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg) reg 125 sound/soc/amd/acp-pcm-dma.c writel(val, acp_mmio + (reg * 4)); reg 70 sound/soc/atmel/atmel-pcm.h #define ssc_readx(base, reg) (__raw_readl((base) + (reg))) reg 71 sound/soc/atmel/atmel-pcm.h #define ssc_writex(base, reg, value) __raw_writel((value), (base) + (reg)) reg 232 sound/soc/atmel/tse850-pcm5142.c #define TSE850_DAPM_SINGLE_EXT(xname, reg, shift, max, invert, xget, xput) \ reg 237 sound/soc/atmel/tse850-pcm5142.c .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) } reg 72 sound/soc/au1x/ac97c.c static inline unsigned long RD(struct au1xpsc_audio_data *ctx, int reg) reg 74 sound/soc/au1x/ac97c.c return __raw_readl(ctx->mmio + reg); reg 77 sound/soc/au1x/ac97c.c static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v) reg 79 sound/soc/au1x/ac97c.c __raw_writel(v, ctx->mmio + reg); reg 70 sound/soc/au1x/i2sc.c static inline unsigned long RD(struct au1xpsc_audio_data *ctx, int reg) reg 72 sound/soc/au1x/i2sc.c return __raw_readl(ctx->mmio + reg); reg 75 sound/soc/au1x/i2sc.c static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v) reg 77 sound/soc/au1x/i2sc.c __raw_writel(v, ctx->mmio + reg); reg 72 sound/soc/au1x/psc-ac97.c unsigned short reg) reg 85 sound/soc/au1x/psc-ac97.c __raw_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg), reg 103 sound/soc/au1x/psc-ac97.c if (reg != ((data >> 16) & 0x7f)) reg 112 sound/soc/au1x/psc-ac97.c static void au1xpsc_ac97_write(struct snd_ac97 *ac97, unsigned short reg, reg 125 sound/soc/au1x/psc-ac97.c __raw_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff), reg 790 sound/soc/bcm/bcm2835-i2s.c static bool bcm2835_i2s_volatile_reg(struct device *dev, unsigned int reg) reg 792 sound/soc/bcm/bcm2835-i2s.c switch (reg) { reg 803 sound/soc/bcm/bcm2835-i2s.c static bool bcm2835_i2s_precious_reg(struct device *dev, unsigned int reg) reg 805 sound/soc/bcm/bcm2835-i2s.c switch (reg) { reg 119 sound/soc/cirrus/ep93xx-ac97.c unsigned reg) reg 121 sound/soc/cirrus/ep93xx-ac97.c return __raw_readl(info->regs + reg); reg 125 sound/soc/cirrus/ep93xx-ac97.c unsigned reg, unsigned val) reg 127 sound/soc/cirrus/ep93xx-ac97.c __raw_writel(val, info->regs + reg); reg 131 sound/soc/cirrus/ep93xx-ac97.c unsigned short reg) reg 138 sound/soc/cirrus/ep93xx-ac97.c ep93xx_ac97_write_reg(info, AC97S1DATA, reg); reg 141 sound/soc/cirrus/ep93xx-ac97.c dev_warn(info->dev, "timeout reading register %x\n", reg); reg 152 sound/soc/cirrus/ep93xx-ac97.c unsigned short reg, reg 164 sound/soc/cirrus/ep93xx-ac97.c ep93xx_ac97_write_reg(info, AC97S1DATA, reg); reg 168 sound/soc/cirrus/ep93xx-ac97.c dev_warn(info->dev, "timeout writing register %x\n", reg); reg 96 sound/soc/cirrus/ep93xx-i2s.c unsigned reg, unsigned val) reg 98 sound/soc/cirrus/ep93xx-i2s.c __raw_writel(val, info->regs + reg); reg 102 sound/soc/cirrus/ep93xx-i2s.c unsigned reg) reg 104 sound/soc/cirrus/ep93xx-i2s.c return __raw_readl(info->regs + reg); reg 273 sound/soc/codecs/88pm860x-codec.c unsigned int reg = mc->reg; reg 277 sound/soc/codecs/88pm860x-codec.c val[0] = snd_soc_component_read32(component, reg) & 0x3f; reg 297 sound/soc/codecs/88pm860x-codec.c unsigned int reg = mc->reg; reg 308 sound/soc/codecs/88pm860x-codec.c err = snd_soc_component_update_bits(component, reg, 0x3f, st_table[val].m); reg 330 sound/soc/codecs/88pm860x-codec.c unsigned int reg = mc->reg; reg 336 sound/soc/codecs/88pm860x-codec.c val = snd_soc_component_read32(component, reg) >> shift; reg 350 sound/soc/codecs/88pm860x-codec.c unsigned int reg = mc->reg; reg 365 sound/soc/codecs/88pm860x-codec.c err = snd_soc_component_update_bits(component, reg, val_mask, val); reg 167 sound/soc/codecs/ab8500-codec.c static int ab8500_codec_read_reg(void *context, unsigned int reg, reg 175 sound/soc/codecs/ab8500-codec.c reg, &value8); reg 182 sound/soc/codecs/ab8500-codec.c static int ab8500_codec_write_reg(void *context, unsigned int reg, reg 188 sound/soc/codecs/ab8500-codec.c reg, value); reg 38 sound/soc/codecs/ac97.c int reg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? reg 40 sound/soc/codecs/ac97.c return snd_ac97_set_rate(ac97, reg, substream->runtime->rate); reg 58 sound/soc/codecs/ad1980.c static bool ad1980_readable_reg(struct device *dev, unsigned int reg) reg 60 sound/soc/codecs/ad1980.c switch (reg) { reg 79 sound/soc/codecs/ad1980.c static bool ad1980_writeable_reg(struct device *dev, unsigned int reg) reg 81 sound/soc/codecs/ad1980.c switch (reg) { reg 86 sound/soc/codecs/ad1980.c return ad1980_readable_reg(dev, reg); reg 1437 sound/soc/codecs/adau1373.c static bool adau1373_register_volatile(struct device *dev, unsigned int reg) reg 1439 sound/soc/codecs/adau1373.c switch (reg) { reg 152 sound/soc/codecs/adau1701.c unsigned int reg) reg 154 sound/soc/codecs/adau1701.c switch (reg) { reg 168 sound/soc/codecs/adau1701.c dev_err(dev, "Unsupported register address: %d\n", reg); reg 172 sound/soc/codecs/adau1701.c static bool adau1701_volatile_reg(struct device *dev, unsigned int reg) reg 174 sound/soc/codecs/adau1701.c switch (reg) { reg 183 sound/soc/codecs/adau1701.c static int adau1701_reg_write(void *context, unsigned int reg, reg 192 sound/soc/codecs/adau1701.c size = adau1701_register_size(&client->dev, reg); reg 196 sound/soc/codecs/adau1701.c buf[0] = reg >> 8; reg 197 sound/soc/codecs/adau1701.c buf[1] = reg & 0xff; reg 213 sound/soc/codecs/adau1701.c static int adau1701_reg_read(void *context, unsigned int reg, reg 223 sound/soc/codecs/adau1701.c size = adau1701_register_size(&client->dev, reg); reg 227 sound/soc/codecs/adau1701.c send_buf[0] = reg >> 8; reg 228 sound/soc/codecs/adau1701.c send_buf[1] = reg & 0xff; reg 608 sound/soc/codecs/adau1761.c static bool adau1761_readable_register(struct device *dev, unsigned int reg) reg 610 sound/soc/codecs/adau1761.c switch (reg) { reg 640 sound/soc/codecs/adau1761.c return adau17x1_readable_register(dev, reg); reg 344 sound/soc/codecs/adau1781.c static bool adau1781_readable_register(struct device *dev, unsigned int reg) reg 346 sound/soc/codecs/adau1781.c switch (reg) { reg 365 sound/soc/codecs/adau1781.c return adau17x1_readable_register(dev, reg); reg 368 sound/soc/codecs/adau1781.c static int adau1781_set_input_mode(struct adau *adau, unsigned int reg, reg 378 sound/soc/codecs/adau1781.c return regmap_update_bits(adau->regmap, reg, reg 196 sound/soc/codecs/adau17x1.c int reg; reg 213 sound/soc/codecs/adau17x1.c reg = ADAU17X1_SERIAL_INPUT_ROUTE; reg 215 sound/soc/codecs/adau17x1.c reg = ADAU17X1_SERIAL_OUTPUT_ROUTE; reg 217 sound/soc/codecs/adau17x1.c change = snd_soc_component_test_bits(component, reg, 0xff, val); reg 221 sound/soc/codecs/adau17x1.c update.reg = reg; reg 238 sound/soc/codecs/adau17x1.c unsigned int reg, val; reg 242 sound/soc/codecs/adau17x1.c reg = ADAU17X1_SERIAL_INPUT_ROUTE; reg 244 sound/soc/codecs/adau17x1.c reg = ADAU17X1_SERIAL_OUTPUT_ROUTE; reg 246 sound/soc/codecs/adau17x1.c ret = regmap_read(adau->regmap, reg, &val); reg 786 sound/soc/codecs/adau17x1.c bool adau17x1_precious_register(struct device *dev, unsigned int reg) reg 789 sound/soc/codecs/adau17x1.c if (reg < 0x400) reg 796 sound/soc/codecs/adau17x1.c bool adau17x1_readable_register(struct device *dev, unsigned int reg) reg 799 sound/soc/codecs/adau17x1.c if (reg < 0x400) reg 802 sound/soc/codecs/adau17x1.c switch (reg) { reg 835 sound/soc/codecs/adau17x1.c bool adau17x1_volatile_register(struct device *dev, unsigned int reg) reg 838 sound/soc/codecs/adau17x1.c if (reg < 0x4000) reg 841 sound/soc/codecs/adau17x1.c switch (reg) { reg 64 sound/soc/codecs/adau17x1.h bool adau17x1_readable_register(struct device *dev, unsigned int reg); reg 65 sound/soc/codecs/adau17x1.h bool adau17x1_volatile_register(struct device *dev, unsigned int reg); reg 66 sound/soc/codecs/adau17x1.h bool adau17x1_precious_register(struct device *dev, unsigned int reg); reg 981 sound/soc/codecs/adau1977.c static bool adau1977_register_volatile(struct device *dev, unsigned int reg) reg 983 sound/soc/codecs/adau1977.c switch (reg) { reg 164 sound/soc/codecs/adav80x.c #define ADAV80X_MUX_ENUM_DECL(name, reg, shift) \ reg 165 sound/soc/codecs/adav80x.c SOC_VALUE_ENUM_DOUBLE_DECL(name, reg, shift, 7, \ reg 408 sound/soc/codecs/ak4458.c int nfs, ndt, ret, reg; reg 413 sound/soc/codecs/ak4458.c reg = snd_soc_component_read32(component, AK4458_0B_CONTROL7); reg 414 sound/soc/codecs/ak4458.c ats = (reg & AK4458_ATS_MASK) >> AK4458_ATS_SHIFT; reg 55 sound/soc/codecs/ak4535.c static bool ak4535_volatile(struct device *dev, unsigned int reg) reg 57 sound/soc/codecs/ak4535.c switch (reg) { reg 526 sound/soc/codecs/alc5623.c u16 reg; reg 537 sound/soc/codecs/alc5623.c reg = snd_soc_component_read32(component, ALC5623_DAI_CONTROL); reg 538 sound/soc/codecs/alc5623.c if (reg & ALC5623_DAI_SDP_SLAVE_MODE) reg 88 sound/soc/codecs/alc5632.c unsigned int reg) reg 90 sound/soc/codecs/alc5632.c switch (reg) { reg 683 sound/soc/codecs/alc5632.c u16 reg; reg 697 sound/soc/codecs/alc5632.c reg = snd_soc_component_read32(component, ALC5632_DAI_CONTROL); reg 698 sound/soc/codecs/alc5632.c if (reg & ALC5632_DAI_SDP_SLAVE_MODE) reg 899 sound/soc/codecs/arizona.c unsigned int reg = ARIZONA_IN1L_CONTROL + ((shift / 2) * 8); reg 900 sound/soc/codecs/arizona.c unsigned int val = snd_soc_component_read32(component, reg); reg 911 sound/soc/codecs/arizona.c unsigned int reg; reg 914 sound/soc/codecs/arizona.c reg = ARIZONA_ADC_DIGITAL_VOLUME_1L + ((w->shift / 2) * 8); reg 916 sound/soc/codecs/arizona.c reg = ARIZONA_ADC_DIGITAL_VOLUME_1R + ((w->shift / 2) * 8); reg 923 sound/soc/codecs/arizona.c snd_soc_component_update_bits(component, reg, reg 934 sound/soc/codecs/arizona.c snd_soc_component_update_bits(component, reg, reg 940 sound/soc/codecs/arizona.c reg = snd_soc_component_read32(component, ARIZONA_INPUT_ENABLES); reg 941 sound/soc/codecs/arizona.c if (reg == 0) reg 1279 sound/soc/codecs/arizona.c unsigned int reg; reg 1285 sound/soc/codecs/arizona.c reg = ARIZONA_OUTPUT_SYSTEM_CLOCK; reg 1289 sound/soc/codecs/arizona.c reg = ARIZONA_OUTPUT_ASYNC_CLOCK; reg 1308 sound/soc/codecs/arizona.c snd_soc_component_update_bits(component, reg, reg 1333 sound/soc/codecs/arizona.c ret = regmap_read(arizona->regmap, w->reg, &val); reg 1370 sound/soc/codecs/arizona.c unsigned int reg; reg 1378 sound/soc/codecs/arizona.c reg = ARIZONA_SYSTEM_CLOCK_1; reg 1384 sound/soc/codecs/arizona.c reg = ARIZONA_ASYNC_CLOCK_1; reg 1437 sound/soc/codecs/arizona.c return regmap_update_bits(arizona->regmap, reg, mask, val); reg 1959 sound/soc/codecs/arizona.c unsigned int reg; reg 1962 sound/soc/codecs/arizona.c reg = ARIZONA_AIF1_TRI; reg 1964 sound/soc/codecs/arizona.c reg = 0; reg 1968 sound/soc/codecs/arizona.c ARIZONA_AIF1_TRI, reg); reg 2366 sound/soc/codecs/arizona.c unsigned int reg; reg 2369 sound/soc/codecs/arizona.c ret = regmap_read(arizona->regmap, base + 1, ®); reg 2376 sound/soc/codecs/arizona.c return reg & ARIZONA_FLL1_ENA; reg 2664 sound/soc/codecs/arizona.c unsigned int reg, val; reg 2669 sound/soc/codecs/arizona.c reg = ARIZONA_OUTPUT_PATH_CONFIG_1L + (output - 1) * 8; reg 2676 sound/soc/codecs/arizona.c return snd_soc_component_update_bits(component, reg, reg 125 sound/soc/codecs/arizona.h #define ARIZONA_MUX_ENUM_DECL(name, reg) \ reg 127 sound/soc/codecs/arizona.h name, reg, 0, 0xff, arizona_mixer_texts, arizona_mixer_values) reg 218 sound/soc/codecs/cpcap.c u16 reg; reg 1143 sound/soc/codecs/cpcap.c static const u16 reg = CPCAP_REG_SDACDI; reg 1216 sound/soc/codecs/cpcap.c return regmap_update_bits(cpcap->regmap, reg, mask, val); reg 1223 sound/soc/codecs/cpcap.c static const u16 reg = CPCAP_REG_RXSDOA; reg 1233 sound/soc/codecs/cpcap.c return regmap_update_bits(cpcap->regmap, reg, mask, val); reg 1377 sound/soc/codecs/cpcap.c static const u16 reg = CPCAP_REG_RXCOA; reg 1387 sound/soc/codecs/cpcap.c return regmap_update_bits(cpcap->regmap, reg, mask, val); reg 1473 sound/soc/codecs/cpcap.c cpcap_default_regs[i].reg, reg 36 sound/soc/codecs/cq93vc.c u8 reg; reg 39 sound/soc/codecs/cq93vc.c reg = DAVINCI_VC_REG09_MUTE; reg 41 sound/soc/codecs/cq93vc.c reg = 0; reg 44 sound/soc/codecs/cq93vc.c reg); reg 70 sound/soc/codecs/cs35l32.c static bool cs35l32_readable_register(struct device *dev, unsigned int reg) reg 72 sound/soc/codecs/cs35l32.c switch (reg) { reg 81 sound/soc/codecs/cs35l32.c static bool cs35l32_volatile_register(struct device *dev, unsigned int reg) reg 83 sound/soc/codecs/cs35l32.c switch (reg) { reg 92 sound/soc/codecs/cs35l32.c static bool cs35l32_precious_register(struct device *dev, unsigned int reg) reg 94 sound/soc/codecs/cs35l32.c switch (reg) { reg 353 sound/soc/codecs/cs35l32.c unsigned int reg; reg 413 sound/soc/codecs/cs35l32.c ret = regmap_read(cs35l32->regmap, CS35L32_DEVID_AB, ®); reg 414 sound/soc/codecs/cs35l32.c devid = (reg & 0xFF) << 12; reg 416 sound/soc/codecs/cs35l32.c ret = regmap_read(cs35l32->regmap, CS35L32_DEVID_CD, ®); reg 417 sound/soc/codecs/cs35l32.c devid |= (reg & 0xFF) << 4; reg 419 sound/soc/codecs/cs35l32.c ret = regmap_read(cs35l32->regmap, CS35L32_DEVID_E, ®); reg 420 sound/soc/codecs/cs35l32.c devid |= (reg & 0xF0) >> 4; reg 430 sound/soc/codecs/cs35l32.c ret = regmap_read(cs35l32->regmap, CS35L32_REV_ID, ®); reg 444 sound/soc/codecs/cs35l32.c "Cirrus Logic CS35L32, Revision: %02X\n", reg & 0xFF); reg 481 sound/soc/codecs/cs35l32.c ret = regmap_read(cs35l32->regmap, CS35L32_INT_STATUS_1, ®); reg 102 sound/soc/codecs/cs35l33.c static bool cs35l33_volatile_register(struct device *dev, unsigned int reg) reg 104 sound/soc/codecs/cs35l33.c switch (reg) { reg 118 sound/soc/codecs/cs35l33.c static bool cs35l33_writeable_register(struct device *dev, unsigned int reg) reg 120 sound/soc/codecs/cs35l33.c switch (reg) { reg 135 sound/soc/codecs/cs35l33.c static bool cs35l33_readable_register(struct device *dev, unsigned int reg) reg 137 sound/soc/codecs/cs35l33.c switch (reg) { reg 555 sound/soc/codecs/cs35l33.c unsigned int reg, bit_pos, i; reg 624 sound/soc/codecs/cs35l33.c reg = CS35L33_TX_EN4 - (slot/8); reg 626 sound/soc/codecs/cs35l33.c regmap_update_bits(priv->regmap, reg, reg 1124 sound/soc/codecs/cs35l33.c unsigned int reg; reg 1193 sound/soc/codecs/cs35l33.c ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_AB, ®); reg 1194 sound/soc/codecs/cs35l33.c devid = (reg & 0xFF) << 12; reg 1195 sound/soc/codecs/cs35l33.c ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_CD, ®); reg 1196 sound/soc/codecs/cs35l33.c devid |= (reg & 0xFF) << 4; reg 1197 sound/soc/codecs/cs35l33.c ret = regmap_read(cs35l33->regmap, CS35L33_DEVID_E, ®); reg 1198 sound/soc/codecs/cs35l33.c devid |= (reg & 0xF0) >> 4; reg 1207 sound/soc/codecs/cs35l33.c ret = regmap_read(cs35l33->regmap, CS35L33_REV_ID, ®); reg 1214 sound/soc/codecs/cs35l33.c "Cirrus Logic CS35L33, Revision: %02X\n", reg & 0xFF); reg 120 sound/soc/codecs/cs35l34.c static bool cs35l34_volatile_register(struct device *dev, unsigned int reg) reg 122 sound/soc/codecs/cs35l34.c switch (reg) { reg 141 sound/soc/codecs/cs35l34.c static bool cs35l34_readable_register(struct device *dev, unsigned int reg) reg 143 sound/soc/codecs/cs35l34.c switch (reg) { reg 220 sound/soc/codecs/cs35l34.c static bool cs35l34_precious_register(struct device *dev, unsigned int reg) reg 222 sound/soc/codecs/cs35l34.c switch (reg) { reg 273 sound/soc/codecs/cs35l34.c unsigned int reg, bit_pos; reg 325 sound/soc/codecs/cs35l34.c reg = CS35L34_TDM_TX_SLOT_EN_4 - (slot/8); reg 327 sound/soc/codecs/cs35l34.c snd_soc_component_update_bits(component, reg, reg 384 sound/soc/codecs/cs35l34.c unsigned int reg; reg 389 sound/soc/codecs/cs35l34.c ®); reg 394 sound/soc/codecs/cs35l34.c if (reg & CS35L34_AMP_DIGSFT) reg 401 sound/soc/codecs/cs35l34.c ®); reg 407 sound/soc/codecs/cs35l34.c if (reg & CS35L34_PDN_DONE) reg 1002 sound/soc/codecs/cs35l34.c unsigned int reg; reg 1069 sound/soc/codecs/cs35l34.c ret = regmap_read(cs35l34->regmap, CS35L34_DEVID_AB, ®); reg 1071 sound/soc/codecs/cs35l34.c devid = (reg & 0xFF) << 12; reg 1072 sound/soc/codecs/cs35l34.c ret = regmap_read(cs35l34->regmap, CS35L34_DEVID_CD, ®); reg 1073 sound/soc/codecs/cs35l34.c devid |= (reg & 0xFF) << 4; reg 1074 sound/soc/codecs/cs35l34.c ret = regmap_read(cs35l34->regmap, CS35L34_DEVID_E, ®); reg 1075 sound/soc/codecs/cs35l34.c devid |= (reg & 0xF0) >> 4; reg 1085 sound/soc/codecs/cs35l34.c ret = regmap_read(cs35l34->regmap, CS35L34_REV_ID, ®); reg 1093 sound/soc/codecs/cs35l34.c reg & 0xFF); reg 107 sound/soc/codecs/cs35l35.c static bool cs35l35_volatile_register(struct device *dev, unsigned int reg) reg 109 sound/soc/codecs/cs35l35.c switch (reg) { reg 122 sound/soc/codecs/cs35l35.c static bool cs35l35_readable_register(struct device *dev, unsigned int reg) reg 124 sound/soc/codecs/cs35l35.c switch (reg) { reg 146 sound/soc/codecs/cs35l35.c static bool cs35l35_precious_register(struct device *dev, unsigned int reg) reg 148 sound/soc/codecs/cs35l35.c switch (reg) { reg 241 sound/soc/codecs/cs35l35.c unsigned int reg[4]; reg 269 sound/soc/codecs/cs35l35.c ®, ARRAY_SIZE(reg)); reg 1478 sound/soc/codecs/cs35l35.c unsigned int reg; reg 1556 sound/soc/codecs/cs35l35.c ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_AB, ®); reg 1558 sound/soc/codecs/cs35l35.c devid = (reg & 0xFF) << 12; reg 1559 sound/soc/codecs/cs35l35.c ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_CD, ®); reg 1560 sound/soc/codecs/cs35l35.c devid |= (reg & 0xFF) << 4; reg 1561 sound/soc/codecs/cs35l35.c ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_E, ®); reg 1562 sound/soc/codecs/cs35l35.c devid |= (reg & 0xF0) >> 4; reg 1571 sound/soc/codecs/cs35l35.c ret = regmap_read(cs35l35->regmap, CS35L35_REV_ID, ®); reg 1585 sound/soc/codecs/cs35l35.c devid, reg & 0xFF); reg 247 sound/soc/codecs/cs35l36.c static bool cs35l36_readable_reg(struct device *dev, unsigned int reg) reg 249 sound/soc/codecs/cs35l36.c switch (reg) { reg 389 sound/soc/codecs/cs35l36.c if (reg >= CS35L36_PAC_PMEM_WORD0 && reg 390 sound/soc/codecs/cs35l36.c reg <= CS35L36_PAC_PMEM_WORD1023) reg 397 sound/soc/codecs/cs35l36.c static bool cs35l36_precious_reg(struct device *dev, unsigned int reg) reg 399 sound/soc/codecs/cs35l36.c switch (reg) { reg 409 sound/soc/codecs/cs35l36.c static bool cs35l36_volatile_reg(struct device *dev, unsigned int reg) reg 411 sound/soc/codecs/cs35l36.c switch (reg) { reg 439 sound/soc/codecs/cs35l36.c if (reg >= CS35L36_PAC_PMEM_WORD0 && reg 440 sound/soc/codecs/cs35l36.c reg <= CS35L36_PAC_PMEM_WORD1023) reg 510 sound/soc/codecs/cs35l36.c u32 reg; reg 520 sound/soc/codecs/cs35l36.c regmap_read(cs35l36->regmap, CS35L36_INT4_RAW_STATUS, ®); reg 522 sound/soc/codecs/cs35l36.c if (WARN_ON_ONCE(reg & CS35L36_PLL_UNLOCK_MASK)) reg 56 sound/soc/codecs/cs4265.c static bool cs4265_readable_register(struct device *dev, unsigned int reg) reg 58 sound/soc/codecs/cs4265.c switch (reg) { reg 66 sound/soc/codecs/cs4265.c static bool cs4265_volatile_register(struct device *dev, unsigned int reg) reg 68 sound/soc/codecs/cs4265.c switch (reg) { reg 577 sound/soc/codecs/cs4265.c unsigned int reg; reg 603 sound/soc/codecs/cs4265.c ret = regmap_read(cs4265->regmap, CS4265_CHIP_ID, ®); reg 604 sound/soc/codecs/cs4265.c devid = reg & CS4265_CHIP_ID_MASK; reg 614 sound/soc/codecs/cs4265.c reg & CS4265_REV_ID_MASK); reg 213 sound/soc/codecs/cs4270.c static bool cs4270_reg_is_readable(struct device *dev, unsigned int reg) reg 215 sound/soc/codecs/cs4270.c return (reg >= CS4270_FIRSTREG) && (reg <= CS4270_LASTREG); reg 218 sound/soc/codecs/cs4270.c static bool cs4270_reg_is_volatile(struct device *dev, unsigned int reg) reg 221 sound/soc/codecs/cs4270.c if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG)) reg 224 sound/soc/codecs/cs4270.c return reg == CS4270_CHIPID; reg 335 sound/soc/codecs/cs4270.c int reg; reg 355 sound/soc/codecs/cs4270.c reg = snd_soc_component_read32(component, CS4270_MODE); reg 356 sound/soc/codecs/cs4270.c reg &= ~(CS4270_MODE_SPEED_MASK | CS4270_MODE_DIV_MASK); reg 357 sound/soc/codecs/cs4270.c reg |= cs4270_mode_ratios[i].mclk; reg 360 sound/soc/codecs/cs4270.c reg |= CS4270_MODE_SLAVE; reg 362 sound/soc/codecs/cs4270.c reg |= cs4270_mode_ratios[i].speed_mode; reg 364 sound/soc/codecs/cs4270.c ret = snd_soc_component_write(component, CS4270_MODE, reg); reg 372 sound/soc/codecs/cs4270.c reg = snd_soc_component_read32(component, CS4270_FORMAT); reg 373 sound/soc/codecs/cs4270.c reg &= ~(CS4270_FORMAT_DAC_MASK | CS4270_FORMAT_ADC_MASK); reg 377 sound/soc/codecs/cs4270.c reg |= CS4270_FORMAT_DAC_I2S | CS4270_FORMAT_ADC_I2S; reg 380 sound/soc/codecs/cs4270.c reg |= CS4270_FORMAT_DAC_LJ | CS4270_FORMAT_ADC_LJ; reg 387 sound/soc/codecs/cs4270.c ret = snd_soc_component_write(component, CS4270_FORMAT, reg); reg 565 sound/soc/codecs/cs4270.c int reg, ret; reg 567 sound/soc/codecs/cs4270.c reg = snd_soc_component_read32(component, CS4270_PWRCTL) | CS4270_PWRCTL_PDN_ALL; reg 568 sound/soc/codecs/cs4270.c if (reg < 0) reg 569 sound/soc/codecs/cs4270.c return reg; reg 571 sound/soc/codecs/cs4270.c ret = snd_soc_component_write(component, CS4270_PWRCTL, reg); reg 584 sound/soc/codecs/cs4270.c int reg, ret; reg 599 sound/soc/codecs/cs4270.c reg = snd_soc_component_read32(component, CS4270_PWRCTL); reg 600 sound/soc/codecs/cs4270.c reg &= ~CS4270_PWRCTL_PDN_ALL; reg 602 sound/soc/codecs/cs4270.c return snd_soc_component_write(component, CS4270_PWRCTL, reg); reg 147 sound/soc/codecs/cs4271.c static bool cs4271_volatile_reg(struct device *dev, unsigned int reg) reg 149 sound/soc/codecs/cs4271.c return reg == CS4271_CHIPID; reg 186 sound/soc/codecs/cs42l42.c static bool cs42l42_readable_register(struct device *dev, unsigned int reg) reg 188 sound/soc/codecs/cs42l42.c switch (reg) { reg 345 sound/soc/codecs/cs42l42.c static bool cs42l42_volatile_register(struct device *dev, unsigned int reg) reg 347 sound/soc/codecs/cs42l42.c switch (reg) { reg 1524 sound/soc/codecs/cs42l42.c unsigned int reg; reg 1556 sound/soc/codecs/cs42l42.c ®); reg 1557 sound/soc/codecs/cs42l42.c cs42l42->plug_state = (((char) reg) & reg 1760 sound/soc/codecs/cs42l42.c unsigned int reg; reg 1820 sound/soc/codecs/cs42l42.c ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_AB, ®); reg 1821 sound/soc/codecs/cs42l42.c devid = (reg & 0xFF) << 12; reg 1823 sound/soc/codecs/cs42l42.c ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_CD, ®); reg 1824 sound/soc/codecs/cs42l42.c devid |= (reg & 0xFF) << 4; reg 1826 sound/soc/codecs/cs42l42.c ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_E, ®); reg 1827 sound/soc/codecs/cs42l42.c devid |= (reg & 0xF0) >> 4; reg 1837 sound/soc/codecs/cs42l42.c ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®); reg 1844 sound/soc/codecs/cs42l42.c "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF); reg 486 sound/soc/codecs/cs42l51.c int reg; reg 489 sound/soc/codecs/cs42l51.c reg = snd_soc_component_read32(component, CS42L51_DAC_OUT_CTL); reg 492 sound/soc/codecs/cs42l51.c reg |= mask; reg 494 sound/soc/codecs/cs42l51.c reg &= ~mask; reg 496 sound/soc/codecs/cs42l51.c return snd_soc_component_write(component, CS42L51_DAC_OUT_CTL, reg); reg 534 sound/soc/codecs/cs42l51.c int ret, reg; reg 551 sound/soc/codecs/cs42l51.c reg = CS42L51_DAC_CTL_DATA_SEL(1) reg 553 sound/soc/codecs/cs42l51.c ret = snd_soc_component_write(component, CS42L51_DAC_CTL, reg); reg 575 sound/soc/codecs/cs42l51.c static bool cs42l51_writeable_reg(struct device *dev, unsigned int reg) reg 577 sound/soc/codecs/cs42l51.c switch (reg) { reg 615 sound/soc/codecs/cs42l51.c static bool cs42l51_volatile_reg(struct device *dev, unsigned int reg) reg 617 sound/soc/codecs/cs42l51.c switch (reg) { reg 625 sound/soc/codecs/cs42l51.c static bool cs42l51_readable_reg(struct device *dev, unsigned int reg) reg 627 sound/soc/codecs/cs42l51.c switch (reg) { reg 106 sound/soc/codecs/cs42l52.c static bool cs42l52_readable_register(struct device *dev, unsigned int reg) reg 108 sound/soc/codecs/cs42l52.c switch (reg) { reg 116 sound/soc/codecs/cs42l52.c static bool cs42l52_volatile_register(struct device *dev, unsigned int reg) reg 118 sound/soc/codecs/cs42l52.c switch (reg) { reg 1095 sound/soc/codecs/cs42l52.c unsigned int reg; reg 1163 sound/soc/codecs/cs42l52.c ret = regmap_read(cs42l52->regmap, CS42L52_CHIP, ®); reg 1164 sound/soc/codecs/cs42l52.c devid = reg & CS42L52_CHIP_ID_MASK; reg 1174 sound/soc/codecs/cs42l52.c reg & CS42L52_CHIP_REV_MASK); reg 109 sound/soc/codecs/cs42l56.c static bool cs42l56_readable_register(struct device *dev, unsigned int reg) reg 111 sound/soc/codecs/cs42l56.c switch (reg) { reg 119 sound/soc/codecs/cs42l56.c static bool cs42l56_volatile_register(struct device *dev, unsigned int reg) reg 121 sound/soc/codecs/cs42l56.c switch (reg) { reg 1178 sound/soc/codecs/cs42l56.c unsigned int reg; reg 1245 sound/soc/codecs/cs42l56.c ret = regmap_read(cs42l56->regmap, CS42L56_CHIP_ID_1, ®); reg 1246 sound/soc/codecs/cs42l56.c devid = reg & CS42L56_CHIP_ID_MASK; reg 1253 sound/soc/codecs/cs42l56.c alpha_rev = reg & CS42L56_AREV_MASK; reg 1254 sound/soc/codecs/cs42l56.c metal_rev = reg & CS42L56_MTLREV_MASK; reg 138 sound/soc/codecs/cs42l73.c static bool cs42l73_volatile_register(struct device *dev, unsigned int reg) reg 140 sound/soc/codecs/cs42l73.c switch (reg) { reg 149 sound/soc/codecs/cs42l73.c static bool cs42l73_readable_register(struct device *dev, unsigned int reg) reg 151 sound/soc/codecs/cs42l73.c switch (reg) { reg 1280 sound/soc/codecs/cs42l73.c unsigned int reg; reg 1329 sound/soc/codecs/cs42l73.c ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_AB, ®); reg 1330 sound/soc/codecs/cs42l73.c devid = (reg & 0xFF) << 12; reg 1332 sound/soc/codecs/cs42l73.c ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_CD, ®); reg 1333 sound/soc/codecs/cs42l73.c devid |= (reg & 0xFF) << 4; reg 1335 sound/soc/codecs/cs42l73.c ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_E, ®); reg 1336 sound/soc/codecs/cs42l73.c devid |= (reg & 0xF0) >> 4; reg 1346 sound/soc/codecs/cs42l73.c ret = regmap_read(cs42l73->regmap, CS42L73_REVID, ®); reg 1353 sound/soc/codecs/cs42l73.c "Cirrus Logic CS42L73, Revision: %02X\n", reg & 0xFF); reg 431 sound/soc/codecs/cs42xx8.c static bool cs42xx8_volatile_register(struct device *dev, unsigned int reg) reg 433 sound/soc/codecs/cs42xx8.c switch (reg) { reg 441 sound/soc/codecs/cs42xx8.c static bool cs42xx8_writeable_register(struct device *dev, unsigned int reg) reg 443 sound/soc/codecs/cs42xx8.c switch (reg) { reg 111 sound/soc/codecs/cs43130.c static bool cs43130_volatile_register(struct device *dev, unsigned int reg) reg 113 sound/soc/codecs/cs43130.c switch (reg) { reg 123 sound/soc/codecs/cs43130.c static bool cs43130_readable_register(struct device *dev, unsigned int reg) reg 125 sound/soc/codecs/cs43130.c switch (reg) { reg 169 sound/soc/codecs/cs43130.c static bool cs43130_precious_register(struct device *dev, unsigned int reg) reg 171 sound/soc/codecs/cs43130.c switch (reg) { reg 1926 sound/soc/codecs/cs43130.c unsigned int reg; reg 1939 sound/soc/codecs/cs43130.c regmap_read(cs43130->regmap, CS43130_HP_LOAD_1, ®); reg 1940 sound/soc/codecs/cs43130.c if (reg & CS43130_HPLOAD_CHN_SEL) reg 1948 sound/soc/codecs/cs43130.c regmap_read(cs43130->regmap, addr, ®); reg 1949 sound/soc/codecs/cs43130.c impedance = reg >> 3; reg 1950 sound/soc/codecs/cs43130.c regmap_read(cs43130->regmap, addr + 1, ®); reg 1951 sound/soc/codecs/cs43130.c impedance |= reg << 5; reg 2053 sound/soc/codecs/cs43130.c unsigned int reg, seq_size; reg 2080 sound/soc/codecs/cs43130.c regmap_read(cs43130->regmap, CS43130_INT_STATUS_4, ®); reg 2284 sound/soc/codecs/cs43130.c unsigned int reg; reg 2327 sound/soc/codecs/cs43130.c regmap_read(cs43130->regmap, CS43130_INT_STATUS_1, ®); reg 2328 sound/soc/codecs/cs43130.c regmap_read(cs43130->regmap, CS43130_HP_STATUS, ®); reg 2428 sound/soc/codecs/cs43130.c unsigned int reg; reg 2474 sound/soc/codecs/cs43130.c ret = regmap_read(cs43130->regmap, CS43130_DEVID_AB, ®); reg 2476 sound/soc/codecs/cs43130.c devid = (reg & 0xFF) << 12; reg 2477 sound/soc/codecs/cs43130.c ret = regmap_read(cs43130->regmap, CS43130_DEVID_CD, ®); reg 2478 sound/soc/codecs/cs43130.c devid |= (reg & 0xFF) << 4; reg 2479 sound/soc/codecs/cs43130.c ret = regmap_read(cs43130->regmap, CS43130_DEVID_E, ®); reg 2480 sound/soc/codecs/cs43130.c devid |= (reg & 0xF0) >> 4; reg 2498 sound/soc/codecs/cs43130.c ret = regmap_read(cs43130->regmap, CS43130_REV_ID, ®); reg 2506 sound/soc/codecs/cs43130.c reg & 0xFF); reg 219 sound/soc/codecs/cs4341.c regmap_write(cs4341->regmap, cs4341_reg_defaults[i].reg, reg 268 sound/soc/codecs/cs4341.c static bool cs4341_reg_readable(struct device *dev, unsigned int reg) reg 51 sound/soc/codecs/cs4349.c static bool cs4349_readable_register(struct device *dev, unsigned int reg) reg 53 sound/soc/codecs/cs4349.c switch (reg) { reg 61 sound/soc/codecs/cs4349.c static bool cs4349_writeable_register(struct device *dev, unsigned int reg) reg 63 sound/soc/codecs/cs4349.c switch (reg) { reg 137 sound/soc/codecs/cs4349.c int reg; reg 139 sound/soc/codecs/cs4349.c reg = 0; reg 141 sound/soc/codecs/cs4349.c reg = MUTE_AB_MASK; reg 143 sound/soc/codecs/cs4349.c return snd_soc_component_update_bits(component, CS4349_MUTE, MUTE_AB_MASK, reg); reg 86 sound/soc/codecs/cs53l30.c static bool cs53l30_volatile_register(struct device *dev, unsigned int reg) reg 88 sound/soc/codecs/cs53l30.c if (reg == CS53L30_IS) reg 94 sound/soc/codecs/cs53l30.c static bool cs53l30_writeable_register(struct device *dev, unsigned int reg) reg 96 sound/soc/codecs/cs53l30.c switch (reg) { reg 108 sound/soc/codecs/cs53l30.c static bool cs53l30_readable_register(struct device *dev, unsigned int reg) reg 110 sound/soc/codecs/cs53l30.c switch (reg) { reg 654 sound/soc/codecs/cs53l30.c unsigned int reg; reg 694 sound/soc/codecs/cs53l30.c regmap_read(priv->regmap, CS53L30_SFT_RAMP, ®); reg 695 sound/soc/codecs/cs53l30.c if (reg & CS53L30_DIGSFT_MASK) reg 706 sound/soc/codecs/cs53l30.c regmap_read(priv->regmap, CS53L30_IS, ®); reg 710 sound/soc/codecs/cs53l30.c regmap_read(priv->regmap, CS53L30_IS, ®); reg 711 sound/soc/codecs/cs53l30.c if (reg & CS53L30_PDN_DONE) reg 715 sound/soc/codecs/cs53l30.c regmap_read(priv->regmap, CS53L30_IS, ®); reg 716 sound/soc/codecs/cs53l30.c if (reg & CS53L30_PDN_DONE) reg 924 sound/soc/codecs/cs53l30.c unsigned int reg; reg 971 sound/soc/codecs/cs53l30.c ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_AB, ®); reg 972 sound/soc/codecs/cs53l30.c devid = reg << 12; reg 974 sound/soc/codecs/cs53l30.c ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_CD, ®); reg 975 sound/soc/codecs/cs53l30.c devid |= reg << 4; reg 977 sound/soc/codecs/cs53l30.c ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_E, ®); reg 978 sound/soc/codecs/cs53l30.c devid |= (reg & 0xF0) >> 4; reg 987 sound/soc/codecs/cs53l30.c ret = regmap_read(cs53l30->regmap, CS53L30_REVID, ®); reg 1029 sound/soc/codecs/cs53l30.c dev_info(dev, "Cirrus Logic CS53L30, Revision: %02X\n", reg & 0xFF); reg 89 sound/soc/codecs/cx20442.c unsigned int reg) reg 93 sound/soc/codecs/cx20442.c if (reg >= 1) reg 152 sound/soc/codecs/cx20442.c static int cx20442_write(struct snd_soc_component *component, unsigned int reg, reg 159 sound/soc/codecs/cx20442.c if (reg >= 1) reg 253 sound/soc/codecs/cx2072x.c static unsigned int cx2072x_register_size(unsigned int reg) reg 255 sound/soc/codecs/cx2072x.c switch (reg) { reg 317 sound/soc/codecs/cx2072x.c static bool cx2072x_readable_register(struct device *dev, unsigned int reg) reg 319 sound/soc/codecs/cx2072x.c switch (reg) { reg 469 sound/soc/codecs/cx2072x.c static bool cx2072x_volatile_register(struct device *dev, unsigned int reg) reg 471 sound/soc/codecs/cx2072x.c switch (reg) { reg 490 sound/soc/codecs/cx2072x.c unsigned int reg, reg 500 sound/soc/codecs/cx2072x.c buf[0] = reg >> 8; reg 501 sound/soc/codecs/cx2072x.c buf[1] = reg & 0xff; reg 513 sound/soc/codecs/cx2072x.c static int cx2072x_reg_write(void *context, unsigned int reg, reg 519 sound/soc/codecs/cx2072x.c size = cx2072x_register_size(reg); reg 521 sound/soc/codecs/cx2072x.c if (reg == CX2072X_UM_INTERRUPT_CRTL_E) { reg 523 sound/soc/codecs/cx2072x.c reg += 3; reg 529 sound/soc/codecs/cx2072x.c return cx2072x_reg_raw_write(context, reg, &raw_value, size); reg 532 sound/soc/codecs/cx2072x.c static int cx2072x_reg_read(void *context, unsigned int reg, reg 543 sound/soc/codecs/cx2072x.c size = cx2072x_register_size(reg); reg 545 sound/soc/codecs/cx2072x.c send_buf[0] = reg >> 8; reg 546 sound/soc/codecs/cx2072x.c send_buf[1] = reg & 0xff; reg 1161 sound/soc/codecs/cx2072x.c .num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \ reg 1168 sound/soc/codecs/cx2072x.c .num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \ reg 1175 sound/soc/codecs/cx2072x.c .num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \ reg 1182 sound/soc/codecs/cx2072x.c .reg = wreg, .shift = wshift, .mask = wmask, \ reg 727 sound/soc/codecs/da7210.c static bool da7210_readable_register(struct device *dev, unsigned int reg) reg 729 sound/soc/codecs/da7210.c switch (reg) { reg 741 sound/soc/codecs/da7210.c unsigned int reg) reg 743 sound/soc/codecs/da7210.c switch (reg) { reg 1115 sound/soc/codecs/da7213.c static bool da7213_volatile_register(struct device *dev, unsigned int reg) reg 1117 sound/soc/codecs/da7213.c switch (reg) { reg 476 sound/soc/codecs/da7218.c unsigned int reg = mixer_ctrl->reg; reg 484 sound/soc/codecs/da7218.c ret = regmap_raw_read(da7218->regmap, reg, &val, 2); reg 500 sound/soc/codecs/da7218.c unsigned int reg = mixer_ctrl->reg; reg 510 sound/soc/codecs/da7218.c return regmap_raw_write(da7218->regmap, reg, &val, 2); reg 536 sound/soc/codecs/da7218.c return snd_soc_component_write(component, mixer_ctrl->reg, reg 592 sound/soc/codecs/da7218.c u8 reg, out_filt1l; reg 602 sound/soc/codecs/da7218.c reg = DA7218_OUT_1_BIQ_5STAGE_DATA; reg 607 sound/soc/codecs/da7218.c reg = DA7218_SIDETONE_BIQ_3STAGE_DATA; reg 623 sound/soc/codecs/da7218.c regmap_raw_write(da7218->regmap, reg, cfg, DA7218_BIQ_CFG_SIZE); reg 1272 sound/soc/codecs/da7218.c #define DA7218_DMIX_CTRLS(reg) \ reg 1273 sound/soc/codecs/da7218.c SOC_DAPM_SINGLE("In Filter1L Switch", reg, \ reg 1276 sound/soc/codecs/da7218.c SOC_DAPM_SINGLE("In Filter1R Switch", reg, \ reg 1279 sound/soc/codecs/da7218.c SOC_DAPM_SINGLE("In Filter2L Switch", reg, \ reg 1282 sound/soc/codecs/da7218.c SOC_DAPM_SINGLE("In Filter2R Switch", reg, \ reg 1285 sound/soc/codecs/da7218.c SOC_DAPM_SINGLE("ToneGen Switch", reg, \ reg 1288 sound/soc/codecs/da7218.c SOC_DAPM_SINGLE("DAIL Switch", reg, DA7218_DMIX_SRC_DAIL, \ reg 1290 sound/soc/codecs/da7218.c SOC_DAPM_SINGLE("DAIR Switch", reg, DA7218_DMIX_SRC_DAIR, \ reg 1317 sound/soc/codecs/da7218.c #define DA7218_DMIX_ST_CTRLS(reg) \ reg 1318 sound/soc/codecs/da7218.c SOC_DAPM_SINGLE("Out FilterL Switch", reg, \ reg 1321 sound/soc/codecs/da7218.c SOC_DAPM_SINGLE("Out FilterR Switch", reg, \ reg 1324 sound/soc/codecs/da7218.c SOC_DAPM_SINGLE("Sidetone Switch", reg, \ reg 1352 sound/soc/codecs/da7218.c switch (w->reg) { reg 1512 sound/soc/codecs/da7218.c snd_soc_component_update_bits(component, w->reg, DA7218_HP_AMP_OE_MASK, reg 1517 sound/soc/codecs/da7218.c snd_soc_component_update_bits(component, w->reg, DA7218_HP_AMP_OE_MASK, 0); reg 3220 sound/soc/codecs/da7218.c static bool da7218_volatile_register(struct device *dev, unsigned int reg) reg 3222 sound/soc/codecs/da7218.c switch (reg) { reg 421 sound/soc/codecs/da7219.c unsigned int reg = mixer_ctrl->reg; reg 426 sound/soc/codecs/da7219.c ret = regmap_raw_read(da7219->regmap, reg, &val, sizeof(val)); reg 448 sound/soc/codecs/da7219.c unsigned int reg = mixer_ctrl->reg; reg 460 sound/soc/codecs/da7219.c ret = regmap_raw_write(da7219->regmap, reg, &val, sizeof(val)); reg 743 sound/soc/codecs/da7219.c #define DA7219_DMIX_ST_CTRLS(reg) \ reg 744 sound/soc/codecs/da7219.c SOC_DAPM_SINGLE("Out FilterL Switch", reg, \ reg 747 sound/soc/codecs/da7219.c SOC_DAPM_SINGLE("Out FilterR Switch", reg, \ reg 750 sound/soc/codecs/da7219.c SOC_DAPM_SINGLE("Sidetone Switch", reg, \ reg 888 sound/soc/codecs/da7219.c switch (w->reg) { reg 2523 sound/soc/codecs/da7219.c static bool da7219_volatile_register(struct device *dev, unsigned int reg) reg 2525 sound/soc/codecs/da7219.c switch (reg) { reg 333 sound/soc/codecs/da732x.c unsigned int reg = enum_ctrl->reg; reg 351 sound/soc/codecs/da732x.c snd_soc_component_update_bits(component, reg, DA732X_HPF_MASK, bits); reg 361 sound/soc/codecs/da732x.c unsigned int reg = enum_ctrl->reg; reg 364 sound/soc/codecs/da732x.c val = snd_soc_component_read32(component, reg) & DA732X_HPF_MASK; reg 613 sound/soc/codecs/da732x.c switch (w->reg) { reg 628 sound/soc/codecs/da732x.c snd_soc_component_update_bits(component, w->reg, DA732X_ADC_RST_MASK, reg 630 sound/soc/codecs/da732x.c snd_soc_component_update_bits(component, w->reg, DA732X_ADC_PD_MASK, reg 634 sound/soc/codecs/da732x.c snd_soc_component_update_bits(component, w->reg, DA732X_ADC_PD_MASK, reg 636 sound/soc/codecs/da732x.c snd_soc_component_update_bits(component, w->reg, DA732X_ADC_RST_MASK, reg 639 sound/soc/codecs/da732x.c switch (w->reg) { reg 667 sound/soc/codecs/da732x.c snd_soc_component_update_bits(component, w->reg, reg 672 sound/soc/codecs/da732x.c snd_soc_component_update_bits(component, w->reg, reg 1245 sound/soc/codecs/da732x.c static bool da732x_volatile(struct device *dev, unsigned int reg) reg 1247 sound/soc/codecs/da732x.c switch (reg) { reg 1518 sound/soc/codecs/da732x.c unsigned int reg; reg 1535 sound/soc/codecs/da732x.c ret = regmap_read(da732x->regmap, DA732X_REG_ID, ®); reg 1542 sound/soc/codecs/da732x.c (reg & DA732X_ID_MAJOR_MASK) >> 4, reg 1543 sound/soc/codecs/da732x.c (reg & DA732X_ID_MINOR_MASK)); reg 1021 sound/soc/codecs/da9055.c unsigned int reg) reg 1023 sound/soc/codecs/da9055.c switch (reg) { reg 480 sound/soc/codecs/es8328.c int reg; reg 485 sound/soc/codecs/es8328.c reg = ES8328_DACCONTROL2; reg 487 sound/soc/codecs/es8328.c reg = ES8328_ADCCONTROL5; reg 548 sound/soc/codecs/es8328.c return snd_soc_component_update_bits(component, reg, ES8328_RATEMASK, ratio); reg 696 sound/soc/codecs/hdac_hdmi.c w->reg = SND_SOC_NOPM; reg 999 sound/soc/codecs/hdac_hdmi.c se->reg = SND_SOC_NOPM; reg 457 sound/soc/codecs/jz4725b.c static bool jz4725b_codec_volatile(struct device *dev, unsigned int reg) reg 459 sound/soc/codecs/jz4725b.c return reg == JZ4725B_CODEC_REG_IFR; reg 462 sound/soc/codecs/jz4725b.c static bool jz4725b_codec_can_access_reg(struct device *dev, unsigned int reg) reg 464 sound/soc/codecs/jz4725b.c return (reg != JZ4725B_CODEC_REG_TR1) && (reg != JZ4725B_CODEC_REG_TR2); reg 469 sound/soc/codecs/jz4725b.c u32 reg; reg 471 sound/soc/codecs/jz4725b.c return readl_poll_timeout(icdc->base + ICDC_RGADW_OFFSET, reg, reg 472 sound/soc/codecs/jz4725b.c !(reg & ICDC_RGADW_RGWR), 1000, 10000); reg 475 sound/soc/codecs/jz4725b.c static int jz4725b_codec_reg_read(void *context, unsigned int reg, reg 489 sound/soc/codecs/jz4725b.c | (reg << ICDC_RGADW_RGADDR_OFFSET); reg 500 sound/soc/codecs/jz4725b.c static int jz4725b_codec_reg_write(void *context, unsigned int reg, reg 510 sound/soc/codecs/jz4725b.c writel(ICDC_RGADW_RGWR | (reg << ICDC_RGADW_RGADDR_OFFSET) | val, reg 618 sound/soc/codecs/madera.c switch (e->reg) { reg 639 sound/soc/codecs/madera.c mux, e->reg, inmode, mask, val); reg 641 sound/soc/codecs/madera.c ret = regmap_update_bits_check(regmap, e->reg, mask, val, &changed); reg 717 sound/soc/codecs/madera.c unsigned int reg) reg 721 sound/soc/codecs/madera.c switch (reg) { reg 812 sound/soc/codecs/madera.c dev_dbg(priv->madera->dev, "Rate reg 0x%x group ref %d\n", reg, count); reg 1021 sound/soc/codecs/madera.c ret = snd_soc_component_read(component, e->reg, &val); reg 1024 sound/soc/codecs/madera.c e->reg, ret); reg 1034 sound/soc/codecs/madera.c if (!madera_can_change_grp_rate(priv, e->reg)) { reg 2120 sound/soc/codecs/madera.c unsigned int reg = e->reg; reg 2124 sound/soc/codecs/madera.c reg = ((reg / 6) * 6) - 2; reg 2128 sound/soc/codecs/madera.c ret = snd_soc_component_read(component, reg, &val); reg 2164 sound/soc/codecs/madera.c mask = (mc->reg - MADERA_ADC_DIGITAL_VOLUME_1L) / 4; reg 2225 sound/soc/codecs/madera.c unsigned int reg, val; reg 2229 sound/soc/codecs/madera.c reg = MADERA_ADC_DIGITAL_VOLUME_1L + ((w->shift / 2) * 8); reg 2231 sound/soc/codecs/madera.c reg = MADERA_ADC_DIGITAL_VOLUME_1R + ((w->shift / 2) * 8); reg 2239 sound/soc/codecs/madera.c snd_soc_component_update_bits(component, reg, reg 2249 sound/soc/codecs/madera.c snd_soc_component_update_bits(component, reg, reg 2462 sound/soc/codecs/madera.c unsigned int reg, val; reg 2471 sound/soc/codecs/madera.c reg = MADERA_OUTPUT_SYSTEM_CLOCK; reg 2475 sound/soc/codecs/madera.c reg = MADERA_OUTPUT_ASYNC_CLOCK; reg 2499 sound/soc/codecs/madera.c snd_soc_component_update_bits(component, reg, reg 2641 sound/soc/codecs/madera.c unsigned int reg, clock_2_val = 0; reg 2650 sound/soc/codecs/madera.c reg = MADERA_SYSTEM_CLOCK_1; reg 2657 sound/soc/codecs/madera.c reg = MADERA_ASYNC_CLOCK_1; reg 2663 sound/soc/codecs/madera.c reg = MADERA_DSP_CLOCK_1; reg 2713 sound/soc/codecs/madera.c return regmap_update_bits(madera->regmap, reg, mask, val); reg 2957 sound/soc/codecs/madera.c unsigned int reg, cur, tar; reg 2973 sound/soc/codecs/madera.c reg = MADERA_SAMPLE_RATE_1; reg 2977 sound/soc/codecs/madera.c reg = MADERA_SAMPLE_RATE_2; reg 2981 sound/soc/codecs/madera.c reg = MADERA_SAMPLE_RATE_3; reg 2985 sound/soc/codecs/madera.c reg = MADERA_ASYNC_SAMPLE_RATE_1, reg 2989 sound/soc/codecs/madera.c reg = MADERA_ASYNC_SAMPLE_RATE_2, reg 2997 sound/soc/codecs/madera.c snd_soc_component_update_bits(component, reg, MADERA_SAMPLE_RATE_1_MASK, reg 3262 sound/soc/codecs/madera.c unsigned int reg; reg 3266 sound/soc/codecs/madera.c reg = MADERA_AIF1_TRI; reg 3268 sound/soc/codecs/madera.c reg = 0; reg 3272 sound/soc/codecs/madera.c MADERA_AIF1_TRI, reg); reg 3744 sound/soc/codecs/madera.c unsigned int reg; reg 3748 sound/soc/codecs/madera.c base + MADERA_FLL_CONTROL_1_OFFS, ®); reg 3754 sound/soc/codecs/madera.c return reg & MADERA_FLL1_ENA; reg 4159 sound/soc/codecs/madera.c if (patch[i].reg == MADERA_FLLAO_CONTROL_6) { reg 4165 sound/soc/codecs/madera.c regmap_write(madera->regmap, patch[i].reg, val); reg 4583 sound/soc/codecs/madera.c unsigned int reg, val; reg 4589 sound/soc/codecs/madera.c reg = MADERA_OUTPUT_PATH_CONFIG_1L + (output - 1) * 8; reg 4596 sound/soc/codecs/madera.c ret = snd_soc_component_update_bits(component, reg, MADERA_OUT1_MONO, reg 205 sound/soc/codecs/madera.h #define MADERA_MUX_ENUM_DECL(name, reg) \ reg 207 sound/soc/codecs/madera.h name, reg, 0, 0xff, madera_mixer_texts, madera_mixer_values) reg 260 sound/soc/codecs/max98088.c static bool max98088_readable_register(struct device *dev, unsigned int reg) reg 262 sound/soc/codecs/max98088.c switch (reg) { reg 271 sound/soc/codecs/max98088.c static bool max98088_writeable_register(struct device *dev, unsigned int reg) reg 273 sound/soc/codecs/max98088.c switch (reg) { reg 281 sound/soc/codecs/max98088.c static bool max98088_volatile_register(struct device *dev, unsigned int reg) reg 283 sound/soc/codecs/max98088.c switch (reg) { reg 624 sound/soc/codecs/max98088.c if (w->reg == M98088_REG_35_LVL_MIC1) { reg 625 sound/soc/codecs/max98088.c snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, reg 628 sound/soc/codecs/max98088.c snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, reg 633 sound/soc/codecs/max98088.c snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, 0); reg 670 sound/soc/codecs/max98088.c snd_soc_component_update_bits(component, w->reg, reg 676 sound/soc/codecs/max98088.c snd_soc_component_update_bits(component, w->reg, reg 1280 sound/soc/codecs/max98088.c int reg; reg 1283 sound/soc/codecs/max98088.c reg = M98088_DAI_MUTE; reg 1285 sound/soc/codecs/max98088.c reg = 0; reg 1288 sound/soc/codecs/max98088.c M98088_DAI_MUTE_MASK, reg); reg 1295 sound/soc/codecs/max98088.c int reg; reg 1298 sound/soc/codecs/max98088.c reg = M98088_DAI_MUTE; reg 1300 sound/soc/codecs/max98088.c reg = 0; reg 1303 sound/soc/codecs/max98088.c M98088_DAI_MUTE_MASK, reg); reg 251 sound/soc/codecs/max98090.c static bool max98090_volatile_register(struct device *dev, unsigned int reg) reg 253 sound/soc/codecs/max98090.c switch (reg) { reg 264 sound/soc/codecs/max98090.c static bool max98090_readable_register(struct device *dev, unsigned int reg) reg 266 sound/soc/codecs/max98090.c switch (reg) { reg 356 sound/soc/codecs/max98090.c unsigned int val = snd_soc_component_read32(component, mc->reg); reg 359 sound/soc/codecs/max98090.c switch (mc->reg) { reg 397 sound/soc/codecs/max98090.c unsigned int val = snd_soc_component_read32(component, mc->reg); reg 400 sound/soc/codecs/max98090.c switch (mc->reg) { reg 426 sound/soc/codecs/max98090.c snd_soc_component_update_bits(component, mc->reg, reg 733 sound/soc/codecs/max98090.c unsigned int val = snd_soc_component_read32(component, w->reg); reg 735 sound/soc/codecs/max98090.c if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) reg 741 sound/soc/codecs/max98090.c if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) { reg 751 sound/soc/codecs/max98090.c if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) reg 764 sound/soc/codecs/max98090.c if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) reg 765 sound/soc/codecs/max98090.c snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK, reg 768 sound/soc/codecs/max98090.c snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK, reg 2133 sound/soc/codecs/max98090.c int reg; reg 2144 sound/soc/codecs/max98090.c reg = snd_soc_component_read32(component, M98090_REG_JACK_STATUS); reg 2150 sound/soc/codecs/max98090.c reg = snd_soc_component_read32(component, M98090_REG_JACK_STATUS); reg 2153 sound/soc/codecs/max98090.c reg = snd_soc_component_read32(component, M98090_REG_JACK_STATUS); reg 2155 sound/soc/codecs/max98090.c switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) { reg 202 sound/soc/codecs/max98095.c static bool max98095_readable(struct device *dev, unsigned int reg) reg 204 sound/soc/codecs/max98095.c switch (reg) { reg 213 sound/soc/codecs/max98095.c static bool max98095_writeable(struct device *dev, unsigned int reg) reg 215 sound/soc/codecs/max98095.c switch (reg) { reg 223 sound/soc/codecs/max98095.c static bool max98095_volatile(struct device *dev, unsigned int reg) reg 225 sound/soc/codecs/max98095.c switch (reg) { reg 603 sound/soc/codecs/max98095.c if (w->reg == M98095_05F_LVL_MIC1) { reg 604 sound/soc/codecs/max98095.c snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK, reg 607 sound/soc/codecs/max98095.c snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK, reg 612 sound/soc/codecs/max98095.c snd_soc_component_update_bits(component, w->reg, M98095_MICPRE_MASK, 0); reg 640 sound/soc/codecs/max98095.c snd_soc_component_update_bits(component, w->reg, reg 646 sound/soc/codecs/max98095.c snd_soc_component_update_bits(component, w->reg, reg 680 sound/soc/codecs/max98095.c snd_soc_component_update_bits(component, w->reg, reg 684 sound/soc/codecs/max98095.c snd_soc_component_update_bits(component, w->reg, reg 129 sound/soc/codecs/max98371.c static bool max98371_volatile_register(struct device *dev, unsigned int reg) reg 131 sound/soc/codecs/max98371.c switch (reg) { reg 142 sound/soc/codecs/max98371.c static bool max98371_readable_register(struct device *dev, unsigned int reg) reg 144 sound/soc/codecs/max98371.c switch (reg) { reg 372 sound/soc/codecs/max98371.c int ret, reg; reg 388 sound/soc/codecs/max98371.c ret = regmap_read(max98371->regmap, MAX98371_VERSION, ®); reg 393 sound/soc/codecs/max98371.c dev_info(&i2c->dev, "device version %x\n", reg); reg 496 sound/soc/codecs/max98373.c static bool max98373_readable_register(struct device *dev, unsigned int reg) reg 498 sound/soc/codecs/max98373.c switch (reg) { reg 527 sound/soc/codecs/max98373.c static bool max98373_volatile_reg(struct device *dev, unsigned int reg) reg 529 sound/soc/codecs/max98373.c switch (reg) { reg 736 sound/soc/codecs/max98373.c int ret, reg, count; reg 751 sound/soc/codecs/max98373.c MAX98373_R21FF_REV_ID, ®); reg 931 sound/soc/codecs/max98373.c int reg = 0; reg 978 sound/soc/codecs/max98373.c MAX98373_R21FF_REV_ID, ®); reg 984 sound/soc/codecs/max98373.c dev_info(&i2c->dev, "MAX98373 revisionID: 0x%02X\n", reg); reg 32 sound/soc/codecs/max9850.c static bool max9850_volatile_register(struct device *dev, unsigned int reg) reg 34 sound/soc/codecs/max9850.c switch (reg) { reg 77 sound/soc/codecs/max98504.c static bool max98504_volatile_register(struct device *dev, unsigned int reg) reg 79 sound/soc/codecs/max98504.c switch (reg) { reg 92 sound/soc/codecs/max98504.c static bool max98504_readable_register(struct device *dev, unsigned int reg) reg 94 sound/soc/codecs/max98504.c switch (reg) { reg 67 sound/soc/codecs/max9860.c static bool max9860_readable(struct device *dev, unsigned int reg) reg 69 sound/soc/codecs/max9860.c switch (reg) { reg 79 sound/soc/codecs/max9860.c static bool max9860_writeable(struct device *dev, unsigned int reg) reg 81 sound/soc/codecs/max9860.c switch (reg) { reg 90 sound/soc/codecs/max9860.c static bool max9860_volatile(struct device *dev, unsigned int reg) reg 92 sound/soc/codecs/max9860.c switch (reg) { reg 101 sound/soc/codecs/max9860.c static bool max9860_precious(struct device *dev, unsigned int reg) reg 103 sound/soc/codecs/max9860.c switch (reg) { reg 673 sound/soc/codecs/max9860.c max9860_regmap.reg_defaults[i].reg, reg 677 sound/soc/codecs/max9860.c max9860_regmap.reg_defaults[i].reg, ret); reg 453 sound/soc/codecs/max9867.c static bool max9867_volatile_register(struct device *dev, unsigned int reg) reg 455 sound/soc/codecs/max9867.c switch (reg) { reg 503 sound/soc/codecs/max9867.c int ret, reg; reg 516 sound/soc/codecs/max9867.c ret = regmap_read(max9867->regmap, MAX9867_REVISION, ®); reg 521 sound/soc/codecs/max9867.c dev_info(&i2c->dev, "device revision: %x\n", reg); reg 148 sound/soc/codecs/max9877.c regmap_write(regmap, max9877_regs[i].reg, max9877_regs[i].def); reg 153 sound/soc/codecs/max98925.c static bool max98925_volatile_register(struct device *dev, unsigned int reg) reg 155 sound/soc/codecs/max98925.c switch (reg) { reg 174 sound/soc/codecs/max98925.c static bool max98925_readable_register(struct device *dev, unsigned int reg) reg 176 sound/soc/codecs/max98925.c switch (reg) { reg 567 sound/soc/codecs/max98925.c int ret, reg; reg 600 sound/soc/codecs/max98925.c ret = regmap_read(max98925->regmap, MAX98925_REV_VERSION, ®); reg 606 sound/soc/codecs/max98925.c if ((reg != MAX98925_VERSION) && (reg != MAX98925_VERSION1)) { reg 609 sound/soc/codecs/max98925.c ret, reg); reg 613 sound/soc/codecs/max98925.c dev_info(&i2c->dev, "device version 0x%02X\n", reg); reg 171 sound/soc/codecs/max98926.c static bool max98926_volatile_register(struct device *dev, unsigned int reg) reg 173 sound/soc/codecs/max98926.c switch (reg) { reg 192 sound/soc/codecs/max98926.c static bool max98926_readable_register(struct device *dev, unsigned int reg) reg 194 sound/soc/codecs/max98926.c switch (reg) { reg 516 sound/soc/codecs/max98926.c int ret, reg; reg 551 sound/soc/codecs/max98926.c MAX98926_VERSION, ®); reg 553 sound/soc/codecs/max98926.c dev_err(&i2c->dev, "Failed to read: %x\n", reg); reg 563 sound/soc/codecs/max98926.c dev_info(&i2c->dev, "device version: %x\n", reg); reg 562 sound/soc/codecs/max98927.c static bool max98927_readable_register(struct device *dev, unsigned int reg) reg 564 sound/soc/codecs/max98927.c switch (reg) { reg 584 sound/soc/codecs/max98927.c static bool max98927_volatile_reg(struct device *dev, unsigned int reg) reg 586 sound/soc/codecs/max98927.c switch (reg) { reg 869 sound/soc/codecs/max98927.c int reg = 0; reg 903 sound/soc/codecs/max98927.c MAX98927_R01FF_REV_ID, ®); reg 909 sound/soc/codecs/max98927.c dev_info(&i2c->dev, "MAX98927 revisionID: 0x%02X\n", reg); reg 148 sound/soc/codecs/mc13783.c unsigned int reg) reg 198 sound/soc/codecs/mc13783.c snd_soc_component_update_bits(component, reg, mask, val); reg 243 sound/soc/codecs/mc13783.c unsigned int reg) reg 265 sound/soc/codecs/mc13783.c snd_soc_component_update_bits(component, reg, mask, val); reg 374 sound/soc/codecs/msm8916-wcd-analog.c int reg, unsigned int cap_mode) reg 389 sound/soc/codecs/msm8916-wcd-analog.c int reg, u32 cap_mode) reg 394 sound/soc/codecs/msm8916-wcd-analog.c snd_soc_component_update_bits(component, reg, MICB_1_EN_PULL_DOWN_EN_MASK, 0); reg 418 sound/soc/codecs/msm8916-wcd-analog.c return pm8916_wcd_analog_enable_micbias_ext(component, event, w->reg, reg 430 sound/soc/codecs/msm8916-wcd-analog.c return pm8916_wcd_analog_enable_micbias_ext(component, event, w->reg, reg 451 sound/soc/codecs/msm8916-wcd-analog.c return pm8916_wcd_analog_enable_micbias_int(component, event, w->reg, reg 574 sound/soc/codecs/msm8916-wcd-analog.c return pm8916_wcd_analog_enable_micbias_int(component, event, w->reg, reg 586 sound/soc/codecs/msm8916-wcd-analog.c if (w->reg == CDC_A_TX_1_EN) reg 593 sound/soc/codecs/msm8916-wcd-analog.c if (w->reg == CDC_A_TX_2_EN) reg 605 sound/soc/codecs/msm8916-wcd-analog.c switch (w->reg) { reg 628 sound/soc/codecs/msm8916-wcd-analog.c switch (w->reg) { reg 677 sound/soc/codecs/msm8916-wcd-analog.c snd_soc_component_update_bits(component, w->reg, reg 720 sound/soc/codecs/msm8916-wcd-analog.c int err, reg; reg 740 sound/soc/codecs/msm8916-wcd-analog.c for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++) reg 741 sound/soc/codecs/msm8916-wcd-analog.c snd_soc_component_write(component, wcd_reg_defaults_2_0[reg].reg, reg 742 sound/soc/codecs/msm8916-wcd-analog.c wcd_reg_defaults_2_0[reg].def); reg 361 sound/soc/codecs/msm8916-wcd-digital.c int value = 0, reg = 0; reg 366 sound/soc/codecs/msm8916-wcd-digital.c reg = LPASS_CDC_IIR1_GAIN_B1_CTL; reg 368 sound/soc/codecs/msm8916-wcd-digital.c reg = LPASS_CDC_IIR2_GAIN_B1_CTL; reg 369 sound/soc/codecs/msm8916-wcd-digital.c value = snd_soc_component_read32(component, reg); reg 370 sound/soc/codecs/msm8916-wcd-digital.c snd_soc_component_write(component, reg, value); reg 589 sound/soc/codecs/mt6351.c w->reg + REG_STRIDE, reg 595 sound/soc/codecs/mt6351.c w->reg + REG_STRIDE * 2, reg 604 sound/soc/codecs/mt6351.c w->reg + REG_STRIDE, reg 610 sound/soc/codecs/mt6351.c w->reg + REG_STRIDE * 2, reg 717 sound/soc/codecs/mt6351.c int reg; reg 739 sound/soc/codecs/mt6351.c regmap_read(cmpnt->regmap, MT6351_ZCD_CON2, ®); reg 740 sound/soc/codecs/mt6351.c priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = reg & 0x1f; reg 741 sound/soc/codecs/mt6351.c priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = (reg >> 7) & 0x1f; reg 424 sound/soc/codecs/mt6358.c unsigned int reg; reg 431 sound/soc/codecs/mt6358.c switch (mc->reg) { reg 433 sound/soc/codecs/mt6358.c regmap_read(priv->regmap, MT6358_ZCD_CON2, ®); reg 435 sound/soc/codecs/mt6358.c (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK; reg 437 sound/soc/codecs/mt6358.c (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK; reg 440 sound/soc/codecs/mt6358.c regmap_read(priv->regmap, MT6358_ZCD_CON1, ®); reg 442 sound/soc/codecs/mt6358.c (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK; reg 444 sound/soc/codecs/mt6358.c (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK; reg 447 sound/soc/codecs/mt6358.c regmap_read(priv->regmap, MT6358_ZCD_CON3, ®); reg 449 sound/soc/codecs/mt6358.c (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK; reg 451 sound/soc/codecs/mt6358.c (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK; reg 455 sound/soc/codecs/mt6358.c regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON0, ®); reg 457 sound/soc/codecs/mt6358.c (reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK; reg 458 sound/soc/codecs/mt6358.c regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON1, ®); reg 460 sound/soc/codecs/mt6358.c (reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK; reg 131 sound/soc/codecs/nau8540.c static bool nau8540_readable_reg(struct device *dev, unsigned int reg) reg 133 sound/soc/codecs/nau8540.c switch (reg) { reg 150 sound/soc/codecs/nau8540.c static bool nau8540_writeable_reg(struct device *dev, unsigned int reg) reg 152 sound/soc/codecs/nau8540.c switch (reg) { reg 168 sound/soc/codecs/nau8540.c static bool nau8540_volatile_reg(struct device *dev, unsigned int reg) reg 170 sound/soc/codecs/nau8540.c switch (reg) { reg 96 sound/soc/codecs/nau8810.c static bool nau8810_readable_reg(struct device *dev, unsigned int reg) reg 98 sound/soc/codecs/nau8810.c switch (reg) { reg 122 sound/soc/codecs/nau8810.c static bool nau8810_writeable_reg(struct device *dev, unsigned int reg) reg 124 sound/soc/codecs/nau8810.c switch (reg) { reg 147 sound/soc/codecs/nau8810.c static bool nau8810_volatile_reg(struct device *dev, unsigned int reg) reg 149 sound/soc/codecs/nau8810.c switch (reg) { reg 170 sound/soc/codecs/nau8810.c int i, reg, reg_val; reg 174 sound/soc/codecs/nau8810.c reg = NAU8810_REG_EQ1; reg 176 sound/soc/codecs/nau8810.c regmap_read(nau8810->regmap, reg + i, ®_val); reg 203 sound/soc/codecs/nau8810.c int i, reg, ret; reg 211 sound/soc/codecs/nau8810.c reg = NAU8810_REG_EQ1; reg 217 sound/soc/codecs/nau8810.c ret = regmap_write(nau8810->regmap, reg + i, value); reg 220 sound/soc/codecs/nau8810.c reg + i, ret); reg 110 sound/soc/codecs/nau8822.c static bool nau8822_readable_reg(struct device *dev, unsigned int reg) reg 112 sound/soc/codecs/nau8822.c switch (reg) { reg 134 sound/soc/codecs/nau8822.c static bool nau8822_writeable_reg(struct device *dev, unsigned int reg) reg 136 sound/soc/codecs/nau8822.c switch (reg) { reg 158 sound/soc/codecs/nau8822.c static bool nau8822_volatile(struct device *dev, unsigned int reg) reg 160 sound/soc/codecs/nau8822.c switch (reg) { reg 185 sound/soc/codecs/nau8822.c int i, reg; reg 189 sound/soc/codecs/nau8822.c reg = NAU8822_REG_EQ1; reg 191 sound/soc/codecs/nau8822.c reg_val = snd_soc_component_read32(component, reg + i); reg 218 sound/soc/codecs/nau8822.c int i, reg, ret; reg 226 sound/soc/codecs/nau8822.c reg = NAU8822_REG_EQ1; reg 232 sound/soc/codecs/nau8822.c ret = snd_soc_component_write(component, reg + i, value); reg 236 sound/soc/codecs/nau8822.c reg + i, ret); reg 220 sound/soc/codecs/nau8824.c static bool nau8824_readable_reg(struct device *dev, unsigned int reg) reg 222 sound/soc/codecs/nau8824.c switch (reg) { reg 248 sound/soc/codecs/nau8824.c static bool nau8824_writeable_reg(struct device *dev, unsigned int reg) reg 250 sound/soc/codecs/nau8824.c switch (reg) { reg 279 sound/soc/codecs/nau8824.c static bool nau8824_volatile_reg(struct device *dev, unsigned int reg) reg 281 sound/soc/codecs/nau8824.c switch (reg) { reg 442 sound/soc/codecs/nau8825.c static int nau8825_xtalk_baktab_index_by_reg(unsigned int reg) reg 447 sound/soc/codecs/nau8825.c if (nau8825_xtalk_baktab[index].reg == reg) reg 461 sound/soc/codecs/nau8825.c regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg, reg 480 sound/soc/codecs/nau8825.c if (!cause_cancel && nau8825_xtalk_baktab[i].reg == reg 488 sound/soc/codecs/nau8825.c regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg, reg 844 sound/soc/codecs/nau8825.c static bool nau8825_readable_reg(struct device *dev, unsigned int reg) reg 846 sound/soc/codecs/nau8825.c switch (reg) { reg 869 sound/soc/codecs/nau8825.c static bool nau8825_writeable_reg(struct device *dev, unsigned int reg) reg 871 sound/soc/codecs/nau8825.c switch (reg) { reg 893 sound/soc/codecs/nau8825.c static bool nau8825_volatile_reg(struct device *dev, unsigned int reg) reg 895 sound/soc/codecs/nau8825.c switch (reg) { reg 62 sound/soc/codecs/pcm1681.c static bool pcm1681_accessible_reg(struct device *dev, unsigned int reg) reg 64 sound/soc/codecs/pcm1681.c return !((reg == 0x00) || (reg == 0x0f)); reg 67 sound/soc/codecs/pcm1681.c static bool pcm1681_writeable_reg(struct device *dev, unsigned int reg) reg 69 sound/soc/codecs/pcm1681.c return pcm1681_accessible_reg(dev, reg) && reg 70 sound/soc/codecs/pcm1681.c (reg != PCM1681_ZERO_DETECT_STATUS); reg 42 sound/soc/codecs/pcm1789.c static bool pcm1789_accessible_reg(struct device *dev, unsigned int reg) reg 44 sound/soc/codecs/pcm1789.c return reg >= PCM1789_MUTE_CONTROL && reg <= PCM1789_DAC_VOL_RIGHT; reg 47 sound/soc/codecs/pcm1789.c static bool pcm1789_writeable_reg(struct device *dev, unsigned int reg) reg 49 sound/soc/codecs/pcm1789.c return pcm1789_accessible_reg(dev, reg); reg 48 sound/soc/codecs/pcm179x.c static bool pcm179x_accessible_reg(struct device *dev, unsigned int reg) reg 50 sound/soc/codecs/pcm179x.c return reg >= 0x10 && reg <= 0x17; reg 53 sound/soc/codecs/pcm179x.c static bool pcm179x_writeable_reg(struct device *dev, unsigned int reg) reg 57 sound/soc/codecs/pcm179x.c accessible = pcm179x_accessible_reg(dev, reg); reg 59 sound/soc/codecs/pcm179x.c return accessible && reg != 0x16 && reg != 0x17; reg 605 sound/soc/codecs/pcm186x.c static bool pcm186x_volatile(struct device *dev, unsigned int reg) reg 607 sound/soc/codecs/pcm186x.c switch (reg) { reg 21 sound/soc/codecs/pcm3060.c unsigned int reg; reg 48 sound/soc/codecs/pcm3060.c reg = PCM3060_REG67; reg 50 sound/soc/codecs/pcm3060.c reg = PCM3060_REG72; reg 52 sound/soc/codecs/pcm3060.c regmap_update_bits(priv->regmap, reg, PCM3060_REG_CSEL, val); reg 63 sound/soc/codecs/pcm3060.c unsigned int reg; reg 99 sound/soc/codecs/pcm3060.c reg = PCM3060_REG67; reg 101 sound/soc/codecs/pcm3060.c reg = PCM3060_REG72; reg 103 sound/soc/codecs/pcm3060.c regmap_update_bits(priv->regmap, reg, PCM3060_REG_MASK_FMT, val); reg 116 sound/soc/codecs/pcm3060.c unsigned int reg; reg 158 sound/soc/codecs/pcm3060.c reg = PCM3060_REG67; reg 160 sound/soc/codecs/pcm3060.c reg = PCM3060_REG72; reg 162 sound/soc/codecs/pcm3060.c regmap_update_bits(priv->regmap, reg, PCM3060_REG_MASK_MS, val); reg 262 sound/soc/codecs/pcm3060.c static bool pcm3060_reg_writeable(struct device *dev, unsigned int reg) reg 264 sound/soc/codecs/pcm3060.c return (reg >= PCM3060_REG64); reg 267 sound/soc/codecs/pcm3060.c static bool pcm3060_reg_readable(struct device *dev, unsigned int reg) reg 269 sound/soc/codecs/pcm3060.c return (reg >= PCM3060_REG64); reg 272 sound/soc/codecs/pcm3060.c static bool pcm3060_reg_volatile(struct device *dev, unsigned int reg) reg 275 sound/soc/codecs/pcm3060.c return (reg == PCM3060_REG64); reg 321 sound/soc/codecs/pcm3168a.c u32 fmt, reg, mask, shift; reg 365 sound/soc/codecs/pcm3168a.c reg = PCM3168A_DAC_PWR_MST_FMT; reg 369 sound/soc/codecs/pcm3168a.c reg = PCM3168A_ADC_MST_FMT; reg 377 sound/soc/codecs/pcm3168a.c regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift); reg 423 sound/soc/codecs/pcm3168a.c u32 val, mask, shift, reg; reg 434 sound/soc/codecs/pcm3168a.c reg = PCM3168A_DAC_PWR_MST_FMT; reg 439 sound/soc/codecs/pcm3168a.c reg = PCM3168A_ADC_MST_FMT; reg 518 sound/soc/codecs/pcm3168a.c regmap_update_bits(pcm3168a->regmap, reg, mask, val); reg 528 sound/soc/codecs/pcm3168a.c regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift); reg 658 sound/soc/codecs/pcm3168a.c static bool pcm3168a_readable_register(struct device *dev, unsigned int reg) reg 660 sound/soc/codecs/pcm3168a.c if (reg >= PCM3168A_RST_SMODE) reg 666 sound/soc/codecs/pcm3168a.c static bool pcm3168a_volatile_register(struct device *dev, unsigned int reg) reg 668 sound/soc/codecs/pcm3168a.c switch (reg) { reg 677 sound/soc/codecs/pcm3168a.c static bool pcm3168a_writeable_register(struct device *dev, unsigned int reg) reg 679 sound/soc/codecs/pcm3168a.c if (reg < PCM3168A_RST_SMODE) reg 682 sound/soc/codecs/pcm3168a.c switch (reg) { reg 121 sound/soc/codecs/pcm512x.c static bool pcm512x_readable(struct device *dev, unsigned int reg) reg 123 sound/soc/codecs/pcm512x.c switch (reg) { reg 196 sound/soc/codecs/pcm512x.c return reg < 0xff; reg 200 sound/soc/codecs/pcm512x.c static bool pcm512x_volatile(struct device *dev, unsigned int reg) reg 202 sound/soc/codecs/pcm512x.c switch (reg) { reg 217 sound/soc/codecs/pcm512x.c return reg < 0xff; reg 201 sound/soc/codecs/rk3328_codec.c playback_open_list[i].reg, reg 258 sound/soc/codecs/rk3328_codec.c playback_close_list[i].reg, reg 386 sound/soc/codecs/rk3328_codec.c static bool rk3328_codec_write_read_reg(struct device *dev, unsigned int reg) reg 388 sound/soc/codecs/rk3328_codec.c switch (reg) { reg 408 sound/soc/codecs/rk3328_codec.c static bool rk3328_codec_volatile_reg(struct device *dev, unsigned int reg) reg 410 sound/soc/codecs/rk3328_codec.c switch (reg) { reg 205 sound/soc/codecs/rk3328_codec.h unsigned int reg; reg 26 sound/soc/codecs/rl6231.c int rl6231_get_pre_div(struct regmap *map, unsigned int reg, int sft) reg 30 sound/soc/codecs/rl6231.c regmap_read(map, reg, &val); reg 30 sound/soc/codecs/rl6231.h int rl6231_get_pre_div(struct regmap *map, unsigned int reg, int sft); reg 16 sound/soc/codecs/rl6347a.c int rl6347a_hw_write(void *context, unsigned int reg, unsigned int value) reg 24 sound/soc/codecs/rl6347a.c if (reg <= 0xff) { reg 25 sound/soc/codecs/rl6347a.c rl6347a_hw_write(client, RL6347A_COEF_INDEX, reg); reg 27 sound/soc/codecs/rl6347a.c if (reg == rl6347a->index_cache[i].reg) { reg 33 sound/soc/codecs/rl6347a.c reg = RL6347A_PROC_COEF; reg 36 sound/soc/codecs/rl6347a.c data[0] = (reg >> 24) & 0xff; reg 37 sound/soc/codecs/rl6347a.c data[1] = (reg >> 16) & 0xff; reg 43 sound/soc/codecs/rl6347a.c data[2] = ((reg >> 8) & 0xff) | ((value >> 8) & 0xff); reg 59 sound/soc/codecs/rl6347a.c int rl6347a_hw_read(void *context, unsigned int reg, unsigned int *value) reg 68 sound/soc/codecs/rl6347a.c if (reg <= 0xff) { reg 69 sound/soc/codecs/rl6347a.c rl6347a_hw_write(client, RL6347A_COEF_INDEX, reg); reg 70 sound/soc/codecs/rl6347a.c reg = RL6347A_PROC_COEF; reg 73 sound/soc/codecs/rl6347a.c reg = reg | 0x80000; reg 74 sound/soc/codecs/rl6347a.c vid = (reg >> 8) & 0xfff; reg 77 sound/soc/codecs/rl6347a.c index = (reg >> 8) & 0xf; reg 78 sound/soc/codecs/rl6347a.c reg = (reg & ~0xf0f) | index; reg 80 sound/soc/codecs/rl6347a.c be_reg = cpu_to_be32(reg); reg 28 sound/soc/codecs/rl6347a.h int rl6347a_hw_write(void *context, unsigned int reg, unsigned int value); reg 29 sound/soc/codecs/rl6347a.h int rl6347a_hw_read(void *context, unsigned int reg, unsigned int *value); reg 691 sound/soc/codecs/rt1011.c static bool rt1011_volatile_register(struct device *dev, unsigned int reg) reg 693 sound/soc/codecs/rt1011.c switch (reg) { reg 770 sound/soc/codecs/rt1011.c static bool rt1011_readable_register(struct device *dev, unsigned int reg) reg 772 sound/soc/codecs/rt1011.c switch (reg) { reg 1091 sound/soc/codecs/rt1011.c static bool rt1011_validate_bq_drc_coeff(unsigned short reg) reg 1093 sound/soc/codecs/rt1011.c if ((reg == RT1011_DAC_SET_1) | reg 1094 sound/soc/codecs/rt1011.c (reg >= RT1011_ADC_SET && reg <= RT1011_ADC_SET_1) | reg 1095 sound/soc/codecs/rt1011.c (reg == RT1011_ADC_SET_4) | (reg == RT1011_ADC_SET_5) | reg 1096 sound/soc/codecs/rt1011.c (reg == RT1011_MIXER_1) | reg 1097 sound/soc/codecs/rt1011.c (reg == RT1011_A_TIMING_1) | (reg >= RT1011_POWER_7 && reg 1098 sound/soc/codecs/rt1011.c reg <= RT1011_POWER_8) | reg 1099 sound/soc/codecs/rt1011.c (reg == RT1011_CLASS_D_POS) | (reg == RT1011_ANALOG_CTRL) | reg 1100 sound/soc/codecs/rt1011.c (reg >= RT1011_SPK_TEMP_PROTECT_0 && reg 1101 sound/soc/codecs/rt1011.c reg <= RT1011_SPK_TEMP_PROTECT_6) | reg 1102 sound/soc/codecs/rt1011.c (reg >= RT1011_SPK_PRO_DC_DET_5 && reg <= RT1011_BAT_GAIN_1) | reg 1103 sound/soc/codecs/rt1011.c (reg >= RT1011_RT_DRC_CROSS && reg <= RT1011_RT_DRC_POS_8) | reg 1104 sound/soc/codecs/rt1011.c (reg >= RT1011_CROSS_BQ_SET_1 && reg <= RT1011_BQ_10_A2_15_0) | reg 1105 sound/soc/codecs/rt1011.c (reg >= RT1011_SMART_BOOST_TIMING_1 && reg 1106 sound/soc/codecs/rt1011.c reg <= RT1011_SMART_BOOST_TIMING_36) | reg 1107 sound/soc/codecs/rt1011.c (reg == RT1011_SINE_GEN_REG_1) | reg 1108 sound/soc/codecs/rt1011.c (reg >= RT1011_STP_ALPHA_RECIPROCAL_MSB && reg 1109 sound/soc/codecs/rt1011.c reg <= RT1011_BQ_6_PARAMS_CHECK_5) | reg 1110 sound/soc/codecs/rt1011.c (reg >= RT1011_BQ_7_PARAMS_CHECK_1 && reg 1111 sound/soc/codecs/rt1011.c reg <= RT1011_BQ_10_PARAMS_CHECK_5)) reg 1147 sound/soc/codecs/rt1011.c params[i].reg = bq_drc_info[i].reg; reg 1189 sound/soc/codecs/rt1011.c bq_drc_info[i].reg = params[i].reg; reg 1194 sound/soc/codecs/rt1011.c if (bq_drc_info[i].reg == 0) reg 1196 sound/soc/codecs/rt1011.c else if (rt1011_validate_bq_drc_coeff(bq_drc_info[i].reg)) { reg 1197 sound/soc/codecs/rt1011.c snd_soc_component_write(component, bq_drc_info[i].reg, reg 638 sound/soc/codecs/rt1011.h unsigned short reg; reg 253 sound/soc/codecs/rt1305.c static bool rt1305_volatile_register(struct device *dev, unsigned int reg) reg 258 sound/soc/codecs/rt1305.c if (reg >= rt1305_ranges[i].range_min && reg 259 sound/soc/codecs/rt1305.c reg <= rt1305_ranges[i].range_max) { reg 264 sound/soc/codecs/rt1305.c switch (reg) { reg 305 sound/soc/codecs/rt1305.c static bool rt1305_readable_register(struct device *dev, unsigned int reg) reg 310 sound/soc/codecs/rt1305.c if (reg >= rt1305_ranges[i].range_min && reg 311 sound/soc/codecs/rt1305.c reg <= rt1305_ranges[i].range_max) { reg 316 sound/soc/codecs/rt1305.c switch (reg) { reg 205 sound/soc/codecs/rt1308.c static bool rt1308_volatile_register(struct device *dev, unsigned int reg) reg 207 sound/soc/codecs/rt1308.c switch (reg) { reg 261 sound/soc/codecs/rt1308.c static bool rt1308_readable_register(struct device *dev, unsigned int reg) reg 263 sound/soc/codecs/rt1308.c switch (reg) { reg 216 sound/soc/codecs/rt274.c static bool rt274_volatile_register(struct device *dev, unsigned int reg) reg 218 sound/soc/codecs/rt274.c switch (reg) { reg 260 sound/soc/codecs/rt274.c static bool rt274_readable_register(struct device *dev, unsigned int reg) reg 262 sound/soc/codecs/rt274.c switch (reg) { reg 344 sound/soc/codecs/rt274.c snd_soc_component_write(component, rt274->index_cache[i].reg, reg 115 sound/soc/codecs/rt286.c static bool rt286_volatile_register(struct device *dev, unsigned int reg) reg 117 sound/soc/codecs/rt286.c switch (reg) { reg 131 sound/soc/codecs/rt286.c static bool rt286_readable_register(struct device *dev, unsigned int reg) reg 133 sound/soc/codecs/rt286.c switch (reg) { reg 193 sound/soc/codecs/rt286.c snd_soc_component_write(component, rt286->index_cache[i].reg, reg 1172 sound/soc/codecs/rt286.c regmap_write(rt286->regmap, rt286->index_cache[i].reg, reg 1175 sound/soc/codecs/rt286.c regmap_write(rt286->regmap, rt286_reg[i].reg, reg 116 sound/soc/codecs/rt298.c static bool rt298_volatile_register(struct device *dev, unsigned int reg) reg 118 sound/soc/codecs/rt298.c switch (reg) { reg 135 sound/soc/codecs/rt298.c static bool rt298_readable_register(struct device *dev, unsigned int reg) reg 137 sound/soc/codecs/rt298.c switch (reg) { reg 200 sound/soc/codecs/rt298.c snd_soc_component_write(component, rt298->index_cache[i].reg, reg 503 sound/soc/codecs/rt298.c nid = (w->reg >> 20) & 0xff; reg 1213 sound/soc/codecs/rt298.c regmap_write(rt298->regmap, rt298->index_cache[i].reg, reg 1216 sound/soc/codecs/rt298.c regmap_write(rt298->regmap, rt298_reg[i].reg, reg 147 sound/soc/codecs/rt5514.c static bool rt5514_volatile_register(struct device *dev, unsigned int reg) reg 149 sound/soc/codecs/rt5514.c switch (reg) { reg 159 sound/soc/codecs/rt5514.c static bool rt5514_readable_register(struct device *dev, unsigned int reg) reg 161 sound/soc/codecs/rt5514.c switch (reg) { reg 217 sound/soc/codecs/rt5514.c unsigned int reg) reg 219 sound/soc/codecs/rt5514.c switch (reg) { reg 1118 sound/soc/codecs/rt5514.c static int rt5514_i2c_read(void *context, unsigned int reg, unsigned int *val) reg 1123 sound/soc/codecs/rt5514.c regmap_read(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val); reg 1128 sound/soc/codecs/rt5514.c static int rt5514_i2c_write(void *context, unsigned int reg, unsigned int val) reg 1133 sound/soc/codecs/rt5514.c regmap_write(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val); reg 159 sound/soc/codecs/rt5616.c static bool rt5616_volatile_register(struct device *dev, unsigned int reg) reg 164 sound/soc/codecs/rt5616.c if (reg >= rt5616_ranges[i].range_min && reg 165 sound/soc/codecs/rt5616.c reg <= rt5616_ranges[i].range_max) reg 169 sound/soc/codecs/rt5616.c switch (reg) { reg 186 sound/soc/codecs/rt5616.c static bool rt5616_readable_register(struct device *dev, unsigned int reg) reg 191 sound/soc/codecs/rt5616.c if (reg >= rt5616_ranges[i].range_min && reg 192 sound/soc/codecs/rt5616.c reg <= rt5616_ranges[i].range_max) reg 196 sound/soc/codecs/rt5616.c switch (reg) { reg 71 sound/soc/codecs/rt5631.c unsigned int reg, unsigned int value) reg 73 sound/soc/codecs/rt5631.c snd_soc_component_write(component, RT5631_INDEX_ADD, reg); reg 81 sound/soc/codecs/rt5631.c unsigned int reg) reg 85 sound/soc/codecs/rt5631.c snd_soc_component_write(component, RT5631_INDEX_ADD, reg); reg 96 sound/soc/codecs/rt5631.c static bool rt5631_volatile_register(struct device *dev, unsigned int reg) reg 98 sound/soc/codecs/rt5631.c switch (reg) { reg 110 sound/soc/codecs/rt5631.c static bool rt5631_readable_register(struct device *dev, unsigned int reg) reg 112 sound/soc/codecs/rt5631.c switch (reg) { reg 286 sound/soc/codecs/rt5631.c unsigned int reg; reg 288 sound/soc/codecs/rt5631.c reg = snd_soc_component_read32(component, RT5631_GLOBAL_CLK_CTRL); reg 289 sound/soc/codecs/rt5631.c return reg & RT5631_SYSCLK_SOUR_SEL_PLL; reg 304 sound/soc/codecs/rt5631.c unsigned int reg; reg 306 sound/soc/codecs/rt5631.c reg = snd_soc_component_read32(component, RT5631_OUTMIXER_L_CTRL); reg 307 sound/soc/codecs/rt5631.c return !(reg & RT5631_M_DAC_L_TO_OUTMIXER_L); reg 314 sound/soc/codecs/rt5631.c unsigned int reg; reg 316 sound/soc/codecs/rt5631.c reg = snd_soc_component_read32(component, RT5631_OUTMIXER_R_CTRL); reg 317 sound/soc/codecs/rt5631.c return !(reg & RT5631_M_DAC_R_TO_OUTMIXER_R); reg 324 sound/soc/codecs/rt5631.c unsigned int reg; reg 326 sound/soc/codecs/rt5631.c reg = snd_soc_component_read32(component, RT5631_SPK_MIXER_CTRL); reg 327 sound/soc/codecs/rt5631.c return !(reg & RT5631_M_DAC_L_TO_SPKMIXER_L); reg 334 sound/soc/codecs/rt5631.c unsigned int reg; reg 336 sound/soc/codecs/rt5631.c reg = snd_soc_component_read32(component, RT5631_SPK_MIXER_CTRL); reg 337 sound/soc/codecs/rt5631.c return !(reg & RT5631_M_DAC_R_TO_SPKMIXER_R); reg 344 sound/soc/codecs/rt5631.c unsigned int reg; reg 346 sound/soc/codecs/rt5631.c reg = snd_soc_component_read32(component, RT5631_ADC_REC_MIXER); reg 347 sound/soc/codecs/rt5631.c return !(reg & RT5631_M_MIC1_TO_RECMIXER_L); reg 354 sound/soc/codecs/rt5631.c unsigned int reg; reg 356 sound/soc/codecs/rt5631.c reg = snd_soc_component_read32(component, RT5631_ADC_REC_MIXER); reg 357 sound/soc/codecs/rt5631.c return !(reg & RT5631_M_MIC2_TO_RECMIXER_R); reg 172 sound/soc/codecs/rt5640.c static bool rt5640_volatile_register(struct device *dev, unsigned int reg) reg 177 sound/soc/codecs/rt5640.c if ((reg >= rt5640_ranges[i].window_start && reg 178 sound/soc/codecs/rt5640.c reg <= rt5640_ranges[i].window_start + reg 180 sound/soc/codecs/rt5640.c (reg >= rt5640_ranges[i].range_min && reg 181 sound/soc/codecs/rt5640.c reg <= rt5640_ranges[i].range_max)) reg 184 sound/soc/codecs/rt5640.c switch (reg) { reg 207 sound/soc/codecs/rt5640.c static bool rt5640_readable_register(struct device *dev, unsigned int reg) reg 212 sound/soc/codecs/rt5640.c if ((reg >= rt5640_ranges[i].window_start && reg 213 sound/soc/codecs/rt5640.c reg <= rt5640_ranges[i].window_start + reg 215 sound/soc/codecs/rt5640.c (reg >= rt5640_ranges[i].range_min && reg 216 sound/soc/codecs/rt5640.c reg <= rt5640_ranges[i].range_max)) reg 219 sound/soc/codecs/rt5640.c switch (reg) { reg 397 sound/soc/codecs/rt5645.c unsigned short reg; reg 402 sound/soc/codecs/rt5645.c __be16 reg; reg 447 sound/soc/codecs/rt5645.c static bool rt5645_volatile_register(struct device *dev, unsigned int reg) reg 452 sound/soc/codecs/rt5645.c if (reg >= rt5645_ranges[i].range_min && reg 453 sound/soc/codecs/rt5645.c reg <= rt5645_ranges[i].range_max) { reg 458 sound/soc/codecs/rt5645.c switch (reg) { reg 483 sound/soc/codecs/rt5645.c static bool rt5645_readable_register(struct device *dev, unsigned int reg) reg 488 sound/soc/codecs/rt5645.c if (reg >= rt5645_ranges[i].range_min && reg 489 sound/soc/codecs/rt5645.c reg <= rt5645_ranges[i].range_max) { reg 494 sound/soc/codecs/rt5645.c switch (reg) { reg 682 sound/soc/codecs/rt5645.c eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg); reg 689 sound/soc/codecs/rt5645.c static bool rt5645_validate_hweq(unsigned short reg) reg 691 sound/soc/codecs/rt5645.c if ((reg >= 0x1a4 && reg <= 0x1cd) | (reg >= 0x1e5 && reg <= 0x1f8) | reg 692 sound/soc/codecs/rt5645.c (reg == RT5645_EQ_CTRL2)) reg 708 sound/soc/codecs/rt5645.c rt5645->eq_param[i].reg = be16_to_cpu(eq_param[i].reg); reg 714 sound/soc/codecs/rt5645.c if (rt5645->eq_param[i].reg == 0) reg 716 sound/soc/codecs/rt5645.c else if (rt5645->eq_param[i].reg != RT5645_EQ_CTRL2) reg 723 sound/soc/codecs/rt5645.c if (!rt5645_validate_hweq(rt5645->eq_param[i].reg) && reg 724 sound/soc/codecs/rt5645.c rt5645->eq_param[i].reg != 0) reg 726 sound/soc/codecs/rt5645.c else if (rt5645->eq_param[i].reg == 0) reg 881 sound/soc/codecs/rt5645.c unsigned int reg, shift, val; reg 885 sound/soc/codecs/rt5645.c reg = RT5645_ASRC_3; reg 889 sound/soc/codecs/rt5645.c reg = RT5645_ASRC_3; reg 893 sound/soc/codecs/rt5645.c reg = RT5645_ASRC_2; reg 897 sound/soc/codecs/rt5645.c reg = RT5645_ASRC_2; reg 901 sound/soc/codecs/rt5645.c reg = RT5645_ASRC_2; reg 905 sound/soc/codecs/rt5645.c reg = RT5645_ASRC_2; reg 912 sound/soc/codecs/rt5645.c val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; reg 931 sound/soc/codecs/rt5645.c if (rt5645_validate_hweq(rt5645->eq_param[i].reg)) reg 932 sound/soc/codecs/rt5645.c regmap_write(rt5645->regmap, rt5645->eq_param[i].reg, reg 135 sound/soc/codecs/rt5651.c static bool rt5651_volatile_register(struct device *dev, unsigned int reg) reg 140 sound/soc/codecs/rt5651.c if ((reg >= rt5651_ranges[i].window_start && reg 141 sound/soc/codecs/rt5651.c reg <= rt5651_ranges[i].window_start + reg 143 sound/soc/codecs/rt5651.c (reg >= rt5651_ranges[i].range_min && reg 144 sound/soc/codecs/rt5651.c reg <= rt5651_ranges[i].range_max)) { reg 149 sound/soc/codecs/rt5651.c switch (reg) { reg 166 sound/soc/codecs/rt5651.c static bool rt5651_readable_register(struct device *dev, unsigned int reg) reg 171 sound/soc/codecs/rt5651.c if ((reg >= rt5651_ranges[i].window_start && reg 172 sound/soc/codecs/rt5651.c reg <= rt5651_ranges[i].window_start + reg 174 sound/soc/codecs/rt5651.c (reg >= rt5651_ranges[i].range_min && reg 175 sound/soc/codecs/rt5651.c reg <= rt5651_ranges[i].range_max)) { reg 180 sound/soc/codecs/rt5651.c switch (reg) { reg 531 sound/soc/codecs/rt5659.c static bool rt5659_volatile_register(struct device *dev, unsigned int reg) reg 533 sound/soc/codecs/rt5659.c switch (reg) { reg 634 sound/soc/codecs/rt5659.c static bool rt5659_readable_register(struct device *dev, unsigned int reg) reg 636 sound/soc/codecs/rt5659.c switch (reg) { reg 1710 sound/soc/codecs/rt5659.c unsigned int reg, shift, val; reg 1715 sound/soc/codecs/rt5659.c reg = RT5659_ASRC_3; reg 1719 sound/soc/codecs/rt5659.c reg = RT5659_ASRC_3; reg 1723 sound/soc/codecs/rt5659.c reg = RT5659_ASRC_2; reg 1727 sound/soc/codecs/rt5659.c reg = RT5659_ASRC_2; reg 1731 sound/soc/codecs/rt5659.c reg = RT5659_ASRC_2; reg 1735 sound/soc/codecs/rt5659.c reg = RT5659_ASRC_2; reg 1742 sound/soc/codecs/rt5659.c val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; reg 153 sound/soc/codecs/rt5660.c static bool rt5660_volatile_register(struct device *dev, unsigned int reg) reg 158 sound/soc/codecs/rt5660.c if ((reg >= rt5660_ranges[i].window_start && reg 159 sound/soc/codecs/rt5660.c reg <= rt5660_ranges[i].window_start + reg 161 sound/soc/codecs/rt5660.c (reg >= rt5660_ranges[i].range_min && reg 162 sound/soc/codecs/rt5660.c reg <= rt5660_ranges[i].range_max)) reg 165 sound/soc/codecs/rt5660.c switch (reg) { reg 180 sound/soc/codecs/rt5660.c static bool rt5660_readable_register(struct device *dev, unsigned int reg) reg 185 sound/soc/codecs/rt5660.c if ((reg >= rt5660_ranges[i].window_start && reg 186 sound/soc/codecs/rt5660.c reg <= rt5660_ranges[i].window_start + reg 188 sound/soc/codecs/rt5660.c (reg >= rt5660_ranges[i].range_min && reg 189 sound/soc/codecs/rt5660.c reg <= rt5660_ranges[i].range_max)) reg 192 sound/soc/codecs/rt5660.c switch (reg) { reg 747 sound/soc/codecs/rt5663.c static bool rt5663_volatile_register(struct device *dev, unsigned int reg) reg 749 sound/soc/codecs/rt5663.c switch (reg) { reg 802 sound/soc/codecs/rt5663.c static bool rt5663_readable_register(struct device *dev, unsigned int reg) reg 804 sound/soc/codecs/rt5663.c switch (reg) { reg 1066 sound/soc/codecs/rt5663.c static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg) reg 1068 sound/soc/codecs/rt5663.c switch (reg) { reg 1121 sound/soc/codecs/rt5663.c static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg) reg 1123 sound/soc/codecs/rt5663.c switch (reg) { reg 1369 sound/soc/codecs/rt5663.c return rt5663_readable_register(dev, reg); reg 2086 sound/soc/codecs/rt5663.c unsigned int reg, shift, val; reg 2093 sound/soc/codecs/rt5663.c reg = RT5663_ASRC_3; reg 2097 sound/soc/codecs/rt5663.c reg = RT5663_ASRC_2; reg 2106 sound/soc/codecs/rt5663.c reg = RT5663_ASRC_2; reg 2110 sound/soc/codecs/rt5663.c reg = RT5663_ASRC_2; reg 2118 sound/soc/codecs/rt5663.c val = (snd_soc_component_read32(component, reg) >> shift) & 0x7; reg 2970 sound/soc/codecs/rt5663.c unsigned int val = 0, reg; reg 3015 sound/soc/codecs/rt5663.c reg = RT5663_TDM_2; reg 3018 sound/soc/codecs/rt5663.c reg = RT5663_TDM_1; reg 3025 sound/soc/codecs/rt5663.c snd_soc_component_update_bits(component, reg, RT5663_TDM_MODE_MASK | reg 3036 sound/soc/codecs/rt5663.c unsigned int reg; reg 3041 sound/soc/codecs/rt5663.c reg = RT5663_TDM_9; reg 3043 sound/soc/codecs/rt5663.c reg = RT5663_TDM_5; reg 3047 sound/soc/codecs/rt5663.c snd_soc_component_update_bits(component, reg, reg 3052 sound/soc/codecs/rt5663.c snd_soc_component_update_bits(component, reg, reg 3057 sound/soc/codecs/rt5663.c snd_soc_component_update_bits(component, reg, reg 3062 sound/soc/codecs/rt5663.c snd_soc_component_update_bits(component, reg, reg 464 sound/soc/codecs/rt5665.c static bool rt5665_volatile_register(struct device *dev, unsigned int reg) reg 466 sound/soc/codecs/rt5665.c switch (reg) { reg 489 sound/soc/codecs/rt5665.c static bool rt5665_readable_register(struct device *dev, unsigned int reg) reg 491 sound/soc/codecs/rt5665.c switch (reg) { reg 1536 sound/soc/codecs/rt5665.c unsigned int reg, shift, val; reg 1541 sound/soc/codecs/rt5665.c reg = RT5665_ASRC_3; reg 1545 sound/soc/codecs/rt5665.c reg = RT5665_ASRC_3; reg 1549 sound/soc/codecs/rt5665.c reg = RT5665_ASRC_3; reg 1553 sound/soc/codecs/rt5665.c reg = RT5665_ASRC_3; reg 1557 sound/soc/codecs/rt5665.c reg = RT5665_ASRC_2; reg 1561 sound/soc/codecs/rt5665.c reg = RT5665_ASRC_2; reg 1565 sound/soc/codecs/rt5665.c reg = RT5665_ASRC_2; reg 1569 sound/soc/codecs/rt5665.c reg = RT5665_ASRC_2; reg 1576 sound/soc/codecs/rt5665.c val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; reg 388 sound/soc/codecs/rt5668.c static bool rt5668_volatile_register(struct device *dev, unsigned int reg) reg 390 sound/soc/codecs/rt5668.c switch (reg) { reg 416 sound/soc/codecs/rt5668.c static bool rt5668_readable_register(struct device *dev, unsigned int reg) reg 418 sound/soc/codecs/rt5668.c switch (reg) { reg 1191 sound/soc/codecs/rt5668.c int ref, val, reg, idx = -EINVAL; reg 1205 sound/soc/codecs/rt5668.c reg = RT5668_PLL_TRACK_3; reg 1207 sound/soc/codecs/rt5668.c reg = RT5668_PLL_TRACK_2; reg 1209 sound/soc/codecs/rt5668.c snd_soc_component_update_bits(component, reg, reg 1233 sound/soc/codecs/rt5668.c unsigned int reg, shift, val; reg 1239 sound/soc/codecs/rt5668.c reg = RT5668_PLL_TRACK_3; reg 1243 sound/soc/codecs/rt5668.c reg = RT5668_PLL_TRACK_2; reg 1250 sound/soc/codecs/rt5668.c val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; reg 213 sound/soc/codecs/rt5670.c static bool rt5670_volatile_register(struct device *dev, unsigned int reg) reg 218 sound/soc/codecs/rt5670.c if ((reg >= rt5670_ranges[i].window_start && reg 219 sound/soc/codecs/rt5670.c reg <= rt5670_ranges[i].window_start + reg 221 sound/soc/codecs/rt5670.c (reg >= rt5670_ranges[i].range_min && reg 222 sound/soc/codecs/rt5670.c reg <= rt5670_ranges[i].range_max)) { reg 227 sound/soc/codecs/rt5670.c switch (reg) { reg 260 sound/soc/codecs/rt5670.c static bool rt5670_readable_register(struct device *dev, unsigned int reg) reg 265 sound/soc/codecs/rt5670.c if ((reg >= rt5670_ranges[i].window_start && reg 266 sound/soc/codecs/rt5670.c reg <= rt5670_ranges[i].window_start + reg 268 sound/soc/codecs/rt5670.c (reg >= rt5670_ranges[i].range_min && reg 269 sound/soc/codecs/rt5670.c reg <= rt5670_ranges[i].range_max)) { reg 274 sound/soc/codecs/rt5670.c switch (reg) { reg 730 sound/soc/codecs/rt5670.c unsigned int reg, shift, val; reg 734 sound/soc/codecs/rt5670.c reg = RT5670_ASRC_3; reg 738 sound/soc/codecs/rt5670.c reg = RT5670_ASRC_3; reg 742 sound/soc/codecs/rt5670.c reg = RT5670_ASRC_5; reg 746 sound/soc/codecs/rt5670.c reg = RT5670_ASRC_2; reg 750 sound/soc/codecs/rt5670.c reg = RT5670_ASRC_2; reg 754 sound/soc/codecs/rt5670.c reg = RT5670_ASRC_2; reg 758 sound/soc/codecs/rt5670.c reg = RT5670_ASRC_2; reg 765 sound/soc/codecs/rt5670.c val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; reg 279 sound/soc/codecs/rt5677.c static bool rt5677_volatile_register(struct device *dev, unsigned int reg) reg 284 sound/soc/codecs/rt5677.c if (reg >= rt5677_ranges[i].range_min && reg 285 sound/soc/codecs/rt5677.c reg <= rt5677_ranges[i].range_max) { reg 290 sound/soc/codecs/rt5677.c switch (reg) { reg 326 sound/soc/codecs/rt5677.c static bool rt5677_readable_register(struct device *dev, unsigned int reg) reg 331 sound/soc/codecs/rt5677.c if (reg >= rt5677_ranges[i].range_min && reg 332 sound/soc/codecs/rt5677.c reg <= rt5677_ranges[i].range_max) { reg 337 sound/soc/codecs/rt5677.c switch (reg) { reg 664 sound/soc/codecs/rt5677.c unsigned int reg, unsigned int value) reg 666 sound/soc/codecs/rt5677.c return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2, reg 680 sound/soc/codecs/rt5677.c struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value) reg 682 sound/soc/codecs/rt5677.c int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2, reg 952 sound/soc/codecs/rt5677.c unsigned int reg, shift, val; reg 954 sound/soc/codecs/rt5677.c if (source->reg == RT5677_ASRC_1) { reg 957 sound/soc/codecs/rt5677.c reg = RT5677_ASRC_4; reg 961 sound/soc/codecs/rt5677.c reg = RT5677_ASRC_4; reg 965 sound/soc/codecs/rt5677.c reg = RT5677_ASRC_4; reg 969 sound/soc/codecs/rt5677.c reg = RT5677_ASRC_4; reg 978 sound/soc/codecs/rt5677.c reg = RT5677_ASRC_6; reg 982 sound/soc/codecs/rt5677.c reg = RT5677_ASRC_6; reg 986 sound/soc/codecs/rt5677.c reg = RT5677_ASRC_5; reg 990 sound/soc/codecs/rt5677.c reg = RT5677_ASRC_5; reg 994 sound/soc/codecs/rt5677.c reg = RT5677_ASRC_5; reg 998 sound/soc/codecs/rt5677.c reg = RT5677_ASRC_5; reg 1002 sound/soc/codecs/rt5677.c reg = RT5677_ASRC_3; reg 1006 sound/soc/codecs/rt5677.c reg = RT5677_ASRC_3; reg 1010 sound/soc/codecs/rt5677.c reg = RT5677_ASRC_3; reg 1018 sound/soc/codecs/rt5677.c regmap_read(rt5677->regmap, reg, &val); reg 4789 sound/soc/codecs/rt5677.c static int rt5677_read(void *context, unsigned int reg, unsigned int *val) reg 4795 sound/soc/codecs/rt5677.c if (reg > 0xff) { reg 4798 sound/soc/codecs/rt5677.c reg & 0xff); reg 4802 sound/soc/codecs/rt5677.c rt5677_dsp_mode_i2c_read(rt5677, reg, val); reg 4805 sound/soc/codecs/rt5677.c regmap_read(rt5677->regmap_physical, reg, val); reg 4811 sound/soc/codecs/rt5677.c static int rt5677_write(void *context, unsigned int reg, unsigned int val) reg 4817 sound/soc/codecs/rt5677.c if (reg > 0xff) { reg 4820 sound/soc/codecs/rt5677.c reg & 0xff); reg 4825 sound/soc/codecs/rt5677.c rt5677_dsp_mode_i2c_write(rt5677, reg, val); reg 4828 sound/soc/codecs/rt5677.c regmap_write(rt5677->regmap_physical, reg, val); reg 399 sound/soc/codecs/rt5682.c static bool rt5682_volatile_register(struct device *dev, unsigned int reg) reg 401 sound/soc/codecs/rt5682.c switch (reg) { reg 427 sound/soc/codecs/rt5682.c static bool rt5682_readable_register(struct device *dev, unsigned int reg) reg 429 sound/soc/codecs/rt5682.c switch (reg) { reg 1217 sound/soc/codecs/rt5682.c int ref, val, reg, idx = -EINVAL; reg 1232 sound/soc/codecs/rt5682.c reg = RT5682_PLL_TRACK_3; reg 1234 sound/soc/codecs/rt5682.c reg = RT5682_PLL_TRACK_2; reg 1236 sound/soc/codecs/rt5682.c snd_soc_component_update_bits(component, reg, reg 1270 sound/soc/codecs/rt5682.c unsigned int reg, shift, val; reg 1276 sound/soc/codecs/rt5682.c reg = RT5682_PLL_TRACK_3; reg 1280 sound/soc/codecs/rt5682.c reg = RT5682_PLL_TRACK_2; reg 1287 sound/soc/codecs/rt5682.c val = (snd_soc_component_read32(component, reg) >> shift) & 0xf; reg 544 sound/soc/codecs/sgtl5000.c int reg; reg 548 sound/soc/codecs/sgtl5000.c reg = snd_soc_component_read32(component, SGTL5000_CHIP_DAC_VOL); reg 551 sound/soc/codecs/sgtl5000.c l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; reg 554 sound/soc/codecs/sgtl5000.c r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT; reg 597 sound/soc/codecs/sgtl5000.c int reg; reg 613 sound/soc/codecs/sgtl5000.c reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT | reg 616 sound/soc/codecs/sgtl5000.c snd_soc_component_write(component, SGTL5000_CHIP_DAC_VOL, reg); reg 636 sound/soc/codecs/sgtl5000.c u16 reg = snd_soc_component_read32(component, SGTL5000_DAP_AVC_THRESHOLD); reg 639 sound/soc/codecs/sgtl5000.c if (!reg) { reg 646 sound/soc/codecs/sgtl5000.c for (i = 0; avc_thr_db2reg[i] > reg; i++) reg 669 sound/soc/codecs/sgtl5000.c u16 reg; reg 674 sound/soc/codecs/sgtl5000.c reg = avc_thr_db2reg[db]; reg 675 sound/soc/codecs/sgtl5000.c snd_soc_component_write(component, SGTL5000_DAP_AVC_THRESHOLD, reg); reg 1192 sound/soc/codecs/sgtl5000.c static bool sgtl5000_volatile(struct device *dev, unsigned int reg) reg 1194 sound/soc/codecs/sgtl5000.c switch (reg) { reg 1204 sound/soc/codecs/sgtl5000.c static bool sgtl5000_readable(struct device *dev, unsigned int reg) reg 1206 sound/soc/codecs/sgtl5000.c switch (reg) { reg 1460 sound/soc/codecs/sgtl5000.c u16 reg; reg 1485 sound/soc/codecs/sgtl5000.c reg = ((sgtl5000->lrclk_strength) << SGTL5000_PAD_I2S_LRCLK_SHIFT | reg 1488 sound/soc/codecs/sgtl5000.c snd_soc_component_write(component, SGTL5000_CHIP_PAD_STRENGTH, reg); reg 1564 sound/soc/codecs/sgtl5000.c index = sgtl5000_reg_defaults[i].reg; reg 1577 sound/soc/codecs/sgtl5000.c int ret, reg, rev; reg 1622 sound/soc/codecs/sgtl5000.c ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®); reg 1628 sound/soc/codecs/sgtl5000.c if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != reg 1631 sound/soc/codecs/sgtl5000.c "Device with ID register %x is not a sgtl5000\n", reg); reg 1636 sound/soc/codecs/sgtl5000.c rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; reg 44 sound/soc/codecs/ssm2602.c { .reg = 0x00, .def = 0x0097 }, reg 45 sound/soc/codecs/ssm2602.c { .reg = 0x01, .def = 0x0097 }, reg 46 sound/soc/codecs/ssm2602.c { .reg = 0x02, .def = 0x0079 }, reg 47 sound/soc/codecs/ssm2602.c { .reg = 0x03, .def = 0x0079 }, reg 48 sound/soc/codecs/ssm2602.c { .reg = 0x04, .def = 0x000a }, reg 49 sound/soc/codecs/ssm2602.c { .reg = 0x05, .def = 0x0008 }, reg 50 sound/soc/codecs/ssm2602.c { .reg = 0x06, .def = 0x009f }, reg 51 sound/soc/codecs/ssm2602.c { .reg = 0x07, .def = 0x000a }, reg 52 sound/soc/codecs/ssm2602.c { .reg = 0x08, .def = 0x0000 }, reg 53 sound/soc/codecs/ssm2602.c { .reg = 0x09, .def = 0x0000 } reg 629 sound/soc/codecs/ssm2602.c static bool ssm2602_register_volatile(struct device *dev, unsigned int reg) reg 631 sound/soc/codecs/ssm2602.c return reg == SSM2602_RESET; reg 120 sound/soc/codecs/ssm4567.c static bool ssm4567_readable_reg(struct device *dev, unsigned int reg) reg 122 sound/soc/codecs/ssm4567.c switch (reg) { reg 131 sound/soc/codecs/ssm4567.c static bool ssm4567_writeable_reg(struct device *dev, unsigned int reg) reg 133 sound/soc/codecs/ssm4567.c switch (reg) { reg 146 sound/soc/codecs/ssm4567.c static bool ssm4567_volatile_reg(struct device *dev, unsigned int reg) reg 148 sound/soc/codecs/ssm4567.c switch (reg) { reg 116 sound/soc/codecs/sta529.c static bool sta529_readable(struct device *dev, unsigned int reg) reg 118 sound/soc/codecs/sta529.c switch (reg) { reg 169 sound/soc/codecs/stac9766.c unsigned short reg; reg 175 sound/soc/codecs/stac9766.c reg = AC97_PCM_FRONT_DAC_RATE; reg 177 sound/soc/codecs/stac9766.c reg = AC97_PCM_LR_ADC_RATE; reg 179 sound/soc/codecs/stac9766.c return snd_soc_component_write(component, reg, runtime->rate); reg 187 sound/soc/codecs/stac9766.c unsigned short reg; reg 194 sound/soc/codecs/stac9766.c reg = AC97_PCM_FRONT_DAC_RATE; reg 196 sound/soc/codecs/stac9766.c return snd_soc_component_write(component, reg, runtime->rate); reg 84 sound/soc/codecs/sti-sas.c static int sti_sas_read_reg(void *context, unsigned int reg, reg 91 sound/soc/codecs/sti-sas.c status = regmap_read(drvdata->dac.regmap, reg, &val); reg 98 sound/soc/codecs/sti-sas.c static int sti_sas_write_reg(void *context, unsigned int reg, reg 104 sound/soc/codecs/sti-sas.c status = regmap_write(drvdata->dac.regmap, reg, value); reg 244 sound/soc/codecs/sti-sas.c static bool sti_sas_volatile_register(struct device *dev, unsigned int reg) reg 246 sound/soc/codecs/sti-sas.c if (reg == STIH407_AUDIO_GLUE_CTRL) reg 398 sound/soc/codecs/tas2552.c u8 reg, mask, val; reg 415 sound/soc/codecs/tas2552.c reg = TAS2552_CFG_1; reg 425 sound/soc/codecs/tas2552.c reg = TAS2552_PDM_CFG; reg 434 sound/soc/codecs/tas2552.c snd_soc_component_update_bits(component, reg, mask, val); reg 123 sound/soc/codecs/tas5086.c static int tas5086_register_size(struct device *dev, unsigned int reg) reg 125 sound/soc/codecs/tas5086.c switch (reg) { reg 133 sound/soc/codecs/tas5086.c dev_err(dev, "Unsupported register address: %d\n", reg); reg 137 sound/soc/codecs/tas5086.c static bool tas5086_accessible_reg(struct device *dev, unsigned int reg) reg 139 sound/soc/codecs/tas5086.c switch (reg) { reg 149 sound/soc/codecs/tas5086.c static bool tas5086_volatile_reg(struct device *dev, unsigned int reg) reg 151 sound/soc/codecs/tas5086.c switch (reg) { reg 160 sound/soc/codecs/tas5086.c static bool tas5086_writeable_reg(struct device *dev, unsigned int reg) reg 162 sound/soc/codecs/tas5086.c return tas5086_accessible_reg(dev, reg) && (reg != TAS5086_DEV_ID); reg 165 sound/soc/codecs/tas5086.c static int tas5086_reg_write(void *context, unsigned int reg, reg 173 sound/soc/codecs/tas5086.c size = tas5086_register_size(&client->dev, reg); reg 177 sound/soc/codecs/tas5086.c buf[0] = reg; reg 193 sound/soc/codecs/tas5086.c static int tas5086_reg_read(void *context, unsigned int reg, reg 203 sound/soc/codecs/tas5086.c size = tas5086_register_size(&client->dev, reg); reg 207 sound/soc/codecs/tas5086.c send_buf = reg; reg 56 sound/soc/codecs/tas571x.c static int tas571x_register_size(struct tas571x_private *priv, unsigned int reg) reg 58 sound/soc/codecs/tas571x.c switch (reg) { reg 76 sound/soc/codecs/tas571x.c static int tas571x_reg_write(void *context, unsigned int reg, reg 85 sound/soc/codecs/tas571x.c size = tas571x_register_size(priv, reg); reg 86 sound/soc/codecs/tas571x.c buf[0] = reg; reg 102 sound/soc/codecs/tas571x.c static int tas571x_reg_read(void *context, unsigned int reg, reg 113 sound/soc/codecs/tas571x.c size = tas571x_register_size(priv, reg); reg 114 sound/soc/codecs/tas571x.c send_buf = reg; reg 146 sound/soc/codecs/tas571x.c unsigned int reg, const long values[], size_t len) reg 156 sound/soc/codecs/tas571x.c buf[0] = reg; reg 177 sound/soc/codecs/tas571x.c unsigned int reg, long values[], size_t len) reg 190 sound/soc/codecs/tas571x.c send_buf = reg; reg 361 sound/soc/codecs/tas571x.c #define BIQUAD_COEFS(xname, reg) \ reg 367 sound/soc/codecs/tas571x.c .private_value = reg | (5 << 16) } reg 454 sound/soc/codecs/tas5720.c static bool tas5720_is_volatile_reg(struct device *dev, unsigned int reg) reg 456 sound/soc/codecs/tas5720.c switch (reg) { reg 407 sound/soc/codecs/tas6424.c unsigned int reg; reg 410 sound/soc/codecs/tas6424.c ret = regmap_read(tas6424->regmap, TAS6424_CHANNEL_FAULT, ®); reg 416 sound/soc/codecs/tas6424.c if (!reg) { reg 417 sound/soc/codecs/tas6424.c tas6424->last_cfault = reg; reg 427 sound/soc/codecs/tas6424.c if ((reg & TAS6424_FAULT_OC_CH1) && !(tas6424->last_cfault & TAS6424_FAULT_OC_CH1)) reg 430 sound/soc/codecs/tas6424.c if ((reg & TAS6424_FAULT_OC_CH2) && !(tas6424->last_cfault & TAS6424_FAULT_OC_CH2)) reg 433 sound/soc/codecs/tas6424.c if ((reg & TAS6424_FAULT_OC_CH3) && !(tas6424->last_cfault & TAS6424_FAULT_OC_CH3)) reg 436 sound/soc/codecs/tas6424.c if ((reg & TAS6424_FAULT_OC_CH4) && !(tas6424->last_cfault & TAS6424_FAULT_OC_CH4)) reg 439 sound/soc/codecs/tas6424.c if ((reg & TAS6424_FAULT_DC_CH1) && !(tas6424->last_cfault & TAS6424_FAULT_DC_CH1)) reg 442 sound/soc/codecs/tas6424.c if ((reg & TAS6424_FAULT_DC_CH2) && !(tas6424->last_cfault & TAS6424_FAULT_DC_CH2)) reg 445 sound/soc/codecs/tas6424.c if ((reg & TAS6424_FAULT_DC_CH3) && !(tas6424->last_cfault & TAS6424_FAULT_DC_CH3)) reg 448 sound/soc/codecs/tas6424.c if ((reg & TAS6424_FAULT_DC_CH4) && !(tas6424->last_cfault & TAS6424_FAULT_DC_CH4)) reg 452 sound/soc/codecs/tas6424.c tas6424->last_cfault = reg; reg 455 sound/soc/codecs/tas6424.c ret = regmap_read(tas6424->regmap, TAS6424_GLOB_FAULT1, ®); reg 468 sound/soc/codecs/tas6424.c reg &= TAS6424_FAULT_PVDD_OV | reg 473 sound/soc/codecs/tas6424.c if (!reg) { reg 474 sound/soc/codecs/tas6424.c tas6424->last_fault1 = reg; reg 478 sound/soc/codecs/tas6424.c if ((reg & TAS6424_FAULT_PVDD_OV) && !(tas6424->last_fault1 & TAS6424_FAULT_PVDD_OV)) reg 481 sound/soc/codecs/tas6424.c if ((reg & TAS6424_FAULT_VBAT_OV) && !(tas6424->last_fault1 & TAS6424_FAULT_VBAT_OV)) reg 484 sound/soc/codecs/tas6424.c if ((reg & TAS6424_FAULT_PVDD_UV) && !(tas6424->last_fault1 & TAS6424_FAULT_PVDD_UV)) reg 487 sound/soc/codecs/tas6424.c if ((reg & TAS6424_FAULT_VBAT_UV) && !(tas6424->last_fault1 & TAS6424_FAULT_VBAT_UV)) reg 491 sound/soc/codecs/tas6424.c tas6424->last_fault1 = reg; reg 494 sound/soc/codecs/tas6424.c ret = regmap_read(tas6424->regmap, TAS6424_GLOB_FAULT2, ®); reg 500 sound/soc/codecs/tas6424.c reg &= TAS6424_FAULT_OTSD | reg 506 sound/soc/codecs/tas6424.c if (!reg) { reg 507 sound/soc/codecs/tas6424.c tas6424->last_fault2 = reg; reg 511 sound/soc/codecs/tas6424.c if ((reg & TAS6424_FAULT_OTSD) && !(tas6424->last_fault2 & TAS6424_FAULT_OTSD)) reg 514 sound/soc/codecs/tas6424.c if ((reg & TAS6424_FAULT_OTSD_CH1) && !(tas6424->last_fault2 & TAS6424_FAULT_OTSD_CH1)) reg 517 sound/soc/codecs/tas6424.c if ((reg & TAS6424_FAULT_OTSD_CH2) && !(tas6424->last_fault2 & TAS6424_FAULT_OTSD_CH2)) reg 520 sound/soc/codecs/tas6424.c if ((reg & TAS6424_FAULT_OTSD_CH3) && !(tas6424->last_fault2 & TAS6424_FAULT_OTSD_CH3)) reg 523 sound/soc/codecs/tas6424.c if ((reg & TAS6424_FAULT_OTSD_CH4) && !(tas6424->last_fault2 & TAS6424_FAULT_OTSD_CH4)) reg 527 sound/soc/codecs/tas6424.c tas6424->last_fault2 = reg; reg 530 sound/soc/codecs/tas6424.c ret = regmap_read(tas6424->regmap, TAS6424_WARN, ®); reg 536 sound/soc/codecs/tas6424.c reg &= TAS6424_WARN_VDD_UV | reg 544 sound/soc/codecs/tas6424.c if (!reg) { reg 545 sound/soc/codecs/tas6424.c tas6424->last_warn = reg; reg 549 sound/soc/codecs/tas6424.c if ((reg & TAS6424_WARN_VDD_UV) && !(tas6424->last_warn & TAS6424_WARN_VDD_UV)) reg 552 sound/soc/codecs/tas6424.c if ((reg & TAS6424_WARN_VDD_POR) && !(tas6424->last_warn & TAS6424_WARN_VDD_POR)) reg 555 sound/soc/codecs/tas6424.c if ((reg & TAS6424_WARN_VDD_OTW) && !(tas6424->last_warn & TAS6424_WARN_VDD_OTW)) reg 558 sound/soc/codecs/tas6424.c if ((reg & TAS6424_WARN_VDD_OTW_CH1) && !(tas6424->last_warn & TAS6424_WARN_VDD_OTW_CH1)) reg 561 sound/soc/codecs/tas6424.c if ((reg & TAS6424_WARN_VDD_OTW_CH2) && !(tas6424->last_warn & TAS6424_WARN_VDD_OTW_CH2)) reg 564 sound/soc/codecs/tas6424.c if ((reg & TAS6424_WARN_VDD_OTW_CH3) && !(tas6424->last_warn & TAS6424_WARN_VDD_OTW_CH3)) reg 567 sound/soc/codecs/tas6424.c if ((reg & TAS6424_WARN_VDD_OTW_CH4) && !(tas6424->last_warn & TAS6424_WARN_VDD_OTW_CH4)) reg 571 sound/soc/codecs/tas6424.c tas6424->last_warn = reg; reg 613 sound/soc/codecs/tas6424.c static bool tas6424_is_writable_reg(struct device *dev, unsigned int reg) reg 615 sound/soc/codecs/tas6424.c switch (reg) { reg 642 sound/soc/codecs/tas6424.c static bool tas6424_is_volatile_reg(struct device *dev, unsigned int reg) reg 644 sound/soc/codecs/tas6424.c switch (reg) { reg 92 sound/soc/codecs/tda7419.c static bool tda7419_readable_reg(struct device *dev, unsigned int reg) reg 130 sound/soc/codecs/tda7419.c unsigned int reg, rreg, mask, thresh; reg 136 sound/soc/codecs/tda7419.c if (tvc->reg == tvc->rreg) reg 183 sound/soc/codecs/tda7419.c unsigned int reg = tvc->reg; reg 192 sound/soc/codecs/tda7419.c ret = snd_soc_component_read(component, reg, &val); reg 231 sound/soc/codecs/tda7419.c unsigned int reg = tvc->reg; reg 241 sound/soc/codecs/tda7419.c ret = snd_soc_component_update_bits(component, reg, reg 258 sound/soc/codecs/tda7419.c {.reg = xreg, .rreg = xreg, .mask = xmask, .min = xmin, \ reg 264 sound/soc/codecs/tda7419.c {.reg = xregl, .rreg = xregr, .mask = xmask, .min = xmin, \ reg 609 sound/soc/codecs/tda7419.c tda7419_regmap_defaults[i].reg, reg 182 sound/soc/codecs/tfa9879.c static bool tfa9879_volatile_reg(struct device *dev, unsigned int reg) reg 184 sound/soc/codecs/tfa9879.c return reg == TFA9879_MISC_STATUS; reg 292 sound/soc/codecs/tfa9879.c tfa9879_regs[i].reg, tfa9879_regs[i].def); reg 81 sound/soc/codecs/tlv320aic23.c u16 val, reg; reg 94 sound/soc/codecs/tlv320aic23.c reg = snd_soc_component_read32(component, TLV320AIC23_ANLG) & (~0x1C0); reg 95 sound/soc/codecs/tlv320aic23.c snd_soc_component_write(component, TLV320AIC23_ANLG, reg | (val << 6)); reg 410 sound/soc/codecs/tlv320aic23.c u16 reg; reg 412 sound/soc/codecs/tlv320aic23.c reg = snd_soc_component_read32(component, TLV320AIC23_DIGT); reg 414 sound/soc/codecs/tlv320aic23.c reg |= TLV320AIC23_DACM_MUTE; reg 417 sound/soc/codecs/tlv320aic23.c reg &= ~TLV320AIC23_DACM_MUTE; reg 419 sound/soc/codecs/tlv320aic23.c snd_soc_component_write(component, TLV320AIC23_DIGT, reg); reg 482 sound/soc/codecs/tlv320aic23.c u16 reg = snd_soc_component_read32(component, TLV320AIC23_PWR) & 0x17f; reg 487 sound/soc/codecs/tlv320aic23.c reg &= ~(TLV320AIC23_DEVICE_PWR_OFF | TLV320AIC23_OSC_OFF | \ reg 489 sound/soc/codecs/tlv320aic23.c snd_soc_component_write(component, TLV320AIC23_PWR, reg); reg 496 sound/soc/codecs/tlv320aic23.c reg | TLV320AIC23_CLK_OFF); reg 71 sound/soc/codecs/tlv320aic26.c u16 reg; reg 115 sound/soc/codecs/tlv320aic26.c reg = 0x8000 | qval << 11 | pval << 8 | jval << 2; reg 116 sound/soc/codecs/tlv320aic26.c snd_soc_component_write(component, AIC26_REG_PLL_PROG1, reg); reg 117 sound/soc/codecs/tlv320aic26.c reg = dval << 2; reg 118 sound/soc/codecs/tlv320aic26.c snd_soc_component_write(component, AIC26_REG_PLL_PROG2, reg); reg 122 sound/soc/codecs/tlv320aic26.c reg = 0x0800; reg 124 sound/soc/codecs/tlv320aic26.c reg = 0x2000; reg 125 sound/soc/codecs/tlv320aic26.c snd_soc_component_update_bits(component, AIC26_REG_AUDIO_CTRL3, 0xf800, reg); reg 128 sound/soc/codecs/tlv320aic26.c reg = wlen | aic26->datfm | (divisor << 3) | divisor; reg 129 sound/soc/codecs/tlv320aic26.c snd_soc_component_update_bits(component, AIC26_REG_AUDIO_CTRL1, 0xfff, reg); reg 141 sound/soc/codecs/tlv320aic26.c u16 reg; reg 147 sound/soc/codecs/tlv320aic26.c reg = 0x8080; reg 149 sound/soc/codecs/tlv320aic26.c reg = 0; reg 150 sound/soc/codecs/tlv320aic26.c snd_soc_component_update_bits(component, AIC26_REG_DAC_GAIN, 0x8000, reg); reg 298 sound/soc/codecs/tlv320aic26.c int ret, reg; reg 309 sound/soc/codecs/tlv320aic26.c reg = snd_soc_component_read32(component, AIC26_REG_AUDIO_CTRL3); reg 310 sound/soc/codecs/tlv320aic26.c reg &= ~0xf800; reg 311 sound/soc/codecs/tlv320aic26.c reg |= 0x0800; /* set master mode */ reg 312 sound/soc/codecs/tlv320aic26.c snd_soc_component_write(component, AIC26_REG_AUDIO_CTRL3, reg); reg 79 sound/soc/codecs/tlv320aic31xx.c static bool aic31xx_volatile(struct device *dev, unsigned int reg) reg 81 sound/soc/codecs/tlv320aic31xx.c switch (reg) { reg 99 sound/soc/codecs/tlv320aic31xx.c static bool aic31xx_writeable(struct device *dev, unsigned int reg) reg 101 sound/soc/codecs/tlv320aic31xx.c switch (reg) { reg 327 sound/soc/codecs/tlv320aic31xx.c static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg, reg 333 sound/soc/codecs/tlv320aic31xx.c int ret = regmap_read(aic31xx->regmap, reg, &bits); reg 337 sound/soc/codecs/tlv320aic31xx.c ret = regmap_read(aic31xx->regmap, reg, &bits); reg 343 sound/soc/codecs/tlv320aic31xx.c __func__, reg, bits, wbits, ret, mask, reg 350 sound/soc/codecs/tlv320aic31xx.c #define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg)) reg 357 sound/soc/codecs/tlv320aic31xx.c unsigned int reg = AIC31XX_DACFLAG1; reg 360 sound/soc/codecs/tlv320aic31xx.c switch (WIDGET_BIT(w->reg, w->shift)) { reg 381 sound/soc/codecs/tlv320aic31xx.c reg = AIC31XX_ADCFLAG; reg 391 sound/soc/codecs/tlv320aic31xx.c return aic31xx_wait_bits(aic31xx, reg, mask, mask, 5000, 100); reg 393 sound/soc/codecs/tlv320aic31xx.c return aic31xx_wait_bits(aic31xx, reg, mask, 0, 5000, 100); reg 42 sound/soc/codecs/tlv320aic31xx.h #define AIC31XX_REG(page, reg) ((page * 128) + reg) reg 22 sound/soc/codecs/tlv320aic32x4-clk.c unsigned int reg; reg 44 sound/soc/codecs/tlv320aic32x4-clk.c unsigned int reg; reg 296 sound/soc/codecs/tlv320aic32x4-clk.c return regmap_update_bits(div->regmap, div->reg, reg 304 sound/soc/codecs/tlv320aic32x4-clk.c regmap_update_bits(div->regmap, div->reg, reg 318 sound/soc/codecs/tlv320aic32x4-clk.c return regmap_update_bits(div->regmap, div->reg, reg 341 sound/soc/codecs/tlv320aic32x4-clk.c regmap_read(div->regmap, div->reg, &val); reg 389 sound/soc/codecs/tlv320aic32x4-clk.c .reg = 0, reg 397 sound/soc/codecs/tlv320aic32x4-clk.c .reg = 0, reg 404 sound/soc/codecs/tlv320aic32x4-clk.c .reg = AIC32X4_NDAC, reg 411 sound/soc/codecs/tlv320aic32x4-clk.c .reg = AIC32X4_MDAC, reg 418 sound/soc/codecs/tlv320aic32x4-clk.c .reg = AIC32X4_NADC, reg 425 sound/soc/codecs/tlv320aic32x4-clk.c .reg = AIC32X4_MADC, reg 433 sound/soc/codecs/tlv320aic32x4-clk.c .reg = AIC32X4_BCLKN, reg 457 sound/soc/codecs/tlv320aic32x4-clk.c priv->reg = desc->reg; reg 20 sound/soc/codecs/tlv320aic32x4.h #define AIC32X4_REG(page, reg) ((page * 128) + reg) reg 128 sound/soc/codecs/tlv320aic3x.c static bool aic3x_volatile_reg(struct device *dev, unsigned int reg) reg 130 sound/soc/codecs/tlv320aic3x.c switch (reg) { reg 151 sound/soc/codecs/tlv320aic3x.c #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ reg 152 sound/soc/codecs/tlv320aic3x.c SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \ reg 166 sound/soc/codecs/tlv320aic3x.c unsigned int reg = mc->reg; reg 189 sound/soc/codecs/tlv320aic3x.c change = snd_soc_component_test_bits(component, reg, mask, val); reg 192 sound/soc/codecs/tlv320aic3x.c update.reg = reg; reg 161 sound/soc/codecs/tlv320dac33.c unsigned reg) reg 165 sound/soc/codecs/tlv320dac33.c if (reg >= DAC33_CACHEREGNUM) reg 168 sound/soc/codecs/tlv320dac33.c return cache[reg]; reg 172 sound/soc/codecs/tlv320dac33.c u8 reg, u8 value) reg 176 sound/soc/codecs/tlv320dac33.c if (reg >= DAC33_CACHEREGNUM) reg 179 sound/soc/codecs/tlv320dac33.c cache[reg] = value; reg 182 sound/soc/codecs/tlv320dac33.c static int dac33_read(struct snd_soc_component *component, unsigned int reg, reg 188 sound/soc/codecs/tlv320dac33.c *value = reg & 0xff; reg 195 sound/soc/codecs/tlv320dac33.c value[0] = dac33_read_reg_cache(component, reg); reg 199 sound/soc/codecs/tlv320dac33.c dac33_write_reg_cache(component, reg, val); reg 202 sound/soc/codecs/tlv320dac33.c value[0] = dac33_read_reg_cache(component, reg); reg 208 sound/soc/codecs/tlv320dac33.c static int dac33_write(struct snd_soc_component *component, unsigned int reg, reg 220 sound/soc/codecs/tlv320dac33.c data[0] = reg & 0xff; reg 235 sound/soc/codecs/tlv320dac33.c static int dac33_write_locked(struct snd_soc_component *component, unsigned int reg, reg 242 sound/soc/codecs/tlv320dac33.c ret = dac33_write(component, reg, value); reg 249 sound/soc/codecs/tlv320dac33.c static int dac33_write16(struct snd_soc_component *component, unsigned int reg, reg 262 sound/soc/codecs/tlv320dac33.c data[0] = reg & 0xff; reg 324 sound/soc/codecs/tlv320dac33.c u8 reg; reg 327 sound/soc/codecs/tlv320dac33.c ret = dac33_read(component, DAC33_DEVICE_ID_MSB + i, ®); reg 337 sound/soc/codecs/tlv320dac33.c u8 reg; reg 339 sound/soc/codecs/tlv320dac33.c reg = dac33_read_reg_cache(component, DAC33_PWR_CTRL); reg 341 sound/soc/codecs/tlv320dac33.c reg |= DAC33_PDNALLB; reg 343 sound/soc/codecs/tlv320dac33.c reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB | reg 345 sound/soc/codecs/tlv320dac33.c dac33_write(component, DAC33_PWR_CTRL, reg); reg 350 sound/soc/codecs/tlv320dac33.c u8 reg; reg 353 sound/soc/codecs/tlv320dac33.c reg = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B); reg 354 sound/soc/codecs/tlv320dac33.c reg &= ~DAC33_BCLKON; reg 355 sound/soc/codecs/tlv320dac33.c dac33_write(component, DAC33_SER_AUDIOIF_CTRL_B, reg); reg 358 sound/soc/codecs/tlv320dac33.c reg = dac33_read_reg_cache(component, DAC33_PWR_CTRL); reg 359 sound/soc/codecs/tlv320dac33.c reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB); reg 360 sound/soc/codecs/tlv320dac33.c dac33_write(component, DAC33_PWR_CTRL, reg); reg 720 sound/soc/codecs/tlv320dac33.c u8 reg; reg 742 sound/soc/codecs/tlv320dac33.c reg = dac33_read_reg_cache(component, DAC33_FIFO_CTRL_A); reg 743 sound/soc/codecs/tlv320dac33.c reg |= DAC33_FIFOFLUSH; reg 744 sound/soc/codecs/tlv320dac33.c dac33_write(component, DAC33_FIFO_CTRL_A, reg); reg 770 sound/soc/codecs/tlv320dac33.c u8 reg; reg 774 sound/soc/codecs/tlv320dac33.c dac33_read(component, DAC33_INT_OSC_STATUS, ®); reg 775 sound/soc/codecs/tlv320dac33.c } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--); reg 776 sound/soc/codecs/tlv320dac33.c if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) reg 114 sound/soc/codecs/ts3a227e.c static bool ts3a227e_readable_reg(struct device *dev, unsigned int reg) reg 116 sound/soc/codecs/ts3a227e.c switch (reg) { reg 124 sound/soc/codecs/ts3a227e.c static bool ts3a227e_writeable_reg(struct device *dev, unsigned int reg) reg 126 sound/soc/codecs/ts3a227e.c switch (reg) { reg 135 sound/soc/codecs/ts3a227e.c static bool ts3a227e_volatile_reg(struct device *dev, unsigned int reg) reg 137 sound/soc/codecs/ts3a227e.c switch (reg) { reg 54 sound/soc/codecs/tscs42xx.c static bool tscs42xx_volatile(struct device *dev, unsigned int reg) reg 56 sound/soc/codecs/tscs42xx.c switch (reg) { reg 72 sound/soc/codecs/tscs42xx.c static bool tscs42xx_precious(struct device *dev, unsigned int reg) reg 74 sound/soc/codecs/tscs42xx.c switch (reg) { reg 1278 sound/soc/codecs/tscs42xx.c unsigned int reg; reg 1280 sound/soc/codecs/tscs42xx.c ret = regmap_read(tscs42xx->regmap, R_DEVIDH, ®); reg 1284 sound/soc/codecs/tscs42xx.c val = reg << 8; reg 1285 sound/soc/codecs/tscs42xx.c ret = regmap_read(tscs42xx->regmap, R_DEVIDL, ®); reg 1289 sound/soc/codecs/tscs42xx.c val |= reg; reg 158 sound/soc/codecs/tscs454.c static bool tscs454_volatile(struct device *dev, unsigned int reg) reg 160 sound/soc/codecs/tscs454.c switch (reg) { reg 183 sound/soc/codecs/tscs454.c static bool tscs454_writable(struct device *dev, unsigned int reg) reg 185 sound/soc/codecs/tscs454.c switch (reg) { reg 203 sound/soc/codecs/tscs454.c static bool tscs454_readable(struct device *dev, unsigned int reg) reg 205 sound/soc/codecs/tscs454.c switch (reg) { reg 223 sound/soc/codecs/tscs454.c static bool tscs454_precious(struct device *dev, unsigned int reg) reg 225 sound/soc/codecs/tscs454.c switch (reg) { reg 767 sound/soc/codecs/tscs454.c unsigned int reg; reg 774 sound/soc/codecs/tscs454.c reg = R_I2SP1CTL; reg 777 sound/soc/codecs/tscs454.c reg = R_I2SP2CTL; reg 780 sound/soc/codecs/tscs454.c reg = R_I2SP3CTL; reg 790 sound/soc/codecs/tscs454.c ret = snd_soc_component_update_bits(component, reg, mask, val); reg 2743 sound/soc/codecs/tscs454.c unsigned int reg; reg 2748 sound/soc/codecs/tscs454.c reg = R_TDMCTL0; reg 2751 sound/soc/codecs/tscs454.c reg = R_PCMP2CTL0; reg 2754 sound/soc/codecs/tscs454.c reg = R_PCMP3CTL0; reg 2763 sound/soc/codecs/tscs454.c reg, FM_TDMCTL0_BDELAY, delay); reg 2776 sound/soc/codecs/tscs454.c unsigned int reg; reg 2782 sound/soc/codecs/tscs454.c reg = R_I2SP1CTL; reg 2785 sound/soc/codecs/tscs454.c reg = R_I2SP2CTL; reg 2788 sound/soc/codecs/tscs454.c reg = R_I2SP3CTL; reg 2826 sound/soc/codecs/tscs454.c reg, FM_I2SPCTL_FORMAT, val); reg 2840 sound/soc/codecs/tscs454.c unsigned int reg; reg 2846 sound/soc/codecs/tscs454.c reg = R_I2SP1CTL; reg 2849 sound/soc/codecs/tscs454.c reg = R_I2SP2CTL; reg 2852 sound/soc/codecs/tscs454.c reg = R_I2SP3CTL; reg 2880 sound/soc/codecs/tscs454.c ret = snd_soc_component_update_bits(component, reg, reg 2976 sound/soc/codecs/tscs454.c unsigned int reg; reg 2991 sound/soc/codecs/tscs454.c reg = R_PCMP2CTL1; reg 2994 sound/soc/codecs/tscs454.c reg = R_PCMP3CTL1; reg 3031 sound/soc/codecs/tscs454.c ret = snd_soc_component_write(component, reg, val); reg 3044 sound/soc/codecs/tscs454.c unsigned int reg; reg 3098 sound/soc/codecs/tscs454.c reg = R_I2S1MRATE; reg 3101 sound/soc/codecs/tscs454.c reg = R_I2S2MRATE; reg 3104 sound/soc/codecs/tscs454.c reg = R_I2S3MRATE; reg 3112 sound/soc/codecs/tscs454.c ret = snd_soc_component_update_bits(component, reg, reg 3127 sound/soc/codecs/tscs454.c unsigned int reg; reg 3153 sound/soc/codecs/tscs454.c reg = R_I2SP1CTL; reg 3156 sound/soc/codecs/tscs454.c reg = R_I2SP2CTL; reg 3159 sound/soc/codecs/tscs454.c reg = R_I2SP3CTL; reg 3168 sound/soc/codecs/tscs454.c reg, FM_I2SPCTL_WL, width); reg 75 sound/soc/codecs/twl4030.c static unsigned int twl4030_read(struct snd_soc_component *component, unsigned int reg) reg 80 sound/soc/codecs/twl4030.c if (reg >= TWL4030_CACHEREGNUM) reg 83 sound/soc/codecs/twl4030.c switch (reg) { reg 90 sound/soc/codecs/twl4030.c value = twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL]; reg 93 sound/soc/codecs/twl4030.c twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &value, reg); reg 101 sound/soc/codecs/twl4030.c unsigned int reg) reg 106 sound/soc/codecs/twl4030.c switch (reg) { reg 140 sound/soc/codecs/twl4030.c static int twl4030_write(struct snd_soc_component *component, unsigned int reg, reg 146 sound/soc/codecs/twl4030.c switch (reg) { reg 153 sound/soc/codecs/twl4030.c twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL] = value; reg 159 sound/soc/codecs/twl4030.c if (twl4030_can_write_to_chip(twl4030, reg)) reg 160 sound/soc/codecs/twl4030.c return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg); reg 243 sound/soc/codecs/twl4030.c u8 reg, byte; reg 281 sound/soc/codecs/twl4030.c reg = twl4030_read(component, TWL4030_REG_MISC_SET_1); reg 283 sound/soc/codecs/twl4030.c reg | TWL4030_SMOOTH_ANAVOL_EN); reg 298 sound/soc/codecs/twl4030.c reg = twl4030_read(component, TWL4030_REG_HS_POPN_SET); reg 299 sound/soc/codecs/twl4030.c reg &= ~TWL4030_RAMP_DELAY; reg 300 sound/soc/codecs/twl4030.c reg |= (pdata->ramp_delay_value << 2); reg 301 sound/soc/codecs/twl4030.c twl4030_write(component, TWL4030_REG_HS_POPN_SET, reg); reg 306 sound/soc/codecs/twl4030.c reg = twl4030_read(component, TWL4030_REG_ANAMICL); reg 307 sound/soc/codecs/twl4030.c reg &= ~TWL4030_OFFSET_CNCL_SEL; reg 308 sound/soc/codecs/twl4030.c reg |= pdata->offset_cncl_path; reg 310 sound/soc/codecs/twl4030.c reg | TWL4030_CNCL_OFFSET_START); reg 552 sound/soc/codecs/twl4030.c #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \ reg 562 sound/soc/codecs/twl4030.c twl4030_write(component, reg, twl4030_read(component, reg)); \ reg 566 sound/soc/codecs/twl4030.c twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 0, reg); \ reg 578 sound/soc/codecs/twl4030.c static void handsfree_ramp(struct snd_soc_component *component, int reg, int ramp) reg 582 sound/soc/codecs/twl4030.c hs_ctl = twl4030_read(component, reg); reg 587 sound/soc/codecs/twl4030.c twl4030_write(component, reg, hs_ctl); reg 590 sound/soc/codecs/twl4030.c twl4030_write(component, reg, hs_ctl); reg 594 sound/soc/codecs/twl4030.c twl4030_write(component, reg, hs_ctl); reg 599 sound/soc/codecs/twl4030.c twl4030_write(component, reg, hs_ctl); reg 601 sound/soc/codecs/twl4030.c twl4030_write(component, reg, hs_ctl); reg 604 sound/soc/codecs/twl4030.c twl4030_write(component, reg, hs_ctl); reg 832 sound/soc/codecs/twl4030.c unsigned int reg = mc->reg; reg 839 sound/soc/codecs/twl4030.c (twl4030_read(component, reg) >> shift) & mask; reg 846 sound/soc/codecs/twl4030.c (twl4030_read(component, reg) >> rshift) & mask; reg 861 sound/soc/codecs/twl4030.c unsigned int reg = mc->reg; reg 881 sound/soc/codecs/twl4030.c return snd_soc_component_update_bits(component, reg, val_mask, val); reg 890 sound/soc/codecs/twl4030.c unsigned int reg = mc->reg; reg 897 sound/soc/codecs/twl4030.c (twl4030_read(component, reg) >> shift) & mask; reg 917 sound/soc/codecs/twl4030.c unsigned int reg = mc->reg; reg 937 sound/soc/codecs/twl4030.c err = snd_soc_component_update_bits(component, reg, val_mask, val); reg 1620 sound/soc/codecs/twl4030.c u8 reg, mask; reg 1622 sound/soc/codecs/twl4030.c reg = twl4030_read(component, TWL4030_REG_OPTION); reg 1630 sound/soc/codecs/twl4030.c reg |= mask; reg 1632 sound/soc/codecs/twl4030.c reg &= ~mask; reg 1634 sound/soc/codecs/twl4030.c twl4030_write(component, TWL4030_REG_OPTION, reg); reg 1890 sound/soc/codecs/twl4030.c u8 reg = twl4030_read(component, TWL4030_REG_AUDIO_IF); reg 1893 sound/soc/codecs/twl4030.c reg |= TWL4030_AIF_TRI_EN; reg 1895 sound/soc/codecs/twl4030.c reg &= ~TWL4030_AIF_TRI_EN; reg 1897 sound/soc/codecs/twl4030.c return twl4030_write(component, TWL4030_REG_AUDIO_IF, reg); reg 1905 sound/soc/codecs/twl4030.c u8 reg, mask; reg 1907 sound/soc/codecs/twl4030.c reg = twl4030_read(component, TWL4030_REG_OPTION); reg 1915 sound/soc/codecs/twl4030.c reg |= mask; reg 1917 sound/soc/codecs/twl4030.c reg &= ~mask; reg 1919 sound/soc/codecs/twl4030.c twl4030_write(component, TWL4030_REG_OPTION, reg); reg 2085 sound/soc/codecs/twl4030.c u8 reg = twl4030_read(component, TWL4030_REG_VOICE_IF); reg 2088 sound/soc/codecs/twl4030.c reg |= TWL4030_VIF_TRI_EN; reg 2090 sound/soc/codecs/twl4030.c reg &= ~TWL4030_VIF_TRI_EN; reg 2092 sound/soc/codecs/twl4030.c return twl4030_write(component, TWL4030_REG_VOICE_IF, reg); reg 97 sound/soc/codecs/twl6040.c static unsigned int twl6040_read(struct snd_soc_component *component, unsigned int reg) reg 103 sound/soc/codecs/twl6040.c if (reg >= TWL6040_CACHEREGNUM) reg 106 sound/soc/codecs/twl6040.c switch (reg) { reg 112 sound/soc/codecs/twl6040.c value = priv->dl12_cache[reg - TWL6040_REG_HSLCTL]; reg 115 sound/soc/codecs/twl6040.c value = twl6040_reg_read(twl6040, reg); reg 123 sound/soc/codecs/twl6040.c unsigned int reg) reg 127 sound/soc/codecs/twl6040.c switch (reg) { reg 142 sound/soc/codecs/twl6040.c u8 reg, u8 value) reg 146 sound/soc/codecs/twl6040.c switch (reg) { reg 152 sound/soc/codecs/twl6040.c priv->dl12_cache[reg - TWL6040_REG_HSLCTL] = value; reg 160 sound/soc/codecs/twl6040.c unsigned int reg, unsigned int value) reg 164 sound/soc/codecs/twl6040.c if (reg >= TWL6040_CACHEREGNUM) reg 167 sound/soc/codecs/twl6040.c twl6040_update_dl12_cache(component, reg, value); reg 168 sound/soc/codecs/twl6040.c if (twl6040_can_write_to_chip(component, reg)) reg 169 sound/soc/codecs/twl6040.c return twl6040_reg_write(twl6040, reg, value); reg 331 sound/soc/codecs/twl6040.c val = twl6040_read(component, e->reg); reg 64 sound/soc/codecs/uda134x.c static int uda134x_regmap_write(void *context, unsigned int reg, reg 72 sound/soc/codecs/uda134x.c switch (reg) { reg 76 sound/soc/codecs/uda134x.c data |= (reg - UDA134X_STATUS0) << 7; reg 83 sound/soc/codecs/uda134x.c data |= (reg - UDA134X_DATA000) << 6; reg 90 sound/soc/codecs/uda134x.c addr = (reg | UDA134X_EXTADDR_PREFIX); reg 62 sound/soc/codecs/uda1380.c unsigned int reg) reg 67 sound/soc/codecs/uda1380.c if (reg == UDA1380_RESET) reg 69 sound/soc/codecs/uda1380.c if (reg >= UDA1380_CACHEREGNUM) reg 71 sound/soc/codecs/uda1380.c return cache[reg]; reg 78 sound/soc/codecs/uda1380.c u16 reg, unsigned int value) reg 83 sound/soc/codecs/uda1380.c if (reg >= UDA1380_CACHEREGNUM) reg 85 sound/soc/codecs/uda1380.c if ((reg >= 0x10) && (cache[reg] != value)) reg 86 sound/soc/codecs/uda1380.c set_bit(reg - 0x10, &uda1380_cache_dirty); reg 87 sound/soc/codecs/uda1380.c cache[reg] = value; reg 93 sound/soc/codecs/uda1380.c static int uda1380_write(struct snd_soc_component *component, unsigned int reg, reg 104 sound/soc/codecs/uda1380.c data[0] = reg; reg 108 sound/soc/codecs/uda1380.c uda1380_write_reg_cache(component, reg, value); reg 113 sound/soc/codecs/uda1380.c if (!snd_soc_component_is_active(component) && (reg >= UDA1380_MVOL)) reg 115 sound/soc/codecs/uda1380.c pr_debug("uda1380: hw write %x val %x\n", reg, value); reg 126 sound/soc/codecs/uda1380.c if (reg >= 0x10) reg 127 sound/soc/codecs/uda1380.c clear_bit(reg - 0x10, &uda1380_cache_dirty); reg 136 sound/soc/codecs/uda1380.c int reg; reg 141 sound/soc/codecs/uda1380.c for (reg = 0; reg < UDA1380_MVOL; reg++) { reg 142 sound/soc/codecs/uda1380.c data[0] = reg; reg 143 sound/soc/codecs/uda1380.c data[1] = (cache[reg] & 0xff00) >> 8; reg 144 sound/soc/codecs/uda1380.c data[2] = cache[reg] & 0x00ff; reg 147 sound/soc/codecs/uda1380.c __func__, reg); reg 180 sound/soc/codecs/uda1380.c int bit, reg; reg 183 sound/soc/codecs/uda1380.c reg = 0x10 + bit; reg 184 sound/soc/codecs/uda1380.c pr_debug("uda1380: flush reg %x val %x:\n", reg, reg 185 sound/soc/codecs/uda1380.c uda1380_read_reg_cache(uda1380_component, reg)); reg 186 sound/soc/codecs/uda1380.c uda1380_write(uda1380_component, reg, reg 187 sound/soc/codecs/uda1380.c uda1380_read_reg_cache(uda1380_component, reg)); reg 592 sound/soc/codecs/uda1380.c int reg; reg 622 sound/soc/codecs/uda1380.c for (reg = UDA1380_MVOL; reg < UDA1380_CACHEREGNUM; reg++) reg 623 sound/soc/codecs/uda1380.c set_bit(reg - 0x10, &uda1380_cache_dirty); reg 428 sound/soc/codecs/wcd9335.c u16 reg; reg 1477 sound/soc/codecs/wcd9335.c unsigned int val, reg, sel; reg 1481 sound/soc/codecs/wcd9335.c switch (e->reg) { reg 1483 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_TX0_TX_PATH_CFG0; reg 1486 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_TX1_TX_PATH_CFG0; reg 1489 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_TX2_TX_PATH_CFG0; reg 1492 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_TX3_TX_PATH_CFG0; reg 1495 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_TX4_TX_PATH_CFG0; reg 1498 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_TX5_TX_PATH_CFG0; reg 1501 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_TX6_TX_PATH_CFG0; reg 1504 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_TX7_TX_PATH_CFG0; reg 1507 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_TX8_TX_PATH_CFG0; reg 1515 sound/soc/codecs/wcd9335.c snd_soc_component_update_bits(component, reg, reg 1527 sound/soc/codecs/wcd9335.c int reg, val; reg 1532 sound/soc/codecs/wcd9335.c if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0) reg 1533 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_RX0_RX_PATH_CFG0; reg 1534 sound/soc/codecs/wcd9335.c else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0) reg 1535 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_RX1_RX_PATH_CFG0; reg 1536 sound/soc/codecs/wcd9335.c else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0) reg 1537 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_RX2_RX_PATH_CFG0; reg 1542 sound/soc/codecs/wcd9335.c snd_soc_component_update_bits(component, reg, reg 2659 sound/soc/codecs/wcd9335.c wcd9335_codec_set_tx_hold(comp, w->reg, true); reg 2671 sound/soc/codecs/wcd9335.c int mux_sel, reg, mreg; reg 2679 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n; reg 2681 sound/soc/codecs/wcd9335.c mux_sel = snd_soc_component_read32(comp, reg) & 0x3; reg 2683 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4; reg 2684 sound/soc/codecs/wcd9335.c mreg = reg; reg 2685 sound/soc/codecs/wcd9335.c mux_sel = snd_soc_component_read32(comp, reg) >> 6; reg 2997 sound/soc/codecs/wcd9335.c unsigned short reg = 0; reg 3005 sound/soc/codecs/wcd9335.c reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8); reg 3008 sound/soc/codecs/wcd9335.c reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8); reg 3011 sound/soc/codecs/wcd9335.c regmap_read(wcd->if_regmap, reg, &val); reg 3013 sound/soc/codecs/wcd9335.c regmap_write(wcd->if_regmap, reg, reg 3047 sound/soc/codecs/wcd9335.c switch (w->reg) { reg 3094 sound/soc/codecs/wcd9335.c static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind) reg 3098 sound/soc/codecs/wcd9335.c switch (reg) { reg 3191 sound/soc/codecs/wcd9335.c u16 reg, int event) reg 3195 sound/soc/codecs/wcd9335.c int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind); reg 3210 sound/soc/codecs/wcd9335.c if ((reg != prim_int_reg) && reg 3213 sound/soc/codecs/wcd9335.c snd_soc_component_update_bits(comp, reg, reg 3303 sound/soc/codecs/wcd9335.c u16 reg; reg 3308 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_RX0_RX_PATH_CTL; reg 3311 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_RX1_RX_PATH_CTL; reg 3314 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_RX2_RX_PATH_CTL; reg 3317 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_RX3_RX_PATH_CTL; reg 3320 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_RX4_RX_PATH_CTL; reg 3323 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_RX5_RX_PATH_CTL; reg 3326 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_RX6_RX_PATH_CTL; reg 3329 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_RX7_RX_PATH_CTL; reg 3332 sound/soc/codecs/wcd9335.c reg = WCD9335_CDC_RX8_RX_PATH_CTL; reg 3343 sound/soc/codecs/wcd9335.c wcd9335_codec_enable_prim_interpolator(comp, reg, event); reg 3353 sound/soc/codecs/wcd9335.c wcd9335_codec_enable_prim_interpolator(comp, reg, event); reg 3788 sound/soc/codecs/wcd9335.c if (w->reg == WCD9335_ANA_LO_1_2) { reg 3796 sound/soc/codecs/wcd9335.c } else if (w->reg == WCD9335_ANA_LO_3_4) { reg 3973 sound/soc/codecs/wcd9335.c unsigned short reg = 0; reg 3988 sound/soc/codecs/wcd9335.c reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + reg 3991 sound/soc/codecs/wcd9335.c reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + reg 3994 sound/soc/codecs/wcd9335.c wcd->if_regmap, reg, &int_val); reg 4016 sound/soc/codecs/wcd9335.c reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + reg 4019 sound/soc/codecs/wcd9335.c reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + reg 4022 sound/soc/codecs/wcd9335.c wcd->if_regmap, reg, &int_val); reg 4026 sound/soc/codecs/wcd9335.c reg, int_val); reg 4837 sound/soc/codecs/wcd9335.c wcd9335_codec_reg_init[i].reg, reg 4937 sound/soc/codecs/wcd9335.c static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg) reg 4939 sound/soc/codecs/wcd9335.c switch (reg) { reg 81 sound/soc/codecs/wm2000.c static int wm2000_write(struct i2c_client *i2c, unsigned int reg, reg 85 sound/soc/codecs/wm2000.c return regmap_write(wm2000->regmap, reg, value); reg 100 sound/soc/codecs/wm2000.c unsigned int reg, u8 mask) reg 106 sound/soc/codecs/wm2000.c regmap_read(wm2000->regmap, reg, &val); reg 110 sound/soc/codecs/wm2000.c regmap_read(wm2000->regmap, reg, &val); reg 736 sound/soc/codecs/wm2000.c static bool wm2000_readable_reg(struct device *dev, unsigned int reg) reg 738 sound/soc/codecs/wm2000.c switch (reg) { reg 818 sound/soc/codecs/wm2000.c unsigned int reg; reg 854 sound/soc/codecs/wm2000.c ret = regmap_read(wm2000->regmap, WM2000_REG_ID1, ®); reg 859 sound/soc/codecs/wm2000.c id = reg << 8; reg 860 sound/soc/codecs/wm2000.c ret = regmap_read(wm2000->regmap, WM2000_REG_ID2, ®); reg 865 sound/soc/codecs/wm2000.c id |= reg & 0xff; reg 873 sound/soc/codecs/wm2000.c ret = regmap_read(wm2000->regmap, WM2000_REG_REVISON, ®); reg 878 sound/soc/codecs/wm2000.c dev_info(&i2c->dev, "revision %c\n", reg + 'A'); reg 509 sound/soc/codecs/wm2200.c static bool wm2200_volatile_register(struct device *dev, unsigned int reg) reg 514 sound/soc/codecs/wm2200.c if ((reg >= wm2200_ranges[i].window_start && reg 515 sound/soc/codecs/wm2200.c reg <= wm2200_ranges[i].window_start + reg 517 sound/soc/codecs/wm2200.c (reg >= wm2200_ranges[i].range_min && reg 518 sound/soc/codecs/wm2200.c reg <= wm2200_ranges[i].range_max)) reg 521 sound/soc/codecs/wm2200.c switch (reg) { reg 535 sound/soc/codecs/wm2200.c static bool wm2200_readable_register(struct device *dev, unsigned int reg) reg 540 sound/soc/codecs/wm2200.c if ((reg >= wm2200_ranges[i].window_start && reg 541 sound/soc/codecs/wm2200.c reg <= wm2200_ranges[i].window_start + reg 543 sound/soc/codecs/wm2200.c (reg >= wm2200_ranges[i].range_min && reg 544 sound/soc/codecs/wm2200.c reg <= wm2200_ranges[i].range_max)) reg 547 sound/soc/codecs/wm2200.c switch (reg) { reg 1079 sound/soc/codecs/wm2200.c #define WM2200_MUX_ENUM_DECL(name, reg) \ reg 1080 sound/soc/codecs/wm2200.c SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \ reg 2192 sound/soc/codecs/wm2200.c unsigned int reg; reg 2282 sound/soc/codecs/wm2200.c ret = regmap_read(wm2200->regmap, WM2200_SOFTWARE_RESET, ®); reg 2287 sound/soc/codecs/wm2200.c switch (reg) { reg 2292 sound/soc/codecs/wm2200.c dev_err(&i2c->dev, "Device is not a WM2200, ID is %x\n", reg); reg 2297 sound/soc/codecs/wm2200.c ret = regmap_read(wm2200->regmap, WM2200_DEVICE_REVISION, ®); reg 2303 sound/soc/codecs/wm2200.c wm2200->rev = reg & WM2200_DEVICE_REVISION_MASK; reg 12 sound/soc/codecs/wm5100-tables.c bool wm5100_volatile_register(struct device *dev, unsigned int reg) reg 14 sound/soc/codecs/wm5100-tables.c switch (reg) { reg 31 sound/soc/codecs/wm5100-tables.c if ((reg >= WM5100_DSP1_PM_0 && reg <= WM5100_DSP1_PM_1535) || reg 32 sound/soc/codecs/wm5100-tables.c (reg >= WM5100_DSP1_ZM_0 && reg <= WM5100_DSP1_ZM_2047) || reg 33 sound/soc/codecs/wm5100-tables.c (reg >= WM5100_DSP1_DM_0 && reg <= WM5100_DSP1_DM_511) || reg 34 sound/soc/codecs/wm5100-tables.c (reg >= WM5100_DSP2_PM_0 && reg <= WM5100_DSP2_PM_1535) || reg 35 sound/soc/codecs/wm5100-tables.c (reg >= WM5100_DSP2_ZM_0 && reg <= WM5100_DSP2_ZM_2047) || reg 36 sound/soc/codecs/wm5100-tables.c (reg >= WM5100_DSP2_DM_0 && reg <= WM5100_DSP2_DM_511) || reg 37 sound/soc/codecs/wm5100-tables.c (reg >= WM5100_DSP3_PM_0 && reg <= WM5100_DSP3_PM_1535) || reg 38 sound/soc/codecs/wm5100-tables.c (reg >= WM5100_DSP3_ZM_0 && reg <= WM5100_DSP3_ZM_2047) || reg 39 sound/soc/codecs/wm5100-tables.c (reg >= WM5100_DSP3_DM_0 && reg <= WM5100_DSP3_DM_511)) reg 46 sound/soc/codecs/wm5100-tables.c bool wm5100_readable_register(struct device *dev, unsigned int reg) reg 48 sound/soc/codecs/wm5100-tables.c switch (reg) { reg 799 sound/soc/codecs/wm5100-tables.c if ((reg >= WM5100_DSP1_PM_0 && reg <= WM5100_DSP1_PM_1535) || reg 800 sound/soc/codecs/wm5100-tables.c (reg >= WM5100_DSP1_ZM_0 && reg <= WM5100_DSP1_ZM_2047) || reg 801 sound/soc/codecs/wm5100-tables.c (reg >= WM5100_DSP1_DM_0 && reg <= WM5100_DSP1_DM_511) || reg 802 sound/soc/codecs/wm5100-tables.c (reg >= WM5100_DSP2_PM_0 && reg <= WM5100_DSP2_PM_1535) || reg 803 sound/soc/codecs/wm5100-tables.c (reg >= WM5100_DSP2_ZM_0 && reg <= WM5100_DSP2_ZM_2047) || reg 804 sound/soc/codecs/wm5100-tables.c (reg >= WM5100_DSP2_DM_0 && reg <= WM5100_DSP2_DM_511) || reg 805 sound/soc/codecs/wm5100-tables.c (reg >= WM5100_DSP3_PM_0 && reg <= WM5100_DSP3_PM_1535) || reg 806 sound/soc/codecs/wm5100-tables.c (reg >= WM5100_DSP3_ZM_0 && reg <= WM5100_DSP3_ZM_2047) || reg 807 sound/soc/codecs/wm5100-tables.c (reg >= WM5100_DSP3_DM_0 && reg <= WM5100_DSP3_DM_511)) reg 385 sound/soc/codecs/wm5100.c #define WM5100_MUX_ENUM_DECL(name, reg) \ reg 386 sound/soc/codecs/wm5100.c SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \ reg 778 sound/soc/codecs/wm5100.c switch (w->reg) { reg 1511 sound/soc/codecs/wm5100.c int fval, audio_rate, ret, reg; reg 1515 sound/soc/codecs/wm5100.c reg = WM5100_CLOCKING_3; reg 1519 sound/soc/codecs/wm5100.c reg = WM5100_CLOCKING_7; reg 1631 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, reg, WM5100_SYSCLK_FREQ_MASK | reg 2264 sound/soc/codecs/wm5100.c unsigned int reg; reg 2267 sound/soc/codecs/wm5100.c ret = regmap_read(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset, ®); reg 2271 sound/soc/codecs/wm5100.c return (reg & WM5100_GP1_LVL) != 0; reg 2419 sound/soc/codecs/wm5100.c unsigned int reg; reg 2486 sound/soc/codecs/wm5100.c ret = regmap_read(wm5100->regmap, WM5100_SOFTWARE_RESET, ®); reg 2491 sound/soc/codecs/wm5100.c switch (reg) { reg 2497 sound/soc/codecs/wm5100.c dev_err(&i2c->dev, "Device is not a WM5100, ID is %x\n", reg); reg 2502 sound/soc/codecs/wm5100.c ret = regmap_read(wm5100->regmap, WM5100_DEVICE_REVISION, ®); reg 2507 sound/soc/codecs/wm5100.c wm5100->rev = reg & WM5100_DEVICE_REVISION_MASK; reg 5306 sound/soc/codecs/wm5100.h bool wm5100_readable_register(struct device *dev, unsigned int reg); reg 5307 sound/soc/codecs/wm5100.h bool wm5100_volatile_register(struct device *dev, unsigned int reg); reg 604 sound/soc/codecs/wm5102.c regmap_write_async(regmap, patch[i].reg, reg 182 sound/soc/codecs/wm5110.c regmap_write_async(regmap, patch[i].reg, reg 391 sound/soc/codecs/wm5110.c unsigned int reg = ARIZONA_OUTPUT_PATH_CONFIG_1L + output * 4; reg 394 sound/soc/codecs/wm5110.c ret = regmap_write(arizona->regmap, reg, 0x80); reg 397 sound/soc/codecs/wm5110.c reg, ret); reg 510 sound/soc/codecs/wm5110.c unsigned int reg, mask; reg 517 sound/soc/codecs/wm5110.c reg = ARIZONA_IN1L_CONTROL + ((w->shift ^ 0x1) * 4); reg 527 sound/soc/codecs/wm5110.c wm5110->in_pga_cache[w->shift] = snd_soc_component_read32(component, reg); reg 529 sound/soc/codecs/wm5110.c snd_soc_component_update_bits(component, reg, mask, reg 546 sound/soc/codecs/wm5110.c snd_soc_component_update_bits(component, reg, mask, reg 80 sound/soc/codecs/wm8350.c u16 reg, val; reg 83 sound/soc/codecs/wm8350.c reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME); reg 84 sound/soc/codecs/wm8350.c val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; reg 90 sound/soc/codecs/wm8350.c reg &= ~WM8350_OUT1L_VOL_MASK; reg 92 sound/soc/codecs/wm8350.c reg | (val << WM8350_OUT1L_VOL_SHIFT)); reg 99 sound/soc/codecs/wm8350.c reg &= ~WM8350_OUT1L_VOL_MASK; reg 101 sound/soc/codecs/wm8350.c reg | (val << WM8350_OUT1L_VOL_SHIFT)); reg 108 sound/soc/codecs/wm8350.c reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME); reg 109 sound/soc/codecs/wm8350.c val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; reg 114 sound/soc/codecs/wm8350.c reg &= ~WM8350_OUT1R_VOL_MASK; reg 116 sound/soc/codecs/wm8350.c reg | (val << WM8350_OUT1R_VOL_SHIFT)); reg 123 sound/soc/codecs/wm8350.c reg &= ~WM8350_OUT1R_VOL_MASK; reg 125 sound/soc/codecs/wm8350.c reg | (val << WM8350_OUT1R_VOL_SHIFT)); reg 145 sound/soc/codecs/wm8350.c u16 reg, val; reg 148 sound/soc/codecs/wm8350.c reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME); reg 149 sound/soc/codecs/wm8350.c val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; reg 154 sound/soc/codecs/wm8350.c reg &= ~WM8350_OUT2L_VOL_MASK; reg 156 sound/soc/codecs/wm8350.c reg | (val << WM8350_OUT1L_VOL_SHIFT)); reg 163 sound/soc/codecs/wm8350.c reg &= ~WM8350_OUT2L_VOL_MASK; reg 165 sound/soc/codecs/wm8350.c reg | (val << WM8350_OUT1L_VOL_SHIFT)); reg 172 sound/soc/codecs/wm8350.c reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME); reg 173 sound/soc/codecs/wm8350.c val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; reg 178 sound/soc/codecs/wm8350.c reg &= ~WM8350_OUT2R_VOL_MASK; reg 180 sound/soc/codecs/wm8350.c reg | (val << WM8350_OUT1R_VOL_SHIFT)); reg 187 sound/soc/codecs/wm8350.c reg &= ~WM8350_OUT2R_VOL_MASK; reg 189 sound/soc/codecs/wm8350.c reg | (val << WM8350_OUT1R_VOL_SHIFT)); reg 305 sound/soc/codecs/wm8350.c unsigned int reg = mc->reg; reg 311 sound/soc/codecs/wm8350.c switch (reg) { reg 334 sound/soc/codecs/wm8350.c val = snd_soc_component_read32(component, reg); reg 335 sound/soc/codecs/wm8350.c snd_soc_component_write(component, reg, val | WM8350_OUT1_VU); reg 348 sound/soc/codecs/wm8350.c unsigned int reg = mc->reg; reg 351 sound/soc/codecs/wm8350.c switch (reg) { reg 1242 sound/soc/codecs/wm8350.c u16 reg; reg 1245 sound/soc/codecs/wm8350.c reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); reg 1246 sound/soc/codecs/wm8350.c if (reg & mask) reg 1367 sound/soc/codecs/wm8350.c u16 reg; reg 1374 sound/soc/codecs/wm8350.c reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); reg 1375 sound/soc/codecs/wm8350.c if (reg & WM8350_JACK_MICSCD_LVL) reg 1377 sound/soc/codecs/wm8350.c if (reg & WM8350_JACK_MICSD_LVL) reg 92 sound/soc/codecs/wm8400.c int reg = mc->reg; reg 101 sound/soc/codecs/wm8400.c val = snd_soc_component_read32(component, reg); reg 102 sound/soc/codecs/wm8400.c return snd_soc_component_write(component, reg, val | 0x0100); reg 105 sound/soc/codecs/wm8400.c #define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \ reg 106 sound/soc/codecs/wm8400.c SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \ reg 327 sound/soc/codecs/wm8400.c u16 reg; reg 331 sound/soc/codecs/wm8400.c reg = snd_soc_component_read32(component, WM8400_OUTPUT_MIXER1); reg 332 sound/soc/codecs/wm8400.c if (reg & WM8400_LDLO) { reg 339 sound/soc/codecs/wm8400.c reg = snd_soc_component_read32(component, WM8400_OUTPUT_MIXER2); reg 340 sound/soc/codecs/wm8400.c if (reg & WM8400_RDRO) { reg 347 sound/soc/codecs/wm8400.c reg = snd_soc_component_read32(component, WM8400_SPEAKER_MIXER); reg 348 sound/soc/codecs/wm8400.c if (reg & WM8400_LDSPK) { reg 355 sound/soc/codecs/wm8400.c reg = snd_soc_component_read32(component, WM8400_SPEAKER_MIXER); reg 356 sound/soc/codecs/wm8400.c if (reg & WM8400_RDSPK) { reg 940 sound/soc/codecs/wm8400.c u16 reg; reg 960 sound/soc/codecs/wm8400.c reg = snd_soc_component_read32(component, WM8400_POWER_MANAGEMENT_2); reg 961 sound/soc/codecs/wm8400.c reg &= ~WM8400_FLL_ENA; reg 962 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_2, reg); reg 964 sound/soc/codecs/wm8400.c reg = snd_soc_component_read32(component, WM8400_FLL_CONTROL_1); reg 965 sound/soc/codecs/wm8400.c reg &= ~WM8400_FLL_OSC_ENA; reg 966 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_FLL_CONTROL_1, reg); reg 971 sound/soc/codecs/wm8400.c reg &= ~(WM8400_FLL_REF_FREQ | WM8400_FLL_FRATIO_MASK); reg 972 sound/soc/codecs/wm8400.c reg |= WM8400_FLL_FRAC | factors.fratio; reg 973 sound/soc/codecs/wm8400.c reg |= factors.freq_ref << WM8400_FLL_REF_FREQ_SHIFT; reg 974 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_FLL_CONTROL_1, reg); reg 979 sound/soc/codecs/wm8400.c reg = snd_soc_component_read32(component, WM8400_FLL_CONTROL_4); reg 980 sound/soc/codecs/wm8400.c reg &= ~WM8400_FLL_OUTDIV_MASK; reg 981 sound/soc/codecs/wm8400.c reg |= factors.outdiv; reg 982 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_FLL_CONTROL_4, reg); reg 1047 sound/soc/codecs/wm8400.c u16 reg; reg 1051 sound/soc/codecs/wm8400.c reg = snd_soc_component_read32(component, WM8400_CLOCKING_2) & reg 1053 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_CLOCKING_2, reg | div); reg 1056 sound/soc/codecs/wm8400.c reg = snd_soc_component_read32(component, WM8400_CLOCKING_2) & reg 1058 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_CLOCKING_2, reg | div); reg 1061 sound/soc/codecs/wm8400.c reg = snd_soc_component_read32(component, WM8400_CLOCKING_2) & reg 1063 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_CLOCKING_2, reg | div); reg 1066 sound/soc/codecs/wm8400.c reg = snd_soc_component_read32(component, WM8400_CLOCKING_1) & reg 1068 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_CLOCKING_1, reg | div); reg 1276 sound/soc/codecs/wm8400.c u16 reg; reg 1296 sound/soc/codecs/wm8400.c reg = snd_soc_component_read32(component, WM8400_POWER_MANAGEMENT_1); reg 1297 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, reg | WM8400_CODEC_ENA); reg 1300 sound/soc/codecs/wm8400.c reg = snd_soc_component_read32(component, WM8400_LEFT_LINE_INPUT_1_2_VOLUME); reg 1302 sound/soc/codecs/wm8400.c reg & WM8400_IPVU); reg 1303 sound/soc/codecs/wm8400.c reg = snd_soc_component_read32(component, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME); reg 1305 sound/soc/codecs/wm8400.c reg & WM8400_IPVU); reg 1315 sound/soc/codecs/wm8400.c u16 reg; reg 1317 sound/soc/codecs/wm8400.c reg = snd_soc_component_read32(component, WM8400_POWER_MANAGEMENT_1); reg 1319 sound/soc/codecs/wm8400.c reg & (~WM8400_CODEC_ENA)); reg 93 sound/soc/codecs/wm8510.c static bool wm8510_volatile(struct device *dev, unsigned int reg) reg 95 sound/soc/codecs/wm8510.c switch (reg) { reg 317 sound/soc/codecs/wm8510.c u16 reg; reg 321 sound/soc/codecs/wm8510.c reg = snd_soc_component_read32(component, WM8510_CLOCK); reg 322 sound/soc/codecs/wm8510.c snd_soc_component_write(component, WM8510_CLOCK, reg & 0x0ff); reg 325 sound/soc/codecs/wm8510.c reg = snd_soc_component_read32(component, WM8510_POWER1); reg 326 sound/soc/codecs/wm8510.c snd_soc_component_write(component, WM8510_POWER1, reg & 0x1df); reg 336 sound/soc/codecs/wm8510.c reg = snd_soc_component_read32(component, WM8510_POWER1); reg 337 sound/soc/codecs/wm8510.c snd_soc_component_write(component, WM8510_POWER1, reg | 0x020); reg 340 sound/soc/codecs/wm8510.c reg = snd_soc_component_read32(component, WM8510_CLOCK); reg 341 sound/soc/codecs/wm8510.c snd_soc_component_write(component, WM8510_CLOCK, reg | 0x100); reg 353 sound/soc/codecs/wm8510.c u16 reg; reg 357 sound/soc/codecs/wm8510.c reg = snd_soc_component_read32(component, WM8510_GPIO) & 0x1cf; reg 358 sound/soc/codecs/wm8510.c snd_soc_component_write(component, WM8510_GPIO, reg | div); reg 361 sound/soc/codecs/wm8510.c reg = snd_soc_component_read32(component, WM8510_CLOCK) & 0x11f; reg 362 sound/soc/codecs/wm8510.c snd_soc_component_write(component, WM8510_CLOCK, reg | div); reg 365 sound/soc/codecs/wm8510.c reg = snd_soc_component_read32(component, WM8510_ADC) & 0x1f7; reg 366 sound/soc/codecs/wm8510.c snd_soc_component_write(component, WM8510_ADC, reg | div); reg 369 sound/soc/codecs/wm8510.c reg = snd_soc_component_read32(component, WM8510_DAC) & 0x1f7; reg 370 sound/soc/codecs/wm8510.c snd_soc_component_write(component, WM8510_DAC, reg | div); reg 373 sound/soc/codecs/wm8510.c reg = snd_soc_component_read32(component, WM8510_CLOCK) & 0x1e3; reg 374 sound/soc/codecs/wm8510.c snd_soc_component_write(component, WM8510_CLOCK, reg | div); reg 56 sound/soc/codecs/wm8523.c static bool wm8523_volatile_register(struct device *dev, unsigned int reg) reg 58 sound/soc/codecs/wm8523.c switch (reg) { reg 218 sound/soc/codecs/wm8580.c static bool wm8580_volatile(struct device *dev, unsigned int reg) reg 220 sound/soc/codecs/wm8580.c switch (reg) { reg 263 sound/soc/codecs/wm8580.c unsigned int reg = mc->reg; reg 269 sound/soc/codecs/wm8580.c regmap_update_bits(wm8580->regmap, reg, 0x100, 0x000); reg 278 sound/soc/codecs/wm8580.c snd_soc_component_update_bits(component, reg, 0x100, 0x100); reg 468 sound/soc/codecs/wm8580.c unsigned int reg; reg 514 sound/soc/codecs/wm8580.c reg = snd_soc_component_read32(component, WM8580_PLLA4 + offset); reg 515 sound/soc/codecs/wm8580.c reg &= ~0x1b; reg 516 sound/soc/codecs/wm8580.c reg |= pll_div.prescale | pll_div.postscale << 1 | reg 519 sound/soc/codecs/wm8580.c snd_soc_component_write(component, WM8580_PLLA4 + offset, reg); reg 688 sound/soc/codecs/wm8580.c unsigned int reg; reg 692 sound/soc/codecs/wm8580.c reg = snd_soc_component_read32(component, WM8580_PLLB4); reg 693 sound/soc/codecs/wm8580.c reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK; reg 701 sound/soc/codecs/wm8580.c reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA; reg 704 sound/soc/codecs/wm8580.c reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB; reg 708 sound/soc/codecs/wm8580.c reg |= WM8580_PLLB4_MCLKOUTSRC_OSC; reg 714 sound/soc/codecs/wm8580.c snd_soc_component_write(component, WM8580_PLLB4, reg); reg 718 sound/soc/codecs/wm8580.c reg = snd_soc_component_read32(component, WM8580_PLLB4); reg 719 sound/soc/codecs/wm8580.c reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK; reg 726 sound/soc/codecs/wm8580.c reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK; reg 730 sound/soc/codecs/wm8580.c reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK; reg 734 sound/soc/codecs/wm8580.c reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK; reg 740 sound/soc/codecs/wm8580.c snd_soc_component_write(component, WM8580_PLLB4, reg); reg 806 sound/soc/codecs/wm8580.c unsigned int reg; reg 808 sound/soc/codecs/wm8580.c reg = snd_soc_component_read32(component, WM8580_DAC_CONTROL5); reg 811 sound/soc/codecs/wm8580.c reg |= WM8580_DAC_CONTROL5_MUTEALL; reg 813 sound/soc/codecs/wm8580.c reg &= ~WM8580_DAC_CONTROL5_MUTEALL; reg 815 sound/soc/codecs/wm8580.c snd_soc_component_write(component, WM8580_DAC_CONTROL5, reg); reg 48 sound/soc/codecs/wm8711.c static bool wm8711_volatile(struct device *dev, unsigned int reg) reg 50 sound/soc/codecs/wm8711.c switch (reg) { reg 301 sound/soc/codecs/wm8711.c u16 reg = snd_soc_component_read32(component, WM8711_PWR) & 0xff7f; reg 305 sound/soc/codecs/wm8711.c snd_soc_component_write(component, WM8711_PWR, reg); reg 313 sound/soc/codecs/wm8711.c snd_soc_component_write(component, WM8711_PWR, reg | 0x0040); reg 164 sound/soc/codecs/wm8728.c u16 reg; reg 172 sound/soc/codecs/wm8728.c reg = snd_soc_component_read32(component, WM8728_DACCTL); reg 173 sound/soc/codecs/wm8728.c snd_soc_component_write(component, WM8728_DACCTL, reg & ~0x4); reg 181 sound/soc/codecs/wm8728.c reg = snd_soc_component_read32(component, WM8728_DACCTL); reg 182 sound/soc/codecs/wm8728.c snd_soc_component_write(component, WM8728_DACCTL, reg | 0x4); reg 74 sound/soc/codecs/wm8731.c static bool wm8731_volatile(struct device *dev, unsigned int reg) reg 76 sound/soc/codecs/wm8731.c return reg == WM8731_RESET; reg 490 sound/soc/codecs/wm8731.c u16 reg; reg 513 sound/soc/codecs/wm8731.c reg = snd_soc_component_read32(component, WM8731_PWR) & 0xff7f; reg 514 sound/soc/codecs/wm8731.c snd_soc_component_write(component, WM8731_PWR, reg | 0x0040); reg 64 sound/soc/codecs/wm8737.c static bool wm8737_volatile(struct device *dev, unsigned int reg) reg 66 sound/soc/codecs/wm8737.c switch (reg) { reg 130 sound/soc/codecs/wm8753.c static bool wm8753_volatile(struct device *dev, unsigned int reg) reg 132 sound/soc/codecs/wm8753.c return reg == WM8753_RESET; reg 741 sound/soc/codecs/wm8753.c u16 reg, enable; reg 751 sound/soc/codecs/wm8753.c reg = snd_soc_component_read32(component, WM8753_CLOCK) & 0xffef; reg 755 sound/soc/codecs/wm8753.c reg = snd_soc_component_read32(component, WM8753_CLOCK) & 0xfff7; reg 761 sound/soc/codecs/wm8753.c snd_soc_component_write(component, WM8753_CLOCK, reg); reg 785 sound/soc/codecs/wm8753.c snd_soc_component_write(component, WM8753_CLOCK, reg | enable); reg 1025 sound/soc/codecs/wm8753.c u16 reg; reg 1029 sound/soc/codecs/wm8753.c reg = snd_soc_component_read32(component, WM8753_CLOCK) & 0x003f; reg 1030 sound/soc/codecs/wm8753.c snd_soc_component_write(component, WM8753_CLOCK, reg | div); reg 1033 sound/soc/codecs/wm8753.c reg = snd_soc_component_read32(component, WM8753_SRATE2) & 0x01c7; reg 1034 sound/soc/codecs/wm8753.c snd_soc_component_write(component, WM8753_SRATE2, reg | div); reg 1037 sound/soc/codecs/wm8753.c reg = snd_soc_component_read32(component, WM8753_SRATE2) & 0x003f; reg 1038 sound/soc/codecs/wm8753.c snd_soc_component_write(component, WM8753_SRATE2, reg | div); reg 70 sound/soc/codecs/wm8770.c static bool wm8770_volatile_reg(struct device *dev, unsigned int reg) reg 72 sound/soc/codecs/wm8770.c switch (reg) { reg 68 sound/soc/codecs/wm8776.c static bool wm8776_volatile(struct device *dev, unsigned int reg) reg 70 sound/soc/codecs/wm8776.c switch (reg) { reg 167 sound/soc/codecs/wm8776.c int reg, iface, master; reg 171 sound/soc/codecs/wm8776.c reg = WM8776_DACIFCTRL; reg 175 sound/soc/codecs/wm8776.c reg = WM8776_ADCIFCTRL; reg 224 sound/soc/codecs/wm8776.c snd_soc_component_update_bits(component, reg, 0xf, iface); reg 173 sound/soc/codecs/wm8804.c if (snd_soc_component_test_bits(component, e->reg, mask, val)) { reg 181 sound/soc/codecs/wm8804.c snd_soc_component_update_bits(component, e->reg, mask, val); reg 192 sound/soc/codecs/wm8804.c static bool wm8804_volatile(struct device *dev, unsigned int reg) reg 194 sound/soc/codecs/wm8804.c switch (reg) { reg 206 sound/soc/codecs/wm8900.c static bool wm8900_volatile_register(struct device *dev, unsigned int reg) reg 208 sound/soc/codecs/wm8900.c switch (reg) { reg 636 sound/soc/codecs/wm8900.c u16 reg; reg 638 sound/soc/codecs/wm8900.c reg = snd_soc_component_read32(component, WM8900_REG_AUDIO1) & ~0x60; reg 644 sound/soc/codecs/wm8900.c reg |= 0x20; reg 647 sound/soc/codecs/wm8900.c reg |= 0x40; reg 650 sound/soc/codecs/wm8900.c reg |= 0x60; reg 656 sound/soc/codecs/wm8900.c snd_soc_component_write(component, WM8900_REG_AUDIO1, reg); reg 659 sound/soc/codecs/wm8900.c reg = snd_soc_component_read32(component, WM8900_REG_DACCTRL); reg 662 sound/soc/codecs/wm8900.c reg |= WM8900_REG_DACCTRL_DAC_SB_FILT; reg 664 sound/soc/codecs/wm8900.c reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT; reg 666 sound/soc/codecs/wm8900.c snd_soc_component_write(component, WM8900_REG_DACCTRL, reg); reg 979 sound/soc/codecs/wm8900.c u16 reg; reg 981 sound/soc/codecs/wm8900.c reg = snd_soc_component_read32(component, WM8900_REG_DACCTRL); reg 984 sound/soc/codecs/wm8900.c reg |= WM8900_REG_DACCTRL_MUTE; reg 986 sound/soc/codecs/wm8900.c reg &= ~WM8900_REG_DACCTRL_MUTE; reg 988 sound/soc/codecs/wm8900.c snd_soc_component_write(component, WM8900_REG_DACCTRL, reg); reg 1031 sound/soc/codecs/wm8900.c u16 reg; reg 1077 sound/soc/codecs/wm8900.c reg = snd_soc_component_read32(component, WM8900_REG_POWER1); reg 1079 sound/soc/codecs/wm8900.c (reg & WM8900_REG_POWER1_FLL_ENA) | reg 1088 sound/soc/codecs/wm8900.c reg = snd_soc_component_read32(component, WM8900_REG_POWER1); reg 1090 sound/soc/codecs/wm8900.c reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA); reg 1177 sound/soc/codecs/wm8900.c int reg; reg 1179 sound/soc/codecs/wm8900.c reg = snd_soc_component_read32(component, WM8900_REG_ID); reg 1180 sound/soc/codecs/wm8900.c if (reg != 0x8900) { reg 1181 sound/soc/codecs/wm8900.c dev_err(component->dev, "Device is not a WM8900 - ID %x\n", reg); reg 154 sound/soc/codecs/wm8903.c static bool wm8903_readable_register(struct device *dev, unsigned int reg) reg 156 sound/soc/codecs/wm8903.c switch (reg) { reg 240 sound/soc/codecs/wm8903.c static bool wm8903_volatile_register(struct device *dev, unsigned int reg) reg 242 sound/soc/codecs/wm8903.c switch (reg) { reg 375 sound/soc/codecs/wm8903.c u16 reg; reg 378 sound/soc/codecs/wm8903.c reg = snd_soc_component_read32(component, WM8903_CLASS_W_0); reg 384 sound/soc/codecs/wm8903.c snd_soc_component_write(component, WM8903_CLASS_W_0, reg & reg 397 sound/soc/codecs/wm8903.c snd_soc_component_write(component, WM8903_CLASS_W_0, reg | reg 409 sound/soc/codecs/wm8903.c #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \ reg 410 sound/soc/codecs/wm8903.c SOC_SINGLE_EXT(xname, reg, shift, max, invert, \ reg 1313 sound/soc/codecs/wm8903.c u16 reg; reg 1315 sound/soc/codecs/wm8903.c reg = snd_soc_component_read32(component, WM8903_DAC_DIGITAL_1); reg 1318 sound/soc/codecs/wm8903.c reg |= WM8903_DAC_MUTE; reg 1320 sound/soc/codecs/wm8903.c reg &= ~WM8903_DAC_MUTE; reg 1322 sound/soc/codecs/wm8903.c snd_soc_component_write(component, WM8903_DAC_DIGITAL_1, reg); reg 1804 sound/soc/codecs/wm8903.c unsigned int reg; reg 1806 sound/soc/codecs/wm8903.c regmap_read(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset, ®); reg 1808 sound/soc/codecs/wm8903.c return !!((reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT); reg 184 sound/soc/codecs/wm8904.c static bool wm8904_volatile_register(struct device *dev, unsigned int reg) reg 186 sound/soc/codecs/wm8904.c switch (reg) { reg 202 sound/soc/codecs/wm8904.c static bool wm8904_readable_register(struct device *dev, unsigned int reg) reg 204 sound/soc/codecs/wm8904.c switch (reg) { reg 696 sound/soc/codecs/wm8904.c int reg, val; reg 707 sound/soc/codecs/wm8904.c reg = w->shift; reg 709 sound/soc/codecs/wm8904.c switch (reg) { reg 727 sound/soc/codecs/wm8904.c WARN(1, "Invalid reg %d\n", reg); reg 739 sound/soc/codecs/wm8904.c snd_soc_component_update_bits(component, reg, reg 745 sound/soc/codecs/wm8904.c snd_soc_component_update_bits(component, reg, reg 792 sound/soc/codecs/wm8904.c snd_soc_component_update_bits(component, reg, reg 799 sound/soc/codecs/wm8904.c snd_soc_component_update_bits(component, reg, reg 809 sound/soc/codecs/wm8904.c snd_soc_component_update_bits(component, reg, reg 824 sound/soc/codecs/wm8904.c snd_soc_component_update_bits(component, reg, reg 44 sound/soc/codecs/wm8940.c static bool wm8940_volatile_register(struct device *dev, unsigned int reg) reg 46 sound/soc/codecs/wm8940.c switch (reg) { reg 54 sound/soc/codecs/wm8940.c static bool wm8940_readable_register(struct device *dev, unsigned int reg) reg 56 sound/soc/codecs/wm8940.c switch (reg) { reg 577 sound/soc/codecs/wm8940.c u16 reg; reg 580 sound/soc/codecs/wm8940.c reg = snd_soc_component_read32(component, WM8940_POWER1); reg 581 sound/soc/codecs/wm8940.c snd_soc_component_write(component, WM8940_POWER1, reg & 0x1df); reg 585 sound/soc/codecs/wm8940.c reg = snd_soc_component_read32(component, WM8940_CLOCK); reg 586 sound/soc/codecs/wm8940.c snd_soc_component_write(component, WM8940_CLOCK, reg & 0x0ff); reg 604 sound/soc/codecs/wm8940.c reg = snd_soc_component_read32(component, WM8940_POWER1); reg 605 sound/soc/codecs/wm8940.c snd_soc_component_write(component, WM8940_POWER1, reg | 0x020); reg 608 sound/soc/codecs/wm8940.c reg = snd_soc_component_read32(component, WM8940_CLOCK); reg 609 sound/soc/codecs/wm8940.c snd_soc_component_write(component, WM8940_CLOCK, reg | 0x100); reg 636 sound/soc/codecs/wm8940.c u16 reg; reg 641 sound/soc/codecs/wm8940.c reg = snd_soc_component_read32(component, WM8940_CLOCK) & 0xFFE3; reg 642 sound/soc/codecs/wm8940.c ret = snd_soc_component_write(component, WM8940_CLOCK, reg | (div << 2)); reg 645 sound/soc/codecs/wm8940.c reg = snd_soc_component_read32(component, WM8940_CLOCK) & 0xFF1F; reg 646 sound/soc/codecs/wm8940.c ret = snd_soc_component_write(component, WM8940_CLOCK, reg | (div << 5)); reg 649 sound/soc/codecs/wm8940.c reg = snd_soc_component_read32(component, WM8940_GPIO) & 0xFFCF; reg 650 sound/soc/codecs/wm8940.c ret = snd_soc_component_write(component, WM8940_GPIO, reg | (div << 4)); reg 697 sound/soc/codecs/wm8940.c u16 reg; reg 714 sound/soc/codecs/wm8940.c reg = snd_soc_component_read32(component, WM8940_OUTPUTCTL); reg 715 sound/soc/codecs/wm8940.c ret = snd_soc_component_write(component, WM8940_OUTPUTCTL, reg | pdata->vroi); reg 80 sound/soc/codecs/wm8955.c static bool wm8955_writeable(struct device *dev, unsigned int reg) reg 82 sound/soc/codecs/wm8955.c switch (reg) { reg 118 sound/soc/codecs/wm8955.c static bool wm8955_volatile(struct device *dev, unsigned int reg) reg 120 sound/soc/codecs/wm8955.c switch (reg) { reg 332 sound/soc/codecs/wm8958-dsp2.c int ena, reg, aif; reg 359 sound/soc/codecs/wm8958-dsp2.c reg = snd_soc_component_read32(component, WM8958_DSP2_PROGRAM); reg 362 sound/soc/codecs/wm8958-dsp2.c path, wm8994->dsp_active, start, pwr_reg, reg); reg 366 sound/soc/codecs/wm8958-dsp2.c if (reg & WM8958_DSP2_ENA) reg 397 sound/soc/codecs/wm8958-dsp2.c if (!(reg & WM8958_DSP2_ENA)) reg 460 sound/soc/codecs/wm8958-dsp2.c int reg; reg 463 sound/soc/codecs/wm8958-dsp2.c reg = snd_soc_component_read32(component, WM8994_CLOCKING_1); reg 464 sound/soc/codecs/wm8958-dsp2.c if (reg < 0 || reg & WM8958_DSP2CLK_ENA) reg 550 sound/soc/codecs/wm8958-dsp2.c int reg; reg 553 sound/soc/codecs/wm8958-dsp2.c reg = snd_soc_component_read32(component, WM8994_CLOCKING_1); reg 554 sound/soc/codecs/wm8958-dsp2.c if (reg < 0 || reg & WM8958_DSP2CLK_ENA) reg 583 sound/soc/codecs/wm8958-dsp2.c int reg; reg 586 sound/soc/codecs/wm8958-dsp2.c reg = snd_soc_component_read32(component, WM8994_CLOCKING_1); reg 587 sound/soc/codecs/wm8958-dsp2.c if (reg < 0 || reg & WM8958_DSP2CLK_ENA) reg 750 sound/soc/codecs/wm8958-dsp2.c int reg; reg 753 sound/soc/codecs/wm8958-dsp2.c reg = snd_soc_component_read32(component, WM8994_CLOCKING_1); reg 754 sound/soc/codecs/wm8958-dsp2.c if (reg < 0 || reg & WM8958_DSP2CLK_ENA) reg 110 sound/soc/codecs/wm8960.c static bool wm8960_volatile(struct device *dev, unsigned int reg) reg 112 sound/soc/codecs/wm8960.c switch (reg) { reg 987 sound/soc/codecs/wm8960.c int reg, ret; reg 1004 sound/soc/codecs/wm8960.c reg = 0; reg 1006 sound/soc/codecs/wm8960.c reg |= WM8960_PWR2_LOUT1; reg 1008 sound/soc/codecs/wm8960.c reg |= WM8960_PWR2_ROUT1; reg 1010 sound/soc/codecs/wm8960.c reg |= WM8960_PWR2_OUT3; reg 1014 sound/soc/codecs/wm8960.c WM8960_PWR2_OUT3, reg); reg 1187 sound/soc/codecs/wm8960.c u16 reg; reg 1205 sound/soc/codecs/wm8960.c reg = snd_soc_component_read32(component, WM8960_PLL1) & ~0x3f; reg 1206 sound/soc/codecs/wm8960.c reg |= pll_div.pre_div << 4; reg 1207 sound/soc/codecs/wm8960.c reg |= pll_div.n; reg 1210 sound/soc/codecs/wm8960.c reg |= 0x20; reg 1216 sound/soc/codecs/wm8960.c snd_soc_component_write(component, WM8960_PLL1, reg); reg 1244 sound/soc/codecs/wm8960.c u16 reg; reg 1248 sound/soc/codecs/wm8960.c reg = snd_soc_component_read32(component, WM8960_CLOCK1) & 0x1f9; reg 1249 sound/soc/codecs/wm8960.c snd_soc_component_write(component, WM8960_CLOCK1, reg | div); reg 1252 sound/soc/codecs/wm8960.c reg = snd_soc_component_read32(component, WM8960_CLOCK1) & 0x1c7; reg 1253 sound/soc/codecs/wm8960.c snd_soc_component_write(component, WM8960_CLOCK1, reg | div); reg 1256 sound/soc/codecs/wm8960.c reg = snd_soc_component_read32(component, WM8960_PLL1) & 0x03f; reg 1257 sound/soc/codecs/wm8960.c snd_soc_component_write(component, WM8960_PLL1, reg | div); reg 1260 sound/soc/codecs/wm8960.c reg = snd_soc_component_read32(component, WM8960_CLOCK2) & 0x03f; reg 1261 sound/soc/codecs/wm8960.c snd_soc_component_write(component, WM8960_CLOCK2, reg | div); reg 1264 sound/soc/codecs/wm8960.c reg = snd_soc_component_read32(component, WM8960_ADDCTL1) & 0x1fd; reg 1265 sound/soc/codecs/wm8960.c snd_soc_component_write(component, WM8960_ADDCTL1, reg | div); reg 110 sound/soc/codecs/wm8961.c static bool wm8961_volatile(struct device *dev, unsigned int reg) reg 112 sound/soc/codecs/wm8961.c switch (reg) { reg 123 sound/soc/codecs/wm8961.c static bool wm8961_readable(struct device *dev, unsigned int reg) reg 125 sound/soc/codecs/wm8961.c switch (reg) { reg 508 sound/soc/codecs/wm8961.c u16 reg; reg 524 sound/soc/codecs/wm8961.c reg = snd_soc_component_read32(component, WM8961_ADDITIONAL_CONTROL_3); reg 525 sound/soc/codecs/wm8961.c reg &= ~WM8961_SAMPLE_RATE_MASK; reg 526 sound/soc/codecs/wm8961.c reg |= wm8961_srate[best].val; reg 527 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_ADDITIONAL_CONTROL_3, reg); reg 557 sound/soc/codecs/wm8961.c reg = snd_soc_component_read32(component, WM8961_CLOCKING_4); reg 558 sound/soc/codecs/wm8961.c reg &= ~WM8961_CLK_SYS_RATE_MASK; reg 559 sound/soc/codecs/wm8961.c reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT; reg 560 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_CLOCKING_4, reg); reg 562 sound/soc/codecs/wm8961.c reg = snd_soc_component_read32(component, WM8961_AUDIO_INTERFACE_0); reg 563 sound/soc/codecs/wm8961.c reg &= ~WM8961_WL_MASK; reg 568 sound/soc/codecs/wm8961.c reg |= 1 << WM8961_WL_SHIFT; reg 571 sound/soc/codecs/wm8961.c reg |= 2 << WM8961_WL_SHIFT; reg 574 sound/soc/codecs/wm8961.c reg |= 3 << WM8961_WL_SHIFT; reg 579 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_0, reg); reg 582 sound/soc/codecs/wm8961.c reg = snd_soc_component_read32(component, WM8961_ADC_DAC_CONTROL_2); reg 584 sound/soc/codecs/wm8961.c reg |= WM8961_DACSLOPE; reg 586 sound/soc/codecs/wm8961.c reg &= ~WM8961_DACSLOPE; reg 587 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_2, reg); reg 598 sound/soc/codecs/wm8961.c u16 reg = snd_soc_component_read32(component, WM8961_CLOCKING1); reg 607 sound/soc/codecs/wm8961.c reg |= WM8961_MCLKDIV; reg 611 sound/soc/codecs/wm8961.c reg &= ~WM8961_MCLKDIV; reg 614 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_CLOCKING1, reg); reg 691 sound/soc/codecs/wm8961.c u16 reg = snd_soc_component_read32(component, WM8961_ADDITIONAL_CONTROL_2); reg 694 sound/soc/codecs/wm8961.c reg |= WM8961_TRIS; reg 696 sound/soc/codecs/wm8961.c reg &= ~WM8961_TRIS; reg 698 sound/soc/codecs/wm8961.c return snd_soc_component_write(component, WM8961_ADDITIONAL_CONTROL_2, reg); reg 704 sound/soc/codecs/wm8961.c u16 reg = snd_soc_component_read32(component, WM8961_ADC_DAC_CONTROL_1); reg 707 sound/soc/codecs/wm8961.c reg |= WM8961_DACMU; reg 709 sound/soc/codecs/wm8961.c reg &= ~WM8961_DACMU; reg 713 sound/soc/codecs/wm8961.c return snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_1, reg); reg 719 sound/soc/codecs/wm8961.c u16 reg; reg 723 sound/soc/codecs/wm8961.c reg = snd_soc_component_read32(component, WM8961_CLOCKING2); reg 724 sound/soc/codecs/wm8961.c reg &= ~WM8961_BCLKDIV_MASK; reg 725 sound/soc/codecs/wm8961.c reg |= div; reg 726 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_CLOCKING2, reg); reg 730 sound/soc/codecs/wm8961.c reg = snd_soc_component_read32(component, WM8961_AUDIO_INTERFACE_2); reg 731 sound/soc/codecs/wm8961.c reg &= ~WM8961_LRCLK_RATE_MASK; reg 732 sound/soc/codecs/wm8961.c reg |= div; reg 733 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_2, reg); reg 746 sound/soc/codecs/wm8961.c u16 reg; reg 760 sound/soc/codecs/wm8961.c reg = snd_soc_component_read32(component, WM8961_ANTI_POP); reg 761 sound/soc/codecs/wm8961.c reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN; reg 762 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_ANTI_POP, reg); reg 765 sound/soc/codecs/wm8961.c reg = snd_soc_component_read32(component, WM8961_PWR_MGMT_1); reg 766 sound/soc/codecs/wm8961.c reg &= ~WM8961_VMIDSEL_MASK; reg 767 sound/soc/codecs/wm8961.c reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF; reg 768 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg); reg 775 sound/soc/codecs/wm8961.c reg = snd_soc_component_read32(component, WM8961_PWR_MGMT_1); reg 776 sound/soc/codecs/wm8961.c reg &= ~WM8961_VREF; reg 777 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg); reg 780 sound/soc/codecs/wm8961.c reg = snd_soc_component_read32(component, WM8961_ANTI_POP); reg 781 sound/soc/codecs/wm8961.c reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN); reg 782 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_ANTI_POP, reg); reg 785 sound/soc/codecs/wm8961.c reg = snd_soc_component_read32(component, WM8961_PWR_MGMT_1); reg 786 sound/soc/codecs/wm8961.c reg &= ~WM8961_VMIDSEL_MASK; reg 787 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg); reg 833 sound/soc/codecs/wm8961.c u16 reg; reg 836 sound/soc/codecs/wm8961.c reg = snd_soc_component_read32(component, WM8961_CHARGE_PUMP_B); reg 837 sound/soc/codecs/wm8961.c reg |= WM8961_CP_DYN_PWR_MASK; reg 838 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_CHARGE_PUMP_B, reg); reg 842 sound/soc/codecs/wm8961.c reg = snd_soc_component_read32(component, WM8961_ROUT1_VOLUME); reg 844 sound/soc/codecs/wm8961.c reg | WM8961_LO1ZC | WM8961_OUT1VU); reg 845 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC); reg 846 sound/soc/codecs/wm8961.c reg = snd_soc_component_read32(component, WM8961_ROUT2_VOLUME); reg 848 sound/soc/codecs/wm8961.c reg | WM8961_SPKRZC | WM8961_SPKVU); reg 849 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC); reg 851 sound/soc/codecs/wm8961.c reg = snd_soc_component_read32(component, WM8961_RIGHT_ADC_VOLUME); reg 852 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU); reg 853 sound/soc/codecs/wm8961.c reg = snd_soc_component_read32(component, WM8961_RIGHT_INPUT_VOLUME); reg 854 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU); reg 857 sound/soc/codecs/wm8961.c reg = snd_soc_component_read32(component, WM8961_ADC_DAC_CONTROL_2); reg 858 sound/soc/codecs/wm8961.c reg |= WM8961_DACSMM; reg 859 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_2, reg); reg 864 sound/soc/codecs/wm8961.c reg = snd_soc_component_read32(component, WM8961_CLOCKING_3); reg 865 sound/soc/codecs/wm8961.c reg &= ~WM8961_MANUAL_MODE; reg 866 sound/soc/codecs/wm8961.c snd_soc_component_write(component, WM8961_CLOCKING_3, reg); reg 787 sound/soc/codecs/wm8962.c static bool wm8962_volatile_register(struct device *dev, unsigned int reg) reg 789 sound/soc/codecs/wm8962.c switch (reg) { reg 805 sound/soc/codecs/wm8962.c static bool wm8962_readable_register(struct device *dev, unsigned int reg) reg 807 sound/soc/codecs/wm8962.c switch (reg) { reg 1864 sound/soc/codecs/wm8962.c int reg; reg 1892 sound/soc/codecs/wm8962.c reg = snd_soc_component_read32(component, WM8962_DC_SERVO_6); reg 1893 sound/soc/codecs/wm8962.c if (reg < 0) { reg 1896 sound/soc/codecs/wm8962.c reg); reg 1899 sound/soc/codecs/wm8962.c dev_dbg(component->dev, "DCS status: %x\n", reg); reg 1900 sound/soc/codecs/wm8962.c } while (++timeout < 200 && (reg & expected) != expected); reg 1902 sound/soc/codecs/wm8962.c if ((reg & expected) != expected) reg 1957 sound/soc/codecs/wm8962.c int reg; reg 1961 sound/soc/codecs/wm8962.c reg = WM8962_HPOUTR_VOLUME; reg 1964 sound/soc/codecs/wm8962.c reg = WM8962_HPOUTL_VOLUME; reg 1967 sound/soc/codecs/wm8962.c reg = WM8962_SPKOUTR_VOLUME; reg 1970 sound/soc/codecs/wm8962.c reg = WM8962_SPKOUTL_VOLUME; reg 1979 sound/soc/codecs/wm8962.c return snd_soc_component_write(component, reg, snd_soc_component_read32(component, reg)); reg 2536 sound/soc/codecs/wm8962.c int reg; reg 2569 sound/soc/codecs/wm8962.c adctl3 |= sr_vals[i].reg; reg 2984 sound/soc/codecs/wm8962.c int reg; reg 2986 sound/soc/codecs/wm8962.c reg = snd_soc_component_read32(component, WM8962_ADDITIONAL_CONTROL_4); reg 2988 sound/soc/codecs/wm8962.c if (reg & WM8962_MICDET_STS) { reg 2993 sound/soc/codecs/wm8962.c if (reg & WM8962_MICSHORT_STS) { reg 3012 sound/soc/codecs/wm8962.c int reg, ret; reg 3060 sound/soc/codecs/wm8962.c WM8962_THERMAL_SHUTDOWN_STATUS, ®); reg 3064 sound/soc/codecs/wm8962.c reg = 0; reg 3067 sound/soc/codecs/wm8962.c if (reg & WM8962_TEMP_ERR_HP) reg 3069 sound/soc/codecs/wm8962.c if (reg & WM8962_TEMP_WARN_HP) reg 3071 sound/soc/codecs/wm8962.c if (reg & WM8962_TEMP_ERR_SPK) reg 3073 sound/soc/codecs/wm8962.c if (reg & WM8962_TEMP_WARN_SPK) reg 3160 sound/soc/codecs/wm8962.c int reg = 0; reg 3173 sound/soc/codecs/wm8962.c reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT); reg 3182 sound/soc/codecs/wm8962.c WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg); reg 3538 sound/soc/codecs/wm8962.c unsigned int reg; reg 3601 sound/soc/codecs/wm8962.c ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, ®); reg 3606 sound/soc/codecs/wm8962.c if (reg != 0x6243) { reg 3608 sound/soc/codecs/wm8962.c "Device is not a WM8962, ID %x != 0x6243\n", reg); reg 3613 sound/soc/codecs/wm8962.c ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, ®); reg 3621 sound/soc/codecs/wm8962.c (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT, reg 3622 sound/soc/codecs/wm8962.c ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT) reg 325 sound/soc/codecs/wm8974.c u16 reg; reg 329 sound/soc/codecs/wm8974.c reg = snd_soc_component_read32(component, WM8974_CLOCK); reg 330 sound/soc/codecs/wm8974.c snd_soc_component_write(component, WM8974_CLOCK, reg & 0x0ff); reg 333 sound/soc/codecs/wm8974.c reg = snd_soc_component_read32(component, WM8974_POWER1); reg 334 sound/soc/codecs/wm8974.c snd_soc_component_write(component, WM8974_POWER1, reg & 0x1df); reg 344 sound/soc/codecs/wm8974.c reg = snd_soc_component_read32(component, WM8974_POWER1); reg 345 sound/soc/codecs/wm8974.c snd_soc_component_write(component, WM8974_POWER1, reg | 0x020); reg 348 sound/soc/codecs/wm8974.c reg = snd_soc_component_read32(component, WM8974_CLOCK); reg 349 sound/soc/codecs/wm8974.c snd_soc_component_write(component, WM8974_CLOCK, reg | 0x100); reg 361 sound/soc/codecs/wm8974.c u16 reg; reg 365 sound/soc/codecs/wm8974.c reg = snd_soc_component_read32(component, WM8974_GPIO) & 0x1cf; reg 366 sound/soc/codecs/wm8974.c snd_soc_component_write(component, WM8974_GPIO, reg | div); reg 369 sound/soc/codecs/wm8974.c reg = snd_soc_component_read32(component, WM8974_CLOCK) & 0x11f; reg 370 sound/soc/codecs/wm8974.c snd_soc_component_write(component, WM8974_CLOCK, reg | div); reg 373 sound/soc/codecs/wm8974.c reg = snd_soc_component_read32(component, WM8974_CLOCK) & 0x1e3; reg 374 sound/soc/codecs/wm8974.c snd_soc_component_write(component, WM8974_CLOCK, reg | div); reg 90 sound/soc/codecs/wm8978.c static bool wm8978_volatile(struct device *dev, unsigned int reg) reg 92 sound/soc/codecs/wm8978.c return reg == WM8978_RESET; reg 493 sound/soc/codecs/wm8983.c unsigned int reg; reg 495 sound/soc/codecs/wm8983.c reg = snd_soc_component_read32(component, WM8983_EQ1_LOW_SHELF); reg 496 sound/soc/codecs/wm8983.c if (reg & WM8983_EQ3DMODE) reg 545 sound/soc/codecs/wm8983.c static bool wm8983_writeable(struct device *dev, unsigned int reg) reg 547 sound/soc/codecs/wm8983.c switch (reg) { reg 105 sound/soc/codecs/wm8985.c static bool wm8985_writeable(struct device *dev, unsigned int reg) reg 107 sound/soc/codecs/wm8985.c switch (reg) { reg 593 sound/soc/codecs/wm8985.c unsigned int reg; reg 595 sound/soc/codecs/wm8985.c reg = snd_soc_component_read32(component, WM8985_EQ1_LOW_SHELF); reg 596 sound/soc/codecs/wm8985.c if (reg & WM8985_EQ3DMODE) reg 69 sound/soc/codecs/wm8988.c static bool wm8988_writeable(struct device *dev, unsigned int reg) reg 71 sound/soc/codecs/wm8988.c switch (reg) { reg 35 sound/soc/codecs/wm8990.c static bool wm8990_volatile_register(struct device *dev, unsigned int reg) reg 37 sound/soc/codecs/wm8990.c switch (reg) { reg 134 sound/soc/codecs/wm8990.c int reg = mc->reg; reg 143 sound/soc/codecs/wm8990.c val = snd_soc_component_read32(component, reg); reg 144 sound/soc/codecs/wm8990.c return snd_soc_component_write(component, reg, val | 0x0100); reg 147 sound/soc/codecs/wm8990.c #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\ reg 149 sound/soc/codecs/wm8990.c SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \ reg 376 sound/soc/codecs/wm8990.c u16 reg; reg 380 sound/soc/codecs/wm8990.c reg = snd_soc_component_read32(component, WM8990_OUTPUT_MIXER1); reg 381 sound/soc/codecs/wm8990.c if (reg & WM8990_LDLO) { reg 388 sound/soc/codecs/wm8990.c reg = snd_soc_component_read32(component, WM8990_OUTPUT_MIXER2); reg 389 sound/soc/codecs/wm8990.c if (reg & WM8990_RDRO) { reg 396 sound/soc/codecs/wm8990.c reg = snd_soc_component_read32(component, WM8990_SPEAKER_MIXER); reg 397 sound/soc/codecs/wm8990.c if (reg & WM8990_LDSPK) { reg 404 sound/soc/codecs/wm8990.c reg = snd_soc_component_read32(component, WM8990_SPEAKER_MIXER); reg 405 sound/soc/codecs/wm8990.c if (reg & WM8990_RDSPK) { reg 100 sound/soc/codecs/wm8991.c static bool wm8991_volatile(struct device *dev, unsigned int reg) reg 102 sound/soc/codecs/wm8991.c switch (reg) { reg 133 sound/soc/codecs/wm8991.c int reg = kcontrol->private_value & 0xff; reg 142 sound/soc/codecs/wm8991.c val = snd_soc_component_read32(component, reg); reg 143 sound/soc/codecs/wm8991.c return snd_soc_component_write(component, reg, val | 0x0100); reg 363 sound/soc/codecs/wm8991.c u16 reg; reg 367 sound/soc/codecs/wm8991.c reg = snd_soc_component_read32(component, WM8991_OUTPUT_MIXER1); reg 368 sound/soc/codecs/wm8991.c if (reg & WM8991_LDLO) { reg 376 sound/soc/codecs/wm8991.c reg = snd_soc_component_read32(component, WM8991_OUTPUT_MIXER2); reg 377 sound/soc/codecs/wm8991.c if (reg & WM8991_RDRO) { reg 385 sound/soc/codecs/wm8991.c reg = snd_soc_component_read32(component, WM8991_SPEAKER_MIXER); reg 386 sound/soc/codecs/wm8991.c if (reg & WM8991_LDSPK) { reg 394 sound/soc/codecs/wm8991.c reg = snd_soc_component_read32(component, WM8991_SPEAKER_MIXER); reg 395 sound/soc/codecs/wm8991.c if (reg & WM8991_RDSPK) { reg 925 sound/soc/codecs/wm8991.c u16 reg; reg 933 sound/soc/codecs/wm8991.c reg = snd_soc_component_read32(component, WM8991_POWER_MANAGEMENT_2); reg 934 sound/soc/codecs/wm8991.c reg |= WM8991_PLL_ENA; reg 935 sound/soc/codecs/wm8991.c snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_2, reg); reg 938 sound/soc/codecs/wm8991.c reg = snd_soc_component_read32(component, WM8991_CLOCKING_2); reg 939 sound/soc/codecs/wm8991.c snd_soc_component_write(component, WM8991_CLOCKING_2, reg | WM8991_SYSCLK_SRC); reg 948 sound/soc/codecs/wm8991.c reg = snd_soc_component_read32(component, WM8991_POWER_MANAGEMENT_2); reg 949 sound/soc/codecs/wm8991.c reg &= ~WM8991_PLL_ENA; reg 950 sound/soc/codecs/wm8991.c snd_soc_component_write(component, WM8991_POWER_MANAGEMENT_2, reg); reg 1015 sound/soc/codecs/wm8991.c u16 reg; reg 1019 sound/soc/codecs/wm8991.c reg = snd_soc_component_read32(component, WM8991_CLOCKING_2) & reg 1021 sound/soc/codecs/wm8991.c snd_soc_component_write(component, WM8991_CLOCKING_2, reg | div); reg 1024 sound/soc/codecs/wm8991.c reg = snd_soc_component_read32(component, WM8991_CLOCKING_2) & reg 1026 sound/soc/codecs/wm8991.c snd_soc_component_write(component, WM8991_CLOCKING_2, reg | div); reg 1029 sound/soc/codecs/wm8991.c reg = snd_soc_component_read32(component, WM8991_CLOCKING_2) & reg 1031 sound/soc/codecs/wm8991.c snd_soc_component_write(component, WM8991_CLOCKING_2, reg | div); reg 1034 sound/soc/codecs/wm8991.c reg = snd_soc_component_read32(component, WM8991_CLOCKING_1) & reg 1036 sound/soc/codecs/wm8991.c snd_soc_component_write(component, WM8991_CLOCKING_1, reg | div); reg 810 sound/soc/codecs/wm8991.h #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\ reg 812 sound/soc/codecs/wm8991.h SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \ reg 223 sound/soc/codecs/wm8993.c static bool wm8993_volatile(struct device *dev, unsigned int reg) reg 225 sound/soc/codecs/wm8993.c switch (reg) { reg 238 sound/soc/codecs/wm8993.c static bool wm8993_readable(struct device *dev, unsigned int reg) reg 240 sound/soc/codecs/wm8993.c switch (reg) { reg 579 sound/soc/codecs/wm8993.c unsigned int reg; reg 586 sound/soc/codecs/wm8993.c reg = snd_soc_component_read32(component, WM8993_CLOCKING_2); reg 587 sound/soc/codecs/wm8993.c reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC); reg 589 sound/soc/codecs/wm8993.c reg |= WM8993_MCLK_DIV; reg 592 sound/soc/codecs/wm8993.c reg &= ~WM8993_MCLK_DIV; reg 595 sound/soc/codecs/wm8993.c snd_soc_component_write(component, WM8993_CLOCKING_2, reg); reg 602 sound/soc/codecs/wm8993.c reg = snd_soc_component_read32(component, WM8993_CLOCKING_2); reg 603 sound/soc/codecs/wm8993.c reg |= WM8993_SYSCLK_SRC; reg 605 sound/soc/codecs/wm8993.c reg |= WM8993_MCLK_DIV; reg 608 sound/soc/codecs/wm8993.c reg &= ~WM8993_MCLK_DIV; reg 611 sound/soc/codecs/wm8993.c snd_soc_component_write(component, WM8993_CLOCKING_2, reg); reg 1336 sound/soc/codecs/wm8993.c unsigned int reg; reg 1338 sound/soc/codecs/wm8993.c reg = snd_soc_component_read32(component, WM8993_DAC_CTRL); reg 1341 sound/soc/codecs/wm8993.c reg |= WM8993_DAC_MUTE; reg 1343 sound/soc/codecs/wm8993.c reg &= ~WM8993_DAC_MUTE; reg 1345 sound/soc/codecs/wm8993.c snd_soc_component_write(component, WM8993_DAC_CTRL, reg); reg 1630 sound/soc/codecs/wm8993.c unsigned int reg; reg 1667 sound/soc/codecs/wm8993.c ret = regmap_read(wm8993->regmap, WM8993_SOFTWARE_RESET, ®); reg 1673 sound/soc/codecs/wm8993.c if (reg != 0x8993) { reg 1674 sound/soc/codecs/wm8993.c dev_err(&i2c->dev, "Invalid ID register value %x\n", reg); reg 47 sound/soc/codecs/wm8994.c unsigned int reg; reg 250 sound/soc/codecs/wm8994.c int reg = snd_soc_component_read32(component, WM8994_CLOCKING_1); reg 254 sound/soc/codecs/wm8994.c if (reg & WM8994_SYSCLK_SRC) reg 290 sound/soc/codecs/wm8994.c #define WM8994_DRC_SWITCH(xname, reg, shift) \ reg 291 sound/soc/codecs/wm8994.c SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \ reg 309 sound/soc/codecs/wm8994.c ret = snd_soc_component_read32(component, mc->reg); reg 1006 sound/soc/codecs/wm8994.c int reg, reg_r; reg 1009 sound/soc/codecs/wm8994.c reg = snd_soc_component_read32(component, WM8994_DAC1_LEFT_MIXER_ROUTING); reg 1010 sound/soc/codecs/wm8994.c switch (reg) { reg 1024 sound/soc/codecs/wm8994.c dev_vdbg(component->dev, "DAC mixer setting: %x\n", reg); reg 1029 sound/soc/codecs/wm8994.c if (reg_r != reg) { reg 1113 sound/soc/codecs/wm8994.c snd_soc_component_write(component, wm8994_vu_bits[i].reg, reg 1115 sound/soc/codecs/wm8994.c wm8994_vu_bits[i].reg)); reg 1196 sound/soc/codecs/wm8994.c snd_soc_component_write(component, wm8994_vu_bits[i].reg, reg 1198 sound/soc/codecs/wm8994.c wm8994_vu_bits[i].reg)); reg 1440 sound/soc/codecs/wm8994.c #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ reg 1441 sound/soc/codecs/wm8994.c SOC_SINGLE_EXT(xname, reg, shift, max, invert, \ reg 2141 sound/soc/codecs/wm8994.c u16 reg, clk1, aif_reg, aif_src; reg 2160 sound/soc/codecs/wm8994.c reg = snd_soc_component_read32(component, WM8994_FLL1_CONTROL_1 + reg_offset); reg 2161 sound/soc/codecs/wm8994.c was_enabled = reg & WM8994_FLL1_ENA; reg 2206 sound/soc/codecs/wm8994.c reg = snd_soc_component_read32(component, aif_reg); reg 2208 sound/soc/codecs/wm8994.c if ((reg & WM8994_AIF1CLK_ENA) && reg 2209 sound/soc/codecs/wm8994.c (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) { reg 2227 sound/soc/codecs/wm8994.c reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) | reg 2231 sound/soc/codecs/wm8994.c WM8994_FLL1_FRATIO_MASK, reg); reg 2282 sound/soc/codecs/wm8994.c reg = WM8994_FLL1_ENA; reg 2285 sound/soc/codecs/wm8994.c reg |= WM8994_FLL1_FRAC; reg 2287 sound/soc/codecs/wm8994.c reg |= WM8994_FLL1_OSC_ENA; reg 2291 sound/soc/codecs/wm8994.c WM8994_FLL1_FRAC, reg); reg 2998 sound/soc/codecs/wm8994.c int reg; reg 3012 sound/soc/codecs/wm8994.c reg = WM8994_AIF1DAC1_MUTE; reg 3014 sound/soc/codecs/wm8994.c reg = 0; reg 3016 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, mute_reg, WM8994_AIF1DAC1_MUTE, reg); reg 3024 sound/soc/codecs/wm8994.c int reg, val, mask; reg 3028 sound/soc/codecs/wm8994.c reg = WM8994_AIF1_MASTER_SLAVE; reg 3032 sound/soc/codecs/wm8994.c reg = WM8994_AIF2_MASTER_SLAVE; reg 3044 sound/soc/codecs/wm8994.c return snd_soc_component_update_bits(component, reg, mask, val); reg 3368 sound/soc/codecs/wm8994.c int reg, ret; reg 3408 sound/soc/codecs/wm8994.c reg = WM8994_MICD_ENA; reg 3410 sound/soc/codecs/wm8994.c reg = 0; reg 3412 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, WM8994_MICBIAS, WM8994_MICD_ENA, reg); reg 3433 sound/soc/codecs/wm8994.c unsigned int reg; reg 3439 sound/soc/codecs/wm8994.c ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, ®); reg 3447 sound/soc/codecs/wm8994.c dev_dbg(dev, "Microphone status: %x\n", reg); reg 3450 sound/soc/codecs/wm8994.c if (reg & WM8994_MIC1_DET_STS) { reg 3454 sound/soc/codecs/wm8994.c if (reg & WM8994_MIC1_SHRT_STS) { reg 3469 sound/soc/codecs/wm8994.c if (reg & WM8994_MIC2_DET_STS) { reg 3473 sound/soc/codecs/wm8994.c if (reg & WM8994_MIC2_SHRT_STS) { reg 3670 sound/soc/codecs/wm8994.c int reg, delay; reg 3679 sound/soc/codecs/wm8994.c reg = snd_soc_component_read32(component, WM1811_JACKDET_CTRL); reg 3680 sound/soc/codecs/wm8994.c if (reg < 0) { reg 3681 sound/soc/codecs/wm8994.c dev_err(component->dev, "Failed to read jack status: %d\n", reg); reg 3687 sound/soc/codecs/wm8994.c dev_dbg(component->dev, "JACKDET %x\n", reg); reg 3689 sound/soc/codecs/wm8994.c present = reg & WM1811_JACKDET_LVL; reg 3883 sound/soc/codecs/wm8994.c int reg, count, ret, id_delay; reg 3903 sound/soc/codecs/wm8994.c reg = snd_soc_component_read32(component, WM8958_MIC_DETECT_3); reg 3904 sound/soc/codecs/wm8994.c if (reg < 0) { reg 3907 sound/soc/codecs/wm8994.c reg); reg 3912 sound/soc/codecs/wm8994.c if (!(reg & WM8958_MICD_VALID)) { reg 3917 sound/soc/codecs/wm8994.c if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK)) reg 3940 sound/soc/codecs/wm8994.c } else if (!(reg & WM8958_MICD_STS)) { reg 3948 sound/soc/codecs/wm8994.c wm8994->mic_status = reg; reg 3956 sound/soc/codecs/wm8994.c wm8958_button_det(component, reg); reg 3995 sound/soc/codecs/wm8994.c unsigned int reg; reg 4191 sound/soc/codecs/wm8994.c ret = regmap_read(control->regmap, WM8994_GPIO_1, ®); reg 4196 sound/soc/codecs/wm8994.c if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { reg 4203 sound/soc/codecs/wm8994.c ret = regmap_read(control->regmap, WM8994_GPIO_6, ®); reg 4208 sound/soc/codecs/wm8994.c if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { reg 4219 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, wm8994_vu_bits[i].reg, reg 489 sound/soc/codecs/wm8995.c int reg, reg_r; reg 492 sound/soc/codecs/wm8995.c reg = snd_soc_component_read32(component, WM8995_DAC1_LEFT_MIXER_ROUTING); reg 493 sound/soc/codecs/wm8995.c switch (reg) { reg 507 sound/soc/codecs/wm8995.c dev_dbg(component->dev, "DAC mixer setting: %x\n", reg); reg 513 sound/soc/codecs/wm8995.c if (reg_r != reg) { reg 535 sound/soc/codecs/wm8995.c unsigned int reg; reg 538 sound/soc/codecs/wm8995.c reg = snd_soc_component_read32(component, WM8995_CLOCKING_1); reg 540 sound/soc/codecs/wm8995.c if (reg & WM8995_SYSCLK_SRC) reg 589 sound/soc/codecs/wm8995.c unsigned int reg, unsigned int val, unsigned int mask) reg 594 sound/soc/codecs/wm8995.c __func__, reg, val, mask); reg 596 sound/soc/codecs/wm8995.c snd_soc_component_write(component, reg, val); reg 611 sound/soc/codecs/wm8995.c unsigned int reg; reg 613 sound/soc/codecs/wm8995.c reg = snd_soc_component_read32(component, WM8995_ANALOGUE_HP_1); reg 629 sound/soc/codecs/wm8995.c reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY; reg 630 sound/soc/codecs/wm8995.c snd_soc_component_write(component, WM8995_ANALOGUE_HP_1, reg); reg 641 sound/soc/codecs/wm8995.c reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT | reg 643 sound/soc/codecs/wm8995.c snd_soc_component_write(component, WM8995_ANALOGUE_HP_1, reg); reg 1180 sound/soc/codecs/wm8995.c static bool wm8995_readable(struct device *dev, unsigned int reg) reg 1182 sound/soc/codecs/wm8995.c switch (reg) { reg 1401 sound/soc/codecs/wm8995.c static bool wm8995_volatile(struct device *dev, unsigned int reg) reg 1403 sound/soc/codecs/wm8995.c switch (reg) { reg 1684 sound/soc/codecs/wm8995.c int reg, val, mask; reg 1688 sound/soc/codecs/wm8995.c reg = WM8995_AIF1_MASTER_SLAVE; reg 1692 sound/soc/codecs/wm8995.c reg = WM8995_AIF2_MASTER_SLAVE; reg 1696 sound/soc/codecs/wm8995.c reg = WM8995_POWER_MANAGEMENT_5; reg 1708 sound/soc/codecs/wm8995.c return snd_soc_component_update_bits(component, reg, mask, val); reg 1802 sound/soc/codecs/wm8995.c u16 reg, aif1, aif2; reg 1868 sound/soc/codecs/wm8995.c reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) | reg 1872 sound/soc/codecs/wm8995.c WM8995_FLL1_FRATIO_MASK, reg); reg 4236 sound/soc/codecs/wm8995.h #define WM8995_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ reg 4237 sound/soc/codecs/wm8995.h SOC_SINGLE_EXT(xname, reg, shift, max, invert, \ reg 1296 sound/soc/codecs/wm8996.c static bool wm8996_readable_register(struct device *dev, unsigned int reg) reg 1302 sound/soc/codecs/wm8996.c switch (reg) { reg 1503 sound/soc/codecs/wm8996.c static bool wm8996_volatile_register(struct device *dev, unsigned int reg) reg 1505 sound/soc/codecs/wm8996.c switch (reg) { reg 2008 sound/soc/codecs/wm8996.c int ret, reg, retry; reg 2035 sound/soc/codecs/wm8996.c reg = 0; reg 2038 sound/soc/codecs/wm8996.c reg = 1; reg 2041 sound/soc/codecs/wm8996.c reg = 2; reg 2044 sound/soc/codecs/wm8996.c reg = 3; reg 2051 sound/soc/codecs/wm8996.c reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT; reg 2052 sound/soc/codecs/wm8996.c reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT; reg 2056 sound/soc/codecs/wm8996.c WM8996_FLL_REFCLK_SRC_MASK, reg); reg 2058 sound/soc/codecs/wm8996.c reg = 0; reg 2060 sound/soc/codecs/wm8996.c reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT); reg 2062 sound/soc/codecs/wm8996.c reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT; reg 2063 sound/soc/codecs/wm8996.c snd_soc_component_write(component, WM8996_FLL_EFS_2, reg); reg 2163 sound/soc/codecs/wm8996.c unsigned int reg; reg 2166 sound/soc/codecs/wm8996.c ret = regmap_read(wm8996->regmap, WM8996_GPIO_1 + offset, ®); reg 2170 sound/soc/codecs/wm8996.c return (reg & WM8996_GP1_LVL) != 0; reg 2287 sound/soc/codecs/wm8996.c int val, reg, report; reg 2294 sound/soc/codecs/wm8996.c reg = snd_soc_component_read32(component, WM8996_HEADPHONE_DETECT_2); reg 2295 sound/soc/codecs/wm8996.c if (reg < 0) { reg 2300 sound/soc/codecs/wm8996.c if (!(reg & WM8996_HP_DONE)) { reg 2305 sound/soc/codecs/wm8996.c val = reg & WM8996_HP_LVL_MASK; reg 2384 sound/soc/codecs/wm8996.c int val, reg; reg 2452 sound/soc/codecs/wm8996.c reg = snd_soc_component_read32(component, WM8996_ACCESSORY_DETECT_MODE_2); reg 2453 sound/soc/codecs/wm8996.c reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC | reg 2457 sound/soc/codecs/wm8996.c WM8996_MICD_BIAS_SRC, reg); reg 2461 sound/soc/codecs/wm8996.c (reg & WM8996_MICD_SRC) != 0); reg 2464 sound/soc/codecs/wm8996.c (reg & WM8996_MICD_SRC) != 0); reg 2760 sound/soc/codecs/wm8996.c unsigned int reg; reg 2829 sound/soc/codecs/wm8996.c ret = regmap_read(wm8996->regmap, WM8996_SOFTWARE_RESET, ®); reg 2834 sound/soc/codecs/wm8996.c if (reg != 0x8915) { reg 2835 sound/soc/codecs/wm8996.c dev_err(&i2c->dev, "Device is not a WM8996, ID %x\n", reg); reg 2840 sound/soc/codecs/wm8996.c ret = regmap_read(wm8996->regmap, WM8996_CHIP_REVISION, ®); reg 2848 sound/soc/codecs/wm8996.c (reg & WM8996_CHIP_REV_MASK) + 'A'); reg 3021 sound/soc/codecs/wm8996.c ret = regmap_read(wm8996->regmap, WM8996_GPIO_1, ®); reg 3027 sound/soc/codecs/wm8996.c if (reg & WM8996_GP1_FN_MASK) reg 3032 sound/soc/codecs/wm8996.c ret = regmap_read(wm8996->regmap, WM8996_GPIO_2, ®); reg 3038 sound/soc/codecs/wm8996.c if (reg & WM8996_GP2_FN_MASK) reg 103 sound/soc/codecs/wm8997.c regmap_write_async(regmap, patch[i].reg, reg 116 sound/soc/codecs/wm8998.c switch (e->reg) { reg 140 sound/soc/codecs/wm8998.c snd_soc_component_update_bits(component, e->reg, reg 159 sound/soc/codecs/wm9081.c static bool wm9081_volatile_register(struct device *dev, unsigned int reg) reg 161 sound/soc/codecs/wm9081.c switch (reg) { reg 170 sound/soc/codecs/wm9081.c static bool wm9081_readable_register(struct device *dev, unsigned int reg) reg 172 sound/soc/codecs/wm9081.c switch (reg) { reg 339 sound/soc/codecs/wm9081.c unsigned int reg; reg 341 sound/soc/codecs/wm9081.c reg = snd_soc_component_read32(component, WM9081_ANALOGUE_SPEAKER_2); reg 342 sound/soc/codecs/wm9081.c if (reg & WM9081_SPK_MODE) reg 640 sound/soc/codecs/wm9081.c unsigned int reg; reg 710 sound/soc/codecs/wm9081.c reg = snd_soc_component_read32(component, WM9081_CLOCK_CONTROL_1); reg 712 sound/soc/codecs/wm9081.c reg |= WM9081_MCLKDIV2; reg 714 sound/soc/codecs/wm9081.c reg &= ~WM9081_MCLKDIV2; reg 715 sound/soc/codecs/wm9081.c snd_soc_component_write(component, WM9081_CLOCK_CONTROL_1, reg); reg 717 sound/soc/codecs/wm9081.c reg = snd_soc_component_read32(component, WM9081_CLOCK_CONTROL_3); reg 719 sound/soc/codecs/wm9081.c reg |= WM9081_CLK_SRC_SEL; reg 721 sound/soc/codecs/wm9081.c reg &= ~WM9081_CLK_SRC_SEL; reg 722 sound/soc/codecs/wm9081.c snd_soc_component_write(component, WM9081_CLOCK_CONTROL_3, reg); reg 1153 sound/soc/codecs/wm9081.c unsigned int reg; reg 1155 sound/soc/codecs/wm9081.c reg = snd_soc_component_read32(component, WM9081_DAC_DIGITAL_2); reg 1158 sound/soc/codecs/wm9081.c reg |= WM9081_DAC_MUTE; reg 1160 sound/soc/codecs/wm9081.c reg &= ~WM9081_DAC_MUTE; reg 1162 sound/soc/codecs/wm9081.c snd_soc_component_write(component, WM9081_DAC_DIGITAL_2, reg); reg 1305 sound/soc/codecs/wm9081.c unsigned int reg; reg 1322 sound/soc/codecs/wm9081.c ret = regmap_read(wm9081->regmap, WM9081_SOFTWARE_RESET, ®); reg 1327 sound/soc/codecs/wm9081.c if (reg != 0x9081) { reg 1328 sound/soc/codecs/wm9081.c dev_err(&i2c->dev, "Device is not a WM9081: ID=0x%x\n", reg); reg 1342 sound/soc/codecs/wm9081.c reg = 0; reg 1344 sound/soc/codecs/wm9081.c reg |= WM9081_IRQ_POL; reg 1346 sound/soc/codecs/wm9081.c reg |= WM9081_IRQ_OP_CTRL; reg 1348 sound/soc/codecs/wm9081.c WM9081_IRQ_POL | WM9081_IRQ_OP_CTRL, reg); reg 68 sound/soc/codecs/wm9090.c static bool wm9090_volatile(struct device *dev, unsigned int reg) reg 70 sound/soc/codecs/wm9090.c switch (reg) { reg 83 sound/soc/codecs/wm9090.c static bool wm9090_readable(struct device *dev, unsigned int reg) reg 85 sound/soc/codecs/wm9090.c switch (reg) { reg 135 sound/soc/codecs/wm9090.c unsigned int reg; reg 142 sound/soc/codecs/wm9090.c reg = snd_soc_component_read32(component, WM9090_DC_SERVO_READBACK_0); reg 143 sound/soc/codecs/wm9090.c dev_dbg(component->dev, "DC servo status: %x\n", reg); reg 144 sound/soc/codecs/wm9090.c } while ((reg & WM9090_DCS_CAL_COMPLETE_MASK) reg 147 sound/soc/codecs/wm9090.c if ((reg & WM9090_DCS_CAL_COMPLETE_MASK) reg 242 sound/soc/codecs/wm9090.c unsigned int reg = snd_soc_component_read32(component, WM9090_ANALOGUE_HP_0); reg 255 sound/soc/codecs/wm9090.c reg |= WM9090_HPOUT1L_DLY | WM9090_HPOUT1R_DLY; reg 256 sound/soc/codecs/wm9090.c snd_soc_component_write(component, WM9090_ANALOGUE_HP_0, reg); reg 271 sound/soc/codecs/wm9090.c reg |= WM9090_HPOUT1R_OUTP | WM9090_HPOUT1R_RMV_SHORT | reg 273 sound/soc/codecs/wm9090.c snd_soc_component_write(component, WM9090_ANALOGUE_HP_0, reg); reg 277 sound/soc/codecs/wm9090.c reg &= ~(WM9090_HPOUT1L_RMV_SHORT | reg 284 sound/soc/codecs/wm9090.c snd_soc_component_write(component, WM9090_ANALOGUE_HP_0, reg); reg 568 sound/soc/codecs/wm9090.c unsigned int reg; reg 582 sound/soc/codecs/wm9090.c ret = regmap_read(wm9090->regmap, WM9090_SOFTWARE_RESET, ®); reg 586 sound/soc/codecs/wm9090.c if (reg != 0x9093) { reg 587 sound/soc/codecs/wm9090.c dev_err(&i2c->dev, "Device is not a WM9090, ID=%x\n", reg); reg 235 sound/soc/codecs/wm9705.c int reg; reg 240 sound/soc/codecs/wm9705.c reg = AC97_PCM_FRONT_DAC_RATE; reg 242 sound/soc/codecs/wm9705.c reg = AC97_PCM_LR_ADC_RATE; reg 244 sound/soc/codecs/wm9705.c return snd_soc_component_write(component, reg, substream->runtime->rate); reg 74 sound/soc/codecs/wm9712.c static bool wm9712_volatile_reg(struct device *dev, unsigned int reg) reg 76 sound/soc/codecs/wm9712.c switch (reg) { reg 80 sound/soc/codecs/wm9712.c return regmap_ac97_default_volatile(dev, reg); reg 242 sound/soc/codecs/wm9712.c update.reg = wm9712_mixer_mute_regs[shift]; reg 527 sound/soc/codecs/wm9712.c int reg; reg 533 sound/soc/codecs/wm9712.c reg = AC97_PCM_FRONT_DAC_RATE; reg 535 sound/soc/codecs/wm9712.c reg = AC97_PCM_LR_ADC_RATE; reg 537 sound/soc/codecs/wm9712.c return snd_soc_component_write(component, reg, runtime->rate); reg 251 sound/soc/codecs/wm9713.c update.reg = wm9713_mixer_mute_regs[shift]; reg 647 sound/soc/codecs/wm9713.c static bool wm9713_readable_reg(struct device *dev, unsigned int reg) reg 649 sound/soc/codecs/wm9713.c switch (reg) { reg 663 sound/soc/codecs/wm9713.c static bool wm9713_writeable_reg(struct device *dev, unsigned int reg) reg 665 sound/soc/codecs/wm9713.c switch (reg) { reg 670 sound/soc/codecs/wm9713.c return wm9713_readable_reg(dev, reg); reg 818 sound/soc/codecs/wm9713.c u16 reg, reg2; reg 833 sound/soc/codecs/wm9713.c reg = (pll_div.n << 12) | (pll_div.lf << 11) | reg 835 sound/soc/codecs/wm9713.c snd_soc_component_write(component, AC97_LINE1_LEVEL, reg); reg 842 sound/soc/codecs/wm9713.c reg = reg2 | (0x5 << 4) | (pll_div.k >> 20); reg 843 sound/soc/codecs/wm9713.c snd_soc_component_write(component, AC97_LINE1_LEVEL, reg); reg 846 sound/soc/codecs/wm9713.c reg = reg2 | (0x4 << 4) | ((pll_div.k >> 16) & 0xf); reg 847 sound/soc/codecs/wm9713.c snd_soc_component_write(component, AC97_LINE1_LEVEL, reg); reg 850 sound/soc/codecs/wm9713.c reg = reg2 | (0x3 << 4) | ((pll_div.k >> 12) & 0xf); reg 851 sound/soc/codecs/wm9713.c snd_soc_component_write(component, AC97_LINE1_LEVEL, reg); reg 854 sound/soc/codecs/wm9713.c reg = reg2 | (0x2 << 4) | ((pll_div.k >> 8) & 0xf); reg 855 sound/soc/codecs/wm9713.c snd_soc_component_write(component, AC97_LINE1_LEVEL, reg); reg 858 sound/soc/codecs/wm9713.c reg = reg2 | (0x1 << 4) | ((pll_div.k >> 4) & 0xf); reg 859 sound/soc/codecs/wm9713.c snd_soc_component_write(component, AC97_LINE1_LEVEL, reg); reg 861 sound/soc/codecs/wm9713.c reg = reg2 | (0x0 << 4) | (pll_div.k & 0xf); /* K [3:0] */ reg 862 sound/soc/codecs/wm9713.c snd_soc_component_write(component, AC97_LINE1_LEVEL, reg); reg 943 sound/soc/codecs/wm9713.c u16 reg = 0x8000; reg 948 sound/soc/codecs/wm9713.c reg |= 0x4000; reg 952 sound/soc/codecs/wm9713.c reg |= 0x6000; reg 956 sound/soc/codecs/wm9713.c reg |= 0x2000; reg 967 sound/soc/codecs/wm9713.c reg |= 0x00c0; reg 970 sound/soc/codecs/wm9713.c reg |= 0x0080; reg 973 sound/soc/codecs/wm9713.c reg |= 0x0040; reg 980 sound/soc/codecs/wm9713.c reg |= 0x0002; reg 985 sound/soc/codecs/wm9713.c reg |= 0x0001; reg 988 sound/soc/codecs/wm9713.c reg |= 0x0003; reg 991 sound/soc/codecs/wm9713.c reg |= 0x0043; reg 996 sound/soc/codecs/wm9713.c snd_soc_component_write(component, AC97_CENTER_LFE_MASTER, reg); reg 1031 sound/soc/codecs/wm9713.c int reg; reg 1036 sound/soc/codecs/wm9713.c reg = AC97_PCM_FRONT_DAC_RATE; reg 1038 sound/soc/codecs/wm9713.c reg = AC97_PCM_LR_ADC_RATE; reg 1040 sound/soc/codecs/wm9713.c return snd_soc_component_write(component, reg, runtime->rate); reg 928 sound/soc/codecs/wm_adsp.c static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg) reg 941 sound/soc/codecs/wm_adsp.c *reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset); reg 975 sound/soc/codecs/wm_adsp.c unsigned int reg; reg 978 sound/soc/codecs/wm_adsp.c ret = wm_coeff_base_reg(ctl, ®); reg 986 sound/soc/codecs/wm_adsp.c ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); reg 988 sound/soc/codecs/wm_adsp.c adsp_err(dsp, "Failed to write %x: %d\n", reg, ret); reg 1010 sound/soc/codecs/wm_adsp.c ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); reg 1012 sound/soc/codecs/wm_adsp.c adsp_err(dsp, "Failed to read %x: %d\n", reg, ret); reg 1023 sound/soc/codecs/wm_adsp.c reg, ctl->alg_region.alg, reg 1036 sound/soc/codecs/wm_adsp.c unsigned int reg; reg 1038 sound/soc/codecs/wm_adsp.c ret = wm_coeff_base_reg(ctl, ®); reg 1046 sound/soc/codecs/wm_adsp.c ret = regmap_raw_write(dsp->regmap, reg, scratch, reg 1050 sound/soc/codecs/wm_adsp.c len, reg, ret); reg 1054 sound/soc/codecs/wm_adsp.c adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg); reg 1141 sound/soc/codecs/wm_adsp.c unsigned int reg; reg 1143 sound/soc/codecs/wm_adsp.c ret = wm_coeff_base_reg(ctl, ®); reg 1151 sound/soc/codecs/wm_adsp.c ret = regmap_raw_read(dsp->regmap, reg, scratch, len); reg 1154 sound/soc/codecs/wm_adsp.c len, reg, ret); reg 1158 sound/soc/codecs/wm_adsp.c adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg); reg 1811 sound/soc/codecs/wm_adsp.c unsigned int reg; reg 1878 sound/soc/codecs/wm_adsp.c reg = 0; reg 1902 sound/soc/codecs/wm_adsp.c reg = offset; reg 1919 sound/soc/codecs/wm_adsp.c reg = dsp->ops->region_to_reg(mem, offset); reg 1949 sound/soc/codecs/wm_adsp.c if (reg) { reg 1959 sound/soc/codecs/wm_adsp.c ret = regmap_raw_write_async(regmap, reg, buf->buf, reg 2017 sound/soc/codecs/wm_adsp.c unsigned int reg; reg 2032 sound/soc/codecs/wm_adsp.c reg = dsp->ops->region_to_reg(mem, pos + len); reg 2034 sound/soc/codecs/wm_adsp.c ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); reg 2043 sound/soc/codecs/wm_adsp.c reg, be32_to_cpu(val)); reg 2052 sound/soc/codecs/wm_adsp.c reg = dsp->ops->region_to_reg(mem, pos); reg 2054 sound/soc/codecs/wm_adsp.c ret = regmap_raw_read(dsp->regmap, reg, alg, len); reg 2465 sound/soc/codecs/wm_adsp.c int ret, pos, blocks, type, offset, reg; reg 2530 sound/soc/codecs/wm_adsp.c reg = 0; reg 2549 sound/soc/codecs/wm_adsp.c reg = dsp->ops->region_to_reg(mem, 0); reg 2553 sound/soc/codecs/wm_adsp.c reg = offset; reg 2577 sound/soc/codecs/wm_adsp.c reg = alg_region->base; reg 2578 sound/soc/codecs/wm_adsp.c reg = dsp->ops->region_to_reg(mem, reg); reg 2579 sound/soc/codecs/wm_adsp.c reg += offset; reg 2592 sound/soc/codecs/wm_adsp.c if (reg) { reg 2615 sound/soc/codecs/wm_adsp.c reg); reg 2616 sound/soc/codecs/wm_adsp.c ret = regmap_raw_write_async(regmap, reg, buf->buf, reg 2621 sound/soc/codecs/wm_adsp.c file, blocks, reg, region_name, ret); reg 3559 sound/soc/codecs/wm_adsp.c unsigned int i, reg; reg 3565 sound/soc/codecs/wm_adsp.c reg = dsp->ops->region_to_reg(mem, mem_addr); reg 3567 sound/soc/codecs/wm_adsp.c ret = regmap_raw_read(dsp->regmap, reg, data, reg 3588 sound/soc/codecs/wm_adsp.c unsigned int reg; reg 3593 sound/soc/codecs/wm_adsp.c reg = dsp->ops->region_to_reg(mem, mem_addr); reg 3597 sound/soc/codecs/wm_adsp.c return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data)); reg 3750 sound/soc/codecs/wm_adsp.c unsigned int val, reg; reg 3753 sound/soc/codecs/wm_adsp.c ret = wm_coeff_base_reg(ctl, ®); reg 3758 sound/soc/codecs/wm_adsp.c ret = regmap_raw_read(ctl->dsp->regmap, reg, &val, sizeof(val)); reg 3793 sound/soc/codecs/wm_adsp.c ret = regmap_raw_read(ctl->dsp->regmap, reg, &coeff_v1, reg 148 sound/soc/codecs/wm_adsp.h .reg = SND_SOC_NOPM, .shift = num, .event = event_fn, \ reg 152 sound/soc/codecs/wm_adsp.h .reg = SND_SOC_NOPM, .shift = num, .event = wm_adsp_event, \ reg 62 sound/soc/codecs/wm_hubs.c unsigned int reg; reg 88 sound/soc/codecs/wm_hubs.c reg = snd_soc_component_read32(component, WM8993_DC_SERVO_0); reg 89 sound/soc/codecs/wm_hubs.c dev_dbg(component->dev, "DC servo: %x\n", reg); reg 90 sound/soc/codecs/wm_hubs.c } while (reg & op && count < timeout); reg 92 sound/soc/codecs/wm_hubs.c if (reg & op) reg 109 sound/soc/codecs/wm_hubs.c int reg; reg 112 sound/soc/codecs/wm_hubs.c reg = snd_soc_component_read32(component, WM8993_OUTPUT_MIXER1); reg 113 sound/soc/codecs/wm_hubs.c if (!(reg & WM8993_DACL_TO_HPOUT1L)) { reg 114 sound/soc/codecs/wm_hubs.c if (reg & ~WM8993_DACL_TO_MIXOUTL) { reg 116 sound/soc/codecs/wm_hubs.c reg & ~WM8993_DACL_TO_HPOUT1L); reg 125 sound/soc/codecs/wm_hubs.c reg = snd_soc_component_read32(component, WM8993_OUTPUT_MIXER2); reg 126 sound/soc/codecs/wm_hubs.c if (!(reg & WM8993_DACR_TO_HPOUT1R)) { reg 127 sound/soc/codecs/wm_hubs.c if (reg & ~WM8993_DACR_TO_MIXOUTR) { reg 129 sound/soc/codecs/wm_hubs.c reg & ~WM8993_DACR_TO_HPOUT1R); reg 199 sound/soc/codecs/wm_hubs.c u16 dcs_reg, reg; reg 226 sound/soc/codecs/wm_hubs.c reg = snd_soc_component_read32(component, dcs_reg); reg 227 sound/soc/codecs/wm_hubs.c *reg_r = (reg & WM8993_DCS_DAC_WR_VAL_1_MASK) reg 229 sound/soc/codecs/wm_hubs.c *reg_l = reg & WM8993_DCS_DAC_WR_VAL_0_MASK; reg 541 sound/soc/codecs/wm_hubs.c unsigned int reg = snd_soc_component_read32(component, WM8993_ANALOGUE_HP_0); reg 554 sound/soc/codecs/wm_hubs.c reg |= WM8993_HPOUT1L_DLY | WM8993_HPOUT1R_DLY; reg 555 sound/soc/codecs/wm_hubs.c snd_soc_component_write(component, WM8993_ANALOGUE_HP_0, reg); reg 562 sound/soc/codecs/wm_hubs.c reg |= WM8993_HPOUT1R_OUTP | WM8993_HPOUT1R_RMV_SHORT | reg 564 sound/soc/codecs/wm_hubs.c snd_soc_component_write(component, WM8993_ANALOGUE_HP_0, reg); reg 593 sound/soc/codecs/wm_hubs.c u16 reg = snd_soc_component_read32(component, WM8993_ANTIPOP1) & ~WM8993_HPOUT2_IN_ENA; reg 597 sound/soc/codecs/wm_hubs.c reg |= WM8993_HPOUT2_IN_ENA; reg 598 sound/soc/codecs/wm_hubs.c snd_soc_component_write(component, WM8993_ANTIPOP1, reg); reg 603 sound/soc/codecs/wm_hubs.c snd_soc_component_write(component, WM8993_ANTIPOP1, reg); reg 689 sound/soc/codecs/wm_hubs.c #define WM_HUBS_SINGLE_W(xname, reg, shift, max, invert) \ reg 690 sound/soc/codecs/wm_hubs.c SOC_SINGLE_EXT(xname, reg, shift, max, invert, \ reg 29 sound/soc/dwc/dwc-i2s.c static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val) reg 31 sound/soc/dwc/dwc-i2s.c writel(val, io_base + reg); reg 34 sound/soc/dwc/dwc-i2s.c static inline u32 i2s_read_reg(void __iomem *io_base, int reg) reg 36 sound/soc/dwc/dwc-i2s.c return readl(io_base + reg); reg 430 sound/soc/fsl/fsl_asrc.c int reg, retry = 10, i; reg 439 sound/soc/fsl/fsl_asrc.c regmap_read(asrc_priv->regmap, REG_ASRCFG, ®); reg 440 sound/soc/fsl/fsl_asrc.c reg &= ASRCFG_INIRQi_MASK(index); reg 441 sound/soc/fsl/fsl_asrc.c } while (!reg && --retry); reg 444 sound/soc/fsl/fsl_asrc.c regmap_read(asrc_priv->regmap, REG_ASRCNCR, ®); reg 632 sound/soc/fsl/fsl_asrc.c static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg) reg 634 sound/soc/fsl/fsl_asrc.c switch (reg) { reg 676 sound/soc/fsl/fsl_asrc.c static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg) reg 678 sound/soc/fsl/fsl_asrc.c switch (reg) { reg 696 sound/soc/fsl/fsl_asrc.c static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg) reg 698 sound/soc/fsl/fsl_asrc.c switch (reg) { reg 377 sound/soc/fsl/fsl_audmix.c static bool fsl_audmix_readable_reg(struct device *dev, unsigned int reg) reg 379 sound/soc/fsl/fsl_audmix.c switch (reg) { reg 402 sound/soc/fsl/fsl_audmix.c static bool fsl_audmix_writeable_reg(struct device *dev, unsigned int reg) reg 404 sound/soc/fsl/fsl_audmix.c switch (reg) { reg 824 sound/soc/fsl/fsl_esai.c static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg) reg 826 sound/soc/fsl/fsl_esai.c switch (reg) { reg 856 sound/soc/fsl/fsl_esai.c static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg) reg 858 sound/soc/fsl/fsl_esai.c switch (reg) { reg 874 sound/soc/fsl/fsl_esai.c static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg) reg 876 sound/soc/fsl/fsl_esai.c switch (reg) { reg 478 sound/soc/fsl/fsl_micfil.c static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg) reg 480 sound/soc/fsl/fsl_micfil.c switch (reg) { reg 510 sound/soc/fsl/fsl_micfil.c static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg) reg 512 sound/soc/fsl/fsl_micfil.c switch (reg) { reg 533 sound/soc/fsl/fsl_micfil.c static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg) reg 535 sound/soc/fsl/fsl_micfil.c switch (reg) { reg 769 sound/soc/fsl/fsl_sai.c static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) reg 774 sound/soc/fsl/fsl_sai.c if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) reg 777 sound/soc/fsl/fsl_sai.c if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) reg 780 sound/soc/fsl/fsl_sai.c switch (reg) { reg 813 sound/soc/fsl/fsl_sai.c static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) reg 818 sound/soc/fsl/fsl_sai.c if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) reg 821 sound/soc/fsl/fsl_sai.c switch (reg) { reg 852 sound/soc/fsl/fsl_sai.c static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) reg 857 sound/soc/fsl/fsl_sai.c if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) reg 860 sound/soc/fsl/fsl_sai.c if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) reg 863 sound/soc/fsl/fsl_sai.c switch (reg) { reg 148 sound/soc/fsl/fsl_spdif.c u32 *pos, size, val, reg; reg 154 sound/soc/fsl/fsl_spdif.c reg = REG_SPDIF_SRU; reg 159 sound/soc/fsl/fsl_spdif.c reg = REG_SPDIF_SRQ; reg 175 sound/soc/fsl/fsl_spdif.c regmap_read(regmap, reg, &val); reg 1031 sound/soc/fsl/fsl_spdif.c static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg) reg 1033 sound/soc/fsl/fsl_spdif.c switch (reg) { reg 1055 sound/soc/fsl/fsl_spdif.c static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg) reg 1057 sound/soc/fsl/fsl_spdif.c switch (reg) { reg 1073 sound/soc/fsl/fsl_spdif.c static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg) reg 1075 sound/soc/fsl/fsl_spdif.c switch (reg) { reg 125 sound/soc/fsl/fsl_ssi.c static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg) reg 127 sound/soc/fsl/fsl_ssi.c switch (reg) { reg 136 sound/soc/fsl/fsl_ssi.c static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) reg 138 sound/soc/fsl/fsl_ssi.c switch (reg) { reg 157 sound/soc/fsl/fsl_ssi.c static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg) reg 159 sound/soc/fsl/fsl_ssi.c switch (reg) { reg 172 sound/soc/fsl/fsl_ssi.c static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg) reg 174 sound/soc/fsl/fsl_ssi.c switch (reg) { reg 1162 sound/soc/fsl/fsl_ssi.c static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, reg 1170 sound/soc/fsl/fsl_ssi.c if (reg > 0x7f) reg 1182 sound/soc/fsl/fsl_ssi.c lreg = reg << 12; reg 1199 sound/soc/fsl/fsl_ssi.c unsigned short reg) reg 1215 sound/soc/fsl/fsl_ssi.c lreg = (reg & 0x7f) << 12; reg 237 sound/soc/fsl/imx-ssi.c u32 reg, sccr; reg 241 sound/soc/fsl/imx-ssi.c reg = SSI_STCCR; reg 243 sound/soc/fsl/imx-ssi.c reg = SSI_SRCCR; reg 246 sound/soc/fsl/imx-ssi.c reg = SSI_STCCR; reg 248 sound/soc/fsl/imx-ssi.c sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK; reg 263 sound/soc/fsl/imx-ssi.c writel(sccr, ssi->base + reg); reg 430 sound/soc/fsl/imx-ssi.c static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, reg 438 sound/soc/fsl/imx-ssi.c if (reg > 0x7f) reg 441 sound/soc/fsl/imx-ssi.c pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val); reg 443 sound/soc/fsl/imx-ssi.c lreg = reg << 12; reg 454 sound/soc/fsl/imx-ssi.c unsigned short reg) reg 462 sound/soc/fsl/imx-ssi.c lreg = (reg & 0x7f) << 12 ; reg 470 sound/soc/fsl/imx-ssi.c pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val); reg 30 sound/soc/fsl/mpc5200_psc_ac97.c static unsigned short psc_ac97_read(struct snd_ac97 *ac97, unsigned short reg) reg 50 sound/soc/fsl/mpc5200_psc_ac97.c out_be32(&psc_dma->psc_regs->ac97_cmd, (1<<31) | ((reg & 0x7f) << 24)); reg 63 sound/soc/fsl/mpc5200_psc_ac97.c if (((val >> 24) & 0x7f) != reg) { reg 75 sound/soc/fsl/mpc5200_psc_ac97.c unsigned short reg, unsigned short val) reg 90 sound/soc/fsl/mpc5200_psc_ac97.c ((reg & 0x7f) << 24) | (val << 8)); reg 71 sound/soc/fsl/mx27vis-aic32x4.c unsigned int reg = mc->reg; reg 77 sound/soc/fsl/mx27vis-aic32x4.c switch (reg) { reg 97 sound/soc/fsl/mx27vis-aic32x4.c unsigned int reg = mc->reg; reg 99 sound/soc/fsl/mx27vis-aic32x4.c switch (reg) { reg 66 sound/soc/generic/audio-graph-card.c const u32 *reg; reg 87 sound/soc/generic/audio-graph-card.c reg = of_get_property(node, "reg", NULL); reg 89 sound/soc/generic/audio-graph-card.c if (reg) reg 81 sound/soc/hisilicon/hi6210-i2s.c static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val) reg 83 sound/soc/hisilicon/hi6210-i2s.c writel(val, i2s->base + reg); reg 86 sound/soc/hisilicon/hi6210-i2s.c static inline u32 hi6210_read_reg(struct hi6210_i2s *i2s, int reg) reg 88 sound/soc/hisilicon/hi6210-i2s.c return readl(i2s->base + reg); reg 88 sound/soc/img/img-i2s-in.c static inline void img_i2s_in_writel(struct img_i2s_in *i2s, u32 val, u32 reg) reg 90 sound/soc/img/img-i2s-in.c writel(val, i2s->base + reg); reg 93 sound/soc/img/img-i2s-in.c static inline u32 img_i2s_in_readl(struct img_i2s_in *i2s, u32 reg) reg 95 sound/soc/img/img-i2s-in.c return readl(i2s->base + reg); reg 99 sound/soc/img/img-i2s-in.c u32 val, u32 reg) reg 101 sound/soc/img/img-i2s-in.c writel(val, i2s->channel_base + (chan * IMG_I2S_IN_CH_STRIDE) + reg); reg 105 sound/soc/img/img-i2s-in.c u32 reg) reg 107 sound/soc/img/img-i2s-in.c return readl(i2s->channel_base + (chan * IMG_I2S_IN_CH_STRIDE) + reg); reg 112 sound/soc/img/img-i2s-in.c u32 reg; reg 114 sound/soc/img/img-i2s-in.c reg = img_i2s_in_ch_readl(i2s, chan, IMG_I2S_IN_CH_CTL); reg 115 sound/soc/img/img-i2s-in.c reg &= ~IMG_I2S_IN_CH_CTL_ME_MASK; reg 116 sound/soc/img/img-i2s-in.c img_i2s_in_ch_writel(i2s, chan, reg, IMG_I2S_IN_CH_CTL); reg 121 sound/soc/img/img-i2s-in.c u32 reg; reg 123 sound/soc/img/img-i2s-in.c reg = img_i2s_in_ch_readl(i2s, chan, IMG_I2S_IN_CH_CTL); reg 124 sound/soc/img/img-i2s-in.c reg |= IMG_I2S_IN_CH_CTL_ME_MASK; reg 125 sound/soc/img/img-i2s-in.c img_i2s_in_ch_writel(i2s, chan, reg, IMG_I2S_IN_CH_CTL); reg 130 sound/soc/img/img-i2s-in.c u32 reg; reg 132 sound/soc/img/img-i2s-in.c reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL); reg 133 sound/soc/img/img-i2s-in.c reg &= ~IMG_I2S_IN_CTL_ME_MASK; reg 134 sound/soc/img/img-i2s-in.c img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL); reg 139 sound/soc/img/img-i2s-in.c u32 reg; reg 141 sound/soc/img/img-i2s-in.c reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL); reg 142 sound/soc/img/img-i2s-in.c reg |= IMG_I2S_IN_CTL_ME_MASK; reg 143 sound/soc/img/img-i2s-in.c img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL); reg 149 sound/soc/img/img-i2s-in.c u32 reg; reg 152 sound/soc/img/img-i2s-in.c reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL); reg 153 sound/soc/img/img-i2s-in.c reg |= IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK; reg 154 sound/soc/img/img-i2s-in.c img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL); reg 155 sound/soc/img/img-i2s-in.c reg &= ~IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK; reg 156 sound/soc/img/img-i2s-in.c img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL); reg 221 sound/soc/img/img-i2s-in.c u32 reg, control_mask, chan_control_mask; reg 279 sound/soc/img/img-i2s-in.c reg = img_i2s_in_readl(i2s, IMG_I2S_IN_CTL); reg 280 sound/soc/img/img-i2s-in.c reg = (reg & ~control_mask) | control_set; reg 281 sound/soc/img/img-i2s-in.c img_i2s_in_writel(i2s, reg, IMG_I2S_IN_CTL); reg 287 sound/soc/img/img-i2s-in.c reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL); reg 288 sound/soc/img/img-i2s-in.c reg = (reg & ~chan_control_mask) | chan_control_set; reg 289 sound/soc/img/img-i2s-in.c img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL); reg 307 sound/soc/img/img-i2s-in.c u32 reg; reg 356 sound/soc/img/img-i2s-in.c reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL); reg 357 sound/soc/img/img-i2s-in.c reg = (reg & ~chan_control_mask) | chan_control_set; reg 358 sound/soc/img/img-i2s-in.c img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL); reg 359 sound/soc/img/img-i2s-in.c reg = (reg & ~IMG_I2S_IN_CH_CTL_BLKP_MASK) | blkp_set; reg 360 sound/soc/img/img-i2s-in.c img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL); reg 361 sound/soc/img/img-i2s-in.c reg = (reg & ~IMG_I2S_IN_CH_CTL_LRD_MASK) | lrd_set; reg 362 sound/soc/img/img-i2s-in.c img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL); reg 550 sound/soc/img/img-i2s-in.c u32 reg; reg 559 sound/soc/img/img-i2s-in.c reg = img_i2s_in_ch_readl(i2s, i, IMG_I2S_IN_CH_CTL); reg 560 sound/soc/img/img-i2s-in.c i2s->suspend_ch_ctl[i] = reg; reg 574 sound/soc/img/img-i2s-in.c u32 reg; reg 581 sound/soc/img/img-i2s-in.c reg = i2s->suspend_ch_ctl[i]; reg 582 sound/soc/img/img-i2s-in.c img_i2s_in_ch_writel(i2s, i, reg, IMG_I2S_IN_CH_CTL); reg 99 sound/soc/img/img-i2s-out.c u32 reg) reg 101 sound/soc/img/img-i2s-out.c writel(val, i2s->base + reg); reg 104 sound/soc/img/img-i2s-out.c static inline u32 img_i2s_out_readl(struct img_i2s_out *i2s, u32 reg) reg 106 sound/soc/img/img-i2s-out.c return readl(i2s->base + reg); reg 110 sound/soc/img/img-i2s-out.c u32 chan, u32 val, u32 reg) reg 112 sound/soc/img/img-i2s-out.c writel(val, i2s->channel_base + (chan * IMG_I2S_OUT_CH_STRIDE) + reg); reg 116 sound/soc/img/img-i2s-out.c u32 reg) reg 118 sound/soc/img/img-i2s-out.c return readl(i2s->channel_base + (chan * IMG_I2S_OUT_CH_STRIDE) + reg); reg 123 sound/soc/img/img-i2s-out.c u32 reg; reg 125 sound/soc/img/img-i2s-out.c reg = img_i2s_out_ch_readl(i2s, chan, IMG_I2S_OUT_CH_CTL); reg 126 sound/soc/img/img-i2s-out.c reg &= ~IMG_I2S_OUT_CHAN_CTL_ME_MASK; reg 127 sound/soc/img/img-i2s-out.c img_i2s_out_ch_writel(i2s, chan, reg, IMG_I2S_OUT_CH_CTL); reg 132 sound/soc/img/img-i2s-out.c u32 reg; reg 134 sound/soc/img/img-i2s-out.c reg = img_i2s_out_ch_readl(i2s, chan, IMG_I2S_OUT_CH_CTL); reg 135 sound/soc/img/img-i2s-out.c reg |= IMG_I2S_OUT_CHAN_CTL_ME_MASK; reg 136 sound/soc/img/img-i2s-out.c img_i2s_out_ch_writel(i2s, chan, reg, IMG_I2S_OUT_CH_CTL); reg 141 sound/soc/img/img-i2s-out.c u32 reg; reg 143 sound/soc/img/img-i2s-out.c reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL); reg 144 sound/soc/img/img-i2s-out.c reg &= ~IMG_I2S_OUT_CTL_ME_MASK; reg 145 sound/soc/img/img-i2s-out.c img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL); reg 150 sound/soc/img/img-i2s-out.c u32 reg; reg 152 sound/soc/img/img-i2s-out.c reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL); reg 153 sound/soc/img/img-i2s-out.c reg |= IMG_I2S_OUT_CTL_ME_MASK; reg 154 sound/soc/img/img-i2s-out.c img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL); reg 189 sound/soc/img/img-i2s-out.c u32 reg; reg 195 sound/soc/img/img-i2s-out.c reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL); reg 197 sound/soc/img/img-i2s-out.c reg |= IMG_I2S_OUT_CTL_CLK_EN_MASK; reg 198 sound/soc/img/img-i2s-out.c reg |= IMG_I2S_OUT_CTL_DATA_EN_MASK; reg 199 sound/soc/img/img-i2s-out.c img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL); reg 220 sound/soc/img/img-i2s-out.c u32 reg, control_mask, control_set = 0; reg 274 sound/soc/img/img-i2s-out.c reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL); reg 275 sound/soc/img/img-i2s-out.c reg = (reg & ~control_mask) | control_set; reg 276 sound/soc/img/img-i2s-out.c img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL); reg 297 sound/soc/img/img-i2s-out.c u32 reg, control_set = 0; reg 355 sound/soc/img/img-i2s-out.c reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL); reg 356 sound/soc/img/img-i2s-out.c reg = (reg & ~control_mask) | control_set; reg 357 sound/soc/img/img-i2s-out.c img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL); reg 363 sound/soc/img/img-i2s-out.c reg = img_i2s_out_ch_readl(i2s, i, IMG_I2S_OUT_CH_CTL); reg 364 sound/soc/img/img-i2s-out.c reg = (reg & ~chan_control_mask) | chan_control_set; reg 365 sound/soc/img/img-i2s-out.c img_i2s_out_ch_writel(i2s, i, reg, IMG_I2S_OUT_CH_CTL); reg 430 sound/soc/img/img-i2s-out.c u32 reg; reg 494 sound/soc/img/img-i2s-out.c reg = IMG_I2S_OUT_CTL_FRM_SIZE_MASK; reg 495 sound/soc/img/img-i2s-out.c img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL); reg 497 sound/soc/img/img-i2s-out.c reg = IMG_I2S_OUT_CHAN_CTL_JUST_MASK | reg 503 sound/soc/img/img-i2s-out.c img_i2s_out_ch_writel(i2s, i, reg, IMG_I2S_OUT_CH_CTL); reg 555 sound/soc/img/img-i2s-out.c u32 reg; reg 564 sound/soc/img/img-i2s-out.c reg = img_i2s_out_ch_readl(i2s, i, IMG_I2S_OUT_CH_CTL); reg 565 sound/soc/img/img-i2s-out.c i2s->suspend_ch_ctl[i] = reg; reg 579 sound/soc/img/img-i2s-out.c u32 reg; reg 586 sound/soc/img/img-i2s-out.c reg = i2s->suspend_ch_ctl[i]; reg 587 sound/soc/img/img-i2s-out.c img_i2s_out_ch_writel(i2s, i, reg, IMG_I2S_OUT_CH_CTL); reg 68 sound/soc/img/img-parallel-out.c u32 val, u32 reg) reg 70 sound/soc/img/img-parallel-out.c writel(val, prl->base + reg); reg 73 sound/soc/img/img-parallel-out.c static inline u32 img_prl_out_readl(struct img_prl_out *prl, u32 reg) reg 75 sound/soc/img/img-parallel-out.c return readl(prl->base + reg); reg 95 sound/soc/img/img-parallel-out.c u32 reg; reg 101 sound/soc/img/img-parallel-out.c reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL); reg 102 sound/soc/img/img-parallel-out.c reg |= IMG_PRL_OUT_CTL_ME_MASK; reg 103 sound/soc/img/img-parallel-out.c img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL); reg 122 sound/soc/img/img-parallel-out.c u32 reg, control_set = 0; reg 142 sound/soc/img/img-parallel-out.c reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL); reg 143 sound/soc/img/img-parallel-out.c reg = (reg & ~IMG_PRL_OUT_CTL_PACKH_MASK) | control_set; reg 144 sound/soc/img/img-parallel-out.c img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL); reg 152 sound/soc/img/img-parallel-out.c u32 reg, control_set = 0; reg 169 sound/soc/img/img-parallel-out.c reg = img_prl_out_readl(prl, IMG_PRL_OUT_CTL); reg 170 sound/soc/img/img-parallel-out.c reg = (reg & ~IMG_PRL_OUT_CTL_EDGE_MASK) | control_set; reg 171 sound/soc/img/img-parallel-out.c img_prl_out_writel(prl, reg, IMG_PRL_OUT_CTL); reg 114 sound/soc/img/img-spdif-in.c u32 val, u32 reg) reg 116 sound/soc/img/img-spdif-in.c writel(val, spdif->base + reg); reg 119 sound/soc/img/img-spdif-in.c static inline u32 img_spdif_in_readl(struct img_spdif_in *spdif, u32 reg) reg 121 sound/soc/img/img-spdif-in.c return readl(spdif->base + reg); reg 184 sound/soc/img/img-spdif-in.c u32 reg; reg 194 sound/soc/img/img-spdif-in.c reg = (nom << IMG_SPDIF_IN_CLKGEN_NOM_SHIFT) & reg 196 sound/soc/img/img-spdif-in.c reg |= (hld << IMG_SPDIF_IN_CLKGEN_HLD_SHIFT) & reg 206 sound/soc/img/img-spdif-in.c img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CLKGEN); reg 221 sound/soc/img/img-spdif-in.c u32 reg, trk_reg, temp_regs[IMG_SPDIF_IN_NUM_ACLKGEN]; reg 238 sound/soc/img/img-spdif-in.c reg = (nom << IMG_SPDIF_IN_ACLKGEN_NOM_SHIFT) & reg 240 sound/soc/img/img-spdif-in.c reg |= (hld << IMG_SPDIF_IN_ACLKGEN_HLD_SHIFT) & reg 242 sound/soc/img/img-spdif-in.c temp_regs[i] = reg; reg 296 sound/soc/img/img-spdif-in.c u32 reg; reg 298 sound/soc/img/img-spdif-in.c reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CSL); reg 299 sound/soc/img/img-spdif-in.c ucontrol->value.iec958.status[0] = reg & 0xff; reg 300 sound/soc/img/img-spdif-in.c ucontrol->value.iec958.status[1] = (reg >> 8) & 0xff; reg 301 sound/soc/img/img-spdif-in.c ucontrol->value.iec958.status[2] = (reg >> 16) & 0xff; reg 302 sound/soc/img/img-spdif-in.c ucontrol->value.iec958.status[3] = (reg >> 24) & 0xff; reg 303 sound/soc/img/img-spdif-in.c reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CSH); reg 304 sound/soc/img/img-spdif-in.c ucontrol->value.iec958.status[4] = (reg & IMG_SPDIF_IN_CSH_MASK) reg 400 sound/soc/img/img-spdif-in.c u32 reg; reg 406 sound/soc/img/img-spdif-in.c reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_STATUS); reg 407 sound/soc/img/img-spdif-in.c if (reg & IMG_SPDIF_IN_STATUS_LOCK_MASK) { reg 409 sound/soc/img/img-spdif-in.c i = ((reg & IMG_SPDIF_IN_STATUS_SAM_MASK) >> reg 453 sound/soc/img/img-spdif-in.c u32 reg; reg 464 sound/soc/img/img-spdif-in.c reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CTL); reg 465 sound/soc/img/img-spdif-in.c reg &= ~IMG_SPDIF_IN_CTL_TRK_MASK; reg 466 sound/soc/img/img-spdif-in.c reg |= spdif->trk << IMG_SPDIF_IN_CTL_TRK_SHIFT; reg 467 sound/soc/img/img-spdif-in.c img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CTL); reg 510 sound/soc/img/img-spdif-in.c u32 reg; reg 521 sound/soc/img/img-spdif-in.c reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CTL); reg 522 sound/soc/img/img-spdif-in.c reg &= ~IMG_SPDIF_IN_CTL_LOCKHI_MASK; reg 523 sound/soc/img/img-spdif-in.c reg |= (spdif->lock_acquire << IMG_SPDIF_IN_CTL_LOCKHI_SHIFT) & reg 525 sound/soc/img/img-spdif-in.c img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CTL); reg 549 sound/soc/img/img-spdif-in.c u32 reg; reg 560 sound/soc/img/img-spdif-in.c reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CTL); reg 561 sound/soc/img/img-spdif-in.c reg &= ~IMG_SPDIF_IN_CTL_LOCKLO_MASK; reg 562 sound/soc/img/img-spdif-in.c reg |= (spdif->lock_release << IMG_SPDIF_IN_CTL_LOCKLO_SHIFT) & reg 564 sound/soc/img/img-spdif-in.c img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CTL); reg 631 sound/soc/img/img-spdif-in.c u32 reg; reg 639 sound/soc/img/img-spdif-in.c reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CTL); reg 641 sound/soc/img/img-spdif-in.c reg &= ~IMG_SPDIF_IN_CTL_SRD_MASK; reg 643 sound/soc/img/img-spdif-in.c reg |= (1UL << IMG_SPDIF_IN_CTL_SRD_SHIFT); reg 644 sound/soc/img/img-spdif-in.c reg |= IMG_SPDIF_IN_CTL_SRT_MASK; reg 645 sound/soc/img/img-spdif-in.c img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CTL); reg 651 sound/soc/img/img-spdif-in.c reg = img_spdif_in_readl(spdif, IMG_SPDIF_IN_CTL); reg 652 sound/soc/img/img-spdif-in.c reg &= ~IMG_SPDIF_IN_CTL_SRT_MASK; reg 653 sound/soc/img/img-spdif-in.c img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CTL); reg 724 sound/soc/img/img-spdif-in.c u32 reg; reg 783 sound/soc/img/img-spdif-in.c reg = (spdif->lock_acquire << IMG_SPDIF_IN_CTL_LOCKHI_SHIFT) & reg 785 sound/soc/img/img-spdif-in.c reg |= (spdif->lock_release << IMG_SPDIF_IN_CTL_LOCKLO_SHIFT) & reg 787 sound/soc/img/img-spdif-in.c reg |= (spdif->trk << IMG_SPDIF_IN_CTL_TRK_SHIFT) & reg 789 sound/soc/img/img-spdif-in.c img_spdif_in_writel(spdif, reg, IMG_SPDIF_IN_CTL); reg 84 sound/soc/img/img-spdif-out.c u32 reg) reg 86 sound/soc/img/img-spdif-out.c writel(val, spdif->base + reg); reg 89 sound/soc/img/img-spdif-out.c static inline u32 img_spdif_out_readl(struct img_spdif_out *spdif, u32 reg) reg 91 sound/soc/img/img-spdif-out.c return readl(spdif->base + reg); reg 137 sound/soc/img/img-spdif-out.c u32 reg; reg 142 sound/soc/img/img-spdif-out.c reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSL); reg 143 sound/soc/img/img-spdif-out.c ucontrol->value.iec958.status[0] = reg & 0xff; reg 144 sound/soc/img/img-spdif-out.c ucontrol->value.iec958.status[1] = (reg >> 8) & 0xff; reg 145 sound/soc/img/img-spdif-out.c ucontrol->value.iec958.status[2] = (reg >> 16) & 0xff; reg 146 sound/soc/img/img-spdif-out.c ucontrol->value.iec958.status[3] = (reg >> 24) & 0xff; reg 148 sound/soc/img/img-spdif-out.c reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV); reg 150 sound/soc/img/img-spdif-out.c (reg & IMG_SPDIF_OUT_CSH_UV_CSH_MASK) >> reg 163 sound/soc/img/img-spdif-out.c u32 reg; reg 166 sound/soc/img/img-spdif-out.c reg = ((u32)ucontrol->value.iec958.status[3] << 24); reg 167 sound/soc/img/img-spdif-out.c reg |= ((u32)ucontrol->value.iec958.status[2] << 16); reg 168 sound/soc/img/img-spdif-out.c reg |= ((u32)ucontrol->value.iec958.status[1] << 8); reg 169 sound/soc/img/img-spdif-out.c reg |= (u32)ucontrol->value.iec958.status[0]; reg 173 sound/soc/img/img-spdif-out.c img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CSL); reg 175 sound/soc/img/img-spdif-out.c reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV); reg 176 sound/soc/img/img-spdif-out.c reg &= ~IMG_SPDIF_OUT_CSH_UV_CSH_MASK; reg 177 sound/soc/img/img-spdif-out.c reg |= (u32)ucontrol->value.iec958.status[4] << reg 179 sound/soc/img/img-spdif-out.c img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CSH_UV); reg 207 sound/soc/img/img-spdif-out.c u32 reg; reg 214 sound/soc/img/img-spdif-out.c reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL); reg 215 sound/soc/img/img-spdif-out.c reg |= IMG_SPDIF_OUT_CTL_SRT_MASK; reg 216 sound/soc/img/img-spdif-out.c img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CTL); reg 238 sound/soc/img/img-spdif-out.c u32 reg; reg 280 sound/soc/img/img-spdif-out.c reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL); reg 282 sound/soc/img/img-spdif-out.c reg &= ~IMG_SPDIF_OUT_CTL_CLK_MASK; reg 284 sound/soc/img/img-spdif-out.c reg |= IMG_SPDIF_OUT_CTL_CLK_MASK; reg 285 sound/soc/img/img-spdif-out.c img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CTL); reg 64 sound/soc/img/pistachio-internal-dac.c u32 val, u32 reg) reg 68 sound/soc/img/pistachio-internal-dac.c reg << PISTACHIO_INTERNAL_DAC_GTI_CTRL_ADDR_SHIFT); reg 149 sound/soc/img/pistachio-internal-dac.c u32 reg; reg 181 sound/soc/img/pistachio-internal-dac.c reg = 0; reg 184 sound/soc/img/pistachio-internal-dac.c reg = PISTACHIO_INTERNAL_DAC_CTRL_PWR_SEL_MASK; reg 193 sound/soc/img/pistachio-internal-dac.c PISTACHIO_INTERNAL_DAC_CTRL_PWR_SEL_MASK, reg); reg 157 sound/soc/intel/atom/sst-atom-controls.c unsigned int ctl_no = e->reg; reg 216 sound/soc/intel/atom/sst-atom-controls.c unsigned int ctl_no = e->reg; reg 550 sound/soc/intel/atom/sst-atom-controls.c struct swm_input_ids *swm_input, unsigned int reg) reg 555 sound/soc/intel/atom/sst-atom-controls.c dev_dbg(cmpnt->dev, "reg: %#x\n", reg); reg 557 sound/soc/intel/atom/sst-atom-controls.c is_set = reg & BIT(i); reg 579 sound/soc/intel/atom/sst-atom-controls.h u8 reg; reg 590 sound/soc/intel/atom/sst-atom-controls.h .reg = SND_SOC_NOPM, .shift = 0, \ reg 598 sound/soc/intel/atom/sst-atom-controls.h .reg = SND_SOC_NOPM, .shift = 0, \ reg 606 sound/soc/intel/atom/sst-atom-controls.h .reg = SND_SOC_NOPM, .shift = 0, \ reg 614 sound/soc/intel/atom/sst-atom-controls.h .reg = SND_SOC_NOPM, .shift = 0, \ reg 622 sound/soc/intel/atom/sst-atom-controls.h .reg = SND_SOC_NOPM, .shift = 0, \ reg 630 sound/soc/intel/atom/sst-atom-controls.h { .id = snd_soc_dapm_pga, .name = wname, .reg = SND_SOC_NOPM, .shift = 0, \ reg 638 sound/soc/intel/atom/sst-atom-controls.h { .id = snd_soc_dapm_pga, .name = wname, .reg = SND_SOC_NOPM, .shift = 0, \ reg 647 sound/soc/intel/atom/sst-atom-controls.h { .id = snd_soc_dapm_pga, .name = wname, .reg = SND_SOC_NOPM, .shift = 0, \ reg 674 sound/soc/intel/atom/sst-atom-controls.h { .id = snd_soc_dapm_mixer, .name = wname, .reg = SND_SOC_NOPM, .shift = 0, \ reg 679 sound/soc/intel/atom/sst-atom-controls.h .reg = wreg } \ reg 839 sound/soc/intel/atom/sst-atom-controls.h unsigned short reg; reg 847 sound/soc/intel/atom/sst-atom-controls.h (struct sst_enum){ .reg = s_ch_no, .tx = is_tx, .max = 4+1, .texts = xtexts, } reg 154 sound/soc/intel/baytrail/sst-baytrail-dsp.c u64 reg; reg 157 sound/soc/intel/baytrail/sst-baytrail-dsp.c reg = sst_dsp_shim_read64_unlocked(sst, i); reg 158 sound/soc/intel/baytrail/sst-baytrail-dsp.c if (reg) reg 160 sound/soc/intel/baytrail/sst-baytrail-dsp.c i, reg); reg 164 sound/soc/intel/baytrail/sst-baytrail-dsp.c reg = readl(sst->addr.pci_cfg + i); reg 165 sound/soc/intel/baytrail/sst-baytrail-dsp.c if (reg) reg 167 sound/soc/intel/baytrail/sst-baytrail-dsp.c i, (u32)reg); reg 248 sound/soc/intel/common/sst-dsp.c u32 reg; reg 263 sound/soc/intel/common/sst-dsp.c while ((((reg = sst_dsp_shim_read_unlocked(ctx, offset)) & mask) != target) reg 272 sound/soc/intel/common/sst-dsp.c if ((reg & mask) == target) { reg 274 sound/soc/intel/common/sst-dsp.c reg, operation); reg 280 sound/soc/intel/common/sst-dsp.c reg, operation); reg 249 sound/soc/intel/haswell/sst-haswell-dsp.c u32 reg; reg 252 sound/soc/intel/haswell/sst-haswell-dsp.c reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); reg 253 sound/soc/intel/haswell/sst-haswell-dsp.c reg &= ~(SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE); reg 254 sound/soc/intel/haswell/sst-haswell-dsp.c writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); reg 279 sound/soc/intel/haswell/sst-haswell-dsp.c reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); reg 280 sound/soc/intel/haswell/sst-haswell-dsp.c reg |= SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE; reg 281 sound/soc/intel/haswell/sst-haswell-dsp.c writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); reg 305 sound/soc/intel/haswell/sst-haswell-dsp.c u32 reg, fw_dump_bit; reg 308 sound/soc/intel/haswell/sst-haswell-dsp.c reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); reg 309 sound/soc/intel/haswell/sst-haswell-dsp.c reg &= ~(SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE); reg 310 sound/soc/intel/haswell/sst-haswell-dsp.c writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); reg 313 sound/soc/intel/haswell/sst-haswell-dsp.c reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0); reg 314 sound/soc/intel/haswell/sst-haswell-dsp.c reg |= SST_VDRTCL0_D3PGD; reg 315 sound/soc/intel/haswell/sst-haswell-dsp.c writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0); reg 318 sound/soc/intel/haswell/sst-haswell-dsp.c reg = readl(sst->addr.pci_cfg + SST_PMCS); reg 319 sound/soc/intel/haswell/sst-haswell-dsp.c reg &= ~SST_PMCS_PS_MASK; reg 320 sound/soc/intel/haswell/sst-haswell-dsp.c writel(reg, sst->addr.pci_cfg + SST_PMCS); reg 324 sound/soc/intel/haswell/sst-haswell-dsp.c reg = readl(sst->addr.pci_cfg + SST_PMCS) & SST_PMCS_PS_MASK; reg 325 sound/soc/intel/haswell/sst-haswell-dsp.c if (reg == 0) reg 352 sound/soc/intel/haswell/sst-haswell-dsp.c reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); reg 353 sound/soc/intel/haswell/sst-haswell-dsp.c reg |= SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE; reg 354 sound/soc/intel/haswell/sst-haswell-dsp.c writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); reg 359 sound/soc/intel/haswell/sst-haswell-dsp.c reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); reg 360 sound/soc/intel/haswell/sst-haswell-dsp.c reg &= ~SST_VDRTCL2_APLLSE_MASK; reg 361 sound/soc/intel/haswell/sst-haswell-dsp.c writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2); reg 365 sound/soc/intel/haswell/sst-haswell-dsp.c reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0); reg 366 sound/soc/intel/haswell/sst-haswell-dsp.c reg |= SST_VDRTCL0_DSRAMPGE_MASK | SST_VDRTCL0_ISRAMPGE_MASK; reg 369 sound/soc/intel/haswell/sst-haswell-dsp.c writel(reg & ~fw_dump_bit, sst->addr.pci_cfg + SST_VDRTCTL0); reg 185 sound/soc/intel/haswell/sst-haswell-pcm.c dai = mod_map[mc->reg].dai_id; reg 186 sound/soc/intel/haswell/sst-haswell-pcm.c stream = mod_map[mc->reg].stream; reg 234 sound/soc/intel/haswell/sst-haswell-pcm.c dai = mod_map[mc->reg].dai_id; reg 235 sound/soc/intel/haswell/sst-haswell-pcm.c stream = mod_map[mc->reg].stream; reg 71 sound/soc/intel/skylake/skl-sst.c u32 reg; reg 127 sound/soc/intel/skylake/skl-sst.c reg = sst_dsp_shim_read(ctx, SKL_ADSP_FW_STATUS); reg 129 sound/soc/intel/skylake/skl-sst.c "Timeout waiting for ROM init done, reg:0x%x\n", reg); reg 44 sound/soc/intel/skylake/skl.c static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg, reg 49 sound/soc/intel/skylake/skl.c pci_read_config_byte(pci, reg, &data); reg 52 sound/soc/intel/skylake/skl.c pci_write_config_byte(pci, reg, data); reg 71 sound/soc/intel/skylake/skl.c unsigned int reg, u32 mask, u32 val) reg 75 sound/soc/intel/skylake/skl.c pci_read_config_dword(pci, reg, &data); reg 78 sound/soc/intel/skylake/skl.c pci_write_config_dword(pci, reg, data); reg 148 sound/soc/intel/skylake/skl.c u8 reg; reg 151 sound/soc/intel/skylake/skl.c reg = snd_hdac_chip_readb(bus, VS_D0I3C); reg 153 sound/soc/intel/skylake/skl.c while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { reg 155 sound/soc/intel/skylake/skl.c reg = snd_hdac_chip_readb(bus, VS_D0I3C); reg 165 sound/soc/intel/skylake/skl.c reg = reg | AZX_REG_VS_D0I3C_I3; reg 167 sound/soc/intel/skylake/skl.c reg = reg & (~AZX_REG_VS_D0I3C_I3); reg 169 sound/soc/intel/skylake/skl.c snd_hdac_chip_writeb(bus, VS_D0I3C, reg); reg 173 sound/soc/intel/skylake/skl.c reg = snd_hdac_chip_readb(bus, VS_D0I3C); reg 174 sound/soc/intel/skylake/skl.c while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) { reg 176 sound/soc/intel/skylake/skl.c reg = snd_hdac_chip_readb(bus, VS_D0I3C); reg 111 sound/soc/jz4740/jz4740-i2s.c unsigned int reg) reg 113 sound/soc/jz4740/jz4740-i2s.c return readl(i2s->base + reg); reg 117 sound/soc/jz4740/jz4740-i2s.c unsigned int reg, uint32_t value) reg 119 sound/soc/jz4740/jz4740-i2s.c writel(value, i2s->base + reg); reg 19 sound/soc/mediatek/common/mtk-afe-fe-dai.c static int mtk_regmap_update_bits(struct regmap *map, int reg, reg 23 sound/soc/mediatek/common/mtk-afe-fe-dai.c if (reg < 0 || WARN_ON_ONCE(shift < 0)) reg 25 sound/soc/mediatek/common/mtk-afe-fe-dai.c return regmap_update_bits(map, reg, mask << shift, val << shift); reg 28 sound/soc/mediatek/common/mtk-afe-fe-dai.c static int mtk_regmap_write(struct regmap *map, int reg, unsigned int val) reg 30 sound/soc/mediatek/common/mtk-afe-fe-dai.c if (reg < 0) reg 32 sound/soc/mediatek/common/mtk-afe-fe-dai.c return regmap_write(map, reg, val); reg 179 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c int reg, fs, w_len = 1; /* now we support bck 64bits only */ reg 200 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c reg = ASMI_TIMING_CON1; reg 206 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c reg = ASMO_TIMING_CON1; reg 211 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c regmap_update_bits(afe->regmap, reg, reg 764 sound/soc/mediatek/mt8183/mt8183-afe-pcm.c static bool mt8183_is_volatile_reg(struct device *dev, unsigned int reg) reg 768 sound/soc/mediatek/mt8183/mt8183-afe-pcm.c switch (reg) { reg 150 sound/soc/meson/axg-spdifin.c unsigned int reg, shift, rem; reg 154 sound/soc/meson/axg-spdifin.c reg = offset * regmap_get_reg_stride(map) + base_reg; reg 157 sound/soc/meson/axg-spdifin.c regmap_update_bits(map, reg, GENMASK(width - 1, 0) << shift, reg 51 sound/soc/pxa/mioa701_wm9713.c unsigned short reg; reg 54 sound/soc/pxa/mioa701_wm9713.c reg = snd_soc_component_read32(component, AC97_GPIO_CFG); reg 55 sound/soc/pxa/mioa701_wm9713.c snd_soc_component_write(component, AC97_GPIO_CFG, reg | 0x0100); reg 56 sound/soc/pxa/mioa701_wm9713.c reg = snd_soc_component_read32(component, AC97_GPIO_PULL); reg 57 sound/soc/pxa/mioa701_wm9713.c snd_soc_component_write(component, AC97_GPIO_PULL, reg | (1<<15)); reg 59 sound/soc/pxa/mioa701_wm9713.c reg = snd_soc_component_read32(component, AC97_GPIO_CFG); reg 60 sound/soc/pxa/mioa701_wm9713.c snd_soc_component_write(component, AC97_GPIO_CFG, reg & ~0x0100); reg 61 sound/soc/pxa/mioa701_wm9713.c reg = snd_soc_component_read32(component, AC97_GPIO_PULL); reg 62 sound/soc/pxa/mioa701_wm9713.c snd_soc_component_write(component, AC97_GPIO_PULL, reg & ~(1<<15)); reg 39 sound/soc/pxa/mmp-sspa.c static void mmp_sspa_write_reg(struct ssp_device *sspa, u32 reg, u32 val) reg 41 sound/soc/pxa/mmp-sspa.c __raw_writel(val, sspa->mmio_base + reg); reg 44 sound/soc/pxa/mmp-sspa.c static u32 mmp_sspa_read_reg(struct ssp_device *sspa, u32 reg) reg 46 sound/soc/pxa/mmp-sspa.c return __raw_readl(sspa->mmio_base + reg); reg 43 sound/soc/pxa/pxa2xx-ac97.c unsigned short reg) reg 45 sound/soc/pxa/pxa2xx-ac97.c return pxa2xx_ac97_read(slot, reg); reg 49 sound/soc/pxa/pxa2xx-ac97.c unsigned short reg, unsigned short val) reg 51 sound/soc/pxa/pxa2xx-ac97.c return pxa2xx_ac97_write(slot, reg, val); reg 297 sound/soc/qcom/lpass-cpu.c static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg) reg 304 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_I2SCTL_REG(v, i)) reg 308 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_IRQEN_REG(v, i)) reg 310 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_IRQCLEAR_REG(v, i)) reg 315 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_RDMACTL_REG(v, i)) reg 317 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_RDMABASE_REG(v, i)) reg 319 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_RDMABUFF_REG(v, i)) reg 321 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_RDMAPER_REG(v, i)) reg 326 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start)) reg 328 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start)) reg 330 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start)) reg 332 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start)) reg 339 sound/soc/qcom/lpass-cpu.c static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg) reg 346 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_I2SCTL_REG(v, i)) reg 350 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_IRQEN_REG(v, i)) reg 352 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_IRQSTAT_REG(v, i)) reg 357 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_RDMACTL_REG(v, i)) reg 359 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_RDMABASE_REG(v, i)) reg 361 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_RDMABUFF_REG(v, i)) reg 363 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_RDMACURR_REG(v, i)) reg 365 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_RDMAPER_REG(v, i)) reg 370 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start)) reg 372 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start)) reg 374 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start)) reg 376 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start)) reg 378 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start)) reg 385 sound/soc/qcom/lpass-cpu.c static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg) reg 392 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_IRQSTAT_REG(v, i)) reg 396 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_RDMACURR_REG(v, i)) reg 400 sound/soc/qcom/lpass-cpu.c if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start)) reg 118 sound/soc/qcom/lpass-lpaif-reg.h #define __LPAIF_DMA_REG(v, chan, dir, reg) \ reg 120 sound/soc/qcom/lpass-lpaif-reg.h LPAIF_RDMA##reg##_REG(v, chan) : \ reg 121 sound/soc/qcom/lpass-lpaif-reg.h LPAIF_WRDMA##reg##_REG(v, chan) reg 227 sound/soc/qcom/lpass-platform.c unsigned int reg; reg 230 sound/soc/qcom/lpass-platform.c reg = LPAIF_DMACTL_REG(v, pcm_data->dma_ch, substream->stream); reg 231 sound/soc/qcom/lpass-platform.c ret = regmap_write(drvdata->lpaif_map, reg, 0); reg 420 sound/soc/qcom/qdsp6/q6routing.c if (session->port_id == mc->reg) reg 438 sound/soc/qcom/qdsp6/q6routing.c int be_id = mc->reg; reg 481 sound/soc/rockchip/rockchip_i2s.c static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg) reg 483 sound/soc/rockchip/rockchip_i2s.c switch (reg) { reg 498 sound/soc/rockchip/rockchip_i2s.c static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg) reg 500 sound/soc/rockchip/rockchip_i2s.c switch (reg) { reg 518 sound/soc/rockchip/rockchip_i2s.c static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg) reg 520 sound/soc/rockchip/rockchip_i2s.c switch (reg) { reg 532 sound/soc/rockchip/rockchip_i2s.c static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg) reg 534 sound/soc/rockchip/rockchip_i2s.c switch (reg) { reg 378 sound/soc/rockchip/rockchip_pdm.c static bool rockchip_pdm_wr_reg(struct device *dev, unsigned int reg) reg 380 sound/soc/rockchip/rockchip_pdm.c switch (reg) { reg 397 sound/soc/rockchip/rockchip_pdm.c static bool rockchip_pdm_rd_reg(struct device *dev, unsigned int reg) reg 399 sound/soc/rockchip/rockchip_pdm.c switch (reg) { reg 419 sound/soc/rockchip/rockchip_pdm.c static bool rockchip_pdm_volatile_reg(struct device *dev, unsigned int reg) reg 421 sound/soc/rockchip/rockchip_pdm.c switch (reg) { reg 433 sound/soc/rockchip/rockchip_pdm.c static bool rockchip_pdm_precious_reg(struct device *dev, unsigned int reg) reg 435 sound/soc/rockchip/rockchip_pdm.c switch (reg) { reg 228 sound/soc/rockchip/rockchip_spdif.c static bool rk_spdif_wr_reg(struct device *dev, unsigned int reg) reg 230 sound/soc/rockchip/rockchip_spdif.c switch (reg) { reg 242 sound/soc/rockchip/rockchip_spdif.c static bool rk_spdif_rd_reg(struct device *dev, unsigned int reg) reg 244 sound/soc/rockchip/rockchip_spdif.c switch (reg) { reg 256 sound/soc/rockchip/rockchip_spdif.c static bool rk_spdif_volatile_reg(struct device *dev, unsigned int reg) reg 258 sound/soc/rockchip/rockchip_spdif.c switch (reg) { reg 1011 sound/soc/samsung/i2s.c u32 reg = readl(priv->addr + I2SFIC); reg 1017 sound/soc/samsung/i2s.c delay = FIC_RXCOUNT(reg); reg 1021 sound/soc/samsung/i2s.c delay = (reg >> priv->variant_regs->ftx0cnt_off) & 0x7f; reg 447 sound/soc/samsung/s3c-i2s-v2.c u32 reg; reg 474 sound/soc/samsung/s3c-i2s-v2.c reg = readl(i2s->regs + S3C2412_IISMOD); reg 475 sound/soc/samsung/s3c-i2s-v2.c reg &= ~S3C2412_IISMOD_BCLK_MASK; reg 476 sound/soc/samsung/s3c-i2s-v2.c writel(reg | div, i2s->regs + S3C2412_IISMOD); reg 503 sound/soc/samsung/s3c-i2s-v2.c reg = readl(i2s->regs + S3C2412_IISMOD); reg 504 sound/soc/samsung/s3c-i2s-v2.c reg &= ~S3C2412_IISMOD_RCLK_MASK; reg 505 sound/soc/samsung/s3c-i2s-v2.c writel(reg | div, i2s->regs + S3C2412_IISMOD); reg 530 sound/soc/samsung/s3c-i2s-v2.c u32 reg = readl(i2s->regs + S3C2412_IISFIC); reg 534 sound/soc/samsung/s3c-i2s-v2.c delay = S3C2412_IISFIC_TXCOUNT(reg); reg 536 sound/soc/samsung/s3c-i2s-v2.c delay = S3C2412_IISFIC_RXCOUNT(reg); reg 303 sound/soc/samsung/s3c24xx-i2s.c u32 reg; reg 307 sound/soc/samsung/s3c24xx-i2s.c reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK; reg 308 sound/soc/samsung/s3c24xx-i2s.c writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD); reg 311 sound/soc/samsung/s3c24xx-i2s.c reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS); reg 312 sound/soc/samsung/s3c24xx-i2s.c writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD); reg 316 sound/soc/samsung/s3c24xx-i2s.c reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON); reg 317 sound/soc/samsung/s3c24xx-i2s.c writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON); reg 311 sound/soc/sh/fsi.c static void __fsi_reg_write(u32 __iomem *reg, u32 data) reg 316 sound/soc/sh/fsi.c __raw_writel(data, reg); reg 319 sound/soc/sh/fsi.c static u32 __fsi_reg_read(u32 __iomem *reg) reg 321 sound/soc/sh/fsi.c return __raw_readl(reg); reg 324 sound/soc/sh/fsi.c static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) reg 326 sound/soc/sh/fsi.c u32 val = __fsi_reg_read(reg); reg 331 sound/soc/sh/fsi.c __fsi_reg_write(reg, val); reg 345 sound/soc/sh/fsi.c static u32 _fsi_master_read(struct fsi_master *master, u32 reg) reg 351 sound/soc/sh/fsi.c ret = __fsi_reg_read(master->base + reg); reg 360 sound/soc/sh/fsi.c u32 reg, u32 mask, u32 data) reg 365 sound/soc/sh/fsi.c __fsi_reg_mask_set(master->base + reg, mask, data); reg 94 sound/soc/sh/hac.c #define HACREG(reg) (*(unsigned long *)(hac->mmio + (reg))) reg 136 sound/soc/sh/hac.c unsigned short reg) reg 145 sound/soc/sh/hac.c HACREG(HACCSAR) = (reg << CSAR_SHIFT) | CSAR_RD; reg 155 sound/soc/sh/hac.c if (hac_get_codec_data(hac, reg, &val) != 0) reg 162 sound/soc/sh/hac.c static void hac_ac97_write(struct snd_ac97 *ac97, unsigned short reg, reg 174 sound/soc/sh/hac.c HACREG(HACCSAR) = (reg << CSAR_SHIFT) & (~CSAR_RD); reg 191 sound/soc/sh/hac.c unsigned short reg) reg 195 sound/soc/sh/hac.c return hac_read_codec_aux(hac, reg); reg 391 sound/soc/sh/rcar/dma.c #define rsnd_dmapp_addr(dmac, dma, reg) \ reg 392 sound/soc/sh/rcar/dma.c (dmac->base + 0x20 + reg + \ reg 394 sound/soc/sh/rcar/dma.c static void rsnd_dmapp_write(struct rsnd_dma *dma, u32 data, u32 reg) reg 401 sound/soc/sh/rcar/dma.c dev_dbg(dev, "w 0x%px : %08x\n", rsnd_dmapp_addr(dmac, dma, reg), data); reg 403 sound/soc/sh/rcar/dma.c iowrite32(data, rsnd_dmapp_addr(dmac, dma, reg)); reg 406 sound/soc/sh/rcar/dma.c static u32 rsnd_dmapp_read(struct rsnd_dma *dma, u32 reg) reg 412 sound/soc/sh/rcar/dma.c return ioread32(rsnd_dmapp_addr(dmac, dma, reg)); reg 415 sound/soc/sh/rcar/dma.c static void rsnd_dmapp_bset(struct rsnd_dma *dma, u32 data, u32 mask, u32 reg) reg 420 sound/soc/sh/rcar/dma.c void __iomem *addr = rsnd_dmapp_addr(dmac, dma, reg); reg 62 sound/soc/sh/rcar/gen.c struct rsnd_gen *gen, enum rsnd_reg reg) reg 64 sound/soc/sh/rcar/gen.c if (!gen->regs[reg]) { reg 67 sound/soc/sh/rcar/gen.c dev_err(dev, "unsupported register access %x\n", reg); reg 82 sound/soc/sh/rcar/gen.c u32 rsnd_mod_read(struct rsnd_mod *mod, enum rsnd_reg reg) reg 89 sound/soc/sh/rcar/gen.c if (!rsnd_is_accessible_reg(priv, gen, reg)) reg 92 sound/soc/sh/rcar/gen.c regmap_fields_read(gen->regs[reg], rsnd_mod_id_cmd(mod), &val); reg 96 sound/soc/sh/rcar/gen.c rsnd_reg_name(gen, reg), reg, val); reg 102 sound/soc/sh/rcar/gen.c enum rsnd_reg reg, u32 data) reg 108 sound/soc/sh/rcar/gen.c if (!rsnd_is_accessible_reg(priv, gen, reg)) reg 111 sound/soc/sh/rcar/gen.c regmap_fields_force_write(gen->regs[reg], rsnd_mod_id_cmd(mod), data); reg 115 sound/soc/sh/rcar/gen.c rsnd_reg_name(gen, reg), reg, data); reg 119 sound/soc/sh/rcar/gen.c enum rsnd_reg reg, u32 mask, u32 data) reg 125 sound/soc/sh/rcar/gen.c if (!rsnd_is_accessible_reg(priv, gen, reg)) reg 128 sound/soc/sh/rcar/gen.c regmap_fields_force_update_bits(gen->regs[reg], reg 133 sound/soc/sh/rcar/gen.c rsnd_reg_name(gen, reg), reg, data, mask); reg 191 sound/soc/sh/rcar/gen.c regf.reg = conf[i].reg_offset; reg 250 sound/soc/sh/rcar/rsnd.h u32 rsnd_mod_read(struct rsnd_mod *mod, enum rsnd_reg reg); reg 251 sound/soc/sh/rcar/rsnd.h void rsnd_mod_write(struct rsnd_mod *mod, enum rsnd_reg reg, u32 data); reg 252 sound/soc/sh/rcar/rsnd.h void rsnd_mod_bset(struct rsnd_mod *mod, enum rsnd_reg reg, u32 mask, u32 data); reg 584 sound/soc/sh/rcar/rsnd.h enum rsnd_reg reg); reg 94 sound/soc/sh/siu.h u32 __iomem *reg; reg 97 sound/soc/sh/siu_dai.c u32 __iomem *base = info->reg; reg 140 sound/soc/sh/siu_dai.c u32 __iomem *base = info->reg; reg 194 sound/soc/sh/siu_dai.c u32 __iomem *base = info->reg; reg 225 sound/soc/sh/siu_dai.c u32 __iomem *base = info->reg; reg 245 sound/soc/sh/siu_dai.c u32 __iomem *base = info->reg; reg 310 sound/soc/sh/siu_dai.c u32 __iomem *base = info->reg; reg 389 sound/soc/sh/siu_dai.c u32 __iomem *base = info->reg; reg 593 sound/soc/sh/siu_dai.c u32 __iomem *base = info->reg; reg 763 sound/soc/sh/siu_dai.c info->reg = devm_ioremap(&pdev->dev, res->start + REG_OFFSET, reg 765 sound/soc/sh/siu_dai.c if (!info->reg) reg 40 sound/soc/sh/siu_pcm.c u32 __iomem *base = info->reg; reg 106 sound/soc/sh/siu_pcm.c u32 __iomem *base = info->reg; reg 154 sound/soc/sh/siu_pcm.c u32 __iomem *base = info->reg; reg 264 sound/soc/sh/siu_pcm.c u32 __iomem *base = info->reg; reg 484 sound/soc/sh/siu_pcm.c u32 __iomem *base = info->reg; reg 62 sound/soc/sh/ssi.c #define SSIREG(reg) (*(unsigned long *)(ssi->mmio + (reg))) reg 387 sound/soc/soc-dapm.c template.reg = mc->reg; reg 425 sound/soc/soc-dapm.c template.reg = e->reg; reg 619 sound/soc/soc-dapm.c static int soc_dapm_read(struct snd_soc_dapm_context *dapm, int reg, reg 624 sound/soc/soc-dapm.c return snd_soc_component_read(dapm->component, reg, value); reg 628 sound/soc/soc-dapm.c int reg, unsigned int mask, unsigned int value) reg 632 sound/soc/soc-dapm.c return snd_soc_component_update_bits(dapm->component, reg, reg 637 sound/soc/soc-dapm.c int reg, unsigned int mask, unsigned int value) reg 641 sound/soc/soc-dapm.c return snd_soc_component_test_bits(dapm->component, reg, mask, value); reg 757 sound/soc/soc-dapm.c if (e->reg != SND_SOC_NOPM) { reg 758 sound/soc/soc-dapm.c soc_dapm_read(dapm, e->reg, &val); reg 787 sound/soc/soc-dapm.c unsigned int reg = mc->reg; reg 794 sound/soc/soc-dapm.c if (reg != SND_SOC_NOPM) { reg 795 sound/soc/soc-dapm.c soc_dapm_read(p->sink->dapm, reg, &val); reg 809 sound/soc/soc-dapm.c if (reg != mc->rreg) reg 1496 sound/soc/soc-dapm.c if (a->reg != b->reg) reg 1497 sound/soc/soc-dapm.c return a->reg - b->reg; reg 1578 sound/soc/soc-dapm.c int reg; reg 1583 sound/soc/soc-dapm.c reg = w->reg; reg 1587 sound/soc/soc-dapm.c WARN_ON(reg != w->reg || dapm != w->dapm); reg 1598 sound/soc/soc-dapm.c w->name, reg, value, mask); reg 1605 sound/soc/soc-dapm.c if (reg >= 0) { reg 1612 sound/soc/soc-dapm.c value, mask, reg, card->pop_time); reg 1614 sound/soc/soc-dapm.c soc_dapm_update_bits(dapm, reg, mask, value); reg 1653 sound/soc/soc-dapm.c if (sort[w->id] != cur_sort || w->reg != cur_reg || reg 1707 sound/soc/soc-dapm.c cur_reg = w->reg; reg 1761 sound/soc/soc-dapm.c ret = soc_dapm_update_bits(w->dapm, update->reg, update->mask, reg 2126 sound/soc/soc-dapm.c if (w->reg >= 0) reg 2129 sound/soc/soc-dapm.c w->reg, w->reg, w->mask << w->shift); reg 3248 sound/soc/soc-dapm.c if (w->reg >= 0) { reg 3249 sound/soc/soc-dapm.c soc_dapm_read(w->dapm, w->reg, &val); reg 3284 sound/soc/soc-dapm.c int reg = mc->reg; reg 3294 sound/soc/soc-dapm.c if (dapm_kcontrol_is_powered(kcontrol) && reg != SND_SOC_NOPM) { reg 3295 sound/soc/soc-dapm.c ret = soc_dapm_read(dapm, reg, ®_val); reg 3298 sound/soc/soc-dapm.c if (ret == 0 && reg != mc->rreg) reg 3347 sound/soc/soc-dapm.c int reg = mc->reg; reg 3380 sound/soc/soc-dapm.c if (reg != SND_SOC_NOPM) { reg 3384 sound/soc/soc-dapm.c reg_change = soc_dapm_test_bits(dapm, reg, mask << shift, val); reg 3401 sound/soc/soc-dapm.c update.reg = reg; reg 3441 sound/soc/soc-dapm.c if (e->reg != SND_SOC_NOPM && dapm_kcontrol_is_powered(kcontrol)) { reg 3442 sound/soc/soc-dapm.c int ret = soc_dapm_read(dapm, e->reg, ®_val); reg 3501 sound/soc/soc-dapm.c if (e->reg != SND_SOC_NOPM) reg 3502 sound/soc/soc-dapm.c reg_change = soc_dapm_test_bits(dapm, e->reg, mask, val); reg 3507 sound/soc/soc-dapm.c update.reg = e->reg; reg 4139 sound/soc/soc-dapm.c template.reg = SND_SOC_NOPM; reg 4201 sound/soc/soc-dapm.c template.reg = SND_SOC_NOPM; reg 24 sound/soc/soc-io.c unsigned int reg, unsigned int *val) reg 29 sound/soc/soc-io.c ret = regmap_read(component->regmap, reg, val); reg 31 sound/soc/soc-io.c *val = component->driver->read(component, reg); reg 42 sound/soc/soc-io.c unsigned int reg) reg 47 sound/soc/soc-io.c ret = snd_soc_component_read(component, reg, &val); reg 64 sound/soc/soc-io.c unsigned int reg, unsigned int val) reg 67 sound/soc/soc-io.c return regmap_write(component->regmap, reg, val); reg 69 sound/soc/soc-io.c return component->driver->write(component, reg, val); reg 76 sound/soc/soc-io.c struct snd_soc_component *component, unsigned int reg, reg 84 sound/soc/soc-io.c ret = snd_soc_component_read(component, reg, &old); reg 91 sound/soc/soc-io.c ret = snd_soc_component_write(component, reg, new); reg 110 sound/soc/soc-io.c unsigned int reg, unsigned int mask, unsigned int val) reg 116 sound/soc/soc-io.c ret = regmap_update_bits_check(component->regmap, reg, mask, reg 119 sound/soc/soc-io.c ret = snd_soc_component_update_bits_legacy(component, reg, reg 146 sound/soc/soc-io.c unsigned int reg, unsigned int mask, unsigned int val) reg 152 sound/soc/soc-io.c ret = regmap_update_bits_check_async(component->regmap, reg, reg 155 sound/soc/soc-io.c ret = snd_soc_component_update_bits_legacy(component, reg, reg 191 sound/soc/soc-io.c unsigned int reg, unsigned int mask, unsigned int value) reg 196 sound/soc/soc-io.c ret = snd_soc_component_read(component, reg, &old); reg 68 sound/soc/soc-ops.c ret = snd_soc_component_read(component, e->reg, ®_val); reg 113 sound/soc/soc-ops.c return snd_soc_component_update_bits(component, e->reg, mask, val); reg 133 sound/soc/soc-ops.c unsigned int reg, unsigned int mask, unsigned int shift, reg 139 sound/soc/soc-ops.c ret = snd_soc_component_read(component, reg, &val); reg 248 sound/soc/soc-ops.c unsigned int reg = mc->reg; reg 263 sound/soc/soc-ops.c ret = snd_soc_read_signed(component, reg, mask, shift, sign_bit, &val); reg 273 sound/soc/soc-ops.c if (reg == reg2) reg 274 sound/soc/soc-ops.c ret = snd_soc_read_signed(component, reg, mask, rshift, reg 308 sound/soc/soc-ops.c unsigned int reg = mc->reg; reg 334 sound/soc/soc-ops.c if (reg == reg2) { reg 342 sound/soc/soc-ops.c err = snd_soc_component_update_bits(component, reg, val_mask, val); reg 370 sound/soc/soc-ops.c unsigned int reg = mc->reg; reg 380 sound/soc/soc-ops.c ret = snd_soc_component_read(component, reg, &val); reg 415 sound/soc/soc-ops.c unsigned int reg = mc->reg; reg 429 sound/soc/soc-ops.c err = snd_soc_component_update_bits(component, reg, val_mask, val); reg 491 sound/soc/soc-ops.c unsigned int reg = mc->reg; reg 508 sound/soc/soc-ops.c ret = snd_soc_component_update_bits(component, reg, val_mask, val); reg 543 sound/soc/soc-ops.c unsigned int reg = mc->reg; reg 553 sound/soc/soc-ops.c ret = snd_soc_component_read(component, reg, &val); reg 923 sound/soc/soc-ops.c unsigned int reg = mc->reg; reg 930 sound/soc/soc-ops.c ret = snd_soc_component_read(component, reg, &val); reg 960 sound/soc/soc-ops.c unsigned int reg = mc->reg; reg 969 sound/soc/soc-ops.c err = snd_soc_component_update_bits(component, reg, mask, val1); reg 973 sound/soc/soc-ops.c return snd_soc_component_update_bits(component, reg, mask, val2); reg 199 sound/soc/soc-topology.c return le32_to_cpu(chan[i].reg); reg 869 sound/soc/soc-topology.c sm->reg = tplc_chan_get_reg(tplg, mc->channel, reg 1044 sound/soc/soc-topology.c se->reg = tplc_chan_get_reg(tplg, ec->channel, SNDRV_CHMAP_FL); reg 1347 sound/soc/soc-topology.c sm->reg = tplc_chan_get_reg(tplg, mc->channel, reg 1439 sound/soc/soc-topology.c se->reg = tplc_chan_get_reg(tplg, ec->channel, SNDRV_CHMAP_FL); reg 1619 sound/soc/soc-topology.c template.reg = le32_to_cpu(w->reg); reg 115 sound/soc/sof/intel/bdw.c u32 reg; reg 132 sound/soc/sof/intel/bdw.c reg = readl(sdev->bar[BDW_PCI_BAR] + PCI_PMCS) reg 134 sound/soc/sof/intel/bdw.c if (reg == 0) reg 240 sound/soc/sof/intel/hda-loader.c unsigned int reg; reg 250 sound/soc/sof/intel/hda-loader.c HDA_DSP_SRAM_REG_ROM_STATUS, reg, reg 251 sound/soc/sof/intel/hda-loader.c ((reg & HDA_DSP_ROM_STS_MASK) reg 118 sound/soc/sprd/sprd-mcdt.c static void sprd_mcdt_update(struct sprd_mcdt_dev *mcdt, u32 reg, u32 val, reg 121 sound/soc/sprd/sprd-mcdt.c u32 orig = readl_relaxed(mcdt->base + reg); reg 125 sound/soc/sprd/sprd-mcdt.c writel_relaxed(tmp, mcdt->base + reg); reg 131 sound/soc/sprd/sprd-mcdt.c u32 reg = MCDT_DAC0_WTMK + channel * 4; reg 136 sound/soc/sprd/sprd-mcdt.c sprd_mcdt_update(mcdt, reg, water_mark, reg 143 sound/soc/sprd/sprd-mcdt.c u32 reg = MCDT_ADC0_WTMK + channel * 4; reg 148 sound/soc/sprd/sprd-mcdt.c sprd_mcdt_update(mcdt, reg, water_mark, reg 185 sound/soc/sprd/sprd-mcdt.c u32 reg = MCDT_CH0_TXD + channel * 4; reg 187 sound/soc/sprd/sprd-mcdt.c writel_relaxed(val, mcdt->base + reg); reg 193 sound/soc/sprd/sprd-mcdt.c u32 reg = MCDT_CH0_RXD + channel * 4; reg 195 sound/soc/sprd/sprd-mcdt.c *val = readl_relaxed(mcdt->base + reg); reg 298 sound/soc/sprd/sprd-mcdt.c u32 reg, shift = sprd_mcdt_dma_ack_shift(channel), ack = dma_chan; reg 302 sound/soc/sprd/sprd-mcdt.c reg = MCDT_DMA_CFG2; reg 306 sound/soc/sprd/sprd-mcdt.c reg = MCDT_DMA_CFG3; reg 313 sound/soc/sprd/sprd-mcdt.c sprd_mcdt_update(mcdt, reg, ack << shift, reg 320 sound/soc/sprd/sprd-mcdt.c u32 reg, shift = sprd_mcdt_dma_ack_shift(channel), ack = dma_chan; reg 324 sound/soc/sprd/sprd-mcdt.c reg = MCDT_DMA_CFG4; reg 328 sound/soc/sprd/sprd-mcdt.c reg = MCDT_DMA_CFG5; reg 335 sound/soc/sprd/sprd-mcdt.c sprd_mcdt_update(mcdt, reg, ack << shift, reg 342 sound/soc/sprd/sprd-mcdt.c u32 reg, shift; reg 346 sound/soc/sprd/sprd-mcdt.c reg = MCDT_CH_FIFO_ST0; reg 349 sound/soc/sprd/sprd-mcdt.c reg = MCDT_CH_FIFO_ST1; reg 352 sound/soc/sprd/sprd-mcdt.c reg = MCDT_CH_FIFO_ST2; reg 385 sound/soc/sprd/sprd-mcdt.c return !!(readl_relaxed(mcdt->base + reg) & BIT(shift)); reg 402 sound/soc/sprd/sprd-mcdt.c u32 reg = MCDT_DAC0_FIFO_ADDR_ST + channel * 8; reg 403 sound/soc/sprd/sprd-mcdt.c u32 r_addr = (readl_relaxed(mcdt->base + reg) >> reg 405 sound/soc/sprd/sprd-mcdt.c u32 w_addr = readl_relaxed(mcdt->base + reg) & MCDT_CH_FIFO_ADDR_MASK; reg 415 sound/soc/sprd/sprd-mcdt.c u32 reg = MCDT_ADC0_FIFO_ADDR_ST + channel * 8; reg 416 sound/soc/sprd/sprd-mcdt.c u32 r_addr = (readl_relaxed(mcdt->base + reg) >> reg 418 sound/soc/sprd/sprd-mcdt.c u32 w_addr = readl_relaxed(mcdt->base + reg) & MCDT_CH_FIFO_ADDR_MASK; reg 456 sound/soc/sprd/sprd-mcdt.c u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type); reg 460 sound/soc/sprd/sprd-mcdt.c reg = MCDT_INT_EN0; reg 463 sound/soc/sprd/sprd-mcdt.c reg = MCDT_INT_EN1; reg 466 sound/soc/sprd/sprd-mcdt.c reg = MCDT_INT_EN2; reg 473 sound/soc/sprd/sprd-mcdt.c sprd_mcdt_update(mcdt, reg, BIT(shift), BIT(shift)); reg 475 sound/soc/sprd/sprd-mcdt.c sprd_mcdt_update(mcdt, reg, 0, BIT(shift)); reg 481 sound/soc/sprd/sprd-mcdt.c u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type); reg 485 sound/soc/sprd/sprd-mcdt.c reg = MCDT_INT_CLR0; reg 488 sound/soc/sprd/sprd-mcdt.c reg = MCDT_INT_CLR1; reg 491 sound/soc/sprd/sprd-mcdt.c reg = MCDT_INT_CLR2; reg 497 sound/soc/sprd/sprd-mcdt.c sprd_mcdt_update(mcdt, reg, BIT(shift), BIT(shift)); reg 503 sound/soc/sprd/sprd-mcdt.c u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type); reg 507 sound/soc/sprd/sprd-mcdt.c reg = MCDT_INT_MSK1; reg 510 sound/soc/sprd/sprd-mcdt.c reg = MCDT_INT_MSK2; reg 513 sound/soc/sprd/sprd-mcdt.c reg = MCDT_INT_MSK3; reg 519 sound/soc/sprd/sprd-mcdt.c return !!(readl_relaxed(mcdt->base + reg) & BIT(shift)); reg 285 sound/soc/stm/stm32_i2s.c static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg) reg 287 sound/soc/stm/stm32_i2s.c switch (reg) { reg 305 sound/soc/stm/stm32_i2s.c static bool stm32_i2s_volatile_reg(struct device *dev, unsigned int reg) reg 307 sound/soc/stm/stm32_i2s.c switch (reg) { reg 316 sound/soc/stm/stm32_i2s.c static bool stm32_i2s_writeable_reg(struct device *dev, unsigned int reg) reg 318 sound/soc/stm/stm32_i2s.c switch (reg) { reg 139 sound/soc/stm/stm32_sai_sub.c static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg) reg 141 sound/soc/stm/stm32_sai_sub.c switch (reg) { reg 158 sound/soc/stm/stm32_sai_sub.c static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg) reg 160 sound/soc/stm/stm32_sai_sub.c switch (reg) { reg 169 sound/soc/stm/stm32_sai_sub.c static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg) reg 171 sound/soc/stm/stm32_sai_sub.c switch (reg) { reg 188 sound/soc/stm/stm32_sai_sub.c unsigned int reg, unsigned int mask, reg 197 sound/soc/stm/stm32_sai_sub.c ret = regmap_update_bits(sai->regmap, reg, mask, val); reg 205 sound/soc/stm/stm32_sai_sub.c unsigned int reg, unsigned int mask, reg 214 sound/soc/stm/stm32_sai_sub.c ret = regmap_write_bits(sai->regmap, reg, mask, val); reg 222 sound/soc/stm/stm32_sai_sub.c unsigned int reg, unsigned int *val) reg 230 sound/soc/stm/stm32_sai_sub.c ret = regmap_read(sai->regmap, reg, val); reg 372 sound/soc/stm/stm32_spdifrx.c int cr, cr_mask, reg; reg 394 sound/soc/stm/stm32_spdifrx.c regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®); reg 395 sound/soc/stm/stm32_spdifrx.c regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®); reg 606 sound/soc/stm/stm32_spdifrx.c static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg) reg 608 sound/soc/stm/stm32_spdifrx.c switch (reg) { reg 625 sound/soc/stm/stm32_spdifrx.c static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg) reg 627 sound/soc/stm/stm32_spdifrx.c switch (reg) { reg 638 sound/soc/stm/stm32_spdifrx.c static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg) reg 640 sound/soc/stm/stm32_spdifrx.c switch (reg) { reg 889 sound/soc/sunxi/sun4i-i2s.c static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg) reg 891 sound/soc/sunxi/sun4i-i2s.c switch (reg) { reg 900 sound/soc/sunxi/sun4i-i2s.c static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg) reg 902 sound/soc/sunxi/sun4i-i2s.c switch (reg) { reg 912 sound/soc/sunxi/sun4i-i2s.c static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg) reg 914 sound/soc/sunxi/sun4i-i2s.c switch (reg) { reg 926 sound/soc/sunxi/sun4i-i2s.c static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg) reg 928 sound/soc/sunxi/sun4i-i2s.c switch (reg) { reg 937 sound/soc/sunxi/sun4i-i2s.c static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg) reg 939 sound/soc/sunxi/sun4i-i2s.c if (reg == SUN8I_I2S_INT_STA_REG) reg 941 sound/soc/sunxi/sun4i-i2s.c if (reg == SUN8I_I2S_FIFO_TX_REG) reg 944 sound/soc/sunxi/sun4i-i2s.c return sun4i_i2s_volatile_reg(dev, reg); reg 29 sound/soc/sunxi/sun8i-adda-pr-regmap.c static int adda_reg_read(void *context, unsigned int reg, unsigned int *val) reg 43 sound/soc/sunxi/sun8i-adda-pr-regmap.c tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT; reg 52 sound/soc/sunxi/sun8i-adda-pr-regmap.c static int adda_reg_write(void *context, unsigned int reg, unsigned int val) reg 63 sound/soc/sunxi/sun8i-adda-pr-regmap.c tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT; reg 89 sound/soc/tegra/tegra20_ac97.c unsigned short reg) reg 95 sound/soc/tegra/tegra20_ac97.c (((reg | 0x80) << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) & reg 113 sound/soc/tegra/tegra20_ac97.c unsigned short reg, unsigned short val) reg 119 sound/soc/tegra/tegra20_ac97.c ((reg << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) & reg 245 sound/soc/tegra/tegra20_ac97.c static bool tegra20_ac97_wr_rd_reg(struct device *dev, unsigned int reg) reg 247 sound/soc/tegra/tegra20_ac97.c switch (reg) { reg 262 sound/soc/tegra/tegra20_ac97.c static bool tegra20_ac97_volatile_reg(struct device *dev, unsigned int reg) reg 264 sound/soc/tegra/tegra20_ac97.c switch (reg) { reg 277 sound/soc/tegra/tegra20_ac97.c static bool tegra20_ac97_precious_reg(struct device *dev, unsigned int reg) reg 279 sound/soc/tegra/tegra20_ac97.c switch (reg) { reg 22 sound/soc/tegra/tegra20_das.c static inline void tegra20_das_write(u32 reg, u32 val) reg 24 sound/soc/tegra/tegra20_das.c regmap_write(das->regmap, reg, val); reg 27 sound/soc/tegra/tegra20_das.c static inline u32 tegra20_das_read(u32 reg) reg 31 sound/soc/tegra/tegra20_das.c regmap_read(das->regmap, reg, &val); reg 38 sound/soc/tegra/tegra20_das.c u32 reg; reg 45 sound/soc/tegra/tegra20_das.c reg = dac << TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P; reg 47 sound/soc/tegra/tegra20_das.c tegra20_das_write(addr, reg); reg 57 sound/soc/tegra/tegra20_das.c u32 reg; reg 64 sound/soc/tegra/tegra20_das.c reg = otherdap << TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P | reg 69 sound/soc/tegra/tegra20_das.c tegra20_das_write(addr, reg); reg 78 sound/soc/tegra/tegra20_das.c u32 reg; reg 85 sound/soc/tegra/tegra20_das.c reg = dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P | reg 89 sound/soc/tegra/tegra20_das.c tegra20_das_write(addr, reg); reg 99 sound/soc/tegra/tegra20_das.c static bool tegra20_das_wr_rd_reg(struct device *dev, unsigned int reg) reg 101 sound/soc/tegra/tegra20_das.c if ((reg >= TEGRA20_DAS_DAP_CTRL_SEL) && reg 102 sound/soc/tegra/tegra20_das.c (reg <= LAST_REG(DAP_CTRL_SEL))) reg 104 sound/soc/tegra/tegra20_das.c if ((reg >= TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL) && reg 105 sound/soc/tegra/tegra20_das.c (reg <= LAST_REG(DAC_INPUT_DATA_CLK_SEL))) reg 270 sound/soc/tegra/tegra20_i2s.c static bool tegra20_i2s_wr_rd_reg(struct device *dev, unsigned int reg) reg 272 sound/soc/tegra/tegra20_i2s.c switch (reg) { reg 289 sound/soc/tegra/tegra20_i2s.c static bool tegra20_i2s_volatile_reg(struct device *dev, unsigned int reg) reg 291 sound/soc/tegra/tegra20_i2s.c switch (reg) { reg 302 sound/soc/tegra/tegra20_i2s.c static bool tegra20_i2s_precious_reg(struct device *dev, unsigned int reg) reg 304 sound/soc/tegra/tegra20_i2s.c switch (reg) { reg 176 sound/soc/tegra/tegra20_spdif.c static bool tegra20_spdif_wr_rd_reg(struct device *dev, unsigned int reg) reg 178 sound/soc/tegra/tegra20_spdif.c switch (reg) { reg 205 sound/soc/tegra/tegra20_spdif.c static bool tegra20_spdif_volatile_reg(struct device *dev, unsigned int reg) reg 207 sound/soc/tegra/tegra20_spdif.c switch (reg) { reg 226 sound/soc/tegra/tegra20_spdif.c static bool tegra20_spdif_precious_reg(struct device *dev, unsigned int reg) reg 228 sound/soc/tegra/tegra20_spdif.c switch (reg) { reg 25 sound/soc/tegra/tegra30_ahub.c static inline void tegra30_apbif_write(u32 reg, u32 val) reg 27 sound/soc/tegra/tegra30_ahub.c regmap_write(ahub->regmap_apbif, reg, val); reg 30 sound/soc/tegra/tegra30_ahub.c static inline u32 tegra30_apbif_read(u32 reg) reg 34 sound/soc/tegra/tegra30_ahub.c regmap_read(ahub->regmap_apbif, reg, &val); reg 38 sound/soc/tegra/tegra30_ahub.c static inline void tegra30_audio_write(u32 reg, u32 val) reg 40 sound/soc/tegra/tegra30_ahub.c regmap_write(ahub->regmap_ahub, reg, val); reg 92 sound/soc/tegra/tegra30_ahub.c u32 reg, val; reg 109 sound/soc/tegra/tegra30_ahub.c reg = TEGRA30_AHUB_CHANNEL_CTRL + reg 111 sound/soc/tegra/tegra30_ahub.c val = tegra30_apbif_read(reg); reg 117 sound/soc/tegra/tegra30_ahub.c tegra30_apbif_write(reg, val); reg 131 sound/soc/tegra/tegra30_ahub.c reg = TEGRA30_AHUB_CIF_RX_CTRL + reg 133 sound/soc/tegra/tegra30_ahub.c ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf); reg 144 sound/soc/tegra/tegra30_ahub.c int reg, val; reg 148 sound/soc/tegra/tegra30_ahub.c reg = TEGRA30_AHUB_CHANNEL_CTRL + reg 150 sound/soc/tegra/tegra30_ahub.c val = tegra30_apbif_read(reg); reg 152 sound/soc/tegra/tegra30_ahub.c tegra30_apbif_write(reg, val); reg 163 sound/soc/tegra/tegra30_ahub.c int reg, val; reg 167 sound/soc/tegra/tegra30_ahub.c reg = TEGRA30_AHUB_CHANNEL_CTRL + reg 169 sound/soc/tegra/tegra30_ahub.c val = tegra30_apbif_read(reg); reg 171 sound/soc/tegra/tegra30_ahub.c tegra30_apbif_write(reg, val); reg 194 sound/soc/tegra/tegra30_ahub.c u32 reg, val; reg 211 sound/soc/tegra/tegra30_ahub.c reg = TEGRA30_AHUB_CHANNEL_CTRL + reg 213 sound/soc/tegra/tegra30_ahub.c val = tegra30_apbif_read(reg); reg 219 sound/soc/tegra/tegra30_ahub.c tegra30_apbif_write(reg, val); reg 233 sound/soc/tegra/tegra30_ahub.c reg = TEGRA30_AHUB_CIF_TX_CTRL + reg 235 sound/soc/tegra/tegra30_ahub.c ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf); reg 246 sound/soc/tegra/tegra30_ahub.c int reg, val; reg 250 sound/soc/tegra/tegra30_ahub.c reg = TEGRA30_AHUB_CHANNEL_CTRL + reg 252 sound/soc/tegra/tegra30_ahub.c val = tegra30_apbif_read(reg); reg 254 sound/soc/tegra/tegra30_ahub.c tegra30_apbif_write(reg, val); reg 265 sound/soc/tegra/tegra30_ahub.c int reg, val; reg 269 sound/soc/tegra/tegra30_ahub.c reg = TEGRA30_AHUB_CHANNEL_CTRL + reg 271 sound/soc/tegra/tegra30_ahub.c val = tegra30_apbif_read(reg); reg 273 sound/soc/tegra/tegra30_ahub.c tegra30_apbif_write(reg, val); reg 295 sound/soc/tegra/tegra30_ahub.c int reg; reg 299 sound/soc/tegra/tegra30_ahub.c reg = TEGRA30_AHUB_AUDIO_RX + reg 301 sound/soc/tegra/tegra30_ahub.c tegra30_audio_write(reg, 1 << txcif); reg 312 sound/soc/tegra/tegra30_ahub.c int reg; reg 316 sound/soc/tegra/tegra30_ahub.c reg = TEGRA30_AHUB_AUDIO_RX + reg 318 sound/soc/tegra/tegra30_ahub.c tegra30_audio_write(reg, 0); reg 365 sound/soc/tegra/tegra30_ahub.c #define REG_IN_ARRAY(reg, name) \ reg 366 sound/soc/tegra/tegra30_ahub.c ((reg >= TEGRA30_AHUB_##name) && \ reg 367 sound/soc/tegra/tegra30_ahub.c (reg <= LAST_REG(name) && \ reg 368 sound/soc/tegra/tegra30_ahub.c (!((reg - TEGRA30_AHUB_##name) % TEGRA30_AHUB_##name##_STRIDE)))) reg 370 sound/soc/tegra/tegra30_ahub.c static bool tegra30_ahub_apbif_wr_rd_reg(struct device *dev, unsigned int reg) reg 372 sound/soc/tegra/tegra30_ahub.c switch (reg) { reg 399 sound/soc/tegra/tegra30_ahub.c if (REG_IN_ARRAY(reg, CHANNEL_CTRL) || reg 400 sound/soc/tegra/tegra30_ahub.c REG_IN_ARRAY(reg, CHANNEL_CLEAR) || reg 401 sound/soc/tegra/tegra30_ahub.c REG_IN_ARRAY(reg, CHANNEL_STATUS) || reg 402 sound/soc/tegra/tegra30_ahub.c REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || reg 403 sound/soc/tegra/tegra30_ahub.c REG_IN_ARRAY(reg, CHANNEL_RXFIFO) || reg 404 sound/soc/tegra/tegra30_ahub.c REG_IN_ARRAY(reg, CIF_TX_CTRL) || reg 405 sound/soc/tegra/tegra30_ahub.c REG_IN_ARRAY(reg, CIF_RX_CTRL) || reg 406 sound/soc/tegra/tegra30_ahub.c REG_IN_ARRAY(reg, DAM_LIVE_STATUS)) reg 413 sound/soc/tegra/tegra30_ahub.c unsigned int reg) reg 415 sound/soc/tegra/tegra30_ahub.c switch (reg) { reg 434 sound/soc/tegra/tegra30_ahub.c if (REG_IN_ARRAY(reg, CHANNEL_CLEAR) || reg 435 sound/soc/tegra/tegra30_ahub.c REG_IN_ARRAY(reg, CHANNEL_STATUS) || reg 436 sound/soc/tegra/tegra30_ahub.c REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || reg 437 sound/soc/tegra/tegra30_ahub.c REG_IN_ARRAY(reg, CHANNEL_RXFIFO) || reg 438 sound/soc/tegra/tegra30_ahub.c REG_IN_ARRAY(reg, DAM_LIVE_STATUS)) reg 445 sound/soc/tegra/tegra30_ahub.c unsigned int reg) reg 447 sound/soc/tegra/tegra30_ahub.c if (REG_IN_ARRAY(reg, CHANNEL_TXFIFO) || reg 448 sound/soc/tegra/tegra30_ahub.c REG_IN_ARRAY(reg, CHANNEL_RXFIFO)) reg 467 sound/soc/tegra/tegra30_ahub.c static bool tegra30_ahub_ahub_wr_rd_reg(struct device *dev, unsigned int reg) reg 469 sound/soc/tegra/tegra30_ahub.c if (REG_IN_ARRAY(reg, AUDIO_RX)) reg 673 sound/soc/tegra/tegra30_ahub.c void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg, reg 701 sound/soc/tegra/tegra30_ahub.c regmap_write(regmap, reg, value); reg 705 sound/soc/tegra/tegra30_ahub.c void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg, reg 733 sound/soc/tegra/tegra30_ahub.c regmap_write(regmap, reg, value); reg 488 sound/soc/tegra/tegra30_ahub.h void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg, reg 490 sound/soc/tegra/tegra30_ahub.h void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg, reg 496 sound/soc/tegra/tegra30_ahub.h unsigned int reg, reg 129 sound/soc/tegra/tegra30_i2s.c unsigned int mask, val, reg; reg 183 sound/soc/tegra/tegra30_i2s.c reg = TEGRA30_I2S_CIF_RX_CTRL; reg 186 sound/soc/tegra/tegra30_i2s.c reg = TEGRA30_I2S_CIF_TX_CTRL; reg 189 sound/soc/tegra/tegra30_i2s.c i2s->soc_data->set_audio_cif(i2s->regmap, reg, &cif_conf); reg 297 sound/soc/tegra/tegra30_i2s.c static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg) reg 299 sound/soc/tegra/tegra30_i2s.c switch (reg) { reg 328 sound/soc/tegra/tegra30_i2s.c static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg) reg 330 sound/soc/tegra/tegra30_i2s.c switch (reg) { reg 219 sound/soc/tegra/tegra30_i2s.h unsigned int reg, reg 167 sound/soc/ti/davinci-i2s.c int reg, u32 val) reg 169 sound/soc/ti/davinci-i2s.c __raw_writel(val, dev->base + reg); reg 172 sound/soc/ti/davinci-i2s.c static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg) reg 174 sound/soc/ti/davinci-i2s.c return __raw_readl(dev->base + reg); reg 130 sound/soc/ti/davinci-mcasp.c void __iomem *reg = mcasp->base + offset; reg 131 sound/soc/ti/davinci-mcasp.c __raw_writel(__raw_readl(reg) | val, reg); reg 137 sound/soc/ti/davinci-mcasp.c void __iomem *reg = mcasp->base + offset; reg 138 sound/soc/ti/davinci-mcasp.c __raw_writel((__raw_readl(reg) & ~(val)), reg); reg 144 sound/soc/ti/davinci-mcasp.c void __iomem *reg = mcasp->base + offset; reg 145 sound/soc/ti/davinci-mcasp.c __raw_writel((__raw_readl(reg) & ~mask) | val, reg); reg 211 sound/soc/ti/davinci-mcasp.c u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; reg 213 sound/soc/ti/davinci-mcasp.c mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); reg 214 sound/soc/ti/davinci-mcasp.c mcasp_set_bits(mcasp, reg, FIFO_ENABLE); reg 251 sound/soc/ti/davinci-mcasp.c u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; reg 253 sound/soc/ti/davinci-mcasp.c mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); reg 254 sound/soc/ti/davinci-mcasp.c mcasp_set_bits(mcasp, reg, FIFO_ENABLE); reg 313 sound/soc/ti/davinci-mcasp.c u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; reg 315 sound/soc/ti/davinci-mcasp.c mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); reg 341 sound/soc/ti/davinci-mcasp.c u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; reg 343 sound/soc/ti/davinci-mcasp.c mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); reg 823 sound/soc/ti/davinci-mcasp.c u32 reg; reg 871 sound/soc/ti/davinci-mcasp.c reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; reg 875 sound/soc/ti/davinci-mcasp.c reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; reg 922 sound/soc/ti/davinci-mcasp.c mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); reg 923 sound/soc/ti/davinci-mcasp.c mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); reg 1080 sound/soc/ti/davinci-mcasp.c u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG); reg 1087 sound/soc/ti/davinci-mcasp.c if (reg & AHCLKXE) { reg 1118 sound/soc/ti/davinci-mcasp.c if (reg & AHCLKXE) reg 2384 sound/soc/ti/davinci-mcasp.c u32 reg; reg 2391 sound/soc/ti/davinci-mcasp.c reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; reg 2392 sound/soc/ti/davinci-mcasp.c context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); reg 2395 sound/soc/ti/davinci-mcasp.c reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; reg 2396 sound/soc/ti/davinci-mcasp.c context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); reg 2410 sound/soc/ti/davinci-mcasp.c u32 reg; reg 2417 sound/soc/ti/davinci-mcasp.c reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; reg 2418 sound/soc/ti/davinci-mcasp.c mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); reg 2421 sound/soc/ti/davinci-mcasp.c reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; reg 2422 sound/soc/ti/davinci-mcasp.c mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); reg 51 sound/soc/ti/omap-dmic.c static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val) reg 53 sound/soc/ti/omap-dmic.c writel_relaxed(val, dmic->io_base + reg); reg 56 sound/soc/ti/omap-dmic.c static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg) reg 58 sound/soc/ti/omap-dmic.c return readl_relaxed(dmic->io_base + reg); reg 282 sound/soc/ti/omap-mcbsp-priv.h static inline void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) reg 284 sound/soc/ti/omap-mcbsp-priv.h void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step; reg 287 sound/soc/ti/omap-mcbsp-priv.h ((u16 *)mcbsp->reg_cache)[reg] = (u16)val; reg 290 sound/soc/ti/omap-mcbsp-priv.h ((u32 *)mcbsp->reg_cache)[reg] = val; reg 295 sound/soc/ti/omap-mcbsp-priv.h static inline int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, reg 298 sound/soc/ti/omap-mcbsp-priv.h void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step; reg 302 sound/soc/ti/omap-mcbsp-priv.h ((u16 *)mcbsp->reg_cache)[reg]; reg 305 sound/soc/ti/omap-mcbsp-priv.h ((u32 *)mcbsp->reg_cache)[reg]; reg 309 sound/soc/ti/omap-mcbsp-priv.h #define MCBSP_READ(mcbsp, reg) \ reg 310 sound/soc/ti/omap-mcbsp-priv.h omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0) reg 311 sound/soc/ti/omap-mcbsp-priv.h #define MCBSP_WRITE(mcbsp, reg, val) \ reg 312 sound/soc/ti/omap-mcbsp-priv.h omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val) reg 313 sound/soc/ti/omap-mcbsp-priv.h #define MCBSP_READ_CACHE(mcbsp, reg) \ reg 314 sound/soc/ti/omap-mcbsp-priv.h omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1) reg 65 sound/soc/ti/omap-mcbsp-st.c static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) reg 67 sound/soc/ti/omap-mcbsp-st.c writel_relaxed(val, mcbsp->st_data->io_base_st + reg); reg 70 sound/soc/ti/omap-mcbsp-st.c static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg) reg 72 sound/soc/ti/omap-mcbsp-st.c return readl_relaxed(mcbsp->st_data->io_base_st + reg); reg 75 sound/soc/ti/omap-mcbsp-st.c #define MCBSP_ST_READ(mcbsp, reg) omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg) reg 76 sound/soc/ti/omap-mcbsp-st.c #define MCBSP_ST_WRITE(mcbsp, reg, val) \ reg 77 sound/soc/ti/omap-mcbsp-st.c omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val) reg 67 sound/soc/ti/omap-mcpdm.c static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val) reg 69 sound/soc/ti/omap-mcpdm.c writel_relaxed(val, mcpdm->io_base + reg); reg 72 sound/soc/ti/omap-mcpdm.c static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg) reg 74 sound/soc/ti/omap-mcpdm.c return readl_relaxed(mcpdm->io_base + reg); reg 46 sound/soc/txx9/txx9aclc-ac97.c unsigned short reg) reg 54 sound/soc/txx9/txx9aclc-ac97.c reg |= ac97->num << 7; reg 55 sound/soc/txx9/txx9aclc-ac97.c dat = (reg << ACREGACC_REG_SHIFT) | ACREGACC_READ; reg 60 sound/soc/txx9/txx9aclc-ac97.c printk(KERN_ERR "ac97 read timeout (reg %#x)\n", reg); reg 65 sound/soc/txx9/txx9aclc-ac97.c if (((dat >> ACREGACC_REG_SHIFT) & 0xff) != reg) { reg 67 sound/soc/txx9/txx9aclc-ac97.c dat, reg); reg 78 sound/soc/txx9/txx9aclc-ac97.c static void txx9aclc_ac97_write(struct snd_ac97 *ac97, unsigned short reg, reg 84 sound/soc/txx9/txx9aclc-ac97.c __raw_writel(((reg | (ac97->num << 7)) << ACREGACC_REG_SHIFT) | reg 90 sound/soc/txx9/txx9aclc-ac97.c "ac97 write timeout (reg %#x)\n", reg); reg 281 sound/soc/xilinx/xlnx_formatter_pcm.c void __iomem *reg; reg 285 sound/soc/xilinx/xlnx_formatter_pcm.c reg = adata->mmio + XLNX_MM2S_OFFSET + XLNX_AUD_STS; reg 286 sound/soc/xilinx/xlnx_formatter_pcm.c val = readl(reg); reg 288 sound/soc/xilinx/xlnx_formatter_pcm.c writel(val & AUD_STS_IOC_IRQ_MASK, reg); reg 300 sound/soc/xilinx/xlnx_formatter_pcm.c void __iomem *reg; reg 304 sound/soc/xilinx/xlnx_formatter_pcm.c reg = adata->mmio + XLNX_S2MM_OFFSET + XLNX_AUD_STS; reg 305 sound/soc/xilinx/xlnx_formatter_pcm.c val = readl(reg); reg 307 sound/soc/xilinx/xlnx_formatter_pcm.c writel(val & AUD_STS_IOC_IRQ_MASK, reg); reg 94 sound/soc/xtensa/xtfpga-i2s.c static bool xtfpga_i2s_wr_reg(struct device *dev, unsigned int reg) reg 96 sound/soc/xtensa/xtfpga-i2s.c return reg >= XTFPGA_I2S_CONFIG; reg 99 sound/soc/xtensa/xtfpga-i2s.c static bool xtfpga_i2s_rd_reg(struct device *dev, unsigned int reg) reg 101 sound/soc/xtensa/xtfpga-i2s.c return reg < XTFPGA_I2S_CHAN0_DATA; reg 104 sound/soc/xtensa/xtfpga-i2s.c static bool xtfpga_i2s_volatile_reg(struct device *dev, unsigned int reg) reg 106 sound/soc/xtensa/xtfpga-i2s.c return reg == XTFPGA_I2S_INT_STATUS; reg 83 sound/soc/zte/zx-tdm.c static inline u32 zx_tdm_readl(struct zx_tdm_info *tdm, u16 reg) reg 85 sound/soc/zte/zx-tdm.c return readl_relaxed(tdm->regbase + reg); reg 88 sound/soc/zte/zx-tdm.c static inline void zx_tdm_writel(struct zx_tdm_info *tdm, u16 reg, u32 val) reg 90 sound/soc/zte/zx-tdm.c writel_relaxed(val, tdm->regbase + reg); reg 290 sound/sparc/cs4231.c static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg, reg 298 sound/sparc/cs4231.c reg, value); reg 300 sound/sparc/cs4231.c __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL)); reg 306 sound/sparc/cs4231.c static inline void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg, reg 309 sound/sparc/cs4231.c unsigned char tmp = (chip->image[reg] & mask) | value; reg 311 sound/sparc/cs4231.c chip->image[reg] = tmp; reg 313 sound/sparc/cs4231.c snd_cs4231_dout(chip, reg, tmp); reg 316 sound/sparc/cs4231.c static void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg, reg 319 sound/sparc/cs4231.c snd_cs4231_dout(chip, reg, value); reg 320 sound/sparc/cs4231.c chip->image[reg] = value; reg 324 sound/sparc/cs4231.c static unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg) reg 330 sound/sparc/cs4231.c reg); reg 332 sound/sparc/cs4231.c __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL)); reg 384 sound/sparc/cs4231.c int reg; reg 394 sound/sparc/cs4231.c reg = __cs4231_readb(chip, CS4231U(chip, REGSEL)); reg 395 sound/sparc/cs4231.c __cs4231_writeb(chip, chip->mce_bit | (reg & 0x1f), reg 397 sound/sparc/cs4231.c if (reg == 0x80) reg 400 sound/sparc/cs4231.c if ((reg & CS4231_MCE) == 0) { reg 413 sound/sparc/cs4231.c reg = snd_cs4231_in(chip, CS4231_TEST_INIT); reg 414 sound/sparc/cs4231.c reg &= CS4231_CALIB_IN_PROGRESS; reg 415 sound/sparc/cs4231.c } while (reg && time_before(jiffies, timeout)); reg 418 sound/sparc/cs4231.c if (reg) reg 1355 sound/sparc/cs4231.c int reg = kcontrol->private_value & 0xff; reg 1362 sound/sparc/cs4231.c ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask; reg 1378 sound/sparc/cs4231.c int reg = kcontrol->private_value & 0xff; reg 1392 sound/sparc/cs4231.c val = (chip->image[reg] & ~(mask << shift)) | val; reg 1393 sound/sparc/cs4231.c change = val != chip->image[reg]; reg 1394 sound/sparc/cs4231.c snd_cs4231_out(chip, reg, val); reg 1483 sound/sparc/cs4231.c #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \ reg 1487 sound/sparc/cs4231.c .private_value = (reg) | ((shift) << 8) | ((mask) << 16) | ((invert) << 24) } reg 84 sound/spi/at73c213.c snd_at73c213_write_reg(struct snd_at73c213 *chip, u8 reg, u8 val) reg 95 sound/spi/at73c213.c chip->spi_wbuffer[0] = reg; reg 105 sound/spi/at73c213.c chip->reg_image[reg] = val; reg 405 sound/spi/at73c213.c int reg = kcontrol->private_value & 0xff; reg 413 sound/spi/at73c213.c (chip->reg_image[reg] >> shift) & mask; reg 428 sound/spi/at73c213.c int reg = kcontrol->private_value & 0xff; reg 442 sound/spi/at73c213.c val = (chip->reg_image[reg] & ~(mask << shift)) | val; reg 443 sound/spi/at73c213.c change = val != chip->reg_image[reg]; reg 444 sound/spi/at73c213.c retval = snd_at73c213_write_reg(chip, reg, val); reg 554 sound/spi/at73c213.c int reg = kcontrol->private_value & 0xff; reg 561 sound/spi/at73c213.c (chip->reg_image[reg] >> shift) & 0x01; reg 576 sound/spi/at73c213.c int reg = kcontrol->private_value & 0xff; reg 594 sound/spi/at73c213.c val |= (chip->reg_image[reg] & ~(mask << shift)); reg 595 sound/spi/at73c213.c change = val != chip->reg_image[reg]; reg 597 sound/spi/at73c213.c retval = snd_at73c213_write_reg(chip, reg, val); reg 644 sound/spi/at73c213.c #define AT73C213_MONO_SWITCH(xname, xindex, reg, shift, mask, invert) \ reg 652 sound/spi/at73c213.c .private_value = (reg | (shift << 8) | (mask << 16) | (invert << 24)) \ reg 200 sound/synth/emux/emux_effect.c srcp = (unsigned char*)&vp->reg.parm + offset; reg 241 sound/synth/emux/emux_effect.c srcp = (unsigned char*)&vp->reg.parm + offset; reg 249 sound/synth/emux/emux_effect.c vp->reg.start += effect_get_offset(chan, EMUX_FX_SAMPLE_START, reg 251 sound/synth/emux/emux_effect.c vp->reg.sample_mode); reg 253 sound/synth/emux/emux_effect.c vp->reg.loopstart += effect_get_offset(chan, EMUX_FX_LOOP_START, reg 255 sound/synth/emux/emux_effect.c vp->reg.sample_mode); reg 257 sound/synth/emux/emux_effect.c vp->reg.loopend += effect_get_offset(chan, EMUX_FX_LOOP_END, reg 259 sound/synth/emux/emux_effect.c vp->reg.sample_mode); reg 54 sound/synth/emux/emux_proc.c vp->reg.parm.moddelay, reg 55 sound/synth/emux/emux_proc.c vp->reg.parm.modatkhld, reg 56 sound/synth/emux/emux_proc.c vp->reg.parm.moddcysus, reg 57 sound/synth/emux/emux_proc.c vp->reg.parm.modrelease); reg 59 sound/synth/emux/emux_proc.c vp->reg.parm.voldelay, reg 60 sound/synth/emux/emux_proc.c vp->reg.parm.volatkhld, reg 61 sound/synth/emux/emux_proc.c vp->reg.parm.voldcysus, reg 62 sound/synth/emux/emux_proc.c vp->reg.parm.volrelease); reg 64 sound/synth/emux/emux_proc.c vp->reg.parm.lfo1delay, reg 65 sound/synth/emux/emux_proc.c vp->reg.parm.lfo2delay, reg 66 sound/synth/emux/emux_proc.c vp->reg.parm.pefe); reg 68 sound/synth/emux/emux_proc.c vp->reg.parm.fmmod, reg 69 sound/synth/emux/emux_proc.c vp->reg.parm.tremfrq, reg 70 sound/synth/emux/emux_proc.c vp->reg.parm.fm2frq2); reg 72 sound/synth/emux/emux_proc.c vp->reg.parm.cutoff, reg 73 sound/synth/emux/emux_proc.c vp->reg.parm.filterQ, reg 74 sound/synth/emux/emux_proc.c vp->reg.parm.chorus, reg 75 sound/synth/emux/emux_proc.c vp->reg.parm.reverb); reg 84 sound/synth/emux/emux_proc.c vp->reg.start, vp->reg.end, vp->reg.loopstart, vp->reg.loopend); reg 85 sound/synth/emux/emux_proc.c snd_iprintf(buf, "sample_mode=%x, rate=%x\n", vp->reg.sample_mode, vp->reg.rate_offset); reg 481 sound/synth/emux/emux_synth.c vp->reg.exclusiveClass == exclass) { reg 552 sound/synth/emux/emux_synth.c vp->reg = vp->zone->v; reg 567 sound/synth/emux/emux_synth.c parm = &vp->reg.parm; reg 645 sound/synth/emux/emux_synth.c if (vp->reg.fixpan > 0) /* 0-127 */ reg 646 sound/synth/emux/emux_synth.c pan = 255 - (int)vp->reg.fixpan * 2; reg 649 sound/synth/emux/emux_synth.c if (vp->reg.pan >= 0) /* 0-127 */ reg 650 sound/synth/emux/emux_synth.c pan += vp->reg.pan - 64; reg 754 sound/synth/emux/emux_synth.c vol = vol * vp->reg.amplitude / 127; reg 762 sound/synth/emux/emux_synth.c main_vol = chan->control[MIDI_CTL_MSB_MAIN_VOLUME] * vp->reg.amplitude / 127; reg 767 sound/synth/emux/emux_synth.c vol += vp->reg.attenuation; reg 789 sound/synth/emux/emux_synth.c && LO_BYTE(vp->reg.parm.volatkhld) < 0x7d) { reg 795 sound/synth/emux/emux_synth.c vp->acutoff = (atten * vp->reg.parm.cutoff + 0xa0) >> 7; reg 797 sound/synth/emux/emux_synth.c vp->acutoff = vp->reg.parm.cutoff; reg 817 sound/synth/emux/emux_synth.c if (vp->reg.fixkey >= 0) { reg 818 sound/synth/emux/emux_synth.c offset = (vp->reg.fixkey - vp->reg.root) * 4096 / 12; reg 820 sound/synth/emux/emux_synth.c offset = (vp->note - vp->reg.root) * 4096 / 12; reg 822 sound/synth/emux/emux_synth.c offset = (offset * vp->reg.scaleTuning) / 100; reg 823 sound/synth/emux/emux_synth.c offset += vp->reg.tune * 4096 / 1200; reg 847 sound/synth/emux/emux_synth.c offset += 0xe000 + vp->reg.rate_offset; reg 56 sound/usb/6fire/comm.c u8 reg, u8 vl, u8 vh) reg 64 sound/usb/6fire/comm.c buffer[4] = reg; reg 78 sound/usb/6fire/comm.c buffer[11] = reg; reg 86 sound/usb/6fire/comm.c buffer[4] = reg; reg 107 sound/usb/6fire/comm.c u8 reg, u8 value) reg 117 sound/usb/6fire/comm.c usb6fire_comm_init_buffer(buffer, 0x00, request, reg, value, 0x00); reg 125 sound/usb/6fire/comm.c u8 reg, u8 vl, u8 vh) reg 135 sound/usb/6fire/comm.c usb6fire_comm_init_buffer(buffer, 0x00, request, reg, vl, vh); reg 30 sound/usb/6fire/comm.h int (*write8)(struct comm_runtime *rt, u8 request, u8 reg, u8 value); reg 31 sound/usb/6fire/comm.h int (*write16)(struct comm_runtime *rt, u8 request, u8 reg, reg 33 sound/usb/6fire/control.c u8 reg; reg 568 sound/usb/6fire/control.c comm_rt->write8(comm_rt, init_data[i].type, init_data[i].reg, reg 1547 sound/usb/mixer_quirks.c u8 reg; reg 1554 sound/usb/mixer_quirks.c reg = ((pval >> 4) & 0xf0) | (pval & 0x0f); reg 1559 sound/usb/mixer_quirks.c reg, reg 1566 sound/usb/mixer_quirks.c reg = (pval & IEC958_AES0_NONAUDIO) ? 0xa0 : 0x20; reg 1567 sound/usb/mixer_quirks.c reg |= (pval >> 12) & 0x0f; reg 1572 sound/usb/mixer_quirks.c reg, reg 1633 sound/usb/mixer_quirks.c u8 reg = list->kctl->private_value; reg 1644 sound/usb/mixer_quirks.c reg, reg 1657 sound/usb/mixer_quirks.c u8 reg; reg 1660 sound/usb/mixer_quirks.c reg = ucontrol->value.integer.value[0] ? 0x28 : 0x2a; reg 1661 sound/usb/mixer_quirks.c if (reg != list->kctl->private_value) reg 1664 sound/usb/mixer_quirks.c kcontrol->private_value = reg; reg 652 sound/usb/quirks.c static int snd_usb_cm106_write_int_reg(struct usb_device *dev, int reg, u16 value) reg 658 sound/usb/quirks.c buf[3] = reg; reg 759 sound/usb/quirks.c int err = 0, reg; reg 802 sound/usb/quirks.c for (reg = 0; reg < ARRAY_SIZE(val); reg++) { reg 803 sound/usb/quirks.c err = snd_usb_cm106_write_int_reg(dev, reg, val[reg]); reg 207 sound/x86/intel_hdmi_audio.c int pipe, u32 reg) reg 209 sound/x86/intel_hdmi_audio.c return ioread32(card_ctx->mmio_start + had_config_offset(pipe) + reg); reg 213 sound/x86/intel_hdmi_audio.c int pipe, u32 reg, u32 val) reg 215 sound/x86/intel_hdmi_audio.c iowrite32(val, card_ctx->mmio_start + had_config_offset(pipe) + reg); reg 218 sound/x86/intel_hdmi_audio.c static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val) reg 223 sound/x86/intel_hdmi_audio.c *val = had_read_register_raw(ctx->card_ctx, ctx->pipe, reg); reg 226 sound/x86/intel_hdmi_audio.c static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val) reg 229 sound/x86/intel_hdmi_audio.c had_write_register_raw(ctx->card_ctx, ctx->pipe, reg, val); reg 8 tools/arch/x86/include/asm/mcsafe_test.h .macro MCSAFE_TEST_SRC reg count target reg 11 tools/arch/x86/include/asm/mcsafe_test.h .macro MCSAFE_TEST_DST reg count target reg 1165 tools/include/uapi/linux/kvm.h __u64 reg[0]; reg 689 tools/lib/traceevent/event-parse.h regex_t reg; reg 101 tools/lib/traceevent/event-plugin.c struct registered_plugin_options *reg; reg 107 tools/lib/traceevent/event-plugin.c for (reg = registered_options; reg; reg = reg->next) { reg 108 tools/lib/traceevent/event-plugin.c for (op = reg->options; op->name; op++) { reg 215 tools/lib/traceevent/event-plugin.c struct registered_plugin_options *reg; reg 217 tools/lib/traceevent/event-plugin.c reg = malloc(sizeof(*reg)); reg 218 tools/lib/traceevent/event-plugin.c if (!reg) reg 220 tools/lib/traceevent/event-plugin.c reg->next = registered_options; reg 221 tools/lib/traceevent/event-plugin.c reg->options = options; reg 222 tools/lib/traceevent/event-plugin.c registered_options = reg; reg 238 tools/lib/traceevent/event-plugin.c struct registered_plugin_options *reg; reg 242 tools/lib/traceevent/event-plugin.c reg = *last; reg 243 tools/lib/traceevent/event-plugin.c *last = reg->next; reg 244 tools/lib/traceevent/event-plugin.c free(reg); reg 211 tools/lib/traceevent/parse-filter.c regfree(&arg->str.reg); reg 267 tools/lib/traceevent/parse-filter.c char *reg; reg 277 tools/lib/traceevent/parse-filter.c ret = asprintf(®, "^%s$", event_name); reg 281 tools/lib/traceevent/parse-filter.c ret = regcomp(&ereg, reg, REG_ICASE|REG_NOSUB); reg 282 tools/lib/traceevent/parse-filter.c free(reg); reg 288 tools/lib/traceevent/parse-filter.c ret = asprintf(®, "^%s$", sys_name); reg 294 tools/lib/traceevent/parse-filter.c ret = regcomp(&sreg, reg, REG_ICASE|REG_NOSUB); reg 295 tools/lib/traceevent/parse-filter.c free(reg); reg 538 tools/lib/traceevent/parse-filter.c ret = regcomp(&op->str.reg, str, REG_ICASE|REG_NOSUB); reg 1773 tools/lib/traceevent/parse-filter.c return !regexec(&arg->str.reg, val, 0, NULL, 0); reg 1776 tools/lib/traceevent/parse-filter.c return regexec(&arg->str.reg, val, 0, NULL, 0); reg 44 tools/objtool/arch.h unsigned char reg; reg 60 tools/objtool/arch.h unsigned char reg; reg 76 tools/objtool/arch.h bool arch_callee_saved_reg(unsigned char reg); reg 42 tools/objtool/arch/x86/decode.c bool arch_callee_saved_reg(unsigned char reg) reg 44 tools/objtool/arch/x86/decode.c switch (reg) { reg 128 tools/objtool/arch/x86/decode.c op->src.reg = op_to_cfi_reg[modrm_reg][rex_r]; reg 130 tools/objtool/arch/x86/decode.c op->dest.reg = CFI_SP; reg 139 tools/objtool/arch/x86/decode.c op->src.reg = op_to_cfi_reg[op1 & 0x7][rex_b]; reg 150 tools/objtool/arch/x86/decode.c op->dest.reg = op_to_cfi_reg[op1 & 0x7][rex_b]; reg 175 tools/objtool/arch/x86/decode.c op->src.reg = CFI_SP; reg 178 tools/objtool/arch/x86/decode.c op->dest.reg = CFI_SP; reg 192 tools/objtool/arch/x86/decode.c op->src.reg = CFI_SP; reg 195 tools/objtool/arch/x86/decode.c op->dest.reg = CFI_SP; reg 204 tools/objtool/arch/x86/decode.c op->src.reg = CFI_SP; reg 206 tools/objtool/arch/x86/decode.c op->dest.reg = op_to_cfi_reg[modrm_rm][rex_b]; reg 215 tools/objtool/arch/x86/decode.c op->src.reg = op_to_cfi_reg[modrm_reg][rex_r]; reg 217 tools/objtool/arch/x86/decode.c op->dest.reg = CFI_SP; reg 229 tools/objtool/arch/x86/decode.c op->src.reg = op_to_cfi_reg[modrm_reg][rex_r]; reg 231 tools/objtool/arch/x86/decode.c op->dest.reg = CFI_BP; reg 239 tools/objtool/arch/x86/decode.c op->src.reg = op_to_cfi_reg[modrm_reg][rex_r]; reg 241 tools/objtool/arch/x86/decode.c op->dest.reg = CFI_SP; reg 253 tools/objtool/arch/x86/decode.c op->src.reg = CFI_BP; reg 256 tools/objtool/arch/x86/decode.c op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r]; reg 264 tools/objtool/arch/x86/decode.c op->src.reg = CFI_SP; reg 267 tools/objtool/arch/x86/decode.c op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r]; reg 284 tools/objtool/arch/x86/decode.c op->src.reg = CFI_SP; reg 286 tools/objtool/arch/x86/decode.c op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r]; reg 293 tools/objtool/arch/x86/decode.c op->src.reg = CFI_BP; reg 296 tools/objtool/arch/x86/decode.c op->dest.reg = CFI_SP; reg 309 tools/objtool/arch/x86/decode.c op->src.reg = CFI_R10; reg 312 tools/objtool/arch/x86/decode.c op->dest.reg = CFI_SP; reg 325 tools/objtool/arch/x86/decode.c op->src.reg = CFI_R13; reg 328 tools/objtool/arch/x86/decode.c op->dest.reg = CFI_SP; reg 1418 tools/objtool/check.c op->dest.reg == CFI_SP && op->src.reg == CFI_SP) reg 1424 tools/objtool/check.c static void save_reg(struct insn_state *state, unsigned char reg, int base, reg 1427 tools/objtool/check.c if (arch_callee_saved_reg(reg) && reg 1428 tools/objtool/check.c state->regs[reg].base == CFI_UNDEFINED) { reg 1429 tools/objtool/check.c state->regs[reg].base = base; reg 1430 tools/objtool/check.c state->regs[reg].offset = offset; reg 1434 tools/objtool/check.c static void restore_reg(struct insn_state *state, unsigned char reg) reg 1436 tools/objtool/check.c state->regs[reg].base = CFI_UNDEFINED; reg 1437 tools/objtool/check.c state->regs[reg].offset = 0; reg 1517 tools/objtool/check.c if (op->src.reg == CFI_SP && op->dest.reg == CFI_BP && reg 1523 tools/objtool/check.c cfa->base = op->dest.reg; reg 1527 tools/objtool/check.c else if (op->src.reg == CFI_SP && reg 1528 tools/objtool/check.c op->dest.reg == CFI_BP && state->drap) { reg 1536 tools/objtool/check.c else if (op->src.reg == CFI_SP && cfa->base == CFI_SP) { reg 1548 tools/objtool/check.c state->vals[op->dest.reg].base = CFI_CFA; reg 1549 tools/objtool/check.c state->vals[op->dest.reg].offset = -state->stack_size; reg 1552 tools/objtool/check.c else if (op->src.reg == CFI_BP && op->dest.reg == CFI_SP && reg 1563 tools/objtool/check.c else if (op->dest.reg == cfa->base) { reg 1567 tools/objtool/check.c state->vals[op->src.reg].base == CFI_CFA) { reg 1577 tools/objtool/check.c cfa->offset = -state->vals[op->src.reg].offset; reg 1589 tools/objtool/check.c if (op->dest.reg == CFI_SP && op->src.reg == CFI_SP) { reg 1598 tools/objtool/check.c if (op->dest.reg == CFI_SP && op->src.reg == CFI_BP) { reg 1605 tools/objtool/check.c if (op->src.reg == CFI_SP && cfa->base == CFI_SP) { reg 1608 tools/objtool/check.c state->drap_reg = op->dest.reg; reg 1620 tools/objtool/check.c state->vals[op->dest.reg].base = CFI_CFA; reg 1621 tools/objtool/check.c state->vals[op->dest.reg].offset = \ reg 1627 tools/objtool/check.c if (state->drap && op->dest.reg == CFI_SP && reg 1628 tools/objtool/check.c op->src.reg == state->drap_reg) { reg 1638 tools/objtool/check.c if (op->dest.reg == state->cfa.base) { reg 1647 tools/objtool/check.c if (op->dest.reg != CFI_SP || reg 1672 tools/objtool/check.c op->dest.reg == cfa->base) { reg 1680 tools/objtool/check.c op->dest.reg == state->drap_reg && reg 1688 tools/objtool/check.c } else if (regs[op->dest.reg].offset == -state->stack_size) { reg 1691 tools/objtool/check.c restore_reg(state, op->dest.reg); reg 1701 tools/objtool/check.c if (state->drap && op->src.reg == CFI_BP && reg 1710 tools/objtool/check.c if (state->drap && op->src.reg == CFI_BP && reg 1711 tools/objtool/check.c op->src.offset == regs[op->dest.reg].offset) { reg 1714 tools/objtool/check.c restore_reg(state, op->dest.reg); reg 1716 tools/objtool/check.c } else if (op->src.reg == cfa->base && reg 1717 tools/objtool/check.c op->src.offset == regs[op->dest.reg].offset + cfa->offset) { reg 1721 tools/objtool/check.c restore_reg(state, op->dest.reg); reg 1744 tools/objtool/check.c if (op->src.reg == cfa->base && op->src.reg == state->drap_reg) { reg 1753 tools/objtool/check.c } else if (op->src.reg == CFI_BP && cfa->base == state->drap_reg) { reg 1758 tools/objtool/check.c } else if (regs[op->src.reg].base == CFI_UNDEFINED) { reg 1761 tools/objtool/check.c save_reg(state, op->src.reg, CFI_BP, -state->stack_size); reg 1767 tools/objtool/check.c save_reg(state, op->src.reg, CFI_CFA, -state->stack_size); reg 1771 tools/objtool/check.c if (!no_fp && insn->func && op->src.reg == CFI_BP && reg 1779 tools/objtool/check.c if (op->src.reg == cfa->base && op->src.reg == state->drap_reg) { reg 1789 tools/objtool/check.c else if (regs[op->src.reg].base == CFI_UNDEFINED) { reg 1792 tools/objtool/check.c save_reg(state, op->src.reg, CFI_BP, op->dest.offset); reg 1795 tools/objtool/check.c } else if (op->dest.reg == cfa->base) { reg 1799 tools/objtool/check.c save_reg(state, op->src.reg, CFI_CFA, reg 10 tools/objtool/orc_dump.c static const char *reg_name(unsigned int reg) reg 12 tools/objtool/orc_dump.c switch (reg) { reg 50 tools/objtool/orc_dump.c static void print_reg(unsigned int reg, int offset) reg 52 tools/objtool/orc_dump.c if (reg == ORC_REG_BP_INDIRECT) reg 54 tools/objtool/orc_dump.c else if (reg == ORC_REG_SP_INDIRECT) reg 56 tools/objtool/orc_dump.c else if (reg == ORC_REG_UNDEFINED) reg 59 tools/objtool/orc_dump.c printf("%s%+d", reg_name(reg), offset); reg 10 tools/perf/arch/powerpc/include/dwarf-regs-table.h #define REG_DWARFNUM_NAME(reg, idx) [idx] = "%" #reg reg 5 tools/perf/arch/s390/include/dwarf-regs-table.h #define REG_DWARFNUM_NAME(reg, idx) [idx] = "%" #reg reg 113 tools/perf/util/bpf-prologue.c const char *reg, int target_reg) reg 115 tools/perf/util/bpf-prologue.c int offset = regs_query_register_offset(reg); reg 119 tools/perf/util/bpf-prologue.c reg); reg 248 tools/perf/util/bpf-prologue.c const char *reg = arg->value; reg 253 tools/perf/util/bpf-prologue.c i, reg); reg 256 tools/perf/util/bpf-prologue.c err = gen_ldx_reg_from_ctx(pos, BPF_REG_CTX, reg, reg 260 tools/perf/util/bpf-prologue.c reg); reg 24 tools/power/cpupower/utils/helpers/cpuid.c #define cpuid_func(reg) \ reg 25 tools/power/cpupower/utils/helpers/cpuid.c unsigned int cpuid_##reg(unsigned int op) \ reg 29 tools/power/cpupower/utils/helpers/cpuid.c return reg; \ reg 454 tools/power/x86/intel-speed-select/isst-config.c static int isst_send_mmio_command(unsigned int cpu, unsigned int reg, int write, reg 462 tools/power/x86/intel-speed-select/isst-config.c debug_printf("mmio_cmd cpu:%d reg:%d write:%d\n", cpu, reg, write); reg 470 tools/power/x86/intel-speed-select/isst-config.c io_regs.io_reg[0].reg = reg; reg 482 tools/power/x86/intel-speed-select/isst-config.c cpu, reg, write); reg 489 tools/power/x86/intel-speed-select/isst-config.c cpu, reg, write, *value); reg 231 tools/power/x86/intel-speed-select/isst.h extern int isst_read_reg(unsigned short reg, unsigned int *val); reg 232 tools/power/x86/intel-speed-select/isst.h extern int isst_write_reg(int reg, unsigned int val); reg 41 tools/testing/selftests/kvm/include/aarch64/processor.h struct kvm_one_reg reg; reg 42 tools/testing/selftests/kvm/include/aarch64/processor.h reg.id = id; reg 43 tools/testing/selftests/kvm/include/aarch64/processor.h reg.addr = (uint64_t)addr; reg 44 tools/testing/selftests/kvm/include/aarch64/processor.h vcpu_ioctl(vm, vcpuid, KVM_GET_ONE_REG, ®); reg 49 tools/testing/selftests/kvm/include/aarch64/processor.h struct kvm_one_reg reg; reg 50 tools/testing/selftests/kvm/include/aarch64/processor.h reg.id = id; reg 51 tools/testing/selftests/kvm/include/aarch64/processor.h reg.addr = (uint64_t)&val; reg 52 tools/testing/selftests/kvm/include/aarch64/processor.h vcpu_ioctl(vm, vcpuid, KVM_SET_ONE_REG, ®); reg 45 tools/testing/selftests/kvm/lib/s390x/ucall.c int reg = run->s390_sieic.ipa & 0xf; reg 47 tools/testing/selftests/kvm/lib/s390x/ucall.c memcpy(&ucall, addr_gva2hva(vm, run->s.regs.gprs[reg]), reg 36 tools/testing/selftests/kvm/s390x/sync_regs_test.c #define REG_COMPARE(reg) \ reg 37 tools/testing/selftests/kvm/s390x/sync_regs_test.c TEST_ASSERT(left->reg == right->reg, \ reg 38 tools/testing/selftests/kvm/s390x/sync_regs_test.c "Register " #reg \ reg 40 tools/testing/selftests/kvm/s390x/sync_regs_test.c left->reg, right->reg) reg 42 tools/testing/selftests/kvm/x86_64/sync_regs_test.c #define REG_COMPARE(reg) \ reg 43 tools/testing/selftests/kvm/x86_64/sync_regs_test.c TEST_ASSERT(left->reg == right->reg, \ reg 44 tools/testing/selftests/kvm/x86_64/sync_regs_test.c "Register " #reg \ reg 46 tools/testing/selftests/kvm/x86_64/sync_regs_test.c left->reg, right->reg) reg 73 tools/testing/selftests/powerpc/alignment/alignment_handler.c #define XFORM(reg, n) " " #reg " ,%"#n",%2 ;" reg 74 tools/testing/selftests/powerpc/alignment/alignment_handler.c #define DFORM(reg, n) " " #reg " ,0(%"#n") ;" reg 8 tools/testing/selftests/powerpc/include/basic_asm.h #define LOAD_REG_IMMEDIATE(reg, expr) \ reg 9 tools/testing/selftests/powerpc/include/basic_asm.h lis reg, (expr)@highest; \ reg 10 tools/testing/selftests/powerpc/include/basic_asm.h ori reg, reg, (expr)@higher; \ reg 11 tools/testing/selftests/powerpc/include/basic_asm.h rldicr reg, reg, 32, 31; \ reg 12 tools/testing/selftests/powerpc/include/basic_asm.h oris reg, reg, (expr)@high; \ reg 13 tools/testing/selftests/powerpc/include/basic_asm.h ori reg, reg, (expr)@l; reg 9 tools/testing/selftests/powerpc/include/vmx_asm.h #define PUSH_VMX(pos,reg) \ reg 10 tools/testing/selftests/powerpc/include/vmx_asm.h li reg,pos; \ reg 11 tools/testing/selftests/powerpc/include/vmx_asm.h stvx v20,reg,%r1; \ reg 12 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 13 tools/testing/selftests/powerpc/include/vmx_asm.h stvx v21,reg,%r1; \ reg 14 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 15 tools/testing/selftests/powerpc/include/vmx_asm.h stvx v22,reg,%r1; \ reg 16 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 17 tools/testing/selftests/powerpc/include/vmx_asm.h stvx v23,reg,%r1; \ reg 18 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 19 tools/testing/selftests/powerpc/include/vmx_asm.h stvx v24,reg,%r1; \ reg 20 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 21 tools/testing/selftests/powerpc/include/vmx_asm.h stvx v25,reg,%r1; \ reg 22 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 23 tools/testing/selftests/powerpc/include/vmx_asm.h stvx v26,reg,%r1; \ reg 24 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 25 tools/testing/selftests/powerpc/include/vmx_asm.h stvx v27,reg,%r1; \ reg 26 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 27 tools/testing/selftests/powerpc/include/vmx_asm.h stvx v28,reg,%r1; \ reg 28 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 29 tools/testing/selftests/powerpc/include/vmx_asm.h stvx v29,reg,%r1; \ reg 30 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 31 tools/testing/selftests/powerpc/include/vmx_asm.h stvx v30,reg,%r1; \ reg 32 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 33 tools/testing/selftests/powerpc/include/vmx_asm.h stvx v31,reg,%r1; reg 36 tools/testing/selftests/powerpc/include/vmx_asm.h #define POP_VMX(pos,reg) \ reg 37 tools/testing/selftests/powerpc/include/vmx_asm.h li reg,pos; \ reg 38 tools/testing/selftests/powerpc/include/vmx_asm.h lvx v20,reg,%r1; \ reg 39 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 40 tools/testing/selftests/powerpc/include/vmx_asm.h lvx v21,reg,%r1; \ reg 41 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 42 tools/testing/selftests/powerpc/include/vmx_asm.h lvx v22,reg,%r1; \ reg 43 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 44 tools/testing/selftests/powerpc/include/vmx_asm.h lvx v23,reg,%r1; \ reg 45 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 46 tools/testing/selftests/powerpc/include/vmx_asm.h lvx v24,reg,%r1; \ reg 47 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 48 tools/testing/selftests/powerpc/include/vmx_asm.h lvx v25,reg,%r1; \ reg 49 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 50 tools/testing/selftests/powerpc/include/vmx_asm.h lvx v26,reg,%r1; \ reg 51 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 52 tools/testing/selftests/powerpc/include/vmx_asm.h lvx v27,reg,%r1; \ reg 53 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 54 tools/testing/selftests/powerpc/include/vmx_asm.h lvx v28,reg,%r1; \ reg 55 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 56 tools/testing/selftests/powerpc/include/vmx_asm.h lvx v29,reg,%r1; \ reg 57 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 58 tools/testing/selftests/powerpc/include/vmx_asm.h lvx v30,reg,%r1; \ reg 59 tools/testing/selftests/powerpc/include/vmx_asm.h addi reg,reg,16; \ reg 60 tools/testing/selftests/powerpc/include/vmx_asm.h lvx v31,reg,%r1; reg 87 tools/testing/selftests/powerpc/pmu/ebb/trace.c int trace_log_reg(struct trace_buffer *tb, u64 reg, u64 value) reg 92 tools/testing/selftests/powerpc/pmu/ebb/trace.c e = trace_alloc_entry(tb, sizeof(reg) + sizeof(value)); reg 98 tools/testing/selftests/powerpc/pmu/ebb/trace.c *p++ = reg; reg 173 tools/testing/selftests/powerpc/pmu/ebb/trace.c static char *trace_decode_reg(int reg) reg 175 tools/testing/selftests/powerpc/pmu/ebb/trace.c switch (reg) { reg 202 tools/testing/selftests/powerpc/pmu/ebb/trace.c u64 *p, *reg, *value; reg 206 tools/testing/selftests/powerpc/pmu/ebb/trace.c reg = p++; reg 209 tools/testing/selftests/powerpc/pmu/ebb/trace.c name = trace_decode_reg(*reg); reg 213 tools/testing/selftests/powerpc/pmu/ebb/trace.c printf("register %lld = 0x%016llx\n", *reg, *value); reg 33 tools/testing/selftests/powerpc/pmu/ebb/trace.h int trace_log_reg(struct trace_buffer *tb, u64 reg, u64 value); reg 308 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define LOAD_REG_ADDR_PIC(reg, name) \ reg 310 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h 0: mflr reg; \ reg 311 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h addis reg,reg,(name - 0b)@ha; \ reg 312 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h addi reg,reg,(name - 0b)@l; reg 348 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr reg 350 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \ reg 352 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h lis reg, (expr)@__AS_ATHIGH; \ reg 354 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h ori reg, reg, (expr)@l; \ reg 355 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h rldimi reg, tmp, 32, 0 reg 357 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define LOAD_REG_ADDR(reg,name) \ reg 358 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h ld reg,name@got(r2) reg 360 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) reg 368 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr reg 370 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define LOAD_REG_IMMEDIATE_SYM(reg,expr) \ reg 371 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h lis reg,(expr)@ha; \ reg 372 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h addi reg,reg,(expr)@l; reg 374 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE_SYM(reg, name) reg 376 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha reg 511 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define MTMSR_EERI(reg) mtmsrd reg,1 reg 519 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define MTMSR_EERI(reg) mtmsr reg reg 828 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define BTB_FLUSH(reg) \ reg 829 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h lis reg,BUCSR_INIT@h; \ reg 830 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h ori reg,reg,BUCSR_INIT@l; \ reg 831 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h mtspr SPRN_BUCSR,reg; \ reg 834 tools/testing/selftests/powerpc/primitives/asm/ppc_asm.h #define BTB_FLUSH(reg) reg 76 tools/testing/selftests/powerpc/ptrace/ptrace-pkey.c unsigned long reg; reg 139 tools/testing/selftests/powerpc/ptrace/ptrace-pkey.c reg = mfspr(SPRN_AMR); reg 141 tools/testing/selftests/powerpc/ptrace/ptrace-pkey.c printf("%-30s AMR: %016lx\n", user_read, reg); reg 143 tools/testing/selftests/powerpc/ptrace/ptrace-pkey.c CHILD_FAIL_IF(reg != info->amr2, &info->child_sync); reg 155 tools/testing/selftests/powerpc/ptrace/ptrace-pkey.c reg = mfspr(SPRN_AMR); reg 157 tools/testing/selftests/powerpc/ptrace/ptrace-pkey.c printf("%-30s AMR: %016lx\n", user_read, reg); reg 159 tools/testing/selftests/powerpc/ptrace/ptrace-pkey.c CHILD_FAIL_IF(reg != info->amr2, &info->child_sync); reg 172 tools/testing/selftests/powerpc/ptrace/ptrace-pkey.c reg = mfspr(SPRN_AMR); reg 174 tools/testing/selftests/powerpc/ptrace/ptrace-pkey.c printf("%-30s AMR: %016lx\n", user_read, reg); reg 176 tools/testing/selftests/powerpc/ptrace/ptrace-pkey.c CHILD_FAIL_IF(reg != info->amr2, &info->child_sync); reg 17 tools/testing/selftests/powerpc/ptrace/ptrace-tar.c unsigned long reg[3]; reg 34 tools/testing/selftests/powerpc/ptrace/ptrace-tar.c reg[0] = mfspr(SPRN_TAR); reg 35 tools/testing/selftests/powerpc/ptrace/ptrace-tar.c reg[1] = mfspr(SPRN_PPR); reg 36 tools/testing/selftests/powerpc/ptrace/ptrace-tar.c reg[2] = mfspr(SPRN_DSCR); reg 39 tools/testing/selftests/powerpc/ptrace/ptrace-tar.c user_read, reg[0], reg[1], reg[2]); reg 45 tools/testing/selftests/powerpc/ptrace/ptrace-tar.c ret = validate_tar_registers(reg, TAR_2, PPR_2, DSCR_2); reg 53 tools/testing/selftests/powerpc/ptrace/ptrace-tar.c unsigned long reg[3]; reg 56 tools/testing/selftests/powerpc/ptrace/ptrace-tar.c FAIL_IF(show_tar_registers(child, reg)); reg 58 tools/testing/selftests/powerpc/ptrace/ptrace-tar.c ptrace_read_running, reg[0], reg[1], reg[2]); reg 60 tools/testing/selftests/powerpc/ptrace/ptrace-tar.c FAIL_IF(validate_tar_registers(reg, TAR_1, PPR_1, DSCR_1)); reg 29 tools/testing/selftests/powerpc/ptrace/ptrace-tar.h int validate_tar_registers(unsigned long *reg, unsigned long tar, reg 34 tools/testing/selftests/powerpc/ptrace/ptrace-tar.h if (reg[0] != tar) reg 37 tools/testing/selftests/powerpc/ptrace/ptrace-tar.h if (reg[1] != ppr) reg 40 tools/testing/selftests/powerpc/ptrace/ptrace-tar.h if (reg[2] != dscr) reg 143 tools/testing/selftests/powerpc/ptrace/ptrace.h unsigned long *reg; reg 146 tools/testing/selftests/powerpc/ptrace/ptrace.h reg = malloc(sizeof(unsigned long)); reg 147 tools/testing/selftests/powerpc/ptrace/ptrace.h if (!reg) { reg 151 tools/testing/selftests/powerpc/ptrace/ptrace.h iov.iov_base = (u64 *) reg; reg 160 tools/testing/selftests/powerpc/ptrace/ptrace.h out[0] = *reg; reg 168 tools/testing/selftests/powerpc/ptrace/ptrace.h out[1] = *reg; reg 176 tools/testing/selftests/powerpc/ptrace/ptrace.h out[2] = *reg; reg 178 tools/testing/selftests/powerpc/ptrace/ptrace.h free(reg); reg 181 tools/testing/selftests/powerpc/ptrace/ptrace.h free(reg); reg 189 tools/testing/selftests/powerpc/ptrace/ptrace.h unsigned long *reg; reg 192 tools/testing/selftests/powerpc/ptrace/ptrace.h reg = malloc(sizeof(unsigned long)); reg 193 tools/testing/selftests/powerpc/ptrace/ptrace.h if (!reg) { reg 198 tools/testing/selftests/powerpc/ptrace/ptrace.h iov.iov_base = (u64 *) reg; reg 201 tools/testing/selftests/powerpc/ptrace/ptrace.h *reg = tar; reg 208 tools/testing/selftests/powerpc/ptrace/ptrace.h *reg = ppr; reg 215 tools/testing/selftests/powerpc/ptrace/ptrace.h *reg = dscr; reg 222 tools/testing/selftests/powerpc/ptrace/ptrace.h free(reg); reg 225 tools/testing/selftests/powerpc/ptrace/ptrace.h free(reg); reg 232 tools/testing/selftests/powerpc/ptrace/ptrace.h unsigned long *reg; reg 235 tools/testing/selftests/powerpc/ptrace/ptrace.h reg = malloc(sizeof(unsigned long)); reg 236 tools/testing/selftests/powerpc/ptrace/ptrace.h if (!reg) { reg 241 tools/testing/selftests/powerpc/ptrace/ptrace.h iov.iov_base = (u64 *) reg; reg 250 tools/testing/selftests/powerpc/ptrace/ptrace.h out[0] = *reg; reg 258 tools/testing/selftests/powerpc/ptrace/ptrace.h out[1] = *reg; reg 266 tools/testing/selftests/powerpc/ptrace/ptrace.h out[2] = *reg; reg 268 tools/testing/selftests/powerpc/ptrace/ptrace.h free(reg); reg 272 tools/testing/selftests/powerpc/ptrace/ptrace.h free(reg); reg 280 tools/testing/selftests/powerpc/ptrace/ptrace.h unsigned long *reg; reg 283 tools/testing/selftests/powerpc/ptrace/ptrace.h reg = malloc(sizeof(unsigned long)); reg 284 tools/testing/selftests/powerpc/ptrace/ptrace.h if (!reg) { reg 289 tools/testing/selftests/powerpc/ptrace/ptrace.h iov.iov_base = (u64 *) reg; reg 292 tools/testing/selftests/powerpc/ptrace/ptrace.h *reg = tar; reg 299 tools/testing/selftests/powerpc/ptrace/ptrace.h *reg = ppr; reg 306 tools/testing/selftests/powerpc/ptrace/ptrace.h *reg = dscr; reg 313 tools/testing/selftests/powerpc/ptrace/ptrace.h free(reg); reg 316 tools/testing/selftests/powerpc/ptrace/ptrace.h free(reg); reg 266 tools/testing/selftests/rseq/param_test.c int reg; reg 276 tools/testing/selftests/rseq/param_test.c int reg; reg 364 tools/testing/selftests/rseq/param_test.c if (!opt_disable_rseq && thread_data->reg && reg 382 tools/testing/selftests/rseq/param_test.c if (!opt_disable_rseq && thread_data->reg && reg 407 tools/testing/selftests/rseq/param_test.c thread_data[i].reg = 1; reg 409 tools/testing/selftests/rseq/param_test.c thread_data[i].reg = 0; reg 443 tools/testing/selftests/rseq/param_test.c if (!opt_disable_rseq && thread_data->reg && reg 464 tools/testing/selftests/rseq/param_test.c if (!opt_disable_rseq && thread_data->reg && reg 483 tools/testing/selftests/rseq/param_test.c thread_data[i].reg = 1; reg 485 tools/testing/selftests/rseq/param_test.c thread_data[i].reg = 0; reg 1126 virt/kvm/arm/arm.c struct kvm_one_reg reg; reg 1133 virt/kvm/arm/arm.c if (copy_from_user(®, argp, sizeof(reg))) reg 1137 virt/kvm/arm/arm.c r = kvm_arm_set_reg(vcpu, ®); reg 1139 virt/kvm/arm/arm.c r = kvm_arm_get_reg(vcpu, ®); reg 1165 virt/kvm/arm/arm.c r = kvm_arm_copy_reg_indices(vcpu, user_list->reg); reg 86 virt/kvm/arm/pmu.c u64 eventsel, reg; reg 93 virt/kvm/arm/pmu.c reg = PMEVTYPER0_EL0 + select_idx; reg 94 virt/kvm/arm/pmu.c eventsel = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_EVENT; reg 107 virt/kvm/arm/pmu.c u64 counter, counter_high, reg, enabled, running; reg 111 virt/kvm/arm/pmu.c reg = PMEVCNTR0_EL0 + pmc->idx; reg 113 virt/kvm/arm/pmu.c counter = __vcpu_sys_reg(vcpu, reg); reg 114 virt/kvm/arm/pmu.c counter_high = __vcpu_sys_reg(vcpu, reg + 1); reg 118 virt/kvm/arm/pmu.c reg = (pmc->idx == ARMV8_PMU_CYCLE_IDX) reg 120 virt/kvm/arm/pmu.c counter = __vcpu_sys_reg(vcpu, reg); reg 164 virt/kvm/arm/pmu.c u64 reg; reg 166 virt/kvm/arm/pmu.c reg = (select_idx == ARMV8_PMU_CYCLE_IDX) reg 168 virt/kvm/arm/pmu.c __vcpu_sys_reg(vcpu, reg) += (s64)val - kvm_pmu_get_counter_value(vcpu, select_idx); reg 196 virt/kvm/arm/pmu.c u64 counter, reg, val; reg 205 virt/kvm/arm/pmu.c reg = PMCCNTR_EL0; reg 208 virt/kvm/arm/pmu.c reg = PMEVCNTR0_EL0 + pmc->idx; reg 212 virt/kvm/arm/pmu.c __vcpu_sys_reg(vcpu, reg) = val; reg 215 virt/kvm/arm/pmu.c __vcpu_sys_reg(vcpu, reg + 1) = upper_32_bits(counter); reg 356 virt/kvm/arm/pmu.c u64 reg = 0; reg 359 virt/kvm/arm/pmu.c reg = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); reg 360 virt/kvm/arm/pmu.c reg &= __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); reg 361 virt/kvm/arm/pmu.c reg &= __vcpu_sys_reg(vcpu, PMINTENSET_EL1); reg 362 virt/kvm/arm/pmu.c reg &= kvm_pmu_valid_counter_mask(vcpu); reg 365 virt/kvm/arm/pmu.c return reg; reg 493 virt/kvm/arm/pmu.c u64 type, reg; reg 505 virt/kvm/arm/pmu.c reg = __vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) + 1; reg 506 virt/kvm/arm/pmu.c reg = lower_32_bits(reg); reg 507 virt/kvm/arm/pmu.c __vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) = reg; reg 509 virt/kvm/arm/pmu.c if (reg) /* no overflow on the low part */ reg 514 virt/kvm/arm/pmu.c reg = __vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i + 1) + 1; reg 515 virt/kvm/arm/pmu.c reg = lower_32_bits(reg); reg 516 virt/kvm/arm/pmu.c __vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i + 1) = reg; reg 517 virt/kvm/arm/pmu.c if (!reg) /* mark overflow on the high counter */ reg 570 virt/kvm/arm/pmu.c u64 eventsel, counter, reg, data; reg 579 virt/kvm/arm/pmu.c reg = (pmc->idx == ARMV8_PMU_CYCLE_IDX) reg 581 virt/kvm/arm/pmu.c data = __vcpu_sys_reg(vcpu, reg); reg 678 virt/kvm/arm/pmu.c u64 reg, event_type = data & ARMV8_PMU_EVTYPE_MASK; reg 680 virt/kvm/arm/pmu.c reg = (select_idx == ARMV8_PMU_CYCLE_IDX) reg 683 virt/kvm/arm/pmu.c __vcpu_sys_reg(vcpu, reg) = event_type; reg 496 virt/kvm/arm/psci.c int kvm_arm_get_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 498 virt/kvm/arm/psci.c void __user *uaddr = (void __user *)(long)reg->addr; reg 501 virt/kvm/arm/psci.c switch (reg->id) { reg 506 virt/kvm/arm/psci.c val = get_kernel_wa_level(reg->id) & KVM_REG_FEATURE_LEVEL_MASK; reg 509 virt/kvm/arm/psci.c val = get_kernel_wa_level(reg->id) & KVM_REG_FEATURE_LEVEL_MASK; reg 519 virt/kvm/arm/psci.c if (copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id))) reg 525 virt/kvm/arm/psci.c int kvm_arm_set_fw_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) reg 527 virt/kvm/arm/psci.c void __user *uaddr = (void __user *)(long)reg->addr; reg 531 virt/kvm/arm/psci.c if (copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id))) reg 534 virt/kvm/arm/psci.c switch (reg->id) { reg 561 virt/kvm/arm/psci.c if (get_kernel_wa_level(reg->id) < val) reg 573 virt/kvm/arm/psci.c if (get_kernel_wa_level(reg->id) < wa_level) reg 471 virt/kvm/arm/vgic/vgic-its.c u64 reg = GITS_TYPER_PLPIS; reg 481 virt/kvm/arm/vgic/vgic-its.c reg |= GIC_ENCODE_SZ(VITS_TYPER_DEVBITS, 5) << GITS_TYPER_DEVBITS_SHIFT; reg 482 virt/kvm/arm/vgic/vgic-its.c reg |= GIC_ENCODE_SZ(VITS_TYPER_IDBITS, 5) << GITS_TYPER_IDBITS_SHIFT; reg 483 virt/kvm/arm/vgic/vgic-its.c reg |= GIC_ENCODE_SZ(abi->ite_esz, 4) << GITS_TYPER_ITT_ENTRY_SIZE_SHIFT; reg 485 virt/kvm/arm/vgic/vgic-its.c return extract_bytes(reg, addr & 7, len); reg 1443 virt/kvm/arm/vgic/vgic-its.c static u64 vgic_sanitise_its_baser(u64 reg) reg 1445 virt/kvm/arm/vgic/vgic-its.c reg = vgic_sanitise_field(reg, GITS_BASER_SHAREABILITY_MASK, reg 1448 virt/kvm/arm/vgic/vgic-its.c reg = vgic_sanitise_field(reg, GITS_BASER_INNER_CACHEABILITY_MASK, reg 1451 virt/kvm/arm/vgic/vgic-its.c reg = vgic_sanitise_field(reg, GITS_BASER_OUTER_CACHEABILITY_MASK, reg 1456 virt/kvm/arm/vgic/vgic-its.c reg = (reg & ~GITS_BASER_PAGE_SIZE_MASK) | GITS_BASER_PAGE_SIZE_64K; reg 1458 virt/kvm/arm/vgic/vgic-its.c return reg; reg 1461 virt/kvm/arm/vgic/vgic-its.c static u64 vgic_sanitise_its_cbaser(u64 reg) reg 1463 virt/kvm/arm/vgic/vgic-its.c reg = vgic_sanitise_field(reg, GITS_CBASER_SHAREABILITY_MASK, reg 1466 virt/kvm/arm/vgic/vgic-its.c reg = vgic_sanitise_field(reg, GITS_CBASER_INNER_CACHEABILITY_MASK, reg 1469 virt/kvm/arm/vgic/vgic-its.c reg = vgic_sanitise_field(reg, GITS_CBASER_OUTER_CACHEABILITY_MASK, reg 1474 virt/kvm/arm/vgic/vgic-its.c reg &= ~GENMASK_ULL(15, 12); reg 1476 virt/kvm/arm/vgic/vgic-its.c return reg; reg 1508 virt/kvm/arm/vgic/vgic-its.c #define ITS_CMD_OFFSET(reg) ((reg) & GENMASK(19, 5)) reg 1551 virt/kvm/arm/vgic/vgic-its.c u64 reg; reg 1558 virt/kvm/arm/vgic/vgic-its.c reg = update_64bit_reg(its->cwriter, addr & 7, len, val); reg 1559 virt/kvm/arm/vgic/vgic-its.c reg = ITS_CMD_OFFSET(reg); reg 1560 virt/kvm/arm/vgic/vgic-its.c if (reg >= ITS_CMD_BUFFER_SIZE(its->cbaser)) { reg 1564 virt/kvm/arm/vgic/vgic-its.c its->cwriter = reg; reg 1617 virt/kvm/arm/vgic/vgic-its.c u64 reg; reg 1621 virt/kvm/arm/vgic/vgic-its.c reg = its->baser_device_table; reg 1624 virt/kvm/arm/vgic/vgic-its.c reg = its->baser_coll_table; reg 1627 virt/kvm/arm/vgic/vgic-its.c reg = 0; reg 1631 virt/kvm/arm/vgic/vgic-its.c return extract_bytes(reg, addr & 7, len); reg 1642 virt/kvm/arm/vgic/vgic-its.c u64 reg, *regptr, clearbits = 0; reg 1664 virt/kvm/arm/vgic/vgic-its.c reg = update_64bit_reg(*regptr, addr & 7, len, val); reg 1665 virt/kvm/arm/vgic/vgic-its.c reg &= ~GITS_BASER_RO_MASK; reg 1666 virt/kvm/arm/vgic/vgic-its.c reg &= ~clearbits; reg 1668 virt/kvm/arm/vgic/vgic-its.c reg |= (entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT; reg 1669 virt/kvm/arm/vgic/vgic-its.c reg |= table_type << GITS_BASER_TYPE_SHIFT; reg 1670 virt/kvm/arm/vgic/vgic-its.c reg = vgic_sanitise_its_baser(reg); reg 1672 virt/kvm/arm/vgic/vgic-its.c *regptr = reg; reg 1674 virt/kvm/arm/vgic/vgic-its.c if (!(reg & GITS_BASER_VALID)) { reg 1693 virt/kvm/arm/vgic/vgic-its.c u32 reg = 0; reg 1697 virt/kvm/arm/vgic/vgic-its.c reg |= GITS_CTLR_QUIESCENT; reg 1699 virt/kvm/arm/vgic/vgic-its.c reg |= GITS_CTLR_ENABLE; reg 1702 virt/kvm/arm/vgic/vgic-its.c return reg; reg 1959 virt/kvm/arm/vgic/vgic-its.c u64 *reg, bool is_write) reg 2012 virt/kvm/arm/vgic/vgic-its.c len, *reg); reg 2014 virt/kvm/arm/vgic/vgic-its.c region->its_write(dev->kvm, its, addr, len, *reg); reg 2016 virt/kvm/arm/vgic/vgic-its.c *reg = region->its_read(dev->kvm, its, addr, len); reg 2716 virt/kvm/arm/vgic/vgic-its.c u64 reg; reg 2718 virt/kvm/arm/vgic/vgic-its.c if (get_user(reg, uaddr)) reg 2721 virt/kvm/arm/vgic/vgic-its.c return vgic_its_attr_regs_access(dev, attr, ®, true); reg 2746 virt/kvm/arm/vgic/vgic-its.c u64 reg; reg 2749 virt/kvm/arm/vgic/vgic-its.c ret = vgic_its_attr_regs_access(dev, attr, ®, false); reg 2752 virt/kvm/arm/vgic/vgic-its.c return put_user(reg, uaddr); reg 346 virt/kvm/arm/vgic/vgic-kvm-device.c u32 *reg, bool is_write) reg 373 virt/kvm/arm/vgic/vgic-kvm-device.c ret = vgic_v2_cpuif_uaccess(vcpu, is_write, addr, reg); reg 376 virt/kvm/arm/vgic/vgic-kvm-device.c ret = vgic_v2_dist_uaccess(vcpu, is_write, addr, reg); reg 402 virt/kvm/arm/vgic/vgic-kvm-device.c u32 reg; reg 404 virt/kvm/arm/vgic/vgic-kvm-device.c if (get_user(reg, uaddr)) reg 407 virt/kvm/arm/vgic/vgic-kvm-device.c return vgic_v2_attr_regs_access(dev, attr, ®, true); reg 427 virt/kvm/arm/vgic/vgic-kvm-device.c u32 reg = 0; reg 429 virt/kvm/arm/vgic/vgic-kvm-device.c ret = vgic_v2_attr_regs_access(dev, attr, ®, false); reg 432 virt/kvm/arm/vgic/vgic-kvm-device.c return put_user(reg, uaddr); reg 510 virt/kvm/arm/vgic/vgic-kvm-device.c u64 *reg, bool is_write) reg 540 virt/kvm/arm/vgic/vgic-kvm-device.c tmp32 = *reg; reg 544 virt/kvm/arm/vgic/vgic-kvm-device.c *reg = tmp32; reg 548 virt/kvm/arm/vgic/vgic-kvm-device.c tmp32 = *reg; reg 552 virt/kvm/arm/vgic/vgic-kvm-device.c *reg = tmp32; reg 559 virt/kvm/arm/vgic/vgic-kvm-device.c regid, reg); reg 571 virt/kvm/arm/vgic/vgic-kvm-device.c intid, reg); reg 602 virt/kvm/arm/vgic/vgic-kvm-device.c u64 reg; reg 607 virt/kvm/arm/vgic/vgic-kvm-device.c reg = tmp32; reg 608 virt/kvm/arm/vgic/vgic-kvm-device.c return vgic_v3_attr_regs_access(dev, attr, ®, true); reg 612 virt/kvm/arm/vgic/vgic-kvm-device.c u64 reg; reg 614 virt/kvm/arm/vgic/vgic-kvm-device.c if (get_user(reg, uaddr)) reg 617 virt/kvm/arm/vgic/vgic-kvm-device.c return vgic_v3_attr_regs_access(dev, attr, ®, true); reg 621 virt/kvm/arm/vgic/vgic-kvm-device.c u64 reg; reg 627 virt/kvm/arm/vgic/vgic-kvm-device.c reg = tmp32; reg 628 virt/kvm/arm/vgic/vgic-kvm-device.c return vgic_v3_attr_regs_access(dev, attr, ®, true); reg 665 virt/kvm/arm/vgic/vgic-kvm-device.c u64 reg; reg 668 virt/kvm/arm/vgic/vgic-kvm-device.c ret = vgic_v3_attr_regs_access(dev, attr, ®, false); reg 671 virt/kvm/arm/vgic/vgic-kvm-device.c tmp32 = reg; reg 676 virt/kvm/arm/vgic/vgic-kvm-device.c u64 reg; reg 678 virt/kvm/arm/vgic/vgic-kvm-device.c ret = vgic_v3_attr_regs_access(dev, attr, ®, false); reg 681 virt/kvm/arm/vgic/vgic-kvm-device.c return put_user(reg, uaddr); reg 685 virt/kvm/arm/vgic/vgic-kvm-device.c u64 reg; reg 688 virt/kvm/arm/vgic/vgic-kvm-device.c ret = vgic_v3_attr_regs_access(dev, attr, ®, false); reg 691 virt/kvm/arm/vgic/vgic-kvm-device.c tmp32 = reg; reg 27 virt/kvm/arm/vgic/vgic-mmio-v3.c u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len, reg 33 virt/kvm/arm/vgic/vgic-mmio-v3.c reg &= ~GENMASK_ULL(upper, lower); reg 36 virt/kvm/arm/vgic/vgic-mmio-v3.c return reg | ((u64)val << lower); reg 336 virt/kvm/arm/vgic/vgic-mmio-v3.c u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift, reg 339 virt/kvm/arm/vgic/vgic-mmio-v3.c u64 field = (reg & field_mask) >> field_shift; reg 342 virt/kvm/arm/vgic/vgic-mmio-v3.c return (reg & ~field_mask) | field; reg 351 virt/kvm/arm/vgic/vgic-mmio-v3.c static u64 vgic_sanitise_pendbaser(u64 reg) reg 353 virt/kvm/arm/vgic/vgic-mmio-v3.c reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK, reg 356 virt/kvm/arm/vgic/vgic-mmio-v3.c reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK, reg 359 virt/kvm/arm/vgic/vgic-mmio-v3.c reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK, reg 363 virt/kvm/arm/vgic/vgic-mmio-v3.c reg &= ~PENDBASER_RES0_MASK; reg 365 virt/kvm/arm/vgic/vgic-mmio-v3.c return reg; reg 368 virt/kvm/arm/vgic/vgic-mmio-v3.c static u64 vgic_sanitise_propbaser(u64 reg) reg 370 virt/kvm/arm/vgic/vgic-mmio-v3.c reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK, reg 373 virt/kvm/arm/vgic/vgic-mmio-v3.c reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK, reg 376 virt/kvm/arm/vgic/vgic-mmio-v3.c reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK, reg 380 virt/kvm/arm/vgic/vgic-mmio-v3.c reg &= ~PROPBASER_RES0_MASK; reg 381 virt/kvm/arm/vgic/vgic-mmio-v3.c return reg; reg 814 virt/kvm/arm/vgic/vgic-mmio-v3.c u64 reg, id; reg 817 virt/kvm/arm/vgic/vgic-mmio-v3.c return vgic_v3_has_cpu_sysregs_attr(vcpu, 0, id, ®); reg 868 virt/kvm/arm/vgic/vgic-mmio-v3.c #define SGI_AFFINITY_LEVEL(reg, level) \ reg 869 virt/kvm/arm/vgic/vgic-mmio-v3.c ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \ reg 886 virt/kvm/arm/vgic/vgic-mmio-v3.c void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1) reg 897 virt/kvm/arm/vgic/vgic-mmio-v3.c sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT; reg 898 virt/kvm/arm/vgic/vgic-mmio-v3.c broadcast = reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT); reg 899 virt/kvm/arm/vgic/vgic-mmio-v3.c target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT; reg 900 virt/kvm/arm/vgic/vgic-mmio-v3.c mpidr = SGI_AFFINITY_LEVEL(reg, 3); reg 901 virt/kvm/arm/vgic/vgic-mmio-v3.c mpidr |= SGI_AFFINITY_LEVEL(reg, 2); reg 902 virt/kvm/arm/vgic/vgic-mmio-v3.c mpidr |= SGI_AFFINITY_LEVEL(reg, 1); reg 114 virt/kvm/arm/vgic/vgic-mmio.h u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len, reg 205 virt/kvm/arm/vgic/vgic-mmio.h u64 vgic_sanitise_outer_cacheability(u64 reg); reg 206 virt/kvm/arm/vgic/vgic-mmio.h u64 vgic_sanitise_inner_cacheability(u64 reg); reg 207 virt/kvm/arm/vgic/vgic-mmio.h u64 vgic_sanitise_shareability(u64 reg); reg 208 virt/kvm/arm/vgic/vgic-mmio.h u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift, reg 31 virt/kvm/arm/vgic/vgic.h #define VGIC_AFFINITY_LEVEL(reg, level) \ reg 32 virt/kvm/arm/vgic/vgic.h ((((reg) & VGIC_AFFINITY_## level ##_MASK) \ reg 243 virt/kvm/arm/vgic/vgic.h u64 *reg);