readl_be            9 arch/powerpc/include/asm/io-defs.h DEF_PCI_AC_RET(readl_be, u32, (const PCI_IO_ADDR addr), (addr), mem, addr)
readl_be          749 arch/powerpc/include/asm/io.h #define mmio_read32be(addr)		readl_be(addr)
readl_be           36 arch/powerpc/kernel/iomap.c 	return readl_be(addr);
readl_be           56 arch/powerpc/platforms/cell/spider-pci.c SPIDER_PCI_MMIO_READ(readl_be, u32)
readl_be          164 arch/powerpc/platforms/cell/spider-pci.c 	.readl_be = spiderpci_readl_be,
readl_be         1142 drivers/crypto/amcc/crypto4xx_core.c 			val[0] = readl_be(dev->ce_base + CRYPTO4XX_PRNG_RES_0);
readl_be         1143 drivers/crypto/amcc/crypto4xx_core.c 			val[1] = readl_be(dev->ce_base + CRYPTO4XX_PRNG_RES_1);
readl_be           20 drivers/misc/ocxl/mmio.c 		*val = readl_be((char *)afu->global_mmio_ptr + offset);
readl_be          124 drivers/misc/ocxl/mmio.c 		tmp = readl_be((char *)afu->global_mmio_ptr + offset);
readl_be          186 drivers/misc/ocxl/mmio.c 		tmp = readl_be((char *)afu->global_mmio_ptr + offset);
readl_be          743 drivers/usb/host/ehci.h 		readl_be(regs) :
readl_be          787 drivers/usb/host/ehci.h 	hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
readl_be          794 drivers/usb/host/ehci.h 	(void) readl_be(ehci->ohci_hcctrl_reg);
readl_be          165 drivers/usb/host/ohci-ppc-of.c 				writel_be((readl_be(&ohci->regs->control) |
readl_be          167 drivers/usb/host/ohci-ppc-of.c 					(void) readl_be(&ohci->regs->control);
readl_be          566 drivers/usb/host/ohci.h 		readl_be (regs) :
readl_be          599 drivers/usb/host/uhci-hcd.h 		return readl_be(uhci->regs + reg);
readl_be         1191 sound/pci/mixart/mixart.c 		ref = readl_be( MIXART_MEM( chip->mgr, MIXART_PSEUDOREG_PERF_SYSTEM_LOAD_OFFSET));
readl_be         1194 sound/pci/mixart/mixart.c 			u32 mailbox   = 100 * readl_be( MIXART_MEM( chip->mgr, MIXART_PSEUDOREG_PERF_MAILBX_LOAD_OFFSET)) / ref;
readl_be         1195 sound/pci/mixart/mixart.c 			u32 streaming = 100 * readl_be( MIXART_MEM( chip->mgr, MIXART_PSEUDOREG_PERF_STREAM_LOAD_OFFSET)) / ref;
readl_be         1196 sound/pci/mixart/mixart.c 			u32 interr    = 100 * readl_be( MIXART_MEM( chip->mgr, MIXART_PSEUDOREG_PERF_INTERR_LOAD_OFFSET)) / ref;
readl_be           41 sound/pci/mixart/mixart_core.c 	tailptr = readl_be(MIXART_MEM(mgr, MSG_OUTBOUND_POST_TAIL));
readl_be           42 sound/pci/mixart/mixart_core.c 	headptr = readl_be(MIXART_MEM(mgr, MSG_OUTBOUND_POST_HEAD));
readl_be           52 sound/pci/mixart/mixart_core.c 	*msg_frame = readl_be(MIXART_MEM(mgr, tailptr));
readl_be           77 sound/pci/mixart/mixart_core.c 	size                =  readl_be(MIXART_MEM(mgr, msg_frame_address));       /* size of descriptor + response */
readl_be           78 sound/pci/mixart/mixart_core.c 	resp->message_id    =  readl_be(MIXART_MEM(mgr, msg_frame_address + 4));   /* dwMessageID */
readl_be           79 sound/pci/mixart/mixart_core.c 	resp->uid.object_id =  readl_be(MIXART_MEM(mgr, msg_frame_address + 8));   /* uidDest */
readl_be           80 sound/pci/mixart/mixart_core.c 	resp->uid.desc      =  readl_be(MIXART_MEM(mgr, msg_frame_address + 12));  /* */
readl_be          104 sound/pci/mixart/mixart_core.c 	headptr = readl_be(MIXART_MEM(mgr, MSG_OUTBOUND_FREE_HEAD));
readl_be          146 sound/pci/mixart/mixart_core.c 	tailptr = readl_be(MIXART_MEM(mgr, MSG_INBOUND_FREE_TAIL));
readl_be          147 sound/pci/mixart/mixart_core.c 	headptr = readl_be(MIXART_MEM(mgr, MSG_INBOUND_FREE_HEAD));
readl_be          158 sound/pci/mixart/mixart_core.c 	msg_frame_address = readl_be(MIXART_MEM(mgr, tailptr));
readl_be          205 sound/pci/mixart/mixart_core.c 	headptr = readl_be(MIXART_MEM(mgr, MSG_INBOUND_POST_HEAD));
readl_be           45 sound/pci/mixart/mixart_hwdep.c 		read = readl_be( MIXART_MEM( mgr, offset ));
readl_be          339 sound/pci/mixart/mixart_hwdep.c 	status_xilinx = readl_be( MIXART_MEM( mgr,MIXART_PSEUDOREG_MXLX_STATUS_OFFSET ));
readl_be          341 sound/pci/mixart/mixart_hwdep.c 	status_elf = readl_be( MIXART_MEM( mgr,MIXART_PSEUDOREG_ELF_STATUS_OFFSET ));
readl_be          343 sound/pci/mixart/mixart_hwdep.c 	status_daught = readl_be( MIXART_MEM( mgr,MIXART_PSEUDOREG_DXLX_STATUS_OFFSET ));
readl_be          457 sound/pci/mixart/mixart_hwdep.c 		mgr->board_type = (DAUGHTER_TYPE_MASK & readl_be( MIXART_MEM( mgr, MIXART_PSEUDOREG_DBRD_TYPE_OFFSET)));
readl_be          494 sound/pci/mixart/mixart_hwdep.c 		val = readl_be( MIXART_MEM( mgr, MIXART_PSEUDOREG_DXLX_BASE_ADDR_OFFSET ));
readl_be           15 sound/pci/mixart/mixart_hwdep.h #ifndef readl_be