read_csr 1201 drivers/firewire/core-cdev.c cycle_time = card->driver->read_csr(card, CSR_CYCLE_TIME); read_csr 1115 drivers/firewire/core-transaction.c *data = cpu_to_be32(card->driver->read_csr(card, reg)); read_csr 91 drivers/firewire/core.h u32 (*read_csr)(struct fw_card *card, int csr_offset); read_csr 3509 drivers/firewire/ohci.c .read_csr = ohci_read_csr, read_csr 1379 drivers/infiniband/hw/hfi1/chip.c ret = read_csr(dd, csr); read_csr 5250 drivers/infiniband/hw/hfi1/chip.c mask = read_csr(rcd->dd, CCE_INT_MASK + (8 * (is / 64))); read_csr 5701 drivers/infiniband/hw/hfi1/chip.c u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */ read_csr 5702 drivers/infiniband/hw/hfi1/chip.c u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO); read_csr 6364 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1); read_csr 6392 drivers/infiniband/hw/hfi1/chip.c (void)read_csr(dd, DCC_CFG_RESET); read_csr 6419 drivers/infiniband/hw/hfi1/chip.c u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); read_csr 6434 drivers/infiniband/hw/hfi1/chip.c u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); read_csr 6507 drivers/infiniband/hw/hfi1/chip.c dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN); read_csr 6508 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DCC_CFG_RESET); read_csr 6511 drivers/infiniband/hw/hfi1/chip.c (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */ read_csr 6740 drivers/infiniband/hw/hfi1/chip.c rcvctrl = read_csr(dd, RCV_CTRL); read_csr 6811 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, CCE_STATUS); read_csr 7524 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, SEND_CM_CTRL); read_csr 7587 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN); read_csr 7761 drivers/infiniband/hw/hfi1/chip.c info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051); read_csr 7866 drivers/infiniband/hw/hfi1/chip.c read_csr(dd, DC_DC8051_ERR_EN) & read_csr 7956 drivers/infiniband/hw/hfi1/chip.c info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE); read_csr 7975 drivers/infiniband/hw/hfi1/chip.c info = read_csr(dd, DCC_ERR_INFO_FMCONFIG); read_csr 8026 drivers/infiniband/hw/hfi1/chip.c info = read_csr(dd, DCC_ERR_INFO_PORTRCV); read_csr 8027 drivers/infiniband/hw/hfi1/chip.c hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0); read_csr 8028 drivers/infiniband/hw/hfi1/chip.c hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1); read_csr 8324 drivers/infiniband/hw/hfi1/chip.c regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) & read_csr 8356 drivers/infiniband/hw/hfi1/chip.c status = read_csr(dd, read_csr 8386 drivers/infiniband/hw/hfi1/chip.c (void)read_csr(dd, addr); read_csr 8503 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DC_DC8051_STS_CUR_STATE); read_csr 8512 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DCC_CFG_PORT_CONFIG); read_csr 8521 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DCC_CFG_PORT_CONFIG); read_csr 8538 drivers/infiniband/hw/hfi1/chip.c *data = read_csr(dd, addr); read_csr 8618 drivers/infiniband/hw/hfi1/chip.c *data = read_csr(dd, addr); read_csr 8730 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_0); read_csr 8754 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1); read_csr 8774 drivers/infiniband/hw/hfi1/chip.c *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1) read_csr 9231 drivers/infiniband/hw/hfi1/chip.c (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK)); read_csr 9448 drivers/infiniband/hw/hfi1/chip.c mask = read_csr(dd, dd->hfi1_id ? read_csr 9466 drivers/infiniband/hw/hfi1/chip.c mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK); read_csr 9492 drivers/infiniband/hw/hfi1/chip.c qsfp_mask = read_csr(dd, read_csr 10123 drivers/infiniband/hw/hfi1/chip.c len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG); read_csr 10136 drivers/infiniband/hw/hfi1/chip.c u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1); read_csr 10308 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE); read_csr 10339 drivers/infiniband/hw/hfi1/chip.c (void)read_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET); read_csr 10611 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(ppd->dd, SEND_CM_CREDIT_VL + (8 * i)); read_csr 11137 drivers/infiniband/hw/hfi1/chip.c u64 reg = read_csr(dd, csr); read_csr 11166 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); read_csr 11183 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0); read_csr 11191 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16); read_csr 11265 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); read_csr 11276 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); read_csr 11293 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, addr); read_csr 11310 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, addr); read_csr 11325 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask; read_csr 13039 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, ASIC_STS_THERM); read_csr 13071 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, CCE_INT_MASK + (8 * idx)); read_csr 13164 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, CCE_INT_MAP + (8 * m)); read_csr 13487 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, CCE_STATUS); read_csr 13497 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, CCE_STATUS); read_csr 13715 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, RCV_STATUS); read_csr 13744 drivers/infiniband/hw/hfi1/chip.c read_csr(dd, RCV_CTRL); read_csr 13751 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, RCV_STATUS); read_csr 13941 drivers/infiniband/hw/hfi1/chip.c (void)read_csr(dd, CCE_DC_CTRL); read_csr 14054 drivers/infiniband/hw/hfi1/chip.c u64 reg = read_csr(dd, RCV_QP_MAP_TABLE + (idx / 8) * 8); read_csr 14416 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, regoff); read_csr 14433 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, regoff); read_csr 14501 drivers/infiniband/hw/hfi1/chip.c val = read_csr(dd, RCV_BYPASS); read_csr 14786 drivers/infiniband/hw/hfi1/chip.c mask = read_csr(dd, CCE_INT_MASK); read_csr 14788 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, CCE_INT_MASK); read_csr 14794 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, CCE_INT_STATUS); read_csr 14800 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, CCE_INT_STATUS); read_csr 14918 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, CCE_REVISION2); read_csr 615 drivers/infiniband/hw/hfi1/chip.h u64 read_csr(const struct hfi1_devdata *dd, u32 offset); read_csr 627 drivers/infiniband/hw/hfi1/chip.h return read_csr(dd, offset0 + (0x100 * ctxt)); read_csr 662 drivers/infiniband/hw/hfi1/chip.h return read_csr(dd, offset0 + (0x1000 * ctxt)); read_csr 674 drivers/infiniband/hw/hfi1/chip.h return read_csr(dd, RCV_CONTEXTS); read_csr 679 drivers/infiniband/hw/hfi1/chip.h return read_csr(dd, SEND_CONTEXTS); read_csr 684 drivers/infiniband/hw/hfi1/chip.h return read_csr(dd, SEND_DMA_ENGINES); read_csr 689 drivers/infiniband/hw/hfi1/chip.h return read_csr(dd, SEND_PIO_MEM_SIZE); read_csr 694 drivers/infiniband/hw/hfi1/chip.h return read_csr(dd, SEND_DMA_MEM_SIZE); read_csr 699 drivers/infiniband/hw/hfi1/chip.h return read_csr(dd, RCV_ARRAY_CNT); read_csr 562 drivers/infiniband/hw/hfi1/debugfs.c scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); read_csr 619 drivers/infiniband/hw/hfi1/debugfs.c scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); read_csr 623 drivers/infiniband/hw/hfi1/debugfs.c (void)read_csr(dd, ASIC_CFG_SCRATCH); read_csr 94 drivers/infiniband/hw/hfi1/eprom.c result[i] = (u32)read_csr(dd, ASIC_EEP_DATA); read_csr 287 drivers/infiniband/hw/hfi1/firmware.c while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS) read_csr 299 drivers/infiniband/hw/hfi1/firmware.c *result = read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_RD_DATA); read_csr 372 drivers/infiniband/hw/hfi1/firmware.c while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS) read_csr 836 drivers/infiniband/hw/hfi1/firmware.c status = (read_csr(dd, MISC_CFG_FW_CTRL) read_csr 871 drivers/infiniband/hw/hfi1/firmware.c status = (read_csr(dd, MISC_CFG_FW_CTRL) read_csr 919 drivers/infiniband/hw/hfi1/firmware.c reg = read_csr(dd, MISC_ERR_STATUS); read_csr 949 drivers/infiniband/hw/hfi1/firmware.c u64 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE); read_csr 1105 drivers/infiniband/hw/hfi1/firmware.c reg = read_csr(dd, ASIC_STS_SBUS_RESULT); read_csr 1226 drivers/infiniband/hw/hfi1/firmware.c reg = read_csr(dd, ASIC_STS_SBUS_RESULT); read_csr 1230 drivers/infiniband/hw/hfi1/firmware.c u64 counts = read_csr(dd, ASIC_STS_SBUS_COUNTERS); read_csr 1243 drivers/infiniband/hw/hfi1/firmware.c reg = read_csr(dd, ASIC_STS_SBUS_RESULT); read_csr 1248 drivers/infiniband/hw/hfi1/firmware.c reg = read_csr(dd, ASIC_STS_SBUS_RESULT); read_csr 1253 drivers/infiniband/hw/hfi1/firmware.c reg = read_csr(dd, ASIC_STS_SBUS_RESULT); read_csr 1400 drivers/infiniband/hw/hfi1/firmware.c u8 user = (u8)read_csr(dd, ASIC_CFG_MUTEX); read_csr 1413 drivers/infiniband/hw/hfi1/firmware.c user = (u8)read_csr(dd, ASIC_CFG_MUTEX); read_csr 1439 drivers/infiniband/hw/hfi1/firmware.c u8 user = (u8)read_csr(dd, ASIC_CFG_MUTEX); read_csr 1501 drivers/infiniband/hw/hfi1/firmware.c scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); read_csr 1507 drivers/infiniband/hw/hfi1/firmware.c (void)read_csr(dd, ASIC_CFG_SCRATCH); read_csr 1564 drivers/infiniband/hw/hfi1/firmware.c scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); read_csr 1569 drivers/infiniband/hw/hfi1/firmware.c (void)read_csr(dd, ASIC_CFG_SCRATCH); read_csr 1595 drivers/infiniband/hw/hfi1/firmware.c scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); read_csr 1619 drivers/infiniband/hw/hfi1/firmware.c scratch0 = read_csr(dd, ASIC_CFG_SCRATCH); read_csr 1623 drivers/infiniband/hw/hfi1/firmware.c (void)read_csr(dd, ASIC_CFG_SCRATCH); read_csr 1653 drivers/infiniband/hw/hfi1/firmware.c reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS); read_csr 1659 drivers/infiniband/hw/hfi1/firmware.c reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS); read_csr 2218 drivers/infiniband/hw/hfi1/firmware.c (void)read_csr(dd, CCE_DC_CTRL); read_csr 2220 drivers/infiniband/hw/hfi1/firmware.c dd->base_guid = read_csr(dd, DC_DC8051_CFG_LOCAL_GUID); read_csr 182 drivers/infiniband/hw/hfi1/intr.c read_csr(dd, DC_DC8051_STS_REMOTE_GUID); read_csr 184 drivers/infiniband/hw/hfi1/intr.c read_csr(dd, DC_DC8051_STS_REMOTE_NODE_TYPE) & read_csr 187 drivers/infiniband/hw/hfi1/intr.c read_csr(dd, DC_DC8051_STS_REMOTE_PORT_NO) & read_csr 190 drivers/infiniband/hw/hfi1/intr.c read_csr(dd, DC_DC8051_STS_REMOTE_FM_SECURITY) & read_csr 1818 drivers/infiniband/hw/hfi1/mad.c *val++ = read_csr(dd, SEND_SC2VLT0); read_csr 1819 drivers/infiniband/hw/hfi1/mad.c *val++ = read_csr(dd, SEND_SC2VLT1); read_csr 1820 drivers/infiniband/hw/hfi1/mad.c *val++ = read_csr(dd, SEND_SC2VLT2); read_csr 1821 drivers/infiniband/hw/hfi1/mad.c *val++ = read_csr(dd, SEND_SC2VLT3); read_csr 3429 drivers/infiniband/hw/hfi1/mad.c reg = read_csr(dd, RCV_ERR_INFO); read_csr 900 drivers/infiniband/hw/hfi1/pcie.c read_csr(dd, ASIC_PCIE_SD_HOST_CMD); read_csr 930 drivers/infiniband/hw/hfi1/pcie.c pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL); read_csr 1068 drivers/infiniband/hw/hfi1/pcie.c therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); read_csr 1297 drivers/infiniband/hw/hfi1/pcie.c (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ read_csr 1299 drivers/infiniband/hw/hfi1/pcie.c fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); read_csr 1363 drivers/infiniband/hw/hfi1/pcie.c reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); read_csr 68 drivers/infiniband/hw/hfi1/pio.c sendctrl = read_csr(dd, SEND_CTRL); read_csr 85 drivers/infiniband/hw/hfi1/pio.c reg = read_csr(dd, SEND_CTRL); read_csr 125 drivers/infiniband/hw/hfi1/pio.c (void)read_csr(dd, SEND_CTRL); /* flush write */ read_csr 1018 drivers/infiniband/hw/hfi1/pio.c reg = read_csr(dd, sc->hw_context * 8 + read_csr 1241 drivers/infiniband/hw/hfi1/pio.c reg = read_csr(dd, SEND_PIO_INIT_CTXT); read_csr 61 drivers/infiniband/hw/hfi1/platform.c temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH); read_csr 80 drivers/infiniband/hw/hfi1/platform.c temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH + (8 * i)); read_csr 90 drivers/infiniband/hw/hfi1/platform.c temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH); read_csr 106 drivers/infiniband/hw/hfi1/platform.c temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH_1); read_csr 136 drivers/infiniband/hw/hfi1/platform.c temp_scratch = read_csr(dd, dd->hfi1_id ? ASIC_CFG_SCRATCH_3 : read_csr 74 drivers/infiniband/hw/hfi1/qsfp.c reg = read_csr(dd, target_oe); read_csr 87 drivers/infiniband/hw/hfi1/qsfp.c (void)read_csr(dd, target_oe); read_csr 98 drivers/infiniband/hw/hfi1/qsfp.c reg = read_csr(dd, target_oe); read_csr 111 drivers/infiniband/hw/hfi1/qsfp.c (void)read_csr(dd, target_oe); read_csr 124 drivers/infiniband/hw/hfi1/qsfp.c reg = read_csr(bus->controlling_dd, target_in); read_csr 138 drivers/infiniband/hw/hfi1/qsfp.c reg = read_csr(bus->controlling_dd, target_in); read_csr 688 drivers/infiniband/hw/hfi1/qsfp.c reg = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_IN : ASIC_QSFP1_IN); read_csr 316 drivers/infiniband/hw/hfi1/sdma.c reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS); read_csr 2086 drivers/infiniband/hw/hfi1/sdma.c csr = read_csr(sde->dd, reg); \ read_csr 2097 drivers/infiniband/hw/hfi1/sdma.c csr = read_csr(sde->dd, reg + (8 * i)); \ read_csr 246 drivers/net/ethernet/amd/pcnet32.c u16 (*read_csr) (unsigned long, int); read_csr 386 drivers/net/ethernet/amd/pcnet32.c .read_csr = pcnet32_wio_read_csr, read_csr 441 drivers/net/ethernet/amd/pcnet32.c .read_csr = pcnet32_dwio_read_csr, read_csr 466 drivers/net/ethernet/amd/pcnet32.c val = lp->a->read_csr(ioaddr, CSR3); read_csr 700 drivers/net/ethernet/amd/pcnet32.c csr5 = a->read_csr(ioaddr, CSR5); read_csr 705 drivers/net/ethernet/amd/pcnet32.c while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) { read_csr 724 drivers/net/ethernet/amd/pcnet32.c int csr5 = lp->a->read_csr(ioaddr, CSR5); read_csr 784 drivers/net/ethernet/amd/pcnet32.c csr15 = lp->a->read_csr(ioaddr, CSR15) & ~0x0180; read_csr 1061 drivers/net/ethernet/amd/pcnet32.c x = a->read_csr(ioaddr, CSR15) & 0xfffc; read_csr 1119 drivers/net/ethernet/amd/pcnet32.c x = a->read_csr(ioaddr, CSR15); read_csr 1419 drivers/net/ethernet/amd/pcnet32.c val = lp->a->read_csr(ioaddr, CSR3); read_csr 1453 drivers/net/ethernet/amd/pcnet32.c csr0 = a->read_csr(ioaddr, CSR0); read_csr 1463 drivers/net/ethernet/amd/pcnet32.c *buff++ = a->read_csr(ioaddr, i); read_csr 1465 drivers/net/ethernet/amd/pcnet32.c *buff++ = a->read_csr(ioaddr, 112); read_csr 1466 drivers/net/ethernet/amd/pcnet32.c *buff++ = a->read_csr(ioaddr, 114); read_csr 1632 drivers/net/ethernet/amd/pcnet32.c a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16); read_csr 1724 drivers/net/ethernet/amd/pcnet32.c (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00); read_csr 1774 drivers/net/ethernet/amd/pcnet32.c val = a->read_csr(ioaddr, i + 12) & 0x0ffff; read_csr 1804 drivers/net/ethernet/amd/pcnet32.c i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */ read_csr 2155 drivers/net/ethernet/amd/pcnet32.c val = lp->a->read_csr(ioaddr, 124) & ~0x10; read_csr 2260 drivers/net/ethernet/amd/pcnet32.c val = lp->a->read_csr(ioaddr, CSR3); read_csr 2294 drivers/net/ethernet/amd/pcnet32.c if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON) read_csr 2306 drivers/net/ethernet/amd/pcnet32.c lp->a->read_csr(ioaddr, CSR0)); read_csr 2437 drivers/net/ethernet/amd/pcnet32.c if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP) read_csr 2452 drivers/net/ethernet/amd/pcnet32.c if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON) read_csr 2467 drivers/net/ethernet/amd/pcnet32.c dev->name, lp->a->read_csr(ioaddr, CSR0)); read_csr 2511 drivers/net/ethernet/amd/pcnet32.c __func__, lp->a->read_csr(ioaddr, CSR0)); read_csr 2572 drivers/net/ethernet/amd/pcnet32.c csr0 = lp->a->read_csr(ioaddr, CSR0); read_csr 2581 drivers/net/ethernet/amd/pcnet32.c csr0, lp->a->read_csr(ioaddr, CSR0)); read_csr 2608 drivers/net/ethernet/amd/pcnet32.c val = lp->a->read_csr(ioaddr, CSR3); read_csr 2615 drivers/net/ethernet/amd/pcnet32.c csr0 = lp->a->read_csr(ioaddr, CSR0); read_csr 2620 drivers/net/ethernet/amd/pcnet32.c lp->a->read_csr(ioaddr, CSR0)); read_csr 2640 drivers/net/ethernet/amd/pcnet32.c dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112); read_csr 2644 drivers/net/ethernet/amd/pcnet32.c lp->a->read_csr(ioaddr, CSR0)); read_csr 2676 drivers/net/ethernet/amd/pcnet32.c dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112); read_csr 2729 drivers/net/ethernet/amd/pcnet32.c csr15 = lp->a->read_csr(ioaddr, CSR15);