read_aux_reg       80 arch/arc/include/asm/irqflags-arcv2.h 	unsigned int irqact = read_aux_reg(AUX_IRQ_ACT);
read_aux_reg      357 arch/arc/include/asm/pgtable.h 	pgd_t *pgd_base = (pgd_t *) read_aux_reg(ARC_REG_SCRATCH_DATA0);  \
read_aux_reg       93 arch/arc/kernel/intc-arcv2.c 	tmp = read_aux_reg(ARC_REG_STATUS32);
read_aux_reg       47 arch/arc/kernel/intc-compact.c 		ienb = read_aux_reg(AUX_IENABLE);
read_aux_reg       68 arch/arc/kernel/intc-compact.c 	ienb = read_aux_reg(AUX_IENABLE);
read_aux_reg       77 arch/arc/kernel/intc-compact.c 	ienb = read_aux_reg(AUX_IENABLE);
read_aux_reg       44 arch/arc/kernel/mcip.c 	gfrc_halt_mask = read_aux_reg(ARC_REG_MCIP_READBACK);
read_aux_reg       64 arch/arc/kernel/mcip.c 	mcip_mask = read_aux_reg(ARC_REG_MCIP_READBACK);
read_aux_reg      117 arch/arc/kernel/mcip.c 	ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK);
read_aux_reg      139 arch/arc/kernel/mcip.c 	cpu = read_aux_reg(ARC_REG_MCIP_READBACK);	/* 1,2,4,8... */
read_aux_reg      110 arch/arc/kernel/perf_event.c 	tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
read_aux_reg      112 arch/arc/kernel/perf_event.c 	result = (u64) (read_aux_reg(ARC_REG_PCT_SNAPH)) << 32;
read_aux_reg      113 arch/arc/kernel/perf_event.c 	result |= read_aux_reg(ARC_REG_PCT_SNAPL);
read_aux_reg      231 arch/arc/kernel/perf_event.c 	tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
read_aux_reg      239 arch/arc/kernel/perf_event.c 	tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
read_aux_reg      307 arch/arc/kernel/perf_event.c 			      read_aux_reg(ARC_REG_PCT_INT_CTRL) | BIT(idx));
read_aux_reg      327 arch/arc/kernel/perf_event.c 			      read_aux_reg(ARC_REG_PCT_INT_CTRL) & ~BIT(idx));
read_aux_reg      410 arch/arc/kernel/perf_event.c 	active_ints = read_aux_reg(ARC_REG_PCT_INT_ACT);
read_aux_reg      431 arch/arc/kernel/perf_event.c 			read_aux_reg(ARC_REG_PCT_INT_CTRL) | BIT(idx));
read_aux_reg      617 arch/arc/kernel/perf_event.c 		cc_name.indiv.word0 = le32_to_cpu(read_aux_reg(ARC_REG_CC_NAME0));
read_aux_reg      618 arch/arc/kernel/perf_event.c 		cc_name.indiv.word1 = le32_to_cpu(read_aux_reg(ARC_REG_CC_NAME1));
read_aux_reg       83 arch/arc/kernel/setup.c 			base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD);
read_aux_reg       97 arch/arc/kernel/setup.c 			region = read_aux_reg(ARC_REG_AUX_ICCM);
read_aux_reg      107 arch/arc/kernel/setup.c 			region = read_aux_reg(ARC_REG_AUX_DCCM);
read_aux_reg      185 arch/arc/kernel/setup.c 	cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
read_aux_reg      328 arch/arc/kernel/setup.c 				ctl = read_aux_reg(ARC_REG_LPB_CTRL);
read_aux_reg      491 arch/arc/mm/cache.c 		write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH);
read_aux_reg      500 arch/arc/mm/cache.c 	unsigned int val = read_aux_reg(ctl);
read_aux_reg      528 arch/arc/mm/cache.c 		while ((reg = read_aux_reg(ctl)) & DC_CTRL_FLUSH_STATUS)
read_aux_reg      564 arch/arc/mm/cache.c 	write_aux_reg(r, read_aux_reg(r) | DC_CTRL_DIS);
read_aux_reg      571 arch/arc/mm/cache.c 	write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS);
read_aux_reg      612 arch/arc/mm/cache.c 	read_aux_reg(ARC_REG_IC_CTRL);	/* blocks */
read_aux_reg      689 arch/arc/mm/cache.c 	ctrl = read_aux_reg(ARC_REG_SLC_CTRL);
read_aux_reg      721 arch/arc/mm/cache.c 	read_aux_reg(ARC_REG_SLC_CTRL);
read_aux_reg      723 arch/arc/mm/cache.c 	while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);
read_aux_reg      748 arch/arc/mm/cache.c 	ctrl = read_aux_reg(ARC_REG_SLC_CTRL);
read_aux_reg      771 arch/arc/mm/cache.c 	read_aux_reg(ARC_REG_SLC_CTRL);
read_aux_reg      773 arch/arc/mm/cache.c 	while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);
read_aux_reg      785 arch/arc/mm/cache.c 	ctrl = read_aux_reg(r);
read_aux_reg      800 arch/arc/mm/cache.c 	read_aux_reg(r);
read_aux_reg      803 arch/arc/mm/cache.c 	while (read_aux_reg(r) & SLC_CTRL_BUSY);
read_aux_reg      811 arch/arc/mm/cache.c 	write_aux_reg(r, read_aux_reg(r) | SLC_CTRL_DIS);
read_aux_reg      818 arch/arc/mm/cache.c 	write_aux_reg(r, read_aux_reg(r) & ~SLC_CTRL_DIS);
read_aux_reg     1166 arch/arc/mm/cache.c 	if (read_aux_reg(ARC_REG_IO_COH_ENABLE) & ARC_IO_COH_ENABLE_BIT)
read_aux_reg     1176 arch/arc/mm/cache.c 	if (read_aux_reg(ARC_REG_SLC_BCR))
read_aux_reg      130 arch/arc/mm/tlb.c 	idx = read_aux_reg(ARC_REG_TLBINDEX);
read_aux_reg      178 arch/arc/mm/tlb.c 	idx = read_aux_reg(ARC_REG_TLBINDEX);
read_aux_reg      562 arch/arc/mm/tlb.c 	asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff;
read_aux_reg      759 arch/arc/mm/tlb.c 	tmp = read_aux_reg(ARC_REG_MMU_BCR);
read_aux_reg      930 arch/arc/mm/tlb.c 			pd0[way] = read_aux_reg(ARC_REG_TLBPD0);
read_aux_reg      993 arch/arc/mm/tlb.c 	mmu_asid = read_aux_reg(ARC_REG_PID) & 0xff;
read_aux_reg      313 arch/arc/plat-axs10x/axs10x.c 	unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
read_aux_reg       16 arch/arc/plat-eznps/ctop.c 	prev_task_dp->eflags = read_aux_reg(CTOP_AUX_EFLAGS);
read_aux_reg       19 arch/arc/plat-eznps/ctop.c 	prev_task_dp->gpa1 = read_aux_reg(CTOP_AUX_GPA1);
read_aux_reg       43 arch/arc/plat-eznps/mtm.c 	udmc.value = read_aux_reg(CTOP_AUX_UDMC);
read_aux_reg       62 arch/arc/plat-eznps/smp.c 	hw_comply.value = read_aux_reg(CTOP_AUX_HW_COMPLY);
read_aux_reg       80 drivers/clocksource/arc_timer.c 	l = read_aux_reg(ARC_REG_MCIP_READBACK);
read_aux_reg       83 drivers/clocksource/arc_timer.c 	h = read_aux_reg(ARC_REG_MCIP_READBACK);
read_aux_reg      140 drivers/clocksource/arc_timer.c 		l = read_aux_reg(AUX_RTC_LOW);
read_aux_reg      141 drivers/clocksource/arc_timer.c 		h = read_aux_reg(AUX_RTC_HIGH);
read_aux_reg      142 drivers/clocksource/arc_timer.c 		status = read_aux_reg(AUX_RTC_CTRL);
read_aux_reg      198 drivers/clocksource/arc_timer.c 	return (u64) read_aux_reg(ARC_REG_TIMER1_CNT);
read_aux_reg      144 drivers/clocksource/timer-nps.c 	enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI);
read_aux_reg      147 drivers/clocksource/timer-nps.c 	thread = read_aux_reg(CTOP_AUX_THREAD_ID);
read_aux_reg      169 drivers/clocksource/timer-nps.c 	thread = read_aux_reg(CTOP_AUX_THREAD_ID);
read_aux_reg      170 drivers/clocksource/timer-nps.c 	enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI);
read_aux_reg       61 drivers/irqchip/irq-eznps.c 	ienb = read_aux_reg(AUX_IENABLE);
read_aux_reg       71 drivers/irqchip/irq-eznps.c 	ienb = read_aux_reg(AUX_IENABLE);
read_aux_reg       37 include/soc/arc/aux.h 	tmp = read_aux_reg(reg);			\
read_aux_reg      130 include/soc/arc/mcip.h 	return read_aux_reg(ARC_REG_MCIP_READBACK);