rdmsrl 592 arch/x86/events/amd/core.c rdmsrl(x86_pmu_event_addr(idx), counter); rdmsrl 358 arch/x86/events/amd/ibs.c rdmsrl(event->hw.config_base, *config); rdmsrl 433 arch/x86/events/amd/ibs.c rdmsrl(hwc->config_base, config); rdmsrl 602 arch/x86/events/amd/ibs.c rdmsrl(msr, *buf); rdmsrl 623 arch/x86/events/amd/ibs.c rdmsrl(msr + offset, *buf++); rdmsrl 636 arch/x86/events/amd/ibs.c rdmsrl(MSR_AMD64_IBSBRTARGET, *buf++); rdmsrl 640 arch/x86/events/amd/ibs.c rdmsrl(MSR_AMD64_IBSOPDATA4, *buf++); rdmsrl 805 arch/x86/events/amd/ibs.c rdmsrl(MSR_AMD64_IBSCTL, val); rdmsrl 920 arch/x86/events/amd/ibs.c rdmsrl(MSR_AMD64_IBSCTL, val); rdmsrl 55 arch/x86/events/amd/power.c rdmsrl(MSR_F15H_CU_PWR_ACCUMULATOR, new_pwr_acc); rdmsrl 56 arch/x86/events/amd/power.c rdmsrl(MSR_F15H_PTSC, new_ptsc); rdmsrl 82 arch/x86/events/amd/power.c rdmsrl(MSR_F15H_PTSC, event->hw.ptsc); rdmsrl 83 arch/x86/events/amd/power.c rdmsrl(MSR_F15H_CU_PWR_ACCUMULATOR, event->hw.pwr_acc); rdmsrl 624 arch/x86/events/core.c rdmsrl(x86_pmu_config_addr(idx), val); rdmsrl 1369 arch/x86/events/core.c rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); rdmsrl 1370 arch/x86/events/core.c rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); rdmsrl 1371 arch/x86/events/core.c rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); rdmsrl 1372 arch/x86/events/core.c rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); rdmsrl 1380 arch/x86/events/core.c rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); rdmsrl 1384 arch/x86/events/core.c rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); rdmsrl 1391 arch/x86/events/core.c rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); rdmsrl 1392 arch/x86/events/core.c rdmsrl(x86_pmu_event_addr(idx), pmc_count); rdmsrl 1404 arch/x86/events/core.c rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); rdmsrl 2122 arch/x86/events/intel/core.c rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); rdmsrl 2139 arch/x86/events/intel/core.c rdmsrl(hwc->config_base, ctrl_val); rdmsrl 2225 arch/x86/events/intel/core.c rdmsrl(hwc->config_base, ctrl_val); rdmsrl 4583 arch/x86/events/intel/core.c rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); rdmsrl 354 arch/x86/events/intel/cstate.c rdmsrl(event->hw.event_base, val); rdmsrl 162 arch/x86/events/intel/knc.c rdmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); rdmsrl 171 arch/x86/events/intel/knc.c rdmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); rdmsrl 203 arch/x86/events/intel/knc.c rdmsrl(MSR_KNC_IA32_PERF_GLOBAL_STATUS, status); rdmsrl 174 arch/x86/events/intel/lbr.c rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); rdmsrl 192 arch/x86/events/intel/lbr.c rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); rdmsrl 240 arch/x86/events/intel/lbr.c rdmsrl(x86_pmu.lbr_tos, tos); rdmsrl 326 arch/x86/events/intel/lbr.c rdmsrl(x86_pmu.lbr_from + idx, val); rdmsrl 335 arch/x86/events/intel/lbr.c rdmsrl(x86_pmu.lbr_to + idx, val); rdmsrl 410 arch/x86/events/intel/lbr.c rdmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]); rdmsrl 552 arch/x86/events/intel/lbr.c rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr); rdmsrl 608 arch/x86/events/intel/lbr.c rdmsrl(MSR_LBR_INFO_0 + lbr_idx, info); rdmsrl 860 arch/x86/events/intel/p4.c rdmsrl(hwc->config_base, v); rdmsrl 873 arch/x86/events/intel/p4.c rdmsrl(hwc->event_base, v); rdmsrl 143 arch/x86/events/intel/p6.c rdmsrl(MSR_P6_EVNTSEL0, val); rdmsrl 153 arch/x86/events/intel/p6.c rdmsrl(MSR_P6_EVNTSEL0, val); rdmsrl 188 arch/x86/events/intel/pt.c rdmsrl(MSR_PLATFORM_INFO, reg); rdmsrl 224 arch/x86/events/intel/pt.c rdmsrl(MSR_IA32_VMX_MISC, reg); rdmsrl 852 arch/x86/events/intel/pt.c rdmsrl(MSR_IA32_RTIT_STATUS, status); rdmsrl 909 arch/x86/events/intel/pt.c rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, base_topa); rdmsrl 913 arch/x86/events/intel/pt.c rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, offset); rdmsrl 157 arch/x86/events/intel/rapl.c rdmsrl(event->hw.event_base, raw); rdmsrl 185 arch/x86/events/intel/rapl.c rdmsrl(event->hw.event_base, new_raw_count); rdmsrl 118 arch/x86/events/intel/uncore.c rdmsrl(event->hw.event_base, count); rdmsrl 216 arch/x86/events/intel/uncore_nhmex.c rdmsrl(msr, config); rdmsrl 231 arch/x86/events/intel/uncore_nhmex.c rdmsrl(msr, config); rdmsrl 352 arch/x86/events/intel/uncore_snb.c rdmsrl(ICL_UNC_CBO_CONFIG, num_boxes); rdmsrl 530 arch/x86/events/intel/uncore_snbep.c rdmsrl(msr, config); rdmsrl 543 arch/x86/events/intel/uncore_snbep.c rdmsrl(msr, config); rdmsrl 220 arch/x86/events/msr.c rdmsrl(event->hw.event_base, now); rdmsrl 41 arch/x86/hyperv/hv_apic.c rdmsrl(HV_X64_MSR_ICR, reg_val); rdmsrl 109 arch/x86/hyperv/hv_init.c rdmsrl(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status); rdmsrl 122 arch/x86/hyperv/hv_init.c rdmsrl(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status); rdmsrl 126 arch/x86/hyperv/hv_init.c rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq); rdmsrl 184 arch/x86/hyperv/hv_init.c rdmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *(u64 *)&re_ctrl); rdmsrl 213 arch/x86/hyperv/hv_init.c rdmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); rdmsrl 310 arch/x86/hyperv/hv_init.c rdmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); rdmsrl 375 arch/x86/hyperv/hv_init.c rdmsrl(HV_X64_MSR_GUEST_OS_ID, guest_id); rdmsrl 433 arch/x86/hyperv/hv_init.c rdmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); rdmsrl 52 arch/x86/hyperv/hv_spinlock.c rdmsrl(HV_X64_MSR_GUEST_IDLE, msr_val); rdmsrl 231 arch/x86/include/asm/apic.h rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); rdmsrl 256 arch/x86/include/asm/apic.h rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); rdmsrl 28 arch/x86/include/asm/fsgsbase.h rdmsrl(MSR_FS_BASE, fsbase); rdmsrl 37 arch/x86/include/asm/fsgsbase.h rdmsrl(MSR_KERNEL_GS_BASE, gsbase); rdmsrl 1494 arch/x86/include/asm/kvm_host.h rdmsrl(msr, value); rdmsrl 20 arch/x86/include/asm/mshyperv.h #define hv_get_simp(val) rdmsrl(HV_X64_MSR_SIMP, val) rdmsrl 23 arch/x86/include/asm/mshyperv.h #define hv_get_siefp(val) rdmsrl(HV_X64_MSR_SIEFP, val) rdmsrl 26 arch/x86/include/asm/mshyperv.h #define hv_get_synic_state(val) rdmsrl(HV_X64_MSR_SCONTROL, val) rdmsrl 29 arch/x86/include/asm/mshyperv.h #define hv_get_vp_index(index) rdmsrl(HV_X64_MSR_VP_INDEX, index) rdmsrl 34 arch/x86/include/asm/mshyperv.h rdmsrl(HV_X64_MSR_SINT0 + int_num, val) rdmsrl 39 arch/x86/include/asm/mshyperv.h rdmsrl(HV_X64_MSR_CRASH_CTL, val) rdmsrl 42 arch/x86/include/asm/mshyperv.h rdmsrl(HV_X64_MSR_TIME_REF_COUNT, val) rdmsrl 45 arch/x86/include/asm/mshyperv.h rdmsrl(HV_X64_MSR_REFERENCE_TSC, val) rdmsrl 364 arch/x86/include/asm/msr.h rdmsrl(msr_no, *q); rdmsrl 754 arch/x86/include/asm/processor.h rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); rdmsrl 115 arch/x86/include/asm/virtext.h rdmsrl(MSR_EFER, efer); rdmsrl 362 arch/x86/kernel/amd_nb.c rdmsrl(address, msr); rdmsrl 1801 arch/x86/kernel/apic/apic.c rdmsrl(MSR_IA32_APICBASE, msr); rdmsrl 1814 arch/x86/kernel/apic/apic.c rdmsrl(MSR_IA32_APICBASE, msr); rdmsrl 34 arch/x86/kernel/apic/apic_numachip.c rdmsrl(MSR_FAM10H_NODE_ID, value); rdmsrl 50 arch/x86/kernel/apic/apic_numachip.c rdmsrl(MSR_FAM10H_MMIO_CONF_BASE, mcfg); rdmsrl 179 arch/x86/kernel/apic/apic_numachip.c rdmsrl(MSR_FAM10H_NODE_ID, val); rdmsrl 373 arch/x86/kernel/cpu/amd.c rdmsrl(MSR_FAM10H_NODE_ID, value); rdmsrl 521 arch/x86/kernel/cpu/amd.c rdmsrl(MSR_K7_HWCR, val); rdmsrl 553 arch/x86/kernel/cpu/amd.c rdmsrl(MSR_FAM10H_NODE_ID, value); rdmsrl 598 arch/x86/kernel/cpu/amd.c rdmsrl(MSR_K8_SYSCFG, msr); rdmsrl 612 arch/x86/kernel/cpu/amd.c rdmsrl(MSR_K7_HWCR, msr); rdmsrl 713 arch/x86/kernel/cpu/amd.c rdmsrl(0xc0011005, value); rdmsrl 1132 arch/x86/kernel/cpu/amd.c rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); rdmsrl 1136 arch/x86/kernel/cpu/amd.c rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), rdmsrl 47 arch/x86/kernel/cpu/aperfmperf.c rdmsrl(MSR_IA32_APERF, aperf); rdmsrl 48 arch/x86/kernel/cpu/aperfmperf.c rdmsrl(MSR_IA32_MPERF, mperf); rdmsrl 99 arch/x86/kernel/cpu/bugs.c rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); rdmsrl 431 arch/x86/kernel/cpu/bugs.c rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); rdmsrl 1129 arch/x86/kernel/cpu/common.c rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); rdmsrl 1358 arch/x86/kernel/cpu/common.c rdmsrl(MSR_FS_BASE, old_base); rdmsrl 1361 arch/x86/kernel/cpu/common.c rdmsrl(MSR_FS_BASE, tmp); rdmsrl 99 arch/x86/kernel/cpu/hygon.c rdmsrl(MSR_FAM10H_NODE_ID, value); rdmsrl 226 arch/x86/kernel/cpu/hygon.c rdmsrl(MSR_K7_HWCR, val); rdmsrl 242 arch/x86/kernel/cpu/hygon.c rdmsrl(MSR_FAM10H_NODE_ID, value); rdmsrl 297 arch/x86/kernel/cpu/intel.c rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); rdmsrl 569 arch/x86/kernel/cpu/intel.c rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate); rdmsrl 65 arch/x86/kernel/cpu/intel_epb.c rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); rdmsrl 80 arch/x86/kernel/cpu/intel_epb.c rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); rdmsrl 609 arch/x86/kernel/cpu/mce/amd.c rdmsrl(MSR_K7_HWCR, hwcr); rdmsrl 899 arch/x86/kernel/cpu/mce/amd.c rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); rdmsrl 902 arch/x86/kernel/cpu/mce/amd.c rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); rdmsrl 926 arch/x86/kernel/cpu/mce/amd.c rdmsrl(msr_stat, status); rdmsrl 931 arch/x86/kernel/cpu/mce/amd.c rdmsrl(msr_addr, addr); rdmsrl 143 arch/x86/kernel/cpu/mce/core.c rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); rdmsrl 146 arch/x86/kernel/cpu/mce/core.c rdmsrl(MSR_PPIN, m->ppin); rdmsrl 1518 arch/x86/kernel/cpu/mce/core.c rdmsrl(MSR_IA32_MCG_CAP, cap); rdmsrl 1557 arch/x86/kernel/cpu/mce/core.c rdmsrl(MSR_IA32_MCG_CAP, cap); rdmsrl 1599 arch/x86/kernel/cpu/mce/core.c rdmsrl(msr_ops.ctl(i), msrval); rdmsrl 92 arch/x86/kernel/cpu/mce/intel.c rdmsrl(MSR_IA32_MCG_CAP, cap); rdmsrl 104 arch/x86/kernel/cpu/mce/intel.c rdmsrl(MSR_IA32_MCG_CAP, tmp); rdmsrl 119 arch/x86/kernel/cpu/mce/intel.c rdmsrl(MSR_IA32_FEATURE_CONTROL, tmp); rdmsrl 161 arch/x86/kernel/cpu/mce/intel.c rdmsrl(MSR_IA32_MCx_CTL2(bank), val); rdmsrl 283 arch/x86/kernel/cpu/mce/intel.c rdmsrl(MSR_IA32_MCx_CTL2(i), val); rdmsrl 307 arch/x86/kernel/cpu/mce/intel.c rdmsrl(MSR_IA32_MCx_CTL2(i), val); rdmsrl 359 arch/x86/kernel/cpu/mce/intel.c rdmsrl(MSR_IA32_MCx_CTL2(bank), val); rdmsrl 452 arch/x86/kernel/cpu/mce/intel.c rdmsrl(MSR_IA32_MCG_EXT_CTL, val); rdmsrl 465 arch/x86/kernel/cpu/mce/intel.c rdmsrl(MSR_IA32_MCG_EXT_CTL, val); rdmsrl 360 arch/x86/kernel/cpu/mce/therm_throt.c rdmsrl(MSR_IA32_THERM_STATUS, msr_val); rdmsrl 375 arch/x86/kernel/cpu/mce/therm_throt.c rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val); rdmsrl 197 arch/x86/kernel/cpu/mshyperv.c rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq); rdmsrl 284 arch/x86/kernel/cpu/mshyperv.c rdmsrl(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency); rdmsrl 90 arch/x86/kernel/cpu/resctrl/monitor.c rdmsrl(MSR_IA32_QM_CTR, val); rdmsrl 23 arch/x86/kernel/cpu/tsx.c rdmsrl(MSR_IA32_TSX_CTRL, tsx); rdmsrl 43 arch/x86/kernel/cpu/tsx.c rdmsrl(MSR_IA32_TSX_CTRL, tsx); rdmsrl 222 arch/x86/kernel/cpu/umwait.c rdmsrl(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached); rdmsrl 99 arch/x86/kernel/mmconf-fam10h_64.c rdmsrl(address, val); rdmsrl 107 arch/x86/kernel/mmconf-fam10h_64.c rdmsrl(address, val); rdmsrl 179 arch/x86/kernel/mmconf-fam10h_64.c rdmsrl(address, val); rdmsrl 508 arch/x86/kernel/process.c rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); rdmsrl 96 arch/x86/kernel/process_64.c rdmsrl(MSR_FS_BASE, fs); rdmsrl 97 arch/x86/kernel/process_64.c rdmsrl(MSR_KERNEL_GS_BASE, shadowgs); rdmsrl 108 arch/x86/kernel/process_64.c rdmsrl(MSR_FS_BASE, fs); rdmsrl 109 arch/x86/kernel/process_64.c rdmsrl(MSR_GS_BASE, gs); rdmsrl 110 arch/x86/kernel/process_64.c rdmsrl(MSR_KERNEL_GS_BASE, shadowgs); rdmsrl 1055 arch/x86/kernel/tsc.c rdmsrl(MSR_IA32_TSC_ADJUST, art_to_tsc_offset); rdmsrl 66 arch/x86/kernel/tsc_sync.c rdmsrl(MSR_IA32_TSC_ADJUST, curval); rdmsrl 126 arch/x86/kernel/tsc_sync.c rdmsrl(MSR_IA32_TSC_ADJUST, bootval); rdmsrl 148 arch/x86/kernel/tsc_sync.c rdmsrl(MSR_IA32_TSC_ADJUST, bootval); rdmsrl 917 arch/x86/kvm/svm.c rdmsrl(MSR_EFER, efer); rdmsrl 1316 arch/x86/kvm/svm.c rdmsrl(MSR_K8_SYSCFG, msr); rdmsrl 2324 arch/x86/kvm/svm.c rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base); rdmsrl 2331 arch/x86/kvm/svm.c rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); rdmsrl 5897 arch/x86/kvm/svm.c rdmsrl(MSR_VM_CR, vm_cr); rdmsrl 225 arch/x86/kvm/vmx/capabilities.h rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); rdmsrl 350 arch/x86/kvm/vmx/capabilities.h rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); rdmsrl 6015 arch/x86/kvm/vmx/nested.c rdmsrl(MSR_IA32_VMX_CR0_FIXED1, msrs->cr0_fixed1); rdmsrl 6016 arch/x86/kvm/vmx/nested.c rdmsrl(MSR_IA32_VMX_CR4_FIXED1, msrs->cr4_fixed1); rdmsrl 225 arch/x86/kvm/vmx/vmx.c rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr); rdmsrl 1039 arch/x86/kvm/vmx/vmx.c rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); rdmsrl 1040 arch/x86/kvm/vmx/vmx.c rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); rdmsrl 1041 arch/x86/kvm/vmx/vmx.c rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); rdmsrl 1042 arch/x86/kvm/vmx/vmx.c rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); rdmsrl 1044 arch/x86/kvm/vmx/vmx.c rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); rdmsrl 1045 arch/x86/kvm/vmx/vmx.c rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); rdmsrl 1058 arch/x86/kvm/vmx/vmx.c rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); rdmsrl 1186 arch/x86/kvm/vmx/vmx.c rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); rdmsrl 1218 arch/x86/kvm/vmx/vmx.c rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); rdmsrl 1349 arch/x86/kvm/vmx/vmx.c rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); rdmsrl 2192 arch/x86/kvm/vmx/vmx.c rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); rdmsrl 2240 arch/x86/kvm/vmx/vmx.c rdmsrl(MSR_IA32_FEATURE_CONTROL, old); rdmsrl 3902 arch/x86/kvm/vmx/vmx.c rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); rdmsrl 7631 arch/x86/kvm/vmx/vmx.c rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs); rdmsrl 7636 arch/x86/kvm/vmx/vmx.c rdmsrl(MSR_IA32_XSS, host_xss); rdmsrl 7730 arch/x86/kvm/vmx/vmx.c rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); rdmsrl 1344 arch/x86/kvm/x86.c rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); rdmsrl 657 arch/x86/lib/insn-eval.c rdmsrl(MSR_FS_BASE, base); rdmsrl 663 arch/x86/lib/insn-eval.c rdmsrl(MSR_KERNEL_GS_BASE, base); rdmsrl 222 arch/x86/mm/pat.c rdmsrl(MSR_IA32_CR_PAT, tmp_pat); rdmsrl 264 arch/x86/mm/pat.c rdmsrl(MSR_IA32_CR_PAT, pat); rdmsrl 83 arch/x86/oprofile/nmi_int.c rdmsrl(counters[i].addr, counters[i].saved); rdmsrl 88 arch/x86/oprofile/nmi_int.c rdmsrl(controls[i].addr, controls[i].saved); rdmsrl 209 arch/x86/oprofile/nmi_int.c rdmsrl(counters[i].addr, multiplex[virt].saved); rdmsrl 142 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl); rdmsrl 144 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSFETCHLINAD, val); rdmsrl 149 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val); rdmsrl 161 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSOPCTL, ctl); rdmsrl 163 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSOPRIP, val); rdmsrl 167 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSOPDATA, val); rdmsrl 169 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSOPDATA2, val); rdmsrl 171 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSOPDATA3, val); rdmsrl 173 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSDCLINAD, val); rdmsrl 175 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSDCPHYSAD, val); rdmsrl 178 arch/x86/oprofile/op_model_amd.c rdmsrl(MSR_AMD64_IBSBRTARGET, val); rdmsrl 279 arch/x86/oprofile/op_model_amd.c rdmsrl(msrs->controls[i].addr, val); rdmsrl 352 arch/x86/oprofile/op_model_amd.c rdmsrl(msrs->controls[i].addr, val); rdmsrl 374 arch/x86/oprofile/op_model_amd.c rdmsrl(msrs->controls[i].addr, val); rdmsrl 391 arch/x86/oprofile/op_model_amd.c rdmsrl(msrs->counters[i].addr, val); rdmsrl 413 arch/x86/oprofile/op_model_amd.c rdmsrl(msrs->controls[i].addr, val); rdmsrl 433 arch/x86/oprofile/op_model_amd.c rdmsrl(msrs->controls[i].addr, val); rdmsrl 99 arch/x86/oprofile/op_model_ppro.c rdmsrl(msrs->controls[i].addr, val); rdmsrl 116 arch/x86/oprofile/op_model_ppro.c rdmsrl(msrs->controls[i].addr, val); rdmsrl 136 arch/x86/oprofile/op_model_ppro.c rdmsrl(msrs->counters[i].addr, val); rdmsrl 165 arch/x86/oprofile/op_model_ppro.c rdmsrl(msrs->controls[i].addr, val); rdmsrl 181 arch/x86/oprofile/op_model_ppro.c rdmsrl(msrs->controls[i].addr, val); rdmsrl 197 arch/x86/pci/amd_bus.c rdmsrl(address, val); rdmsrl 288 arch/x86/pci/amd_bus.c rdmsrl(address, val); rdmsrl 293 arch/x86/pci/amd_bus.c rdmsrl(address, val); rdmsrl 336 arch/x86/pci/amd_bus.c rdmsrl(MSR_AMD64_NB_CFG, reg); rdmsrl 67 arch/x86/platform/olpc/olpc-xo1-rtc.c rdmsrl(MSR_RTC_DOMA_OFFSET, rtc_info.rtc_day_alarm); rdmsrl 68 arch/x86/platform/olpc/olpc-xo1-rtc.c rdmsrl(MSR_RTC_MONA_OFFSET, rtc_info.rtc_mon_alarm); rdmsrl 69 arch/x86/platform/olpc/olpc-xo1-rtc.c rdmsrl(MSR_RTC_CEN_OFFSET, rtc_info.rtc_century); rdmsrl 111 arch/x86/power/cpu.c rdmsrl(MSR_FS_BASE, ctxt->fs_base); rdmsrl 112 arch/x86/power/cpu.c rdmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base); rdmsrl 113 arch/x86/power/cpu.c rdmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); rdmsrl 116 arch/x86/power/cpu.c rdmsrl(MSR_EFER, ctxt->efer); rdmsrl 97 arch/x86/realmode/init.c rdmsrl(MSR_EFER, efer); rdmsrl 60 arch/x86/xen/suspend.c rdmsrl(MSR_IA32_SPEC_CTRL, tmp); rdmsrl 226 drivers/acpi/acpi_extlog.c rdmsrl(MSR_IA32_MCG_CAP, cap); rdmsrl 110 drivers/cpufreq/acpi-cpufreq.c rdmsrl(msr_addr, val); rdmsrl 229 drivers/cpufreq/e_powersaver.c rdmsrl(MSR_IA32_MISC_ENABLE, val); rdmsrl 234 drivers/cpufreq/e_powersaver.c rdmsrl(MSR_IA32_MISC_ENABLE, val); rdmsrl 507 drivers/cpufreq/intel_pstate.c rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); rdmsrl 1313 drivers/cpufreq/intel_pstate.c rdmsrl(MSR_ATOM_CORE_RATIOS, value); rdmsrl 1321 drivers/cpufreq/intel_pstate.c rdmsrl(MSR_ATOM_CORE_RATIOS, value); rdmsrl 1329 drivers/cpufreq/intel_pstate.c rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); rdmsrl 1364 drivers/cpufreq/intel_pstate.c rdmsrl(MSR_FSB_FREQ, value); rdmsrl 1380 drivers/cpufreq/intel_pstate.c rdmsrl(MSR_FSB_FREQ, value); rdmsrl 1391 drivers/cpufreq/intel_pstate.c rdmsrl(MSR_ATOM_CORE_VIDS, value); rdmsrl 1399 drivers/cpufreq/intel_pstate.c rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); rdmsrl 1407 drivers/cpufreq/intel_pstate.c rdmsrl(MSR_PLATFORM_INFO, value); rdmsrl 1415 drivers/cpufreq/intel_pstate.c rdmsrl(MSR_PLATFORM_INFO, value); rdmsrl 1460 drivers/cpufreq/intel_pstate.c rdmsrl(MSR_PLATFORM_INFO, plat_info); rdmsrl 1492 drivers/cpufreq/intel_pstate.c rdmsrl(MSR_TURBO_RATIO_LIMIT, value); rdmsrl 1526 drivers/cpufreq/intel_pstate.c rdmsrl(MSR_TURBO_RATIO_LIMIT, value); rdmsrl 1711 drivers/cpufreq/intel_pstate.c rdmsrl(MSR_IA32_APERF, aperf); rdmsrl 1712 drivers/cpufreq/intel_pstate.c rdmsrl(MSR_IA32_MPERF, mperf); rdmsrl 2687 drivers/cpufreq/intel_pstate.c rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); rdmsrl 139 drivers/cpufreq/longhaul.c rdmsrl(MSR_VIA_BCR2, bcr2.val); rdmsrl 154 drivers/cpufreq/longhaul.c rdmsrl(MSR_VIA_BCR2, bcr2.val); rdmsrl 167 drivers/cpufreq/longhaul.c rdmsrl(MSR_VIA_LONGHAUL, longhaul.val); rdmsrl 536 drivers/cpufreq/longhaul.c rdmsrl(MSR_VIA_LONGHAUL, longhaul.val); rdmsrl 222 drivers/cpufreq/powernow-k7.c rdmsrl(MSR_K7_FID_VID_CTL, fidvidctl.val); rdmsrl 237 drivers/cpufreq/powernow-k7.c rdmsrl(MSR_K7_FID_VID_CTL, fidvidctl.val); rdmsrl 263 drivers/cpufreq/powernow-k7.c rdmsrl(MSR_K7_FID_VID_STATUS, fidvidstatus.val); rdmsrl 560 drivers/cpufreq/powernow-k7.c rdmsrl(MSR_K7_FID_VID_STATUS, fidvidstatus.val); rdmsrl 601 drivers/cpufreq/powernow-k7.c rdmsrl(MSR_K7_FID_VID_STATUS, fidvidstatus.val); rdmsrl 2775 drivers/edac/amd64_edac.c rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); rdmsrl 2779 drivers/edac/amd64_edac.c rdmsrl(MSR_K8_SYSCFG, msr_val); rdmsrl 2781 drivers/edac/amd64_edac.c rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); rdmsrl 959 drivers/idle/intel_idle.c rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits); rdmsrl 967 drivers/idle/intel_idle.c rdmsrl(MSR_IA32_POWER_CTL, msr_bits); rdmsrl 1219 drivers/idle/intel_idle.c rdmsrl(MSR_PKGC6_IRTL, msr); rdmsrl 1226 drivers/idle/intel_idle.c rdmsrl(MSR_PKGC7_IRTL, msr); rdmsrl 1233 drivers/idle/intel_idle.c rdmsrl(MSR_PKGC8_IRTL, msr); rdmsrl 1240 drivers/idle/intel_idle.c rdmsrl(MSR_PKGC9_IRTL, msr); rdmsrl 1247 drivers/idle/intel_idle.c rdmsrl(MSR_PKGC10_IRTL, msr); rdmsrl 1275 drivers/idle/intel_idle.c rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr); rdmsrl 1287 drivers/idle/intel_idle.c rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); rdmsrl 276 drivers/mtd/nand/raw/cs553x_nand.c rdmsrl(MSR_DIVIL_GLD_CAP, val); rdmsrl 282 drivers/mtd/nand/raw/cs553x_nand.c rdmsrl(MSR_DIVIL_BALL_OPTS, val); rdmsrl 289 drivers/mtd/nand/raw/cs553x_nand.c rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val); rdmsrl 372 drivers/platform/x86/intel_ips.c rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); rdmsrl 407 drivers/platform/x86/intel_ips.c rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); rdmsrl 439 drivers/platform/x86/intel_ips.c rdmsrl(IA32_PERF_CTL, perf_ctl); rdmsrl 477 drivers/platform/x86/intel_ips.c rdmsrl(IA32_PERF_CTL, perf_ctl); rdmsrl 1239 drivers/platform/x86/intel_ips.c rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); rdmsrl 1311 drivers/platform/x86/intel_ips.c rdmsrl(IA32_MISC_ENABLE, misc_en); rdmsrl 1333 drivers/platform/x86/intel_ips.c rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_power); rdmsrl 1515 drivers/platform/x86/intel_ips.c rdmsrl(PLATFORM_INFO, platform_info); rdmsrl 1548 drivers/platform/x86/intel_ips.c rdmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit); rdmsrl 1615 drivers/platform/x86/intel_ips.c rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); rdmsrl 44 drivers/platform/x86/intel_speed_select_if/isst_if_mbox_msr.c rdmsrl(MSR_OS_MAILBOX_INTERFACE, data); rdmsrl 69 drivers/platform/x86/intel_speed_select_if/isst_if_mbox_msr.c rdmsrl(MSR_OS_MAILBOX_INTERFACE, data); rdmsrl 79 drivers/platform/x86/intel_speed_select_if/isst_if_mbox_msr.c rdmsrl(MSR_OS_MAILBOX_DATA, data); rdmsrl 280 drivers/thermal/intel/x86_pkg_temp_thermal.c rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val); rdmsrl 383 drivers/video/fbdev/geode/gxfb_core.c rdmsrl(MSR_GX_GLD_MSR_CONFIG, val); rdmsrl 361 drivers/video/fbdev/geode/lxfb_ops.c rdmsrl(MSR_LX_GLD_MSR_CONFIG, msrval); rdmsrl 422 drivers/video/fbdev/geode/lxfb_ops.c rdmsrl(MSR_LX_SPARE_MSR, msrval); rdmsrl 596 drivers/video/fbdev/geode/lxfb_ops.c rdmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel); rdmsrl 597 drivers/video/fbdev/geode/lxfb_ops.c rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll); rdmsrl 598 drivers/video/fbdev/geode/lxfb_ops.c rdmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg); rdmsrl 599 drivers/video/fbdev/geode/lxfb_ops.c rdmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare); rdmsrl 26 drivers/video/fbdev/geode/suspend_gx.c rdmsrl(MSR_GX_MSR_PADSEL, par->msr.padsel); rdmsrl 27 drivers/video/fbdev/geode/suspend_gx.c rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll); rdmsrl 48 drivers/video/fbdev/geode/suspend_gx.c rdmsrl(MSR_GLCP_DOTPLL, dotpll_lo); rdmsrl 55 drivers/video/fbdev/geode/suspend_gx.c rdmsrl(MSR_GLCP_DOTPLL, dotpll_lo); rdmsrl 145 drivers/video/fbdev/geode/video_gx.c rdmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll); rdmsrl 146 drivers/video/fbdev/geode/video_gx.c rdmsrl(MSR_GLCP_DOTPLL, dotpll); rdmsrl 170 drivers/video/fbdev/geode/video_gx.c rdmsrl(MSR_GLCP_DOTPLL, dotpll); rdmsrl 183 drivers/video/fbdev/geode/video_gx.c rdmsrl(MSR_GX_MSR_PADSEL, val);