rd_cio_state      547 drivers/gpu/drm/nouveau/dispnv04/hw.c 		rd_cio_state(dev, head, regp, i);
rd_cio_state      595 drivers/gpu/drm/nouveau/dispnv04/hw.c 	rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
rd_cio_state      596 drivers/gpu/drm/nouveau/dispnv04/hw.c 	rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
rd_cio_state      597 drivers/gpu/drm/nouveau/dispnv04/hw.c 	rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
rd_cio_state      598 drivers/gpu/drm/nouveau/dispnv04/hw.c 	rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
rd_cio_state      599 drivers/gpu/drm/nouveau/dispnv04/hw.c 	rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
rd_cio_state      600 drivers/gpu/drm/nouveau/dispnv04/hw.c 	rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
rd_cio_state      601 drivers/gpu/drm/nouveau/dispnv04/hw.c 	rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
rd_cio_state      603 drivers/gpu/drm/nouveau/dispnv04/hw.c 	rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
rd_cio_state      604 drivers/gpu/drm/nouveau/dispnv04/hw.c 	rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
rd_cio_state      605 drivers/gpu/drm/nouveau/dispnv04/hw.c 	rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
rd_cio_state      608 drivers/gpu/drm/nouveau/dispnv04/hw.c 		rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
rd_cio_state      611 drivers/gpu/drm/nouveau/dispnv04/hw.c 		rd_cio_state(dev, head, regp, 0x9f);
rd_cio_state      613 drivers/gpu/drm/nouveau/dispnv04/hw.c 	rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
rd_cio_state      614 drivers/gpu/drm/nouveau/dispnv04/hw.c 	rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
rd_cio_state      615 drivers/gpu/drm/nouveau/dispnv04/hw.c 	rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
rd_cio_state      616 drivers/gpu/drm/nouveau/dispnv04/hw.c 	rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
rd_cio_state      617 drivers/gpu/drm/nouveau/dispnv04/hw.c 	rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
rd_cio_state      636 drivers/gpu/drm/nouveau/dispnv04/hw.c 	rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
rd_cio_state      637 drivers/gpu/drm/nouveau/dispnv04/hw.c 	rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
rd_cio_state      639 drivers/gpu/drm/nouveau/dispnv04/hw.c 		rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
rd_cio_state      640 drivers/gpu/drm/nouveau/dispnv04/hw.c 		rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
rd_cio_state      641 drivers/gpu/drm/nouveau/dispnv04/hw.c 		rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);
rd_cio_state      642 drivers/gpu/drm/nouveau/dispnv04/hw.c 		rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
rd_cio_state      646 drivers/gpu/drm/nouveau/dispnv04/hw.c 		rd_cio_state(dev, head, regp, NV_CIO_CRE_42);
rd_cio_state      647 drivers/gpu/drm/nouveau/dispnv04/hw.c 		rd_cio_state(dev, head, regp, NV_CIO_CRE_53);
rd_cio_state      648 drivers/gpu/drm/nouveau/dispnv04/hw.c 		rd_cio_state(dev, head, regp, NV_CIO_CRE_54);
rd_cio_state      652 drivers/gpu/drm/nouveau/dispnv04/hw.c 		rd_cio_state(dev, head, regp, NV_CIO_CRE_59);
rd_cio_state      653 drivers/gpu/drm/nouveau/dispnv04/hw.c 		rd_cio_state(dev, head, regp, NV_CIO_CRE_5B);
rd_cio_state      655 drivers/gpu/drm/nouveau/dispnv04/hw.c 		rd_cio_state(dev, head, regp, NV_CIO_CRE_85);
rd_cio_state      656 drivers/gpu/drm/nouveau/dispnv04/hw.c 		rd_cio_state(dev, head, regp, NV_CIO_CRE_86);