radeon_ring_write 3478 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); radeon_ring_write 3479 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2)); radeon_ring_write 3480 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0xDEADBEEF); radeon_ring_write 3534 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); radeon_ring_write 3535 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ radeon_ring_write 3538 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2); radeon_ring_write 3539 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2); radeon_ring_write 3540 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, ref_and_mask); radeon_ring_write 3541 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, ref_and_mask); radeon_ring_write 3542 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0x20); /* poll interval */ radeon_ring_write 3563 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); radeon_ring_write 3564 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | radeon_ring_write 3568 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, addr & 0xfffffffc); radeon_ring_write 3569 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | radeon_ring_write 3571 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, fence->seq - 1); radeon_ring_write 3572 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0); radeon_ring_write 3575 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); radeon_ring_write 3576 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | radeon_ring_write 3580 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, addr & 0xfffffffc); radeon_ring_write 3581 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2)); radeon_ring_write 3582 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, fence->seq); radeon_ring_write 3583 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0); radeon_ring_write 3602 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); radeon_ring_write 3603 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | radeon_ring_write 3607 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2)); radeon_ring_write 3608 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, addr & 0xfffffffc); radeon_ring_write 3609 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, upper_32_bits(addr)); radeon_ring_write 3610 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, fence->seq); radeon_ring_write 3611 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0); radeon_ring_write 3633 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); radeon_ring_write 3634 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, lower_32_bits(addr)); radeon_ring_write 3635 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); radeon_ring_write 3639 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); radeon_ring_write 3640 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0x0); radeon_ring_write 3694 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); radeon_ring_write 3695 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, control); radeon_ring_write 3696 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, lower_32_bits(src_offset)); radeon_ring_write 3697 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, upper_32_bits(src_offset)); radeon_ring_write 3698 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, lower_32_bits(dst_offset)); radeon_ring_write 3699 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, upper_32_bits(dst_offset)); radeon_ring_write 3700 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, cur_size_in_bytes); radeon_ring_write 3741 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); radeon_ring_write 3742 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0); radeon_ring_write 3749 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); radeon_ring_write 3750 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, ((ring->rptr_save_reg - radeon_ring_write 3752 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, next_rptr); radeon_ring_write 3755 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); radeon_ring_write 3756 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); radeon_ring_write 3757 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); radeon_ring_write 3758 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); radeon_ring_write 3759 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, next_rptr); radeon_ring_write 3767 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, header); radeon_ring_write 3768 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFFC)); radeon_ring_write 3769 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); radeon_ring_write 3770 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, control); radeon_ring_write 4004 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); radeon_ring_write 4005 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); radeon_ring_write 4006 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0x8000); radeon_ring_write 4007 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0x8000); radeon_ring_write 4010 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); radeon_ring_write 4011 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); radeon_ring_write 4013 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); radeon_ring_write 4014 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0x80000000); radeon_ring_write 4015 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0x80000000); radeon_ring_write 4018 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, cik_default_state[i]); radeon_ring_write 4020 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); radeon_ring_write 4021 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); radeon_ring_write 4024 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); radeon_ring_write 4025 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0); radeon_ring_write 4027 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); radeon_ring_write 4028 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0x00000316); radeon_ring_write 4029 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ radeon_ring_write 4030 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ radeon_ring_write 5697 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); radeon_ring_write 5698 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | radeon_ring_write 5701 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, radeon_ring_write 5704 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, radeon_ring_write 5707 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0); radeon_ring_write 5708 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, pd_addr >> 12); radeon_ring_write 5711 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); radeon_ring_write 5712 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | radeon_ring_write 5714 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); radeon_ring_write 5715 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0); radeon_ring_write 5716 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, VMID(vm_id)); radeon_ring_write 5718 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); radeon_ring_write 5719 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | radeon_ring_write 5721 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, SH_MEM_BASES >> 2); radeon_ring_write 5722 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0); radeon_ring_write 5724 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0); /* SH_MEM_BASES */ radeon_ring_write 5725 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, SH_MEM_CONFIG_GFX_DEFAULT); /* SH_MEM_CONFIG */ radeon_ring_write 5726 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */ radeon_ring_write 5727 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ radeon_ring_write 5729 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); radeon_ring_write 5730 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | radeon_ring_write 5732 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); radeon_ring_write 5733 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0); radeon_ring_write 5734 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, VMID(0)); radeon_ring_write 5740 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); radeon_ring_write 5741 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | radeon_ring_write 5743 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); radeon_ring_write 5744 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0); radeon_ring_write 5745 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 1 << vm_id); radeon_ring_write 5748 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); radeon_ring_write 5749 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ radeon_ring_write 5752 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); radeon_ring_write 5753 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0); radeon_ring_write 5754 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0); /* ref */ radeon_ring_write 5755 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0); /* mask */ radeon_ring_write 5756 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0x20); /* poll interval */ radeon_ring_write 5761 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); radeon_ring_write 5762 drivers/gpu/drm/radeon/cik.c radeon_ring_write(ring, 0x0); radeon_ring_write 144 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); radeon_ring_write 145 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); radeon_ring_write 146 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); radeon_ring_write 147 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, 1); /* number of DWs to follow */ radeon_ring_write 148 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, next_rptr); radeon_ring_write 153 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); radeon_ring_write 154 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); radeon_ring_write 155 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ radeon_ring_write 156 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); radeon_ring_write 157 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, ib->length_dw); radeon_ring_write 182 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); radeon_ring_write 183 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); radeon_ring_write 184 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); radeon_ring_write 185 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, ref_and_mask); /* reference */ radeon_ring_write 186 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, ref_and_mask); /* mask */ radeon_ring_write 187 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ radeon_ring_write 207 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); radeon_ring_write 208 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, lower_32_bits(addr)); radeon_ring_write 209 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, upper_32_bits(addr)); radeon_ring_write 210 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, fence->seq); radeon_ring_write 212 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); radeon_ring_write 236 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits)); radeon_ring_write 237 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, addr & 0xfffffff8); radeon_ring_write 238 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, upper_32_bits(addr)); radeon_ring_write 611 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0)); radeon_ring_write 612 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, cur_size_in_bytes); radeon_ring_write 613 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, 0); /* src/dst endian swap */ radeon_ring_write 614 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, lower_32_bits(src_offset)); radeon_ring_write 615 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, upper_32_bits(src_offset)); radeon_ring_write 616 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, lower_32_bits(dst_offset)); radeon_ring_write 617 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, upper_32_bits(dst_offset)); radeon_ring_write 669 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); radeon_ring_write 670 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, lower_32_bits(gpu_addr)); radeon_ring_write 671 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, upper_32_bits(gpu_addr)); radeon_ring_write 672 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, 1); /* number of DWs to follow */ radeon_ring_write 673 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, 0xDEADBEEF); radeon_ring_write 953 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); radeon_ring_write 955 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2); radeon_ring_write 957 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2); radeon_ring_write 959 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, pd_addr >> 12); radeon_ring_write 962 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); radeon_ring_write 963 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); radeon_ring_write 964 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, VMID(vm_id)); radeon_ring_write 966 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); radeon_ring_write 967 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SH_MEM_BASES >> 2); radeon_ring_write 968 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, 0); radeon_ring_write 970 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); radeon_ring_write 971 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SH_MEM_CONFIG >> 2); radeon_ring_write 972 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, 0); radeon_ring_write 974 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); radeon_ring_write 975 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2); radeon_ring_write 976 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, 1); radeon_ring_write 978 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); radeon_ring_write 979 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2); radeon_ring_write 980 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, 0); radeon_ring_write 982 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); radeon_ring_write 983 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); radeon_ring_write 984 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, VMID(0)); radeon_ring_write 990 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); radeon_ring_write 991 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); radeon_ring_write 992 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, 1 << vm_id); radeon_ring_write 994 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); radeon_ring_write 995 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); radeon_ring_write 996 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, 0); radeon_ring_write 997 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, 0); /* reference */ radeon_ring_write 998 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, 0); /* mask */ radeon_ring_write 999 drivers/gpu/drm/radeon/cik_sdma.c radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ radeon_ring_write 2936 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); radeon_ring_write 2937 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 1); radeon_ring_write 2941 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); radeon_ring_write 2942 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, ((ring->rptr_save_reg - radeon_ring_write 2944 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, next_rptr); radeon_ring_write 2947 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); radeon_ring_write 2948 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); radeon_ring_write 2949 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); radeon_ring_write 2950 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, next_rptr); radeon_ring_write 2951 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0); radeon_ring_write 2954 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); radeon_ring_write 2955 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, radeon_ring_write 2960 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); radeon_ring_write 2961 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, ib->length_dw); radeon_ring_write 3008 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); radeon_ring_write 3009 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0x1); radeon_ring_write 3010 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0x0); radeon_ring_write 3011 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1); radeon_ring_write 3012 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); radeon_ring_write 3013 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0); radeon_ring_write 3014 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0); radeon_ring_write 3027 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); radeon_ring_write 3028 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); radeon_ring_write 3031 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, evergreen_default_state[i]); radeon_ring_write 3033 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); radeon_ring_write 3034 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); radeon_ring_write 3037 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); radeon_ring_write 3038 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0); radeon_ring_write 3041 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0xc0026f00); radeon_ring_write 3042 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0x00000000); radeon_ring_write 3043 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0x00000000); radeon_ring_write 3044 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0x00000000); radeon_ring_write 3047 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0xc0036f00); radeon_ring_write 3048 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0x00000bc4); radeon_ring_write 3049 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0xffffffff); radeon_ring_write 3050 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0xffffffff); radeon_ring_write 3051 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0xffffffff); radeon_ring_write 3053 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0xc0026900); radeon_ring_write 3054 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0x00000316); radeon_ring_write 3055 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ radeon_ring_write 3056 drivers/gpu/drm/radeon/evergreen.c radeon_ring_write(ring, 0x00000010); /* */ radeon_ring_write 47 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0)); radeon_ring_write 48 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, addr & 0xfffffffc); radeon_ring_write 49 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); radeon_ring_write 50 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, fence->seq); radeon_ring_write 52 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0)); radeon_ring_write 54 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0)); radeon_ring_write 55 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); radeon_ring_write 56 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, 1); radeon_ring_write 77 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1)); radeon_ring_write 78 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); radeon_ring_write 79 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); radeon_ring_write 80 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, next_rptr); radeon_ring_write 87 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0)); radeon_ring_write 88 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0)); radeon_ring_write 89 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); radeon_ring_write 90 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); radeon_ring_write 140 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw)); radeon_ring_write 141 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, dst_offset & 0xfffffffc); radeon_ring_write 142 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, src_offset & 0xfffffffc); radeon_ring_write 143 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); radeon_ring_write 144 drivers/gpu/drm/radeon/evergreen_dma.c radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); radeon_ring_write 1411 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); radeon_ring_write 1412 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); radeon_ring_write 1413 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0xFFFFFFFF); radeon_ring_write 1414 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0); radeon_ring_write 1415 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 10); /* poll interval */ radeon_ring_write 1417 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); radeon_ring_write 1418 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); radeon_ring_write 1419 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, lower_32_bits(addr)); radeon_ring_write 1420 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); radeon_ring_write 1421 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, fence->seq); radeon_ring_write 1422 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0); radeon_ring_write 1433 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); radeon_ring_write 1434 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 1); radeon_ring_write 1438 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); radeon_ring_write 1439 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, ((ring->rptr_save_reg - radeon_ring_write 1441 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, next_rptr); radeon_ring_write 1444 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); radeon_ring_write 1445 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, radeon_ring_write 1450 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); radeon_ring_write 1451 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, ib->length_dw | (vm_id << 24)); radeon_ring_write 1454 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); radeon_ring_write 1455 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); radeon_ring_write 1456 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0xFFFFFFFF); radeon_ring_write 1457 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0); radeon_ring_write 1458 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, (vm_id << 24) | 10); /* poll interval */ radeon_ring_write 1560 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); radeon_ring_write 1561 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0x1); radeon_ring_write 1562 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0x0); radeon_ring_write 1563 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1); radeon_ring_write 1564 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); radeon_ring_write 1565 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0); radeon_ring_write 1566 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0); radeon_ring_write 1578 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); radeon_ring_write 1579 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); radeon_ring_write 1582 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, cayman_default_state[i]); radeon_ring_write 1584 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); radeon_ring_write 1585 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); radeon_ring_write 1588 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); radeon_ring_write 1589 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0); radeon_ring_write 1592 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0xc0026f00); radeon_ring_write 1593 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0x00000000); radeon_ring_write 1594 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0x00000000); radeon_ring_write 1595 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0x00000000); radeon_ring_write 1598 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0xc0036f00); radeon_ring_write 1599 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0x00000bc4); radeon_ring_write 1600 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0xffffffff); radeon_ring_write 1601 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0xffffffff); radeon_ring_write 1602 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0xffffffff); radeon_ring_write 1604 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0xc0026900); radeon_ring_write 1605 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0x00000316); radeon_ring_write 1606 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ radeon_ring_write 1607 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0x00000010); /* */ radeon_ring_write 2696 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0)); radeon_ring_write 2697 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, pd_addr >> 12); radeon_ring_write 2700 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); radeon_ring_write 2701 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0x1); radeon_ring_write 2704 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); radeon_ring_write 2705 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 1 << vm_id); radeon_ring_write 2708 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); radeon_ring_write 2709 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ radeon_ring_write 2711 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); radeon_ring_write 2712 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0); radeon_ring_write 2713 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0); /* ref */ radeon_ring_write 2714 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0); /* mask */ radeon_ring_write 2715 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0x20); /* poll interval */ radeon_ring_write 2718 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); radeon_ring_write 2719 drivers/gpu/drm/radeon/ni.c radeon_ring_write(ring, 0x0); radeon_ring_write 133 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); radeon_ring_write 134 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); radeon_ring_write 135 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); radeon_ring_write 136 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, next_rptr); radeon_ring_write 143 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); radeon_ring_write 144 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vm_id, 0)); radeon_ring_write 145 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); radeon_ring_write 146 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); radeon_ring_write 452 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0)); radeon_ring_write 453 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2)); radeon_ring_write 454 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, pd_addr >> 12); radeon_ring_write 457 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0)); radeon_ring_write 458 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); radeon_ring_write 459 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, 1); radeon_ring_write 462 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0)); radeon_ring_write 463 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2)); radeon_ring_write 464 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, 1 << vm_id); radeon_ring_write 467 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, DMA_SRBM_READ_PACKET); radeon_ring_write 468 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, (0xff << 20) | (VM_INVALIDATE_REQUEST >> 2)); radeon_ring_write 469 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, 0); /* mask */ radeon_ring_write 470 drivers/gpu/drm/radeon/ni_dma.c radeon_ring_write(ring, 0); /* value */ radeon_ring_write 849 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); radeon_ring_write 850 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, rdev->config.r100.hdp_cntl | radeon_ring_write 852 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); radeon_ring_write 853 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, rdev->config.r100.hdp_cntl); radeon_ring_write 865 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); radeon_ring_write 866 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); radeon_ring_write 867 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); radeon_ring_write 868 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); radeon_ring_write 870 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); radeon_ring_write 871 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); radeon_ring_write 874 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); radeon_ring_write 875 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, fence->seq); radeon_ring_write 876 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); radeon_ring_write 877 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, RADEON_SW_INT_FIRE); radeon_ring_write 929 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); radeon_ring_write 930 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, radeon_ring_write 942 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); radeon_ring_write 943 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); radeon_ring_write 944 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); radeon_ring_write 945 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, 0); radeon_ring_write 946 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); radeon_ring_write 947 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, num_gpu_pages); radeon_ring_write 948 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, num_gpu_pages); radeon_ring_write 949 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); radeon_ring_write 951 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); radeon_ring_write 952 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); radeon_ring_write 953 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); radeon_ring_write 954 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, radeon_ring_write 990 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); radeon_ring_write 991 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, radeon_ring_write 3670 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(scratch, 0)); radeon_ring_write 3671 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, 0xDEADBEEF); radeon_ring_write 3697 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); radeon_ring_write 3698 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, next_rptr); radeon_ring_write 3701 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); radeon_ring_write 3702 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, ib->gpu_addr); radeon_ring_write 3703 drivers/gpu/drm/radeon/r100.c radeon_ring_write(ring, ib->length_dw); radeon_ring_write 105 drivers/gpu/drm/radeon/r200.c radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); radeon_ring_write 106 drivers/gpu/drm/radeon/r200.c radeon_ring_write(ring, (1 << 16)); radeon_ring_write 113 drivers/gpu/drm/radeon/r200.c radeon_ring_write(ring, PACKET0(0x720, 2)); radeon_ring_write 114 drivers/gpu/drm/radeon/r200.c radeon_ring_write(ring, src_offset); radeon_ring_write 115 drivers/gpu/drm/radeon/r200.c radeon_ring_write(ring, dst_offset); radeon_ring_write 116 drivers/gpu/drm/radeon/r200.c radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30)); radeon_ring_write 120 drivers/gpu/drm/radeon/r200.c radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); radeon_ring_write 121 drivers/gpu/drm/radeon/r200.c radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE); radeon_ring_write 222 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); radeon_ring_write 223 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, 0); radeon_ring_write 224 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); radeon_ring_write 225 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, 0); radeon_ring_write 227 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); radeon_ring_write 228 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, R300_RB3D_DC_FLUSH); radeon_ring_write 229 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); radeon_ring_write 230 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, R300_ZC_FLUSH); radeon_ring_write 232 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); radeon_ring_write 233 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN | radeon_ring_write 236 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); radeon_ring_write 237 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, rdev->config.r300.hdp_cntl | radeon_ring_write 239 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); radeon_ring_write 240 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, rdev->config.r300.hdp_cntl); radeon_ring_write 242 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); radeon_ring_write 243 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, fence->seq); radeon_ring_write 244 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); radeon_ring_write 245 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, RADEON_SW_INT_FIRE); radeon_ring_write 275 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); radeon_ring_write 276 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, radeon_ring_write 281 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0)); radeon_ring_write 282 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, gb_tile_config); radeon_ring_write 283 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); radeon_ring_write 284 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, radeon_ring_write 287 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); radeon_ring_write 288 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); radeon_ring_write 289 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0)); radeon_ring_write 290 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, 0); radeon_ring_write 291 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0)); radeon_ring_write 292 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, 0); radeon_ring_write 293 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); radeon_ring_write 294 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); radeon_ring_write 295 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); radeon_ring_write 296 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); radeon_ring_write 297 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); radeon_ring_write 298 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, radeon_ring_write 301 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0)); radeon_ring_write 302 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, 0); radeon_ring_write 303 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); radeon_ring_write 304 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); radeon_ring_write 305 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); radeon_ring_write 306 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); radeon_ring_write 307 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0)); radeon_ring_write 308 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, radeon_ring_write 317 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0)); radeon_ring_write 318 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, radeon_ring_write 326 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0)); radeon_ring_write 327 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); radeon_ring_write 328 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0)); radeon_ring_write 329 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, radeon_ring_write 331 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0)); radeon_ring_write 332 drivers/gpu/drm/radeon/r300.c radeon_ring_write(ring, radeon_ring_write 225 drivers/gpu/drm/radeon/r420.c radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); radeon_ring_write 226 drivers/gpu/drm/radeon/r420.c radeon_ring_write(ring, rdev->config.r300.resync_scratch); radeon_ring_write 227 drivers/gpu/drm/radeon/r420.c radeon_ring_write(ring, 0xDEADBEEF); radeon_ring_write 241 drivers/gpu/drm/radeon/r420.c radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); radeon_ring_write 242 drivers/gpu/drm/radeon/r420.c radeon_ring_write(ring, R300_RB3D_DC_FINISH); radeon_ring_write 2696 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); radeon_ring_write 2697 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, 0x1); radeon_ring_write 2699 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, 0x0); radeon_ring_write 2700 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); radeon_ring_write 2702 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, 0x3); radeon_ring_write 2703 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); radeon_ring_write 2705 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); radeon_ring_write 2706 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, 0); radeon_ring_write 2707 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, 0); radeon_ring_write 2841 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); radeon_ring_write 2842 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); radeon_ring_write 2843 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, 0xDEADBEEF); radeon_ring_write 2879 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); radeon_ring_write 2880 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, cp_coher_cntl); radeon_ring_write 2881 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, 0xFFFFFFFF); radeon_ring_write 2882 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, 0); radeon_ring_write 2883 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, 10); /* poll interval */ radeon_ring_write 2885 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); radeon_ring_write 2886 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); radeon_ring_write 2887 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, lower_32_bits(addr)); radeon_ring_write 2888 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); radeon_ring_write 2889 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, fence->seq); radeon_ring_write 2890 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, 0); radeon_ring_write 2893 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); radeon_ring_write 2894 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, cp_coher_cntl); radeon_ring_write 2895 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, 0xFFFFFFFF); radeon_ring_write 2896 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, 0); radeon_ring_write 2897 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, 10); /* poll interval */ radeon_ring_write 2898 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); radeon_ring_write 2899 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); radeon_ring_write 2901 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); radeon_ring_write 2902 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); radeon_ring_write 2903 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); radeon_ring_write 2905 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); radeon_ring_write 2906 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); radeon_ring_write 2907 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, fence->seq); radeon_ring_write 2909 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); radeon_ring_write 2910 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, RB_INT_STAT); radeon_ring_write 2936 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); radeon_ring_write 2937 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, lower_32_bits(addr)); radeon_ring_write 2938 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); radeon_ring_write 2943 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); radeon_ring_write 2944 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, 0x0); radeon_ring_write 2990 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); radeon_ring_write 2991 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); radeon_ring_write 2992 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, WAIT_3D_IDLE_bit); radeon_ring_write 3001 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); radeon_ring_write 3002 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, lower_32_bits(src_offset)); radeon_ring_write 3003 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, tmp); radeon_ring_write 3004 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, lower_32_bits(dst_offset)); radeon_ring_write 3005 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); radeon_ring_write 3006 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, cur_size_in_bytes); radeon_ring_write 3010 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); radeon_ring_write 3011 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); radeon_ring_write 3012 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); radeon_ring_write 3376 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); radeon_ring_write 3377 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, ((ring->rptr_save_reg - radeon_ring_write 3379 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, next_rptr); radeon_ring_write 3382 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); radeon_ring_write 3383 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); radeon_ring_write 3384 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); radeon_ring_write 3385 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, next_rptr); radeon_ring_write 3386 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, 0); radeon_ring_write 3389 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); radeon_ring_write 3390 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, radeon_ring_write 3395 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); radeon_ring_write 3396 drivers/gpu/drm/radeon/r600.c radeon_ring_write(ring, ib->length_dw); radeon_ring_write 254 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); radeon_ring_write 255 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, lower_32_bits(gpu_addr)); radeon_ring_write 256 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); radeon_ring_write 257 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, 0xDEADBEEF); radeon_ring_write 294 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0)); radeon_ring_write 295 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, addr & 0xfffffffc); radeon_ring_write 296 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); radeon_ring_write 297 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, lower_32_bits(fence->seq)); radeon_ring_write 299 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0)); radeon_ring_write 321 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0)); radeon_ring_write 322 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, addr & 0xfffffffc); radeon_ring_write 323 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, upper_32_bits(addr) & 0xff); radeon_ring_write 414 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); radeon_ring_write 415 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); radeon_ring_write 416 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); radeon_ring_write 417 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, next_rptr); radeon_ring_write 424 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); radeon_ring_write 425 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0)); radeon_ring_write 426 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); radeon_ring_write 427 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); radeon_ring_write 476 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); radeon_ring_write 477 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, dst_offset & 0xfffffffc); radeon_ring_write 478 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, src_offset & 0xfffffffc); radeon_ring_write 479 drivers/gpu/drm/radeon/r600_dma.c radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | radeon_ring_write 178 drivers/gpu/drm/radeon/radeon_ring.c radeon_ring_write(ring, ring->nop); radeon_ring_write 359 drivers/gpu/drm/radeon/radeon_ring.c radeon_ring_write(ring, data[i]); radeon_ring_write 702 drivers/gpu/drm/radeon/radeon_vce.c radeon_ring_write(ring, cpu_to_le32(VCE_CMD_SEMAPHORE)); radeon_ring_write 703 drivers/gpu/drm/radeon/radeon_vce.c radeon_ring_write(ring, cpu_to_le32((addr >> 3) & 0x000FFFFF)); radeon_ring_write 704 drivers/gpu/drm/radeon/radeon_vce.c radeon_ring_write(ring, cpu_to_le32((addr >> 23) & 0x000FFFFF)); radeon_ring_write 705 drivers/gpu/drm/radeon/radeon_vce.c radeon_ring_write(ring, cpu_to_le32(0x01003000 | (emit_wait ? 1 : 0))); radeon_ring_write 707 drivers/gpu/drm/radeon/radeon_vce.c radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END)); radeon_ring_write 722 drivers/gpu/drm/radeon/radeon_vce.c radeon_ring_write(ring, cpu_to_le32(VCE_CMD_IB)); radeon_ring_write 723 drivers/gpu/drm/radeon/radeon_vce.c radeon_ring_write(ring, cpu_to_le32(ib->gpu_addr)); radeon_ring_write 724 drivers/gpu/drm/radeon/radeon_vce.c radeon_ring_write(ring, cpu_to_le32(upper_32_bits(ib->gpu_addr))); radeon_ring_write 725 drivers/gpu/drm/radeon/radeon_vce.c radeon_ring_write(ring, cpu_to_le32(ib->length_dw)); radeon_ring_write 741 drivers/gpu/drm/radeon/radeon_vce.c radeon_ring_write(ring, cpu_to_le32(VCE_CMD_FENCE)); radeon_ring_write 742 drivers/gpu/drm/radeon/radeon_vce.c radeon_ring_write(ring, cpu_to_le32(addr)); radeon_ring_write 743 drivers/gpu/drm/radeon/radeon_vce.c radeon_ring_write(ring, cpu_to_le32(upper_32_bits(addr))); radeon_ring_write 744 drivers/gpu/drm/radeon/radeon_vce.c radeon_ring_write(ring, cpu_to_le32(fence->seq)); radeon_ring_write 745 drivers/gpu/drm/radeon/radeon_vce.c radeon_ring_write(ring, cpu_to_le32(VCE_CMD_TRAP)); radeon_ring_write 746 drivers/gpu/drm/radeon/radeon_vce.c radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END)); radeon_ring_write 768 drivers/gpu/drm/radeon/radeon_vce.c radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END)); radeon_ring_write 75 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); radeon_ring_write 76 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, radeon_ring_write 81 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); radeon_ring_write 82 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); radeon_ring_write 83 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); radeon_ring_write 84 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); radeon_ring_write 85 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); radeon_ring_write 86 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, 0); radeon_ring_write 87 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); radeon_ring_write 88 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, 0); radeon_ring_write 89 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); radeon_ring_write 90 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1); radeon_ring_write 91 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); radeon_ring_write 92 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, 0); radeon_ring_write 93 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); radeon_ring_write 94 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); radeon_ring_write 95 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); radeon_ring_write 96 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); radeon_ring_write 97 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); radeon_ring_write 98 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); radeon_ring_write 99 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)); radeon_ring_write 100 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, 0); radeon_ring_write 101 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); radeon_ring_write 102 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE); radeon_ring_write 103 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); radeon_ring_write 104 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, ZC_FLUSH | ZC_FREE); radeon_ring_write 105 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)); radeon_ring_write 106 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, radeon_ring_write 115 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)); radeon_ring_write 116 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, radeon_ring_write 124 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)); radeon_ring_write 125 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); radeon_ring_write 126 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)); radeon_ring_write 127 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); radeon_ring_write 128 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)); radeon_ring_write 129 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); radeon_ring_write 130 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, PACKET0(0x20C8, 0)); radeon_ring_write 131 drivers/gpu/drm/radeon/rv515.c radeon_ring_write(ring, 0); radeon_ring_write 74 drivers/gpu/drm/radeon/rv770_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); radeon_ring_write 75 drivers/gpu/drm/radeon/rv770_dma.c radeon_ring_write(ring, dst_offset & 0xfffffffc); radeon_ring_write 76 drivers/gpu/drm/radeon/rv770_dma.c radeon_ring_write(ring, src_offset & 0xfffffffc); radeon_ring_write 77 drivers/gpu/drm/radeon/rv770_dma.c radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); radeon_ring_write 78 drivers/gpu/drm/radeon/rv770_dma.c radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); radeon_ring_write 3381 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); radeon_ring_write 3382 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); radeon_ring_write 3383 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0); radeon_ring_write 3384 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); radeon_ring_write 3385 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | radeon_ring_write 3389 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0xFFFFFFFF); radeon_ring_write 3390 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0); radeon_ring_write 3391 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 10); /* poll interval */ radeon_ring_write 3393 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); radeon_ring_write 3394 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); radeon_ring_write 3395 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, lower_32_bits(addr)); radeon_ring_write 3396 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); radeon_ring_write 3397 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, fence->seq); radeon_ring_write 3398 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0); radeon_ring_write 3412 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); radeon_ring_write 3413 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0); radeon_ring_write 3420 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); radeon_ring_write 3421 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, ((ring->rptr_save_reg - radeon_ring_write 3423 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, next_rptr); radeon_ring_write 3426 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); radeon_ring_write 3427 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, (1 << 8)); radeon_ring_write 3428 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); radeon_ring_write 3429 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); radeon_ring_write 3430 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, next_rptr); radeon_ring_write 3436 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, header); radeon_ring_write 3437 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, radeon_ring_write 3442 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); radeon_ring_write 3443 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, ib->length_dw | (vm_id << 24)); radeon_ring_write 3447 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); radeon_ring_write 3448 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); radeon_ring_write 3449 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, vm_id); radeon_ring_write 3450 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); radeon_ring_write 3451 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | radeon_ring_write 3455 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0xFFFFFFFF); radeon_ring_write 3456 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0); radeon_ring_write 3457 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 10); /* poll interval */ radeon_ring_write 3572 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); radeon_ring_write 3573 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0x1); radeon_ring_write 3574 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0x0); radeon_ring_write 3575 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1); radeon_ring_write 3576 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); radeon_ring_write 3577 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0); radeon_ring_write 3578 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0); radeon_ring_write 3581 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); radeon_ring_write 3582 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); radeon_ring_write 3583 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0xc000); radeon_ring_write 3584 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0xe000); radeon_ring_write 3596 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); radeon_ring_write 3597 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); radeon_ring_write 3600 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, si_default_state[i]); radeon_ring_write 3602 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); radeon_ring_write 3603 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); radeon_ring_write 3606 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); radeon_ring_write 3607 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0); radeon_ring_write 3609 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); radeon_ring_write 3610 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0x00000316); radeon_ring_write 3611 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ radeon_ring_write 3612 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ radeon_ring_write 3621 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); radeon_ring_write 3622 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0); radeon_ring_write 5080 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); radeon_ring_write 5081 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | radeon_ring_write 5085 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, radeon_ring_write 5088 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, radeon_ring_write 5091 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0); radeon_ring_write 5092 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, pd_addr >> 12); radeon_ring_write 5095 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); radeon_ring_write 5096 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | radeon_ring_write 5098 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); radeon_ring_write 5099 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0); radeon_ring_write 5100 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0x1); radeon_ring_write 5103 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); radeon_ring_write 5104 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | radeon_ring_write 5106 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); radeon_ring_write 5107 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0); radeon_ring_write 5108 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 1 << vm_id); radeon_ring_write 5111 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); radeon_ring_write 5112 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ radeon_ring_write 5114 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); radeon_ring_write 5115 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0); radeon_ring_write 5116 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0); /* ref */ radeon_ring_write 5117 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0); /* mask */ radeon_ring_write 5118 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0x20); /* poll interval */ radeon_ring_write 5121 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); radeon_ring_write 5122 drivers/gpu/drm/radeon/si.c radeon_ring_write(ring, 0x0); radeon_ring_write 191 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); radeon_ring_write 193 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2)); radeon_ring_write 195 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2)); radeon_ring_write 197 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, pd_addr >> 12); radeon_ring_write 200 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); radeon_ring_write 201 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); radeon_ring_write 202 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, 1); radeon_ring_write 205 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); radeon_ring_write 206 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2)); radeon_ring_write 207 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, 1 << vm_id); radeon_ring_write 210 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0)); radeon_ring_write 211 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, VM_INVALIDATE_REQUEST); radeon_ring_write 212 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, 0xff << 16); /* retry */ radeon_ring_write 213 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, 1 << vm_id); /* mask */ radeon_ring_write 214 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, 0); /* value */ radeon_ring_write 215 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */ radeon_ring_write 263 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes)); radeon_ring_write 264 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, lower_32_bits(dst_offset)); radeon_ring_write 265 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, lower_32_bits(src_offset)); radeon_ring_write 266 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); radeon_ring_write 267 drivers/gpu/drm/radeon/si_dma.c radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); radeon_ring_write 87 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); radeon_ring_write 88 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, addr & 0xffffffff); radeon_ring_write 89 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); radeon_ring_write 90 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, fence->seq); radeon_ring_write 91 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); radeon_ring_write 92 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, 0); radeon_ring_write 94 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); radeon_ring_write 95 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, 0); radeon_ring_write 96 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); radeon_ring_write 97 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, 0); radeon_ring_write 98 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); radeon_ring_write 99 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, 2); radeon_ring_write 187 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, tmp); radeon_ring_write 188 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, 0xFFFFF); radeon_ring_write 191 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, tmp); radeon_ring_write 192 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, 0xFFFFF); radeon_ring_write 195 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, tmp); radeon_ring_write 196 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, 0xFFFFF); radeon_ring_write 199 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0)); radeon_ring_write 200 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, 0x8); radeon_ring_write 202 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0)); radeon_ring_write 203 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, 3); radeon_ring_write 434 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); radeon_ring_write 435 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, 0xDEADBEEF); radeon_ring_write 486 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0)); radeon_ring_write 487 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, ib->gpu_addr); radeon_ring_write 488 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0)); radeon_ring_write 489 drivers/gpu/drm/radeon/uvd_v1_0.c radeon_ring_write(ring, ib->length_dw); radeon_ring_write 45 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); radeon_ring_write 46 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, fence->seq); radeon_ring_write 47 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); radeon_ring_write 48 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, lower_32_bits(addr)); radeon_ring_write 49 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); radeon_ring_write 50 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, upper_32_bits(addr) & 0xff); radeon_ring_write 51 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); radeon_ring_write 52 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, 0); radeon_ring_write 54 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); radeon_ring_write 55 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, 0); radeon_ring_write 56 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); radeon_ring_write 57 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, 0); radeon_ring_write 58 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); radeon_ring_write 59 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, 2); radeon_ring_write 79 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); radeon_ring_write 80 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF); radeon_ring_write 82 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); radeon_ring_write 83 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF); radeon_ring_write 85 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); radeon_ring_write 86 drivers/gpu/drm/radeon/uvd_v2_2.c radeon_ring_write(ring, emit_wait ? 1 : 0); radeon_ring_write 46 drivers/gpu/drm/radeon/uvd_v3_1.c radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); radeon_ring_write 47 drivers/gpu/drm/radeon/uvd_v3_1.c radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF); radeon_ring_write 49 drivers/gpu/drm/radeon/uvd_v3_1.c radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); radeon_ring_write 50 drivers/gpu/drm/radeon/uvd_v3_1.c radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF); radeon_ring_write 52 drivers/gpu/drm/radeon/uvd_v3_1.c radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); radeon_ring_write 53 drivers/gpu/drm/radeon/uvd_v3_1.c radeon_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));