rFPGA0_XCD_RFInterfaceSW  972 drivers/staging/rtl8188eu/hal/phy.c 					      rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB,
rFPGA0_XCD_RFInterfaceSW 1007 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
rFPGA0_XCD_RFInterfaceSW  384 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 	priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
rFPGA0_XCD_RFInterfaceSW  385 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 	priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
rFPGA0_XCD_RFInterfaceSW  560 drivers/staging/rtl8192u/r819xU_phy.c 	priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
rFPGA0_XCD_RFInterfaceSW  562 drivers/staging/rtl8192u/r819xU_phy.c 	priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
rFPGA0_XCD_RFInterfaceSW 1530 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c 		rFPGA0_XCD_RFInterfaceSW,
rFPGA0_XCD_RFInterfaceSW 1574 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c 	PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);