rFPGA0_XA_HSSIParameter2  608 drivers/staging/rtl8188eu/hal/bb_cfg.c 	reg[RF_PATH_A]->rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
rFPGA0_XA_HSSIParameter2   64 drivers/staging/rtl8188eu/hal/phy.c 	tmplong = phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter2, bMaskDWord);
rFPGA0_XA_HSSIParameter2   74 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_XA_HSSIParameter2, bMaskDWord,
rFPGA0_XA_HSSIParameter2 1501 drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c 						rFPGA0_XA_HSSIParameter2,
rFPGA0_XA_HSSIParameter2  422 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 	priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
rFPGA0_XA_HSSIParameter2  622 drivers/staging/rtl8192u/r819xU_phy.c 	priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
rFPGA0_XA_HSSIParameter2  825 drivers/staging/rtl8192u/r819xU_phy.c 						     rFPGA0_XA_HSSIParameter2,
rFPGA0_XA_HSSIParameter2  422 drivers/staging/rtl8712/rtl871x_mp.c 		set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
rFPGA0_XA_HSSIParameter2  429 drivers/staging/rtl8712/rtl871x_mp.c 		set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
rFPGA0_XA_HSSIParameter2  436 drivers/staging/rtl8712/rtl871x_mp.c 		set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
rFPGA0_XA_HSSIParameter2  147 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c 		tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);
rFPGA0_XA_HSSIParameter2  149 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c 		PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));
rFPGA0_XA_HSSIParameter2  156 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c 	tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);
rFPGA0_XA_HSSIParameter2  157 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c 	PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
rFPGA0_XA_HSSIParameter2  158 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c 	PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
rFPGA0_XA_HSSIParameter2  416 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c 	pHalData->PHYRegDef[ODM_RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  /* wire control parameter2 */