rFPGA0_XAB_RFInterfaceSW  584 drivers/staging/rtl8188eu/hal/bb_cfg.c 	reg[RF_PATH_A]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
rFPGA0_XAB_RFInterfaceSW  585 drivers/staging/rtl8188eu/hal/bb_cfg.c 	reg[RF_PATH_B]->rfintfs = rFPGA0_XAB_RFInterfaceSW;
rFPGA0_XAB_RFInterfaceSW  973 drivers/staging/rtl8188eu/hal/phy.c 					      rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
rFPGA0_XAB_RFInterfaceSW 1009 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(10), 0x01);
rFPGA0_XAB_RFInterfaceSW 1010 drivers/staging/rtl8188eu/hal/phy.c 	phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(26), 0x01);
rFPGA0_XAB_RFInterfaceSW  382 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 	priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
rFPGA0_XAB_RFInterfaceSW  383 drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c 	priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
rFPGA0_XAB_RFInterfaceSW  556 drivers/staging/rtl8192u/r819xU_phy.c 	priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
rFPGA0_XAB_RFInterfaceSW  558 drivers/staging/rtl8192u/r819xU_phy.c 	priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
rFPGA0_XAB_RFInterfaceSW 1533 drivers/staging/rtl8723bs/hal/HalPhyRf_8723B.c 		rFPGA0_XAB_RFInterfaceSW,
rFPGA0_XAB_RFInterfaceSW  402 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c 	pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /*  16 LSBs if read 32-bit from 0x870 */
rFPGA0_XAB_RFInterfaceSW  403 drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c 	pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /*  16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */