r4030_write_reg32  153 arch/mips/jazz/irq.c 	r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9);
r4030_write_reg32   84 arch/mips/jazz/jazzdma.c 	r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE,
r4030_write_reg32   86 arch/mips/jazz/jazzdma.c 	r4030_write_reg32(JAZZ_R4030_TRSTBL_LIM, VDMA_PGTBL_SIZE);
r4030_write_reg32   87 arch/mips/jazz/jazzdma.c 	r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0);
r4030_write_reg32  155 arch/mips/jazz/jazzdma.c 	r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0);
r4030_write_reg32  262 arch/mips/jazz/jazzdma.c 	r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0);
r4030_write_reg32  381 arch/mips/jazz/jazzdma.c 	r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),
r4030_write_reg32  389 arch/mips/jazz/jazzdma.c 	r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),
r4030_write_reg32  420 arch/mips/jazz/jazzdma.c 	r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),
r4030_write_reg32  451 arch/mips/jazz/jazzdma.c 		r4030_write_reg32(JAZZ_R4030_CHNL_MODE + (channel << 5),
r4030_write_reg32  460 arch/mips/jazz/jazzdma.c 		r4030_write_reg32(JAZZ_R4030_CHNL_MODE + (channel << 5),
r4030_write_reg32  481 arch/mips/jazz/jazzdma.c 		r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),
r4030_write_reg32  488 arch/mips/jazz/jazzdma.c 		r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),
r4030_write_reg32  512 arch/mips/jazz/jazzdma.c 	r4030_write_reg32(JAZZ_R4030_CHNL_ADDR + (channel << 5), addr);
r4030_write_reg32  526 arch/mips/jazz/jazzdma.c 	r4030_write_reg32(JAZZ_R4030_CHNL_COUNT + (channel << 5), count);