qm                141 drivers/crypto/caam/qi.c static void caam_fq_ern_cb(struct qman_portal *qm, struct qman_fq *fq,
qm                526 drivers/crypto/caam/qi.c static void cgr_cb(struct qman_portal *qm, struct qman_cgr *cgr, int congested)
qm                273 drivers/crypto/hisilicon/qm.c 	int (*get_vft)(struct hisi_qm *qm, u32 *base, u32 *number);
qm                274 drivers/crypto/hisilicon/qm.c 	void (*qm_db)(struct hisi_qm *qm, u16 qn,
qm                276 drivers/crypto/hisilicon/qm.c 	u32 (*get_irq_num)(struct hisi_qm *qm);
qm                277 drivers/crypto/hisilicon/qm.c 	int (*debug_init)(struct hisi_qm *qm);
qm                278 drivers/crypto/hisilicon/qm.c 	void (*hw_error_init)(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,
qm                280 drivers/crypto/hisilicon/qm.c 	pci_ers_result_t (*hw_error_handle)(struct hisi_qm *qm);
qm                319 drivers/crypto/hisilicon/qm.c static int qm_wait_mb_ready(struct hisi_qm *qm)
qm                323 drivers/crypto/hisilicon/qm.c 	return readl_relaxed_poll_timeout(qm->io_base + QM_MB_CMD_SEND_BASE,
qm                329 drivers/crypto/hisilicon/qm.c static void qm_mb_write(struct hisi_qm *qm, const void *src)
qm                331 drivers/crypto/hisilicon/qm.c 	void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE;
qm                344 drivers/crypto/hisilicon/qm.c static int qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
qm                350 drivers/crypto/hisilicon/qm.c 	dev_dbg(&qm->pdev->dev, "QM mailbox request to q%u: %u-%llx\n",
qm                361 drivers/crypto/hisilicon/qm.c 	mutex_lock(&qm->mailbox_lock);
qm                363 drivers/crypto/hisilicon/qm.c 	if (unlikely(qm_wait_mb_ready(qm))) {
qm                365 drivers/crypto/hisilicon/qm.c 		dev_err(&qm->pdev->dev, "QM mailbox is busy to start!\n");
qm                369 drivers/crypto/hisilicon/qm.c 	qm_mb_write(qm, &mailbox);
qm                371 drivers/crypto/hisilicon/qm.c 	if (unlikely(qm_wait_mb_ready(qm))) {
qm                373 drivers/crypto/hisilicon/qm.c 		dev_err(&qm->pdev->dev, "QM mailbox operation timeout!\n");
qm                378 drivers/crypto/hisilicon/qm.c 	mutex_unlock(&qm->mailbox_lock);
qm                383 drivers/crypto/hisilicon/qm.c static void qm_db_v1(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
qm                391 drivers/crypto/hisilicon/qm.c 	writeq(doorbell, qm->io_base + QM_DOORBELL_BASE_V1);
qm                394 drivers/crypto/hisilicon/qm.c static void qm_db_v2(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
qm                410 drivers/crypto/hisilicon/qm.c 	writeq(doorbell, qm->io_base + dbase);
qm                413 drivers/crypto/hisilicon/qm.c static void qm_db(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
qm                415 drivers/crypto/hisilicon/qm.c 	dev_dbg(&qm->pdev->dev, "QM doorbell request: qn=%u, cmd=%u, index=%u\n",
qm                418 drivers/crypto/hisilicon/qm.c 	qm->ops->qm_db(qm, qn, cmd, index, priority);
qm                421 drivers/crypto/hisilicon/qm.c static int qm_dev_mem_reset(struct hisi_qm *qm)
qm                425 drivers/crypto/hisilicon/qm.c 	writel(0x1, qm->io_base + QM_MEM_START_INIT);
qm                426 drivers/crypto/hisilicon/qm.c 	return readl_relaxed_poll_timeout(qm->io_base + QM_MEM_INIT_DONE, val,
qm                430 drivers/crypto/hisilicon/qm.c static u32 qm_get_irq_num_v1(struct hisi_qm *qm)
qm                435 drivers/crypto/hisilicon/qm.c static u32 qm_get_irq_num_v2(struct hisi_qm *qm)
qm                437 drivers/crypto/hisilicon/qm.c 	if (qm->fun_type == QM_HW_PF)
qm                443 drivers/crypto/hisilicon/qm.c static struct hisi_qp *qm_to_hisi_qp(struct hisi_qm *qm, struct qm_eqe *eqe)
qm                447 drivers/crypto/hisilicon/qm.c 	return qm->qp_array[cqn];
qm                460 drivers/crypto/hisilicon/qm.c static void qm_poll_qp(struct hisi_qp *qp, struct hisi_qm *qm)
qm                467 drivers/crypto/hisilicon/qm.c 			qp->req_cb(qp, qp->sqe + qm->sqe_size * cqe->sq_head);
qm                470 drivers/crypto/hisilicon/qm.c 			qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ,
qm                476 drivers/crypto/hisilicon/qm.c 		qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ,
qm                486 drivers/crypto/hisilicon/qm.c 	qm_poll_qp(qp, qp->qm);
qm                491 drivers/crypto/hisilicon/qm.c 	struct hisi_qm *qm = data;
qm                492 drivers/crypto/hisilicon/qm.c 	struct qm_eqe *eqe = qm->eqe + qm->status.eq_head;
qm                496 drivers/crypto/hisilicon/qm.c 	while (QM_EQE_PHASE(eqe) == qm->status.eqc_phase) {
qm                498 drivers/crypto/hisilicon/qm.c 		qp = qm_to_hisi_qp(qm, eqe);
qm                502 drivers/crypto/hisilicon/qm.c 		if (qm->status.eq_head == QM_Q_DEPTH - 1) {
qm                503 drivers/crypto/hisilicon/qm.c 			qm->status.eqc_phase = !qm->status.eqc_phase;
qm                504 drivers/crypto/hisilicon/qm.c 			eqe = qm->eqe;
qm                505 drivers/crypto/hisilicon/qm.c 			qm->status.eq_head = 0;
qm                508 drivers/crypto/hisilicon/qm.c 			qm->status.eq_head++;
qm                513 drivers/crypto/hisilicon/qm.c 			qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
qm                517 drivers/crypto/hisilicon/qm.c 	qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
qm                524 drivers/crypto/hisilicon/qm.c 	struct hisi_qm *qm = data;
qm                526 drivers/crypto/hisilicon/qm.c 	if (readl(qm->io_base + QM_VF_EQ_INT_SOURCE))
qm                529 drivers/crypto/hisilicon/qm.c 	dev_err(&qm->pdev->dev, "invalid int source\n");
qm                530 drivers/crypto/hisilicon/qm.c 	qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
qm                537 drivers/crypto/hisilicon/qm.c 	struct hisi_qm *qm = data;
qm                538 drivers/crypto/hisilicon/qm.c 	struct qm_aeqe *aeqe = qm->aeqe + qm->status.aeq_head;
qm                541 drivers/crypto/hisilicon/qm.c 	if (!readl(qm->io_base + QM_VF_AEQ_INT_SOURCE))
qm                544 drivers/crypto/hisilicon/qm.c 	while (QM_AEQE_PHASE(aeqe) == qm->status.aeqc_phase) {
qm                547 drivers/crypto/hisilicon/qm.c 			dev_err(&qm->pdev->dev, "%s overflow\n",
qm                550 drivers/crypto/hisilicon/qm.c 			dev_err(&qm->pdev->dev, "unknown error type %d\n",
qm                553 drivers/crypto/hisilicon/qm.c 		if (qm->status.aeq_head == QM_Q_DEPTH - 1) {
qm                554 drivers/crypto/hisilicon/qm.c 			qm->status.aeqc_phase = !qm->status.aeqc_phase;
qm                555 drivers/crypto/hisilicon/qm.c 			aeqe = qm->aeqe;
qm                556 drivers/crypto/hisilicon/qm.c 			qm->status.aeq_head = 0;
qm                559 drivers/crypto/hisilicon/qm.c 			qm->status.aeq_head++;
qm                562 drivers/crypto/hisilicon/qm.c 		qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0);
qm                571 drivers/crypto/hisilicon/qm.c 	struct hisi_qm *qm = data;
qm                572 drivers/crypto/hisilicon/qm.c 	struct device *dev = &qm->pdev->dev;
qm                576 drivers/crypto/hisilicon/qm.c 	tmp = readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
qm                577 drivers/crypto/hisilicon/qm.c 	error_status = qm->msi_mask & tmp;
qm                588 drivers/crypto/hisilicon/qm.c 	writel(error_status, qm->io_base + QM_ABNORMAL_INT_SOURCE);
qm                593 drivers/crypto/hisilicon/qm.c static int qm_irq_register(struct hisi_qm *qm)
qm                595 drivers/crypto/hisilicon/qm.c 	struct pci_dev *pdev = qm->pdev;
qm                599 drivers/crypto/hisilicon/qm.c 			  qm_irq, IRQF_SHARED, qm->dev_name, qm);
qm                603 drivers/crypto/hisilicon/qm.c 	if (qm->ver == QM_HW_V2) {
qm                605 drivers/crypto/hisilicon/qm.c 				  qm_aeq_irq, IRQF_SHARED, qm->dev_name, qm);
qm                609 drivers/crypto/hisilicon/qm.c 		if (qm->fun_type == QM_HW_PF) {
qm                613 drivers/crypto/hisilicon/qm.c 					  qm->dev_name, qm);
qm                622 drivers/crypto/hisilicon/qm.c 	free_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR), qm);
qm                624 drivers/crypto/hisilicon/qm.c 	free_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR), qm);
qm                628 drivers/crypto/hisilicon/qm.c static void qm_irq_unregister(struct hisi_qm *qm)
qm                630 drivers/crypto/hisilicon/qm.c 	struct pci_dev *pdev = qm->pdev;
qm                632 drivers/crypto/hisilicon/qm.c 	free_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR), qm);
qm                634 drivers/crypto/hisilicon/qm.c 	if (qm->ver == QM_HW_V2) {
qm                635 drivers/crypto/hisilicon/qm.c 		free_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR), qm);
qm                637 drivers/crypto/hisilicon/qm.c 		if (qm->fun_type == QM_HW_PF)
qm                639 drivers/crypto/hisilicon/qm.c 				 QM_ABNORMAL_EVENT_IRQ_VECTOR), qm);
qm                653 drivers/crypto/hisilicon/qm.c static void qm_vft_data_cfg(struct hisi_qm *qm, enum vft_type type, u32 base,
qm                661 drivers/crypto/hisilicon/qm.c 			switch (qm->ver) {
qm                679 drivers/crypto/hisilicon/qm.c 			switch (qm->ver) {
qm                696 drivers/crypto/hisilicon/qm.c 	writel(lower_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_L);
qm                697 drivers/crypto/hisilicon/qm.c 	writel(upper_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_H);
qm                700 drivers/crypto/hisilicon/qm.c static int qm_set_vft_common(struct hisi_qm *qm, enum vft_type type,
qm                706 drivers/crypto/hisilicon/qm.c 	ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
qm                711 drivers/crypto/hisilicon/qm.c 	writel(0x0, qm->io_base + QM_VFT_CFG_OP_WR);
qm                712 drivers/crypto/hisilicon/qm.c 	writel(type, qm->io_base + QM_VFT_CFG_TYPE);
qm                713 drivers/crypto/hisilicon/qm.c 	writel(fun_num, qm->io_base + QM_VFT_CFG);
qm                715 drivers/crypto/hisilicon/qm.c 	qm_vft_data_cfg(qm, type, base, number);
qm                717 drivers/crypto/hisilicon/qm.c 	writel(0x0, qm->io_base + QM_VFT_CFG_RDY);
qm                718 drivers/crypto/hisilicon/qm.c 	writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);
qm                720 drivers/crypto/hisilicon/qm.c 	return readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
qm                725 drivers/crypto/hisilicon/qm.c static int qm_set_sqc_cqc_vft(struct hisi_qm *qm, u32 fun_num, u32 base,
qm                731 drivers/crypto/hisilicon/qm.c 		ret = qm_set_vft_common(qm, i, fun_num, base, number);
qm                739 drivers/crypto/hisilicon/qm.c static int qm_get_vft_v2(struct hisi_qm *qm, u32 *base, u32 *number)
qm                744 drivers/crypto/hisilicon/qm.c 	ret = qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1);
qm                748 drivers/crypto/hisilicon/qm.c 	sqc_vft = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
qm                749 drivers/crypto/hisilicon/qm.c 		  ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32);
qm                766 drivers/crypto/hisilicon/qm.c 	struct hisi_qm *qm = file_to_qm(file);
qm                768 drivers/crypto/hisilicon/qm.c 	return readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) >> QM_DFX_QN_SHIFT;
qm                773 drivers/crypto/hisilicon/qm.c 	struct hisi_qm *qm = file_to_qm(file);
qm                776 drivers/crypto/hisilicon/qm.c 	if (val >= qm->debug.curr_qm_qp_num)
qm                780 drivers/crypto/hisilicon/qm.c 	      (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_FUN_MASK);
qm                781 drivers/crypto/hisilicon/qm.c 	writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
qm                784 drivers/crypto/hisilicon/qm.c 	      (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_FUN_MASK);
qm                785 drivers/crypto/hisilicon/qm.c 	writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
qm                792 drivers/crypto/hisilicon/qm.c 	struct hisi_qm *qm = file_to_qm(file);
qm                794 drivers/crypto/hisilicon/qm.c 	return readl(qm->io_base + QM_DFX_CNT_CLR_CE);
qm                800 drivers/crypto/hisilicon/qm.c 	struct hisi_qm *qm = file_to_qm(file);
qm                805 drivers/crypto/hisilicon/qm.c 	writel(rd_clr_ctrl, qm->io_base + QM_DFX_CNT_CLR_CE);
qm                934 drivers/crypto/hisilicon/qm.c 	struct hisi_qm *qm = s->private;
qm                938 drivers/crypto/hisilicon/qm.c 	if (qm->fun_type == QM_HW_PF)
qm                944 drivers/crypto/hisilicon/qm.c 		val = readl(qm->io_base + regs->reg_offset);
qm                964 drivers/crypto/hisilicon/qm.c static int qm_create_debugfs_file(struct hisi_qm *qm, enum qm_debug_file index)
qm                966 drivers/crypto/hisilicon/qm.c 	struct dentry *qm_d = qm->debug.qm_d, *tmp;
qm                967 drivers/crypto/hisilicon/qm.c 	struct debugfs_file *file = qm->debug.files + index;
qm                976 drivers/crypto/hisilicon/qm.c 	file->debug = &qm->debug;
qm                981 drivers/crypto/hisilicon/qm.c static void qm_hw_error_init_v1(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,
qm                984 drivers/crypto/hisilicon/qm.c 	dev_info(&qm->pdev->dev,
qm                985 drivers/crypto/hisilicon/qm.c 		 "QM v%d does not support hw error handle\n", qm->ver);
qm                987 drivers/crypto/hisilicon/qm.c 	writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK);
qm                990 drivers/crypto/hisilicon/qm.c static void qm_hw_error_init_v2(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,
qm                996 drivers/crypto/hisilicon/qm.c 	qm->error_mask = ce | nfe | fe;
qm                997 drivers/crypto/hisilicon/qm.c 	qm->msi_mask = msi;
qm               1000 drivers/crypto/hisilicon/qm.c 	writel(ce, qm->io_base + QM_RAS_CE_ENABLE);
qm               1001 drivers/crypto/hisilicon/qm.c 	writel(QM_RAS_CE_TIMES_PER_IRQ, qm->io_base + QM_RAS_CE_THRESHOLD);
qm               1002 drivers/crypto/hisilicon/qm.c 	writel(nfe, qm->io_base + QM_RAS_NFE_ENABLE);
qm               1003 drivers/crypto/hisilicon/qm.c 	writel(fe, qm->io_base + QM_RAS_FE_ENABLE);
qm               1006 drivers/crypto/hisilicon/qm.c 	writel(msi, qm->io_base + QM_RAS_MSI_INT_SEL);
qm               1008 drivers/crypto/hisilicon/qm.c 	irq_unmask &= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
qm               1009 drivers/crypto/hisilicon/qm.c 	writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK);
qm               1012 drivers/crypto/hisilicon/qm.c static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status)
qm               1015 drivers/crypto/hisilicon/qm.c 	struct device *dev = &qm->pdev->dev;
qm               1024 drivers/crypto/hisilicon/qm.c 				reg_val = readl(qm->io_base +
qm               1034 drivers/crypto/hisilicon/qm.c 				reg_val = readl(qm->io_base +
qm               1052 drivers/crypto/hisilicon/qm.c static pci_ers_result_t qm_hw_error_handle_v2(struct hisi_qm *qm)
qm               1057 drivers/crypto/hisilicon/qm.c 	tmp = readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
qm               1058 drivers/crypto/hisilicon/qm.c 	error_status = qm->error_mask & tmp;
qm               1061 drivers/crypto/hisilicon/qm.c 		qm_log_hw_error(qm, error_status);
qm               1064 drivers/crypto/hisilicon/qm.c 		writel(error_status, qm->io_base + QM_ABNORMAL_INT_SOURCE);
qm               1094 drivers/crypto/hisilicon/qm.c 	return qp->sqe + sq_tail * qp->qm->sqe_size;
qm               1105 drivers/crypto/hisilicon/qm.c struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type)
qm               1107 drivers/crypto/hisilicon/qm.c 	struct device *dev = &qm->pdev->dev;
qm               1115 drivers/crypto/hisilicon/qm.c 	write_lock(&qm->qps_lock);
qm               1117 drivers/crypto/hisilicon/qm.c 	qp_id = find_first_zero_bit(qm->qp_bitmap, qm->qp_num);
qm               1118 drivers/crypto/hisilicon/qm.c 	if (qp_id >= qm->qp_num) {
qm               1119 drivers/crypto/hisilicon/qm.c 		write_unlock(&qm->qps_lock);
qm               1120 drivers/crypto/hisilicon/qm.c 		dev_info(&qm->pdev->dev, "QM all queues are busy!\n");
qm               1124 drivers/crypto/hisilicon/qm.c 	set_bit(qp_id, qm->qp_bitmap);
qm               1125 drivers/crypto/hisilicon/qm.c 	qm->qp_array[qp_id] = qp;
qm               1127 drivers/crypto/hisilicon/qm.c 	write_unlock(&qm->qps_lock);
qm               1129 drivers/crypto/hisilicon/qm.c 	qp->qm = qm;
qm               1131 drivers/crypto/hisilicon/qm.c 	if (qm->use_dma_api) {
qm               1132 drivers/crypto/hisilicon/qm.c 		qp->qdma.size = qm->sqe_size * QM_Q_DEPTH +
qm               1158 drivers/crypto/hisilicon/qm.c 	if (qm->use_dma_api)
qm               1162 drivers/crypto/hisilicon/qm.c 	write_lock(&qm->qps_lock);
qm               1163 drivers/crypto/hisilicon/qm.c 	qm->qp_array[qp_id] = NULL;
qm               1164 drivers/crypto/hisilicon/qm.c 	clear_bit(qp_id, qm->qp_bitmap);
qm               1165 drivers/crypto/hisilicon/qm.c 	write_unlock(&qm->qps_lock);
qm               1180 drivers/crypto/hisilicon/qm.c 	struct hisi_qm *qm = qp->qm;
qm               1182 drivers/crypto/hisilicon/qm.c 	struct device *dev = &qm->pdev->dev;
qm               1184 drivers/crypto/hisilicon/qm.c 	if (qm->use_dma_api && qdma->va)
qm               1187 drivers/crypto/hisilicon/qm.c 	write_lock(&qm->qps_lock);
qm               1188 drivers/crypto/hisilicon/qm.c 	qm->qp_array[qp->qp_id] = NULL;
qm               1189 drivers/crypto/hisilicon/qm.c 	clear_bit(qp->qp_id, qm->qp_bitmap);
qm               1190 drivers/crypto/hisilicon/qm.c 	write_unlock(&qm->qps_lock);
qm               1198 drivers/crypto/hisilicon/qm.c 	struct hisi_qm *qm = qp->qm;
qm               1199 drivers/crypto/hisilicon/qm.c 	struct device *dev = &qm->pdev->dev;
qm               1200 drivers/crypto/hisilicon/qm.c 	enum qm_hw_ver ver = qm->ver;
qm               1221 drivers/crypto/hisilicon/qm.c 		sqc->dw3 = QM_MK_SQC_DW3_V1(0, 0, 0, qm->sqe_size);
qm               1224 drivers/crypto/hisilicon/qm.c 		sqc->dw3 = QM_MK_SQC_DW3_V2(qm->sqe_size);
qm               1230 drivers/crypto/hisilicon/qm.c 	ret = qm_mb(qm, QM_MB_CMD_SQC, sqc_dma, qp_id, 0);
qm               1256 drivers/crypto/hisilicon/qm.c 	ret = qm_mb(qm, QM_MB_CMD_CQC, cqc_dma, qp_id, 0);
qm               1273 drivers/crypto/hisilicon/qm.c 	struct hisi_qm *qm = qp->qm;
qm               1274 drivers/crypto/hisilicon/qm.c 	struct device *dev = &qm->pdev->dev;
qm               1275 drivers/crypto/hisilicon/qm.c 	enum qm_hw_ver ver = qm->ver;
qm               1298 drivers/crypto/hisilicon/qm.c 	QP_INIT_BUF(qp, sqe, qm->sqe_size * QM_Q_DEPTH);
qm               1325 drivers/crypto/hisilicon/qm.c 	struct device *dev = &qp->qm->pdev->dev;
qm               1365 drivers/crypto/hisilicon/qm.c 		dev_info(&qp->qm->pdev->dev, "QP is stopped or resetting\n");
qm               1372 drivers/crypto/hisilicon/qm.c 	memcpy(sqe, msg, qp->qm->sqe_size);
qm               1374 drivers/crypto/hisilicon/qm.c 	qm_db(qp->qm, qp->qp_id, QM_DOORBELL_CMD_SQ, sq_tail_next, 0);
qm               1382 drivers/crypto/hisilicon/qm.c static void hisi_qm_cache_wb(struct hisi_qm *qm)
qm               1386 drivers/crypto/hisilicon/qm.c 	if (qm->ver == QM_HW_V2) {
qm               1387 drivers/crypto/hisilicon/qm.c 		writel(0x1, qm->io_base + QM_CACHE_WB_START);
qm               1388 drivers/crypto/hisilicon/qm.c 		if (readl_relaxed_poll_timeout(qm->io_base + QM_CACHE_WB_DONE,
qm               1390 drivers/crypto/hisilicon/qm.c 			dev_err(&qm->pdev->dev, "QM writeback sqc cache fail!\n");
qm               1400 drivers/crypto/hisilicon/qm.c int hisi_qm_init(struct hisi_qm *qm)
qm               1402 drivers/crypto/hisilicon/qm.c 	struct pci_dev *pdev = qm->pdev;
qm               1407 drivers/crypto/hisilicon/qm.c 	switch (qm->ver) {
qm               1409 drivers/crypto/hisilicon/qm.c 		qm->ops = &qm_hw_ops_v1;
qm               1412 drivers/crypto/hisilicon/qm.c 		qm->ops = &qm_hw_ops_v2;
qm               1424 drivers/crypto/hisilicon/qm.c 	ret = pci_request_mem_regions(pdev, qm->dev_name);
qm               1430 drivers/crypto/hisilicon/qm.c 	qm->io_base = ioremap(pci_resource_start(pdev, PCI_BAR_2),
qm               1431 drivers/crypto/hisilicon/qm.c 			      pci_resource_len(qm->pdev, PCI_BAR_2));
qm               1432 drivers/crypto/hisilicon/qm.c 	if (!qm->io_base) {
qm               1442 drivers/crypto/hisilicon/qm.c 	if (!qm->ops->get_irq_num) {
qm               1446 drivers/crypto/hisilicon/qm.c 	num_vec = qm->ops->get_irq_num(qm);
qm               1453 drivers/crypto/hisilicon/qm.c 	ret = qm_irq_register(qm);
qm               1457 drivers/crypto/hisilicon/qm.c 	mutex_init(&qm->mailbox_lock);
qm               1458 drivers/crypto/hisilicon/qm.c 	rwlock_init(&qm->qps_lock);
qm               1461 drivers/crypto/hisilicon/qm.c 		qm->use_dma_api ? "dma api" : "iommu api");
qm               1468 drivers/crypto/hisilicon/qm.c 	iounmap(qm->io_base);
qm               1484 drivers/crypto/hisilicon/qm.c void hisi_qm_uninit(struct hisi_qm *qm)
qm               1486 drivers/crypto/hisilicon/qm.c 	struct pci_dev *pdev = qm->pdev;
qm               1489 drivers/crypto/hisilicon/qm.c 	if (qm->use_dma_api && qm->qdma.va) {
qm               1490 drivers/crypto/hisilicon/qm.c 		hisi_qm_cache_wb(qm);
qm               1491 drivers/crypto/hisilicon/qm.c 		dma_free_coherent(dev, qm->qdma.size,
qm               1492 drivers/crypto/hisilicon/qm.c 				  qm->qdma.va, qm->qdma.dma);
qm               1493 drivers/crypto/hisilicon/qm.c 		memset(&qm->qdma, 0, sizeof(qm->qdma));
qm               1496 drivers/crypto/hisilicon/qm.c 	qm_irq_unregister(qm);
qm               1498 drivers/crypto/hisilicon/qm.c 	iounmap(qm->io_base);
qm               1516 drivers/crypto/hisilicon/qm.c int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number)
qm               1521 drivers/crypto/hisilicon/qm.c 	if (!qm->ops->get_vft) {
qm               1522 drivers/crypto/hisilicon/qm.c 		dev_err(&qm->pdev->dev, "Don't support vft read!\n");
qm               1526 drivers/crypto/hisilicon/qm.c 	return qm->ops->get_vft(qm, base, number);
qm               1544 drivers/crypto/hisilicon/qm.c int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base,
qm               1547 drivers/crypto/hisilicon/qm.c 	u32 max_q_num = qm->ctrl_qp_num;
qm               1553 drivers/crypto/hisilicon/qm.c 	return qm_set_sqc_cqc_vft(qm, fun_num, base, number);
qm               1557 drivers/crypto/hisilicon/qm.c static void qm_init_eq_aeq_status(struct hisi_qm *qm)
qm               1559 drivers/crypto/hisilicon/qm.c 	struct hisi_qm_status *status = &qm->status;
qm               1567 drivers/crypto/hisilicon/qm.c static int qm_eq_ctx_cfg(struct hisi_qm *qm)
qm               1569 drivers/crypto/hisilicon/qm.c 	struct device *dev = &qm->pdev->dev;
qm               1576 drivers/crypto/hisilicon/qm.c 	qm_init_eq_aeq_status(qm);
qm               1588 drivers/crypto/hisilicon/qm.c 	eqc->base_l = lower_32_bits(qm->eqe_dma);
qm               1589 drivers/crypto/hisilicon/qm.c 	eqc->base_h = upper_32_bits(qm->eqe_dma);
qm               1590 drivers/crypto/hisilicon/qm.c 	if (qm->ver == QM_HW_V1)
qm               1593 drivers/crypto/hisilicon/qm.c 	ret = qm_mb(qm, QM_MB_CMD_EQC, eqc_dma, 0, 0);
qm               1609 drivers/crypto/hisilicon/qm.c 	aeqc->base_l = lower_32_bits(qm->aeqe_dma);
qm               1610 drivers/crypto/hisilicon/qm.c 	aeqc->base_h = upper_32_bits(qm->aeqe_dma);
qm               1613 drivers/crypto/hisilicon/qm.c 	ret = qm_mb(qm, QM_MB_CMD_AEQC, aeqc_dma, 0, 0);
qm               1620 drivers/crypto/hisilicon/qm.c static int __hisi_qm_start(struct hisi_qm *qm)
qm               1622 drivers/crypto/hisilicon/qm.c 	struct pci_dev *pdev = qm->pdev;
qm               1627 drivers/crypto/hisilicon/qm.c #define QM_INIT_BUF(qm, type, num) do { \
qm               1628 drivers/crypto/hisilicon/qm.c 	(qm)->type = ((qm)->qdma.va + (off)); \
qm               1629 drivers/crypto/hisilicon/qm.c 	(qm)->type##_dma = (qm)->qdma.dma + (off); \
qm               1633 drivers/crypto/hisilicon/qm.c 	WARN_ON(!qm->qdma.dma);
qm               1635 drivers/crypto/hisilicon/qm.c 	if (qm->qp_num == 0)
qm               1638 drivers/crypto/hisilicon/qm.c 	if (qm->fun_type == QM_HW_PF) {
qm               1639 drivers/crypto/hisilicon/qm.c 		ret = qm_dev_mem_reset(qm);
qm               1643 drivers/crypto/hisilicon/qm.c 		ret = hisi_qm_set_vft(qm, 0, qm->qp_base, qm->qp_num);
qm               1648 drivers/crypto/hisilicon/qm.c 	QM_INIT_BUF(qm, eqe, QM_Q_DEPTH);
qm               1649 drivers/crypto/hisilicon/qm.c 	QM_INIT_BUF(qm, aeqe, QM_Q_DEPTH);
qm               1650 drivers/crypto/hisilicon/qm.c 	QM_INIT_BUF(qm, sqc, qm->qp_num);
qm               1651 drivers/crypto/hisilicon/qm.c 	QM_INIT_BUF(qm, cqc, qm->qp_num);
qm               1658 drivers/crypto/hisilicon/qm.c 		     qm->eqe, (unsigned long)qm->eqe_dma,
qm               1659 drivers/crypto/hisilicon/qm.c 		     qm->aeqe, (unsigned long)qm->aeqe_dma,
qm               1660 drivers/crypto/hisilicon/qm.c 		     qm->sqc, (unsigned long)qm->sqc_dma,
qm               1661 drivers/crypto/hisilicon/qm.c 		     qm->cqc, (unsigned long)qm->cqc_dma);
qm               1663 drivers/crypto/hisilicon/qm.c 	ret = qm_eq_ctx_cfg(qm);
qm               1667 drivers/crypto/hisilicon/qm.c 	ret = qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0);
qm               1671 drivers/crypto/hisilicon/qm.c 	ret = qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0);
qm               1675 drivers/crypto/hisilicon/qm.c 	writel(0x0, qm->io_base + QM_VF_EQ_INT_MASK);
qm               1676 drivers/crypto/hisilicon/qm.c 	writel(0x0, qm->io_base + QM_VF_AEQ_INT_MASK);
qm               1687 drivers/crypto/hisilicon/qm.c int hisi_qm_start(struct hisi_qm *qm)
qm               1689 drivers/crypto/hisilicon/qm.c 	struct device *dev = &qm->pdev->dev;
qm               1691 drivers/crypto/hisilicon/qm.c 	dev_dbg(dev, "qm start with %d queue pairs\n", qm->qp_num);
qm               1693 drivers/crypto/hisilicon/qm.c 	if (!qm->qp_num) {
qm               1698 drivers/crypto/hisilicon/qm.c 	if (!qm->qp_bitmap) {
qm               1699 drivers/crypto/hisilicon/qm.c 		qm->qp_bitmap = devm_kcalloc(dev, BITS_TO_LONGS(qm->qp_num),
qm               1701 drivers/crypto/hisilicon/qm.c 		qm->qp_array = devm_kcalloc(dev, qm->qp_num,
qm               1704 drivers/crypto/hisilicon/qm.c 		if (!qm->qp_bitmap || !qm->qp_array)
qm               1708 drivers/crypto/hisilicon/qm.c 	if (!qm->use_dma_api) {
qm               1709 drivers/crypto/hisilicon/qm.c 		dev_dbg(&qm->pdev->dev, "qm delay start\n");
qm               1711 drivers/crypto/hisilicon/qm.c 	} else if (!qm->qdma.va) {
qm               1712 drivers/crypto/hisilicon/qm.c 		qm->qdma.size = QMC_ALIGN(sizeof(struct qm_eqe) * QM_Q_DEPTH) +
qm               1714 drivers/crypto/hisilicon/qm.c 				QMC_ALIGN(sizeof(struct qm_sqc) * qm->qp_num) +
qm               1715 drivers/crypto/hisilicon/qm.c 				QMC_ALIGN(sizeof(struct qm_cqc) * qm->qp_num);
qm               1716 drivers/crypto/hisilicon/qm.c 		qm->qdma.va = dma_alloc_coherent(dev, qm->qdma.size,
qm               1717 drivers/crypto/hisilicon/qm.c 						 &qm->qdma.dma, GFP_KERNEL);
qm               1719 drivers/crypto/hisilicon/qm.c 			qm->qdma.va, &qm->qdma.dma, qm->qdma.size);
qm               1720 drivers/crypto/hisilicon/qm.c 		if (!qm->qdma.va)
qm               1724 drivers/crypto/hisilicon/qm.c 	return __hisi_qm_start(qm);
qm               1736 drivers/crypto/hisilicon/qm.c int hisi_qm_stop(struct hisi_qm *qm)
qm               1742 drivers/crypto/hisilicon/qm.c 	if (!qm || !qm->pdev) {
qm               1747 drivers/crypto/hisilicon/qm.c 	dev = &qm->pdev->dev;
qm               1750 drivers/crypto/hisilicon/qm.c 	writel(0x1, qm->io_base + QM_VF_EQ_INT_MASK);
qm               1751 drivers/crypto/hisilicon/qm.c 	writel(0x1, qm->io_base + QM_VF_AEQ_INT_MASK);
qm               1754 drivers/crypto/hisilicon/qm.c 	for (i = 0; i < qm->qp_num; i++) {
qm               1755 drivers/crypto/hisilicon/qm.c 		qp = qm->qp_array[i];
qm               1765 drivers/crypto/hisilicon/qm.c 	if (qm->fun_type == QM_HW_PF) {
qm               1766 drivers/crypto/hisilicon/qm.c 		ret = hisi_qm_set_vft(qm, 0, 0, 0);
qm               1781 drivers/crypto/hisilicon/qm.c int hisi_qm_debug_init(struct hisi_qm *qm)
qm               1786 drivers/crypto/hisilicon/qm.c 	qm_d = debugfs_create_dir("qm", qm->debug.debug_root);
qm               1789 drivers/crypto/hisilicon/qm.c 	qm->debug.qm_d = qm_d;
qm               1792 drivers/crypto/hisilicon/qm.c 	if (qm->fun_type == QM_HW_PF)
qm               1794 drivers/crypto/hisilicon/qm.c 			if (qm_create_debugfs_file(qm, i)) {
qm               1799 drivers/crypto/hisilicon/qm.c 	qm_regs = debugfs_create_file("qm_regs", 0444, qm->debug.qm_d, qm,
qm               1818 drivers/crypto/hisilicon/qm.c void hisi_qm_debug_regs_clear(struct hisi_qm *qm)
qm               1824 drivers/crypto/hisilicon/qm.c 	writel(0x0, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
qm               1825 drivers/crypto/hisilicon/qm.c 	writel(0x0, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
qm               1831 drivers/crypto/hisilicon/qm.c 	writel(0x1, qm->io_base + QM_DFX_CNT_CLR_CE);
qm               1835 drivers/crypto/hisilicon/qm.c 		readl(qm->io_base + regs->reg_offset);
qm               1839 drivers/crypto/hisilicon/qm.c 	writel(0x0, qm->io_base + QM_DFX_CNT_CLR_CE);
qm               1861 drivers/crypto/hisilicon/qm.c void hisi_qm_hw_error_init(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,
qm               1864 drivers/crypto/hisilicon/qm.c 	if (!qm->ops->hw_error_init) {
qm               1865 drivers/crypto/hisilicon/qm.c 		dev_err(&qm->pdev->dev, "QM version %d doesn't support hw error handling!\n",
qm               1866 drivers/crypto/hisilicon/qm.c 			qm->ver);
qm               1870 drivers/crypto/hisilicon/qm.c 	qm->ops->hw_error_init(qm, ce, nfe, fe, msi);
qm               1880 drivers/crypto/hisilicon/qm.c int hisi_qm_hw_error_handle(struct hisi_qm *qm)
qm               1882 drivers/crypto/hisilicon/qm.c 	if (!qm->ops->hw_error_handle) {
qm               1883 drivers/crypto/hisilicon/qm.c 		dev_err(&qm->pdev->dev, "QM version %d doesn't support hw error report!\n",
qm               1884 drivers/crypto/hisilicon/qm.c 			qm->ver);
qm               1888 drivers/crypto/hisilicon/qm.c 	return qm->ops->hw_error_handle(qm);
qm                195 drivers/crypto/hisilicon/qm.h 	struct hisi_qm *qm;
qm                198 drivers/crypto/hisilicon/qm.h int hisi_qm_init(struct hisi_qm *qm);
qm                199 drivers/crypto/hisilicon/qm.h void hisi_qm_uninit(struct hisi_qm *qm);
qm                200 drivers/crypto/hisilicon/qm.h int hisi_qm_start(struct hisi_qm *qm);
qm                201 drivers/crypto/hisilicon/qm.h int hisi_qm_stop(struct hisi_qm *qm);
qm                202 drivers/crypto/hisilicon/qm.h struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type);
qm                207 drivers/crypto/hisilicon/qm.h int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number);
qm                208 drivers/crypto/hisilicon/qm.h int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base, u32 number);
qm                209 drivers/crypto/hisilicon/qm.h int hisi_qm_debug_init(struct hisi_qm *qm);
qm                210 drivers/crypto/hisilicon/qm.h void hisi_qm_hw_error_init(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,
qm                212 drivers/crypto/hisilicon/qm.h int hisi_qm_hw_error_handle(struct hisi_qm *qm);
qm                214 drivers/crypto/hisilicon/qm.h void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
qm                 35 drivers/crypto/hisilicon/zip/zip.h 	struct hisi_qm qm;
qm                110 drivers/crypto/hisilicon/zip/zip_crypto.c static int hisi_zip_create_qp(struct hisi_qm *qm, struct hisi_zip_qp_ctx *ctx,
qm                116 drivers/crypto/hisilicon/zip/zip_crypto.c 	qp = hisi_qm_create_qp(qm, alg_type);
qm                144 drivers/crypto/hisilicon/zip/zip_crypto.c 	struct hisi_qm *qm;
qm                153 drivers/crypto/hisilicon/zip/zip_crypto.c 	qm = &hisi_zip->qm;
qm                157 drivers/crypto/hisilicon/zip/zip_crypto.c 		ret = hisi_zip_create_qp(qm, &hisi_zip_ctx->qp_ctx[i], i,
qm                272 drivers/crypto/hisilicon/zip/zip_crypto.c 		ret = hisi_acc_create_sgl_pool(&tmp->qp->qm->pdev->dev,
qm                285 drivers/crypto/hisilicon/zip/zip_crypto.c 	hisi_acc_free_sgl_pool(&ctx->qp_ctx[QPC_COMP].qp->qm->pdev->dev,
qm                295 drivers/crypto/hisilicon/zip/zip_crypto.c 		hisi_acc_free_sgl_pool(&ctx->qp_ctx[i].qp->qm->pdev->dev,
qm                317 drivers/crypto/hisilicon/zip/zip_crypto.c 	struct device *dev = &qp->qm->pdev->dev;
qm                440 drivers/crypto/hisilicon/zip/zip_crypto.c 		dev_dbg(&qp_ctx->qp->qm->pdev->dev, "req cache is full!\n");
qm                468 drivers/crypto/hisilicon/zip/zip_crypto.c 	struct device *dev = &qp->qm->pdev->dev;
qm                 99 drivers/crypto/hisilicon/zip/zip_main.c 		dev = &hisi_zip->qm.pdev->dev;
qm                293 drivers/crypto/hisilicon/zip/zip_main.c 	void __iomem *base = hisi_zip->qm.io_base;
qm                334 drivers/crypto/hisilicon/zip/zip_main.c 	struct hisi_qm *qm = &hisi_zip->qm;
qm                336 drivers/crypto/hisilicon/zip/zip_main.c 	if (qm->ver == QM_HW_V1) {
qm                337 drivers/crypto/hisilicon/zip/zip_main.c 		writel(HZIP_CORE_INT_DISABLE, qm->io_base + HZIP_CORE_INT_MASK);
qm                338 drivers/crypto/hisilicon/zip/zip_main.c 		dev_info(&qm->pdev->dev, "ZIP v%d does not support hw error handle\n",
qm                339 drivers/crypto/hisilicon/zip/zip_main.c 			 qm->ver);
qm                345 drivers/crypto/hisilicon/zip/zip_main.c 		writel(HZIP_CORE_INT_DISABLE, hisi_zip->qm.io_base +
qm                348 drivers/crypto/hisilicon/zip/zip_main.c 		writel(0, hisi_zip->qm.io_base + HZIP_CORE_INT_MASK);
qm                352 drivers/crypto/hisilicon/zip/zip_main.c 		       hisi_zip->qm.io_base + HZIP_CORE_INT_MASK);
qm                360 drivers/crypto/hisilicon/zip/zip_main.c 	return &hisi_zip->qm;
qm                365 drivers/crypto/hisilicon/zip/zip_main.c 	struct hisi_qm *qm = file_to_qm(file);
qm                367 drivers/crypto/hisilicon/zip/zip_main.c 	return readl(qm->io_base + QM_DFX_MB_CNT_VF);
qm                372 drivers/crypto/hisilicon/zip/zip_main.c 	struct hisi_qm *qm = file_to_qm(file);
qm                382 drivers/crypto/hisilicon/zip/zip_main.c 		qm->debug.curr_qm_qp_num = qm->qp_num;
qm                384 drivers/crypto/hisilicon/zip/zip_main.c 		vfq_num = (qm->ctrl_qp_num - qm->qp_num) / ctrl->num_vfs;
qm                386 drivers/crypto/hisilicon/zip/zip_main.c 			qm->debug.curr_qm_qp_num = qm->ctrl_qp_num -
qm                387 drivers/crypto/hisilicon/zip/zip_main.c 				qm->qp_num - (ctrl->num_vfs - 1) * vfq_num;
qm                389 drivers/crypto/hisilicon/zip/zip_main.c 			qm->debug.curr_qm_qp_num = vfq_num;
qm                392 drivers/crypto/hisilicon/zip/zip_main.c 	writel(val, qm->io_base + QM_DFX_MB_CNT_VF);
qm                393 drivers/crypto/hisilicon/zip/zip_main.c 	writel(val, qm->io_base + QM_DFX_DB_CNT_VF);
qm                396 drivers/crypto/hisilicon/zip/zip_main.c 	      (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK);
qm                397 drivers/crypto/hisilicon/zip/zip_main.c 	writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
qm                400 drivers/crypto/hisilicon/zip/zip_main.c 	      (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK);
qm                401 drivers/crypto/hisilicon/zip/zip_main.c 	writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
qm                408 drivers/crypto/hisilicon/zip/zip_main.c 	struct hisi_qm *qm = file_to_qm(file);
qm                410 drivers/crypto/hisilicon/zip/zip_main.c 	return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
qm                416 drivers/crypto/hisilicon/zip/zip_main.c 	struct hisi_qm *qm = file_to_qm(file);
qm                422 drivers/crypto/hisilicon/zip/zip_main.c 	tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
qm                424 drivers/crypto/hisilicon/zip/zip_main.c 	writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
qm                511 drivers/crypto/hisilicon/zip/zip_main.c 	struct hisi_qm *qm = &hisi_zip->qm;
qm                512 drivers/crypto/hisilicon/zip/zip_main.c 	struct device *dev = &qm->pdev->dev;
qm                534 drivers/crypto/hisilicon/zip/zip_main.c 		regset->base = qm->io_base + core_offsets[i];
qm                566 drivers/crypto/hisilicon/zip/zip_main.c 	struct hisi_qm *qm = &hisi_zip->qm;
qm                567 drivers/crypto/hisilicon/zip/zip_main.c 	struct device *dev = &qm->pdev->dev;
qm                575 drivers/crypto/hisilicon/zip/zip_main.c 	qm->debug.debug_root = dev_d;
qm                576 drivers/crypto/hisilicon/zip/zip_main.c 	ret = hisi_qm_debug_init(qm);
qm                580 drivers/crypto/hisilicon/zip/zip_main.c 	if (qm->fun_type == QM_HW_PF) {
qm                596 drivers/crypto/hisilicon/zip/zip_main.c 	struct hisi_qm *qm = &hisi_zip->qm;
qm                598 drivers/crypto/hisilicon/zip/zip_main.c 	writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);
qm                599 drivers/crypto/hisilicon/zip/zip_main.c 	writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);
qm                600 drivers/crypto/hisilicon/zip/zip_main.c 	writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
qm                602 drivers/crypto/hisilicon/zip/zip_main.c 	hisi_qm_debug_regs_clear(qm);
qm                607 drivers/crypto/hisilicon/zip/zip_main.c 	struct hisi_qm *qm = &hisi_zip->qm;
qm                609 drivers/crypto/hisilicon/zip/zip_main.c 	debugfs_remove_recursive(qm->debug.debug_root);
qm                611 drivers/crypto/hisilicon/zip/zip_main.c 	if (qm->fun_type == QM_HW_PF)
qm                617 drivers/crypto/hisilicon/zip/zip_main.c 	hisi_qm_hw_error_init(&hisi_zip->qm, QM_BASE_CE,
qm                625 drivers/crypto/hisilicon/zip/zip_main.c 	struct hisi_qm *qm = &hisi_zip->qm;
qm                628 drivers/crypto/hisilicon/zip/zip_main.c 	ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL);
qm                635 drivers/crypto/hisilicon/zip/zip_main.c 	switch (qm->ver) {
qm                637 drivers/crypto/hisilicon/zip/zip_main.c 		qm->ctrl_qp_num = HZIP_QUEUE_NUM_V1;
qm                641 drivers/crypto/hisilicon/zip/zip_main.c 		qm->ctrl_qp_num = HZIP_QUEUE_NUM_V2;
qm                659 drivers/crypto/hisilicon/zip/zip_main.c 	struct hisi_qm *qm;
qm                671 drivers/crypto/hisilicon/zip/zip_main.c 	qm = &hisi_zip->qm;
qm                672 drivers/crypto/hisilicon/zip/zip_main.c 	qm->pdev = pdev;
qm                673 drivers/crypto/hisilicon/zip/zip_main.c 	qm->ver = rev_id;
qm                675 drivers/crypto/hisilicon/zip/zip_main.c 	qm->sqe_size = HZIP_SQE_SIZE;
qm                676 drivers/crypto/hisilicon/zip/zip_main.c 	qm->dev_name = hisi_zip_name;
qm                677 drivers/crypto/hisilicon/zip/zip_main.c 	qm->fun_type = (pdev->device == PCI_DEVICE_ID_ZIP_PF) ? QM_HW_PF :
qm                681 drivers/crypto/hisilicon/zip/zip_main.c 		qm->use_dma_api = true;
qm                684 drivers/crypto/hisilicon/zip/zip_main.c 		qm->use_dma_api = false;
qm                687 drivers/crypto/hisilicon/zip/zip_main.c 		qm->use_dma_api = true;
qm                693 drivers/crypto/hisilicon/zip/zip_main.c 	ret = hisi_qm_init(qm);
qm                699 drivers/crypto/hisilicon/zip/zip_main.c 	if (qm->fun_type == QM_HW_PF) {
qm                704 drivers/crypto/hisilicon/zip/zip_main.c 		qm->qp_base = HZIP_PF_DEF_Q_BASE;
qm                705 drivers/crypto/hisilicon/zip/zip_main.c 		qm->qp_num = pf_q_num;
qm                706 drivers/crypto/hisilicon/zip/zip_main.c 	} else if (qm->fun_type == QM_HW_VF) {
qm                714 drivers/crypto/hisilicon/zip/zip_main.c 		if (qm->ver == QM_HW_V1) {
qm                715 drivers/crypto/hisilicon/zip/zip_main.c 			qm->qp_base = HZIP_PF_DEF_Q_NUM;
qm                716 drivers/crypto/hisilicon/zip/zip_main.c 			qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM;
qm                717 drivers/crypto/hisilicon/zip/zip_main.c 		} else if (qm->ver == QM_HW_V2)
qm                719 drivers/crypto/hisilicon/zip/zip_main.c 			hisi_qm_get_vft(qm, &qm->qp_base, &qm->qp_num);
qm                722 drivers/crypto/hisilicon/zip/zip_main.c 	ret = hisi_qm_start(qm);
qm                735 drivers/crypto/hisilicon/zip/zip_main.c 	hisi_qm_uninit(qm);
qm                742 drivers/crypto/hisilicon/zip/zip_main.c 	struct hisi_qm *qm = &hisi_zip->qm;
qm                743 drivers/crypto/hisilicon/zip/zip_main.c 	u32 qp_num = qm->qp_num;
qm                751 drivers/crypto/hisilicon/zip/zip_main.c 	remain_q_num = qm->ctrl_qp_num - qp_num;
qm                759 drivers/crypto/hisilicon/zip/zip_main.c 		ret = hisi_qm_set_vft(qm, i, q_base, q_num);
qm                771 drivers/crypto/hisilicon/zip/zip_main.c 	struct hisi_qm *qm = &hisi_zip->qm;
qm                776 drivers/crypto/hisilicon/zip/zip_main.c 		ret = hisi_qm_set_vft(qm, i, 0, 0);
qm                846 drivers/crypto/hisilicon/zip/zip_main.c 	struct hisi_qm *qm = &hisi_zip->qm;
qm                848 drivers/crypto/hisilicon/zip/zip_main.c 	if (qm->fun_type == QM_HW_PF && hisi_zip->ctrl->num_vfs != 0)
qm                852 drivers/crypto/hisilicon/zip/zip_main.c 	hisi_qm_stop(qm);
qm                854 drivers/crypto/hisilicon/zip/zip_main.c 	if (qm->fun_type == QM_HW_PF)
qm                857 drivers/crypto/hisilicon/zip/zip_main.c 	hisi_qm_uninit(qm);
qm                864 drivers/crypto/hisilicon/zip/zip_main.c 	struct device *dev = &hisi_zip->qm.pdev->dev;
qm                873 drivers/crypto/hisilicon/zip/zip_main.c 				err_val = readl(hisi_zip->qm.io_base +
qm                891 drivers/crypto/hisilicon/zip/zip_main.c 	err_sts = readl(hisi_zip->qm.io_base + HZIP_CORE_INT_STATUS);
qm                896 drivers/crypto/hisilicon/zip/zip_main.c 		writel(err_sts, hisi_zip->qm.io_base + HZIP_CORE_INT_SOURCE);
qm                916 drivers/crypto/hisilicon/zip/zip_main.c 	qm_ret = hisi_qm_hw_error_handle(&hisi_zip->qm);
qm                350 drivers/media/i2c/st-mipid02.c 	struct v4l2_querymenu qm = {.id = V4L2_CID_LINK_FREQ, };
qm                357 drivers/media/i2c/st-mipid02.c 	qm.index = v4l2_ctrl_g_ctrl(ctrl);
qm                359 drivers/media/i2c/st-mipid02.c 	ret = v4l2_querymenu(subdev->ctrl_handler, &qm);
qm                363 drivers/media/i2c/st-mipid02.c 	return qm.value;
qm                298 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	struct v4l2_querymenu qm = {.id = V4L2_CID_LINK_FREQ, };
qm                312 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	qm.index = v4l2_ctrl_g_ctrl(link_freq);
qm                313 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	r = v4l2_querymenu(q->sensor->ctrl_handler, &qm);
qm                319 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	if (!qm.value) {
qm                323 drivers/media/pci/intel/ipu3/ipu3-cio2.c 	freq = qm.value;
qm               1099 drivers/media/usb/uvc/uvc_v4l2.c 			       struct v4l2_querymenu *qm)
qm               1104 drivers/media/usb/uvc/uvc_v4l2.c 	return uvc_query_v4l2_menu(chain, qm);
qm               3064 drivers/media/v4l2-core/v4l2-ctrls.c int v4l2_querymenu(struct v4l2_ctrl_handler *hdl, struct v4l2_querymenu *qm)
qm               3067 drivers/media/v4l2-core/v4l2-ctrls.c 	u32 i = qm->index;
qm               3069 drivers/media/v4l2-core/v4l2-ctrls.c 	ctrl = v4l2_ctrl_find(hdl, qm->id);
qm               3073 drivers/media/v4l2-core/v4l2-ctrls.c 	qm->reserved = 0;
qm               3098 drivers/media/v4l2-core/v4l2-ctrls.c 		strscpy(qm->name, ctrl->qmenu[i], sizeof(qm->name));
qm               3100 drivers/media/v4l2-core/v4l2-ctrls.c 		qm->value = ctrl->qmenu_int[i];
qm                794 drivers/net/ethernet/freescale/dpaa/dpaa_eth.c static void dpaa_eth_cgscn(struct qman_portal *qm, struct qman_cgr *cgr,
qm               1380 drivers/soc/fsl/qbman/qman.c static void qman_destroy_portal(struct qman_portal *qm)
qm               1385 drivers/soc/fsl/qbman/qman.c 	qm_dqrr_sdqcr_set(&qm->p, 0);
qm               1396 drivers/soc/fsl/qbman/qman.c 	qm_eqcr_cce_update(&qm->p);
qm               1397 drivers/soc/fsl/qbman/qman.c 	qm_eqcr_cce_update(&qm->p);
qm               1398 drivers/soc/fsl/qbman/qman.c 	pcfg = qm->config;
qm               1400 drivers/soc/fsl/qbman/qman.c 	free_irq(pcfg->irq, qm);
qm               1402 drivers/soc/fsl/qbman/qman.c 	kfree(qm->cgrs);
qm               1403 drivers/soc/fsl/qbman/qman.c 	qm_mc_finish(&qm->p);
qm               1404 drivers/soc/fsl/qbman/qman.c 	qm_mr_finish(&qm->p);
qm               1405 drivers/soc/fsl/qbman/qman.c 	qm_dqrr_finish(&qm->p);
qm               1406 drivers/soc/fsl/qbman/qman.c 	qm_eqcr_finish(&qm->p);
qm               1408 drivers/soc/fsl/qbman/qman.c 	qm->config = NULL;
qm               1413 drivers/soc/fsl/qbman/qman.c 	struct qman_portal *qm = get_affine_portal();
qm               1417 drivers/soc/fsl/qbman/qman.c 	pcfg = qm->config;
qm               1420 drivers/soc/fsl/qbman/qman.c 	qman_destroy_portal(qm);
qm                197 fs/quota/dquot.c 		int qm;
qm                201 fs/quota/dquot.c 		for (qm = 0; module_names[qm].qm_fmt_id &&
qm                202 fs/quota/dquot.c 			     module_names[qm].qm_fmt_id != id; qm++)
qm                204 fs/quota/dquot.c 		if (!module_names[qm].qm_fmt_id ||
qm                205 fs/quota/dquot.c 		    request_module(module_names[qm].qm_mod_name))
qm               1239 include/media/v4l2-ctrls.h int v4l2_querymenu(struct v4l2_ctrl_handler *hdl, struct v4l2_querymenu *qm);