psr_context       179 drivers/gpu/drm/amd/display/dc/dc_link.h 		struct psr_context *psr_context);
psr_context       160 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		struct psr_context *psr_context)
psr_context       172 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			psr_context->psrExitLinkTrainingRequired);
psr_context       182 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	switch (psr_context->controllerId) {
psr_context       220 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			psr_context->sdpTransmitLineNumDeadline);
psr_context       229 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
psr_context       230 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
psr_context       232 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			psr_context->rfb_update_auto_en;
psr_context       233 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
psr_context       234 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.dcp_sel = psr_context->controllerId;
psr_context       235 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.phy_type  = psr_context->phyType;
psr_context       237 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			psr_context->psrFrameCaptureIndicationReq;
psr_context       238 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.aux_chan = psr_context->channel;
psr_context       239 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
psr_context       244 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData2.bits.dig_fe = psr_context->engineId;
psr_context       245 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData2.bits.dig_be = psr_context->transmitterId;
psr_context       247 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			psr_context->skipPsrWaitForPllLock;
psr_context       248 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData2.bits.frame_delay = psr_context->frame_delay;
psr_context       249 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
psr_context       251 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			psr_context->numberOfControllers;
psr_context       256 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
psr_context       565 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 		struct psr_context *psr_context)
psr_context       581 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			psr_context->psrExitLinkTrainingRequired);
psr_context       591 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	switch (psr_context->controllerId) {
psr_context       629 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			psr_context->sdpTransmitLineNumDeadline);
psr_context       631 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	if (psr_context->allow_smu_optimizations)
psr_context       641 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
psr_context       642 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
psr_context       644 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			psr_context->rfb_update_auto_en;
psr_context       645 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
psr_context       646 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.dcp_sel = psr_context->controllerId;
psr_context       647 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.phy_type  = psr_context->phyType;
psr_context       649 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			psr_context->psrFrameCaptureIndicationReq;
psr_context       650 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.aux_chan = psr_context->channel;
psr_context       651 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
psr_context       652 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations;
psr_context       657 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData2.bits.dig_fe = psr_context->engineId;
psr_context       658 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData2.bits.dig_be = psr_context->transmitterId;
psr_context       660 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			psr_context->skipPsrWaitForPllLock;
psr_context       661 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData2.bits.frame_delay = psr_context->frame_delay;
psr_context       662 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
psr_context       664 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			psr_context->numberOfControllers;
psr_context       669 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
psr_context        66 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h 			struct psr_context *psr_context);