ppe 30 arch/mips/lantiq/clk.c unsigned long io, unsigned long ppe) ppe 35 arch/mips/lantiq/clk.c cpu_clk_generic[3].rate = ppe; ppe 73 arch/mips/lantiq/clk.h unsigned long io, unsigned long ppe); ppe 49 arch/powerpc/include/asm/cell-regs.h u32 ppe; ppe 273 arch/powerpc/platforms/cell/cbe_thermal.c static DEVICE_PREFIX_ATTR(ppe, throttle_end, 0600); ppe 274 arch/powerpc/platforms/cell/cbe_thermal.c static DEVICE_PREFIX_ATTR(ppe, throttle_begin, 0600); ppe 275 arch/powerpc/platforms/cell/cbe_thermal.c static DEVICE_PREFIX_ATTR(ppe, throttle_full_stop, 0600); ppe 310 arch/powerpc/platforms/cell/cbe_thermal.c tpr.ppe = 0x1F0803; ppe 65 block/partitions/aix.c struct ppe ppe[1016]; ppe 249 block/partitions/aix.c struct ppe *p = pvd->ppe + i; ppe 678 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c unsigned int ppe = mode_422 ? 2 : 1; ppe 682 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c vp_width = pipe_src_param.viewport_width_c / ppe; ppe 687 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c vp_width = pipe_src_param.viewport_width / ppe; ppe 678 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c unsigned int ppe = mode_422 ? 2 : 1; ppe 682 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c vp_width = pipe_src_param.viewport_width_c / ppe; ppe 687 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c vp_width = pipe_src_param.viewport_width / ppe; ppe 688 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c unsigned int ppe = mode_422 ? 2 : 1; ppe 692 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c vp_width = pipe_param.src.viewport_width_c / ppe; ppe 697 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c vp_width = pipe_param.src.viewport_width / ppe; ppe 549 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c unsigned int ppe = mode_422 ? 2 : 1; ppe 607 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c vp_width = pipe_src_param.viewport_width_c / ppe; ppe 612 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c vp_width = pipe_src_param.viewport_width / ppe; ppe 1976 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c static u8 iwl_mvm_he_get_ppe_val(u8 *ppe, u8 ppe_pos_bit) ppe 1984 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c return (ppe[byte_num] >> bit_num) & ppe 1995 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c res = (ppe[byte_num + 1] & ppe 1998 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c res += (ppe[byte_num] >> bit_num) & (BIT(residue_bits) - 1); ppe 2087 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c u8 *ppe = &sta->he_cap.ppe_thres[0]; ppe 2112 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c iwl_mvm_he_get_ppe_val(ppe, ppe 2117 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c iwl_mvm_he_get_ppe_val(ppe, ppe 313 drivers/staging/media/tegra-vde/vde.c tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x14); ppe 314 drivers/staging/media/tegra-vde/vde.c tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x28); ppe 990 drivers/staging/media/tegra-vde/vde.c vde->ppe = devm_ioremap_resource(dev, regs); ppe 991 drivers/staging/media/tegra-vde/vde.c if (IS_ERR(vde->ppe)) ppe 992 drivers/staging/media/tegra-vde/vde.c return PTR_ERR(vde->ppe); ppe 31 drivers/staging/media/tegra-vde/vde.h void __iomem *ppe; ppe 86 drivers/staging/media/tegra-vde/vde.h if (vde->ppe == base) ppe 39 include/linux/mtd/nand.h #define NAND_MEMORG(bpc, ps, os, ppe, epl, mbb, ppl, lpt, nt) \ ppe 44 include/linux/mtd/nand.h .pages_per_eraseblock = (ppe), \