pp_smu_status     664 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
pp_smu_status     725 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum pp_smu_status pp_nv_set_pme_wa_enable(struct pp_smu *pp)
pp_smu_status     741 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count)
pp_smu_status     757 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum pp_smu_status pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz)
pp_smu_status     773 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum pp_smu_status pp_nv_set_hard_min_dcefclk_by_freq(
pp_smu_status     796 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum pp_smu_status pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz)
pp_smu_status     818 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum pp_smu_status pp_nv_set_pstate_handshake_support(
pp_smu_status     831 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
pp_smu_status     866 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum pp_smu_status pp_nv_get_maximum_sustainable_clocks(
pp_smu_status     885 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp,
pp_smu_status    3397 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		enum pp_smu_status status;
pp_smu_status    1322 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
pp_smu_status    1328 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
pp_smu_status     180 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	enum pp_smu_status (*set_display_count)(struct pp_smu *pp, int count);
pp_smu_status     185 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	enum pp_smu_status (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int Mhz);
pp_smu_status     191 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	enum pp_smu_status (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int Mhz);
pp_smu_status     196 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	enum pp_smu_status (*set_hard_min_uclk_by_freq)(struct pp_smu *pp, int Mhz);
pp_smu_status     201 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	enum pp_smu_status (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int Mhz);
pp_smu_status     204 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	enum pp_smu_status (*set_pme_wa_enable)(struct pp_smu *pp);
pp_smu_status     209 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	enum pp_smu_status (*set_voltage_by_freq)(struct pp_smu *pp,
pp_smu_status     224 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
pp_smu_status     230 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	enum pp_smu_status (*get_maximum_sustainable_clocks)(struct pp_smu *pp,
pp_smu_status     235 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	enum pp_smu_status (*get_uclk_dpm_states)(struct pp_smu *pp,
pp_smu_status     247 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	enum pp_smu_status (*set_pstate_handshake_support)(struct pp_smu *pp,
pp_smu_status     285 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
pp_smu_status     288 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,