pp_smu 543 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c void pp_rv_set_wm_ranges(struct pp_smu *pp, pp_smu 599 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c void pp_rv_set_pme_wa_enable(struct pp_smu *pp) pp_smu 612 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c void pp_rv_set_active_display_count(struct pp_smu *pp, int count) pp_smu 625 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c void pp_rv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int clock) pp_smu 638 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c void pp_rv_set_hard_min_dcefclk_by_freq(struct pp_smu *pp, int clock) pp_smu 651 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz) pp_smu 664 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp, pp_smu 725 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum pp_smu_status pp_nv_set_pme_wa_enable(struct pp_smu *pp) pp_smu 741 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count) pp_smu 757 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum pp_smu_status pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz) pp_smu 774 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c struct pp_smu *pp, int mhz) pp_smu 796 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum pp_smu_status pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz) pp_smu 819 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c struct pp_smu *pp, BOOLEAN pstate_handshake_supported) pp_smu 831 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp, pp_smu 867 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c struct pp_smu *pp, struct pp_smu_nv_clock_table *max_clocks) pp_smu 885 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp, pp_smu 913 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c funcs->rv_funcs.pp_smu.dm = ctx; pp_smu 928 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c funcs->nv_funcs.pp_smu.dm = ctx; pp_smu 1506 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c if (dc->res_pool->pp_smu) pp_smu 1507 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pp = &dc->res_pool->pp_smu->rv_funcs; pp_smu 1561 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pp->set_wm_ranges(&pp->pp_smu, &ranges); pp_smu 69 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg) pp_smu 116 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); pp_smu 121 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu); pp_smu 126 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); pp_smu 134 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); pp_smu 133 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c struct pp_smu_funcs_rv *pp_smu = NULL; pp_smu 140 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c ASSERT(clk_mgr->pp_smu); pp_smu 142 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu = &clk_mgr->pp_smu->rv_funcs; pp_smu 155 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c if (pp_smu->set_display_count) pp_smu 156 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_display_count(&pp_smu->pp_smu, display_count); pp_smu 196 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c if (pp_smu->set_hard_min_fclk_by_freq && pp_smu 197 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_hard_min_dcfclk_by_freq && pp_smu 198 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_min_deep_sleep_dcfclk) { pp_smu 199 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000); pp_smu 200 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000); pp_smu 201 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000); pp_smu 216 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c if (pp_smu->set_hard_min_fclk_by_freq && pp_smu 217 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_hard_min_dcfclk_by_freq && pp_smu 218 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_min_deep_sleep_dcfclk) { pp_smu 219 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000); pp_smu 220 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000); pp_smu 221 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000); pp_smu 229 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c struct pp_smu_funcs_rv *pp_smu = NULL; pp_smu 231 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c if (clk_mgr->pp_smu) { pp_smu 232 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu = &clk_mgr->pp_smu->rv_funcs; pp_smu 234 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c if (pp_smu->set_pme_wa_enable) pp_smu 235 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); pp_smu 251 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu) pp_smu 257 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c clk_mgr->pp_smu = pp_smu; pp_smu 29 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.h void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu); pp_smu 37 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv2_clk_mgr.c void rv2_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu) pp_smu 40 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv2_clk_mgr.c rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); pp_smu 29 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv2_clk_mgr.h void rv2_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu); pp_smu 147 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c struct pp_smu_funcs_nv *pp_smu = NULL; pp_smu 150 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (dc->res_pool->pp_smu) pp_smu 151 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu = &dc->res_pool->pp_smu->nv_funcs; pp_smu 155 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (going_up && pp_smu && pp_smu->set_voltage_by_freq) pp_smu 156 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000); pp_smu 160 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (!going_up && pp_smu && pp_smu->set_voltage_by_freq) pp_smu 161 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000); pp_smu 168 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c struct pp_smu_funcs_nv *pp_smu = NULL; pp_smu 171 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (dc->res_pool->pp_smu) pp_smu 172 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu = &dc->res_pool->pp_smu->nv_funcs; pp_smu 177 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (going_up && pp_smu && pp_smu->set_voltage_by_freq) pp_smu 178 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000); pp_smu 182 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (!going_up && pp_smu && pp_smu->set_voltage_by_freq) pp_smu 183 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000); pp_smu 193 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c struct pp_smu_funcs_nv *pp_smu = NULL; pp_smu 211 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (dc->res_pool->pp_smu) pp_smu 212 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu = &dc->res_pool->pp_smu->nv_funcs; pp_smu 218 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (pp_smu && pp_smu->set_display_count) pp_smu 219 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu->set_display_count(&pp_smu->pp_smu, display_count); pp_smu 224 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (pp_smu && pp_smu->set_voltage_by_freq) pp_smu 225 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000); pp_smu 235 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq) pp_smu 236 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000); pp_smu 242 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk) pp_smu 243 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000); pp_smu 248 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (pp_smu && pp_smu->set_hard_min_socclk_by_freq) pp_smu 249 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000); pp_smu 256 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (pp_smu && pp_smu->set_pstate_handshake_support) pp_smu 257 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support); pp_smu 263 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (pp_smu && pp_smu->set_hard_min_uclk_by_freq) pp_smu 264 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000); pp_smu 388 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c struct pp_smu_funcs_nv *pp_smu = NULL; pp_smu 390 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (clk_mgr->pp_smu) { pp_smu 391 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu = &clk_mgr->pp_smu->nv_funcs; pp_smu 393 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (pp_smu->set_pme_wa_enable) pp_smu 394 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); pp_smu 430 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c struct pp_smu_funcs *pp_smu, pp_smu 434 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c clk_mgr->pp_smu = pp_smu; pp_smu 43 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h struct pp_smu_funcs *pp_smu, pp_smu 519 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c struct pp_smu_funcs *pp_smu, pp_smu 529 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c clk_mgr->pp_smu = pp_smu; pp_smu 572 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (pp_smu) { pp_smu 573 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table); pp_smu 588 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c if (pp_smu && pp_smu->rn_funcs.set_wm_ranges) pp_smu 589 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges); pp_smu 36 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h struct pp_smu_funcs *pp_smu, pp_smu 694 drivers/gpu/drm/amd/display/dc/core/dc.c dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); pp_smu 947 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pp_smu_funcs *pp_smu = NULL; pp_smu 960 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (core_dc->res_pool->pp_smu) pp_smu 961 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pp_smu = core_dc->res_pool->pp_smu; pp_smu 987 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pp_smu_funcs *pp_smu = NULL; pp_smu 1004 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (dc->res_pool->pp_smu) pp_smu 1005 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pp_smu = dc->res_pool->pp_smu; pp_smu 876 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); pp_smu 878 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (!pp_smu) pp_smu 879 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c return pp_smu; pp_smu 881 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c dm_pp_get_funcs(ctx, pp_smu); pp_smu 882 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c return pp_smu; pp_smu 967 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c kfree(pool->base.pp_smu); pp_smu 1418 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c pool->base.pp_smu = dcn10_pp_smu_create(ctx); pp_smu 1424 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c if (pool->base.pp_smu != NULL pp_smu 1425 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) pp_smu 1410 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.pp_smu != NULL) pp_smu 1411 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dcn20_pp_smu_destroy(&pool->base.pp_smu); pp_smu 3071 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); pp_smu 3073 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!pp_smu) pp_smu 3074 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return pp_smu; pp_smu 3076 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dm_pp_get_funcs(ctx, pp_smu); pp_smu 3078 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pp_smu->ctx.ver != PP_SMU_VER_NV) pp_smu 3079 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); pp_smu 3081 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c return pp_smu; pp_smu 3084 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu) pp_smu 3086 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pp_smu && *pp_smu) { pp_smu 3087 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c kfree(*pp_smu); pp_smu 3088 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c *pp_smu = NULL; pp_smu 3393 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.pp_smu) { pp_smu 3401 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) { pp_smu 3402 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) pp_smu 3403 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); pp_smu 3408 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) { pp_smu 3409 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) pp_smu 3410 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks); pp_smu 3559 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.pp_smu = dcn20_pp_smu_create(ctx); pp_smu 3608 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pool->base.pp_smu->nv_funcs.set_wm_ranges) pp_smu 3609 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges); pp_smu 99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu); pp_smu 943 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pool->base.pp_smu != NULL) pp_smu 944 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c dcn20_pp_smu_destroy(&pool->base.pp_smu); pp_smu 1322 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp, pp_smu 1328 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp, pp_smu 1337 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); pp_smu 1339 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pp_smu->ctx.ver = PP_SMU_VER_RN; pp_smu 1341 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table; pp_smu 1342 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges; pp_smu 1344 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c return pp_smu; pp_smu 1347 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu) pp_smu 1349 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pp_smu && *pp_smu) { pp_smu 1350 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c kfree(*pp_smu); pp_smu 1351 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c *pp_smu = NULL; pp_smu 1537 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pool->base.pp_smu = dcn21_pp_smu_create(ctx); pp_smu 103 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h struct pp_smu pp_smu; pp_smu 109 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h void (*set_display_count)(struct pp_smu *pp, int count); pp_smu 118 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h void (*set_wm_ranges)(struct pp_smu *pp, pp_smu 124 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz); pp_smu 130 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz); pp_smu 135 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int mhz); pp_smu 140 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h void (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int mhz); pp_smu 143 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h void (*set_pme_wa_enable)(struct pp_smu *pp); pp_smu 175 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h struct pp_smu pp_smu; pp_smu 180 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*set_display_count)(struct pp_smu *pp, int count); pp_smu 185 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int Mhz); pp_smu 191 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int Mhz); pp_smu 196 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*set_hard_min_uclk_by_freq)(struct pp_smu *pp, int Mhz); pp_smu 201 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int Mhz); pp_smu 204 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*set_pme_wa_enable)(struct pp_smu *pp); pp_smu 209 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*set_voltage_by_freq)(struct pp_smu *pp, pp_smu 224 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp, pp_smu 230 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*get_maximum_sustainable_clocks)(struct pp_smu *pp, pp_smu 235 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*get_uclk_dpm_states)(struct pp_smu *pp, pp_smu 247 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*set_pstate_handshake_support)(struct pp_smu *pp, pp_smu 275 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h struct pp_smu pp_smu; pp_smu 285 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp, pp_smu 288 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp, pp_smu 294 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h struct pp_smu ctx; pp_smu 175 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct pp_smu_funcs *pp_smu; pp_smu 198 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg); pp_smu 195 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h struct pp_smu_funcs *pp_smu;