CRTC_WRITE 307 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_CONTROL, 0); CRTC_WRITE 308 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN); CRTC_WRITE 309 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_CONTROL, 0); CRTC_WRITE 311 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_HORZA, CRTC_WRITE 318 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_HORZB, CRTC_WRITE 324 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_VERTA, CRTC_WRITE 329 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_VERTB, CRTC_WRITE 335 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_VERTA_EVEN, CRTC_WRITE 342 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_VERTB_EVEN, CRTC_WRITE 353 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_V_CONTROL, CRTC_WRITE 359 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_VSYNCD_EVEN, 0); CRTC_WRITE 361 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_V_CONTROL, CRTC_WRITE 366 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); CRTC_WRITE 368 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_CONTROL, CRTC_WRITE 465 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_V_CONTROL, CRTC_WRITE 577 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_V_CONTROL, CRTC_WRITE 769 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_INTEN, PV_INT_VFP_START); CRTC_WRITE 778 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_INTEN, 0); CRTC_WRITE 823 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); CRTC_WRITE 1209 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_INTEN, 0); CRTC_WRITE 1210 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); CRTC_WRITE 1249 drivers/gpu/drm/vc4/vc4_crtc.c CRTC_WRITE(PV_INTEN, 0);