CRTC_REG_UPDATE_N   49 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		CRTC_REG_UPDATE_N(reg, 1, FD(reg##__##field), val)
CRTC_REG_UPDATE_N   52 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		CRTC_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
CRTC_REG_UPDATE_N   55 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
CRTC_REG_UPDATE_N   58 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3, FD(reg##__##field4), val4)
CRTC_REG_UPDATE_N   61 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3, FD(reg##__##field4), val4, FD(reg##__##field5), val5)
CRTC_REG_UPDATE_N  263 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	CRTC_REG_UPDATE_N(DCP0_DCP_GSL_CONTROL, 6,
CRTC_REG_UPDATE_N  330 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	CRTC_REG_UPDATE_N(CRTC0_CRTC_TRIGB_CNTL, 7,