CRTC_REG_SET_N     64 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		CRTC_REG_SET_N(reg, 1, FD(reg##__##field), val)
CRTC_REG_SET_N     67 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		CRTC_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
CRTC_REG_SET_N     70 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		CRTC_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
CRTC_REG_SET_N    288 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	CRTC_REG_SET_N(DCP0_DCP_GSL_CONTROL, 6,
CRTC_REG_SET_N    560 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		CRTC_REG_SET_N(CRTC0_CRTC_V_TOTAL_CONTROL, 6,
CRTC_REG_SET_N    573 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		CRTC_REG_SET_N(CRTC0_CRTC_V_TOTAL_CONTROL, 5,