pmcmsptwi_writel  178 drivers/i2c/busses/i2c-pmcmsp.c 	pmcmsptwi_writel(pmcmsptwi_clock_to_reg(&cfg->standard),
pmcmsptwi_writel  180 drivers/i2c/busses/i2c-pmcmsp.c 	pmcmsptwi_writel(pmcmsptwi_clock_to_reg(&cfg->highspeed),
pmcmsptwi_writel  204 drivers/i2c/busses/i2c-pmcmsp.c 	pmcmsptwi_writel(pmcmsptwi_cfg_to_reg(cfg),
pmcmsptwi_writel  246 drivers/i2c/busses/i2c-pmcmsp.c 	pmcmsptwi_writel(reason, data->iobase + MSP_TWI_INT_STS_REG_OFFSET);
pmcmsptwi_writel  307 drivers/i2c/busses/i2c-pmcmsp.c 			pmcmsptwi_writel(MSP_TWI_INT_STS_DONE,
pmcmsptwi_writel  339 drivers/i2c/busses/i2c-pmcmsp.c 		pmcmsptwi_writel(0,
pmcmsptwi_writel  363 drivers/i2c/busses/i2c-pmcmsp.c 		pmcmsptwi_writel(0,
pmcmsptwi_writel  390 drivers/i2c/busses/i2c-pmcmsp.c 			pmcmsptwi_writel(reason, data->iobase +
pmcmsptwi_writel  412 drivers/i2c/busses/i2c-pmcmsp.c 	pmcmsptwi_writel(reg, data->iobase + MSP_TWI_CMD_REG_OFFSET);
pmcmsptwi_writel  450 drivers/i2c/busses/i2c-pmcmsp.c 	pmcmsptwi_writel(cmd->addr, data->iobase + MSP_TWI_ADD_REG_OFFSET);
pmcmsptwi_writel  457 drivers/i2c/busses/i2c-pmcmsp.c 		pmcmsptwi_writel(tmp & 0x00000000ffffffffLL,
pmcmsptwi_writel  460 drivers/i2c/busses/i2c-pmcmsp.c 			pmcmsptwi_writel(tmp >> 32,