pll_write_udelay  499 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c 	pll_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10);
pll_write_udelay  119 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG,
pll_write_udelay  121 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1);
pll_write_udelay  332 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1);
pll_write_udelay  335 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
pll_write_udelay  338 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
pll_write_udelay  341 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
pll_write_udelay  345 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2,
pll_write_udelay  362 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1);
pll_write_udelay  365 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
pll_write_udelay  368 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250);
pll_write_udelay  371 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
pll_write_udelay  374 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
pll_write_udelay  377 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
pll_write_udelay  419 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x05, 512);