pll_write 2013 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c atom_card_info->pll_write = cail_pll_write; pll_write 543 drivers/gpu/drm/amd/amdgpu/atom.c gctx->card->pll_write(gctx->card, idx, val); pll_write 123 drivers/gpu/drm/amd/amdgpu/atom.h void (* pll_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ pll_write 54 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h pll_write(reg, data); pll_write 60 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h pll_write((reg), data); pll_write 252 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1, pll_write 254 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1, pll_write 256 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1, pll_write 258 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1, pll_write 260 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1, pll_write 262 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1, pll_write 264 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL, pll_write 273 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80); pll_write 274 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03); pll_write 275 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00); pll_write 276 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_DSM_DIVIDER, 0x00); pll_write 277 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e); pll_write 278 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40); pll_write 279 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, pll_write 281 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c); pll_write 282 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00); pll_write 283 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE, 0x00); pll_write 284 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08); pll_write 285 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x08); pll_write 286 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1, 0xc0); pll_write 287 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0xfa); pll_write 288 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, pll_write 290 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80); pll_write 291 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_PFILT, 0x29); pll_write 292 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f); pll_write 300 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12); pll_write 301 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1, pll_write 303 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1, pll_write 305 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1, pll_write 307 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1, pll_write 309 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40); pll_write 310 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); pll_write 311 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10); pll_write 312 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS, pll_write 370 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0); pll_write 371 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0, pll_write 380 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0, pll_write 382 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0); pll_write 391 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1, pll_write 400 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1, pll_write 421 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, pll_write 443 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, pll_write 446 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll_10nm->slave->phy_cmn_mmio + pll_write 455 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0); pll_write 470 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0); pll_write 566 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val); pll_write 568 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0, pll_write 574 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val); pll_write 604 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2)); pll_write 400 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data); pll_write 403 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data); pll_write 407 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data); pll_write 410 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data); pll_write 414 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data); pll_write 417 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data); pll_write 422 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data); pll_write 436 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data); pll_write 439 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, data); pll_write 442 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, data); pll_write 444 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, data); pll_write 446 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, data); pll_write 449 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data); pll_write 451 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data); pll_write 454 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data); pll_write 456 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data); pll_write 459 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, data); pll_write 462 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, data); pll_write 465 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, data); pll_write 468 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, data); pll_write 471 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, data); pll_write 474 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, data); pll_write 477 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, data); pll_write 480 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, data); pll_write 483 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, data); pll_write 486 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, data); pll_write 496 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); pll_write 502 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0); pll_write 517 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data); pll_write 524 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, data); pll_write 527 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data); pll_write 531 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data); pll_write 534 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data); pll_write 536 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data); pll_write 538 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data); pll_write 541 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data); pll_write 544 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data); pll_write 547 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data); pll_write 550 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data); pll_write 553 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data); pll_write 555 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data); pll_write 558 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data); pll_write 560 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data); pll_write 563 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, data); pll_write 735 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); pll_write 744 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); pll_write 771 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10); pll_write 772 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1); pll_write 792 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0); pll_write 834 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); pll_write 841 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); pll_write 870 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en); pll_write 872 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap); pll_write 144 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3); pll_write 155 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance); pll_write 158 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); pll_write 159 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); pll_write 211 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02); pll_write 212 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b); pll_write 213 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06); pll_write 214 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); pll_write 216 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1); pll_write 217 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2, pll_write 219 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3, pll_write 221 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00); pll_write 227 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg); pll_write 228 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00); pll_write 229 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG, 0x31); pll_write 230 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0); pll_write 231 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG0, 0x12); pll_write 232 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG6, 0x30); pll_write 233 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG7, 0x00); pll_write 234 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG8, 0x60); pll_write 235 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG9, 0x00); pll_write 236 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG10, cal_cfg10 & 0xff); pll_write 237 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG11, cal_cfg11 & 0xff); pll_write 238 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG, 0x20); pll_write 347 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); pll_write 436 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00); pll_write 468 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG, pll_write 470 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG, pll_write 472 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_VREG_CFG, pll_write 123 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1, pll_write 130 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2, pll_write 137 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3, pll_write 140 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6, pll_write 145 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, pll_write 272 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(bytediv->reg, val); pll_write 313 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val); pll_write 316 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, pll_write 334 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_0, 0x00); pll_write 368 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10, pll_write 370 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9, pll_write 372 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, pll_write 262 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d); pll_write 263 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0, 0x10); pll_write 264 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1, 0x1a); pll_write 274 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d); pll_write 301 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B, val); pll_write 321 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d); pll_write 323 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d); pll_write 352 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B, val); pll_write 394 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, pll_rate->conf[i].reg, pll_rate->conf[i].val); pll_write 549 drivers/gpu/drm/radeon/atom.c gctx->card->pll_write(gctx->card, idx, val); pll_write 120 drivers/gpu/drm/radeon/atom.h void (* pll_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ pll_write 997 drivers/gpu/drm/radeon/radeon_device.c atom_card_info->pll_write = cail_pll_write;