pll_state 671 drivers/clk/clk-stm32f4.c int pll_state; pll_state 673 drivers/clk/clk-stm32f4.c pll_state = stm32f4_pll_is_enabled(hw); pll_state 675 drivers/clk/clk-stm32f4.c if (pll_state) pll_state 684 drivers/clk/clk-stm32f4.c if (pll_state) pll_state 721 drivers/clk/clk-stm32f4.c int pll_state, ret; pll_state 726 drivers/clk/clk-stm32f4.c pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll); pll_state 728 drivers/clk/clk-stm32f4.c if (pll_state) pll_state 733 drivers/clk/clk-stm32f4.c if (pll_state) pll_state 1275 drivers/gpu/drm/i915/display/intel_ddi.c static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state) pll_state 1279 drivers/gpu/drm/i915/display/intel_ddi.c p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; pll_state 1280 drivers/gpu/drm/i915/display/intel_ddi.c p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK; pll_state 1282 drivers/gpu/drm/i915/display/intel_ddi.c if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1)) pll_state 1283 drivers/gpu/drm/i915/display/intel_ddi.c p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; pll_state 1318 drivers/gpu/drm/i915/display/intel_ddi.c dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) pll_state 1321 drivers/gpu/drm/i915/display/intel_ddi.c dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) pll_state 1331 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_dpll_hw_state *pll_state) pll_state 1335 drivers/gpu/drm/i915/display/intel_ddi.c p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK; pll_state 1336 drivers/gpu/drm/i915/display/intel_ddi.c p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK; pll_state 1338 drivers/gpu/drm/i915/display/intel_ddi.c if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) pll_state 1339 drivers/gpu/drm/i915/display/intel_ddi.c p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> pll_state 1374 drivers/gpu/drm/i915/display/intel_ddi.c dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) pll_state 1377 drivers/gpu/drm/i915/display/intel_ddi.c dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> pll_state 1409 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_dpll_hw_state *pll_state) pll_state 1416 drivers/gpu/drm/i915/display/intel_ddi.c m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK; pll_state 1417 drivers/gpu/drm/i915/display/intel_ddi.c m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; pll_state 1418 drivers/gpu/drm/i915/display/intel_ddi.c m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ? pll_state 1419 drivers/gpu/drm/i915/display/intel_ddi.c (pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >> pll_state 1422 drivers/gpu/drm/i915/display/intel_ddi.c switch (pll_state->mg_clktop2_hsclkctl & pll_state 1437 drivers/gpu/drm/i915/display/intel_ddi.c MISSING_CASE(pll_state->mg_clktop2_hsclkctl); pll_state 1441 drivers/gpu/drm/i915/display/intel_ddi.c div2 = (pll_state->mg_clktop2_hsclkctl & pll_state 1489 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; pll_state 1495 drivers/gpu/drm/i915/display/intel_ddi.c link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); pll_state 1503 drivers/gpu/drm/i915/display/intel_ddi.c link_clock = icl_calc_mg_pll_link(dev_priv, pll_state); pll_state 1515 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; pll_state 1518 drivers/gpu/drm/i915/display/intel_ddi.c if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { pll_state 1519 drivers/gpu/drm/i915/display/intel_ddi.c link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); pll_state 1521 drivers/gpu/drm/i915/display/intel_ddi.c link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK; pll_state 1563 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; pll_state 1570 drivers/gpu/drm/i915/display/intel_ddi.c if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) { pll_state 1571 drivers/gpu/drm/i915/display/intel_ddi.c link_clock = skl_calc_wrpll_link(pll_state); pll_state 1573 drivers/gpu/drm/i915/display/intel_ddi.c link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0); pll_state 1654 drivers/gpu/drm/i915/display/intel_ddi.c static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state) pll_state 1659 drivers/gpu/drm/i915/display/intel_ddi.c clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22; pll_state 1660 drivers/gpu/drm/i915/display/intel_ddi.c if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE) pll_state 1661 drivers/gpu/drm/i915/display/intel_ddi.c clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK; pll_state 1662 drivers/gpu/drm/i915/display/intel_ddi.c clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; pll_state 1663 drivers/gpu/drm/i915/display/intel_ddi.c clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; pll_state 1664 drivers/gpu/drm/i915/display/intel_ddi.c clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; pll_state 249 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const struct intel_dpll_hw_state *pll_state, pll_state 270 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (memcmp(pll_state, pll_state 272 drivers/gpu/drm/i915/display/intel_dpll_mgr.c sizeof(*pll_state)) == 0) { pll_state 297 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const struct intel_dpll_hw_state *pll_state) pll_state 305 drivers/gpu/drm/i915/display/intel_dpll_mgr.c shared_dpll[id].hw_state = *pll_state; pll_state 2572 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *pll_state) pll_state 2604 drivers/gpu/drm/i915/display/intel_dpll_mgr.c memset(pll_state, 0, sizeof(*pll_state)); pll_state 2606 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll_state->cfgcr0 = cfgcr0; pll_state 2607 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll_state->cfgcr1 = cfgcr1; pll_state 2698 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *pll_state) pll_state 2712 drivers/gpu/drm/i915/display/intel_dpll_mgr.c memset(pll_state, 0, sizeof(*pll_state)); pll_state 2715 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll_state)) { pll_state 2804 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll_state->mg_pll_div0 = (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) | pll_state 2808 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll_state->mg_pll_div1 = MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) | pll_state 2813 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll_state->mg_pll_lf = MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) | pll_state 2819 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll_state->mg_pll_frac_lock = MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 | pll_state 2825 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll_state->mg_pll_frac_lock |= MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN; pll_state 2827 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll_state->mg_pll_ssc = (use_ssc ? MG_PLL_SSC_EN : 0) | pll_state 2834 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll_state->mg_pll_tdc_coldst_bias = MG_PLL_TDC_COLDST_COLDSTART | pll_state 2840 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll_state->mg_pll_bias = MG_PLL_BIAS_BIAS_GB_SEL(3) | pll_state 2849 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART; pll_state 2850 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll_state->mg_pll_bias_mask = 0; pll_state 2852 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll_state->mg_pll_tdc_coldst_bias_mask = -1U; pll_state 2853 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll_state->mg_pll_bias_mask = -1U; pll_state 2856 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll_state->mg_pll_tdc_coldst_bias &= pll_state->mg_pll_tdc_coldst_bias_mask; pll_state 2857 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask; pll_state 248 sound/soc/codecs/wm8580.c struct pll_state a; pll_state 249 sound/soc/codecs/wm8580.c struct pll_state b; pll_state 466 sound/soc/codecs/wm8580.c struct pll_state *state;