pll_settings 95 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c &pipes[i].pll_settings); pll_settings 196 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c struct pll_settings *pll_settings, pll_settings 209 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->adjusted_pix_clk_100hz, pll_settings 228 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->adjusted_pix_clk_100hz) pll_settings 230 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->adjusted_pix_clk_100hz pll_settings 231 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c : pll_settings->adjusted_pix_clk_100hz - pll_settings 236 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->reference_freq = calc_pll_cs->ref_freq_khz; pll_settings 237 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->reference_divider = ref_divider; pll_settings 238 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->feedback_divider = feedback_divider; pll_settings 239 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->fract_feedback_divider = fract_feedback_divider; pll_settings 240 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->pix_clk_post_divider = post_divider; pll_settings 241 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->calculated_pix_clk_100hz = pll_settings 243 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->vco_freq = pll_settings 252 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c struct pll_settings *pll_settings, pll_settings 265 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) / pll_settings 280 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings, pll_settings 294 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c struct pll_settings *pll_settings) pll_settings 302 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c if (pll_settings->adjusted_pix_clk_100hz == 0) { pll_settings 309 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c if (pll_settings->pix_clk_post_divider) { pll_settings 310 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c min_post_divider = pll_settings->pix_clk_post_divider; pll_settings 311 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c max_post_divider = pll_settings->pix_clk_post_divider; pll_settings 314 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c if (min_post_divider * pll_settings->adjusted_pix_clk_100hz < pll_settings 317 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->adjusted_pix_clk_100hz; pll_settings 319 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->adjusted_pix_clk_100hz) < pll_settings 325 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c if (max_post_divider * pll_settings->adjusted_pix_clk_100hz pll_settings 328 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->adjusted_pix_clk_100hz; pll_settings 337 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c if (pll_settings->reference_divider) { pll_settings 338 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c min_ref_divider = pll_settings->reference_divider; pll_settings 339 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c max_ref_divider = pll_settings->reference_divider; pll_settings 382 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings, pll_settings 398 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c struct pll_settings *pll_settings) pll_settings 449 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz; pll_settings 450 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->adjusted_pix_clk_100hz = pll_settings 452 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->reference_divider = pll_settings 454 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->pix_clk_post_divider = pll_settings 476 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c struct pll_settings *pll_settings, pll_settings 487 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->use_external_clk = (field > 1); pll_settings 498 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->adjusted_pix_clk_100hz / 10); pll_settings 501 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->ss_percentage = ss_data->percentage; pll_settings 505 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) { pll_settings 510 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->actual_pix_clk_100hz = pll_settings 512 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->adjusted_pix_clk_100hz = pll_settings 516 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->adjusted_pix_clk_100hz = 1000000; pll_settings 525 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings); pll_settings 531 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings); pll_settings 538 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c struct pll_settings *pll_settings, pll_settings 560 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz; pll_settings 561 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->adjusted_pix_clk_100hz = actual_pixel_clock_100hz; pll_settings 562 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; pll_settings 568 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c struct pll_settings *pll_settings) pll_settings 574 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c if (pix_clk_params == NULL || pll_settings == NULL pll_settings 581 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c memset(pll_settings, 0, sizeof(*pll_settings)); pll_settings 585 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10; pll_settings 586 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10; pll_settings 587 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->actual_pix_clk_100hz = pll_settings 593 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings, pix_clk_params); pll_settings 601 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c struct pll_settings *pll_settings) pll_settings 606 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c if (pix_clk_params == NULL || pll_settings == NULL pll_settings 613 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c memset(pll_settings, 0, sizeof(*pll_settings)); pll_settings 617 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10; pll_settings 618 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10; pll_settings 619 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->actual_pix_clk_100hz = pll_settings 625 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings, pix_clk_params); pll_settings 647 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c const struct pll_settings *pll_settings, pll_settings 664 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c if (pll_settings == NULL) pll_settings 672 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->fract_feedback_divider, 1000000); pll_settings 673 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider); pll_settings 695 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->reference_freq * 1000, pll_settings 696 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->reference_divider * ss_data->modulation_freq_hz); pll_settings 713 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c enum signal_type signal, struct pll_settings *pll_settings) pll_settings 722 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->calculated_pix_clk_100hz / 10); pll_settings 727 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c if (ss_data != NULL && pll_settings->ss_percentage != 0) { pll_settings 728 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c if (calculate_ss(pll_settings, ss_data, &d_s_data)) { pll_settings 844 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c struct pll_settings *pll_settings) pll_settings 861 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; pll_settings 865 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c bp_pc_params.reference_divider = pll_settings->reference_divider; pll_settings 866 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c bp_pc_params.feedback_divider = pll_settings->feedback_divider; pll_settings 868 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->fract_feedback_divider; pll_settings 870 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->pix_clk_post_divider; pll_settings 872 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->use_external_clk; pll_settings 888 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings)) pll_settings 903 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c struct pll_settings *pll_settings) pll_settings 912 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c unsigned clock_100hz = pll_settings->actual_pix_clk_100hz; pll_settings 935 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; pll_settings 941 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->use_external_clk; pll_settings 943 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c !pll_settings->use_external_clk; pll_settings 1054 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c struct pll_settings *pll_settings) pll_settings 1056 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings); pll_settings 1180 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->pll_settings.feedback_divider; pll_settings 1190 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->pll_settings.ss_percentage; pll_settings 1297 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &pipe_ctx->pll_settings)) { pll_settings 850 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c &pipe_ctx->pll_settings); pll_settings 757 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->pll_settings)) { pll_settings 1028 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c &pipe_ctx->pll_settings); pll_settings 563 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &pipe_ctx->pll_settings)) { pll_settings 1486 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c &pipe_ctx->pll_settings); pll_settings 164 drivers/gpu/drm/amd/display/dc/inc/clock_source.h struct pixel_clk_params *, struct pll_settings *); pll_settings 168 drivers/gpu/drm/amd/display/dc/inc/clock_source.h struct pll_settings *); pll_settings 297 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct pll_settings pll_settings;