pll_read 239 arch/c6x/platforms/pll.c v = pll_read(pll, clk->div); pll_read 275 arch/c6x/platforms/pll.c ctrl = pll_read(pll, PLLCTL); pll_read 284 arch/c6x/platforms/pll.c mult = pll_read(pll, PLLM); pll_read 288 arch/c6x/platforms/pll.c prediv = pll_read(pll, PLLPRE); pll_read 295 arch/c6x/platforms/pll.c postdiv = pll_read(pll, PLLPOST); pll_read 2012 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c atom_card_info->pll_read = cail_pll_read; pll_read 317 drivers/gpu/drm/amd/amdgpu/atom.c val = gctx->card->pll_read(gctx->card, idx); pll_read 124 drivers/gpu/drm/amd/amdgpu/atom.h uint32_t (* pll_read)(struct card_info *, uint32_t); /* filled by driver */ pll_read 368 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0); pll_read 378 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0); pll_read 390 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1); pll_read 399 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1); pll_read 494 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c dec = pll_read(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1); pll_read 497 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c frac = pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1); pll_read 498 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c frac |= ((pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) & pll_read 500 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c frac |= ((pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1) & pll_read 540 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c cached->pll_out_div = pll_read(pll_10nm->mmio + pll_read 544 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c cmn_clk_cfg0 = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0); pll_read 548 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c cmn_clk_cfg1 = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); pll_read 563 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c val = pll_read(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE); pll_read 571 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c val = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1); pll_read 185 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c val = pll_read(base + pll_read 198 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c val = pll_read(base + pll_read 635 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c dec_start = pll_read(base + REG_DSI_14nm_PHY_PLL_DEC_START); pll_read 640 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c div_frac_start = (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3) pll_read 642 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c div_frac_start |= (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2) pll_read 644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c div_frac_start |= pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1) pll_read 689 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift; pll_read 731 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); pll_read 802 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c data = pll_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); pll_read 98 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c val = pll_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS); pll_read 184 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c sdm_cfg1 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1); pll_read 266 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) & pll_read 271 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0); pll_read 275 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0), pll_read 281 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1), pll_read 284 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c sdm2 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2), pll_read 286 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c sdm3 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3), pll_read 446 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG); pll_read 448 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG); pll_read 449 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c cached_state->byte_mux = pll_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG); pll_read 93 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_RDY); pll_read 126 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2); pll_read 133 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); pll_read 143 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); pll_read 171 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c status = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0); pll_read 174 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c fb_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1); pll_read 176 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c temp = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2) & 0x07; pll_read 180 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c ref_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); pll_read 224 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c div = pll_read(bytediv->reg) & 0xff; pll_read 270 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(bytediv->reg); pll_read 306 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); pll_read 310 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); pll_read 344 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10); pll_read 346 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_9); pll_read 348 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); pll_read 298 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val = pll_read(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B); pll_read 307 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val = pll_read(pll, REG_HDMI_8960_PHY_PLL_STATUS0); pll_read 349 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val = pll_read(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B); pll_read 323 drivers/gpu/drm/radeon/atom.c val = gctx->card->pll_read(gctx->card, idx); pll_read 121 drivers/gpu/drm/radeon/atom.h uint32_t (* pll_read)(struct card_info *, uint32_t); /* filled by driver */ pll_read 996 drivers/gpu/drm/radeon/radeon_device.c atom_card_info->pll_read = cail_pll_read;