pll_rate 221 arch/arm/mach-omap1/clock.c ck_dpll1_p->rate = ptr->pll_rate; pll_rate 18 arch/arm/mach-omap1/opp.h unsigned long pll_rate; pll_rate 451 arch/mips/ralink/mt7620.c mt7620_get_cpu_rate(unsigned long pll_rate) pll_rate 463 arch/mips/ralink/mt7620.c return mt7620_calc_rate(pll_rate, mul, div); pll_rate 475 arch/mips/ralink/mt7620.c mt7620_get_dram_rate(unsigned long pll_rate) pll_rate 478 arch/mips/ralink/mt7620.c return pll_rate / 4; pll_rate 480 arch/mips/ralink/mt7620.c return pll_rate / 3; pll_rate 509 arch/mips/ralink/mt7620.c unsigned long pll_rate; pll_rate 535 arch/mips/ralink/mt7620.c pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate); pll_rate 537 arch/mips/ralink/mt7620.c cpu_rate = mt7620_get_cpu_rate(pll_rate); pll_rate 538 arch/mips/ralink/mt7620.c dram_rate = mt7620_get_dram_rate(pll_rate); pll_rate 546 arch/mips/ralink/mt7620.c RINT(pll_rate), RFRAC(pll_rate)); pll_rate 179 arch/unicore32/kernel/clock.c u32 pll_rate, divstatus = readl(PM_DIVSTATUS); pll_rate 186 arch/unicore32/kernel/clock.c pll_rate = mclk_clk_table[i].prate; pll_rate 201 arch/unicore32/kernel/clock.c writel(pll_rate, PM_PLLSYSCFG); pll_rate 419 drivers/clk/clk-cdce925.c long pll_rate = clk_round_rate(pll, target_rate); pll_rate 423 drivers/clk/clk-cdce925.c if (pll_rate <= 0) pll_rate 425 drivers/clk/clk-cdce925.c actual_rate = pll_rate / pdiv_now; pll_rate 70 drivers/clk/spear/clk-vco-pll.c unsigned long prate, int index, unsigned long *pll_rate) pll_rate 78 drivers/clk/spear/clk-vco-pll.c if (pll_rate) pll_rate 79 drivers/clk/spear/clk-vco-pll.c *pll_rate = (rate / (1 << rtbl[index].p)) * 10000; pll_rate 426 drivers/gpu/drm/mediatek/mtk_dpi.c unsigned long pll_rate; pll_rate 432 drivers/gpu/drm/mediatek/mtk_dpi.c pll_rate = vm.pixelclock * factor; pll_rate 435 drivers/gpu/drm/mediatek/mtk_dpi.c pll_rate, vm.pixelclock); pll_rate 437 drivers/gpu/drm/mediatek/mtk_dpi.c clk_set_rate(dpi->tvd_clk, pll_rate); pll_rate 438 drivers/gpu/drm/mediatek/mtk_dpi.c pll_rate = clk_get_rate(dpi->tvd_clk); pll_rate 440 drivers/gpu/drm/mediatek/mtk_dpi.c vm.pixelclock = pll_rate / factor; pll_rate 445 drivers/gpu/drm/mediatek/mtk_dpi.c pll_rate, vm.pixelclock); pll_rate 36 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h unsigned long pll_rate; pll_rate 199 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c hdmi_phy->pll_rate = rate; pll_rate 299 drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c return hdmi_phy->pll_rate; pll_rate 34 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c static const struct pll_rate freqtbl[] = { pll_rate 48 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c static const struct pll_rate *find_rate(unsigned long rate) pll_rate 61 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c const struct pll_rate *pll_rate = find_rate(lvds_pll->pixclk); pll_rate 64 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c DBG("pixclk=%lu (%lu)", lvds_pll->pixclk, pll_rate->rate); pll_rate 66 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c if (WARN_ON(!pll_rate)) pll_rate 71 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c for (i = 0; pll_rate->conf[i].reg; i++) pll_rate 72 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate->conf[i].val); pll_rate 104 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c const struct pll_rate *pll_rate = find_rate(rate); pll_rate 105 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c return pll_rate->rate; pll_rate 40 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c static const struct pll_rate freqtbl[] = { pll_rate 357 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c static const struct pll_rate *find_rate(unsigned long rate) pll_rate 379 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c const struct pll_rate *pll_rate = find_rate(rate); pll_rate 381 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c return pll_rate->rate; pll_rate 388 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c const struct pll_rate *pll_rate = find_rate(rate); pll_rate 393 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c for (i = 0; i < pll_rate->num_reg; i++) pll_rate 394 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, pll_rate->conf[i].reg, pll_rate->conf[i].val); pll_rate 1526 drivers/mfd/db8500-prcmu.c rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); pll_rate 1528 drivers/mfd/db8500-prcmu.c rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); pll_rate 1530 drivers/mfd/db8500-prcmu.c rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); pll_rate 1558 drivers/mfd/db8500-prcmu.c rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX); pll_rate 1570 drivers/mfd/db8500-prcmu.c rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV); pll_rate 1597 drivers/mfd/db8500-prcmu.c return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), pll_rate 1622 drivers/mfd/db8500-prcmu.c return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); pll_rate 1624 drivers/mfd/db8500-prcmu.c return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); pll_rate 1628 drivers/mfd/db8500-prcmu.c return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); pll_rate 1630 drivers/mfd/db8500-prcmu.c return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), pll_rate 1646 drivers/mfd/db8500-prcmu.c return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch); pll_rate 1648 drivers/mfd/db8500-prcmu.c return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch); pll_rate 1650 drivers/mfd/db8500-prcmu.c return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch); pll_rate 1786 drivers/mfd/db8500-prcmu.c src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), pll_rate 1954 drivers/mfd/db8500-prcmu.c div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ, pll_rate 792 sound/pci/ctxfi/ctatc.c unsigned int pitch, rsr = atc->pll_rate; pll_rate 851 sound/pci/ctxfi/ctatc.c atc->pll_rate = err ? 0 : rate; pll_rate 886 sound/pci/ctxfi/ctatc.c if ((rate != atc->pll_rate) && (32000 != rate)) pll_rate 1132 sound/pci/ctxfi/ctatc.c if (atc->pll_rate != atc->rsr) pll_rate 78 sound/pci/ctxfi/ctatc.h unsigned int pll_rate; /* current rate of Phase Lock Loop */ pll_rate 429 sound/soc/codecs/adau17x1.c unsigned int pll_rate; pll_rate 439 sound/soc/codecs/adau17x1.c pll_rate = 48000 * 1024; pll_rate 448 sound/soc/codecs/adau17x1.c pll_rate = 44100 * 1024; pll_rate 455 sound/soc/codecs/adau17x1.c clk_get_rate(adau->mclk), pll_rate); pll_rate 748 sound/soc/codecs/pcm512x.c unsigned long pll_rate) pll_rate 759 sound/soc/codecs/pcm512x.c common = gcd(pll_rate, pllin_rate); pll_rate 761 sound/soc/codecs/pcm512x.c pll_rate, pllin_rate, common); pll_rate 762 sound/soc/codecs/pcm512x.c num = pll_rate / common; pll_rate 786 sound/soc/codecs/pcm512x.c pcm512x->real_pll = pll_rate; pll_rate 816 sound/soc/codecs/pcm512x.c pcm512x->real_pll = pll_rate; pll_rate 835 sound/soc/codecs/pcm512x.c K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate); pll_rate 892 sound/soc/codecs/pcm512x.c unsigned long pll_rate; pll_rate 945 sound/soc/codecs/pcm512x.c pll_rate = 4 * sck_rate; pll_rate 947 sound/soc/codecs/pcm512x.c ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate); pll_rate 30 sound/soc/samsung/snow.c static const unsigned int pll_rate[] = { pll_rate 79 sound/soc/samsung/snow.c for (i = 0; i < ARRAY_SIZE(pll_rate); i++) { pll_rate 80 sound/soc/samsung/snow.c if ((pll_rate[i] - rclk * psr) <= 2) { pll_rate 81 sound/soc/samsung/snow.c freq = pll_rate[i]; pll_rate 107 sound/soc/tegra/tegra_asoc_utils.c const int pll_rate = 73728000; pll_rate 119 sound/soc/tegra/tegra_asoc_utils.c err = clk_set_rate(data->clk_pll_a, pll_rate); pll_rate 151 sound/soc/tegra/tegra_asoc_utils.c data->set_baseclock = pll_rate;