pll_clock         274 arch/m68k/q40/config.c 	pll->pll_clock = 125829120;
pll_clock         512 drivers/ata/pata_pdc2027x.c static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx)
pll_clock         516 drivers/ata/pata_pdc2027x.c 	long pll_clock_khz = pll_clock / 1000;
pll_clock         604 drivers/ata/pata_pdc2027x.c 	long pll_clock, usec_elapsed;
pll_clock         632 drivers/ata/pata_pdc2027x.c 	pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 *
pll_clock         636 drivers/ata/pata_pdc2027x.c 	PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
pll_clock         638 drivers/ata/pata_pdc2027x.c 	return pll_clock;
pll_clock         648 drivers/ata/pata_pdc2027x.c 	long pll_clock;
pll_clock         656 drivers/ata/pata_pdc2027x.c 	pll_clock = pdc_detect_pll_input_clock(host);
pll_clock         658 drivers/ata/pata_pdc2027x.c 	dev_info(host->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
pll_clock         661 drivers/ata/pata_pdc2027x.c 	pdc_adjust_pll(host, pll_clock, board_idx);
pll_clock          26 drivers/clk/h8300/clk-h8s2678.c #define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw)
pll_clock          31 drivers/clk/h8300/clk-h8s2678.c 	struct pll_clock *pll_clock = to_pll_clock(hw);
pll_clock          32 drivers/clk/h8300/clk-h8s2678.c 	int mul = 1 << (readb(pll_clock->pllcr) & 3);
pll_clock          65 drivers/clk/h8300/clk-h8s2678.c 	struct pll_clock *pll_clock = to_pll_clock(hw);
pll_clock          69 drivers/clk/h8300/clk-h8s2678.c 	val = readb(pll_clock->sckcr);
pll_clock          71 drivers/clk/h8300/clk-h8s2678.c 	writeb(val, pll_clock->sckcr);
pll_clock          72 drivers/clk/h8300/clk-h8s2678.c 	val = readb(pll_clock->pllcr);
pll_clock          75 drivers/clk/h8300/clk-h8s2678.c 	writeb(val, pll_clock->pllcr);
pll_clock          91 drivers/clk/h8300/clk-h8s2678.c 	struct pll_clock *pll_clock;
pll_clock         102 drivers/clk/h8300/clk-h8s2678.c 	pll_clock = kzalloc(sizeof(*pll_clock), GFP_KERNEL);
pll_clock         103 drivers/clk/h8300/clk-h8s2678.c 	if (!pll_clock)
pll_clock         106 drivers/clk/h8300/clk-h8s2678.c 	pll_clock->sckcr = of_iomap(node, 0);
pll_clock         107 drivers/clk/h8300/clk-h8s2678.c 	if (pll_clock->sckcr == NULL) {
pll_clock         112 drivers/clk/h8300/clk-h8s2678.c 	pll_clock->pllcr = of_iomap(node, 1);
pll_clock         113 drivers/clk/h8300/clk-h8s2678.c 	if (pll_clock->pllcr == NULL) {
pll_clock         124 drivers/clk/h8300/clk-h8s2678.c 	pll_clock->hw.init = &init;
pll_clock         126 drivers/clk/h8300/clk-h8s2678.c 	ret = clk_hw_register(NULL, &pll_clock->hw);
pll_clock         133 drivers/clk/h8300/clk-h8s2678.c 	of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clock->hw);
pll_clock         137 drivers/clk/h8300/clk-h8s2678.c 	iounmap(pll_clock->pllcr);
pll_clock         139 drivers/clk/h8300/clk-h8s2678.c 	iounmap(pll_clock->sckcr);
pll_clock         141 drivers/clk/h8300/clk-h8s2678.c 	kfree(pll_clock);
pll_clock         824 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c 	u32 pll_clock = mode->clock;
pll_clock         854 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c 	amdgpu_pll_compute(pll, amdgpu_crtc->adjusted_clock, &pll_clock,
pll_clock         507 drivers/gpu/drm/i915/display/intel_display.h int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
pll_clock        1070 drivers/gpu/drm/radeon/atombios_crtc.c 	u32 pll_clock = mode->clock;
pll_clock        1103 drivers/gpu/drm/radeon/atombios_crtc.c 		radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
pll_clock        1106 drivers/gpu/drm/radeon/atombios_crtc.c 		radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
pll_clock        1109 drivers/gpu/drm/radeon/atombios_crtc.c 		radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
pll_clock         788 drivers/gpu/drm/vc4/vc4_dsi.c 	unsigned long pll_clock = pixel_clock_hz * dsi->divider;
pll_clock         795 drivers/gpu/drm/vc4/vc4_dsi.c 		if (parent_rate / divider < pll_clock) {
pll_clock         804 drivers/gpu/drm/vc4/vc4_dsi.c 	pll_clock = parent_rate / divider;
pll_clock         805 drivers/gpu/drm/vc4/vc4_dsi.c 	pixel_clock_hz = pll_clock / dsi->divider;
pll_clock          63 include/uapi/linux/rtc.h 	long pll_clock;     /* base PLL frequency */