pll3               55 drivers/clk/qcom/gcc-ipq806x.c static struct clk_pll pll3 = {
pll3             2756 drivers/clk/qcom/gcc-ipq806x.c 	[PLL3] = &pll3.clkr,
pll3               28 drivers/clk/qcom/gcc-msm8960.c static struct clk_pll pll3 = {
pll3             3142 drivers/clk/qcom/gcc-msm8960.c 	[PLL3] = &pll3.clkr,
pll3             3370 drivers/clk/qcom/gcc-msm8960.c 	[PLL3] = &pll3.clkr,
pll3             1660 drivers/gpu/drm/i915/display/intel_ddi.c 	if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
pll3             12810 drivers/gpu/drm/i915/display/intel_display.c 	PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
pll3             1562 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	temp |= pll->state.hw_state.pll3;
pll3             1686 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3));
pll3             1687 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
pll3             1846 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
pll3             1930 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		      hw_state->pll3,
pll3              195 drivers/gpu/drm/i915/display/intel_dpll_mgr.h 	u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
pll3              367 drivers/gpu/drm/tegra/sor.c 	unsigned int pll3;
pll3             1732 drivers/gpu/drm/tegra/sor.c 	value = tegra_sor_readl(sor, sor->soc->regs->pll3);
pll3             1734 drivers/gpu/drm/tegra/sor.c 	tegra_sor_writel(sor, value, sor->soc->regs->pll3);
pll3             2462 drivers/gpu/drm/tegra/sor.c 	value = tegra_sor_readl(sor, sor->soc->regs->pll3);
pll3             2464 drivers/gpu/drm/tegra/sor.c 	tegra_sor_writel(sor, value, sor->soc->regs->pll3);
pll3             2664 drivers/gpu/drm/tegra/sor.c 	value = tegra_sor_readl(sor, sor->soc->regs->pll3);
pll3             2673 drivers/gpu/drm/tegra/sor.c 	tegra_sor_writel(sor, value, sor->soc->regs->pll3);
pll3             3041 drivers/gpu/drm/tegra/sor.c 	.pll3 = 0x1a,
pll3             3066 drivers/gpu/drm/tegra/sor.c 	.pll3 = 0x1a,
pll3             3110 drivers/gpu/drm/tegra/sor.c 	.pll3 = 0x166,
pll3             3152 drivers/gpu/drm/tegra/sor.c 	.pll3 = 0x16c,