pll2 772 arch/arm/mach-davinci/dm365.c void __iomem *pll1, *pll2, *psc; pll2 780 arch/arm/mach-davinci/dm365.c pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K); pll2 781 arch/arm/mach-davinci/dm365.c dm365_pll2_init(NULL, pll2, NULL); pll2 170 drivers/clk/mxs/clk-imx28.c clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); pll2 108 drivers/clk/qcom/mmcc-msm8960.c static struct clk_pll pll2 = { pll2 2717 drivers/clk/qcom/mmcc-msm8960.c [PLL2] = &pll2.clkr, pll2 2893 drivers/clk/qcom/mmcc-msm8960.c [PLL2] = &pll2.clkr, pll2 285 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c u32 *pll1, u32 *pll2) pll2 294 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c *pll2 = hibmc_pll_table[i].pll2_config_value; pll2 301 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c *pll2 = CRT_PLL2_HS_25MHZ; pll2 317 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c u32 pll2; /* bit[63:32] of PLL */ pll2 323 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c get_pll_config(x, y, &pll1, &pll2); pll2 324 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c writel(pll2, priv->mmio + CRT_PLL2_HS); pll2 1661 drivers/gpu/drm/i915/display/intel_ddi.c clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK; pll2 12809 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.pll2); pll2 1556 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll2; pll2 1683 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll2 = I915_READ(BXT_PORT_PLL(phy, ch, 2)); pll2 1684 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; pll2 1843 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dpll_hw_state->pll2 = clk_div->m2_frac; pll2 1929 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll2, pll2 195 drivers/gpu/drm/i915/display/intel_dpll_mgr.h u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; pll2 132 drivers/gpu/drm/nouveau/dispnv04/hw.c uint32_t pll2, struct nvkm_pll_vals *pllvals) pll2 143 drivers/gpu/drm/nouveau/dispnv04/hw.c pllvals->NM1 = pll2 & 0xffff; pll2 146 drivers/gpu/drm/nouveau/dispnv04/hw.c pllvals->NM2 = pll2 >> 16; pll2 149 drivers/gpu/drm/nouveau/dispnv04/hw.c if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) pll2 150 drivers/gpu/drm/nouveau/dispnv04/hw.c pllvals->NM2 = pll2 & 0xffff; pll2 169 drivers/gpu/drm/nouveau/dispnv04/hw.c uint32_t reg1, pll1, pll2 = 0; pll2 179 drivers/gpu/drm/nouveau/dispnv04/hw.c pll2 = nvif_rd32(device, reg1 + 4); pll2 183 drivers/gpu/drm/nouveau/dispnv04/hw.c pll2 = nvif_rd32(device, reg2); pll2 192 drivers/gpu/drm/nouveau/dispnv04/hw.c pll2 = 0; pll2 195 drivers/gpu/drm/nouveau/dispnv04/hw.c pll2 = 0; pll2 198 drivers/gpu/drm/nouveau/dispnv04/hw.c nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals); pll2 208 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; pll2 218 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c pll2 = 0; pll2 227 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c pll2 |= 0x011f; pll2 233 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c if (oldpll1 == pll1 && oldpll2 == pll2) pll2 266 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c nvkm_wr32(device, reg2, pll2); pll2 366 drivers/gpu/drm/tegra/sor.c unsigned int pll2; pll2 1226 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); pll2 1228 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); pll2 1236 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); pll2 1239 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); pll2 1727 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); pll2 1729 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); pll2 1740 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); pll2 1744 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); pll2 1750 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); pll2 1757 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); pll2 1760 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); pll2 1773 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); pll2 1776 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); pll2 1794 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); pll2 1796 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); pll2 1806 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); pll2 1808 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); pll2 1813 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); pll2 1815 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); pll2 2456 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); pll2 2458 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); pll2 2471 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); pll2 2473 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); pll2 2477 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll2); pll2 2480 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll2); pll2 3040 drivers/gpu/drm/tegra/sor.c .pll2 = 0x19, pll2 3065 drivers/gpu/drm/tegra/sor.c .pll2 = 0x19, pll2 3109 drivers/gpu/drm/tegra/sor.c .pll2 = 0x165, pll2 3151 drivers/gpu/drm/tegra/sor.c .pll2 = 0x16b, pll2 116 drivers/mfd/sm501.c static unsigned long decode_div(unsigned long pll2, unsigned long val, pll2 121 drivers/mfd/sm501.c pll2 = 288 * MHZ; pll2 123 drivers/mfd/sm501.c return pll2 / div_tab[(val >> lshft) & mask]; pll2 140 drivers/mfd/sm501.c unsigned long pll2 = 0; pll2 144 drivers/mfd/sm501.c pll2 = 336 * MHZ; pll2 147 drivers/mfd/sm501.c pll2 = 288 * MHZ; pll2 150 drivers/mfd/sm501.c pll2 = 240 * MHZ; pll2 153 drivers/mfd/sm501.c pll2 = 192 * MHZ; pll2 157 drivers/mfd/sm501.c sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; pll2 160 drivers/mfd/sm501.c sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; pll2 167 drivers/mfd/sm501.c fmt_freq(pll2), sdclk0, sdclk1); pll2 175 drivers/mfd/sm501.c fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)), pll2 176 drivers/mfd/sm501.c fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)), pll2 177 drivers/mfd/sm501.c fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)), pll2 178 drivers/mfd/sm501.c fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15))); pll2 184 drivers/mfd/sm501.c fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)), pll2 185 drivers/mfd/sm501.c fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)), pll2 186 drivers/mfd/sm501.c fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)), pll2 187 drivers/mfd/sm501.c fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15))); pll2 132 sound/soc/codecs/tscs454.c struct pll pll2; pll2 293 sound/soc/codecs/tscs454.c pll_init(&tscs454->pll2, 2); pll2 445 sound/soc/codecs/tscs454.c mutex_lock(&tscs454->pll2.lock); pll2 467 sound/soc/codecs/tscs454.c mutex_unlock(&tscs454->pll2.lock); pll2 699 sound/soc/codecs/tscs454.c mutex_lock(&tscs454->pll2.lock); pll2 700 sound/soc/codecs/tscs454.c users = tscs454->pll2.users; pll2 701 sound/soc/codecs/tscs454.c mutex_unlock(&tscs454->pll2.lock); pll2 3198 sound/soc/codecs/tscs454.c aif->pll = &tscs454->pll2; pll2 3214 sound/soc/codecs/tscs454.c tscs454->internal_rate.pll = &tscs454->pll2;