pll1 734 arch/arm/mach-davinci/dm355.c void __iomem *pll1, *psc; pll1 740 arch/arm/mach-davinci/dm355.c pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); pll1 741 arch/arm/mach-davinci/dm355.c dm355_pll1_init(NULL, pll1, NULL); pll1 772 arch/arm/mach-davinci/dm365.c void __iomem *pll1, *pll2, *psc; pll1 777 arch/arm/mach-davinci/dm365.c pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); pll1 778 arch/arm/mach-davinci/dm365.c dm365_pll1_init(NULL, pll1, NULL); pll1 670 arch/arm/mach-davinci/dm644x.c void __iomem *pll1, *psc; pll1 676 arch/arm/mach-davinci/dm644x.c pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); pll1 677 arch/arm/mach-davinci/dm644x.c dm644x_pll1_init(NULL, pll1, NULL); pll1 653 arch/arm/mach-davinci/dm646x.c void __iomem *pll1, *psc; pll1 660 arch/arm/mach-davinci/dm646x.c pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K); pll1 661 arch/arm/mach-davinci/dm646x.c dm646x_pll1_init(NULL, pll1, NULL); pll1 169 drivers/clk/mxs/clk-imx28.c clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); pll1 136 drivers/clk/sirf/clk-atlas6.c for (i = pll1; i < maxclk; i++) { pll1 135 drivers/clk/sirf/clk-prima2.c for (i = pll1; i < maxclk; i++) { pll1 285 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c u32 *pll1, u32 *pll2) pll1 293 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c *pll1 = hibmc_pll_table[i].pll1_config_value; pll1 300 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c *pll1 = CRT_PLL1_HS_25MHZ; pll1 316 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c u32 pll1; /* bit[31:0] of PLL */ pll1 323 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c get_pll_config(x, y, &pll1, &pll2); pll1 325 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c set_vclock_hisilicon(dev, pll1); pll1 1662 drivers/gpu/drm/i915/display/intel_ddi.c clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; pll1 12808 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.pll1); pll1 1550 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll1; pll1 1680 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1)); pll1 1681 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll1 &= PORT_PLL_N_MASK; pll1 1842 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n); pll1 1928 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll1, pll1 195 drivers/gpu/drm/i915/display/intel_dpll_mgr.h u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; pll1 131 drivers/gpu/drm/nouveau/dispnv04/hw.c nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, pll1 139 drivers/gpu/drm/nouveau/dispnv04/hw.c pllvals->log2P = (pll1 >> 16) & 0x7; pll1 145 drivers/gpu/drm/nouveau/dispnv04/hw.c if (!(pll1 & 0x1100)) pll1 148 drivers/gpu/drm/nouveau/dispnv04/hw.c pllvals->NM1 = pll1 & 0xffff; pll1 153 drivers/gpu/drm/nouveau/dispnv04/hw.c if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { pll1 154 drivers/gpu/drm/nouveau/dispnv04/hw.c pllvals->M2 = (pll1 >> 4) & 0x7; pll1 155 drivers/gpu/drm/nouveau/dispnv04/hw.c pllvals->N2 = ((pll1 >> 21) & 0x18) | pll1 156 drivers/gpu/drm/nouveau/dispnv04/hw.c ((pll1 >> 19) & 0x7); pll1 169 drivers/gpu/drm/nouveau/dispnv04/hw.c uint32_t reg1, pll1, pll2 = 0; pll1 177 drivers/gpu/drm/nouveau/dispnv04/hw.c pll1 = nvif_rd32(device, reg1); pll1 198 drivers/gpu/drm/nouveau/dispnv04/hw.c nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals); pll1 207 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; pll1 216 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | pll1 231 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; pll1 233 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c if (oldpll1 == pll1 && oldpll2 == pll2) pll1 267 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c nvkm_wr32(device, reg1, pll1); pll1 37 drivers/gpu/drm/tegra/hdmi.c u32 pll1; pll1 132 drivers/gpu/drm/tegra/hdmi.c .pll1 = SOR_PLL_TMDS_TERM_ENABLE, pll1 147 drivers/gpu/drm/tegra/hdmi.c .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, pll1 165 drivers/gpu/drm/tegra/hdmi.c .pll1 = SOR_PLL_TMDS_TERM_ENABLE, pll1 179 drivers/gpu/drm/tegra/hdmi.c .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, pll1 193 drivers/gpu/drm/tegra/hdmi.c .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, pll1 210 drivers/gpu/drm/tegra/hdmi.c .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), pll1 228 drivers/gpu/drm/tegra/hdmi.c .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | pll1 247 drivers/gpu/drm/tegra/hdmi.c .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | pll1 266 drivers/gpu/drm/tegra/hdmi.c .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7) pll1 289 drivers/gpu/drm/tegra/hdmi.c .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), pll1 307 drivers/gpu/drm/tegra/hdmi.c .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | pll1 326 drivers/gpu/drm/tegra/hdmi.c .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | pll1 345 drivers/gpu/drm/tegra/hdmi.c .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7) pll1 817 drivers/gpu/drm/tegra/hdmi.c tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1); pll1 365 drivers/gpu/drm/tegra/sor.c unsigned int pll1; pll1 1747 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll1); pll1 2656 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll1); pll1 2662 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll1); pll1 3039 drivers/gpu/drm/tegra/sor.c .pll1 = 0x18, pll1 3064 drivers/gpu/drm/tegra/sor.c .pll1 = 0x18, pll1 3108 drivers/gpu/drm/tegra/sor.c .pll1 = 0x164, pll1 3150 drivers/gpu/drm/tegra/sor.c .pll1 = 0x16a, pll1 131 sound/soc/codecs/tscs454.c struct pll pll1; pll1 292 sound/soc/codecs/tscs454.c pll_init(&tscs454->pll1, 1); pll1 444 sound/soc/codecs/tscs454.c mutex_lock(&tscs454->pll1.lock); pll1 468 sound/soc/codecs/tscs454.c mutex_unlock(&tscs454->pll1.lock); pll1 693 sound/soc/codecs/tscs454.c mutex_lock(&tscs454->pll1.lock); pll1 694 sound/soc/codecs/tscs454.c users = tscs454->pll1.users; pll1 695 sound/soc/codecs/tscs454.c mutex_unlock(&tscs454->pll1.lock); pll1 720 sound/soc/codecs/tscs454.c bool pll1; pll1 726 sound/soc/codecs/tscs454.c pll1 = true; pll1 728 sound/soc/codecs/tscs454.c pll1 = false; pll1 730 sound/soc/codecs/tscs454.c msk = pll1 ? FM_PLLCTL_PLL1CLKEN : FM_PLLCTL_PLL2CLKEN; pll1 738 sound/soc/codecs/tscs454.c val = pll1 ? FV_PLL1CLKEN_ENABLE : FV_PLL2CLKEN_ENABLE; pll1 740 sound/soc/codecs/tscs454.c val = pll1 ? FV_PLL1CLKEN_DISABLE : FV_PLL2CLKEN_DISABLE; pll1 746 sound/soc/codecs/tscs454.c pll1 ? 1 : 2, pll1 3196 sound/soc/codecs/tscs454.c aif->pll = &tscs454->pll1; pll1 3212 sound/soc/codecs/tscs454.c tscs454->internal_rate.pll = &tscs454->pll1;