pll0 650 arch/arm/mach-davinci/da850.c void __iomem *pll0; pll0 657 arch/arm/mach-davinci/da850.c pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K); pll0 660 arch/arm/mach-davinci/da850.c da850_pll0_init(NULL, pll0, cfgchip); pll0 84 drivers/bcma/driver_chipcommon_pmu.c u32 pll0, mask; pll0 115 drivers/bcma/driver_chipcommon_pmu.c pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); pll0 116 drivers/bcma/driver_chipcommon_pmu.c freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> pll0 137 drivers/bcma/driver_chipcommon_pmu.c pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; pll0 138 drivers/bcma/driver_chipcommon_pmu.c pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; pll0 139 drivers/bcma/driver_chipcommon_pmu.c bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); pll0 349 drivers/bcma/driver_chipcommon_pmu.c static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) pll0 354 drivers/bcma/driver_chipcommon_pmu.c BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); pll0 366 drivers/bcma/driver_chipcommon_pmu.c tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); pll0 370 drivers/bcma/driver_chipcommon_pmu.c tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF); pll0 374 drivers/bcma/driver_chipcommon_pmu.c tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF); pll0 385 drivers/bcma/driver_chipcommon_pmu.c static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m) pll0 393 drivers/bcma/driver_chipcommon_pmu.c tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF); pll0 168 drivers/clk/mxs/clk-imx28.c clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); pll0 28 drivers/clk/qcom/gcc-ipq806x.c static struct clk_pll pll0 = { pll0 2754 drivers/clk/qcom/gcc-ipq806x.c [PLL0] = &pll0.clkr, pll0 40 drivers/clk/qcom/gcc-mdm9615.c static struct clk_pll pll0 = { pll0 1589 drivers/clk/qcom/gcc-mdm9615.c [PLL0] = &pll0.clkr, pll0 1659 drivers/gpu/drm/i915/display/intel_ddi.c clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22; pll0 12807 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.pll0); pll0 1544 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll0; pll0 1677 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll0 = I915_READ(BXT_PORT_PLL(phy, ch, 0)); pll0 1678 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll0 &= PORT_PLL_M2_MASK; pll0 1841 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dpll_hw_state->pll0 = clk_div->m2_int; pll0 1927 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll0, pll0 195 drivers/gpu/drm/i915/display/intel_dpll_mgr.h u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; pll0 36 drivers/gpu/drm/tegra/hdmi.c u32 pll0; pll0 129 drivers/gpu/drm/tegra/hdmi.c .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | pll0 144 drivers/gpu/drm/tegra/hdmi.c .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | pll0 162 drivers/gpu/drm/tegra/hdmi.c .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | pll0 176 drivers/gpu/drm/tegra/hdmi.c .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | pll0 190 drivers/gpu/drm/tegra/hdmi.c .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | pll0 208 drivers/gpu/drm/tegra/hdmi.c .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | pll0 226 drivers/gpu/drm/tegra/hdmi.c .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | pll0 245 drivers/gpu/drm/tegra/hdmi.c .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | pll0 264 drivers/gpu/drm/tegra/hdmi.c .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | pll0 287 drivers/gpu/drm/tegra/hdmi.c .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | pll0 305 drivers/gpu/drm/tegra/hdmi.c .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | pll0 324 drivers/gpu/drm/tegra/hdmi.c .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | pll0 343 drivers/gpu/drm/tegra/hdmi.c .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | pll0 816 drivers/gpu/drm/tegra/hdmi.c tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0); pll0 364 drivers/gpu/drm/tegra/sor.c unsigned int pll0; pll0 1232 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll0); pll0 1234 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll0); pll0 1738 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll0); pll0 1778 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll0); pll0 1780 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll0); pll0 1801 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll0); pll0 1804 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll0); pll0 2466 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll0); pll0 2469 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll0); pll0 2646 drivers/gpu/drm/tegra/sor.c value = tegra_sor_readl(sor, sor->soc->regs->pll0); pll0 2653 drivers/gpu/drm/tegra/sor.c tegra_sor_writel(sor, value, sor->soc->regs->pll0); pll0 3038 drivers/gpu/drm/tegra/sor.c .pll0 = 0x17, pll0 3063 drivers/gpu/drm/tegra/sor.c .pll0 = 0x17, pll0 3107 drivers/gpu/drm/tegra/sor.c .pll0 = 0x163, pll0 3149 drivers/gpu/drm/tegra/sor.c .pll0 = 0x169,