pll 269 arch/alpha/include/asm/core_marvel.h #define IO7_PLL_RNGA(pll) (((pll) >> 3) & 0x7) pll 270 arch/alpha/include/asm/core_marvel.h #define IO7_PLL_RNGB(pll) (((pll) >> 6) & 0x7) pll 729 arch/arm/mach-davinci/da830.c void __iomem *pll; pll 735 arch/arm/mach-davinci/da830.c pll = ioremap(DA8XX_PLL0_BASE, SZ_4K); pll 737 arch/arm/mach-davinci/da830.c da830_pll_init(NULL, pll, NULL); pll 61 arch/arm/mach-s3c24xx/cpufreq-utils.c clk_set_rate(cfg->mpll, cfg->pll.frequency); pll 119 arch/arm/plat-samsung/include/plat/cpu-freq-core.h struct cpufreq_frequency_table pll; pll 200 arch/c6x/platforms/pll.c static u32 pll_read(struct pll_data *pll, int reg) pll 202 arch/c6x/platforms/pll.c return soc_readl(pll->base + reg); pll 208 arch/c6x/platforms/pll.c struct pll_data *pll; pll 220 arch/c6x/platforms/pll.c pll = clk->parent->pll_data; pll 224 arch/c6x/platforms/pll.c rate = pll->input_rate; pll 239 arch/c6x/platforms/pll.c v = pll_read(pll, clk->div); pll 269 arch/c6x/platforms/pll.c struct pll_data *pll = clk->pll_data; pll 275 arch/c6x/platforms/pll.c ctrl = pll_read(pll, PLLCTL); pll 276 arch/c6x/platforms/pll.c rate = pll->input_rate = clk->parent->rate; pll 283 arch/c6x/platforms/pll.c if (pll->flags & PLL_HAS_MUL) { pll 284 arch/c6x/platforms/pll.c mult = pll_read(pll, PLLM); pll 287 arch/c6x/platforms/pll.c if (pll->flags & PLL_HAS_PRE) { pll 288 arch/c6x/platforms/pll.c prediv = pll_read(pll, PLLPRE); pll 294 arch/c6x/platforms/pll.c if (pll->flags & PLL_HAS_POST) { pll 295 arch/c6x/platforms/pll.c postdiv = pll_read(pll, PLLPOST); pll 312 arch/c6x/platforms/pll.c pll->num, clk->parent->rate / 1000000, pll 316 arch/c6x/platforms/pll.c pll->num, clk->parent->rate / 1000000); pll 170 arch/c6x/platforms/plldata.c struct pll_data *pll = &c6x_soc_pll1; pll 171 arch/c6x/platforms/plldata.c struct clk *sysclks = pll->sysclks; pll 173 arch/c6x/platforms/plldata.c pll->flags = PLL_HAS_PRE | PLL_HAS_MUL; pll 208 arch/c6x/platforms/plldata.c struct pll_data *pll = &c6x_soc_pll1; pll 209 arch/c6x/platforms/plldata.c struct clk *sysclks = pll->sysclks; pll 211 arch/c6x/platforms/plldata.c pll->flags = PLL_HAS_MUL | PLL_HAS_POST; pll 258 arch/c6x/platforms/plldata.c struct pll_data *pll = &c6x_soc_pll1; pll 259 arch/c6x/platforms/plldata.c struct clk *sysclks = pll->sysclks; pll 262 arch/c6x/platforms/plldata.c pll->flags = PLL_HAS_MUL; pll 307 arch/c6x/platforms/plldata.c struct pll_data *pll = &c6x_soc_pll1; pll 308 arch/c6x/platforms/plldata.c struct clk *sysclks = pll->sysclks; pll 310 arch/c6x/platforms/plldata.c pll->flags = PLL_HAS_MUL; pll 356 arch/c6x/platforms/plldata.c struct pll_data *pll = &c6x_soc_pll1; pll 357 arch/c6x/platforms/plldata.c struct clk *sysclks = pll->sysclks; pll 359 arch/c6x/platforms/plldata.c pll->flags = PLL_HAS_MUL; pll 421 arch/c6x/platforms/plldata.c struct pll_data *pll = &c6x_soc_pll1; pll 431 arch/c6x/platforms/plldata.c pll->base = of_iomap(node, 0); pll 432 arch/c6x/platforms/plldata.c if (!pll->base) pll 446 arch/c6x/platforms/plldata.c pll->bypass_delay = val; pll 451 arch/c6x/platforms/plldata.c pll->reset_delay = val; pll 456 arch/c6x/platforms/plldata.c pll->lock_delay = val; pll 24 arch/m68k/coldfire/m5206.c DEFINE_CLK(pll, "pll.0", MCF_CLK); pll 27 arch/m68k/coldfire/m523x.c DEFINE_CLK(pll, "pll.0", MCF_CLK); pll 24 arch/m68k/coldfire/m5249.c DEFINE_CLK(pll, "pll.0", MCF_CLK); pll 24 arch/m68k/coldfire/m525x.c DEFINE_CLK(pll, "pll.0", MCF_CLK); pll 35 arch/m68k/coldfire/m5272.c DEFINE_CLK(pll, "pll.0", MCF_CLK); pll 28 arch/m68k/coldfire/m527x.c DEFINE_CLK(pll, "pll.0", MCF_CLK); pll 29 arch/m68k/coldfire/m528x.c DEFINE_CLK(pll, "pll.0", MCF_CLK); pll 33 arch/m68k/coldfire/m5307.c DEFINE_CLK(pll, "pll.0", MCF_CLK); pll 24 arch/m68k/coldfire/m5407.c DEFINE_CLK(pll, "pll.0", MCF_CLK); pll 33 arch/m68k/coldfire/m54xx.c DEFINE_CLK(pll, "pll.0", MCF_CLK); pll 110 arch/m68k/kernel/time.c struct rtc_pll_info pll; pll 115 arch/m68k/kernel/time.c if (!mach_get_rtc_pll || mach_get_rtc_pll(&pll)) pll 117 arch/m68k/kernel/time.c return copy_to_user(argp, &pll, sizeof pll) ? -EFAULT : 0; pll 124 arch/m68k/kernel/time.c if (copy_from_user(&pll, argp, sizeof(pll))) pll 126 arch/m68k/kernel/time.c return mach_set_rtc_pll(&pll); pll 45 arch/m68k/q40/config.c static int q40_get_rtc_pll(struct rtc_pll_info *pll); pll 46 arch/m68k/q40/config.c static int q40_set_rtc_pll(struct rtc_pll_info *pll); pll 263 arch/m68k/q40/config.c static int q40_get_rtc_pll(struct rtc_pll_info *pll) pll 267 arch/m68k/q40/config.c pll->pll_value = tmp & Q40_RTC_PLL_MASK; pll 269 arch/m68k/q40/config.c pll->pll_value = -pll->pll_value; pll 270 arch/m68k/q40/config.c pll->pll_max = 31; pll 271 arch/m68k/q40/config.c pll->pll_min = -31; pll 272 arch/m68k/q40/config.c pll->pll_posmult = 512; pll 273 arch/m68k/q40/config.c pll->pll_negmult = 256; pll 274 arch/m68k/q40/config.c pll->pll_clock = 125829120; pll 279 arch/m68k/q40/config.c static int q40_set_rtc_pll(struct rtc_pll_info *pll) pll 281 arch/m68k/q40/config.c if (!pll->pll_ctrl) { pll 284 arch/m68k/q40/config.c int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) | pll 49 arch/mips/ar7/clock.c u32 pll; pll 165 arch/mips/ar7/clock.c u32 pll = readl(&clock->pll); pll 169 arch/mips/ar7/clock.c int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1; pll 189 arch/mips/ar7/clock.c if ((pll & PLL_MODE_MASK) == 0) pll 192 arch/mips/ar7/clock.c if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) { pll 230 arch/mips/ar7/clock.c writel(4, &clock->pll); pll 231 arch/mips/ar7/clock.c while (readl(&clock->pll) & PLL_STATUS) pll 233 arch/mips/ar7/clock.c writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll); pll 99 arch/mips/ath79/clock.c u32 pll; pll 105 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); pll 107 arch/mips/ath79/clock.c div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; pll 110 arch/mips/ath79/clock.c div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; pll 113 arch/mips/ath79/clock.c div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; pll 116 arch/mips/ath79/clock.c div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; pll 127 arch/mips/ath79/clock.c u32 pll; pll 131 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); pll 133 arch/mips/ath79/clock.c mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK); pll 134 arch/mips/ath79/clock.c div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2; pll 136 arch/mips/ath79/clock.c ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; pll 137 arch/mips/ath79/clock.c ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; pll 238 arch/mips/ath79/clock.c u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; pll 253 arch/mips/ath79/clock.c pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); pll 254 arch/mips/ath79/clock.c if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { pll 255 arch/mips/ath79/clock.c out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & pll 257 arch/mips/ath79/clock.c pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG); pll 258 arch/mips/ath79/clock.c nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & pll 260 arch/mips/ath79/clock.c nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; pll 261 arch/mips/ath79/clock.c ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & pll 265 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG); pll 266 arch/mips/ath79/clock.c out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & pll 268 arch/mips/ath79/clock.c ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & pll 270 arch/mips/ath79/clock.c nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & pll 272 arch/mips/ath79/clock.c nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & pll 280 arch/mips/ath79/clock.c pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); pll 281 arch/mips/ath79/clock.c if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { pll 282 arch/mips/ath79/clock.c out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & pll 284 arch/mips/ath79/clock.c pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG); pll 285 arch/mips/ath79/clock.c nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & pll 287 arch/mips/ath79/clock.c nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; pll 288 arch/mips/ath79/clock.c ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & pll 292 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG); pll 293 arch/mips/ath79/clock.c out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & pll 295 arch/mips/ath79/clock.c ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & pll 297 arch/mips/ath79/clock.c nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & pll 299 arch/mips/ath79/clock.c nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & pll 356 arch/mips/ath79/clock.c u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; pll 368 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG); pll 369 arch/mips/ath79/clock.c out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & pll 371 arch/mips/ath79/clock.c ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) & pll 373 arch/mips/ath79/clock.c nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) & pll 375 arch/mips/ath79/clock.c frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) & pll 382 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG); pll 383 arch/mips/ath79/clock.c out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & pll 385 arch/mips/ath79/clock.c ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) & pll 387 arch/mips/ath79/clock.c nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) & pll 389 arch/mips/ath79/clock.c frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) & pll 439 arch/mips/ath79/clock.c u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; pll 451 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG); pll 452 arch/mips/ath79/clock.c out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & pll 454 arch/mips/ath79/clock.c ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) & pll 456 arch/mips/ath79/clock.c nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) & pll 458 arch/mips/ath79/clock.c frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) & pll 465 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG); pll 466 arch/mips/ath79/clock.c out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & pll 468 arch/mips/ath79/clock.c ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) & pll 470 arch/mips/ath79/clock.c nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) & pll 472 arch/mips/ath79/clock.c frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) & pll 522 arch/mips/ath79/clock.c u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv; pll 544 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG); pll 545 arch/mips/ath79/clock.c out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & pll 547 arch/mips/ath79/clock.c ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) & pll 550 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG); pll 551 arch/mips/ath79/clock.c nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) & pll 553 arch/mips/ath79/clock.c hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) & pll 555 arch/mips/ath79/clock.c lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) & pll 563 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG); pll 564 arch/mips/ath79/clock.c out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & pll 566 arch/mips/ath79/clock.c ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) & pll 568 arch/mips/ath79/clock.c pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG); pll 569 arch/mips/ath79/clock.c nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) & pll 571 arch/mips/ath79/clock.c hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) & pll 573 arch/mips/ath79/clock.c lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) & pll 457 drivers/bcma/driver_chipcommon_pmu.c u32 pll; pll 464 drivers/bcma/driver_chipcommon_pmu.c pll = BCMA_CC_PMU5356_MAINPLL_PLL0; pll 468 drivers/bcma/driver_chipcommon_pmu.c pll = BCMA_CC_PMU5357_MAINPLL_PLL0; pll 471 drivers/bcma/driver_chipcommon_pmu.c pll = BCMA_CC_PMU4716_MAINPLL_PLL0; pll 475 drivers/bcma/driver_chipcommon_pmu.c return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU); pll 62 drivers/clk/actions/owl-pll.c struct owl_pll *pll = hw_to_owl_pll(hw); pll 63 drivers/clk/actions/owl-pll.c struct owl_pll_hw *pll_hw = &pll->pll_hw; pll 84 drivers/clk/actions/owl-pll.c struct owl_pll *pll = hw_to_owl_pll(hw); pll 85 drivers/clk/actions/owl-pll.c struct owl_pll_hw *pll_hw = &pll->pll_hw; pll 86 drivers/clk/actions/owl-pll.c const struct owl_clk_common *common = &pll->common; pll 112 drivers/clk/actions/owl-pll.c struct owl_pll *pll = hw_to_owl_pll(hw); pll 113 drivers/clk/actions/owl-pll.c struct owl_pll_hw *pll_hw = &pll->pll_hw; pll 114 drivers/clk/actions/owl-pll.c const struct owl_clk_common *common = &pll->common; pll 139 drivers/clk/actions/owl-pll.c struct owl_pll *pll = hw_to_owl_pll(hw); pll 140 drivers/clk/actions/owl-pll.c const struct owl_clk_common *common = &pll->common; pll 142 drivers/clk/actions/owl-pll.c owl_pll_set(common, &pll->pll_hw, true); pll 149 drivers/clk/actions/owl-pll.c struct owl_pll *pll = hw_to_owl_pll(hw); pll 150 drivers/clk/actions/owl-pll.c const struct owl_clk_common *common = &pll->common; pll 152 drivers/clk/actions/owl-pll.c owl_pll_set(common, &pll->pll_hw, false); pll 158 drivers/clk/actions/owl-pll.c struct owl_pll *pll = hw_to_owl_pll(hw); pll 159 drivers/clk/actions/owl-pll.c struct owl_pll_hw *pll_hw = &pll->pll_hw; pll 160 drivers/clk/actions/owl-pll.c const struct owl_clk_common *common = &pll->common; pll 56 drivers/clk/at91/clk-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 57 drivers/clk/at91/clk-pll.c struct regmap *regmap = pll->regmap; pll 58 drivers/clk/at91/clk-pll.c const struct clk_pll_layout *layout = pll->layout; pll 60 drivers/clk/at91/clk-pll.c pll->characteristics; pll 61 drivers/clk/at91/clk-pll.c u8 id = pll->id; pll 76 drivers/clk/at91/clk-pll.c (div == pll->div && mul == pll->mul)) pll 80 drivers/clk/at91/clk-pll.c out = characteristics->out[pll->range]; pll 84 drivers/clk/at91/clk-pll.c characteristics->icpll[pll->range] << PLL_ICPR_SHIFT(id)); pll 87 drivers/clk/at91/clk-pll.c pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) | pll 89 drivers/clk/at91/clk-pll.c ((pll->mul & layout->mul_mask) << layout->mul_shift)); pll 91 drivers/clk/at91/clk-pll.c while (!clk_pll_ready(regmap, pll->id)) pll 99 drivers/clk/at91/clk-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 101 drivers/clk/at91/clk-pll.c return clk_pll_ready(pll->regmap, pll->id); pll 106 drivers/clk/at91/clk-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 107 drivers/clk/at91/clk-pll.c unsigned int mask = pll->layout->pllr_mask; pll 109 drivers/clk/at91/clk-pll.c regmap_update_bits(pll->regmap, PLL_REG(pll->id), mask, ~mask); pll 115 drivers/clk/at91/clk-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 117 drivers/clk/at91/clk-pll.c if (!pll->div || !pll->mul) pll 120 drivers/clk/at91/clk-pll.c return (parent_rate / pll->div) * (pll->mul + 1); pll 123 drivers/clk/at91/clk-pll.c static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate, pll 127 drivers/clk/at91/clk-pll.c const struct clk_pll_layout *layout = pll->layout; pll 129 drivers/clk/at91/clk-pll.c pll->characteristics; pll 236 drivers/clk/at91/clk-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 238 drivers/clk/at91/clk-pll.c return clk_pll_get_best_div_mul(pll, rate, *parent_rate, pll 245 drivers/clk/at91/clk-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 251 drivers/clk/at91/clk-pll.c ret = clk_pll_get_best_div_mul(pll, rate, parent_rate, pll 256 drivers/clk/at91/clk-pll.c pll->range = index; pll 257 drivers/clk/at91/clk-pll.c pll->div = div; pll 258 drivers/clk/at91/clk-pll.c pll->mul = mul; pll 278 drivers/clk/at91/clk-pll.c struct clk_pll *pll; pll 288 drivers/clk/at91/clk-pll.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 289 drivers/clk/at91/clk-pll.c if (!pll) pll 298 drivers/clk/at91/clk-pll.c pll->id = id; pll 299 drivers/clk/at91/clk-pll.c pll->hw.init = &init; pll 300 drivers/clk/at91/clk-pll.c pll->layout = layout; pll 301 drivers/clk/at91/clk-pll.c pll->characteristics = characteristics; pll 302 drivers/clk/at91/clk-pll.c pll->regmap = regmap; pll 304 drivers/clk/at91/clk-pll.c pll->div = PLL_DIV(pllr); pll 305 drivers/clk/at91/clk-pll.c pll->mul = PLL_MUL(pllr, layout); pll 307 drivers/clk/at91/clk-pll.c hw = &pll->hw; pll 308 drivers/clk/at91/clk-pll.c ret = clk_hw_register(NULL, &pll->hw); pll 310 drivers/clk/at91/clk-pll.c kfree(pll); pll 68 drivers/clk/at91/clk-sam9x60-pll.c struct sam9x60_pll *pll = to_sam9x60_pll(hw); pll 69 drivers/clk/at91/clk-sam9x60-pll.c struct regmap *regmap = pll->regmap; pll 75 drivers/clk/at91/clk-sam9x60-pll.c spin_lock_irqsave(pll->lock, flags); pll 76 drivers/clk/at91/clk-sam9x60-pll.c regmap_write(regmap, PMC_PLL_UPDT, pll->id); pll 84 drivers/clk/at91/clk-sam9x60-pll.c if (sam9x60_pll_ready(regmap, pll->id) && pll 85 drivers/clk/at91/clk-sam9x60-pll.c (div == pll->div && mul == pll->mul)) { pll 86 drivers/clk/at91/clk-sam9x60-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 95 drivers/clk/at91/clk-sam9x60-pll.c FIELD_PREP(PMC_PLL_CTRL1_MUL_MSK, pll->mul)); pll 97 drivers/clk/at91/clk-sam9x60-pll.c if (pll->characteristics->upll) { pll 116 drivers/clk/at91/clk-sam9x60-pll.c PMC_PLL_CTRL0_ENPLLCK | pll->div); pll 121 drivers/clk/at91/clk-sam9x60-pll.c while (!sam9x60_pll_ready(regmap, pll->id)) pll 124 drivers/clk/at91/clk-sam9x60-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 131 drivers/clk/at91/clk-sam9x60-pll.c struct sam9x60_pll *pll = to_sam9x60_pll(hw); pll 133 drivers/clk/at91/clk-sam9x60-pll.c return sam9x60_pll_ready(pll->regmap, pll->id); pll 138 drivers/clk/at91/clk-sam9x60-pll.c struct sam9x60_pll *pll = to_sam9x60_pll(hw); pll 141 drivers/clk/at91/clk-sam9x60-pll.c spin_lock_irqsave(pll->lock, flags); pll 143 drivers/clk/at91/clk-sam9x60-pll.c regmap_write(pll->regmap, PMC_PLL_UPDT, pll->id); pll 145 drivers/clk/at91/clk-sam9x60-pll.c regmap_update_bits(pll->regmap, PMC_PLL_CTRL0, pll 148 drivers/clk/at91/clk-sam9x60-pll.c regmap_update_bits(pll->regmap, PMC_PLL_UPDT, pll 151 drivers/clk/at91/clk-sam9x60-pll.c regmap_update_bits(pll->regmap, PMC_PLL_CTRL0, PMC_PLL_CTRL0_ENPLL, 0); pll 153 drivers/clk/at91/clk-sam9x60-pll.c if (pll->characteristics->upll) pll 154 drivers/clk/at91/clk-sam9x60-pll.c regmap_update_bits(pll->regmap, PMC_PLL_ACR, pll 157 drivers/clk/at91/clk-sam9x60-pll.c regmap_update_bits(pll->regmap, PMC_PLL_UPDT, pll 160 drivers/clk/at91/clk-sam9x60-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 166 drivers/clk/at91/clk-sam9x60-pll.c struct sam9x60_pll *pll = to_sam9x60_pll(hw); pll 168 drivers/clk/at91/clk-sam9x60-pll.c return (parent_rate * (pll->mul + 1)) / (pll->div + 1); pll 171 drivers/clk/at91/clk-sam9x60-pll.c static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll, pll 177 drivers/clk/at91/clk-sam9x60-pll.c pll->characteristics; pll 189 drivers/clk/at91/clk-sam9x60-pll.c if (!pll->characteristics->upll) { pll 252 drivers/clk/at91/clk-sam9x60-pll.c pll->div = bestdiv - 1; pll 253 drivers/clk/at91/clk-sam9x60-pll.c pll->mul = bestmul - 1; pll 254 drivers/clk/at91/clk-sam9x60-pll.c pll->frac = bestfrac; pll 263 drivers/clk/at91/clk-sam9x60-pll.c struct sam9x60_pll *pll = to_sam9x60_pll(hw); pll 265 drivers/clk/at91/clk-sam9x60-pll.c return sam9x60_pll_get_best_div_mul(pll, rate, *parent_rate, false); pll 271 drivers/clk/at91/clk-sam9x60-pll.c struct sam9x60_pll *pll = to_sam9x60_pll(hw); pll 273 drivers/clk/at91/clk-sam9x60-pll.c return sam9x60_pll_get_best_div_mul(pll, rate, parent_rate, true); pll 290 drivers/clk/at91/clk-sam9x60-pll.c struct sam9x60_pll *pll; pll 299 drivers/clk/at91/clk-sam9x60-pll.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 300 drivers/clk/at91/clk-sam9x60-pll.c if (!pll) pll 309 drivers/clk/at91/clk-sam9x60-pll.c pll->id = id; pll 310 drivers/clk/at91/clk-sam9x60-pll.c pll->hw.init = &init; pll 311 drivers/clk/at91/clk-sam9x60-pll.c pll->characteristics = characteristics; pll 312 drivers/clk/at91/clk-sam9x60-pll.c pll->regmap = regmap; pll 313 drivers/clk/at91/clk-sam9x60-pll.c pll->lock = lock; pll 317 drivers/clk/at91/clk-sam9x60-pll.c pll->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, pllr); pll 319 drivers/clk/at91/clk-sam9x60-pll.c pll->mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, pllr); pll 321 drivers/clk/at91/clk-sam9x60-pll.c hw = &pll->hw; pll 324 drivers/clk/at91/clk-sam9x60-pll.c kfree(pll); pll 127 drivers/clk/at91/sam9x60.c bool pll; pll 148 drivers/clk/at91/sam9x60.c .pll = true, }, pll 151 drivers/clk/at91/sam9x60.c .pll = true, }, pll 292 drivers/clk/at91/sam9x60.c sam9x60_gck[i].pll, pll 118 drivers/clk/at91/sama5d2.c bool pll; pll 127 drivers/clk/at91/sama5d2.c { .n = "i2s0_gclk", .id = 54, .pll = true }, pll 128 drivers/clk/at91/sama5d2.c { .n = "i2s1_gclk", .id = 55, .pll = true }, pll 132 drivers/clk/at91/sama5d2.c .pll = true }, pll 320 drivers/clk/at91/sama5d2.c sama5d2_gck[i].pll, pll 520 drivers/clk/bcm/clk-bcm2835.c struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); pll 521 drivers/clk/bcm/clk-bcm2835.c struct bcm2835_cprman *cprman = pll->cprman; pll 522 drivers/clk/bcm/clk-bcm2835.c const struct bcm2835_pll_data *data = pll->data; pll 557 drivers/clk/bcm/clk-bcm2835.c struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); pll 558 drivers/clk/bcm/clk-bcm2835.c const struct bcm2835_pll_data *data = pll->data; pll 571 drivers/clk/bcm/clk-bcm2835.c struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); pll 572 drivers/clk/bcm/clk-bcm2835.c struct bcm2835_cprman *cprman = pll->cprman; pll 573 drivers/clk/bcm/clk-bcm2835.c const struct bcm2835_pll_data *data = pll->data; pll 597 drivers/clk/bcm/clk-bcm2835.c struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); pll 598 drivers/clk/bcm/clk-bcm2835.c struct bcm2835_cprman *cprman = pll->cprman; pll 599 drivers/clk/bcm/clk-bcm2835.c const struct bcm2835_pll_data *data = pll->data; pll 611 drivers/clk/bcm/clk-bcm2835.c struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); pll 612 drivers/clk/bcm/clk-bcm2835.c struct bcm2835_cprman *cprman = pll->cprman; pll 613 drivers/clk/bcm/clk-bcm2835.c const struct bcm2835_pll_data *data = pll->data; pll 665 drivers/clk/bcm/clk-bcm2835.c struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); pll 666 drivers/clk/bcm/clk-bcm2835.c struct bcm2835_cprman *cprman = pll->cprman; pll 667 drivers/clk/bcm/clk-bcm2835.c const struct bcm2835_pll_data *data = pll->data; pll 733 drivers/clk/bcm/clk-bcm2835.c struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); pll 734 drivers/clk/bcm/clk-bcm2835.c struct bcm2835_cprman *cprman = pll->cprman; pll 735 drivers/clk/bcm/clk-bcm2835.c const struct bcm2835_pll_data *data = pll->data; pll 1301 drivers/clk/bcm/clk-bcm2835.c struct bcm2835_pll *pll; pll 1314 drivers/clk/bcm/clk-bcm2835.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 1315 drivers/clk/bcm/clk-bcm2835.c if (!pll) pll 1318 drivers/clk/bcm/clk-bcm2835.c pll->cprman = cprman; pll 1319 drivers/clk/bcm/clk-bcm2835.c pll->data = data; pll 1320 drivers/clk/bcm/clk-bcm2835.c pll->hw.init = &init; pll 1322 drivers/clk/bcm/clk-bcm2835.c ret = devm_clk_hw_register(cprman->dev, &pll->hw); pll 1325 drivers/clk/bcm/clk-bcm2835.c return &pll->hw; pll 76 drivers/clk/bcm/clk-iproc-armpll.c static unsigned int __get_fid(struct iproc_arm_pll *pll) pll 81 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); pll 90 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); pll 94 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); pll 116 drivers/clk/bcm/clk-iproc-armpll.c static int __get_mdiv(struct iproc_arm_pll *pll) pll 122 drivers/clk/bcm/clk-iproc-armpll.c fid = __get_fid(pll); pll 131 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET); pll 138 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARMCTL5_OFFSET); pll 151 drivers/clk/bcm/clk-iproc-armpll.c static unsigned int __get_ndiv(struct iproc_arm_pll *pll) pll 156 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARM_OFFSET_OFFSET); pll 170 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET); pll 176 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARMB_OFFSET); pll 198 drivers/clk/bcm/clk-iproc-armpll.c struct iproc_arm_pll *pll = to_iproc_arm_pll(hw); pll 205 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET); pll 207 drivers/clk/bcm/clk-iproc-armpll.c pll->rate = parent_rate; pll 208 drivers/clk/bcm/clk-iproc-armpll.c return pll->rate; pll 212 drivers/clk/bcm/clk-iproc-armpll.c val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET); pll 214 drivers/clk/bcm/clk-iproc-armpll.c pll->rate = 0; pll 223 drivers/clk/bcm/clk-iproc-armpll.c ndiv = __get_ndiv(pll); pll 224 drivers/clk/bcm/clk-iproc-armpll.c mdiv = __get_mdiv(pll); pll 226 drivers/clk/bcm/clk-iproc-armpll.c pll->rate = 0; pll 229 drivers/clk/bcm/clk-iproc-armpll.c pll->rate = (ndiv * parent_rate) >> 20; pll 230 drivers/clk/bcm/clk-iproc-armpll.c pll->rate = (pll->rate / pdiv) / mdiv; pll 233 drivers/clk/bcm/clk-iproc-armpll.c pll->rate, parent_rate); pll 237 drivers/clk/bcm/clk-iproc-armpll.c return pll->rate; pll 247 drivers/clk/bcm/clk-iproc-armpll.c struct iproc_arm_pll *pll; pll 251 drivers/clk/bcm/clk-iproc-armpll.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 252 drivers/clk/bcm/clk-iproc-armpll.c if (WARN_ON(!pll)) pll 255 drivers/clk/bcm/clk-iproc-armpll.c pll->base = of_iomap(node, 0); pll 256 drivers/clk/bcm/clk-iproc-armpll.c if (WARN_ON(!pll->base)) pll 265 drivers/clk/bcm/clk-iproc-armpll.c pll->hw.init = &init; pll 267 drivers/clk/bcm/clk-iproc-armpll.c ret = clk_hw_register(NULL, &pll->hw); pll 271 drivers/clk/bcm/clk-iproc-armpll.c ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll->hw); pll 278 drivers/clk/bcm/clk-iproc-armpll.c clk_hw_unregister(&pll->hw); pll 280 drivers/clk/bcm/clk-iproc-armpll.c iounmap(pll->base); pll 282 drivers/clk/bcm/clk-iproc-armpll.c kfree(pll); pll 85 drivers/clk/bcm/clk-iproc-pll.c struct iproc_pll *pll; pll 128 drivers/clk/bcm/clk-iproc-pll.c static int pll_get_rate_index(struct iproc_pll *pll, unsigned int target_rate) pll 132 drivers/clk/bcm/clk-iproc-pll.c for (i = 0; i < pll->num_vco_entries; i++) pll 133 drivers/clk/bcm/clk-iproc-pll.c if (target_rate == pll->vco_param[i].rate) pll 136 drivers/clk/bcm/clk-iproc-pll.c if (i >= pll->num_vco_entries) pll 157 drivers/clk/bcm/clk-iproc-pll.c static int pll_wait_for_lock(struct iproc_pll *pll) pll 160 drivers/clk/bcm/clk-iproc-pll.c const struct iproc_pll_ctrl *ctrl = pll->ctrl; pll 163 drivers/clk/bcm/clk-iproc-pll.c u32 val = readl(pll->status_base + ctrl->status.offset); pll 173 drivers/clk/bcm/clk-iproc-pll.c static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base, pll 176 drivers/clk/bcm/clk-iproc-pll.c const struct iproc_pll_ctrl *ctrl = pll->ctrl; pll 181 drivers/clk/bcm/clk-iproc-pll.c (base == pll->status_base || base == pll->control_base))) pll 185 drivers/clk/bcm/clk-iproc-pll.c static void __pll_disable(struct iproc_pll *pll) pll 187 drivers/clk/bcm/clk-iproc-pll.c const struct iproc_pll_ctrl *ctrl = pll->ctrl; pll 191 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->asiu_base + ctrl->asiu.offset); pll 193 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); pll 197 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->aon.offset); pll 199 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); pll 202 drivers/clk/bcm/clk-iproc-pll.c if (pll->pwr_base) { pll 204 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->pwr_base + ctrl->aon.offset); pll 206 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); pll 210 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); pll 214 drivers/clk/bcm/clk-iproc-pll.c static int __pll_enable(struct iproc_pll *pll) pll 216 drivers/clk/bcm/clk-iproc-pll.c const struct iproc_pll_ctrl *ctrl = pll->ctrl; pll 220 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->aon.offset); pll 222 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); pll 225 drivers/clk/bcm/clk-iproc-pll.c if (pll->pwr_base) { pll 227 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->pwr_base + ctrl->aon.offset); pll 230 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); pll 235 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->asiu_base + ctrl->asiu.offset); pll 237 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); pll 243 drivers/clk/bcm/clk-iproc-pll.c static void __pll_put_in_reset(struct iproc_pll *pll) pll 246 drivers/clk/bcm/clk-iproc-pll.c const struct iproc_pll_ctrl *ctrl = pll->ctrl; pll 249 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + reset->offset); pll 254 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, reset->offset, val); pll 257 drivers/clk/bcm/clk-iproc-pll.c static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, pll 261 drivers/clk/bcm/clk-iproc-pll.c const struct iproc_pll_ctrl *ctrl = pll->ctrl; pll 265 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + dig_filter->offset); pll 271 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, dig_filter->offset, val); pll 273 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + reset->offset); pll 278 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, reset->offset, val); pll 286 drivers/clk/bcm/clk-iproc-pll.c static bool pll_fractional_change_only(struct iproc_pll *pll, pll 289 drivers/clk/bcm/clk-iproc-pll.c const struct iproc_pll_ctrl *ctrl = pll->ctrl; pll 295 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->status_base + ctrl->status.offset); pll 299 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->ndiv_int.offset); pll 306 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->pdiv.offset); pll 318 drivers/clk/bcm/clk-iproc-pll.c struct iproc_pll *pll = clk->pll; pll 319 drivers/clk/bcm/clk-iproc-pll.c const struct iproc_pll_ctrl *ctrl = pll->ctrl; pll 358 drivers/clk/bcm/clk-iproc-pll.c ret = __pll_enable(pll); pll 364 drivers/clk/bcm/clk-iproc-pll.c if (pll_fractional_change_only(clk->pll, vco)) { pll 367 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->ndiv_frac.offset); pll 371 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, pll 378 drivers/clk/bcm/clk-iproc-pll.c __pll_put_in_reset(pll); pll 382 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->macro_mode.offset); pll 386 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, pll 390 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.u_offset, 0); pll 392 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->vco_ctrl.l_offset); pll 402 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.l_offset, val); pll 405 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->ndiv_int.offset); pll 408 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->ndiv_int.offset, val); pll 412 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->ndiv_frac.offset); pll 416 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->ndiv_frac.offset, pll 421 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->pdiv.offset); pll 424 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->pdiv.offset, val); pll 426 drivers/clk/bcm/clk-iproc-pll.c __pll_bring_out_reset(pll, kp, ka, ki); pll 428 drivers/clk/bcm/clk-iproc-pll.c ret = pll_wait_for_lock(pll); pll 440 drivers/clk/bcm/clk-iproc-pll.c struct iproc_pll *pll = clk->pll; pll 442 drivers/clk/bcm/clk-iproc-pll.c return __pll_enable(pll); pll 448 drivers/clk/bcm/clk-iproc-pll.c struct iproc_pll *pll = clk->pll; pll 449 drivers/clk/bcm/clk-iproc-pll.c const struct iproc_pll_ctrl *ctrl = pll->ctrl; pll 454 drivers/clk/bcm/clk-iproc-pll.c __pll_disable(pll); pll 461 drivers/clk/bcm/clk-iproc-pll.c struct iproc_pll *pll = clk->pll; pll 462 drivers/clk/bcm/clk-iproc-pll.c const struct iproc_pll_ctrl *ctrl = pll->ctrl; pll 472 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->status_base + ctrl->status.offset); pll 481 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->ndiv_int.offset); pll 487 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->ndiv_frac.offset); pll 493 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->pdiv.offset); pll 511 drivers/clk/bcm/clk-iproc-pll.c struct iproc_pll *pll = clk->pll; pll 512 drivers/clk/bcm/clk-iproc-pll.c const struct iproc_pll_ctrl *ctrl = pll->ctrl; pll 532 drivers/clk/bcm/clk-iproc-pll.c if (!pll->vco_param) pll 536 drivers/clk/bcm/clk-iproc-pll.c for (i = 0; i < pll->num_vco_entries; i++) { pll 537 drivers/clk/bcm/clk-iproc-pll.c diff = abs(req->rate - pll->vco_param[i].rate); pll 547 drivers/clk/bcm/clk-iproc-pll.c req->rate = pll->vco_param[best_idx].rate; pll 556 drivers/clk/bcm/clk-iproc-pll.c struct iproc_pll *pll = clk->pll; pll 557 drivers/clk/bcm/clk-iproc-pll.c const struct iproc_pll_ctrl *ctrl = pll->ctrl; pll 566 drivers/clk/bcm/clk-iproc-pll.c rate_index = pll_get_rate_index(pll, rate); pll 570 drivers/clk/bcm/clk-iproc-pll.c vco_param = pll->vco_param[rate_index]; pll 589 drivers/clk/bcm/clk-iproc-pll.c struct iproc_pll *pll = clk->pll; pll 593 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->enable.offset); pll 595 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); pll 598 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->enable.offset); pll 600 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); pll 609 drivers/clk/bcm/clk-iproc-pll.c struct iproc_pll *pll = clk->pll; pll 615 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->enable.offset); pll 617 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); pll 625 drivers/clk/bcm/clk-iproc-pll.c struct iproc_pll *pll = clk->pll; pll 633 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->mdiv.offset); pll 673 drivers/clk/bcm/clk-iproc-pll.c struct iproc_pll *pll = clk->pll; pll 687 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->mdiv.offset); pll 694 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->mdiv.offset, val); pll 711 drivers/clk/bcm/clk-iproc-pll.c static void iproc_pll_sw_cfg(struct iproc_pll *pll) pll 713 drivers/clk/bcm/clk-iproc-pll.c const struct iproc_pll_ctrl *ctrl = pll->ctrl; pll 718 drivers/clk/bcm/clk-iproc-pll.c val = readl(pll->control_base + ctrl->sw_ctrl.offset); pll 720 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_write(pll, pll->control_base, ctrl->sw_ctrl.offset, pll 733 drivers/clk/bcm/clk-iproc-pll.c struct iproc_pll *pll; pll 743 drivers/clk/bcm/clk-iproc-pll.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 744 drivers/clk/bcm/clk-iproc-pll.c if (WARN_ON(!pll)) pll 756 drivers/clk/bcm/clk-iproc-pll.c pll->control_base = of_iomap(node, 0); pll 757 drivers/clk/bcm/clk-iproc-pll.c if (WARN_ON(!pll->control_base)) pll 761 drivers/clk/bcm/clk-iproc-pll.c pll->pwr_base = of_iomap(node, 1); pll 765 drivers/clk/bcm/clk-iproc-pll.c pll->asiu_base = of_iomap(node, 2); pll 766 drivers/clk/bcm/clk-iproc-pll.c if (WARN_ON(!pll->asiu_base)) pll 774 drivers/clk/bcm/clk-iproc-pll.c pll->status_base = of_iomap(node, 2); pll 775 drivers/clk/bcm/clk-iproc-pll.c if (!pll->status_base) pll 778 drivers/clk/bcm/clk-iproc-pll.c pll->status_base = pll->control_base; pll 781 drivers/clk/bcm/clk-iproc-pll.c pll->ctrl = pll_ctrl; pll 784 drivers/clk/bcm/clk-iproc-pll.c iclk->pll = pll; pll 795 drivers/clk/bcm/clk-iproc-pll.c pll->num_vco_entries = num_vco_entries; pll 796 drivers/clk/bcm/clk-iproc-pll.c pll->vco_param = vco; pll 799 drivers/clk/bcm/clk-iproc-pll.c iproc_pll_sw_cfg(pll); pll 820 drivers/clk/bcm/clk-iproc-pll.c iclk->pll = pll; pll 848 drivers/clk/bcm/clk-iproc-pll.c if (pll->status_base != pll->control_base) pll 849 drivers/clk/bcm/clk-iproc-pll.c iounmap(pll->status_base); pll 852 drivers/clk/bcm/clk-iproc-pll.c if (pll->asiu_base) pll 853 drivers/clk/bcm/clk-iproc-pll.c iounmap(pll->asiu_base); pll 856 drivers/clk/bcm/clk-iproc-pll.c if (pll->pwr_base) pll 857 drivers/clk/bcm/clk-iproc-pll.c iounmap(pll->pwr_base); pll 859 drivers/clk/bcm/clk-iproc-pll.c iounmap(pll->control_base); pll 868 drivers/clk/bcm/clk-iproc-pll.c kfree(pll); pll 44 drivers/clk/berlin/berlin2-pll.c struct berlin2_pll *pll = to_berlin2_pll(hw); pll 45 drivers/clk/berlin/berlin2-pll.c struct berlin2_pll_map *map = &pll->map; pll 49 drivers/clk/berlin/berlin2-pll.c val = readl_relaxed(pll->base + SPLL_CTRL0); pll 57 drivers/clk/berlin/berlin2-pll.c val = readl_relaxed(pll->base + SPLL_CTRL1); pll 82 drivers/clk/berlin/berlin2-pll.c struct berlin2_pll *pll; pll 84 drivers/clk/berlin/berlin2-pll.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 85 drivers/clk/berlin/berlin2-pll.c if (!pll) pll 89 drivers/clk/berlin/berlin2-pll.c memcpy(&pll->map, map, sizeof(*map)); pll 90 drivers/clk/berlin/berlin2-pll.c pll->base = base; pll 91 drivers/clk/berlin/berlin2-pll.c pll->hw.init = &init; pll 98 drivers/clk/berlin/berlin2-pll.c return clk_hw_register(NULL, &pll->hw); pll 51 drivers/clk/clk-axm5516.c struct axxia_pllclk *pll = to_axxia_pllclk(aclk); pll 55 drivers/clk/clk-axm5516.c regmap_read(aclk->regmap, pll->reg, &control); pll 24 drivers/clk/clk-cdce706.c #define CDCE706_PLL_M_LOW(pll) (1 + 3 * (pll)) pll 25 drivers/clk/clk-cdce706.c #define CDCE706_PLL_N_LOW(pll) (2 + 3 * (pll)) pll 26 drivers/clk/clk-cdce706.c #define CDCE706_PLL_HI(pll) (3 + 3 * (pll)) pll 37 drivers/clk/clk-cdce706.c #define CDCE706_PLL_MUX_MASK(pll) (0x80 >> (pll)) pll 45 drivers/clk/clk-cdce706.c #define CDCE706_PLL_FVCO_MASK(pll) (0x80 >> (pll)) pll 83 drivers/clk/clk-cdce706.c struct cdce706_hw_data pll[3]; pll 525 drivers/clk/clk-cdce706.c for (i = 0; i < ARRAY_SIZE(cdce->pll); ++i) { pll 537 drivers/clk/clk-cdce706.c cdce->pll[i].div = m | ((v & CDCE706_PLL_HI_M_MASK) << 8); pll 538 drivers/clk/clk-cdce706.c cdce->pll[i].mul = n | ((v & CDCE706_PLL_HI_N_MASK) << pll 540 drivers/clk/clk-cdce706.c cdce->pll[i].mux = mux & CDCE706_PLL_MUX_MASK(i); pll 543 drivers/clk/clk-cdce706.c cdce->pll[i].div, cdce->pll[i].mul, cdce->pll[i].mux); pll 546 drivers/clk/clk-cdce706.c ret = cdce706_register_hw(cdce, cdce->pll, pll 547 drivers/clk/clk-cdce706.c ARRAY_SIZE(cdce->pll), pll 86 drivers/clk/clk-cdce925.c struct clk_cdce925_pll pll[MAX_NUMBER_OF_PLLS]; pll 226 drivers/clk/clk-cdce925.c u8 pll[4]; /* Bits are spread out over 4 byte registers */ pll 254 drivers/clk/clk-cdce925.c pll[0] = n >> 4; pll 255 drivers/clk/clk-cdce925.c pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F); pll 256 drivers/clk/clk-cdce925.c pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07); pll 257 drivers/clk/clk-cdce925.c pll[3] = ((q & 0x07) << 5) | (p << 2) | pll 260 drivers/clk/clk-cdce925.c for (i = 0; i < ARRAY_SIZE(pll); ++i) pll 262 drivers/clk/clk-cdce925.c reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]); pll 398 drivers/clk/clk-cdce925.c struct clk *pll = clk_get_parent(hw->clk); pll 399 drivers/clk/clk-cdce925.c struct clk *root = clk_get_parent(pll); pll 419 drivers/clk/clk-cdce925.c long pll_rate = clk_round_rate(pll, target_rate); pll 709 drivers/clk/clk-cdce925.c data->pll[i].chip = data; pll 710 drivers/clk/clk-cdce925.c data->pll[i].hw.init = &init; pll 711 drivers/clk/clk-cdce925.c data->pll[i].index = i; pll 712 drivers/clk/clk-cdce925.c err = devm_clk_hw_register(&client->dev, &data->pll[i].hw); pll 723 drivers/clk/clk-cdce925.c err = clk_set_rate(data->pll[i].hw.clk, value); pll 166 drivers/clk/clk-nomadik.c struct clk_pll *pll = to_pll(hw); pll 171 drivers/clk/clk-nomadik.c if (pll->id == 1) { pll 176 drivers/clk/clk-nomadik.c } else if (pll->id == 2) { pll 186 drivers/clk/clk-nomadik.c struct clk_pll *pll = to_pll(hw); pll 191 drivers/clk/clk-nomadik.c if (pll->id == 1) { pll 196 drivers/clk/clk-nomadik.c } else if (pll->id == 2) { pll 205 drivers/clk/clk-nomadik.c struct clk_pll *pll = to_pll(hw); pll 209 drivers/clk/clk-nomadik.c if (pll->id == 1) { pll 212 drivers/clk/clk-nomadik.c } else if (pll->id == 2) { pll 221 drivers/clk/clk-nomadik.c struct clk_pll *pll = to_pll(hw); pll 226 drivers/clk/clk-nomadik.c if (pll->id == 1) { pll 236 drivers/clk/clk-nomadik.c if (pll->id == 2) { pll 261 drivers/clk/clk-nomadik.c struct clk_pll *pll; pll 269 drivers/clk/clk-nomadik.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 270 drivers/clk/clk-nomadik.c if (!pll) pll 277 drivers/clk/clk-nomadik.c pll->hw.init = &init; pll 278 drivers/clk/clk-nomadik.c pll->id = id; pll 282 drivers/clk/clk-nomadik.c ret = clk_hw_register(dev, &pll->hw); pll 284 drivers/clk/clk-nomadik.c kfree(pll); pll 288 drivers/clk/clk-nomadik.c return &pll->hw; pll 41 drivers/clk/clk-npcm7xx.c struct npcm7xx_clk_pll *pll = to_npcm7xx_clk_pll(hw); pll 51 drivers/clk/clk-npcm7xx.c val = readl_relaxed(pll->pllcon); pll 72 drivers/clk/clk-npcm7xx.c struct npcm7xx_clk_pll *pll; pll 77 drivers/clk/clk-npcm7xx.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 78 drivers/clk/clk-npcm7xx.c if (!pll) pll 89 drivers/clk/clk-npcm7xx.c pll->pllcon = pllcon; pll 90 drivers/clk/clk-npcm7xx.c pll->hw.init = &init; pll 92 drivers/clk/clk-npcm7xx.c hw = &pll->hw; pll 96 drivers/clk/clk-npcm7xx.c kfree(pll); pll 50 drivers/clk/clk-qoriq.c int pll; /* CGx_PLLn */ pll 90 drivers/clk/clk-qoriq.c struct clockgen_pll pll[6]; pll 439 drivers/clk/clk-qoriq.c cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; pll 441 drivers/clk/clk-qoriq.c cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; pll 451 drivers/clk/clk-qoriq.c cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; pll 453 drivers/clk/clk-qoriq.c cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; pll 456 drivers/clk/clk-qoriq.c cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; pll 458 drivers/clk/clk-qoriq.c cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; pll 471 drivers/clk/clk-qoriq.c cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk; pll 473 drivers/clk/clk-qoriq.c cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; pll 486 drivers/clk/clk-qoriq.c cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk; pll 488 drivers/clk/clk-qoriq.c cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; pll 491 drivers/clk/clk-qoriq.c cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk; pll 493 drivers/clk/clk-qoriq.c cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; pll 503 drivers/clk/clk-qoriq.c cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk; pll 834 drivers/clk/clk-qoriq.c int pll, div; pll 839 drivers/clk/clk-qoriq.c pll = hwc->info->clksel[idx].pll; pll 842 drivers/clk/clk-qoriq.c return &cg->pll[pll].div[div]; pll 943 drivers/clk/clk-qoriq.c plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk); pll 1145 drivers/clk/clk-qoriq.c struct clockgen_pll *pll = &cg->pll[idx]; pll 1202 drivers/clk/clk-qoriq.c for (i = 0; i < ARRAY_SIZE(pll->div); i++) { pll 1213 drivers/clk/clk-qoriq.c snprintf(pll->div[i].name, sizeof(pll->div[i].name), pll 1217 drivers/clk/clk-qoriq.c pll->div[i].name, input, 0, mult, i + 1); pll 1220 drivers/clk/clk-qoriq.c __func__, pll->div[i].name, PTR_ERR(clk)); pll 1224 drivers/clk/clk-qoriq.c pll->div[i].clk = clk; pll 1225 drivers/clk/clk-qoriq.c ret = clk_register_clkdev(clk, pll->div[i].name, NULL); pll 1228 drivers/clk/clk-qoriq.c __func__, pll->div[i].name, ret); pll 1237 drivers/clk/clk-qoriq.c for (i = 0; i < ARRAY_SIZE(cg->pll); i++) pll 1243 drivers/clk/clk-qoriq.c struct clockgen_pll *pll; pll 1250 drivers/clk/clk-qoriq.c pll = &clockgen.pll[idx]; pll 1253 drivers/clk/clk-qoriq.c BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4); pll 1263 drivers/clk/clk-qoriq.c subclks[0] = pll->div[0].clk; pll 1264 drivers/clk/clk-qoriq.c subclks[1] = pll->div[1].clk; pll 1265 drivers/clk/clk-qoriq.c subclks[2] = pll->div[3].clk; pll 1267 drivers/clk/clk-qoriq.c subclks[0] = pll->div[0].clk; pll 1268 drivers/clk/clk-qoriq.c subclks[1] = pll->div[1].clk; pll 1269 drivers/clk/clk-qoriq.c subclks[2] = pll->div[2].clk; pll 1270 drivers/clk/clk-qoriq.c subclks[3] = pll->div[3].clk; pll 1321 drivers/clk/clk-qoriq.c struct clockgen_pll *pll; pll 1354 drivers/clk/clk-qoriq.c pll = &cg->pll[PLATFORM_PLL]; pll 1355 drivers/clk/clk-qoriq.c if (idx >= ARRAY_SIZE(pll->div)) pll 1357 drivers/clk/clk-qoriq.c clk = pll->div[idx].clk; pll 61 drivers/clk/clk-si5351.c struct si5351_hw_data pll[2]; pll 1510 drivers/clk/clk-si5351.c drvdata->pll[0].num = 0; pll 1511 drivers/clk/clk-si5351.c drvdata->pll[0].drvdata = drvdata; pll 1512 drivers/clk/clk-si5351.c drvdata->pll[0].hw.init = &init; pll 1519 drivers/clk/clk-si5351.c ret = devm_clk_hw_register(&client->dev, &drvdata->pll[0].hw); pll 1526 drivers/clk/clk-si5351.c drvdata->pll[1].num = 1; pll 1527 drivers/clk/clk-si5351.c drvdata->pll[1].drvdata = drvdata; pll 1528 drivers/clk/clk-si5351.c drvdata->pll[1].hw.init = &init; pll 1543 drivers/clk/clk-si5351.c ret = devm_clk_hw_register(&client->dev, &drvdata->pll[1].hw); pll 612 drivers/clk/clk-stm32f4.c struct stm32f4_pll *pll = to_stm32f4_pll(gate); pll 622 drivers/clk/clk-stm32f4.c bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx)); pll 638 drivers/clk/clk-stm32f4.c struct stm32f4_pll *pll = to_stm32f4_pll(gate); pll 641 drivers/clk/clk-stm32f4.c n = (readl(base + pll->offset) >> 6) & 0x1ff; pll 650 drivers/clk/clk-stm32f4.c struct stm32f4_pll *pll = to_stm32f4_pll(gate); pll 655 drivers/clk/clk-stm32f4.c if (n < pll->n_start) pll 656 drivers/clk/clk-stm32f4.c n = pll->n_start; pll 667 drivers/clk/clk-stm32f4.c struct stm32f4_pll *pll = to_stm32f4_pll(gate); pll 680 drivers/clk/clk-stm32f4.c val = readl(base + pll->offset) & ~(0x1ff << 6); pll 682 drivers/clk/clk-stm32f4.c writel(val | ((n & 0x1ff) << 6), base + pll->offset); pll 792 drivers/clk/clk-stm32f4.c struct stm32f4_pll *pll; pll 801 drivers/clk/clk-stm32f4.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 802 drivers/clk/clk-stm32f4.c if (!pll) pll 813 drivers/clk/clk-stm32f4.c pll->gate.lock = lock; pll 814 drivers/clk/clk-stm32f4.c pll->gate.reg = base + STM32F4_RCC_CR; pll 815 drivers/clk/clk-stm32f4.c pll->gate.bit_idx = vco->bit_idx; pll 816 drivers/clk/clk-stm32f4.c pll->gate.hw.init = &init; pll 818 drivers/clk/clk-stm32f4.c pll->offset = vco->offset; pll 819 drivers/clk/clk-stm32f4.c pll->n_start = data->n_start; pll 820 drivers/clk/clk-stm32f4.c pll->bit_rdy_idx = vco->bit_rdy_idx; pll 821 drivers/clk/clk-stm32f4.c pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1; pll 823 drivers/clk/clk-stm32f4.c reg = base + pll->offset; pll 825 drivers/clk/clk-stm32f4.c pll_hw = &pll->gate.hw; pll 828 drivers/clk/clk-stm32f4.c kfree(pll); pll 789 drivers/clk/clk-stm32h7.c struct stm32_pll_obj *pll; pll 796 drivers/clk/clk-stm32h7.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 797 drivers/clk/clk-stm32h7.c if (!pll) pll 805 drivers/clk/clk-stm32h7.c pll->hw.init = &init; pll 807 drivers/clk/clk-stm32h7.c hw = &pll->hw; pll 808 drivers/clk/clk-stm32h7.c rgate = &pll->rgate; pll 815 drivers/clk/clk-stm32h7.c div = &pll->div; pll 834 drivers/clk/clk-stm32h7.c kfree(pll); pll 549 drivers/clk/clk-vt8500.c struct clk_pll *pll = to_clk_pll(hw); pll 557 drivers/clk/clk-vt8500.c switch (pll->type) { pll 586 drivers/clk/clk-vt8500.c spin_lock_irqsave(pll->lock, flags); pll 589 drivers/clk/clk-vt8500.c writel(pll_val, pll->reg); pll 592 drivers/clk/clk-vt8500.c spin_unlock_irqrestore(pll->lock, flags); pll 600 drivers/clk/clk-vt8500.c struct clk_pll *pll = to_clk_pll(hw); pll 605 drivers/clk/clk-vt8500.c switch (pll->type) { pll 639 drivers/clk/clk-vt8500.c struct clk_pll *pll = to_clk_pll(hw); pll 640 drivers/clk/clk-vt8500.c u32 pll_val = readl(pll->reg); pll 643 drivers/clk/clk-vt8500.c switch (pll->type) { pll 76 drivers/clk/clk-xgene.c u32 pll; pll 81 drivers/clk/clk-xgene.c pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); pll 90 drivers/clk/clk-xgene.c fvco = parent_rate * (N_DIV_RD(pll) + 4); pll 97 drivers/clk/clk-xgene.c nref = CLKR_RD(pll) + 1; pll 98 drivers/clk/clk-xgene.c nout = CLKOD_RD(pll) + 1; pll 99 drivers/clk/clk-xgene.c nfb = CLKF_RD(pll); pll 108 drivers/clk/clk-xgene.c nout = SC_OUTDIV2(pll) ? 2 : 3; pll 109 drivers/clk/clk-xgene.c fvco = parent_rate * SC_N_DIV_RD(pll); pll 118 drivers/clk/davinci/pll.c struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); pll 122 drivers/clk/davinci/pll.c mult = readl(pll->base + PLLM) & pll->pllm_mask; pll 131 drivers/clk/davinci/pll.c struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); pll 151 drivers/clk/davinci/pll.c if (mult < pll->pllm_min || mult > pll->pllm_max) pll 162 drivers/clk/davinci/pll.c for (mult = pll->pllm_min; mult <= pll->pllm_max; mult++) { pll 184 drivers/clk/davinci/pll.c struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); pll 188 drivers/clk/davinci/pll.c writel(mult - 1, pll->base + PLLM); pll 210 drivers/clk/davinci/pll.c struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); pll 214 drivers/clk/davinci/pll.c mult = readl(pll->base + PLLM) & pll->pllm_mask; pll 311 drivers/clk/davinci/pll.c struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw); pll 314 drivers/clk/davinci/pll.c ctrl = readl(pll->base + PLLCTL); pll 319 drivers/clk/davinci/pll.c writel(ctrl, pll->base + PLLCTL); pll 325 drivers/clk/davinci/pll.c writel(ctrl, pll->base + PLLCTL); pll 331 drivers/clk/davinci/pll.c writel(ctrl, pll->base + PLLCTL); pll 337 drivers/clk/davinci/pll.c writel(ctrl, pll->base + PLLCTL); pll 645 drivers/clk/davinci/pll.c struct davinci_pllen_clk *pll = to_davinci_pllen_clk(hw); pll 651 drivers/clk/davinci/pll.c pllcmd = readl(pll->base + PLLCMD); pll 653 drivers/clk/davinci/pll.c writel(pllcmd, pll->base + PLLCMD); pll 658 drivers/clk/davinci/pll.c pllstat = readl(pll->base + PLLSTAT); pll 997 drivers/clk/davinci/pll.c struct davinci_pll_clk *pll = to_davinci_pll_clk(hw); pll 1006 drivers/clk/davinci/pll.c regset->base = pll->base; pll 62 drivers/clk/h8300/clk-h8s2678.c int pll; pll 67 drivers/clk/h8300/clk-h8s2678.c pll = ((rate / parent_rate) / 2) & 0x03; pll 74 drivers/clk/h8300/clk-h8s2678.c val |= pll; pll 15 drivers/clk/imx/clk-cpu.c struct clk *pll; pll 37 drivers/clk/imx/clk-cpu.c return clk_round_rate(cpu->pll, rate); pll 52 drivers/clk/imx/clk-cpu.c ret = clk_set_rate(cpu->pll, rate); pll 54 drivers/clk/imx/clk-cpu.c clk_set_parent(cpu->mux, cpu->pll); pll 58 drivers/clk/imx/clk-cpu.c clk_set_parent(cpu->mux, cpu->pll); pll 73 drivers/clk/imx/clk-cpu.c struct clk *div, struct clk *mux, struct clk *pll, pll 87 drivers/clk/imx/clk-cpu.c cpu->pll = pll; pll 43 drivers/clk/imx/clk-frac-pll.c static int clk_wait_lock(struct clk_frac_pll *pll) pll 47 drivers/clk/imx/clk-frac-pll.c return readl_poll_timeout(pll->base, val, val & PLL_LOCK_STATUS, 0, pll 51 drivers/clk/imx/clk-frac-pll.c static int clk_wait_ack(struct clk_frac_pll *pll) pll 56 drivers/clk/imx/clk-frac-pll.c if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK)) pll 60 drivers/clk/imx/clk-frac-pll.c return readl_poll_timeout(pll->base, val, val & PLL_NEWDIV_ACK, 0, pll 66 drivers/clk/imx/clk-frac-pll.c struct clk_frac_pll *pll = to_clk_frac_pll(hw); pll 69 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); pll 71 drivers/clk/imx/clk-frac-pll.c writel_relaxed(val, pll->base + PLL_CFG0); pll 73 drivers/clk/imx/clk-frac-pll.c return clk_wait_lock(pll); pll 78 drivers/clk/imx/clk-frac-pll.c struct clk_frac_pll *pll = to_clk_frac_pll(hw); pll 81 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); pll 83 drivers/clk/imx/clk-frac-pll.c writel_relaxed(val, pll->base + PLL_CFG0); pll 88 drivers/clk/imx/clk-frac-pll.c struct clk_frac_pll *pll = to_clk_frac_pll(hw); pll 91 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); pll 98 drivers/clk/imx/clk-frac-pll.c struct clk_frac_pll *pll = to_clk_frac_pll(hw); pll 103 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); pll 105 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG1); pll 157 drivers/clk/imx/clk-frac-pll.c struct clk_frac_pll *pll = to_clk_frac_pll(hw); pll 171 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG1); pll 174 drivers/clk/imx/clk-frac-pll.c writel_relaxed(val, pll->base + PLL_CFG1); pll 176 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); pll 178 drivers/clk/imx/clk-frac-pll.c writel_relaxed(val, pll->base + PLL_CFG0); pll 181 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); pll 183 drivers/clk/imx/clk-frac-pll.c writel_relaxed(val, pll->base + PLL_CFG0); pll 185 drivers/clk/imx/clk-frac-pll.c ret = clk_wait_ack(pll); pll 188 drivers/clk/imx/clk-frac-pll.c val = readl_relaxed(pll->base + PLL_CFG0); pll 190 drivers/clk/imx/clk-frac-pll.c writel_relaxed(val, pll->base + PLL_CFG0); pll 208 drivers/clk/imx/clk-frac-pll.c struct clk_frac_pll *pll; pll 212 drivers/clk/imx/clk-frac-pll.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 213 drivers/clk/imx/clk-frac-pll.c if (!pll) pll 222 drivers/clk/imx/clk-frac-pll.c pll->base = base; pll 223 drivers/clk/imx/clk-frac-pll.c pll->hw.init = &init; pll 225 drivers/clk/imx/clk-frac-pll.c hw = &pll->hw; pll 229 drivers/clk/imx/clk-frac-pll.c kfree(pll); pll 45 drivers/clk/imx/clk-pll14xx.c struct clk_pll14xx *pll, unsigned long rate) pll 47 drivers/clk/imx/clk-pll14xx.c const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; pll 50 drivers/clk/imx/clk-pll14xx.c for (i = 0; i < pll->rate_count; i++) pll 60 drivers/clk/imx/clk-pll14xx.c struct clk_pll14xx *pll = to_clk_pll14xx(hw); pll 61 drivers/clk/imx/clk-pll14xx.c const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; pll 65 drivers/clk/imx/clk-pll14xx.c for (i = 0; i < pll->rate_count; i++) pll 76 drivers/clk/imx/clk-pll14xx.c struct clk_pll14xx *pll = to_clk_pll14xx(hw); pll 80 drivers/clk/imx/clk-pll14xx.c pll_div = readl_relaxed(pll->base + 4); pll 94 drivers/clk/imx/clk-pll14xx.c struct clk_pll14xx *pll = to_clk_pll14xx(hw); pll 99 drivers/clk/imx/clk-pll14xx.c pll_div_ctl0 = readl_relaxed(pll->base + 4); pll 100 drivers/clk/imx/clk-pll14xx.c pll_div_ctl1 = readl_relaxed(pll->base + 8); pll 126 drivers/clk/imx/clk-pll14xx.c static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll) pll 130 drivers/clk/imx/clk-pll14xx.c return readl_poll_timeout(pll->base, val, val & LOCK_STATUS, 0, pll 137 drivers/clk/imx/clk-pll14xx.c struct clk_pll14xx *pll = to_clk_pll14xx(hw); pll 142 drivers/clk/imx/clk-pll14xx.c rate = imx_get_pll_settings(pll, drate); pll 149 drivers/clk/imx/clk-pll14xx.c tmp = readl_relaxed(pll->base + 4); pll 154 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base + 4); pll 160 drivers/clk/imx/clk-pll14xx.c tmp = readl_relaxed(pll->base); pll 162 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base); pll 166 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base); pll 170 drivers/clk/imx/clk-pll14xx.c writel(tmp, pll->base); pll 174 drivers/clk/imx/clk-pll14xx.c writel_relaxed(div_val, pll->base + 0x4); pll 186 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base); pll 189 drivers/clk/imx/clk-pll14xx.c ret = clk_pll14xx_wait_lock(pll); pll 195 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base); pll 203 drivers/clk/imx/clk-pll14xx.c struct clk_pll14xx *pll = to_clk_pll14xx(hw); pll 208 drivers/clk/imx/clk-pll14xx.c rate = imx_get_pll_settings(pll, drate); pll 215 drivers/clk/imx/clk-pll14xx.c tmp = readl_relaxed(pll->base + 4); pll 220 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base + 4); pll 223 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base + 8); pll 229 drivers/clk/imx/clk-pll14xx.c tmp = readl_relaxed(pll->base); pll 231 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base); pll 235 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base); pll 239 drivers/clk/imx/clk-pll14xx.c writel_relaxed(div_val, pll->base + 0x4); pll 240 drivers/clk/imx/clk-pll14xx.c writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + 0x8); pll 252 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base); pll 255 drivers/clk/imx/clk-pll14xx.c ret = clk_pll14xx_wait_lock(pll); pll 261 drivers/clk/imx/clk-pll14xx.c writel_relaxed(tmp, pll->base); pll 268 drivers/clk/imx/clk-pll14xx.c struct clk_pll14xx *pll = to_clk_pll14xx(hw); pll 276 drivers/clk/imx/clk-pll14xx.c val = readl_relaxed(pll->base + GNRL_CTL); pll 280 drivers/clk/imx/clk-pll14xx.c writel_relaxed(val, pll->base + GNRL_CTL); pll 282 drivers/clk/imx/clk-pll14xx.c writel_relaxed(val, pll->base + GNRL_CTL); pll 284 drivers/clk/imx/clk-pll14xx.c ret = clk_pll14xx_wait_lock(pll); pll 289 drivers/clk/imx/clk-pll14xx.c writel_relaxed(val, pll->base + GNRL_CTL); pll 296 drivers/clk/imx/clk-pll14xx.c struct clk_pll14xx *pll = to_clk_pll14xx(hw); pll 299 drivers/clk/imx/clk-pll14xx.c val = readl_relaxed(pll->base + GNRL_CTL); pll 306 drivers/clk/imx/clk-pll14xx.c struct clk_pll14xx *pll = to_clk_pll14xx(hw); pll 313 drivers/clk/imx/clk-pll14xx.c val = readl_relaxed(pll->base + GNRL_CTL); pll 315 drivers/clk/imx/clk-pll14xx.c writel_relaxed(val, pll->base + GNRL_CTL); pll 344 drivers/clk/imx/clk-pll14xx.c struct clk_pll14xx *pll; pll 349 drivers/clk/imx/clk-pll14xx.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 350 drivers/clk/imx/clk-pll14xx.c if (!pll) pll 373 drivers/clk/imx/clk-pll14xx.c pll->base = base; pll 374 drivers/clk/imx/clk-pll14xx.c pll->hw.init = &init; pll 375 drivers/clk/imx/clk-pll14xx.c pll->type = pll_clk->type; pll 376 drivers/clk/imx/clk-pll14xx.c pll->rate_table = pll_clk->rate_table; pll 377 drivers/clk/imx/clk-pll14xx.c pll->rate_count = pll_clk->rate_count; pll 379 drivers/clk/imx/clk-pll14xx.c val = readl_relaxed(pll->base + GNRL_CTL); pll 381 drivers/clk/imx/clk-pll14xx.c writel_relaxed(val, pll->base + GNRL_CTL); pll 383 drivers/clk/imx/clk-pll14xx.c clk = clk_register(NULL, &pll->hw); pll 387 drivers/clk/imx/clk-pll14xx.c kfree(pll); pll 32 drivers/clk/imx/clk-pllv1.c static inline bool is_imx1_pllv1(struct clk_pllv1 *pll) pll 34 drivers/clk/imx/clk-pllv1.c return pll->type == IMX_PLLV1_IMX1; pll 37 drivers/clk/imx/clk-pllv1.c static inline bool is_imx21_pllv1(struct clk_pllv1 *pll) pll 39 drivers/clk/imx/clk-pllv1.c return pll->type == IMX_PLLV1_IMX21; pll 42 drivers/clk/imx/clk-pllv1.c static inline bool is_imx27_pllv1(struct clk_pllv1 *pll) pll 44 drivers/clk/imx/clk-pllv1.c return pll->type == IMX_PLLV1_IMX27; pll 47 drivers/clk/imx/clk-pllv1.c static inline bool mfn_is_negative(struct clk_pllv1 *pll, unsigned int mfn) pll 49 drivers/clk/imx/clk-pllv1.c return !is_imx1_pllv1(pll) && !is_imx21_pllv1(pll) && (mfn & MFN_SIGN); pll 55 drivers/clk/imx/clk-pllv1.c struct clk_pllv1 *pll = to_clk_pllv1(hw); pll 62 drivers/clk/imx/clk-pllv1.c reg = readl(pll->base); pll 88 drivers/clk/imx/clk-pllv1.c if (mfn_is_negative(pll, mfn)) { pll 89 drivers/clk/imx/clk-pllv1.c if (is_imx27_pllv1(pll)) pll 102 drivers/clk/imx/clk-pllv1.c if (mfn_is_negative(pll, mfn)) pll 117 drivers/clk/imx/clk-pllv1.c struct clk_pllv1 *pll; pll 121 drivers/clk/imx/clk-pllv1.c pll = kmalloc(sizeof(*pll), GFP_KERNEL); pll 122 drivers/clk/imx/clk-pllv1.c if (!pll) pll 125 drivers/clk/imx/clk-pllv1.c pll->base = base; pll 126 drivers/clk/imx/clk-pllv1.c pll->type = type; pll 134 drivers/clk/imx/clk-pllv1.c pll->hw.init = &init; pll 136 drivers/clk/imx/clk-pllv1.c clk = clk_register(NULL, &pll->hw); pll 138 drivers/clk/imx/clk-pllv1.c kfree(pll); pll 114 drivers/clk/imx/clk-pllv2.c struct clk_pllv2 *pll = to_clk_pllv2(hw); pll 116 drivers/clk/imx/clk-pllv2.c pllbase = pll->base; pll 158 drivers/clk/imx/clk-pllv2.c struct clk_pllv2 *pll = to_clk_pllv2(hw); pll 163 drivers/clk/imx/clk-pllv2.c pllbase = pll->base; pll 197 drivers/clk/imx/clk-pllv2.c struct clk_pllv2 *pll = to_clk_pllv2(hw); pll 202 drivers/clk/imx/clk-pllv2.c pllbase = pll->base; pll 225 drivers/clk/imx/clk-pllv2.c struct clk_pllv2 *pll = to_clk_pllv2(hw); pll 229 drivers/clk/imx/clk-pllv2.c pllbase = pll->base; pll 245 drivers/clk/imx/clk-pllv2.c struct clk_pllv2 *pll; pll 249 drivers/clk/imx/clk-pllv2.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 250 drivers/clk/imx/clk-pllv2.c if (!pll) pll 253 drivers/clk/imx/clk-pllv2.c pll->base = base; pll 261 drivers/clk/imx/clk-pllv2.c pll->hw.init = &init; pll 263 drivers/clk/imx/clk-pllv2.c clk = clk_register(NULL, &pll->hw); pll 265 drivers/clk/imx/clk-pllv2.c kfree(pll); pll 54 drivers/clk/imx/clk-pllv3.c static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) pll 57 drivers/clk/imx/clk-pllv3.c u32 val = readl_relaxed(pll->base) & pll->power_bit; pll 60 drivers/clk/imx/clk-pllv3.c if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) pll 65 drivers/clk/imx/clk-pllv3.c if (readl_relaxed(pll->base) & BM_PLL_LOCK) pll 72 drivers/clk/imx/clk-pllv3.c return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT; pll 77 drivers/clk/imx/clk-pllv3.c struct clk_pllv3 *pll = to_clk_pllv3(hw); pll 80 drivers/clk/imx/clk-pllv3.c val = readl_relaxed(pll->base); pll 81 drivers/clk/imx/clk-pllv3.c if (pll->powerup_set) pll 82 drivers/clk/imx/clk-pllv3.c val |= pll->power_bit; pll 84 drivers/clk/imx/clk-pllv3.c val &= ~pll->power_bit; pll 85 drivers/clk/imx/clk-pllv3.c writel_relaxed(val, pll->base); pll 87 drivers/clk/imx/clk-pllv3.c return clk_pllv3_wait_lock(pll); pll 92 drivers/clk/imx/clk-pllv3.c struct clk_pllv3 *pll = to_clk_pllv3(hw); pll 95 drivers/clk/imx/clk-pllv3.c val = readl_relaxed(pll->base); pll 96 drivers/clk/imx/clk-pllv3.c if (pll->powerup_set) pll 97 drivers/clk/imx/clk-pllv3.c val &= ~pll->power_bit; pll 99 drivers/clk/imx/clk-pllv3.c val |= pll->power_bit; pll 100 drivers/clk/imx/clk-pllv3.c writel_relaxed(val, pll->base); pll 105 drivers/clk/imx/clk-pllv3.c struct clk_pllv3 *pll = to_clk_pllv3(hw); pll 107 drivers/clk/imx/clk-pllv3.c if (readl_relaxed(pll->base) & BM_PLL_LOCK) pll 116 drivers/clk/imx/clk-pllv3.c struct clk_pllv3 *pll = to_clk_pllv3(hw); pll 117 drivers/clk/imx/clk-pllv3.c u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; pll 134 drivers/clk/imx/clk-pllv3.c struct clk_pllv3 *pll = to_clk_pllv3(hw); pll 144 drivers/clk/imx/clk-pllv3.c val = readl_relaxed(pll->base); pll 145 drivers/clk/imx/clk-pllv3.c val &= ~(pll->div_mask << pll->div_shift); pll 146 drivers/clk/imx/clk-pllv3.c val |= (div << pll->div_shift); pll 147 drivers/clk/imx/clk-pllv3.c writel_relaxed(val, pll->base); pll 149 drivers/clk/imx/clk-pllv3.c return clk_pllv3_wait_lock(pll); pll 164 drivers/clk/imx/clk-pllv3.c struct clk_pllv3 *pll = to_clk_pllv3(hw); pll 165 drivers/clk/imx/clk-pllv3.c u32 div = readl_relaxed(pll->base) & pll->div_mask; pll 190 drivers/clk/imx/clk-pllv3.c struct clk_pllv3 *pll = to_clk_pllv3(hw); pll 199 drivers/clk/imx/clk-pllv3.c val = readl_relaxed(pll->base); pll 200 drivers/clk/imx/clk-pllv3.c val &= ~pll->div_mask; pll 202 drivers/clk/imx/clk-pllv3.c writel_relaxed(val, pll->base); pll 204 drivers/clk/imx/clk-pllv3.c return clk_pllv3_wait_lock(pll); pll 219 drivers/clk/imx/clk-pllv3.c struct clk_pllv3 *pll = to_clk_pllv3(hw); pll 220 drivers/clk/imx/clk-pllv3.c u32 mfn = readl_relaxed(pll->base + pll->num_offset); pll 221 drivers/clk/imx/clk-pllv3.c u32 mfd = readl_relaxed(pll->base + pll->denom_offset); pll 222 drivers/clk/imx/clk-pllv3.c u32 div = readl_relaxed(pll->base) & pll->div_mask; pll 266 drivers/clk/imx/clk-pllv3.c struct clk_pllv3 *pll = to_clk_pllv3(hw); pll 286 drivers/clk/imx/clk-pllv3.c val = readl_relaxed(pll->base); pll 287 drivers/clk/imx/clk-pllv3.c val &= ~pll->div_mask; pll 289 drivers/clk/imx/clk-pllv3.c writel_relaxed(val, pll->base); pll 290 drivers/clk/imx/clk-pllv3.c writel_relaxed(mfn, pll->base + pll->num_offset); pll 291 drivers/clk/imx/clk-pllv3.c writel_relaxed(mfd, pll->base + pll->denom_offset); pll 293 drivers/clk/imx/clk-pllv3.c return clk_pllv3_wait_lock(pll); pll 350 drivers/clk/imx/clk-pllv3.c struct clk_pllv3 *pll = to_clk_pllv3(hw); pll 353 drivers/clk/imx/clk-pllv3.c mf.mfn = readl_relaxed(pll->base + pll->num_offset); pll 354 drivers/clk/imx/clk-pllv3.c mf.mfd = readl_relaxed(pll->base + pll->denom_offset); pll 355 drivers/clk/imx/clk-pllv3.c mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20; pll 371 drivers/clk/imx/clk-pllv3.c struct clk_pllv3 *pll = to_clk_pllv3(hw); pll 376 drivers/clk/imx/clk-pllv3.c val = readl_relaxed(pll->base); pll 378 drivers/clk/imx/clk-pllv3.c val &= ~pll->div_mask; /* clear bit for mfi=20 */ pll 380 drivers/clk/imx/clk-pllv3.c val |= pll->div_mask; /* set bit for mfi=22 */ pll 381 drivers/clk/imx/clk-pllv3.c writel_relaxed(val, pll->base); pll 383 drivers/clk/imx/clk-pllv3.c writel_relaxed(mf.mfn, pll->base + pll->num_offset); pll 384 drivers/clk/imx/clk-pllv3.c writel_relaxed(mf.mfd, pll->base + pll->denom_offset); pll 386 drivers/clk/imx/clk-pllv3.c return clk_pllv3_wait_lock(pll); pll 401 drivers/clk/imx/clk-pllv3.c struct clk_pllv3 *pll = to_clk_pllv3(hw); pll 403 drivers/clk/imx/clk-pllv3.c return pll->ref_clock; pll 417 drivers/clk/imx/clk-pllv3.c struct clk_pllv3 *pll; pll 423 drivers/clk/imx/clk-pllv3.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 424 drivers/clk/imx/clk-pllv3.c if (!pll) pll 427 drivers/clk/imx/clk-pllv3.c pll->power_bit = BM_PLL_POWER; pll 428 drivers/clk/imx/clk-pllv3.c pll->num_offset = PLL_NUM_OFFSET; pll 429 drivers/clk/imx/clk-pllv3.c pll->denom_offset = PLL_DENOM_OFFSET; pll 437 drivers/clk/imx/clk-pllv3.c pll->num_offset = PLL_VF610_NUM_OFFSET; pll 438 drivers/clk/imx/clk-pllv3.c pll->denom_offset = PLL_VF610_DENOM_OFFSET; pll 441 drivers/clk/imx/clk-pllv3.c pll->div_shift = 1; pll 445 drivers/clk/imx/clk-pllv3.c pll->powerup_set = true; pll 448 drivers/clk/imx/clk-pllv3.c pll->num_offset = PLL_IMX7_NUM_OFFSET; pll 449 drivers/clk/imx/clk-pllv3.c pll->denom_offset = PLL_IMX7_DENOM_OFFSET; pll 455 drivers/clk/imx/clk-pllv3.c pll->power_bit = IMX7_ENET_PLL_POWER; pll 456 drivers/clk/imx/clk-pllv3.c pll->ref_clock = 1000000000; pll 460 drivers/clk/imx/clk-pllv3.c pll->ref_clock = 500000000; pll 464 drivers/clk/imx/clk-pllv3.c pll->power_bit = IMX7_DDR_PLL_POWER; pll 465 drivers/clk/imx/clk-pllv3.c pll->num_offset = PLL_IMX7_NUM_OFFSET; pll 466 drivers/clk/imx/clk-pllv3.c pll->denom_offset = PLL_IMX7_DENOM_OFFSET; pll 472 drivers/clk/imx/clk-pllv3.c pll->base = base; pll 473 drivers/clk/imx/clk-pllv3.c pll->div_mask = div_mask; pll 481 drivers/clk/imx/clk-pllv3.c pll->hw.init = &init; pll 482 drivers/clk/imx/clk-pllv3.c hw = &pll->hw; pll 486 drivers/clk/imx/clk-pllv3.c kfree(pll); pll 49 drivers/clk/imx/clk-pllv4.c static inline int clk_pllv4_wait_lock(struct clk_pllv4 *pll) pll 53 drivers/clk/imx/clk-pllv4.c return readl_poll_timeout(pll->base + PLL_CSR_OFFSET, pll 59 drivers/clk/imx/clk-pllv4.c struct clk_pllv4 *pll = to_clk_pllv4(hw); pll 61 drivers/clk/imx/clk-pllv4.c if (readl_relaxed(pll->base) & PLL_EN) pll 70 drivers/clk/imx/clk-pllv4.c struct clk_pllv4 *pll = to_clk_pllv4(hw); pll 74 drivers/clk/imx/clk-pllv4.c mult = readl_relaxed(pll->base + PLL_CFG_OFFSET); pll 78 drivers/clk/imx/clk-pllv4.c mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET); pll 79 drivers/clk/imx/clk-pllv4.c mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET); pll 150 drivers/clk/imx/clk-pllv4.c struct clk_pllv4 *pll = to_clk_pllv4(hw); pll 167 drivers/clk/imx/clk-pllv4.c val = readl_relaxed(pll->base + PLL_CFG_OFFSET); pll 170 drivers/clk/imx/clk-pllv4.c writel_relaxed(val, pll->base + PLL_CFG_OFFSET); pll 172 drivers/clk/imx/clk-pllv4.c writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); pll 173 drivers/clk/imx/clk-pllv4.c writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); pll 181 drivers/clk/imx/clk-pllv4.c struct clk_pllv4 *pll = to_clk_pllv4(hw); pll 183 drivers/clk/imx/clk-pllv4.c val = readl_relaxed(pll->base); pll 185 drivers/clk/imx/clk-pllv4.c writel_relaxed(val, pll->base); pll 187 drivers/clk/imx/clk-pllv4.c return clk_pllv4_wait_lock(pll); pll 193 drivers/clk/imx/clk-pllv4.c struct clk_pllv4 *pll = to_clk_pllv4(hw); pll 195 drivers/clk/imx/clk-pllv4.c val = readl_relaxed(pll->base); pll 197 drivers/clk/imx/clk-pllv4.c writel_relaxed(val, pll->base); pll 212 drivers/clk/imx/clk-pllv4.c struct clk_pllv4 *pll; pll 217 drivers/clk/imx/clk-pllv4.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 218 drivers/clk/imx/clk-pllv4.c if (!pll) pll 221 drivers/clk/imx/clk-pllv4.c pll->base = base; pll 229 drivers/clk/imx/clk-pllv4.c pll->hw.init = &init; pll 231 drivers/clk/imx/clk-pllv4.c hw = &pll->hw; pll 234 drivers/clk/imx/clk-pllv4.c kfree(pll); pll 101 drivers/clk/imx/clk-sccg-pll.c static int clk_sccg_pll_wait_lock(struct clk_sccg_pll *pll) pll 105 drivers/clk/imx/clk-sccg-pll.c val = readl_relaxed(pll->base + PLL_CFG0); pll 109 drivers/clk/imx/clk-sccg-pll.c return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK, pll 307 drivers/clk/imx/clk-sccg-pll.c struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); pll 309 drivers/clk/imx/clk-sccg-pll.c u32 val = readl_relaxed(pll->base + PLL_CFG0); pll 316 drivers/clk/imx/clk-sccg-pll.c struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); pll 319 drivers/clk/imx/clk-sccg-pll.c val = readl_relaxed(pll->base + PLL_CFG0); pll 321 drivers/clk/imx/clk-sccg-pll.c writel_relaxed(val, pll->base + PLL_CFG0); pll 323 drivers/clk/imx/clk-sccg-pll.c return clk_sccg_pll_wait_lock(pll); pll 328 drivers/clk/imx/clk-sccg-pll.c struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); pll 331 drivers/clk/imx/clk-sccg-pll.c val = readl_relaxed(pll->base + PLL_CFG0); pll 333 drivers/clk/imx/clk-sccg-pll.c writel_relaxed(val, pll->base + PLL_CFG0); pll 339 drivers/clk/imx/clk-sccg-pll.c struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); pll 343 drivers/clk/imx/clk-sccg-pll.c val = readl_relaxed(pll->base + PLL_CFG2); pll 352 drivers/clk/imx/clk-sccg-pll.c val = readl(pll->base + PLL_CFG0); pll 370 drivers/clk/imx/clk-sccg-pll.c struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); pll 371 drivers/clk/imx/clk-sccg-pll.c struct clk_sccg_pll_setup *setup = &pll->setup; pll 375 drivers/clk/imx/clk-sccg-pll.c val = readl(pll->base + PLL_CFG0); pll 378 drivers/clk/imx/clk-sccg-pll.c writel(val, pll->base + PLL_CFG0); pll 380 drivers/clk/imx/clk-sccg-pll.c val = readl_relaxed(pll->base + PLL_CFG2); pll 388 drivers/clk/imx/clk-sccg-pll.c writel_relaxed(val, pll->base + PLL_CFG2); pll 390 drivers/clk/imx/clk-sccg-pll.c return clk_sccg_pll_wait_lock(pll); pll 395 drivers/clk/imx/clk-sccg-pll.c struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); pll 397 drivers/clk/imx/clk-sccg-pll.c u8 ret = pll->parent; pll 399 drivers/clk/imx/clk-sccg-pll.c val = readl(pll->base + PLL_CFG0); pll 401 drivers/clk/imx/clk-sccg-pll.c ret = pll->bypass2; pll 403 drivers/clk/imx/clk-sccg-pll.c ret = pll->bypass1; pll 409 drivers/clk/imx/clk-sccg-pll.c struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); pll 412 drivers/clk/imx/clk-sccg-pll.c val = readl(pll->base + PLL_CFG0); pll 414 drivers/clk/imx/clk-sccg-pll.c val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass); pll 415 drivers/clk/imx/clk-sccg-pll.c writel(val, pll->base + PLL_CFG0); pll 417 drivers/clk/imx/clk-sccg-pll.c return clk_sccg_pll_wait_lock(pll); pll 427 drivers/clk/imx/clk-sccg-pll.c struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); pll 428 drivers/clk/imx/clk-sccg-pll.c struct clk_sccg_pll_setup *setup = &pll->setup; pll 438 drivers/clk/imx/clk-sccg-pll.c bypass_parent_index = pll->bypass2; pll 441 drivers/clk/imx/clk-sccg-pll.c bypass_parent_index = pll->bypass1; pll 444 drivers/clk/imx/clk-sccg-pll.c bypass_parent_index = pll->parent; pll 465 drivers/clk/imx/clk-sccg-pll.c struct clk_sccg_pll *pll = to_clk_sccg_pll(hw); pll 466 drivers/clk/imx/clk-sccg-pll.c struct clk_sccg_pll_setup *setup = &pll->setup; pll 516 drivers/clk/imx/clk-sccg-pll.c struct clk_sccg_pll *pll; pll 521 drivers/clk/imx/clk-sccg-pll.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 522 drivers/clk/imx/clk-sccg-pll.c if (!pll) pll 525 drivers/clk/imx/clk-sccg-pll.c pll->parent = parent; pll 526 drivers/clk/imx/clk-sccg-pll.c pll->bypass1 = bypass1; pll 527 drivers/clk/imx/clk-sccg-pll.c pll->bypass2 = bypass2; pll 529 drivers/clk/imx/clk-sccg-pll.c pll->base = base; pll 537 drivers/clk/imx/clk-sccg-pll.c pll->base = base; pll 538 drivers/clk/imx/clk-sccg-pll.c pll->hw.init = &init; pll 540 drivers/clk/imx/clk-sccg-pll.c hw = &pll->hw; pll 544 drivers/clk/imx/clk-sccg-pll.c kfree(pll); pll 53 drivers/clk/imx/clk.h #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \ pll 54 drivers/clk/imx/clk.h to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)) pll 450 drivers/clk/imx/clk.h struct clk *div, struct clk *mux, struct clk *pll, pll 84 drivers/clk/ingenic/cgu.c pll_info = &clk_info->pll; pll 120 drivers/clk/ingenic/cgu.c pll_info = &clk_info->pll; pll 128 drivers/clk/ingenic/cgu.c n = min_t(unsigned, n, 1 << clk_info->pll.n_bits); pll 132 drivers/clk/ingenic/cgu.c m = min_t(unsigned, m, 1 << clk_info->pll.m_bits); pll 174 drivers/clk/ingenic/cgu.c const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; pll 208 drivers/clk/ingenic/cgu.c const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; pll 243 drivers/clk/ingenic/cgu.c const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; pll 261 drivers/clk/ingenic/cgu.c const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; pll 159 drivers/clk/ingenic/cgu.h struct ingenic_cgu_pll_info pll; pll 55 drivers/clk/ingenic/jz4725b-cgu.c .pll = { pll 70 drivers/clk/ingenic/jz4740-cgu.c .pll = { pll 103 drivers/clk/ingenic/jz4770-cgu.c .pll = { pll 125 drivers/clk/ingenic/jz4770-cgu.c .pll = { pll 242 drivers/clk/ingenic/jz4780-cgu.c .pll = DEF_PLL(APLL), pll 248 drivers/clk/ingenic/jz4780-cgu.c .pll = DEF_PLL(MPLL), pll 254 drivers/clk/ingenic/jz4780-cgu.c .pll = DEF_PLL(EPLL), pll 260 drivers/clk/ingenic/jz4780-cgu.c .pll = DEF_PLL(VPLL), pll 78 drivers/clk/keystone/pll.c struct clk_pll *pll = to_clk_pll(hw); pll 79 drivers/clk/keystone/pll.c struct clk_pll_data *pll_data = pll->pll_data; pll 126 drivers/clk/keystone/pll.c struct clk_pll *pll; pll 129 drivers/clk/keystone/pll.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 130 drivers/clk/keystone/pll.c if (!pll) pll 139 drivers/clk/keystone/pll.c pll->pll_data = pll_data; pll 140 drivers/clk/keystone/pll.c pll->hw.init = &init; pll 142 drivers/clk/keystone/pll.c clk = clk_register(NULL, &pll->hw); pll 148 drivers/clk/keystone/pll.c kfree(pll); pll 22 drivers/clk/loongson1/clk-loongson1b.c u32 pll, rate; pll 24 drivers/clk/loongson1/clk-loongson1b.c pll = __raw_readl(LS1X_CLK_PLL_FREQ); pll 25 drivers/clk/loongson1/clk-loongson1b.c rate = 12 + (pll & GENMASK(5, 0)); pll 21 drivers/clk/loongson1/clk-loongson1c.c u32 pll, rate; pll 23 drivers/clk/loongson1/clk-loongson1c.c pll = __raw_readl(LS1X_CLK_PLL_FREQ); pll 24 drivers/clk/loongson1/clk-loongson1c.c rate = ((pll >> 8) & 0xff) + ((pll >> 16) & 0xff); pll 57 drivers/clk/mediatek/clk-pll.c struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); pll 59 drivers/clk/mediatek/clk-pll.c return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; pll 62 drivers/clk/mediatek/clk-pll.c static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, pll 65 drivers/clk/mediatek/clk-pll.c int pcwbits = pll->data->pcwbits; pll 72 drivers/clk/mediatek/clk-pll.c ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; pll 89 drivers/clk/mediatek/clk-pll.c static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll) pll 93 drivers/clk/mediatek/clk-pll.c if (pll->tuner_en_addr) { pll 94 drivers/clk/mediatek/clk-pll.c r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); pll 95 drivers/clk/mediatek/clk-pll.c writel(r, pll->tuner_en_addr); pll 96 drivers/clk/mediatek/clk-pll.c } else if (pll->tuner_addr) { pll 97 drivers/clk/mediatek/clk-pll.c r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; pll 98 drivers/clk/mediatek/clk-pll.c writel(r, pll->tuner_addr); pll 102 drivers/clk/mediatek/clk-pll.c static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll) pll 106 drivers/clk/mediatek/clk-pll.c if (pll->tuner_en_addr) { pll 107 drivers/clk/mediatek/clk-pll.c r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit); pll 108 drivers/clk/mediatek/clk-pll.c writel(r, pll->tuner_en_addr); pll 109 drivers/clk/mediatek/clk-pll.c } else if (pll->tuner_addr) { pll 110 drivers/clk/mediatek/clk-pll.c r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; pll 111 drivers/clk/mediatek/clk-pll.c writel(r, pll->tuner_addr); pll 115 drivers/clk/mediatek/clk-pll.c static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, pll 121 drivers/clk/mediatek/clk-pll.c __mtk_pll_tuner_disable(pll); pll 124 drivers/clk/mediatek/clk-pll.c val = readl(pll->pd_addr); pll 125 drivers/clk/mediatek/clk-pll.c val &= ~(POSTDIV_MASK << pll->data->pd_shift); pll 126 drivers/clk/mediatek/clk-pll.c val |= (ffs(postdiv) - 1) << pll->data->pd_shift; pll 129 drivers/clk/mediatek/clk-pll.c if (pll->pd_addr != pll->pcw_addr) { pll 130 drivers/clk/mediatek/clk-pll.c writel(val, pll->pd_addr); pll 131 drivers/clk/mediatek/clk-pll.c val = readl(pll->pcw_addr); pll 135 drivers/clk/mediatek/clk-pll.c val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1, pll 136 drivers/clk/mediatek/clk-pll.c pll->data->pcw_shift); pll 137 drivers/clk/mediatek/clk-pll.c val |= pcw << pll->data->pcw_shift; pll 138 drivers/clk/mediatek/clk-pll.c writel(val, pll->pcw_addr); pll 139 drivers/clk/mediatek/clk-pll.c chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; pll 140 drivers/clk/mediatek/clk-pll.c writel(chg, pll->pcw_chg_addr); pll 141 drivers/clk/mediatek/clk-pll.c if (pll->tuner_addr) pll 142 drivers/clk/mediatek/clk-pll.c writel(val + 1, pll->tuner_addr); pll 145 drivers/clk/mediatek/clk-pll.c __mtk_pll_tuner_enable(pll); pll 159 drivers/clk/mediatek/clk-pll.c static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, pll 162 drivers/clk/mediatek/clk-pll.c unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ); pll 163 drivers/clk/mediatek/clk-pll.c const struct mtk_pll_div_table *div_table = pll->data->div_table; pll 168 drivers/clk/mediatek/clk-pll.c if (freq > pll->data->fmax) pll 169 drivers/clk/mediatek/clk-pll.c freq = pll->data->fmax; pll 189 drivers/clk/mediatek/clk-pll.c ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; pll 190 drivers/clk/mediatek/clk-pll.c _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits); pll 199 drivers/clk/mediatek/clk-pll.c struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); pll 203 drivers/clk/mediatek/clk-pll.c mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); pll 204 drivers/clk/mediatek/clk-pll.c mtk_pll_set_rate_regs(pll, pcw, postdiv); pll 212 drivers/clk/mediatek/clk-pll.c struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); pll 216 drivers/clk/mediatek/clk-pll.c postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK; pll 219 drivers/clk/mediatek/clk-pll.c pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift; pll 220 drivers/clk/mediatek/clk-pll.c pcw &= GENMASK(pll->data->pcwbits - 1, 0); pll 222 drivers/clk/mediatek/clk-pll.c return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv); pll 228 drivers/clk/mediatek/clk-pll.c struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); pll 232 drivers/clk/mediatek/clk-pll.c mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate); pll 234 drivers/clk/mediatek/clk-pll.c return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv); pll 239 drivers/clk/mediatek/clk-pll.c struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); pll 242 drivers/clk/mediatek/clk-pll.c r = readl(pll->pwr_addr) | CON0_PWR_ON; pll 243 drivers/clk/mediatek/clk-pll.c writel(r, pll->pwr_addr); pll 246 drivers/clk/mediatek/clk-pll.c r = readl(pll->pwr_addr) & ~CON0_ISO_EN; pll 247 drivers/clk/mediatek/clk-pll.c writel(r, pll->pwr_addr); pll 250 drivers/clk/mediatek/clk-pll.c r = readl(pll->base_addr + REG_CON0); pll 251 drivers/clk/mediatek/clk-pll.c r |= pll->data->en_mask; pll 252 drivers/clk/mediatek/clk-pll.c writel(r, pll->base_addr + REG_CON0); pll 254 drivers/clk/mediatek/clk-pll.c __mtk_pll_tuner_enable(pll); pll 258 drivers/clk/mediatek/clk-pll.c if (pll->data->flags & HAVE_RST_BAR) { pll 259 drivers/clk/mediatek/clk-pll.c r = readl(pll->base_addr + REG_CON0); pll 260 drivers/clk/mediatek/clk-pll.c r |= pll->data->rst_bar_mask; pll 261 drivers/clk/mediatek/clk-pll.c writel(r, pll->base_addr + REG_CON0); pll 269 drivers/clk/mediatek/clk-pll.c struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); pll 272 drivers/clk/mediatek/clk-pll.c if (pll->data->flags & HAVE_RST_BAR) { pll 273 drivers/clk/mediatek/clk-pll.c r = readl(pll->base_addr + REG_CON0); pll 274 drivers/clk/mediatek/clk-pll.c r &= ~pll->data->rst_bar_mask; pll 275 drivers/clk/mediatek/clk-pll.c writel(r, pll->base_addr + REG_CON0); pll 278 drivers/clk/mediatek/clk-pll.c __mtk_pll_tuner_disable(pll); pll 280 drivers/clk/mediatek/clk-pll.c r = readl(pll->base_addr + REG_CON0); pll 282 drivers/clk/mediatek/clk-pll.c writel(r, pll->base_addr + REG_CON0); pll 284 drivers/clk/mediatek/clk-pll.c r = readl(pll->pwr_addr) | CON0_ISO_EN; pll 285 drivers/clk/mediatek/clk-pll.c writel(r, pll->pwr_addr); pll 287 drivers/clk/mediatek/clk-pll.c r = readl(pll->pwr_addr) & ~CON0_PWR_ON; pll 288 drivers/clk/mediatek/clk-pll.c writel(r, pll->pwr_addr); pll 303 drivers/clk/mediatek/clk-pll.c struct mtk_clk_pll *pll; pll 308 drivers/clk/mediatek/clk-pll.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 309 drivers/clk/mediatek/clk-pll.c if (!pll) pll 312 drivers/clk/mediatek/clk-pll.c pll->base_addr = base + data->reg; pll 313 drivers/clk/mediatek/clk-pll.c pll->pwr_addr = base + data->pwr_reg; pll 314 drivers/clk/mediatek/clk-pll.c pll->pd_addr = base + data->pd_reg; pll 315 drivers/clk/mediatek/clk-pll.c pll->pcw_addr = base + data->pcw_reg; pll 317 drivers/clk/mediatek/clk-pll.c pll->pcw_chg_addr = base + data->pcw_chg_reg; pll 319 drivers/clk/mediatek/clk-pll.c pll->pcw_chg_addr = pll->base_addr + REG_CON1; pll 321 drivers/clk/mediatek/clk-pll.c pll->tuner_addr = base + data->tuner_reg; pll 323 drivers/clk/mediatek/clk-pll.c pll->tuner_en_addr = base + data->tuner_en_reg; pll 324 drivers/clk/mediatek/clk-pll.c pll->hw.init = &init; pll 325 drivers/clk/mediatek/clk-pll.c pll->data = data; pll 336 drivers/clk/mediatek/clk-pll.c clk = clk_register(NULL, &pll->hw); pll 339 drivers/clk/mediatek/clk-pll.c kfree(pll); pll 358 drivers/clk/mediatek/clk-pll.c const struct mtk_pll_data *pll = &plls[i]; pll 360 drivers/clk/mediatek/clk-pll.c clk = mtk_clk_register_pll(pll, base); pll 364 drivers/clk/mediatek/clk-pll.c pll->name, PTR_ERR(clk)); pll 368 drivers/clk/mediatek/clk-pll.c clk_data->clks[pll->id] = clk; pll 46 drivers/clk/meson/clk-pll.c static int __pll_round_closest_mult(struct meson_clk_pll_data *pll) pll 48 drivers/clk/meson/clk-pll.c if ((pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) && pll 49 drivers/clk/meson/clk-pll.c !MESON_PARM_APPLICABLE(&pll->frac)) pll 58 drivers/clk/meson/clk-pll.c struct meson_clk_pll_data *pll) pll 62 drivers/clk/meson/clk-pll.c if (frac && MESON_PARM_APPLICABLE(&pll->frac)) { pll 66 drivers/clk/meson/clk-pll.c (1 << pll->frac.width)); pll 76 drivers/clk/meson/clk-pll.c struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); pll 79 drivers/clk/meson/clk-pll.c n = meson_parm_read(clk->map, &pll->n); pll 89 drivers/clk/meson/clk-pll.c m = meson_parm_read(clk->map, &pll->m); pll 91 drivers/clk/meson/clk-pll.c frac = MESON_PARM_APPLICABLE(&pll->frac) ? pll 92 drivers/clk/meson/clk-pll.c meson_parm_read(clk->map, &pll->frac) : pll 95 drivers/clk/meson/clk-pll.c return __pll_params_to_rate(parent_rate, m, n, frac, pll); pll 102 drivers/clk/meson/clk-pll.c struct meson_clk_pll_data *pll) pll 104 drivers/clk/meson/clk-pll.c unsigned int frac_max = (1 << pll->frac.width); pll 111 drivers/clk/meson/clk-pll.c if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) pll 124 drivers/clk/meson/clk-pll.c struct meson_clk_pll_data *pll) pll 126 drivers/clk/meson/clk-pll.c if (__pll_round_closest_mult(pll)) { pll 142 drivers/clk/meson/clk-pll.c struct meson_clk_pll_data *pll) pll 144 drivers/clk/meson/clk-pll.c if (!pll->table[index].n) pll 147 drivers/clk/meson/clk-pll.c *m = pll->table[index].m; pll 148 drivers/clk/meson/clk-pll.c *n = pll->table[index].n; pll 156 drivers/clk/meson/clk-pll.c struct meson_clk_pll_data *pll) pll 160 drivers/clk/meson/clk-pll.c if (__pll_round_closest_mult(pll)) pll 171 drivers/clk/meson/clk-pll.c struct meson_clk_pll_data *pll) pll 176 drivers/clk/meson/clk-pll.c if (*n >= (1 << pll->n.width)) pll 181 drivers/clk/meson/clk-pll.c if (rate <= pll->range->min * parent_rate) { pll 182 drivers/clk/meson/clk-pll.c *m = pll->range->min; pll 184 drivers/clk/meson/clk-pll.c } else if (rate >= pll->range->max * parent_rate) { pll 185 drivers/clk/meson/clk-pll.c *m = pll->range->max; pll 190 drivers/clk/meson/clk-pll.c *m = meson_clk_get_pll_range_m(rate, parent_rate, *n, pll); pll 193 drivers/clk/meson/clk-pll.c if (*m >= (1 << pll->m.width)) pll 204 drivers/clk/meson/clk-pll.c struct meson_clk_pll_data *pll) pll 206 drivers/clk/meson/clk-pll.c if (pll->range) pll 208 drivers/clk/meson/clk-pll.c index, m, n, pll); pll 209 drivers/clk/meson/clk-pll.c else if (pll->table) pll 210 drivers/clk/meson/clk-pll.c return meson_clk_get_pll_table_index(index, m, n, pll); pll 219 drivers/clk/meson/clk-pll.c struct meson_clk_pll_data *pll) pll 227 drivers/clk/meson/clk-pll.c i, &m, &n, pll); pll 231 drivers/clk/meson/clk-pll.c now = __pll_params_to_rate(parent_rate, m, n, 0, pll); pll 232 drivers/clk/meson/clk-pll.c if (meson_clk_pll_is_better(rate, best, now, pll)) { pll 249 drivers/clk/meson/clk-pll.c struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); pll 254 drivers/clk/meson/clk-pll.c ret = meson_clk_get_pll_settings(rate, *parent_rate, &m, &n, pll); pll 258 drivers/clk/meson/clk-pll.c round = __pll_params_to_rate(*parent_rate, m, n, 0, pll); pll 260 drivers/clk/meson/clk-pll.c if (!MESON_PARM_APPLICABLE(&pll->frac) || rate == round) pll 267 drivers/clk/meson/clk-pll.c frac = __pll_params_with_frac(rate, *parent_rate, m, n, pll); pll 269 drivers/clk/meson/clk-pll.c return __pll_params_to_rate(*parent_rate, m, n, frac, pll); pll 275 drivers/clk/meson/clk-pll.c struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); pll 280 drivers/clk/meson/clk-pll.c if (meson_parm_read(clk->map, &pll->l)) pll 292 drivers/clk/meson/clk-pll.c struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); pll 294 drivers/clk/meson/clk-pll.c if (pll->init_count) { pll 295 drivers/clk/meson/clk-pll.c meson_parm_write(clk->map, &pll->rst, 1); pll 296 drivers/clk/meson/clk-pll.c regmap_multi_reg_write(clk->map, pll->init_regs, pll 297 drivers/clk/meson/clk-pll.c pll->init_count); pll 298 drivers/clk/meson/clk-pll.c meson_parm_write(clk->map, &pll->rst, 0); pll 305 drivers/clk/meson/clk-pll.c struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); pll 307 drivers/clk/meson/clk-pll.c if (meson_parm_read(clk->map, &pll->rst) || pll 308 drivers/clk/meson/clk-pll.c !meson_parm_read(clk->map, &pll->en) || pll 309 drivers/clk/meson/clk-pll.c !meson_parm_read(clk->map, &pll->l)) pll 328 drivers/clk/meson/clk-pll.c struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); pll 335 drivers/clk/meson/clk-pll.c meson_parm_write(clk->map, &pll->rst, 1); pll 338 drivers/clk/meson/clk-pll.c meson_parm_write(clk->map, &pll->en, 1); pll 341 drivers/clk/meson/clk-pll.c meson_parm_write(clk->map, &pll->rst, 0); pll 352 drivers/clk/meson/clk-pll.c struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); pll 355 drivers/clk/meson/clk-pll.c meson_parm_write(clk->map, &pll->rst, 1); pll 358 drivers/clk/meson/clk-pll.c meson_parm_write(clk->map, &pll->en, 0); pll 365 drivers/clk/meson/clk-pll.c struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); pll 374 drivers/clk/meson/clk-pll.c ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll); pll 378 drivers/clk/meson/clk-pll.c enabled = meson_parm_read(clk->map, &pll->en); pll 382 drivers/clk/meson/clk-pll.c meson_parm_write(clk->map, &pll->n, n); pll 383 drivers/clk/meson/clk-pll.c meson_parm_write(clk->map, &pll->m, m); pll 385 drivers/clk/meson/clk-pll.c if (MESON_PARM_APPLICABLE(&pll->frac)) { pll 386 drivers/clk/meson/clk-pll.c frac = __pll_params_with_frac(rate, parent_rate, m, n, pll); pll 387 drivers/clk/meson/clk-pll.c meson_parm_write(clk->map, &pll->frac, frac); pll 596 drivers/clk/microchip/clk-core.c static unsigned long spll_calc_mult_div(struct pic32_sys_pll *pll, pll 606 drivers/clk/microchip/clk-core.c parent_rate /= pll->idiv; pll 645 drivers/clk/microchip/clk-core.c struct pic32_sys_pll *pll = clkhw_to_spll(hw); pll 650 drivers/clk/microchip/clk-core.c v = readl(pll->ctrl_reg); pll 658 drivers/clk/microchip/clk-core.c pll_in_rate = parent_rate / pll->idiv; pll 669 drivers/clk/microchip/clk-core.c struct pic32_sys_pll *pll = clkhw_to_spll(hw); pll 671 drivers/clk/microchip/clk-core.c return spll_calc_mult_div(pll, rate, *parent_rate, NULL, NULL); pll 677 drivers/clk/microchip/clk-core.c struct pic32_sys_pll *pll = clkhw_to_spll(hw); pll 682 drivers/clk/microchip/clk-core.c ret = spll_calc_mult_div(pll, rate, parent_rate, &mult, &odiv); pll 697 drivers/clk/microchip/clk-core.c spin_lock_irqsave(&pll->core->reg_lock, flags); pll 700 drivers/clk/microchip/clk-core.c v = readl(pll->ctrl_reg); pll 708 drivers/clk/microchip/clk-core.c writel(v, pll->ctrl_reg); pll 716 drivers/clk/microchip/clk-core.c err = readl_poll_timeout_atomic(pll->status_reg, v, pll 717 drivers/clk/microchip/clk-core.c v & pll->lock_mask, 1, 100); pll 718 drivers/clk/microchip/clk-core.c spin_unlock_irqrestore(&pll->core->reg_lock, flags); pll 113 drivers/clk/mxs/clk-imx23.c clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); pll 34 drivers/clk/mxs/clk-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 36 drivers/clk/mxs/clk-pll.c writel_relaxed(1 << pll->power, pll->base + SET); pll 45 drivers/clk/mxs/clk-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 47 drivers/clk/mxs/clk-pll.c writel_relaxed(1 << pll->power, pll->base + CLR); pll 52 drivers/clk/mxs/clk-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 54 drivers/clk/mxs/clk-pll.c writel_relaxed(1 << 31, pll->base + CLR); pll 61 drivers/clk/mxs/clk-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 63 drivers/clk/mxs/clk-pll.c writel_relaxed(1 << 31, pll->base + SET); pll 69 drivers/clk/mxs/clk-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 71 drivers/clk/mxs/clk-pll.c return pll->rate; pll 85 drivers/clk/mxs/clk-pll.c struct clk_pll *pll; pll 89 drivers/clk/mxs/clk-pll.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 90 drivers/clk/mxs/clk-pll.c if (!pll) pll 99 drivers/clk/mxs/clk-pll.c pll->base = base; pll 100 drivers/clk/mxs/clk-pll.c pll->rate = rate; pll 101 drivers/clk/mxs/clk-pll.c pll->power = power; pll 102 drivers/clk/mxs/clk-pll.c pll->hw.init = &init; pll 104 drivers/clk/mxs/clk-pll.c clk = clk_register(NULL, &pll->hw); pll 106 drivers/clk/mxs/clk-pll.c kfree(pll); pll 268 drivers/clk/nxp/clk-lpc18xx-cgu.c struct lpc18xx_pll pll; pll 353 drivers/clk/nxp/clk-lpc18xx-cgu.c struct lpc18xx_pll *pll = to_lpc_pll(hw); pll 356 drivers/clk/nxp/clk-lpc18xx-cgu.c ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL); pll 357 drivers/clk/nxp/clk-lpc18xx-cgu.c mdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV); pll 358 drivers/clk/nxp/clk-lpc18xx-cgu.c npdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV); pll 399 drivers/clk/nxp/clk-lpc18xx-cgu.c struct lpc18xx_pll *pll = to_lpc_pll(hw); pll 419 drivers/clk/nxp/clk-lpc18xx-cgu.c ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL); pll 423 drivers/clk/nxp/clk-lpc18xx-cgu.c writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL); pll 426 drivers/clk/nxp/clk-lpc18xx-cgu.c writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV); pll 427 drivers/clk/nxp/clk-lpc18xx-cgu.c writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV); pll 431 drivers/clk/nxp/clk-lpc18xx-cgu.c writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL); pll 434 drivers/clk/nxp/clk-lpc18xx-cgu.c stat = readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT); pll 437 drivers/clk/nxp/clk-lpc18xx-cgu.c writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL); pll 457 drivers/clk/nxp/clk-lpc18xx-cgu.c struct lpc18xx_pll *pll = to_lpc_pll(hw); pll 462 drivers/clk/nxp/clk-lpc18xx-cgu.c stat = readl(pll->reg + LPC18XX_CGU_PLL1_STAT); pll 463 drivers/clk/nxp/clk-lpc18xx-cgu.c ctrl = readl(pll->reg + LPC18XX_CGU_PLL1_CTRL); pll 588 drivers/clk/nxp/clk-lpc18xx-cgu.c clk->pll.reg = base; pll 596 drivers/clk/nxp/clk-lpc18xx-cgu.c &clk->pll.hw, clk->pll_ops, pll 1058 drivers/clk/nxp/clk-lpc32xx.c struct lpc32xx_pll_clk pll; pll 1100 drivers/clk/nxp/clk-lpc32xx.c .pll = { \ pll 1416 drivers/clk/nxp/clk-lpc32xx.c hw = &clk_hw->hw0.pll.hw; pll 78 drivers/clk/pistachio/clk-pll.c static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg) pll 80 drivers/clk/pistachio/clk-pll.c return readl(pll->base + reg); pll 83 drivers/clk/pistachio/clk-pll.c static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg) pll 85 drivers/clk/pistachio/clk-pll.c writel(val, pll->base + reg); pll 88 drivers/clk/pistachio/clk-pll.c static inline void pll_lock(struct pistachio_clk_pll *pll) pll 90 drivers/clk/pistachio/clk-pll.c while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK)) pll 107 drivers/clk/pistachio/clk-pll.c struct pistachio_clk_pll *pll = to_pistachio_pll(hw); pll 110 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_DSMPD; pll 116 drivers/clk/pistachio/clk-pll.c struct pistachio_clk_pll *pll = to_pistachio_pll(hw); pll 119 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL3); pll 125 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL3); pll 129 drivers/clk/pistachio/clk-pll.c pll_get_params(struct pistachio_clk_pll *pll, unsigned long fref, pll 134 drivers/clk/pistachio/clk-pll.c for (i = 0; i < pll->nr_rates; i++) { pll 135 drivers/clk/pistachio/clk-pll.c if (pll->rates[i].fref == fref && pll->rates[i].fout == fout) pll 136 drivers/clk/pistachio/clk-pll.c return &pll->rates[i]; pll 145 drivers/clk/pistachio/clk-pll.c struct pistachio_clk_pll *pll = to_pistachio_pll(hw); pll 148 drivers/clk/pistachio/clk-pll.c for (i = 0; i < pll->nr_rates; i++) { pll 149 drivers/clk/pistachio/clk-pll.c if (i > 0 && pll->rates[i].fref == *parent_rate && pll 150 drivers/clk/pistachio/clk-pll.c pll->rates[i].fout <= rate) pll 151 drivers/clk/pistachio/clk-pll.c return pll->rates[i - 1].fout; pll 154 drivers/clk/pistachio/clk-pll.c return pll->rates[0].fout; pll 159 drivers/clk/pistachio/clk-pll.c struct pistachio_clk_pll *pll = to_pistachio_pll(hw); pll 162 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL3); pll 165 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL3); pll 167 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL4); pll 169 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL4); pll 171 drivers/clk/pistachio/clk-pll.c pll_lock(pll); pll 178 drivers/clk/pistachio/clk-pll.c struct pistachio_clk_pll *pll = to_pistachio_pll(hw); pll 181 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL3); pll 183 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL3); pll 188 drivers/clk/pistachio/clk-pll.c struct pistachio_clk_pll *pll = to_pistachio_pll(hw); pll 190 drivers/clk/pistachio/clk-pll.c return !(pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_PD); pll 196 drivers/clk/pistachio/clk-pll.c struct pistachio_clk_pll *pll = to_pistachio_pll(hw); pll 205 drivers/clk/pistachio/clk-pll.c params = pll_get_params(pll, parent_rate, rate); pll 226 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL1); pll 231 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL1); pll 233 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL2); pll 255 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL2); pll 264 drivers/clk/pistachio/clk-pll.c pll_lock(pll); pll 272 drivers/clk/pistachio/clk-pll.c struct pistachio_clk_pll *pll = to_pistachio_pll(hw); pll 275 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL1); pll 279 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL2); pll 316 drivers/clk/pistachio/clk-pll.c struct pistachio_clk_pll *pll = to_pistachio_pll(hw); pll 319 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL1); pll 322 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL1); pll 324 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL2); pll 326 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL2); pll 328 drivers/clk/pistachio/clk-pll.c pll_lock(pll); pll 335 drivers/clk/pistachio/clk-pll.c struct pistachio_clk_pll *pll = to_pistachio_pll(hw); pll 338 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL1); pll 340 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL1); pll 345 drivers/clk/pistachio/clk-pll.c struct pistachio_clk_pll *pll = to_pistachio_pll(hw); pll 347 drivers/clk/pistachio/clk-pll.c return !(pll_readl(pll, PLL_CTRL1) & PLL_INT_CTRL1_PD); pll 353 drivers/clk/pistachio/clk-pll.c struct pistachio_clk_pll *pll = to_pistachio_pll(hw); pll 362 drivers/clk/pistachio/clk-pll.c params = pll_get_params(pll, parent_rate, rate); pll 379 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL1); pll 401 drivers/clk/pistachio/clk-pll.c pll_writel(pll, val, PLL_CTRL1); pll 404 drivers/clk/pistachio/clk-pll.c pll_lock(pll); pll 412 drivers/clk/pistachio/clk-pll.c struct pistachio_clk_pll *pll = to_pistachio_pll(hw); pll 416 drivers/clk/pistachio/clk-pll.c val = pll_readl(pll, PLL_CTRL1); pll 452 drivers/clk/pistachio/clk-pll.c struct pistachio_clk_pll *pll; pll 456 drivers/clk/pistachio/clk-pll.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 457 drivers/clk/pistachio/clk-pll.c if (!pll) pll 480 drivers/clk/pistachio/clk-pll.c kfree(pll); pll 484 drivers/clk/pistachio/clk-pll.c pll->hw.init = &init; pll 485 drivers/clk/pistachio/clk-pll.c pll->base = base; pll 486 drivers/clk/pistachio/clk-pll.c pll->rates = rates; pll 487 drivers/clk/pistachio/clk-pll.c pll->nr_rates = nr_rates; pll 489 drivers/clk/pistachio/clk-pll.c clk = clk_register(NULL, &pll->hw); pll 491 drivers/clk/pistachio/clk-pll.c kfree(pll); pll 497 drivers/clk/pistachio/clk-pll.c struct pistachio_pll *pll, pll 504 drivers/clk/pistachio/clk-pll.c clk = pll_register(pll[i].name, pll[i].parent, pll 505 drivers/clk/pistachio/clk-pll.c 0, p->base + pll[i].reg_base, pll 506 drivers/clk/pistachio/clk-pll.c pll[i].type, pll[i].rates, pll 507 drivers/clk/pistachio/clk-pll.c pll[i].nr_rates); pll 508 drivers/clk/pistachio/clk-pll.c p->clk_data.clks[pll[i].id] = clk; pll 165 drivers/clk/pistachio/clk.h struct pistachio_pll *pll, pll 42 drivers/clk/qcom/a53-pll.c struct clk_pll *pll; pll 47 drivers/clk/qcom/a53-pll.c pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); pll 48 drivers/clk/qcom/a53-pll.c if (!pll) pll 60 drivers/clk/qcom/a53-pll.c pll->l_reg = 0x04; pll 61 drivers/clk/qcom/a53-pll.c pll->m_reg = 0x08; pll 62 drivers/clk/qcom/a53-pll.c pll->n_reg = 0x0c; pll 63 drivers/clk/qcom/a53-pll.c pll->config_reg = 0x14; pll 64 drivers/clk/qcom/a53-pll.c pll->mode_reg = 0x00; pll 65 drivers/clk/qcom/a53-pll.c pll->status_reg = 0x1c; pll 66 drivers/clk/qcom/a53-pll.c pll->status_bit = 16; pll 67 drivers/clk/qcom/a53-pll.c pll->freq_tbl = a53pll_freq; pll 74 drivers/clk/qcom/a53-pll.c pll->clkr.hw.init = &init; pll 76 drivers/clk/qcom/a53-pll.c ret = devm_clk_register_regmap(dev, &pll->clkr); pll 83 drivers/clk/qcom/a53-pll.c &pll->clkr.hw); pll 159 drivers/clk/qcom/clk-alpha-pll.c static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, pll 165 drivers/clk/qcom/clk-alpha-pll.c const char *name = clk_hw_get_name(&pll->clkr.hw); pll 167 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); pll 172 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); pll 187 drivers/clk/qcom/clk-alpha-pll.c #define wait_for_pll_enable_active(pll) \ pll 188 drivers/clk/qcom/clk-alpha-pll.c wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable") pll 190 drivers/clk/qcom/clk-alpha-pll.c #define wait_for_pll_enable_lock(pll) \ pll 191 drivers/clk/qcom/clk-alpha-pll.c wait_for_pll(pll, PLL_LOCK_DET, 0, "enable") pll 193 drivers/clk/qcom/clk-alpha-pll.c #define wait_for_pll_disable(pll) \ pll 194 drivers/clk/qcom/clk-alpha-pll.c wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable") pll 196 drivers/clk/qcom/clk-alpha-pll.c #define wait_for_pll_offline(pll) \ pll 197 drivers/clk/qcom/clk-alpha-pll.c wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") pll 199 drivers/clk/qcom/clk-alpha-pll.c #define wait_for_pll_update(pll) \ pll 200 drivers/clk/qcom/clk-alpha-pll.c wait_for_pll(pll, PLL_UPDATE, 1, "update") pll 202 drivers/clk/qcom/clk-alpha-pll.c #define wait_for_pll_update_ack_set(pll) \ pll 203 drivers/clk/qcom/clk-alpha-pll.c wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") pll 205 drivers/clk/qcom/clk-alpha-pll.c #define wait_for_pll_update_ack_clear(pll) \ pll 206 drivers/clk/qcom/clk-alpha-pll.c wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") pll 208 drivers/clk/qcom/clk-alpha-pll.c void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, pll 213 drivers/clk/qcom/clk-alpha-pll.c regmap_write(regmap, PLL_L_VAL(pll), config->l); pll 214 drivers/clk/qcom/clk-alpha-pll.c regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); pll 215 drivers/clk/qcom/clk-alpha-pll.c regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); pll 217 drivers/clk/qcom/clk-alpha-pll.c if (pll_has_64bit_config(pll)) pll 218 drivers/clk/qcom/clk-alpha-pll.c regmap_write(regmap, PLL_CONFIG_CTL_U(pll), pll 221 drivers/clk/qcom/clk-alpha-pll.c if (pll_alpha_width(pll) > 32) pll 222 drivers/clk/qcom/clk-alpha-pll.c regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); pll 242 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); pll 244 drivers/clk/qcom/clk-alpha-pll.c if (pll->flags & SUPPORTS_FSM_MODE) pll 245 drivers/clk/qcom/clk-alpha-pll.c qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); pll 252 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 255 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); pll 261 drivers/clk/qcom/clk-alpha-pll.c if (pll->flags & SUPPORTS_OFFLINE_REQ) pll 264 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); pll 271 drivers/clk/qcom/clk-alpha-pll.c return wait_for_pll_enable_active(pll); pll 277 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 280 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); pll 284 drivers/clk/qcom/clk-alpha-pll.c if (pll->flags & SUPPORTS_OFFLINE_REQ) { pll 285 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), pll 290 drivers/clk/qcom/clk-alpha-pll.c ret = wait_for_pll_offline(pll); pll 296 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), pll 301 drivers/clk/qcom/clk-alpha-pll.c wait_for_pll_disable(pll); pll 307 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 310 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); pll 330 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 334 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); pll 343 drivers/clk/qcom/clk-alpha-pll.c return wait_for_pll_enable_active(pll); pll 350 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), pll 362 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), pll 367 drivers/clk/qcom/clk-alpha-pll.c ret = wait_for_pll_enable_lock(pll); pll 371 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), pll 382 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 385 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); pll 396 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); pll 403 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); pll 441 drivers/clk/qcom/clk-alpha-pll.c alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) pll 443 drivers/clk/qcom/clk-alpha-pll.c const struct pll_vco *v = pll->vco_table; pll 444 drivers/clk/qcom/clk-alpha-pll.c const struct pll_vco *end = v + pll->num_vco; pll 458 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 459 drivers/clk/qcom/clk-alpha-pll.c u32 alpha_width = pll_alpha_width(pll); pll 461 drivers/clk/qcom/clk-alpha-pll.c regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); pll 463 drivers/clk/qcom/clk-alpha-pll.c regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); pll 465 drivers/clk/qcom/clk-alpha-pll.c regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); pll 467 drivers/clk/qcom/clk-alpha-pll.c regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), pll 482 drivers/clk/qcom/clk-alpha-pll.c static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) pll 487 drivers/clk/qcom/clk-alpha-pll.c regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); pll 490 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, pll 504 drivers/clk/qcom/clk-alpha-pll.c ret = wait_for_pll_update_ack_set(pll); pll 508 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); pll 510 drivers/clk/qcom/clk-alpha-pll.c ret = wait_for_pll_update(pll); pll 515 drivers/clk/qcom/clk-alpha-pll.c ret = wait_for_pll_update_ack_clear(pll); pll 525 drivers/clk/qcom/clk-alpha-pll.c static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, pll 528 drivers/clk/qcom/clk-alpha-pll.c if (!is_enabled(&pll->clkr.hw) || pll 529 drivers/clk/qcom/clk-alpha-pll.c !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) pll 532 drivers/clk/qcom/clk-alpha-pll.c return __clk_alpha_pll_update_latch(pll); pll 539 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 541 drivers/clk/qcom/clk-alpha-pll.c u32 l, alpha_width = pll_alpha_width(pll); pll 545 drivers/clk/qcom/clk-alpha-pll.c vco = alpha_pll_find_vco(pll, rate); pll 546 drivers/clk/qcom/clk-alpha-pll.c if (pll->vco_table && !vco) { pll 551 drivers/clk/qcom/clk-alpha-pll.c regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); pll 557 drivers/clk/qcom/clk-alpha-pll.c regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); pll 559 drivers/clk/qcom/clk-alpha-pll.c regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); pll 562 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), pll 567 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), pll 570 drivers/clk/qcom/clk-alpha-pll.c return clk_alpha_pll_update_latch(pll, is_enabled); pll 590 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 591 drivers/clk/qcom/clk-alpha-pll.c u32 l, alpha_width = pll_alpha_width(pll); pll 596 drivers/clk/qcom/clk-alpha-pll.c if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) pll 599 drivers/clk/qcom/clk-alpha-pll.c min_freq = pll->vco_table[0].min_freq; pll 600 drivers/clk/qcom/clk-alpha-pll.c max_freq = pll->vco_table[pll->num_vco - 1].max_freq; pll 656 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 659 drivers/clk/qcom/clk-alpha-pll.c regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); pll 660 drivers/clk/qcom/clk-alpha-pll.c regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); pll 663 drivers/clk/qcom/clk-alpha-pll.c regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); pll 709 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 714 drivers/clk/qcom/clk-alpha-pll.c regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); pll 717 drivers/clk/qcom/clk-alpha-pll.c regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); pll 730 drivers/clk/qcom/clk-alpha-pll.c regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); pll 733 drivers/clk/qcom/clk-alpha-pll.c return wait_for_pll_enable_lock(pll); pll 736 drivers/clk/qcom/clk-alpha-pll.c regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); pll 737 drivers/clk/qcom/clk-alpha-pll.c regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); pll 740 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), pll 743 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), pll 757 drivers/clk/qcom/clk-alpha-pll.c static int trion_pll_is_enabled(struct clk_alpha_pll *pll, pll 763 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval); pll 764 drivers/clk/qcom/clk-alpha-pll.c ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_regval); pll 773 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 775 drivers/clk/qcom/clk-alpha-pll.c return trion_pll_is_enabled(pll, pll->clkr.regmap); pll 780 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 781 drivers/clk/qcom/clk-alpha-pll.c struct regmap *regmap = pll->clkr.regmap; pll 785 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(regmap, PLL_MODE(pll), &val); pll 794 drivers/clk/qcom/clk-alpha-pll.c return wait_for_pll_enable_active(pll); pll 798 drivers/clk/qcom/clk-alpha-pll.c regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_RUN); pll 800 drivers/clk/qcom/clk-alpha-pll.c ret = wait_for_pll_enable_lock(pll); pll 805 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), pll 811 drivers/clk/qcom/clk-alpha-pll.c return regmap_update_bits(regmap, PLL_MODE(pll), pll 817 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 818 drivers/clk/qcom/clk-alpha-pll.c struct regmap *regmap = pll->clkr.regmap; pll 822 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(regmap, PLL_MODE(pll), &val); pll 833 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); pll 838 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), pll 844 drivers/clk/qcom/clk-alpha-pll.c regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_STANDBY); pll 845 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); pll 851 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 852 drivers/clk/qcom/clk-alpha-pll.c struct regmap *regmap = pll->clkr.regmap; pll 856 drivers/clk/qcom/clk-alpha-pll.c regmap_read(regmap, PLL_L_VAL(pll), &l); pll 857 drivers/clk/qcom/clk-alpha-pll.c regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac); pll 865 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 872 drivers/clk/qcom/clk-alpha-pll.c if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) pll 875 drivers/clk/qcom/clk-alpha-pll.c min_freq = pll->vco_table[0].min_freq; pll 876 drivers/clk/qcom/clk-alpha-pll.c max_freq = pll->vco_table[pll->num_vco - 1].max_freq; pll 923 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); pll 926 drivers/clk/qcom/clk-alpha-pll.c regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); pll 929 drivers/clk/qcom/clk-alpha-pll.c ctl &= PLL_POST_DIV_MASK(pll); pll 954 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); pll 957 drivers/clk/qcom/clk-alpha-pll.c if (pll->width == 2) pll 963 drivers/clk/qcom/clk-alpha-pll.c pll->width, CLK_DIVIDER_POWER_OF_TWO); pll 970 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); pll 973 drivers/clk/qcom/clk-alpha-pll.c regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); pll 976 drivers/clk/qcom/clk-alpha-pll.c ctl &= BIT(pll->width) - 1; pll 988 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); pll 994 drivers/clk/qcom/clk-alpha-pll.c return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), pll 995 drivers/clk/qcom/clk-alpha-pll.c PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, pll 1012 drivers/clk/qcom/clk-alpha-pll.c void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, pll 1018 drivers/clk/qcom/clk-alpha-pll.c regmap_write(regmap, PLL_L_VAL(pll), config->l); pll 1021 drivers/clk/qcom/clk-alpha-pll.c regmap_write(regmap, PLL_FRAC(pll), config->alpha); pll 1024 drivers/clk/qcom/clk-alpha-pll.c regmap_write(regmap, PLL_CONFIG_CTL(pll), pll 1030 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); pll 1033 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, pll 1036 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); pll 1043 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 1045 drivers/clk/qcom/clk-alpha-pll.c struct regmap *regmap = pll->clkr.regmap; pll 1047 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(regmap, PLL_MODE(pll), &val); pll 1056 drivers/clk/qcom/clk-alpha-pll.c return wait_for_pll_enable_active(pll); pll 1059 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); pll 1067 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); pll 1071 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY); pll 1075 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, pll 1080 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_RUN); pll 1084 drivers/clk/qcom/clk-alpha-pll.c ret = wait_for_pll_enable_lock(pll); pll 1088 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), pll 1093 drivers/clk/qcom/clk-alpha-pll.c return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, pll 1100 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 1102 drivers/clk/qcom/clk-alpha-pll.c struct regmap *regmap = pll->clkr.regmap; pll 1104 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(regmap, PLL_MODE(pll), &val); pll 1114 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); pll 1119 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), FABIA_PLL_OUT_MASK, pll 1125 drivers/clk/qcom/clk-alpha-pll.c regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY); pll 1131 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 1132 drivers/clk/qcom/clk-alpha-pll.c u32 l, frac, alpha_width = pll_alpha_width(pll); pll 1134 drivers/clk/qcom/clk-alpha-pll.c regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); pll 1135 drivers/clk/qcom/clk-alpha-pll.c regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac); pll 1143 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); pll 1144 drivers/clk/qcom/clk-alpha-pll.c u32 val, l, alpha_width = pll_alpha_width(pll); pll 1149 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); pll 1164 drivers/clk/qcom/clk-alpha-pll.c regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); pll 1165 drivers/clk/qcom/clk-alpha-pll.c regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); pll 1167 drivers/clk/qcom/clk-alpha-pll.c return __clk_alpha_pll_update_latch(pll); pll 1192 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); pll 1196 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); pll 1200 drivers/clk/qcom/clk-alpha-pll.c val >>= pll->post_div_shift; pll 1201 drivers/clk/qcom/clk-alpha-pll.c val &= BIT(pll->width) - 1; pll 1203 drivers/clk/qcom/clk-alpha-pll.c for (i = 0; i < pll->num_post_div; i++) { pll 1204 drivers/clk/qcom/clk-alpha-pll.c if (pll->post_div_table[i].val == val) { pll 1205 drivers/clk/qcom/clk-alpha-pll.c div = pll->post_div_table[i].div; pll 1216 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); pll 1217 drivers/clk/qcom/clk-alpha-pll.c struct regmap *regmap = pll->clkr.regmap; pll 1220 drivers/clk/qcom/clk-alpha-pll.c regmap_read(regmap, PLL_USER_CTL(pll), &val); pll 1222 drivers/clk/qcom/clk-alpha-pll.c val >>= pll->post_div_shift; pll 1223 drivers/clk/qcom/clk-alpha-pll.c val &= PLL_POST_DIV_MASK(pll); pll 1225 drivers/clk/qcom/clk-alpha-pll.c for (i = 0; i < pll->num_post_div; i++) { pll 1226 drivers/clk/qcom/clk-alpha-pll.c if (pll->post_div_table[i].val == val) { pll 1227 drivers/clk/qcom/clk-alpha-pll.c div = pll->post_div_table[i].div; pll 1239 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); pll 1241 drivers/clk/qcom/clk-alpha-pll.c return divider_round_rate(hw, rate, prate, pll->post_div_table, pll 1242 drivers/clk/qcom/clk-alpha-pll.c pll->width, CLK_DIVIDER_ROUND_CLOSEST); pll 1249 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); pll 1250 drivers/clk/qcom/clk-alpha-pll.c struct regmap *regmap = pll->clkr.regmap; pll 1254 drivers/clk/qcom/clk-alpha-pll.c for (i = 0; i < pll->num_post_div; i++) { pll 1255 drivers/clk/qcom/clk-alpha-pll.c if (pll->post_div_table[i].div == div) { pll 1256 drivers/clk/qcom/clk-alpha-pll.c val = pll->post_div_table[i].val; pll 1261 drivers/clk/qcom/clk-alpha-pll.c return regmap_update_bits(regmap, PLL_USER_CTL(pll), pll 1262 drivers/clk/qcom/clk-alpha-pll.c PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, pll 1276 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); pll 1278 drivers/clk/qcom/clk-alpha-pll.c return divider_round_rate(hw, rate, prate, pll->post_div_table, pll 1279 drivers/clk/qcom/clk-alpha-pll.c pll->width, CLK_DIVIDER_ROUND_CLOSEST); pll 1285 drivers/clk/qcom/clk-alpha-pll.c struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); pll 1292 drivers/clk/qcom/clk-alpha-pll.c ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); pll 1300 drivers/clk/qcom/clk-alpha-pll.c for (i = 0; i < pll->num_post_div; i++) { pll 1301 drivers/clk/qcom/clk-alpha-pll.c if (pll->post_div_table[i].div == div) { pll 1302 drivers/clk/qcom/clk-alpha-pll.c val = pll->post_div_table[i].val; pll 1307 drivers/clk/qcom/clk-alpha-pll.c return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), pll 1308 drivers/clk/qcom/clk-alpha-pll.c (BIT(pll->width) - 1) << pll->post_div_shift, pll 1309 drivers/clk/qcom/clk-alpha-pll.c val << pll->post_div_shift); pll 121 drivers/clk/qcom/clk-alpha-pll.h void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, pll 123 drivers/clk/qcom/clk-alpha-pll.h void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, pll 26 drivers/clk/qcom/clk-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 31 drivers/clk/qcom/clk-pll.c ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); pll 40 drivers/clk/qcom/clk-pll.c ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, pll 52 drivers/clk/qcom/clk-pll.c ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, pll 61 drivers/clk/qcom/clk-pll.c return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, pll 67 drivers/clk/qcom/clk-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 71 drivers/clk/qcom/clk-pll.c regmap_read(pll->clkr.regmap, pll->mode_reg, &val); pll 76 drivers/clk/qcom/clk-pll.c regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0); pll 82 drivers/clk/qcom/clk-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 87 drivers/clk/qcom/clk-pll.c regmap_read(pll->clkr.regmap, pll->l_reg, &l); pll 88 drivers/clk/qcom/clk-pll.c regmap_read(pll->clkr.regmap, pll->m_reg, &m); pll 89 drivers/clk/qcom/clk-pll.c regmap_read(pll->clkr.regmap, pll->n_reg, &n); pll 102 drivers/clk/qcom/clk-pll.c if (pll->post_div_width) { pll 103 drivers/clk/qcom/clk-pll.c regmap_read(pll->clkr.regmap, pll->config_reg, &config); pll 104 drivers/clk/qcom/clk-pll.c config >>= pll->post_div_shift; pll 105 drivers/clk/qcom/clk-pll.c config &= BIT(pll->post_div_width) - 1; pll 128 drivers/clk/qcom/clk-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 131 drivers/clk/qcom/clk-pll.c f = find_freq(pll->freq_tbl, req->rate); pll 143 drivers/clk/qcom/clk-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 149 drivers/clk/qcom/clk-pll.c f = find_freq(pll->freq_tbl, rate); pll 153 drivers/clk/qcom/clk-pll.c regmap_read(pll->clkr.regmap, pll->mode_reg, &mode); pll 159 drivers/clk/qcom/clk-pll.c regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l); pll 160 drivers/clk/qcom/clk-pll.c regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m); pll 161 drivers/clk/qcom/clk-pll.c regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n); pll 162 drivers/clk/qcom/clk-pll.c regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits); pll 179 drivers/clk/qcom/clk-pll.c static int wait_for_pll(struct clk_pll *pll) pll 184 drivers/clk/qcom/clk-pll.c const char *name = clk_hw_get_name(&pll->clkr.hw); pll 188 drivers/clk/qcom/clk-pll.c ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val); pll 191 drivers/clk/qcom/clk-pll.c if (val & BIT(pll->status_bit)) pll 218 drivers/clk/qcom/clk-pll.c static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap, pll 224 drivers/clk/qcom/clk-pll.c regmap_write(regmap, pll->l_reg, config->l); pll 225 drivers/clk/qcom/clk-pll.c regmap_write(regmap, pll->m_reg, config->m); pll 226 drivers/clk/qcom/clk-pll.c regmap_write(regmap, pll->n_reg, config->n); pll 242 drivers/clk/qcom/clk-pll.c regmap_update_bits(regmap, pll->config_reg, mask, val); pll 245 drivers/clk/qcom/clk-pll.c void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap, pll 248 drivers/clk/qcom/clk-pll.c clk_pll_configure(pll, regmap, config); pll 250 drivers/clk/qcom/clk-pll.c qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 8); pll 254 drivers/clk/qcom/clk-pll.c void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, pll 257 drivers/clk/qcom/clk-pll.c clk_pll_configure(pll, regmap, config); pll 259 drivers/clk/qcom/clk-pll.c qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 0); pll 265 drivers/clk/qcom/clk-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 269 drivers/clk/qcom/clk-pll.c ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode); pll 274 drivers/clk/qcom/clk-pll.c ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, pll 286 drivers/clk/qcom/clk-pll.c ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, pll 291 drivers/clk/qcom/clk-pll.c ret = wait_for_pll(pll); pll 296 drivers/clk/qcom/clk-pll.c return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, pll 303 drivers/clk/qcom/clk-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 309 drivers/clk/qcom/clk-pll.c f = find_freq(pll->freq_tbl, rate); pll 313 drivers/clk/qcom/clk-pll.c regmap_read(pll->clkr.regmap, pll->mode_reg, &mode); pll 319 drivers/clk/qcom/clk-pll.c regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l); pll 320 drivers/clk/qcom/clk-pll.c regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m); pll 321 drivers/clk/qcom/clk-pll.c regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n); pll 76 drivers/clk/qcom/clk-pll.h void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap, pll 78 drivers/clk/qcom/clk-pll.h void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, pll 1254 drivers/clk/qcom/gcc-ipq4019.c struct clk_fepll *pll = to_clk_fepll(hw); pll 1258 drivers/clk/qcom/gcc-ipq4019.c f = qcom_find_freq(pll->freq_tbl, rate); pll 1276 drivers/clk/qcom/gcc-ipq4019.c struct clk_fepll *pll = to_clk_fepll(hw); pll 1281 drivers/clk/qcom/gcc-ipq4019.c f = qcom_find_freq(pll->freq_tbl, rate); pll 1285 drivers/clk/qcom/gcc-ipq4019.c mask = (BIT(pll->cdiv.width) - 1) << pll->cdiv.shift; pll 1286 drivers/clk/qcom/gcc-ipq4019.c ret = regmap_update_bits(pll->cdiv.clkr.regmap, pll 1287 drivers/clk/qcom/gcc-ipq4019.c pll->cdiv.reg, mask, pll 1288 drivers/clk/qcom/gcc-ipq4019.c f->pre_div << pll->cdiv.shift); pll 1308 drivers/clk/qcom/gcc-ipq4019.c struct clk_fepll *pll = to_clk_fepll(hw); pll 1312 drivers/clk/qcom/gcc-ipq4019.c regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv); pll 1313 drivers/clk/qcom/gcc-ipq4019.c cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1); pll 1325 drivers/clk/qcom/gcc-ipq4019.c rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2; pll 1384 drivers/clk/qcom/gcc-ipq4019.c struct clk_fepll *pll = to_clk_fepll(hw); pll 1389 drivers/clk/qcom/gcc-ipq4019.c if (pll->fixed_div) { pll 1390 drivers/clk/qcom/gcc-ipq4019.c pre_div = pll->fixed_div; pll 1392 drivers/clk/qcom/gcc-ipq4019.c regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv); pll 1393 drivers/clk/qcom/gcc-ipq4019.c cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1); pll 1395 drivers/clk/qcom/gcc-ipq4019.c for (clkt = pll->div_table; clkt->div; clkt++) { pll 1401 drivers/clk/qcom/gcc-ipq4019.c rate = clk_fepll_vco_calc_rate(pll, parent_rate); pll 50 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll, unsigned long rate) pll 52 drivers/clk/rockchip/clk-pll.c const struct rockchip_pll_rate_table *rate_table = pll->rate_table; pll 55 drivers/clk/rockchip/clk-pll.c for (i = 0; i < pll->rate_count; i++) { pll 66 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 67 drivers/clk/rockchip/clk-pll.c const struct rockchip_pll_rate_table *rate_table = pll->rate_table; pll 71 drivers/clk/rockchip/clk-pll.c for (i = 0; i < pll->rate_count; i++) { pll 85 drivers/clk/rockchip/clk-pll.c static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) pll 87 drivers/clk/rockchip/clk-pll.c struct regmap *grf = pll->ctx->grf; pll 92 drivers/clk/rockchip/clk-pll.c ret = regmap_read(grf, pll->lock_offset, &val); pll 99 drivers/clk/rockchip/clk-pll.c if (val & BIT(pll->lock_shift)) pll 128 drivers/clk/rockchip/clk-pll.c static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll, pll 133 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0)); pll 139 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1)); pll 147 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); pll 155 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 159 drivers/clk/rockchip/clk-pll.c rockchip_rk3036_pll_get_params(pll, &cur); pll 178 drivers/clk/rockchip/clk-pll.c static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, pll 181 drivers/clk/rockchip/clk-pll.c const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; pll 182 drivers/clk/rockchip/clk-pll.c struct clk_mux *pll_mux = &pll->pll_mux; pll 193 drivers/clk/rockchip/clk-pll.c rockchip_rk3036_pll_get_params(pll, &cur); pll 207 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3036_PLLCON(0)); pll 215 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3036_PLLCON(1)); pll 218 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); pll 221 drivers/clk/rockchip/clk-pll.c writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); pll 224 drivers/clk/rockchip/clk-pll.c ret = rockchip_pll_wait_lock(pll); pll 228 drivers/clk/rockchip/clk-pll.c rockchip_rk3036_pll_set_params(pll, &cur); pll 240 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 247 drivers/clk/rockchip/clk-pll.c rate = rockchip_get_pll_settings(pll, drate); pll 254 drivers/clk/rockchip/clk-pll.c return rockchip_rk3036_pll_set_params(pll, rate); pll 259 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 262 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3036_PLLCON(1)); pll 263 drivers/clk/rockchip/clk-pll.c rockchip_pll_wait_lock(pll); pll 270 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 274 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3036_PLLCON(1)); pll 279 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 280 drivers/clk/rockchip/clk-pll.c u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1)); pll 287 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 292 drivers/clk/rockchip/clk-pll.c if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) pll 296 drivers/clk/rockchip/clk-pll.c rate = rockchip_get_pll_settings(pll, drate); pll 302 drivers/clk/rockchip/clk-pll.c rockchip_rk3036_pll_get_params(pll, &cur); pll 327 drivers/clk/rockchip/clk-pll.c rockchip_rk3036_pll_set_params(pll, rate); pll 367 drivers/clk/rockchip/clk-pll.c static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll, pll 372 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); pll 378 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); pll 382 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); pll 390 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 395 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); pll 402 drivers/clk/rockchip/clk-pll.c rockchip_rk3066_pll_get_params(pll, &cur); pll 411 drivers/clk/rockchip/clk-pll.c static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll, pll 414 drivers/clk/rockchip/clk-pll.c const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; pll 415 drivers/clk/rockchip/clk-pll.c struct clk_mux *pll_mux = &pll->pll_mux; pll 424 drivers/clk/rockchip/clk-pll.c rockchip_rk3066_pll_get_params(pll, &cur); pll 435 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3066_PLLCON(3)); pll 442 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3066_PLLCON(0)); pll 446 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3066_PLLCON(1)); pll 449 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3066_PLLCON(2)); pll 453 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3066_PLLCON(3)); pll 457 drivers/clk/rockchip/clk-pll.c ret = rockchip_pll_wait_lock(pll); pll 461 drivers/clk/rockchip/clk-pll.c rockchip_rk3066_pll_set_params(pll, &cur); pll 473 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 480 drivers/clk/rockchip/clk-pll.c rate = rockchip_get_pll_settings(pll, drate); pll 487 drivers/clk/rockchip/clk-pll.c return rockchip_rk3066_pll_set_params(pll, rate); pll 492 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 495 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3066_PLLCON(3)); pll 496 drivers/clk/rockchip/clk-pll.c rockchip_pll_wait_lock(pll); pll 503 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 507 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3066_PLLCON(3)); pll 512 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 513 drivers/clk/rockchip/clk-pll.c u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3)); pll 520 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 525 drivers/clk/rockchip/clk-pll.c if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) pll 529 drivers/clk/rockchip/clk-pll.c rate = rockchip_get_pll_settings(pll, drate); pll 535 drivers/clk/rockchip/clk-pll.c rockchip_rk3066_pll_get_params(pll, &cur); pll 544 drivers/clk/rockchip/clk-pll.c rockchip_rk3066_pll_set_params(pll, rate); pll 585 drivers/clk/rockchip/clk-pll.c static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll) pll 592 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); pll 603 drivers/clk/rockchip/clk-pll.c static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll, pll 608 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0)); pll 612 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1)); pll 620 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); pll 624 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3)); pll 632 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 636 drivers/clk/rockchip/clk-pll.c rockchip_rk3399_pll_get_params(pll, &cur); pll 655 drivers/clk/rockchip/clk-pll.c static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, pll 658 drivers/clk/rockchip/clk-pll.c const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; pll 659 drivers/clk/rockchip/clk-pll.c struct clk_mux *pll_mux = &pll->pll_mux; pll 670 drivers/clk/rockchip/clk-pll.c rockchip_rk3399_pll_get_params(pll, &cur); pll 682 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3399_PLLCON(0)); pll 690 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3399_PLLCON(1)); pll 693 drivers/clk/rockchip/clk-pll.c pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); pll 696 drivers/clk/rockchip/clk-pll.c writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2)); pll 700 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3399_PLLCON(3)); pll 703 drivers/clk/rockchip/clk-pll.c ret = rockchip_rk3399_pll_wait_lock(pll); pll 707 drivers/clk/rockchip/clk-pll.c rockchip_rk3399_pll_set_params(pll, &cur); pll 719 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 726 drivers/clk/rockchip/clk-pll.c rate = rockchip_get_pll_settings(pll, drate); pll 733 drivers/clk/rockchip/clk-pll.c return rockchip_rk3399_pll_set_params(pll, rate); pll 738 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 741 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3399_PLLCON(3)); pll 742 drivers/clk/rockchip/clk-pll.c rockchip_rk3399_pll_wait_lock(pll); pll 749 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 753 drivers/clk/rockchip/clk-pll.c pll->reg_base + RK3399_PLLCON(3)); pll 758 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 759 drivers/clk/rockchip/clk-pll.c u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3)); pll 766 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); pll 771 drivers/clk/rockchip/clk-pll.c if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) pll 775 drivers/clk/rockchip/clk-pll.c rate = rockchip_get_pll_settings(pll, drate); pll 781 drivers/clk/rockchip/clk-pll.c rockchip_rk3399_pll_get_params(pll, &cur); pll 806 drivers/clk/rockchip/clk-pll.c rockchip_rk3399_pll_set_params(pll, rate); pll 841 drivers/clk/rockchip/clk-pll.c struct rockchip_clk_pll *pll; pll 855 drivers/clk/rockchip/clk-pll.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 856 drivers/clk/rockchip/clk-pll.c if (!pll) pll 860 drivers/clk/rockchip/clk-pll.c pll->pll_mux_ops = &clk_mux_ops; pll 861 drivers/clk/rockchip/clk-pll.c pll_mux = &pll->pll_mux; pll 885 drivers/clk/rockchip/clk-pll.c init.ops = pll->pll_mux_ops; pll 912 drivers/clk/rockchip/clk-pll.c pll->rate_count = len; pll 913 drivers/clk/rockchip/clk-pll.c pll->rate_table = kmemdup(rate_table, pll 914 drivers/clk/rockchip/clk-pll.c pll->rate_count * pll 917 drivers/clk/rockchip/clk-pll.c WARN(!pll->rate_table, pll 925 drivers/clk/rockchip/clk-pll.c if (!pll->rate_table || IS_ERR(ctx->grf)) pll 931 drivers/clk/rockchip/clk-pll.c if (!pll->rate_table || IS_ERR(ctx->grf)) pll 937 drivers/clk/rockchip/clk-pll.c if (!pll->rate_table) pll 947 drivers/clk/rockchip/clk-pll.c pll->hw.init = &init; pll 948 drivers/clk/rockchip/clk-pll.c pll->type = pll_type; pll 949 drivers/clk/rockchip/clk-pll.c pll->reg_base = ctx->reg_base + con_offset; pll 950 drivers/clk/rockchip/clk-pll.c pll->lock_offset = grf_lock_offset; pll 951 drivers/clk/rockchip/clk-pll.c pll->lock_shift = lock_shift; pll 952 drivers/clk/rockchip/clk-pll.c pll->flags = clk_pll_flags; pll 953 drivers/clk/rockchip/clk-pll.c pll->lock = &ctx->lock; pll 954 drivers/clk/rockchip/clk-pll.c pll->ctx = ctx; pll 956 drivers/clk/rockchip/clk-pll.c pll_clk = clk_register(NULL, &pll->hw); pll 969 drivers/clk/rockchip/clk-pll.c kfree(pll); pll 857 drivers/clk/rockchip/clk-rk3188.c struct rockchip_pll_clock *pll = &rk3188_pll_clks[i]; pll 860 drivers/clk/rockchip/clk-rk3188.c if (!pll->rate_table) pll 863 drivers/clk/rockchip/clk-rk3188.c rate = pll->rate_table; pll 36 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll, unsigned long rate) pll 38 drivers/clk/samsung/clk-pll.c const struct samsung_pll_rate_table *rate_table = pll->rate_table; pll 41 drivers/clk/samsung/clk-pll.c for (i = 0; i < pll->rate_count; i++) { pll 52 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 53 drivers/clk/samsung/clk-pll.c const struct samsung_pll_rate_table *rate_table = pll->rate_table; pll 57 drivers/clk/samsung/clk-pll.c for (i = 0; i < pll->rate_count; i++) { pll 68 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 71 drivers/clk/samsung/clk-pll.c tmp = readl_relaxed(pll->con_reg); pll 72 drivers/clk/samsung/clk-pll.c tmp |= BIT(pll->enable_offs); pll 73 drivers/clk/samsung/clk-pll.c writel_relaxed(tmp, pll->con_reg); pll 78 drivers/clk/samsung/clk-pll.c tmp = readl_relaxed(pll->con_reg); pll 79 drivers/clk/samsung/clk-pll.c } while (!(tmp & BIT(pll->lock_offs))); pll 86 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 89 drivers/clk/samsung/clk-pll.c tmp = readl_relaxed(pll->con_reg); pll 90 drivers/clk/samsung/clk-pll.c tmp &= ~BIT(pll->enable_offs); pll 91 drivers/clk/samsung/clk-pll.c writel_relaxed(tmp, pll->con_reg); pll 108 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 112 drivers/clk/samsung/clk-pll.c pll_con = readl_relaxed(pll->con_reg); pll 141 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 145 drivers/clk/samsung/clk-pll.c pll_con = readl_relaxed(pll->con_reg); pll 178 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 182 drivers/clk/samsung/clk-pll.c pll_con = readl_relaxed(pll->con_reg); pll 207 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 212 drivers/clk/samsung/clk-pll.c rate = samsung_get_pll_settings(pll, drate); pll 219 drivers/clk/samsung/clk-pll.c tmp = readl_relaxed(pll->con_reg); pll 225 drivers/clk/samsung/clk-pll.c writel_relaxed(tmp, pll->con_reg); pll 232 drivers/clk/samsung/clk-pll.c pll->lock_reg); pll 241 drivers/clk/samsung/clk-pll.c writel_relaxed(tmp, pll->con_reg); pll 244 drivers/clk/samsung/clk-pll.c if (tmp & BIT(pll->enable_offs)) { pll 247 drivers/clk/samsung/clk-pll.c tmp = readl_relaxed(pll->con_reg); pll 248 drivers/clk/samsung/clk-pll.c } while (!(tmp & BIT(pll->lock_offs))); pll 285 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 290 drivers/clk/samsung/clk-pll.c pll_con0 = readl_relaxed(pll->con_reg); pll 291 drivers/clk/samsung/clk-pll.c pll_con1 = readl_relaxed(pll->con_reg + 4); pll 320 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 324 drivers/clk/samsung/clk-pll.c rate = samsung_get_pll_settings(pll, drate); pll 331 drivers/clk/samsung/clk-pll.c pll_con0 = readl_relaxed(pll->con_reg); pll 332 drivers/clk/samsung/clk-pll.c pll_con1 = readl_relaxed(pll->con_reg + 4); pll 338 drivers/clk/samsung/clk-pll.c writel_relaxed(pll_con0, pll->con_reg); pll 344 drivers/clk/samsung/clk-pll.c writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); pll 353 drivers/clk/samsung/clk-pll.c writel_relaxed(pll_con0, pll->con_reg); pll 357 drivers/clk/samsung/clk-pll.c writel_relaxed(pll_con1, pll->con_reg + 4); pll 360 drivers/clk/samsung/clk-pll.c if (pll_con0 & BIT(pll->enable_offs)) { pll 363 drivers/clk/samsung/clk-pll.c tmp = readl_relaxed(pll->con_reg); pll 364 drivers/clk/samsung/clk-pll.c } while (!(tmp & BIT(pll->lock_offs))); pll 403 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 407 drivers/clk/samsung/clk-pll.c pll_con = readl_relaxed(pll->con_reg); pll 412 drivers/clk/samsung/clk-pll.c if (pll->type == pll_4508) pll 437 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 443 drivers/clk/samsung/clk-pll.c rate = samsung_get_pll_settings(pll, drate); pll 450 drivers/clk/samsung/clk-pll.c con0 = readl_relaxed(pll->con_reg); pll 451 drivers/clk/samsung/clk-pll.c con1 = readl_relaxed(pll->con_reg + 0x4); pll 457 drivers/clk/samsung/clk-pll.c writel_relaxed(con0, pll->con_reg); pll 471 drivers/clk/samsung/clk-pll.c con1 = readl_relaxed(pll->con_reg + 0x4); pll 476 drivers/clk/samsung/clk-pll.c switch (pll->type) { pll 478 drivers/clk/samsung/clk-pll.c writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); pll 481 drivers/clk/samsung/clk-pll.c writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); pll 488 drivers/clk/samsung/clk-pll.c writel_relaxed(con1, pll->con_reg + 0x4); pll 489 drivers/clk/samsung/clk-pll.c writel_relaxed(con0, pll->con_reg); pll 493 drivers/clk/samsung/clk-pll.c while (!(readl_relaxed(pll->con_reg) & PLL45XX_LOCKED)) { pll 550 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 554 drivers/clk/samsung/clk-pll.c pll_con0 = readl_relaxed(pll->con_reg); pll 555 drivers/clk/samsung/clk-pll.c pll_con1 = readl_relaxed(pll->con_reg + 4); pll 556 drivers/clk/samsung/clk-pll.c mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? pll 560 drivers/clk/samsung/clk-pll.c kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : pll 563 drivers/clk/samsung/clk-pll.c shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10; pll 588 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 594 drivers/clk/samsung/clk-pll.c rate = samsung_get_pll_settings(pll, drate); pll 601 drivers/clk/samsung/clk-pll.c con0 = readl_relaxed(pll->con_reg); pll 602 drivers/clk/samsung/clk-pll.c con1 = readl_relaxed(pll->con_reg + 0x4); pll 608 drivers/clk/samsung/clk-pll.c writel_relaxed(con0, pll->con_reg); pll 620 drivers/clk/samsung/clk-pll.c if (pll->type == pll_1460x) { pll 637 drivers/clk/samsung/clk-pll.c con1 = readl_relaxed(pll->con_reg + 0x4); pll 646 drivers/clk/samsung/clk-pll.c writel_relaxed(lock, pll->lock_reg); pll 647 drivers/clk/samsung/clk-pll.c writel_relaxed(con0, pll->con_reg); pll 648 drivers/clk/samsung/clk-pll.c writel_relaxed(con1, pll->con_reg + 0x4); pll 652 drivers/clk/samsung/clk-pll.c while (!(readl_relaxed(pll->con_reg) & PLL46XX_LOCKED)) { pll 693 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 697 drivers/clk/samsung/clk-pll.c pll_con = readl_relaxed(pll->con_reg); pll 698 drivers/clk/samsung/clk-pll.c if (pll->type == pll_6552_s3c2416) { pll 733 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 737 drivers/clk/samsung/clk-pll.c pll_con0 = readl_relaxed(pll->con_reg); pll 738 drivers/clk/samsung/clk-pll.c pll_con1 = readl_relaxed(pll->con_reg + 0x4); pll 771 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 775 drivers/clk/samsung/clk-pll.c pll_con = readl_relaxed(pll->con_reg); pll 789 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 793 drivers/clk/samsung/clk-pll.c pll_con = readl_relaxed(pll->con_reg); pll 807 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 812 drivers/clk/samsung/clk-pll.c rate = samsung_get_pll_settings(pll, drate); pll 819 drivers/clk/samsung/clk-pll.c tmp = readl_relaxed(pll->con_reg); pll 828 drivers/clk/samsung/clk-pll.c writel_relaxed(tmp, pll->con_reg); pll 838 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 839 drivers/clk/samsung/clk-pll.c u32 pll_en = readl_relaxed(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); pll 847 drivers/clk/samsung/clk-pll.c writel_relaxed(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET); pll 934 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 938 drivers/clk/samsung/clk-pll.c pll_stat = readl_relaxed(pll->con_reg); pll 975 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 979 drivers/clk/samsung/clk-pll.c pll_con = readl_relaxed(pll->con_reg); pll 1003 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 1008 drivers/clk/samsung/clk-pll.c rate = samsung_get_pll_settings(pll, drate); pll 1015 drivers/clk/samsung/clk-pll.c tmp = readl_relaxed(pll->con_reg); pll 1021 drivers/clk/samsung/clk-pll.c writel_relaxed(tmp, pll->con_reg); pll 1027 drivers/clk/samsung/clk-pll.c writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); pll 1036 drivers/clk/samsung/clk-pll.c writel_relaxed(tmp, pll->con_reg); pll 1041 drivers/clk/samsung/clk-pll.c tmp = readl_relaxed(pll->con_reg); pll 1080 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 1085 drivers/clk/samsung/clk-pll.c pll_con0 = readl_relaxed(pll->con_reg); pll 1090 drivers/clk/samsung/clk-pll.c pll_con1 = readl_relaxed(pll->con_reg + 4); pll 1103 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 1108 drivers/clk/samsung/clk-pll.c rate = samsung_get_pll_settings(pll, drate); pll 1115 drivers/clk/samsung/clk-pll.c con0 = readl_relaxed(pll->con_reg); pll 1116 drivers/clk/samsung/clk-pll.c con1 = readl_relaxed(pll->con_reg + 4); pll 1119 drivers/clk/samsung/clk-pll.c writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg); pll 1129 drivers/clk/samsung/clk-pll.c writel_relaxed(con0, pll->con_reg); pll 1133 drivers/clk/samsung/clk-pll.c writel_relaxed(con1, pll->con_reg + 4); pll 1137 drivers/clk/samsung/clk-pll.c con0 = readl_relaxed(pll->con_reg); pll 1176 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 1181 drivers/clk/samsung/clk-pll.c pll_con0 = readl_relaxed(pll->con_reg); pll 1182 drivers/clk/samsung/clk-pll.c pll_con2 = readl_relaxed(pll->con_reg + 8); pll 1198 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll = to_clk_pll(hw); pll 1202 drivers/clk/samsung/clk-pll.c rate = samsung_get_pll_settings(pll, drate); pll 1209 drivers/clk/samsung/clk-pll.c pll_con0 = readl_relaxed(pll->con_reg); pll 1210 drivers/clk/samsung/clk-pll.c pll_con2 = readl_relaxed(pll->con_reg + 8); pll 1227 drivers/clk/samsung/clk-pll.c writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); pll 1229 drivers/clk/samsung/clk-pll.c writel_relaxed(pll_con0, pll->con_reg); pll 1230 drivers/clk/samsung/clk-pll.c writel_relaxed(pll_con2, pll->con_reg + 8); pll 1233 drivers/clk/samsung/clk-pll.c tmp = readl_relaxed(pll->con_reg); pll 1253 drivers/clk/samsung/clk-pll.c struct samsung_clk_pll *pll; pll 1257 drivers/clk/samsung/clk-pll.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 1258 drivers/clk/samsung/clk-pll.c if (!pll) { pll 1274 drivers/clk/samsung/clk-pll.c pll->rate_count = len; pll 1275 drivers/clk/samsung/clk-pll.c pll->rate_table = kmemdup(pll_clk->rate_table, pll 1276 drivers/clk/samsung/clk-pll.c pll->rate_count * pll 1279 drivers/clk/samsung/clk-pll.c WARN(!pll->rate_table, pll 1297 drivers/clk/samsung/clk-pll.c pll->enable_offs = PLL35XX_ENABLE_SHIFT; pll 1298 drivers/clk/samsung/clk-pll.c pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; pll 1299 drivers/clk/samsung/clk-pll.c if (!pll->rate_table) pll 1309 drivers/clk/samsung/clk-pll.c if (!pll->rate_table) pll 1317 drivers/clk/samsung/clk-pll.c pll->enable_offs = PLL36XX_ENABLE_SHIFT; pll 1318 drivers/clk/samsung/clk-pll.c pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT; pll 1319 drivers/clk/samsung/clk-pll.c if (!pll->rate_table) pll 1335 drivers/clk/samsung/clk-pll.c if (!pll->rate_table) pll 1341 drivers/clk/samsung/clk-pll.c if (!pll->rate_table) pll 1347 drivers/clk/samsung/clk-pll.c if (!pll->rate_table) pll 1353 drivers/clk/samsung/clk-pll.c if (!pll->rate_table) pll 1362 drivers/clk/samsung/clk-pll.c if (!pll->rate_table) pll 1368 drivers/clk/samsung/clk-pll.c if (!pll->rate_table) pll 1374 drivers/clk/samsung/clk-pll.c if (!pll->rate_table) pll 1384 drivers/clk/samsung/clk-pll.c pll->hw.init = &init; pll 1385 drivers/clk/samsung/clk-pll.c pll->type = pll_clk->type; pll 1386 drivers/clk/samsung/clk-pll.c pll->lock_reg = base + pll_clk->lock_offset; pll 1387 drivers/clk/samsung/clk-pll.c pll->con_reg = base + pll_clk->con_offset; pll 1389 drivers/clk/samsung/clk-pll.c ret = clk_hw_register(ctx->dev, &pll->hw); pll 1393 drivers/clk/samsung/clk-pll.c kfree(pll); pll 1397 drivers/clk/samsung/clk-pll.c samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id); pll 87 drivers/clk/spear/clk-vco-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 97 drivers/clk/spear/clk-vco-pll.c for (*index = 0; *index < pll->vco->rtbl_cnt; (*index)++) { pll 100 drivers/clk/spear/clk-vco-pll.c *prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index, pll 127 drivers/clk/spear/clk-vco-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 131 drivers/clk/spear/clk-vco-pll.c if (pll->vco->lock) pll 132 drivers/clk/spear/clk-vco-pll.c spin_lock_irqsave(pll->vco->lock, flags); pll 134 drivers/clk/spear/clk-vco-pll.c p = readl_relaxed(pll->vco->cfg_reg); pll 136 drivers/clk/spear/clk-vco-pll.c if (pll->vco->lock) pll 137 drivers/clk/spear/clk-vco-pll.c spin_unlock_irqrestore(pll->vco->lock, flags); pll 147 drivers/clk/spear/clk-vco-pll.c struct clk_pll *pll = to_clk_pll(hw); pll 148 drivers/clk/spear/clk-vco-pll.c struct pll_rate_tbl *rtbl = pll->vco->rtbl; pll 154 drivers/clk/spear/clk-vco-pll.c if (pll->vco->lock) pll 155 drivers/clk/spear/clk-vco-pll.c spin_lock_irqsave(pll->vco->lock, flags); pll 157 drivers/clk/spear/clk-vco-pll.c val = readl_relaxed(pll->vco->cfg_reg); pll 160 drivers/clk/spear/clk-vco-pll.c writel_relaxed(val, pll->vco->cfg_reg); pll 162 drivers/clk/spear/clk-vco-pll.c if (pll->vco->lock) pll 163 drivers/clk/spear/clk-vco-pll.c spin_unlock_irqrestore(pll->vco->lock, flags); pll 283 drivers/clk/spear/clk-vco-pll.c struct clk_pll *pll; pll 298 drivers/clk/spear/clk-vco-pll.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 299 drivers/clk/spear/clk-vco-pll.c if (!pll) pll 310 drivers/clk/spear/clk-vco-pll.c pll->vco = vco; pll 311 drivers/clk/spear/clk-vco-pll.c pll->hw.init = &pll_init; pll 342 drivers/clk/spear/clk-vco-pll.c tpll_clk = clk_register(NULL, &pll->hw); pll 352 drivers/clk/spear/clk-vco-pll.c kfree(pll); pll 18 drivers/clk/sprd/pll.c #define pindex(pll, member) \ pll 19 drivers/clk/sprd/pll.c (pll->factors[member].shift / (8 * sizeof(pll->regs_num))) pll 21 drivers/clk/sprd/pll.c #define pshift(pll, member) \ pll 22 drivers/clk/sprd/pll.c (pll->factors[member].shift % (8 * sizeof(pll->regs_num))) pll 24 drivers/clk/sprd/pll.c #define pwidth(pll, member) \ pll 25 drivers/clk/sprd/pll.c pll->factors[member].width pll 27 drivers/clk/sprd/pll.c #define pmask(pll, member) \ pll 28 drivers/clk/sprd/pll.c ((pwidth(pll, member)) ? \ pll 29 drivers/clk/sprd/pll.c GENMASK(pwidth(pll, member) + pshift(pll, member) - 1, \ pll 30 drivers/clk/sprd/pll.c pshift(pll, member)) : 0) pll 32 drivers/clk/sprd/pll.c #define pinternal(pll, cfg, member) \ pll 33 drivers/clk/sprd/pll.c (cfg[pindex(pll, member)] & pmask(pll, member)) pll 35 drivers/clk/sprd/pll.c #define pinternal_val(pll, cfg, member) \ pll 36 drivers/clk/sprd/pll.c (pinternal(pll, cfg, member) >> pshift(pll, member)) pll 39 drivers/clk/sprd/pll.c sprd_pll_read(const struct sprd_pll *pll, u8 index) pll 41 drivers/clk/sprd/pll.c const struct sprd_clk_common *common = &pll->common; pll 44 drivers/clk/sprd/pll.c if (WARN_ON(index >= pll->regs_num)) pll 53 drivers/clk/sprd/pll.c sprd_pll_write(const struct sprd_pll *pll, u8 index, pll 56 drivers/clk/sprd/pll.c const struct sprd_clk_common *common = &pll->common; pll 60 drivers/clk/sprd/pll.c if (WARN_ON(index >= pll->regs_num)) pll 69 drivers/clk/sprd/pll.c static unsigned long pll_get_refin(const struct sprd_pll *pll) pll 74 drivers/clk/sprd/pll.c if (pwidth(pll, PLL_REFIN)) { pll 75 drivers/clk/sprd/pll.c index = pindex(pll, PLL_REFIN); pll 76 drivers/clk/sprd/pll.c shift = pshift(pll, PLL_REFIN); pll 77 drivers/clk/sprd/pll.c mask = pmask(pll, PLL_REFIN); pll 78 drivers/clk/sprd/pll.c refin_id = (sprd_pll_read(pll, index) & mask) >> shift; pll 97 drivers/clk/sprd/pll.c static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll, pll 101 drivers/clk/sprd/pll.c u32 i, mask, regs_num = pll->regs_num; pll 111 drivers/clk/sprd/pll.c cfg[i] = sprd_pll_read(pll, i); pll 113 drivers/clk/sprd/pll.c refin = pll_get_refin(pll); pll 115 drivers/clk/sprd/pll.c if (pinternal(pll, cfg, PLL_PREDIV)) pll 118 drivers/clk/sprd/pll.c if (pwidth(pll, PLL_POSTDIV) && pll 119 drivers/clk/sprd/pll.c ((pll->fflag == 1 && pinternal(pll, cfg, PLL_POSTDIV)) || pll 120 drivers/clk/sprd/pll.c (!pll->fflag && !pinternal(pll, cfg, PLL_POSTDIV)))) pll 123 drivers/clk/sprd/pll.c if (!pinternal(pll, cfg, PLL_DIV_S)) { pll 124 drivers/clk/sprd/pll.c rate = refin * pinternal_val(pll, cfg, PLL_N) * CLK_PLL_10M; pll 126 drivers/clk/sprd/pll.c nint = pinternal_val(pll, cfg, PLL_NINT); pll 127 drivers/clk/sprd/pll.c if (pinternal(pll, cfg, PLL_SDM_EN)) pll 128 drivers/clk/sprd/pll.c kint = pinternal_val(pll, cfg, PLL_KINT); pll 130 drivers/clk/sprd/pll.c mask = pmask(pll, PLL_KINT); pll 132 drivers/clk/sprd/pll.c k1 = pll->k1; pll 133 drivers/clk/sprd/pll.c k2 = pll->k2; pll 143 drivers/clk/sprd/pll.c #define SPRD_PLL_WRITE_CHECK(pll, i, mask, val) \ pll 144 drivers/clk/sprd/pll.c (((sprd_pll_read(pll, i) & mask) == val) ? 0 : (-EFAULT)) pll 146 drivers/clk/sprd/pll.c static int _sprd_pll_set_rate(const struct sprd_pll *pll, pll 153 drivers/clk/sprd/pll.c u32 regs_num = pll->regs_num, i = 0; pll 161 drivers/clk/sprd/pll.c refin = pll_get_refin(pll); pll 163 drivers/clk/sprd/pll.c mask = pmask(pll, PLL_PREDIV); pll 164 drivers/clk/sprd/pll.c index = pindex(pll, PLL_PREDIV); pll 165 drivers/clk/sprd/pll.c width = pwidth(pll, PLL_PREDIV); pll 166 drivers/clk/sprd/pll.c if (width && (sprd_pll_read(pll, index) & mask)) pll 169 drivers/clk/sprd/pll.c mask = pmask(pll, PLL_POSTDIV); pll 170 drivers/clk/sprd/pll.c index = pindex(pll, PLL_POSTDIV); pll 171 drivers/clk/sprd/pll.c width = pwidth(pll, PLL_POSTDIV); pll 173 drivers/clk/sprd/pll.c if (width && ((pll->fflag == 1 && fvco <= pll->fvco) || pll 174 drivers/clk/sprd/pll.c (pll->fflag == 0 && fvco > pll->fvco))) pll 177 drivers/clk/sprd/pll.c if (width && fvco <= pll->fvco) pll 180 drivers/clk/sprd/pll.c mask = pmask(pll, PLL_DIV_S); pll 181 drivers/clk/sprd/pll.c index = pindex(pll, PLL_DIV_S); pll 185 drivers/clk/sprd/pll.c mask = pmask(pll, PLL_SDM_EN); pll 186 drivers/clk/sprd/pll.c index = pindex(pll, PLL_SDM_EN); pll 191 drivers/clk/sprd/pll.c mask = pmask(pll, PLL_NINT); pll 192 drivers/clk/sprd/pll.c index = pindex(pll, PLL_NINT); pll 193 drivers/clk/sprd/pll.c shift = pshift(pll, PLL_NINT); pll 197 drivers/clk/sprd/pll.c mask = pmask(pll, PLL_KINT); pll 198 drivers/clk/sprd/pll.c index = pindex(pll, PLL_KINT); pll 199 drivers/clk/sprd/pll.c width = pwidth(pll, PLL_KINT); pll 200 drivers/clk/sprd/pll.c shift = pshift(pll, PLL_KINT); pll 207 drivers/clk/sprd/pll.c ibias_val = pll_get_ibias(fvco, pll->itable); pll 209 drivers/clk/sprd/pll.c mask = pmask(pll, PLL_IBIAS); pll 210 drivers/clk/sprd/pll.c index = pindex(pll, PLL_IBIAS); pll 211 drivers/clk/sprd/pll.c shift = pshift(pll, PLL_IBIAS); pll 217 drivers/clk/sprd/pll.c sprd_pll_write(pll, i, cfg[i].msk, cfg[i].val); pll 218 drivers/clk/sprd/pll.c ret |= SPRD_PLL_WRITE_CHECK(pll, i, cfg[i].msk, pll 224 drivers/clk/sprd/pll.c udelay(pll->udelay); pll 233 drivers/clk/sprd/pll.c struct sprd_pll *pll = hw_to_sprd_pll(hw); pll 235 drivers/clk/sprd/pll.c return _sprd_pll_recalc_rate(pll, parent_rate); pll 242 drivers/clk/sprd/pll.c struct sprd_pll *pll = hw_to_sprd_pll(hw); pll 244 drivers/clk/sprd/pll.c return _sprd_pll_set_rate(pll, rate, parent_rate); pll 249 drivers/clk/sprd/pll.c struct sprd_pll *pll = hw_to_sprd_pll(hw); pll 251 drivers/clk/sprd/pll.c udelay(pll->udelay); pll 192 drivers/clk/st/clkgen-fsyn.c struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw); pll 195 drivers/clk/st/clkgen-fsyn.c if (pll->lock) pll 196 drivers/clk/st/clkgen-fsyn.c spin_lock_irqsave(pll->lock, flags); pll 201 drivers/clk/st/clkgen-fsyn.c if (pll->data->reset_present) pll 202 drivers/clk/st/clkgen-fsyn.c CLKGEN_WRITE(pll, nreset, 1); pll 207 drivers/clk/st/clkgen-fsyn.c if (pll->data->bwfilter_present) pll 208 drivers/clk/st/clkgen-fsyn.c CLKGEN_WRITE(pll, ref_bw, PLL_BW_GOODREF); pll 211 drivers/clk/st/clkgen-fsyn.c CLKGEN_WRITE(pll, ndiv, pll->ndiv); pll 216 drivers/clk/st/clkgen-fsyn.c CLKGEN_WRITE(pll, npda, !pll->data->powerup_polarity); pll 218 drivers/clk/st/clkgen-fsyn.c if (pll->lock) pll 219 drivers/clk/st/clkgen-fsyn.c spin_unlock_irqrestore(pll->lock, flags); pll 221 drivers/clk/st/clkgen-fsyn.c if (pll->data->lockstatus_present) pll 222 drivers/clk/st/clkgen-fsyn.c while (!CLKGEN_READ(pll, lock_status)) { pll 233 drivers/clk/st/clkgen-fsyn.c struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw); pll 236 drivers/clk/st/clkgen-fsyn.c if (pll->lock) pll 237 drivers/clk/st/clkgen-fsyn.c spin_lock_irqsave(pll->lock, flags); pll 243 drivers/clk/st/clkgen-fsyn.c CLKGEN_WRITE(pll, npda, pll->data->powerup_polarity); pll 245 drivers/clk/st/clkgen-fsyn.c if (pll->data->reset_present) pll 246 drivers/clk/st/clkgen-fsyn.c CLKGEN_WRITE(pll, nreset, 0); pll 248 drivers/clk/st/clkgen-fsyn.c if (pll->lock) pll 249 drivers/clk/st/clkgen-fsyn.c spin_unlock_irqrestore(pll->lock, flags); pll 254 drivers/clk/st/clkgen-fsyn.c struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw); pll 255 drivers/clk/st/clkgen-fsyn.c u32 npda = CLKGEN_READ(pll, npda); pll 257 drivers/clk/st/clkgen-fsyn.c return pll->data->powerup_polarity ? !npda : !!npda; pll 273 drivers/clk/st/clkgen-fsyn.c struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw); pll 277 drivers/clk/st/clkgen-fsyn.c params.ndiv = CLKGEN_READ(pll, ndiv); pll 282 drivers/clk/st/clkgen-fsyn.c pll->ndiv = params.ndiv; pll 337 drivers/clk/st/clkgen-fsyn.c struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw); pll 359 drivers/clk/st/clkgen-fsyn.c pll->ndiv = params.ndiv; pll 361 drivers/clk/st/clkgen-fsyn.c if (pll->lock) pll 362 drivers/clk/st/clkgen-fsyn.c spin_lock_irqsave(pll->lock, flags); pll 364 drivers/clk/st/clkgen-fsyn.c CLKGEN_WRITE(pll, ndiv, pll->ndiv); pll 366 drivers/clk/st/clkgen-fsyn.c if (pll->lock) pll 367 drivers/clk/st/clkgen-fsyn.c spin_unlock_irqrestore(pll->lock, flags); pll 386 drivers/clk/st/clkgen-fsyn.c struct st_clk_quadfs_pll *pll; pll 396 drivers/clk/st/clkgen-fsyn.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 397 drivers/clk/st/clkgen-fsyn.c if (!pll) pll 406 drivers/clk/st/clkgen-fsyn.c pll->data = quadfs; pll 407 drivers/clk/st/clkgen-fsyn.c pll->regs_base = reg; pll 408 drivers/clk/st/clkgen-fsyn.c pll->lock = lock; pll 409 drivers/clk/st/clkgen-fsyn.c pll->hw.init = &init; pll 411 drivers/clk/st/clkgen-fsyn.c clk = clk_register(NULL, &pll->hw); pll 414 drivers/clk/st/clkgen-fsyn.c kfree(pll); pll 168 drivers/clk/st/clkgen-pll.c struct clkgen_pll *pll = to_clkgen_pll(hw); pll 169 drivers/clk/st/clkgen-pll.c u32 locked = CLKGEN_READ(pll, locked_status); pll 176 drivers/clk/st/clkgen-pll.c struct clkgen_pll *pll = to_clkgen_pll(hw); pll 177 drivers/clk/st/clkgen-pll.c u32 poweroff = CLKGEN_READ(pll, pdn_status); pll 183 drivers/clk/st/clkgen-pll.c struct clkgen_pll *pll = to_clkgen_pll(hw); pll 184 drivers/clk/st/clkgen-pll.c void __iomem *base = pll->regs_base; pll 185 drivers/clk/st/clkgen-pll.c struct clkgen_field *field = &pll->data->locked_status; pll 192 drivers/clk/st/clkgen-pll.c CLKGEN_WRITE(pll, pdn_ctrl, 0); pll 198 drivers/clk/st/clkgen-pll.c if (pll->data->switch2pll_en) pll 199 drivers/clk/st/clkgen-pll.c CLKGEN_WRITE(pll, switch2pll, 0); pll 209 drivers/clk/st/clkgen-pll.c struct clkgen_pll *pll = to_clkgen_pll(hw); pll 213 drivers/clk/st/clkgen-pll.c if (pll->lock) pll 214 drivers/clk/st/clkgen-pll.c spin_lock_irqsave(pll->lock, flags); pll 218 drivers/clk/st/clkgen-pll.c if (pll->lock) pll 219 drivers/clk/st/clkgen-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 226 drivers/clk/st/clkgen-pll.c struct clkgen_pll *pll = to_clkgen_pll(hw); pll 231 drivers/clk/st/clkgen-pll.c if (pll->data->switch2pll_en) pll 232 drivers/clk/st/clkgen-pll.c CLKGEN_WRITE(pll, switch2pll, 1); pll 234 drivers/clk/st/clkgen-pll.c CLKGEN_WRITE(pll, pdn_ctrl, 1); pll 241 drivers/clk/st/clkgen-pll.c struct clkgen_pll *pll = to_clkgen_pll(hw); pll 244 drivers/clk/st/clkgen-pll.c if (pll->lock) pll 245 drivers/clk/st/clkgen-pll.c spin_lock_irqsave(pll->lock, flags); pll 249 drivers/clk/st/clkgen-pll.c if (pll->lock) pll 250 drivers/clk/st/clkgen-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 254 drivers/clk/st/clkgen-pll.c struct stm_pll *pll) pll 287 drivers/clk/st/clkgen-pll.c pll->idf = i; pll 288 drivers/clk/st/clkgen-pll.c pll->ndiv = n; pll 297 drivers/clk/st/clkgen-pll.c for (pll->cp = 6; pll->ndiv > cp_table[pll->cp-6]; (pll->cp)++) pll 303 drivers/clk/st/clkgen-pll.c static int clk_pll3200c32_get_rate(unsigned long input, struct stm_pll *pll, pll 306 drivers/clk/st/clkgen-pll.c if (!pll->idf) pll 307 drivers/clk/st/clkgen-pll.c pll->idf = 1; pll 309 drivers/clk/st/clkgen-pll.c *rate = ((2 * (input / 1000) * pll->ndiv) / pll->idf) * 1000; pll 317 drivers/clk/st/clkgen-pll.c struct clkgen_pll *pll = to_clkgen_pll(hw); pll 324 drivers/clk/st/clkgen-pll.c ndiv = CLKGEN_READ(pll, ndiv); pll 325 drivers/clk/st/clkgen-pll.c idf = CLKGEN_READ(pll, idf); pll 360 drivers/clk/st/clkgen-pll.c struct clkgen_pll *pll = to_clkgen_pll(hw); pll 379 drivers/clk/st/clkgen-pll.c pll->ndiv = params.ndiv; pll 380 drivers/clk/st/clkgen-pll.c pll->idf = params.idf; pll 381 drivers/clk/st/clkgen-pll.c pll->cp = params.cp; pll 385 drivers/clk/st/clkgen-pll.c if (pll->lock) pll 386 drivers/clk/st/clkgen-pll.c spin_lock_irqsave(pll->lock, flags); pll 388 drivers/clk/st/clkgen-pll.c CLKGEN_WRITE(pll, ndiv, pll->ndiv); pll 389 drivers/clk/st/clkgen-pll.c CLKGEN_WRITE(pll, idf, pll->idf); pll 390 drivers/clk/st/clkgen-pll.c CLKGEN_WRITE(pll, cp, pll->cp); pll 392 drivers/clk/st/clkgen-pll.c if (pll->lock) pll 393 drivers/clk/st/clkgen-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 415 drivers/clk/st/clkgen-pll.c struct stm_pll *pll) pll 446 drivers/clk/st/clkgen-pll.c pll->idf = i; pll 447 drivers/clk/st/clkgen-pll.c pll->ndiv = n; pll 459 drivers/clk/st/clkgen-pll.c static int clk_pll4600c28_get_rate(unsigned long input, struct stm_pll *pll, pll 462 drivers/clk/st/clkgen-pll.c if (!pll->idf) pll 463 drivers/clk/st/clkgen-pll.c pll->idf = 1; pll 465 drivers/clk/st/clkgen-pll.c *rate = (input / pll->idf) * 2 * pll->ndiv; pll 473 drivers/clk/st/clkgen-pll.c struct clkgen_pll *pll = to_clkgen_pll(hw); pll 480 drivers/clk/st/clkgen-pll.c params.ndiv = CLKGEN_READ(pll, ndiv); pll 481 drivers/clk/st/clkgen-pll.c params.idf = CLKGEN_READ(pll, idf); pll 514 drivers/clk/st/clkgen-pll.c struct clkgen_pll *pll = to_clkgen_pll(hw); pll 538 drivers/clk/st/clkgen-pll.c pll->ndiv = params.ndiv; pll 539 drivers/clk/st/clkgen-pll.c pll->idf = params.idf; pll 543 drivers/clk/st/clkgen-pll.c if (pll->lock) pll 544 drivers/clk/st/clkgen-pll.c spin_lock_irqsave(pll->lock, flags); pll 546 drivers/clk/st/clkgen-pll.c CLKGEN_WRITE(pll, ndiv, pll->ndiv); pll 547 drivers/clk/st/clkgen-pll.c CLKGEN_WRITE(pll, idf, pll->idf); pll 549 drivers/clk/st/clkgen-pll.c if (pll->lock) pll 550 drivers/clk/st/clkgen-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 587 drivers/clk/st/clkgen-pll.c struct clkgen_pll *pll; pll 591 drivers/clk/st/clkgen-pll.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 592 drivers/clk/st/clkgen-pll.c if (!pll) pll 602 drivers/clk/st/clkgen-pll.c pll->data = pll_data; pll 603 drivers/clk/st/clkgen-pll.c pll->regs_base = reg; pll 604 drivers/clk/st/clkgen-pll.c pll->hw.init = &init; pll 605 drivers/clk/st/clkgen-pll.c pll->lock = lock; pll 607 drivers/clk/st/clkgen-pll.c clk = clk_register(NULL, &pll->hw); pll 609 drivers/clk/st/clkgen-pll.c kfree(pll); pll 44 drivers/clk/st/clkgen.h #define CLKGEN_READ(pll, field) clkgen_read(pll->regs_base, \ pll 45 drivers/clk/st/clkgen.h &pll->data->field) pll 47 drivers/clk/st/clkgen.h #define CLKGEN_WRITE(pll, field, val) clkgen_write(pll->regs_base, \ pll 48 drivers/clk/st/clkgen.h &pll->data->field, val) pll 56 drivers/clk/sunxi-ng/ccu_common.c struct ccu_pll_nb *pll = to_ccu_pll_nb(nb); pll 62 drivers/clk/sunxi-ng/ccu_common.c ccu_gate_helper_disable(pll->common, pll->enable); pll 64 drivers/clk/sunxi-ng/ccu_common.c ret = ccu_gate_helper_enable(pll->common, pll->enable); pll 68 drivers/clk/sunxi-ng/ccu_common.c ccu_helper_wait_for_lock(pll->common, pll->lock); pll 276 drivers/clk/tegra/clk-pll.c static void clk_pll_enable_lock(struct tegra_clk_pll *pll) pll 280 drivers/clk/tegra/clk-pll.c if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) pll 283 drivers/clk/tegra/clk-pll.c if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) pll 286 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); pll 287 drivers/clk/tegra/clk-pll.c val |= BIT(pll->params->lock_enable_bit_idx); pll 288 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); pll 291 drivers/clk/tegra/clk-pll.c static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) pll 297 drivers/clk/tegra/clk-pll.c if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { pll 298 drivers/clk/tegra/clk-pll.c udelay(pll->params->lock_delay); pll 302 drivers/clk/tegra/clk-pll.c lock_addr = pll->clk_base; pll 303 drivers/clk/tegra/clk-pll.c if (pll->params->flags & TEGRA_PLL_LOCK_MISC) pll 304 drivers/clk/tegra/clk-pll.c lock_addr += pll->params->misc_reg; pll 306 drivers/clk/tegra/clk-pll.c lock_addr += pll->params->base_reg; pll 308 drivers/clk/tegra/clk-pll.c lock_mask = pll->params->lock_mask; pll 310 drivers/clk/tegra/clk-pll.c for (i = 0; i < pll->params->lock_delay; i++) { pll 320 drivers/clk/tegra/clk-pll.c clk_hw_get_name(&pll->hw)); pll 325 drivers/clk/tegra/clk-pll.c int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll) pll 327 drivers/clk/tegra/clk-pll.c return clk_pll_wait_for_lock(pll); pll 332 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 335 drivers/clk/tegra/clk-pll.c if (pll->params->flags & TEGRA_PLLM) { pll 336 drivers/clk/tegra/clk-pll.c val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); pll 341 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 348 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 351 drivers/clk/tegra/clk-pll.c if (pll->params->iddq_reg) { pll 352 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->iddq_reg, pll); pll 353 drivers/clk/tegra/clk-pll.c val &= ~BIT(pll->params->iddq_bit_idx); pll 354 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->iddq_reg, pll); pll 358 drivers/clk/tegra/clk-pll.c if (pll->params->reset_reg) { pll 359 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->reset_reg, pll); pll 360 drivers/clk/tegra/clk-pll.c val &= ~BIT(pll->params->reset_bit_idx); pll 361 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->reset_reg, pll); pll 364 drivers/clk/tegra/clk-pll.c clk_pll_enable_lock(pll); pll 366 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 367 drivers/clk/tegra/clk-pll.c if (pll->params->flags & TEGRA_PLL_BYPASS) pll 370 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); pll 372 drivers/clk/tegra/clk-pll.c if (pll->params->flags & TEGRA_PLLM) { pll 373 drivers/clk/tegra/clk-pll.c val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); pll 375 drivers/clk/tegra/clk-pll.c writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); pll 381 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 384 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 385 drivers/clk/tegra/clk-pll.c if (pll->params->flags & TEGRA_PLL_BYPASS) pll 388 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); pll 390 drivers/clk/tegra/clk-pll.c if (pll->params->flags & TEGRA_PLLM) { pll 391 drivers/clk/tegra/clk-pll.c val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); pll 393 drivers/clk/tegra/clk-pll.c writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); pll 396 drivers/clk/tegra/clk-pll.c if (pll->params->reset_reg) { pll 397 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->reset_reg, pll); pll 398 drivers/clk/tegra/clk-pll.c val |= BIT(pll->params->reset_bit_idx); pll 399 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->reset_reg, pll); pll 402 drivers/clk/tegra/clk-pll.c if (pll->params->iddq_reg) { pll 403 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->iddq_reg, pll); pll 404 drivers/clk/tegra/clk-pll.c val |= BIT(pll->params->iddq_bit_idx); pll 405 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->iddq_reg, pll); pll 410 drivers/clk/tegra/clk-pll.c static void pll_clk_start_ss(struct tegra_clk_pll *pll) pll 412 drivers/clk/tegra/clk-pll.c if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) { pll 413 drivers/clk/tegra/clk-pll.c u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); pll 415 drivers/clk/tegra/clk-pll.c val |= pll->params->ssc_ctrl_en_mask; pll 416 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->ssc_ctrl_reg, pll); pll 420 drivers/clk/tegra/clk-pll.c static void pll_clk_stop_ss(struct tegra_clk_pll *pll) pll 422 drivers/clk/tegra/clk-pll.c if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) { pll 423 drivers/clk/tegra/clk-pll.c u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); pll 425 drivers/clk/tegra/clk-pll.c val &= ~pll->params->ssc_ctrl_en_mask; pll 426 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->ssc_ctrl_reg, pll); pll 432 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 439 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 440 drivers/clk/tegra/clk-pll.c spin_lock_irqsave(pll->lock, flags); pll 444 drivers/clk/tegra/clk-pll.c ret = clk_pll_wait_for_lock(pll); pll 446 drivers/clk/tegra/clk-pll.c pll_clk_start_ss(pll); pll 448 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 449 drivers/clk/tegra/clk-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 456 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 459 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 460 drivers/clk/tegra/clk-pll.c spin_lock_irqsave(pll->lock, flags); pll 462 drivers/clk/tegra/clk-pll.c pll_clk_stop_ss(pll); pll 466 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 467 drivers/clk/tegra/clk-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 472 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 473 drivers/clk/tegra/clk-pll.c const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; pll 486 drivers/clk/tegra/clk-pll.c int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div) pll 488 drivers/clk/tegra/clk-pll.c return _p_div_to_hw(&pll->hw, p_div); pll 493 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 494 drivers/clk/tegra/clk-pll.c const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; pll 512 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 516 drivers/clk/tegra/clk-pll.c for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) pll 524 drivers/clk/tegra/clk-pll.c if (pll->params->pdiv_tohw) { pll 546 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 585 drivers/clk/tegra/clk-pll.c if (cfg->m == 0 || cfg->m > divm_max(pll) || pll 586 drivers/clk/tegra/clk-pll.c cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) || pll 587 drivers/clk/tegra/clk-pll.c cfg->output_rate > pll->params->vco_max) { pll 594 drivers/clk/tegra/clk-pll.c if (pll->params->pdiv_tohw) { pll 617 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 621 drivers/clk/tegra/clk-pll.c if (!pll->params->sdm_din_reg) pll 625 drivers/clk/tegra/clk-pll.c val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll)); pll 626 drivers/clk/tegra/clk-pll.c val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll); pll 627 drivers/clk/tegra/clk-pll.c pll_writel_sdm_din(val, pll); pll 630 drivers/clk/tegra/clk-pll.c val = pll_readl_sdm_ctrl(pll); pll 631 drivers/clk/tegra/clk-pll.c enabled = (val & sdm_en_mask(pll)); pll 634 drivers/clk/tegra/clk-pll.c val &= ~pll->params->sdm_ctrl_en_mask; pll 637 drivers/clk/tegra/clk-pll.c val |= pll->params->sdm_ctrl_en_mask; pll 639 drivers/clk/tegra/clk-pll.c pll_writel_sdm_ctrl(val, pll); pll 642 drivers/clk/tegra/clk-pll.c static void _update_pll_mnp(struct tegra_clk_pll *pll, pll 646 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll_params *params = pll->params; pll 650 drivers/clk/tegra/clk-pll.c (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & pll 652 drivers/clk/tegra/clk-pll.c val = pll_override_readl(params->pmc_divp_reg, pll); pll 653 drivers/clk/tegra/clk-pll.c val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); pll 655 drivers/clk/tegra/clk-pll.c pll_override_writel(val, params->pmc_divp_reg, pll); pll 657 drivers/clk/tegra/clk-pll.c val = pll_override_readl(params->pmc_divnm_reg, pll); pll 658 drivers/clk/tegra/clk-pll.c val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) | pll 659 drivers/clk/tegra/clk-pll.c (divn_mask(pll) << div_nmp->override_divn_shift)); pll 662 drivers/clk/tegra/clk-pll.c pll_override_writel(val, params->pmc_divnm_reg, pll); pll 664 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 666 drivers/clk/tegra/clk-pll.c val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) | pll 667 drivers/clk/tegra/clk-pll.c divp_mask_shifted(pll)); pll 669 drivers/clk/tegra/clk-pll.c val |= (cfg->m << divm_shift(pll)) | pll 670 drivers/clk/tegra/clk-pll.c (cfg->n << divn_shift(pll)) | pll 671 drivers/clk/tegra/clk-pll.c (cfg->p << divp_shift(pll)); pll 673 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); pll 675 drivers/clk/tegra/clk-pll.c clk_pll_set_sdm_data(&pll->hw, cfg); pll 679 drivers/clk/tegra/clk-pll.c static void _get_pll_mnp(struct tegra_clk_pll *pll, pll 683 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll_params *params = pll->params; pll 689 drivers/clk/tegra/clk-pll.c (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & pll 691 drivers/clk/tegra/clk-pll.c val = pll_override_readl(params->pmc_divp_reg, pll); pll 692 drivers/clk/tegra/clk-pll.c cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); pll 694 drivers/clk/tegra/clk-pll.c val = pll_override_readl(params->pmc_divnm_reg, pll); pll 695 drivers/clk/tegra/clk-pll.c cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); pll 696 drivers/clk/tegra/clk-pll.c cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); pll 698 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 700 drivers/clk/tegra/clk-pll.c cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); pll 701 drivers/clk/tegra/clk-pll.c cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); pll 702 drivers/clk/tegra/clk-pll.c cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); pll 704 drivers/clk/tegra/clk-pll.c if (pll->params->sdm_din_reg) { pll 705 drivers/clk/tegra/clk-pll.c if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) { pll 706 drivers/clk/tegra/clk-pll.c val = pll_readl_sdm_din(pll); pll 707 drivers/clk/tegra/clk-pll.c val &= sdm_din_mask(pll); pll 714 drivers/clk/tegra/clk-pll.c static void _update_pll_cpcon(struct tegra_clk_pll *pll, pll 720 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); pll 725 drivers/clk/tegra/clk-pll.c if (pll->params->flags & TEGRA_PLL_SET_LFCON) { pll 729 drivers/clk/tegra/clk-pll.c } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) { pll 731 drivers/clk/tegra/clk-pll.c if (rate >= (pll->params->vco_max >> 1)) pll 735 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); pll 741 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 747 drivers/clk/tegra/clk-pll.c _get_pll_mnp(pll, &old_cfg); pll 749 drivers/clk/tegra/clk-pll.c if (state && pll->params->defaults_set && pll->params->dyn_ramp && pll 751 drivers/clk/tegra/clk-pll.c ret = pll->params->dyn_ramp(pll, cfg); pll 757 drivers/clk/tegra/clk-pll.c pll_clk_stop_ss(pll); pll 761 drivers/clk/tegra/clk-pll.c if (!pll->params->defaults_set && pll->params->set_defaults) pll 762 drivers/clk/tegra/clk-pll.c pll->params->set_defaults(pll); pll 764 drivers/clk/tegra/clk-pll.c _update_pll_mnp(pll, cfg); pll 766 drivers/clk/tegra/clk-pll.c if (pll->params->flags & TEGRA_PLL_HAS_CPCON) pll 767 drivers/clk/tegra/clk-pll.c _update_pll_cpcon(pll, cfg, rate); pll 771 drivers/clk/tegra/clk-pll.c ret = clk_pll_wait_for_lock(pll); pll 772 drivers/clk/tegra/clk-pll.c pll_clk_start_ss(pll); pll 781 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 786 drivers/clk/tegra/clk-pll.c if (pll->params->flags & TEGRA_PLL_FIXED) { pll 787 drivers/clk/tegra/clk-pll.c if (rate != pll->params->fixed_rate) { pll 790 drivers/clk/tegra/clk-pll.c pll->params->fixed_rate, rate); pll 797 drivers/clk/tegra/clk-pll.c pll->params->calc_rate(hw, &cfg, rate, parent_rate)) { pll 803 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 804 drivers/clk/tegra/clk-pll.c spin_lock_irqsave(pll->lock, flags); pll 806 drivers/clk/tegra/clk-pll.c _get_pll_mnp(pll, &old_cfg); pll 807 drivers/clk/tegra/clk-pll.c if (pll->params->flags & TEGRA_PLL_VCO_OUT) pll 814 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 815 drivers/clk/tegra/clk-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 823 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 826 drivers/clk/tegra/clk-pll.c if (pll->params->flags & TEGRA_PLL_FIXED) { pll 828 drivers/clk/tegra/clk-pll.c if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) pll 830 drivers/clk/tegra/clk-pll.c return pll->params->fixed_rate; pll 834 drivers/clk/tegra/clk-pll.c pll->params->calc_rate(hw, &cfg, rate, *prate)) pll 843 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 849 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 851 drivers/clk/tegra/clk-pll.c if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) pll 854 drivers/clk/tegra/clk-pll.c if ((pll->params->flags & TEGRA_PLL_FIXED) && pll 855 drivers/clk/tegra/clk-pll.c !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && pll 858 drivers/clk/tegra/clk-pll.c if (_get_table_rate(hw, &sel, pll->params->fixed_rate, pll 864 drivers/clk/tegra/clk-pll.c return pll->params->fixed_rate; pll 867 drivers/clk/tegra/clk-pll.c _get_pll_mnp(pll, &cfg); pll 869 drivers/clk/tegra/clk-pll.c if (pll->params->flags & TEGRA_PLL_VCO_OUT) { pll 880 drivers/clk/tegra/clk-pll.c if (pll->params->set_gain) pll 881 drivers/clk/tegra/clk-pll.c pll->params->set_gain(&cfg); pll 891 drivers/clk/tegra/clk-pll.c static int clk_plle_training(struct tegra_clk_pll *pll) pll 896 drivers/clk/tegra/clk-pll.c if (!pll->pmc) pll 903 drivers/clk/tegra/clk-pll.c val = readl(pll->pmc + PMC_SATA_PWRGT); pll 905 drivers/clk/tegra/clk-pll.c writel(val, pll->pmc + PMC_SATA_PWRGT); pll 907 drivers/clk/tegra/clk-pll.c val = readl(pll->pmc + PMC_SATA_PWRGT); pll 909 drivers/clk/tegra/clk-pll.c writel(val, pll->pmc + PMC_SATA_PWRGT); pll 911 drivers/clk/tegra/clk-pll.c val = readl(pll->pmc + PMC_SATA_PWRGT); pll 913 drivers/clk/tegra/clk-pll.c writel(val, pll->pmc + PMC_SATA_PWRGT); pll 915 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); pll 919 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); pll 934 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 945 drivers/clk/tegra/clk-pll.c if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) pll 950 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); pll 952 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); pll 954 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); pll 956 drivers/clk/tegra/clk-pll.c err = clk_plle_training(pll); pll 961 drivers/clk/tegra/clk-pll.c if (pll->params->flags & TEGRA_PLLE_CONFIGURE) { pll 963 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 964 drivers/clk/tegra/clk-pll.c val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | pll 965 drivers/clk/tegra/clk-pll.c divm_mask_shifted(pll)); pll 967 drivers/clk/tegra/clk-pll.c val |= sel.m << divm_shift(pll); pll 968 drivers/clk/tegra/clk-pll.c val |= sel.n << divn_shift(pll); pll 969 drivers/clk/tegra/clk-pll.c val |= sel.p << divp_shift(pll); pll 971 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); pll 974 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); pll 977 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); pll 979 drivers/clk/tegra/clk-pll.c val = readl(pll->clk_base + PLLE_SS_CTRL); pll 982 drivers/clk/tegra/clk-pll.c writel(val, pll->clk_base + PLLE_SS_CTRL); pll 984 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 986 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); pll 988 drivers/clk/tegra/clk-pll.c clk_pll_wait_for_lock(pll); pll 996 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 997 drivers/clk/tegra/clk-pll.c u32 val = pll_readl_base(pll); pll 1001 drivers/clk/tegra/clk-pll.c divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); pll 1002 drivers/clk/tegra/clk-pll.c divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); pll 1003 drivers/clk/tegra/clk-pll.c divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); pll 1073 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 1089 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 1090 drivers/clk/tegra/clk-pll.c spin_lock_irqsave(pll->lock, flags); pll 1094 drivers/clk/tegra/clk-pll.c ret = clk_pll_wait_for_lock(pll); pll 1112 drivers/clk/tegra/clk-pll.c value = pll_readl_base(pll); pll 1114 drivers/clk/tegra/clk-pll.c pll_writel_base(value, pll); pll 1116 drivers/clk/tegra/clk-pll.c value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); pll 1126 drivers/clk/tegra/clk-pll.c writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); pll 1128 drivers/clk/tegra/clk-pll.c value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); pll 1138 drivers/clk/tegra/clk-pll.c writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); pll 1141 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 1142 drivers/clk/tegra/clk-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 1178 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 1185 drivers/clk/tegra/clk-pll.c p = DIV_ROUND_UP(pll->params->vco_min, rate); pll 1186 drivers/clk/tegra/clk-pll.c cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); pll 1197 drivers/clk/tegra/clk-pll.c if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) pll 1210 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 1212 drivers/clk/tegra/clk-pll.c return (u16)_pll_fixed_mdiv(pll->params, input_rate); pll 1261 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 1268 drivers/clk/tegra/clk-pll.c if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) { pll 1275 drivers/clk/tegra/clk-pll.c if (cfg->p > pll->params->max_p) pll 1285 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 1294 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 1295 drivers/clk/tegra/clk-pll.c spin_lock_irqsave(pll->lock, flags); pll 1297 drivers/clk/tegra/clk-pll.c _get_pll_mnp(pll, &old_cfg); pll 1298 drivers/clk/tegra/clk-pll.c if (pll->params->flags & TEGRA_PLL_VCO_OUT) pll 1304 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 1305 drivers/clk/tegra/clk-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 1313 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 1326 drivers/clk/tegra/clk-pll.c if (pll->params->set_gain) pll 1327 drivers/clk/tegra/clk-pll.c pll->params->set_gain(&cfg); pll 1335 drivers/clk/tegra/clk-pll.c static void _pllcx_strobe(struct tegra_clk_pll *pll) pll 1339 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); pll 1341 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); pll 1345 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); pll 1350 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 1358 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 1359 drivers/clk/tegra/clk-pll.c spin_lock_irqsave(pll->lock, flags); pll 1364 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); pll 1366 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); pll 1369 drivers/clk/tegra/clk-pll.c _pllcx_strobe(pll); pll 1371 drivers/clk/tegra/clk-pll.c ret = clk_pll_wait_for_lock(pll); pll 1373 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 1374 drivers/clk/tegra/clk-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 1381 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 1386 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); pll 1388 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); pll 1394 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 1397 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 1398 drivers/clk/tegra/clk-pll.c spin_lock_irqsave(pll->lock, flags); pll 1402 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 1403 drivers/clk/tegra/clk-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 1406 drivers/clk/tegra/clk-pll.c static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll, pll 1431 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); pll 1435 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); pll 1444 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 1448 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 1449 drivers/clk/tegra/clk-pll.c spin_lock_irqsave(pll->lock, flags); pll 1455 drivers/clk/tegra/clk-pll.c _get_pll_mnp(pll, &old_cfg); pll 1469 drivers/clk/tegra/clk-pll.c ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); pll 1473 drivers/clk/tegra/clk-pll.c _update_pll_mnp(pll, &cfg); pll 1479 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 1480 drivers/clk/tegra/clk-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 1485 drivers/clk/tegra/clk-pll.c static long _pllre_calc_rate(struct tegra_clk_pll *pll, pll 1492 drivers/clk/tegra/clk-pll.c m = _pll_fixed_mdiv(pll->params, parent_rate); pll 1510 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 1514 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 1515 drivers/clk/tegra/clk-pll.c spin_lock_irqsave(pll->lock, flags); pll 1517 drivers/clk/tegra/clk-pll.c _pllre_calc_rate(pll, &cfg, rate, parent_rate); pll 1518 drivers/clk/tegra/clk-pll.c _get_pll_mnp(pll, &old_cfg); pll 1526 drivers/clk/tegra/clk-pll.c _update_pll_mnp(pll, &cfg); pll 1530 drivers/clk/tegra/clk-pll.c ret = clk_pll_wait_for_lock(pll); pll 1534 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 1535 drivers/clk/tegra/clk-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 1544 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 1547 drivers/clk/tegra/clk-pll.c _get_pll_mnp(pll, &cfg); pll 1558 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 1560 drivers/clk/tegra/clk-pll.c return _pllre_calc_rate(pll, NULL, rate, *prate); pll 1565 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 1577 drivers/clk/tegra/clk-pll.c if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) pll 1580 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 1581 drivers/clk/tegra/clk-pll.c spin_lock_irqsave(pll->lock, flags); pll 1583 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 1585 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); pll 1587 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->aux_reg, pll); pll 1590 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->aux_reg, pll); pll 1593 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); pll 1599 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); pll 1602 drivers/clk/tegra/clk-pll.c val = pll_readl(PLLE_SS_CTRL, pll); pll 1604 drivers/clk/tegra/clk-pll.c pll_writel(val, PLLE_SS_CTRL, pll); pll 1606 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 1607 drivers/clk/tegra/clk-pll.c val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | pll 1608 drivers/clk/tegra/clk-pll.c divm_mask_shifted(pll)); pll 1610 drivers/clk/tegra/clk-pll.c val |= sel.m << divm_shift(pll); pll 1611 drivers/clk/tegra/clk-pll.c val |= sel.n << divn_shift(pll); pll 1613 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); pll 1617 drivers/clk/tegra/clk-pll.c ret = clk_pll_wait_for_lock(pll); pll 1622 drivers/clk/tegra/clk-pll.c val = pll_readl(PLLE_SS_CTRL, pll); pll 1626 drivers/clk/tegra/clk-pll.c pll_writel(val, PLLE_SS_CTRL, pll); pll 1628 drivers/clk/tegra/clk-pll.c pll_writel(val, PLLE_SS_CTRL, pll); pll 1631 drivers/clk/tegra/clk-pll.c pll_writel(val, PLLE_SS_CTRL, pll); pll 1635 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); pll 1637 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); pll 1639 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->aux_reg, pll); pll 1642 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->aux_reg, pll); pll 1645 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->aux_reg, pll); pll 1647 drivers/clk/tegra/clk-pll.c val = pll_readl(XUSBIO_PLL_CFG0, pll); pll 1652 drivers/clk/tegra/clk-pll.c pll_writel(val, XUSBIO_PLL_CFG0, pll); pll 1655 drivers/clk/tegra/clk-pll.c pll_writel(val, XUSBIO_PLL_CFG0, pll); pll 1658 drivers/clk/tegra/clk-pll.c val = pll_readl(SATA_PLL_CFG0, pll); pll 1662 drivers/clk/tegra/clk-pll.c pll_writel(val, SATA_PLL_CFG0, pll); pll 1666 drivers/clk/tegra/clk-pll.c val = pll_readl(SATA_PLL_CFG0, pll); pll 1668 drivers/clk/tegra/clk-pll.c pll_writel(val, SATA_PLL_CFG0, pll); pll 1671 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 1672 drivers/clk/tegra/clk-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 1679 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 1683 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 1684 drivers/clk/tegra/clk-pll.c spin_lock_irqsave(pll->lock, flags); pll 1688 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); pll 1690 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); pll 1693 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 1694 drivers/clk/tegra/clk-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 1699 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 1717 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 1718 drivers/clk/tegra/clk-pll.c spin_lock_irqsave(pll->lock, flags); pll 1722 drivers/clk/tegra/clk-pll.c ret = clk_pll_wait_for_lock(pll); pll 1740 drivers/clk/tegra/clk-pll.c value = pll_readl_base(pll); pll 1742 drivers/clk/tegra/clk-pll.c pll_writel_base(value, pll); pll 1744 drivers/clk/tegra/clk-pll.c value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); pll 1754 drivers/clk/tegra/clk-pll.c writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); pll 1756 drivers/clk/tegra/clk-pll.c value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); pll 1767 drivers/clk/tegra/clk-pll.c writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); pll 1770 drivers/clk/tegra/clk-pll.c value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); pll 1774 drivers/clk/tegra/clk-pll.c writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); pll 1776 drivers/clk/tegra/clk-pll.c value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); pll 1779 drivers/clk/tegra/clk-pll.c writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); pll 1787 drivers/clk/tegra/clk-pll.c value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); pll 1790 drivers/clk/tegra/clk-pll.c writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); pll 1795 drivers/clk/tegra/clk-pll.c value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); pll 1797 drivers/clk/tegra/clk-pll.c writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); pll 1800 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 1801 drivers/clk/tegra/clk-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 1811 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll; pll 1813 drivers/clk/tegra/clk-pll.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 1814 drivers/clk/tegra/clk-pll.c if (!pll) pll 1817 drivers/clk/tegra/clk-pll.c pll->clk_base = clk_base; pll 1818 drivers/clk/tegra/clk-pll.c pll->pmc = pmc; pll 1820 drivers/clk/tegra/clk-pll.c pll->params = pll_params; pll 1821 drivers/clk/tegra/clk-pll.c pll->lock = lock; pll 1826 drivers/clk/tegra/clk-pll.c return pll; pll 1829 drivers/clk/tegra/clk-pll.c static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, pll 1842 drivers/clk/tegra/clk-pll.c if (!pll->params->calc_rate) { pll 1843 drivers/clk/tegra/clk-pll.c if (pll->params->flags & TEGRA_PLLM) pll 1844 drivers/clk/tegra/clk-pll.c pll->params->calc_rate = _calc_dynamic_ramp_rate; pll 1846 drivers/clk/tegra/clk-pll.c pll->params->calc_rate = _calc_rate; pll 1849 drivers/clk/tegra/clk-pll.c if (pll->params->set_defaults) pll 1850 drivers/clk/tegra/clk-pll.c pll->params->set_defaults(pll); pll 1853 drivers/clk/tegra/clk-pll.c pll->hw.init = &init; pll 1855 drivers/clk/tegra/clk-pll.c return clk_register(NULL, &pll->hw); pll 1863 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll; pll 1868 drivers/clk/tegra/clk-pll.c pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); pll 1869 drivers/clk/tegra/clk-pll.c if (IS_ERR(pll)) pll 1870 drivers/clk/tegra/clk-pll.c return ERR_CAST(pll); pll 1872 drivers/clk/tegra/clk-pll.c clk = _tegra_clk_register_pll(pll, name, parent_name, flags, pll 1875 drivers/clk/tegra/clk-pll.c kfree(pll); pll 1894 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll; pll 1902 drivers/clk/tegra/clk-pll.c pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); pll 1903 drivers/clk/tegra/clk-pll.c if (IS_ERR(pll)) pll 1904 drivers/clk/tegra/clk-pll.c return ERR_CAST(pll); pll 1906 drivers/clk/tegra/clk-pll.c clk = _tegra_clk_register_pll(pll, name, parent_name, flags, pll 1909 drivers/clk/tegra/clk-pll.c kfree(pll); pll 1918 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll; pll 1923 drivers/clk/tegra/clk-pll.c pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); pll 1924 drivers/clk/tegra/clk-pll.c if (IS_ERR(pll)) pll 1925 drivers/clk/tegra/clk-pll.c return ERR_CAST(pll); pll 1927 drivers/clk/tegra/clk-pll.c clk = _tegra_clk_register_pll(pll, name, parent_name, flags, pll 1930 drivers/clk/tegra/clk-pll.c kfree(pll); pll 1986 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll; pll 2032 drivers/clk/tegra/clk-pll.c pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); pll 2033 drivers/clk/tegra/clk-pll.c if (IS_ERR(pll)) pll 2034 drivers/clk/tegra/clk-pll.c return ERR_CAST(pll); pll 2036 drivers/clk/tegra/clk-pll.c clk = _tegra_clk_register_pll(pll, name, parent_name, flags, pll 2039 drivers/clk/tegra/clk-pll.c kfree(pll); pll 2051 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll; pll 2060 drivers/clk/tegra/clk-pll.c pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); pll 2061 drivers/clk/tegra/clk-pll.c if (IS_ERR(pll)) pll 2062 drivers/clk/tegra/clk-pll.c return ERR_CAST(pll); pll 2066 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 2074 drivers/clk/tegra/clk-pll.c val = m << divm_shift(pll); pll 2075 drivers/clk/tegra/clk-pll.c val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); pll 2076 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); pll 2081 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); pll 2083 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); pll 2085 drivers/clk/tegra/clk-pll.c clk = _tegra_clk_register_pll(pll, name, parent_name, flags, pll 2088 drivers/clk/tegra/clk-pll.c kfree(pll); pll 2099 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll; pll 2123 drivers/clk/tegra/clk-pll.c pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); pll 2124 drivers/clk/tegra/clk-pll.c if (IS_ERR(pll)) pll 2125 drivers/clk/tegra/clk-pll.c return ERR_CAST(pll); pll 2127 drivers/clk/tegra/clk-pll.c clk = _tegra_clk_register_pll(pll, name, parent_name, flags, pll 2130 drivers/clk/tegra/clk-pll.c kfree(pll); pll 2143 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll; pll 2162 drivers/clk/tegra/clk-pll.c pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); pll 2163 drivers/clk/tegra/clk-pll.c if (IS_ERR(pll)) pll 2164 drivers/clk/tegra/clk-pll.c return ERR_CAST(pll); pll 2191 drivers/clk/tegra/clk-pll.c pll_writel_base(0, pll); pll 2192 drivers/clk/tegra/clk-pll.c _update_pll_mnp(pll, &cfg); pll 2194 drivers/clk/tegra/clk-pll.c pll_writel_misc(PLLCX_MISC_DEFAULT, pll); pll 2195 drivers/clk/tegra/clk-pll.c pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); pll 2196 drivers/clk/tegra/clk-pll.c pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); pll 2197 drivers/clk/tegra/clk-pll.c pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); pll 2199 drivers/clk/tegra/clk-pll.c _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); pll 2201 drivers/clk/tegra/clk-pll.c clk = _tegra_clk_register_pll(pll, name, parent_name, flags, pll 2204 drivers/clk/tegra/clk-pll.c kfree(pll); pll 2215 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll; pll 2219 drivers/clk/tegra/clk-pll.c pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); pll 2220 drivers/clk/tegra/clk-pll.c if (IS_ERR(pll)) pll 2221 drivers/clk/tegra/clk-pll.c return ERR_CAST(pll); pll 2225 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 2226 drivers/clk/tegra/clk-pll.c val_aux = pll_readl(pll_params->aux_reg, pll); pll 2236 drivers/clk/tegra/clk-pll.c pll_writel(val_aux, pll_params->aux_reg, pll); pll 2239 drivers/clk/tegra/clk-pll.c clk = _tegra_clk_register_pll(pll, name, parent_name, flags, pll 2242 drivers/clk/tegra/clk-pll.c kfree(pll); pll 2253 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll; pll 2258 drivers/clk/tegra/clk-pll.c pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); pll 2259 drivers/clk/tegra/clk-pll.c if (IS_ERR(pll)) pll 2260 drivers/clk/tegra/clk-pll.c return ERR_CAST(pll); pll 2262 drivers/clk/tegra/clk-pll.c clk = _tegra_clk_register_pll(pll, name, parent_name, flags, pll 2265 drivers/clk/tegra/clk-pll.c kfree(pll); pll 2286 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll; pll 2303 drivers/clk/tegra/clk-pll.c pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); pll 2304 drivers/clk/tegra/clk-pll.c if (IS_ERR(pll)) pll 2305 drivers/clk/tegra/clk-pll.c return ERR_CAST(pll); pll 2307 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 2309 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); pll 2323 drivers/clk/tegra/clk-pll.c kfree(pll); pll 2329 drivers/clk/tegra/clk-pll.c _update_pll_mnp(pll, &cfg); pll 2331 drivers/clk/tegra/clk-pll.c pll_writel_misc(PLLSS_MISC_DEFAULT, pll); pll 2332 drivers/clk/tegra/clk-pll.c pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); pll 2333 drivers/clk/tegra/clk-pll.c pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); pll 2334 drivers/clk/tegra/clk-pll.c pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); pll 2336 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 2341 drivers/clk/tegra/clk-pll.c kfree(pll); pll 2350 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); pll 2352 drivers/clk/tegra/clk-pll.c clk = _tegra_clk_register_pll(pll, name, parent_name, flags, pll 2356 drivers/clk/tegra/clk-pll.c kfree(pll); pll 2369 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll; pll 2378 drivers/clk/tegra/clk-pll.c pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); pll 2379 drivers/clk/tegra/clk-pll.c if (IS_ERR(pll)) pll 2380 drivers/clk/tegra/clk-pll.c return ERR_CAST(pll); pll 2382 drivers/clk/tegra/clk-pll.c clk = _tegra_clk_register_pll(pll, name, parent_name, flags, pll 2385 drivers/clk/tegra/clk-pll.c kfree(pll); pll 2392 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 2395 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 2402 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 2414 drivers/clk/tegra/clk-pll.c if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) pll 2417 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 2418 drivers/clk/tegra/clk-pll.c spin_lock_irqsave(pll->lock, flags); pll 2420 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->aux_reg, pll); pll 2424 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 2426 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); pll 2428 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); pll 2434 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); pll 2437 drivers/clk/tegra/clk-pll.c val = pll_readl(PLLE_SS_CTRL, pll); pll 2439 drivers/clk/tegra/clk-pll.c pll_writel(val, PLLE_SS_CTRL, pll); pll 2441 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 2442 drivers/clk/tegra/clk-pll.c val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | pll 2443 drivers/clk/tegra/clk-pll.c divm_mask_shifted(pll)); pll 2445 drivers/clk/tegra/clk-pll.c val |= sel.m << divm_shift(pll); pll 2446 drivers/clk/tegra/clk-pll.c val |= sel.n << divn_shift(pll); pll 2448 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); pll 2451 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 2453 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); pll 2455 drivers/clk/tegra/clk-pll.c ret = clk_pll_wait_for_lock(pll); pll 2460 drivers/clk/tegra/clk-pll.c val = pll_readl(PLLE_SS_CTRL, pll); pll 2464 drivers/clk/tegra/clk-pll.c pll_writel(val, PLLE_SS_CTRL, pll); pll 2466 drivers/clk/tegra/clk-pll.c pll_writel(val, PLLE_SS_CTRL, pll); pll 2469 drivers/clk/tegra/clk-pll.c pll_writel(val, PLLE_SS_CTRL, pll); pll 2472 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); pll 2474 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); pll 2476 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->aux_reg, pll); pll 2479 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->aux_reg, pll); pll 2482 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->aux_reg, pll); pll 2485 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 2486 drivers/clk/tegra/clk-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 2493 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 2497 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 2498 drivers/clk/tegra/clk-pll.c spin_lock_irqsave(pll->lock, flags); pll 2501 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->aux_reg, pll); pll 2505 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 2507 drivers/clk/tegra/clk-pll.c pll_writel_base(val, pll); pll 2509 drivers/clk/tegra/clk-pll.c val = pll_readl(pll->params->aux_reg, pll); pll 2511 drivers/clk/tegra/clk-pll.c pll_writel(val, pll->params->aux_reg, pll); pll 2513 drivers/clk/tegra/clk-pll.c val = pll_readl_misc(pll); pll 2515 drivers/clk/tegra/clk-pll.c pll_writel_misc(val, pll); pll 2519 drivers/clk/tegra/clk-pll.c if (pll->lock) pll 2520 drivers/clk/tegra/clk-pll.c spin_unlock_irqrestore(pll->lock, flags); pll 2536 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll; pll 2540 drivers/clk/tegra/clk-pll.c pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); pll 2541 drivers/clk/tegra/clk-pll.c if (IS_ERR(pll)) pll 2542 drivers/clk/tegra/clk-pll.c return ERR_CAST(pll); pll 2546 drivers/clk/tegra/clk-pll.c val = pll_readl_base(pll); pll 2547 drivers/clk/tegra/clk-pll.c val_aux = pll_readl(pll_params->aux_reg, pll); pll 2557 drivers/clk/tegra/clk-pll.c pll_writel(val_aux, pll_params->aux_reg, pll); pll 2560 drivers/clk/tegra/clk-pll.c clk = _tegra_clk_register_pll(pll, name, parent_name, flags, pll 2563 drivers/clk/tegra/clk-pll.c kfree(pll); pll 2576 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll; pll 2598 drivers/clk/tegra/clk-pll.c pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); pll 2599 drivers/clk/tegra/clk-pll.c if (IS_ERR(pll)) pll 2600 drivers/clk/tegra/clk-pll.c return ERR_CAST(pll); pll 2602 drivers/clk/tegra/clk-pll.c clk = _tegra_clk_register_pll(pll, name, parent_name, flags, pll 2605 drivers/clk/tegra/clk-pll.c kfree(pll); pll 2616 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll; pll 2646 drivers/clk/tegra/clk-pll.c pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); pll 2647 drivers/clk/tegra/clk-pll.c if (IS_ERR(pll)) pll 2648 drivers/clk/tegra/clk-pll.c return ERR_CAST(pll); pll 2650 drivers/clk/tegra/clk-pll.c clk = _tegra_clk_register_pll(pll, name, parent_name, flags, pll 2654 drivers/clk/tegra/clk-pll.c kfree(pll); pll 2665 drivers/clk/tegra/clk-pll.c struct tegra_clk_pll *pll; pll 2689 drivers/clk/tegra/clk-pll.c pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); pll 2690 drivers/clk/tegra/clk-pll.c if (IS_ERR(pll)) pll 2691 drivers/clk/tegra/clk-pll.c return ERR_CAST(pll); pll 2693 drivers/clk/tegra/clk-pll.c clk = _tegra_clk_register_pll(pll, name, parent_name, flags, pll 2696 drivers/clk/tegra/clk-pll.c kfree(pll); pll 1066 drivers/clk/tegra/clk-tegra210.c static void pllx_check_defaults(struct tegra_clk_pll *pll) pll 1072 drivers/clk/tegra/clk-tegra210.c _pll_misc_chk_default(clk_base, pll->params, 0, default_val, pll 1076 drivers/clk/tegra/clk-tegra210.c _pll_misc_chk_default(clk_base, pll->params, 1, default_val, pll 1081 drivers/clk/tegra/clk-tegra210.c _pll_misc_chk_default(clk_base, pll->params, 2, pll 1085 drivers/clk/tegra/clk-tegra210.c _pll_misc_chk_default(clk_base, pll->params, 3, default_val, pll 1089 drivers/clk/tegra/clk-tegra210.c _pll_misc_chk_default(clk_base, pll->params, 4, default_val, pll 1093 drivers/clk/tegra/clk-tegra210.c _pll_misc_chk_default(clk_base, pll->params, 5, default_val, pll 1199 drivers/clk/tegra/clk-tegra210.c static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled) pll 1208 drivers/clk/tegra/clk-tegra210.c _pll_misc_chk_default(clk_base, pll->params, 0, val, pll 1214 drivers/clk/tegra/clk-tegra210.c _pll_misc_chk_default(clk_base, pll->params, 1, val, pll 1336 drivers/clk/tegra/clk-tegra210.c static int tegra210_wait_for_mask(struct tegra_clk_pll *pll, pll 1342 drivers/clk/tegra/clk-tegra210.c for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) { pll 1405 drivers/clk/tegra/clk-tegra210.c struct tegra_clk_pll *pll = to_clk_pll(hw); pll 1406 drivers/clk/tegra/clk-tegra210.c struct tegra_clk_pll_params *params = pll->params; pll 1428 drivers/clk/tegra/clk-tegra210.c cfg->p = tegra_pll_p_div_to_hw(pll, cfg->p); pll 283 drivers/clk/tegra/clk.h void (*set_defaults)(struct tegra_clk_pll *pll); pll 284 drivers/clk/tegra/clk.h int (*dyn_ramp)(struct tegra_clk_pll *pll, pll 827 drivers/clk/tegra/clk.h int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll); pll 829 drivers/clk/tegra/clk.h int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div); pll 188 drivers/clk/zynq/pll.c struct zynq_pll *pll; pll 201 drivers/clk/zynq/pll.c pll = kmalloc(sizeof(*pll), GFP_KERNEL); pll 202 drivers/clk/zynq/pll.c if (!pll) pll 206 drivers/clk/zynq/pll.c pll->hw.init = &initd; pll 207 drivers/clk/zynq/pll.c pll->pll_ctrl = pll_ctrl; pll 208 drivers/clk/zynq/pll.c pll->pll_status = pll_status; pll 209 drivers/clk/zynq/pll.c pll->lockbit = lock_index; pll 210 drivers/clk/zynq/pll.c pll->lock = lock; pll 212 drivers/clk/zynq/pll.c spin_lock_irqsave(pll->lock, flags); pll 214 drivers/clk/zynq/pll.c reg = readl(pll->pll_ctrl); pll 216 drivers/clk/zynq/pll.c writel(reg, pll->pll_ctrl); pll 218 drivers/clk/zynq/pll.c spin_unlock_irqrestore(pll->lock, flags); pll 220 drivers/clk/zynq/pll.c clk = clk_register(NULL, &pll->hw); pll 227 drivers/clk/zynq/pll.c kfree(pll); pll 305 drivers/clk/zynqmp/pll.c struct zynqmp_pll *pll; pll 316 drivers/clk/zynqmp/pll.c pll = kzalloc(sizeof(*pll), GFP_KERNEL); pll 317 drivers/clk/zynqmp/pll.c if (!pll) pll 320 drivers/clk/zynqmp/pll.c pll->hw.init = &init; pll 321 drivers/clk/zynqmp/pll.c pll->clk_id = clk_id; pll 323 drivers/clk/zynqmp/pll.c hw = &pll->hw; pll 326 drivers/clk/zynqmp/pll.c kfree(pll); pll 67 drivers/cpufreq/cpufreq-nforce2.c static int nforce2_calc_fsb(int pll) pll 71 drivers/cpufreq/cpufreq-nforce2.c mul = (pll >> 8) & 0xff; pll 72 drivers/cpufreq/cpufreq-nforce2.c div = pll & 0xff; pll 116 drivers/cpufreq/cpufreq-nforce2.c static void nforce2_write_pll(int pll) pll 125 drivers/cpufreq/cpufreq-nforce2.c pci_write_config_dword(nforce2_dev, NFORCE2_PLLREG, pll); pll 172 drivers/cpufreq/cpufreq-nforce2.c int pll = 0; pll 188 drivers/cpufreq/cpufreq-nforce2.c pll = nforce2_calc_pll(tfsb); pll 190 drivers/cpufreq/cpufreq-nforce2.c if (pll < 0) pll 193 drivers/cpufreq/cpufreq-nforce2.c nforce2_write_pll(pll); pll 212 drivers/cpufreq/cpufreq-nforce2.c pll = nforce2_calc_pll(tfsb); pll 213 drivers/cpufreq/cpufreq-nforce2.c if (pll == -1) pll 216 drivers/cpufreq/cpufreq-nforce2.c nforce2_write_pll(pll); pll 46 drivers/cpufreq/pmac32-cpufreq.c extern void low_choose_750fx_pll(int pll); pll 71 drivers/cpufreq/s3c24xx-cpufreq.c cfg->pll.driver_data = __raw_readl(S3C2410_MPLLCON); pll 72 drivers/cpufreq/s3c24xx-cpufreq.c cfg->pll.frequency = fclk; pll 82 drivers/cpufreq/s3c24xx-cpufreq.c unsigned long pll = cfg->pll.frequency; pll 84 drivers/cpufreq/s3c24xx-cpufreq.c cfg->freq.fclk = pll; pll 85 drivers/cpufreq/s3c24xx-cpufreq.c cfg->freq.hclk = pll / cfg->divs.h_divisor; pll 86 drivers/cpufreq/s3c24xx-cpufreq.c cfg->freq.pclk = pll / cfg->divs.p_divisor; pll 104 drivers/cpufreq/s3c24xx-cpufreq.c pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk, pll 154 drivers/cpufreq/s3c24xx-cpufreq.c struct cpufreq_frequency_table *pll) pll 166 drivers/cpufreq/s3c24xx-cpufreq.c cpu_new.pll = pll ? *pll : cpu_cur.pll; pll 168 drivers/cpufreq/s3c24xx-cpufreq.c if (pll) pll 174 drivers/cpufreq/s3c24xx-cpufreq.c cpu_new.freq.fclk = cpu_new.pll.frequency; pll 208 drivers/cpufreq/s3c24xx-cpufreq.c s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency); pll 278 drivers/cpufreq/s3c24xx-cpufreq.c struct cpufreq_frequency_table *pll; pll 308 drivers/cpufreq/s3c24xx-cpufreq.c pll = NULL; pll 326 drivers/cpufreq/s3c24xx-cpufreq.c pll = pll_reg + index; pll 329 drivers/cpufreq/s3c24xx-cpufreq.c __func__, target_freq, pll->frequency); pll 331 drivers/cpufreq/s3c24xx-cpufreq.c target_freq = pll->frequency; pll 334 drivers/cpufreq/s3c24xx-cpufreq.c return s3c_cpufreq_settarget(policy, target_freq, pll); pll 114 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c void amdgpu_pll_compute(struct amdgpu_pll *pll, pll 122 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ? pll 132 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c fb_div_min = pll->min_feedback_div; pll 133 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c fb_div_max = pll->max_feedback_div; pll 135 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { pll 141 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c if (pll->flags & AMDGPU_PLL_USE_REF_DIV) pll 142 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c ref_div_min = pll->reference_div; pll 144 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c ref_div_min = pll->min_ref_div; pll 146 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && pll 147 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c pll->flags & AMDGPU_PLL_USE_REF_DIV) pll 148 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c ref_div_max = pll->reference_div; pll 150 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c ref_div_max = pll->max_ref_div; pll 153 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c if (pll->flags & AMDGPU_PLL_USE_POST_DIV) { pll 154 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c post_div_min = pll->post_div; pll 155 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c post_div_max = pll->post_div; pll 159 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c if (pll->flags & AMDGPU_PLL_IS_LCD) { pll 160 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c vco_min = pll->lcd_pll_out_min; pll 161 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c vco_max = pll->lcd_pll_out_max; pll 163 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c vco_min = pll->pll_out_min; pll 164 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c vco_max = pll->pll_out_max; pll 167 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { pll 175 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c if (post_div_min < pll->min_post_div) pll 176 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c post_div_min = pll->min_post_div; pll 181 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c if (post_div_max > pll->max_post_div) pll 182 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c post_div_max = pll->max_post_div; pll 187 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c den = pll->reference_freq; pll 193 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c if (pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP) pll 203 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c diff = abs(target_clock - (pll->reference_freq * fb_div) / pll 207 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c !(pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP))) { pll 224 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { pll 234 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { pll 242 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + pll 243 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c (pll->reference_freq * *frac_fb_div_p)) / pll 27 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.h void amdgpu_pll_compute(struct amdgpu_pll *pll, pll 827 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c struct amdgpu_pll *pll; pll 837 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c pll = &adev->clock.ppll[0]; pll 840 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c pll = &adev->clock.ppll[1]; pll 845 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c pll = &adev->clock.ppll[2]; pll 850 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c pll->flags = amdgpu_crtc->pll_flags; pll 851 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c pll->reference_div = amdgpu_crtc->pll_reference_div; pll 852 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c pll->post_div = amdgpu_crtc->pll_post_div; pll 854 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c amdgpu_pll_compute(pll, amdgpu_crtc->adjusted_clock, &pll_clock, pll 876 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c (125 * 25 * pll->reference_freq / 100); pll 879 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c (125 * 25 * pll->reference_freq / 100); pll 2237 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c int pll; pll 2245 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c pll = amdgpu_pll_get_shared_dp_ppll(crtc); pll 2246 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (pll != ATOM_PPLL_INVALID) pll 2247 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c return pll; pll 2251 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c pll = amdgpu_pll_get_shared_nondp_ppll(crtc); pll 2252 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (pll != ATOM_PPLL_INVALID) pll 2253 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c return pll; pll 2270 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c int pll; pll 2314 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c pll = amdgpu_pll_get_shared_dp_ppll(crtc); pll 2315 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (pll != ATOM_PPLL_INVALID) pll 2316 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c return pll; pll 2320 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c pll = amdgpu_pll_get_shared_nondp_ppll(crtc); pll 2321 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (pll != ATOM_PPLL_INVALID) pll 2322 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c return pll; pll 2133 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c int pll; pll 2143 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c pll = amdgpu_pll_get_shared_nondp_ppll(crtc); pll 2144 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (pll != ATOM_PPLL_INVALID) pll 2145 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c return pll; pll 2127 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c int pll; pll 2135 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c pll = amdgpu_pll_get_shared_dp_ppll(crtc); pll 2136 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (pll != ATOM_PPLL_INVALID) pll 2137 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c return pll; pll 2141 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c pll = amdgpu_pll_get_shared_nondp_ppll(crtc); pll 2142 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (pll != ATOM_PPLL_INVALID) pll 2143 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c return pll; pll 235 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c struct hibmc_display_panel_pll pll = {0}; pll 246 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POD, pll.POD); pll 247 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_OD, pll.OD); pll 248 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_N, pll.N); pll 249 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M); pll 254 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c static void set_vclock_hisilicon(struct drm_device *dev, unsigned long pll) pll 266 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c writel(pll, priv->mmio + CRT_PLL1_HS); pll 270 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c val = pll & ~(CRT_PLL1_HS_POWERON(1)); pll 596 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_shared_dpll *pll = crtc_state->shared_dpll; pll 605 drivers/gpu/drm/i915/display/icl_dsi.c val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); pll 998 drivers/gpu/drm/i915/display/intel_ddi.c static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) pll 1000 drivers/gpu/drm/i915/display/intel_ddi.c switch (pll->info->id) { pll 1014 drivers/gpu/drm/i915/display/intel_ddi.c MISSING_CASE(pll->info->id); pll 1022 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_shared_dpll *pll = crtc_state->shared_dpll; pll 1024 drivers/gpu/drm/i915/display/intel_ddi.c const enum intel_dpll_id id = pll->info->id; pll 1612 drivers/gpu/drm/i915/display/intel_ddi.c u32 val, pll; pll 1632 drivers/gpu/drm/i915/display/intel_ddi.c pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK; pll 1633 drivers/gpu/drm/i915/display/intel_ddi.c if (pll == SPLL_FREQ_810MHz) pll 1635 drivers/gpu/drm/i915/display/intel_ddi.c else if (pll == SPLL_FREQ_1350MHz) pll 1637 drivers/gpu/drm/i915/display/intel_ddi.c else if (pll == SPLL_FREQ_2700MHz) pll 2793 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_shared_dpll *pll = crtc_state->shared_dpll; pll 2814 drivers/gpu/drm/i915/display/intel_ddi.c val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); pll 2925 drivers/gpu/drm/i915/display/intel_ddi.c const struct intel_shared_dpll *pll = crtc_state->shared_dpll; pll 2927 drivers/gpu/drm/i915/display/intel_ddi.c if (WARN_ON(!pll)) pll 2946 drivers/gpu/drm/i915/display/intel_ddi.c val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); pll 2963 drivers/gpu/drm/i915/display/intel_ddi.c val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | pll 2969 drivers/gpu/drm/i915/display/intel_ddi.c I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); pll 9995 drivers/gpu/drm/i915/display/intel_display.c struct intel_shared_dpll *pll; pll 10022 drivers/gpu/drm/i915/display/intel_display.c pll = pipe_config->shared_dpll; pll 10024 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll, pll 10118 drivers/gpu/drm/i915/display/intel_display.c pipe_config->icl_port_dplls[port_dpll_id].pll = pll 10355 drivers/gpu/drm/i915/display/intel_display.c struct intel_shared_dpll *pll; pll 10377 drivers/gpu/drm/i915/display/intel_display.c pll = pipe_config->shared_dpll; pll 10378 drivers/gpu/drm/i915/display/intel_display.c if (pll) { pll 10379 drivers/gpu/drm/i915/display/intel_display.c WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll, pll 13169 drivers/gpu/drm/i915/display/intel_display.c struct intel_shared_dpll *pll, pll 13179 drivers/gpu/drm/i915/display/intel_display.c DRM_DEBUG_KMS("%s\n", pll->info->name); pll 13181 drivers/gpu/drm/i915/display/intel_display.c active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state); pll 13183 drivers/gpu/drm/i915/display/intel_display.c if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) { pll 13184 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(!pll->on && pll->active_mask, pll 13186 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(pll->on && !pll->active_mask, pll 13188 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(pll->on != active, pll 13190 drivers/gpu/drm/i915/display/intel_display.c pll->on, active); pll 13194 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask, pll 13196 drivers/gpu/drm/i915/display/intel_display.c pll->active_mask, pll->state.crtc_mask); pll 13204 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(!(pll->active_mask & crtc_mask), pll 13206 drivers/gpu/drm/i915/display/intel_display.c pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask); pll 13208 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(pll->active_mask & crtc_mask, pll 13210 drivers/gpu/drm/i915/display/intel_display.c pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask); pll 13212 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask), pll 13214 drivers/gpu/drm/i915/display/intel_display.c crtc_mask, pll->state.crtc_mask); pll 13216 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, pll 13235 drivers/gpu/drm/i915/display/intel_display.c struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; pll 13237 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(pll->active_mask & crtc_mask, pll 13240 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(pll->state.crtc_mask & crtc_mask, pll 16697 drivers/gpu/drm/i915/display/intel_display.c struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; pll 16699 drivers/gpu/drm/i915/display/intel_display.c pll->on = pll->info->funcs->get_hw_state(dev_priv, pll, pll 16700 drivers/gpu/drm/i915/display/intel_display.c &pll->state.hw_state); pll 16702 drivers/gpu/drm/i915/display/intel_display.c if (IS_ELKHARTLAKE(dev_priv) && pll->on && pll 16703 drivers/gpu/drm/i915/display/intel_display.c pll->info->id == DPLL_ID_EHL_DPLL4) { pll 16704 drivers/gpu/drm/i915/display/intel_display.c pll->wakeref = intel_display_power_get(dev_priv, pll 16708 drivers/gpu/drm/i915/display/intel_display.c pll->state.crtc_mask = 0; pll 16714 drivers/gpu/drm/i915/display/intel_display.c crtc_state->shared_dpll == pll) pll 16715 drivers/gpu/drm/i915/display/intel_display.c pll->state.crtc_mask |= 1 << crtc->pipe; pll 16717 drivers/gpu/drm/i915/display/intel_display.c pll->active_mask = pll->state.crtc_mask; pll 16720 drivers/gpu/drm/i915/display/intel_display.c pll->info->name, pll->state.crtc_mask, pll->on); pll 17003 drivers/gpu/drm/i915/display/intel_display.c struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; pll 17005 drivers/gpu/drm/i915/display/intel_display.c if (!pll->on || pll->active_mask) pll 17009 drivers/gpu/drm/i915/display/intel_display.c pll->info->name); pll 17011 drivers/gpu/drm/i915/display/intel_display.c pll->info->funcs->disable(dev_priv, pll); pll 17012 drivers/gpu/drm/i915/display/intel_display.c pll->on = false; pll 850 drivers/gpu/drm/i915/display/intel_display_types.h struct intel_shared_dpll *pll; pll 56 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; pll 58 drivers/gpu/drm/i915/display/intel_dpll_mgr.c shared_dpll[i] = pll->state; pll 104 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 106 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (WARN_ON(pll < dev_priv->shared_dplls|| pll 107 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll])) pll 110 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return (enum intel_dpll_id) (pll - dev_priv->shared_dplls); pll 115 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll, pll 121 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state))) pll 124 drivers/gpu/drm/i915/display/intel_dpll_mgr.c cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state); pll 127 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->info->name, onoff(state), onoff(cur_state)); pll 141 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll = crtc_state->shared_dpll; pll 143 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (WARN_ON(pll == NULL)) pll 147 drivers/gpu/drm/i915/display/intel_dpll_mgr.c WARN_ON(!pll->state.crtc_mask); pll 148 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!pll->active_mask) { pll 149 drivers/gpu/drm/i915/display/intel_dpll_mgr.c DRM_DEBUG_DRIVER("setting up %s\n", pll->info->name); pll 150 drivers/gpu/drm/i915/display/intel_dpll_mgr.c WARN_ON(pll->on); pll 151 drivers/gpu/drm/i915/display/intel_dpll_mgr.c assert_shared_dpll_disabled(dev_priv, pll); pll 153 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->info->funcs->prepare(dev_priv, pll); pll 168 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll = crtc_state->shared_dpll; pll 172 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (WARN_ON(pll == NULL)) pll 176 drivers/gpu/drm/i915/display/intel_dpll_mgr.c old_mask = pll->active_mask; pll 178 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (WARN_ON(!(pll->state.crtc_mask & crtc_mask)) || pll 179 drivers/gpu/drm/i915/display/intel_dpll_mgr.c WARN_ON(pll->active_mask & crtc_mask)) pll 182 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->active_mask |= crtc_mask; pll 185 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->info->name, pll->active_mask, pll->on, pll 189 drivers/gpu/drm/i915/display/intel_dpll_mgr.c WARN_ON(!pll->on); pll 190 drivers/gpu/drm/i915/display/intel_dpll_mgr.c assert_shared_dpll_enabled(dev_priv, pll); pll 193 drivers/gpu/drm/i915/display/intel_dpll_mgr.c WARN_ON(pll->on); pll 195 drivers/gpu/drm/i915/display/intel_dpll_mgr.c DRM_DEBUG_KMS("enabling %s\n", pll->info->name); pll 196 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->info->funcs->enable(dev_priv, pll); pll 197 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->on = true; pll 213 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll = crtc_state->shared_dpll; pll 220 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (pll == NULL) pll 224 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (WARN_ON(!(pll->active_mask & crtc_mask))) pll 228 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->info->name, pll->active_mask, pll->on, pll 231 drivers/gpu/drm/i915/display/intel_dpll_mgr.c assert_shared_dpll_enabled(dev_priv, pll); pll 232 drivers/gpu/drm/i915/display/intel_dpll_mgr.c WARN_ON(!pll->on); pll 234 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->active_mask &= ~crtc_mask; pll 235 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (pll->active_mask) pll 238 drivers/gpu/drm/i915/display/intel_dpll_mgr.c DRM_DEBUG_KMS("disabling %s\n", pll->info->name); pll 239 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->info->funcs->disable(dev_priv, pll); pll 240 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->on = false; pll 254 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll, *unused_pll = NULL; pll 261 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll = &dev_priv->shared_dplls[i]; pll 266 drivers/gpu/drm/i915/display/intel_dpll_mgr.c unused_pll = pll; pll 275 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->info->name, pll 277 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->active_mask); pll 278 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return pll; pll 296 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const struct intel_shared_dpll *pll, pll 300 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 307 drivers/gpu/drm/i915/display/intel_dpll_mgr.c DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->info->name, pll 315 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const struct intel_shared_dpll *pll) pll 320 drivers/gpu/drm/i915/display/intel_dpll_mgr.c shared_dpll[pll->info->id].crtc_mask &= ~(1 << crtc->pipe); pll 360 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll = pll 363 drivers/gpu/drm/i915/display/intel_dpll_mgr.c swap(pll->state, shared_dpll[i]); pll 368 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll, pll 371 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 391 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 393 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 395 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(PCH_FP0(id), pll->state.hw_state.fp0); pll 396 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(PCH_FP1(id), pll->state.hw_state.fp1); pll 413 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 415 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 420 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll); pll 431 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll); pll 437 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 439 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 453 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll; pll 459 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll = &dev_priv->shared_dplls[i]; pll 463 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->info->name); pll 465 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll = intel_find_shared_dpll(state, crtc, pll 471 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!pll) pll 476 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll, &crtc_state->dpll_hw_state); pll 478 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->shared_dpll = pll; pll 502 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 504 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 506 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(WRPLL_CTL(id), pll->state.hw_state.wrpll); pll 512 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 514 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(SPLL_CTL, pll->state.hw_state.spll); pll 520 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 522 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 538 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 540 drivers/gpu/drm/i915/display/intel_dpll_mgr.c enum intel_dpll_id id = pll->info->id; pll 556 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll, pll 559 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 577 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll, pll 818 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll; pll 830 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll = intel_find_shared_dpll(state, crtc, pll 834 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!pll) pll 837 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return pll; pll 844 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll; pll 863 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll = intel_get_shared_dpll_by_id(dev_priv, pll_id); pll 865 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!pll) pll 868 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return pll; pll 877 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll; pll 883 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll = hsw_ddi_hdmi_get_dpll(state, crtc); pll 885 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll = hsw_ddi_dp_get_dpll(crtc_state); pll 893 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll = intel_find_shared_dpll(state, crtc, pll 900 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!pll) pll 904 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll, &crtc_state->dpll_hw_state); pll 906 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->shared_dpll = pll; pll 931 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 936 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 941 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll, pll 985 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 987 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 995 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val |= pll->state.hw_state.ctrl1 << (id * 6); pll 1002 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 1005 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 1007 drivers/gpu/drm/i915/display/intel_dpll_mgr.c skl_ddi_pll_write_ctrl1(dev_priv, pll); pll 1009 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(regs[id].cfgcr1, pll->state.hw_state.cfgcr1); pll 1010 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(regs[id].cfgcr2, pll->state.hw_state.cfgcr2); pll 1023 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 1025 drivers/gpu/drm/i915/display/intel_dpll_mgr.c skl_ddi_pll_write_ctrl1(dev_priv, pll); pll 1029 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 1032 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 1041 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 1046 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll, pll 1051 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 1083 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll, pll 1087 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 1443 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll; pll 1463 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll = intel_find_shared_dpll(state, crtc, pll 1468 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll = intel_find_shared_dpll(state, crtc, pll 1472 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!pll) pll 1476 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll, &crtc_state->dpll_hw_state); pll 1478 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->shared_dpll = pll; pll 1506 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 1509 drivers/gpu/drm/i915/display/intel_dpll_mgr.c enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ pll 1538 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.ebb0; pll 1544 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll0; pll 1550 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll1; pll 1556 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll2; pll 1562 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll3; pll 1570 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll6; pll 1576 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll8; pll 1581 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll9; pll 1587 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll10; pll 1595 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.ebb4; pll 1621 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pcsdw12; pll 1626 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 1628 drivers/gpu/drm/i915/display/intel_dpll_mgr.c enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ pll 1648 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll, pll 1651 drivers/gpu/drm/i915/display/intel_dpll_mgr.c enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ pll 1893 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll; pll 1906 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll = intel_get_shared_dpll_by_id(dev_priv, id); pll 1909 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc->base.base.id, crtc->base.name, pll->info->name); pll 1912 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll, &crtc_state->dpll_hw_state); pll 1914 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->shared_dpll = pll; pll 2019 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 2021 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 2038 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = pll->state.hw_state.cfgcr0; pll 2046 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { pll 2047 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = pll->state.hw_state.cfgcr1; pll 2087 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 2089 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 2136 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll, pll 2139 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 2396 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll; pll 2417 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll = intel_find_shared_dpll(state, crtc, pll 2421 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!pll) { pll 2427 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll, &crtc_state->dpll_hw_state); pll 2429 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->shared_dpll = pll; pll 2876 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->shared_dpll = port_dpll->pll; pll 2922 drivers/gpu/drm/i915/display/intel_dpll_mgr.c port_dpll->pll = intel_find_shared_dpll(state, crtc, pll 2927 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!port_dpll->pll) { pll 2934 drivers/gpu/drm/i915/display/intel_dpll_mgr.c port_dpll->pll, &port_dpll->hw_state); pll 2957 drivers/gpu/drm/i915/display/intel_dpll_mgr.c port_dpll->pll = intel_find_shared_dpll(state, crtc, pll 2961 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!port_dpll->pll) { pll 2966 drivers/gpu/drm/i915/display/intel_dpll_mgr.c port_dpll->pll, &port_dpll->hw_state); pll 2977 drivers/gpu/drm/i915/display/intel_dpll_mgr.c port_dpll->pll = intel_find_shared_dpll(state, crtc, pll 2981 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!port_dpll->pll) { pll 2986 drivers/gpu/drm/i915/display/intel_dpll_mgr.c port_dpll->pll, &port_dpll->hw_state); pll 2994 drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_unreference_shared_dpll(state, crtc, port_dpll->pll); pll 3033 drivers/gpu/drm/i915/display/intel_dpll_mgr.c new_port_dpll->pll = NULL; pll 3035 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!old_port_dpll->pll) pll 3038 drivers/gpu/drm/i915/display/intel_dpll_mgr.c intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll); pll 3043 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll, pll 3046 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 3105 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll, pll 3109 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 3143 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll, pll 3146 drivers/gpu/drm/i915/display/intel_dpll_mgr.c i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); pll 3149 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->info->id == DPLL_ID_EHL_DPLL4) { pll 3153 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg); pll 3157 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll, pll 3160 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return icl_pll_get_hw_state(dev_priv, pll, hw_state, TBT_PLL_ENABLE); pll 3164 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 3166 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *hw_state = &pll->state.hw_state; pll 3167 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const enum intel_dpll_id id = pll->info->id; pll 3189 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 3191 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *hw_state = &pll->state.hw_state; pll 3192 drivers/gpu/drm/i915/display/intel_dpll_mgr.c enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id); pll 3239 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll, pll 3253 drivers/gpu/drm/i915/display/intel_dpll_mgr.c DRM_ERROR("PLL %d Power not enabled\n", pll->info->id); pll 3257 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll, pll 3268 drivers/gpu/drm/i915/display/intel_dpll_mgr.c DRM_ERROR("PLL %d not locked\n", pll->info->id); pll 3272 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 3274 drivers/gpu/drm/i915/display/intel_dpll_mgr.c i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); pll 3277 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->info->id == DPLL_ID_EHL_DPLL4) { pll 3285 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->wakeref = intel_display_power_get(dev_priv, pll 3289 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_power_enable(dev_priv, pll, enable_reg); pll 3291 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_dpll_write(dev_priv, pll); pll 3299 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_enable(dev_priv, pll, enable_reg); pll 3305 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 3307 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_power_enable(dev_priv, pll, TBT_PLL_ENABLE); pll 3309 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_dpll_write(dev_priv, pll); pll 3317 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_enable(dev_priv, pll, TBT_PLL_ENABLE); pll 3323 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 3326 drivers/gpu/drm/i915/display/intel_dpll_mgr.c MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id)); pll 3328 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_power_enable(dev_priv, pll, enable_reg); pll 3330 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_mg_pll_write(dev_priv, pll); pll 3338 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_enable(dev_priv, pll, enable_reg); pll 3344 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll, pll 3363 drivers/gpu/drm/i915/display/intel_dpll_mgr.c DRM_ERROR("PLL %d locked\n", pll->info->id); pll 3376 drivers/gpu/drm/i915/display/intel_dpll_mgr.c DRM_ERROR("PLL %d Power not disabled\n", pll->info->id); pll 3380 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 3382 drivers/gpu/drm/i915/display/intel_dpll_mgr.c i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); pll 3385 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->info->id == DPLL_ID_EHL_DPLL4) { pll 3387 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_disable(dev_priv, pll, enable_reg); pll 3390 drivers/gpu/drm/i915/display/intel_dpll_mgr.c pll->wakeref); pll 3394 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_disable(dev_priv, pll, enable_reg); pll 3398 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 3400 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_disable(dev_priv, pll, TBT_PLL_ENABLE); pll 3404 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_shared_dpll *pll) pll 3407 drivers/gpu/drm/i915/display/intel_dpll_mgr.c MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id)); pll 3409 drivers/gpu/drm/i915/display/intel_dpll_mgr.c icl_pll_disable(dev_priv, pll, enable_reg); pll 250 drivers/gpu/drm/i915/display/intel_dpll_mgr.h struct intel_shared_dpll *pll); pll 259 drivers/gpu/drm/i915/display/intel_dpll_mgr.h struct intel_shared_dpll *pll); pll 269 drivers/gpu/drm/i915/display/intel_dpll_mgr.h struct intel_shared_dpll *pll); pll 279 drivers/gpu/drm/i915/display/intel_dpll_mgr.h struct intel_shared_dpll *pll, pll 354 drivers/gpu/drm/i915/display/intel_dpll_mgr.h struct intel_shared_dpll *pll); pll 356 drivers/gpu/drm/i915/display/intel_dpll_mgr.h struct intel_shared_dpll *pll, pll 2832 drivers/gpu/drm/i915/i915_debugfs.c struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; pll 2834 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name, pll 2835 drivers/gpu/drm/i915/i915_debugfs.c pll->info->id); pll 2837 drivers/gpu/drm/i915/i915_debugfs.c pll->state.crtc_mask, pll->active_mask, yesno(pll->on)); pll 2839 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); pll 2841 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.dpll_md); pll 2842 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); pll 2843 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); pll 2844 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); pll 2845 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0); pll 2846 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1); pll 2848 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_refclkin_ctl); pll 2850 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_clktop2_coreclkctl1); pll 2852 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_clktop2_hsclkctl); pll 2854 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_pll_div0); pll 2856 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_pll_div1); pll 2858 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_pll_lf); pll 2860 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_pll_frac_lock); pll 2862 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_pll_ssc); pll 2864 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_pll_bias); pll 2866 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_pll_tdc_coldst_bias); pll 232 drivers/gpu/drm/i915/i915_reg.h #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) pll 238 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) pll 245 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c)) pll 8070 drivers/gpu/drm/i915/i915_reg.h #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) pll 8077 drivers/gpu/drm/i915/i915_reg.h #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) pll 8078 drivers/gpu/drm/i915/i915_reg.h #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) pll 9553 drivers/gpu/drm/i915/i915_reg.h #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) pll 9579 drivers/gpu/drm/i915/i915_reg.h #define PORT_CLK_SEL_WRPLL(pll) (((pll) + 4) << 29) pll 9741 drivers/gpu/drm/i915/i915_reg.h #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) pll 9750 drivers/gpu/drm/i915/i915_reg.h #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) pll 9759 drivers/gpu/drm/i915/i915_reg.h #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE) pll 9932 drivers/gpu/drm/i915/i915_reg.h #define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0) pll 9957 drivers/gpu/drm/i915/i915_reg.h #define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1) pll 9961 drivers/gpu/drm/i915/i915_reg.h #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ pll 9966 drivers/gpu/drm/i915/i915_reg.h #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ pll 9973 drivers/gpu/drm/i915/i915_reg.h #define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ pll 9981 drivers/gpu/drm/i915/i915_reg.h #define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ pll 61 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c ret = clk_prepare_enable(hdmi_phy->pll); pll 74 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c clk_disable_unprepare(hdmi_phy->pll); pll 147 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw); pll 148 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c if (IS_ERR(hdmi_phy->pll)) { pll 149 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c ret = PTR_ERR(hdmi_phy->pll); pll 188 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c hdmi_phy->pll); pll 34 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h struct clk *pll; pll 132 drivers/gpu/drm/mediatek/mtk_mipi_tx.c struct clk *pll; pll 339 drivers/gpu/drm/mediatek/mtk_mipi_tx.c ret = clk_prepare_enable(mipi_tx->pll); pll 370 drivers/gpu/drm/mediatek/mtk_mipi_tx.c clk_disable_unprepare(mipi_tx->pll); pll 427 drivers/gpu/drm/mediatek/mtk_mipi_tx.c mipi_tx->pll = devm_clk_register(dev, &mipi_tx->pll_hw); pll 428 drivers/gpu/drm/mediatek/mtk_mipi_tx.c if (IS_ERR(mipi_tx->pll)) { pll 429 drivers/gpu/drm/mediatek/mtk_mipi_tx.c ret = PTR_ERR(mipi_tx->pll); pll 451 drivers/gpu/drm/mediatek/mtk_mipi_tx.c mipi_tx->pll); pll 109 drivers/gpu/drm/msm/dsi/dsi.h void msm_dsi_pll_destroy(struct msm_dsi_pll *pll); pll 110 drivers/gpu/drm/msm/dsi/dsi.h int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll, pll 112 drivers/gpu/drm/msm/dsi/dsi.h void msm_dsi_pll_save_state(struct msm_dsi_pll *pll); pll 113 drivers/gpu/drm/msm/dsi/dsi.h int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll); pll 114 drivers/gpu/drm/msm/dsi/dsi.h int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll, pll 121 drivers/gpu/drm/msm/dsi/dsi.h static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll) pll 124 drivers/gpu/drm/msm/dsi/dsi.h static inline int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll, pll 129 drivers/gpu/drm/msm/dsi/dsi.h static inline void msm_dsi_pll_save_state(struct msm_dsi_pll *pll) pll 132 drivers/gpu/drm/msm/dsi/dsi.h static inline int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll) pll 136 drivers/gpu/drm/msm/dsi/dsi.h static inline int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll, pll 614 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id); pll 615 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c if (IS_ERR_OR_NULL(phy->pll)) { pll 618 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c __func__, PTR_ERR(phy->pll)); pll 619 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c phy->pll = NULL; pll 636 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c if (phy && phy->pll) { pll 637 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c msm_dsi_pll_destroy(phy->pll); pll 638 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c phy->pll = NULL; pll 701 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c ret = msm_dsi_pll_restore_state(phy->pll); pll 745 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c return phy->pll; pll 91 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h struct msm_dsi_pll *pll; pll 178 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c ret = msm_dsi_pll_set_usecase(phy->pll, phy->usecase); pll 110 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c ret = msm_dsi_pll_set_usecase(phy->pll, phy->usecase); pll 8 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c static int dsi_pll_enable(struct msm_dsi_pll *pll) pll 16 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c if (unlikely(pll->pll_on)) pll 20 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c for (i = 0; i < pll->en_seq_cnt; i++) { pll 21 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c ret = pll->enable_seqs[i](pll); pll 33 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c pll->pll_on = true; pll 38 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c static void dsi_pll_disable(struct msm_dsi_pll *pll) pll 40 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c if (unlikely(!pll->pll_on)) pll 43 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c pll->disable_seq(pll); pll 45 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c pll->pll_on = false; pll 54 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c struct msm_dsi_pll *pll = hw_clk_to_pll(hw); pll 56 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c if (rate < pll->min_rate) pll 57 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c return pll->min_rate; pll 58 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c else if (rate > pll->max_rate) pll 59 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c return pll->max_rate; pll 66 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c struct msm_dsi_pll *pll = hw_clk_to_pll(hw); pll 68 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c return dsi_pll_enable(pll); pll 73 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c struct msm_dsi_pll *pll = hw_clk_to_pll(hw); pll 75 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c dsi_pll_disable(pll); pll 95 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll, pll 98 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c if (pll->get_provider) pll 99 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c return pll->get_provider(pll, pll 106 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c void msm_dsi_pll_destroy(struct msm_dsi_pll *pll) pll 108 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c if (pll->destroy) pll 109 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c pll->destroy(pll); pll 112 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c void msm_dsi_pll_save_state(struct msm_dsi_pll *pll) pll 114 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c if (pll->save_state) { pll 115 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c pll->save_state(pll); pll 116 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c pll->state_saved = true; pll 120 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll) pll 124 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c if (pll->restore_state && pll->state_saved) { pll 125 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c ret = pll->restore_state(pll); pll 129 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c pll->state_saved = false; pll 135 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll, pll 138 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c if (pll->set_usecase) pll 139 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c return pll->set_usecase(pll, uc); pll 148 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c struct msm_dsi_pll *pll; pll 153 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c pll = msm_dsi_pll_28nm_init(pdev, type, id); pll 156 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c pll = msm_dsi_pll_28nm_8960_init(pdev, id); pll 159 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c pll = msm_dsi_pll_14nm_init(pdev, id); pll 162 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c pll = msm_dsi_pll_10nm_init(pdev, id); pll 165 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c pll = ERR_PTR(-ENXIO); pll 169 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c if (IS_ERR(pll)) { pll 171 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c return pll; pll 174 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c pll->type = type; pll 178 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c return pll; pll 28 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h int (*enable_seqs[MAX_DSI_PLL_EN_SEQS])(struct msm_dsi_pll *pll); pll 29 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h void (*disable_seq)(struct msm_dsi_pll *pll); pll 30 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h int (*get_provider)(struct msm_dsi_pll *pll, pll 33 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h void (*destroy)(struct msm_dsi_pll *pll); pll 34 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h void (*save_state)(struct msm_dsi_pll *pll); pll 35 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h int (*restore_state)(struct msm_dsi_pll *pll); pll 36 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h int (*set_usecase)(struct msm_dsi_pll *pll, pll 132 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c static void dsi_pll_setup_config(struct dsi_pll_10nm *pll) pll 134 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_config *config = &pll->pll_configuration; pll 136 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c config->ref_freq = pll->vco_ref_clk_rate; pll 155 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll) pll 157 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_config *config = &pll->pll_configuration; pll 158 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_regs *regs = &pll->reg_setup; pll 159 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c u64 fref = pll->vco_ref_clk_rate; pll 166 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_freq = pll->vco_current_rate; pll 200 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll) pll 202 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_config *config = &pll->pll_configuration; pll 203 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_regs *regs = &pll->reg_setup; pll 244 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll) pll 246 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c void __iomem *base = pll->mmio; pll 247 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_regs *regs = &pll->reg_setup; pll 249 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c if (pll->pll_configuration.enable_ssc) { pll 269 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll) pll 271 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c void __iomem *base = pll->mmio; pll 295 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c static void dsi_pll_commit(struct dsi_pll_10nm *pll) pll 297 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c void __iomem *base = pll->mmio; pll 298 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_regs *reg = &pll->reg_setup; pll 319 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct msm_dsi_pll *pll = hw_clk_to_pll(hw); pll 320 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); pll 346 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll) pll 353 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c rc = readl_poll_timeout_atomic(pll->mmio + pll 361 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll->id, status); pll 366 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c static void dsi_pll_disable_pll_bias(struct dsi_pll_10nm *pll) pll 368 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0); pll 370 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0); pll 371 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0, pll 376 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c static void dsi_pll_enable_pll_bias(struct dsi_pll_10nm *pll) pll 378 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0); pll 380 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0, pll 382 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0); pll 386 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c static void dsi_pll_disable_global_clk(struct dsi_pll_10nm *pll) pll 390 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1); pll 391 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1, pll 395 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll) pll 399 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1); pll 400 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1, pll 406 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct msm_dsi_pll *pll = hw_clk_to_pll(hw); pll 407 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); pll 437 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll->pll_on = true; pll 453 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll) pll 455 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0); pll 456 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c dsi_pll_disable_pll_bias(pll); pll 461 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct msm_dsi_pll *pll = hw_clk_to_pll(hw); pll 462 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); pll 478 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll->pll_on = false; pll 484 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct msm_dsi_pll *pll = hw_clk_to_pll(hw); pll 485 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); pll 533 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c static void dsi_pll_10nm_save_state(struct msm_dsi_pll *pll) pll 535 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); pll 556 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c static int dsi_pll_10nm_restore_state(struct msm_dsi_pll *pll) pll 558 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); pll 581 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll, pll 584 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); pll 611 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c static int dsi_pll_10nm_get_provider(struct msm_dsi_pll *pll, pll 615 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); pll 628 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll) pll 630 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll); pll 824 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c struct msm_dsi_pll *pll; pll 851 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll = &pll_10nm->base; pll 852 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll->min_rate = 1000000000UL; pll 853 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll->max_rate = 3500000000UL; pll 854 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll->get_provider = dsi_pll_10nm_get_provider; pll 855 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll->destroy = dsi_pll_10nm_destroy; pll 856 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll->save_state = dsi_pll_10nm_save_state; pll 857 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll->restore_state = dsi_pll_10nm_restore_state; pll 858 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c pll->set_usecase = dsi_pll_10nm_set_usecase; pll 869 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c msm_dsi_pll_save_state(pll); pll 871 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c return pll; pll 165 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm *pll; pll 214 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c static void dsi_pll_14nm_input_init(struct dsi_pll_14nm *pll) pll 216 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.fref = pll->vco_ref_clk_rate; pll 217 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.fdata = 0; pll 218 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.dsiclk_sel = 1; /* Use the /2 path in Mux */ pll 219 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.ldo_en = 0; /* disabled for now */ pll 222 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.refclk_dbler_en = 0; pll 223 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.vco_measure_time = 5; pll 224 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.kvco_measure_time = 5; pll 225 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.bandgap_timer = 4; pll 226 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.pll_wakeup_timer = 5; pll 227 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.plllock_cnt = 1; pll 228 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.plllock_rng = 0; pll 234 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.ssc_en = 1; pll 235 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.ssc_center = 0; /* down spread by default */ pll 236 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.ssc_spread = 5; /* PPM / 1000 */ pll 237 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.ssc_freq = 31500; /* default recommended */ pll 238 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.ssc_adj_period = 37; pll 240 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.pll_ie_trim = 4; pll 241 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.pll_ip_trim = 4; pll 242 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.pll_cpcset_cur = 1; pll 243 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.pll_cpmset_cur = 1; pll 244 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.pll_icpmset = 4; pll 245 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.pll_icpcset = 4; pll 246 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.pll_icpmset_p = 0; pll 247 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.pll_icpmset_m = 0; pll 248 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.pll_icpcset_p = 0; pll 249 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.pll_icpcset_m = 0; pll 250 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.pll_lpf_res1 = 3; pll 251 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.pll_lpf_cap1 = 11; pll 252 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.pll_lpf_cap2 = 1; pll 253 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.pll_iptat_trim = 7; pll 254 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.pll_c3ctrl = 2; pll 255 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.pll_r3ctrl = 1; pll 260 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll) pll 266 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c DBG("vco=%lld ref=%lld", pll->vco_current_rate, pll->vco_ref_clk_rate); pll 268 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c ssc_period = pll->in.ssc_freq / 500; pll 269 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c period = (u32)pll->vco_ref_clk_rate / 1000; pll 272 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->out.ssc_period = ssc_period; pll 274 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c DBG("ssc freq=%d spread=%d period=%d", pll->in.ssc_freq, pll 275 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->in.ssc_spread, pll->out.ssc_period); pll 277 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c step_size = (u32)pll->vco_current_rate; pll 278 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c ref = pll->vco_ref_clk_rate; pll 283 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c step_size *= pll->in.ssc_spread; pll 285 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c step_size *= (pll->in.ssc_adj_period + 1); pll 296 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->out.ssc_step_size = step_size; pll 299 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll) pll 301 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_input *pin = &pll->in; pll 302 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_output *pout = &pll->out; pll 306 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c u64 vco_clk_rate = pll->vco_current_rate; pll 307 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c u64 fref = pll->vco_ref_clk_rate; pll 352 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll) pll 354 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_input *pin = &pll->in; pll 355 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_output *pout = &pll->out; pll 356 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c u64 vco_clk_rate = pll->vco_current_rate; pll 357 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c u64 fref = pll->vco_ref_clk_rate; pll 391 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c static void pll_db_commit_ssc(struct dsi_pll_14nm *pll) pll 393 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *base = pll->mmio; pll 394 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_input *pin = &pll->in; pll 395 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_output *pout = &pll->out; pll 427 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c static void pll_db_commit_common(struct dsi_pll_14nm *pll, pll 431 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *base = pll->mmio; pll 506 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c static void pll_db_commit_14nm(struct dsi_pll_14nm *pll, pll 510 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *base = pll->mmio; pll 511 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c void __iomem *cmn_base = pll->phy_cmn_mmio; pll 514 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c DBG("DSI%d PLL", pll->id); pll 519 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_db_commit_common(pll, pin, pout); pll 521 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_14nm_software_reset(pll); pll 566 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_db_commit_ssc(pll); pll 577 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct msm_dsi_pll *pll = hw_clk_to_pll(hw); pll 578 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); pll 627 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct msm_dsi_pll *pll = hw_clk_to_pll(hw); pll 628 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); pll 681 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm *pll_14nm = postdiv->pll; pll 701 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm *pll_14nm = postdiv->pll; pll 714 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm *pll_14nm = postdiv->pll; pll 762 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c static int dsi_pll_14nm_enable_seq(struct msm_dsi_pll *pll) pll 764 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); pll 785 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c static void dsi_pll_14nm_disable_seq(struct msm_dsi_pll *pll) pll 787 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); pll 795 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c static void dsi_pll_14nm_save_state(struct msm_dsi_pll *pll) pll 797 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); pll 810 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw); pll 813 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c static int dsi_pll_14nm_restore_state(struct msm_dsi_pll *pll) pll 815 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); pll 821 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c ret = dsi_pll_14nm_vco_set_rate(&pll->clk_hw, pll 847 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll, pll 850 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); pll 879 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c static int dsi_pll_14nm_get_provider(struct msm_dsi_pll *pll, pll 883 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); pll 894 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c static void dsi_pll_14nm_destroy(struct msm_dsi_pll *pll) pll 896 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll); pll 927 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll_postdiv->pll = pll_14nm; pll 1044 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c struct msm_dsi_pll *pll; pll 1074 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll = &pll_14nm->base; pll 1075 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->min_rate = VCO_MIN_RATE; pll 1076 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->max_rate = VCO_MAX_RATE; pll 1077 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->get_provider = dsi_pll_14nm_get_provider; pll 1078 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->destroy = dsi_pll_14nm_destroy; pll 1079 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->disable_seq = dsi_pll_14nm_disable_seq; pll 1080 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->save_state = dsi_pll_14nm_save_state; pll 1081 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->restore_state = dsi_pll_14nm_restore_state; pll 1082 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->set_usecase = dsi_pll_14nm_set_usecase; pll 1086 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->en_seq_cnt = 1; pll 1087 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c pll->enable_seqs[0] = dsi_pll_14nm_enable_seq; pll 1095 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c return pll; pll 130 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct msm_dsi_pll *pll = hw_clk_to_pll(hw); pll 131 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 245 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct msm_dsi_pll *pll = hw_clk_to_pll(hw); pll 246 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 255 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct msm_dsi_pll *pll = hw_clk_to_pll(hw); pll 256 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 313 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c static int dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll) pll 315 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 388 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll) pll 390 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 431 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll) pll 433 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 439 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll) pll 441 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 450 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw); pll 453 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll) pll 455 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 460 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw, pll 478 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll, pll 482 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 493 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) pll 495 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 587 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c struct msm_dsi_pll *pll; pll 606 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll = &pll_28nm->base; pll 607 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll->min_rate = VCO_MIN_RATE; pll 608 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll->max_rate = VCO_MAX_RATE; pll 609 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll->get_provider = dsi_pll_28nm_get_provider; pll 610 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll->destroy = dsi_pll_28nm_destroy; pll 611 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll->disable_seq = dsi_pll_28nm_disable_seq; pll 612 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll->save_state = dsi_pll_28nm_save_state; pll 613 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll->restore_state = dsi_pll_28nm_restore_state; pll 618 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll->en_seq_cnt = 3; pll 619 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll->enable_seqs[0] = dsi_pll_28nm_enable_seq_hpm; pll 620 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll->enable_seqs[1] = dsi_pll_28nm_enable_seq_hpm; pll 621 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll->enable_seqs[2] = dsi_pll_28nm_enable_seq_hpm; pll 625 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll->en_seq_cnt = 1; pll 626 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll->enable_seqs[0] = dsi_pll_28nm_enable_seq_lp; pll 638 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c return pll; pll 112 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct msm_dsi_pll *pll = hw_clk_to_pll(hw); pll 113 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 153 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct msm_dsi_pll *pll = hw_clk_to_pll(hw); pll 154 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 163 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct msm_dsi_pll *pll = hw_clk_to_pll(hw); pll 164 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 287 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c static int dsi_pll_28nm_enable_seq(struct msm_dsi_pll *pll) pll 289 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 329 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll) pll 331 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 337 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll) pll 339 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 350 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw); pll 353 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll) pll 355 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 360 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw, pll 378 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll, pll 382 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 393 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) pll 395 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); pll 488 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c struct msm_dsi_pll *pll; pll 507 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll = &pll_28nm->base; pll 508 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll->min_rate = VCO_MIN_RATE; pll 509 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll->max_rate = VCO_MAX_RATE; pll 510 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll->get_provider = dsi_pll_28nm_get_provider; pll 511 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll->destroy = dsi_pll_28nm_destroy; pll 512 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll->disable_seq = dsi_pll_28nm_disable_seq; pll 513 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll->save_state = dsi_pll_28nm_save_state; pll 514 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll->restore_state = dsi_pll_28nm_restore_state; pll 516 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll->en_seq_cnt = 1; pll 517 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c pll->enable_seqs[0] = dsi_pll_28nm_enable_seq; pll 525 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c return pll; pll 81 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll) pll 83 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c return platform_get_drvdata(pll->pdev); pll 86 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset, pll 89 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c msm_writel(data, pll->mmio_qserdes_com + offset); pll 92 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset) pll 94 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c return msm_readl(pll->mmio_qserdes_com + offset); pll 97 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel, pll 100 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c msm_writel(data, pll->mmio_qserdes_tx[channel] + offset); pll 398 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw); pll 399 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c struct hdmi_phy *phy = pll_get_phy(pll); pll 417 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BG_CTRL, 0x04); pll 420 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL, 0x20); pll 425 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_tx_chan_write(pll, i, pll 428 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_tx_chan_write(pll, i, pll 431 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_tx_chan_write(pll, i, pll 436 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_tx_chan_write(pll, 0, REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE, pll 438 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_tx_chan_write(pll, 2, REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE, pll 441 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1E); pll 442 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x07); pll 443 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL, 0x37); pll 444 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL, 0x02); pll 445 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1, 0x0E); pll 448 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL, pll 451 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BG_TRIM, 0x0F); pll 452 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_PLL_IVCO, 0x0F); pll 453 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL, pll 456 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BG_CTRL, 0x06); pll 458 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CLK_SELECT, 0x30); pll 459 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL, pll 461 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN, pll 464 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0, pll 466 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0, pll 468 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0, pll 470 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0, pll 472 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0, pll 474 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0, pll 476 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0, pll 479 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0, pll 481 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0, pll 484 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0, pll 486 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0, pll 488 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0, pll 491 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP, 0x00); pll 492 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN, pll 494 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV, pll 496 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG, 0x02); pll 498 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM, 0x15); pll 502 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_tx_chan_write(pll, i, pll 505 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_tx_chan_write(pll, i, pll 508 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_tx_chan_write(pll, i, pll 511 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_tx_chan_write(pll, i, pll 514 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_tx_chan_write(pll, i, pll 517 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_tx_chan_write(pll, i, pll 520 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_tx_chan_write(pll, i, pll 523 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_tx_chan_write(pll, i, pll 526 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_tx_chan_write(pll, i, pll 567 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c static int hdmi_8996_pll_lock_status(struct hdmi_pll_8996 *pll) pll 577 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c status = hdmi_pll_read(pll, pll 594 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw); pll 595 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c struct hdmi_phy *phy = pll_get_phy(pll); pll 604 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c ret = hdmi_8996_pll_lock_status(pll); pll 609 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_tx_chan_write(pll, i, pll 614 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_PER1, 0x0); pll 615 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_PER2, 0x0); pll 616 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1, 0x0); pll 617 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2, 0x0); pll 618 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER, 0x2); pll 647 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw); pll 651 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c cmp1 = hdmi_pll_read(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0); pll 652 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c cmp2 = hdmi_pll_read(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0); pll 653 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c cmp3 = hdmi_pll_read(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0); pll 666 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw); pll 667 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c struct hdmi_phy *phy = pll_get_phy(pll); pll 675 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw); pll 679 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c status = hdmi_pll_read(pll, REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS); pll 709 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c struct hdmi_pll_8996 *pll; pll 713 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); pll 714 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c if (!pll) pll 717 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c pll->pdev = pdev; pll 719 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c pll->mmio_qserdes_com = msm_ioremap(pdev, "hdmi_pll", "HDMI_PLL"); pll 720 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c if (IS_ERR(pll->mmio_qserdes_com)) { pll 731 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c pll->mmio_qserdes_tx[i] = msm_ioremap(pdev, name, label); pll 732 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c if (IS_ERR(pll->mmio_qserdes_tx[i])) { pll 737 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c pll->clk_hw.init = &pll_init; pll 739 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c clk = devm_clk_register(dev, &pll->clk_hw); pll 237 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c static inline void pll_write(struct hdmi_pll_8960 *pll, u32 reg, u32 data) pll 239 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c msm_writel(data, pll->mmio + reg); pll 242 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c static inline u32 pll_read(struct hdmi_pll_8960 *pll, u32 reg) pll 244 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c return msm_readl(pll->mmio + reg); pll 247 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8960 *pll) pll 249 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c return platform_get_drvdata(pll->pdev); pll 254 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw); pll 255 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c struct hdmi_phy *phy = pll_get_phy(pll); pll 262 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d); pll 263 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0, 0x10); pll 264 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1, 0x1a); pll 274 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d); pll 298 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val = pll_read(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B); pll 301 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B, val); pll 307 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val = pll_read(pll, REG_HDMI_8960_PHY_PLL_STATUS0); pll 321 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d); pll 323 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d); pll 339 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw); pll 340 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c struct hdmi_phy *phy = pll_get_phy(pll); pll 349 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c val = pll_read(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B); pll 352 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B, val); pll 371 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw); pll 373 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c return pll->pixclk; pll 387 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw); pll 394 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll_write(pll, pll_rate->conf[i].reg, pll_rate->conf[i].val); pll 396 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll->pixclk = rate; pll 424 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c struct hdmi_pll_8960 *pll; pll 433 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); pll 434 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c if (!pll) pll 437 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll->mmio = msm_ioremap(pdev, "hdmi_pll", "HDMI_PLL"); pll 438 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c if (IS_ERR(pll->mmio)) { pll 443 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll->pdev = pdev; pll 444 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c pll->clk_hw.init = &pll_init; pll 446 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c clk = devm_clk_register(dev, &pll->clk_hw); pll 264 drivers/gpu/drm/nouveau/dispnv04/hw.c enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0; pll 266 drivers/gpu/drm/nouveau/dispnv04/hw.c if (nvbios_pll_parse(bios, pll, &pll_lim)) pll 268 drivers/gpu/drm/nouveau/dispnv04/hw.c nouveau_hw_get_pllvals(dev, pll, &pv); pll 59 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c read_pll(struct gf100_clk *clk, u32 pll) pll 62 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c u32 ctrl = nvkm_rd32(device, pll + 0x00); pll 63 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c u32 coef = nvkm_rd32(device, pll + 0x04); pll 72 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c switch (pll) { pll 88 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); pll 60 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c read_pll(struct gk104_clk *clk, u32 pll) pll 63 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c u32 ctrl = nvkm_rd32(device, pll + 0x00); pll 64 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c u32 coef = nvkm_rd32(device, pll + 0x04); pll 74 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c switch (pll) { pll 86 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c fN = nvkm_rd32(device, pll + 0x10) >> 16; pll 92 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); pll 65 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll) pll 71 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); pll 72 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); pll 73 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); pll 77 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll) pll 82 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c val = (pll->m & MASK(GPCPLL_COEFF_M_WIDTH)) << GPCPLL_COEFF_M_SHIFT; pll 83 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c val |= (pll->n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; pll 84 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c val |= (pll->pl & MASK(GPCPLL_COEFF_P_WIDTH)) << GPCPLL_COEFF_P_SHIFT; pll 89 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_calc_rate(struct gk20a_clk *clk, struct gk20a_pll *pll) pll 94 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c rate = clk->parent_rate * pll->n; pll 95 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c divider = pll->m * clk->pl_to_div(pll->pl); pll 102 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct gk20a_pll *pll) pll 197 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c pll->m = best_m; pll 198 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c pll->n = best_n; pll 199 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c pll->pl = best_pl; pll 201 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c target_freq = gk20a_pllg_calc_rate(clk, pll); pll 205 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c target_freq / KHZ, pll->m, pll->n, pll->pl, pll 206 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c clk->pl_to_div(pll->pl)); pll 215 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct gk20a_pll pll; pll 219 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_read_mnp(clk, &pll); pll 221 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c if (n == pll.n) pll 230 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c pll.n = n; pll 232 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_write_mnp(clk, &pll); pll 296 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_program_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll) pll 316 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_write_mnp(clk, pll); pll 335 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_program_mnp_slide(struct gk20a_clk *clk, const struct gk20a_pll *pll) pll 344 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c if (pll->m == cur_pll.m && pll->pl == cur_pll.pl) pll 345 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c return gk20a_pllg_slide(clk, pll->n); pll 355 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c cur_pll = *pll; pll 362 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c return gk20a_pllg_slide(clk, pll->n); pll 465 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct gk20a_pll pll; pll 471 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_read_mnp(clk, &pll); pll 472 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c return gk20a_pllg_calc_rate(clk, &pll) / GK20A_CLK_GPC_MDIV; pll 485 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c GK20A_CLK_GPC_MDIV, &clk->pll); pll 494 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c ret = gk20a_pllg_program_mnp_slide(clk, &clk->pll); pll 496 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c ret = gk20a_pllg_program_mnp(clk, &clk->pll); pll 550 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c struct gk20a_pll pll; pll 553 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c gk20a_pllg_read_mnp(clk, &pll); pll 554 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c n_lo = gk20a_pllg_n_lo(clk, &pll); pll 119 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h struct gk20a_pll pll; pll 143 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h gk20a_pllg_n_lo(struct gk20a_clk *clk, struct gk20a_pll *pll) pll 145 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h return DIV_ROUND_UP(pll->m * clk->params->min_vco, pll 160 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gm20b_pllg_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll) pll 166 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gk20a_pllg_read_mnp(&clk->base, &pll->base); pll 168 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c pll->sdm_din = (val >> GPCPLL_CFG2_SDM_DIN_SHIFT) & pll 173 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gm20b_pllg_write_mnp(struct gm20b_clk *clk, const struct gm20b_pll *pll) pll 178 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c pll->sdm_din << GPCPLL_CFG2_SDM_DIN_SHIFT); pll 179 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gk20a_pllg_write_mnp(&clk->base, &pll->base); pll 270 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct gm20b_pll pll; pll 278 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gm20b_pllg_read_mnp(clk, &pll); pll 280 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c if (n_int == pll.base.n && sdm_din == pll.sdm_din) pll 292 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c pll.base.n = n_int; pll 294 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gk20a_pllg_write_mnp(&clk->base, &pll.base); pll 360 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gm20b_pllg_program_mnp(struct gm20b_clk *clk, const struct gk20a_pll *pll) pll 370 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gm20b_dvfs_calc_ndiv(clk, pll->n, &n_int, &sdm_din); pll 373 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c cur_pll.base.m == pll->m; pll 390 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c u32 new = pll->pl; pll 410 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c cur_pll.base = *pll; pll 433 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gm20b_pllg_program_mnp_slide(struct gm20b_clk *clk, const struct gk20a_pll *pll) pll 442 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c if (pll->m == cur_pll.m && pll->pl == cur_pll.pl) pll 443 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c return gm20b_pllg_slide(clk, pll->n); pll 453 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c cur_pll = *pll; pll 460 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c return gm20b_pllg_slide(clk, pll->n); pll 488 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gm20b_dvfs_calc_safe_pll(struct gm20b_clk *clk, struct gk20a_pll *pll) pll 490 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c u32 rate = gk20a_pllg_calc_rate(&clk->base, pll) / KHZ; pll 501 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c nmin = DIV_ROUND_UP(pll->m * clk->base.params->min_vco, parent_rate); pll 502 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c nsafe = pll->m * rate / (clk->base.parent_rate); pll 505 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c pll->pl = DIV_ROUND_UP(nmin * parent_rate, pll->m * rate); pll 509 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c pll->n = nsafe; pll 607 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c pll_safe = clk->base.pll; pll 632 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c clk->base.pll = clk->new_pll; pll 634 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c return gm20b_pllg_program_mnp_slide(clk, &clk->base.pll); pll 727 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c struct gk20a_pll pll; pll 730 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gk20a_pllg_read_mnp(&clk->base, &pll); pll 731 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c n_lo = gk20a_pllg_n_lo(&clk->base, &pll); pll 108 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c read_pll(struct gt215_clk *clk, int idx, u32 pll) pll 111 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c u32 ctrl = nvkm_rd32(device, pll + 0); pll 117 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c u32 coef = nvkm_rd32(device, pll + 4); pll 125 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c if ((pll & 0x00ff00) == 0x00e800) pll 235 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c gt215_pll_info(struct nvkm_clk *base, int idx, u32 pll, u32 khz, pll 244 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c info->pll = 0; pll 250 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c if (!pll || (diff >= -2000 && diff < 3000)) { pll 255 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c ret = nvbios_pll_parse(subdev->device->bios, pll, &limits); pll 265 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c info->pll = (P << 16) | (N << 8) | M; pll 275 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c int idx, u32 pll, int dom) pll 277 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c int ret = gt215_pll_info(&clk->base, idx, pll, cstate->domain[dom], pll 363 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c prog_pll(struct gt215_clk *clk, int idx, u32 pll, int dom) pll 369 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c const u32 ctrl = pll + 0; pll 370 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c const u32 coef = pll + 4; pll 373 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c if (info->pll) { pll 383 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c nvkm_wr32(device, coef, info->pll); pll 474 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c if (core->pll) { pll 498 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c if (core->pll) pll 8 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h u32 pll; pll 169 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c struct nvbios_pll pll; pll 172 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c ret = nvbios_pll_parse(subdev->device->bios, reg, &pll); pll 176 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c pll.vco2.max_freq = 0; pll 177 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c pll.refclk = nvkm_clk_read(&clk->base, nv_clk_src_href); pll 178 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c if (!pll.refclk) pll 181 drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c return nv04_pll_calc(subdev, &pll, clock, N, M, NULL, NULL, P); pll 128 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c struct nvbios_pll pll; pll 131 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c ret = nvbios_pll_parse(subdev->device->bios, reg, &pll); pll 135 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c if (khz < pll.vco1.max_freq) pll 136 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c pll.vco2.max_freq = 0; pll 138 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P); pll 328 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c struct nvbios_pll pll; pll 331 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c ret = nvbios_pll_parse(subdev->device->bios, reg, &pll); pll 335 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c pll.vco2.max_freq = 0; pll 336 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c pll.refclk = read_pll_ref(clk, reg); pll 337 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c if (!pll.refclk) pll 340 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c return nv04_pll_calc(subdev, &pll, idx, N, M, NULL, NULL, P); pll 150 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; pll 154 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c if (oldpll == pll) pll 178 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c nvkm_wr32(device, reg, pll); pll 458 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c ram_wr32(fuc, 0x004004, mclk->pll); pll 602 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c pll2pll = (!(ctrl & 0x00000008)) && mclk.pll; pll 615 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c if (mclk.pll && !pll2pll) { pll 694 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c if (mclk.pll) { pll 737 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c if (mclk.pll) { pll 870 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c if (mclk.pll) { pll 39 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c struct nvbios_pll pll; pll 43 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c ret = nvbios_pll_parse(bios, 0x04, &pll); pll 49 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P); pll 54 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20; pll 3294 drivers/gpu/drm/omapdrm/dss/dispc.c struct dss_pll *pll; pll 3297 drivers/gpu/drm/omapdrm/dss/dispc.c pll = dss_pll_find_by_src(dispc->dss, src); pll 3300 drivers/gpu/drm/omapdrm/dss/dispc.c r = pll->cinfo.clkout[clkout_idx]; pll 3322 drivers/gpu/drm/omapdrm/dss/dispc.c struct dss_pll *pll; pll 3325 drivers/gpu/drm/omapdrm/dss/dispc.c pll = dss_pll_find_by_src(dispc->dss, src); pll 3328 drivers/gpu/drm/omapdrm/dss/dispc.c r = pll->cinfo.clkout[clkout_idx]; pll 35 drivers/gpu/drm/omapdrm/dss/dpi.c struct dss_pll *pll; pll 201 drivers/gpu/drm/omapdrm/dss/dpi.c return dss_pll_hsdiv_calc_a(ctx->dpi->pll, clkdco, pll 226 drivers/gpu/drm/omapdrm/dss/dpi.c clkin = clk_get_rate(dpi->pll->clkin); pll 228 drivers/gpu/drm/omapdrm/dss/dpi.c if (dpi->pll->hw->type == DSS_PLL_TYPE_A) { pll 237 drivers/gpu/drm/omapdrm/dss/dpi.c return dss_pll_calc_a(ctx->dpi->pll, clkin, pll 241 drivers/gpu/drm/omapdrm/dss/dpi.c dss_pll_calc_b(dpi->pll, clkin, pck, &ctx->pll_cinfo); pll 298 drivers/gpu/drm/omapdrm/dss/dpi.c r = dss_pll_set_config(dpi->pll, &ctx.pll_cinfo); pll 343 drivers/gpu/drm/omapdrm/dss/dpi.c if (dpi->pll) pll 391 drivers/gpu/drm/omapdrm/dss/dpi.c if (dpi->pll) { pll 392 drivers/gpu/drm/omapdrm/dss/dpi.c r = dss_pll_enable(dpi->pll); pll 415 drivers/gpu/drm/omapdrm/dss/dpi.c if (dpi->pll) pll 416 drivers/gpu/drm/omapdrm/dss/dpi.c dss_pll_disable(dpi->pll); pll 435 drivers/gpu/drm/omapdrm/dss/dpi.c if (dpi->pll) { pll 438 drivers/gpu/drm/omapdrm/dss/dpi.c dss_pll_disable(dpi->pll); pll 479 drivers/gpu/drm/omapdrm/dss/dpi.c if (dpi->pll) { pll 503 drivers/gpu/drm/omapdrm/dss/dpi.c static int dpi_verify_pll(struct dss_pll *pll) pll 509 drivers/gpu/drm/omapdrm/dss/dpi.c r = dss_pll_enable(pll); pll 513 drivers/gpu/drm/omapdrm/dss/dpi.c dss_pll_disable(pll); pll 520 drivers/gpu/drm/omapdrm/dss/dpi.c struct dss_pll *pll; pll 522 drivers/gpu/drm/omapdrm/dss/dpi.c if (dpi->pll) pll 527 drivers/gpu/drm/omapdrm/dss/dpi.c pll = dss_pll_find_by_src(dpi->dss, dpi->clk_src); pll 528 drivers/gpu/drm/omapdrm/dss/dpi.c if (!pll) pll 531 drivers/gpu/drm/omapdrm/dss/dpi.c if (dpi_verify_pll(pll)) { pll 536 drivers/gpu/drm/omapdrm/dss/dpi.c dpi->pll = pll; pll 274 drivers/gpu/drm/omapdrm/dss/dsi.c struct dss_pll *pll; pll 342 drivers/gpu/drm/omapdrm/dss/dsi.c struct dss_pll pll; pll 1182 drivers/gpu/drm/omapdrm/dss/dsi.c return dsi->pll.cinfo.clkout[HSDIV_DISPC]; pll 1187 drivers/gpu/drm/omapdrm/dss/dsi.c return dsi->pll.cinfo.clkout[HSDIV_DSI]; pll 1192 drivers/gpu/drm/omapdrm/dss/dsi.c return dsi->pll.cinfo.clkdco / 16; pll 1318 drivers/gpu/drm/omapdrm/dss/dsi.c static int dsi_pll_enable(struct dss_pll *pll) pll 1320 drivers/gpu/drm/omapdrm/dss/dsi.c struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); pll 1368 drivers/gpu/drm/omapdrm/dss/dsi.c static void dsi_pll_disable(struct dss_pll *pll) pll 1370 drivers/gpu/drm/omapdrm/dss/dsi.c struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); pll 1385 drivers/gpu/drm/omapdrm/dss/dsi.c struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; pll 1388 drivers/gpu/drm/omapdrm/dss/dsi.c struct dss_pll *pll = &dsi->pll; pll 1398 drivers/gpu/drm/omapdrm/dss/dsi.c seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin)); pll 1731 drivers/gpu/drm/omapdrm/dss/dsi.c unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; pll 1738 drivers/gpu/drm/omapdrm/dss/dsi.c unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; pll 4052 drivers/gpu/drm/omapdrm/dss/dsi.c r = dss_pll_set_config(&dsi->pll, &cinfo); pll 4065 drivers/gpu/drm/omapdrm/dss/dsi.c r = dss_pll_enable(&dsi->pll); pll 4120 drivers/gpu/drm/omapdrm/dss/dsi.c dss_pll_disable(&dsi->pll); pll 4140 drivers/gpu/drm/omapdrm/dss/dsi.c dss_pll_disable(&dsi->pll); pll 4342 drivers/gpu/drm/omapdrm/dss/dsi.c return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, pll 4356 drivers/gpu/drm/omapdrm/dss/dsi.c clkin = clk_get_rate(dsi->pll.clkin); pll 4372 drivers/gpu/drm/omapdrm/dss/dsi.c ctx->pll = &dsi->pll; pll 4381 drivers/gpu/drm/omapdrm/dss/dsi.c return dss_pll_calc_a(ctx->pll, clkin, pll 4643 drivers/gpu/drm/omapdrm/dss/dsi.c return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, pll 4660 drivers/gpu/drm/omapdrm/dss/dsi.c clkin = clk_get_rate(dsi->pll.clkin); pll 4664 drivers/gpu/drm/omapdrm/dss/dsi.c ctx->pll = &dsi->pll; pll 4685 drivers/gpu/drm/omapdrm/dss/dsi.c return dss_pll_calc_a(ctx->pll, clkin, pll 5017 drivers/gpu/drm/omapdrm/dss/dsi.c struct dss_pll *pll = &dsi->pll; pll 5027 drivers/gpu/drm/omapdrm/dss/dsi.c pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1"; pll 5028 drivers/gpu/drm/omapdrm/dss/dsi.c pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2; pll 5029 drivers/gpu/drm/omapdrm/dss/dsi.c pll->clkin = clk; pll 5030 drivers/gpu/drm/omapdrm/dss/dsi.c pll->base = dsi->pll_base; pll 5031 drivers/gpu/drm/omapdrm/dss/dsi.c pll->hw = dsi->data->pll_hw; pll 5032 drivers/gpu/drm/omapdrm/dss/dsi.c pll->ops = &dsi_pll_ops; pll 5034 drivers/gpu/drm/omapdrm/dss/dsi.c r = dss_pll_register(dss, pll); pll 5094 drivers/gpu/drm/omapdrm/dss/dsi.c dss_pll_unregister(&dsi->pll); pll 146 drivers/gpu/drm/omapdrm/dss/dss.c void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable) pll 151 drivers/gpu/drm/omapdrm/dss/dss.c if (!pll->dss->syscon_pll_ctrl) pll 156 drivers/gpu/drm/omapdrm/dss/dss.c switch (pll->id) { pll 167 drivers/gpu/drm/omapdrm/dss/dss.c DSSERR("illegal DSS PLL ID %d\n", pll->id); pll 171 drivers/gpu/drm/omapdrm/dss/dss.c regmap_update_bits(pll->dss->syscon_pll_ctrl, pll 172 drivers/gpu/drm/omapdrm/dss/dss.c pll->dss->syscon_pll_ctrl_offset, pll 144 drivers/gpu/drm/omapdrm/dss/dss.h int (*enable)(struct dss_pll *pll); pll 145 drivers/gpu/drm/omapdrm/dss/dss.h void (*disable)(struct dss_pll *pll); pll 146 drivers/gpu/drm/omapdrm/dss/dss.h int (*set_config)(struct dss_pll *pll, pll 319 drivers/gpu/drm/omapdrm/dss/dss.h void dss_video_pll_uninit(struct dss_pll *pll); pll 321 drivers/gpu/drm/omapdrm/dss/dss.h void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable); pll 446 drivers/gpu/drm/omapdrm/dss/dss.h int dss_pll_register(struct dss_device *dss, struct dss_pll *pll); pll 447 drivers/gpu/drm/omapdrm/dss/dss.h void dss_pll_unregister(struct dss_pll *pll); pll 452 drivers/gpu/drm/omapdrm/dss/dss.h int dss_pll_enable(struct dss_pll *pll); pll 453 drivers/gpu/drm/omapdrm/dss/dss.h void dss_pll_disable(struct dss_pll *pll); pll 454 drivers/gpu/drm/omapdrm/dss/dss.h int dss_pll_set_config(struct dss_pll *pll, pll 457 drivers/gpu/drm/omapdrm/dss/dss.h bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco, pll 460 drivers/gpu/drm/omapdrm/dss/dss.h bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin, pll 464 drivers/gpu/drm/omapdrm/dss/dss.h bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin, pll 467 drivers/gpu/drm/omapdrm/dss/dss.h int dss_pll_write_config_type_a(struct dss_pll *pll, pll 469 drivers/gpu/drm/omapdrm/dss/dss.h int dss_pll_write_config_type_b(struct dss_pll *pll, pll 471 drivers/gpu/drm/omapdrm/dss/dss.h int dss_pll_wait_reset_done(struct dss_pll *pll); pll 233 drivers/gpu/drm/omapdrm/dss/hdmi.h struct dss_pll pll; pll 317 drivers/gpu/drm/omapdrm/dss/hdmi.h void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s); pll 319 drivers/gpu/drm/omapdrm/dss/hdmi.h struct hdmi_pll_data *pll, struct hdmi_wp_data *wp); pll 356 drivers/gpu/drm/omapdrm/dss/hdmi.h struct hdmi_pll_data pll; pll 171 drivers/gpu/drm/omapdrm/dss/hdmi4.c dss_pll_calc_b(&hdmi->pll.pll, clk_get_rate(hdmi->pll.pll.clkin), pll 174 drivers/gpu/drm/omapdrm/dss/hdmi4.c r = dss_pll_enable(&hdmi->pll.pll); pll 180 drivers/gpu/drm/omapdrm/dss/hdmi4.c r = dss_pll_set_config(&hdmi->pll.pll, &hdmi_cinfo); pll 219 drivers/gpu/drm/omapdrm/dss/hdmi4.c dss_pll_disable(&hdmi->pll.pll); pll 235 drivers/gpu/drm/omapdrm/dss/hdmi4.c dss_pll_disable(&hdmi->pll.pll); pll 266 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_pll_dump(&hdmi->pll, s); pll 612 drivers/gpu/drm/omapdrm/dss/hdmi4.c r = hdmi_pll_init(dss, hdmi->pdev, &hdmi->pll, &hdmi->wp); pll 636 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_pll_uninit(&hdmi->pll); pll 652 drivers/gpu/drm/omapdrm/dss/hdmi4.c hdmi_pll_uninit(&hdmi->pll); pll 165 drivers/gpu/drm/omapdrm/dss/hdmi5.c dss_pll_calc_b(&hdmi->pll.pll, clk_get_rate(hdmi->pll.pll.clkin), pll 173 drivers/gpu/drm/omapdrm/dss/hdmi5.c r = dss_pll_enable(&hdmi->pll.pll); pll 179 drivers/gpu/drm/omapdrm/dss/hdmi5.c r = dss_pll_set_config(&hdmi->pll.pll, &hdmi_cinfo); pll 218 drivers/gpu/drm/omapdrm/dss/hdmi5.c dss_pll_disable(&hdmi->pll.pll); pll 234 drivers/gpu/drm/omapdrm/dss/hdmi5.c dss_pll_disable(&hdmi->pll.pll); pll 265 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_pll_dump(&hdmi->pll, s); pll 607 drivers/gpu/drm/omapdrm/dss/hdmi5.c r = hdmi_pll_init(dss, hdmi->pdev, &hdmi->pll, &hdmi->wp); pll 623 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_pll_uninit(&hdmi->pll); pll 636 drivers/gpu/drm/omapdrm/dss/hdmi5.c hdmi_pll_uninit(&hdmi->pll); pll 23 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s) pll 26 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c hdmi_read_reg(pll->base, r)) pll 41 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); pll 42 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c struct hdmi_wp_data *wp = pll->wp; pll 45 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c r = pm_runtime_get_sync(&pll->pdev->dev); pll 59 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); pll 60 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c struct hdmi_wp_data *wp = pll->wp; pll 67 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c r = pm_runtime_put_sync(&pll->pdev->dev); pll 132 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c struct dss_pll *pll = &hpll->pll; pll 142 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c pll->name = "hdmi"; pll 143 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c pll->id = DSS_PLL_HDMI; pll 144 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c pll->base = hpll->base; pll 145 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c pll->clkin = clk; pll 148 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c pll->hw = &dss_omap4_hdmi_pll_hw; pll 150 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c pll->hw = &dss_omap5_hdmi_pll_hw; pll 152 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c pll->ops = &hdmi_pll_ops; pll 154 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c r = dss_pll_register(dss, pll); pll 162 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c struct hdmi_pll_data *pll, struct hdmi_wp_data *wp) pll 167 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c pll->pdev = pdev; pll 168 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c pll->wp = wp; pll 171 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c pll->base = devm_ioremap_resource(&pdev->dev, res); pll 172 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c if (IS_ERR(pll->base)) pll 173 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c return PTR_ERR(pll->base); pll 175 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c r = hdmi_init_pll_data(dss, pdev, pll); pll 186 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c struct dss_pll *pll = &hpll->pll; pll 188 drivers/gpu/drm/omapdrm/dss/hdmi_pll.c dss_pll_unregister(pll); pll 28 drivers/gpu/drm/omapdrm/dss/pll.c int dss_pll_register(struct dss_device *dss, struct dss_pll *pll) pll 34 drivers/gpu/drm/omapdrm/dss/pll.c dss->plls[i] = pll; pll 35 drivers/gpu/drm/omapdrm/dss/pll.c pll->dss = dss; pll 43 drivers/gpu/drm/omapdrm/dss/pll.c void dss_pll_unregister(struct dss_pll *pll) pll 45 drivers/gpu/drm/omapdrm/dss/pll.c struct dss_device *dss = pll->dss; pll 49 drivers/gpu/drm/omapdrm/dss/pll.c if (dss->plls[i] == pll) { pll 51 drivers/gpu/drm/omapdrm/dss/pll.c pll->dss = NULL; pll 72 drivers/gpu/drm/omapdrm/dss/pll.c struct dss_pll *pll; pll 85 drivers/gpu/drm/omapdrm/dss/pll.c pll = dss_pll_find(dss, "dsi0"); pll 86 drivers/gpu/drm/omapdrm/dss/pll.c if (!pll) pll 87 drivers/gpu/drm/omapdrm/dss/pll.c pll = dss_pll_find(dss, "video0"); pll 88 drivers/gpu/drm/omapdrm/dss/pll.c return pll; pll 93 drivers/gpu/drm/omapdrm/dss/pll.c pll = dss_pll_find(dss, "dsi1"); pll 94 drivers/gpu/drm/omapdrm/dss/pll.c if (!pll) pll 95 drivers/gpu/drm/omapdrm/dss/pll.c pll = dss_pll_find(dss, "video1"); pll 96 drivers/gpu/drm/omapdrm/dss/pll.c return pll; pll 123 drivers/gpu/drm/omapdrm/dss/pll.c int dss_pll_enable(struct dss_pll *pll) pll 127 drivers/gpu/drm/omapdrm/dss/pll.c r = clk_prepare_enable(pll->clkin); pll 131 drivers/gpu/drm/omapdrm/dss/pll.c if (pll->regulator) { pll 132 drivers/gpu/drm/omapdrm/dss/pll.c r = regulator_enable(pll->regulator); pll 137 drivers/gpu/drm/omapdrm/dss/pll.c r = pll->ops->enable(pll); pll 144 drivers/gpu/drm/omapdrm/dss/pll.c if (pll->regulator) pll 145 drivers/gpu/drm/omapdrm/dss/pll.c regulator_disable(pll->regulator); pll 147 drivers/gpu/drm/omapdrm/dss/pll.c clk_disable_unprepare(pll->clkin); pll 151 drivers/gpu/drm/omapdrm/dss/pll.c void dss_pll_disable(struct dss_pll *pll) pll 153 drivers/gpu/drm/omapdrm/dss/pll.c pll->ops->disable(pll); pll 155 drivers/gpu/drm/omapdrm/dss/pll.c if (pll->regulator) pll 156 drivers/gpu/drm/omapdrm/dss/pll.c regulator_disable(pll->regulator); pll 158 drivers/gpu/drm/omapdrm/dss/pll.c clk_disable_unprepare(pll->clkin); pll 160 drivers/gpu/drm/omapdrm/dss/pll.c memset(&pll->cinfo, 0, sizeof(pll->cinfo)); pll 163 drivers/gpu/drm/omapdrm/dss/pll.c int dss_pll_set_config(struct dss_pll *pll, const struct dss_pll_clock_info *cinfo) pll 167 drivers/gpu/drm/omapdrm/dss/pll.c r = pll->ops->set_config(pll, cinfo); pll 171 drivers/gpu/drm/omapdrm/dss/pll.c pll->cinfo = *cinfo; pll 176 drivers/gpu/drm/omapdrm/dss/pll.c bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco, pll 180 drivers/gpu/drm/omapdrm/dss/pll.c const struct dss_pll_hw *hw = pll->hw; pll 205 drivers/gpu/drm/omapdrm/dss/pll.c bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin, pll 209 drivers/gpu/drm/omapdrm/dss/pll.c const struct dss_pll_hw *hw = pll->hw; pll 266 drivers/gpu/drm/omapdrm/dss/pll.c bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin, pll 273 drivers/gpu/drm/omapdrm/dss/pll.c const struct dss_pll_hw *hw = pll->hw; pll 350 drivers/gpu/drm/omapdrm/dss/pll.c int dss_pll_wait_reset_done(struct dss_pll *pll) pll 352 drivers/gpu/drm/omapdrm/dss/pll.c void __iomem *base = pll->base; pll 360 drivers/gpu/drm/omapdrm/dss/pll.c static int dss_wait_hsdiv_ack(struct dss_pll *pll, u32 hsdiv_ack_mask) pll 365 drivers/gpu/drm/omapdrm/dss/pll.c u32 v = readl_relaxed(pll->base + PLL_STATUS); pll 390 drivers/gpu/drm/omapdrm/dss/pll.c int dss_pll_write_config_type_a(struct dss_pll *pll, pll 393 drivers/gpu/drm/omapdrm/dss/pll.c const struct dss_pll_hw *hw = pll->hw; pll 394 drivers/gpu/drm/omapdrm/dss/pll.c void __iomem *base = pll->base; pll 504 drivers/gpu/drm/omapdrm/dss/pll.c r = dss_wait_hsdiv_ack(pll, pll 518 drivers/gpu/drm/omapdrm/dss/pll.c int dss_pll_write_config_type_b(struct dss_pll *pll, pll 521 drivers/gpu/drm/omapdrm/dss/pll.c const struct dss_pll_hw *hw = pll->hw; pll 522 drivers/gpu/drm/omapdrm/dss/pll.c void __iomem *base = pll->base; pll 18 drivers/gpu/drm/omapdrm/dss/video-pll.c struct dss_pll pll; pll 54 drivers/gpu/drm/omapdrm/dss/video-pll.c static int dss_video_pll_enable(struct dss_pll *pll) pll 56 drivers/gpu/drm/omapdrm/dss/video-pll.c struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); pll 59 drivers/gpu/drm/omapdrm/dss/video-pll.c r = dss_runtime_get(pll->dss); pll 63 drivers/gpu/drm/omapdrm/dss/video-pll.c dss_ctrl_pll_enable(pll, true); pll 67 drivers/gpu/drm/omapdrm/dss/video-pll.c r = dss_pll_wait_reset_done(pll); pll 77 drivers/gpu/drm/omapdrm/dss/video-pll.c dss_ctrl_pll_enable(pll, false); pll 78 drivers/gpu/drm/omapdrm/dss/video-pll.c dss_runtime_put(pll->dss); pll 83 drivers/gpu/drm/omapdrm/dss/video-pll.c static void dss_video_pll_disable(struct dss_pll *pll) pll 85 drivers/gpu/drm/omapdrm/dss/video-pll.c struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); pll 91 drivers/gpu/drm/omapdrm/dss/video-pll.c dss_ctrl_pll_enable(pll, false); pll 93 drivers/gpu/drm/omapdrm/dss/video-pll.c dss_runtime_put(pll->dss); pll 144 drivers/gpu/drm/omapdrm/dss/video-pll.c struct dss_pll *pll; pll 177 drivers/gpu/drm/omapdrm/dss/video-pll.c pll = &vpll->pll; pll 179 drivers/gpu/drm/omapdrm/dss/video-pll.c pll->name = id == 0 ? "video0" : "video1"; pll 180 drivers/gpu/drm/omapdrm/dss/video-pll.c pll->id = id == 0 ? DSS_PLL_VIDEO1 : DSS_PLL_VIDEO2; pll 181 drivers/gpu/drm/omapdrm/dss/video-pll.c pll->clkin = clk; pll 182 drivers/gpu/drm/omapdrm/dss/video-pll.c pll->regulator = regulator; pll 183 drivers/gpu/drm/omapdrm/dss/video-pll.c pll->base = pll_base; pll 184 drivers/gpu/drm/omapdrm/dss/video-pll.c pll->hw = &dss_dra7_video_pll_hw; pll 185 drivers/gpu/drm/omapdrm/dss/video-pll.c pll->ops = &dss_pll_ops; pll 187 drivers/gpu/drm/omapdrm/dss/video-pll.c r = dss_pll_register(dss, pll); pll 191 drivers/gpu/drm/omapdrm/dss/video-pll.c return pll; pll 194 drivers/gpu/drm/omapdrm/dss/video-pll.c void dss_video_pll_uninit(struct dss_pll *pll) pll 196 drivers/gpu/drm/omapdrm/dss/video-pll.c dss_pll_unregister(pll); pll 1073 drivers/gpu/drm/radeon/atombios_crtc.c struct radeon_pll *pll; pll 1084 drivers/gpu/drm/radeon/atombios_crtc.c pll = &rdev->clock.p1pll; pll 1087 drivers/gpu/drm/radeon/atombios_crtc.c pll = &rdev->clock.p2pll; pll 1092 drivers/gpu/drm/radeon/atombios_crtc.c pll = &rdev->clock.dcpll; pll 1097 drivers/gpu/drm/radeon/atombios_crtc.c pll->flags = radeon_crtc->pll_flags; pll 1098 drivers/gpu/drm/radeon/atombios_crtc.c pll->reference_div = radeon_crtc->pll_reference_div; pll 1099 drivers/gpu/drm/radeon/atombios_crtc.c pll->post_div = radeon_crtc->pll_post_div; pll 1103 drivers/gpu/drm/radeon/atombios_crtc.c radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, pll 1106 drivers/gpu/drm/radeon/atombios_crtc.c radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, pll 1109 drivers/gpu/drm/radeon/atombios_crtc.c radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, pll 1132 drivers/gpu/drm/radeon/atombios_crtc.c (125 * 25 * pll->reference_freq / 100); pll 1135 drivers/gpu/drm/radeon/atombios_crtc.c (125 * 25 * pll->reference_freq / 100); pll 1883 drivers/gpu/drm/radeon/atombios_crtc.c int pll; pll 1892 drivers/gpu/drm/radeon/atombios_crtc.c pll = radeon_get_shared_dp_ppll(crtc); pll 1893 drivers/gpu/drm/radeon/atombios_crtc.c if (pll != ATOM_PPLL_INVALID) pll 1894 drivers/gpu/drm/radeon/atombios_crtc.c return pll; pll 1898 drivers/gpu/drm/radeon/atombios_crtc.c pll = radeon_get_shared_nondp_ppll(crtc); pll 1899 drivers/gpu/drm/radeon/atombios_crtc.c if (pll != ATOM_PPLL_INVALID) pll 1900 drivers/gpu/drm/radeon/atombios_crtc.c return pll; pll 1940 drivers/gpu/drm/radeon/atombios_crtc.c pll = radeon_get_shared_dp_ppll(crtc); pll 1941 drivers/gpu/drm/radeon/atombios_crtc.c if (pll != ATOM_PPLL_INVALID) pll 1942 drivers/gpu/drm/radeon/atombios_crtc.c return pll; pll 1946 drivers/gpu/drm/radeon/atombios_crtc.c pll = radeon_get_shared_nondp_ppll(crtc); pll 1947 drivers/gpu/drm/radeon/atombios_crtc.c if (pll != ATOM_PPLL_INVALID) pll 1948 drivers/gpu/drm/radeon/atombios_crtc.c return pll; pll 1995 drivers/gpu/drm/radeon/atombios_crtc.c pll = radeon_get_shared_dp_ppll(crtc); pll 1996 drivers/gpu/drm/radeon/atombios_crtc.c if (pll != ATOM_PPLL_INVALID) pll 1997 drivers/gpu/drm/radeon/atombios_crtc.c return pll; pll 2001 drivers/gpu/drm/radeon/atombios_crtc.c pll = radeon_get_shared_nondp_ppll(crtc); pll 2002 drivers/gpu/drm/radeon/atombios_crtc.c if (pll != ATOM_PPLL_INVALID) pll 2003 drivers/gpu/drm/radeon/atombios_crtc.c return pll; pll 955 drivers/gpu/drm/radeon/radeon_display.c void radeon_compute_pll_avivo(struct radeon_pll *pll, pll 963 drivers/gpu/drm/radeon/radeon_display.c unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? pll 973 drivers/gpu/drm/radeon/radeon_display.c fb_div_min = pll->min_feedback_div; pll 974 drivers/gpu/drm/radeon/radeon_display.c fb_div_max = pll->max_feedback_div; pll 976 drivers/gpu/drm/radeon/radeon_display.c if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { pll 982 drivers/gpu/drm/radeon/radeon_display.c if (pll->flags & RADEON_PLL_USE_REF_DIV) pll 983 drivers/gpu/drm/radeon/radeon_display.c ref_div_min = pll->reference_div; pll 985 drivers/gpu/drm/radeon/radeon_display.c ref_div_min = pll->min_ref_div; pll 987 drivers/gpu/drm/radeon/radeon_display.c if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && pll 988 drivers/gpu/drm/radeon/radeon_display.c pll->flags & RADEON_PLL_USE_REF_DIV) pll 989 drivers/gpu/drm/radeon/radeon_display.c ref_div_max = pll->reference_div; pll 990 drivers/gpu/drm/radeon/radeon_display.c else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) pll 992 drivers/gpu/drm/radeon/radeon_display.c ref_div_max = min(pll->max_ref_div, 7u); pll 994 drivers/gpu/drm/radeon/radeon_display.c ref_div_max = pll->max_ref_div; pll 997 drivers/gpu/drm/radeon/radeon_display.c if (pll->flags & RADEON_PLL_USE_POST_DIV) { pll 998 drivers/gpu/drm/radeon/radeon_display.c post_div_min = pll->post_div; pll 999 drivers/gpu/drm/radeon/radeon_display.c post_div_max = pll->post_div; pll 1003 drivers/gpu/drm/radeon/radeon_display.c if (pll->flags & RADEON_PLL_IS_LCD) { pll 1004 drivers/gpu/drm/radeon/radeon_display.c vco_min = pll->lcd_pll_out_min; pll 1005 drivers/gpu/drm/radeon/radeon_display.c vco_max = pll->lcd_pll_out_max; pll 1007 drivers/gpu/drm/radeon/radeon_display.c vco_min = pll->pll_out_min; pll 1008 drivers/gpu/drm/radeon/radeon_display.c vco_max = pll->pll_out_max; pll 1011 drivers/gpu/drm/radeon/radeon_display.c if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { pll 1019 drivers/gpu/drm/radeon/radeon_display.c if (post_div_min < pll->min_post_div) pll 1020 drivers/gpu/drm/radeon/radeon_display.c post_div_min = pll->min_post_div; pll 1025 drivers/gpu/drm/radeon/radeon_display.c if (post_div_max > pll->max_post_div) pll 1026 drivers/gpu/drm/radeon/radeon_display.c post_div_max = pll->max_post_div; pll 1031 drivers/gpu/drm/radeon/radeon_display.c den = pll->reference_freq; pll 1037 drivers/gpu/drm/radeon/radeon_display.c if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) pll 1047 drivers/gpu/drm/radeon/radeon_display.c diff = abs(target_clock - (pll->reference_freq * fb_div) / pll 1051 drivers/gpu/drm/radeon/radeon_display.c !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { pll 1068 drivers/gpu/drm/radeon/radeon_display.c if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { pll 1078 drivers/gpu/drm/radeon/radeon_display.c if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { pll 1086 drivers/gpu/drm/radeon/radeon_display.c *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + pll 1087 drivers/gpu/drm/radeon/radeon_display.c (pll->reference_freq * *frac_fb_div_p)) / pll 1108 drivers/gpu/drm/radeon/radeon_display.c void radeon_compute_pll_legacy(struct radeon_pll *pll, pll 1116 drivers/gpu/drm/radeon/radeon_display.c uint32_t min_ref_div = pll->min_ref_div; pll 1117 drivers/gpu/drm/radeon/radeon_display.c uint32_t max_ref_div = pll->max_ref_div; pll 1118 drivers/gpu/drm/radeon/radeon_display.c uint32_t min_post_div = pll->min_post_div; pll 1119 drivers/gpu/drm/radeon/radeon_display.c uint32_t max_post_div = pll->max_post_div; pll 1122 drivers/gpu/drm/radeon/radeon_display.c uint32_t best_vco = pll->best_vco; pll 1133 drivers/gpu/drm/radeon/radeon_display.c DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); pll 1136 drivers/gpu/drm/radeon/radeon_display.c if (pll->flags & RADEON_PLL_IS_LCD) { pll 1137 drivers/gpu/drm/radeon/radeon_display.c pll_out_min = pll->lcd_pll_out_min; pll 1138 drivers/gpu/drm/radeon/radeon_display.c pll_out_max = pll->lcd_pll_out_max; pll 1140 drivers/gpu/drm/radeon/radeon_display.c pll_out_min = pll->pll_out_min; pll 1141 drivers/gpu/drm/radeon/radeon_display.c pll_out_max = pll->pll_out_max; pll 1147 drivers/gpu/drm/radeon/radeon_display.c if (pll->flags & RADEON_PLL_USE_REF_DIV) pll 1148 drivers/gpu/drm/radeon/radeon_display.c min_ref_div = max_ref_div = pll->reference_div; pll 1152 drivers/gpu/drm/radeon/radeon_display.c uint32_t pll_in = pll->reference_freq / mid; pll 1153 drivers/gpu/drm/radeon/radeon_display.c if (pll_in < pll->pll_in_min) pll 1155 drivers/gpu/drm/radeon/radeon_display.c else if (pll_in > pll->pll_in_max) pll 1162 drivers/gpu/drm/radeon/radeon_display.c if (pll->flags & RADEON_PLL_USE_POST_DIV) pll 1163 drivers/gpu/drm/radeon/radeon_display.c min_post_div = max_post_div = pll->post_div; pll 1165 drivers/gpu/drm/radeon/radeon_display.c if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { pll 1166 drivers/gpu/drm/radeon/radeon_display.c min_fractional_feed_div = pll->min_frac_feedback_div; pll 1167 drivers/gpu/drm/radeon/radeon_display.c max_fractional_feed_div = pll->max_frac_feedback_div; pll 1173 drivers/gpu/drm/radeon/radeon_display.c if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) pll 1177 drivers/gpu/drm/radeon/radeon_display.c if (pll->flags & RADEON_PLL_LEGACY) { pll 1191 drivers/gpu/drm/radeon/radeon_display.c uint32_t pll_in = pll->reference_freq / ref_div; pll 1192 drivers/gpu/drm/radeon/radeon_display.c uint32_t min_feed_div = pll->min_feedback_div; pll 1193 drivers/gpu/drm/radeon/radeon_display.c uint32_t max_feed_div = pll->max_feedback_div + 1; pll 1195 drivers/gpu/drm/radeon/radeon_display.c if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) pll 1207 drivers/gpu/drm/radeon/radeon_display.c tmp = (uint64_t)pll->reference_freq * feedback_div; pll 1220 drivers/gpu/drm/radeon/radeon_display.c tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; pll 1221 drivers/gpu/drm/radeon/radeon_display.c tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; pll 1224 drivers/gpu/drm/radeon/radeon_display.c if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { pll 1253 drivers/gpu/drm/radeon/radeon_display.c } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || pll 1254 drivers/gpu/drm/radeon/radeon_display.c ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || pll 1255 drivers/gpu/drm/radeon/radeon_display.c ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || pll 1256 drivers/gpu/drm/radeon/radeon_display.c ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || pll 1257 drivers/gpu/drm/radeon/radeon_display.c ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || pll 1258 drivers/gpu/drm/radeon/radeon_display.c ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { pll 751 drivers/gpu/drm/radeon/radeon_legacy_crtc.c struct radeon_pll *pll; pll 774 drivers/gpu/drm/radeon/radeon_legacy_crtc.c pll = &rdev->clock.p2pll; pll 776 drivers/gpu/drm/radeon/radeon_legacy_crtc.c pll = &rdev->clock.p1pll; pll 778 drivers/gpu/drm/radeon/radeon_legacy_crtc.c pll->flags = RADEON_PLL_LEGACY; pll 781 drivers/gpu/drm/radeon/radeon_legacy_crtc.c pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; pll 783 drivers/gpu/drm/radeon/radeon_legacy_crtc.c pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; pll 795 drivers/gpu/drm/radeon/radeon_legacy_crtc.c pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; pll 810 drivers/gpu/drm/radeon/radeon_legacy_crtc.c pll->flags |= RADEON_PLL_USE_REF_DIV; pll 818 drivers/gpu/drm/radeon/radeon_legacy_crtc.c radeon_compute_pll_legacy(pll, mode->clock, pll 849 drivers/gpu/drm/radeon/radeon_legacy_crtc.c pll_gain = radeon_compute_pll_gain(pll->reference_freq, pll 245 drivers/gpu/drm/radeon/radeon_legacy_tv.c struct radeon_pll *pll; pll 249 drivers/gpu/drm/radeon/radeon_legacy_tv.c pll = &rdev->clock.p2pll; pll 251 drivers/gpu/drm/radeon/radeon_legacy_tv.c pll = &rdev->clock.p1pll; pll 254 drivers/gpu/drm/radeon/radeon_legacy_tv.c *pll_ref_freq = pll->reference_freq; pll 259 drivers/gpu/drm/radeon/radeon_legacy_tv.c if (pll->reference_freq == 2700) pll 264 drivers/gpu/drm/radeon/radeon_legacy_tv.c if (pll->reference_freq == 2700) pll 815 drivers/gpu/drm/radeon/radeon_mode.h extern void radeon_compute_pll_legacy(struct radeon_pll *pll, pll 823 drivers/gpu/drm/radeon/radeon_mode.h extern void radeon_compute_pll_avivo(struct radeon_pll *pll, pll 191 drivers/gpu/drm/rcar-du/rcar_lvds.c unsigned long target, struct pll_info *pll, pll 294 drivers/gpu/drm/rcar-du/rcar_lvds.c if (diff < pll->diff) { pll 295 drivers/gpu/drm/rcar-du/rcar_lvds.c pll->diff = diff; pll 296 drivers/gpu/drm/rcar-du/rcar_lvds.c pll->pll_m = m; pll 297 drivers/gpu/drm/rcar-du/rcar_lvds.c pll->pll_n = n; pll 298 drivers/gpu/drm/rcar-du/rcar_lvds.c pll->pll_e = e; pll 299 drivers/gpu/drm/rcar-du/rcar_lvds.c pll->div = div; pll 300 drivers/gpu/drm/rcar-du/rcar_lvds.c pll->clksel = clksel; pll 310 drivers/gpu/drm/rcar-du/rcar_lvds.c output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e) pll 311 drivers/gpu/drm/rcar-du/rcar_lvds.c / div7 / pll->div; pll 318 drivers/gpu/drm/rcar-du/rcar_lvds.c pll->pll_m, pll->pll_n, pll->pll_e, pll->div); pll 324 drivers/gpu/drm/rcar-du/rcar_lvds.c struct pll_info pll = { .diff = (unsigned long)-1 }; pll 327 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll, pll 329 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll, pll 331 drivers/gpu/drm/rcar-du/rcar_lvds.c rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll, pll 334 drivers/gpu/drm/rcar-du/rcar_lvds.c lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT pll 335 drivers/gpu/drm/rcar-du/rcar_lvds.c | LVDPLLCR_PLLN(pll.pll_n - 1) | LVDPLLCR_PLLM(pll.pll_m - 1); pll 337 drivers/gpu/drm/rcar-du/rcar_lvds.c if (pll.pll_e > 0) pll 339 drivers/gpu/drm/rcar-du/rcar_lvds.c | LVDPLLCR_PLLE(pll.pll_e - 1); pll 346 drivers/gpu/drm/rcar-du/rcar_lvds.c if (pll.div > 1) pll 352 drivers/gpu/drm/rcar-du/rcar_lvds.c LVDDIV_DIVRESET | LVDDIV_DIV(pll.div - 1)); pll 61 drivers/gpu/drm/tegra/hdmi.c struct regulator *pll; pll 1464 drivers/gpu/drm/tegra/hdmi.c err = regulator_enable(hdmi->pll); pll 1486 drivers/gpu/drm/tegra/hdmi.c regulator_disable(hdmi->pll); pll 1629 drivers/gpu/drm/tegra/hdmi.c hdmi->pll = devm_regulator_get(&pdev->dev, "pll"); pll 1630 drivers/gpu/drm/tegra/hdmi.c if (IS_ERR(hdmi->pll)) { pll 1632 drivers/gpu/drm/tegra/hdmi.c return PTR_ERR(hdmi->pll); pll 2233 drivers/media/dvb-frontends/dib0090.c const struct dib0090_pll *pll = state->current_pll_table_index; pll 2347 drivers/media/dvb-frontends/dib0090.c pll = dib0090_pll_table; pll 2349 drivers/media/dvb-frontends/dib0090.c pll = dib0090_p1g_pll_table; pll 2354 drivers/media/dvb-frontends/dib0090.c while (state->rf_request > pll->max_freq) pll 2355 drivers/media/dvb-frontends/dib0090.c pll++; pll 2358 drivers/media/dvb-frontends/dib0090.c state->current_pll_table_index = pll; pll 2362 drivers/media/dvb-frontends/dib0090.c VCOF_kHz = (pll->hfdiv * state->rf_request) * 2; pll 2368 drivers/media/dvb-frontends/dib0090.c FBDiv = (VCOF_kHz / pll->topresc / FREF); pll 2369 drivers/media/dvb-frontends/dib0090.c Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF; pll 2388 drivers/media/dvb-frontends/dib0090.c if (pll->vco_band) pll 2393 drivers/media/dvb-frontends/dib0090.c if (pll->vco_band) pll 2411 drivers/media/dvb-frontends/dib0090.c lo5 |= (pll->hfdiv_code << 11) | (pll->vco_band << 7); /* bit 15 is the split to the slave, we do not do it here */ pll 2461 drivers/media/dvb-frontends/dib0090.c dprintk("HFDIV code: %d\n", (u32) pll->hfdiv_code); pll 2462 drivers/media/dvb-frontends/dib0090.c dprintk("VCO = %d\n", (u32) pll->vco_band); pll 2463 drivers/media/dvb-frontends/dib0090.c dprintk("VCOF in kHz: %d ((%d*%d) << 1))\n", (u32) ((pll->hfdiv * state->rf_request) * 2), (u32) pll->hfdiv, (u32) state->rf_request); pll 695 drivers/media/dvb-frontends/dib8000.c const struct dibx000_bandwidth_config *pll = state->cfg.pll; pll 700 drivers/media/dvb-frontends/dib8000.c (pll->pll_prediv << 8) | (pll->pll_ratio << 0)); pll 702 drivers/media/dvb-frontends/dib8000.c clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) | pll 703 drivers/media/dvb-frontends/dib8000.c (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | pll 704 drivers/media/dvb-frontends/dib8000.c (1 << 3) | (pll->pll_range << 1) | pll 705 drivers/media/dvb-frontends/dib8000.c (pll->pll_reset << 0); pll 708 drivers/media/dvb-frontends/dib8000.c clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3); pll 714 drivers/media/dvb-frontends/dib8000.c if (state->cfg.pll->ADClkSrc == 0) pll 717 drivers/media/dvb-frontends/dib8000.c (pll->modulo << 8) | pll 718 drivers/media/dvb-frontends/dib8000.c (pll->ADClkSrc << 7) | (0 << 1)); pll 722 drivers/media/dvb-frontends/dib8000.c (pll->modulo << 8) | pll 723 drivers/media/dvb-frontends/dib8000.c (pll->ADClkSrc << 7) | (0 << 1)); pll 726 drivers/media/dvb-frontends/dib8000.c (3 << 10) | (pll->modulo << 8) | pll 727 drivers/media/dvb-frontends/dib8000.c (pll->ADClkSrc << 7) | (0 << 1)); pll 729 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 1856, (!pll->pll_reset<<13) | pll 730 drivers/media/dvb-frontends/dib8000.c (pll->pll_range<<12) | (pll->pll_ratio<<6) | pll 731 drivers/media/dvb-frontends/dib8000.c (pll->pll_prediv)); pll 734 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15)); pll 739 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 904, (pll->modulo << 8)); pll 742 drivers/media/dvb-frontends/dib8000.c dib8000_reset_pll_common(state, pll); pll 746 drivers/media/dvb-frontends/dib8000.c struct dibx000_bandwidth_config *pll, u32 bw, u8 ratio) pll 750 drivers/media/dvb-frontends/dib8000.c u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ; pll 757 drivers/media/dvb-frontends/dib8000.c if ((pll == NULL) || (pll->pll_prediv == prediv && pll 758 drivers/media/dvb-frontends/dib8000.c pll->pll_ratio == loopdiv)) pll 761 drivers/media/dvb-frontends/dib8000.c dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio); pll 769 drivers/media/dvb-frontends/dib8000.c ((pll->pll_ratio & 0x3f) << 6) | pll 770 drivers/media/dvb-frontends/dib8000.c (pll->pll_prediv & 0x3f)); pll 776 drivers/media/dvb-frontends/dib8000.c internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio; pll 796 drivers/media/dvb-frontends/dib8000.c dprintk("PLL: Bandwidth Change %d MHz -> %d MHz (prediv: %d->%d)\n", state->current_demod_bw / 1000, bw / 1000, oldprediv, state->cfg.pll->pll_prediv); pll 798 drivers/media/dvb-frontends/dib8000.c if (state->cfg.pll->pll_prediv != oldprediv) { pll 802 drivers/media/dvb-frontends/dib8000.c dprintk("PLL: New Setting for %d MHz Bandwidth (prediv: %d, ratio: %d)\n", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll->pll_ratio); pll 807 drivers/media/dvb-frontends/dib8000.c ratio = state->cfg.pll->pll_ratio; pll 814 drivers/media/dvb-frontends/dib8000.c dprintk("PLL: Update ratio (prediv: %d, ratio: %d)\n", state->cfg.pll->pll_prediv, ratio); pll 815 drivers/media/dvb-frontends/dib8000.c dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL ratio is updated. */ pll 1097 drivers/media/dvb-frontends/dib8000.c if (state->cfg.pll->ifreq == 0) pll 2172 drivers/media/dvb-frontends/dib8000.c if (state->cfg.pll->ifreq == 0) pll 2497 drivers/media/dvb-frontends/dib8000.c u32 value, internal = state->cfg.pll->internal; pll 2678 drivers/media/dvb-frontends/dib8000.c u32 dds = state->cfg.pll->ifreq & 0x1ffffff; pll 2679 drivers/media/dvb-frontends/dib8000.c u8 invert = !!(state->cfg.pll->ifreq & (1 << 25)); pll 2694 drivers/media/dvb-frontends/dib8000.c unit_khz_dds_val = (u16) (67108864 / state->cfg.pll->internal); pll 2708 drivers/media/dvb-frontends/dib8000.c if (abs_offset_khz <= (state->cfg.pll->internal / ratio)) { pll 2736 drivers/media/dvb-frontends/dib8000.c if (state->cfg.pll->ifreq == 0) { /* low if tuner */ pll 4450 drivers/media/dvb-frontends/dib8000.c state->timf_default = cfg->pll->timf; pll 15 drivers/media/dvb-frontends/dib8000.h struct dibx000_bandwidth_config *pll; pll 46 drivers/media/dvb-frontends/dib8000.h struct dibx000_bandwidth_config *pll, u32 bw, u8 ratio); pll 1755 drivers/media/dvb-frontends/mb86a20s.c u64 pll; pll 1802 drivers/media/dvb-frontends/mb86a20s.c pll = (((u64)1) << 34) * state->if_freq; pll 1803 drivers/media/dvb-frontends/mb86a20s.c do_div(pll, 63 * fclk); pll 1804 drivers/media/dvb-frontends/mb86a20s.c pll = (1 << 25) - pll; pll 1808 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff); pll 1811 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff); pll 1814 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x2b, pll & 0xff); pll 1818 drivers/media/dvb-frontends/mb86a20s.c __func__, fclk, state->if_freq, (long long)pll); pll 1821 drivers/media/dvb-frontends/mb86a20s.c pll = state->if_freq * 1677721600L; pll 1822 drivers/media/dvb-frontends/mb86a20s.c do_div(pll, 1628571429L); pll 1826 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff); pll 1829 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff); pll 1832 drivers/media/dvb-frontends/mb86a20s.c rc = mb86a20s_writereg(state, 0x2b, pll & 0xff); pll 1836 drivers/media/dvb-frontends/mb86a20s.c __func__, state->if_freq, (long long)pll); pll 991 drivers/media/i2c/adv7604.c const u8 pll[2] = { pll 1009 drivers/media/i2c/adv7604.c 0x16, pll, 2)) pll 1063 drivers/media/i2c/adv7842.c const u8 pll[2] = { pll 1082 drivers/media/i2c/adv7842.c if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) { pll 18 drivers/media/i2c/aptina-pll.c struct aptina_pll *pll) pll 28 drivers/media/i2c/aptina-pll.c pll->ext_clock, pll->pix_clock); pll 30 drivers/media/i2c/aptina-pll.c if (pll->ext_clock < limits->ext_clock_min || pll 31 drivers/media/i2c/aptina-pll.c pll->ext_clock > limits->ext_clock_max) { pll 36 drivers/media/i2c/aptina-pll.c if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) { pll 42 drivers/media/i2c/aptina-pll.c div = gcd(pll->pix_clock, pll->ext_clock); pll 43 drivers/media/i2c/aptina-pll.c pll->m = pll->pix_clock / div; pll 44 drivers/media/i2c/aptina-pll.c div = pll->ext_clock / div; pll 56 drivers/media/i2c/aptina-pll.c mf_min = DIV_ROUND_UP(limits->m_min, pll->m); pll 58 drivers/media/i2c/aptina-pll.c (pll->ext_clock / limits->n_min * pll->m)); pll 60 drivers/media/i2c/aptina-pll.c mf_max = limits->m_max / pll->m; pll 62 drivers/media/i2c/aptina-pll.c (pll->ext_clock / limits->n_max * pll->m)); pll 129 drivers/media/i2c/aptina-pll.c pll->ext_clock * pll->m)); pll 131 drivers/media/i2c/aptina-pll.c (pll->ext_clock * pll->m)); pll 138 drivers/media/i2c/aptina-pll.c mf_low = roundup(max(mf_min, DIV_ROUND_UP(pll->ext_clock * p1, pll 140 drivers/media/i2c/aptina-pll.c mf_high = min(mf_max, pll->ext_clock * p1 / pll 146 drivers/media/i2c/aptina-pll.c pll->n = div * mf_low / p1; pll 147 drivers/media/i2c/aptina-pll.c pll->m *= mf_low; pll 148 drivers/media/i2c/aptina-pll.c pll->p1 = p1; pll 149 drivers/media/i2c/aptina-pll.c dev_dbg(dev, "PLL: N %u M %u P1 %u\n", pll->n, pll->m, pll->p1); pll 41 drivers/media/i2c/aptina-pll.h struct aptina_pll *pll); pll 1212 drivers/media/i2c/cx25840/cx25840-core.c int pll = (28636363L * ((((u64)pll_int) << 25L) + pll_frac)) >> 25L; pll 1214 drivers/media/i2c/cx25840/cx25840-core.c pll /= pll_post; pll 1217 drivers/media/i2c/cx25840/cx25840-core.c pll / 1000000, pll % 1000000); pll 1220 drivers/media/i2c/cx25840/cx25840-core.c pll / 8000000, (pll / 8) % 1000000); pll 1222 drivers/media/i2c/cx25840/cx25840-core.c fin = ((u64)src_decimation * pll) >> 12; pll 1227 drivers/media/i2c/cx25840/cx25840-core.c fsc = (((u64)sc) * pll) >> 24L; pll 269 drivers/media/i2c/mt9m032.c struct aptina_pll pll; pll 273 drivers/media/i2c/mt9m032.c pll.ext_clock = pdata->ext_clock; pll 274 drivers/media/i2c/mt9m032.c pll.pix_clock = pdata->pix_clock; pll 276 drivers/media/i2c/mt9m032.c ret = aptina_pll_calculate(&client->dev, &limits, &pll); pll 283 drivers/media/i2c/mt9m032.c (pll.m << MT9M032_PLL_CONFIG1_MUL_SHIFT) | pll 284 drivers/media/i2c/mt9m032.c ((pll.n - 1) & MT9M032_PLL_CONFIG1_PREDIV_MASK)); pll 294 drivers/media/i2c/mt9m032.c reg_val = (pll.p1 == 6 ? MT9M032_FORMATTER1_PLL_P1_6 : 0) pll 132 drivers/media/i2c/mt9p031.c struct aptina_pll pll; pll 257 drivers/media/i2c/mt9p031.c mt9p031->pll.ext_clock = pdata->ext_freq; pll 258 drivers/media/i2c/mt9p031.c mt9p031->pll.pix_clock = pdata->target_freq; pll 261 drivers/media/i2c/mt9p031.c return aptina_pll_calculate(&client->dev, &limits, &mt9p031->pll); pll 278 drivers/media/i2c/mt9p031.c (mt9p031->pll.m << 8) | (mt9p031->pll.n - 1)); pll 282 drivers/media/i2c/mt9p031.c ret = mt9p031_write(client, MT9P031_PLL_CONFIG_2, mt9p031->pll.p1 - 1); pll 233 drivers/media/i2c/ov2659.c struct ov2659_pll_ctrl pll; pll 943 drivers/media/i2c/ov2659.c ov2659->pll.ctrl1 = ctrl1_reg; pll 944 drivers/media/i2c/ov2659.c ov2659->pll.ctrl2 = ctrl2_reg; pll 945 drivers/media/i2c/ov2659.c ov2659->pll.ctrl3 = ctrl3_reg; pll 956 drivers/media/i2c/ov2659.c {REG_SC_PLL_CTRL1, ov2659->pll.ctrl1}, pll 957 drivers/media/i2c/ov2659.c {REG_SC_PLL_CTRL2, ov2659->pll.ctrl2}, pll 958 drivers/media/i2c/ov2659.c {REG_SC_PLL_CTRL3, ov2659->pll.ctrl3}, pll 53 drivers/media/i2c/smiapp-pll.c static void print_pll(struct device *dev, struct smiapp_pll *pll) pll 55 drivers/media/i2c/smiapp-pll.c dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div); pll 56 drivers/media/i2c/smiapp-pll.c dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier); pll 57 drivers/media/i2c/smiapp-pll.c if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) { pll 58 drivers/media/i2c/smiapp-pll.c dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div); pll 59 drivers/media/i2c/smiapp-pll.c dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div); pll 61 drivers/media/i2c/smiapp-pll.c dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt.sys_clk_div); pll 62 drivers/media/i2c/smiapp-pll.c dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt.pix_clk_div); pll 64 drivers/media/i2c/smiapp-pll.c dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz); pll 65 drivers/media/i2c/smiapp-pll.c dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->pll_ip_clk_freq_hz); pll 66 drivers/media/i2c/smiapp-pll.c dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->pll_op_clk_freq_hz); pll 67 drivers/media/i2c/smiapp-pll.c if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) { pll 69 drivers/media/i2c/smiapp-pll.c pll->op.sys_clk_freq_hz); pll 71 drivers/media/i2c/smiapp-pll.c pll->op.pix_clk_freq_hz); pll 73 drivers/media/i2c/smiapp-pll.c dev_dbg(dev, "vt_sys_clk_freq_hz \t%u\n", pll->vt.sys_clk_freq_hz); pll 74 drivers/media/i2c/smiapp-pll.c dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt.pix_clk_freq_hz); pll 80 drivers/media/i2c/smiapp-pll.c struct smiapp_pll *pll, pll 85 drivers/media/i2c/smiapp-pll.c rval = bounds_check(dev, pll->pll_ip_clk_freq_hz, pll 91 drivers/media/i2c/smiapp-pll.c dev, pll->pll_multiplier, pll 96 drivers/media/i2c/smiapp-pll.c dev, pll->pll_op_clk_freq_hz, pll 121 drivers/media/i2c/smiapp-pll.c if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) pll 126 drivers/media/i2c/smiapp-pll.c dev, pll->vt.sys_clk_freq_hz, pll 132 drivers/media/i2c/smiapp-pll.c dev, pll->vt.pix_clk_freq_hz, pll 154 drivers/media/i2c/smiapp-pll.c struct smiapp_pll *pll, struct smiapp_pll_branch *op_pll, uint32_t mul, pll 176 drivers/media/i2c/smiapp-pll.c dev_dbg(dev, "pre_pll_clk_div %u\n", pll->pre_pll_clk_div); pll 187 drivers/media/i2c/smiapp-pll.c / (pll->ext_clk_freq_hz / pll->pre_pll_clk_div * mul)); pll 192 drivers/media/i2c/smiapp-pll.c op_limits->max_sys_clk_div * pll->pre_pll_clk_div pll 204 drivers/media/i2c/smiapp-pll.c pll->ext_clk_freq_hz / pll->pre_pll_clk_div pll 220 drivers/media/i2c/smiapp-pll.c more_mul_factor = lcm(div, pll->pre_pll_clk_div) / div; pll 235 drivers/media/i2c/smiapp-pll.c pll->pll_multiplier = mul * i; pll 236 drivers/media/i2c/smiapp-pll.c op_pll->sys_clk_div = div * i / pll->pre_pll_clk_div; pll 239 drivers/media/i2c/smiapp-pll.c pll->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz pll 240 drivers/media/i2c/smiapp-pll.c / pll->pre_pll_clk_div; pll 242 drivers/media/i2c/smiapp-pll.c pll->pll_op_clk_freq_hz = pll->pll_ip_clk_freq_hz pll 243 drivers/media/i2c/smiapp-pll.c * pll->pll_multiplier; pll 247 drivers/media/i2c/smiapp-pll.c pll->pll_op_clk_freq_hz / op_pll->sys_clk_div; pll 249 drivers/media/i2c/smiapp-pll.c op_pll->pix_clk_div = pll->bits_per_pixel; pll 255 drivers/media/i2c/smiapp-pll.c if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) { pll 268 drivers/media/i2c/smiapp-pll.c / pll->binning_horizontal) pll 269 drivers/media/i2c/smiapp-pll.c vt_op_binning_div = pll->binning_horizontal; pll 285 drivers/media/i2c/smiapp-pll.c dev_dbg(dev, "scale_m: %u\n", pll->scale_m); pll 287 drivers/media/i2c/smiapp-pll.c * pll->scale_n, pll 289 drivers/media/i2c/smiapp-pll.c * pll->scale_m); pll 294 drivers/media/i2c/smiapp-pll.c DIV_ROUND_UP(pll->pll_op_clk_freq_hz, pll 306 drivers/media/i2c/smiapp-pll.c DIV_ROUND_UP(pll->pll_op_clk_freq_hz, pll 322 drivers/media/i2c/smiapp-pll.c pll->pll_op_clk_freq_hz pll 335 drivers/media/i2c/smiapp-pll.c DIV_ROUND_UP(pll->pll_op_clk_freq_hz, pll 370 drivers/media/i2c/smiapp-pll.c pll->vt.sys_clk_div = DIV_ROUND_UP(min_vt_div, best_pix_div); pll 371 drivers/media/i2c/smiapp-pll.c pll->vt.pix_clk_div = best_pix_div; pll 373 drivers/media/i2c/smiapp-pll.c pll->vt.sys_clk_freq_hz = pll 374 drivers/media/i2c/smiapp-pll.c pll->pll_op_clk_freq_hz / pll->vt.sys_clk_div; pll 375 drivers/media/i2c/smiapp-pll.c pll->vt.pix_clk_freq_hz = pll 376 drivers/media/i2c/smiapp-pll.c pll->vt.sys_clk_freq_hz / pll->vt.pix_clk_div; pll 379 drivers/media/i2c/smiapp-pll.c pll->pixel_rate_csi = pll 381 drivers/media/i2c/smiapp-pll.c pll->pixel_rate_pixel_array = pll->vt.pix_clk_freq_hz; pll 383 drivers/media/i2c/smiapp-pll.c return check_all_bounds(dev, limits, op_limits, pll, op_pll); pll 388 drivers/media/i2c/smiapp-pll.c struct smiapp_pll *pll) pll 391 drivers/media/i2c/smiapp-pll.c struct smiapp_pll_branch *op_pll = &pll->op; pll 399 drivers/media/i2c/smiapp-pll.c if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) { pll 406 drivers/media/i2c/smiapp-pll.c op_pll = &pll->vt; pll 409 drivers/media/i2c/smiapp-pll.c if (pll->flags & SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE) pll 410 drivers/media/i2c/smiapp-pll.c lane_op_clock_ratio = pll->csi2.lanes; pll 415 drivers/media/i2c/smiapp-pll.c dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal, pll 416 drivers/media/i2c/smiapp-pll.c pll->binning_vertical); pll 418 drivers/media/i2c/smiapp-pll.c switch (pll->bus_type) { pll 421 drivers/media/i2c/smiapp-pll.c pll->pll_op_clk_freq_hz = pll->link_freq * 2 pll 422 drivers/media/i2c/smiapp-pll.c * (pll->csi2.lanes / lane_op_clock_ratio); pll 425 drivers/media/i2c/smiapp-pll.c pll->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel pll 426 drivers/media/i2c/smiapp-pll.c / DIV_ROUND_UP(pll->bits_per_pixel, pll 427 drivers/media/i2c/smiapp-pll.c pll->parallel.bus_width); pll 438 drivers/media/i2c/smiapp-pll.c clk_div_even(pll->ext_clk_freq_hz / pll 443 drivers/media/i2c/smiapp-pll.c DIV_ROUND_UP(pll->ext_clk_freq_hz, pll 448 drivers/media/i2c/smiapp-pll.c i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz); pll 449 drivers/media/i2c/smiapp-pll.c mul = div_u64(pll->pll_op_clk_freq_hz, i); pll 450 drivers/media/i2c/smiapp-pll.c div = pll->ext_clk_freq_hz / i; pll 456 drivers/media/i2c/smiapp-pll.c DIV_ROUND_UP(mul * pll->ext_clk_freq_hz, pll 461 drivers/media/i2c/smiapp-pll.c for (pll->pre_pll_clk_div = min_pre_pll_clk_div; pll 462 drivers/media/i2c/smiapp-pll.c pll->pre_pll_clk_div <= max_pre_pll_clk_div; pll 463 drivers/media/i2c/smiapp-pll.c pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) { pll 464 drivers/media/i2c/smiapp-pll.c rval = __smiapp_pll_calculate(dev, limits, op_limits, pll, pll 470 drivers/media/i2c/smiapp-pll.c print_pll(dev, pll); pll 97 drivers/media/i2c/smiapp-pll.h struct smiapp_pll *pll); pll 199 drivers/media/i2c/smiapp/smiapp-core.c struct smiapp_pll *pll = &sensor->pll; pll 203 drivers/media/i2c/smiapp/smiapp-core.c sensor, SMIAPP_REG_U16_VT_PIX_CLK_DIV, pll->vt.pix_clk_div); pll 208 drivers/media/i2c/smiapp/smiapp-core.c sensor, SMIAPP_REG_U16_VT_SYS_CLK_DIV, pll->vt.sys_clk_div); pll 213 drivers/media/i2c/smiapp/smiapp-core.c sensor, SMIAPP_REG_U16_PRE_PLL_CLK_DIV, pll->pre_pll_clk_div); pll 218 drivers/media/i2c/smiapp/smiapp-core.c sensor, SMIAPP_REG_U16_PLL_MULTIPLIER, pll->pll_multiplier); pll 225 drivers/media/i2c/smiapp/smiapp-core.c DIV_ROUND_UP(pll->op.sys_clk_freq_hz, 1000000 / 256 / 256)); pll 230 drivers/media/i2c/smiapp/smiapp-core.c sensor, SMIAPP_REG_U16_OP_PIX_CLK_DIV, pll->op.pix_clk_div); pll 235 drivers/media/i2c/smiapp/smiapp-core.c sensor, SMIAPP_REG_U16_OP_SYS_CLK_DIV, pll->op.sys_clk_div); pll 239 drivers/media/i2c/smiapp/smiapp-core.c struct smiapp_pll *pll) pll 274 drivers/media/i2c/smiapp/smiapp-core.c return smiapp_pll_calculate(&client->dev, &lim, pll); pll 279 drivers/media/i2c/smiapp/smiapp-core.c struct smiapp_pll *pll = &sensor->pll; pll 282 drivers/media/i2c/smiapp/smiapp-core.c pll->binning_horizontal = sensor->binning_horizontal; pll 283 drivers/media/i2c/smiapp/smiapp-core.c pll->binning_vertical = sensor->binning_vertical; pll 284 drivers/media/i2c/smiapp/smiapp-core.c pll->link_freq = pll 286 drivers/media/i2c/smiapp/smiapp-core.c pll->scale_m = sensor->scale_m; pll 287 drivers/media/i2c/smiapp/smiapp-core.c pll->bits_per_pixel = sensor->csi_format->compressed; pll 289 drivers/media/i2c/smiapp/smiapp-core.c rval = smiapp_pll_try(sensor, pll); pll 294 drivers/media/i2c/smiapp/smiapp-core.c pll->pixel_rate_pixel_array); pll 295 drivers/media/i2c/smiapp/smiapp-core.c __v4l2_ctrl_s_ctrl_int64(sensor->pixel_rate_csi, pll->pixel_rate_csi); pll 748 drivers/media/i2c/smiapp/smiapp-core.c struct smiapp_pll *pll = &sensor->pll; pll 817 drivers/media/i2c/smiapp/smiapp-core.c pll->binning_horizontal = 1; pll 818 drivers/media/i2c/smiapp/smiapp-core.c pll->binning_vertical = 1; pll 819 drivers/media/i2c/smiapp/smiapp-core.c pll->scale_m = sensor->scale_m; pll 848 drivers/media/i2c/smiapp/smiapp-core.c pll->bits_per_pixel = f->compressed; pll 851 drivers/media/i2c/smiapp/smiapp-core.c pll->link_freq = sensor->hwcfg->op_sys_clock[j]; pll 853 drivers/media/i2c/smiapp/smiapp-core.c rval = smiapp_pll_try(sensor, pll); pll 855 drivers/media/i2c/smiapp/smiapp-core.c pll->link_freq, pll->bits_per_pixel, pll 959 drivers/media/i2c/smiapp/smiapp-core.c sensor->pll.pixel_rate_pixel_array / pll 3052 drivers/media/i2c/smiapp/smiapp-core.c sensor->pll.bus_type = SMIAPP_PLL_BUS_TYPE_CSI2; pll 3053 drivers/media/i2c/smiapp/smiapp-core.c sensor->pll.csi2.lanes = sensor->hwcfg->lanes; pll 3054 drivers/media/i2c/smiapp/smiapp-core.c sensor->pll.ext_clk_freq_hz = sensor->hwcfg->ext_clk; pll 3055 drivers/media/i2c/smiapp/smiapp-core.c sensor->pll.scale_n = sensor->limits[SMIAPP_LIMIT_SCALER_N_MIN]; pll 3058 drivers/media/i2c/smiapp/smiapp-core.c sensor->pll.flags |= SMIAPP_PLL_FLAG_NO_OP_CLOCKS; pll 209 drivers/media/i2c/smiapp/smiapp-quirk.c sensor->pll.flags |= SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE; pll 216 drivers/media/i2c/smiapp/smiapp.h struct smiapp_pll pll; pll 87 drivers/media/pci/bt8xx/bttv-cards.c static unsigned int pll[BTTV_MAX] = { [ 0 ... (BTTV_MAX-1) ] = UNSET }; pll 109 drivers/media/pci/bt8xx/bttv-cards.c module_param_array(pll, int, NULL, 0444); pll 120 drivers/media/pci/bt8xx/bttv-cards.c MODULE_PARM_DESC(pll, "specify installed crystal (0=none, 28=28 MHz, 35=35 MHz, 14=14 MHz)"); pll 393 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 457 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 469 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 482 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 520 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 535 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 563 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 624 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 637 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 652 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 667 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 707 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 780 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 792 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 818 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 844 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 860 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 875 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 890 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 903 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 917 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 935 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 946 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 961 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 990 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_NONE, pll 1003 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1017 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1031 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_35, pll 1047 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1060 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1077 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1100 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1125 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1140 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1163 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1178 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1194 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1210 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_35, pll 1224 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1238 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1255 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_35, pll 1269 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1285 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1299 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1315 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1334 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1347 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1362 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1386 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1406 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1416 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1430 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1449 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1467 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1519 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1547 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1568 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1590 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1602 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1619 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1631 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1643 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1657 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1669 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1681 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1693 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1707 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1719 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1731 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1741 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1755 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1773 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1785 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1798 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1823 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1834 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1848 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1865 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1880 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1905 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1923 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1934 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1948 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1959 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1977 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 1990 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2002 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2018 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2032 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2045 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2060 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2094 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2106 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_35, pll 2117 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2131 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2159 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2174 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2196 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2225 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2240 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2258 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2273 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2289 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2302 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2319 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2344 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2380 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2401 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2417 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2447 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2462 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2481 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2498 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2526 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2542 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2557 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2593 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2640 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2655 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2673 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2696 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2709 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2722 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2735 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2761 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2785 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2799 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2811 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2830 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2837 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_14, pll 2846 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2860 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_28, pll 2880 drivers/media/pci/bt8xx/bttv-cards.c .pll = PLL_35, pll 3441 drivers/media/pci/bt8xx/bttv-cards.c if (PLL_28 == bttv_tvcards[btv->c.type].pll) { pll 3442 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_ifreq=28636363; pll 3443 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_crystal=BT848_IFORM_XT0; pll 3445 drivers/media/pci/bt8xx/bttv-cards.c if (PLL_35 == bttv_tvcards[btv->c.type].pll) { pll 3446 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_ifreq=35468950; pll 3447 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_crystal=BT848_IFORM_XT1; pll 3449 drivers/media/pci/bt8xx/bttv-cards.c if (PLL_14 == bttv_tvcards[btv->c.type].pll) { pll 3450 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_ifreq = 14318181; pll 3451 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_crystal = BT848_IFORM_XT0; pll 3454 drivers/media/pci/bt8xx/bttv-cards.c switch (pll[btv->c.nr]) { pll 3456 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_crystal = 0; pll 3457 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_ifreq = 0; pll 3458 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_ofreq = 0; pll 3462 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_ifreq = 28636363; pll 3463 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_ofreq = 0; pll 3464 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_crystal = BT848_IFORM_XT0; pll 3468 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_ifreq = 35468950; pll 3469 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_ofreq = 0; pll 3470 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_crystal = BT848_IFORM_XT1; pll 3474 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_ifreq = 14318181; pll 3475 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_ofreq = 0; pll 3476 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_crystal = BT848_IFORM_XT0; pll 3480 drivers/media/pci/bt8xx/bttv-cards.c btv->pll.pll_current = -1; pll 799 drivers/media/pci/bt8xx/bttv-driver.c if (!btv->pll.pll_crystal) pll 802 drivers/media/pci/bt8xx/bttv-driver.c if (btv->pll.pll_ofreq == btv->pll.pll_current) { pll 807 drivers/media/pci/bt8xx/bttv-driver.c if (btv->pll.pll_ifreq == btv->pll.pll_ofreq) { pll 809 drivers/media/pci/bt8xx/bttv-driver.c if (btv->pll.pll_current == 0) pll 813 drivers/media/pci/bt8xx/bttv-driver.c btv->c.nr, btv->pll.pll_ifreq); pll 816 drivers/media/pci/bt8xx/bttv-driver.c btv->pll.pll_current = 0; pll 823 drivers/media/pci/bt8xx/bttv-driver.c btv->pll.pll_ifreq, btv->pll.pll_ofreq); pll 824 drivers/media/pci/bt8xx/bttv-driver.c set_pll_freq(btv, btv->pll.pll_ifreq, btv->pll.pll_ofreq); pll 834 drivers/media/pci/bt8xx/bttv-driver.c btv->pll.pll_current = btv->pll.pll_ofreq; pll 840 drivers/media/pci/bt8xx/bttv-driver.c btv->pll.pll_current = -1; pll 865 drivers/media/pci/bt8xx/bttv-driver.c btv->pll.pll_ofreq = 27000000; pll 871 drivers/media/pci/bt8xx/bttv-driver.c btv->pll.pll_ofreq = fsc; pll 1248 drivers/media/pci/bt8xx/bttv-driver.c btv->pll.pll_current = -1; pll 236 drivers/media/pci/bt8xx/bttv.h unsigned int pll:2; pll 369 drivers/media/pci/bt8xx/bttvp.h struct bttv_pll_info pll; pll 191 drivers/media/pci/bt8xx/dvb-bt8xx.c u32 band, pll; pll 220 drivers/media/pci/bt8xx/dvb-bt8xx.c pll=0xf8000000| pll 232 drivers/media/pci/bt8xx/dvb-bt8xx.c cx24110_pll_write(fe,pll); pll 447 drivers/media/pci/cx18/cx18-av-core.c int fsc, pll; pll 450 drivers/media/pci/cx18/cx18-av-core.c pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25; pll 451 drivers/media/pci/cx18/cx18-av-core.c pll /= pll_post; pll 453 drivers/media/pci/cx18/cx18-av-core.c pll / 1000000, pll % 1000000); pll 455 drivers/media/pci/cx18/cx18-av-core.c pll / 8000000, (pll / 8) % 1000000); pll 743 drivers/media/pci/cx88/cx88-core.c u64 pll; pll 752 drivers/media/pci/cx88/cx88-core.c pll = ofreq * 8 * prescale * (u64)(1 << 20); pll 753 drivers/media/pci/cx88/cx88-core.c do_div(pll, xtal); pll 754 drivers/media/pci/cx88/cx88-core.c reg = (pll & 0x3ffffff) | (pre[prescale] << 26); pll 96 drivers/media/radio/tef6862.c u16 pll; pll 104 drivers/media/radio/tef6862.c pll = 1964 + ((freq - TEF6862_LO_FREQ) * 20) / FREQ_MUL; pll 106 drivers/media/radio/tef6862.c i2cmsg[1] = (pll >> 8) & 0xff; pll 107 drivers/media/radio/tef6862.c i2cmsg[2] = pll & 0xff; pll 107 drivers/media/tuners/qm1d1b0004.c u32 frequency, pll, lpf_freq; pll 115 drivers/media/tuners/qm1d1b0004.c pll = QM1D1B0004_XTL_FREQ / 4; pll 117 drivers/media/tuners/qm1d1b0004.c pll /= 2; pll 118 drivers/media/tuners/qm1d1b0004.c word = DIV_ROUND_CLOSEST(frequency, pll); pll 80 drivers/media/tuners/r820t.c u16 pll; /* kHz */ pll 256 drivers/media/tuners/tda18271-common.c enum tda18271_pll pll, int force, pll 262 drivers/media/tuners/tda18271-common.c int r_cp = (pll == TDA18271_CAL_PLL) ? R_EB7 : R_EB4; pll 271 drivers/media/tuners/tda18271-common.c enum tda18271_pll pll, int force) pll 273 drivers/media/tuners/tda18271-common.c return __tda18271_charge_pump_source(fe, pll, force, true); pll 204 drivers/media/tuners/tda18271-priv.h enum tda18271_pll pll, int force); pll 1199 drivers/media/usb/dvb-usb/dib0700_devices.c .pll = &dib807x_bw_config_12_mhz, pll 1216 drivers/media/usb/dvb-usb/dib0700_devices.c .pll = &dib807x_bw_config_12_mhz, pll 1560 drivers/media/usb/dvb-usb/dib0700_devices.c .pll = &dib8090_pll_config_12mhz, pll 1579 drivers/media/usb/dvb-usb/dib0700_devices.c .pll = &dib8090_pll_config_12mhz, pll 1981 drivers/media/usb/dvb-usb/dib0700_devices.c .pll = &dib8096p_clock_config_12_mhz, pll 2121 drivers/media/usb/dvb-usb/dib0700_devices.c struct dibx000_bandwidth_config pll; pll 2129 drivers/media/usb/dvb-usb/dib0700_devices.c memset(&pll, 0, sizeof(struct dibx000_bandwidth_config)); pll 2138 drivers/media/usb/dvb-usb/dib0700_devices.c pll.pll_ratio = adc.pll_loopdiv; pll 2139 drivers/media/usb/dvb-usb/dib0700_devices.c pll.pll_prediv = adc.pll_prediv; pll 2142 drivers/media/usb/dvb-usb/dib0700_devices.c state->dib8000_ops.update_pll(fe, &pll, fe->dtv_property_cache.bandwidth_hz / 1000, 0); pll 2635 drivers/media/usb/dvb-usb/dib0700_devices.c struct dibx000_bandwidth_config pll; pll 2644 drivers/media/usb/dvb-usb/dib0700_devices.c memset(&pll, 0, sizeof(struct dibx000_bandwidth_config)); pll 2650 drivers/media/usb/dvb-usb/dib0700_devices.c pll.pll_ratio = adc.pll_loopdiv; pll 2651 drivers/media/usb/dvb-usb/dib0700_devices.c pll.pll_prediv = adc.pll_prediv; pll 2653 drivers/media/usb/dvb-usb/dib0700_devices.c state->dib7000p_ops.update_pll(fe, &pll); pll 326 drivers/mfd/twl6040.c twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL; pll 357 drivers/mfd/twl6040.c if (twl6040->pll == TWL6040_SYSCLK_SEL_HPPLL) { pll 383 drivers/mfd/twl6040.c if (pll_id != twl6040->pll) { pll 412 drivers/mfd/twl6040.c if (twl6040->pll == pll_id) pll 478 drivers/mfd/twl6040.c if (pll_id != twl6040->pll) pll 506 drivers/mfd/twl6040.c twl6040->pll = pll_id; pll 517 drivers/mfd/twl6040.c return twl6040->pll; pll 577 drivers/net/dsa/sja1105/sja1105_clocking.c struct sja1105_cgu_pll_ctrl pll = {0}; pll 588 drivers/net/dsa/sja1105/sja1105_clocking.c pll.pllclksrc = 0xA; pll 589 drivers/net/dsa/sja1105/sja1105_clocking.c pll.msel = 0x1; pll 590 drivers/net/dsa/sja1105/sja1105_clocking.c pll.autoblock = 0x1; pll 591 drivers/net/dsa/sja1105/sja1105_clocking.c pll.psel = 0x1; pll 592 drivers/net/dsa/sja1105/sja1105_clocking.c pll.direct = 0x0; pll 593 drivers/net/dsa/sja1105/sja1105_clocking.c pll.fbsel = 0x1; pll 594 drivers/net/dsa/sja1105/sja1105_clocking.c pll.bypass = 0x0; pll 595 drivers/net/dsa/sja1105/sja1105_clocking.c pll.pd = 0x1; pll 597 drivers/net/dsa/sja1105/sja1105_clocking.c sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK); pll 606 drivers/net/dsa/sja1105/sja1105_clocking.c pll.pd = 0x0; pll 608 drivers/net/dsa/sja1105/sja1105_clocking.c sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK); pll 59 drivers/net/phy/mdio-mux-meson-g12a.c struct clk *pll; pll 73 drivers/net/phy/mdio-mux-meson-g12a.c struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw); pll 76 drivers/net/phy/mdio-mux-meson-g12a.c val = readl(pll->base + ETH_PLL_CTL0); pll 85 drivers/net/phy/mdio-mux-meson-g12a.c struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw); pll 86 drivers/net/phy/mdio-mux-meson-g12a.c u32 val = readl(pll->base + ETH_PLL_CTL0); pll 90 drivers/net/phy/mdio-mux-meson-g12a.c writel(val, pll->base + ETH_PLL_CTL0); pll 94 drivers/net/phy/mdio-mux-meson-g12a.c writel(val, pll->base + ETH_PLL_CTL0); pll 101 drivers/net/phy/mdio-mux-meson-g12a.c return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val, pll 107 drivers/net/phy/mdio-mux-meson-g12a.c struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw); pll 110 drivers/net/phy/mdio-mux-meson-g12a.c val = readl(pll->base + ETH_PLL_CTL0); pll 113 drivers/net/phy/mdio-mux-meson-g12a.c writel(val, pll->base + ETH_PLL_CTL0); pll 118 drivers/net/phy/mdio-mux-meson-g12a.c struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw); pll 121 drivers/net/phy/mdio-mux-meson-g12a.c val = readl(pll->base + ETH_PLL_CTL0); pll 128 drivers/net/phy/mdio-mux-meson-g12a.c struct g12a_ephy_pll *pll = g12a_ephy_pll_to_dev(hw); pll 131 drivers/net/phy/mdio-mux-meson-g12a.c writel(0x29c0040a, pll->base + ETH_PLL_CTL0); pll 132 drivers/net/phy/mdio-mux-meson-g12a.c writel(0x927e0000, pll->base + ETH_PLL_CTL1); pll 133 drivers/net/phy/mdio-mux-meson-g12a.c writel(0xac5f49e5, pll->base + ETH_PLL_CTL2); pll 134 drivers/net/phy/mdio-mux-meson-g12a.c writel(0x00000000, pll->base + ETH_PLL_CTL3); pll 135 drivers/net/phy/mdio-mux-meson-g12a.c writel(0x00000000, pll->base + ETH_PLL_CTL4); pll 136 drivers/net/phy/mdio-mux-meson-g12a.c writel(0x20200000, pll->base + ETH_PLL_CTL5); pll 137 drivers/net/phy/mdio-mux-meson-g12a.c writel(0x0000c002, pll->base + ETH_PLL_CTL6); pll 138 drivers/net/phy/mdio-mux-meson-g12a.c writel(0x00000023, pll->base + ETH_PLL_CTL7); pll 155 drivers/net/phy/mdio-mux-meson-g12a.c ret = clk_prepare_enable(priv->pll); pll 186 drivers/net/phy/mdio-mux-meson-g12a.c clk_disable_unprepare(priv->pll); pll 222 drivers/net/phy/mdio-mux-meson-g12a.c struct g12a_ephy_pll *pll; pll 271 drivers/net/phy/mdio-mux-meson-g12a.c pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); pll 272 drivers/net/phy/mdio-mux-meson-g12a.c if (!pll) pll 286 drivers/net/phy/mdio-mux-meson-g12a.c pll->base = priv->regs; pll 287 drivers/net/phy/mdio-mux-meson-g12a.c pll->hw.init = &init; pll 289 drivers/net/phy/mdio-mux-meson-g12a.c clk = devm_clk_register(dev, &pll->hw); pll 296 drivers/net/phy/mdio-mux-meson-g12a.c priv->pll = clk; pll 359 drivers/net/phy/mdio-mux-meson-g12a.c clk_disable_unprepare(priv->pll); pll 896 drivers/net/wireless/ath/ath9k/ar5008_phy.c u32 pll; pll 898 drivers/net/wireless/ath/ath9k/ar5008_phy.c pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); pll 901 drivers/net/wireless/ath/ath9k/ar5008_phy.c pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); pll 903 drivers/net/wireless/ath/ath9k/ar5008_phy.c pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); pll 906 drivers/net/wireless/ath/ath9k/ar5008_phy.c pll |= SM(0x50, AR_RTC_9160_PLL_DIV); pll 908 drivers/net/wireless/ath/ath9k/ar5008_phy.c pll |= SM(0x58, AR_RTC_9160_PLL_DIV); pll 910 drivers/net/wireless/ath/ath9k/ar5008_phy.c return pll; pll 916 drivers/net/wireless/ath/ath9k/ar5008_phy.c u32 pll; pll 918 drivers/net/wireless/ath/ath9k/ar5008_phy.c pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; pll 921 drivers/net/wireless/ath/ath9k/ar5008_phy.c pll |= SM(0x1, AR_RTC_PLL_CLKSEL); pll 923 drivers/net/wireless/ath/ath9k/ar5008_phy.c pll |= SM(0x2, AR_RTC_PLL_CLKSEL); pll 926 drivers/net/wireless/ath/ath9k/ar5008_phy.c pll |= SM(0xa, AR_RTC_PLL_DIV); pll 928 drivers/net/wireless/ath/ath9k/ar5008_phy.c pll |= SM(0xb, AR_RTC_PLL_DIV); pll 930 drivers/net/wireless/ath/ath9k/ar5008_phy.c return pll; pll 309 drivers/net/wireless/ath/ath9k/ar9002_phy.c u32 pll; pll 320 drivers/net/wireless/ath/ath9k/ar9002_phy.c pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV); pll 321 drivers/net/wireless/ath/ath9k/ar9002_phy.c pll |= SM(pll_div, AR_RTC_9160_PLL_DIV); pll 324 drivers/net/wireless/ath/ath9k/ar9002_phy.c pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); pll 326 drivers/net/wireless/ath/ath9k/ar9002_phy.c pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); pll 328 drivers/net/wireless/ath/ath9k/ar9002_phy.c return pll; pll 588 drivers/net/wireless/ath/ath9k/ar9003_phy.c u32 pll; pll 590 drivers/net/wireless/ath/ath9k/ar9003_phy.c pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV); pll 593 drivers/net/wireless/ath/ath9k/ar9003_phy.c pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL); pll 595 drivers/net/wireless/ath/ath9k/ar9003_phy.c pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL); pll 597 drivers/net/wireless/ath/ath9k/ar9003_phy.c pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT); pll 599 drivers/net/wireless/ath/ath9k/ar9003_phy.c return pll; pll 605 drivers/net/wireless/ath/ath9k/ar9003_phy.c u32 pll; pll 607 drivers/net/wireless/ath/ath9k/ar9003_phy.c pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); pll 610 drivers/net/wireless/ath/ath9k/ar9003_phy.c pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); pll 612 drivers/net/wireless/ath/ath9k/ar9003_phy.c pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); pll 614 drivers/net/wireless/ath/ath9k/ar9003_phy.c pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); pll 616 drivers/net/wireless/ath/ath9k/ar9003_phy.c return pll; pll 764 drivers/net/wireless/ath/ath9k/hw.c u32 pll; pll 766 drivers/net/wireless/ath/ath9k/hw.c pll = ath9k_hw_compute_pll_control(ah, chan); pll 819 drivers/net/wireless/ath/ath9k/hw.c pll | AR_RTC_9300_PLL_BYPASS); pll 837 drivers/net/wireless/ath/ath9k/hw.c pll | AR_RTC_9300_SOC_PLL_BYPASS); pll 914 drivers/net/wireless/ath/ath9k/hw.c pll |= 0x40000; pll 915 drivers/net/wireless/ath/ath9k/hw.c REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); pll 256 drivers/phy/tegra/xusb-tegra210.c err = clk_prepare_enable(pcie->pll); pll 449 drivers/phy/tegra/xusb-tegra210.c clk_disable_unprepare(pcie->pll); pll 466 drivers/phy/tegra/xusb-tegra210.c clk_disable_unprepare(pcie->pll); pll 485 drivers/phy/tegra/xusb-tegra210.c err = clk_prepare_enable(sata->pll); pll 691 drivers/phy/tegra/xusb-tegra210.c clk_disable_unprepare(sata->pll); pll 708 drivers/phy/tegra/xusb-tegra210.c clk_disable_unprepare(sata->pll); pll 1543 drivers/phy/tegra/xusb-tegra210.c pcie->pll = devm_clk_get(&pad->dev, "pll"); pll 1544 drivers/phy/tegra/xusb-tegra210.c if (IS_ERR(pcie->pll)) { pll 1545 drivers/phy/tegra/xusb-tegra210.c err = PTR_ERR(pcie->pll); pll 230 drivers/phy/tegra/xusb.h struct clk *pll; pll 245 drivers/phy/tegra/xusb.h struct clk *pll; pll 58 drivers/staging/sm750fb/ddk750_chip.c struct pll_value pll; pll 69 drivers/staging/sm750fb/ddk750_chip.c pll.inputFreq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */ pll 70 drivers/staging/sm750fb/ddk750_chip.c pll.clockType = MXCLK_PLL; pll 79 drivers/staging/sm750fb/ddk750_chip.c actual_mx_clk = sm750_calc_pll_value(frequency, &pll); pll 82 drivers/staging/sm750fb/ddk750_chip.c poke32(MXCLK_PLL_CTRL, sm750_format_pll_reg(&pll)); pll 314 drivers/staging/sm750fb/ddk750_chip.c struct pll_value *pll) pll 340 drivers/staging/sm750fb/ddk750_chip.c input = pll->inputFreq / 1000; pll 346 drivers/staging/sm750fb/ddk750_chip.c if (pll->clockType == MXCLK_PLL) pll 368 drivers/staging/sm750fb/ddk750_chip.c tmp_clock = pll->inputFreq * M / N / X; pll 371 drivers/staging/sm750fb/ddk750_chip.c pll->M = M; pll 372 drivers/staging/sm750fb/ddk750_chip.c pll->N = N; pll 373 drivers/staging/sm750fb/ddk750_chip.c pll->POD = 0; pll 375 drivers/staging/sm750fb/ddk750_chip.c pll->POD = d - max_OD; pll 376 drivers/staging/sm750fb/ddk750_chip.c pll->OD = d - pll->POD; pll 97 drivers/staging/sm750fb/ddk750_chip.h unsigned int sm750_calc_pll_value(unsigned int request, struct pll_value *pll); pll 78 drivers/staging/sm750fb/ddk750_mode.c struct pll_value *pll) pll 84 drivers/staging/sm750fb/ddk750_mode.c if (pll->clockType == SECONDARY_PLL) { pll 86 drivers/staging/sm750fb/ddk750_mode.c poke32(CRT_PLL_CTRL, sm750_format_pll_reg(pll)); pll 137 drivers/staging/sm750fb/ddk750_mode.c } else if (pll->clockType == PRIMARY_PLL) { pll 140 drivers/staging/sm750fb/ddk750_mode.c poke32(PANEL_PLL_CTRL, sm750_format_pll_reg(pll)); pll 211 drivers/staging/sm750fb/ddk750_mode.c struct pll_value pll; pll 214 drivers/staging/sm750fb/ddk750_mode.c pll.inputFreq = DEFAULT_INPUT_CLOCK; pll 215 drivers/staging/sm750fb/ddk750_mode.c pll.clockType = clock; pll 217 drivers/staging/sm750fb/ddk750_mode.c uiActualPixelClk = sm750_calc_pll_value(parm->pixel_clock, &pll); pll 223 drivers/staging/sm750fb/ddk750_mode.c programModeRegisters(parm, &pll); pll 444 drivers/video/fbdev/aty/aty128fb.c struct aty128_pll pll; pll 1326 drivers/video/fbdev/aty/aty128fb.c static void aty128_set_pll(struct aty128_pll *pll, pll 1348 drivers/video/fbdev/aty/aty128fb.c div3 |= pll->feedback_divider; pll 1350 drivers/video/fbdev/aty/aty128fb.c div3 |= post_conv[pll->post_divider] << 16; pll 1366 drivers/video/fbdev/aty/aty128fb.c static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll, pll 1388 drivers/video/fbdev/aty/aty128fb.c pll->post_divider = post_dividers[i]; pll 1400 drivers/video/fbdev/aty/aty128fb.c pll->feedback_divider = round_div(n, d); pll 1401 drivers/video/fbdev/aty/aty128fb.c pll->vclk = vclk; pll 1404 drivers/video/fbdev/aty/aty128fb.c "vclk_per: %d\n", pll->post_divider, pll 1405 drivers/video/fbdev/aty/aty128fb.c pll->feedback_divider, vclk, output_freq, pll 1412 drivers/video/fbdev/aty/aty128fb.c static int aty128_pll_to_var(const struct aty128_pll *pll, pll 1415 drivers/video/fbdev/aty/aty128fb.c var->pixclock = 100000000 / pll->vclk; pll 1430 drivers/video/fbdev/aty/aty128fb.c const struct aty128_pll *pll, pll 1445 drivers/video/fbdev/aty/aty128fb.c d = pll->vclk * bpp; pll 1518 drivers/video/fbdev/aty/aty128fb.c aty128_set_pll(&par->pll, par); pll 1564 drivers/video/fbdev/aty/aty128fb.c struct aty128_pll pll; pll 1570 drivers/video/fbdev/aty/aty128fb.c if ((err = aty128_var_to_pll(var->pixclock, &pll, par))) pll 1573 drivers/video/fbdev/aty/aty128fb.c if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par))) pll 1577 drivers/video/fbdev/aty/aty128fb.c par->pll = pll; pll 1593 drivers/video/fbdev/aty/aty128fb.c if ((err = aty128_pll_to_var(&par->pll, var))) pll 137 drivers/video/fbdev/aty/atyfb.h union aty_pll pll; pll 302 drivers/video/fbdev/aty/atyfb.h const union aty_pll * pll, u32 bpp, u32 accel); pll 317 drivers/video/fbdev/aty/atyfb.h int (*var_to_pll) (const struct fb_info * info, u32 vclk_per, u32 bpp, union aty_pll * pll); pll 318 drivers/video/fbdev/aty/atyfb.h u32 (*pll_to_var) (const struct fb_info * info, const union aty_pll * pll); pll 319 drivers/video/fbdev/aty/atyfb.h void (*set_pll) (const struct fb_info * info, const union aty_pll * pll); pll 320 drivers/video/fbdev/aty/atyfb.h void (*get_pll) (const struct fb_info *info, union aty_pll * pll); pll 321 drivers/video/fbdev/aty/atyfb.h int (*init_pll) (const struct fb_info * info, union aty_pll * pll); pll 322 drivers/video/fbdev/aty/atyfb.h void (*resume_pll)(const struct fb_info *info, union aty_pll *pll); pll 334 drivers/video/fbdev/aty/atyfb.h extern void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll); pll 305 drivers/video/fbdev/aty/atyfb_base.c static int pll; pll 368 drivers/video/fbdev/aty/atyfb_base.c int pll, mclk, xclk, ecp_max; pll 455 drivers/video/fbdev/aty/atyfb_base.c par->pll_limits.pll_max = aty_chips[i].pll; pll 583 drivers/video/fbdev/aty/atyfb_base.c par->pll.ct.xres = 0; pll 587 drivers/video/fbdev/aty/atyfb_base.c par->pll.ct.xres = var->xres; pll 1311 drivers/video/fbdev/aty/atyfb_base.c var->bits_per_pixel, &par->pll); pll 1330 drivers/video/fbdev/aty/atyfb_base.c par->dac_ops->set_dac(info, &par->pll, pll 1332 drivers/video/fbdev/aty/atyfb_base.c par->pll_ops->set_pll(info, &par->pll); pll 1336 drivers/video/fbdev/aty/atyfb_base.c pixclock_in_ps = par->pll_ops->pll_to_var(info, &par->pll); pll 1523 drivers/video/fbdev/aty/atyfb_base.c union aty_pll pll; pll 1526 drivers/video/fbdev/aty/atyfb_base.c memcpy(&pll, &par->pll, sizeof(pll)); pll 1540 drivers/video/fbdev/aty/atyfb_base.c var->bits_per_pixel, &pll); pll 1551 drivers/video/fbdev/aty/atyfb_base.c var->pixclock = par->pll_ops->pll_to_var(info, &pll); pll 1845 drivers/video/fbdev/aty/atyfb_base.c union aty_pll *pll = &par->pll; pll 1846 drivers/video/fbdev/aty/atyfb_base.c u32 dsp_config = pll->ct.dsp_config; pll 1847 drivers/video/fbdev/aty/atyfb_base.c u32 dsp_on_off = pll->ct.dsp_on_off; pll 1849 drivers/video/fbdev/aty/atyfb_base.c clk.pll_ref_div = pll->ct.pll_ref_div; pll 1850 drivers/video/fbdev/aty/atyfb_base.c clk.mclk_fb_div = pll->ct.mclk_fb_div; pll 1851 drivers/video/fbdev/aty/atyfb_base.c clk.mclk_post_div = pll->ct.mclk_post_div_real; pll 1852 drivers/video/fbdev/aty/atyfb_base.c clk.mclk_fb_mult = pll->ct.mclk_fb_mult; pll 1853 drivers/video/fbdev/aty/atyfb_base.c clk.xclk_post_div = pll->ct.xclk_post_div_real; pll 1854 drivers/video/fbdev/aty/atyfb_base.c clk.vclk_fb_div = pll->ct.vclk_fb_div; pll 1855 drivers/video/fbdev/aty/atyfb_base.c clk.vclk_post_div = pll->ct.vclk_post_div_real; pll 1870 drivers/video/fbdev/aty/atyfb_base.c union aty_pll *pll = &par->pll; pll 1875 drivers/video/fbdev/aty/atyfb_base.c pll->ct.pll_ref_div = clk.pll_ref_div; pll 1876 drivers/video/fbdev/aty/atyfb_base.c pll->ct.mclk_fb_div = clk.mclk_fb_div; pll 1877 drivers/video/fbdev/aty/atyfb_base.c pll->ct.mclk_post_div_real = clk.mclk_post_div; pll 1878 drivers/video/fbdev/aty/atyfb_base.c pll->ct.mclk_fb_mult = clk.mclk_fb_mult; pll 1879 drivers/video/fbdev/aty/atyfb_base.c pll->ct.xclk_post_div_real = clk.xclk_post_div; pll 1880 drivers/video/fbdev/aty/atyfb_base.c pll->ct.vclk_fb_div = clk.vclk_fb_div; pll 1881 drivers/video/fbdev/aty/atyfb_base.c pll->ct.vclk_post_div_real = clk.vclk_post_div; pll 1882 drivers/video/fbdev/aty/atyfb_base.c pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) | pll 1885 drivers/video/fbdev/aty/atyfb_base.c pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | pll 1888 drivers/video/fbdev/aty/atyfb_base.c aty_set_pll_ct(info, pll); pll 2105 drivers/video/fbdev/aty/atyfb_base.c par->pll_ops->resume_pll(info, &par->pll); pll 2418 drivers/video/fbdev/aty/atyfb_base.c if (pll) pll 2419 drivers/video/fbdev/aty/atyfb_base.c par->pll_limits.pll_max = pll; pll 2580 drivers/video/fbdev/aty/atyfb_base.c par->pll_ops->init_pll(info, &par->pll); pll 2582 drivers/video/fbdev/aty/atyfb_base.c par->pll_ops->resume_pll(info, &par->pll); pll 3818 drivers/video/fbdev/aty/atyfb_base.c pll = simple_strtoul(this_opt + 4, NULL, 0); pll 3973 drivers/video/fbdev/aty/atyfb_base.c module_param(pll, int, 0); pll 3974 drivers/video/fbdev/aty/atyfb_base.c MODULE_PARM_DESC(pll, "int: override video clock"); pll 18 drivers/video/fbdev/aty/mach64_ct.c static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll); pll 19 drivers/video/fbdev/aty/mach64_ct.c static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll); pll 20 drivers/video/fbdev/aty/mach64_ct.c static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll); pll 21 drivers/video/fbdev/aty/mach64_ct.c static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll); pll 120 drivers/video/fbdev/aty/mach64_ct.c static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll) pll 127 drivers/video/fbdev/aty/mach64_ct.c multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real; pll 128 drivers/video/fbdev/aty/mach64_ct.c divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; pll 130 drivers/video/fbdev/aty/mach64_ct.c ras_multiplier = pll->xclkmaxrasdelay; pll 136 drivers/video/fbdev/aty/mach64_ct.c vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */ pll 142 drivers/video/fbdev/aty/mach64_ct.c if (pll->xres != 0) { pll 146 drivers/video/fbdev/aty/mach64_ct.c divider = divider * pll->xres & ~7; pll 149 drivers/video/fbdev/aty/mach64_ct.c ras_divider = ras_divider * pll->xres & ~7; pll 160 drivers/video/fbdev/aty/mach64_ct.c tmp = ((multiplier * pll->fifo_size) << vshift) / divider; pll 173 drivers/video/fbdev/aty/mach64_ct.c dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider - pll 184 drivers/video/fbdev/aty/mach64_ct.c dsp_on = dsp_on + (tmp * 2) + (pll->xclkpagefaultdelay << xshift); pll 200 drivers/video/fbdev/aty/mach64_ct.c pll->dsp_on_off = (dsp_on << 16) + dsp_off; pll 201 drivers/video/fbdev/aty/mach64_ct.c pll->dsp_config = (dsp_precision << 20) | (pll->dsp_loop_latency << 16) | dsp_xclks; pll 204 drivers/video/fbdev/aty/mach64_ct.c __func__, pll->dsp_config, pll->dsp_on_off); pll 209 drivers/video/fbdev/aty/mach64_ct.c static int aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll_ct *pll) pll 216 drivers/video/fbdev/aty/mach64_ct.c q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per; pll 221 drivers/video/fbdev/aty/mach64_ct.c pll->vclk_post_div = (q < 128*8); pll 222 drivers/video/fbdev/aty/mach64_ct.c pll->vclk_post_div += (q < 64*8); pll 223 drivers/video/fbdev/aty/mach64_ct.c pll->vclk_post_div += (q < 32*8); pll 225 drivers/video/fbdev/aty/mach64_ct.c pll->vclk_post_div_real = aty_postdividers[pll->vclk_post_div]; pll 227 drivers/video/fbdev/aty/mach64_ct.c pll->vclk_fb_div = q * pll->vclk_post_div_real / 8; pll 228 drivers/video/fbdev/aty/mach64_ct.c pllvclk = (1000000 * 2 * pll->vclk_fb_div) / pll 229 drivers/video/fbdev/aty/mach64_ct.c (par->ref_clk_per * pll->pll_ref_div); pll 232 drivers/video/fbdev/aty/mach64_ct.c __func__, pllvclk, pllvclk / pll->vclk_post_div_real); pll 234 drivers/video/fbdev/aty/mach64_ct.c pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */ pll 238 drivers/video/fbdev/aty/mach64_ct.c int ecp = pllvclk / pll->vclk_post_div_real; pll 245 drivers/video/fbdev/aty/mach64_ct.c pll->pll_vclk_cntl |= ecp_div << 4; pll 251 drivers/video/fbdev/aty/mach64_ct.c static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) pll 256 drivers/video/fbdev/aty/mach64_ct.c if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct))) pll 258 drivers/video/fbdev/aty/mach64_ct.c if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct))) pll 264 drivers/video/fbdev/aty/mach64_ct.c static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll) pll 268 drivers/video/fbdev/aty/mach64_ct.c ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2; pll 270 drivers/video/fbdev/aty/mach64_ct.c if(pll->ct.xres > 0) { pll 272 drivers/video/fbdev/aty/mach64_ct.c ret /= pll->ct.xres; pll 281 drivers/video/fbdev/aty/mach64_ct.c void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll) pll 292 drivers/video/fbdev/aty/mach64_ct.c pll->ct.pll_ext_cntl, pll->ct.pll_gen_cntl, pll->ct.pll_vclk_cntl); pll 296 drivers/video/fbdev/aty/mach64_ct.c par->clk_wr_offset, pll->ct.vclk_fb_div, pll 297 drivers/video/fbdev/aty/mach64_ct.c pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real); pll 314 drivers/video/fbdev/aty/mach64_ct.c aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par); pll 320 drivers/video/fbdev/aty/mach64_ct.c tmp |= ((pll->ct.vclk_post_div & 0x03U) << tmp2); pll 327 drivers/video/fbdev/aty/mach64_ct.c tmp |= pll->ct.pll_ext_cntl; pll 332 drivers/video/fbdev/aty/mach64_ct.c aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par); pll 334 drivers/video/fbdev/aty/mach64_ct.c aty_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par); pll 337 drivers/video/fbdev/aty/mach64_ct.c aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par); pll 340 drivers/video/fbdev/aty/mach64_ct.c aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par); pll 341 drivers/video/fbdev/aty/mach64_ct.c aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par); pll 359 drivers/video/fbdev/aty/mach64_ct.c aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par); pll 360 drivers/video/fbdev/aty/mach64_ct.c aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par); pll 377 drivers/video/fbdev/aty/mach64_ct.c static void aty_get_pll_ct(const struct fb_info *info, union aty_pll *pll) pll 384 drivers/video/fbdev/aty/mach64_ct.c pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U; pll 386 drivers/video/fbdev/aty/mach64_ct.c pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU; pll 387 drivers/video/fbdev/aty/mach64_ct.c pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU; pll 388 drivers/video/fbdev/aty/mach64_ct.c pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); pll 389 drivers/video/fbdev/aty/mach64_ct.c pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par); pll 391 drivers/video/fbdev/aty/mach64_ct.c pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par); pll 392 drivers/video/fbdev/aty/mach64_ct.c pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par); pll 395 drivers/video/fbdev/aty/mach64_ct.c pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par); pll 396 drivers/video/fbdev/aty/mach64_ct.c pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par); pll 400 drivers/video/fbdev/aty/mach64_ct.c static int aty_init_pll_ct(const struct fb_info *info, union aty_pll *pll) pll 409 drivers/video/fbdev/aty/mach64_ct.c pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par); pll 410 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclk_post_div = pll->ct.pll_ext_cntl & 0x07; pll 411 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclk_ref_div = 1; pll 412 drivers/video/fbdev/aty/mach64_ct.c switch (pll->ct.xclk_post_div) { pll 417 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclk_ref_div = 3; pll 418 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclk_post_div = 0; pll 422 drivers/video/fbdev/aty/mach64_ct.c printk(KERN_CRIT "atyfb: Unsupported xclk source: %d.\n", pll->ct.xclk_post_div); pll 425 drivers/video/fbdev/aty/mach64_ct.c pll->ct.mclk_fb_mult = 2; pll 426 drivers/video/fbdev/aty/mach64_ct.c if(pll->ct.pll_ext_cntl & PLL_MFB_TIMES_4_2B) { pll 427 drivers/video/fbdev/aty/mach64_ct.c pll->ct.mclk_fb_mult = 4; pll 428 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclk_post_div -= 1; pll 433 drivers/video/fbdev/aty/mach64_ct.c __func__, pll->ct.mclk_fb_mult, pll->ct.xclk_post_div); pll 439 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclkpagefaultdelay = ((memcntl & 0xc00) >> 10) + ((memcntl & 0x1000) >> 12) + trp + 2; pll 440 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclkmaxrasdelay = ((memcntl & 0x70000) >> 16) + trp + 2; pll 443 drivers/video/fbdev/aty/mach64_ct.c pll->ct.fifo_size = 32; pll 445 drivers/video/fbdev/aty/mach64_ct.c pll->ct.fifo_size = 24; pll 446 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclkpagefaultdelay += 2; pll 447 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclkmaxrasdelay += 3; pll 453 drivers/video/fbdev/aty/mach64_ct.c pll->ct.dsp_loop_latency = 10; pll 455 drivers/video/fbdev/aty/mach64_ct.c pll->ct.dsp_loop_latency = 8; pll 456 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclkpagefaultdelay += 2; pll 462 drivers/video/fbdev/aty/mach64_ct.c pll->ct.dsp_loop_latency = 9; pll 464 drivers/video/fbdev/aty/mach64_ct.c pll->ct.dsp_loop_latency = 8; pll 465 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclkpagefaultdelay += 1; pll 470 drivers/video/fbdev/aty/mach64_ct.c pll->ct.dsp_loop_latency = 11; pll 472 drivers/video/fbdev/aty/mach64_ct.c pll->ct.dsp_loop_latency = 10; pll 473 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclkpagefaultdelay += 1; pll 477 drivers/video/fbdev/aty/mach64_ct.c pll->ct.dsp_loop_latency = 8; pll 478 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclkpagefaultdelay += 3; pll 481 drivers/video/fbdev/aty/mach64_ct.c pll->ct.dsp_loop_latency = 11; pll 482 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclkpagefaultdelay += 3; pll 486 drivers/video/fbdev/aty/mach64_ct.c if (pll->ct.xclkmaxrasdelay <= pll->ct.xclkpagefaultdelay) pll 487 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclkmaxrasdelay = pll->ct.xclkpagefaultdelay + 1; pll 496 drivers/video/fbdev/aty/mach64_ct.c pll->ct.dsp_loop_latency = (dsp_config & DSP_LOOP_LATENCY) >> 16; pll 505 drivers/video/fbdev/aty/mach64_ct.c pll->ct.fifo_size = 32; pll 507 drivers/video/fbdev/aty/mach64_ct.c pll->ct.fifo_size = 24; pll 514 drivers/video/fbdev/aty/mach64_ct.c pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); pll 516 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclk_post_div_real = aty_postdividers[pll_ext_cntl & 0x07]; pll 520 drivers/video/fbdev/aty/mach64_ct.c pll->ct.mclk_fb_div = mclk_fb_div; pll 524 drivers/video/fbdev/aty/mach64_ct.c pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per; pll 527 drivers/video/fbdev/aty/mach64_ct.c q = par->ref_clk_per * pll->ct.pll_ref_div * 8 / pll 528 drivers/video/fbdev/aty/mach64_ct.c (pll->ct.mclk_fb_mult * par->xclk_per); pll 538 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclk_post_div_real = aty_postdividers[xpost_div]; pll 539 drivers/video/fbdev/aty/mach64_ct.c pll->ct.mclk_fb_div = q * pll->ct.xclk_post_div_real / 8; pll 544 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclk_post_div = xpost_div; pll 545 drivers/video/fbdev/aty/mach64_ct.c pll->ct.xclk_ref_div = 1; pll 550 drivers/video/fbdev/aty/mach64_ct.c pllmclk = (1000000 * pll->ct.mclk_fb_mult * pll->ct.mclk_fb_div) / pll 551 drivers/video/fbdev/aty/mach64_ct.c (par->ref_clk_per * pll->ct.pll_ref_div); pll 553 drivers/video/fbdev/aty/mach64_ct.c __func__, pllmclk, pllmclk / pll->ct.xclk_post_div_real); pll 557 drivers/video/fbdev/aty/mach64_ct.c pll->ct.pll_gen_cntl = OSC_EN; pll 559 drivers/video/fbdev/aty/mach64_ct.c pll->ct.pll_gen_cntl = OSC_EN | DLL_PWDN /* | FORCE_DCLK_TRI_STATE */; pll 562 drivers/video/fbdev/aty/mach64_ct.c pll->ct.pll_ext_cntl = 0; pll 564 drivers/video/fbdev/aty/mach64_ct.c pll->ct.pll_ext_cntl = xpost_div; pll 566 drivers/video/fbdev/aty/mach64_ct.c if (pll->ct.mclk_fb_mult == 4) pll 567 drivers/video/fbdev/aty/mach64_ct.c pll->ct.pll_ext_cntl |= PLL_MFB_TIMES_4_2B; pll 570 drivers/video/fbdev/aty/mach64_ct.c pll->ct.pll_gen_cntl |= (xpost_div << 4); /* mclk == xclk */ pll 576 drivers/video/fbdev/aty/mach64_ct.c pll->ct.pll_gen_cntl |= (6 << 4); /* mclk == sclk */ pll 578 drivers/video/fbdev/aty/mach64_ct.c q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per; pll 588 drivers/video/fbdev/aty/mach64_ct.c pll->ct.sclk_fb_div = q * sclk_post_div_real / 8; pll 589 drivers/video/fbdev/aty/mach64_ct.c pll->ct.spll_cntl2 = mpost_div << 4; pll 591 drivers/video/fbdev/aty/mach64_ct.c pllsclk = (1000000 * 2 * pll->ct.sclk_fb_div) / pll 592 drivers/video/fbdev/aty/mach64_ct.c (par->ref_clk_per * pll->ct.pll_ref_div); pll 599 drivers/video/fbdev/aty/mach64_ct.c pll->ct.ext_vpll_cntl = aty_ld_pll_ct(EXT_VPLL_CNTL, par); pll 600 drivers/video/fbdev/aty/mach64_ct.c pll->ct.ext_vpll_cntl &= ~(EXT_VPLL_EN | EXT_VPLL_VGA_EN | EXT_VPLL_INSYNC); pll 606 drivers/video/fbdev/aty/mach64_ct.c union aty_pll *pll) pll 618 drivers/video/fbdev/aty/mach64_ct.c aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par); pll 619 drivers/video/fbdev/aty/mach64_ct.c aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par); pll 627 drivers/video/fbdev/aty/mach64_ct.c aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par); pll 628 drivers/video/fbdev/aty/mach64_ct.c aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par); pll 629 drivers/video/fbdev/aty/mach64_ct.c aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par); pll 630 drivers/video/fbdev/aty/mach64_ct.c aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par); pll 631 drivers/video/fbdev/aty/mach64_ct.c aty_st_pll_ct(EXT_VPLL_CNTL, pll->ct.ext_vpll_cntl, par); pll 81 drivers/video/fbdev/aty/mach64_gx.c const union aty_pll *pll, u32 bpp, u32 accel) pll 124 drivers/video/fbdev/aty/mach64_gx.c u32 bpp, union aty_pll *pll) pll 154 drivers/video/fbdev/aty/mach64_gx.c pll->ibm514.m = RGB514_clocks[i].m; pll 155 drivers/video/fbdev/aty/mach64_gx.c pll->ibm514.n = RGB514_clocks[i].n; pll 162 drivers/video/fbdev/aty/mach64_gx.c const union aty_pll *pll) pll 167 drivers/video/fbdev/aty/mach64_gx.c df = pll->ibm514.m >> 6; pll 168 drivers/video/fbdev/aty/mach64_gx.c vco_div_count = pll->ibm514.m & 0x3f; pll 169 drivers/video/fbdev/aty/mach64_gx.c ref_div_count = pll->ibm514.n; pll 176 drivers/video/fbdev/aty/mach64_gx.c const union aty_pll *pll) pll 186 drivers/video/fbdev/aty/mach64_gx.c aty_st_514(0x20, pll->ibm514.m, par); /* F0 / M0 */ pll 187 drivers/video/fbdev/aty/mach64_gx.c aty_st_514(0x21, pll->ibm514.n, par); /* F1 / N0 */ pll 206 drivers/video/fbdev/aty/mach64_gx.c const union aty_pll *pll, u32 bpp, pll 289 drivers/video/fbdev/aty/mach64_gx.c const union aty_pll *pll, u32 bpp, pll 297 drivers/video/fbdev/aty/mach64_gx.c dotClock = 100000000 / pll->ics2595.period_in_ps; pll 342 drivers/video/fbdev/aty/mach64_gx.c u32 bpp, union aty_pll *pll) pll 392 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.program_bits = program_bits; pll 393 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.locationAddr = 0; pll 394 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.post_divider = post_divider; pll 395 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.period_in_ps = vclk_per; pll 401 drivers/video/fbdev/aty/mach64_gx.c const union aty_pll *pll) pll 403 drivers/video/fbdev/aty/mach64_gx.c return (pll->ics2595.period_in_ps); /* default for now */ pll 430 drivers/video/fbdev/aty/mach64_gx.c const union aty_pll *pll) pll 450 drivers/video/fbdev/aty/mach64_gx.c program_bits = pll->ics2595.program_bits; pll 451 drivers/video/fbdev/aty/mach64_gx.c locationAddr = pll->ics2595.locationAddr; pll 482 drivers/video/fbdev/aty/mach64_gx.c ((pll->ics2595.locationAddr & 0x0F) | CLOCK_STROBE), par); pll 498 drivers/video/fbdev/aty/mach64_gx.c u32 bpp, union aty_pll *pll) pll 558 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.program_bits = program_bits; pll 559 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.locationAddr = 0; pll 560 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.post_divider = divider; /* fuer nix */ pll 561 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.period_in_ps = vclk_per; pll 567 drivers/video/fbdev/aty/mach64_gx.c const union aty_pll *pll) pll 569 drivers/video/fbdev/aty/mach64_gx.c return (pll->ics2595.period_in_ps); /* default for now */ pll 573 drivers/video/fbdev/aty/mach64_gx.c const union aty_pll *pll) pll 585 drivers/video/fbdev/aty/mach64_gx.c program_bits = pll->ics2595.program_bits; pll 586 drivers/video/fbdev/aty/mach64_gx.c locationAddr = pll->ics2595.locationAddr; pll 614 drivers/video/fbdev/aty/mach64_gx.c u32 bpp, union aty_pll *pll) pll 677 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.program_bits = program_bits; pll 678 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.locationAddr = 0; pll 679 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.post_divider = 0; pll 680 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.period_in_ps = vclk_per; pll 686 drivers/video/fbdev/aty/mach64_gx.c const union aty_pll *pll) pll 688 drivers/video/fbdev/aty/mach64_gx.c return (pll->ics2595.period_in_ps); /* default for now */ pll 692 drivers/video/fbdev/aty/mach64_gx.c const union aty_pll *pll) pll 705 drivers/video/fbdev/aty/mach64_gx.c program_bits = pll->ics2595.program_bits; pll 706 drivers/video/fbdev/aty/mach64_gx.c locationAddr = pll->ics2595.locationAddr; pll 738 drivers/video/fbdev/aty/mach64_gx.c u32 bpp, union aty_pll *pll) pll 795 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.program_bits = program_bits; pll 796 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.locationAddr = 0; pll 797 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.post_divider = divider; /* fuer nix */ pll 798 drivers/video/fbdev/aty/mach64_gx.c pll->ics2595.period_in_ps = vclk_per; pll 804 drivers/video/fbdev/aty/mach64_gx.c const union aty_pll *pll) pll 806 drivers/video/fbdev/aty/mach64_gx.c return (pll->ics2595.period_in_ps); /* default for now */ pll 810 drivers/video/fbdev/aty/mach64_gx.c const union aty_pll *pll) pll 823 drivers/video/fbdev/aty/mach64_gx.c program_bits = pll->ics2595.program_bits; pll 824 drivers/video/fbdev/aty/mach64_gx.c locationAddr = pll->ics2595.locationAddr; pll 885 drivers/video/fbdev/aty/mach64_gx.c const union aty_pll *pll, u32 bpp, pll 561 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_clk = (*val) / 10; pll 565 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = (*val) / 10; pll 569 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.mclk = (*val) / 10; pll 701 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_clk = xtal; pll 702 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_div = ref_div; pll 703 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = sclk; pll 704 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.mclk = mclk; pll 722 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ppll_max = 35000; pll 723 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ppll_min = 12000; pll 724 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.mclk = 23000; pll 725 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = 23000; pll 726 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_clk = 2700; pll 733 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ppll_max = 35000; pll 734 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ppll_min = 12000; pll 735 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.mclk = 27500; pll 736 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = 27500; pll 737 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_clk = 2700; pll 743 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ppll_max = 35000; pll 744 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ppll_min = 12000; pll 745 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.mclk = 25000; pll 746 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = 25000; pll 747 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_clk = 2700; pll 753 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ppll_max = 40000; pll 754 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ppll_min = 20000; pll 755 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.mclk = 27000; pll 756 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = 27000; pll 757 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_clk = 2700; pll 764 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ppll_max = 35000; pll 765 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ppll_min = 12000; pll 766 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.mclk = 16600; pll 767 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = 16600; pll 768 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_clk = 2700; pll 771 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; pll 791 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08); pll 792 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a); pll 793 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e); pll 794 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10); pll 795 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12); pll 796 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16); pll 822 drivers/video/fbdev/aty/radeon_base.c if (rinfo->pll.mclk == 0) pll 823 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.mclk = 20000; pll 824 drivers/video/fbdev/aty/radeon_base.c if (rinfo->pll.sclk == 0) pll 825 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = 20000; pll 828 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100, pll 829 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_div, pll 830 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.mclk / 100, rinfo->pll.mclk % 100, pll 831 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk / 100, rinfo->pll.sclk % 100); pll 832 drivers/video/fbdev/aty/radeon_base.c printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max); pll 1598 drivers/video/fbdev/aty/radeon_base.c if (freq > rinfo->pll.ppll_max) pll 1599 drivers/video/fbdev/aty/radeon_base.c freq = rinfo->pll.ppll_max; pll 1600 drivers/video/fbdev/aty/radeon_base.c if (freq*12 < rinfo->pll.ppll_min) pll 1601 drivers/video/fbdev/aty/radeon_base.c freq = rinfo->pll.ppll_min / 12; pll 1603 drivers/video/fbdev/aty/radeon_base.c freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max); pll 1612 drivers/video/fbdev/aty/radeon_base.c if (pll_output_freq >= rinfo->pll.ppll_min && pll 1613 drivers/video/fbdev/aty/radeon_base.c pll_output_freq <= rinfo->pll.ppll_max) pll 1624 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_div, rinfo->pll.ref_clk, pll 1634 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_div, rinfo->pll.ref_clk, pll 1637 drivers/video/fbdev/aty/radeon_base.c fb_div = round_div(rinfo->pll.ref_div*pll_output_freq, pll 1638 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_clk); pll 1639 drivers/video/fbdev/aty/radeon_base.c regs->ppll_ref_div = rinfo->pll.ref_div; pll 669 drivers/video/fbdev/aty/radeon_monitor.c rinfo->panel_info.ref_divider = rinfo->pll.ref_div; pll 1651 drivers/video/fbdev/aty/radeon_pm.c tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div; pll 2196 drivers/video/fbdev/aty/radeon_pm.c OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div); pll 2453 drivers/video/fbdev/aty/radeon_pm.c tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div; pll 342 drivers/video/fbdev/aty/radeonfb.h struct pll_info pll; pll 381 drivers/video/fbdev/core/svgalib.c int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node) pll 388 drivers/video/fbdev/core/svgalib.c ar = pll->r_max; pll 398 drivers/video/fbdev/core/svgalib.c while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) { pll 404 drivers/video/fbdev/core/svgalib.c if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max)) pll 412 drivers/video/fbdev/core/svgalib.c am = pll->m_min; pll 413 drivers/video/fbdev/core/svgalib.c an = pll->n_min; pll 415 drivers/video/fbdev/core/svgalib.c while ((am <= pll->m_max) && (an <= pll->n_max)) { pll 416 drivers/video/fbdev/core/svgalib.c f_current = (pll->f_base * am) / an; pll 432 drivers/video/fbdev/core/svgalib.c f_current = (pll->f_base * *m) / *n; pll 669 drivers/video/fbdev/intelfb/intelfbhw.c struct pll_min_max *pll = &plls[index]; pll 674 drivers/video/fbdev/intelfb/intelfbhw.c vco = pll->ref_clk * m / n; pll 885 drivers/video/fbdev/intelfb/intelfbhw.c struct pll_min_max *pll = &plls[index]; pll 888 drivers/video/fbdev/intelfb/intelfbhw.c for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) { pll 889 drivers/video/fbdev/intelfb/intelfbhw.c for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) { pll 906 drivers/video/fbdev/intelfb/intelfbhw.c struct pll_min_max *pll = &plls[index]; pll 923 drivers/video/fbdev/intelfb/intelfbhw.c if (p % 4 == 0 && p1 < pll->min_p1) { pll 927 drivers/video/fbdev/intelfb/intelfbhw.c if (p1 < pll->min_p1 || p1 > pll->max_p1 || pll 945 drivers/video/fbdev/intelfb/intelfbhw.c struct pll_min_max *pll = &plls[index]; pll 949 drivers/video/fbdev/intelfb/intelfbhw.c div_max = pll->max_vco / clock; pll 951 drivers/video/fbdev/intelfb/intelfbhw.c p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi; pll 954 drivers/video/fbdev/intelfb/intelfbhw.c if (p_min < pll->min_p) pll 955 drivers/video/fbdev/intelfb/intelfbhw.c p_min = pll->min_p; pll 956 drivers/video/fbdev/intelfb/intelfbhw.c if (p_max > pll->max_p) pll 957 drivers/video/fbdev/intelfb/intelfbhw.c p_max = pll->max_p; pll 968 drivers/video/fbdev/intelfb/intelfbhw.c n = pll->min_n; pll 972 drivers/video/fbdev/intelfb/intelfbhw.c m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk; pll 973 drivers/video/fbdev/intelfb/intelfbhw.c if (m < pll->min_m) pll 974 drivers/video/fbdev/intelfb/intelfbhw.c m = pll->min_m + 1; pll 975 drivers/video/fbdev/intelfb/intelfbhw.c if (m > pll->max_m) pll 976 drivers/video/fbdev/intelfb/intelfbhw.c m = pll->max_m - 1; pll 997 drivers/video/fbdev/intelfb/intelfbhw.c } while ((n <= pll->max_n) && (f_out >= clock)); pll 35 drivers/video/fbdev/matrox/g450_pll.c return (minfo->features.pll.ref_freq * n + (m >> 1)) / m; pll 99 drivers/video/fbdev/matrox/g450_pll.c n = ((tvco * (m+1) + minfo->features.pll.ref_freq) / (minfo->features.pll.ref_freq * 2)) - 2; pll 137 drivers/video/fbdev/matrox/g450_pll.c unsigned int mnp, unsigned int pll) pll 139 drivers/video/fbdev/matrox/g450_pll.c switch (pll) { pll 174 drivers/video/fbdev/matrox/g450_pll.c unsigned int mnp, unsigned int pll) pll 180 drivers/video/fbdev/matrox/g450_pll.c switch (pll) { pll 230 drivers/video/fbdev/matrox/g450_pll.c unsigned int pll) pll 232 drivers/video/fbdev/matrox/g450_pll.c return g450_isplllocked(minfo, g450_setpll(minfo, mnp, pll)); pll 235 drivers/video/fbdev/matrox/g450_pll.c static void updatehwstate_clk(struct matrox_hw_state* hw, unsigned int mnp, unsigned int pll) { pll 236 drivers/video/fbdev/matrox/g450_pll.c switch (pll) { pll 246 drivers/video/fbdev/matrox/g450_pll.c unsigned int pll) pll 248 drivers/video/fbdev/matrox/g450_pll.c if (g450_cmppll(minfo, mnp, pll)) { pll 249 drivers/video/fbdev/matrox/g450_pll.c g450_setpll(minfo, mnp, pll); pll 254 drivers/video/fbdev/matrox/g450_pll.c unsigned int pll, pll 281 drivers/video/fbdev/matrox/g450_pll.c if (g450_testpll(minfo, mnp - 0x0300, pll) && pll 282 drivers/video/fbdev/matrox/g450_pll.c g450_testpll(minfo, mnp + 0x0300, pll) && pll 283 drivers/video/fbdev/matrox/g450_pll.c g450_testpll(minfo, mnp - 0x0200, pll) && pll 284 drivers/video/fbdev/matrox/g450_pll.c g450_testpll(minfo, mnp + 0x0200, pll) && pll 285 drivers/video/fbdev/matrox/g450_pll.c g450_testpll(minfo, mnp - 0x0100, pll) && pll 286 drivers/video/fbdev/matrox/g450_pll.c g450_testpll(minfo, mnp + 0x0100, pll)) { pll 287 drivers/video/fbdev/matrox/g450_pll.c if (g450_testpll(minfo, mnp, pll)) { pll 290 drivers/video/fbdev/matrox/g450_pll.c } else if (!found && g450_testpll(minfo, mnp, pll)) { pll 296 drivers/video/fbdev/matrox/g450_pll.c g450_setpll(minfo, mnpfound, pll); pll 332 drivers/video/fbdev/matrox/g450_pll.c unsigned int pll, unsigned int *mnparray, pll 341 drivers/video/fbdev/matrox/g450_pll.c switch (pll) { pll 382 drivers/video/fbdev/matrox/g450_pll.c switch (pll) { pll 445 drivers/video/fbdev/matrox/g450_pll.c if (pll == M_VIDEO_PLL) { pll 501 drivers/video/fbdev/matrox/g450_pll.c matroxfb_g450_setpll_cond(minfo, mnp, pll); pll 503 drivers/video/fbdev/matrox/g450_pll.c mnp = g450_findworkingpll(minfo, pll, mnparray, mnpcount); pll 506 drivers/video/fbdev/matrox/g450_pll.c updatehwstate_clk(&minfo->hw, mnp, pll); pll 517 drivers/video/fbdev/matrox/g450_pll.c unsigned int pll) pll 525 drivers/video/fbdev/matrox/g450_pll.c r = __g450_setclk(minfo, fout, pll, arr, arr + MNP_TABLE_SIZE); pll 8 drivers/video/fbdev/matrox/g450_pll.h unsigned int pll); pll 11 drivers/video/fbdev/matrox/g450_pll.h unsigned int pll); pll 181 drivers/video/fbdev/matrox/matroxfb_DAC1064.c } else if (minfo->crtc2.pixclock == minfo->features.pll.ref_freq) { pll 589 drivers/video/fbdev/matrox/matroxfb_DAC1064.c minfo->features.pll.vco_freq_min = 62000; pll 590 drivers/video/fbdev/matrox/matroxfb_DAC1064.c minfo->features.pll.ref_freq = 14318; pll 591 drivers/video/fbdev/matrox/matroxfb_DAC1064.c minfo->features.pll.feed_div_min = 100; pll 592 drivers/video/fbdev/matrox/matroxfb_DAC1064.c minfo->features.pll.feed_div_max = 127; pll 593 drivers/video/fbdev/matrox/matroxfb_DAC1064.c minfo->features.pll.in_div_min = 1; pll 594 drivers/video/fbdev/matrox/matroxfb_DAC1064.c minfo->features.pll.in_div_max = 31; pll 595 drivers/video/fbdev/matrox/matroxfb_DAC1064.c minfo->features.pll.post_shift_max = 3; pll 727 drivers/video/fbdev/matrox/matroxfb_DAC1064.c matroxfb_g450_setclk(minfo, minfo->values.pll.video, M_VIDEO_PLL); pll 737 drivers/video/fbdev/matrox/matroxfb_DAC1064.c matroxfb_g450_setclk(minfo, minfo->values.pll.system, M_SYSTEM_PLL); pll 854 drivers/video/fbdev/matrox/matroxfb_DAC1064.c minfo->features.pll.vco_freq_min = 130000; /* my sample: >118 */ pll 856 drivers/video/fbdev/matrox/matroxfb_DAC1064.c minfo->features.pll.vco_freq_min = 62000; pll 858 drivers/video/fbdev/matrox/matroxfb_DAC1064.c if (!minfo->features.pll.ref_freq) { pll 859 drivers/video/fbdev/matrox/matroxfb_DAC1064.c minfo->features.pll.ref_freq = 27000; pll 861 drivers/video/fbdev/matrox/matroxfb_DAC1064.c minfo->features.pll.feed_div_min = 7; pll 862 drivers/video/fbdev/matrox/matroxfb_DAC1064.c minfo->features.pll.feed_div_max = 127; pll 863 drivers/video/fbdev/matrox/matroxfb_DAC1064.c minfo->features.pll.in_div_min = 1; pll 864 drivers/video/fbdev/matrox/matroxfb_DAC1064.c minfo->features.pll.in_div_max = 31; pll 865 drivers/video/fbdev/matrox/matroxfb_DAC1064.c minfo->features.pll.post_shift_max = 3; pll 546 drivers/video/fbdev/matrox/matroxfb_Ti3026.c minfo->features.pll.vco_freq_min = 110000; pll 547 drivers/video/fbdev/matrox/matroxfb_Ti3026.c minfo->features.pll.ref_freq = 114545; pll 548 drivers/video/fbdev/matrox/matroxfb_Ti3026.c minfo->features.pll.feed_div_min = 2; pll 549 drivers/video/fbdev/matrox/matroxfb_Ti3026.c minfo->features.pll.feed_div_max = 24; pll 550 drivers/video/fbdev/matrox/matroxfb_Ti3026.c minfo->features.pll.in_div_min = 2; pll 551 drivers/video/fbdev/matrox/matroxfb_Ti3026.c minfo->features.pll.in_div_max = 63; pll 552 drivers/video/fbdev/matrox/matroxfb_Ti3026.c minfo->features.pll.post_shift_max = 3; pll 411 drivers/video/fbdev/matrox/matroxfb_base.h struct matrox_pll_features pll; pll 477 drivers/video/fbdev/matrox/matroxfb_base.h } pll; pll 224 drivers/video/fbdev/matrox/matroxfb_maven.c static int matroxfb_PLL_mavenclock(const struct matrox_pll_features2* pll, pll 231 drivers/video/fbdev/matrox/matroxfb_maven.c unsigned int fmin = pll->vco_freq_min / ctl->den; pll 241 drivers/video/fbdev/matrox/matroxfb_maven.c fmax = pll->vco_freq_max / ctl->den; pll 245 drivers/video/fbdev/matrox/matroxfb_maven.c for (p = 1; p <= pll->post_shift_max; p++) { pll 256 drivers/video/fbdev/matrox/matroxfb_maven.c for (m = pll->in_div_min; m <= pll->in_div_max; m++) { pll 262 drivers/video/fbdev/matrox/matroxfb_maven.c if (n < pll->feed_div_min) pll 264 drivers/video/fbdev/matrox/matroxfb_maven.c if (n > pll->feed_div_max) pll 129 drivers/video/fbdev/matrox/matroxfb_misc.c int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax, pll 133 drivers/video/fbdev/matrox/matroxfb_misc.c unsigned int fxtal = pll->ref_freq; pll 142 drivers/video/fbdev/matrox/matroxfb_misc.c printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max); pll 143 drivers/video/fbdev/matrox/matroxfb_misc.c printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq); pll 145 drivers/video/fbdev/matrox/matroxfb_misc.c printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min); pll 146 drivers/video/fbdev/matrox/matroxfb_misc.c printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min); pll 147 drivers/video/fbdev/matrox/matroxfb_misc.c printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max); pll 148 drivers/video/fbdev/matrox/matroxfb_misc.c printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min); pll 149 drivers/video/fbdev/matrox/matroxfb_misc.c printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max); pll 152 drivers/video/fbdev/matrox/matroxfb_misc.c for (p = 1; p <= pll->post_shift_max; p++) { pll 157 drivers/video/fbdev/matrox/matroxfb_misc.c if (fwant < pll->vco_freq_min) fwant = pll->vco_freq_min; pll 162 drivers/video/fbdev/matrox/matroxfb_misc.c if (fwant < pll->vco_freq_min) break; pll 163 drivers/video/fbdev/matrox/matroxfb_misc.c for (m = pll->in_div_min; m <= pll->in_div_max; m++) { pll 168 drivers/video/fbdev/matrox/matroxfb_misc.c if (n > pll->feed_div_max) pll 170 drivers/video/fbdev/matrox/matroxfb_misc.c if (n < pll->feed_div_min) pll 171 drivers/video/fbdev/matrox/matroxfb_misc.c n = pll->feed_div_min; pll 544 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.pll.system = get_unaligned_le16(bd->pins + 28) ? pll 547 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->features.pll.ref_freq = 14318; pll 556 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.pll.system = 50000; pll 557 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->features.pll.ref_freq = 14318; pll 570 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000); pll 571 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->features.pll.ref_freq = 14318; pll 581 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.pll.system = 50000; pll 582 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->features.pll.ref_freq = 14318; pll 599 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000; pll 612 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->features.pll.ref_freq = 27000; pll 629 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000; pll 630 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000; pll 643 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.pll.system = 200000; pll 644 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->features.pll.ref_freq = 27000; pll 660 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.pll.system = pll 661 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000; pll 668 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000; pll 693 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.pll.system = pll 694 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->values.pll.video = 284000; pll 702 drivers/video/fbdev/matrox/matroxfb_misc.c minfo->features.pll.ref_freq = 27000; pll 8 drivers/video/fbdev/matrox/matroxfb_misc.h int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax, pll 15 drivers/video/fbdev/matrox/matroxfb_misc.h return matroxfb_PLL_calcclock(&minfo->features.pll, freq, fmax, in, feed, post); pll 144 drivers/video/fbdev/nvidia/nv_hw.c unsigned int pll, N, M, MB, NB, P; pll 147 drivers/video/fbdev/nvidia/nv_hw.c pll = NV_RD32(par->PMC, 0x4020); pll 148 drivers/video/fbdev/nvidia/nv_hw.c P = (pll >> 16) & 0x07; pll 149 drivers/video/fbdev/nvidia/nv_hw.c pll = NV_RD32(par->PMC, 0x4024); pll 150 drivers/video/fbdev/nvidia/nv_hw.c M = pll & 0xFF; pll 151 drivers/video/fbdev/nvidia/nv_hw.c N = (pll >> 8) & 0xFF; pll 157 drivers/video/fbdev/nvidia/nv_hw.c MB = (pll >> 16) & 0xFF; pll 158 drivers/video/fbdev/nvidia/nv_hw.c NB = (pll >> 24) & 0xFF; pll 162 drivers/video/fbdev/nvidia/nv_hw.c pll = NV_RD32(par->PMC, 0x4000); pll 163 drivers/video/fbdev/nvidia/nv_hw.c P = (pll >> 16) & 0x07; pll 164 drivers/video/fbdev/nvidia/nv_hw.c pll = NV_RD32(par->PMC, 0x4004); pll 165 drivers/video/fbdev/nvidia/nv_hw.c M = pll & 0xFF; pll 166 drivers/video/fbdev/nvidia/nv_hw.c N = (pll >> 8) & 0xFF; pll 167 drivers/video/fbdev/nvidia/nv_hw.c MB = (pll >> 16) & 0xFF; pll 168 drivers/video/fbdev/nvidia/nv_hw.c NB = (pll >> 24) & 0xFF; pll 172 drivers/video/fbdev/nvidia/nv_hw.c pll = NV_RD32(par->PRAMDAC0, 0x0504); pll 173 drivers/video/fbdev/nvidia/nv_hw.c M = pll & 0xFF; pll 174 drivers/video/fbdev/nvidia/nv_hw.c N = (pll >> 8) & 0xFF; pll 175 drivers/video/fbdev/nvidia/nv_hw.c P = (pll >> 16) & 0x0F; pll 176 drivers/video/fbdev/nvidia/nv_hw.c pll = NV_RD32(par->PRAMDAC0, 0x0574); pll 177 drivers/video/fbdev/nvidia/nv_hw.c if (pll & 0x80000000) { pll 178 drivers/video/fbdev/nvidia/nv_hw.c MB = pll & 0xFF; pll 179 drivers/video/fbdev/nvidia/nv_hw.c NB = (pll >> 8) & 0xFF; pll 186 drivers/video/fbdev/nvidia/nv_hw.c pll = NV_RD32(par->PRAMDAC0, 0x0500); pll 187 drivers/video/fbdev/nvidia/nv_hw.c M = pll & 0xFF; pll 188 drivers/video/fbdev/nvidia/nv_hw.c N = (pll >> 8) & 0xFF; pll 189 drivers/video/fbdev/nvidia/nv_hw.c P = (pll >> 16) & 0x0F; pll 190 drivers/video/fbdev/nvidia/nv_hw.c pll = NV_RD32(par->PRAMDAC0, 0x0570); pll 191 drivers/video/fbdev/nvidia/nv_hw.c if (pll & 0x80000000) { pll 192 drivers/video/fbdev/nvidia/nv_hw.c MB = pll & 0xFF; pll 193 drivers/video/fbdev/nvidia/nv_hw.c NB = (pll >> 8) & 0xFF; pll 202 drivers/video/fbdev/nvidia/nv_hw.c pll = NV_RD32(par->PRAMDAC0, 0x0504); pll 203 drivers/video/fbdev/nvidia/nv_hw.c M = pll & 0x0F; pll 204 drivers/video/fbdev/nvidia/nv_hw.c N = (pll >> 8) & 0xFF; pll 205 drivers/video/fbdev/nvidia/nv_hw.c P = (pll >> 16) & 0x07; pll 206 drivers/video/fbdev/nvidia/nv_hw.c if (pll & 0x00000080) { pll 207 drivers/video/fbdev/nvidia/nv_hw.c MB = (pll >> 4) & 0x07; pll 208 drivers/video/fbdev/nvidia/nv_hw.c NB = (pll >> 19) & 0x1f; pll 215 drivers/video/fbdev/nvidia/nv_hw.c pll = NV_RD32(par->PRAMDAC0, 0x0500); pll 216 drivers/video/fbdev/nvidia/nv_hw.c M = pll & 0x0F; pll 217 drivers/video/fbdev/nvidia/nv_hw.c N = (pll >> 8) & 0xFF; pll 218 drivers/video/fbdev/nvidia/nv_hw.c P = (pll >> 16) & 0x07; pll 219 drivers/video/fbdev/nvidia/nv_hw.c if (pll & 0x00000080) { pll 220 drivers/video/fbdev/nvidia/nv_hw.c MB = (pll >> 4) & 0x07; pll 221 drivers/video/fbdev/nvidia/nv_hw.c NB = (pll >> 19) & 0x1f; pll 228 drivers/video/fbdev/nvidia/nv_hw.c pll = NV_RD32(par->PRAMDAC0, 0x0504); pll 229 drivers/video/fbdev/nvidia/nv_hw.c M = pll & 0xFF; pll 230 drivers/video/fbdev/nvidia/nv_hw.c N = (pll >> 8) & 0xFF; pll 231 drivers/video/fbdev/nvidia/nv_hw.c P = (pll >> 16) & 0x0F; pll 234 drivers/video/fbdev/nvidia/nv_hw.c pll = NV_RD32(par->PRAMDAC0, 0x0500); pll 235 drivers/video/fbdev/nvidia/nv_hw.c M = pll & 0xFF; pll 236 drivers/video/fbdev/nvidia/nv_hw.c N = (pll >> 8) & 0xFF; pll 237 drivers/video/fbdev/nvidia/nv_hw.c P = (pll >> 16) & 0x0F; pll 684 drivers/video/fbdev/nvidia/nv_hw.c unsigned int M, N, P, pll, MClk, NVClk, memctrl; pll 703 drivers/video/fbdev/nvidia/nv_hw.c pll = NV_RD32(par->PRAMDAC0, 0x0500); pll 704 drivers/video/fbdev/nvidia/nv_hw.c M = (pll >> 0) & 0xFF; pll 705 drivers/video/fbdev/nvidia/nv_hw.c N = (pll >> 8) & 0xFF; pll 706 drivers/video/fbdev/nvidia/nv_hw.c P = (pll >> 16) & 0x0F; pll 874 drivers/video/fbdev/nvidia/nv_hw.c CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, pll 877 drivers/video/fbdev/nvidia/nv_hw.c CalcVClock(dotClock, &VClk, &state->pll, par); pll 69 drivers/video/fbdev/nvidia/nv_type.h u32 pll; pll 435 drivers/video/fbdev/nvidia/nvidia.c state->vpll = state->pll; pll 436 drivers/video/fbdev/nvidia/nvidia.c state->vpll2 = state->pll; pll 3312 drivers/video/fbdev/omap2/omapfb/dss/dispc.c struct dss_pll *pll; pll 3320 drivers/video/fbdev/omap2/omapfb/dss/dispc.c pll = dss_pll_find("dsi0"); pll 3321 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (!pll) pll 3322 drivers/video/fbdev/omap2/omapfb/dss/dispc.c pll = dss_pll_find("video0"); pll 3324 drivers/video/fbdev/omap2/omapfb/dss/dispc.c r = pll->cinfo.clkout[0]; pll 3327 drivers/video/fbdev/omap2/omapfb/dss/dispc.c pll = dss_pll_find("dsi1"); pll 3328 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (!pll) pll 3329 drivers/video/fbdev/omap2/omapfb/dss/dispc.c pll = dss_pll_find("video1"); pll 3331 drivers/video/fbdev/omap2/omapfb/dss/dispc.c r = pll->cinfo.clkout[0]; pll 3343 drivers/video/fbdev/omap2/omapfb/dss/dispc.c struct dss_pll *pll; pll 3358 drivers/video/fbdev/omap2/omapfb/dss/dispc.c pll = dss_pll_find("dsi0"); pll 3359 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (!pll) pll 3360 drivers/video/fbdev/omap2/omapfb/dss/dispc.c pll = dss_pll_find("video0"); pll 3362 drivers/video/fbdev/omap2/omapfb/dss/dispc.c r = pll->cinfo.clkout[0]; pll 3365 drivers/video/fbdev/omap2/omapfb/dss/dispc.c pll = dss_pll_find("dsi1"); pll 3366 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (!pll) pll 3367 drivers/video/fbdev/omap2/omapfb/dss/dispc.c pll = dss_pll_find("video1"); pll 3369 drivers/video/fbdev/omap2/omapfb/dss/dispc.c r = pll->cinfo.clkout[0]; pll 37 drivers/video/fbdev/omap2/omapfb/dss/dpi.c struct dss_pll *pll; pll 132 drivers/video/fbdev/omap2/omapfb/dss/dpi.c struct dss_pll *pll; pll 204 drivers/video/fbdev/omap2/omapfb/dss/dpi.c return dss_pll_hsdiv_calc(ctx->pll, clkdco, pll 226 drivers/video/fbdev/omap2/omapfb/dss/dpi.c ctx->pll = dpi->pll; pll 233 drivers/video/fbdev/omap2/omapfb/dss/dpi.c clkin = clk_get_rate(ctx->pll->clkin); pll 235 drivers/video/fbdev/omap2/omapfb/dss/dpi.c return dss_pll_calc(ctx->pll, clkin, pll 283 drivers/video/fbdev/omap2/omapfb/dss/dpi.c r = dss_pll_set_config(dpi->pll, &ctx.dsi_cinfo); pll 333 drivers/video/fbdev/omap2/omapfb/dss/dpi.c if (dpi->pll) pll 407 drivers/video/fbdev/omap2/omapfb/dss/dpi.c if (dpi->pll) { pll 408 drivers/video/fbdev/omap2/omapfb/dss/dpi.c r = dss_pll_enable(dpi->pll); pll 431 drivers/video/fbdev/omap2/omapfb/dss/dpi.c if (dpi->pll) pll 432 drivers/video/fbdev/omap2/omapfb/dss/dpi.c dss_pll_disable(dpi->pll); pll 455 drivers/video/fbdev/omap2/omapfb/dss/dpi.c if (dpi->pll) { pll 457 drivers/video/fbdev/omap2/omapfb/dss/dpi.c dss_pll_disable(dpi->pll); pll 511 drivers/video/fbdev/omap2/omapfb/dss/dpi.c if (dpi->pll) { pll 546 drivers/video/fbdev/omap2/omapfb/dss/dpi.c static int dpi_verify_dsi_pll(struct dss_pll *pll) pll 552 drivers/video/fbdev/omap2/omapfb/dss/dpi.c r = dss_pll_enable(pll); pll 556 drivers/video/fbdev/omap2/omapfb/dss/dpi.c dss_pll_disable(pll); pll 585 drivers/video/fbdev/omap2/omapfb/dss/dpi.c struct dss_pll *pll; pll 587 drivers/video/fbdev/omap2/omapfb/dss/dpi.c if (dpi->pll) pll 590 drivers/video/fbdev/omap2/omapfb/dss/dpi.c pll = dpi_get_pll(dpi->output.dispc_channel); pll 591 drivers/video/fbdev/omap2/omapfb/dss/dpi.c if (!pll) pll 596 drivers/video/fbdev/omap2/omapfb/dss/dpi.c dss_ctrl_pll_set_control_mux(pll->id, dpi->output.dispc_channel); pll 598 drivers/video/fbdev/omap2/omapfb/dss/dpi.c if (dpi_verify_dsi_pll(pll)) { pll 603 drivers/video/fbdev/omap2/omapfb/dss/dpi.c dpi->pll = pll; pll 268 drivers/video/fbdev/omap2/omapfb/dss/dsi.c struct dss_pll *pll; pll 310 drivers/video/fbdev/omap2/omapfb/dss/dsi.c struct dss_pll pll; pll 1231 drivers/video/fbdev/omap2/omapfb/dss/dsi.c return dsi->pll.cinfo.clkout[HSDIV_DISPC]; pll 1238 drivers/video/fbdev/omap2/omapfb/dss/dsi.c return dsi->pll.cinfo.clkout[HSDIV_DSI]; pll 1245 drivers/video/fbdev/omap2/omapfb/dss/dsi.c return dsi->pll.cinfo.clkdco / 16; pll 1375 drivers/video/fbdev/omap2/omapfb/dss/dsi.c static int dsi_pll_enable(struct dss_pll *pll) pll 1377 drivers/video/fbdev/omap2/omapfb/dss/dsi.c struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); pll 1453 drivers/video/fbdev/omap2/omapfb/dss/dsi.c static void dsi_pll_disable(struct dss_pll *pll) pll 1455 drivers/video/fbdev/omap2/omapfb/dss/dsi.c struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); pll 1465 drivers/video/fbdev/omap2/omapfb/dss/dsi.c struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; pll 1468 drivers/video/fbdev/omap2/omapfb/dss/dsi.c struct dss_pll *pll = &dsi->pll; pll 1478 drivers/video/fbdev/omap2/omapfb/dss/dsi.c seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin)); pll 1851 drivers/video/fbdev/omap2/omapfb/dss/dsi.c unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; pll 1859 drivers/video/fbdev/omap2/omapfb/dss/dsi.c unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; pll 4165 drivers/video/fbdev/omap2/omapfb/dss/dsi.c r = dss_pll_set_config(&dsi->pll, &cinfo); pll 4179 drivers/video/fbdev/omap2/omapfb/dss/dsi.c r = dss_pll_enable(&dsi->pll); pll 4223 drivers/video/fbdev/omap2/omapfb/dss/dsi.c dss_pll_disable(&dsi->pll); pll 4444 drivers/video/fbdev/omap2/omapfb/dss/dsi.c return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min, pll 4458 drivers/video/fbdev/omap2/omapfb/dss/dsi.c clkin = clk_get_rate(dsi->pll.clkin); pll 4474 drivers/video/fbdev/omap2/omapfb/dss/dsi.c ctx->pll = &dsi->pll; pll 4483 drivers/video/fbdev/omap2/omapfb/dss/dsi.c return dss_pll_calc(ctx->pll, clkin, pll 4742 drivers/video/fbdev/omap2/omapfb/dss/dsi.c return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min, pll 4759 drivers/video/fbdev/omap2/omapfb/dss/dsi.c clkin = clk_get_rate(dsi->pll.clkin); pll 4763 drivers/video/fbdev/omap2/omapfb/dss/dsi.c ctx->pll = &dsi->pll; pll 4784 drivers/video/fbdev/omap2/omapfb/dss/dsi.c return dss_pll_calc(ctx->pll, clkin, pll 5210 drivers/video/fbdev/omap2/omapfb/dss/dsi.c struct dss_pll *pll = &dsi->pll; pll 5220 drivers/video/fbdev/omap2/omapfb/dss/dsi.c pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1"; pll 5221 drivers/video/fbdev/omap2/omapfb/dss/dsi.c pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2; pll 5222 drivers/video/fbdev/omap2/omapfb/dss/dsi.c pll->clkin = clk; pll 5223 drivers/video/fbdev/omap2/omapfb/dss/dsi.c pll->base = dsi->pll_base; pll 5230 drivers/video/fbdev/omap2/omapfb/dss/dsi.c pll->hw = &dss_omap3_dsi_pll_hw; pll 5236 drivers/video/fbdev/omap2/omapfb/dss/dsi.c pll->hw = &dss_omap4_dsi_pll_hw; pll 5240 drivers/video/fbdev/omap2/omapfb/dss/dsi.c pll->hw = &dss_omap5_dsi_pll_hw; pll 5247 drivers/video/fbdev/omap2/omapfb/dss/dsi.c pll->ops = &dsi_pll_ops; pll 5249 drivers/video/fbdev/omap2/omapfb/dss/dsi.c r = dss_pll_register(pll); pll 5475 drivers/video/fbdev/omap2/omapfb/dss/dsi.c dss_pll_unregister(&dsi->pll); pll 134 drivers/video/fbdev/omap2/omapfb/dss/dss.h int (*enable)(struct dss_pll *pll); pll 135 drivers/video/fbdev/omap2/omapfb/dss/dss.h void (*disable)(struct dss_pll *pll); pll 136 drivers/video/fbdev/omap2/omapfb/dss/dss.h int (*set_config)(struct dss_pll *pll, pll 275 drivers/video/fbdev/omap2/omapfb/dss/dss.h void dss_video_pll_uninit(struct dss_pll *pll); pll 482 drivers/video/fbdev/omap2/omapfb/dss/dss.h int dss_pll_register(struct dss_pll *pll); pll 483 drivers/video/fbdev/omap2/omapfb/dss/dss.h void dss_pll_unregister(struct dss_pll *pll); pll 485 drivers/video/fbdev/omap2/omapfb/dss/dss.h int dss_pll_enable(struct dss_pll *pll); pll 486 drivers/video/fbdev/omap2/omapfb/dss/dss.h void dss_pll_disable(struct dss_pll *pll); pll 487 drivers/video/fbdev/omap2/omapfb/dss/dss.h int dss_pll_set_config(struct dss_pll *pll, pll 490 drivers/video/fbdev/omap2/omapfb/dss/dss.h bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco, pll 493 drivers/video/fbdev/omap2/omapfb/dss/dss.h bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin, pll 496 drivers/video/fbdev/omap2/omapfb/dss/dss.h int dss_pll_write_config_type_a(struct dss_pll *pll, pll 498 drivers/video/fbdev/omap2/omapfb/dss/dss.h int dss_pll_write_config_type_b(struct dss_pll *pll, pll 500 drivers/video/fbdev/omap2/omapfb/dss/dss.h int dss_pll_wait_reset_done(struct dss_pll *pll); pll 229 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h struct dss_pll pll; pll 298 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s); pll 299 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h void hdmi_pll_compute(struct hdmi_pll_data *pll, pll 301 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll, pll 335 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h struct hdmi_pll_data pll; pll 163 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); pll 165 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c r = dss_pll_enable(&hdmi.pll.pll); pll 171 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo); pll 216 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c dss_pll_disable(&hdmi.pll.pll); pll 234 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c dss_pll_disable(&hdmi.pll.pll); pll 278 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_pll_dump(&hdmi.pll, s); pll 691 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp); pll 734 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_pll_uninit(&hdmi.pll); pll 747 drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c hdmi_pll_uninit(&hdmi.pll); pll 175 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); pll 182 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c r = dss_pll_enable(&hdmi.pll.pll); pll 188 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo); pll 233 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c dss_pll_disable(&hdmi.pll.pll); pll 251 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c dss_pll_disable(&hdmi.pll.pll); pll 299 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_pll_dump(&hdmi.pll, s); pll 730 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp); pll 773 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_pll_uninit(&hdmi.pll); pll 786 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c hdmi_pll_uninit(&hdmi.pll); pll 23 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s) pll 26 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c hdmi_read_reg(pll->base, r)) pll 39 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c void hdmi_pll_compute(struct hdmi_pll_data *pll, pll 47 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c const struct dss_pll_hw *hw = pll->pll.hw; pll 49 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c clkin = clk_get_rate(pll->pll.clkin); pll 101 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); pll 102 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c struct hdmi_wp_data *wp = pll->wp; pll 116 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); pll 117 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c struct hdmi_wp_data *wp = pll->wp; pll 179 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c struct dss_pll *pll = &hpll->pll; pll 189 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c pll->name = "hdmi"; pll 190 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c pll->id = DSS_PLL_HDMI; pll 191 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c pll->base = hpll->base; pll 192 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c pll->clkin = clk; pll 198 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c pll->hw = &dss_omap4_hdmi_pll_hw; pll 203 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c pll->hw = &dss_omap5_hdmi_pll_hw; pll 210 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c pll->ops = &dsi_pll_ops; pll 212 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c r = dss_pll_register(pll); pll 219 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll, pll 225 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c pll->wp = wp; pll 233 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c pll->base = devm_ioremap_resource(&pdev->dev, res); pll 234 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c if (IS_ERR(pll->base)) { pll 236 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c return PTR_ERR(pll->base); pll 239 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c r = dsi_init_pll_data(pdev, pll); pll 250 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c struct dss_pll *pll = &hpll->pll; pll 252 drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c dss_pll_unregister(pll); pll 30 drivers/video/fbdev/omap2/omapfb/dss/pll.c int dss_pll_register(struct dss_pll *pll) pll 36 drivers/video/fbdev/omap2/omapfb/dss/pll.c dss_plls[i] = pll; pll 44 drivers/video/fbdev/omap2/omapfb/dss/pll.c void dss_pll_unregister(struct dss_pll *pll) pll 49 drivers/video/fbdev/omap2/omapfb/dss/pll.c if (dss_plls[i] == pll) { pll 68 drivers/video/fbdev/omap2/omapfb/dss/pll.c int dss_pll_enable(struct dss_pll *pll) pll 72 drivers/video/fbdev/omap2/omapfb/dss/pll.c r = clk_prepare_enable(pll->clkin); pll 76 drivers/video/fbdev/omap2/omapfb/dss/pll.c if (pll->regulator) { pll 77 drivers/video/fbdev/omap2/omapfb/dss/pll.c r = regulator_enable(pll->regulator); pll 82 drivers/video/fbdev/omap2/omapfb/dss/pll.c r = pll->ops->enable(pll); pll 89 drivers/video/fbdev/omap2/omapfb/dss/pll.c if (pll->regulator) pll 90 drivers/video/fbdev/omap2/omapfb/dss/pll.c regulator_disable(pll->regulator); pll 92 drivers/video/fbdev/omap2/omapfb/dss/pll.c clk_disable_unprepare(pll->clkin); pll 96 drivers/video/fbdev/omap2/omapfb/dss/pll.c void dss_pll_disable(struct dss_pll *pll) pll 98 drivers/video/fbdev/omap2/omapfb/dss/pll.c pll->ops->disable(pll); pll 100 drivers/video/fbdev/omap2/omapfb/dss/pll.c if (pll->regulator) pll 101 drivers/video/fbdev/omap2/omapfb/dss/pll.c regulator_disable(pll->regulator); pll 103 drivers/video/fbdev/omap2/omapfb/dss/pll.c clk_disable_unprepare(pll->clkin); pll 105 drivers/video/fbdev/omap2/omapfb/dss/pll.c memset(&pll->cinfo, 0, sizeof(pll->cinfo)); pll 108 drivers/video/fbdev/omap2/omapfb/dss/pll.c int dss_pll_set_config(struct dss_pll *pll, const struct dss_pll_clock_info *cinfo) pll 112 drivers/video/fbdev/omap2/omapfb/dss/pll.c r = pll->ops->set_config(pll, cinfo); pll 116 drivers/video/fbdev/omap2/omapfb/dss/pll.c pll->cinfo = *cinfo; pll 121 drivers/video/fbdev/omap2/omapfb/dss/pll.c bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco, pll 125 drivers/video/fbdev/omap2/omapfb/dss/pll.c const struct dss_pll_hw *hw = pll->hw; pll 146 drivers/video/fbdev/omap2/omapfb/dss/pll.c bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin, pll 150 drivers/video/fbdev/omap2/omapfb/dss/pll.c const struct dss_pll_hw *hw = pll->hw; pll 214 drivers/video/fbdev/omap2/omapfb/dss/pll.c int dss_pll_wait_reset_done(struct dss_pll *pll) pll 216 drivers/video/fbdev/omap2/omapfb/dss/pll.c void __iomem *base = pll->base; pll 224 drivers/video/fbdev/omap2/omapfb/dss/pll.c static int dss_wait_hsdiv_ack(struct dss_pll *pll, u32 hsdiv_ack_mask) pll 229 drivers/video/fbdev/omap2/omapfb/dss/pll.c u32 v = readl_relaxed(pll->base + PLL_STATUS); pll 238 drivers/video/fbdev/omap2/omapfb/dss/pll.c int dss_pll_write_config_type_a(struct dss_pll *pll, pll 241 drivers/video/fbdev/omap2/omapfb/dss/pll.c const struct dss_pll_hw *hw = pll->hw; pll 242 drivers/video/fbdev/omap2/omapfb/dss/pll.c void __iomem *base = pll->base; pll 316 drivers/video/fbdev/omap2/omapfb/dss/pll.c r = dss_wait_hsdiv_ack(pll, pll 330 drivers/video/fbdev/omap2/omapfb/dss/pll.c int dss_pll_write_config_type_b(struct dss_pll *pll, pll 333 drivers/video/fbdev/omap2/omapfb/dss/pll.c const struct dss_pll_hw *hw = pll->hw; pll 334 drivers/video/fbdev/omap2/omapfb/dss/pll.c void __iomem *base = pll->base; pll 20 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c struct dss_pll pll; pll 56 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c static int dss_video_pll_enable(struct dss_pll *pll) pll 58 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); pll 65 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c dss_ctrl_pll_enable(pll->id, true); pll 69 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c r = dss_pll_wait_reset_done(pll); pll 79 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c dss_ctrl_pll_enable(pll->id, false); pll 85 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c static void dss_video_pll_disable(struct dss_pll *pll) pll 87 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); pll 93 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c dss_ctrl_pll_enable(pll->id, false); pll 136 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c struct dss_pll *pll; pll 185 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c pll = &vpll->pll; pll 187 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c pll->name = id == 0 ? "video0" : "video1"; pll 188 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c pll->id = id == 0 ? DSS_PLL_VIDEO1 : DSS_PLL_VIDEO2; pll 189 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c pll->clkin = clk; pll 190 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c pll->regulator = regulator; pll 191 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c pll->base = pll_base; pll 192 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c pll->hw = &dss_dra7_video_pll_hw; pll 193 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c pll->ops = &dss_pll_ops; pll 195 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c r = dss_pll_register(pll); pll 199 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c return pll; pll 202 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c void dss_video_pll_uninit(struct dss_pll *pll) pll 204 drivers/video/fbdev/omap2/omapfb/dss/video-pll.c dss_pll_unregister(pll); pll 619 drivers/video/fbdev/riva/riva_hw.c unsigned int M, N, P, pll, MClk; pll 621 drivers/video/fbdev/riva/riva_hw.c pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); pll 622 drivers/video/fbdev/riva/riva_hw.c M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; pll 808 drivers/video/fbdev/riva/riva_hw.c unsigned int M, N, P, pll, MClk, NVClk, cfg1; pll 810 drivers/video/fbdev/riva/riva_hw.c pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); pll 811 drivers/video/fbdev/riva/riva_hw.c M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; pll 813 drivers/video/fbdev/riva/riva_hw.c pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); pll 814 drivers/video/fbdev/riva/riva_hw.c M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; pll 1071 drivers/video/fbdev/riva/riva_hw.c unsigned int M, N, P, pll, MClk, NVClk, cfg1; pll 1073 drivers/video/fbdev/riva/riva_hw.c pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); pll 1074 drivers/video/fbdev/riva/riva_hw.c M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; pll 1076 drivers/video/fbdev/riva/riva_hw.c pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); pll 1077 drivers/video/fbdev/riva/riva_hw.c M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; pll 1117 drivers/video/fbdev/riva/riva_hw.c unsigned int M, N, P, pll, MClk, NVClk; pll 1130 drivers/video/fbdev/riva/riva_hw.c pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); pll 1131 drivers/video/fbdev/riva/riva_hw.c M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; pll 361 drivers/video/fbdev/sstfb.c if (sst_calc_pll(PICOS2KHZ(var->pixclock), &freq, &par->pll)) { pll 493 drivers/video/fbdev/sstfb.c sst_calc_pll(PICOS2KHZ(info->var.pixclock), &freq, &par->pll); pll 547 drivers/video/fbdev/sstfb.c par->dac_sw.set_pll(info, &par->pll, VID_CLOCK); pll 21 drivers/video/fbdev/via/via_clock.c static inline u32 cle266_encode_pll(struct via_pll_config pll) pll 23 drivers/video/fbdev/via/via_clock.c return (pll.multiplier << 8) pll 24 drivers/video/fbdev/via/via_clock.c | (pll.rshift << 6) pll 25 drivers/video/fbdev/via/via_clock.c | pll.divisor; pll 28 drivers/video/fbdev/via/via_clock.c static inline u32 k800_encode_pll(struct via_pll_config pll) pll 30 drivers/video/fbdev/via/via_clock.c return ((pll.divisor - 2) << 16) pll 31 drivers/video/fbdev/via/via_clock.c | (pll.rshift << 10) pll 32 drivers/video/fbdev/via/via_clock.c | (pll.multiplier - 2); pll 35 drivers/video/fbdev/via/via_clock.c static inline u32 vx855_encode_pll(struct via_pll_config pll) pll 37 drivers/video/fbdev/via/via_clock.c return (pll.divisor << 16) pll 38 drivers/video/fbdev/via/via_clock.c | (pll.rshift << 10) pll 39 drivers/video/fbdev/via/via_clock.c | pll.multiplier; pll 48 drivers/video/fbdev/via/via_clock.h struct via_pll_config pll) pll 50 drivers/video/fbdev/via/via_clock.h return ref_freq / pll.divisor * pll.multiplier; pll 54 drivers/video/fbdev/via/via_clock.h struct via_pll_config pll) pll 56 drivers/video/fbdev/via/via_clock.h return get_pll_internal_frequency(ref_freq, pll) >> pll.rshift; pll 1062 drivers/video/fbdev/w100fb.c static int w100_pll_adjust(struct w100_pll_info *pll) pll 1086 drivers/video/fbdev/w100fb.c if (tf80 >= (pll->tfgoal)) { pll 1092 drivers/video/fbdev/w100fb.c if (tf20 <= (pll->tfgoal)) pll 1120 drivers/video/fbdev/w100fb.c static int w100_pll_calibration(struct w100_pll_info *pll) pll 1124 drivers/video/fbdev/w100fb.c status = w100_pll_adjust(pll); pll 1149 drivers/video/fbdev/w100fb.c static int w100_pll_set_clk(struct w100_pll_info *pll) pll 1164 drivers/video/fbdev/w100fb.c w100_pwr_state.pll_ref_fb_div.f.pll_ref_div = pll->M; pll 1165 drivers/video/fbdev/w100fb.c w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_int = pll->N_int; pll 1166 drivers/video/fbdev/w100fb.c w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_frac = pll->N_fac; pll 1167 drivers/video/fbdev/w100fb.c w100_pwr_state.pll_ref_fb_div.f.pll_lock_time = pll->lock_time; pll 1173 drivers/video/fbdev/w100fb.c status = w100_pll_calibration(pll); pll 1187 drivers/video/fbdev/w100fb.c struct w100_pll_info *pll = par->pll_table; pll 1190 drivers/video/fbdev/w100fb.c if (freq == pll->freq) { pll 1191 drivers/video/fbdev/w100fb.c return w100_pll_set_clk(pll); pll 1193 drivers/video/fbdev/w100fb.c pll++; pll 1194 drivers/video/fbdev/w100fb.c } while(pll->freq); pll 226 include/linux/mfd/twl6040.h int pll; pll 118 include/linux/svga.h int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node); pll 346 include/video/sstfb.h struct pll_timing pll; pll 46 sound/soc/codecs/adav80x.c #define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll) 0x00 pll 47 sound/soc/codecs/adav80x.c #define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll) (0x40 << (pll)) pll 48 sound/soc/codecs/adav80x.c #define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll) (0x40 << (pll)) pll 56 sound/soc/codecs/adav80x.c #define ADAV80X_PLL_CTRL1_PLLPD(pll) (0x04 << (pll)) pll 59 sound/soc/codecs/adav80x.c #define ADAV80X_PLL_CTRL2_FIELD(pll, x) ((x) << ((pll) * 4)) pll 61 sound/soc/codecs/adav80x.c #define ADAV80X_PLL_CTRL2_FS_48(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x00) pll 62 sound/soc/codecs/adav80x.c #define ADAV80X_PLL_CTRL2_FS_32(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x08) pll 63 sound/soc/codecs/adav80x.c #define ADAV80X_PLL_CTRL2_FS_44(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0c) pll 65 sound/soc/codecs/adav80x.c #define ADAV80X_PLL_CTRL2_SEL(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x02) pll 66 sound/soc/codecs/adav80x.c #define ADAV80X_PLL_CTRL2_DOUB(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x01) pll 67 sound/soc/codecs/adav80x.c #define ADAV80X_PLL_CTRL2_PLL_MASK(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0f) pll 340 sound/soc/codecs/ak4642.c u8 pll; pll 345 sound/soc/codecs/ak4642.c pll = PLL2; pll 348 sound/soc/codecs/ak4642.c pll = PLL2 | PLL0; pll 351 sound/soc/codecs/ak4642.c pll = PLL2 | PLL1; pll 354 sound/soc/codecs/ak4642.c pll = PLL2 | PLL1 | PLL0; pll 357 sound/soc/codecs/ak4642.c pll = PLL3 | PLL2; pll 360 sound/soc/codecs/ak4642.c pll = PLL3 | PLL2 | PLL0; pll 363 sound/soc/codecs/ak4642.c pll = PLL3; pll 367 sound/soc/codecs/ak4642.c pll = PLL3 | PLL2 | PLL1; pll 371 sound/soc/codecs/ak4642.c pll = PLL3 | PLL2 | PLL1 | PLL0; pll 381 sound/soc/codecs/ak4642.c snd_soc_component_update_bits(component, MD_CTL1, PLL_MASK, pll); pll 472 sound/soc/codecs/ak4671.c u8 pll; pll 474 sound/soc/codecs/ak4671.c pll = snd_soc_component_read32(component, AK4671_PLL_MODE_SELECT0); pll 475 sound/soc/codecs/ak4671.c pll &= ~AK4671_PLL; pll 479 sound/soc/codecs/ak4671.c pll |= AK4671_PLL_11_2896MHZ; pll 482 sound/soc/codecs/ak4671.c pll |= AK4671_PLL_12MHZ; pll 485 sound/soc/codecs/ak4671.c pll |= AK4671_PLL_12_288MHZ; pll 488 sound/soc/codecs/ak4671.c pll |= AK4671_PLL_13MHZ; pll 491 sound/soc/codecs/ak4671.c pll |= AK4671_PLL_13_5MHZ; pll 494 sound/soc/codecs/ak4671.c pll |= AK4671_PLL_19_2MHZ; pll 497 sound/soc/codecs/ak4671.c pll |= AK4671_PLL_24MHZ; pll 500 sound/soc/codecs/ak4671.c pll |= AK4671_PLL_26MHZ; pll 503 sound/soc/codecs/ak4671.c pll |= AK4671_PLL_27MHZ; pll 509 sound/soc/codecs/ak4671.c snd_soc_component_write(component, AK4671_PLL_MODE_SELECT0, pll); pll 539 sound/soc/codecs/nau8810.c struct nau8810_pll *pll_param = &nau8810->pll; pll 273 sound/soc/codecs/nau8810.h struct nau8810_pll pll; pll 670 sound/soc/codecs/nau8822.c struct nau8822_pll *pll = &nau8822->pll; pll 701 sound/soc/codecs/nau8822.c if (pll->mclk_scaler != div) { pll 726 sound/soc/codecs/nau8822.c struct nau8822_pll *pll_param = &nau8822->pll; pll 205 sound/soc/codecs/nau8822.h struct nau8822_pll pll; pll 49 sound/soc/codecs/tlv320aic32x4-clk.c struct clk_aic32x4 *pll = to_clk_aic32x4(hw); pll 51 sound/soc/codecs/tlv320aic32x4-clk.c return regmap_update_bits(pll->regmap, AIC32X4_PLLPR, pll 57 sound/soc/codecs/tlv320aic32x4-clk.c struct clk_aic32x4 *pll = to_clk_aic32x4(hw); pll 59 sound/soc/codecs/tlv320aic32x4-clk.c regmap_update_bits(pll->regmap, AIC32X4_PLLPR, pll 65 sound/soc/codecs/tlv320aic32x4-clk.c struct clk_aic32x4 *pll = to_clk_aic32x4(hw); pll 70 sound/soc/codecs/tlv320aic32x4-clk.c ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val); pll 77 sound/soc/codecs/tlv320aic32x4-clk.c static int clk_aic32x4_pll_get_muldiv(struct clk_aic32x4 *pll, pll 84 sound/soc/codecs/tlv320aic32x4-clk.c ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val); pll 90 sound/soc/codecs/tlv320aic32x4-clk.c ret = regmap_read(pll->regmap, AIC32X4_PLLJ, &val); pll 95 sound/soc/codecs/tlv320aic32x4-clk.c ret = regmap_read(pll->regmap, AIC32X4_PLLDMSB, &val); pll 100 sound/soc/codecs/tlv320aic32x4-clk.c ret = regmap_read(pll->regmap, AIC32X4_PLLDLSB, &val); pll 108 sound/soc/codecs/tlv320aic32x4-clk.c static int clk_aic32x4_pll_set_muldiv(struct clk_aic32x4 *pll, pll 114 sound/soc/codecs/tlv320aic32x4-clk.c ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR, pll 119 sound/soc/codecs/tlv320aic32x4-clk.c ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR, pll 125 sound/soc/codecs/tlv320aic32x4-clk.c ret = regmap_write(pll->regmap, AIC32X4_PLLJ, settings->j); pll 129 sound/soc/codecs/tlv320aic32x4-clk.c ret = regmap_write(pll->regmap, AIC32X4_PLLDMSB, (settings->d >> 8)); pll 132 sound/soc/codecs/tlv320aic32x4-clk.c ret = regmap_write(pll->regmap, AIC32X4_PLLDLSB, (settings->d & 0xff)); pll 196 sound/soc/codecs/tlv320aic32x4-clk.c struct clk_aic32x4 *pll = to_clk_aic32x4(hw); pll 200 sound/soc/codecs/tlv320aic32x4-clk.c ret = clk_aic32x4_pll_get_muldiv(pll, &settings); pll 225 sound/soc/codecs/tlv320aic32x4-clk.c struct clk_aic32x4 *pll = to_clk_aic32x4(hw); pll 233 sound/soc/codecs/tlv320aic32x4-clk.c return clk_aic32x4_pll_set_muldiv(pll, &settings); pll 238 sound/soc/codecs/tlv320aic32x4-clk.c struct clk_aic32x4 *pll = to_clk_aic32x4(hw); pll 240 sound/soc/codecs/tlv320aic32x4-clk.c return regmap_update_bits(pll->regmap, pll 248 sound/soc/codecs/tlv320aic32x4-clk.c struct clk_aic32x4 *pll = to_clk_aic32x4(hw); pll 251 sound/soc/codecs/tlv320aic32x4-clk.c regmap_read(pll->regmap, AIC32X4_PLLPR, &val); pll 573 sound/soc/codecs/tlv320aic32x4.c struct clk *pll; pll 575 sound/soc/codecs/tlv320aic32x4.c pll = devm_clk_get(component->dev, "pll"); pll 576 sound/soc/codecs/tlv320aic32x4.c mclk = clk_get_parent(pll); pll 48 sound/soc/codecs/tscs454.c static inline void pll_init(struct pll *pll, int id) pll 50 sound/soc/codecs/tscs454.c pll->id = id; pll 51 sound/soc/codecs/tscs454.c mutex_init(&pll->lock); pll 55 sound/soc/codecs/tscs454.c struct pll *pll; pll 61 sound/soc/codecs/tscs454.c struct pll *pll; pll 131 sound/soc/codecs/tscs454.c struct pll pll1; pll 132 sound/soc/codecs/tscs454.c struct pll pll2; pll 670 sound/soc/codecs/tscs454.c static inline void reserve_pll(struct pll *pll) pll 672 sound/soc/codecs/tscs454.c mutex_lock(&pll->lock); pll 673 sound/soc/codecs/tscs454.c pll->users++; pll 674 sound/soc/codecs/tscs454.c mutex_unlock(&pll->lock); pll 677 sound/soc/codecs/tscs454.c static inline void free_pll(struct pll *pll) pll 679 sound/soc/codecs/tscs454.c mutex_lock(&pll->lock); pll 680 sound/soc/codecs/tscs454.c pll->users--; pll 681 sound/soc/codecs/tscs454.c mutex_unlock(&pll->lock); pll 830 sound/soc/codecs/tscs454.c aif->pll->id, aif->id); pll 831 sound/soc/codecs/tscs454.c free_pll(aif->pll); pll 836 sound/soc/codecs/tscs454.c tscs454->internal_rate.pll->id); pll 837 sound/soc/codecs/tscs454.c free_pll(tscs454->internal_rate.pll); pll 3196 sound/soc/codecs/tscs454.c aif->pll = &tscs454->pll1; pll 3198 sound/soc/codecs/tscs454.c aif->pll = &tscs454->pll2; pll 3201 sound/soc/codecs/tscs454.c aif->pll->id, aif->id); pll 3203 sound/soc/codecs/tscs454.c reserve_pll(aif->pll); pll 3212 sound/soc/codecs/tscs454.c tscs454->internal_rate.pll = &tscs454->pll1; pll 3214 sound/soc/codecs/tscs454.c tscs454->internal_rate.pll = &tscs454->pll2; pll 3217 sound/soc/codecs/tscs454.c tscs454->internal_rate.pll->id); pll 3219 sound/soc/codecs/tscs454.c reserve_pll(tscs454->internal_rate.pll); pll 55 sound/soc/codecs/twl6040.c int pll; pll 887 sound/soc/codecs/twl6040.c if (unlikely(priv->pll == TWL6040_SYSCLK_SEL_HPPLL)) { pll 923 sound/soc/codecs/twl6040.c ret = twl6040_set_pll(twl6040, priv->pll, priv->clk_in, priv->sysclk); pll 941 sound/soc/codecs/twl6040.c priv->pll = clk_id; pll 144 sound/soc/codecs/wm8955.c int Fref, int Fout, struct pll_factors *pll) pll 157 sound/soc/codecs/wm8955.c pll->outdiv = 1; pll 160 sound/soc/codecs/wm8955.c pll->outdiv = 0; pll 170 sound/soc/codecs/wm8955.c pll->n = Ndiv; pll 185 sound/soc/codecs/wm8955.c pll->k = K / 10; pll 187 sound/soc/codecs/wm8955.c dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv); pll 249 sound/soc/codecs/wm8955.c struct pll_factors pll; pll 283 sound/soc/codecs/wm8955.c clock_cfgs[sr].mclk, &pll); pll 293 sound/soc/codecs/wm8955.c (pll.n << WM8955_N_SHIFT) | pll 294 sound/soc/codecs/wm8955.c pll.k >> 18); pll 297 sound/soc/codecs/wm8955.c (pll.k >> 9) & WM8955_K_17_9_MASK); pll 300 sound/soc/codecs/wm8955.c pll.k & WM8955_K_8_0_MASK); pll 301 sound/soc/codecs/wm8955.c if (pll.k) pll 308 sound/soc/codecs/wm8955.c if (pll.outdiv) pll 529 sound/soc/pxa/pxa-ssp.c int pll; pll 535 sound/soc/pxa/pxa-ssp.c { .rate = 8000, .pll = 32842000, .acds = SSACD_ACDS_32, .scdb = SSACD_SCDB_4X }, pll 536 sound/soc/pxa/pxa-ssp.c { .rate = 11025, .pll = 5622000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_4X }, pll 537 sound/soc/pxa/pxa-ssp.c { .rate = 16000, .pll = 32842000, .acds = SSACD_ACDS_16, .scdb = SSACD_SCDB_4X }, pll 538 sound/soc/pxa/pxa-ssp.c { .rate = 22050, .pll = 5622000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X }, pll 539 sound/soc/pxa/pxa-ssp.c { .rate = 44100, .pll = 11345000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X }, pll 540 sound/soc/pxa/pxa-ssp.c { .rate = 48000, .pll = 12235000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X }, pll 541 sound/soc/pxa/pxa-ssp.c { .rate = 96000, .pll = 12235000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_1X }, pll 130 sound/soc/uniphier/aio-cpu.c struct uniphier_aio_pll *pll; pll 138 sound/soc/uniphier/aio-cpu.c pll = &aio->chip->plls[pll_id]; pll 140 sound/soc/uniphier/aio-cpu.c if (pll->freq * mul[i] / div[i] == freq)