plane_state      2892 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
plane_state      2900 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
plane_state      2903 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
plane_state      2909 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		uint32_t format = plane_state->fb->format->format;
plane_state      2920 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	if (plane_state->alpha < 0xffff) {
plane_state      2922 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		*global_alpha_value = plane_state->alpha >> 8;
plane_state      2927 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c fill_plane_color_attributes(const struct drm_plane_state *plane_state,
plane_state      2939 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
plane_state      2941 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	switch (plane_state->color_encoding) {
plane_state      2972 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			    const struct drm_plane_state *plane_state,
plane_state      2978 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	const struct drm_framebuffer *fb = plane_state->fb;
plane_state      2980 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		to_amdgpu_framebuffer(plane_state->fb);
plane_state      3023 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
plane_state      3046 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	ret = fill_plane_color_attributes(plane_state, plane_info->format,
plane_state      3061 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		plane_state, &plane_info->per_pixel_alpha,
plane_state      3069 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 				    struct drm_plane_state *plane_state,
plane_state      3074 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		to_amdgpu_framebuffer(plane_state->fb);
plane_state      3081 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	ret = fill_dc_scaling_info(plane_state, &scaling_info);
plane_state      3095 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
plane_state      4557 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
plane_state      4561 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			adev, afb, plane_state->format, plane_state->rotation,
plane_state      4562 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			tiling_flags, &plane_state->tiling_info,
plane_state      4563 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			&plane_state->plane_size, &plane_state->dcc,
plane_state      4564 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			&plane_state->address,
plane_state      6446 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	struct drm_plane_state *plane_state;
plane_state      6475 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	plane_state = drm_atomic_get_plane_state(state, plane);
plane_state      6477 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	ret = PTR_ERR_OR_ZERO(plane_state);
plane_state      2780 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		ASSERT(pipe[i].plane_state);
plane_state      2783 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			if (!pipe[i].plane_state->visible)
plane_state      2788 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			if (!pipe[i].plane_state->visible)
plane_state      2806 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		switch (pipe[i].plane_state->rotation) {
plane_state      2822 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		switch (pipe[i].plane_state->format) {
plane_state      2856 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 					pipe[i].bottom_pipe->plane_state->plane_size.surface_pitch);
plane_state      2863 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			switch (pipe[i].bottom_pipe->plane_state->rotation) {
plane_state      2900 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		if (pipe[i].plane_state) {
plane_state      2908 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			switch (pipe[i].plane_state->rotation) {
plane_state      2924 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			switch (pipe[i].plane_state->format) {
plane_state       308 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state)
plane_state       310 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state)
plane_state       318 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0;
plane_state       329 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0;
plane_state       332 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->src.meta_pitch          = pipe->plane_state->dcc.meta_pitch;
plane_state       334 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->src.sw_mode             = pipe->plane_state->tiling_info.gfx9.swizzle;
plane_state       343 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle);
plane_state       345 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	switch (pipe->plane_state->rotation) {
plane_state       360 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	switch (pipe->plane_state->format) {
plane_state       506 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			pipe->plane_state->flip_immediate);
plane_state       517 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	if (!primary_pipe->plane_state)
plane_state       871 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
plane_state       887 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		if (!pipe->plane_state) {
plane_state       918 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {
plane_state       919 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				if (pipe->plane_state->rotation % 2 == 0) {
plane_state       948 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			if (pipe->plane_state->rotation % 2 == 0) {
plane_state       965 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
plane_state       976 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 						pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no;
plane_state       980 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 					pipe->plane_state->format);
plane_state       982 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 					pipe->plane_state->tiling_info.gfx9.swizzle);
plane_state       997 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
plane_state      1178 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
plane_state      1206 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			if (pipe->plane_state) {
plane_state      1209 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				pipe->plane_state->update_flags.bits.full_update = 1;
plane_state      1220 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 					if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
plane_state      1239 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
plane_state      1244 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 					hsplit_pipe->plane_state = NULL;
plane_state       104 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 		if (!pipe_ctx->plane_state)
plane_state       110 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		if (!context->res_ctx.pipe_ctx[i].plane_state)
plane_state       284 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 				if (!context->res_ctx.pipe_ctx[i].plane_state)
plane_state       301 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 				if (!context->res_ctx.pipe_ctx[i].plane_state)
plane_state       912 drivers/gpu/drm/amd/display/dc/core/dc.c 			if (pipe_set[j]->plane_state) {
plane_state       937 drivers/gpu/drm/amd/display/dc/core/dc.c 			if (pipe_set[j]->plane_state) {
plane_state      1193 drivers/gpu/drm/amd/display/dc/core/dc.c 		if (!pipe->plane_state)
plane_state      1197 drivers/gpu/drm/amd/display/dc/core/dc.c 		pipe->plane_state->status.is_flip_pending = false;
plane_state      1199 drivers/gpu/drm/amd/display/dc/core/dc.c 		if (pipe->plane_state->status.is_flip_pending)
plane_state      1220 drivers/gpu/drm/amd/display/dc/core/dc.c 		    context->res_ctx.pipe_ctx[i].plane_state == NULL) {
plane_state      1357 drivers/gpu/drm/amd/display/dc/core/dc.c 		const struct dc_plane_state *plane_state)
plane_state      1364 drivers/gpu/drm/amd/display/dc/core/dc.c 		if (plane_state == pipe_ctx->plane_state) {
plane_state      2039 drivers/gpu/drm/amd/display/dc/core/dc.c 			struct dc_plane_state *plane_state = srf_updates[i].surface;
plane_state      2043 drivers/gpu/drm/amd/display/dc/core/dc.c 				if (!pipe_ctx->plane_state)
plane_state      2045 drivers/gpu/drm/amd/display/dc/core/dc.c 				if (pipe_ctx->plane_state != plane_state)
plane_state      2047 drivers/gpu/drm/amd/display/dc/core/dc.c 				plane_state->triplebuffer_flips = false;
plane_state      2050 drivers/gpu/drm/amd/display/dc/core/dc.c 					!plane_state->flip_immediate &&
plane_state      2053 drivers/gpu/drm/amd/display/dc/core/dc.c 						plane_state->triplebuffer_flips = true;
plane_state      2072 drivers/gpu/drm/amd/display/dc/core/dc.c 			if (!pipe_ctx->plane_state)
plane_state      2080 drivers/gpu/drm/amd/display/dc/core/dc.c 			ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
plane_state      2086 drivers/gpu/drm/amd/display/dc/core/dc.c 					dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
plane_state      2108 drivers/gpu/drm/amd/display/dc/core/dc.c 				struct dc_plane_state *plane_state = srf_updates[i].surface;
plane_state      2116 drivers/gpu/drm/amd/display/dc/core/dc.c 					if (pipe_ctx->plane_state != plane_state)
plane_state      2121 drivers/gpu/drm/amd/display/dc/core/dc.c 							plane_state->flip_immediate);
plane_state      2127 drivers/gpu/drm/amd/display/dc/core/dc.c 			struct dc_plane_state *plane_state = srf_updates[i].surface;
plane_state      2135 drivers/gpu/drm/amd/display/dc/core/dc.c 				if (pipe_ctx->plane_state != plane_state)
plane_state      2143 drivers/gpu/drm/amd/display/dc/core/dc.c 						dc, pipe_ctx, plane_state->triplebuffer_flips);
plane_state      2161 drivers/gpu/drm/amd/display/dc/core/dc.c 				!pipe_ctx->plane_state->update_flags.bits.addr_update)
plane_state      2207 drivers/gpu/drm/amd/display/dc/core/dc.c 			if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
plane_state      2208 drivers/gpu/drm/amd/display/dc/core/dc.c 				new_pipe->plane_state->force_full_update = true;
plane_state      2223 drivers/gpu/drm/amd/display/dc/core/dc.c 				if (pipe_ctx->plane_state != surface)
plane_state      2252 drivers/gpu/drm/amd/display/dc/core/dc.c 			if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
plane_state      2253 drivers/gpu/drm/amd/display/dc/core/dc.c 				pipe_ctx->plane_state->force_full_update = false;
plane_state        67 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 		const struct dc_plane_state *plane_state = plane_states[i];
plane_state        81 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->visible,
plane_state        82 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->flip_immediate,
plane_state        83 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->address.type,
plane_state        84 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->address.grph.addr.quad_part,
plane_state        85 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->address.grph.meta_addr.quad_part,
plane_state        86 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->scaling_quality.h_taps,
plane_state        87 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->scaling_quality.v_taps,
plane_state        88 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->scaling_quality.h_taps_c,
plane_state        89 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->scaling_quality.v_taps_c);
plane_state       104 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->src_rect.x,
plane_state       105 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->src_rect.y,
plane_state       106 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->src_rect.width,
plane_state       107 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->src_rect.height,
plane_state       108 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->dst_rect.x,
plane_state       109 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->dst_rect.y,
plane_state       110 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->dst_rect.width,
plane_state       111 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->dst_rect.height,
plane_state       112 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->clip_rect.x,
plane_state       113 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->clip_rect.y,
plane_state       114 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->clip_rect.width,
plane_state       115 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->clip_rect.height);
plane_state       123 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->plane_size.surface_size.x,
plane_state       124 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->plane_size.surface_size.y,
plane_state       125 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->plane_size.surface_size.width,
plane_state       126 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->plane_size.surface_size.height,
plane_state       127 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->plane_size.surface_pitch);
plane_state       142 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->tiling_info.gfx8.num_banks,
plane_state       143 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->tiling_info.gfx8.bank_width,
plane_state       144 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->tiling_info.gfx8.bank_width_c,
plane_state       145 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->tiling_info.gfx8.bank_height,
plane_state       146 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->tiling_info.gfx8.bank_height_c,
plane_state       147 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->tiling_info.gfx8.tile_aspect,
plane_state       148 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->tiling_info.gfx8.tile_aspect_c,
plane_state       149 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->tiling_info.gfx8.tile_split,
plane_state       150 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->tiling_info.gfx8.tile_split_c,
plane_state       151 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->tiling_info.gfx8.tile_mode,
plane_state       152 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->tiling_info.gfx8.tile_mode_c);
plane_state       162 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->tiling_info.gfx8.pipe_config,
plane_state       163 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->tiling_info.gfx8.array_mode,
plane_state       164 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->color_space,
plane_state       165 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->dcc.enable,
plane_state       166 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->format,
plane_state       167 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->rotation,
plane_state       168 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->stereo_format);
plane_state       171 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 				plane_state->tiling_info.gfx9.swizzle);
plane_state      2356 drivers/gpu/drm/amd/display/dc/core/dc_link.c 					if (core_dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL)
plane_state       549 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
plane_state       552 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct rect surf_src = plane_state->src_rect;
plane_state       557 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
plane_state       559 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
plane_state       571 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	dest = plane_state->dst_rect;
plane_state       572 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	clip.x = stream->src.x > plane_state->clip_rect.x ?
plane_state       573 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			stream->src.x : plane_state->clip_rect.x;
plane_state       576 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			plane_state->clip_rect.x + plane_state->clip_rect.width ?
plane_state       578 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
plane_state       580 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	clip.y = stream->src.y > plane_state->clip_rect.y ?
plane_state       581 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			stream->src.y : plane_state->clip_rect.y;
plane_state       584 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			plane_state->clip_rect.y + plane_state->clip_rect.height ?
plane_state       586 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
plane_state       593 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			plane_state->rotation,
plane_state       594 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			plane_state->horizontal_mirror,
plane_state       657 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
plane_state       659 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct rect surf_clip = plane_state->clip_rect;
plane_state       661 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state;
plane_state       663 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
plane_state       715 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
plane_state       717 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct rect surf_src = plane_state->src_rect;
plane_state       724 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
plane_state       725 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
plane_state       730 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 					plane_state->dst_rect.width);
plane_state       733 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 					plane_state->dst_rect.height);
plane_state       845 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
plane_state       848 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct rect src = pipe_ctx->plane_state->src_rect;
plane_state       858 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			plane_state->rotation,
plane_state       859 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			plane_state->horizontal_mirror,
plane_state       880 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	recout_skip_h = data->recout.x - (stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
plane_state       882 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 					src.x * plane_state->dst_rect.width / src.width
plane_state       884 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	recout_skip_v = data->recout.y - (stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
plane_state       886 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 					src.y * plane_state->dst_rect.height / src.height
plane_state       964 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
plane_state       973 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->plane_state->format);
plane_state       999 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
plane_state      1003 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
plane_state      1006 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	    plane_state->scaling_quality.integer_scaling &&
plane_state      1021 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 					&plane_state->scaling_quality);
plane_state      1027 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 					&plane_state->scaling_quality);
plane_state      1043 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				plane_state->dst_rect.height,
plane_state      1044 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				plane_state->dst_rect.width,
plane_state      1045 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				plane_state->dst_rect.x,
plane_state      1046 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				plane_state->dst_rect.y);
plane_state      1059 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
plane_state      1171 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (!head_pipe->plane_state)
plane_state      1177 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				!res_ctx->pipe_ctx[i].plane_state) {
plane_state      1205 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
plane_state      1210 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			if (split_pipe->top_pipe->plane_state)
plane_state      1233 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		struct dc_plane_state *plane_state,
plane_state      1254 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				plane_state, MAX_SURFACE_NUM);
plane_state      1266 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	dc_plane_state_retain(plane_state);
plane_state      1282 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			dc_plane_state_release(plane_state);
plane_state      1286 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		free_pipe->plane_state = plane_state;
plane_state      1301 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	stream_status->plane_states[stream_status->plane_count] = plane_state;
plane_state      1311 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		struct dc_plane_state *plane_state,
plane_state      1333 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		if (pipe_ctx->plane_state == plane_state) {
plane_state      1349 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				pipe_ctx->plane_state = NULL;
plane_state      1357 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		if (stream_status->plane_states[i] == plane_state) {
plane_state      2061 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 					pipe_ctx->plane_state &&
plane_state      2062 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 					pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
plane_state      2063 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				result = dc->res_pool->funcs->get_default_swizzle_mode(pipe_ctx->plane_state);
plane_state      2773 drivers/gpu/drm/amd/display/dc/core/dc_resource.c enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
plane_state      2779 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
plane_state       349 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 				!pipe_ctx->plane_state ||
plane_state        40 drivers/gpu/drm/amd/display/dc/core/dc_surface.c static void construct(struct dc_context *ctx, struct dc_plane_state *plane_state)
plane_state        42 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	plane_state->ctx = ctx;
plane_state        44 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	plane_state->gamma_correction = dc_create_gamma();
plane_state        45 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	if (plane_state->gamma_correction != NULL)
plane_state        46 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		plane_state->gamma_correction->is_identity = true;
plane_state        48 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	plane_state->in_transfer_func = dc_create_transfer_func();
plane_state        49 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	if (plane_state->in_transfer_func != NULL) {
plane_state        50 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		plane_state->in_transfer_func->type = TF_TYPE_BYPASS;
plane_state        51 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		plane_state->in_transfer_func->ctx = ctx;
plane_state        54 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	plane_state->in_shaper_func = dc_create_transfer_func();
plane_state        55 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	if (plane_state->in_shaper_func != NULL) {
plane_state        56 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		plane_state->in_shaper_func->type = TF_TYPE_BYPASS;
plane_state        57 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		plane_state->in_shaper_func->ctx = ctx;
plane_state        60 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	plane_state->lut3d_func = dc_create_3dlut_func();
plane_state        61 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	if (plane_state->lut3d_func != NULL) {
plane_state        62 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		plane_state->lut3d_func->ctx = ctx;
plane_state        64 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	plane_state->blend_tf = dc_create_transfer_func();
plane_state        65 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	if (plane_state->blend_tf != NULL) {
plane_state        66 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		plane_state->blend_tf->type = TF_TYPE_BYPASS;
plane_state        67 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		plane_state->blend_tf->ctx = ctx;
plane_state        73 drivers/gpu/drm/amd/display/dc/core/dc_surface.c static void destruct(struct dc_plane_state *plane_state)
plane_state        75 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	if (plane_state->gamma_correction != NULL) {
plane_state        76 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		dc_gamma_release(&plane_state->gamma_correction);
plane_state        78 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	if (plane_state->in_transfer_func != NULL) {
plane_state        80 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 				plane_state->in_transfer_func);
plane_state        81 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		plane_state->in_transfer_func = NULL;
plane_state        84 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	if (plane_state->in_shaper_func != NULL) {
plane_state        86 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 				plane_state->in_shaper_func);
plane_state        87 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		plane_state->in_shaper_func = NULL;
plane_state        89 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	if (plane_state->lut3d_func != NULL) {
plane_state        91 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 				plane_state->lut3d_func);
plane_state        92 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		plane_state->lut3d_func = NULL;
plane_state        94 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	if (plane_state->blend_tf != NULL) {
plane_state        96 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 				plane_state->blend_tf);
plane_state        97 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		plane_state->blend_tf = NULL;
plane_state       106 drivers/gpu/drm/amd/display/dc/core/dc_surface.c void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
plane_state       109 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	plane_state->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1;
plane_state       117 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	struct dc_plane_state *plane_state = kvzalloc(sizeof(*plane_state),
plane_state       120 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	if (NULL == plane_state)
plane_state       123 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	kref_init(&plane_state->refcount);
plane_state       124 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	construct(core_dc->ctx, plane_state);
plane_state       126 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	return plane_state;
plane_state       141 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		const struct dc_plane_state *plane_state)
plane_state       147 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	if (!plane_state ||
plane_state       148 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		!plane_state->ctx ||
plane_state       149 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		!plane_state->ctx->dc) {
plane_state       154 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	plane_status = &plane_state->status;
plane_state       155 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	core_dc = plane_state->ctx->dc;
plane_state       165 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		if (pipe_ctx->plane_state != plane_state)
plane_state       168 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		pipe_ctx->plane_state->status.is_flip_pending = false;
plane_state       177 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 		if (pipe_ctx->plane_state != plane_state)
plane_state       186 drivers/gpu/drm/amd/display/dc/core/dc_surface.c void dc_plane_state_retain(struct dc_plane_state *plane_state)
plane_state       188 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	kref_get(&plane_state->refcount);
plane_state       193 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount);
plane_state       194 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	destruct(plane_state);
plane_state       195 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	kvfree(plane_state);
plane_state       198 drivers/gpu/drm/amd/display/dc/core/dc_surface.c void dc_plane_state_release(struct dc_plane_state *plane_state)
plane_state       200 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	kref_put(&plane_state->refcount, dc_plane_state_free);
plane_state       825 drivers/gpu/drm/amd/display/dc/dc.h 		const struct dc_plane_state *plane_state);
plane_state       827 drivers/gpu/drm/amd/display/dc/dc.h void dc_plane_state_retain(struct dc_plane_state *plane_state);
plane_state       828 drivers/gpu/drm/amd/display/dc/dc.h void dc_plane_state_release(struct dc_plane_state *plane_state);
plane_state       873 drivers/gpu/drm/amd/display/dc/dc.h enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
plane_state       315 drivers/gpu/drm/amd/display/dc/dc_stream.h 		struct dc_plane_state *plane_state,
plane_state       321 drivers/gpu/drm/amd/display/dc/dc_stream.h 		struct dc_plane_state *plane_state,
plane_state       847 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
plane_state       850 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
plane_state        42 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps);
plane_state       244 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		const struct dc_plane_state *plane_state)
plane_state       248 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	switch (plane_state->format) {
plane_state       272 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			       const struct dc_plane_state *plane_state)
plane_state       282 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (plane_state->in_transfer_func)
plane_state       283 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		tf = plane_state->in_transfer_func;
plane_state       285 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	build_prescale_params(&prescale_params, plane_state);
plane_state       288 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (plane_state->gamma_correction &&
plane_state       289 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			!plane_state->gamma_correction->is_identity &&
plane_state       290 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			dce_use_lut(plane_state->format))
plane_state       291 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
plane_state      1841 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (!pipe_ctx->plane_state)
plane_state      1845 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
plane_state      2118 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
plane_state      2165 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		if (pipe_ctx->bottom_pipe->plane_state->visible) {
plane_state      2166 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			if (pipe_ctx->plane_state->visible)
plane_state      2171 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		} else if (!pipe_ctx->plane_state->visible)
plane_state      2174 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	} else if (!pipe_ctx->plane_state->visible)
plane_state      2203 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
plane_state      2205 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (plane_state == NULL)
plane_state      2210 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			&plane_state->address,
plane_state      2211 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			plane_state->flip_immediate);
plane_state      2213 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	plane_state->status.requested_address = plane_state->address;
plane_state      2218 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
plane_state      2220 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (plane_state == NULL)
plane_state      2223 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	plane_state->status.is_flip_pending =
plane_state      2227 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (plane_state->status.is_flip_pending && !plane_state->visible)
plane_state      2230 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
plane_state      2233 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		plane_state->status.is_right_eye =\
plane_state      2468 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
plane_state      2513 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			plane_state->format,
plane_state      2514 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			&plane_state->tiling_info,
plane_state      2515 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			&plane_state->plane_size,
plane_state      2516 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			plane_state->rotation,
plane_state      2520 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
plane_state      2525 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				plane_state->format,
plane_state      2526 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				&plane_state->tiling_info,
plane_state      2527 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				plane_state->rotation);
plane_state      2530 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (pipe_ctx->plane_state->update_flags.bits.full_update ||
plane_state      2531 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
plane_state      2532 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_state->update_flags.bits.gamma_change)
plane_state      2533 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
plane_state      2535 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (pipe_ctx->plane_state->update_flags.bits.full_update)
plane_state      2545 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			(void *) pipe_ctx->plane_state,
plane_state      2546 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_state->address.grph.addr.high_part,
plane_state      2547 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_state->address.grph.addr.low_part,
plane_state      2548 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_state->src_rect.x,
plane_state      2549 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_state->src_rect.y,
plane_state      2550 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_state->src_rect.width,
plane_state      2551 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_state->src_rect.height,
plane_state      2552 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_state->dst_rect.x,
plane_state      2553 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_state->dst_rect.y,
plane_state      2554 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_state->dst_rect.width,
plane_state      2555 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_state->dst_rect.height,
plane_state      2556 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_state->clip_rect.x,
plane_state      2557 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_state->clip_rect.y,
plane_state      2558 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_state->clip_rect.width,
plane_state      2559 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_state->clip_rect.height);
plane_state      2596 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				(pipe_ctx->plane_state || old_pipe_ctx->plane_state))
plane_state      2629 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			(pipe_ctx->plane_state || old_pipe_ctx->plane_state))
plane_state      2694 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		.rotation = pipe_ctx->plane_state->rotation,
plane_state      2695 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		.mirror = pipe_ctx->plane_state->horizontal_mirror
plane_state      2698 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (pipe_ctx->plane_state->address.type
plane_state      2702 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
plane_state       860 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	if (!pipe_ctx->plane_state)
plane_state       862 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
plane_state       964 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,
plane_state       967 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) ||
plane_state       968 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	    ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height))
plane_state      1058 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	pipe_ctx->plane_state = NULL;
plane_state      1339 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
plane_state      1341 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
plane_state      1342 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
plane_state      1347 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		*addr = plane_state->address.grph_stereo.left_addr;
plane_state      1348 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->address.grph_stereo.left_addr =
plane_state      1349 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->address.grph_stereo.right_addr;
plane_state      1353 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
plane_state      1354 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
plane_state      1355 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			plane_state->address.grph_stereo.right_addr =
plane_state      1356 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			plane_state->address.grph_stereo.left_addr;
plane_state      1368 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
plane_state      1370 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (plane_state == NULL)
plane_state      1377 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			&plane_state->address,
plane_state      1378 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			plane_state->flip_immediate);
plane_state      1380 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	plane_state->status.requested_address = plane_state->address;
plane_state      1382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (plane_state->flip_immediate)
plane_state      1383 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->status.current_address = plane_state->address;
plane_state      1386 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
plane_state      1390 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 					  const struct dc_plane_state *plane_state)
plane_state      1399 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (plane_state->in_transfer_func)
plane_state      1400 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		tf = plane_state->in_transfer_func;
plane_state      1402 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (plane_state->gamma_correction &&
plane_state      1404 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		&& !plane_state->gamma_correction->is_identity
plane_state      1405 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			&& dce_use_lut(plane_state->format))
plane_state      1406 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
plane_state      1915 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (pipe_ctx->plane_state && pipe_ctx->plane_state->layer_index > 0 && is_rgb_cspace(colorspace)) {
plane_state      1921 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			if (top->plane_state && top->plane_state->layer_index == 0)
plane_state      1976 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
plane_state      1985 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
plane_state      1994 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
plane_state      2141 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		const struct dc_plane_state *plane_state)
plane_state      2143 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
plane_state      2144 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			&& plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
plane_state      2145 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			&& plane_state->input_csc_color_matrix.enable_adjustment
plane_state      2146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			&& plane_state->coeff_reduction_factor.value != 0) {
plane_state      2148 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			dc_fixpt_mul(plane_state->coeff_reduction_factor,
plane_state      2161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
plane_state      2167 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			plane_state->format,
plane_state      2169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			plane_state->input_csc_color_matrix,
plane_state      2171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			plane_state->color_space,
plane_state      2174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			plane_state->color_space);
plane_state      2178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	dcn10_build_prescale_params(&bns_params, plane_state);
plane_state      2187 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
plane_state      2213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (pipe_ctx->plane_state->global_alpha)
plane_state      2214 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
plane_state      2237 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
plane_state      2270 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
plane_state      2286 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
plane_state      2287 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct plane_size size = plane_state->plane_size;
plane_state      2294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (plane_state->update_flags.bits.full_update) {
plane_state      2319 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (plane_state->update_flags.bits.full_update) {
plane_state      2336 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (plane_state->update_flags.bits.full_update ||
plane_state      2337 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->update_flags.bits.bpp_change)
plane_state      2338 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		update_dpp(dpp, plane_state);
plane_state      2340 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (plane_state->update_flags.bits.full_update ||
plane_state      2341 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->update_flags.bits.per_pixel_alpha_change ||
plane_state      2342 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->update_flags.bits.global_alpha_change)
plane_state      2345 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (plane_state->update_flags.bits.full_update ||
plane_state      2346 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->update_flags.bits.per_pixel_alpha_change ||
plane_state      2347 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->update_flags.bits.global_alpha_change ||
plane_state      2348 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->update_flags.bits.scaling_change ||
plane_state      2349 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->update_flags.bits.position_change) {
plane_state      2353 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (plane_state->update_flags.bits.full_update ||
plane_state      2354 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->update_flags.bits.scaling_change ||
plane_state      2355 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->update_flags.bits.position_change) {
plane_state      2370 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (plane_state->update_flags.bits.full_update) {
plane_state      2381 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (plane_state->update_flags.bits.full_update ||
plane_state      2382 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->update_flags.bits.pixel_format_change ||
plane_state      2383 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->update_flags.bits.horizontal_mirror_change ||
plane_state      2384 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->update_flags.bits.rotation_change ||
plane_state      2385 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->update_flags.bits.swizzle_change ||
plane_state      2386 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->update_flags.bits.dcc_change ||
plane_state      2387 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->update_flags.bits.bpp_change ||
plane_state      2388 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->update_flags.bits.scaling_change ||
plane_state      2389 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->update_flags.bits.plane_size_change) {
plane_state      2392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			plane_state->format,
plane_state      2393 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			&plane_state->tiling_info,
plane_state      2395 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			plane_state->rotation,
plane_state      2396 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			&plane_state->dcc,
plane_state      2397 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			plane_state->horizontal_mirror,
plane_state      2455 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pipe_ctx->plane_state->sdr_white_level, 80);
plane_state      2463 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (pipe_ctx->plane_state->sdr_white_level > 80)
plane_state      2475 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (pipe_ctx->plane_state->update_flags.bits.full_update)
plane_state      2482 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (pipe_ctx->plane_state->update_flags.bits.full_update ||
plane_state      2483 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
plane_state      2484 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pipe_ctx->plane_state->update_flags.bits.gamma_change)
plane_state      2485 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
plane_state      2493 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (pipe_ctx->plane_state->update_flags.bits.full_update)
plane_state      2519 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (pipe_ctx->plane_state != NULL)
plane_state      2538 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
plane_state      2570 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	interdependent_update = top_pipe_to_program->plane_state &&
plane_state      2571 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		top_pipe_to_program->plane_state->update_flags.bits.full_update;
plane_state      2605 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
plane_state      2612 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if ((!pipe_ctx->plane_state ||
plane_state      2614 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		    old_pipe_ctx->plane_state &&
plane_state      2638 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			    !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg))
plane_state      2924 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
plane_state      2928 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (plane_state == NULL)
plane_state      2934 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	plane_state->status.is_flip_pending = plane_state->status.is_flip_pending || flip_pending;
plane_state      2937 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->status.current_address = plane_state->status.requested_address;
plane_state      2939 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (plane_state->status.current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
plane_state      2941 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		plane_state->status.is_right_eye =
plane_state      2965 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		.rotation = pipe_ctx->plane_state->rotation,
plane_state      2966 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		.mirror = pipe_ctx->plane_state->horizontal_mirror
plane_state      2968 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	uint32_t x_plane = pipe_ctx->plane_state->dst_rect.x;
plane_state      2969 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	uint32_t y_plane = pipe_ctx->plane_state->dst_rect.y;
plane_state      2978 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (pipe_ctx->plane_state->address.type
plane_state      3009 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 					|| pos_cpy.x <= (int)hubp->curs_attr.width + pipe_ctx->plane_state->src_rect.x) {
plane_state      3120 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		    !pipe_ctx->stream || !pipe_ctx->plane_state ||
plane_state        89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h 		const struct dc_plane_state *plane_state);
plane_state      1137 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
plane_state      1139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
plane_state      1141 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 			&& plane_state->src_rect.width > caps->max_video_width)
plane_state      1197 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plane_state)
plane_state      1201 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	enum surface_pixel_format surf_pix_format = plane_state->format;
plane_state      1211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	plane_state->tiling_info.gfx9.swizzle = swizzle;
plane_state       506 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	pipe_ctx->plane_state = NULL;
plane_state       691 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
plane_state       697 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (plane_state->blend_tf) {
plane_state       698 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
plane_state       699 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			blend_lut = &plane_state->blend_tf->pwl;
plane_state       700 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
plane_state       702 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 					plane_state->blend_tf,
plane_state       713 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
plane_state       719 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (plane_state->in_shaper_func) {
plane_state       720 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
plane_state       721 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			shaper_lut = &plane_state->in_shaper_func->pwl;
plane_state       722 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
plane_state       724 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 					plane_state->in_shaper_func,
plane_state       731 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (plane_state->lut3d_func &&
plane_state       732 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		plane_state->lut3d_func->state.bits.initialized == 1)
plane_state       734 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 								&plane_state->lut3d_func->lut_3d);
plane_state       738 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (plane_state->lut3d_func &&
plane_state       739 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		plane_state->lut3d_func->state.bits.initialized == 1 &&
plane_state       740 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		plane_state->lut3d_func->hdr_multiplier != 0)
plane_state       742 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 				plane_state->lut3d_func->hdr_multiplier);
plane_state       750 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 					  const struct dc_plane_state *plane_state)
plane_state       757 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (dpp_base == NULL || plane_state == NULL)
plane_state       760 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dcn20_set_shaper_3dlut(pipe_ctx, plane_state);
plane_state       761 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	dcn20_set_blend_lut(pipe_ctx, plane_state);
plane_state       763 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (plane_state->in_transfer_func)
plane_state       764 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		tf = plane_state->in_transfer_func;
plane_state      1006 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	pipe_ctx->plane_state->update_flags.bits.full_update =
plane_state      1007 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			context->commit_hints.full_update_needed ? 1 : pipe_ctx->plane_state->update_flags.bits.full_update;
plane_state      1009 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (pipe_ctx->plane_state->update_flags.bits.full_update)
plane_state      1016 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (pipe_ctx->plane_state->update_flags.bits.full_update ||
plane_state      1017 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
plane_state      1018 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			pipe_ctx->plane_state->update_flags.bits.gamma_change)
plane_state      1019 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
plane_state      1027 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (pipe_ctx->plane_state->update_flags.bits.full_update)
plane_state      1055 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (pipe_ctx->plane_state != NULL)
plane_state      1102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (pipe->plane_state != NULL)
plane_state      1103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		flip_immediate = pipe->plane_state->flip_immediate;
plane_state      1132 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
plane_state      1179 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	interdependent_update = top_pipe_to_program->plane_state &&
plane_state      1180 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		top_pipe_to_program->plane_state->update_flags.bits.full_update;
plane_state      1203 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
plane_state      1210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		if ((!pipe_ctx->plane_state ||
plane_state      1212 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		     old_pipe_ctx->plane_state &&
plane_state      1236 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			    !pipe_ctx->plane_state || !tg->funcs->is_tg_enabled(tg))
plane_state      1262 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			(prev_top_pipe_to_program == NULL || prev_top_pipe_to_program->plane_state == NULL)) {
plane_state      1325 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		if (pipe_ctx->plane_state == NULL)
plane_state      1530 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
plane_state      1532 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
plane_state      1533 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
plane_state      1538 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		*addr = plane_state->address.grph_stereo.left_addr;
plane_state      1539 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		plane_state->address.grph_stereo.left_addr =
plane_state      1540 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 				plane_state->address.grph_stereo.right_addr;
plane_state      1545 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
plane_state      1546 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
plane_state      1547 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		plane_state->address.grph_stereo.right_addr =
plane_state      1548 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 				plane_state->address.grph_stereo.left_addr;
plane_state      1558 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
plane_state      1560 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (plane_state == NULL)
plane_state      1566 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
plane_state      1570 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			&plane_state->address,
plane_state      1571 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			plane_state->flip_immediate);
plane_state      1573 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	plane_state->status.requested_address = plane_state->address;
plane_state      1575 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (plane_state->flip_immediate)
plane_state      1576 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		plane_state->status.current_address = plane_state->address;
plane_state      1579 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
plane_state      1728 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
plane_state      1751 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (pipe_ctx->plane_state->global_alpha)
plane_state      1752 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
plane_state      1774 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
plane_state        72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h 			const struct dc_plane_state *plane_state);
plane_state      1751 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	if (prev_odm_pipe->plane_state) {
plane_state      1830 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	ASSERT(primary_pipe->plane_state);
plane_state      1948 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
plane_state      1949 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				== res_ctx->pipe_ctx[i].plane_state)
plane_state      2044 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (!res_ctx->pipe_ctx[i].plane_state) {
plane_state      2071 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
plane_state      2076 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 					&& res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
plane_state      2078 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 					&& res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
plane_state      2101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			if (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) {
plane_state      2106 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			} else if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) {
plane_state      2400 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			odm_pipe->plane_state = NULL;
plane_state      2415 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (pipe->plane_state)
plane_state      2424 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
plane_state      2430 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		hsplit_pipe->plane_state = NULL;
plane_state      2438 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (pipe->plane_state)
plane_state      2544 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
plane_state      2555 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (!pipe->plane_state)
plane_state      2558 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
plane_state      2578 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
plane_state      2583 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
plane_state      2602 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
plane_state      2986 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state)
plane_state      2990 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	enum surface_pixel_format surf_pix_format = plane_state->format;
plane_state      3000 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	plane_state->tiling_info.gfx9.swizzle = swizzle;
plane_state       135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state);
plane_state        46 drivers/gpu/drm/amd/display/dc/inc/core_types.h void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
plane_state       118 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps);
plane_state       130 drivers/gpu/drm/amd/display/dc/inc/core_types.h 			struct dc_plane_state *plane_state);
plane_state       289 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct dc_plane_state *plane_state;
plane_state       158 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h 				const struct dc_plane_state *plane_state);
plane_state       134 drivers/gpu/drm/amd/display/dc/inc/resource.h 		struct dc_plane_state *const *plane_state,
plane_state       258 drivers/gpu/drm/armada/armada_overlay.c 	struct drm_plane_state *plane_state;
plane_state       270 drivers/gpu/drm/armada/armada_overlay.c 	plane_state = drm_atomic_get_plane_state(state, plane);
plane_state       271 drivers/gpu/drm/armada/armada_overlay.c 	if (IS_ERR(plane_state)) {
plane_state       272 drivers/gpu/drm/armada/armada_overlay.c 		ret = PTR_ERR(plane_state);
plane_state       276 drivers/gpu/drm/armada/armada_overlay.c 	ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
plane_state       280 drivers/gpu/drm/armada/armada_overlay.c 	drm_atomic_set_fb_for_plane(plane_state, fb);
plane_state       281 drivers/gpu/drm/armada/armada_overlay.c 	plane_state->crtc_x = crtc_x;
plane_state       282 drivers/gpu/drm/armada/armada_overlay.c 	plane_state->crtc_y = crtc_y;
plane_state       283 drivers/gpu/drm/armada/armada_overlay.c 	plane_state->crtc_h = crtc_h;
plane_state       284 drivers/gpu/drm/armada/armada_overlay.c 	plane_state->crtc_w = crtc_w;
plane_state       285 drivers/gpu/drm/armada/armada_overlay.c 	plane_state->src_x = src_x;
plane_state       286 drivers/gpu/drm/armada/armada_overlay.c 	plane_state->src_y = src_y;
plane_state       287 drivers/gpu/drm/armada/armada_overlay.c 	plane_state->src_h = src_h;
plane_state       288 drivers/gpu/drm/armada/armada_overlay.c 	plane_state->src_w = src_w;
plane_state       143 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c 			      struct drm_plane_state *plane_state)
plane_state       163 drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c 				   struct drm_plane_state *plane_state)
plane_state       487 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 		struct atmel_hlcdc_plane_state *plane_state;
plane_state       496 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 		plane_state =
plane_state       499 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 		pixels = (plane_state->src_w * plane_state->src_h) -
plane_state       500 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 			 (plane_state->disc_w * plane_state->disc_h);
plane_state       502 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 		for (i = 0; i < plane_state->nplanes; i++)
plane_state       503 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 			load += pixels * plane_state->bpp[i];
plane_state       506 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 			plane_state->ahb_id = 0;
plane_state       508 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 			plane_state->ahb_id = 1;
plane_state       510 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c 		ahb_load[plane_state->ahb_id] += load;
plane_state        48 drivers/gpu/drm/bochs/bochs_kms.c 			      struct drm_plane_state *plane_state)
plane_state        53 drivers/gpu/drm/bochs/bochs_kms.c 	bochs_plane_update(bochs, plane_state);
plane_state       402 drivers/gpu/drm/cirrus/cirrus.c 			     struct drm_plane_state *plane_state,
plane_state       405 drivers/gpu/drm/cirrus/cirrus.c 	struct drm_framebuffer *fb = plane_state->fb;
plane_state       414 drivers/gpu/drm/cirrus/cirrus.c 			       struct drm_plane_state *plane_state)
plane_state       418 drivers/gpu/drm/cirrus/cirrus.c 	cirrus_mode_set(cirrus, &crtc_state->mode, plane_state->fb);
plane_state       419 drivers/gpu/drm/cirrus/cirrus.c 	cirrus_fb_blit_fullscreen(plane_state->fb);
plane_state       467 drivers/gpu/drm/drm_atomic.c 	struct drm_plane_state *plane_state;
plane_state       476 drivers/gpu/drm/drm_atomic.c 	plane_state = drm_atomic_get_existing_plane_state(state, plane);
plane_state       477 drivers/gpu/drm/drm_atomic.c 	if (plane_state)
plane_state       478 drivers/gpu/drm/drm_atomic.c 		return plane_state;
plane_state       484 drivers/gpu/drm/drm_atomic.c 	plane_state = plane->funcs->atomic_duplicate_state(plane);
plane_state       485 drivers/gpu/drm/drm_atomic.c 	if (!plane_state)
plane_state       488 drivers/gpu/drm/drm_atomic.c 	state->planes[index].state = plane_state;
plane_state       491 drivers/gpu/drm/drm_atomic.c 	state->planes[index].new_state = plane_state;
plane_state       492 drivers/gpu/drm/drm_atomic.c 	plane_state->state = state;
plane_state       495 drivers/gpu/drm/drm_atomic.c 			 plane->base.id, plane->name, plane_state, state);
plane_state       497 drivers/gpu/drm/drm_atomic.c 	if (plane_state->crtc) {
plane_state       501 drivers/gpu/drm/drm_atomic.c 						       plane_state->crtc);
plane_state       506 drivers/gpu/drm/drm_atomic.c 	return plane_state;
plane_state      1112 drivers/gpu/drm/drm_atomic.c 		struct drm_plane_state *plane_state =
plane_state      1115 drivers/gpu/drm/drm_atomic.c 		if (IS_ERR(plane_state))
plane_state      1116 drivers/gpu/drm/drm_atomic.c 			return PTR_ERR(plane_state);
plane_state      1260 drivers/gpu/drm/drm_atomic.c 				      struct drm_plane_state *plane_state)
plane_state      1264 drivers/gpu/drm/drm_atomic.c 	ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
plane_state      1268 drivers/gpu/drm/drm_atomic.c 	drm_atomic_set_fb_for_plane(plane_state, NULL);
plane_state      1269 drivers/gpu/drm/drm_atomic.c 	plane_state->crtc_x = 0;
plane_state      1270 drivers/gpu/drm/drm_atomic.c 	plane_state->crtc_y = 0;
plane_state      1271 drivers/gpu/drm/drm_atomic.c 	plane_state->crtc_w = 0;
plane_state      1272 drivers/gpu/drm/drm_atomic.c 	plane_state->crtc_h = 0;
plane_state      1273 drivers/gpu/drm/drm_atomic.c 	plane_state->src_x = 0;
plane_state      1274 drivers/gpu/drm/drm_atomic.c 	plane_state->src_y = 0;
plane_state      1275 drivers/gpu/drm/drm_atomic.c 	plane_state->src_w = 0;
plane_state      1276 drivers/gpu/drm/drm_atomic.c 	plane_state->src_h = 0;
plane_state      1430 drivers/gpu/drm/drm_atomic.c 	struct drm_plane_state *plane_state;
plane_state      1439 drivers/gpu/drm/drm_atomic.c 	for_each_new_plane_in_state(state, plane, plane_state, i)
plane_state      1440 drivers/gpu/drm/drm_atomic.c 		drm_atomic_plane_print_state(&p, plane_state);
plane_state        75 drivers/gpu/drm/drm_atomic_helper.c 				struct drm_plane_state *plane_state,
plane_state        90 drivers/gpu/drm/drm_atomic_helper.c 	if (plane_state->crtc) {
plane_state        91 drivers/gpu/drm/drm_atomic_helper.c 		crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
plane_state       767 drivers/gpu/drm/drm_atomic_helper.c int drm_atomic_helper_check_plane_state(struct drm_plane_state *plane_state,
plane_state       774 drivers/gpu/drm/drm_atomic_helper.c 	struct drm_framebuffer *fb = plane_state->fb;
plane_state       775 drivers/gpu/drm/drm_atomic_helper.c 	struct drm_rect *src = &plane_state->src;
plane_state       776 drivers/gpu/drm/drm_atomic_helper.c 	struct drm_rect *dst = &plane_state->dst;
plane_state       777 drivers/gpu/drm/drm_atomic_helper.c 	unsigned int rotation = plane_state->rotation;
plane_state       781 drivers/gpu/drm/drm_atomic_helper.c 	WARN_ON(plane_state->crtc && plane_state->crtc != crtc_state->crtc);
plane_state       783 drivers/gpu/drm/drm_atomic_helper.c 	*src = drm_plane_state_src(plane_state);
plane_state       784 drivers/gpu/drm/drm_atomic_helper.c 	*dst = drm_plane_state_dest(plane_state);
plane_state       787 drivers/gpu/drm/drm_atomic_helper.c 		plane_state->visible = false;
plane_state       792 drivers/gpu/drm/drm_atomic_helper.c 	if (WARN_ON(!plane_state->crtc)) {
plane_state       793 drivers/gpu/drm/drm_atomic_helper.c 		plane_state->visible = false;
plane_state       809 drivers/gpu/drm/drm_atomic_helper.c 		drm_rect_debug_print("src: ", &plane_state->src, true);
plane_state       810 drivers/gpu/drm/drm_atomic_helper.c 		drm_rect_debug_print("dst: ", &plane_state->dst, false);
plane_state       817 drivers/gpu/drm/drm_atomic_helper.c 	plane_state->visible = drm_rect_clip_scaled(src, dst, &clip);
plane_state       821 drivers/gpu/drm/drm_atomic_helper.c 	if (!plane_state->visible)
plane_state      1718 drivers/gpu/drm/drm_atomic_helper.c 	struct drm_plane_state *plane_state;
plane_state      1722 drivers/gpu/drm/drm_atomic_helper.c 	for_each_new_plane_in_state(state, plane, plane_state, i) {
plane_state      1723 drivers/gpu/drm/drm_atomic_helper.c 		struct drm_framebuffer *new_fb = plane_state->fb;
plane_state      1727 drivers/gpu/drm/drm_atomic_helper.c 		funcs->atomic_async_update(plane, plane_state);
plane_state      1735 drivers/gpu/drm/drm_atomic_helper.c 		WARN_ON_ONCE(plane->state->crtc_x != plane_state->crtc_x);
plane_state      1736 drivers/gpu/drm/drm_atomic_helper.c 		WARN_ON_ONCE(plane->state->crtc_y != plane_state->crtc_y);
plane_state      1737 drivers/gpu/drm/drm_atomic_helper.c 		WARN_ON_ONCE(plane->state->src_x != plane_state->src_x);
plane_state      1738 drivers/gpu/drm/drm_atomic_helper.c 		WARN_ON_ONCE(plane->state->src_y != plane_state->src_y);
plane_state      1744 drivers/gpu/drm/drm_atomic_helper.c 		WARN_ON_ONCE(plane_state->fb != old_fb);
plane_state      2643 drivers/gpu/drm/drm_atomic_helper.c 		struct drm_plane_state *plane_state;
plane_state      2650 drivers/gpu/drm/drm_atomic_helper.c 			plane_state = new_plane_state;
plane_state      2652 drivers/gpu/drm/drm_atomic_helper.c 			plane_state = old_plane_state;
plane_state      2657 drivers/gpu/drm/drm_atomic_helper.c 			funcs->cleanup_fb(plane, plane_state);
plane_state      2838 drivers/gpu/drm/drm_atomic_helper.c 	struct drm_plane_state *plane_state;
plane_state      2846 drivers/gpu/drm/drm_atomic_helper.c 	plane_state = drm_atomic_get_plane_state(state, plane);
plane_state      2847 drivers/gpu/drm/drm_atomic_helper.c 	if (IS_ERR(plane_state)) {
plane_state      2848 drivers/gpu/drm/drm_atomic_helper.c 		ret = PTR_ERR(plane_state);
plane_state      2852 drivers/gpu/drm/drm_atomic_helper.c 	ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
plane_state      2855 drivers/gpu/drm/drm_atomic_helper.c 	drm_atomic_set_fb_for_plane(plane_state, fb);
plane_state      2856 drivers/gpu/drm/drm_atomic_helper.c 	plane_state->crtc_x = crtc_x;
plane_state      2857 drivers/gpu/drm/drm_atomic_helper.c 	plane_state->crtc_y = crtc_y;
plane_state      2858 drivers/gpu/drm/drm_atomic_helper.c 	plane_state->crtc_w = crtc_w;
plane_state      2859 drivers/gpu/drm/drm_atomic_helper.c 	plane_state->crtc_h = crtc_h;
plane_state      2860 drivers/gpu/drm/drm_atomic_helper.c 	plane_state->src_x = src_x;
plane_state      2861 drivers/gpu/drm/drm_atomic_helper.c 	plane_state->src_y = src_y;
plane_state      2862 drivers/gpu/drm/drm_atomic_helper.c 	plane_state->src_w = src_w;
plane_state      2863 drivers/gpu/drm/drm_atomic_helper.c 	plane_state->src_h = src_h;
plane_state      2889 drivers/gpu/drm/drm_atomic_helper.c 	struct drm_plane_state *plane_state;
plane_state      2897 drivers/gpu/drm/drm_atomic_helper.c 	plane_state = drm_atomic_get_plane_state(state, plane);
plane_state      2898 drivers/gpu/drm/drm_atomic_helper.c 	if (IS_ERR(plane_state)) {
plane_state      2899 drivers/gpu/drm/drm_atomic_helper.c 		ret = PTR_ERR(plane_state);
plane_state      2903 drivers/gpu/drm/drm_atomic_helper.c 	if (plane_state->crtc && plane_state->crtc->cursor == plane)
plane_state      2904 drivers/gpu/drm/drm_atomic_helper.c 		plane_state->state->legacy_cursor_update = true;
plane_state      2906 drivers/gpu/drm/drm_atomic_helper.c 	ret = __drm_atomic_helper_disable_plane(plane, plane_state);
plane_state      2990 drivers/gpu/drm/drm_atomic_helper.c 	struct drm_plane_state *plane_state;
plane_state      3030 drivers/gpu/drm/drm_atomic_helper.c 	for_each_new_plane_in_state(state, plane, plane_state, i) {
plane_state      3031 drivers/gpu/drm/drm_atomic_helper.c 		ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
plane_state      3035 drivers/gpu/drm/drm_atomic_helper.c 		drm_atomic_set_fb_for_plane(plane_state, NULL);
plane_state      3124 drivers/gpu/drm/drm_atomic_helper.c 		struct drm_plane_state *plane_state;
plane_state      3126 drivers/gpu/drm/drm_atomic_helper.c 		plane_state = drm_atomic_get_plane_state(state, plane);
plane_state      3127 drivers/gpu/drm/drm_atomic_helper.c 		if (IS_ERR(plane_state)) {
plane_state      3128 drivers/gpu/drm/drm_atomic_helper.c 			err = PTR_ERR(plane_state);
plane_state      3302 drivers/gpu/drm/drm_atomic_helper.c 	struct drm_plane_state *plane_state;
plane_state      3313 drivers/gpu/drm/drm_atomic_helper.c 	plane_state = drm_atomic_get_plane_state(state, plane);
plane_state      3314 drivers/gpu/drm/drm_atomic_helper.c 	if (IS_ERR(plane_state))
plane_state      3315 drivers/gpu/drm/drm_atomic_helper.c 		return PTR_ERR(plane_state);
plane_state      3317 drivers/gpu/drm/drm_atomic_helper.c 	ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
plane_state      3320 drivers/gpu/drm/drm_atomic_helper.c 	drm_atomic_set_fb_for_plane(plane_state, fb);
plane_state       177 drivers/gpu/drm/drm_atomic_uapi.c drm_atomic_set_crtc_for_plane(struct drm_plane_state *plane_state,
plane_state       180 drivers/gpu/drm/drm_atomic_uapi.c 	struct drm_plane *plane = plane_state->plane;
plane_state       183 drivers/gpu/drm/drm_atomic_uapi.c 	if (plane_state->crtc == crtc)
plane_state       185 drivers/gpu/drm/drm_atomic_uapi.c 	if (plane_state->crtc) {
plane_state       186 drivers/gpu/drm/drm_atomic_uapi.c 		crtc_state = drm_atomic_get_crtc_state(plane_state->state,
plane_state       187 drivers/gpu/drm/drm_atomic_uapi.c 						       plane_state->crtc);
plane_state       194 drivers/gpu/drm/drm_atomic_uapi.c 	plane_state->crtc = crtc;
plane_state       197 drivers/gpu/drm/drm_atomic_uapi.c 		crtc_state = drm_atomic_get_crtc_state(plane_state->state,
plane_state       206 drivers/gpu/drm/drm_atomic_uapi.c 				 plane->base.id, plane->name, plane_state,
plane_state       210 drivers/gpu/drm/drm_atomic_uapi.c 				 plane->base.id, plane->name, plane_state);
plane_state       227 drivers/gpu/drm/drm_atomic_uapi.c drm_atomic_set_fb_for_plane(struct drm_plane_state *plane_state,
plane_state       230 drivers/gpu/drm/drm_atomic_uapi.c 	struct drm_plane *plane = plane_state->plane;
plane_state       235 drivers/gpu/drm/drm_atomic_uapi.c 				 plane_state);
plane_state       238 drivers/gpu/drm/drm_atomic_uapi.c 				 plane->base.id, plane->name, plane_state);
plane_state       240 drivers/gpu/drm/drm_atomic_uapi.c 	drm_framebuffer_assign(&plane_state->fb, fb);
plane_state       269 drivers/gpu/drm/drm_atomic_uapi.c drm_atomic_set_fence_for_plane(struct drm_plane_state *plane_state,
plane_state       272 drivers/gpu/drm/drm_atomic_uapi.c 	if (plane_state->fence) {
plane_state       277 drivers/gpu/drm/drm_atomic_uapi.c 	plane_state->fence = fence;
plane_state      1006 drivers/gpu/drm/drm_atomic_uapi.c 		struct drm_plane_state *plane_state;
plane_state      1008 drivers/gpu/drm/drm_atomic_uapi.c 		plane_state = drm_atomic_get_plane_state(state, plane);
plane_state      1009 drivers/gpu/drm/drm_atomic_uapi.c 		if (IS_ERR(plane_state)) {
plane_state      1010 drivers/gpu/drm/drm_atomic_uapi.c 			ret = PTR_ERR(plane_state);
plane_state      1015 drivers/gpu/drm/drm_atomic_uapi.c 				plane_state, file_priv,
plane_state       445 drivers/gpu/drm/drm_blend.c 		struct drm_plane_state *plane_state =
plane_state       447 drivers/gpu/drm/drm_blend.c 		if (IS_ERR(plane_state)) {
plane_state       448 drivers/gpu/drm/drm_blend.c 			ret = PTR_ERR(plane_state);
plane_state       451 drivers/gpu/drm/drm_blend.c 		states[n++] = plane_state;
plane_state       454 drivers/gpu/drm/drm_blend.c 				 plane_state->zpos);
plane_state       918 drivers/gpu/drm/drm_client_modeset.c 		struct drm_plane_state *plane_state;
plane_state       920 drivers/gpu/drm/drm_client_modeset.c 		plane_state = drm_atomic_get_plane_state(state, plane);
plane_state       921 drivers/gpu/drm/drm_client_modeset.c 		if (IS_ERR(plane_state)) {
plane_state       922 drivers/gpu/drm/drm_client_modeset.c 			ret = PTR_ERR(plane_state);
plane_state       926 drivers/gpu/drm/drm_client_modeset.c 		plane_state->rotation = DRM_MODE_ROTATE_0;
plane_state       932 drivers/gpu/drm/drm_client_modeset.c 		ret = __drm_atomic_helper_disable_plane(plane, plane_state);
plane_state       942 drivers/gpu/drm/drm_client_modeset.c 			struct drm_plane_state *plane_state;
plane_state       945 drivers/gpu/drm/drm_client_modeset.c 			plane_state = drm_atomic_get_new_plane_state(state, primary);
plane_state       946 drivers/gpu/drm/drm_client_modeset.c 			plane_state->rotation = rotation;
plane_state       229 drivers/gpu/drm/drm_crtc_internal.h 				      struct drm_plane_state *plane_state);
plane_state       121 drivers/gpu/drm/drm_damage_helper.c 					  struct drm_plane_state *plane_state)
plane_state       125 drivers/gpu/drm/drm_damage_helper.c 	if (plane_state->crtc) {
plane_state       127 drivers/gpu/drm/drm_damage_helper.c 							   plane_state->crtc);
plane_state       133 drivers/gpu/drm/drm_damage_helper.c 			drm_property_blob_put(plane_state->fb_damage_clips);
plane_state       134 drivers/gpu/drm/drm_damage_helper.c 			plane_state->fb_damage_clips = NULL;
plane_state       213 drivers/gpu/drm/drm_damage_helper.c 		struct drm_plane_state *plane_state;
plane_state       224 drivers/gpu/drm/drm_damage_helper.c 		plane_state = drm_atomic_get_plane_state(state, plane);
plane_state       225 drivers/gpu/drm/drm_damage_helper.c 		if (IS_ERR(plane_state)) {
plane_state       226 drivers/gpu/drm/drm_damage_helper.c 			ret = PTR_ERR(plane_state);
plane_state       230 drivers/gpu/drm/drm_damage_helper.c 		drm_property_replace_blob(&plane_state->fb_damage_clips,
plane_state       861 drivers/gpu/drm/drm_framebuffer.c 		struct drm_plane_state *plane_state;
plane_state       866 drivers/gpu/drm/drm_framebuffer.c 		plane_state = drm_atomic_get_plane_state(state, plane);
plane_state       867 drivers/gpu/drm/drm_framebuffer.c 		if (IS_ERR(plane_state)) {
plane_state       868 drivers/gpu/drm/drm_framebuffer.c 			ret = PTR_ERR(plane_state);
plane_state       872 drivers/gpu/drm/drm_framebuffer.c 		if (disable_crtcs && plane_state->crtc->primary == plane) {
plane_state       875 drivers/gpu/drm/drm_framebuffer.c 			crtc_state = drm_atomic_get_existing_crtc_state(state, plane_state->crtc);
plane_state       877 drivers/gpu/drm/drm_framebuffer.c 			ret = drm_atomic_add_affected_connectors(state, plane_state->crtc);
plane_state       887 drivers/gpu/drm/drm_framebuffer.c 		drm_atomic_set_fb_for_plane(plane_state, NULL);
plane_state       888 drivers/gpu/drm/drm_framebuffer.c 		ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
plane_state       320 drivers/gpu/drm/drm_gem_framebuffer_helper.c 					      struct drm_plane_state *plane_state)
plane_state       322 drivers/gpu/drm/drm_gem_framebuffer_helper.c 	return drm_gem_fb_prepare_fb(&pipe->plane, plane_state);
plane_state       333 drivers/gpu/drm/drm_mipi_dbi.c 			   struct drm_plane_state *plane_state)
plane_state       335 drivers/gpu/drm/drm_mipi_dbi.c 	struct drm_framebuffer *fb = plane_state->fb;
plane_state       113 drivers/gpu/drm/drm_plane_helper.c 	struct drm_plane_state plane_state = {
plane_state       135 drivers/gpu/drm/drm_plane_helper.c 	ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state,
plane_state       142 drivers/gpu/drm/drm_plane_helper.c 	*src = plane_state.src;
plane_state       143 drivers/gpu/drm/drm_plane_helper.c 	*dst = plane_state.dst;
plane_state       144 drivers/gpu/drm/drm_plane_helper.c 	*visible = plane_state.visible;
plane_state       128 drivers/gpu/drm/drm_simple_kms_helper.c 					struct drm_plane_state *plane_state)
plane_state       135 drivers/gpu/drm/drm_simple_kms_helper.c 	crtc_state = drm_atomic_get_new_crtc_state(plane_state->state,
plane_state       138 drivers/gpu/drm/drm_simple_kms_helper.c 	ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,
plane_state       145 drivers/gpu/drm/drm_simple_kms_helper.c 	if (!plane_state->visible)
plane_state       151 drivers/gpu/drm/drm_simple_kms_helper.c 	return pipe->funcs->check(pipe, plane_state, crtc_state);
plane_state       230 drivers/gpu/drm/i915/display/intel_atomic.c 				      struct intel_plane_state *plane_state,
plane_state       253 drivers/gpu/drm/i915/display/intel_atomic.c 	if (plane_state && plane_state->base.fb &&
plane_state       254 drivers/gpu/drm/i915/display/intel_atomic.c 	    plane_state->base.fb->format->is_yuv &&
plane_state       255 drivers/gpu/drm/i915/display/intel_atomic.c 	    plane_state->base.fb->format->num_planes > 1) {
plane_state       256 drivers/gpu/drm/i915/display/intel_atomic.c 		struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state       270 drivers/gpu/drm/i915/display/intel_atomic.c 			if (plane_state->linked_plane)
plane_state       271 drivers/gpu/drm/i915/display/intel_atomic.c 				mode |= PS_PLANE_Y_SEL(plane_state->linked_plane->id);
plane_state       317 drivers/gpu/drm/i915/display/intel_atomic.c 	struct intel_plane_state *plane_state = NULL;
plane_state       398 drivers/gpu/drm/i915/display/intel_atomic.c 			plane_state = intel_atomic_get_new_plane_state(intel_state,
plane_state       400 drivers/gpu/drm/i915/display/intel_atomic.c 			scaler_id = &plane_state->scaler_id;
plane_state       405 drivers/gpu/drm/i915/display/intel_atomic.c 					  plane_state, scaler_id);
plane_state        46 drivers/gpu/drm/i915/display/intel_atomic_plane.c 	struct intel_plane_state *plane_state;
plane_state        53 drivers/gpu/drm/i915/display/intel_atomic_plane.c 	plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL);
plane_state        54 drivers/gpu/drm/i915/display/intel_atomic_plane.c 	if (!plane_state) {
plane_state        59 drivers/gpu/drm/i915/display/intel_atomic_plane.c 	__drm_atomic_helper_plane_reset(&plane->base, &plane_state->base);
plane_state        60 drivers/gpu/drm/i915/display/intel_atomic_plane.c 	plane_state->scaler_id = -1;
plane_state       119 drivers/gpu/drm/i915/display/intel_atomic_plane.c 				   const struct intel_plane_state *plane_state)
plane_state       121 drivers/gpu/drm/i915/display/intel_atomic_plane.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state       124 drivers/gpu/drm/i915/display/intel_atomic_plane.c 	if (!plane_state->base.visible)
plane_state       234 drivers/gpu/drm/i915/display/intel_atomic_plane.c 	struct intel_plane_state *plane_state;
plane_state       241 drivers/gpu/drm/i915/display/intel_atomic_plane.c 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
plane_state       271 drivers/gpu/drm/i915/display/intel_atomic_plane.c 			const struct intel_plane_state *plane_state)
plane_state       276 drivers/gpu/drm/i915/display/intel_atomic_plane.c 	plane->update_plane(plane, crtc_state, plane_state);
plane_state       281 drivers/gpu/drm/i915/display/intel_atomic_plane.c 			const struct intel_plane_state *plane_state)
plane_state       286 drivers/gpu/drm/i915/display/intel_atomic_plane.c 	plane->update_slave(plane, crtc_state, plane_state);
plane_state        22 drivers/gpu/drm/i915/display/intel_atomic_plane.h 				   const struct intel_plane_state *plane_state);
plane_state        25 drivers/gpu/drm/i915/display/intel_atomic_plane.h 			const struct intel_plane_state *plane_state);
plane_state        28 drivers/gpu/drm/i915/display/intel_atomic_plane.h 			const struct intel_plane_state *plane_state);
plane_state        47 drivers/gpu/drm/i915/display/intel_atomic_plane.h 				    struct intel_plane_state *plane_state);
plane_state      1092 drivers/gpu/drm/i915/display/intel_color.c 		struct intel_plane_state *plane_state;
plane_state      1097 drivers/gpu/drm/i915/display/intel_color.c 		plane_state = intel_atomic_get_plane_state(state, plane);
plane_state      1098 drivers/gpu/drm/i915/display/intel_color.c 		if (IS_ERR(plane_state))
plane_state      1099 drivers/gpu/drm/i915/display/intel_color.c 			return PTR_ERR(plane_state);
plane_state      2058 drivers/gpu/drm/i915/display/intel_display.c static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
plane_state      2060 drivers/gpu/drm/i915/display/intel_display.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      2065 drivers/gpu/drm/i915/display/intel_display.c 		 plane_state->view.type == I915_GGTT_VIEW_NORMAL);
plane_state      2559 drivers/gpu/drm/i915/display/intel_display.c bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
plane_state      2561 drivers/gpu/drm/i915/display/intel_display.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      2563 drivers/gpu/drm/i915/display/intel_display.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      2599 drivers/gpu/drm/i915/display/intel_display.c static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
plane_state      2601 drivers/gpu/drm/i915/display/intel_display.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      2602 drivers/gpu/drm/i915/display/intel_display.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      2603 drivers/gpu/drm/i915/display/intel_display.c 	unsigned int rotation = plane_state->base.rotation;
plane_state      2610 drivers/gpu/drm/i915/display/intel_display.c 	if (!plane_state->base.visible)
plane_state      2613 drivers/gpu/drm/i915/display/intel_display.c 	if (!intel_plane_can_remap(plane_state))
plane_state      2793 drivers/gpu/drm/i915/display/intel_display.c intel_plane_remap_gtt(struct intel_plane_state *plane_state)
plane_state      2796 drivers/gpu/drm/i915/display/intel_display.c 		to_i915(plane_state->base.plane->dev);
plane_state      2797 drivers/gpu/drm/i915/display/intel_display.c 	struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      2799 drivers/gpu/drm/i915/display/intel_display.c 	struct intel_rotation_info *info = &plane_state->view.rotated;
plane_state      2800 drivers/gpu/drm/i915/display/intel_display.c 	unsigned int rotation = plane_state->base.rotation;
plane_state      2807 drivers/gpu/drm/i915/display/intel_display.c 	memset(&plane_state->view, 0, sizeof(plane_state->view));
plane_state      2808 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->view.type = drm_rotation_90_or_270(rotation) ?
plane_state      2811 drivers/gpu/drm/i915/display/intel_display.c 	src_x = plane_state->base.src.x1 >> 16;
plane_state      2812 drivers/gpu/drm/i915/display/intel_display.c 	src_y = plane_state->base.src.y1 >> 16;
plane_state      2813 drivers/gpu/drm/i915/display/intel_display.c 	src_w = drm_rect_width(&plane_state->base.src) >> 16;
plane_state      2814 drivers/gpu/drm/i915/display/intel_display.c 	src_h = drm_rect_height(&plane_state->base.src) >> 16;
plane_state      2819 drivers/gpu/drm/i915/display/intel_display.c 	drm_rect_translate(&plane_state->base.src,
plane_state      2824 drivers/gpu/drm/i915/display/intel_display.c 		drm_rect_rotate(&plane_state->base.src,
plane_state      2879 drivers/gpu/drm/i915/display/intel_display.c 			plane_state->color_plane[i].stride = pitch_tiles * tile_height;
plane_state      2885 drivers/gpu/drm/i915/display/intel_display.c 			plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
plane_state      2899 drivers/gpu/drm/i915/display/intel_display.c 		plane_state->color_plane[i].offset = 0;
plane_state      2900 drivers/gpu/drm/i915/display/intel_display.c 		plane_state->color_plane[i].x = x;
plane_state      2901 drivers/gpu/drm/i915/display/intel_display.c 		plane_state->color_plane[i].y = y;
plane_state      2906 drivers/gpu/drm/i915/display/intel_display.c intel_plane_compute_gtt(struct intel_plane_state *plane_state)
plane_state      2909 drivers/gpu/drm/i915/display/intel_display.c 		to_intel_framebuffer(plane_state->base.fb);
plane_state      2910 drivers/gpu/drm/i915/display/intel_display.c 	unsigned int rotation = plane_state->base.rotation;
plane_state      2918 drivers/gpu/drm/i915/display/intel_display.c 	if (intel_plane_needs_remap(plane_state)) {
plane_state      2919 drivers/gpu/drm/i915/display/intel_display.c 		intel_plane_remap_gtt(plane_state);
plane_state      2927 drivers/gpu/drm/i915/display/intel_display.c 		return intel_plane_check_stride(plane_state);
plane_state      2930 drivers/gpu/drm/i915/display/intel_display.c 	intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
plane_state      2933 drivers/gpu/drm/i915/display/intel_display.c 		plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
plane_state      2934 drivers/gpu/drm/i915/display/intel_display.c 		plane_state->color_plane[i].offset = 0;
plane_state      2937 drivers/gpu/drm/i915/display/intel_display.c 			plane_state->color_plane[i].x = fb->rotated[i].x;
plane_state      2938 drivers/gpu/drm/i915/display/intel_display.c 			plane_state->color_plane[i].y = fb->rotated[i].y;
plane_state      2940 drivers/gpu/drm/i915/display/intel_display.c 			plane_state->color_plane[i].x = fb->normal[i].x;
plane_state      2941 drivers/gpu/drm/i915/display/intel_display.c 			plane_state->color_plane[i].y = fb->normal[i].y;
plane_state      2947 drivers/gpu/drm/i915/display/intel_display.c 		drm_rect_rotate(&plane_state->base.src,
plane_state      2951 drivers/gpu/drm/i915/display/intel_display.c 	return intel_plane_check_stride(plane_state);
plane_state      3112 drivers/gpu/drm/i915/display/intel_display.c 			struct intel_plane_state *plane_state,
plane_state      3115 drivers/gpu/drm/i915/display/intel_display.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      3117 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->base.visible = visible;
plane_state      3147 drivers/gpu/drm/i915/display/intel_display.c 	struct intel_plane_state *plane_state =
plane_state      3154 drivers/gpu/drm/i915/display/intel_display.c 	intel_set_plane_visible(crtc_state, plane_state, false);
plane_state      3178 drivers/gpu/drm/i915/display/intel_display.c 	struct drm_plane_state *plane_state = primary->state;
plane_state      3181 drivers/gpu/drm/i915/display/intel_display.c 		to_intel_plane_state(plane_state);
plane_state      3254 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->src_x = 0;
plane_state      3255 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->src_y = 0;
plane_state      3256 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->src_w = fb->width << 16;
plane_state      3257 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->src_h = fb->height << 16;
plane_state      3259 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->crtc_x = 0;
plane_state      3260 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->crtc_y = 0;
plane_state      3261 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->crtc_w = fb->width;
plane_state      3262 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->crtc_h = fb->height;
plane_state      3264 drivers/gpu/drm/i915/display/intel_display.c 	intel_state->base.src = drm_plane_state_src(plane_state);
plane_state      3265 drivers/gpu/drm/i915/display/intel_display.c 	intel_state->base.dst = drm_plane_state_dest(plane_state);
plane_state      3270 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->fb = fb;
plane_state      3271 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->crtc = &intel_crtc->base;
plane_state      3350 drivers/gpu/drm/i915/display/intel_display.c static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
plane_state      3353 drivers/gpu/drm/i915/display/intel_display.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      3356 drivers/gpu/drm/i915/display/intel_display.c 	int aux_x = plane_state->color_plane[1].x;
plane_state      3357 drivers/gpu/drm/i915/display/intel_display.c 	int aux_y = plane_state->color_plane[1].y;
plane_state      3358 drivers/gpu/drm/i915/display/intel_display.c 	u32 aux_offset = plane_state->color_plane[1].offset;
plane_state      3372 drivers/gpu/drm/i915/display/intel_display.c 		aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
plane_state      3381 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->color_plane[1].offset = aux_offset;
plane_state      3382 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->color_plane[1].x = aux_x;
plane_state      3383 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->color_plane[1].y = aux_y;
plane_state      3388 drivers/gpu/drm/i915/display/intel_display.c static int skl_check_main_surface(struct intel_plane_state *plane_state)
plane_state      3390 drivers/gpu/drm/i915/display/intel_display.c 	struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
plane_state      3391 drivers/gpu/drm/i915/display/intel_display.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      3392 drivers/gpu/drm/i915/display/intel_display.c 	unsigned int rotation = plane_state->base.rotation;
plane_state      3393 drivers/gpu/drm/i915/display/intel_display.c 	int x = plane_state->base.src.x1 >> 16;
plane_state      3394 drivers/gpu/drm/i915/display/intel_display.c 	int y = plane_state->base.src.y1 >> 16;
plane_state      3395 drivers/gpu/drm/i915/display/intel_display.c 	int w = drm_rect_width(&plane_state->base.src) >> 16;
plane_state      3396 drivers/gpu/drm/i915/display/intel_display.c 	int h = drm_rect_height(&plane_state->base.src) >> 16;
plane_state      3399 drivers/gpu/drm/i915/display/intel_display.c 	u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
plane_state      3414 drivers/gpu/drm/i915/display/intel_display.c 	intel_add_fb_offsets(&x, &y, plane_state, 0);
plane_state      3415 drivers/gpu/drm/i915/display/intel_display.c 	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
plane_state      3424 drivers/gpu/drm/i915/display/intel_display.c 		offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
plane_state      3436 drivers/gpu/drm/i915/display/intel_display.c 		while ((x + w) * cpp > plane_state->color_plane[0].stride) {
plane_state      3442 drivers/gpu/drm/i915/display/intel_display.c 			offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
plane_state      3452 drivers/gpu/drm/i915/display/intel_display.c 		while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) {
plane_state      3456 drivers/gpu/drm/i915/display/intel_display.c 			offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
plane_state      3460 drivers/gpu/drm/i915/display/intel_display.c 		if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
plane_state      3466 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->color_plane[0].offset = offset;
plane_state      3467 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->color_plane[0].x = x;
plane_state      3468 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->color_plane[0].y = y;
plane_state      3474 drivers/gpu/drm/i915/display/intel_display.c 	drm_rect_translate(&plane_state->base.src,
plane_state      3475 drivers/gpu/drm/i915/display/intel_display.c 			   (x << 16) - plane_state->base.src.x1,
plane_state      3476 drivers/gpu/drm/i915/display/intel_display.c 			   (y << 16) - plane_state->base.src.y1);
plane_state      3481 drivers/gpu/drm/i915/display/intel_display.c static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
plane_state      3483 drivers/gpu/drm/i915/display/intel_display.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      3484 drivers/gpu/drm/i915/display/intel_display.c 	unsigned int rotation = plane_state->base.rotation;
plane_state      3487 drivers/gpu/drm/i915/display/intel_display.c 	int x = plane_state->base.src.x1 >> 17;
plane_state      3488 drivers/gpu/drm/i915/display/intel_display.c 	int y = plane_state->base.src.y1 >> 17;
plane_state      3489 drivers/gpu/drm/i915/display/intel_display.c 	int w = drm_rect_width(&plane_state->base.src) >> 17;
plane_state      3490 drivers/gpu/drm/i915/display/intel_display.c 	int h = drm_rect_height(&plane_state->base.src) >> 17;
plane_state      3493 drivers/gpu/drm/i915/display/intel_display.c 	intel_add_fb_offsets(&x, &y, plane_state, 1);
plane_state      3494 drivers/gpu/drm/i915/display/intel_display.c 	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
plane_state      3503 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->color_plane[1].offset = offset;
plane_state      3504 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->color_plane[1].x = x;
plane_state      3505 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->color_plane[1].y = y;
plane_state      3510 drivers/gpu/drm/i915/display/intel_display.c static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
plane_state      3512 drivers/gpu/drm/i915/display/intel_display.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      3513 drivers/gpu/drm/i915/display/intel_display.c 	int src_x = plane_state->base.src.x1 >> 16;
plane_state      3514 drivers/gpu/drm/i915/display/intel_display.c 	int src_y = plane_state->base.src.y1 >> 16;
plane_state      3521 drivers/gpu/drm/i915/display/intel_display.c 	intel_add_fb_offsets(&x, &y, plane_state, 1);
plane_state      3522 drivers/gpu/drm/i915/display/intel_display.c 	offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
plane_state      3524 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->color_plane[1].offset = offset;
plane_state      3525 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->color_plane[1].x = x * hsub + src_x % hsub;
plane_state      3526 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->color_plane[1].y = y * vsub + src_y % vsub;
plane_state      3531 drivers/gpu/drm/i915/display/intel_display.c int skl_check_plane_surface(struct intel_plane_state *plane_state)
plane_state      3533 drivers/gpu/drm/i915/display/intel_display.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      3536 drivers/gpu/drm/i915/display/intel_display.c 	ret = intel_plane_compute_gtt(plane_state);
plane_state      3540 drivers/gpu/drm/i915/display/intel_display.c 	if (!plane_state->base.visible)
plane_state      3548 drivers/gpu/drm/i915/display/intel_display.c 		ret = skl_check_nv12_aux_surface(plane_state);
plane_state      3552 drivers/gpu/drm/i915/display/intel_display.c 		ret = skl_check_ccs_aux_surface(plane_state);
plane_state      3556 drivers/gpu/drm/i915/display/intel_display.c 		plane_state->color_plane[1].offset = ~0xfff;
plane_state      3557 drivers/gpu/drm/i915/display/intel_display.c 		plane_state->color_plane[1].x = 0;
plane_state      3558 drivers/gpu/drm/i915/display/intel_display.c 		plane_state->color_plane[1].y = 0;
plane_state      3561 drivers/gpu/drm/i915/display/intel_display.c 	ret = skl_check_main_surface(plane_state);
plane_state      3614 drivers/gpu/drm/i915/display/intel_display.c 			  const struct intel_plane_state *plane_state)
plane_state      3617 drivers/gpu/drm/i915/display/intel_display.c 		to_i915(plane_state->base.plane->dev);
plane_state      3618 drivers/gpu/drm/i915/display/intel_display.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      3619 drivers/gpu/drm/i915/display/intel_display.c 	unsigned int rotation = plane_state->base.rotation;
plane_state      3668 drivers/gpu/drm/i915/display/intel_display.c int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
plane_state      3671 drivers/gpu/drm/i915/display/intel_display.c 		to_i915(plane_state->base.plane->dev);
plane_state      3676 drivers/gpu/drm/i915/display/intel_display.c 	ret = intel_plane_compute_gtt(plane_state);
plane_state      3680 drivers/gpu/drm/i915/display/intel_display.c 	if (!plane_state->base.visible)
plane_state      3683 drivers/gpu/drm/i915/display/intel_display.c 	src_x = plane_state->base.src.x1 >> 16;
plane_state      3684 drivers/gpu/drm/i915/display/intel_display.c 	src_y = plane_state->base.src.y1 >> 16;
plane_state      3686 drivers/gpu/drm/i915/display/intel_display.c 	intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
plane_state      3690 drivers/gpu/drm/i915/display/intel_display.c 							    plane_state, 0);
plane_state      3698 drivers/gpu/drm/i915/display/intel_display.c 	drm_rect_translate(&plane_state->base.src,
plane_state      3699 drivers/gpu/drm/i915/display/intel_display.c 			   (src_x << 16) - plane_state->base.src.x1,
plane_state      3700 drivers/gpu/drm/i915/display/intel_display.c 			   (src_y << 16) - plane_state->base.src.y1);
plane_state      3704 drivers/gpu/drm/i915/display/intel_display.c 		unsigned int rotation = plane_state->base.rotation;
plane_state      3705 drivers/gpu/drm/i915/display/intel_display.c 		int src_w = drm_rect_width(&plane_state->base.src) >> 16;
plane_state      3706 drivers/gpu/drm/i915/display/intel_display.c 		int src_h = drm_rect_height(&plane_state->base.src) >> 16;
plane_state      3716 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->color_plane[0].offset = offset;
plane_state      3717 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->color_plane[0].x = src_x;
plane_state      3718 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->color_plane[0].y = src_y;
plane_state      3741 drivers/gpu/drm/i915/display/intel_display.c 		 struct intel_plane_state *plane_state)
plane_state      3743 drivers/gpu/drm/i915/display/intel_display.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      3746 drivers/gpu/drm/i915/display/intel_display.c 	ret = chv_plane_check_rotation(plane_state);
plane_state      3750 drivers/gpu/drm/i915/display/intel_display.c 	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
plane_state      3759 drivers/gpu/drm/i915/display/intel_display.c 	ret = i9xx_check_plane_surface(plane_state);
plane_state      3763 drivers/gpu/drm/i915/display/intel_display.c 	if (!plane_state->base.visible)
plane_state      3766 drivers/gpu/drm/i915/display/intel_display.c 	ret = intel_plane_check_src_coordinates(plane_state);
plane_state      3770 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
plane_state      3777 drivers/gpu/drm/i915/display/intel_display.c 			      const struct intel_plane_state *plane_state)
plane_state      3782 drivers/gpu/drm/i915/display/intel_display.c 	int x = plane_state->color_plane[0].x;
plane_state      3783 drivers/gpu/drm/i915/display/intel_display.c 	int y = plane_state->color_plane[0].y;
plane_state      3784 drivers/gpu/drm/i915/display/intel_display.c 	int crtc_x = plane_state->base.dst.x1;
plane_state      3785 drivers/gpu/drm/i915/display/intel_display.c 	int crtc_y = plane_state->base.dst.y1;
plane_state      3786 drivers/gpu/drm/i915/display/intel_display.c 	int crtc_w = drm_rect_width(&plane_state->base.dst);
plane_state      3787 drivers/gpu/drm/i915/display/intel_display.c 	int crtc_h = drm_rect_height(&plane_state->base.dst);
plane_state      3792 drivers/gpu/drm/i915/display/intel_display.c 	dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
plane_state      3794 drivers/gpu/drm/i915/display/intel_display.c 	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
plane_state      3797 drivers/gpu/drm/i915/display/intel_display.c 		dspaddr_offset = plane_state->color_plane[0].offset;
plane_state      3803 drivers/gpu/drm/i915/display/intel_display.c 	I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
plane_state      3836 drivers/gpu/drm/i915/display/intel_display.c 			      intel_plane_ggtt_offset(plane_state) +
plane_state      3840 drivers/gpu/drm/i915/display/intel_display.c 			      intel_plane_ggtt_offset(plane_state) +
plane_state      3954 drivers/gpu/drm/i915/display/intel_display.c u32 skl_plane_stride(const struct intel_plane_state *plane_state,
plane_state      3957 drivers/gpu/drm/i915/display/intel_display.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      3958 drivers/gpu/drm/i915/display/intel_display.c 	unsigned int rotation = plane_state->base.rotation;
plane_state      3959 drivers/gpu/drm/i915/display/intel_display.c 	u32 stride = plane_state->color_plane[color_plane].stride;
plane_state      4025 drivers/gpu/drm/i915/display/intel_display.c static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
plane_state      4027 drivers/gpu/drm/i915/display/intel_display.c 	if (!plane_state->base.fb->format->has_alpha)
plane_state      4030 drivers/gpu/drm/i915/display/intel_display.c 	switch (plane_state->base.pixel_blend_mode) {
plane_state      4038 drivers/gpu/drm/i915/display/intel_display.c 		MISSING_CASE(plane_state->base.pixel_blend_mode);
plane_state      4043 drivers/gpu/drm/i915/display/intel_display.c static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
plane_state      4045 drivers/gpu/drm/i915/display/intel_display.c 	if (!plane_state->base.fb->format->has_alpha)
plane_state      4048 drivers/gpu/drm/i915/display/intel_display.c 	switch (plane_state->base.pixel_blend_mode) {
plane_state      4056 drivers/gpu/drm/i915/display/intel_display.c 		MISSING_CASE(plane_state->base.pixel_blend_mode);
plane_state      4138 drivers/gpu/drm/i915/display/intel_display.c 		  const struct intel_plane_state *plane_state)
plane_state      4141 drivers/gpu/drm/i915/display/intel_display.c 		to_i915(plane_state->base.plane->dev);
plane_state      4142 drivers/gpu/drm/i915/display/intel_display.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      4143 drivers/gpu/drm/i915/display/intel_display.c 	unsigned int rotation = plane_state->base.rotation;
plane_state      4144 drivers/gpu/drm/i915/display/intel_display.c 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
plane_state      4150 drivers/gpu/drm/i915/display/intel_display.c 		plane_ctl |= skl_plane_ctl_alpha(plane_state);
plane_state      4153 drivers/gpu/drm/i915/display/intel_display.c 		if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
plane_state      4156 drivers/gpu/drm/i915/display/intel_display.c 		if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
plane_state      4194 drivers/gpu/drm/i915/display/intel_display.c 			const struct intel_plane_state *plane_state)
plane_state      4197 drivers/gpu/drm/i915/display/intel_display.c 		to_i915(plane_state->base.plane->dev);
plane_state      4198 drivers/gpu/drm/i915/display/intel_display.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      4199 drivers/gpu/drm/i915/display/intel_display.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      4203 drivers/gpu/drm/i915/display/intel_display.c 	plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
plane_state      4206 drivers/gpu/drm/i915/display/intel_display.c 		if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
plane_state      4211 drivers/gpu/drm/i915/display/intel_display.c 		if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
plane_state      5530 drivers/gpu/drm/i915/display/intel_display.c 				   struct intel_plane_state *plane_state)
plane_state      5533 drivers/gpu/drm/i915/display/intel_display.c 		to_intel_plane(plane_state->base.plane);
plane_state      5535 drivers/gpu/drm/i915/display/intel_display.c 	struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      5537 drivers/gpu/drm/i915/display/intel_display.c 	bool force_detach = !fb || !plane_state->base.visible;
plane_state      5547 drivers/gpu/drm/i915/display/intel_display.c 				&plane_state->scaler_id,
plane_state      5548 drivers/gpu/drm/i915/display/intel_display.c 				drm_rect_width(&plane_state->base.src) >> 16,
plane_state      5549 drivers/gpu/drm/i915/display/intel_display.c 				drm_rect_height(&plane_state->base.src) >> 16,
plane_state      5550 drivers/gpu/drm/i915/display/intel_display.c 				drm_rect_width(&plane_state->base.dst),
plane_state      5551 drivers/gpu/drm/i915/display/intel_display.c 				drm_rect_height(&plane_state->base.dst),
plane_state      5554 drivers/gpu/drm/i915/display/intel_display.c 	if (ret || plane_state->scaler_id < 0)
plane_state      5558 drivers/gpu/drm/i915/display/intel_display.c 	if (plane_state->ckey.flags) {
plane_state      7051 drivers/gpu/drm/i915/display/intel_display.c 		const struct intel_plane_state *plane_state =
plane_state      7054 drivers/gpu/drm/i915/display/intel_display.c 		if (plane_state->base.visible)
plane_state      10504 drivers/gpu/drm/i915/display/intel_display.c static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
plane_state      10507 drivers/gpu/drm/i915/display/intel_display.c 		to_i915(plane_state->base.plane->dev);
plane_state      10508 drivers/gpu/drm/i915/display/intel_display.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      10515 drivers/gpu/drm/i915/display/intel_display.c 		base = intel_plane_ggtt_offset(plane_state);
plane_state      10517 drivers/gpu/drm/i915/display/intel_display.c 	base += plane_state->color_plane[0].offset;
plane_state      10521 drivers/gpu/drm/i915/display/intel_display.c 	    plane_state->base.rotation & DRM_MODE_ROTATE_180)
plane_state      10522 drivers/gpu/drm/i915/display/intel_display.c 		base += (plane_state->base.crtc_h *
plane_state      10523 drivers/gpu/drm/i915/display/intel_display.c 			 plane_state->base.crtc_w - 1) * fb->format->cpp[0];
plane_state      10528 drivers/gpu/drm/i915/display/intel_display.c static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
plane_state      10530 drivers/gpu/drm/i915/display/intel_display.c 	int x = plane_state->base.crtc_x;
plane_state      10531 drivers/gpu/drm/i915/display/intel_display.c 	int y = plane_state->base.crtc_y;
plane_state      10549 drivers/gpu/drm/i915/display/intel_display.c static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
plane_state      10552 drivers/gpu/drm/i915/display/intel_display.c 		&plane_state->base.plane->dev->mode_config;
plane_state      10553 drivers/gpu/drm/i915/display/intel_display.c 	int width = plane_state->base.crtc_w;
plane_state      10554 drivers/gpu/drm/i915/display/intel_display.c 	int height = plane_state->base.crtc_h;
plane_state      10560 drivers/gpu/drm/i915/display/intel_display.c static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
plane_state      10566 drivers/gpu/drm/i915/display/intel_display.c 	ret = intel_plane_compute_gtt(plane_state);
plane_state      10570 drivers/gpu/drm/i915/display/intel_display.c 	if (!plane_state->base.visible)
plane_state      10573 drivers/gpu/drm/i915/display/intel_display.c 	src_x = plane_state->base.src_x >> 16;
plane_state      10574 drivers/gpu/drm/i915/display/intel_display.c 	src_y = plane_state->base.src_y >> 16;
plane_state      10576 drivers/gpu/drm/i915/display/intel_display.c 	intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
plane_state      10578 drivers/gpu/drm/i915/display/intel_display.c 						    plane_state, 0);
plane_state      10585 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->color_plane[0].offset = offset;
plane_state      10591 drivers/gpu/drm/i915/display/intel_display.c 			      struct intel_plane_state *plane_state)
plane_state      10593 drivers/gpu/drm/i915/display/intel_display.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      10601 drivers/gpu/drm/i915/display/intel_display.c 	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
plane_state      10609 drivers/gpu/drm/i915/display/intel_display.c 	ret = intel_cursor_check_surface(plane_state);
plane_state      10613 drivers/gpu/drm/i915/display/intel_display.c 	if (!plane_state->base.visible)
plane_state      10616 drivers/gpu/drm/i915/display/intel_display.c 	ret = intel_plane_check_src_coordinates(plane_state);
plane_state      10642 drivers/gpu/drm/i915/display/intel_display.c 			   const struct intel_plane_state *plane_state)
plane_state      10646 drivers/gpu/drm/i915/display/intel_display.c 		CURSOR_STRIDE(plane_state->color_plane[0].stride);
plane_state      10649 drivers/gpu/drm/i915/display/intel_display.c static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
plane_state      10651 drivers/gpu/drm/i915/display/intel_display.c 	int width = plane_state->base.crtc_w;
plane_state      10657 drivers/gpu/drm/i915/display/intel_display.c 	return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
plane_state      10661 drivers/gpu/drm/i915/display/intel_display.c 			     struct intel_plane_state *plane_state)
plane_state      10663 drivers/gpu/drm/i915/display/intel_display.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      10666 drivers/gpu/drm/i915/display/intel_display.c 	ret = intel_check_cursor(crtc_state, plane_state);
plane_state      10675 drivers/gpu/drm/i915/display/intel_display.c 	if (!i845_cursor_size_ok(plane_state)) {
plane_state      10677 drivers/gpu/drm/i915/display/intel_display.c 			  plane_state->base.crtc_w,
plane_state      10678 drivers/gpu/drm/i915/display/intel_display.c 			  plane_state->base.crtc_h);
plane_state      10682 drivers/gpu/drm/i915/display/intel_display.c 	WARN_ON(plane_state->base.visible &&
plane_state      10683 drivers/gpu/drm/i915/display/intel_display.c 		plane_state->color_plane[0].stride != fb->pitches[0]);
plane_state      10697 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
plane_state      10704 drivers/gpu/drm/i915/display/intel_display.c 			       const struct intel_plane_state *plane_state)
plane_state      10710 drivers/gpu/drm/i915/display/intel_display.c 	if (plane_state && plane_state->base.visible) {
plane_state      10711 drivers/gpu/drm/i915/display/intel_display.c 		unsigned int width = plane_state->base.crtc_w;
plane_state      10712 drivers/gpu/drm/i915/display/intel_display.c 		unsigned int height = plane_state->base.crtc_h;
plane_state      10714 drivers/gpu/drm/i915/display/intel_display.c 		cntl = plane_state->ctl |
plane_state      10719 drivers/gpu/drm/i915/display/intel_display.c 		base = intel_cursor_base(plane_state);
plane_state      10720 drivers/gpu/drm/i915/display/intel_display.c 		pos = intel_cursor_position(plane_state);
plane_state      10805 drivers/gpu/drm/i915/display/intel_display.c 			   const struct intel_plane_state *plane_state)
plane_state      10808 drivers/gpu/drm/i915/display/intel_display.c 		to_i915(plane_state->base.plane->dev);
plane_state      10814 drivers/gpu/drm/i915/display/intel_display.c 	switch (plane_state->base.crtc_w) {
plane_state      10825 drivers/gpu/drm/i915/display/intel_display.c 		MISSING_CASE(plane_state->base.crtc_w);
plane_state      10829 drivers/gpu/drm/i915/display/intel_display.c 	if (plane_state->base.rotation & DRM_MODE_ROTATE_180)
plane_state      10835 drivers/gpu/drm/i915/display/intel_display.c static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
plane_state      10838 drivers/gpu/drm/i915/display/intel_display.c 		to_i915(plane_state->base.plane->dev);
plane_state      10839 drivers/gpu/drm/i915/display/intel_display.c 	int width = plane_state->base.crtc_w;
plane_state      10840 drivers/gpu/drm/i915/display/intel_display.c 	int height = plane_state->base.crtc_h;
plane_state      10842 drivers/gpu/drm/i915/display/intel_display.c 	if (!intel_cursor_size_ok(plane_state))
plane_state      10862 drivers/gpu/drm/i915/display/intel_display.c 	    plane_state->base.rotation & DRM_MODE_ROTATE_0) {
plane_state      10874 drivers/gpu/drm/i915/display/intel_display.c 			     struct intel_plane_state *plane_state)
plane_state      10876 drivers/gpu/drm/i915/display/intel_display.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      10878 drivers/gpu/drm/i915/display/intel_display.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      10882 drivers/gpu/drm/i915/display/intel_display.c 	ret = intel_check_cursor(crtc_state, plane_state);
plane_state      10891 drivers/gpu/drm/i915/display/intel_display.c 	if (!i9xx_cursor_size_ok(plane_state)) {
plane_state      10893 drivers/gpu/drm/i915/display/intel_display.c 			  plane_state->base.crtc_w,
plane_state      10894 drivers/gpu/drm/i915/display/intel_display.c 			  plane_state->base.crtc_h);
plane_state      10898 drivers/gpu/drm/i915/display/intel_display.c 	WARN_ON(plane_state->base.visible &&
plane_state      10899 drivers/gpu/drm/i915/display/intel_display.c 		plane_state->color_plane[0].stride != fb->pitches[0]);
plane_state      10901 drivers/gpu/drm/i915/display/intel_display.c 	if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
plane_state      10903 drivers/gpu/drm/i915/display/intel_display.c 			      fb->pitches[0], plane_state->base.crtc_w);
plane_state      10918 drivers/gpu/drm/i915/display/intel_display.c 	    plane_state->base.visible && plane_state->base.crtc_x < 0) {
plane_state      10923 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
plane_state      10930 drivers/gpu/drm/i915/display/intel_display.c 			       const struct intel_plane_state *plane_state)
plane_state      10937 drivers/gpu/drm/i915/display/intel_display.c 	if (plane_state && plane_state->base.visible) {
plane_state      10938 drivers/gpu/drm/i915/display/intel_display.c 		cntl = plane_state->ctl |
plane_state      10941 drivers/gpu/drm/i915/display/intel_display.c 		if (plane_state->base.crtc_h != plane_state->base.crtc_w)
plane_state      10942 drivers/gpu/drm/i915/display/intel_display.c 			fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1);
plane_state      10944 drivers/gpu/drm/i915/display/intel_display.c 		base = intel_cursor_base(plane_state);
plane_state      10945 drivers/gpu/drm/i915/display/intel_display.c 		pos = intel_cursor_position(plane_state);
plane_state      11065 drivers/gpu/drm/i915/display/intel_display.c 	struct drm_plane_state *plane_state;
plane_state      11072 drivers/gpu/drm/i915/display/intel_display.c 	for_each_new_plane_in_state(state, plane, plane_state, i) {
plane_state      11073 drivers/gpu/drm/i915/display/intel_display.c 		if (plane_state->crtc != crtc)
plane_state      11076 drivers/gpu/drm/i915/display/intel_display.c 		ret = drm_atomic_set_crtc_for_plane(plane_state, NULL);
plane_state      11080 drivers/gpu/drm/i915/display/intel_display.c 		drm_atomic_set_fb_for_plane(plane_state, NULL);
plane_state      11504 drivers/gpu/drm/i915/display/intel_display.c 				    struct intel_plane_state *plane_state)
plane_state      11507 drivers/gpu/drm/i915/display/intel_display.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      11513 drivers/gpu/drm/i915/display/intel_display.c 	struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      11517 drivers/gpu/drm/i915/display/intel_display.c 		ret = skl_update_scaler_plane(crtc_state, plane_state);
plane_state      11523 drivers/gpu/drm/i915/display/intel_display.c 	visible = plane_state->base.visible;
plane_state      11539 drivers/gpu/drm/i915/display/intel_display.c 		plane_state->base.visible = visible = false;
plane_state      11577 drivers/gpu/drm/i915/display/intel_display.c 	} else if (intel_wm_need_update(old_plane_state, plane_state)) {
plane_state      11625 drivers/gpu/drm/i915/display/intel_display.c 			 needs_scaling(plane_state))))
plane_state      11664 drivers/gpu/drm/i915/display/intel_display.c 	struct intel_plane_state *plane_state, *linked_plane_state;
plane_state      11667 drivers/gpu/drm/i915/display/intel_display.c 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
plane_state      11668 drivers/gpu/drm/i915/display/intel_display.c 		linked = plane_state->linked_plane;
plane_state      11678 drivers/gpu/drm/i915/display/intel_display.c 		WARN_ON(linked_plane_state->slave == plane_state->slave);
plane_state      11690 drivers/gpu/drm/i915/display/intel_display.c 	struct intel_plane_state *plane_state;
plane_state      11700 drivers/gpu/drm/i915/display/intel_display.c 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
plane_state      11701 drivers/gpu/drm/i915/display/intel_display.c 		if (plane->pipe != crtc->pipe || !plane_state->linked_plane)
plane_state      11704 drivers/gpu/drm/i915/display/intel_display.c 		plane_state->linked_plane = NULL;
plane_state      11705 drivers/gpu/drm/i915/display/intel_display.c 		if (plane_state->slave && !plane_state->base.visible) {
plane_state      11710 drivers/gpu/drm/i915/display/intel_display.c 		plane_state->slave = false;
plane_state      11716 drivers/gpu/drm/i915/display/intel_display.c 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
plane_state      11744 drivers/gpu/drm/i915/display/intel_display.c 		plane_state->linked_plane = linked;
plane_state      12044 drivers/gpu/drm/i915/display/intel_display.c static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
plane_state      12046 drivers/gpu/drm/i915/display/intel_display.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      12047 drivers/gpu/drm/i915/display/intel_display.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      12053 drivers/gpu/drm/i915/display/intel_display.c 			      yesno(plane_state->base.visible));
plane_state      12061 drivers/gpu/drm/i915/display/intel_display.c 		      yesno(plane_state->base.visible));
plane_state      12063 drivers/gpu/drm/i915/display/intel_display.c 		      plane_state->base.rotation, plane_state->scaler_id);
plane_state      12064 drivers/gpu/drm/i915/display/intel_display.c 	if (plane_state->base.visible)
plane_state      12066 drivers/gpu/drm/i915/display/intel_display.c 			      DRM_RECT_FP_ARG(&plane_state->base.src),
plane_state      12067 drivers/gpu/drm/i915/display/intel_display.c 			      DRM_RECT_ARG(&plane_state->base.dst));
plane_state      12076 drivers/gpu/drm/i915/display/intel_display.c 	const struct intel_plane_state *plane_state;
plane_state      12166 drivers/gpu/drm/i915/display/intel_display.c 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
plane_state      12168 drivers/gpu/drm/i915/display/intel_display.c 			intel_dump_plane_state(plane_state);
plane_state      13158 drivers/gpu/drm/i915/display/intel_display.c 	const struct intel_plane_state *plane_state;
plane_state      13162 drivers/gpu/drm/i915/display/intel_display.c 					  plane_state, i)
plane_state      13163 drivers/gpu/drm/i915/display/intel_display.c 		assert_plane(plane, plane_state->slave ||
plane_state      13164 drivers/gpu/drm/i915/display/intel_display.c 			     plane_state->base.visible);
plane_state      14302 drivers/gpu/drm/i915/display/intel_display.c static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
plane_state      14304 drivers/gpu/drm/i915/display/intel_display.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      14306 drivers/gpu/drm/i915/display/intel_display.c 	struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      14321 drivers/gpu/drm/i915/display/intel_display.c 					 &plane_state->view,
plane_state      14322 drivers/gpu/drm/i915/display/intel_display.c 					 intel_plane_uses_fence(plane_state),
plane_state      14323 drivers/gpu/drm/i915/display/intel_display.c 					 &plane_state->flags);
plane_state      14327 drivers/gpu/drm/i915/display/intel_display.c 	plane_state->vma = vma;
plane_state      16455 drivers/gpu/drm/i915/display/intel_display.c 			const struct intel_plane_state *plane_state =
plane_state      16458 drivers/gpu/drm/i915/display/intel_display.c 			if (plane_state->base.visible &&
plane_state      16634 drivers/gpu/drm/i915/display/intel_display.c 		struct intel_plane_state *plane_state =
plane_state      16645 drivers/gpu/drm/i915/display/intel_display.c 		intel_set_plane_visible(crtc_state, plane_state, visible);
plane_state      16820 drivers/gpu/drm/i915/display/intel_display.c 			const struct intel_plane_state *plane_state =
plane_state      16827 drivers/gpu/drm/i915/display/intel_display.c 			if (plane_state->base.visible)
plane_state       422 drivers/gpu/drm/i915/display/intel_display.h bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
plane_state       526 drivers/gpu/drm/i915/display/intel_display.h 			const struct intel_plane_state *plane_state);
plane_state       529 drivers/gpu/drm/i915/display/intel_display.h 		  const struct intel_plane_state *plane_state);
plane_state       531 drivers/gpu/drm/i915/display/intel_display.h u32 skl_plane_stride(const struct intel_plane_state *plane_state,
plane_state       533 drivers/gpu/drm/i915/display/intel_display.h int skl_check_plane_surface(struct intel_plane_state *plane_state);
plane_state       534 drivers/gpu/drm/i915/display/intel_display.h int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
plane_state      1056 drivers/gpu/drm/i915/display/intel_display_types.h 			     const struct intel_plane_state *plane_state);
plane_state      1059 drivers/gpu/drm/i915/display/intel_display_types.h 			     const struct intel_plane_state *plane_state);
plane_state      1064 drivers/gpu/drm/i915/display/intel_display_types.h 			   struct intel_plane_state *plane_state);
plane_state       423 drivers/gpu/drm/i915/display/intel_fbc.c 			      struct intel_plane_state *plane_state)
plane_state       433 drivers/gpu/drm/i915/display/intel_fbc.c 	if (plane_state->base.visible)
plane_state       659 drivers/gpu/drm/i915/display/intel_fbc.c 					 struct intel_plane_state *plane_state)
plane_state       664 drivers/gpu/drm/i915/display/intel_fbc.c 	struct drm_framebuffer *fb = plane_state->base.fb;
plane_state       673 drivers/gpu/drm/i915/display/intel_fbc.c 	cache->plane.rotation = plane_state->base.rotation;
plane_state       679 drivers/gpu/drm/i915/display/intel_fbc.c 	cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
plane_state       680 drivers/gpu/drm/i915/display/intel_fbc.c 	cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
plane_state       681 drivers/gpu/drm/i915/display/intel_fbc.c 	cache->plane.visible = plane_state->base.visible;
plane_state       682 drivers/gpu/drm/i915/display/intel_fbc.c 	cache->plane.adjusted_x = plane_state->color_plane[0].x;
plane_state       683 drivers/gpu/drm/i915/display/intel_fbc.c 	cache->plane.adjusted_y = plane_state->color_plane[0].y;
plane_state       684 drivers/gpu/drm/i915/display/intel_fbc.c 	cache->plane.y = plane_state->base.src.y1 >> 16;
plane_state       686 drivers/gpu/drm/i915/display/intel_fbc.c 	cache->plane.pixel_blend_mode = plane_state->base.pixel_blend_mode;
plane_state       694 drivers/gpu/drm/i915/display/intel_fbc.c 	cache->vma = plane_state->vma;
plane_state       695 drivers/gpu/drm/i915/display/intel_fbc.c 	cache->flags = plane_state->flags;
plane_state       858 drivers/gpu/drm/i915/display/intel_fbc.c 			  struct intel_plane_state *plane_state)
plane_state       869 drivers/gpu/drm/i915/display/intel_fbc.c 	if (!multiple_pipes_ok(crtc, plane_state)) {
plane_state       877 drivers/gpu/drm/i915/display/intel_fbc.c 	intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
plane_state      1029 drivers/gpu/drm/i915/display/intel_fbc.c 	struct intel_plane_state *plane_state;
plane_state      1047 drivers/gpu/drm/i915/display/intel_fbc.c 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
plane_state      1049 drivers/gpu/drm/i915/display/intel_fbc.c 		struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
plane_state      1054 drivers/gpu/drm/i915/display/intel_fbc.c 		if (!plane_state->base.visible)
plane_state      1084 drivers/gpu/drm/i915/display/intel_fbc.c 		      struct intel_plane_state *plane_state)
plane_state      1109 drivers/gpu/drm/i915/display/intel_fbc.c 	intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
plane_state        24 drivers/gpu/drm/i915/display/intel_fbc.h 			  struct intel_plane_state *plane_state);
plane_state        30 drivers/gpu/drm/i915/display/intel_fbc.h 		      struct intel_plane_state *plane_state);
plane_state       253 drivers/gpu/drm/i915/display/intel_sprite.c int intel_plane_check_stride(const struct intel_plane_state *plane_state)
plane_state       255 drivers/gpu/drm/i915/display/intel_sprite.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state       256 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state       257 drivers/gpu/drm/i915/display/intel_sprite.c 	unsigned int rotation = plane_state->base.rotation;
plane_state       266 drivers/gpu/drm/i915/display/intel_sprite.c 	if (intel_plane_can_remap(plane_state) &&
plane_state       267 drivers/gpu/drm/i915/display/intel_sprite.c 	    !plane_state->base.visible)
plane_state       271 drivers/gpu/drm/i915/display/intel_sprite.c 	stride = plane_state->color_plane[0].stride;
plane_state       285 drivers/gpu/drm/i915/display/intel_sprite.c int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
plane_state       287 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state       288 drivers/gpu/drm/i915/display/intel_sprite.c 	struct drm_rect *src = &plane_state->base.src;
plane_state       290 drivers/gpu/drm/i915/display/intel_sprite.c 	bool rotated = drm_rotation_90_or_270(plane_state->base.rotation);
plane_state       361 drivers/gpu/drm/i915/display/intel_sprite.c 		   const struct intel_plane_state *plane_state)
plane_state       365 drivers/gpu/drm/i915/display/intel_sprite.c 	int scaler_id = plane_state->scaler_id;
plane_state       368 drivers/gpu/drm/i915/display/intel_sprite.c 	int crtc_x = plane_state->base.dst.x1;
plane_state       369 drivers/gpu/drm/i915/display/intel_sprite.c 	int crtc_y = plane_state->base.dst.y1;
plane_state       370 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 crtc_w = drm_rect_width(&plane_state->base.dst);
plane_state       371 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 crtc_h = drm_rect_height(&plane_state->base.dst);
plane_state       376 drivers/gpu/drm/i915/display/intel_sprite.c 	hscale = drm_rect_calc_hscale(&plane_state->base.src,
plane_state       377 drivers/gpu/drm/i915/display/intel_sprite.c 				      &plane_state->base.dst,
plane_state       379 drivers/gpu/drm/i915/display/intel_sprite.c 	vscale = drm_rect_calc_vscale(&plane_state->base.src,
plane_state       380 drivers/gpu/drm/i915/display/intel_sprite.c 				      &plane_state->base.dst,
plane_state       384 drivers/gpu/drm/i915/display/intel_sprite.c 	if (is_planar_yuv_format(plane_state->base.fb->format->format) &&
plane_state       423 drivers/gpu/drm/i915/display/intel_sprite.c 		      const struct intel_plane_state *plane_state)
plane_state       509 drivers/gpu/drm/i915/display/intel_sprite.c 	if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
plane_state       510 drivers/gpu/drm/i915/display/intel_sprite.c 		csc = input_csc_matrix[plane_state->base.color_encoding];
plane_state       512 drivers/gpu/drm/i915/display/intel_sprite.c 		csc = input_csc_matrix_lr[plane_state->base.color_encoding];
plane_state       526 drivers/gpu/drm/i915/display/intel_sprite.c 	if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
plane_state       541 drivers/gpu/drm/i915/display/intel_sprite.c 		  const struct intel_plane_state *plane_state,
plane_state       547 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
plane_state       548 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 surf_addr = plane_state->color_plane[color_plane].offset;
plane_state       549 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 stride = skl_plane_stride(plane_state, color_plane);
plane_state       550 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 aux_stride = skl_plane_stride(plane_state, 1);
plane_state       551 drivers/gpu/drm/i915/display/intel_sprite.c 	int crtc_x = plane_state->base.dst.x1;
plane_state       552 drivers/gpu/drm/i915/display/intel_sprite.c 	int crtc_y = plane_state->base.dst.y1;
plane_state       553 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 x = plane_state->color_plane[color_plane].x;
plane_state       554 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 y = plane_state->color_plane[color_plane].y;
plane_state       555 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
plane_state       556 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
plane_state       557 drivers/gpu/drm/i915/display/intel_sprite.c 	struct intel_plane *linked = plane_state->linked_plane;
plane_state       558 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state       559 drivers/gpu/drm/i915/display/intel_sprite.c 	u8 alpha = plane_state->base.alpha >> 8;
plane_state       567 drivers/gpu/drm/i915/display/intel_sprite.c 		plane_color_ctl = plane_state->color_ctl |
plane_state       581 drivers/gpu/drm/i915/display/intel_sprite.c 	if (plane_state->scaler_id >= 0) {
plane_state       592 drivers/gpu/drm/i915/display/intel_sprite.c 		      (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
plane_state       619 drivers/gpu/drm/i915/display/intel_sprite.c 		icl_program_input_csc(plane, crtc_state, plane_state);
plane_state       631 drivers/gpu/drm/i915/display/intel_sprite.c 			      (plane_state->color_plane[1].y << 16) |
plane_state       632 drivers/gpu/drm/i915/display/intel_sprite.c 			      plane_state->color_plane[1].x);
plane_state       641 drivers/gpu/drm/i915/display/intel_sprite.c 		      intel_plane_ggtt_offset(plane_state) + surf_addr);
plane_state       643 drivers/gpu/drm/i915/display/intel_sprite.c 	if (!slave && plane_state->scaler_id >= 0)
plane_state       644 drivers/gpu/drm/i915/display/intel_sprite.c 		skl_program_scaler(plane, crtc_state, plane_state);
plane_state       652 drivers/gpu/drm/i915/display/intel_sprite.c 		 const struct intel_plane_state *plane_state)
plane_state       656 drivers/gpu/drm/i915/display/intel_sprite.c 	if (plane_state->linked_plane) {
plane_state       661 drivers/gpu/drm/i915/display/intel_sprite.c 	skl_program_plane(plane, crtc_state, plane_state,
plane_state       662 drivers/gpu/drm/i915/display/intel_sprite.c 			  color_plane, false, plane_state->ctl);
plane_state       668 drivers/gpu/drm/i915/display/intel_sprite.c 		 const struct intel_plane_state *plane_state)
plane_state       670 drivers/gpu/drm/i915/display/intel_sprite.c 	skl_program_plane(plane, crtc_state, plane_state, 0, true,
plane_state       671 drivers/gpu/drm/i915/display/intel_sprite.c 			  plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE);
plane_state       731 drivers/gpu/drm/i915/display/intel_sprite.c chv_update_csc(const struct intel_plane_state *plane_state)
plane_state       733 drivers/gpu/drm/i915/display/intel_sprite.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state       735 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state       761 drivers/gpu/drm/i915/display/intel_sprite.c 	const s16 *csc = csc_matrix[plane_state->base.color_encoding];
plane_state       790 drivers/gpu/drm/i915/display/intel_sprite.c vlv_update_clrc(const struct intel_plane_state *plane_state)
plane_state       792 drivers/gpu/drm/i915/display/intel_sprite.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state       794 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state       800 drivers/gpu/drm/i915/display/intel_sprite.c 	    plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
plane_state       839 drivers/gpu/drm/i915/display/intel_sprite.c 			  const struct intel_plane_state *plane_state)
plane_state       841 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state       842 drivers/gpu/drm/i915/display/intel_sprite.c 	unsigned int rotation = plane_state->base.rotation;
plane_state       843 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
plane_state       887 drivers/gpu/drm/i915/display/intel_sprite.c 	if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
plane_state       905 drivers/gpu/drm/i915/display/intel_sprite.c static void vlv_update_gamma(const struct intel_plane_state *plane_state)
plane_state       907 drivers/gpu/drm/i915/display/intel_sprite.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state       909 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state       933 drivers/gpu/drm/i915/display/intel_sprite.c 		 const struct intel_plane_state *plane_state)
plane_state       938 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 sprsurf_offset = plane_state->color_plane[0].offset;
plane_state       940 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
plane_state       941 drivers/gpu/drm/i915/display/intel_sprite.c 	int crtc_x = plane_state->base.dst.x1;
plane_state       942 drivers/gpu/drm/i915/display/intel_sprite.c 	int crtc_y = plane_state->base.dst.y1;
plane_state       943 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 crtc_w = drm_rect_width(&plane_state->base.dst);
plane_state       944 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 crtc_h = drm_rect_height(&plane_state->base.dst);
plane_state       945 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 x = plane_state->color_plane[0].x;
plane_state       946 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 y = plane_state->color_plane[0].y;
plane_state       950 drivers/gpu/drm/i915/display/intel_sprite.c 	sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
plane_state       956 drivers/gpu/drm/i915/display/intel_sprite.c 	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
plane_state       961 drivers/gpu/drm/i915/display/intel_sprite.c 		      plane_state->color_plane[0].stride);
plane_state       967 drivers/gpu/drm/i915/display/intel_sprite.c 		chv_update_csc(plane_state);
plane_state       985 drivers/gpu/drm/i915/display/intel_sprite.c 		      intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
plane_state       987 drivers/gpu/drm/i915/display/intel_sprite.c 	vlv_update_clrc(plane_state);
plane_state       988 drivers/gpu/drm/i915/display/intel_sprite.c 	vlv_update_gamma(plane_state);
plane_state      1048 drivers/gpu/drm/i915/display/intel_sprite.c 			  const struct intel_plane_state *plane_state)
plane_state      1051 drivers/gpu/drm/i915/display/intel_sprite.c 		to_i915(plane_state->base.plane->dev);
plane_state      1052 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      1053 drivers/gpu/drm/i915/display/intel_sprite.c 	unsigned int rotation = plane_state->base.rotation;
plane_state      1054 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
plane_state      1088 drivers/gpu/drm/i915/display/intel_sprite.c 	if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
plane_state      1091 drivers/gpu/drm/i915/display/intel_sprite.c 	if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
plane_state      1119 drivers/gpu/drm/i915/display/intel_sprite.c static void ivb_update_gamma(const struct intel_plane_state *plane_state)
plane_state      1121 drivers/gpu/drm/i915/display/intel_sprite.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      1150 drivers/gpu/drm/i915/display/intel_sprite.c 		 const struct intel_plane_state *plane_state)
plane_state      1154 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 sprsurf_offset = plane_state->color_plane[0].offset;
plane_state      1156 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
plane_state      1157 drivers/gpu/drm/i915/display/intel_sprite.c 	int crtc_x = plane_state->base.dst.x1;
plane_state      1158 drivers/gpu/drm/i915/display/intel_sprite.c 	int crtc_y = plane_state->base.dst.y1;
plane_state      1159 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 crtc_w = drm_rect_width(&plane_state->base.dst);
plane_state      1160 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 crtc_h = drm_rect_height(&plane_state->base.dst);
plane_state      1161 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 x = plane_state->color_plane[0].x;
plane_state      1162 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 y = plane_state->color_plane[0].y;
plane_state      1163 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
plane_state      1164 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
plane_state      1168 drivers/gpu/drm/i915/display/intel_sprite.c 	sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);
plane_state      1179 drivers/gpu/drm/i915/display/intel_sprite.c 	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
plane_state      1183 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride);
plane_state      1211 drivers/gpu/drm/i915/display/intel_sprite.c 		      intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
plane_state      1213 drivers/gpu/drm/i915/display/intel_sprite.c 	ivb_update_gamma(plane_state);
plane_state      1282 drivers/gpu/drm/i915/display/intel_sprite.c 			  const struct intel_plane_state *plane_state)
plane_state      1285 drivers/gpu/drm/i915/display/intel_sprite.c 		to_i915(plane_state->base.plane->dev);
plane_state      1286 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      1287 drivers/gpu/drm/i915/display/intel_sprite.c 	unsigned int rotation = plane_state->base.rotation;
plane_state      1288 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
plane_state      1320 drivers/gpu/drm/i915/display/intel_sprite.c 	if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
plane_state      1323 drivers/gpu/drm/i915/display/intel_sprite.c 	if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
plane_state      1340 drivers/gpu/drm/i915/display/intel_sprite.c static void g4x_update_gamma(const struct intel_plane_state *plane_state)
plane_state      1342 drivers/gpu/drm/i915/display/intel_sprite.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      1344 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      1372 drivers/gpu/drm/i915/display/intel_sprite.c static void ilk_update_gamma(const struct intel_plane_state *plane_state)
plane_state      1374 drivers/gpu/drm/i915/display/intel_sprite.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      1376 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      1403 drivers/gpu/drm/i915/display/intel_sprite.c 		 const struct intel_plane_state *plane_state)
plane_state      1407 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 dvssurf_offset = plane_state->color_plane[0].offset;
plane_state      1409 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
plane_state      1410 drivers/gpu/drm/i915/display/intel_sprite.c 	int crtc_x = plane_state->base.dst.x1;
plane_state      1411 drivers/gpu/drm/i915/display/intel_sprite.c 	int crtc_y = plane_state->base.dst.y1;
plane_state      1412 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 crtc_w = drm_rect_width(&plane_state->base.dst);
plane_state      1413 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 crtc_h = drm_rect_height(&plane_state->base.dst);
plane_state      1414 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 x = plane_state->color_plane[0].x;
plane_state      1415 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 y = plane_state->color_plane[0].y;
plane_state      1416 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 src_w = drm_rect_width(&plane_state->base.src) >> 16;
plane_state      1417 drivers/gpu/drm/i915/display/intel_sprite.c 	u32 src_h = drm_rect_height(&plane_state->base.src) >> 16;
plane_state      1421 drivers/gpu/drm/i915/display/intel_sprite.c 	dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);
plane_state      1432 drivers/gpu/drm/i915/display/intel_sprite.c 	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
plane_state      1436 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride);
plane_state      1457 drivers/gpu/drm/i915/display/intel_sprite.c 		      intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
plane_state      1460 drivers/gpu/drm/i915/display/intel_sprite.c 		g4x_update_gamma(plane_state);
plane_state      1462 drivers/gpu/drm/i915/display/intel_sprite.c 		ilk_update_gamma(plane_state);
plane_state      1523 drivers/gpu/drm/i915/display/intel_sprite.c 			 struct intel_plane_state *plane_state)
plane_state      1525 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      1526 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_rect *src = &plane_state->base.src;
plane_state      1527 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_rect *dst = &plane_state->base.dst;
plane_state      1531 drivers/gpu/drm/i915/display/intel_sprite.c 	unsigned int stride = plane_state->color_plane[0].stride;
plane_state      1584 drivers/gpu/drm/i915/display/intel_sprite.c 		 struct intel_plane_state *plane_state)
plane_state      1586 drivers/gpu/drm/i915/display/intel_sprite.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      1592 drivers/gpu/drm/i915/display/intel_sprite.c 	if (intel_fb_scalable(plane_state->base.fb)) {
plane_state      1602 drivers/gpu/drm/i915/display/intel_sprite.c 	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
plane_state      1609 drivers/gpu/drm/i915/display/intel_sprite.c 	ret = i9xx_check_plane_surface(plane_state);
plane_state      1613 drivers/gpu/drm/i915/display/intel_sprite.c 	if (!plane_state->base.visible)
plane_state      1616 drivers/gpu/drm/i915/display/intel_sprite.c 	ret = intel_plane_check_src_coordinates(plane_state);
plane_state      1620 drivers/gpu/drm/i915/display/intel_sprite.c 	ret = g4x_sprite_check_scaling(crtc_state, plane_state);
plane_state      1625 drivers/gpu/drm/i915/display/intel_sprite.c 		plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
plane_state      1627 drivers/gpu/drm/i915/display/intel_sprite.c 		plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state);
plane_state      1632 drivers/gpu/drm/i915/display/intel_sprite.c int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
plane_state      1634 drivers/gpu/drm/i915/display/intel_sprite.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      1636 drivers/gpu/drm/i915/display/intel_sprite.c 	unsigned int rotation = plane_state->base.rotation;
plane_state      1651 drivers/gpu/drm/i915/display/intel_sprite.c 		 struct intel_plane_state *plane_state)
plane_state      1655 drivers/gpu/drm/i915/display/intel_sprite.c 	ret = chv_plane_check_rotation(plane_state);
plane_state      1659 drivers/gpu/drm/i915/display/intel_sprite.c 	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
plane_state      1667 drivers/gpu/drm/i915/display/intel_sprite.c 	ret = i9xx_check_plane_surface(plane_state);
plane_state      1671 drivers/gpu/drm/i915/display/intel_sprite.c 	if (!plane_state->base.visible)
plane_state      1674 drivers/gpu/drm/i915/display/intel_sprite.c 	ret = intel_plane_check_src_coordinates(plane_state);
plane_state      1678 drivers/gpu/drm/i915/display/intel_sprite.c 	plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
plane_state      1684 drivers/gpu/drm/i915/display/intel_sprite.c 			      const struct intel_plane_state *plane_state)
plane_state      1686 drivers/gpu/drm/i915/display/intel_sprite.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      1688 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      1689 drivers/gpu/drm/i915/display/intel_sprite.c 	unsigned int rotation = plane_state->base.rotation;
plane_state      1758 drivers/gpu/drm/i915/display/intel_sprite.c 					   const struct intel_plane_state *plane_state)
plane_state      1761 drivers/gpu/drm/i915/display/intel_sprite.c 		to_i915(plane_state->base.plane->dev);
plane_state      1762 drivers/gpu/drm/i915/display/intel_sprite.c 	int crtc_x = plane_state->base.dst.x1;
plane_state      1763 drivers/gpu/drm/i915/display/intel_sprite.c 	int crtc_w = drm_rect_width(&plane_state->base.dst);
plane_state      1787 drivers/gpu/drm/i915/display/intel_sprite.c static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state)
plane_state      1789 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      1790 drivers/gpu/drm/i915/display/intel_sprite.c 	unsigned int rotation = plane_state->base.rotation;
plane_state      1791 drivers/gpu/drm/i915/display/intel_sprite.c 	int src_w = drm_rect_width(&plane_state->base.src) >> 16;
plane_state      1805 drivers/gpu/drm/i915/display/intel_sprite.c 			   struct intel_plane_state *plane_state)
plane_state      1807 drivers/gpu/drm/i915/display/intel_sprite.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      1809 drivers/gpu/drm/i915/display/intel_sprite.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      1814 drivers/gpu/drm/i915/display/intel_sprite.c 	ret = skl_plane_check_fb(crtc_state, plane_state);
plane_state      1819 drivers/gpu/drm/i915/display/intel_sprite.c 	if (!plane_state->ckey.flags && intel_fb_scalable(fb)) {
plane_state      1824 drivers/gpu/drm/i915/display/intel_sprite.c 	ret = drm_atomic_helper_check_plane_state(&plane_state->base,
plane_state      1831 drivers/gpu/drm/i915/display/intel_sprite.c 	ret = skl_check_plane_surface(plane_state);
plane_state      1835 drivers/gpu/drm/i915/display/intel_sprite.c 	if (!plane_state->base.visible)
plane_state      1838 drivers/gpu/drm/i915/display/intel_sprite.c 	ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
plane_state      1842 drivers/gpu/drm/i915/display/intel_sprite.c 	ret = intel_plane_check_src_coordinates(plane_state);
plane_state      1846 drivers/gpu/drm/i915/display/intel_sprite.c 	ret = skl_plane_check_nv12_rotation(plane_state);
plane_state      1851 drivers/gpu/drm/i915/display/intel_sprite.c 	if (!(plane_state->base.alpha >> 8))
plane_state      1852 drivers/gpu/drm/i915/display/intel_sprite.c 		plane_state->base.visible = false;
plane_state      1854 drivers/gpu/drm/i915/display/intel_sprite.c 	plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
plane_state      1857 drivers/gpu/drm/i915/display/intel_sprite.c 		plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
plane_state      1858 drivers/gpu/drm/i915/display/intel_sprite.c 							     plane_state);
plane_state      1868 drivers/gpu/drm/i915/display/intel_sprite.c static void intel_plane_set_ckey(struct intel_plane_state *plane_state,
plane_state      1871 drivers/gpu/drm/i915/display/intel_sprite.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      1873 drivers/gpu/drm/i915/display/intel_sprite.c 	struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
plane_state      1900 drivers/gpu/drm/i915/display/intel_sprite.c 	struct drm_plane_state *plane_state;
plane_state      1943 drivers/gpu/drm/i915/display/intel_sprite.c 		plane_state = drm_atomic_get_plane_state(state, plane);
plane_state      1944 drivers/gpu/drm/i915/display/intel_sprite.c 		ret = PTR_ERR_OR_ZERO(plane_state);
plane_state      1946 drivers/gpu/drm/i915/display/intel_sprite.c 			intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
plane_state      1957 drivers/gpu/drm/i915/display/intel_sprite.c 			plane_state = drm_atomic_get_plane_state(state,
plane_state      1959 drivers/gpu/drm/i915/display/intel_sprite.c 			ret = PTR_ERR_OR_ZERO(plane_state);
plane_state      1961 drivers/gpu/drm/i915/display/intel_sprite.c 				intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
plane_state        29 drivers/gpu/drm/i915/display/intel_sprite.h int intel_plane_check_stride(const struct intel_plane_state *plane_state);
plane_state        30 drivers/gpu/drm/i915/display/intel_sprite.h int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
plane_state        31 drivers/gpu/drm/i915/display/intel_sprite.h int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
plane_state      2466 drivers/gpu/drm/i915/i915_debugfs.c 	struct drm_plane_state *plane_state = crtc->primary->state;
plane_state      2467 drivers/gpu/drm/i915/i915_debugfs.c 	struct drm_framebuffer *fb = plane_state->fb;
plane_state      2471 drivers/gpu/drm/i915/i915_debugfs.c 			   fb->base.id, plane_state->src_x >> 16,
plane_state      2472 drivers/gpu/drm/i915/i915_debugfs.c 			   plane_state->src_y >> 16, fb->width, fb->height);
plane_state       824 drivers/gpu/drm/i915/intel_pm.c 				   const struct intel_plane_state *plane_state)
plane_state       826 drivers/gpu/drm/i915/intel_pm.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state       841 drivers/gpu/drm/i915/intel_pm.c 		return plane_state->base.fb != NULL;
plane_state       843 drivers/gpu/drm/i915/intel_pm.c 		return plane_state->base.visible;
plane_state      1112 drivers/gpu/drm/i915/intel_pm.c 			  const struct intel_plane_state *plane_state,
plane_state      1115 drivers/gpu/drm/i915/intel_pm.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      1125 drivers/gpu/drm/i915/intel_pm.c 	if (!intel_wm_plane_visible(crtc_state, plane_state))
plane_state      1128 drivers/gpu/drm/i915/intel_pm.c 	cpp = plane_state->base.fb->format->cpp[0];
plane_state      1149 drivers/gpu/drm/i915/intel_pm.c 		width = plane_state->base.crtc_w;
plane_state      1151 drivers/gpu/drm/i915/intel_pm.c 		width = drm_rect_width(&plane_state->base.dst);
plane_state      1211 drivers/gpu/drm/i915/intel_pm.c 			      const struct intel_plane_state *plane_state,
plane_state      1215 drivers/gpu/drm/i915/intel_pm.c 				     const struct intel_plane_state *plane_state)
plane_state      1217 drivers/gpu/drm/i915/intel_pm.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      1223 drivers/gpu/drm/i915/intel_pm.c 	if (!intel_wm_plane_visible(crtc_state, plane_state)) {
plane_state      1234 drivers/gpu/drm/i915/intel_pm.c 		wm = g4x_compute_wm(crtc_state, plane_state, level);
plane_state      1247 drivers/gpu/drm/i915/intel_pm.c 		wm = ilk_compute_fbc_wm(crtc_state, plane_state,
plane_state      1621 drivers/gpu/drm/i915/intel_pm.c 				const struct intel_plane_state *plane_state,
plane_state      1624 drivers/gpu/drm/i915/intel_pm.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      1633 drivers/gpu/drm/i915/intel_pm.c 	if (!intel_wm_plane_visible(crtc_state, plane_state))
plane_state      1636 drivers/gpu/drm/i915/intel_pm.c 	cpp = plane_state->base.fb->format->cpp[0];
plane_state      1792 drivers/gpu/drm/i915/intel_pm.c 				     const struct intel_plane_state *plane_state)
plane_state      1794 drivers/gpu/drm/i915/intel_pm.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      1800 drivers/gpu/drm/i915/intel_pm.c 	if (!intel_wm_plane_visible(crtc_state, plane_state)) {
plane_state      1807 drivers/gpu/drm/i915/intel_pm.c 		int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
plane_state      2506 drivers/gpu/drm/i915/intel_pm.c 			      const struct intel_plane_state *plane_state,
plane_state      2515 drivers/gpu/drm/i915/intel_pm.c 	if (!intel_wm_plane_visible(crtc_state, plane_state))
plane_state      2518 drivers/gpu/drm/i915/intel_pm.c 	cpp = plane_state->base.fb->format->cpp[0];
plane_state      2527 drivers/gpu/drm/i915/intel_pm.c 				 drm_rect_width(&plane_state->base.dst),
plane_state      2538 drivers/gpu/drm/i915/intel_pm.c 			      const struct intel_plane_state *plane_state,
plane_state      2547 drivers/gpu/drm/i915/intel_pm.c 	if (!intel_wm_plane_visible(crtc_state, plane_state))
plane_state      2550 drivers/gpu/drm/i915/intel_pm.c 	cpp = plane_state->base.fb->format->cpp[0];
plane_state      2555 drivers/gpu/drm/i915/intel_pm.c 				 drm_rect_width(&plane_state->base.dst),
plane_state      2565 drivers/gpu/drm/i915/intel_pm.c 			      const struct intel_plane_state *plane_state,
plane_state      2573 drivers/gpu/drm/i915/intel_pm.c 	if (!intel_wm_plane_visible(crtc_state, plane_state))
plane_state      2576 drivers/gpu/drm/i915/intel_pm.c 	cpp = plane_state->base.fb->format->cpp[0];
plane_state      2580 drivers/gpu/drm/i915/intel_pm.c 			      plane_state->base.crtc_w, cpp, mem_value);
plane_state      2585 drivers/gpu/drm/i915/intel_pm.c 			      const struct intel_plane_state *plane_state,
plane_state      2590 drivers/gpu/drm/i915/intel_pm.c 	if (!intel_wm_plane_visible(crtc_state, plane_state))
plane_state      2593 drivers/gpu/drm/i915/intel_pm.c 	cpp = plane_state->base.fb->format->cpp[0];
plane_state      2595 drivers/gpu/drm/i915/intel_pm.c 	return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->base.dst), cpp);
plane_state      3121 drivers/gpu/drm/i915/intel_pm.c 	const struct drm_plane_state *plane_state;
plane_state      3130 drivers/gpu/drm/i915/intel_pm.c 	drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &crtc_state->base) {
plane_state      3131 drivers/gpu/drm/i915/intel_pm.c 		const struct intel_plane_state *ps = to_intel_plane_state(plane_state);
plane_state      4072 drivers/gpu/drm/i915/intel_pm.c 			   const struct intel_plane_state *plane_state)
plane_state      4074 drivers/gpu/drm/i915/intel_pm.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      4079 drivers/gpu/drm/i915/intel_pm.c 	if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))
plane_state      4088 drivers/gpu/drm/i915/intel_pm.c 		src_w = plane_state->base.src_w >> 16;
plane_state      4089 drivers/gpu/drm/i915/intel_pm.c 		src_h = plane_state->base.src_h >> 16;
plane_state      4090 drivers/gpu/drm/i915/intel_pm.c 		dst_w = plane_state->base.crtc_w;
plane_state      4091 drivers/gpu/drm/i915/intel_pm.c 		dst_h = plane_state->base.crtc_h;
plane_state      4098 drivers/gpu/drm/i915/intel_pm.c 		src_w = drm_rect_width(&plane_state->base.src) >> 16;
plane_state      4099 drivers/gpu/drm/i915/intel_pm.c 		src_h = drm_rect_height(&plane_state->base.src) >> 16;
plane_state      4100 drivers/gpu/drm/i915/intel_pm.c 		dst_w = drm_rect_width(&plane_state->base.dst);
plane_state      4101 drivers/gpu/drm/i915/intel_pm.c 		dst_h = drm_rect_height(&plane_state->base.dst);
plane_state      4164 drivers/gpu/drm/i915/intel_pm.c 		const struct intel_plane_state *plane_state =
plane_state      4167 drivers/gpu/drm/i915/intel_pm.c 		if (!intel_wm_plane_visible(crtc_state, plane_state))
plane_state      4170 drivers/gpu/drm/i915/intel_pm.c 		if (WARN_ON(!plane_state->base.fb))
plane_state      4173 drivers/gpu/drm/i915/intel_pm.c 		plane_downscale = skl_plane_downscale_amount(crtc_state, plane_state);
plane_state      4174 drivers/gpu/drm/i915/intel_pm.c 		bpp = plane_state->base.fb->format->cpp[0] * 8;
plane_state      4203 drivers/gpu/drm/i915/intel_pm.c 			     const struct intel_plane_state *plane_state,
plane_state      4206 drivers/gpu/drm/i915/intel_pm.c 	struct intel_plane *intel_plane = to_intel_plane(plane_state->base.plane);
plane_state      4214 drivers/gpu/drm/i915/intel_pm.c 	if (!plane_state->base.visible)
plane_state      4217 drivers/gpu/drm/i915/intel_pm.c 	fb = plane_state->base.fb;
plane_state      4230 drivers/gpu/drm/i915/intel_pm.c 	width = drm_rect_width(&plane_state->base.src) >> 16;
plane_state      4231 drivers/gpu/drm/i915/intel_pm.c 	height = drm_rect_height(&plane_state->base.src) >> 16;
plane_state      4241 drivers/gpu/drm/i915/intel_pm.c 	down_scale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
plane_state      4265 drivers/gpu/drm/i915/intel_pm.c 		const struct intel_plane_state *plane_state =
plane_state      4270 drivers/gpu/drm/i915/intel_pm.c 		rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
plane_state      4275 drivers/gpu/drm/i915/intel_pm.c 		rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
plane_state      4296 drivers/gpu/drm/i915/intel_pm.c 		const struct intel_plane_state *plane_state =
plane_state      4301 drivers/gpu/drm/i915/intel_pm.c 		if (!plane_state->linked_plane) {
plane_state      4302 drivers/gpu/drm/i915/intel_pm.c 			rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
plane_state      4315 drivers/gpu/drm/i915/intel_pm.c 			if (plane_state->slave)
plane_state      4319 drivers/gpu/drm/i915/intel_pm.c 			rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
plane_state      4320 drivers/gpu/drm/i915/intel_pm.c 			y_plane_id = plane_state->linked_plane->id;
plane_state      4324 drivers/gpu/drm/i915/intel_pm.c 			rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
plane_state      4618 drivers/gpu/drm/i915/intel_pm.c 			      const struct intel_plane_state *plane_state)
plane_state      4624 drivers/gpu/drm/i915/intel_pm.c 	if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))
plane_state      4632 drivers/gpu/drm/i915/intel_pm.c 	downscale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
plane_state      4731 drivers/gpu/drm/i915/intel_pm.c 			    const struct intel_plane_state *plane_state,
plane_state      4734 drivers/gpu/drm/i915/intel_pm.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      4735 drivers/gpu/drm/i915/intel_pm.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      4739 drivers/gpu/drm/i915/intel_pm.c 		width = plane_state->base.crtc_w;
plane_state      4746 drivers/gpu/drm/i915/intel_pm.c 		width = drm_rect_width(&plane_state->base.src) >> 16;
plane_state      4751 drivers/gpu/drm/i915/intel_pm.c 				     plane_state->base.rotation,
plane_state      4752 drivers/gpu/drm/i915/intel_pm.c 				     skl_adjusted_plane_pixel_rate(crtc_state, plane_state),
plane_state      4987 drivers/gpu/drm/i915/intel_pm.c 				     const struct intel_plane_state *plane_state,
plane_state      4994 drivers/gpu/drm/i915/intel_pm.c 	ret = skl_compute_plane_wm_params(crtc_state, plane_state,
plane_state      5006 drivers/gpu/drm/i915/intel_pm.c 				 const struct intel_plane_state *plane_state,
plane_state      5016 drivers/gpu/drm/i915/intel_pm.c 	ret = skl_compute_plane_wm_params(crtc_state, plane_state,
plane_state      5027 drivers/gpu/drm/i915/intel_pm.c 			      const struct intel_plane_state *plane_state)
plane_state      5029 drivers/gpu/drm/i915/intel_pm.c 	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
plane_state      5030 drivers/gpu/drm/i915/intel_pm.c 	const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      5034 drivers/gpu/drm/i915/intel_pm.c 	if (!intel_wm_plane_visible(crtc_state, plane_state))
plane_state      5037 drivers/gpu/drm/i915/intel_pm.c 	ret = skl_build_plane_wm_single(crtc_state, plane_state,
plane_state      5043 drivers/gpu/drm/i915/intel_pm.c 		ret = skl_build_plane_wm_uv(crtc_state, plane_state,
plane_state      5053 drivers/gpu/drm/i915/intel_pm.c 			      const struct intel_plane_state *plane_state)
plane_state      5055 drivers/gpu/drm/i915/intel_pm.c 	enum plane_id plane_id = to_intel_plane(plane_state->base.plane)->id;
plane_state      5059 drivers/gpu/drm/i915/intel_pm.c 	if (plane_state->slave)
plane_state      5062 drivers/gpu/drm/i915/intel_pm.c 	if (plane_state->linked_plane) {
plane_state      5063 drivers/gpu/drm/i915/intel_pm.c 		const struct drm_framebuffer *fb = plane_state->base.fb;
plane_state      5064 drivers/gpu/drm/i915/intel_pm.c 		enum plane_id y_plane_id = plane_state->linked_plane->id;
plane_state      5066 drivers/gpu/drm/i915/intel_pm.c 		WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state));
plane_state      5070 drivers/gpu/drm/i915/intel_pm.c 		ret = skl_build_plane_wm_single(crtc_state, plane_state,
plane_state      5075 drivers/gpu/drm/i915/intel_pm.c 		ret = skl_build_plane_wm_single(crtc_state, plane_state,
plane_state      5079 drivers/gpu/drm/i915/intel_pm.c 	} else if (intel_wm_plane_visible(crtc_state, plane_state)) {
plane_state      5080 drivers/gpu/drm/i915/intel_pm.c 		ret = skl_build_plane_wm_single(crtc_state, plane_state,
plane_state      5105 drivers/gpu/drm/i915/intel_pm.c 		const struct intel_plane_state *plane_state =
plane_state      5109 drivers/gpu/drm/i915/intel_pm.c 			ret = icl_build_plane_wm(crtc_state, plane_state);
plane_state      5111 drivers/gpu/drm/i915/intel_pm.c 			ret = skl_build_plane_wm(crtc_state, plane_state);
plane_state      5289 drivers/gpu/drm/i915/intel_pm.c 		struct intel_plane_state *plane_state;
plane_state      5298 drivers/gpu/drm/i915/intel_pm.c 		plane_state = intel_atomic_get_plane_state(state, plane);
plane_state      5299 drivers/gpu/drm/i915/intel_pm.c 		if (IS_ERR(plane_state))
plane_state      5300 drivers/gpu/drm/i915/intel_pm.c 			return PTR_ERR(plane_state);
plane_state      5573 drivers/gpu/drm/i915/intel_pm.c 		struct intel_plane_state *plane_state;
plane_state      5590 drivers/gpu/drm/i915/intel_pm.c 		plane_state = intel_atomic_get_plane_state(state, plane);
plane_state      5591 drivers/gpu/drm/i915/intel_pm.c 		if (IS_ERR(plane_state))
plane_state      5592 drivers/gpu/drm/i915/intel_pm.c 			return PTR_ERR(plane_state);
plane_state      6082 drivers/gpu/drm/i915/intel_pm.c 		struct intel_plane_state *plane_state =
plane_state      6088 drivers/gpu/drm/i915/intel_pm.c 		if (plane_state->base.visible)
plane_state      6235 drivers/gpu/drm/i915/intel_pm.c 		struct intel_plane_state *plane_state =
plane_state      6243 drivers/gpu/drm/i915/intel_pm.c 		if (plane_state->base.visible)
plane_state       747 drivers/gpu/drm/imx/ipuv3-plane.c 	struct drm_plane_state *plane_state;
plane_state       769 drivers/gpu/drm/imx/ipuv3-plane.c 	for_each_new_plane_in_state(state, plane, plane_state, i) {
plane_state       770 drivers/gpu/drm/imx/ipuv3-plane.c 		ipu_state = to_ipu_plane_state(plane_state);
plane_state       773 drivers/gpu/drm/imx/ipuv3-plane.c 		if (!plane_state->fb) {
plane_state       778 drivers/gpu/drm/imx/ipuv3-plane.c 		if (!(plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) ||
plane_state       779 drivers/gpu/drm/imx/ipuv3-plane.c 		    plane_state->fb->modifier == DRM_FORMAT_MOD_LINEAR)
plane_state       786 drivers/gpu/drm/imx/ipuv3-plane.c 					      plane_state->fb->format->format,
plane_state       787 drivers/gpu/drm/imx/ipuv3-plane.c 					      plane_state->fb->modifier))
plane_state       794 drivers/gpu/drm/imx/ipuv3-plane.c 	for_each_new_plane_in_state(state, plane, plane_state, i) {
plane_state       795 drivers/gpu/drm/imx/ipuv3-plane.c 		ipu_state = to_ipu_plane_state(plane_state);
plane_state       798 drivers/gpu/drm/imx/ipuv3-plane.c 		if (!plane_state->fb) {
plane_state       803 drivers/gpu/drm/imx/ipuv3-plane.c 		if ((plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) &&
plane_state       804 drivers/gpu/drm/imx/ipuv3-plane.c 		    plane_state->fb->modifier != DRM_FORMAT_MOD_LINEAR)
plane_state       808 drivers/gpu/drm/imx/ipuv3-plane.c 		plane_state->fb->modifier = DRM_FORMAT_MOD_LINEAR;
plane_state       812 drivers/gpu/drm/imx/ipuv3-plane.c 					     plane_state->fb->format->format,
plane_state       813 drivers/gpu/drm/imx/ipuv3-plane.c 					     plane_state->fb->modifier)) {
plane_state       814 drivers/gpu/drm/mcde/mcde_display.c 				struct drm_plane_state *plane_state)
plane_state       282 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 		struct mtk_plane_state *plane_state;
plane_state       284 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 		plane_state = to_mtk_plane_state(plane->state);
plane_state       286 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 					  plane_state);
plane_state       355 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 			struct mtk_plane_state *plane_state;
plane_state       357 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 			plane_state = to_mtk_plane_state(plane->state);
plane_state       359 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 			if (plane_state->pending.config) {
plane_state       360 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 				mtk_ddp_comp_layer_config(comp, i, plane_state);
plane_state       361 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 				plane_state->pending.config = false;
plane_state       407 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 		struct mtk_plane_state *plane_state;
plane_state       409 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 		plane_state = to_mtk_plane_state(plane->state);
plane_state       410 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 		plane_state->pending.enable = false;
plane_state       411 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 		plane_state->pending.config = true;
plane_state       454 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 		struct mtk_plane_state *plane_state;
plane_state       456 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 		plane_state = to_mtk_plane_state(plane->state);
plane_state       457 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 		if (plane_state->pending.dirty) {
plane_state       458 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 			plane_state->pending.config = true;
plane_state       459 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 			plane_state->pending.dirty = false;
plane_state       815 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 	struct plane_state *pstates;
plane_state       982 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		struct plane_state *prv_pstate, *cur_pstate;
plane_state       573 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct plane_state *pa = (struct plane_state *)a;
plane_state       574 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct plane_state *pb = (struct plane_state *)b;
plane_state       616 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct plane_state pstates[STAGE_MAX + 1];
plane_state       102 drivers/gpu/drm/mxsfb/mxsfb_drv.c 			      struct drm_plane_state *plane_state)
plane_state       135 drivers/gpu/drm/mxsfb/mxsfb_drv.c 			      struct drm_plane_state *plane_state)
plane_state       139 drivers/gpu/drm/mxsfb/mxsfb_drv.c 	mxsfb_plane_atomic_update(mxsfb, plane_state);
plane_state       658 drivers/gpu/drm/omapdrm/omap_crtc.c 	struct drm_plane_state *plane_state;
plane_state       666 drivers/gpu/drm/omapdrm/omap_crtc.c 	plane_state = drm_atomic_get_plane_state(state->state, crtc->primary);
plane_state       667 drivers/gpu/drm/omapdrm/omap_crtc.c 	if (IS_ERR(plane_state))
plane_state       668 drivers/gpu/drm/omapdrm/omap_crtc.c 		return PTR_ERR(plane_state);
plane_state       671 drivers/gpu/drm/omapdrm/omap_crtc.c 		plane_state->rotation = val;
plane_state       673 drivers/gpu/drm/omapdrm/omap_crtc.c 		plane_state->zpos = val;
plane_state       121 drivers/gpu/drm/pl111/pl111_display.c 				 struct drm_plane_state *plane_state)
plane_state        14 drivers/gpu/drm/selftests/test-drm_plane_helper.c static void set_src(struct drm_plane_state *plane_state,
plane_state        18 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	plane_state->src_x = src_x;
plane_state        19 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	plane_state->src_y = src_y;
plane_state        20 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	plane_state->src_w = src_w;
plane_state        21 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	plane_state->src_h = src_h;
plane_state        24 drivers/gpu/drm/selftests/test-drm_plane_helper.c static bool check_src_eq(struct drm_plane_state *plane_state,
plane_state        28 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	if (plane_state->src.x1 < 0) {
plane_state        29 drivers/gpu/drm/selftests/test-drm_plane_helper.c 		pr_err("src x coordinate %x should never be below 0.\n", plane_state->src.x1);
plane_state        30 drivers/gpu/drm/selftests/test-drm_plane_helper.c 		drm_rect_debug_print("src: ", &plane_state->src, true);
plane_state        33 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	if (plane_state->src.y1 < 0) {
plane_state        34 drivers/gpu/drm/selftests/test-drm_plane_helper.c 		pr_err("src y coordinate %x should never be below 0.\n", plane_state->src.y1);
plane_state        35 drivers/gpu/drm/selftests/test-drm_plane_helper.c 		drm_rect_debug_print("src: ", &plane_state->src, true);
plane_state        39 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	if (plane_state->src.x1 != src_x ||
plane_state        40 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	    plane_state->src.y1 != src_y ||
plane_state        41 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	    drm_rect_width(&plane_state->src) != src_w ||
plane_state        42 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	    drm_rect_height(&plane_state->src) != src_h) {
plane_state        43 drivers/gpu/drm/selftests/test-drm_plane_helper.c 		drm_rect_debug_print("src: ", &plane_state->src, true);
plane_state        50 drivers/gpu/drm/selftests/test-drm_plane_helper.c static void set_crtc(struct drm_plane_state *plane_state,
plane_state        54 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	plane_state->crtc_x = crtc_x;
plane_state        55 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	plane_state->crtc_y = crtc_y;
plane_state        56 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	plane_state->crtc_w = crtc_w;
plane_state        57 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	plane_state->crtc_h = crtc_h;
plane_state        60 drivers/gpu/drm/selftests/test-drm_plane_helper.c static bool check_crtc_eq(struct drm_plane_state *plane_state,
plane_state        64 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	if (plane_state->dst.x1 != crtc_x ||
plane_state        65 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	    plane_state->dst.y1 != crtc_y ||
plane_state        66 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	    drm_rect_width(&plane_state->dst) != crtc_w ||
plane_state        67 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	    drm_rect_height(&plane_state->dst) != crtc_h) {
plane_state        68 drivers/gpu/drm/selftests/test-drm_plane_helper.c 		drm_rect_debug_print("dst: ", &plane_state->dst, false);
plane_state        94 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	struct drm_plane_state plane_state = {
plane_state       101 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	set_src(&plane_state, 0, 0, fb.width << 16, fb.height << 16);
plane_state       102 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	set_crtc(&plane_state, 0, 0, fb.width, fb.height);
plane_state       103 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state,
plane_state       108 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!plane_state.visible);
plane_state       109 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!check_src_eq(&plane_state, 0, 0, 1024 << 16, 768 << 16));
plane_state       110 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!check_crtc_eq(&plane_state, 0, 0, 1024, 768));
plane_state       113 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	plane_state.rotation = DRM_MODE_ROTATE_90 | DRM_MODE_REFLECT_X;
plane_state       114 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state,
plane_state       119 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!plane_state.visible);
plane_state       120 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!check_src_eq(&plane_state, 0, 0, 768 << 16, 1024 << 16));
plane_state       121 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!check_crtc_eq(&plane_state, 0, 0, 1024, 768));
plane_state       122 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	plane_state.rotation = DRM_MODE_ROTATE_0;
plane_state       125 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	set_src(&plane_state, 0, 0, 1023 << 16, 767 << 16);
plane_state       126 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	set_crtc(&plane_state, 0, 0, 1023, 767);
plane_state       127 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state,
plane_state       133 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state,
plane_state       138 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!plane_state.visible);
plane_state       139 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!check_src_eq(&plane_state, 0, 0, 1023 << 16, 767 << 16));
plane_state       140 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!check_crtc_eq(&plane_state, 0, 0, 1023, 767));
plane_state       143 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	set_src(&plane_state, 0, 0, 512 << 16, 384 << 16);
plane_state       144 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	set_crtc(&plane_state, 0, 0, 1024, 768);
plane_state       145 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state,
plane_state       150 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state,
plane_state       155 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!plane_state.visible);
plane_state       156 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!check_src_eq(&plane_state, 0, 0, 512 << 16, 384 << 16));
plane_state       157 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!check_crtc_eq(&plane_state, 0, 0, 1024, 768));
plane_state       159 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	set_src(&plane_state, 0, 0, 2048 << 16, 1536 << 16);
plane_state       160 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state,
plane_state       164 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state,
plane_state       168 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!plane_state.visible);
plane_state       169 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!check_src_eq(&plane_state, 0, 0, 2048 << 16, 1536 << 16));
plane_state       170 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!check_crtc_eq(&plane_state, 0, 0, 1024, 768));
plane_state       173 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	set_src(&plane_state, 0, 0, 0x40001, 0x40001);
plane_state       174 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	set_crtc(&plane_state, 1022, 766, 4, 4);
plane_state       175 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state,
plane_state       180 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!plane_state.visible);
plane_state       181 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!check_src_eq(&plane_state, 0, 0, 2 << 16, 2 << 16));
plane_state       182 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!check_crtc_eq(&plane_state, 1022, 766, 2, 2));
plane_state       184 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	set_src(&plane_state, 0x20001, 0x20001, 0x4040001, 0x3040001);
plane_state       185 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	set_crtc(&plane_state, -2, -2, 1028, 772);
plane_state       186 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state,
plane_state       191 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!plane_state.visible);
plane_state       192 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!check_src_eq(&plane_state, 0x40002, 0x40002, 1024 << 16, 768 << 16));
plane_state       193 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!check_crtc_eq(&plane_state, 0, 0, 1024, 768));
plane_state       195 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	set_src(&plane_state, 0, 0, 0x3ffff, 0x3ffff);
plane_state       196 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	set_crtc(&plane_state, 1022, 766, 4, 4);
plane_state       197 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state,
plane_state       202 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!plane_state.visible);
plane_state       204 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!check_src_eq(&plane_state, 0, 0, 2 << 16, 2 << 16));
plane_state       205 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!check_crtc_eq(&plane_state, 1022, 766, 2, 2));
plane_state       207 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	set_src(&plane_state, 0x1ffff, 0x1ffff, 0x403ffff, 0x303ffff);
plane_state       208 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	set_crtc(&plane_state, -2, -2, 1028, 772);
plane_state       209 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state,
plane_state       214 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!plane_state.visible);
plane_state       215 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!check_src_eq(&plane_state, 0x3fffe, 0x3fffe, 1024 << 16, 768 << 16));
plane_state       216 drivers/gpu/drm/selftests/test-drm_plane_helper.c 	FAIL_ON(!check_crtc_eq(&plane_state, 0, 0, 1024, 768));
plane_state       507 drivers/gpu/drm/sun4i/sun4i_backend.c 		struct drm_plane_state *plane_state =
plane_state       510 drivers/gpu/drm/sun4i/sun4i_backend.c 			state_to_sun4i_layer_state(plane_state);
plane_state       511 drivers/gpu/drm/sun4i/sun4i_backend.c 		struct drm_framebuffer *fb = plane_state->fb;
plane_state       514 drivers/gpu/drm/sun4i/sun4i_backend.c 		if (!sun4i_backend_plane_is_supported(plane_state,
plane_state       532 drivers/gpu/drm/sun4i/sun4i_backend.c 		if (fb->format->has_alpha || (plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE))
plane_state       536 drivers/gpu/drm/sun4i/sun4i_backend.c 				 plane_state->normalized_zpos);
plane_state       539 drivers/gpu/drm/sun4i/sun4i_backend.c 		plane_states[plane_state->normalized_zpos] = plane_state;
plane_state       603 drivers/gpu/drm/tegra/dc.c 	struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
plane_state       605 drivers/gpu/drm/tegra/dc.c 	struct tegra_bo_tiling *tiling = &plane_state->tiling;
plane_state       615 drivers/gpu/drm/tegra/dc.c 				 &plane_state->format,
plane_state       616 drivers/gpu/drm/tegra/dc.c 				 &plane_state->swap);
plane_state       627 drivers/gpu/drm/tegra/dc.c 		err = tegra_plane_setup_legacy_state(tegra, plane_state);
plane_state       645 drivers/gpu/drm/tegra/dc.c 		plane_state->bottom_up = true;
plane_state       647 drivers/gpu/drm/tegra/dc.c 		plane_state->bottom_up = false;
plane_state       329 drivers/gpu/drm/tegra/hub.c 	struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
plane_state       331 drivers/gpu/drm/tegra/hub.c 	struct tegra_bo_tiling *tiling = &plane_state->tiling;
plane_state       340 drivers/gpu/drm/tegra/hub.c 				 &plane_state->format,
plane_state       341 drivers/gpu/drm/tegra/hub.c 				 &plane_state->swap);
plane_state       339 drivers/gpu/drm/tegra/plane.c 	struct drm_plane_state *old, *plane_state;
plane_state       357 drivers/gpu/drm/tegra/plane.c 		plane_state = drm_atomic_get_plane_state(state->base.state,
plane_state       359 drivers/gpu/drm/tegra/plane.c 		if (IS_ERR(plane_state))
plane_state       360 drivers/gpu/drm/tegra/plane.c 			return PTR_ERR(plane_state);
plane_state       591 drivers/gpu/drm/tiny/gm12u320.c 				 struct drm_plane_state *plane_state)
plane_state       596 drivers/gpu/drm/tiny/gm12u320.c 	gm12u320_fb_mark_dirty(plane_state->fb, &rect);
plane_state        48 drivers/gpu/drm/tiny/hx8357d.c 			     struct drm_plane_state *plane_state)
plane_state       177 drivers/gpu/drm/tiny/hx8357d.c 	mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
plane_state       184 drivers/gpu/drm/tiny/ili9225.c 				struct drm_plane_state *plane_state)
plane_state       187 drivers/gpu/drm/tiny/ili9225.c 	struct drm_framebuffer *fb = plane_state->fb;
plane_state        54 drivers/gpu/drm/tiny/ili9341.c 			     struct drm_plane_state *plane_state)
plane_state       133 drivers/gpu/drm/tiny/ili9341.c 	mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
plane_state        52 drivers/gpu/drm/tiny/mi0283qt.c 			    struct drm_plane_state *plane_state)
plane_state       137 drivers/gpu/drm/tiny/mi0283qt.c 	mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
plane_state       655 drivers/gpu/drm/tiny/repaper.c 				struct drm_plane_state *plane_state)
plane_state       178 drivers/gpu/drm/tiny/st7586.c 			       struct drm_plane_state *plane_state)
plane_state       181 drivers/gpu/drm/tiny/st7586.c 	struct drm_framebuffer *fb = plane_state->fb;
plane_state        43 drivers/gpu/drm/tiny/st7735r.c 				      struct drm_plane_state *plane_state)
plane_state       107 drivers/gpu/drm/tiny/st7735r.c 	mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
plane_state       122 drivers/gpu/drm/tve200/tve200_display.c 				 struct drm_plane_state *plane_state)
plane_state       633 drivers/gpu/drm/vc4/vc4_crtc.c 	const struct drm_plane_state *plane_state;
plane_state       645 drivers/gpu/drm/vc4/vc4_crtc.c 	drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
plane_state       646 drivers/gpu/drm/vc4/vc4_crtc.c 		dlist_count += vc4_plane_dlist_size(plane_state);
plane_state       168 drivers/gpu/drm/vkms/vkms_crtc.c 	struct drm_plane_state *plane_state;
plane_state       179 drivers/gpu/drm/vkms/vkms_crtc.c 		plane_state = drm_atomic_get_existing_plane_state(state->state,
plane_state       181 drivers/gpu/drm/vkms/vkms_crtc.c 		WARN_ON(!plane_state);
plane_state       183 drivers/gpu/drm/vkms/vkms_crtc.c 		if (!plane_state->visible)
plane_state       196 drivers/gpu/drm/vkms/vkms_crtc.c 		plane_state = drm_atomic_get_existing_plane_state(state->state,
plane_state       199 drivers/gpu/drm/vkms/vkms_crtc.c 		if (!plane_state->visible)
plane_state       203 drivers/gpu/drm/vkms/vkms_crtc.c 			to_vkms_plane_state(plane_state);
plane_state      1561 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 	struct drm_plane_state *plane_state;
plane_state      1580 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 		plane_state = du->primary.state;
plane_state      1581 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 		if (plane_state->crtc != crtc)
plane_state      1585 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 			implicit_fb = plane_state->fb;
plane_state      1586 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 		else if (implicit_fb != plane_state->fb)
plane_state       113 drivers/gpu/drm/xen/xen_drm_front_kms.c 			   struct drm_plane_state *plane_state)
plane_state       118 drivers/gpu/drm/xen/xen_drm_front_kms.c 	struct drm_framebuffer *fb = plane_state->fb;
plane_state       186 drivers/gpu/drm/xen/xen_drm_front_kms.c 	struct drm_plane_state *plane_state =
plane_state       198 drivers/gpu/drm/xen/xen_drm_front_kms.c 	if (old_plane_state->fb && plane_state->fb) {
plane_state       209 drivers/gpu/drm/xen/xen_drm_front_kms.c 					      xen_drm_front_fb_to_cookie(plane_state->fb));
plane_state        49 drivers/gpu/drm/zte/zx_plane.c 				    struct drm_plane_state *plane_state)
plane_state        51 drivers/gpu/drm/zte/zx_plane.c 	struct drm_framebuffer *fb = plane_state->fb;
plane_state        52 drivers/gpu/drm/zte/zx_plane.c 	struct drm_crtc *crtc = plane_state->crtc;
plane_state        60 drivers/gpu/drm/zte/zx_plane.c 	crtc_state = drm_atomic_get_existing_crtc_state(plane_state->state,
plane_state        70 drivers/gpu/drm/zte/zx_plane.c 	if (!plane_state->crtc)
plane_state        73 drivers/gpu/drm/zte/zx_plane.c 	return drm_atomic_helper_check_plane_state(plane_state, crtc_state,
plane_state       278 drivers/gpu/drm/zte/zx_plane.c 				    struct drm_plane_state *plane_state)
plane_state       280 drivers/gpu/drm/zte/zx_plane.c 	struct drm_framebuffer *fb = plane_state->fb;
plane_state       281 drivers/gpu/drm/zte/zx_plane.c 	struct drm_crtc *crtc = plane_state->crtc;
plane_state       287 drivers/gpu/drm/zte/zx_plane.c 	crtc_state = drm_atomic_get_existing_crtc_state(plane_state->state,
plane_state       297 drivers/gpu/drm/zte/zx_plane.c 	if (!plane_state->crtc)
plane_state       300 drivers/gpu/drm/zte/zx_plane.c 	return drm_atomic_helper_check_plane_state(plane_state, crtc_state,
plane_state        43 include/drm/drm_atomic_helper.h int drm_atomic_helper_check_plane_state(struct drm_plane_state *plane_state,
plane_state       194 include/drm/drm_atomic_helper.h #define drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) \
plane_state       196 include/drm/drm_atomic_helper.h 		for_each_if ((plane_state = \
plane_state        48 include/drm/drm_atomic_uapi.h drm_atomic_set_crtc_for_plane(struct drm_plane_state *plane_state,
plane_state        50 include/drm/drm_atomic_uapi.h void drm_atomic_set_fb_for_plane(struct drm_plane_state *plane_state,
plane_state        52 include/drm/drm_atomic_uapi.h void drm_atomic_set_fence_for_plane(struct drm_plane_state *plane_state,
plane_state        69 include/drm/drm_damage_helper.h 					  struct drm_plane_state *plane_state);
plane_state        35 include/drm/drm_gem_framebuffer_helper.h 					      struct drm_plane_state *plane_state);
plane_state        64 include/drm/drm_simple_kms_helper.h 		       struct drm_plane_state *plane_state);
plane_state        92 include/drm/drm_simple_kms_helper.h 		     struct drm_plane_state *plane_state,
plane_state       120 include/drm/drm_simple_kms_helper.h 			  struct drm_plane_state *plane_state);
plane_state       130 include/drm/drm_simple_kms_helper.h 			   struct drm_plane_state *plane_state);