plane_id         2161 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			    struct amdgpu_mode_info *mode_info, int plane_id,
plane_id         2182 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	possible_crtcs = 1 << plane_id;
plane_id         2183 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	if (plane_id >= dm->dc->caps.max_streams)
plane_id         2195 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		mode_info->planes[plane_id] = plane;
plane_id          602 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	int plane_id)
plane_id          608 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		hws->ctx->dc->hwss.dpp_pg_control(hws, plane_id, true);
plane_id          609 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		hws->ctx->dc->hwss.hubp_pg_control(hws, plane_id, true);
plane_id          613 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				"Un-gated front end for pipe %d\n", plane_id);
plane_id          522 drivers/gpu/drm/drm_plane.c 	plane = drm_plane_find(dev, file_priv, plane_resp->plane_id);
plane_id          542 drivers/gpu/drm/drm_plane.c 	plane_resp->plane_id = plane->base.id;
plane_id          806 drivers/gpu/drm/drm_plane.c 	plane = drm_plane_find(dev, file_priv, plane_req->plane_id);
plane_id          809 drivers/gpu/drm/drm_plane.c 			      plane_req->plane_id);
plane_id          242 drivers/gpu/drm/i915/display/intel_atomic_plane.c 		enum plane_id plane_id = plane->id;
plane_id          245 drivers/gpu/drm/i915/display/intel_atomic_plane.c 		    !(*update_mask & BIT(plane_id)))
plane_id          248 drivers/gpu/drm/i915/display/intel_atomic_plane.c 		if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
plane_id          250 drivers/gpu/drm/i915/display/intel_atomic_plane.c 						I915_MAX_PLANES, plane_id) ||
plane_id          251 drivers/gpu/drm/i915/display/intel_atomic_plane.c 		    skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id],
plane_id          253 drivers/gpu/drm/i915/display/intel_atomic_plane.c 						I915_MAX_PLANES, plane_id))
plane_id          256 drivers/gpu/drm/i915/display/intel_atomic_plane.c 		*update_mask &= ~BIT(plane_id);
plane_id          257 drivers/gpu/drm/i915/display/intel_atomic_plane.c 		entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
plane_id          258 drivers/gpu/drm/i915/display/intel_atomic_plane.c 		entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id];
plane_id          269 drivers/gpu/drm/i915/display/intel_bw.c 	enum plane_id plane_id;
plane_id          271 drivers/gpu/drm/i915/display/intel_bw.c 	for_each_plane_id_on_crtc(crtc, plane_id) {
plane_id          276 drivers/gpu/drm/i915/display/intel_bw.c 		if (plane_id == PLANE_CURSOR)
plane_id          279 drivers/gpu/drm/i915/display/intel_bw.c 		data_rate += crtc_state->data_rate[plane_id];
plane_id         9798 drivers/gpu/drm/i915/display/intel_display.c 	enum plane_id plane_id = plane->id;
plane_id         9821 drivers/gpu/drm/i915/display/intel_display.c 	val = I915_READ(PLANE_CTL(pipe, plane_id));
plane_id         9829 drivers/gpu/drm/i915/display/intel_display.c 		alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
plane_id         9889 drivers/gpu/drm/i915/display/intel_display.c 	base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
plane_id         9892 drivers/gpu/drm/i915/display/intel_display.c 	offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
plane_id         9894 drivers/gpu/drm/i915/display/intel_display.c 	val = I915_READ(PLANE_SIZE(pipe, plane_id));
plane_id         9898 drivers/gpu/drm/i915/display/intel_display.c 	val = I915_READ(PLANE_STRIDE(pipe, plane_id));
plane_id         1035 drivers/gpu/drm/i915/display/intel_display_types.h 	enum plane_id id;
plane_id          334 drivers/gpu/drm/i915/display/intel_sprite.c bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id)
plane_id          337 drivers/gpu/drm/i915/display/intel_sprite.c 		icl_hdr_plane_mask() & BIT(plane_id);
plane_id          427 drivers/gpu/drm/i915/display/intel_sprite.c 	enum plane_id plane_id = plane->id;
plane_id          514 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), ROFF(csc[0]) |
plane_id          516 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), BOFF(csc[2]));
plane_id          517 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), ROFF(csc[3]) |
plane_id          519 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), BOFF(csc[5]));
plane_id          520 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), ROFF(csc[6]) |
plane_id          522 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), BOFF(csc[8]));
plane_id          524 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
plane_id          527 drivers/gpu/drm/i915/display/intel_sprite.c 		I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 0);
plane_id          529 drivers/gpu/drm/i915/display/intel_sprite.c 		I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
plane_id          531 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
plane_id          533 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);
plane_id          534 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0);
plane_id          535 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
plane_id          545 drivers/gpu/drm/i915/display/intel_sprite.c 	enum plane_id plane_id = plane->id;
plane_id          588 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
plane_id          589 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
plane_id          590 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
plane_id          591 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
plane_id          594 drivers/gpu/drm/i915/display/intel_sprite.c 	if (icl_is_hdr_plane(dev_priv, plane_id)) {
plane_id          612 drivers/gpu/drm/i915/display/intel_sprite.c 		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), cus_ctl);
plane_id          616 drivers/gpu/drm/i915/display/intel_sprite.c 		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
plane_id          618 drivers/gpu/drm/i915/display/intel_sprite.c 	if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
plane_id          623 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
plane_id          624 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk);
plane_id          625 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax);
plane_id          627 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
plane_id          630 drivers/gpu/drm/i915/display/intel_sprite.c 		I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
plane_id          639 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
plane_id          640 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
plane_id          679 drivers/gpu/drm/i915/display/intel_sprite.c 	enum plane_id plane_id = plane->id;
plane_id          685 drivers/gpu/drm/i915/display/intel_sprite.c 	if (icl_is_hdr_plane(dev_priv, plane_id))
plane_id          686 drivers/gpu/drm/i915/display/intel_sprite.c 		I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), 0);
plane_id          690 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
plane_id          691 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
plane_id          702 drivers/gpu/drm/i915/display/intel_sprite.c 	enum plane_id plane_id = plane->id;
plane_id          711 drivers/gpu/drm/i915/display/intel_sprite.c 	ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
plane_id          736 drivers/gpu/drm/i915/display/intel_sprite.c 	enum plane_id plane_id = plane->id;
plane_id          767 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
plane_id          768 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
plane_id          769 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
plane_id          771 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));
plane_id          772 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));
plane_id          773 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));
plane_id          774 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));
plane_id          775 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8]));
plane_id          777 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));
plane_id          778 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
plane_id          779 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
plane_id          781 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
plane_id          782 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
plane_id          783 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
plane_id          796 drivers/gpu/drm/i915/display/intel_sprite.c 	enum plane_id plane_id = plane->id;
plane_id          822 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCLRC0(pipe, plane_id),
plane_id          824 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCLRC1(pipe, plane_id),
plane_id          911 drivers/gpu/drm/i915/display/intel_sprite.c 	enum plane_id plane_id = plane->id;
plane_id          924 drivers/gpu/drm/i915/display/intel_sprite.c 		I915_WRITE_FW(SPGAMC(pipe, plane_id, i - 1),
plane_id          937 drivers/gpu/drm/i915/display/intel_sprite.c 	enum plane_id plane_id = plane->id;
plane_id          960 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
plane_id          962 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
plane_id          963 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
plane_id          964 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
plane_id          970 drivers/gpu/drm/i915/display/intel_sprite.c 		I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
plane_id          971 drivers/gpu/drm/i915/display/intel_sprite.c 		I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
plane_id          972 drivers/gpu/drm/i915/display/intel_sprite.c 		I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
plane_id          975 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
plane_id          976 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
plane_id          983 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
plane_id          984 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPSURF(pipe, plane_id),
plane_id          999 drivers/gpu/drm/i915/display/intel_sprite.c 	enum plane_id plane_id = plane->id;
plane_id         1004 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
plane_id         1005 drivers/gpu/drm/i915/display/intel_sprite.c 	I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
plane_id         1016 drivers/gpu/drm/i915/display/intel_sprite.c 	enum plane_id plane_id = plane->id;
plane_id         1025 drivers/gpu/drm/i915/display/intel_sprite.c 	ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
plane_id         1919 drivers/gpu/drm/i915/display/intel_sprite.c 	plane = drm_plane_find(dev, file_priv, set->plane_id);
plane_id         2346 drivers/gpu/drm/i915/display/intel_sprite.c 			      enum pipe pipe, enum plane_id plane_id)
plane_id         2351 drivers/gpu/drm/i915/display/intel_sprite.c 	return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
plane_id         2355 drivers/gpu/drm/i915/display/intel_sprite.c 				 enum pipe pipe, enum plane_id plane_id)
plane_id         2364 drivers/gpu/drm/i915/display/intel_sprite.c 	if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
plane_id         2371 drivers/gpu/drm/i915/display/intel_sprite.c 					enum pipe pipe, enum plane_id plane_id,
plane_id         2374 drivers/gpu/drm/i915/display/intel_sprite.c 	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
plane_id         2384 drivers/gpu/drm/i915/display/intel_sprite.c 					enum pipe pipe, enum plane_id plane_id,
plane_id         2387 drivers/gpu/drm/i915/display/intel_sprite.c 	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
plane_id         2397 drivers/gpu/drm/i915/display/intel_sprite.c 					enum pipe pipe, enum plane_id plane_id,
plane_id         2400 drivers/gpu/drm/i915/display/intel_sprite.c 	if (icl_is_hdr_plane(dev_priv, plane_id)) {
plane_id         2403 drivers/gpu/drm/i915/display/intel_sprite.c 	} else if (icl_is_nv12_y_plane(plane_id)) {
plane_id         2413 drivers/gpu/drm/i915/display/intel_sprite.c 			      enum pipe pipe, enum plane_id plane_id)
plane_id         2415 drivers/gpu/drm/i915/display/intel_sprite.c 	if (plane_id == PLANE_CURSOR)
plane_id         2425 drivers/gpu/drm/i915/display/intel_sprite.c 		(plane_id == PLANE_PRIMARY ||
plane_id         2426 drivers/gpu/drm/i915/display/intel_sprite.c 		 plane_id == PLANE_SPRITE0);
plane_id         2431 drivers/gpu/drm/i915/display/intel_sprite.c 			   enum pipe pipe, enum plane_id plane_id)
plane_id         2447 drivers/gpu/drm/i915/display/intel_sprite.c 	plane->id = plane_id;
plane_id         2448 drivers/gpu/drm/i915/display/intel_sprite.c 	plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id);
plane_id         2450 drivers/gpu/drm/i915/display/intel_sprite.c 	plane->has_fbc = skl_plane_has_fbc(dev_priv, pipe, plane_id);
plane_id         2462 drivers/gpu/drm/i915/display/intel_sprite.c 	if (icl_is_nv12_y_plane(plane_id))
plane_id         2467 drivers/gpu/drm/i915/display/intel_sprite.c 						plane_id, &num_formats);
plane_id         2470 drivers/gpu/drm/i915/display/intel_sprite.c 						plane_id, &num_formats);
plane_id         2473 drivers/gpu/drm/i915/display/intel_sprite.c 						plane_id, &num_formats);
plane_id         2475 drivers/gpu/drm/i915/display/intel_sprite.c 	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
plane_id         2481 drivers/gpu/drm/i915/display/intel_sprite.c 	if (plane_id == PLANE_PRIMARY)
plane_id         2492 drivers/gpu/drm/i915/display/intel_sprite.c 				       "plane %d%c", plane_id + 1,
plane_id           34 drivers/gpu/drm/i915/display/intel_sprite.h 			   enum pipe pipe, enum plane_id plane_id);
plane_id           36 drivers/gpu/drm/i915/display/intel_sprite.h static inline bool icl_is_nv12_y_plane(enum plane_id id)
plane_id           51 drivers/gpu/drm/i915/display/intel_sprite.h bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
plane_id          209 drivers/gpu/drm/i915/gvt/dmabuf.c 		int plane_id)
plane_id          217 drivers/gpu/drm/i915/gvt/dmabuf.c 	if (plane_id == DRM_PLANE_TYPE_PRIMARY) {
plane_id          247 drivers/gpu/drm/i915/gvt/dmabuf.c 	} else if (plane_id == DRM_PLANE_TYPE_CURSOR) {
plane_id          269 drivers/gpu/drm/i915/gvt/dmabuf.c 		gvt_vgpu_err("invalid plane id:%d\n", plane_id);
plane_id          797 drivers/gpu/drm/i915/gvt/handlers.c 	enum plane_id plane = REG_50080_TO_PLANE(offset);
plane_id         2971 drivers/gpu/drm/i915/i915_debugfs.c 		enum plane_id plane_id;
plane_id         2975 drivers/gpu/drm/i915/i915_debugfs.c 		for_each_plane_id_on_crtc(crtc, plane_id) {
plane_id         2976 drivers/gpu/drm/i915/i915_debugfs.c 			entry = &crtc_state->wm.skl.plane_ddb_y[plane_id];
plane_id         2977 drivers/gpu/drm/i915/i915_debugfs.c 			seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane_id + 1,
plane_id         1824 drivers/gpu/drm/i915/i915_drv.h #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
plane_id         1827 drivers/gpu/drm/i915/i915_drv.h 	BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
plane_id         6561 drivers/gpu/drm/i915/i915_reg.h #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
plane_id         6562 drivers/gpu/drm/i915/i915_reg.h 	_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
plane_id         6563 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
plane_id         6564 drivers/gpu/drm/i915/i915_reg.h 	_MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
plane_id         6566 drivers/gpu/drm/i915/i915_reg.h #define SPCNTR(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
plane_id         6567 drivers/gpu/drm/i915/i915_reg.h #define SPLINOFF(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
plane_id         6568 drivers/gpu/drm/i915/i915_reg.h #define SPSTRIDE(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
plane_id         6569 drivers/gpu/drm/i915/i915_reg.h #define SPPOS(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
plane_id         6570 drivers/gpu/drm/i915/i915_reg.h #define SPSIZE(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
plane_id         6571 drivers/gpu/drm/i915/i915_reg.h #define SPKEYMINVAL(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
plane_id         6572 drivers/gpu/drm/i915/i915_reg.h #define SPKEYMSK(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
plane_id         6573 drivers/gpu/drm/i915/i915_reg.h #define SPSURF(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
plane_id         6574 drivers/gpu/drm/i915/i915_reg.h #define SPKEYMAXVAL(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
plane_id         6575 drivers/gpu/drm/i915/i915_reg.h #define SPTILEOFF(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
plane_id         6576 drivers/gpu/drm/i915/i915_reg.h #define SPCONSTALPHA(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
plane_id         6577 drivers/gpu/drm/i915/i915_reg.h #define SPCLRC0(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
plane_id         6578 drivers/gpu/drm/i915/i915_reg.h #define SPCLRC1(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
plane_id         6579 drivers/gpu/drm/i915/i915_reg.h #define SPGAMC(pipe, plane_id, i)	_MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
plane_id         6588 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_CHV_SPCSC(plane_id, reg) \
plane_id         6589 drivers/gpu/drm/i915/i915_reg.h 	_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
plane_id         6591 drivers/gpu/drm/i915/i915_reg.h #define SPCSCYGOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d900)
plane_id         6592 drivers/gpu/drm/i915/i915_reg.h #define SPCSCCBOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d904)
plane_id         6593 drivers/gpu/drm/i915/i915_reg.h #define SPCSCCROFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d908)
plane_id         6597 drivers/gpu/drm/i915/i915_reg.h #define SPCSCC01(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d90c)
plane_id         6598 drivers/gpu/drm/i915/i915_reg.h #define SPCSCC23(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d910)
plane_id         6599 drivers/gpu/drm/i915/i915_reg.h #define SPCSCC45(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d914)
plane_id         6600 drivers/gpu/drm/i915/i915_reg.h #define SPCSCC67(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d918)
plane_id         6601 drivers/gpu/drm/i915/i915_reg.h #define SPCSCC8(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d91c)
plane_id         6605 drivers/gpu/drm/i915/i915_reg.h #define SPCSCYGICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d920)
plane_id         6606 drivers/gpu/drm/i915/i915_reg.h #define SPCSCCBICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d924)
plane_id         6607 drivers/gpu/drm/i915/i915_reg.h #define SPCSCCRICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d928)
plane_id         6611 drivers/gpu/drm/i915/i915_reg.h #define SPCSCYGOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d92c)
plane_id         6612 drivers/gpu/drm/i915/i915_reg.h #define SPCSCCBOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d930)
plane_id         6613 drivers/gpu/drm/i915/i915_reg.h #define SPCSCCROCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d934)
plane_id         1069 drivers/gpu/drm/i915/intel_pm.c static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
plane_id         1085 drivers/gpu/drm/i915/intel_pm.c 	switch (plane_id) {
plane_id         1093 drivers/gpu/drm/i915/intel_pm.c 		MISSING_CASE(plane_id);
plane_id         1176 drivers/gpu/drm/i915/intel_pm.c 				 int level, enum plane_id plane_id, u16 value)
plane_id         1184 drivers/gpu/drm/i915/intel_pm.c 		dirty |= raw->plane[plane_id] != value;
plane_id         1185 drivers/gpu/drm/i915/intel_pm.c 		raw->plane[plane_id] = value;
plane_id         1219 drivers/gpu/drm/i915/intel_pm.c 	enum plane_id plane_id = plane->id;
plane_id         1224 drivers/gpu/drm/i915/intel_pm.c 		dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
plane_id         1225 drivers/gpu/drm/i915/intel_pm.c 		if (plane_id == PLANE_PRIMARY)
plane_id         1235 drivers/gpu/drm/i915/intel_pm.c 		max_wm = g4x_plane_fifo_size(plane_id, level);
plane_id         1240 drivers/gpu/drm/i915/intel_pm.c 		dirty |= raw->plane[plane_id] != wm;
plane_id         1241 drivers/gpu/drm/i915/intel_pm.c 		raw->plane[plane_id] = wm;
plane_id         1243 drivers/gpu/drm/i915/intel_pm.c 		if (plane_id != PLANE_PRIMARY ||
plane_id         1248 drivers/gpu/drm/i915/intel_pm.c 					raw->plane[plane_id]);
plane_id         1263 drivers/gpu/drm/i915/intel_pm.c 	dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
plane_id         1265 drivers/gpu/drm/i915/intel_pm.c 	if (plane_id == PLANE_PRIMARY)
plane_id         1272 drivers/gpu/drm/i915/intel_pm.c 			      crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
plane_id         1273 drivers/gpu/drm/i915/intel_pm.c 			      crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
plane_id         1274 drivers/gpu/drm/i915/intel_pm.c 			      crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
plane_id         1276 drivers/gpu/drm/i915/intel_pm.c 		if (plane_id == PLANE_PRIMARY)
plane_id         1286 drivers/gpu/drm/i915/intel_pm.c 				      enum plane_id plane_id, int level)
plane_id         1290 drivers/gpu/drm/i915/intel_pm.c 	return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);
plane_id         1311 drivers/gpu/drm/i915/intel_pm.c 		enum plane_id plane_id;
plane_id         1313 drivers/gpu/drm/i915/intel_pm.c 		for_each_plane_id_on_crtc(crtc, plane_id)
plane_id         1314 drivers/gpu/drm/i915/intel_pm.c 			wm_state->wm.plane[plane_id] = USHRT_MAX;
plane_id         1344 drivers/gpu/drm/i915/intel_pm.c 	enum plane_id plane_id;
plane_id         1367 drivers/gpu/drm/i915/intel_pm.c 	for_each_plane_id_on_crtc(crtc, plane_id)
plane_id         1368 drivers/gpu/drm/i915/intel_pm.c 		wm_state->wm.plane[plane_id] = raw->plane[plane_id];
plane_id         1431 drivers/gpu/drm/i915/intel_pm.c 	enum plane_id plane_id;
plane_id         1447 drivers/gpu/drm/i915/intel_pm.c 	for_each_plane_id_on_crtc(crtc, plane_id) {
plane_id         1448 drivers/gpu/drm/i915/intel_pm.c 		intermediate->wm.plane[plane_id] =
plane_id         1449 drivers/gpu/drm/i915/intel_pm.c 			max(optimal->wm.plane[plane_id],
plane_id         1450 drivers/gpu/drm/i915/intel_pm.c 			    active->wm.plane[plane_id]);
plane_id         1452 drivers/gpu/drm/i915/intel_pm.c 		WARN_ON(intermediate->wm.plane[plane_id] >
plane_id         1453 drivers/gpu/drm/i915/intel_pm.c 			g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));
plane_id         1675 drivers/gpu/drm/i915/intel_pm.c 	enum plane_id plane_id;
plane_id         1699 drivers/gpu/drm/i915/intel_pm.c 	for_each_plane_id_on_crtc(crtc, plane_id) {
plane_id         1702 drivers/gpu/drm/i915/intel_pm.c 		if ((active_planes & BIT(plane_id)) == 0) {
plane_id         1703 drivers/gpu/drm/i915/intel_pm.c 			fifo_state->plane[plane_id] = 0;
plane_id         1707 drivers/gpu/drm/i915/intel_pm.c 		rate = raw->plane[plane_id];
plane_id         1708 drivers/gpu/drm/i915/intel_pm.c 		fifo_state->plane[plane_id] = fifo_size * rate / total_rate;
plane_id         1709 drivers/gpu/drm/i915/intel_pm.c 		fifo_left -= fifo_state->plane[plane_id];
plane_id         1720 drivers/gpu/drm/i915/intel_pm.c 	for_each_plane_id_on_crtc(crtc, plane_id) {
plane_id         1726 drivers/gpu/drm/i915/intel_pm.c 		if ((active_planes & BIT(plane_id)) == 0)
plane_id         1730 drivers/gpu/drm/i915/intel_pm.c 		fifo_state->plane[plane_id] += plane_extra;
plane_id         1752 drivers/gpu/drm/i915/intel_pm.c 		enum plane_id plane_id;
plane_id         1754 drivers/gpu/drm/i915/intel_pm.c 		for_each_plane_id_on_crtc(crtc, plane_id)
plane_id         1755 drivers/gpu/drm/i915/intel_pm.c 			wm_state->wm[level].plane[plane_id] = USHRT_MAX;
plane_id         1775 drivers/gpu/drm/i915/intel_pm.c 				 int level, enum plane_id plane_id, u16 value)
plane_id         1784 drivers/gpu/drm/i915/intel_pm.c 		dirty |= raw->plane[plane_id] != value;
plane_id         1785 drivers/gpu/drm/i915/intel_pm.c 		raw->plane[plane_id] = value;
plane_id         1795 drivers/gpu/drm/i915/intel_pm.c 	enum plane_id plane_id = plane->id;
plane_id         1801 drivers/gpu/drm/i915/intel_pm.c 		dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
plane_id         1808 drivers/gpu/drm/i915/intel_pm.c 		int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;
plane_id         1813 drivers/gpu/drm/i915/intel_pm.c 		dirty |= raw->plane[plane_id] != wm;
plane_id         1814 drivers/gpu/drm/i915/intel_pm.c 		raw->plane[plane_id] = wm;
plane_id         1818 drivers/gpu/drm/i915/intel_pm.c 	dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
plane_id         1824 drivers/gpu/drm/i915/intel_pm.c 			      crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
plane_id         1825 drivers/gpu/drm/i915/intel_pm.c 			      crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
plane_id         1826 drivers/gpu/drm/i915/intel_pm.c 			      crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
plane_id         1832 drivers/gpu/drm/i915/intel_pm.c 				      enum plane_id plane_id, int level)
plane_id         1839 drivers/gpu/drm/i915/intel_pm.c 	return raw->plane[plane_id] <= fifo_state->plane[plane_id];
plane_id         1865 drivers/gpu/drm/i915/intel_pm.c 	enum plane_id plane_id;
plane_id         1925 drivers/gpu/drm/i915/intel_pm.c 		for_each_plane_id_on_crtc(crtc, plane_id) {
plane_id         1926 drivers/gpu/drm/i915/intel_pm.c 			wm_state->wm[level].plane[plane_id] =
plane_id         1927 drivers/gpu/drm/i915/intel_pm.c 				vlv_invert_wm_value(raw->plane[plane_id],
plane_id         1928 drivers/gpu/drm/i915/intel_pm.c 						    fifo_state->plane[plane_id]);
plane_id         2078 drivers/gpu/drm/i915/intel_pm.c 		enum plane_id plane_id;
plane_id         2080 drivers/gpu/drm/i915/intel_pm.c 		for_each_plane_id_on_crtc(crtc, plane_id) {
plane_id         2081 drivers/gpu/drm/i915/intel_pm.c 			intermediate->wm[level].plane[plane_id] =
plane_id         2082 drivers/gpu/drm/i915/intel_pm.c 				min(optimal->wm[level].plane[plane_id],
plane_id         2083 drivers/gpu/drm/i915/intel_pm.c 				    active->wm[level].plane[plane_id]);
plane_id         3987 drivers/gpu/drm/i915/intel_pm.c 			   const enum plane_id plane_id,
plane_id         3995 drivers/gpu/drm/i915/intel_pm.c 	if (plane_id == PLANE_CURSOR) {
plane_id         4001 drivers/gpu/drm/i915/intel_pm.c 	val = I915_READ(PLANE_CTL(pipe, plane_id));
plane_id         4010 drivers/gpu/drm/i915/intel_pm.c 		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
plane_id         4013 drivers/gpu/drm/i915/intel_pm.c 		val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
plane_id         4014 drivers/gpu/drm/i915/intel_pm.c 		val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
plane_id         4032 drivers/gpu/drm/i915/intel_pm.c 	enum plane_id plane_id;
plane_id         4039 drivers/gpu/drm/i915/intel_pm.c 	for_each_plane_id_on_crtc(crtc, plane_id)
plane_id         4041 drivers/gpu/drm/i915/intel_pm.c 					   plane_id,
plane_id         4042 drivers/gpu/drm/i915/intel_pm.c 					   &ddb_y[plane_id],
plane_id         4043 drivers/gpu/drm/i915/intel_pm.c 					   &ddb_uv[plane_id]);
plane_id         4264 drivers/gpu/drm/i915/intel_pm.c 		enum plane_id plane_id = to_intel_plane(plane)->id;
plane_id         4271 drivers/gpu/drm/i915/intel_pm.c 		plane_data_rate[plane_id] = rate;
plane_id         4276 drivers/gpu/drm/i915/intel_pm.c 		uv_plane_data_rate[plane_id] = rate;
plane_id         4298 drivers/gpu/drm/i915/intel_pm.c 		enum plane_id plane_id = to_intel_plane(plane)->id;
plane_id         4303 drivers/gpu/drm/i915/intel_pm.c 			plane_data_rate[plane_id] = rate;
plane_id         4306 drivers/gpu/drm/i915/intel_pm.c 			enum plane_id y_plane_id;
plane_id         4325 drivers/gpu/drm/i915/intel_pm.c 			plane_data_rate[plane_id] = rate;
plane_id         4346 drivers/gpu/drm/i915/intel_pm.c 	enum plane_id plane_id;
plane_id         4398 drivers/gpu/drm/i915/intel_pm.c 		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
plane_id         4400 drivers/gpu/drm/i915/intel_pm.c 				&crtc_state->wm.skl.optimal.planes[plane_id];
plane_id         4402 drivers/gpu/drm/i915/intel_pm.c 			if (plane_id == PLANE_CURSOR) {
plane_id         4433 drivers/gpu/drm/i915/intel_pm.c 	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
plane_id         4435 drivers/gpu/drm/i915/intel_pm.c 			&crtc_state->wm.skl.optimal.planes[plane_id];
plane_id         4439 drivers/gpu/drm/i915/intel_pm.c 		if (plane_id == PLANE_CURSOR)
plane_id         4449 drivers/gpu/drm/i915/intel_pm.c 		rate = plane_data_rate[plane_id];
plane_id         4453 drivers/gpu/drm/i915/intel_pm.c 		total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
plane_id         4460 drivers/gpu/drm/i915/intel_pm.c 		rate = uv_plane_data_rate[plane_id];
plane_id         4464 drivers/gpu/drm/i915/intel_pm.c 		uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
plane_id         4472 drivers/gpu/drm/i915/intel_pm.c 	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
plane_id         4474 drivers/gpu/drm/i915/intel_pm.c 			&crtc_state->wm.skl.plane_ddb_y[plane_id];
plane_id         4476 drivers/gpu/drm/i915/intel_pm.c 			&crtc_state->wm.skl.plane_ddb_uv[plane_id];
plane_id         4478 drivers/gpu/drm/i915/intel_pm.c 		if (plane_id == PLANE_CURSOR)
plane_id         4482 drivers/gpu/drm/i915/intel_pm.c 		WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
plane_id         4485 drivers/gpu/drm/i915/intel_pm.c 		if (total[plane_id]) {
plane_id         4487 drivers/gpu/drm/i915/intel_pm.c 			start += total[plane_id];
plane_id         4491 drivers/gpu/drm/i915/intel_pm.c 		if (uv_total[plane_id]) {
plane_id         4493 drivers/gpu/drm/i915/intel_pm.c 			start += uv_total[plane_id];
plane_id         4505 drivers/gpu/drm/i915/intel_pm.c 		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
plane_id         4507 drivers/gpu/drm/i915/intel_pm.c 				&crtc_state->wm.skl.optimal.planes[plane_id];
plane_id         4521 drivers/gpu/drm/i915/intel_pm.c 			if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
plane_id         4522 drivers/gpu/drm/i915/intel_pm.c 			    wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
plane_id         4542 drivers/gpu/drm/i915/intel_pm.c 	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
plane_id         4544 drivers/gpu/drm/i915/intel_pm.c 			&crtc_state->wm.skl.optimal.planes[plane_id];
plane_id         4546 drivers/gpu/drm/i915/intel_pm.c 		if (wm->trans_wm.plane_res_b >= total[plane_id])
plane_id         4988 drivers/gpu/drm/i915/intel_pm.c 				     enum plane_id plane_id, int color_plane)
plane_id         4990 drivers/gpu/drm/i915/intel_pm.c 	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
plane_id         5007 drivers/gpu/drm/i915/intel_pm.c 				 enum plane_id plane_id)
plane_id         5009 drivers/gpu/drm/i915/intel_pm.c 	struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
plane_id         5031 drivers/gpu/drm/i915/intel_pm.c 	enum plane_id plane_id = plane->id;
plane_id         5038 drivers/gpu/drm/i915/intel_pm.c 					plane_id, 0);
plane_id         5044 drivers/gpu/drm/i915/intel_pm.c 					    plane_id);
plane_id         5055 drivers/gpu/drm/i915/intel_pm.c 	enum plane_id plane_id = to_intel_plane(plane_state->base.plane)->id;
plane_id         5064 drivers/gpu/drm/i915/intel_pm.c 		enum plane_id y_plane_id = plane_state->linked_plane->id;
plane_id         5076 drivers/gpu/drm/i915/intel_pm.c 						plane_id, 1);
plane_id         5081 drivers/gpu/drm/i915/intel_pm.c 						plane_id, 0);
plane_id         5152 drivers/gpu/drm/i915/intel_pm.c 	enum plane_id plane_id = plane->id;
plane_id         5155 drivers/gpu/drm/i915/intel_pm.c 		&crtc_state->wm.skl.optimal.planes[plane_id];
plane_id         5157 drivers/gpu/drm/i915/intel_pm.c 		&crtc_state->wm.skl.plane_ddb_y[plane_id];
plane_id         5159 drivers/gpu/drm/i915/intel_pm.c 		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
plane_id         5162 drivers/gpu/drm/i915/intel_pm.c 		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
plane_id         5165 drivers/gpu/drm/i915/intel_pm.c 	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
plane_id         5170 drivers/gpu/drm/i915/intel_pm.c 				    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
plane_id         5178 drivers/gpu/drm/i915/intel_pm.c 			    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
plane_id         5180 drivers/gpu/drm/i915/intel_pm.c 			    PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
plane_id         5188 drivers/gpu/drm/i915/intel_pm.c 	enum plane_id plane_id = plane->id;
plane_id         5191 drivers/gpu/drm/i915/intel_pm.c 		&crtc_state->wm.skl.optimal.planes[plane_id];
plane_id         5193 drivers/gpu/drm/i915/intel_pm.c 		&crtc_state->wm.skl.plane_ddb_y[plane_id];
plane_id         5233 drivers/gpu/drm/i915/intel_pm.c 	enum plane_id plane_id;
plane_id         5235 drivers/gpu/drm/i915/intel_pm.c 	for_each_plane_id_on_crtc(crtc, plane_id) {
plane_id         5237 drivers/gpu/drm/i915/intel_pm.c 					 &wm1->planes[plane_id],
plane_id         5238 drivers/gpu/drm/i915/intel_pm.c 					 &wm2->planes[plane_id]))
plane_id         5290 drivers/gpu/drm/i915/intel_pm.c 		enum plane_id plane_id = plane->id;
plane_id         5292 drivers/gpu/drm/i915/intel_pm.c 		if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
plane_id         5293 drivers/gpu/drm/i915/intel_pm.c 					&new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
plane_id         5294 drivers/gpu/drm/i915/intel_pm.c 		    skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
plane_id         5295 drivers/gpu/drm/i915/intel_pm.c 					&new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
plane_id         5302 drivers/gpu/drm/i915/intel_pm.c 		new_crtc_state->update_planes |= BIT(plane_id);
plane_id         5361 drivers/gpu/drm/i915/intel_pm.c 			enum plane_id plane_id = plane->id;
plane_id         5364 drivers/gpu/drm/i915/intel_pm.c 			old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
plane_id         5365 drivers/gpu/drm/i915/intel_pm.c 			new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
plane_id         5377 drivers/gpu/drm/i915/intel_pm.c 			enum plane_id plane_id = plane->id;
plane_id         5380 drivers/gpu/drm/i915/intel_pm.c 			old_wm = &old_pipe_wm->planes[plane_id];
plane_id         5381 drivers/gpu/drm/i915/intel_pm.c 			new_wm = &new_pipe_wm->planes[plane_id];
plane_id         5574 drivers/gpu/drm/i915/intel_pm.c 		enum plane_id plane_id = plane->id;
plane_id         5586 drivers/gpu/drm/i915/intel_pm.c 					&old_crtc_state->wm.skl.optimal.planes[plane_id],
plane_id         5587 drivers/gpu/drm/i915/intel_pm.c 					&new_crtc_state->wm.skl.optimal.planes[plane_id]))
plane_id         5594 drivers/gpu/drm/i915/intel_pm.c 		new_crtc_state->update_planes |= BIT(plane_id);
plane_id         5774 drivers/gpu/drm/i915/intel_pm.c 	enum plane_id plane_id;
plane_id         5779 drivers/gpu/drm/i915/intel_pm.c 	for_each_plane_id_on_crtc(crtc, plane_id) {
plane_id         5780 drivers/gpu/drm/i915/intel_pm.c 		struct skl_plane_wm *wm = &out->planes[plane_id];
plane_id         5783 drivers/gpu/drm/i915/intel_pm.c 			if (plane_id != PLANE_CURSOR)
plane_id         5784 drivers/gpu/drm/i915/intel_pm.c 				val = I915_READ(PLANE_WM(pipe, plane_id, level));
plane_id         5791 drivers/gpu/drm/i915/intel_pm.c 		if (plane_id != PLANE_CURSOR)
plane_id         5792 drivers/gpu/drm/i915/intel_pm.c 			val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
plane_id         6001 drivers/gpu/drm/i915/intel_pm.c 		enum plane_id plane_id;
plane_id         6011 drivers/gpu/drm/i915/intel_pm.c 		for_each_plane_id_on_crtc(crtc, plane_id) {
plane_id         6012 drivers/gpu/drm/i915/intel_pm.c 			active->wm.plane[plane_id] =
plane_id         6013 drivers/gpu/drm/i915/intel_pm.c 				wm->pipe[pipe].plane[plane_id];
plane_id         6025 drivers/gpu/drm/i915/intel_pm.c 		for_each_plane_id_on_crtc(crtc, plane_id)
plane_id         6026 drivers/gpu/drm/i915/intel_pm.c 			raw->plane[plane_id] = active->wm.plane[plane_id];
plane_id         6047 drivers/gpu/drm/i915/intel_pm.c 		for_each_plane_id_on_crtc(crtc, plane_id)
plane_id         6049 drivers/gpu/drm/i915/intel_pm.c 					     plane_id, USHRT_MAX);
plane_id         6085 drivers/gpu/drm/i915/intel_pm.c 		enum plane_id plane_id = plane->id;
plane_id         6095 drivers/gpu/drm/i915/intel_pm.c 			raw->plane[plane_id] = 0;
plane_id         6096 drivers/gpu/drm/i915/intel_pm.c 			wm_state->wm.plane[plane_id] = 0;
plane_id         6099 drivers/gpu/drm/i915/intel_pm.c 		if (plane_id == PLANE_PRIMARY) {
plane_id         6178 drivers/gpu/drm/i915/intel_pm.c 		enum plane_id plane_id;
plane_id         6193 drivers/gpu/drm/i915/intel_pm.c 			for_each_plane_id_on_crtc(crtc, plane_id) {
plane_id         6194 drivers/gpu/drm/i915/intel_pm.c 				active->wm[level].plane[plane_id] =
plane_id         6195 drivers/gpu/drm/i915/intel_pm.c 					wm->pipe[pipe].plane[plane_id];
plane_id         6197 drivers/gpu/drm/i915/intel_pm.c 				raw->plane[plane_id] =
plane_id         6198 drivers/gpu/drm/i915/intel_pm.c 					vlv_invert_wm_value(active->wm[level].plane[plane_id],
plane_id         6199 drivers/gpu/drm/i915/intel_pm.c 							    fifo_state->plane[plane_id]);
plane_id         6203 drivers/gpu/drm/i915/intel_pm.c 		for_each_plane_id_on_crtc(crtc, plane_id)
plane_id         6205 drivers/gpu/drm/i915/intel_pm.c 					     plane_id, USHRT_MAX);
plane_id         6240 drivers/gpu/drm/i915/intel_pm.c 		enum plane_id plane_id = plane->id;
plane_id         6250 drivers/gpu/drm/i915/intel_pm.c 			raw->plane[plane_id] = 0;
plane_id         6252 drivers/gpu/drm/i915/intel_pm.c 			wm_state->wm[level].plane[plane_id] =
plane_id         6253 drivers/gpu/drm/i915/intel_pm.c 				vlv_invert_wm_value(raw->plane[plane_id],
plane_id         6254 drivers/gpu/drm/i915/intel_pm.c 						    fifo_state->plane[plane_id]);
plane_id          643 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h 	TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
plane_id          647 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h 	TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, sspp,
plane_id          651 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h 		__field(	uint32_t,		plane_id	)
plane_id          665 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h 		__entry->plane_id = plane_id;
plane_id          681 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h 		  __entry->crtc_id, __entry->plane_id, __entry->fb_id,
plane_id          239 drivers/gpu/drm/sti/sti_mixer.c 	int plane_id, depth = plane->drm_plane.state->normalized_zpos;
plane_id          245 drivers/gpu/drm/sti/sti_mixer.c 		plane_id = GAM_DEPTH_GDP0_ID;
plane_id          248 drivers/gpu/drm/sti/sti_mixer.c 		plane_id = GAM_DEPTH_GDP1_ID;
plane_id          251 drivers/gpu/drm/sti/sti_mixer.c 		plane_id = GAM_DEPTH_GDP2_ID;
plane_id          254 drivers/gpu/drm/sti/sti_mixer.c 		plane_id = GAM_DEPTH_GDP3_ID;
plane_id          257 drivers/gpu/drm/sti/sti_mixer.c 		plane_id = GAM_DEPTH_VID0_ID;
plane_id          271 drivers/gpu/drm/sti/sti_mixer.c 		if ((val & mask) == plane_id << (3 * i))
plane_id          276 drivers/gpu/drm/sti/sti_mixer.c 	plane_id = plane_id << (3 * depth);
plane_id          281 drivers/gpu/drm/sti/sti_mixer.c 		plane_id, mask);
plane_id          284 drivers/gpu/drm/sti/sti_mixer.c 	val |= plane_id;
plane_id          276 include/uapi/drm/drm_mode.h 	__u32 plane_id;
plane_id          295 include/uapi/drm/drm_mode.h 	__u32 plane_id;
plane_id         1465 include/uapi/drm/i915_drm.h 	__u32 plane_id;
plane_id         1465 tools/include/uapi/drm/i915_drm.h 	__u32 plane_id;