pipe_state        405 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct pipe_state pipe_state;
pipe_state        435 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct pipe_state *pipe = &chan->pipe_state;
pipe_state        563 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct pipe_state *pipe = &chan->pipe_state;
pipe_state        582 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct pipe_state *pipe = &chan->pipe_state;
pipe_state        634 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 	struct pipe_state *pipe_state = &chan->pipe_state;
pipe_state        639 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 		pipe_state_addr = pipe_state->pipe_##addr; \
pipe_state        643 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 		u32 *__end_addr = pipe_state->pipe_##addr + \
pipe_state        644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c 				ARRAY_SIZE(pipe_state->pipe_##addr); \
pipe_state         17 drivers/nfc/st-nci/se.c 	u8 pipe_state;
pipe_state        225 drivers/nfc/st-nci/se.c 		    ST_NCI_DM_IS_PIPE_OPEN(dm_pipe_info->pipe_state)) {
pipe_state         95 drivers/nfc/st21nfca/core.c 	u8 pipe_state;
pipe_state        181 drivers/nfc/st21nfca/core.c 			ST21NFCA_DM_IS_PIPE_OPEN(info->pipe_state)) {